2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
45 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
47 static void intel_increase_pllclock(struct drm_crtc *crtc);
48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
50 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
51 struct intel_crtc_config *pipe_config);
52 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
53 struct intel_crtc_config *pipe_config);
55 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
56 int x, int y, struct drm_framebuffer *old_fb);
57 static int intel_framebuffer_init(struct drm_device *dev,
58 struct intel_framebuffer *ifb,
59 struct drm_mode_fb_cmd2 *mode_cmd,
60 struct drm_i915_gem_object *obj);
71 typedef struct intel_limit intel_limit_t;
73 intel_range_t dot, vco, n, m, m1, m2, p, p1;
78 intel_pch_rawclk(struct drm_device *dev)
80 struct drm_i915_private *dev_priv = dev->dev_private;
82 WARN_ON(!HAS_PCH_SPLIT(dev));
84 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
87 static inline u32 /* units of 100MHz */
88 intel_fdi_link_freq(struct drm_device *dev)
91 struct drm_i915_private *dev_priv = dev->dev_private;
92 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
97 static const intel_limit_t intel_limits_i8xx_dac = {
98 .dot = { .min = 25000, .max = 350000 },
99 .vco = { .min = 908000, .max = 1512000 },
100 .n = { .min = 2, .max = 16 },
101 .m = { .min = 96, .max = 140 },
102 .m1 = { .min = 18, .max = 26 },
103 .m2 = { .min = 6, .max = 16 },
104 .p = { .min = 4, .max = 128 },
105 .p1 = { .min = 2, .max = 33 },
106 .p2 = { .dot_limit = 165000,
107 .p2_slow = 4, .p2_fast = 2 },
110 static const intel_limit_t intel_limits_i8xx_dvo = {
111 .dot = { .min = 25000, .max = 350000 },
112 .vco = { .min = 908000, .max = 1512000 },
113 .n = { .min = 2, .max = 16 },
114 .m = { .min = 96, .max = 140 },
115 .m1 = { .min = 18, .max = 26 },
116 .m2 = { .min = 6, .max = 16 },
117 .p = { .min = 4, .max = 128 },
118 .p1 = { .min = 2, .max = 33 },
119 .p2 = { .dot_limit = 165000,
120 .p2_slow = 4, .p2_fast = 4 },
123 static const intel_limit_t intel_limits_i8xx_lvds = {
124 .dot = { .min = 25000, .max = 350000 },
125 .vco = { .min = 908000, .max = 1512000 },
126 .n = { .min = 2, .max = 16 },
127 .m = { .min = 96, .max = 140 },
128 .m1 = { .min = 18, .max = 26 },
129 .m2 = { .min = 6, .max = 16 },
130 .p = { .min = 4, .max = 128 },
131 .p1 = { .min = 1, .max = 6 },
132 .p2 = { .dot_limit = 165000,
133 .p2_slow = 14, .p2_fast = 7 },
136 static const intel_limit_t intel_limits_i9xx_sdvo = {
137 .dot = { .min = 20000, .max = 400000 },
138 .vco = { .min = 1400000, .max = 2800000 },
139 .n = { .min = 1, .max = 6 },
140 .m = { .min = 70, .max = 120 },
141 .m1 = { .min = 8, .max = 18 },
142 .m2 = { .min = 3, .max = 7 },
143 .p = { .min = 5, .max = 80 },
144 .p1 = { .min = 1, .max = 8 },
145 .p2 = { .dot_limit = 200000,
146 .p2_slow = 10, .p2_fast = 5 },
149 static const intel_limit_t intel_limits_i9xx_lvds = {
150 .dot = { .min = 20000, .max = 400000 },
151 .vco = { .min = 1400000, .max = 2800000 },
152 .n = { .min = 1, .max = 6 },
153 .m = { .min = 70, .max = 120 },
154 .m1 = { .min = 8, .max = 18 },
155 .m2 = { .min = 3, .max = 7 },
156 .p = { .min = 7, .max = 98 },
157 .p1 = { .min = 1, .max = 8 },
158 .p2 = { .dot_limit = 112000,
159 .p2_slow = 14, .p2_fast = 7 },
163 static const intel_limit_t intel_limits_g4x_sdvo = {
164 .dot = { .min = 25000, .max = 270000 },
165 .vco = { .min = 1750000, .max = 3500000},
166 .n = { .min = 1, .max = 4 },
167 .m = { .min = 104, .max = 138 },
168 .m1 = { .min = 17, .max = 23 },
169 .m2 = { .min = 5, .max = 11 },
170 .p = { .min = 10, .max = 30 },
171 .p1 = { .min = 1, .max = 3},
172 .p2 = { .dot_limit = 270000,
178 static const intel_limit_t intel_limits_g4x_hdmi = {
179 .dot = { .min = 22000, .max = 400000 },
180 .vco = { .min = 1750000, .max = 3500000},
181 .n = { .min = 1, .max = 4 },
182 .m = { .min = 104, .max = 138 },
183 .m1 = { .min = 16, .max = 23 },
184 .m2 = { .min = 5, .max = 11 },
185 .p = { .min = 5, .max = 80 },
186 .p1 = { .min = 1, .max = 8},
187 .p2 = { .dot_limit = 165000,
188 .p2_slow = 10, .p2_fast = 5 },
191 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
192 .dot = { .min = 20000, .max = 115000 },
193 .vco = { .min = 1750000, .max = 3500000 },
194 .n = { .min = 1, .max = 3 },
195 .m = { .min = 104, .max = 138 },
196 .m1 = { .min = 17, .max = 23 },
197 .m2 = { .min = 5, .max = 11 },
198 .p = { .min = 28, .max = 112 },
199 .p1 = { .min = 2, .max = 8 },
200 .p2 = { .dot_limit = 0,
201 .p2_slow = 14, .p2_fast = 14
205 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
206 .dot = { .min = 80000, .max = 224000 },
207 .vco = { .min = 1750000, .max = 3500000 },
208 .n = { .min = 1, .max = 3 },
209 .m = { .min = 104, .max = 138 },
210 .m1 = { .min = 17, .max = 23 },
211 .m2 = { .min = 5, .max = 11 },
212 .p = { .min = 14, .max = 42 },
213 .p1 = { .min = 2, .max = 6 },
214 .p2 = { .dot_limit = 0,
215 .p2_slow = 7, .p2_fast = 7
219 static const intel_limit_t intel_limits_pineview_sdvo = {
220 .dot = { .min = 20000, .max = 400000},
221 .vco = { .min = 1700000, .max = 3500000 },
222 /* Pineview's Ncounter is a ring counter */
223 .n = { .min = 3, .max = 6 },
224 .m = { .min = 2, .max = 256 },
225 /* Pineview only has one combined m divider, which we treat as m2. */
226 .m1 = { .min = 0, .max = 0 },
227 .m2 = { .min = 0, .max = 254 },
228 .p = { .min = 5, .max = 80 },
229 .p1 = { .min = 1, .max = 8 },
230 .p2 = { .dot_limit = 200000,
231 .p2_slow = 10, .p2_fast = 5 },
234 static const intel_limit_t intel_limits_pineview_lvds = {
235 .dot = { .min = 20000, .max = 400000 },
236 .vco = { .min = 1700000, .max = 3500000 },
237 .n = { .min = 3, .max = 6 },
238 .m = { .min = 2, .max = 256 },
239 .m1 = { .min = 0, .max = 0 },
240 .m2 = { .min = 0, .max = 254 },
241 .p = { .min = 7, .max = 112 },
242 .p1 = { .min = 1, .max = 8 },
243 .p2 = { .dot_limit = 112000,
244 .p2_slow = 14, .p2_fast = 14 },
247 /* Ironlake / Sandybridge
249 * We calculate clock using (register_value + 2) for N/M1/M2, so here
250 * the range value for them is (actual_value - 2).
252 static const intel_limit_t intel_limits_ironlake_dac = {
253 .dot = { .min = 25000, .max = 350000 },
254 .vco = { .min = 1760000, .max = 3510000 },
255 .n = { .min = 1, .max = 5 },
256 .m = { .min = 79, .max = 127 },
257 .m1 = { .min = 12, .max = 22 },
258 .m2 = { .min = 5, .max = 9 },
259 .p = { .min = 5, .max = 80 },
260 .p1 = { .min = 1, .max = 8 },
261 .p2 = { .dot_limit = 225000,
262 .p2_slow = 10, .p2_fast = 5 },
265 static const intel_limit_t intel_limits_ironlake_single_lvds = {
266 .dot = { .min = 25000, .max = 350000 },
267 .vco = { .min = 1760000, .max = 3510000 },
268 .n = { .min = 1, .max = 3 },
269 .m = { .min = 79, .max = 118 },
270 .m1 = { .min = 12, .max = 22 },
271 .m2 = { .min = 5, .max = 9 },
272 .p = { .min = 28, .max = 112 },
273 .p1 = { .min = 2, .max = 8 },
274 .p2 = { .dot_limit = 225000,
275 .p2_slow = 14, .p2_fast = 14 },
278 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
279 .dot = { .min = 25000, .max = 350000 },
280 .vco = { .min = 1760000, .max = 3510000 },
281 .n = { .min = 1, .max = 3 },
282 .m = { .min = 79, .max = 127 },
283 .m1 = { .min = 12, .max = 22 },
284 .m2 = { .min = 5, .max = 9 },
285 .p = { .min = 14, .max = 56 },
286 .p1 = { .min = 2, .max = 8 },
287 .p2 = { .dot_limit = 225000,
288 .p2_slow = 7, .p2_fast = 7 },
291 /* LVDS 100mhz refclk limits. */
292 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
293 .dot = { .min = 25000, .max = 350000 },
294 .vco = { .min = 1760000, .max = 3510000 },
295 .n = { .min = 1, .max = 2 },
296 .m = { .min = 79, .max = 126 },
297 .m1 = { .min = 12, .max = 22 },
298 .m2 = { .min = 5, .max = 9 },
299 .p = { .min = 28, .max = 112 },
300 .p1 = { .min = 2, .max = 8 },
301 .p2 = { .dot_limit = 225000,
302 .p2_slow = 14, .p2_fast = 14 },
305 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
306 .dot = { .min = 25000, .max = 350000 },
307 .vco = { .min = 1760000, .max = 3510000 },
308 .n = { .min = 1, .max = 3 },
309 .m = { .min = 79, .max = 126 },
310 .m1 = { .min = 12, .max = 22 },
311 .m2 = { .min = 5, .max = 9 },
312 .p = { .min = 14, .max = 42 },
313 .p1 = { .min = 2, .max = 6 },
314 .p2 = { .dot_limit = 225000,
315 .p2_slow = 7, .p2_fast = 7 },
318 static const intel_limit_t intel_limits_vlv = {
320 * These are the data rate limits (measured in fast clocks)
321 * since those are the strictest limits we have. The fast
322 * clock and actual rate limits are more relaxed, so checking
323 * them would make no difference.
325 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
326 .vco = { .min = 4000000, .max = 6000000 },
327 .n = { .min = 1, .max = 7 },
328 .m1 = { .min = 2, .max = 3 },
329 .m2 = { .min = 11, .max = 156 },
330 .p1 = { .min = 2, .max = 3 },
331 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
334 static const intel_limit_t intel_limits_chv = {
336 * These are the data rate limits (measured in fast clocks)
337 * since those are the strictest limits we have. The fast
338 * clock and actual rate limits are more relaxed, so checking
339 * them would make no difference.
341 .dot = { .min = 25000 * 5, .max = 540000 * 5},
342 .vco = { .min = 4860000, .max = 6700000 },
343 .n = { .min = 1, .max = 1 },
344 .m1 = { .min = 2, .max = 2 },
345 .m2 = { .min = 24 << 22, .max = 175 << 22 },
346 .p1 = { .min = 2, .max = 4 },
347 .p2 = { .p2_slow = 1, .p2_fast = 14 },
350 static void vlv_clock(int refclk, intel_clock_t *clock)
352 clock->m = clock->m1 * clock->m2;
353 clock->p = clock->p1 * clock->p2;
354 if (WARN_ON(clock->n == 0 || clock->p == 0))
356 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
357 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
361 * Returns whether any output on the specified pipe is of the specified type
363 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
365 struct drm_device *dev = crtc->dev;
366 struct intel_encoder *encoder;
368 for_each_encoder_on_crtc(dev, crtc, encoder)
369 if (encoder->type == type)
375 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
378 struct drm_device *dev = crtc->dev;
379 const intel_limit_t *limit;
381 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
382 if (intel_is_dual_link_lvds(dev)) {
383 if (refclk == 100000)
384 limit = &intel_limits_ironlake_dual_lvds_100m;
386 limit = &intel_limits_ironlake_dual_lvds;
388 if (refclk == 100000)
389 limit = &intel_limits_ironlake_single_lvds_100m;
391 limit = &intel_limits_ironlake_single_lvds;
394 limit = &intel_limits_ironlake_dac;
399 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
401 struct drm_device *dev = crtc->dev;
402 const intel_limit_t *limit;
404 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
405 if (intel_is_dual_link_lvds(dev))
406 limit = &intel_limits_g4x_dual_channel_lvds;
408 limit = &intel_limits_g4x_single_channel_lvds;
409 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
410 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
411 limit = &intel_limits_g4x_hdmi;
412 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
413 limit = &intel_limits_g4x_sdvo;
414 } else /* The option is for other outputs */
415 limit = &intel_limits_i9xx_sdvo;
420 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
422 struct drm_device *dev = crtc->dev;
423 const intel_limit_t *limit;
425 if (HAS_PCH_SPLIT(dev))
426 limit = intel_ironlake_limit(crtc, refclk);
427 else if (IS_G4X(dev)) {
428 limit = intel_g4x_limit(crtc);
429 } else if (IS_PINEVIEW(dev)) {
430 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
431 limit = &intel_limits_pineview_lvds;
433 limit = &intel_limits_pineview_sdvo;
434 } else if (IS_CHERRYVIEW(dev)) {
435 limit = &intel_limits_chv;
436 } else if (IS_VALLEYVIEW(dev)) {
437 limit = &intel_limits_vlv;
438 } else if (!IS_GEN2(dev)) {
439 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
440 limit = &intel_limits_i9xx_lvds;
442 limit = &intel_limits_i9xx_sdvo;
444 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
445 limit = &intel_limits_i8xx_lvds;
446 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
447 limit = &intel_limits_i8xx_dvo;
449 limit = &intel_limits_i8xx_dac;
454 /* m1 is reserved as 0 in Pineview, n is a ring counter */
455 static void pineview_clock(int refclk, intel_clock_t *clock)
457 clock->m = clock->m2 + 2;
458 clock->p = clock->p1 * clock->p2;
459 if (WARN_ON(clock->n == 0 || clock->p == 0))
461 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
462 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
465 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
467 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
470 static void i9xx_clock(int refclk, intel_clock_t *clock)
472 clock->m = i9xx_dpll_compute_m(clock);
473 clock->p = clock->p1 * clock->p2;
474 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
476 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
477 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
480 static void chv_clock(int refclk, intel_clock_t *clock)
482 clock->m = clock->m1 * clock->m2;
483 clock->p = clock->p1 * clock->p2;
484 if (WARN_ON(clock->n == 0 || clock->p == 0))
486 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
488 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
491 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
493 * Returns whether the given set of divisors are valid for a given refclk with
494 * the given connectors.
497 static bool intel_PLL_is_valid(struct drm_device *dev,
498 const intel_limit_t *limit,
499 const intel_clock_t *clock)
501 if (clock->n < limit->n.min || limit->n.max < clock->n)
502 INTELPllInvalid("n out of range\n");
503 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
504 INTELPllInvalid("p1 out of range\n");
505 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
506 INTELPllInvalid("m2 out of range\n");
507 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
508 INTELPllInvalid("m1 out of range\n");
510 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
511 if (clock->m1 <= clock->m2)
512 INTELPllInvalid("m1 <= m2\n");
514 if (!IS_VALLEYVIEW(dev)) {
515 if (clock->p < limit->p.min || limit->p.max < clock->p)
516 INTELPllInvalid("p out of range\n");
517 if (clock->m < limit->m.min || limit->m.max < clock->m)
518 INTELPllInvalid("m out of range\n");
521 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
522 INTELPllInvalid("vco out of range\n");
523 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
524 * connector, etc., rather than just a single range.
526 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
527 INTELPllInvalid("dot out of range\n");
533 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
534 int target, int refclk, intel_clock_t *match_clock,
535 intel_clock_t *best_clock)
537 struct drm_device *dev = crtc->dev;
541 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
543 * For LVDS just rely on its current settings for dual-channel.
544 * We haven't figured out how to reliably set up different
545 * single/dual channel state, if we even can.
547 if (intel_is_dual_link_lvds(dev))
548 clock.p2 = limit->p2.p2_fast;
550 clock.p2 = limit->p2.p2_slow;
552 if (target < limit->p2.dot_limit)
553 clock.p2 = limit->p2.p2_slow;
555 clock.p2 = limit->p2.p2_fast;
558 memset(best_clock, 0, sizeof(*best_clock));
560 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
562 for (clock.m2 = limit->m2.min;
563 clock.m2 <= limit->m2.max; clock.m2++) {
564 if (clock.m2 >= clock.m1)
566 for (clock.n = limit->n.min;
567 clock.n <= limit->n.max; clock.n++) {
568 for (clock.p1 = limit->p1.min;
569 clock.p1 <= limit->p1.max; clock.p1++) {
572 i9xx_clock(refclk, &clock);
573 if (!intel_PLL_is_valid(dev, limit,
577 clock.p != match_clock->p)
580 this_err = abs(clock.dot - target);
581 if (this_err < err) {
590 return (err != target);
594 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
595 int target, int refclk, intel_clock_t *match_clock,
596 intel_clock_t *best_clock)
598 struct drm_device *dev = crtc->dev;
602 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
604 * For LVDS just rely on its current settings for dual-channel.
605 * We haven't figured out how to reliably set up different
606 * single/dual channel state, if we even can.
608 if (intel_is_dual_link_lvds(dev))
609 clock.p2 = limit->p2.p2_fast;
611 clock.p2 = limit->p2.p2_slow;
613 if (target < limit->p2.dot_limit)
614 clock.p2 = limit->p2.p2_slow;
616 clock.p2 = limit->p2.p2_fast;
619 memset(best_clock, 0, sizeof(*best_clock));
621 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
623 for (clock.m2 = limit->m2.min;
624 clock.m2 <= limit->m2.max; clock.m2++) {
625 for (clock.n = limit->n.min;
626 clock.n <= limit->n.max; clock.n++) {
627 for (clock.p1 = limit->p1.min;
628 clock.p1 <= limit->p1.max; clock.p1++) {
631 pineview_clock(refclk, &clock);
632 if (!intel_PLL_is_valid(dev, limit,
636 clock.p != match_clock->p)
639 this_err = abs(clock.dot - target);
640 if (this_err < err) {
649 return (err != target);
653 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
654 int target, int refclk, intel_clock_t *match_clock,
655 intel_clock_t *best_clock)
657 struct drm_device *dev = crtc->dev;
661 /* approximately equals target * 0.00585 */
662 int err_most = (target >> 8) + (target >> 9);
665 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
666 if (intel_is_dual_link_lvds(dev))
667 clock.p2 = limit->p2.p2_fast;
669 clock.p2 = limit->p2.p2_slow;
671 if (target < limit->p2.dot_limit)
672 clock.p2 = limit->p2.p2_slow;
674 clock.p2 = limit->p2.p2_fast;
677 memset(best_clock, 0, sizeof(*best_clock));
678 max_n = limit->n.max;
679 /* based on hardware requirement, prefer smaller n to precision */
680 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
681 /* based on hardware requirement, prefere larger m1,m2 */
682 for (clock.m1 = limit->m1.max;
683 clock.m1 >= limit->m1.min; clock.m1--) {
684 for (clock.m2 = limit->m2.max;
685 clock.m2 >= limit->m2.min; clock.m2--) {
686 for (clock.p1 = limit->p1.max;
687 clock.p1 >= limit->p1.min; clock.p1--) {
690 i9xx_clock(refclk, &clock);
691 if (!intel_PLL_is_valid(dev, limit,
695 this_err = abs(clock.dot - target);
696 if (this_err < err_most) {
710 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
711 int target, int refclk, intel_clock_t *match_clock,
712 intel_clock_t *best_clock)
714 struct drm_device *dev = crtc->dev;
716 unsigned int bestppm = 1000000;
717 /* min update 19.2 MHz */
718 int max_n = min(limit->n.max, refclk / 19200);
721 target *= 5; /* fast clock */
723 memset(best_clock, 0, sizeof(*best_clock));
725 /* based on hardware requirement, prefer smaller n to precision */
726 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
727 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
728 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
729 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
730 clock.p = clock.p1 * clock.p2;
731 /* based on hardware requirement, prefer bigger m1,m2 values */
732 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
733 unsigned int ppm, diff;
735 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
738 vlv_clock(refclk, &clock);
740 if (!intel_PLL_is_valid(dev, limit,
744 diff = abs(clock.dot - target);
745 ppm = div_u64(1000000ULL * diff, target);
747 if (ppm < 100 && clock.p > best_clock->p) {
753 if (bestppm >= 10 && ppm < bestppm - 10) {
767 chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
768 int target, int refclk, intel_clock_t *match_clock,
769 intel_clock_t *best_clock)
771 struct drm_device *dev = crtc->dev;
776 memset(best_clock, 0, sizeof(*best_clock));
779 * Based on hardware doc, the n always set to 1, and m1 always
780 * set to 2. If requires to support 200Mhz refclk, we need to
781 * revisit this because n may not 1 anymore.
783 clock.n = 1, clock.m1 = 2;
784 target *= 5; /* fast clock */
786 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
787 for (clock.p2 = limit->p2.p2_fast;
788 clock.p2 >= limit->p2.p2_slow;
789 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
791 clock.p = clock.p1 * clock.p2;
793 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
794 clock.n) << 22, refclk * clock.m1);
796 if (m2 > INT_MAX/clock.m1)
801 chv_clock(refclk, &clock);
803 if (!intel_PLL_is_valid(dev, limit, &clock))
806 /* based on hardware requirement, prefer bigger p
808 if (clock.p > best_clock->p) {
818 bool intel_crtc_active(struct drm_crtc *crtc)
820 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
822 /* Be paranoid as we can arrive here with only partial
823 * state retrieved from the hardware during setup.
825 * We can ditch the adjusted_mode.crtc_clock check as soon
826 * as Haswell has gained clock readout/fastboot support.
828 * We can ditch the crtc->primary->fb check as soon as we can
829 * properly reconstruct framebuffers.
831 return intel_crtc->active && crtc->primary->fb &&
832 intel_crtc->config.adjusted_mode.crtc_clock;
835 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
838 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
839 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
841 return intel_crtc->config.cpu_transcoder;
844 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
846 struct drm_i915_private *dev_priv = dev->dev_private;
847 u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
849 frame = I915_READ(frame_reg);
851 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
852 WARN(1, "vblank wait timed out\n");
856 * intel_wait_for_vblank - wait for vblank on a given pipe
858 * @pipe: pipe to wait for
860 * Wait for vblank to occur on a given pipe. Needed for various bits of
863 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
865 struct drm_i915_private *dev_priv = dev->dev_private;
866 int pipestat_reg = PIPESTAT(pipe);
868 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
869 g4x_wait_for_vblank(dev, pipe);
873 /* Clear existing vblank status. Note this will clear any other
874 * sticky status fields as well.
876 * This races with i915_driver_irq_handler() with the result
877 * that either function could miss a vblank event. Here it is not
878 * fatal, as we will either wait upon the next vblank interrupt or
879 * timeout. Generally speaking intel_wait_for_vblank() is only
880 * called during modeset at which time the GPU should be idle and
881 * should *not* be performing page flips and thus not waiting on
883 * Currently, the result of us stealing a vblank from the irq
884 * handler is that a single frame will be skipped during swapbuffers.
886 I915_WRITE(pipestat_reg,
887 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
889 /* Wait for vblank interrupt bit to set */
890 if (wait_for(I915_READ(pipestat_reg) &
891 PIPE_VBLANK_INTERRUPT_STATUS,
893 DRM_DEBUG_KMS("vblank wait timed out\n");
896 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
898 struct drm_i915_private *dev_priv = dev->dev_private;
899 u32 reg = PIPEDSL(pipe);
904 line_mask = DSL_LINEMASK_GEN2;
906 line_mask = DSL_LINEMASK_GEN3;
908 line1 = I915_READ(reg) & line_mask;
910 line2 = I915_READ(reg) & line_mask;
912 return line1 == line2;
916 * intel_wait_for_pipe_off - wait for pipe to turn off
918 * @pipe: pipe to wait for
920 * After disabling a pipe, we can't wait for vblank in the usual way,
921 * spinning on the vblank interrupt status bit, since we won't actually
922 * see an interrupt when the pipe is disabled.
925 * wait for the pipe register state bit to turn off
928 * wait for the display line value to settle (it usually
929 * ends up stopping at the start of the next frame).
932 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
934 struct drm_i915_private *dev_priv = dev->dev_private;
935 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
938 if (INTEL_INFO(dev)->gen >= 4) {
939 int reg = PIPECONF(cpu_transcoder);
941 /* Wait for the Pipe State to go off */
942 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
944 WARN(1, "pipe_off wait timed out\n");
946 /* Wait for the display line to settle */
947 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
948 WARN(1, "pipe_off wait timed out\n");
953 * ibx_digital_port_connected - is the specified port connected?
954 * @dev_priv: i915 private structure
955 * @port: the port to test
957 * Returns true if @port is connected, false otherwise.
959 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
960 struct intel_digital_port *port)
964 if (HAS_PCH_IBX(dev_priv->dev)) {
967 bit = SDE_PORTB_HOTPLUG;
970 bit = SDE_PORTC_HOTPLUG;
973 bit = SDE_PORTD_HOTPLUG;
981 bit = SDE_PORTB_HOTPLUG_CPT;
984 bit = SDE_PORTC_HOTPLUG_CPT;
987 bit = SDE_PORTD_HOTPLUG_CPT;
994 return I915_READ(SDEISR) & bit;
997 static const char *state_string(bool enabled)
999 return enabled ? "on" : "off";
1002 /* Only for pre-ILK configs */
1003 void assert_pll(struct drm_i915_private *dev_priv,
1004 enum pipe pipe, bool state)
1011 val = I915_READ(reg);
1012 cur_state = !!(val & DPLL_VCO_ENABLE);
1013 WARN(cur_state != state,
1014 "PLL state assertion failure (expected %s, current %s)\n",
1015 state_string(state), state_string(cur_state));
1018 /* XXX: the dsi pll is shared between MIPI DSI ports */
1019 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1024 mutex_lock(&dev_priv->dpio_lock);
1025 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1026 mutex_unlock(&dev_priv->dpio_lock);
1028 cur_state = val & DSI_PLL_VCO_EN;
1029 WARN(cur_state != state,
1030 "DSI PLL state assertion failure (expected %s, current %s)\n",
1031 state_string(state), state_string(cur_state));
1033 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1034 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1036 struct intel_shared_dpll *
1037 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1039 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1041 if (crtc->config.shared_dpll < 0)
1044 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1048 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1049 struct intel_shared_dpll *pll,
1053 struct intel_dpll_hw_state hw_state;
1055 if (HAS_PCH_LPT(dev_priv->dev)) {
1056 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1061 "asserting DPLL %s with no DPLL\n", state_string(state)))
1064 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1065 WARN(cur_state != state,
1066 "%s assertion failure (expected %s, current %s)\n",
1067 pll->name, state_string(state), state_string(cur_state));
1070 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1071 enum pipe pipe, bool state)
1076 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1079 if (HAS_DDI(dev_priv->dev)) {
1080 /* DDI does not have a specific FDI_TX register */
1081 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1082 val = I915_READ(reg);
1083 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1085 reg = FDI_TX_CTL(pipe);
1086 val = I915_READ(reg);
1087 cur_state = !!(val & FDI_TX_ENABLE);
1089 WARN(cur_state != state,
1090 "FDI TX state assertion failure (expected %s, current %s)\n",
1091 state_string(state), state_string(cur_state));
1093 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1094 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1096 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1097 enum pipe pipe, bool state)
1103 reg = FDI_RX_CTL(pipe);
1104 val = I915_READ(reg);
1105 cur_state = !!(val & FDI_RX_ENABLE);
1106 WARN(cur_state != state,
1107 "FDI RX state assertion failure (expected %s, current %s)\n",
1108 state_string(state), state_string(cur_state));
1110 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1111 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1113 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1119 /* ILK FDI PLL is always enabled */
1120 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1123 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1124 if (HAS_DDI(dev_priv->dev))
1127 reg = FDI_TX_CTL(pipe);
1128 val = I915_READ(reg);
1129 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1132 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1133 enum pipe pipe, bool state)
1139 reg = FDI_RX_CTL(pipe);
1140 val = I915_READ(reg);
1141 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1142 WARN(cur_state != state,
1143 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1144 state_string(state), state_string(cur_state));
1147 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1150 int pp_reg, lvds_reg;
1152 enum pipe panel_pipe = PIPE_A;
1155 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1156 pp_reg = PCH_PP_CONTROL;
1157 lvds_reg = PCH_LVDS;
1159 pp_reg = PP_CONTROL;
1163 val = I915_READ(pp_reg);
1164 if (!(val & PANEL_POWER_ON) ||
1165 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1168 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1169 panel_pipe = PIPE_B;
1171 WARN(panel_pipe == pipe && locked,
1172 "panel assertion failure, pipe %c regs locked\n",
1176 static void assert_cursor(struct drm_i915_private *dev_priv,
1177 enum pipe pipe, bool state)
1179 struct drm_device *dev = dev_priv->dev;
1182 if (IS_845G(dev) || IS_I865G(dev))
1183 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1184 else if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev))
1185 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1187 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1189 WARN(cur_state != state,
1190 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1191 pipe_name(pipe), state_string(state), state_string(cur_state));
1193 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1194 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1196 void assert_pipe(struct drm_i915_private *dev_priv,
1197 enum pipe pipe, bool state)
1202 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1205 /* if we need the pipe A quirk it must be always on */
1206 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1209 if (!intel_display_power_enabled(dev_priv,
1210 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1213 reg = PIPECONF(cpu_transcoder);
1214 val = I915_READ(reg);
1215 cur_state = !!(val & PIPECONF_ENABLE);
1218 WARN(cur_state != state,
1219 "pipe %c assertion failure (expected %s, current %s)\n",
1220 pipe_name(pipe), state_string(state), state_string(cur_state));
1223 static void assert_plane(struct drm_i915_private *dev_priv,
1224 enum plane plane, bool state)
1230 reg = DSPCNTR(plane);
1231 val = I915_READ(reg);
1232 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1233 WARN(cur_state != state,
1234 "plane %c assertion failure (expected %s, current %s)\n",
1235 plane_name(plane), state_string(state), state_string(cur_state));
1238 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1239 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1241 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1244 struct drm_device *dev = dev_priv->dev;
1249 /* Primary planes are fixed to pipes on gen4+ */
1250 if (INTEL_INFO(dev)->gen >= 4) {
1251 reg = DSPCNTR(pipe);
1252 val = I915_READ(reg);
1253 WARN(val & DISPLAY_PLANE_ENABLE,
1254 "plane %c assertion failure, should be disabled but not\n",
1259 /* Need to check both planes against the pipe */
1262 val = I915_READ(reg);
1263 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1264 DISPPLANE_SEL_PIPE_SHIFT;
1265 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1266 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1267 plane_name(i), pipe_name(pipe));
1271 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1274 struct drm_device *dev = dev_priv->dev;
1278 if (IS_VALLEYVIEW(dev)) {
1279 for_each_sprite(pipe, sprite) {
1280 reg = SPCNTR(pipe, sprite);
1281 val = I915_READ(reg);
1282 WARN(val & SP_ENABLE,
1283 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1284 sprite_name(pipe, sprite), pipe_name(pipe));
1286 } else if (INTEL_INFO(dev)->gen >= 7) {
1288 val = I915_READ(reg);
1289 WARN(val & SPRITE_ENABLE,
1290 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1291 plane_name(pipe), pipe_name(pipe));
1292 } else if (INTEL_INFO(dev)->gen >= 5) {
1293 reg = DVSCNTR(pipe);
1294 val = I915_READ(reg);
1295 WARN(val & DVS_ENABLE,
1296 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1297 plane_name(pipe), pipe_name(pipe));
1301 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1306 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1308 val = I915_READ(PCH_DREF_CONTROL);
1309 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1310 DREF_SUPERSPREAD_SOURCE_MASK));
1311 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1314 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1321 reg = PCH_TRANSCONF(pipe);
1322 val = I915_READ(reg);
1323 enabled = !!(val & TRANS_ENABLE);
1325 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1329 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1330 enum pipe pipe, u32 port_sel, u32 val)
1332 if ((val & DP_PORT_EN) == 0)
1335 if (HAS_PCH_CPT(dev_priv->dev)) {
1336 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1337 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1338 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1340 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1341 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1344 if ((val & DP_PIPE_MASK) != (pipe << 30))
1350 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1351 enum pipe pipe, u32 val)
1353 if ((val & SDVO_ENABLE) == 0)
1356 if (HAS_PCH_CPT(dev_priv->dev)) {
1357 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1359 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1360 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1363 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1369 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1370 enum pipe pipe, u32 val)
1372 if ((val & LVDS_PORT_EN) == 0)
1375 if (HAS_PCH_CPT(dev_priv->dev)) {
1376 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1379 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1385 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1386 enum pipe pipe, u32 val)
1388 if ((val & ADPA_DAC_ENABLE) == 0)
1390 if (HAS_PCH_CPT(dev_priv->dev)) {
1391 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1394 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1400 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1401 enum pipe pipe, int reg, u32 port_sel)
1403 u32 val = I915_READ(reg);
1404 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1405 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1406 reg, pipe_name(pipe));
1408 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1409 && (val & DP_PIPEB_SELECT),
1410 "IBX PCH dp port still using transcoder B\n");
1413 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1414 enum pipe pipe, int reg)
1416 u32 val = I915_READ(reg);
1417 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1418 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1419 reg, pipe_name(pipe));
1421 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1422 && (val & SDVO_PIPE_B_SELECT),
1423 "IBX PCH hdmi port still using transcoder B\n");
1426 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1432 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1433 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1434 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1437 val = I915_READ(reg);
1438 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1439 "PCH VGA enabled on transcoder %c, should be disabled\n",
1443 val = I915_READ(reg);
1444 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1445 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1448 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1449 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1450 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1453 static void intel_init_dpio(struct drm_device *dev)
1455 struct drm_i915_private *dev_priv = dev->dev_private;
1457 if (!IS_VALLEYVIEW(dev))
1461 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1462 * CHV x1 PHY (DP/HDMI D)
1463 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1465 if (IS_CHERRYVIEW(dev)) {
1466 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1467 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1469 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1473 static void intel_reset_dpio(struct drm_device *dev)
1475 struct drm_i915_private *dev_priv = dev->dev_private;
1477 if (!IS_VALLEYVIEW(dev))
1481 * Enable the CRI clock source so we can get at the display and the
1482 * reference clock for VGA hotplug / manual detection.
1484 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
1485 DPLL_REFA_CLK_ENABLE_VLV |
1486 DPLL_INTEGRATED_CRI_CLK_VLV);
1488 if (IS_CHERRYVIEW(dev)) {
1492 for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) {
1493 /* Poll for phypwrgood signal */
1494 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) &
1495 PHY_POWERGOOD(phy), 1))
1496 DRM_ERROR("Display PHY %d is not power up\n", phy);
1499 * Deassert common lane reset for PHY.
1501 * This should only be done on init and resume from S3
1502 * with both PLLs disabled, or we risk losing DPIO and
1503 * PLL synchronization.
1505 val = I915_READ(DISPLAY_PHY_CONTROL);
1506 I915_WRITE(DISPLAY_PHY_CONTROL,
1507 PHY_COM_LANE_RESET_DEASSERT(phy, val));
1512 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1513 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
1514 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
1515 * b. The other bits such as sfr settings / modesel may all
1518 * This should only be done on init and resume from S3 with
1519 * both PLLs disabled, or we risk losing DPIO and PLL
1522 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1526 static void vlv_enable_pll(struct intel_crtc *crtc)
1528 struct drm_device *dev = crtc->base.dev;
1529 struct drm_i915_private *dev_priv = dev->dev_private;
1530 int reg = DPLL(crtc->pipe);
1531 u32 dpll = crtc->config.dpll_hw_state.dpll;
1533 assert_pipe_disabled(dev_priv, crtc->pipe);
1535 /* No really, not for ILK+ */
1536 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1538 /* PLL is protected by panel, make sure we can write it */
1539 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1540 assert_panel_unlocked(dev_priv, crtc->pipe);
1542 I915_WRITE(reg, dpll);
1546 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1547 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1549 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1550 POSTING_READ(DPLL_MD(crtc->pipe));
1552 /* We do this three times for luck */
1553 I915_WRITE(reg, dpll);
1555 udelay(150); /* wait for warmup */
1556 I915_WRITE(reg, dpll);
1558 udelay(150); /* wait for warmup */
1559 I915_WRITE(reg, dpll);
1561 udelay(150); /* wait for warmup */
1564 static void chv_enable_pll(struct intel_crtc *crtc)
1566 struct drm_device *dev = crtc->base.dev;
1567 struct drm_i915_private *dev_priv = dev->dev_private;
1568 int pipe = crtc->pipe;
1569 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1570 int dpll = DPLL(crtc->pipe);
1573 assert_pipe_disabled(dev_priv, crtc->pipe);
1575 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1577 mutex_lock(&dev_priv->dpio_lock);
1579 /* Enable back the 10bit clock to display controller */
1580 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1581 tmp |= DPIO_DCLKP_EN;
1582 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1585 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1590 tmp = I915_READ(dpll);
1591 tmp |= DPLL_VCO_ENABLE;
1592 I915_WRITE(dpll, tmp);
1594 /* Check PLL is locked */
1595 if (wait_for(((I915_READ(dpll) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1596 DRM_ERROR("PLL %d failed to lock\n", pipe);
1598 /* Deassert soft data lane reset*/
1599 tmp = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(port));
1600 tmp |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1601 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), tmp);
1604 mutex_unlock(&dev_priv->dpio_lock);
1607 static void i9xx_enable_pll(struct intel_crtc *crtc)
1609 struct drm_device *dev = crtc->base.dev;
1610 struct drm_i915_private *dev_priv = dev->dev_private;
1611 int reg = DPLL(crtc->pipe);
1612 u32 dpll = crtc->config.dpll_hw_state.dpll;
1614 assert_pipe_disabled(dev_priv, crtc->pipe);
1616 /* No really, not for ILK+ */
1617 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1619 /* PLL is protected by panel, make sure we can write it */
1620 if (IS_MOBILE(dev) && !IS_I830(dev))
1621 assert_panel_unlocked(dev_priv, crtc->pipe);
1623 I915_WRITE(reg, dpll);
1625 /* Wait for the clocks to stabilize. */
1629 if (INTEL_INFO(dev)->gen >= 4) {
1630 I915_WRITE(DPLL_MD(crtc->pipe),
1631 crtc->config.dpll_hw_state.dpll_md);
1633 /* The pixel multiplier can only be updated once the
1634 * DPLL is enabled and the clocks are stable.
1636 * So write it again.
1638 I915_WRITE(reg, dpll);
1641 /* We do this three times for luck */
1642 I915_WRITE(reg, dpll);
1644 udelay(150); /* wait for warmup */
1645 I915_WRITE(reg, dpll);
1647 udelay(150); /* wait for warmup */
1648 I915_WRITE(reg, dpll);
1650 udelay(150); /* wait for warmup */
1654 * i9xx_disable_pll - disable a PLL
1655 * @dev_priv: i915 private structure
1656 * @pipe: pipe PLL to disable
1658 * Disable the PLL for @pipe, making sure the pipe is off first.
1660 * Note! This is for pre-ILK only.
1662 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1664 /* Don't disable pipe A or pipe A PLLs if needed */
1665 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1668 /* Make sure the pipe isn't still relying on us */
1669 assert_pipe_disabled(dev_priv, pipe);
1671 I915_WRITE(DPLL(pipe), 0);
1672 POSTING_READ(DPLL(pipe));
1675 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1679 /* Make sure the pipe isn't still relying on us */
1680 assert_pipe_disabled(dev_priv, pipe);
1683 * Leave integrated clock source and reference clock enabled for pipe B.
1684 * The latter is needed for VGA hotplug / manual detection.
1687 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1688 I915_WRITE(DPLL(pipe), val);
1689 POSTING_READ(DPLL(pipe));
1693 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1695 int dpll = DPLL(pipe);
1698 /* Set PLL en = 0 */
1699 val = I915_READ(dpll);
1700 val &= ~DPLL_VCO_ENABLE;
1701 I915_WRITE(dpll, val);
1705 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1706 struct intel_digital_port *dport)
1711 switch (dport->port) {
1713 port_mask = DPLL_PORTB_READY_MASK;
1717 port_mask = DPLL_PORTC_READY_MASK;
1721 port_mask = DPLL_PORTD_READY_MASK;
1722 dpll_reg = DPIO_PHY_STATUS;
1728 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1729 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1730 port_name(dport->port), I915_READ(dpll_reg));
1734 * ironlake_enable_shared_dpll - enable PCH PLL
1735 * @dev_priv: i915 private structure
1736 * @pipe: pipe PLL to enable
1738 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1739 * drives the transcoder clock.
1741 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1743 struct drm_device *dev = crtc->base.dev;
1744 struct drm_i915_private *dev_priv = dev->dev_private;
1745 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1747 /* PCH PLLs only available on ILK, SNB and IVB */
1748 BUG_ON(INTEL_INFO(dev)->gen < 5);
1749 if (WARN_ON(pll == NULL))
1752 if (WARN_ON(pll->refcount == 0))
1755 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1756 pll->name, pll->active, pll->on,
1757 crtc->base.base.id);
1759 if (pll->active++) {
1761 assert_shared_dpll_enabled(dev_priv, pll);
1766 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1767 pll->enable(dev_priv, pll);
1771 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1773 struct drm_device *dev = crtc->base.dev;
1774 struct drm_i915_private *dev_priv = dev->dev_private;
1775 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1777 /* PCH only available on ILK+ */
1778 BUG_ON(INTEL_INFO(dev)->gen < 5);
1779 if (WARN_ON(pll == NULL))
1782 if (WARN_ON(pll->refcount == 0))
1785 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1786 pll->name, pll->active, pll->on,
1787 crtc->base.base.id);
1789 if (WARN_ON(pll->active == 0)) {
1790 assert_shared_dpll_disabled(dev_priv, pll);
1794 assert_shared_dpll_enabled(dev_priv, pll);
1799 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1800 pll->disable(dev_priv, pll);
1804 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1807 struct drm_device *dev = dev_priv->dev;
1808 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1809 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1810 uint32_t reg, val, pipeconf_val;
1812 /* PCH only available on ILK+ */
1813 BUG_ON(INTEL_INFO(dev)->gen < 5);
1815 /* Make sure PCH DPLL is enabled */
1816 assert_shared_dpll_enabled(dev_priv,
1817 intel_crtc_to_shared_dpll(intel_crtc));
1819 /* FDI must be feeding us bits for PCH ports */
1820 assert_fdi_tx_enabled(dev_priv, pipe);
1821 assert_fdi_rx_enabled(dev_priv, pipe);
1823 if (HAS_PCH_CPT(dev)) {
1824 /* Workaround: Set the timing override bit before enabling the
1825 * pch transcoder. */
1826 reg = TRANS_CHICKEN2(pipe);
1827 val = I915_READ(reg);
1828 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1829 I915_WRITE(reg, val);
1832 reg = PCH_TRANSCONF(pipe);
1833 val = I915_READ(reg);
1834 pipeconf_val = I915_READ(PIPECONF(pipe));
1836 if (HAS_PCH_IBX(dev_priv->dev)) {
1838 * make the BPC in transcoder be consistent with
1839 * that in pipeconf reg.
1841 val &= ~PIPECONF_BPC_MASK;
1842 val |= pipeconf_val & PIPECONF_BPC_MASK;
1845 val &= ~TRANS_INTERLACE_MASK;
1846 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1847 if (HAS_PCH_IBX(dev_priv->dev) &&
1848 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1849 val |= TRANS_LEGACY_INTERLACED_ILK;
1851 val |= TRANS_INTERLACED;
1853 val |= TRANS_PROGRESSIVE;
1855 I915_WRITE(reg, val | TRANS_ENABLE);
1856 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1857 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1860 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1861 enum transcoder cpu_transcoder)
1863 u32 val, pipeconf_val;
1865 /* PCH only available on ILK+ */
1866 BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1868 /* FDI must be feeding us bits for PCH ports */
1869 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1870 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1872 /* Workaround: set timing override bit. */
1873 val = I915_READ(_TRANSA_CHICKEN2);
1874 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1875 I915_WRITE(_TRANSA_CHICKEN2, val);
1878 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1880 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1881 PIPECONF_INTERLACED_ILK)
1882 val |= TRANS_INTERLACED;
1884 val |= TRANS_PROGRESSIVE;
1886 I915_WRITE(LPT_TRANSCONF, val);
1887 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1888 DRM_ERROR("Failed to enable PCH transcoder\n");
1891 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1894 struct drm_device *dev = dev_priv->dev;
1897 /* FDI relies on the transcoder */
1898 assert_fdi_tx_disabled(dev_priv, pipe);
1899 assert_fdi_rx_disabled(dev_priv, pipe);
1901 /* Ports must be off as well */
1902 assert_pch_ports_disabled(dev_priv, pipe);
1904 reg = PCH_TRANSCONF(pipe);
1905 val = I915_READ(reg);
1906 val &= ~TRANS_ENABLE;
1907 I915_WRITE(reg, val);
1908 /* wait for PCH transcoder off, transcoder state */
1909 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1910 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1912 if (!HAS_PCH_IBX(dev)) {
1913 /* Workaround: Clear the timing override chicken bit again. */
1914 reg = TRANS_CHICKEN2(pipe);
1915 val = I915_READ(reg);
1916 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1917 I915_WRITE(reg, val);
1921 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1925 val = I915_READ(LPT_TRANSCONF);
1926 val &= ~TRANS_ENABLE;
1927 I915_WRITE(LPT_TRANSCONF, val);
1928 /* wait for PCH transcoder off, transcoder state */
1929 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1930 DRM_ERROR("Failed to disable PCH transcoder\n");
1932 /* Workaround: clear timing override bit. */
1933 val = I915_READ(_TRANSA_CHICKEN2);
1934 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1935 I915_WRITE(_TRANSA_CHICKEN2, val);
1939 * intel_enable_pipe - enable a pipe, asserting requirements
1940 * @crtc: crtc responsible for the pipe
1942 * Enable @crtc's pipe, making sure that various hardware specific requirements
1943 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1945 static void intel_enable_pipe(struct intel_crtc *crtc)
1947 struct drm_device *dev = crtc->base.dev;
1948 struct drm_i915_private *dev_priv = dev->dev_private;
1949 enum pipe pipe = crtc->pipe;
1950 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1952 enum pipe pch_transcoder;
1956 assert_planes_disabled(dev_priv, pipe);
1957 assert_cursor_disabled(dev_priv, pipe);
1958 assert_sprites_disabled(dev_priv, pipe);
1960 if (HAS_PCH_LPT(dev_priv->dev))
1961 pch_transcoder = TRANSCODER_A;
1963 pch_transcoder = pipe;
1966 * A pipe without a PLL won't actually be able to drive bits from
1967 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1970 if (!HAS_PCH_SPLIT(dev_priv->dev))
1971 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
1972 assert_dsi_pll_enabled(dev_priv);
1974 assert_pll_enabled(dev_priv, pipe);
1976 if (crtc->config.has_pch_encoder) {
1977 /* if driving the PCH, we need FDI enabled */
1978 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1979 assert_fdi_tx_pll_enabled(dev_priv,
1980 (enum pipe) cpu_transcoder);
1982 /* FIXME: assert CPU port conditions for SNB+ */
1985 reg = PIPECONF(cpu_transcoder);
1986 val = I915_READ(reg);
1987 if (val & PIPECONF_ENABLE) {
1988 WARN_ON(!(pipe == PIPE_A &&
1989 dev_priv->quirks & QUIRK_PIPEA_FORCE));
1993 I915_WRITE(reg, val | PIPECONF_ENABLE);
1998 * intel_disable_pipe - disable a pipe, asserting requirements
1999 * @dev_priv: i915 private structure
2000 * @pipe: pipe to disable
2002 * Disable @pipe, making sure that various hardware specific requirements
2003 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
2005 * @pipe should be %PIPE_A or %PIPE_B.
2007 * Will wait until the pipe has shut down before returning.
2009 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
2012 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2018 * Make sure planes won't keep trying to pump pixels to us,
2019 * or we might hang the display.
2021 assert_planes_disabled(dev_priv, pipe);
2022 assert_cursor_disabled(dev_priv, pipe);
2023 assert_sprites_disabled(dev_priv, pipe);
2025 /* Don't disable pipe A or pipe A PLLs if needed */
2026 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2029 reg = PIPECONF(cpu_transcoder);
2030 val = I915_READ(reg);
2031 if ((val & PIPECONF_ENABLE) == 0)
2034 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
2035 intel_wait_for_pipe_off(dev_priv->dev, pipe);
2039 * Plane regs are double buffered, going from enabled->disabled needs a
2040 * trigger in order to latch. The display address reg provides this.
2042 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2045 struct drm_device *dev = dev_priv->dev;
2046 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2048 I915_WRITE(reg, I915_READ(reg));
2053 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2054 * @dev_priv: i915 private structure
2055 * @plane: plane to enable
2056 * @pipe: pipe being fed
2058 * Enable @plane on @pipe, making sure that @pipe is running first.
2060 static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
2061 enum plane plane, enum pipe pipe)
2063 struct intel_crtc *intel_crtc =
2064 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2068 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2069 assert_pipe_enabled(dev_priv, pipe);
2071 if (intel_crtc->primary_enabled)
2074 intel_crtc->primary_enabled = true;
2076 reg = DSPCNTR(plane);
2077 val = I915_READ(reg);
2078 WARN_ON(val & DISPLAY_PLANE_ENABLE);
2080 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
2081 intel_flush_primary_plane(dev_priv, plane);
2082 intel_wait_for_vblank(dev_priv->dev, pipe);
2086 * intel_disable_primary_hw_plane - disable the primary hardware plane
2087 * @dev_priv: i915 private structure
2088 * @plane: plane to disable
2089 * @pipe: pipe consuming the data
2091 * Disable @plane; should be an independent operation.
2093 static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
2094 enum plane plane, enum pipe pipe)
2096 struct intel_crtc *intel_crtc =
2097 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2101 if (!intel_crtc->primary_enabled)
2104 intel_crtc->primary_enabled = false;
2106 reg = DSPCNTR(plane);
2107 val = I915_READ(reg);
2108 WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0);
2110 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
2111 intel_flush_primary_plane(dev_priv, plane);
2112 intel_wait_for_vblank(dev_priv->dev, pipe);
2115 static bool need_vtd_wa(struct drm_device *dev)
2117 #ifdef CONFIG_INTEL_IOMMU
2118 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2124 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2128 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2129 return ALIGN(height, tile_height);
2133 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2134 struct drm_i915_gem_object *obj,
2135 struct intel_ring_buffer *pipelined)
2137 struct drm_i915_private *dev_priv = dev->dev_private;
2141 switch (obj->tiling_mode) {
2142 case I915_TILING_NONE:
2143 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2144 alignment = 128 * 1024;
2145 else if (INTEL_INFO(dev)->gen >= 4)
2146 alignment = 4 * 1024;
2148 alignment = 64 * 1024;
2151 /* pin() will align the object as required by fence */
2155 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2161 /* Note that the w/a also requires 64 PTE of padding following the
2162 * bo. We currently fill all unused PTE with the shadow page and so
2163 * we should always have valid PTE following the scanout preventing
2166 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2167 alignment = 256 * 1024;
2169 dev_priv->mm.interruptible = false;
2170 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2172 goto err_interruptible;
2174 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2175 * fence, whereas 965+ only requires a fence if using
2176 * framebuffer compression. For simplicity, we always install
2177 * a fence as the cost is not that onerous.
2179 ret = i915_gem_object_get_fence(obj);
2183 i915_gem_object_pin_fence(obj);
2185 dev_priv->mm.interruptible = true;
2189 i915_gem_object_unpin_from_display_plane(obj);
2191 dev_priv->mm.interruptible = true;
2195 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2197 i915_gem_object_unpin_fence(obj);
2198 i915_gem_object_unpin_from_display_plane(obj);
2201 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2202 * is assumed to be a power-of-two. */
2203 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2204 unsigned int tiling_mode,
2208 if (tiling_mode != I915_TILING_NONE) {
2209 unsigned int tile_rows, tiles;
2214 tiles = *x / (512/cpp);
2217 return tile_rows * pitch * 8 + tiles * 4096;
2219 unsigned int offset;
2221 offset = *y * pitch + *x * cpp;
2223 *x = (offset & 4095) / cpp;
2224 return offset & -4096;
2228 int intel_format_to_fourcc(int format)
2231 case DISPPLANE_8BPP:
2232 return DRM_FORMAT_C8;
2233 case DISPPLANE_BGRX555:
2234 return DRM_FORMAT_XRGB1555;
2235 case DISPPLANE_BGRX565:
2236 return DRM_FORMAT_RGB565;
2238 case DISPPLANE_BGRX888:
2239 return DRM_FORMAT_XRGB8888;
2240 case DISPPLANE_RGBX888:
2241 return DRM_FORMAT_XBGR8888;
2242 case DISPPLANE_BGRX101010:
2243 return DRM_FORMAT_XRGB2101010;
2244 case DISPPLANE_RGBX101010:
2245 return DRM_FORMAT_XBGR2101010;
2249 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2250 struct intel_plane_config *plane_config)
2252 struct drm_device *dev = crtc->base.dev;
2253 struct drm_i915_gem_object *obj = NULL;
2254 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2255 u32 base = plane_config->base;
2257 if (plane_config->size == 0)
2260 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2261 plane_config->size);
2265 if (plane_config->tiled) {
2266 obj->tiling_mode = I915_TILING_X;
2267 obj->stride = crtc->base.primary->fb->pitches[0];
2270 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2271 mode_cmd.width = crtc->base.primary->fb->width;
2272 mode_cmd.height = crtc->base.primary->fb->height;
2273 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2275 mutex_lock(&dev->struct_mutex);
2277 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2279 DRM_DEBUG_KMS("intel fb init failed\n");
2283 mutex_unlock(&dev->struct_mutex);
2285 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2289 drm_gem_object_unreference(&obj->base);
2290 mutex_unlock(&dev->struct_mutex);
2294 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2295 struct intel_plane_config *plane_config)
2297 struct drm_device *dev = intel_crtc->base.dev;
2299 struct intel_crtc *i;
2300 struct intel_framebuffer *fb;
2302 if (!intel_crtc->base.primary->fb)
2305 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2308 kfree(intel_crtc->base.primary->fb);
2309 intel_crtc->base.primary->fb = NULL;
2312 * Failed to alloc the obj, check to see if we should share
2313 * an fb with another CRTC instead
2315 list_for_each_entry(c, &dev->mode_config.crtc_list, head) {
2316 i = to_intel_crtc(c);
2318 if (c == &intel_crtc->base)
2321 if (!i->active || !c->primary->fb)
2324 fb = to_intel_framebuffer(c->primary->fb);
2325 if (i915_gem_obj_ggtt_offset(fb->obj) == plane_config->base) {
2326 drm_framebuffer_reference(c->primary->fb);
2327 intel_crtc->base.primary->fb = c->primary->fb;
2333 static int i9xx_update_primary_plane(struct drm_crtc *crtc,
2334 struct drm_framebuffer *fb,
2337 struct drm_device *dev = crtc->dev;
2338 struct drm_i915_private *dev_priv = dev->dev_private;
2339 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2340 struct intel_framebuffer *intel_fb;
2341 struct drm_i915_gem_object *obj;
2342 int plane = intel_crtc->plane;
2343 unsigned long linear_offset;
2347 intel_fb = to_intel_framebuffer(fb);
2348 obj = intel_fb->obj;
2350 reg = DSPCNTR(plane);
2351 dspcntr = I915_READ(reg);
2352 /* Mask out pixel format bits in case we change it */
2353 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2354 switch (fb->pixel_format) {
2356 dspcntr |= DISPPLANE_8BPP;
2358 case DRM_FORMAT_XRGB1555:
2359 case DRM_FORMAT_ARGB1555:
2360 dspcntr |= DISPPLANE_BGRX555;
2362 case DRM_FORMAT_RGB565:
2363 dspcntr |= DISPPLANE_BGRX565;
2365 case DRM_FORMAT_XRGB8888:
2366 case DRM_FORMAT_ARGB8888:
2367 dspcntr |= DISPPLANE_BGRX888;
2369 case DRM_FORMAT_XBGR8888:
2370 case DRM_FORMAT_ABGR8888:
2371 dspcntr |= DISPPLANE_RGBX888;
2373 case DRM_FORMAT_XRGB2101010:
2374 case DRM_FORMAT_ARGB2101010:
2375 dspcntr |= DISPPLANE_BGRX101010;
2377 case DRM_FORMAT_XBGR2101010:
2378 case DRM_FORMAT_ABGR2101010:
2379 dspcntr |= DISPPLANE_RGBX101010;
2385 if (INTEL_INFO(dev)->gen >= 4) {
2386 if (obj->tiling_mode != I915_TILING_NONE)
2387 dspcntr |= DISPPLANE_TILED;
2389 dspcntr &= ~DISPPLANE_TILED;
2393 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2395 I915_WRITE(reg, dspcntr);
2397 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2399 if (INTEL_INFO(dev)->gen >= 4) {
2400 intel_crtc->dspaddr_offset =
2401 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2402 fb->bits_per_pixel / 8,
2404 linear_offset -= intel_crtc->dspaddr_offset;
2406 intel_crtc->dspaddr_offset = linear_offset;
2409 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2410 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2412 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2413 if (INTEL_INFO(dev)->gen >= 4) {
2414 I915_WRITE(DSPSURF(plane),
2415 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2416 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2417 I915_WRITE(DSPLINOFF(plane), linear_offset);
2419 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2425 static int ironlake_update_primary_plane(struct drm_crtc *crtc,
2426 struct drm_framebuffer *fb,
2429 struct drm_device *dev = crtc->dev;
2430 struct drm_i915_private *dev_priv = dev->dev_private;
2431 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2432 struct intel_framebuffer *intel_fb;
2433 struct drm_i915_gem_object *obj;
2434 int plane = intel_crtc->plane;
2435 unsigned long linear_offset;
2439 intel_fb = to_intel_framebuffer(fb);
2440 obj = intel_fb->obj;
2442 reg = DSPCNTR(plane);
2443 dspcntr = I915_READ(reg);
2444 /* Mask out pixel format bits in case we change it */
2445 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2446 switch (fb->pixel_format) {
2448 dspcntr |= DISPPLANE_8BPP;
2450 case DRM_FORMAT_RGB565:
2451 dspcntr |= DISPPLANE_BGRX565;
2453 case DRM_FORMAT_XRGB8888:
2454 case DRM_FORMAT_ARGB8888:
2455 dspcntr |= DISPPLANE_BGRX888;
2457 case DRM_FORMAT_XBGR8888:
2458 case DRM_FORMAT_ABGR8888:
2459 dspcntr |= DISPPLANE_RGBX888;
2461 case DRM_FORMAT_XRGB2101010:
2462 case DRM_FORMAT_ARGB2101010:
2463 dspcntr |= DISPPLANE_BGRX101010;
2465 case DRM_FORMAT_XBGR2101010:
2466 case DRM_FORMAT_ABGR2101010:
2467 dspcntr |= DISPPLANE_RGBX101010;
2473 if (obj->tiling_mode != I915_TILING_NONE)
2474 dspcntr |= DISPPLANE_TILED;
2476 dspcntr &= ~DISPPLANE_TILED;
2478 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2479 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2481 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2483 I915_WRITE(reg, dspcntr);
2485 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2486 intel_crtc->dspaddr_offset =
2487 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2488 fb->bits_per_pixel / 8,
2490 linear_offset -= intel_crtc->dspaddr_offset;
2492 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2493 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2495 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2496 I915_WRITE(DSPSURF(plane),
2497 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2498 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2499 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2501 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2502 I915_WRITE(DSPLINOFF(plane), linear_offset);
2509 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2511 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2512 int x, int y, enum mode_set_atomic state)
2514 struct drm_device *dev = crtc->dev;
2515 struct drm_i915_private *dev_priv = dev->dev_private;
2517 if (dev_priv->display.disable_fbc)
2518 dev_priv->display.disable_fbc(dev);
2519 intel_increase_pllclock(crtc);
2521 return dev_priv->display.update_primary_plane(crtc, fb, x, y);
2524 void intel_display_handle_reset(struct drm_device *dev)
2526 struct drm_i915_private *dev_priv = dev->dev_private;
2527 struct drm_crtc *crtc;
2530 * Flips in the rings have been nuked by the reset,
2531 * so complete all pending flips so that user space
2532 * will get its events and not get stuck.
2534 * Also update the base address of all primary
2535 * planes to the the last fb to make sure we're
2536 * showing the correct fb after a reset.
2538 * Need to make two loops over the crtcs so that we
2539 * don't try to grab a crtc mutex before the
2540 * pending_flip_queue really got woken up.
2543 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2544 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2545 enum plane plane = intel_crtc->plane;
2547 intel_prepare_page_flip(dev, plane);
2548 intel_finish_page_flip_plane(dev, plane);
2551 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2552 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2554 mutex_lock(&crtc->mutex);
2556 * FIXME: Once we have proper support for primary planes (and
2557 * disabling them without disabling the entire crtc) allow again
2558 * a NULL crtc->primary->fb.
2560 if (intel_crtc->active && crtc->primary->fb)
2561 dev_priv->display.update_primary_plane(crtc,
2565 mutex_unlock(&crtc->mutex);
2570 intel_finish_fb(struct drm_framebuffer *old_fb)
2572 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2573 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2574 bool was_interruptible = dev_priv->mm.interruptible;
2577 /* Big Hammer, we also need to ensure that any pending
2578 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2579 * current scanout is retired before unpinning the old
2582 * This should only fail upon a hung GPU, in which case we
2583 * can safely continue.
2585 dev_priv->mm.interruptible = false;
2586 ret = i915_gem_object_finish_gpu(obj);
2587 dev_priv->mm.interruptible = was_interruptible;
2592 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2594 struct drm_device *dev = crtc->dev;
2595 struct drm_i915_private *dev_priv = dev->dev_private;
2596 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2597 unsigned long flags;
2600 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2601 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2604 spin_lock_irqsave(&dev->event_lock, flags);
2605 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2606 spin_unlock_irqrestore(&dev->event_lock, flags);
2612 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2613 struct drm_framebuffer *fb)
2615 struct drm_device *dev = crtc->dev;
2616 struct drm_i915_private *dev_priv = dev->dev_private;
2617 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2618 struct drm_framebuffer *old_fb;
2621 if (intel_crtc_has_pending_flip(crtc)) {
2622 DRM_ERROR("pipe is still busy with an old pageflip\n");
2628 DRM_ERROR("No FB bound\n");
2632 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2633 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2634 plane_name(intel_crtc->plane),
2635 INTEL_INFO(dev)->num_pipes);
2639 mutex_lock(&dev->struct_mutex);
2640 ret = intel_pin_and_fence_fb_obj(dev,
2641 to_intel_framebuffer(fb)->obj,
2643 mutex_unlock(&dev->struct_mutex);
2645 DRM_ERROR("pin & fence failed\n");
2650 * Update pipe size and adjust fitter if needed: the reason for this is
2651 * that in compute_mode_changes we check the native mode (not the pfit
2652 * mode) to see if we can flip rather than do a full mode set. In the
2653 * fastboot case, we'll flip, but if we don't update the pipesrc and
2654 * pfit state, we'll end up with a big fb scanned out into the wrong
2657 * To fix this properly, we need to hoist the checks up into
2658 * compute_mode_changes (or above), check the actual pfit state and
2659 * whether the platform allows pfit disable with pipe active, and only
2660 * then update the pipesrc and pfit state, even on the flip path.
2662 if (i915.fastboot) {
2663 const struct drm_display_mode *adjusted_mode =
2664 &intel_crtc->config.adjusted_mode;
2666 I915_WRITE(PIPESRC(intel_crtc->pipe),
2667 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2668 (adjusted_mode->crtc_vdisplay - 1));
2669 if (!intel_crtc->config.pch_pfit.enabled &&
2670 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2671 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2672 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2673 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2674 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2676 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2677 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2680 ret = dev_priv->display.update_primary_plane(crtc, fb, x, y);
2682 mutex_lock(&dev->struct_mutex);
2683 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2684 mutex_unlock(&dev->struct_mutex);
2685 DRM_ERROR("failed to update base address\n");
2689 old_fb = crtc->primary->fb;
2690 crtc->primary->fb = fb;
2695 if (intel_crtc->active && old_fb != fb)
2696 intel_wait_for_vblank(dev, intel_crtc->pipe);
2697 mutex_lock(&dev->struct_mutex);
2698 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2699 mutex_unlock(&dev->struct_mutex);
2702 mutex_lock(&dev->struct_mutex);
2703 intel_update_fbc(dev);
2704 intel_edp_psr_update(dev);
2705 mutex_unlock(&dev->struct_mutex);
2710 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2712 struct drm_device *dev = crtc->dev;
2713 struct drm_i915_private *dev_priv = dev->dev_private;
2714 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2715 int pipe = intel_crtc->pipe;
2718 /* enable normal train */
2719 reg = FDI_TX_CTL(pipe);
2720 temp = I915_READ(reg);
2721 if (IS_IVYBRIDGE(dev)) {
2722 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2723 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2725 temp &= ~FDI_LINK_TRAIN_NONE;
2726 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2728 I915_WRITE(reg, temp);
2730 reg = FDI_RX_CTL(pipe);
2731 temp = I915_READ(reg);
2732 if (HAS_PCH_CPT(dev)) {
2733 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2734 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2736 temp &= ~FDI_LINK_TRAIN_NONE;
2737 temp |= FDI_LINK_TRAIN_NONE;
2739 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2741 /* wait one idle pattern time */
2745 /* IVB wants error correction enabled */
2746 if (IS_IVYBRIDGE(dev))
2747 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2748 FDI_FE_ERRC_ENABLE);
2751 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2753 return crtc->base.enabled && crtc->active &&
2754 crtc->config.has_pch_encoder;
2757 static void ivb_modeset_global_resources(struct drm_device *dev)
2759 struct drm_i915_private *dev_priv = dev->dev_private;
2760 struct intel_crtc *pipe_B_crtc =
2761 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2762 struct intel_crtc *pipe_C_crtc =
2763 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2767 * When everything is off disable fdi C so that we could enable fdi B
2768 * with all lanes. Note that we don't care about enabled pipes without
2769 * an enabled pch encoder.
2771 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2772 !pipe_has_enabled_pch(pipe_C_crtc)) {
2773 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2774 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2776 temp = I915_READ(SOUTH_CHICKEN1);
2777 temp &= ~FDI_BC_BIFURCATION_SELECT;
2778 DRM_DEBUG_KMS("disabling fdi C rx\n");
2779 I915_WRITE(SOUTH_CHICKEN1, temp);
2783 /* The FDI link training functions for ILK/Ibexpeak. */
2784 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2786 struct drm_device *dev = crtc->dev;
2787 struct drm_i915_private *dev_priv = dev->dev_private;
2788 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2789 int pipe = intel_crtc->pipe;
2790 u32 reg, temp, tries;
2792 /* FDI needs bits from pipe first */
2793 assert_pipe_enabled(dev_priv, pipe);
2795 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2797 reg = FDI_RX_IMR(pipe);
2798 temp = I915_READ(reg);
2799 temp &= ~FDI_RX_SYMBOL_LOCK;
2800 temp &= ~FDI_RX_BIT_LOCK;
2801 I915_WRITE(reg, temp);
2805 /* enable CPU FDI TX and PCH FDI RX */
2806 reg = FDI_TX_CTL(pipe);
2807 temp = I915_READ(reg);
2808 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2809 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2810 temp &= ~FDI_LINK_TRAIN_NONE;
2811 temp |= FDI_LINK_TRAIN_PATTERN_1;
2812 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2814 reg = FDI_RX_CTL(pipe);
2815 temp = I915_READ(reg);
2816 temp &= ~FDI_LINK_TRAIN_NONE;
2817 temp |= FDI_LINK_TRAIN_PATTERN_1;
2818 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2823 /* Ironlake workaround, enable clock pointer after FDI enable*/
2824 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2825 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2826 FDI_RX_PHASE_SYNC_POINTER_EN);
2828 reg = FDI_RX_IIR(pipe);
2829 for (tries = 0; tries < 5; tries++) {
2830 temp = I915_READ(reg);
2831 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2833 if ((temp & FDI_RX_BIT_LOCK)) {
2834 DRM_DEBUG_KMS("FDI train 1 done.\n");
2835 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2840 DRM_ERROR("FDI train 1 fail!\n");
2843 reg = FDI_TX_CTL(pipe);
2844 temp = I915_READ(reg);
2845 temp &= ~FDI_LINK_TRAIN_NONE;
2846 temp |= FDI_LINK_TRAIN_PATTERN_2;
2847 I915_WRITE(reg, temp);
2849 reg = FDI_RX_CTL(pipe);
2850 temp = I915_READ(reg);
2851 temp &= ~FDI_LINK_TRAIN_NONE;
2852 temp |= FDI_LINK_TRAIN_PATTERN_2;
2853 I915_WRITE(reg, temp);
2858 reg = FDI_RX_IIR(pipe);
2859 for (tries = 0; tries < 5; tries++) {
2860 temp = I915_READ(reg);
2861 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2863 if (temp & FDI_RX_SYMBOL_LOCK) {
2864 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2865 DRM_DEBUG_KMS("FDI train 2 done.\n");
2870 DRM_ERROR("FDI train 2 fail!\n");
2872 DRM_DEBUG_KMS("FDI train done\n");
2876 static const int snb_b_fdi_train_param[] = {
2877 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2878 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2879 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2880 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2883 /* The FDI link training functions for SNB/Cougarpoint. */
2884 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2886 struct drm_device *dev = crtc->dev;
2887 struct drm_i915_private *dev_priv = dev->dev_private;
2888 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2889 int pipe = intel_crtc->pipe;
2890 u32 reg, temp, i, retry;
2892 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2894 reg = FDI_RX_IMR(pipe);
2895 temp = I915_READ(reg);
2896 temp &= ~FDI_RX_SYMBOL_LOCK;
2897 temp &= ~FDI_RX_BIT_LOCK;
2898 I915_WRITE(reg, temp);
2903 /* enable CPU FDI TX and PCH FDI RX */
2904 reg = FDI_TX_CTL(pipe);
2905 temp = I915_READ(reg);
2906 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2907 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2908 temp &= ~FDI_LINK_TRAIN_NONE;
2909 temp |= FDI_LINK_TRAIN_PATTERN_1;
2910 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2912 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2913 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2915 I915_WRITE(FDI_RX_MISC(pipe),
2916 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2918 reg = FDI_RX_CTL(pipe);
2919 temp = I915_READ(reg);
2920 if (HAS_PCH_CPT(dev)) {
2921 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2922 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2924 temp &= ~FDI_LINK_TRAIN_NONE;
2925 temp |= FDI_LINK_TRAIN_PATTERN_1;
2927 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2932 for (i = 0; i < 4; i++) {
2933 reg = FDI_TX_CTL(pipe);
2934 temp = I915_READ(reg);
2935 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2936 temp |= snb_b_fdi_train_param[i];
2937 I915_WRITE(reg, temp);
2942 for (retry = 0; retry < 5; retry++) {
2943 reg = FDI_RX_IIR(pipe);
2944 temp = I915_READ(reg);
2945 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2946 if (temp & FDI_RX_BIT_LOCK) {
2947 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2948 DRM_DEBUG_KMS("FDI train 1 done.\n");
2957 DRM_ERROR("FDI train 1 fail!\n");
2960 reg = FDI_TX_CTL(pipe);
2961 temp = I915_READ(reg);
2962 temp &= ~FDI_LINK_TRAIN_NONE;
2963 temp |= FDI_LINK_TRAIN_PATTERN_2;
2965 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2967 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2969 I915_WRITE(reg, temp);
2971 reg = FDI_RX_CTL(pipe);
2972 temp = I915_READ(reg);
2973 if (HAS_PCH_CPT(dev)) {
2974 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2975 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2977 temp &= ~FDI_LINK_TRAIN_NONE;
2978 temp |= FDI_LINK_TRAIN_PATTERN_2;
2980 I915_WRITE(reg, temp);
2985 for (i = 0; i < 4; i++) {
2986 reg = FDI_TX_CTL(pipe);
2987 temp = I915_READ(reg);
2988 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2989 temp |= snb_b_fdi_train_param[i];
2990 I915_WRITE(reg, temp);
2995 for (retry = 0; retry < 5; retry++) {
2996 reg = FDI_RX_IIR(pipe);
2997 temp = I915_READ(reg);
2998 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2999 if (temp & FDI_RX_SYMBOL_LOCK) {
3000 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3001 DRM_DEBUG_KMS("FDI train 2 done.\n");
3010 DRM_ERROR("FDI train 2 fail!\n");
3012 DRM_DEBUG_KMS("FDI train done.\n");
3015 /* Manual link training for Ivy Bridge A0 parts */
3016 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3018 struct drm_device *dev = crtc->dev;
3019 struct drm_i915_private *dev_priv = dev->dev_private;
3020 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3021 int pipe = intel_crtc->pipe;
3022 u32 reg, temp, i, j;
3024 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3026 reg = FDI_RX_IMR(pipe);
3027 temp = I915_READ(reg);
3028 temp &= ~FDI_RX_SYMBOL_LOCK;
3029 temp &= ~FDI_RX_BIT_LOCK;
3030 I915_WRITE(reg, temp);
3035 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3036 I915_READ(FDI_RX_IIR(pipe)));
3038 /* Try each vswing and preemphasis setting twice before moving on */
3039 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3040 /* disable first in case we need to retry */
3041 reg = FDI_TX_CTL(pipe);
3042 temp = I915_READ(reg);
3043 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3044 temp &= ~FDI_TX_ENABLE;
3045 I915_WRITE(reg, temp);
3047 reg = FDI_RX_CTL(pipe);
3048 temp = I915_READ(reg);
3049 temp &= ~FDI_LINK_TRAIN_AUTO;
3050 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3051 temp &= ~FDI_RX_ENABLE;
3052 I915_WRITE(reg, temp);
3054 /* enable CPU FDI TX and PCH FDI RX */
3055 reg = FDI_TX_CTL(pipe);
3056 temp = I915_READ(reg);
3057 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3058 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3059 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3060 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3061 temp |= snb_b_fdi_train_param[j/2];
3062 temp |= FDI_COMPOSITE_SYNC;
3063 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3065 I915_WRITE(FDI_RX_MISC(pipe),
3066 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3068 reg = FDI_RX_CTL(pipe);
3069 temp = I915_READ(reg);
3070 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3071 temp |= FDI_COMPOSITE_SYNC;
3072 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3075 udelay(1); /* should be 0.5us */
3077 for (i = 0; i < 4; i++) {
3078 reg = FDI_RX_IIR(pipe);
3079 temp = I915_READ(reg);
3080 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3082 if (temp & FDI_RX_BIT_LOCK ||
3083 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3084 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3085 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3089 udelay(1); /* should be 0.5us */
3092 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3097 reg = FDI_TX_CTL(pipe);
3098 temp = I915_READ(reg);
3099 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3100 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3101 I915_WRITE(reg, temp);
3103 reg = FDI_RX_CTL(pipe);
3104 temp = I915_READ(reg);
3105 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3106 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3107 I915_WRITE(reg, temp);
3110 udelay(2); /* should be 1.5us */
3112 for (i = 0; i < 4; i++) {
3113 reg = FDI_RX_IIR(pipe);
3114 temp = I915_READ(reg);
3115 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3117 if (temp & FDI_RX_SYMBOL_LOCK ||
3118 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3119 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3120 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3124 udelay(2); /* should be 1.5us */
3127 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3131 DRM_DEBUG_KMS("FDI train done.\n");
3134 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3136 struct drm_device *dev = intel_crtc->base.dev;
3137 struct drm_i915_private *dev_priv = dev->dev_private;
3138 int pipe = intel_crtc->pipe;
3142 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3143 reg = FDI_RX_CTL(pipe);
3144 temp = I915_READ(reg);
3145 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3146 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3147 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3148 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3153 /* Switch from Rawclk to PCDclk */
3154 temp = I915_READ(reg);
3155 I915_WRITE(reg, temp | FDI_PCDCLK);
3160 /* Enable CPU FDI TX PLL, always on for Ironlake */
3161 reg = FDI_TX_CTL(pipe);
3162 temp = I915_READ(reg);
3163 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3164 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3171 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3173 struct drm_device *dev = intel_crtc->base.dev;
3174 struct drm_i915_private *dev_priv = dev->dev_private;
3175 int pipe = intel_crtc->pipe;
3178 /* Switch from PCDclk to Rawclk */
3179 reg = FDI_RX_CTL(pipe);
3180 temp = I915_READ(reg);
3181 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3183 /* Disable CPU FDI TX PLL */
3184 reg = FDI_TX_CTL(pipe);
3185 temp = I915_READ(reg);
3186 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3191 reg = FDI_RX_CTL(pipe);
3192 temp = I915_READ(reg);
3193 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3195 /* Wait for the clocks to turn off. */
3200 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3202 struct drm_device *dev = crtc->dev;
3203 struct drm_i915_private *dev_priv = dev->dev_private;
3204 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3205 int pipe = intel_crtc->pipe;
3208 /* disable CPU FDI tx and PCH FDI rx */
3209 reg = FDI_TX_CTL(pipe);
3210 temp = I915_READ(reg);
3211 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3214 reg = FDI_RX_CTL(pipe);
3215 temp = I915_READ(reg);
3216 temp &= ~(0x7 << 16);
3217 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3218 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3223 /* Ironlake workaround, disable clock pointer after downing FDI */
3224 if (HAS_PCH_IBX(dev)) {
3225 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3228 /* still set train pattern 1 */
3229 reg = FDI_TX_CTL(pipe);
3230 temp = I915_READ(reg);
3231 temp &= ~FDI_LINK_TRAIN_NONE;
3232 temp |= FDI_LINK_TRAIN_PATTERN_1;
3233 I915_WRITE(reg, temp);
3235 reg = FDI_RX_CTL(pipe);
3236 temp = I915_READ(reg);
3237 if (HAS_PCH_CPT(dev)) {
3238 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3239 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3241 temp &= ~FDI_LINK_TRAIN_NONE;
3242 temp |= FDI_LINK_TRAIN_PATTERN_1;
3244 /* BPC in FDI rx is consistent with that in PIPECONF */
3245 temp &= ~(0x07 << 16);
3246 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3247 I915_WRITE(reg, temp);
3253 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3255 struct intel_crtc *crtc;
3257 /* Note that we don't need to be called with mode_config.lock here
3258 * as our list of CRTC objects is static for the lifetime of the
3259 * device and so cannot disappear as we iterate. Similarly, we can
3260 * happily treat the predicates as racy, atomic checks as userspace
3261 * cannot claim and pin a new fb without at least acquring the
3262 * struct_mutex and so serialising with us.
3264 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3265 if (atomic_read(&crtc->unpin_work_count) == 0)
3268 if (crtc->unpin_work)
3269 intel_wait_for_vblank(dev, crtc->pipe);
3277 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3279 struct drm_device *dev = crtc->dev;
3280 struct drm_i915_private *dev_priv = dev->dev_private;
3282 if (crtc->primary->fb == NULL)
3285 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3287 wait_event(dev_priv->pending_flip_queue,
3288 !intel_crtc_has_pending_flip(crtc));
3290 mutex_lock(&dev->struct_mutex);
3291 intel_finish_fb(crtc->primary->fb);
3292 mutex_unlock(&dev->struct_mutex);
3295 /* Program iCLKIP clock to the desired frequency */
3296 static void lpt_program_iclkip(struct drm_crtc *crtc)
3298 struct drm_device *dev = crtc->dev;
3299 struct drm_i915_private *dev_priv = dev->dev_private;
3300 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3301 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3304 mutex_lock(&dev_priv->dpio_lock);
3306 /* It is necessary to ungate the pixclk gate prior to programming
3307 * the divisors, and gate it back when it is done.
3309 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3311 /* Disable SSCCTL */
3312 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3313 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3317 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3318 if (clock == 20000) {
3323 /* The iCLK virtual clock root frequency is in MHz,
3324 * but the adjusted_mode->crtc_clock in in KHz. To get the
3325 * divisors, it is necessary to divide one by another, so we
3326 * convert the virtual clock precision to KHz here for higher
3329 u32 iclk_virtual_root_freq = 172800 * 1000;
3330 u32 iclk_pi_range = 64;
3331 u32 desired_divisor, msb_divisor_value, pi_value;
3333 desired_divisor = (iclk_virtual_root_freq / clock);
3334 msb_divisor_value = desired_divisor / iclk_pi_range;
3335 pi_value = desired_divisor % iclk_pi_range;
3338 divsel = msb_divisor_value - 2;
3339 phaseinc = pi_value;
3342 /* This should not happen with any sane values */
3343 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3344 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3345 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3346 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3348 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3355 /* Program SSCDIVINTPHASE6 */
3356 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3357 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3358 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3359 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3360 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3361 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3362 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3363 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3365 /* Program SSCAUXDIV */
3366 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3367 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3368 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3369 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3371 /* Enable modulator and associated divider */
3372 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3373 temp &= ~SBI_SSCCTL_DISABLE;
3374 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3376 /* Wait for initialization time */
3379 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3381 mutex_unlock(&dev_priv->dpio_lock);
3384 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3385 enum pipe pch_transcoder)
3387 struct drm_device *dev = crtc->base.dev;
3388 struct drm_i915_private *dev_priv = dev->dev_private;
3389 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3391 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3392 I915_READ(HTOTAL(cpu_transcoder)));
3393 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3394 I915_READ(HBLANK(cpu_transcoder)));
3395 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3396 I915_READ(HSYNC(cpu_transcoder)));
3398 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3399 I915_READ(VTOTAL(cpu_transcoder)));
3400 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3401 I915_READ(VBLANK(cpu_transcoder)));
3402 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3403 I915_READ(VSYNC(cpu_transcoder)));
3404 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3405 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3408 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3410 struct drm_i915_private *dev_priv = dev->dev_private;
3413 temp = I915_READ(SOUTH_CHICKEN1);
3414 if (temp & FDI_BC_BIFURCATION_SELECT)
3417 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3418 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3420 temp |= FDI_BC_BIFURCATION_SELECT;
3421 DRM_DEBUG_KMS("enabling fdi C rx\n");
3422 I915_WRITE(SOUTH_CHICKEN1, temp);
3423 POSTING_READ(SOUTH_CHICKEN1);
3426 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3428 struct drm_device *dev = intel_crtc->base.dev;
3429 struct drm_i915_private *dev_priv = dev->dev_private;
3431 switch (intel_crtc->pipe) {
3435 if (intel_crtc->config.fdi_lanes > 2)
3436 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3438 cpt_enable_fdi_bc_bifurcation(dev);
3442 cpt_enable_fdi_bc_bifurcation(dev);
3451 * Enable PCH resources required for PCH ports:
3453 * - FDI training & RX/TX
3454 * - update transcoder timings
3455 * - DP transcoding bits
3458 static void ironlake_pch_enable(struct drm_crtc *crtc)
3460 struct drm_device *dev = crtc->dev;
3461 struct drm_i915_private *dev_priv = dev->dev_private;
3462 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3463 int pipe = intel_crtc->pipe;
3466 assert_pch_transcoder_disabled(dev_priv, pipe);
3468 if (IS_IVYBRIDGE(dev))
3469 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3471 /* Write the TU size bits before fdi link training, so that error
3472 * detection works. */
3473 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3474 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3476 /* For PCH output, training FDI link */
3477 dev_priv->display.fdi_link_train(crtc);
3479 /* We need to program the right clock selection before writing the pixel
3480 * mutliplier into the DPLL. */
3481 if (HAS_PCH_CPT(dev)) {
3484 temp = I915_READ(PCH_DPLL_SEL);
3485 temp |= TRANS_DPLL_ENABLE(pipe);
3486 sel = TRANS_DPLLB_SEL(pipe);
3487 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3491 I915_WRITE(PCH_DPLL_SEL, temp);
3494 /* XXX: pch pll's can be enabled any time before we enable the PCH
3495 * transcoder, and we actually should do this to not upset any PCH
3496 * transcoder that already use the clock when we share it.
3498 * Note that enable_shared_dpll tries to do the right thing, but
3499 * get_shared_dpll unconditionally resets the pll - we need that to have
3500 * the right LVDS enable sequence. */
3501 ironlake_enable_shared_dpll(intel_crtc);
3503 /* set transcoder timing, panel must allow it */
3504 assert_panel_unlocked(dev_priv, pipe);
3505 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3507 intel_fdi_normal_train(crtc);
3509 /* For PCH DP, enable TRANS_DP_CTL */
3510 if (HAS_PCH_CPT(dev) &&
3511 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3512 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3513 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3514 reg = TRANS_DP_CTL(pipe);
3515 temp = I915_READ(reg);
3516 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3517 TRANS_DP_SYNC_MASK |
3519 temp |= (TRANS_DP_OUTPUT_ENABLE |
3520 TRANS_DP_ENH_FRAMING);
3521 temp |= bpc << 9; /* same format but at 11:9 */
3523 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3524 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3525 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3526 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3528 switch (intel_trans_dp_port_sel(crtc)) {
3530 temp |= TRANS_DP_PORT_SEL_B;
3533 temp |= TRANS_DP_PORT_SEL_C;
3536 temp |= TRANS_DP_PORT_SEL_D;
3542 I915_WRITE(reg, temp);
3545 ironlake_enable_pch_transcoder(dev_priv, pipe);
3548 static void lpt_pch_enable(struct drm_crtc *crtc)
3550 struct drm_device *dev = crtc->dev;
3551 struct drm_i915_private *dev_priv = dev->dev_private;
3552 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3553 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3555 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3557 lpt_program_iclkip(crtc);
3559 /* Set transcoder timing. */
3560 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3562 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3565 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3567 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3572 if (pll->refcount == 0) {
3573 WARN(1, "bad %s refcount\n", pll->name);
3577 if (--pll->refcount == 0) {
3579 WARN_ON(pll->active);
3582 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3585 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3587 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3588 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3589 enum intel_dpll_id i;
3592 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3593 crtc->base.base.id, pll->name);
3594 intel_put_shared_dpll(crtc);
3597 if (HAS_PCH_IBX(dev_priv->dev)) {
3598 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3599 i = (enum intel_dpll_id) crtc->pipe;
3600 pll = &dev_priv->shared_dplls[i];
3602 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3603 crtc->base.base.id, pll->name);
3608 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3609 pll = &dev_priv->shared_dplls[i];
3611 /* Only want to check enabled timings first */
3612 if (pll->refcount == 0)
3615 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3616 sizeof(pll->hw_state)) == 0) {
3617 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3619 pll->name, pll->refcount, pll->active);
3625 /* Ok no matching timings, maybe there's a free one? */
3626 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3627 pll = &dev_priv->shared_dplls[i];
3628 if (pll->refcount == 0) {
3629 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3630 crtc->base.base.id, pll->name);
3638 crtc->config.shared_dpll = i;
3639 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3640 pipe_name(crtc->pipe));
3642 if (pll->active == 0) {
3643 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3644 sizeof(pll->hw_state));
3646 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3648 assert_shared_dpll_disabled(dev_priv, pll);
3650 pll->mode_set(dev_priv, pll);
3657 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3659 struct drm_i915_private *dev_priv = dev->dev_private;
3660 int dslreg = PIPEDSL(pipe);
3663 temp = I915_READ(dslreg);
3665 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3666 if (wait_for(I915_READ(dslreg) != temp, 5))
3667 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3671 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3673 struct drm_device *dev = crtc->base.dev;
3674 struct drm_i915_private *dev_priv = dev->dev_private;
3675 int pipe = crtc->pipe;
3677 if (crtc->config.pch_pfit.enabled) {
3678 /* Force use of hard-coded filter coefficients
3679 * as some pre-programmed values are broken,
3682 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3683 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3684 PF_PIPE_SEL_IVB(pipe));
3686 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3687 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3688 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3692 static void intel_enable_planes(struct drm_crtc *crtc)
3694 struct drm_device *dev = crtc->dev;
3695 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3696 struct drm_plane *plane;
3697 struct intel_plane *intel_plane;
3699 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3700 intel_plane = to_intel_plane(plane);
3701 if (intel_plane->pipe == pipe)
3702 intel_plane_restore(&intel_plane->base);
3706 static void intel_disable_planes(struct drm_crtc *crtc)
3708 struct drm_device *dev = crtc->dev;
3709 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3710 struct drm_plane *plane;
3711 struct intel_plane *intel_plane;
3713 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3714 intel_plane = to_intel_plane(plane);
3715 if (intel_plane->pipe == pipe)
3716 intel_plane_disable(&intel_plane->base);
3720 void hsw_enable_ips(struct intel_crtc *crtc)
3722 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3724 if (!crtc->config.ips_enabled)
3727 /* We can only enable IPS after we enable a plane and wait for a vblank.
3728 * We guarantee that the plane is enabled by calling intel_enable_ips
3729 * only after intel_enable_plane. And intel_enable_plane already waits
3730 * for a vblank, so all we need to do here is to enable the IPS bit. */
3731 assert_plane_enabled(dev_priv, crtc->plane);
3732 if (IS_BROADWELL(crtc->base.dev)) {
3733 mutex_lock(&dev_priv->rps.hw_lock);
3734 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3735 mutex_unlock(&dev_priv->rps.hw_lock);
3736 /* Quoting Art Runyan: "its not safe to expect any particular
3737 * value in IPS_CTL bit 31 after enabling IPS through the
3738 * mailbox." Moreover, the mailbox may return a bogus state,
3739 * so we need to just enable it and continue on.
3742 I915_WRITE(IPS_CTL, IPS_ENABLE);
3743 /* The bit only becomes 1 in the next vblank, so this wait here
3744 * is essentially intel_wait_for_vblank. If we don't have this
3745 * and don't wait for vblanks until the end of crtc_enable, then
3746 * the HW state readout code will complain that the expected
3747 * IPS_CTL value is not the one we read. */
3748 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3749 DRM_ERROR("Timed out waiting for IPS enable\n");
3753 void hsw_disable_ips(struct intel_crtc *crtc)
3755 struct drm_device *dev = crtc->base.dev;
3756 struct drm_i915_private *dev_priv = dev->dev_private;
3758 if (!crtc->config.ips_enabled)
3761 assert_plane_enabled(dev_priv, crtc->plane);
3762 if (IS_BROADWELL(dev)) {
3763 mutex_lock(&dev_priv->rps.hw_lock);
3764 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3765 mutex_unlock(&dev_priv->rps.hw_lock);
3766 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3767 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3768 DRM_ERROR("Timed out waiting for IPS disable\n");
3770 I915_WRITE(IPS_CTL, 0);
3771 POSTING_READ(IPS_CTL);
3774 /* We need to wait for a vblank before we can disable the plane. */
3775 intel_wait_for_vblank(dev, crtc->pipe);
3778 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3779 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3781 struct drm_device *dev = crtc->dev;
3782 struct drm_i915_private *dev_priv = dev->dev_private;
3783 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3784 enum pipe pipe = intel_crtc->pipe;
3785 int palreg = PALETTE(pipe);
3787 bool reenable_ips = false;
3789 /* The clocks have to be on to load the palette. */
3790 if (!crtc->enabled || !intel_crtc->active)
3793 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3794 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3795 assert_dsi_pll_enabled(dev_priv);
3797 assert_pll_enabled(dev_priv, pipe);
3800 /* use legacy palette for Ironlake */
3801 if (HAS_PCH_SPLIT(dev))
3802 palreg = LGC_PALETTE(pipe);
3804 /* Workaround : Do not read or write the pipe palette/gamma data while
3805 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3807 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3808 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3809 GAMMA_MODE_MODE_SPLIT)) {
3810 hsw_disable_ips(intel_crtc);
3811 reenable_ips = true;
3814 for (i = 0; i < 256; i++) {
3815 I915_WRITE(palreg + 4 * i,
3816 (intel_crtc->lut_r[i] << 16) |
3817 (intel_crtc->lut_g[i] << 8) |
3818 intel_crtc->lut_b[i]);
3822 hsw_enable_ips(intel_crtc);
3825 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3827 if (!enable && intel_crtc->overlay) {
3828 struct drm_device *dev = intel_crtc->base.dev;
3829 struct drm_i915_private *dev_priv = dev->dev_private;
3831 mutex_lock(&dev->struct_mutex);
3832 dev_priv->mm.interruptible = false;
3833 (void) intel_overlay_switch_off(intel_crtc->overlay);
3834 dev_priv->mm.interruptible = true;
3835 mutex_unlock(&dev->struct_mutex);
3838 /* Let userspace switch the overlay on again. In most cases userspace
3839 * has to recompute where to put it anyway.
3844 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3845 * cursor plane briefly if not already running after enabling the display
3847 * This workaround avoids occasional blank screens when self refresh is
3851 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3853 u32 cntl = I915_READ(CURCNTR(pipe));
3855 if ((cntl & CURSOR_MODE) == 0) {
3856 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3858 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3859 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3860 intel_wait_for_vblank(dev_priv->dev, pipe);
3861 I915_WRITE(CURCNTR(pipe), cntl);
3862 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3863 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3867 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
3869 struct drm_device *dev = crtc->dev;
3870 struct drm_i915_private *dev_priv = dev->dev_private;
3871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3872 int pipe = intel_crtc->pipe;
3873 int plane = intel_crtc->plane;
3875 intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3876 intel_enable_planes(crtc);
3877 /* The fixup needs to happen before cursor is enabled */
3879 g4x_fixup_plane(dev_priv, pipe);
3880 intel_crtc_update_cursor(crtc, true);
3881 intel_crtc_dpms_overlay(intel_crtc, true);
3883 hsw_enable_ips(intel_crtc);
3885 mutex_lock(&dev->struct_mutex);
3886 intel_update_fbc(dev);
3887 mutex_unlock(&dev->struct_mutex);
3890 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
3892 struct drm_device *dev = crtc->dev;
3893 struct drm_i915_private *dev_priv = dev->dev_private;
3894 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3895 int pipe = intel_crtc->pipe;
3896 int plane = intel_crtc->plane;
3898 intel_crtc_wait_for_pending_flips(crtc);
3899 drm_vblank_off(dev, pipe);
3901 if (dev_priv->fbc.plane == plane)
3902 intel_disable_fbc(dev);
3904 hsw_disable_ips(intel_crtc);
3906 intel_crtc_dpms_overlay(intel_crtc, false);
3907 intel_crtc_update_cursor(crtc, false);
3908 intel_disable_planes(crtc);
3909 intel_disable_primary_hw_plane(dev_priv, plane, pipe);
3912 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3914 struct drm_device *dev = crtc->dev;
3915 struct drm_i915_private *dev_priv = dev->dev_private;
3916 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3917 struct intel_encoder *encoder;
3918 int pipe = intel_crtc->pipe;
3920 WARN_ON(!crtc->enabled);
3922 if (intel_crtc->active)
3925 intel_crtc->active = true;
3927 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3928 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3930 for_each_encoder_on_crtc(dev, crtc, encoder)
3931 if (encoder->pre_enable)
3932 encoder->pre_enable(encoder);
3934 if (intel_crtc->config.has_pch_encoder) {
3935 /* Note: FDI PLL enabling _must_ be done before we enable the
3936 * cpu pipes, hence this is separate from all the other fdi/pch
3938 ironlake_fdi_pll_enable(intel_crtc);
3940 assert_fdi_tx_disabled(dev_priv, pipe);
3941 assert_fdi_rx_disabled(dev_priv, pipe);
3944 ironlake_pfit_enable(intel_crtc);
3947 * On ILK+ LUT must be loaded before the pipe is running but with
3950 intel_crtc_load_lut(crtc);
3952 intel_update_watermarks(crtc);
3953 intel_enable_pipe(intel_crtc);
3955 if (intel_crtc->config.has_pch_encoder)
3956 ironlake_pch_enable(crtc);
3958 for_each_encoder_on_crtc(dev, crtc, encoder)
3959 encoder->enable(encoder);
3961 if (HAS_PCH_CPT(dev))
3962 cpt_verify_modeset(dev, intel_crtc->pipe);
3964 intel_crtc_enable_planes(crtc);
3967 * There seems to be a race in PCH platform hw (at least on some
3968 * outputs) where an enabled pipe still completes any pageflip right
3969 * away (as if the pipe is off) instead of waiting for vblank. As soon
3970 * as the first vblank happend, everything works as expected. Hence just
3971 * wait for one vblank before returning to avoid strange things
3974 intel_wait_for_vblank(dev, intel_crtc->pipe);
3977 /* IPS only exists on ULT machines and is tied to pipe A. */
3978 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3980 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3984 * This implements the workaround described in the "notes" section of the mode
3985 * set sequence documentation. When going from no pipes or single pipe to
3986 * multiple pipes, and planes are enabled after the pipe, we need to wait at
3987 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3989 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3991 struct drm_device *dev = crtc->base.dev;
3992 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3994 /* We want to get the other_active_crtc only if there's only 1 other
3996 list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3997 if (!crtc_it->active || crtc_it == crtc)
4000 if (other_active_crtc)
4003 other_active_crtc = crtc_it;
4005 if (!other_active_crtc)
4008 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4009 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4012 static void haswell_crtc_enable(struct drm_crtc *crtc)
4014 struct drm_device *dev = crtc->dev;
4015 struct drm_i915_private *dev_priv = dev->dev_private;
4016 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4017 struct intel_encoder *encoder;
4018 int pipe = intel_crtc->pipe;
4020 WARN_ON(!crtc->enabled);
4022 if (intel_crtc->active)
4025 intel_crtc->active = true;
4027 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4028 if (intel_crtc->config.has_pch_encoder)
4029 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4031 if (intel_crtc->config.has_pch_encoder)
4032 dev_priv->display.fdi_link_train(crtc);
4034 for_each_encoder_on_crtc(dev, crtc, encoder)
4035 if (encoder->pre_enable)
4036 encoder->pre_enable(encoder);
4038 intel_ddi_enable_pipe_clock(intel_crtc);
4040 ironlake_pfit_enable(intel_crtc);
4043 * On ILK+ LUT must be loaded before the pipe is running but with
4046 intel_crtc_load_lut(crtc);
4048 intel_ddi_set_pipe_settings(crtc);
4049 intel_ddi_enable_transcoder_func(crtc);
4051 intel_update_watermarks(crtc);
4052 intel_enable_pipe(intel_crtc);
4054 if (intel_crtc->config.has_pch_encoder)
4055 lpt_pch_enable(crtc);
4057 for_each_encoder_on_crtc(dev, crtc, encoder) {
4058 encoder->enable(encoder);
4059 intel_opregion_notify_encoder(encoder, true);
4062 /* If we change the relative order between pipe/planes enabling, we need
4063 * to change the workaround. */
4064 haswell_mode_set_planes_workaround(intel_crtc);
4065 intel_crtc_enable_planes(crtc);
4068 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4070 struct drm_device *dev = crtc->base.dev;
4071 struct drm_i915_private *dev_priv = dev->dev_private;
4072 int pipe = crtc->pipe;
4074 /* To avoid upsetting the power well on haswell only disable the pfit if
4075 * it's in use. The hw state code will make sure we get this right. */
4076 if (crtc->config.pch_pfit.enabled) {
4077 I915_WRITE(PF_CTL(pipe), 0);
4078 I915_WRITE(PF_WIN_POS(pipe), 0);
4079 I915_WRITE(PF_WIN_SZ(pipe), 0);
4083 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4085 struct drm_device *dev = crtc->dev;
4086 struct drm_i915_private *dev_priv = dev->dev_private;
4087 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4088 struct intel_encoder *encoder;
4089 int pipe = intel_crtc->pipe;
4092 if (!intel_crtc->active)
4095 intel_crtc_disable_planes(crtc);
4097 for_each_encoder_on_crtc(dev, crtc, encoder)
4098 encoder->disable(encoder);
4100 if (intel_crtc->config.has_pch_encoder)
4101 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4103 intel_disable_pipe(dev_priv, pipe);
4105 ironlake_pfit_disable(intel_crtc);
4107 for_each_encoder_on_crtc(dev, crtc, encoder)
4108 if (encoder->post_disable)
4109 encoder->post_disable(encoder);
4111 if (intel_crtc->config.has_pch_encoder) {
4112 ironlake_fdi_disable(crtc);
4114 ironlake_disable_pch_transcoder(dev_priv, pipe);
4115 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4117 if (HAS_PCH_CPT(dev)) {
4118 /* disable TRANS_DP_CTL */
4119 reg = TRANS_DP_CTL(pipe);
4120 temp = I915_READ(reg);
4121 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4122 TRANS_DP_PORT_SEL_MASK);
4123 temp |= TRANS_DP_PORT_SEL_NONE;
4124 I915_WRITE(reg, temp);
4126 /* disable DPLL_SEL */
4127 temp = I915_READ(PCH_DPLL_SEL);
4128 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4129 I915_WRITE(PCH_DPLL_SEL, temp);
4132 /* disable PCH DPLL */
4133 intel_disable_shared_dpll(intel_crtc);
4135 ironlake_fdi_pll_disable(intel_crtc);
4138 intel_crtc->active = false;
4139 intel_update_watermarks(crtc);
4141 mutex_lock(&dev->struct_mutex);
4142 intel_update_fbc(dev);
4143 mutex_unlock(&dev->struct_mutex);
4146 static void haswell_crtc_disable(struct drm_crtc *crtc)
4148 struct drm_device *dev = crtc->dev;
4149 struct drm_i915_private *dev_priv = dev->dev_private;
4150 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4151 struct intel_encoder *encoder;
4152 int pipe = intel_crtc->pipe;
4153 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4155 if (!intel_crtc->active)
4158 intel_crtc_disable_planes(crtc);
4160 for_each_encoder_on_crtc(dev, crtc, encoder) {
4161 intel_opregion_notify_encoder(encoder, false);
4162 encoder->disable(encoder);
4165 if (intel_crtc->config.has_pch_encoder)
4166 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4167 intel_disable_pipe(dev_priv, pipe);
4169 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4171 ironlake_pfit_disable(intel_crtc);
4173 intel_ddi_disable_pipe_clock(intel_crtc);
4175 for_each_encoder_on_crtc(dev, crtc, encoder)
4176 if (encoder->post_disable)
4177 encoder->post_disable(encoder);
4179 if (intel_crtc->config.has_pch_encoder) {
4180 lpt_disable_pch_transcoder(dev_priv);
4181 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4182 intel_ddi_fdi_disable(crtc);
4185 intel_crtc->active = false;
4186 intel_update_watermarks(crtc);
4188 mutex_lock(&dev->struct_mutex);
4189 intel_update_fbc(dev);
4190 mutex_unlock(&dev->struct_mutex);
4193 static void ironlake_crtc_off(struct drm_crtc *crtc)
4195 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4196 intel_put_shared_dpll(intel_crtc);
4199 static void haswell_crtc_off(struct drm_crtc *crtc)
4201 intel_ddi_put_crtc_pll(crtc);
4204 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4206 struct drm_device *dev = crtc->base.dev;
4207 struct drm_i915_private *dev_priv = dev->dev_private;
4208 struct intel_crtc_config *pipe_config = &crtc->config;
4210 if (!crtc->config.gmch_pfit.control)
4214 * The panel fitter should only be adjusted whilst the pipe is disabled,
4215 * according to register description and PRM.
4217 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4218 assert_pipe_disabled(dev_priv, crtc->pipe);
4220 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4221 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4223 /* Border color in case we don't scale up to the full screen. Black by
4224 * default, change to something else for debugging. */
4225 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4228 #define for_each_power_domain(domain, mask) \
4229 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4230 if ((1 << (domain)) & (mask))
4232 enum intel_display_power_domain
4233 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4235 struct drm_device *dev = intel_encoder->base.dev;
4236 struct intel_digital_port *intel_dig_port;
4238 switch (intel_encoder->type) {
4239 case INTEL_OUTPUT_UNKNOWN:
4240 /* Only DDI platforms should ever use this output type */
4241 WARN_ON_ONCE(!HAS_DDI(dev));
4242 case INTEL_OUTPUT_DISPLAYPORT:
4243 case INTEL_OUTPUT_HDMI:
4244 case INTEL_OUTPUT_EDP:
4245 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4246 switch (intel_dig_port->port) {
4248 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4250 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4252 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4254 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4257 return POWER_DOMAIN_PORT_OTHER;
4259 case INTEL_OUTPUT_ANALOG:
4260 return POWER_DOMAIN_PORT_CRT;
4261 case INTEL_OUTPUT_DSI:
4262 return POWER_DOMAIN_PORT_DSI;
4264 return POWER_DOMAIN_PORT_OTHER;
4268 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4270 struct drm_device *dev = crtc->dev;
4271 struct intel_encoder *intel_encoder;
4272 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4273 enum pipe pipe = intel_crtc->pipe;
4274 bool pfit_enabled = intel_crtc->config.pch_pfit.enabled;
4276 enum transcoder transcoder;
4278 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4280 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4281 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4283 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4285 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4286 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4291 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4294 if (dev_priv->power_domains.init_power_on == enable)
4298 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4300 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4302 dev_priv->power_domains.init_power_on = enable;
4305 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4307 struct drm_i915_private *dev_priv = dev->dev_private;
4308 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4309 struct intel_crtc *crtc;
4312 * First get all needed power domains, then put all unneeded, to avoid
4313 * any unnecessary toggling of the power wells.
4315 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
4316 enum intel_display_power_domain domain;
4318 if (!crtc->base.enabled)
4321 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4323 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4324 intel_display_power_get(dev_priv, domain);
4327 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
4328 enum intel_display_power_domain domain;
4330 for_each_power_domain(domain, crtc->enabled_power_domains)
4331 intel_display_power_put(dev_priv, domain);
4333 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4336 intel_display_set_init_power(dev_priv, false);
4339 int valleyview_get_vco(struct drm_i915_private *dev_priv)
4341 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4343 /* Obtain SKU information */
4344 mutex_lock(&dev_priv->dpio_lock);
4345 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4346 CCK_FUSE_HPLL_FREQ_MASK;
4347 mutex_unlock(&dev_priv->dpio_lock);
4349 return vco_freq[hpll_freq];
4352 /* Adjust CDclk dividers to allow high res or save power if possible */
4353 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4355 struct drm_i915_private *dev_priv = dev->dev_private;
4358 WARN_ON(valleyview_cur_cdclk(dev_priv) != dev_priv->vlv_cdclk_freq);
4359 dev_priv->vlv_cdclk_freq = cdclk;
4361 if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
4363 else if (cdclk == 266)
4368 mutex_lock(&dev_priv->rps.hw_lock);
4369 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4370 val &= ~DSPFREQGUAR_MASK;
4371 val |= (cmd << DSPFREQGUAR_SHIFT);
4372 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4373 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4374 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4376 DRM_ERROR("timed out waiting for CDclk change\n");
4378 mutex_unlock(&dev_priv->rps.hw_lock);
4383 vco = valleyview_get_vco(dev_priv);
4384 divider = ((vco << 1) / cdclk) - 1;
4386 mutex_lock(&dev_priv->dpio_lock);
4387 /* adjust cdclk divider */
4388 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4391 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4392 mutex_unlock(&dev_priv->dpio_lock);
4395 mutex_lock(&dev_priv->dpio_lock);
4396 /* adjust self-refresh exit latency value */
4397 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4401 * For high bandwidth configs, we set a higher latency in the bunit
4402 * so that the core display fetch happens in time to avoid underruns.
4405 val |= 4500 / 250; /* 4.5 usec */
4407 val |= 3000 / 250; /* 3.0 usec */
4408 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4409 mutex_unlock(&dev_priv->dpio_lock);
4411 /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4412 intel_i2c_reset(dev);
4415 int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4420 vco = valleyview_get_vco(dev_priv);
4422 mutex_lock(&dev_priv->dpio_lock);
4423 divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4424 mutex_unlock(&dev_priv->dpio_lock);
4428 cur_cdclk = (vco << 1) / (divider + 1);
4433 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4437 * Really only a few cases to deal with, as only 4 CDclks are supported:
4442 * So we check to see whether we're above 90% of the lower bin and
4445 if (max_pixclk > 288000) {
4447 } else if (max_pixclk > 240000) {
4451 /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4454 /* compute the max pixel clock for new configuration */
4455 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4457 struct drm_device *dev = dev_priv->dev;
4458 struct intel_crtc *intel_crtc;
4461 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4463 if (intel_crtc->new_enabled)
4464 max_pixclk = max(max_pixclk,
4465 intel_crtc->new_config->adjusted_mode.crtc_clock);
4471 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4472 unsigned *prepare_pipes)
4474 struct drm_i915_private *dev_priv = dev->dev_private;
4475 struct intel_crtc *intel_crtc;
4476 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4478 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4479 dev_priv->vlv_cdclk_freq)
4482 /* disable/enable all currently active pipes while we change cdclk */
4483 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4485 if (intel_crtc->base.enabled)
4486 *prepare_pipes |= (1 << intel_crtc->pipe);
4489 static void valleyview_modeset_global_resources(struct drm_device *dev)
4491 struct drm_i915_private *dev_priv = dev->dev_private;
4492 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4493 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4495 if (req_cdclk != dev_priv->vlv_cdclk_freq)
4496 valleyview_set_cdclk(dev, req_cdclk);
4497 modeset_update_crtc_power_domains(dev);
4500 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4502 struct drm_device *dev = crtc->dev;
4503 struct drm_i915_private *dev_priv = dev->dev_private;
4504 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4505 struct intel_encoder *encoder;
4506 int pipe = intel_crtc->pipe;
4509 WARN_ON(!crtc->enabled);
4511 if (intel_crtc->active)
4514 intel_crtc->active = true;
4516 for_each_encoder_on_crtc(dev, crtc, encoder)
4517 if (encoder->pre_pll_enable)
4518 encoder->pre_pll_enable(encoder);
4520 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4523 if (IS_CHERRYVIEW(dev))
4524 chv_enable_pll(intel_crtc);
4526 vlv_enable_pll(intel_crtc);
4529 for_each_encoder_on_crtc(dev, crtc, encoder)
4530 if (encoder->pre_enable)
4531 encoder->pre_enable(encoder);
4533 i9xx_pfit_enable(intel_crtc);
4535 intel_crtc_load_lut(crtc);
4537 intel_update_watermarks(crtc);
4538 intel_enable_pipe(intel_crtc);
4539 intel_wait_for_vblank(dev_priv->dev, pipe);
4540 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4542 for_each_encoder_on_crtc(dev, crtc, encoder)
4543 encoder->enable(encoder);
4545 intel_crtc_enable_planes(crtc);
4548 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4550 struct drm_device *dev = crtc->dev;
4551 struct drm_i915_private *dev_priv = dev->dev_private;
4552 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4553 struct intel_encoder *encoder;
4554 int pipe = intel_crtc->pipe;
4556 WARN_ON(!crtc->enabled);
4558 if (intel_crtc->active)
4561 intel_crtc->active = true;
4563 for_each_encoder_on_crtc(dev, crtc, encoder)
4564 if (encoder->pre_enable)
4565 encoder->pre_enable(encoder);
4567 i9xx_enable_pll(intel_crtc);
4569 i9xx_pfit_enable(intel_crtc);
4571 intel_crtc_load_lut(crtc);
4573 intel_update_watermarks(crtc);
4574 intel_enable_pipe(intel_crtc);
4575 intel_wait_for_vblank(dev_priv->dev, pipe);
4576 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4578 for_each_encoder_on_crtc(dev, crtc, encoder)
4579 encoder->enable(encoder);
4581 intel_crtc_enable_planes(crtc);
4584 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4586 struct drm_device *dev = crtc->base.dev;
4587 struct drm_i915_private *dev_priv = dev->dev_private;
4589 if (!crtc->config.gmch_pfit.control)
4592 assert_pipe_disabled(dev_priv, crtc->pipe);
4594 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4595 I915_READ(PFIT_CONTROL));
4596 I915_WRITE(PFIT_CONTROL, 0);
4599 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4601 struct drm_device *dev = crtc->dev;
4602 struct drm_i915_private *dev_priv = dev->dev_private;
4603 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4604 struct intel_encoder *encoder;
4605 int pipe = intel_crtc->pipe;
4607 if (!intel_crtc->active)
4610 intel_crtc_disable_planes(crtc);
4612 for_each_encoder_on_crtc(dev, crtc, encoder)
4613 encoder->disable(encoder);
4615 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4616 intel_disable_pipe(dev_priv, pipe);
4618 i9xx_pfit_disable(intel_crtc);
4620 for_each_encoder_on_crtc(dev, crtc, encoder)
4621 if (encoder->post_disable)
4622 encoder->post_disable(encoder);
4624 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4625 if (IS_CHERRYVIEW(dev))
4626 chv_disable_pll(dev_priv, pipe);
4627 else if (IS_VALLEYVIEW(dev))
4628 vlv_disable_pll(dev_priv, pipe);
4630 i9xx_disable_pll(dev_priv, pipe);
4633 intel_crtc->active = false;
4634 intel_update_watermarks(crtc);
4636 intel_update_fbc(dev);
4639 static void i9xx_crtc_off(struct drm_crtc *crtc)
4643 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4646 struct drm_device *dev = crtc->dev;
4647 struct drm_i915_master_private *master_priv;
4648 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4649 int pipe = intel_crtc->pipe;
4651 if (!dev->primary->master)
4654 master_priv = dev->primary->master->driver_priv;
4655 if (!master_priv->sarea_priv)
4660 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4661 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4664 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4665 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4668 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4674 * Sets the power management mode of the pipe and plane.
4676 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4678 struct drm_device *dev = crtc->dev;
4679 struct drm_i915_private *dev_priv = dev->dev_private;
4680 struct intel_encoder *intel_encoder;
4681 bool enable = false;
4683 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4684 enable |= intel_encoder->connectors_active;
4687 dev_priv->display.crtc_enable(crtc);
4689 dev_priv->display.crtc_disable(crtc);
4691 intel_crtc_update_sarea(crtc, enable);
4694 static void intel_crtc_disable(struct drm_crtc *crtc)
4696 struct drm_device *dev = crtc->dev;
4697 struct drm_connector *connector;
4698 struct drm_i915_private *dev_priv = dev->dev_private;
4699 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4701 /* crtc should still be enabled when we disable it. */
4702 WARN_ON(!crtc->enabled);
4704 dev_priv->display.crtc_disable(crtc);
4705 intel_crtc->eld_vld = false;
4706 intel_crtc_update_sarea(crtc, false);
4707 dev_priv->display.off(crtc);
4709 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4710 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4711 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4713 if (crtc->primary->fb) {
4714 mutex_lock(&dev->struct_mutex);
4715 intel_unpin_fb_obj(to_intel_framebuffer(crtc->primary->fb)->obj);
4716 mutex_unlock(&dev->struct_mutex);
4717 crtc->primary->fb = NULL;
4720 /* Update computed state. */
4721 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4722 if (!connector->encoder || !connector->encoder->crtc)
4725 if (connector->encoder->crtc != crtc)
4728 connector->dpms = DRM_MODE_DPMS_OFF;
4729 to_intel_encoder(connector->encoder)->connectors_active = false;
4733 void intel_encoder_destroy(struct drm_encoder *encoder)
4735 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4737 drm_encoder_cleanup(encoder);
4738 kfree(intel_encoder);
4741 /* Simple dpms helper for encoders with just one connector, no cloning and only
4742 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4743 * state of the entire output pipe. */
4744 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4746 if (mode == DRM_MODE_DPMS_ON) {
4747 encoder->connectors_active = true;
4749 intel_crtc_update_dpms(encoder->base.crtc);
4751 encoder->connectors_active = false;
4753 intel_crtc_update_dpms(encoder->base.crtc);
4757 /* Cross check the actual hw state with our own modeset state tracking (and it's
4758 * internal consistency). */
4759 static void intel_connector_check_state(struct intel_connector *connector)
4761 if (connector->get_hw_state(connector)) {
4762 struct intel_encoder *encoder = connector->encoder;
4763 struct drm_crtc *crtc;
4764 bool encoder_enabled;
4767 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4768 connector->base.base.id,
4769 drm_get_connector_name(&connector->base));
4771 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4772 "wrong connector dpms state\n");
4773 WARN(connector->base.encoder != &encoder->base,
4774 "active connector not linked to encoder\n");
4775 WARN(!encoder->connectors_active,
4776 "encoder->connectors_active not set\n");
4778 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4779 WARN(!encoder_enabled, "encoder not enabled\n");
4780 if (WARN_ON(!encoder->base.crtc))
4783 crtc = encoder->base.crtc;
4785 WARN(!crtc->enabled, "crtc not enabled\n");
4786 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4787 WARN(pipe != to_intel_crtc(crtc)->pipe,
4788 "encoder active on the wrong pipe\n");
4792 /* Even simpler default implementation, if there's really no special case to
4794 void intel_connector_dpms(struct drm_connector *connector, int mode)
4796 /* All the simple cases only support two dpms states. */
4797 if (mode != DRM_MODE_DPMS_ON)
4798 mode = DRM_MODE_DPMS_OFF;
4800 if (mode == connector->dpms)
4803 connector->dpms = mode;
4805 /* Only need to change hw state when actually enabled */
4806 if (connector->encoder)
4807 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
4809 intel_modeset_check_state(connector->dev);
4812 /* Simple connector->get_hw_state implementation for encoders that support only
4813 * one connector and no cloning and hence the encoder state determines the state
4814 * of the connector. */
4815 bool intel_connector_get_hw_state(struct intel_connector *connector)
4818 struct intel_encoder *encoder = connector->encoder;
4820 return encoder->get_hw_state(encoder, &pipe);
4823 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4824 struct intel_crtc_config *pipe_config)
4826 struct drm_i915_private *dev_priv = dev->dev_private;
4827 struct intel_crtc *pipe_B_crtc =
4828 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4830 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4831 pipe_name(pipe), pipe_config->fdi_lanes);
4832 if (pipe_config->fdi_lanes > 4) {
4833 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4834 pipe_name(pipe), pipe_config->fdi_lanes);
4838 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4839 if (pipe_config->fdi_lanes > 2) {
4840 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4841 pipe_config->fdi_lanes);
4848 if (INTEL_INFO(dev)->num_pipes == 2)
4851 /* Ivybridge 3 pipe is really complicated */
4856 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4857 pipe_config->fdi_lanes > 2) {
4858 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4859 pipe_name(pipe), pipe_config->fdi_lanes);
4864 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4865 pipe_B_crtc->config.fdi_lanes <= 2) {
4866 if (pipe_config->fdi_lanes > 2) {
4867 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4868 pipe_name(pipe), pipe_config->fdi_lanes);
4872 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4882 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4883 struct intel_crtc_config *pipe_config)
4885 struct drm_device *dev = intel_crtc->base.dev;
4886 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4887 int lane, link_bw, fdi_dotclock;
4888 bool setup_ok, needs_recompute = false;
4891 /* FDI is a binary signal running at ~2.7GHz, encoding
4892 * each output octet as 10 bits. The actual frequency
4893 * is stored as a divider into a 100MHz clock, and the
4894 * mode pixel clock is stored in units of 1KHz.
4895 * Hence the bw of each lane in terms of the mode signal
4898 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4900 fdi_dotclock = adjusted_mode->crtc_clock;
4902 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4903 pipe_config->pipe_bpp);
4905 pipe_config->fdi_lanes = lane;
4907 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4908 link_bw, &pipe_config->fdi_m_n);
4910 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4911 intel_crtc->pipe, pipe_config);
4912 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4913 pipe_config->pipe_bpp -= 2*3;
4914 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4915 pipe_config->pipe_bpp);
4916 needs_recompute = true;
4917 pipe_config->bw_constrained = true;
4922 if (needs_recompute)
4925 return setup_ok ? 0 : -EINVAL;
4928 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4929 struct intel_crtc_config *pipe_config)
4931 pipe_config->ips_enabled = i915.enable_ips &&
4932 hsw_crtc_supports_ips(crtc) &&
4933 pipe_config->pipe_bpp <= 24;
4936 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4937 struct intel_crtc_config *pipe_config)
4939 struct drm_device *dev = crtc->base.dev;
4940 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4942 /* FIXME should check pixel clock limits on all platforms */
4943 if (INTEL_INFO(dev)->gen < 4) {
4944 struct drm_i915_private *dev_priv = dev->dev_private;
4946 dev_priv->display.get_display_clock_speed(dev);
4949 * Enable pixel doubling when the dot clock
4950 * is > 90% of the (display) core speed.
4952 * GDG double wide on either pipe,
4953 * otherwise pipe A only.
4955 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4956 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
4958 pipe_config->double_wide = true;
4961 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
4966 * Pipe horizontal size must be even in:
4968 * - LVDS dual channel mode
4969 * - Double wide pipe
4971 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4972 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4973 pipe_config->pipe_src_w &= ~1;
4975 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4976 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4978 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4979 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4982 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4983 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4984 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4985 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4987 pipe_config->pipe_bpp = 8*3;
4991 hsw_compute_ips_config(crtc, pipe_config);
4993 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4994 * clock survives for now. */
4995 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4996 pipe_config->shared_dpll = crtc->config.shared_dpll;
4998 if (pipe_config->has_pch_encoder)
4999 return ironlake_fdi_compute_config(crtc, pipe_config);
5004 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5006 return 400000; /* FIXME */
5009 static int i945_get_display_clock_speed(struct drm_device *dev)
5014 static int i915_get_display_clock_speed(struct drm_device *dev)
5019 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5024 static int pnv_get_display_clock_speed(struct drm_device *dev)
5028 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5030 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5031 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5033 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5035 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5037 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5040 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5041 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5043 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5048 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5052 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5054 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5057 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5058 case GC_DISPLAY_CLOCK_333_MHZ:
5061 case GC_DISPLAY_CLOCK_190_200_MHZ:
5067 static int i865_get_display_clock_speed(struct drm_device *dev)
5072 static int i855_get_display_clock_speed(struct drm_device *dev)
5075 /* Assume that the hardware is in the high speed state. This
5076 * should be the default.
5078 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5079 case GC_CLOCK_133_200:
5080 case GC_CLOCK_100_200:
5082 case GC_CLOCK_166_250:
5084 case GC_CLOCK_100_133:
5088 /* Shouldn't happen */
5092 static int i830_get_display_clock_speed(struct drm_device *dev)
5098 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5100 while (*num > DATA_LINK_M_N_MASK ||
5101 *den > DATA_LINK_M_N_MASK) {
5107 static void compute_m_n(unsigned int m, unsigned int n,
5108 uint32_t *ret_m, uint32_t *ret_n)
5110 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5111 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5112 intel_reduce_m_n_ratio(ret_m, ret_n);
5116 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5117 int pixel_clock, int link_clock,
5118 struct intel_link_m_n *m_n)
5122 compute_m_n(bits_per_pixel * pixel_clock,
5123 link_clock * nlanes * 8,
5124 &m_n->gmch_m, &m_n->gmch_n);
5126 compute_m_n(pixel_clock, link_clock,
5127 &m_n->link_m, &m_n->link_n);
5130 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5132 if (i915.panel_use_ssc >= 0)
5133 return i915.panel_use_ssc != 0;
5134 return dev_priv->vbt.lvds_use_ssc
5135 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5138 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5140 struct drm_device *dev = crtc->dev;
5141 struct drm_i915_private *dev_priv = dev->dev_private;
5144 if (IS_VALLEYVIEW(dev)) {
5146 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5147 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5148 refclk = dev_priv->vbt.lvds_ssc_freq;
5149 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5150 } else if (!IS_GEN2(dev)) {
5159 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5161 return (1 << dpll->n) << 16 | dpll->m2;
5164 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5166 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5169 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5170 intel_clock_t *reduced_clock)
5172 struct drm_device *dev = crtc->base.dev;
5173 struct drm_i915_private *dev_priv = dev->dev_private;
5174 int pipe = crtc->pipe;
5177 if (IS_PINEVIEW(dev)) {
5178 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5180 fp2 = pnv_dpll_compute_fp(reduced_clock);
5182 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5184 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5187 I915_WRITE(FP0(pipe), fp);
5188 crtc->config.dpll_hw_state.fp0 = fp;
5190 crtc->lowfreq_avail = false;
5191 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5192 reduced_clock && i915.powersave) {
5193 I915_WRITE(FP1(pipe), fp2);
5194 crtc->config.dpll_hw_state.fp1 = fp2;
5195 crtc->lowfreq_avail = true;
5197 I915_WRITE(FP1(pipe), fp);
5198 crtc->config.dpll_hw_state.fp1 = fp;
5202 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5208 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5209 * and set it to a reasonable value instead.
5211 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5212 reg_val &= 0xffffff00;
5213 reg_val |= 0x00000030;
5214 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5216 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5217 reg_val &= 0x8cffffff;
5218 reg_val = 0x8c000000;
5219 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5221 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5222 reg_val &= 0xffffff00;
5223 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5225 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5226 reg_val &= 0x00ffffff;
5227 reg_val |= 0xb0000000;
5228 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5231 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5232 struct intel_link_m_n *m_n)
5234 struct drm_device *dev = crtc->base.dev;
5235 struct drm_i915_private *dev_priv = dev->dev_private;
5236 int pipe = crtc->pipe;
5238 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5239 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5240 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5241 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5244 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5245 struct intel_link_m_n *m_n)
5247 struct drm_device *dev = crtc->base.dev;
5248 struct drm_i915_private *dev_priv = dev->dev_private;
5249 int pipe = crtc->pipe;
5250 enum transcoder transcoder = crtc->config.cpu_transcoder;
5252 if (INTEL_INFO(dev)->gen >= 5) {
5253 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5254 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5255 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5256 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5258 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5259 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5260 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5261 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5265 static void intel_dp_set_m_n(struct intel_crtc *crtc)
5267 if (crtc->config.has_pch_encoder)
5268 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5270 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5273 static void vlv_update_pll(struct intel_crtc *crtc)
5275 struct drm_device *dev = crtc->base.dev;
5276 struct drm_i915_private *dev_priv = dev->dev_private;
5277 int pipe = crtc->pipe;
5279 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5280 u32 coreclk, reg_val, dpll_md;
5282 mutex_lock(&dev_priv->dpio_lock);
5284 bestn = crtc->config.dpll.n;
5285 bestm1 = crtc->config.dpll.m1;
5286 bestm2 = crtc->config.dpll.m2;
5287 bestp1 = crtc->config.dpll.p1;
5288 bestp2 = crtc->config.dpll.p2;
5290 /* See eDP HDMI DPIO driver vbios notes doc */
5292 /* PLL B needs special handling */
5294 vlv_pllb_recal_opamp(dev_priv, pipe);
5296 /* Set up Tx target for periodic Rcomp update */
5297 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5299 /* Disable target IRef on PLL */
5300 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5301 reg_val &= 0x00ffffff;
5302 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5304 /* Disable fast lock */
5305 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5307 /* Set idtafcrecal before PLL is enabled */
5308 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5309 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5310 mdiv |= ((bestn << DPIO_N_SHIFT));
5311 mdiv |= (1 << DPIO_K_SHIFT);
5314 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5315 * but we don't support that).
5316 * Note: don't use the DAC post divider as it seems unstable.
5318 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5319 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5321 mdiv |= DPIO_ENABLE_CALIBRATION;
5322 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5324 /* Set HBR and RBR LPF coefficients */
5325 if (crtc->config.port_clock == 162000 ||
5326 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5327 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5328 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5331 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5334 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5335 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5336 /* Use SSC source */
5338 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5341 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5343 } else { /* HDMI or VGA */
5344 /* Use bend source */
5346 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5349 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5353 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5354 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5355 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5356 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5357 coreclk |= 0x01000000;
5358 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5360 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5363 * Enable DPIO clock input. We should never disable the reference
5364 * clock for pipe B, since VGA hotplug / manual detection depends
5367 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5368 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5369 /* We should never disable this, set it here for state tracking */
5371 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5372 dpll |= DPLL_VCO_ENABLE;
5373 crtc->config.dpll_hw_state.dpll = dpll;
5375 dpll_md = (crtc->config.pixel_multiplier - 1)
5376 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5377 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5379 mutex_unlock(&dev_priv->dpio_lock);
5382 static void chv_update_pll(struct intel_crtc *crtc)
5384 struct drm_device *dev = crtc->base.dev;
5385 struct drm_i915_private *dev_priv = dev->dev_private;
5386 int pipe = crtc->pipe;
5387 int dpll_reg = DPLL(crtc->pipe);
5388 enum dpio_channel port = vlv_pipe_to_channel(pipe);
5389 u32 val, loopfilter, intcoeff;
5390 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5393 mutex_lock(&dev_priv->dpio_lock);
5395 bestn = crtc->config.dpll.n;
5396 bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5397 bestm1 = crtc->config.dpll.m1;
5398 bestm2 = crtc->config.dpll.m2 >> 22;
5399 bestp1 = crtc->config.dpll.p1;
5400 bestp2 = crtc->config.dpll.p2;
5403 * Enable Refclk and SSC
5405 val = I915_READ(dpll_reg);
5406 val |= (DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV);
5407 I915_WRITE(dpll_reg, val);
5409 /* Propagate soft reset to data lane reset */
5410 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(port));
5411 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
5412 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), val);
5414 /* Disable 10bit clock to display controller */
5415 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
5416 val &= ~DPIO_DCLKP_EN;
5417 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
5419 /* p1 and p2 divider */
5420 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5421 5 << DPIO_CHV_S1_DIV_SHIFT |
5422 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5423 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5424 1 << DPIO_CHV_K_DIV_SHIFT);
5426 /* Feedback post-divider - m2 */
5427 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5429 /* Feedback refclk divider - n and m1 */
5430 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5431 DPIO_CHV_M1_DIV_BY_2 |
5432 1 << DPIO_CHV_N_DIV_SHIFT);
5434 /* M2 fraction division */
5435 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5437 /* M2 fraction division enable */
5438 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5439 DPIO_CHV_FRAC_DIV_EN |
5440 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5443 refclk = i9xx_get_refclk(&crtc->base, 0);
5444 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5445 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5446 if (refclk == 100000)
5448 else if (refclk == 38400)
5452 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5453 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5456 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5457 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5460 mutex_unlock(&dev_priv->dpio_lock);
5463 static void i9xx_update_pll(struct intel_crtc *crtc,
5464 intel_clock_t *reduced_clock,
5467 struct drm_device *dev = crtc->base.dev;
5468 struct drm_i915_private *dev_priv = dev->dev_private;
5471 struct dpll *clock = &crtc->config.dpll;
5473 i9xx_update_pll_dividers(crtc, reduced_clock);
5475 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5476 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5478 dpll = DPLL_VGA_MODE_DIS;
5480 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5481 dpll |= DPLLB_MODE_LVDS;
5483 dpll |= DPLLB_MODE_DAC_SERIAL;
5485 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5486 dpll |= (crtc->config.pixel_multiplier - 1)
5487 << SDVO_MULTIPLIER_SHIFT_HIRES;
5491 dpll |= DPLL_SDVO_HIGH_SPEED;
5493 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5494 dpll |= DPLL_SDVO_HIGH_SPEED;
5496 /* compute bitmask from p1 value */
5497 if (IS_PINEVIEW(dev))
5498 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5500 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5501 if (IS_G4X(dev) && reduced_clock)
5502 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5504 switch (clock->p2) {
5506 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5509 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5512 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5515 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5518 if (INTEL_INFO(dev)->gen >= 4)
5519 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5521 if (crtc->config.sdvo_tv_clock)
5522 dpll |= PLL_REF_INPUT_TVCLKINBC;
5523 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5524 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5525 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5527 dpll |= PLL_REF_INPUT_DREFCLK;
5529 dpll |= DPLL_VCO_ENABLE;
5530 crtc->config.dpll_hw_state.dpll = dpll;
5532 if (INTEL_INFO(dev)->gen >= 4) {
5533 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5534 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5535 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5539 static void i8xx_update_pll(struct intel_crtc *crtc,
5540 intel_clock_t *reduced_clock,
5543 struct drm_device *dev = crtc->base.dev;
5544 struct drm_i915_private *dev_priv = dev->dev_private;
5546 struct dpll *clock = &crtc->config.dpll;
5548 i9xx_update_pll_dividers(crtc, reduced_clock);
5550 dpll = DPLL_VGA_MODE_DIS;
5552 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5553 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5556 dpll |= PLL_P1_DIVIDE_BY_TWO;
5558 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5560 dpll |= PLL_P2_DIVIDE_BY_4;
5563 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5564 dpll |= DPLL_DVO_2X_MODE;
5566 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5567 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5568 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5570 dpll |= PLL_REF_INPUT_DREFCLK;
5572 dpll |= DPLL_VCO_ENABLE;
5573 crtc->config.dpll_hw_state.dpll = dpll;
5576 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5578 struct drm_device *dev = intel_crtc->base.dev;
5579 struct drm_i915_private *dev_priv = dev->dev_private;
5580 enum pipe pipe = intel_crtc->pipe;
5581 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5582 struct drm_display_mode *adjusted_mode =
5583 &intel_crtc->config.adjusted_mode;
5584 uint32_t crtc_vtotal, crtc_vblank_end;
5587 /* We need to be careful not to changed the adjusted mode, for otherwise
5588 * the hw state checker will get angry at the mismatch. */
5589 crtc_vtotal = adjusted_mode->crtc_vtotal;
5590 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5592 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5593 /* the chip adds 2 halflines automatically */
5595 crtc_vblank_end -= 1;
5597 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5598 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5600 vsyncshift = adjusted_mode->crtc_hsync_start -
5601 adjusted_mode->crtc_htotal / 2;
5603 vsyncshift += adjusted_mode->crtc_htotal;
5606 if (INTEL_INFO(dev)->gen > 3)
5607 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5609 I915_WRITE(HTOTAL(cpu_transcoder),
5610 (adjusted_mode->crtc_hdisplay - 1) |
5611 ((adjusted_mode->crtc_htotal - 1) << 16));
5612 I915_WRITE(HBLANK(cpu_transcoder),
5613 (adjusted_mode->crtc_hblank_start - 1) |
5614 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5615 I915_WRITE(HSYNC(cpu_transcoder),
5616 (adjusted_mode->crtc_hsync_start - 1) |
5617 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5619 I915_WRITE(VTOTAL(cpu_transcoder),
5620 (adjusted_mode->crtc_vdisplay - 1) |
5621 ((crtc_vtotal - 1) << 16));
5622 I915_WRITE(VBLANK(cpu_transcoder),
5623 (adjusted_mode->crtc_vblank_start - 1) |
5624 ((crtc_vblank_end - 1) << 16));
5625 I915_WRITE(VSYNC(cpu_transcoder),
5626 (adjusted_mode->crtc_vsync_start - 1) |
5627 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5629 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5630 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5631 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5633 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5634 (pipe == PIPE_B || pipe == PIPE_C))
5635 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5637 /* pipesrc controls the size that is scaled from, which should
5638 * always be the user's requested size.
5640 I915_WRITE(PIPESRC(pipe),
5641 ((intel_crtc->config.pipe_src_w - 1) << 16) |
5642 (intel_crtc->config.pipe_src_h - 1));
5645 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5646 struct intel_crtc_config *pipe_config)
5648 struct drm_device *dev = crtc->base.dev;
5649 struct drm_i915_private *dev_priv = dev->dev_private;
5650 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5653 tmp = I915_READ(HTOTAL(cpu_transcoder));
5654 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5655 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5656 tmp = I915_READ(HBLANK(cpu_transcoder));
5657 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5658 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5659 tmp = I915_READ(HSYNC(cpu_transcoder));
5660 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5661 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5663 tmp = I915_READ(VTOTAL(cpu_transcoder));
5664 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5665 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5666 tmp = I915_READ(VBLANK(cpu_transcoder));
5667 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5668 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5669 tmp = I915_READ(VSYNC(cpu_transcoder));
5670 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5671 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5673 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5674 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5675 pipe_config->adjusted_mode.crtc_vtotal += 1;
5676 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5679 tmp = I915_READ(PIPESRC(crtc->pipe));
5680 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5681 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5683 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5684 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5687 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5688 struct intel_crtc_config *pipe_config)
5690 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5691 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5692 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5693 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5695 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5696 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5697 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5698 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5700 mode->flags = pipe_config->adjusted_mode.flags;
5702 mode->clock = pipe_config->adjusted_mode.crtc_clock;
5703 mode->flags |= pipe_config->adjusted_mode.flags;
5706 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5708 struct drm_device *dev = intel_crtc->base.dev;
5709 struct drm_i915_private *dev_priv = dev->dev_private;
5714 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5715 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5716 pipeconf |= PIPECONF_ENABLE;
5718 if (intel_crtc->config.double_wide)
5719 pipeconf |= PIPECONF_DOUBLE_WIDE;
5721 /* only g4x and later have fancy bpc/dither controls */
5722 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5723 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5724 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5725 pipeconf |= PIPECONF_DITHER_EN |
5726 PIPECONF_DITHER_TYPE_SP;
5728 switch (intel_crtc->config.pipe_bpp) {
5730 pipeconf |= PIPECONF_6BPC;
5733 pipeconf |= PIPECONF_8BPC;
5736 pipeconf |= PIPECONF_10BPC;
5739 /* Case prevented by intel_choose_pipe_bpp_dither. */
5744 if (HAS_PIPE_CXSR(dev)) {
5745 if (intel_crtc->lowfreq_avail) {
5746 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5747 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5749 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5753 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
5754 if (INTEL_INFO(dev)->gen < 4 ||
5755 intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5756 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5758 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
5760 pipeconf |= PIPECONF_PROGRESSIVE;
5762 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5763 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5765 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5766 POSTING_READ(PIPECONF(intel_crtc->pipe));
5769 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5771 struct drm_framebuffer *fb)
5773 struct drm_device *dev = crtc->dev;
5774 struct drm_i915_private *dev_priv = dev->dev_private;
5775 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5776 int pipe = intel_crtc->pipe;
5777 int plane = intel_crtc->plane;
5778 int refclk, num_connectors = 0;
5779 intel_clock_t clock, reduced_clock;
5781 bool ok, has_reduced_clock = false;
5782 bool is_lvds = false, is_dsi = false;
5783 struct intel_encoder *encoder;
5784 const intel_limit_t *limit;
5787 for_each_encoder_on_crtc(dev, crtc, encoder) {
5788 switch (encoder->type) {
5789 case INTEL_OUTPUT_LVDS:
5792 case INTEL_OUTPUT_DSI:
5803 if (!intel_crtc->config.clock_set) {
5804 refclk = i9xx_get_refclk(crtc, num_connectors);
5807 * Returns a set of divisors for the desired target clock with
5808 * the given refclk, or FALSE. The returned values represent
5809 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5812 limit = intel_limit(crtc, refclk);
5813 ok = dev_priv->display.find_dpll(limit, crtc,
5814 intel_crtc->config.port_clock,
5815 refclk, NULL, &clock);
5817 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5821 if (is_lvds && dev_priv->lvds_downclock_avail) {
5823 * Ensure we match the reduced clock's P to the target
5824 * clock. If the clocks don't match, we can't switch
5825 * the display clock by using the FP0/FP1. In such case
5826 * we will disable the LVDS downclock feature.
5829 dev_priv->display.find_dpll(limit, crtc,
5830 dev_priv->lvds_downclock,
5834 /* Compat-code for transition, will disappear. */
5835 intel_crtc->config.dpll.n = clock.n;
5836 intel_crtc->config.dpll.m1 = clock.m1;
5837 intel_crtc->config.dpll.m2 = clock.m2;
5838 intel_crtc->config.dpll.p1 = clock.p1;
5839 intel_crtc->config.dpll.p2 = clock.p2;
5843 i8xx_update_pll(intel_crtc,
5844 has_reduced_clock ? &reduced_clock : NULL,
5846 } else if (IS_CHERRYVIEW(dev)) {
5847 chv_update_pll(intel_crtc);
5848 } else if (IS_VALLEYVIEW(dev)) {
5849 vlv_update_pll(intel_crtc);
5851 i9xx_update_pll(intel_crtc,
5852 has_reduced_clock ? &reduced_clock : NULL,
5857 /* Set up the display plane register */
5858 dspcntr = DISPPLANE_GAMMA_ENABLE;
5860 if (!IS_VALLEYVIEW(dev)) {
5862 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5864 dspcntr |= DISPPLANE_SEL_PIPE_B;
5867 if (intel_crtc->config.has_dp_encoder)
5868 intel_dp_set_m_n(intel_crtc);
5870 intel_set_pipe_timings(intel_crtc);
5872 /* pipesrc and dspsize control the size that is scaled from,
5873 * which should always be the user's requested size.
5875 I915_WRITE(DSPSIZE(plane),
5876 ((intel_crtc->config.pipe_src_h - 1) << 16) |
5877 (intel_crtc->config.pipe_src_w - 1));
5878 I915_WRITE(DSPPOS(plane), 0);
5880 i9xx_set_pipeconf(intel_crtc);
5882 I915_WRITE(DSPCNTR(plane), dspcntr);
5883 POSTING_READ(DSPCNTR(plane));
5885 ret = intel_pipe_set_base(crtc, x, y, fb);
5890 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5891 struct intel_crtc_config *pipe_config)
5893 struct drm_device *dev = crtc->base.dev;
5894 struct drm_i915_private *dev_priv = dev->dev_private;
5897 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
5900 tmp = I915_READ(PFIT_CONTROL);
5901 if (!(tmp & PFIT_ENABLE))
5904 /* Check whether the pfit is attached to our pipe. */
5905 if (INTEL_INFO(dev)->gen < 4) {
5906 if (crtc->pipe != PIPE_B)
5909 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5913 pipe_config->gmch_pfit.control = tmp;
5914 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5915 if (INTEL_INFO(dev)->gen < 5)
5916 pipe_config->gmch_pfit.lvds_border_bits =
5917 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5920 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5921 struct intel_crtc_config *pipe_config)
5923 struct drm_device *dev = crtc->base.dev;
5924 struct drm_i915_private *dev_priv = dev->dev_private;
5925 int pipe = pipe_config->cpu_transcoder;
5926 intel_clock_t clock;
5928 int refclk = 100000;
5930 mutex_lock(&dev_priv->dpio_lock);
5931 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
5932 mutex_unlock(&dev_priv->dpio_lock);
5934 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5935 clock.m2 = mdiv & DPIO_M2DIV_MASK;
5936 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5937 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5938 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5940 vlv_clock(refclk, &clock);
5942 /* clock.dot is the fast clock */
5943 pipe_config->port_clock = clock.dot / 5;
5946 static void i9xx_get_plane_config(struct intel_crtc *crtc,
5947 struct intel_plane_config *plane_config)
5949 struct drm_device *dev = crtc->base.dev;
5950 struct drm_i915_private *dev_priv = dev->dev_private;
5951 u32 val, base, offset;
5952 int pipe = crtc->pipe, plane = crtc->plane;
5953 int fourcc, pixel_format;
5956 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
5957 if (!crtc->base.primary->fb) {
5958 DRM_DEBUG_KMS("failed to alloc fb\n");
5962 val = I915_READ(DSPCNTR(plane));
5964 if (INTEL_INFO(dev)->gen >= 4)
5965 if (val & DISPPLANE_TILED)
5966 plane_config->tiled = true;
5968 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
5969 fourcc = intel_format_to_fourcc(pixel_format);
5970 crtc->base.primary->fb->pixel_format = fourcc;
5971 crtc->base.primary->fb->bits_per_pixel =
5972 drm_format_plane_cpp(fourcc, 0) * 8;
5974 if (INTEL_INFO(dev)->gen >= 4) {
5975 if (plane_config->tiled)
5976 offset = I915_READ(DSPTILEOFF(plane));
5978 offset = I915_READ(DSPLINOFF(plane));
5979 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
5981 base = I915_READ(DSPADDR(plane));
5983 plane_config->base = base;
5985 val = I915_READ(PIPESRC(pipe));
5986 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
5987 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
5989 val = I915_READ(DSPSTRIDE(pipe));
5990 crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
5992 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
5993 plane_config->tiled);
5995 plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
5996 aligned_height, PAGE_SIZE);
5998 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
5999 pipe, plane, crtc->base.primary->fb->width,
6000 crtc->base.primary->fb->height,
6001 crtc->base.primary->fb->bits_per_pixel, base,
6002 crtc->base.primary->fb->pitches[0],
6003 plane_config->size);
6007 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6008 struct intel_crtc_config *pipe_config)
6010 struct drm_device *dev = crtc->base.dev;
6011 struct drm_i915_private *dev_priv = dev->dev_private;
6012 int pipe = pipe_config->cpu_transcoder;
6013 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6014 intel_clock_t clock;
6015 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6016 int refclk = 100000;
6018 mutex_lock(&dev_priv->dpio_lock);
6019 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6020 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6021 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6022 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6023 mutex_unlock(&dev_priv->dpio_lock);
6025 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6026 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6027 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6028 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6029 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6031 chv_clock(refclk, &clock);
6033 /* clock.dot is the fast clock */
6034 pipe_config->port_clock = clock.dot / 5;
6037 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6038 struct intel_crtc_config *pipe_config)
6040 struct drm_device *dev = crtc->base.dev;
6041 struct drm_i915_private *dev_priv = dev->dev_private;
6044 if (!intel_display_power_enabled(dev_priv,
6045 POWER_DOMAIN_PIPE(crtc->pipe)))
6048 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6049 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6051 tmp = I915_READ(PIPECONF(crtc->pipe));
6052 if (!(tmp & PIPECONF_ENABLE))
6055 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6056 switch (tmp & PIPECONF_BPC_MASK) {
6058 pipe_config->pipe_bpp = 18;
6061 pipe_config->pipe_bpp = 24;
6063 case PIPECONF_10BPC:
6064 pipe_config->pipe_bpp = 30;
6071 if (INTEL_INFO(dev)->gen < 4)
6072 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6074 intel_get_pipe_timings(crtc, pipe_config);
6076 i9xx_get_pfit_config(crtc, pipe_config);
6078 if (INTEL_INFO(dev)->gen >= 4) {
6079 tmp = I915_READ(DPLL_MD(crtc->pipe));
6080 pipe_config->pixel_multiplier =
6081 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6082 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6083 pipe_config->dpll_hw_state.dpll_md = tmp;
6084 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6085 tmp = I915_READ(DPLL(crtc->pipe));
6086 pipe_config->pixel_multiplier =
6087 ((tmp & SDVO_MULTIPLIER_MASK)
6088 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6090 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6091 * port and will be fixed up in the encoder->get_config
6093 pipe_config->pixel_multiplier = 1;
6095 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6096 if (!IS_VALLEYVIEW(dev)) {
6097 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6098 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6100 /* Mask out read-only status bits. */
6101 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6102 DPLL_PORTC_READY_MASK |
6103 DPLL_PORTB_READY_MASK);
6106 if (IS_CHERRYVIEW(dev))
6107 chv_crtc_clock_get(crtc, pipe_config);
6108 else if (IS_VALLEYVIEW(dev))
6109 vlv_crtc_clock_get(crtc, pipe_config);
6111 i9xx_crtc_clock_get(crtc, pipe_config);
6116 static void ironlake_init_pch_refclk(struct drm_device *dev)
6118 struct drm_i915_private *dev_priv = dev->dev_private;
6119 struct drm_mode_config *mode_config = &dev->mode_config;
6120 struct intel_encoder *encoder;
6122 bool has_lvds = false;
6123 bool has_cpu_edp = false;
6124 bool has_panel = false;
6125 bool has_ck505 = false;
6126 bool can_ssc = false;
6128 /* We need to take the global config into account */
6129 list_for_each_entry(encoder, &mode_config->encoder_list,
6131 switch (encoder->type) {
6132 case INTEL_OUTPUT_LVDS:
6136 case INTEL_OUTPUT_EDP:
6138 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6144 if (HAS_PCH_IBX(dev)) {
6145 has_ck505 = dev_priv->vbt.display_clock_mode;
6146 can_ssc = has_ck505;
6152 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6153 has_panel, has_lvds, has_ck505);
6155 /* Ironlake: try to setup display ref clock before DPLL
6156 * enabling. This is only under driver's control after
6157 * PCH B stepping, previous chipset stepping should be
6158 * ignoring this setting.
6160 val = I915_READ(PCH_DREF_CONTROL);
6162 /* As we must carefully and slowly disable/enable each source in turn,
6163 * compute the final state we want first and check if we need to
6164 * make any changes at all.
6167 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6169 final |= DREF_NONSPREAD_CK505_ENABLE;
6171 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6173 final &= ~DREF_SSC_SOURCE_MASK;
6174 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6175 final &= ~DREF_SSC1_ENABLE;
6178 final |= DREF_SSC_SOURCE_ENABLE;
6180 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6181 final |= DREF_SSC1_ENABLE;
6184 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6185 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6187 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6189 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6191 final |= DREF_SSC_SOURCE_DISABLE;
6192 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6198 /* Always enable nonspread source */
6199 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6202 val |= DREF_NONSPREAD_CK505_ENABLE;
6204 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6207 val &= ~DREF_SSC_SOURCE_MASK;
6208 val |= DREF_SSC_SOURCE_ENABLE;
6210 /* SSC must be turned on before enabling the CPU output */
6211 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6212 DRM_DEBUG_KMS("Using SSC on panel\n");
6213 val |= DREF_SSC1_ENABLE;
6215 val &= ~DREF_SSC1_ENABLE;
6217 /* Get SSC going before enabling the outputs */
6218 I915_WRITE(PCH_DREF_CONTROL, val);
6219 POSTING_READ(PCH_DREF_CONTROL);
6222 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6224 /* Enable CPU source on CPU attached eDP */
6226 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6227 DRM_DEBUG_KMS("Using SSC on eDP\n");
6228 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6231 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6233 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6235 I915_WRITE(PCH_DREF_CONTROL, val);
6236 POSTING_READ(PCH_DREF_CONTROL);
6239 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6241 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6243 /* Turn off CPU output */
6244 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6246 I915_WRITE(PCH_DREF_CONTROL, val);
6247 POSTING_READ(PCH_DREF_CONTROL);
6250 /* Turn off the SSC source */
6251 val &= ~DREF_SSC_SOURCE_MASK;
6252 val |= DREF_SSC_SOURCE_DISABLE;
6255 val &= ~DREF_SSC1_ENABLE;
6257 I915_WRITE(PCH_DREF_CONTROL, val);
6258 POSTING_READ(PCH_DREF_CONTROL);
6262 BUG_ON(val != final);
6265 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6269 tmp = I915_READ(SOUTH_CHICKEN2);
6270 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6271 I915_WRITE(SOUTH_CHICKEN2, tmp);
6273 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6274 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6275 DRM_ERROR("FDI mPHY reset assert timeout\n");
6277 tmp = I915_READ(SOUTH_CHICKEN2);
6278 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6279 I915_WRITE(SOUTH_CHICKEN2, tmp);
6281 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6282 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6283 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6286 /* WaMPhyProgramming:hsw */
6287 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6291 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6292 tmp &= ~(0xFF << 24);
6293 tmp |= (0x12 << 24);
6294 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6296 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6298 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6300 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6302 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6304 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6305 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6306 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6308 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6309 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6310 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6312 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6315 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6317 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6320 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6322 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6325 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6327 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6330 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6332 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6333 tmp &= ~(0xFF << 16);
6334 tmp |= (0x1C << 16);
6335 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6337 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6338 tmp &= ~(0xFF << 16);
6339 tmp |= (0x1C << 16);
6340 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6342 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6344 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6346 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6348 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6350 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6351 tmp &= ~(0xF << 28);
6353 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6355 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6356 tmp &= ~(0xF << 28);
6358 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6361 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6362 * Programming" based on the parameters passed:
6363 * - Sequence to enable CLKOUT_DP
6364 * - Sequence to enable CLKOUT_DP without spread
6365 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6367 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6370 struct drm_i915_private *dev_priv = dev->dev_private;
6373 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6375 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6376 with_fdi, "LP PCH doesn't have FDI\n"))
6379 mutex_lock(&dev_priv->dpio_lock);
6381 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6382 tmp &= ~SBI_SSCCTL_DISABLE;
6383 tmp |= SBI_SSCCTL_PATHALT;
6384 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6389 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6390 tmp &= ~SBI_SSCCTL_PATHALT;
6391 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6394 lpt_reset_fdi_mphy(dev_priv);
6395 lpt_program_fdi_mphy(dev_priv);
6399 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6400 SBI_GEN0 : SBI_DBUFF0;
6401 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6402 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6403 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6405 mutex_unlock(&dev_priv->dpio_lock);
6408 /* Sequence to disable CLKOUT_DP */
6409 static void lpt_disable_clkout_dp(struct drm_device *dev)
6411 struct drm_i915_private *dev_priv = dev->dev_private;
6414 mutex_lock(&dev_priv->dpio_lock);
6416 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6417 SBI_GEN0 : SBI_DBUFF0;
6418 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6419 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6420 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6422 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6423 if (!(tmp & SBI_SSCCTL_DISABLE)) {
6424 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6425 tmp |= SBI_SSCCTL_PATHALT;
6426 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6429 tmp |= SBI_SSCCTL_DISABLE;
6430 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6433 mutex_unlock(&dev_priv->dpio_lock);
6436 static void lpt_init_pch_refclk(struct drm_device *dev)
6438 struct drm_mode_config *mode_config = &dev->mode_config;
6439 struct intel_encoder *encoder;
6440 bool has_vga = false;
6442 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
6443 switch (encoder->type) {
6444 case INTEL_OUTPUT_ANALOG:
6451 lpt_enable_clkout_dp(dev, true, true);
6453 lpt_disable_clkout_dp(dev);
6457 * Initialize reference clocks when the driver loads
6459 void intel_init_pch_refclk(struct drm_device *dev)
6461 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6462 ironlake_init_pch_refclk(dev);
6463 else if (HAS_PCH_LPT(dev))
6464 lpt_init_pch_refclk(dev);
6467 static int ironlake_get_refclk(struct drm_crtc *crtc)
6469 struct drm_device *dev = crtc->dev;
6470 struct drm_i915_private *dev_priv = dev->dev_private;
6471 struct intel_encoder *encoder;
6472 int num_connectors = 0;
6473 bool is_lvds = false;
6475 for_each_encoder_on_crtc(dev, crtc, encoder) {
6476 switch (encoder->type) {
6477 case INTEL_OUTPUT_LVDS:
6484 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6485 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6486 dev_priv->vbt.lvds_ssc_freq);
6487 return dev_priv->vbt.lvds_ssc_freq;
6493 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6495 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6496 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6497 int pipe = intel_crtc->pipe;
6502 switch (intel_crtc->config.pipe_bpp) {
6504 val |= PIPECONF_6BPC;
6507 val |= PIPECONF_8BPC;
6510 val |= PIPECONF_10BPC;
6513 val |= PIPECONF_12BPC;
6516 /* Case prevented by intel_choose_pipe_bpp_dither. */
6520 if (intel_crtc->config.dither)
6521 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6523 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6524 val |= PIPECONF_INTERLACED_ILK;
6526 val |= PIPECONF_PROGRESSIVE;
6528 if (intel_crtc->config.limited_color_range)
6529 val |= PIPECONF_COLOR_RANGE_SELECT;
6531 I915_WRITE(PIPECONF(pipe), val);
6532 POSTING_READ(PIPECONF(pipe));
6536 * Set up the pipe CSC unit.
6538 * Currently only full range RGB to limited range RGB conversion
6539 * is supported, but eventually this should handle various
6540 * RGB<->YCbCr scenarios as well.
6542 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6544 struct drm_device *dev = crtc->dev;
6545 struct drm_i915_private *dev_priv = dev->dev_private;
6546 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6547 int pipe = intel_crtc->pipe;
6548 uint16_t coeff = 0x7800; /* 1.0 */
6551 * TODO: Check what kind of values actually come out of the pipe
6552 * with these coeff/postoff values and adjust to get the best
6553 * accuracy. Perhaps we even need to take the bpc value into
6557 if (intel_crtc->config.limited_color_range)
6558 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6561 * GY/GU and RY/RU should be the other way around according
6562 * to BSpec, but reality doesn't agree. Just set them up in
6563 * a way that results in the correct picture.
6565 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6566 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6568 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6569 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6571 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6572 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6574 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6575 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6576 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6578 if (INTEL_INFO(dev)->gen > 6) {
6579 uint16_t postoff = 0;
6581 if (intel_crtc->config.limited_color_range)
6582 postoff = (16 * (1 << 12) / 255) & 0x1fff;
6584 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6585 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6586 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6588 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6590 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6592 if (intel_crtc->config.limited_color_range)
6593 mode |= CSC_BLACK_SCREEN_OFFSET;
6595 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6599 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6601 struct drm_device *dev = crtc->dev;
6602 struct drm_i915_private *dev_priv = dev->dev_private;
6603 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6604 enum pipe pipe = intel_crtc->pipe;
6605 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6610 if (IS_HASWELL(dev) && intel_crtc->config.dither)
6611 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6613 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6614 val |= PIPECONF_INTERLACED_ILK;
6616 val |= PIPECONF_PROGRESSIVE;
6618 I915_WRITE(PIPECONF(cpu_transcoder), val);
6619 POSTING_READ(PIPECONF(cpu_transcoder));
6621 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6622 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6624 if (IS_BROADWELL(dev)) {
6627 switch (intel_crtc->config.pipe_bpp) {
6629 val |= PIPEMISC_DITHER_6_BPC;
6632 val |= PIPEMISC_DITHER_8_BPC;
6635 val |= PIPEMISC_DITHER_10_BPC;
6638 val |= PIPEMISC_DITHER_12_BPC;
6641 /* Case prevented by pipe_config_set_bpp. */
6645 if (intel_crtc->config.dither)
6646 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6648 I915_WRITE(PIPEMISC(pipe), val);
6652 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6653 intel_clock_t *clock,
6654 bool *has_reduced_clock,
6655 intel_clock_t *reduced_clock)
6657 struct drm_device *dev = crtc->dev;
6658 struct drm_i915_private *dev_priv = dev->dev_private;
6659 struct intel_encoder *intel_encoder;
6661 const intel_limit_t *limit;
6662 bool ret, is_lvds = false;
6664 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6665 switch (intel_encoder->type) {
6666 case INTEL_OUTPUT_LVDS:
6672 refclk = ironlake_get_refclk(crtc);
6675 * Returns a set of divisors for the desired target clock with the given
6676 * refclk, or FALSE. The returned values represent the clock equation:
6677 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6679 limit = intel_limit(crtc, refclk);
6680 ret = dev_priv->display.find_dpll(limit, crtc,
6681 to_intel_crtc(crtc)->config.port_clock,
6682 refclk, NULL, clock);
6686 if (is_lvds && dev_priv->lvds_downclock_avail) {
6688 * Ensure we match the reduced clock's P to the target clock.
6689 * If the clocks don't match, we can't switch the display clock
6690 * by using the FP0/FP1. In such case we will disable the LVDS
6691 * downclock feature.
6693 *has_reduced_clock =
6694 dev_priv->display.find_dpll(limit, crtc,
6695 dev_priv->lvds_downclock,
6703 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6706 * Account for spread spectrum to avoid
6707 * oversubscribing the link. Max center spread
6708 * is 2.5%; use 5% for safety's sake.
6710 u32 bps = target_clock * bpp * 21 / 20;
6711 return DIV_ROUND_UP(bps, link_bw * 8);
6714 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6716 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6719 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6721 intel_clock_t *reduced_clock, u32 *fp2)
6723 struct drm_crtc *crtc = &intel_crtc->base;
6724 struct drm_device *dev = crtc->dev;
6725 struct drm_i915_private *dev_priv = dev->dev_private;
6726 struct intel_encoder *intel_encoder;
6728 int factor, num_connectors = 0;
6729 bool is_lvds = false, is_sdvo = false;
6731 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6732 switch (intel_encoder->type) {
6733 case INTEL_OUTPUT_LVDS:
6736 case INTEL_OUTPUT_SDVO:
6737 case INTEL_OUTPUT_HDMI:
6745 /* Enable autotuning of the PLL clock (if permissible) */
6748 if ((intel_panel_use_ssc(dev_priv) &&
6749 dev_priv->vbt.lvds_ssc_freq == 100000) ||
6750 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6752 } else if (intel_crtc->config.sdvo_tv_clock)
6755 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6758 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6764 dpll |= DPLLB_MODE_LVDS;
6766 dpll |= DPLLB_MODE_DAC_SERIAL;
6768 dpll |= (intel_crtc->config.pixel_multiplier - 1)
6769 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6772 dpll |= DPLL_SDVO_HIGH_SPEED;
6773 if (intel_crtc->config.has_dp_encoder)
6774 dpll |= DPLL_SDVO_HIGH_SPEED;
6776 /* compute bitmask from p1 value */
6777 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6779 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6781 switch (intel_crtc->config.dpll.p2) {
6783 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6786 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6789 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6792 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6796 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6797 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6799 dpll |= PLL_REF_INPUT_DREFCLK;
6801 return dpll | DPLL_VCO_ENABLE;
6804 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
6806 struct drm_framebuffer *fb)
6808 struct drm_device *dev = crtc->dev;
6809 struct drm_i915_private *dev_priv = dev->dev_private;
6810 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6811 int pipe = intel_crtc->pipe;
6812 int plane = intel_crtc->plane;
6813 int num_connectors = 0;
6814 intel_clock_t clock, reduced_clock;
6815 u32 dpll = 0, fp = 0, fp2 = 0;
6816 bool ok, has_reduced_clock = false;
6817 bool is_lvds = false;
6818 struct intel_encoder *encoder;
6819 struct intel_shared_dpll *pll;
6822 for_each_encoder_on_crtc(dev, crtc, encoder) {
6823 switch (encoder->type) {
6824 case INTEL_OUTPUT_LVDS:
6832 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6833 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6835 ok = ironlake_compute_clocks(crtc, &clock,
6836 &has_reduced_clock, &reduced_clock);
6837 if (!ok && !intel_crtc->config.clock_set) {
6838 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6841 /* Compat-code for transition, will disappear. */
6842 if (!intel_crtc->config.clock_set) {
6843 intel_crtc->config.dpll.n = clock.n;
6844 intel_crtc->config.dpll.m1 = clock.m1;
6845 intel_crtc->config.dpll.m2 = clock.m2;
6846 intel_crtc->config.dpll.p1 = clock.p1;
6847 intel_crtc->config.dpll.p2 = clock.p2;
6850 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6851 if (intel_crtc->config.has_pch_encoder) {
6852 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6853 if (has_reduced_clock)
6854 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6856 dpll = ironlake_compute_dpll(intel_crtc,
6857 &fp, &reduced_clock,
6858 has_reduced_clock ? &fp2 : NULL);
6860 intel_crtc->config.dpll_hw_state.dpll = dpll;
6861 intel_crtc->config.dpll_hw_state.fp0 = fp;
6862 if (has_reduced_clock)
6863 intel_crtc->config.dpll_hw_state.fp1 = fp2;
6865 intel_crtc->config.dpll_hw_state.fp1 = fp;
6867 pll = intel_get_shared_dpll(intel_crtc);
6869 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6874 intel_put_shared_dpll(intel_crtc);
6876 if (intel_crtc->config.has_dp_encoder)
6877 intel_dp_set_m_n(intel_crtc);
6879 if (is_lvds && has_reduced_clock && i915.powersave)
6880 intel_crtc->lowfreq_avail = true;
6882 intel_crtc->lowfreq_avail = false;
6884 intel_set_pipe_timings(intel_crtc);
6886 if (intel_crtc->config.has_pch_encoder) {
6887 intel_cpu_transcoder_set_m_n(intel_crtc,
6888 &intel_crtc->config.fdi_m_n);
6891 ironlake_set_pipeconf(crtc);
6893 /* Set up the display plane register */
6894 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
6895 POSTING_READ(DSPCNTR(plane));
6897 ret = intel_pipe_set_base(crtc, x, y, fb);
6902 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6903 struct intel_link_m_n *m_n)
6905 struct drm_device *dev = crtc->base.dev;
6906 struct drm_i915_private *dev_priv = dev->dev_private;
6907 enum pipe pipe = crtc->pipe;
6909 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6910 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6911 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6913 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6914 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6915 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6918 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6919 enum transcoder transcoder,
6920 struct intel_link_m_n *m_n)
6922 struct drm_device *dev = crtc->base.dev;
6923 struct drm_i915_private *dev_priv = dev->dev_private;
6924 enum pipe pipe = crtc->pipe;
6926 if (INTEL_INFO(dev)->gen >= 5) {
6927 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6928 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6929 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6931 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6932 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6933 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6935 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6936 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6937 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6939 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6940 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6941 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6945 void intel_dp_get_m_n(struct intel_crtc *crtc,
6946 struct intel_crtc_config *pipe_config)
6948 if (crtc->config.has_pch_encoder)
6949 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6951 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6952 &pipe_config->dp_m_n);
6955 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6956 struct intel_crtc_config *pipe_config)
6958 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6959 &pipe_config->fdi_m_n);
6962 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6963 struct intel_crtc_config *pipe_config)
6965 struct drm_device *dev = crtc->base.dev;
6966 struct drm_i915_private *dev_priv = dev->dev_private;
6969 tmp = I915_READ(PF_CTL(crtc->pipe));
6971 if (tmp & PF_ENABLE) {
6972 pipe_config->pch_pfit.enabled = true;
6973 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6974 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
6976 /* We currently do not free assignements of panel fitters on
6977 * ivb/hsw (since we don't use the higher upscaling modes which
6978 * differentiates them) so just WARN about this case for now. */
6980 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6981 PF_PIPE_SEL_IVB(crtc->pipe));
6986 static void ironlake_get_plane_config(struct intel_crtc *crtc,
6987 struct intel_plane_config *plane_config)
6989 struct drm_device *dev = crtc->base.dev;
6990 struct drm_i915_private *dev_priv = dev->dev_private;
6991 u32 val, base, offset;
6992 int pipe = crtc->pipe, plane = crtc->plane;
6993 int fourcc, pixel_format;
6996 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6997 if (!crtc->base.primary->fb) {
6998 DRM_DEBUG_KMS("failed to alloc fb\n");
7002 val = I915_READ(DSPCNTR(plane));
7004 if (INTEL_INFO(dev)->gen >= 4)
7005 if (val & DISPPLANE_TILED)
7006 plane_config->tiled = true;
7008 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7009 fourcc = intel_format_to_fourcc(pixel_format);
7010 crtc->base.primary->fb->pixel_format = fourcc;
7011 crtc->base.primary->fb->bits_per_pixel =
7012 drm_format_plane_cpp(fourcc, 0) * 8;
7014 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7015 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7016 offset = I915_READ(DSPOFFSET(plane));
7018 if (plane_config->tiled)
7019 offset = I915_READ(DSPTILEOFF(plane));
7021 offset = I915_READ(DSPLINOFF(plane));
7023 plane_config->base = base;
7025 val = I915_READ(PIPESRC(pipe));
7026 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7027 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7029 val = I915_READ(DSPSTRIDE(pipe));
7030 crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
7032 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7033 plane_config->tiled);
7035 plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
7036 aligned_height, PAGE_SIZE);
7038 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7039 pipe, plane, crtc->base.primary->fb->width,
7040 crtc->base.primary->fb->height,
7041 crtc->base.primary->fb->bits_per_pixel, base,
7042 crtc->base.primary->fb->pitches[0],
7043 plane_config->size);
7046 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7047 struct intel_crtc_config *pipe_config)
7049 struct drm_device *dev = crtc->base.dev;
7050 struct drm_i915_private *dev_priv = dev->dev_private;
7053 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7054 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7056 tmp = I915_READ(PIPECONF(crtc->pipe));
7057 if (!(tmp & PIPECONF_ENABLE))
7060 switch (tmp & PIPECONF_BPC_MASK) {
7062 pipe_config->pipe_bpp = 18;
7065 pipe_config->pipe_bpp = 24;
7067 case PIPECONF_10BPC:
7068 pipe_config->pipe_bpp = 30;
7070 case PIPECONF_12BPC:
7071 pipe_config->pipe_bpp = 36;
7077 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7078 struct intel_shared_dpll *pll;
7080 pipe_config->has_pch_encoder = true;
7082 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7083 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7084 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7086 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7088 if (HAS_PCH_IBX(dev_priv->dev)) {
7089 pipe_config->shared_dpll =
7090 (enum intel_dpll_id) crtc->pipe;
7092 tmp = I915_READ(PCH_DPLL_SEL);
7093 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7094 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7096 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7099 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7101 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7102 &pipe_config->dpll_hw_state));
7104 tmp = pipe_config->dpll_hw_state.dpll;
7105 pipe_config->pixel_multiplier =
7106 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7107 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7109 ironlake_pch_clock_get(crtc, pipe_config);
7111 pipe_config->pixel_multiplier = 1;
7114 intel_get_pipe_timings(crtc, pipe_config);
7116 ironlake_get_pfit_config(crtc, pipe_config);
7121 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7123 struct drm_device *dev = dev_priv->dev;
7124 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
7125 struct intel_crtc *crtc;
7127 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
7128 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7129 pipe_name(crtc->pipe));
7131 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7132 WARN(plls->spll_refcount, "SPLL enabled\n");
7133 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
7134 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
7135 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7136 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7137 "CPU PWM1 enabled\n");
7138 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7139 "CPU PWM2 enabled\n");
7140 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7141 "PCH PWM1 enabled\n");
7142 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7143 "Utility pin enabled\n");
7144 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7147 * In theory we can still leave IRQs enabled, as long as only the HPD
7148 * interrupts remain enabled. We used to check for that, but since it's
7149 * gen-specific and since we only disable LCPLL after we fully disable
7150 * the interrupts, the check below should be enough.
7152 WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n");
7155 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7157 struct drm_device *dev = dev_priv->dev;
7159 if (IS_HASWELL(dev)) {
7160 mutex_lock(&dev_priv->rps.hw_lock);
7161 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7163 DRM_ERROR("Failed to disable D_COMP\n");
7164 mutex_unlock(&dev_priv->rps.hw_lock);
7166 I915_WRITE(D_COMP, val);
7168 POSTING_READ(D_COMP);
7172 * This function implements pieces of two sequences from BSpec:
7173 * - Sequence for display software to disable LCPLL
7174 * - Sequence for display software to allow package C8+
7175 * The steps implemented here are just the steps that actually touch the LCPLL
7176 * register. Callers should take care of disabling all the display engine
7177 * functions, doing the mode unset, fixing interrupts, etc.
7179 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7180 bool switch_to_fclk, bool allow_power_down)
7184 assert_can_disable_lcpll(dev_priv);
7186 val = I915_READ(LCPLL_CTL);
7188 if (switch_to_fclk) {
7189 val |= LCPLL_CD_SOURCE_FCLK;
7190 I915_WRITE(LCPLL_CTL, val);
7192 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7193 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7194 DRM_ERROR("Switching to FCLK failed\n");
7196 val = I915_READ(LCPLL_CTL);
7199 val |= LCPLL_PLL_DISABLE;
7200 I915_WRITE(LCPLL_CTL, val);
7201 POSTING_READ(LCPLL_CTL);
7203 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7204 DRM_ERROR("LCPLL still locked\n");
7206 val = I915_READ(D_COMP);
7207 val |= D_COMP_COMP_DISABLE;
7208 hsw_write_dcomp(dev_priv, val);
7211 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
7212 DRM_ERROR("D_COMP RCOMP still in progress\n");
7214 if (allow_power_down) {
7215 val = I915_READ(LCPLL_CTL);
7216 val |= LCPLL_POWER_DOWN_ALLOW;
7217 I915_WRITE(LCPLL_CTL, val);
7218 POSTING_READ(LCPLL_CTL);
7223 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7226 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7229 unsigned long irqflags;
7231 val = I915_READ(LCPLL_CTL);
7233 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7234 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7238 * Make sure we're not on PC8 state before disabling PC8, otherwise
7239 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7241 * The other problem is that hsw_restore_lcpll() is called as part of
7242 * the runtime PM resume sequence, so we can't just call
7243 * gen6_gt_force_wake_get() because that function calls
7244 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7245 * while we are on the resume sequence. So to solve this problem we have
7246 * to call special forcewake code that doesn't touch runtime PM and
7247 * doesn't enable the forcewake delayed work.
7249 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7250 if (dev_priv->uncore.forcewake_count++ == 0)
7251 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7252 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7254 if (val & LCPLL_POWER_DOWN_ALLOW) {
7255 val &= ~LCPLL_POWER_DOWN_ALLOW;
7256 I915_WRITE(LCPLL_CTL, val);
7257 POSTING_READ(LCPLL_CTL);
7260 val = I915_READ(D_COMP);
7261 val |= D_COMP_COMP_FORCE;
7262 val &= ~D_COMP_COMP_DISABLE;
7263 hsw_write_dcomp(dev_priv, val);
7265 val = I915_READ(LCPLL_CTL);
7266 val &= ~LCPLL_PLL_DISABLE;
7267 I915_WRITE(LCPLL_CTL, val);
7269 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7270 DRM_ERROR("LCPLL not locked yet\n");
7272 if (val & LCPLL_CD_SOURCE_FCLK) {
7273 val = I915_READ(LCPLL_CTL);
7274 val &= ~LCPLL_CD_SOURCE_FCLK;
7275 I915_WRITE(LCPLL_CTL, val);
7277 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7278 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7279 DRM_ERROR("Switching back to LCPLL failed\n");
7282 /* See the big comment above. */
7283 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7284 if (--dev_priv->uncore.forcewake_count == 0)
7285 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7286 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7290 * Package states C8 and deeper are really deep PC states that can only be
7291 * reached when all the devices on the system allow it, so even if the graphics
7292 * device allows PC8+, it doesn't mean the system will actually get to these
7293 * states. Our driver only allows PC8+ when going into runtime PM.
7295 * The requirements for PC8+ are that all the outputs are disabled, the power
7296 * well is disabled and most interrupts are disabled, and these are also
7297 * requirements for runtime PM. When these conditions are met, we manually do
7298 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7299 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7302 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7303 * the state of some registers, so when we come back from PC8+ we need to
7304 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7305 * need to take care of the registers kept by RC6. Notice that this happens even
7306 * if we don't put the device in PCI D3 state (which is what currently happens
7307 * because of the runtime PM support).
7309 * For more, read "Display Sequences for Package C8" on the hardware
7312 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7314 struct drm_device *dev = dev_priv->dev;
7317 DRM_DEBUG_KMS("Enabling package C8+\n");
7319 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7320 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7321 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7322 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7325 lpt_disable_clkout_dp(dev);
7326 hsw_disable_lcpll(dev_priv, true, true);
7329 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7331 struct drm_device *dev = dev_priv->dev;
7334 DRM_DEBUG_KMS("Disabling package C8+\n");
7336 hsw_restore_lcpll(dev_priv);
7337 lpt_init_pch_refclk(dev);
7339 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7340 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7341 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7342 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7345 intel_prepare_ddi(dev);
7348 static void snb_modeset_global_resources(struct drm_device *dev)
7350 modeset_update_crtc_power_domains(dev);
7353 static void haswell_modeset_global_resources(struct drm_device *dev)
7355 modeset_update_crtc_power_domains(dev);
7358 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7360 struct drm_framebuffer *fb)
7362 struct drm_device *dev = crtc->dev;
7363 struct drm_i915_private *dev_priv = dev->dev_private;
7364 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7365 int plane = intel_crtc->plane;
7368 if (!intel_ddi_pll_select(intel_crtc))
7370 intel_ddi_pll_enable(intel_crtc);
7372 if (intel_crtc->config.has_dp_encoder)
7373 intel_dp_set_m_n(intel_crtc);
7375 intel_crtc->lowfreq_avail = false;
7377 intel_set_pipe_timings(intel_crtc);
7379 if (intel_crtc->config.has_pch_encoder) {
7380 intel_cpu_transcoder_set_m_n(intel_crtc,
7381 &intel_crtc->config.fdi_m_n);
7384 haswell_set_pipeconf(crtc);
7386 intel_set_pipe_csc(crtc);
7388 /* Set up the display plane register */
7389 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
7390 POSTING_READ(DSPCNTR(plane));
7392 ret = intel_pipe_set_base(crtc, x, y, fb);
7397 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7398 struct intel_crtc_config *pipe_config)
7400 struct drm_device *dev = crtc->base.dev;
7401 struct drm_i915_private *dev_priv = dev->dev_private;
7402 enum intel_display_power_domain pfit_domain;
7405 if (!intel_display_power_enabled(dev_priv,
7406 POWER_DOMAIN_PIPE(crtc->pipe)))
7409 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7410 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7412 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7413 if (tmp & TRANS_DDI_FUNC_ENABLE) {
7414 enum pipe trans_edp_pipe;
7415 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7417 WARN(1, "unknown pipe linked to edp transcoder\n");
7418 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7419 case TRANS_DDI_EDP_INPUT_A_ON:
7420 trans_edp_pipe = PIPE_A;
7422 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7423 trans_edp_pipe = PIPE_B;
7425 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7426 trans_edp_pipe = PIPE_C;
7430 if (trans_edp_pipe == crtc->pipe)
7431 pipe_config->cpu_transcoder = TRANSCODER_EDP;
7434 if (!intel_display_power_enabled(dev_priv,
7435 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7438 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7439 if (!(tmp & PIPECONF_ENABLE))
7443 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7444 * DDI E. So just check whether this pipe is wired to DDI E and whether
7445 * the PCH transcoder is on.
7447 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7448 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
7449 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7450 pipe_config->has_pch_encoder = true;
7452 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7453 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7454 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7456 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7459 intel_get_pipe_timings(crtc, pipe_config);
7461 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7462 if (intel_display_power_enabled(dev_priv, pfit_domain))
7463 ironlake_get_pfit_config(crtc, pipe_config);
7465 if (IS_HASWELL(dev))
7466 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7467 (I915_READ(IPS_CTL) & IPS_ENABLE);
7469 pipe_config->pixel_multiplier = 1;
7474 static int intel_crtc_mode_set(struct drm_crtc *crtc,
7476 struct drm_framebuffer *fb)
7478 struct drm_device *dev = crtc->dev;
7479 struct drm_i915_private *dev_priv = dev->dev_private;
7480 struct intel_encoder *encoder;
7481 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7482 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
7483 int pipe = intel_crtc->pipe;
7486 drm_vblank_pre_modeset(dev, pipe);
7488 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
7490 drm_vblank_post_modeset(dev, pipe);
7495 for_each_encoder_on_crtc(dev, crtc, encoder) {
7496 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7497 encoder->base.base.id,
7498 drm_get_encoder_name(&encoder->base),
7499 mode->base.id, mode->name);
7501 if (encoder->mode_set)
7502 encoder->mode_set(encoder);
7511 } hdmi_audio_clock[] = {
7512 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7513 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7514 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7515 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7516 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7517 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7518 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7519 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7520 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7521 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7524 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7525 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7529 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7530 if (mode->clock == hdmi_audio_clock[i].clock)
7534 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7535 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7539 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7540 hdmi_audio_clock[i].clock,
7541 hdmi_audio_clock[i].config);
7543 return hdmi_audio_clock[i].config;
7546 static bool intel_eld_uptodate(struct drm_connector *connector,
7547 int reg_eldv, uint32_t bits_eldv,
7548 int reg_elda, uint32_t bits_elda,
7551 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7552 uint8_t *eld = connector->eld;
7555 i = I915_READ(reg_eldv);
7564 i = I915_READ(reg_elda);
7566 I915_WRITE(reg_elda, i);
7568 for (i = 0; i < eld[2]; i++)
7569 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7575 static void g4x_write_eld(struct drm_connector *connector,
7576 struct drm_crtc *crtc,
7577 struct drm_display_mode *mode)
7579 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7580 uint8_t *eld = connector->eld;
7585 i = I915_READ(G4X_AUD_VID_DID);
7587 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7588 eldv = G4X_ELDV_DEVCL_DEVBLC;
7590 eldv = G4X_ELDV_DEVCTG;
7592 if (intel_eld_uptodate(connector,
7593 G4X_AUD_CNTL_ST, eldv,
7594 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7595 G4X_HDMIW_HDMIEDID))
7598 i = I915_READ(G4X_AUD_CNTL_ST);
7599 i &= ~(eldv | G4X_ELD_ADDR);
7600 len = (i >> 9) & 0x1f; /* ELD buffer size */
7601 I915_WRITE(G4X_AUD_CNTL_ST, i);
7606 len = min_t(uint8_t, eld[2], len);
7607 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7608 for (i = 0; i < len; i++)
7609 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7611 i = I915_READ(G4X_AUD_CNTL_ST);
7613 I915_WRITE(G4X_AUD_CNTL_ST, i);
7616 static void haswell_write_eld(struct drm_connector *connector,
7617 struct drm_crtc *crtc,
7618 struct drm_display_mode *mode)
7620 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7621 uint8_t *eld = connector->eld;
7622 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7626 int pipe = to_intel_crtc(crtc)->pipe;
7629 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7630 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7631 int aud_config = HSW_AUD_CFG(pipe);
7632 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7634 /* Audio output enable */
7635 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7636 tmp = I915_READ(aud_cntrl_st2);
7637 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7638 I915_WRITE(aud_cntrl_st2, tmp);
7639 POSTING_READ(aud_cntrl_st2);
7641 assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
7643 /* Set ELD valid state */
7644 tmp = I915_READ(aud_cntrl_st2);
7645 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7646 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7647 I915_WRITE(aud_cntrl_st2, tmp);
7648 tmp = I915_READ(aud_cntrl_st2);
7649 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7651 /* Enable HDMI mode */
7652 tmp = I915_READ(aud_config);
7653 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7654 /* clear N_programing_enable and N_value_index */
7655 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7656 I915_WRITE(aud_config, tmp);
7658 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7660 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7661 intel_crtc->eld_vld = true;
7663 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7664 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7665 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7666 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7668 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7671 if (intel_eld_uptodate(connector,
7672 aud_cntrl_st2, eldv,
7673 aud_cntl_st, IBX_ELD_ADDRESS,
7677 i = I915_READ(aud_cntrl_st2);
7679 I915_WRITE(aud_cntrl_st2, i);
7684 i = I915_READ(aud_cntl_st);
7685 i &= ~IBX_ELD_ADDRESS;
7686 I915_WRITE(aud_cntl_st, i);
7687 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
7688 DRM_DEBUG_DRIVER("port num:%d\n", i);
7690 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7691 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7692 for (i = 0; i < len; i++)
7693 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7695 i = I915_READ(aud_cntrl_st2);
7697 I915_WRITE(aud_cntrl_st2, i);
7701 static void ironlake_write_eld(struct drm_connector *connector,
7702 struct drm_crtc *crtc,
7703 struct drm_display_mode *mode)
7705 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7706 uint8_t *eld = connector->eld;
7714 int pipe = to_intel_crtc(crtc)->pipe;
7716 if (HAS_PCH_IBX(connector->dev)) {
7717 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7718 aud_config = IBX_AUD_CFG(pipe);
7719 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7720 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7721 } else if (IS_VALLEYVIEW(connector->dev)) {
7722 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7723 aud_config = VLV_AUD_CFG(pipe);
7724 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7725 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7727 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7728 aud_config = CPT_AUD_CFG(pipe);
7729 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7730 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7733 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7735 if (IS_VALLEYVIEW(connector->dev)) {
7736 struct intel_encoder *intel_encoder;
7737 struct intel_digital_port *intel_dig_port;
7739 intel_encoder = intel_attached_encoder(connector);
7740 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7741 i = intel_dig_port->port;
7743 i = I915_READ(aud_cntl_st);
7744 i = (i >> 29) & DIP_PORT_SEL_MASK;
7745 /* DIP_Port_Select, 0x1 = PortB */
7749 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7750 /* operate blindly on all ports */
7751 eldv = IBX_ELD_VALIDB;
7752 eldv |= IBX_ELD_VALIDB << 4;
7753 eldv |= IBX_ELD_VALIDB << 8;
7755 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7756 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7759 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7760 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7761 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7762 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7764 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7767 if (intel_eld_uptodate(connector,
7768 aud_cntrl_st2, eldv,
7769 aud_cntl_st, IBX_ELD_ADDRESS,
7773 i = I915_READ(aud_cntrl_st2);
7775 I915_WRITE(aud_cntrl_st2, i);
7780 i = I915_READ(aud_cntl_st);
7781 i &= ~IBX_ELD_ADDRESS;
7782 I915_WRITE(aud_cntl_st, i);
7784 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7785 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7786 for (i = 0; i < len; i++)
7787 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7789 i = I915_READ(aud_cntrl_st2);
7791 I915_WRITE(aud_cntrl_st2, i);
7794 void intel_write_eld(struct drm_encoder *encoder,
7795 struct drm_display_mode *mode)
7797 struct drm_crtc *crtc = encoder->crtc;
7798 struct drm_connector *connector;
7799 struct drm_device *dev = encoder->dev;
7800 struct drm_i915_private *dev_priv = dev->dev_private;
7802 connector = drm_select_eld(encoder, mode);
7806 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7808 drm_get_connector_name(connector),
7809 connector->encoder->base.id,
7810 drm_get_encoder_name(connector->encoder));
7812 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7814 if (dev_priv->display.write_eld)
7815 dev_priv->display.write_eld(connector, crtc, mode);
7818 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7820 struct drm_device *dev = crtc->dev;
7821 struct drm_i915_private *dev_priv = dev->dev_private;
7822 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7823 bool visible = base != 0;
7826 if (intel_crtc->cursor_visible == visible)
7829 cntl = I915_READ(_CURACNTR);
7831 /* On these chipsets we can only modify the base whilst
7832 * the cursor is disabled.
7834 I915_WRITE(_CURABASE, base);
7836 cntl &= ~(CURSOR_FORMAT_MASK);
7837 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7838 cntl |= CURSOR_ENABLE |
7839 CURSOR_GAMMA_ENABLE |
7842 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
7843 I915_WRITE(_CURACNTR, cntl);
7845 intel_crtc->cursor_visible = visible;
7848 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7850 struct drm_device *dev = crtc->dev;
7851 struct drm_i915_private *dev_priv = dev->dev_private;
7852 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7853 int pipe = intel_crtc->pipe;
7854 bool visible = base != 0;
7856 if (intel_crtc->cursor_visible != visible) {
7857 int16_t width = intel_crtc->cursor_width;
7858 uint32_t cntl = I915_READ(CURCNTR(pipe));
7860 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7861 cntl |= MCURSOR_GAMMA_ENABLE;
7865 cntl |= CURSOR_MODE_64_ARGB_AX;
7868 cntl |= CURSOR_MODE_128_ARGB_AX;
7871 cntl |= CURSOR_MODE_256_ARGB_AX;
7877 cntl |= pipe << 28; /* Connect to correct pipe */
7879 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7880 cntl |= CURSOR_MODE_DISABLE;
7882 I915_WRITE(CURCNTR(pipe), cntl);
7884 intel_crtc->cursor_visible = visible;
7886 /* and commit changes on next vblank */
7887 POSTING_READ(CURCNTR(pipe));
7888 I915_WRITE(CURBASE(pipe), base);
7889 POSTING_READ(CURBASE(pipe));
7892 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7894 struct drm_device *dev = crtc->dev;
7895 struct drm_i915_private *dev_priv = dev->dev_private;
7896 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7897 int pipe = intel_crtc->pipe;
7898 bool visible = base != 0;
7900 if (intel_crtc->cursor_visible != visible) {
7901 int16_t width = intel_crtc->cursor_width;
7902 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7904 cntl &= ~CURSOR_MODE;
7905 cntl |= MCURSOR_GAMMA_ENABLE;
7908 cntl |= CURSOR_MODE_64_ARGB_AX;
7911 cntl |= CURSOR_MODE_128_ARGB_AX;
7914 cntl |= CURSOR_MODE_256_ARGB_AX;
7921 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7922 cntl |= CURSOR_MODE_DISABLE;
7924 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7925 cntl |= CURSOR_PIPE_CSC_ENABLE;
7926 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7928 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7930 intel_crtc->cursor_visible = visible;
7932 /* and commit changes on next vblank */
7933 POSTING_READ(CURCNTR_IVB(pipe));
7934 I915_WRITE(CURBASE_IVB(pipe), base);
7935 POSTING_READ(CURBASE_IVB(pipe));
7938 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7939 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7942 struct drm_device *dev = crtc->dev;
7943 struct drm_i915_private *dev_priv = dev->dev_private;
7944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7945 int pipe = intel_crtc->pipe;
7946 int x = intel_crtc->cursor_x;
7947 int y = intel_crtc->cursor_y;
7948 u32 base = 0, pos = 0;
7952 base = intel_crtc->cursor_addr;
7954 if (x >= intel_crtc->config.pipe_src_w)
7957 if (y >= intel_crtc->config.pipe_src_h)
7961 if (x + intel_crtc->cursor_width <= 0)
7964 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7967 pos |= x << CURSOR_X_SHIFT;
7970 if (y + intel_crtc->cursor_height <= 0)
7973 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7976 pos |= y << CURSOR_Y_SHIFT;
7978 visible = base != 0;
7979 if (!visible && !intel_crtc->cursor_visible)
7982 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7983 I915_WRITE(CURPOS_IVB(pipe), pos);
7984 ivb_update_cursor(crtc, base);
7986 I915_WRITE(CURPOS(pipe), pos);
7987 if (IS_845G(dev) || IS_I865G(dev))
7988 i845_update_cursor(crtc, base);
7990 i9xx_update_cursor(crtc, base);
7994 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
7995 struct drm_file *file,
7997 uint32_t width, uint32_t height)
7999 struct drm_device *dev = crtc->dev;
8000 struct drm_i915_private *dev_priv = dev->dev_private;
8001 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8002 struct drm_i915_gem_object *obj;
8007 /* if we want to turn off the cursor ignore width and height */
8009 DRM_DEBUG_KMS("cursor off\n");
8012 mutex_lock(&dev->struct_mutex);
8016 /* Check for which cursor types we support */
8017 if (!((width == 64 && height == 64) ||
8018 (width == 128 && height == 128 && !IS_GEN2(dev)) ||
8019 (width == 256 && height == 256 && !IS_GEN2(dev)))) {
8020 DRM_DEBUG("Cursor dimension not supported\n");
8024 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
8025 if (&obj->base == NULL)
8028 if (obj->base.size < width * height * 4) {
8029 DRM_DEBUG_KMS("buffer is to small\n");
8034 /* we only need to pin inside GTT if cursor is non-phy */
8035 mutex_lock(&dev->struct_mutex);
8036 if (!INTEL_INFO(dev)->cursor_needs_physical) {
8039 if (obj->tiling_mode) {
8040 DRM_DEBUG_KMS("cursor cannot be tiled\n");
8045 /* Note that the w/a also requires 2 PTE of padding following
8046 * the bo. We currently fill all unused PTE with the shadow
8047 * page and so we should always have valid PTE following the
8048 * cursor preventing the VT-d warning.
8051 if (need_vtd_wa(dev))
8052 alignment = 64*1024;
8054 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8056 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8060 ret = i915_gem_object_put_fence(obj);
8062 DRM_DEBUG_KMS("failed to release fence for cursor");
8066 addr = i915_gem_obj_ggtt_offset(obj);
8068 int align = IS_I830(dev) ? 16 * 1024 : 256;
8069 ret = i915_gem_attach_phys_object(dev, obj,
8070 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
8073 DRM_DEBUG_KMS("failed to attach phys object\n");
8076 addr = obj->phys_obj->handle->busaddr;
8080 I915_WRITE(CURSIZE, (height << 12) | width);
8083 if (intel_crtc->cursor_bo) {
8084 if (INTEL_INFO(dev)->cursor_needs_physical) {
8085 if (intel_crtc->cursor_bo != obj)
8086 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
8088 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8089 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
8092 mutex_unlock(&dev->struct_mutex);
8094 old_width = intel_crtc->cursor_width;
8096 intel_crtc->cursor_addr = addr;
8097 intel_crtc->cursor_bo = obj;
8098 intel_crtc->cursor_width = width;
8099 intel_crtc->cursor_height = height;
8101 if (intel_crtc->active) {
8102 if (old_width != width)
8103 intel_update_watermarks(crtc);
8104 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8109 i915_gem_object_unpin_from_display_plane(obj);
8111 mutex_unlock(&dev->struct_mutex);
8113 drm_gem_object_unreference_unlocked(&obj->base);
8117 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
8119 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8121 intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
8122 intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
8124 if (intel_crtc->active)
8125 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8130 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8131 u16 *blue, uint32_t start, uint32_t size)
8133 int end = (start + size > 256) ? 256 : start + size, i;
8134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8136 for (i = start; i < end; i++) {
8137 intel_crtc->lut_r[i] = red[i] >> 8;
8138 intel_crtc->lut_g[i] = green[i] >> 8;
8139 intel_crtc->lut_b[i] = blue[i] >> 8;
8142 intel_crtc_load_lut(crtc);
8145 /* VESA 640x480x72Hz mode to set on the pipe */
8146 static struct drm_display_mode load_detect_mode = {
8147 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8148 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8151 struct drm_framebuffer *
8152 __intel_framebuffer_create(struct drm_device *dev,
8153 struct drm_mode_fb_cmd2 *mode_cmd,
8154 struct drm_i915_gem_object *obj)
8156 struct intel_framebuffer *intel_fb;
8159 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8161 drm_gem_object_unreference_unlocked(&obj->base);
8162 return ERR_PTR(-ENOMEM);
8165 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8169 return &intel_fb->base;
8171 drm_gem_object_unreference_unlocked(&obj->base);
8174 return ERR_PTR(ret);
8177 static struct drm_framebuffer *
8178 intel_framebuffer_create(struct drm_device *dev,
8179 struct drm_mode_fb_cmd2 *mode_cmd,
8180 struct drm_i915_gem_object *obj)
8182 struct drm_framebuffer *fb;
8185 ret = i915_mutex_lock_interruptible(dev);
8187 return ERR_PTR(ret);
8188 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8189 mutex_unlock(&dev->struct_mutex);
8195 intel_framebuffer_pitch_for_width(int width, int bpp)
8197 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8198 return ALIGN(pitch, 64);
8202 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8204 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8205 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
8208 static struct drm_framebuffer *
8209 intel_framebuffer_create_for_mode(struct drm_device *dev,
8210 struct drm_display_mode *mode,
8213 struct drm_i915_gem_object *obj;
8214 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8216 obj = i915_gem_alloc_object(dev,
8217 intel_framebuffer_size_for_mode(mode, bpp));
8219 return ERR_PTR(-ENOMEM);
8221 mode_cmd.width = mode->hdisplay;
8222 mode_cmd.height = mode->vdisplay;
8223 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8225 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8227 return intel_framebuffer_create(dev, &mode_cmd, obj);
8230 static struct drm_framebuffer *
8231 mode_fits_in_fbdev(struct drm_device *dev,
8232 struct drm_display_mode *mode)
8234 #ifdef CONFIG_DRM_I915_FBDEV
8235 struct drm_i915_private *dev_priv = dev->dev_private;
8236 struct drm_i915_gem_object *obj;
8237 struct drm_framebuffer *fb;
8239 if (!dev_priv->fbdev)
8242 if (!dev_priv->fbdev->fb)
8245 obj = dev_priv->fbdev->fb->obj;
8248 fb = &dev_priv->fbdev->fb->base;
8249 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8250 fb->bits_per_pixel))
8253 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8262 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8263 struct drm_display_mode *mode,
8264 struct intel_load_detect_pipe *old)
8266 struct intel_crtc *intel_crtc;
8267 struct intel_encoder *intel_encoder =
8268 intel_attached_encoder(connector);
8269 struct drm_crtc *possible_crtc;
8270 struct drm_encoder *encoder = &intel_encoder->base;
8271 struct drm_crtc *crtc = NULL;
8272 struct drm_device *dev = encoder->dev;
8273 struct drm_framebuffer *fb;
8276 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8277 connector->base.id, drm_get_connector_name(connector),
8278 encoder->base.id, drm_get_encoder_name(encoder));
8281 * Algorithm gets a little messy:
8283 * - if the connector already has an assigned crtc, use it (but make
8284 * sure it's on first)
8286 * - try to find the first unused crtc that can drive this connector,
8287 * and use that if we find one
8290 /* See if we already have a CRTC for this connector */
8291 if (encoder->crtc) {
8292 crtc = encoder->crtc;
8294 mutex_lock(&crtc->mutex);
8296 old->dpms_mode = connector->dpms;
8297 old->load_detect_temp = false;
8299 /* Make sure the crtc and connector are running */
8300 if (connector->dpms != DRM_MODE_DPMS_ON)
8301 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8306 /* Find an unused one (if possible) */
8307 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
8309 if (!(encoder->possible_crtcs & (1 << i)))
8311 if (!possible_crtc->enabled) {
8312 crtc = possible_crtc;
8318 * If we didn't find an unused CRTC, don't use any.
8321 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8325 mutex_lock(&crtc->mutex);
8326 intel_encoder->new_crtc = to_intel_crtc(crtc);
8327 to_intel_connector(connector)->new_encoder = intel_encoder;
8329 intel_crtc = to_intel_crtc(crtc);
8330 intel_crtc->new_enabled = true;
8331 intel_crtc->new_config = &intel_crtc->config;
8332 old->dpms_mode = connector->dpms;
8333 old->load_detect_temp = true;
8334 old->release_fb = NULL;
8337 mode = &load_detect_mode;
8339 /* We need a framebuffer large enough to accommodate all accesses
8340 * that the plane may generate whilst we perform load detection.
8341 * We can not rely on the fbcon either being present (we get called
8342 * during its initialisation to detect all boot displays, or it may
8343 * not even exist) or that it is large enough to satisfy the
8346 fb = mode_fits_in_fbdev(dev, mode);
8348 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8349 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8350 old->release_fb = fb;
8352 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8354 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8358 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8359 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8360 if (old->release_fb)
8361 old->release_fb->funcs->destroy(old->release_fb);
8365 /* let the connector get through one full cycle before testing */
8366 intel_wait_for_vblank(dev, intel_crtc->pipe);
8370 intel_crtc->new_enabled = crtc->enabled;
8371 if (intel_crtc->new_enabled)
8372 intel_crtc->new_config = &intel_crtc->config;
8374 intel_crtc->new_config = NULL;
8375 mutex_unlock(&crtc->mutex);
8379 void intel_release_load_detect_pipe(struct drm_connector *connector,
8380 struct intel_load_detect_pipe *old)
8382 struct intel_encoder *intel_encoder =
8383 intel_attached_encoder(connector);
8384 struct drm_encoder *encoder = &intel_encoder->base;
8385 struct drm_crtc *crtc = encoder->crtc;
8386 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8388 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8389 connector->base.id, drm_get_connector_name(connector),
8390 encoder->base.id, drm_get_encoder_name(encoder));
8392 if (old->load_detect_temp) {
8393 to_intel_connector(connector)->new_encoder = NULL;
8394 intel_encoder->new_crtc = NULL;
8395 intel_crtc->new_enabled = false;
8396 intel_crtc->new_config = NULL;
8397 intel_set_mode(crtc, NULL, 0, 0, NULL);
8399 if (old->release_fb) {
8400 drm_framebuffer_unregister_private(old->release_fb);
8401 drm_framebuffer_unreference(old->release_fb);
8404 mutex_unlock(&crtc->mutex);
8408 /* Switch crtc and encoder back off if necessary */
8409 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8410 connector->funcs->dpms(connector, old->dpms_mode);
8412 mutex_unlock(&crtc->mutex);
8415 static int i9xx_pll_refclk(struct drm_device *dev,
8416 const struct intel_crtc_config *pipe_config)
8418 struct drm_i915_private *dev_priv = dev->dev_private;
8419 u32 dpll = pipe_config->dpll_hw_state.dpll;
8421 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8422 return dev_priv->vbt.lvds_ssc_freq;
8423 else if (HAS_PCH_SPLIT(dev))
8425 else if (!IS_GEN2(dev))
8431 /* Returns the clock of the currently programmed mode of the given pipe. */
8432 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8433 struct intel_crtc_config *pipe_config)
8435 struct drm_device *dev = crtc->base.dev;
8436 struct drm_i915_private *dev_priv = dev->dev_private;
8437 int pipe = pipe_config->cpu_transcoder;
8438 u32 dpll = pipe_config->dpll_hw_state.dpll;
8440 intel_clock_t clock;
8441 int refclk = i9xx_pll_refclk(dev, pipe_config);
8443 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8444 fp = pipe_config->dpll_hw_state.fp0;
8446 fp = pipe_config->dpll_hw_state.fp1;
8448 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8449 if (IS_PINEVIEW(dev)) {
8450 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8451 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8453 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8454 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8457 if (!IS_GEN2(dev)) {
8458 if (IS_PINEVIEW(dev))
8459 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8460 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8462 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8463 DPLL_FPA01_P1_POST_DIV_SHIFT);
8465 switch (dpll & DPLL_MODE_MASK) {
8466 case DPLLB_MODE_DAC_SERIAL:
8467 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8470 case DPLLB_MODE_LVDS:
8471 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8475 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8476 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8480 if (IS_PINEVIEW(dev))
8481 pineview_clock(refclk, &clock);
8483 i9xx_clock(refclk, &clock);
8485 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8486 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8489 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8490 DPLL_FPA01_P1_POST_DIV_SHIFT);
8492 if (lvds & LVDS_CLKB_POWER_UP)
8497 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8500 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8501 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8503 if (dpll & PLL_P2_DIVIDE_BY_4)
8509 i9xx_clock(refclk, &clock);
8513 * This value includes pixel_multiplier. We will use
8514 * port_clock to compute adjusted_mode.crtc_clock in the
8515 * encoder's get_config() function.
8517 pipe_config->port_clock = clock.dot;
8520 int intel_dotclock_calculate(int link_freq,
8521 const struct intel_link_m_n *m_n)
8524 * The calculation for the data clock is:
8525 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8526 * But we want to avoid losing precison if possible, so:
8527 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8529 * and the link clock is simpler:
8530 * link_clock = (m * link_clock) / n
8536 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8539 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8540 struct intel_crtc_config *pipe_config)
8542 struct drm_device *dev = crtc->base.dev;
8544 /* read out port_clock from the DPLL */
8545 i9xx_crtc_clock_get(crtc, pipe_config);
8548 * This value does not include pixel_multiplier.
8549 * We will check that port_clock and adjusted_mode.crtc_clock
8550 * agree once we know their relationship in the encoder's
8551 * get_config() function.
8553 pipe_config->adjusted_mode.crtc_clock =
8554 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8555 &pipe_config->fdi_m_n);
8558 /** Returns the currently programmed mode of the given pipe. */
8559 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8560 struct drm_crtc *crtc)
8562 struct drm_i915_private *dev_priv = dev->dev_private;
8563 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8564 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8565 struct drm_display_mode *mode;
8566 struct intel_crtc_config pipe_config;
8567 int htot = I915_READ(HTOTAL(cpu_transcoder));
8568 int hsync = I915_READ(HSYNC(cpu_transcoder));
8569 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8570 int vsync = I915_READ(VSYNC(cpu_transcoder));
8571 enum pipe pipe = intel_crtc->pipe;
8573 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8578 * Construct a pipe_config sufficient for getting the clock info
8579 * back out of crtc_clock_get.
8581 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8582 * to use a real value here instead.
8584 pipe_config.cpu_transcoder = (enum transcoder) pipe;
8585 pipe_config.pixel_multiplier = 1;
8586 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8587 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8588 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8589 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8591 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8592 mode->hdisplay = (htot & 0xffff) + 1;
8593 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8594 mode->hsync_start = (hsync & 0xffff) + 1;
8595 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8596 mode->vdisplay = (vtot & 0xffff) + 1;
8597 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8598 mode->vsync_start = (vsync & 0xffff) + 1;
8599 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8601 drm_mode_set_name(mode);
8606 static void intel_increase_pllclock(struct drm_crtc *crtc)
8608 struct drm_device *dev = crtc->dev;
8609 struct drm_i915_private *dev_priv = dev->dev_private;
8610 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8611 int pipe = intel_crtc->pipe;
8612 int dpll_reg = DPLL(pipe);
8615 if (HAS_PCH_SPLIT(dev))
8618 if (!dev_priv->lvds_downclock_avail)
8621 dpll = I915_READ(dpll_reg);
8622 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8623 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8625 assert_panel_unlocked(dev_priv, pipe);
8627 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8628 I915_WRITE(dpll_reg, dpll);
8629 intel_wait_for_vblank(dev, pipe);
8631 dpll = I915_READ(dpll_reg);
8632 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8633 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8637 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8639 struct drm_device *dev = crtc->dev;
8640 struct drm_i915_private *dev_priv = dev->dev_private;
8641 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8643 if (HAS_PCH_SPLIT(dev))
8646 if (!dev_priv->lvds_downclock_avail)
8650 * Since this is called by a timer, we should never get here in
8653 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8654 int pipe = intel_crtc->pipe;
8655 int dpll_reg = DPLL(pipe);
8658 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8660 assert_panel_unlocked(dev_priv, pipe);
8662 dpll = I915_READ(dpll_reg);
8663 dpll |= DISPLAY_RATE_SELECT_FPA1;
8664 I915_WRITE(dpll_reg, dpll);
8665 intel_wait_for_vblank(dev, pipe);
8666 dpll = I915_READ(dpll_reg);
8667 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8668 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8673 void intel_mark_busy(struct drm_device *dev)
8675 struct drm_i915_private *dev_priv = dev->dev_private;
8677 if (dev_priv->mm.busy)
8680 intel_runtime_pm_get(dev_priv);
8681 i915_update_gfx_val(dev_priv);
8682 dev_priv->mm.busy = true;
8685 void intel_mark_idle(struct drm_device *dev)
8687 struct drm_i915_private *dev_priv = dev->dev_private;
8688 struct drm_crtc *crtc;
8690 if (!dev_priv->mm.busy)
8693 dev_priv->mm.busy = false;
8695 if (!i915.powersave)
8698 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8699 if (!crtc->primary->fb)
8702 intel_decrease_pllclock(crtc);
8705 if (INTEL_INFO(dev)->gen >= 6)
8706 gen6_rps_idle(dev->dev_private);
8709 intel_runtime_pm_put(dev_priv);
8712 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
8713 struct intel_ring_buffer *ring)
8715 struct drm_device *dev = obj->base.dev;
8716 struct drm_crtc *crtc;
8718 if (!i915.powersave)
8721 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8722 if (!crtc->primary->fb)
8725 if (to_intel_framebuffer(crtc->primary->fb)->obj != obj)
8728 intel_increase_pllclock(crtc);
8729 if (ring && intel_fbc_enabled(dev))
8730 ring->fbc_dirty = true;
8734 static void intel_crtc_destroy(struct drm_crtc *crtc)
8736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8737 struct drm_device *dev = crtc->dev;
8738 struct intel_unpin_work *work;
8739 unsigned long flags;
8741 spin_lock_irqsave(&dev->event_lock, flags);
8742 work = intel_crtc->unpin_work;
8743 intel_crtc->unpin_work = NULL;
8744 spin_unlock_irqrestore(&dev->event_lock, flags);
8747 cancel_work_sync(&work->work);
8751 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
8753 drm_crtc_cleanup(crtc);
8758 static void intel_unpin_work_fn(struct work_struct *__work)
8760 struct intel_unpin_work *work =
8761 container_of(__work, struct intel_unpin_work, work);
8762 struct drm_device *dev = work->crtc->dev;
8764 mutex_lock(&dev->struct_mutex);
8765 intel_unpin_fb_obj(work->old_fb_obj);
8766 drm_gem_object_unreference(&work->pending_flip_obj->base);
8767 drm_gem_object_unreference(&work->old_fb_obj->base);
8769 intel_update_fbc(dev);
8770 mutex_unlock(&dev->struct_mutex);
8772 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8773 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8778 static void do_intel_finish_page_flip(struct drm_device *dev,
8779 struct drm_crtc *crtc)
8781 struct drm_i915_private *dev_priv = dev->dev_private;
8782 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8783 struct intel_unpin_work *work;
8784 unsigned long flags;
8786 /* Ignore early vblank irqs */
8787 if (intel_crtc == NULL)
8790 spin_lock_irqsave(&dev->event_lock, flags);
8791 work = intel_crtc->unpin_work;
8793 /* Ensure we don't miss a work->pending update ... */
8796 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8797 spin_unlock_irqrestore(&dev->event_lock, flags);
8801 /* and that the unpin work is consistent wrt ->pending. */
8804 intel_crtc->unpin_work = NULL;
8807 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
8809 drm_vblank_put(dev, intel_crtc->pipe);
8811 spin_unlock_irqrestore(&dev->event_lock, flags);
8813 wake_up_all(&dev_priv->pending_flip_queue);
8815 queue_work(dev_priv->wq, &work->work);
8817 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
8820 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8822 struct drm_i915_private *dev_priv = dev->dev_private;
8823 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8825 do_intel_finish_page_flip(dev, crtc);
8828 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8830 struct drm_i915_private *dev_priv = dev->dev_private;
8831 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8833 do_intel_finish_page_flip(dev, crtc);
8836 void intel_prepare_page_flip(struct drm_device *dev, int plane)
8838 struct drm_i915_private *dev_priv = dev->dev_private;
8839 struct intel_crtc *intel_crtc =
8840 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8841 unsigned long flags;
8843 /* NB: An MMIO update of the plane base pointer will also
8844 * generate a page-flip completion irq, i.e. every modeset
8845 * is also accompanied by a spurious intel_prepare_page_flip().
8847 spin_lock_irqsave(&dev->event_lock, flags);
8848 if (intel_crtc->unpin_work)
8849 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
8850 spin_unlock_irqrestore(&dev->event_lock, flags);
8853 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8855 /* Ensure that the work item is consistent when activating it ... */
8857 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8858 /* and that it is marked active as soon as the irq could fire. */
8862 static int intel_gen2_queue_flip(struct drm_device *dev,
8863 struct drm_crtc *crtc,
8864 struct drm_framebuffer *fb,
8865 struct drm_i915_gem_object *obj,
8868 struct drm_i915_private *dev_priv = dev->dev_private;
8869 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8871 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8874 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8878 ret = intel_ring_begin(ring, 6);
8882 /* Can't queue multiple flips, so wait for the previous
8883 * one to finish before executing the next.
8885 if (intel_crtc->plane)
8886 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8888 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8889 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8890 intel_ring_emit(ring, MI_NOOP);
8891 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8892 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8893 intel_ring_emit(ring, fb->pitches[0]);
8894 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8895 intel_ring_emit(ring, 0); /* aux display base address, unused */
8897 intel_mark_page_flip_active(intel_crtc);
8898 __intel_ring_advance(ring);
8902 intel_unpin_fb_obj(obj);
8907 static int intel_gen3_queue_flip(struct drm_device *dev,
8908 struct drm_crtc *crtc,
8909 struct drm_framebuffer *fb,
8910 struct drm_i915_gem_object *obj,
8913 struct drm_i915_private *dev_priv = dev->dev_private;
8914 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8916 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8919 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8923 ret = intel_ring_begin(ring, 6);
8927 if (intel_crtc->plane)
8928 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8930 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8931 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8932 intel_ring_emit(ring, MI_NOOP);
8933 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8934 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8935 intel_ring_emit(ring, fb->pitches[0]);
8936 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8937 intel_ring_emit(ring, MI_NOOP);
8939 intel_mark_page_flip_active(intel_crtc);
8940 __intel_ring_advance(ring);
8944 intel_unpin_fb_obj(obj);
8949 static int intel_gen4_queue_flip(struct drm_device *dev,
8950 struct drm_crtc *crtc,
8951 struct drm_framebuffer *fb,
8952 struct drm_i915_gem_object *obj,
8955 struct drm_i915_private *dev_priv = dev->dev_private;
8956 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8957 uint32_t pf, pipesrc;
8958 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8961 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8965 ret = intel_ring_begin(ring, 4);
8969 /* i965+ uses the linear or tiled offsets from the
8970 * Display Registers (which do not change across a page-flip)
8971 * so we need only reprogram the base address.
8973 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8974 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8975 intel_ring_emit(ring, fb->pitches[0]);
8976 intel_ring_emit(ring,
8977 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
8980 /* XXX Enabling the panel-fitter across page-flip is so far
8981 * untested on non-native modes, so ignore it for now.
8982 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8985 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8986 intel_ring_emit(ring, pf | pipesrc);
8988 intel_mark_page_flip_active(intel_crtc);
8989 __intel_ring_advance(ring);
8993 intel_unpin_fb_obj(obj);
8998 static int intel_gen6_queue_flip(struct drm_device *dev,
8999 struct drm_crtc *crtc,
9000 struct drm_framebuffer *fb,
9001 struct drm_i915_gem_object *obj,
9004 struct drm_i915_private *dev_priv = dev->dev_private;
9005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9006 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
9007 uint32_t pf, pipesrc;
9010 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9014 ret = intel_ring_begin(ring, 4);
9018 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9019 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9020 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9021 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
9023 /* Contrary to the suggestions in the documentation,
9024 * "Enable Panel Fitter" does not seem to be required when page
9025 * flipping with a non-native mode, and worse causes a normal
9027 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9030 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9031 intel_ring_emit(ring, pf | pipesrc);
9033 intel_mark_page_flip_active(intel_crtc);
9034 __intel_ring_advance(ring);
9038 intel_unpin_fb_obj(obj);
9043 static int intel_gen7_queue_flip(struct drm_device *dev,
9044 struct drm_crtc *crtc,
9045 struct drm_framebuffer *fb,
9046 struct drm_i915_gem_object *obj,
9049 struct drm_i915_private *dev_priv = dev->dev_private;
9050 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9051 struct intel_ring_buffer *ring;
9052 uint32_t plane_bit = 0;
9056 if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
9057 ring = &dev_priv->ring[BCS];
9059 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9063 switch(intel_crtc->plane) {
9065 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9068 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9071 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9074 WARN_ONCE(1, "unknown plane in flip command\n");
9080 if (ring->id == RCS) {
9083 * On Gen 8, SRM is now taking an extra dword to accommodate
9084 * 48bits addresses, and we need a NOOP for the batch size to
9092 * BSpec MI_DISPLAY_FLIP for IVB:
9093 * "The full packet must be contained within the same cache line."
9095 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9096 * cacheline, if we ever start emitting more commands before
9097 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9098 * then do the cacheline alignment, and finally emit the
9101 ret = intel_ring_cacheline_align(ring);
9105 ret = intel_ring_begin(ring, len);
9109 /* Unmask the flip-done completion message. Note that the bspec says that
9110 * we should do this for both the BCS and RCS, and that we must not unmask
9111 * more than one flip event at any time (or ensure that one flip message
9112 * can be sent by waiting for flip-done prior to queueing new flips).
9113 * Experimentation says that BCS works despite DERRMR masking all
9114 * flip-done completion events and that unmasking all planes at once
9115 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9116 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9118 if (ring->id == RCS) {
9119 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9120 intel_ring_emit(ring, DERRMR);
9121 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9122 DERRMR_PIPEB_PRI_FLIP_DONE |
9123 DERRMR_PIPEC_PRI_FLIP_DONE));
9125 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9126 MI_SRM_LRM_GLOBAL_GTT);
9128 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9129 MI_SRM_LRM_GLOBAL_GTT);
9130 intel_ring_emit(ring, DERRMR);
9131 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9133 intel_ring_emit(ring, 0);
9134 intel_ring_emit(ring, MI_NOOP);
9138 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9139 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9140 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
9141 intel_ring_emit(ring, (MI_NOOP));
9143 intel_mark_page_flip_active(intel_crtc);
9144 __intel_ring_advance(ring);
9148 intel_unpin_fb_obj(obj);
9153 static int intel_default_queue_flip(struct drm_device *dev,
9154 struct drm_crtc *crtc,
9155 struct drm_framebuffer *fb,
9156 struct drm_i915_gem_object *obj,
9162 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9163 struct drm_framebuffer *fb,
9164 struct drm_pending_vblank_event *event,
9165 uint32_t page_flip_flags)
9167 struct drm_device *dev = crtc->dev;
9168 struct drm_i915_private *dev_priv = dev->dev_private;
9169 struct drm_framebuffer *old_fb = crtc->primary->fb;
9170 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
9171 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9172 struct intel_unpin_work *work;
9173 unsigned long flags;
9176 /* Can't change pixel format via MI display flips. */
9177 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9181 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9182 * Note that pitch changes could also affect these register.
9184 if (INTEL_INFO(dev)->gen > 3 &&
9185 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9186 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9189 if (i915_terminally_wedged(&dev_priv->gpu_error))
9192 work = kzalloc(sizeof(*work), GFP_KERNEL);
9196 work->event = event;
9198 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
9199 INIT_WORK(&work->work, intel_unpin_work_fn);
9201 ret = drm_vblank_get(dev, intel_crtc->pipe);
9205 /* We borrow the event spin lock for protecting unpin_work */
9206 spin_lock_irqsave(&dev->event_lock, flags);
9207 if (intel_crtc->unpin_work) {
9208 spin_unlock_irqrestore(&dev->event_lock, flags);
9210 drm_vblank_put(dev, intel_crtc->pipe);
9212 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9215 intel_crtc->unpin_work = work;
9216 spin_unlock_irqrestore(&dev->event_lock, flags);
9218 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9219 flush_workqueue(dev_priv->wq);
9221 ret = i915_mutex_lock_interruptible(dev);
9225 /* Reference the objects for the scheduled work. */
9226 drm_gem_object_reference(&work->old_fb_obj->base);
9227 drm_gem_object_reference(&obj->base);
9229 crtc->primary->fb = fb;
9231 work->pending_flip_obj = obj;
9233 work->enable_stall_check = true;
9235 atomic_inc(&intel_crtc->unpin_work_count);
9236 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9238 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
9240 goto cleanup_pending;
9242 intel_disable_fbc(dev);
9243 intel_mark_fb_busy(obj, NULL);
9244 mutex_unlock(&dev->struct_mutex);
9246 trace_i915_flip_request(intel_crtc->plane, obj);
9251 atomic_dec(&intel_crtc->unpin_work_count);
9252 crtc->primary->fb = old_fb;
9253 drm_gem_object_unreference(&work->old_fb_obj->base);
9254 drm_gem_object_unreference(&obj->base);
9255 mutex_unlock(&dev->struct_mutex);
9258 spin_lock_irqsave(&dev->event_lock, flags);
9259 intel_crtc->unpin_work = NULL;
9260 spin_unlock_irqrestore(&dev->event_lock, flags);
9262 drm_vblank_put(dev, intel_crtc->pipe);
9268 intel_crtc_wait_for_pending_flips(crtc);
9269 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9270 if (ret == 0 && event)
9271 drm_send_vblank_event(dev, intel_crtc->pipe, event);
9276 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9277 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9278 .load_lut = intel_crtc_load_lut,
9282 * intel_modeset_update_staged_output_state
9284 * Updates the staged output configuration state, e.g. after we've read out the
9287 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9289 struct intel_crtc *crtc;
9290 struct intel_encoder *encoder;
9291 struct intel_connector *connector;
9293 list_for_each_entry(connector, &dev->mode_config.connector_list,
9295 connector->new_encoder =
9296 to_intel_encoder(connector->base.encoder);
9299 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9302 to_intel_crtc(encoder->base.crtc);
9305 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9307 crtc->new_enabled = crtc->base.enabled;
9309 if (crtc->new_enabled)
9310 crtc->new_config = &crtc->config;
9312 crtc->new_config = NULL;
9317 * intel_modeset_commit_output_state
9319 * This function copies the stage display pipe configuration to the real one.
9321 static void intel_modeset_commit_output_state(struct drm_device *dev)
9323 struct intel_crtc *crtc;
9324 struct intel_encoder *encoder;
9325 struct intel_connector *connector;
9327 list_for_each_entry(connector, &dev->mode_config.connector_list,
9329 connector->base.encoder = &connector->new_encoder->base;
9332 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9334 encoder->base.crtc = &encoder->new_crtc->base;
9337 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9339 crtc->base.enabled = crtc->new_enabled;
9344 connected_sink_compute_bpp(struct intel_connector * connector,
9345 struct intel_crtc_config *pipe_config)
9347 int bpp = pipe_config->pipe_bpp;
9349 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9350 connector->base.base.id,
9351 drm_get_connector_name(&connector->base));
9353 /* Don't use an invalid EDID bpc value */
9354 if (connector->base.display_info.bpc &&
9355 connector->base.display_info.bpc * 3 < bpp) {
9356 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9357 bpp, connector->base.display_info.bpc*3);
9358 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9361 /* Clamp bpp to 8 on screens without EDID 1.4 */
9362 if (connector->base.display_info.bpc == 0 && bpp > 24) {
9363 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9365 pipe_config->pipe_bpp = 24;
9370 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9371 struct drm_framebuffer *fb,
9372 struct intel_crtc_config *pipe_config)
9374 struct drm_device *dev = crtc->base.dev;
9375 struct intel_connector *connector;
9378 switch (fb->pixel_format) {
9380 bpp = 8*3; /* since we go through a colormap */
9382 case DRM_FORMAT_XRGB1555:
9383 case DRM_FORMAT_ARGB1555:
9384 /* checked in intel_framebuffer_init already */
9385 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9387 case DRM_FORMAT_RGB565:
9388 bpp = 6*3; /* min is 18bpp */
9390 case DRM_FORMAT_XBGR8888:
9391 case DRM_FORMAT_ABGR8888:
9392 /* checked in intel_framebuffer_init already */
9393 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9395 case DRM_FORMAT_XRGB8888:
9396 case DRM_FORMAT_ARGB8888:
9399 case DRM_FORMAT_XRGB2101010:
9400 case DRM_FORMAT_ARGB2101010:
9401 case DRM_FORMAT_XBGR2101010:
9402 case DRM_FORMAT_ABGR2101010:
9403 /* checked in intel_framebuffer_init already */
9404 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9408 /* TODO: gen4+ supports 16 bpc floating point, too. */
9410 DRM_DEBUG_KMS("unsupported depth\n");
9414 pipe_config->pipe_bpp = bpp;
9416 /* Clamp display bpp to EDID value */
9417 list_for_each_entry(connector, &dev->mode_config.connector_list,
9419 if (!connector->new_encoder ||
9420 connector->new_encoder->new_crtc != crtc)
9423 connected_sink_compute_bpp(connector, pipe_config);
9429 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9431 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9432 "type: 0x%x flags: 0x%x\n",
9434 mode->crtc_hdisplay, mode->crtc_hsync_start,
9435 mode->crtc_hsync_end, mode->crtc_htotal,
9436 mode->crtc_vdisplay, mode->crtc_vsync_start,
9437 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9440 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9441 struct intel_crtc_config *pipe_config,
9442 const char *context)
9444 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9445 context, pipe_name(crtc->pipe));
9447 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9448 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9449 pipe_config->pipe_bpp, pipe_config->dither);
9450 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9451 pipe_config->has_pch_encoder,
9452 pipe_config->fdi_lanes,
9453 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9454 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9455 pipe_config->fdi_m_n.tu);
9456 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9457 pipe_config->has_dp_encoder,
9458 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9459 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9460 pipe_config->dp_m_n.tu);
9461 DRM_DEBUG_KMS("requested mode:\n");
9462 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9463 DRM_DEBUG_KMS("adjusted mode:\n");
9464 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9465 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9466 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9467 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9468 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9469 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9470 pipe_config->gmch_pfit.control,
9471 pipe_config->gmch_pfit.pgm_ratios,
9472 pipe_config->gmch_pfit.lvds_border_bits);
9473 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9474 pipe_config->pch_pfit.pos,
9475 pipe_config->pch_pfit.size,
9476 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9477 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9478 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
9481 static bool encoders_cloneable(const struct intel_encoder *a,
9482 const struct intel_encoder *b)
9484 /* masks could be asymmetric, so check both ways */
9485 return a == b || (a->cloneable & (1 << b->type) &&
9486 b->cloneable & (1 << a->type));
9489 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9490 struct intel_encoder *encoder)
9492 struct drm_device *dev = crtc->base.dev;
9493 struct intel_encoder *source_encoder;
9495 list_for_each_entry(source_encoder,
9496 &dev->mode_config.encoder_list, base.head) {
9497 if (source_encoder->new_crtc != crtc)
9500 if (!encoders_cloneable(encoder, source_encoder))
9507 static bool check_encoder_cloning(struct intel_crtc *crtc)
9509 struct drm_device *dev = crtc->base.dev;
9510 struct intel_encoder *encoder;
9512 list_for_each_entry(encoder,
9513 &dev->mode_config.encoder_list, base.head) {
9514 if (encoder->new_crtc != crtc)
9517 if (!check_single_encoder_cloning(crtc, encoder))
9524 static struct intel_crtc_config *
9525 intel_modeset_pipe_config(struct drm_crtc *crtc,
9526 struct drm_framebuffer *fb,
9527 struct drm_display_mode *mode)
9529 struct drm_device *dev = crtc->dev;
9530 struct intel_encoder *encoder;
9531 struct intel_crtc_config *pipe_config;
9532 int plane_bpp, ret = -EINVAL;
9535 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
9536 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
9537 return ERR_PTR(-EINVAL);
9540 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9542 return ERR_PTR(-ENOMEM);
9544 drm_mode_copy(&pipe_config->adjusted_mode, mode);
9545 drm_mode_copy(&pipe_config->requested_mode, mode);
9547 pipe_config->cpu_transcoder =
9548 (enum transcoder) to_intel_crtc(crtc)->pipe;
9549 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9552 * Sanitize sync polarity flags based on requested ones. If neither
9553 * positive or negative polarity is requested, treat this as meaning
9554 * negative polarity.
9556 if (!(pipe_config->adjusted_mode.flags &
9557 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
9558 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
9560 if (!(pipe_config->adjusted_mode.flags &
9561 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
9562 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
9564 /* Compute a starting value for pipe_config->pipe_bpp taking the source
9565 * plane pixel format and any sink constraints into account. Returns the
9566 * source plane bpp so that dithering can be selected on mismatches
9567 * after encoders and crtc also have had their say. */
9568 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
9574 * Determine the real pipe dimensions. Note that stereo modes can
9575 * increase the actual pipe size due to the frame doubling and
9576 * insertion of additional space for blanks between the frame. This
9577 * is stored in the crtc timings. We use the requested mode to do this
9578 * computation to clearly distinguish it from the adjusted mode, which
9579 * can be changed by the connectors in the below retry loop.
9581 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
9582 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
9583 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
9586 /* Ensure the port clock defaults are reset when retrying. */
9587 pipe_config->port_clock = 0;
9588 pipe_config->pixel_multiplier = 1;
9590 /* Fill in default crtc timings, allow encoders to overwrite them. */
9591 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
9593 /* Pass our mode to the connectors and the CRTC to give them a chance to
9594 * adjust it according to limitations or connector properties, and also
9595 * a chance to reject the mode entirely.
9597 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9600 if (&encoder->new_crtc->base != crtc)
9603 if (!(encoder->compute_config(encoder, pipe_config))) {
9604 DRM_DEBUG_KMS("Encoder config failure\n");
9609 /* Set default port clock if not overwritten by the encoder. Needs to be
9610 * done afterwards in case the encoder adjusts the mode. */
9611 if (!pipe_config->port_clock)
9612 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
9613 * pipe_config->pixel_multiplier;
9615 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
9617 DRM_DEBUG_KMS("CRTC fixup failed\n");
9622 if (WARN(!retry, "loop in pipe configuration computation\n")) {
9627 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9632 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
9633 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9634 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
9639 return ERR_PTR(ret);
9642 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
9643 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9645 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
9646 unsigned *prepare_pipes, unsigned *disable_pipes)
9648 struct intel_crtc *intel_crtc;
9649 struct drm_device *dev = crtc->dev;
9650 struct intel_encoder *encoder;
9651 struct intel_connector *connector;
9652 struct drm_crtc *tmp_crtc;
9654 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
9656 /* Check which crtcs have changed outputs connected to them, these need
9657 * to be part of the prepare_pipes mask. We don't (yet) support global
9658 * modeset across multiple crtcs, so modeset_pipes will only have one
9659 * bit set at most. */
9660 list_for_each_entry(connector, &dev->mode_config.connector_list,
9662 if (connector->base.encoder == &connector->new_encoder->base)
9665 if (connector->base.encoder) {
9666 tmp_crtc = connector->base.encoder->crtc;
9668 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9671 if (connector->new_encoder)
9673 1 << connector->new_encoder->new_crtc->pipe;
9676 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9678 if (encoder->base.crtc == &encoder->new_crtc->base)
9681 if (encoder->base.crtc) {
9682 tmp_crtc = encoder->base.crtc;
9684 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9687 if (encoder->new_crtc)
9688 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
9691 /* Check for pipes that will be enabled/disabled ... */
9692 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9694 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
9697 if (!intel_crtc->new_enabled)
9698 *disable_pipes |= 1 << intel_crtc->pipe;
9700 *prepare_pipes |= 1 << intel_crtc->pipe;
9704 /* set_mode is also used to update properties on life display pipes. */
9705 intel_crtc = to_intel_crtc(crtc);
9706 if (intel_crtc->new_enabled)
9707 *prepare_pipes |= 1 << intel_crtc->pipe;
9710 * For simplicity do a full modeset on any pipe where the output routing
9711 * changed. We could be more clever, but that would require us to be
9712 * more careful with calling the relevant encoder->mode_set functions.
9715 *modeset_pipes = *prepare_pipes;
9717 /* ... and mask these out. */
9718 *modeset_pipes &= ~(*disable_pipes);
9719 *prepare_pipes &= ~(*disable_pipes);
9722 * HACK: We don't (yet) fully support global modesets. intel_set_config
9723 * obies this rule, but the modeset restore mode of
9724 * intel_modeset_setup_hw_state does not.
9726 *modeset_pipes &= 1 << intel_crtc->pipe;
9727 *prepare_pipes &= 1 << intel_crtc->pipe;
9729 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9730 *modeset_pipes, *prepare_pipes, *disable_pipes);
9733 static bool intel_crtc_in_use(struct drm_crtc *crtc)
9735 struct drm_encoder *encoder;
9736 struct drm_device *dev = crtc->dev;
9738 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
9739 if (encoder->crtc == crtc)
9746 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
9748 struct intel_encoder *intel_encoder;
9749 struct intel_crtc *intel_crtc;
9750 struct drm_connector *connector;
9752 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
9754 if (!intel_encoder->base.crtc)
9757 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
9759 if (prepare_pipes & (1 << intel_crtc->pipe))
9760 intel_encoder->connectors_active = false;
9763 intel_modeset_commit_output_state(dev);
9765 /* Double check state. */
9766 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9768 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
9769 WARN_ON(intel_crtc->new_config &&
9770 intel_crtc->new_config != &intel_crtc->config);
9771 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
9774 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9775 if (!connector->encoder || !connector->encoder->crtc)
9778 intel_crtc = to_intel_crtc(connector->encoder->crtc);
9780 if (prepare_pipes & (1 << intel_crtc->pipe)) {
9781 struct drm_property *dpms_property =
9782 dev->mode_config.dpms_property;
9784 connector->dpms = DRM_MODE_DPMS_ON;
9785 drm_object_property_set_value(&connector->base,
9789 intel_encoder = to_intel_encoder(connector->encoder);
9790 intel_encoder->connectors_active = true;
9796 static bool intel_fuzzy_clock_check(int clock1, int clock2)
9800 if (clock1 == clock2)
9803 if (!clock1 || !clock2)
9806 diff = abs(clock1 - clock2);
9808 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
9814 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9815 list_for_each_entry((intel_crtc), \
9816 &(dev)->mode_config.crtc_list, \
9818 if (mask & (1 <<(intel_crtc)->pipe))
9821 intel_pipe_config_compare(struct drm_device *dev,
9822 struct intel_crtc_config *current_config,
9823 struct intel_crtc_config *pipe_config)
9825 #define PIPE_CONF_CHECK_X(name) \
9826 if (current_config->name != pipe_config->name) { \
9827 DRM_ERROR("mismatch in " #name " " \
9828 "(expected 0x%08x, found 0x%08x)\n", \
9829 current_config->name, \
9830 pipe_config->name); \
9834 #define PIPE_CONF_CHECK_I(name) \
9835 if (current_config->name != pipe_config->name) { \
9836 DRM_ERROR("mismatch in " #name " " \
9837 "(expected %i, found %i)\n", \
9838 current_config->name, \
9839 pipe_config->name); \
9843 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
9844 if ((current_config->name ^ pipe_config->name) & (mask)) { \
9845 DRM_ERROR("mismatch in " #name "(" #mask ") " \
9846 "(expected %i, found %i)\n", \
9847 current_config->name & (mask), \
9848 pipe_config->name & (mask)); \
9852 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9853 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9854 DRM_ERROR("mismatch in " #name " " \
9855 "(expected %i, found %i)\n", \
9856 current_config->name, \
9857 pipe_config->name); \
9861 #define PIPE_CONF_QUIRK(quirk) \
9862 ((current_config->quirks | pipe_config->quirks) & (quirk))
9864 PIPE_CONF_CHECK_I(cpu_transcoder);
9866 PIPE_CONF_CHECK_I(has_pch_encoder);
9867 PIPE_CONF_CHECK_I(fdi_lanes);
9868 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9869 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9870 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9871 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9872 PIPE_CONF_CHECK_I(fdi_m_n.tu);
9874 PIPE_CONF_CHECK_I(has_dp_encoder);
9875 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9876 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9877 PIPE_CONF_CHECK_I(dp_m_n.link_m);
9878 PIPE_CONF_CHECK_I(dp_m_n.link_n);
9879 PIPE_CONF_CHECK_I(dp_m_n.tu);
9881 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9882 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9883 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9884 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9885 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9886 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9888 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9889 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9890 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9891 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9892 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9893 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9895 PIPE_CONF_CHECK_I(pixel_multiplier);
9897 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9898 DRM_MODE_FLAG_INTERLACE);
9900 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9901 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9902 DRM_MODE_FLAG_PHSYNC);
9903 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9904 DRM_MODE_FLAG_NHSYNC);
9905 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9906 DRM_MODE_FLAG_PVSYNC);
9907 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9908 DRM_MODE_FLAG_NVSYNC);
9911 PIPE_CONF_CHECK_I(pipe_src_w);
9912 PIPE_CONF_CHECK_I(pipe_src_h);
9915 * FIXME: BIOS likes to set up a cloned config with lvds+external
9916 * screen. Since we don't yet re-compute the pipe config when moving
9917 * just the lvds port away to another pipe the sw tracking won't match.
9919 * Proper atomic modesets with recomputed global state will fix this.
9920 * Until then just don't check gmch state for inherited modes.
9922 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
9923 PIPE_CONF_CHECK_I(gmch_pfit.control);
9924 /* pfit ratios are autocomputed by the hw on gen4+ */
9925 if (INTEL_INFO(dev)->gen < 4)
9926 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9927 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9930 PIPE_CONF_CHECK_I(pch_pfit.enabled);
9931 if (current_config->pch_pfit.enabled) {
9932 PIPE_CONF_CHECK_I(pch_pfit.pos);
9933 PIPE_CONF_CHECK_I(pch_pfit.size);
9936 /* BDW+ don't expose a synchronous way to read the state */
9937 if (IS_HASWELL(dev))
9938 PIPE_CONF_CHECK_I(ips_enabled);
9940 PIPE_CONF_CHECK_I(double_wide);
9942 PIPE_CONF_CHECK_I(shared_dpll);
9943 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
9944 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
9945 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
9946 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
9948 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
9949 PIPE_CONF_CHECK_I(pipe_bpp);
9951 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
9952 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
9954 #undef PIPE_CONF_CHECK_X
9955 #undef PIPE_CONF_CHECK_I
9956 #undef PIPE_CONF_CHECK_FLAGS
9957 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
9958 #undef PIPE_CONF_QUIRK
9964 check_connector_state(struct drm_device *dev)
9966 struct intel_connector *connector;
9968 list_for_each_entry(connector, &dev->mode_config.connector_list,
9970 /* This also checks the encoder/connector hw state with the
9971 * ->get_hw_state callbacks. */
9972 intel_connector_check_state(connector);
9974 WARN(&connector->new_encoder->base != connector->base.encoder,
9975 "connector's staged encoder doesn't match current encoder\n");
9980 check_encoder_state(struct drm_device *dev)
9982 struct intel_encoder *encoder;
9983 struct intel_connector *connector;
9985 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9987 bool enabled = false;
9988 bool active = false;
9989 enum pipe pipe, tracked_pipe;
9991 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
9992 encoder->base.base.id,
9993 drm_get_encoder_name(&encoder->base));
9995 WARN(&encoder->new_crtc->base != encoder->base.crtc,
9996 "encoder's stage crtc doesn't match current crtc\n");
9997 WARN(encoder->connectors_active && !encoder->base.crtc,
9998 "encoder's active_connectors set, but no crtc\n");
10000 list_for_each_entry(connector, &dev->mode_config.connector_list,
10002 if (connector->base.encoder != &encoder->base)
10005 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10008 WARN(!!encoder->base.crtc != enabled,
10009 "encoder's enabled state mismatch "
10010 "(expected %i, found %i)\n",
10011 !!encoder->base.crtc, enabled);
10012 WARN(active && !encoder->base.crtc,
10013 "active encoder with no crtc\n");
10015 WARN(encoder->connectors_active != active,
10016 "encoder's computed active state doesn't match tracked active state "
10017 "(expected %i, found %i)\n", active, encoder->connectors_active);
10019 active = encoder->get_hw_state(encoder, &pipe);
10020 WARN(active != encoder->connectors_active,
10021 "encoder's hw state doesn't match sw tracking "
10022 "(expected %i, found %i)\n",
10023 encoder->connectors_active, active);
10025 if (!encoder->base.crtc)
10028 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10029 WARN(active && pipe != tracked_pipe,
10030 "active encoder's pipe doesn't match"
10031 "(expected %i, found %i)\n",
10032 tracked_pipe, pipe);
10038 check_crtc_state(struct drm_device *dev)
10040 struct drm_i915_private *dev_priv = dev->dev_private;
10041 struct intel_crtc *crtc;
10042 struct intel_encoder *encoder;
10043 struct intel_crtc_config pipe_config;
10045 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10047 bool enabled = false;
10048 bool active = false;
10050 memset(&pipe_config, 0, sizeof(pipe_config));
10052 DRM_DEBUG_KMS("[CRTC:%d]\n",
10053 crtc->base.base.id);
10055 WARN(crtc->active && !crtc->base.enabled,
10056 "active crtc, but not enabled in sw tracking\n");
10058 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10060 if (encoder->base.crtc != &crtc->base)
10063 if (encoder->connectors_active)
10067 WARN(active != crtc->active,
10068 "crtc's computed active state doesn't match tracked active state "
10069 "(expected %i, found %i)\n", active, crtc->active);
10070 WARN(enabled != crtc->base.enabled,
10071 "crtc's computed enabled state doesn't match tracked enabled state "
10072 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10074 active = dev_priv->display.get_pipe_config(crtc,
10077 /* hw state is inconsistent with the pipe A quirk */
10078 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
10079 active = crtc->active;
10081 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10084 if (encoder->base.crtc != &crtc->base)
10086 if (encoder->get_hw_state(encoder, &pipe))
10087 encoder->get_config(encoder, &pipe_config);
10090 WARN(crtc->active != active,
10091 "crtc active state doesn't match with hw state "
10092 "(expected %i, found %i)\n", crtc->active, active);
10095 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10096 WARN(1, "pipe state doesn't match!\n");
10097 intel_dump_pipe_config(crtc, &pipe_config,
10099 intel_dump_pipe_config(crtc, &crtc->config,
10106 check_shared_dpll_state(struct drm_device *dev)
10108 struct drm_i915_private *dev_priv = dev->dev_private;
10109 struct intel_crtc *crtc;
10110 struct intel_dpll_hw_state dpll_hw_state;
10113 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10114 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10115 int enabled_crtcs = 0, active_crtcs = 0;
10118 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10120 DRM_DEBUG_KMS("%s\n", pll->name);
10122 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10124 WARN(pll->active > pll->refcount,
10125 "more active pll users than references: %i vs %i\n",
10126 pll->active, pll->refcount);
10127 WARN(pll->active && !pll->on,
10128 "pll in active use but not on in sw tracking\n");
10129 WARN(pll->on && !pll->active,
10130 "pll in on but not on in use in sw tracking\n");
10131 WARN(pll->on != active,
10132 "pll on state mismatch (expected %i, found %i)\n",
10135 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10137 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10139 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10142 WARN(pll->active != active_crtcs,
10143 "pll active crtcs mismatch (expected %i, found %i)\n",
10144 pll->active, active_crtcs);
10145 WARN(pll->refcount != enabled_crtcs,
10146 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10147 pll->refcount, enabled_crtcs);
10149 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10150 sizeof(dpll_hw_state)),
10151 "pll hw state mismatch\n");
10156 intel_modeset_check_state(struct drm_device *dev)
10158 check_connector_state(dev);
10159 check_encoder_state(dev);
10160 check_crtc_state(dev);
10161 check_shared_dpll_state(dev);
10164 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10168 * FDI already provided one idea for the dotclock.
10169 * Yell if the encoder disagrees.
10171 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10172 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10173 pipe_config->adjusted_mode.crtc_clock, dotclock);
10176 static int __intel_set_mode(struct drm_crtc *crtc,
10177 struct drm_display_mode *mode,
10178 int x, int y, struct drm_framebuffer *fb)
10180 struct drm_device *dev = crtc->dev;
10181 struct drm_i915_private *dev_priv = dev->dev_private;
10182 struct drm_display_mode *saved_mode;
10183 struct intel_crtc_config *pipe_config = NULL;
10184 struct intel_crtc *intel_crtc;
10185 unsigned disable_pipes, prepare_pipes, modeset_pipes;
10188 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10192 intel_modeset_affected_pipes(crtc, &modeset_pipes,
10193 &prepare_pipes, &disable_pipes);
10195 *saved_mode = crtc->mode;
10197 /* Hack: Because we don't (yet) support global modeset on multiple
10198 * crtcs, we don't keep track of the new mode for more than one crtc.
10199 * Hence simply check whether any bit is set in modeset_pipes in all the
10200 * pieces of code that are not yet converted to deal with mutliple crtcs
10201 * changing their mode at the same time. */
10202 if (modeset_pipes) {
10203 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10204 if (IS_ERR(pipe_config)) {
10205 ret = PTR_ERR(pipe_config);
10206 pipe_config = NULL;
10210 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10212 to_intel_crtc(crtc)->new_config = pipe_config;
10216 * See if the config requires any additional preparation, e.g.
10217 * to adjust global state with pipes off. We need to do this
10218 * here so we can get the modeset_pipe updated config for the new
10219 * mode set on this crtc. For other crtcs we need to use the
10220 * adjusted_mode bits in the crtc directly.
10222 if (IS_VALLEYVIEW(dev)) {
10223 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10225 /* may have added more to prepare_pipes than we should */
10226 prepare_pipes &= ~disable_pipes;
10229 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10230 intel_crtc_disable(&intel_crtc->base);
10232 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10233 if (intel_crtc->base.enabled)
10234 dev_priv->display.crtc_disable(&intel_crtc->base);
10237 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10238 * to set it here already despite that we pass it down the callchain.
10240 if (modeset_pipes) {
10241 crtc->mode = *mode;
10242 /* mode_set/enable/disable functions rely on a correct pipe
10244 to_intel_crtc(crtc)->config = *pipe_config;
10245 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10248 * Calculate and store various constants which
10249 * are later needed by vblank and swap-completion
10250 * timestamping. They are derived from true hwmode.
10252 drm_calc_timestamping_constants(crtc,
10253 &pipe_config->adjusted_mode);
10256 /* Only after disabling all output pipelines that will be changed can we
10257 * update the the output configuration. */
10258 intel_modeset_update_state(dev, prepare_pipes);
10260 if (dev_priv->display.modeset_global_resources)
10261 dev_priv->display.modeset_global_resources(dev);
10263 /* Set up the DPLL and any encoders state that needs to adjust or depend
10266 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10267 ret = intel_crtc_mode_set(&intel_crtc->base,
10273 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10274 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
10275 dev_priv->display.crtc_enable(&intel_crtc->base);
10277 /* FIXME: add subpixel order */
10279 if (ret && crtc->enabled)
10280 crtc->mode = *saved_mode;
10283 kfree(pipe_config);
10288 static int intel_set_mode(struct drm_crtc *crtc,
10289 struct drm_display_mode *mode,
10290 int x, int y, struct drm_framebuffer *fb)
10294 ret = __intel_set_mode(crtc, mode, x, y, fb);
10297 intel_modeset_check_state(crtc->dev);
10302 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10304 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10307 #undef for_each_intel_crtc_masked
10309 static void intel_set_config_free(struct intel_set_config *config)
10314 kfree(config->save_connector_encoders);
10315 kfree(config->save_encoder_crtcs);
10316 kfree(config->save_crtc_enabled);
10320 static int intel_set_config_save_state(struct drm_device *dev,
10321 struct intel_set_config *config)
10323 struct drm_crtc *crtc;
10324 struct drm_encoder *encoder;
10325 struct drm_connector *connector;
10328 config->save_crtc_enabled =
10329 kcalloc(dev->mode_config.num_crtc,
10330 sizeof(bool), GFP_KERNEL);
10331 if (!config->save_crtc_enabled)
10334 config->save_encoder_crtcs =
10335 kcalloc(dev->mode_config.num_encoder,
10336 sizeof(struct drm_crtc *), GFP_KERNEL);
10337 if (!config->save_encoder_crtcs)
10340 config->save_connector_encoders =
10341 kcalloc(dev->mode_config.num_connector,
10342 sizeof(struct drm_encoder *), GFP_KERNEL);
10343 if (!config->save_connector_encoders)
10346 /* Copy data. Note that driver private data is not affected.
10347 * Should anything bad happen only the expected state is
10348 * restored, not the drivers personal bookkeeping.
10351 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10352 config->save_crtc_enabled[count++] = crtc->enabled;
10356 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10357 config->save_encoder_crtcs[count++] = encoder->crtc;
10361 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10362 config->save_connector_encoders[count++] = connector->encoder;
10368 static void intel_set_config_restore_state(struct drm_device *dev,
10369 struct intel_set_config *config)
10371 struct intel_crtc *crtc;
10372 struct intel_encoder *encoder;
10373 struct intel_connector *connector;
10377 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
10378 crtc->new_enabled = config->save_crtc_enabled[count++];
10380 if (crtc->new_enabled)
10381 crtc->new_config = &crtc->config;
10383 crtc->new_config = NULL;
10387 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10388 encoder->new_crtc =
10389 to_intel_crtc(config->save_encoder_crtcs[count++]);
10393 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10394 connector->new_encoder =
10395 to_intel_encoder(config->save_connector_encoders[count++]);
10400 is_crtc_connector_off(struct drm_mode_set *set)
10404 if (set->num_connectors == 0)
10407 if (WARN_ON(set->connectors == NULL))
10410 for (i = 0; i < set->num_connectors; i++)
10411 if (set->connectors[i]->encoder &&
10412 set->connectors[i]->encoder->crtc == set->crtc &&
10413 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
10420 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
10421 struct intel_set_config *config)
10424 /* We should be able to check here if the fb has the same properties
10425 * and then just flip_or_move it */
10426 if (is_crtc_connector_off(set)) {
10427 config->mode_changed = true;
10428 } else if (set->crtc->primary->fb != set->fb) {
10429 /* If we have no fb then treat it as a full mode set */
10430 if (set->crtc->primary->fb == NULL) {
10431 struct intel_crtc *intel_crtc =
10432 to_intel_crtc(set->crtc);
10434 if (intel_crtc->active && i915.fastboot) {
10435 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
10436 config->fb_changed = true;
10438 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
10439 config->mode_changed = true;
10441 } else if (set->fb == NULL) {
10442 config->mode_changed = true;
10443 } else if (set->fb->pixel_format !=
10444 set->crtc->primary->fb->pixel_format) {
10445 config->mode_changed = true;
10447 config->fb_changed = true;
10451 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
10452 config->fb_changed = true;
10454 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
10455 DRM_DEBUG_KMS("modes are different, full mode set\n");
10456 drm_mode_debug_printmodeline(&set->crtc->mode);
10457 drm_mode_debug_printmodeline(set->mode);
10458 config->mode_changed = true;
10461 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
10462 set->crtc->base.id, config->mode_changed, config->fb_changed);
10466 intel_modeset_stage_output_state(struct drm_device *dev,
10467 struct drm_mode_set *set,
10468 struct intel_set_config *config)
10470 struct intel_connector *connector;
10471 struct intel_encoder *encoder;
10472 struct intel_crtc *crtc;
10475 /* The upper layers ensure that we either disable a crtc or have a list
10476 * of connectors. For paranoia, double-check this. */
10477 WARN_ON(!set->fb && (set->num_connectors != 0));
10478 WARN_ON(set->fb && (set->num_connectors == 0));
10480 list_for_each_entry(connector, &dev->mode_config.connector_list,
10482 /* Otherwise traverse passed in connector list and get encoders
10484 for (ro = 0; ro < set->num_connectors; ro++) {
10485 if (set->connectors[ro] == &connector->base) {
10486 connector->new_encoder = connector->encoder;
10491 /* If we disable the crtc, disable all its connectors. Also, if
10492 * the connector is on the changing crtc but not on the new
10493 * connector list, disable it. */
10494 if ((!set->fb || ro == set->num_connectors) &&
10495 connector->base.encoder &&
10496 connector->base.encoder->crtc == set->crtc) {
10497 connector->new_encoder = NULL;
10499 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
10500 connector->base.base.id,
10501 drm_get_connector_name(&connector->base));
10505 if (&connector->new_encoder->base != connector->base.encoder) {
10506 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
10507 config->mode_changed = true;
10510 /* connector->new_encoder is now updated for all connectors. */
10512 /* Update crtc of enabled connectors. */
10513 list_for_each_entry(connector, &dev->mode_config.connector_list,
10515 struct drm_crtc *new_crtc;
10517 if (!connector->new_encoder)
10520 new_crtc = connector->new_encoder->base.crtc;
10522 for (ro = 0; ro < set->num_connectors; ro++) {
10523 if (set->connectors[ro] == &connector->base)
10524 new_crtc = set->crtc;
10527 /* Make sure the new CRTC will work with the encoder */
10528 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
10532 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
10534 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
10535 connector->base.base.id,
10536 drm_get_connector_name(&connector->base),
10537 new_crtc->base.id);
10540 /* Check for any encoders that needs to be disabled. */
10541 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10543 int num_connectors = 0;
10544 list_for_each_entry(connector,
10545 &dev->mode_config.connector_list,
10547 if (connector->new_encoder == encoder) {
10548 WARN_ON(!connector->new_encoder->new_crtc);
10553 if (num_connectors == 0)
10554 encoder->new_crtc = NULL;
10555 else if (num_connectors > 1)
10558 /* Only now check for crtc changes so we don't miss encoders
10559 * that will be disabled. */
10560 if (&encoder->new_crtc->base != encoder->base.crtc) {
10561 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
10562 config->mode_changed = true;
10565 /* Now we've also updated encoder->new_crtc for all encoders. */
10567 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10569 crtc->new_enabled = false;
10571 list_for_each_entry(encoder,
10572 &dev->mode_config.encoder_list,
10574 if (encoder->new_crtc == crtc) {
10575 crtc->new_enabled = true;
10580 if (crtc->new_enabled != crtc->base.enabled) {
10581 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
10582 crtc->new_enabled ? "en" : "dis");
10583 config->mode_changed = true;
10586 if (crtc->new_enabled)
10587 crtc->new_config = &crtc->config;
10589 crtc->new_config = NULL;
10595 static void disable_crtc_nofb(struct intel_crtc *crtc)
10597 struct drm_device *dev = crtc->base.dev;
10598 struct intel_encoder *encoder;
10599 struct intel_connector *connector;
10601 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
10602 pipe_name(crtc->pipe));
10604 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10605 if (connector->new_encoder &&
10606 connector->new_encoder->new_crtc == crtc)
10607 connector->new_encoder = NULL;
10610 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10611 if (encoder->new_crtc == crtc)
10612 encoder->new_crtc = NULL;
10615 crtc->new_enabled = false;
10616 crtc->new_config = NULL;
10619 static int intel_crtc_set_config(struct drm_mode_set *set)
10621 struct drm_device *dev;
10622 struct drm_mode_set save_set;
10623 struct intel_set_config *config;
10627 BUG_ON(!set->crtc);
10628 BUG_ON(!set->crtc->helper_private);
10630 /* Enforce sane interface api - has been abused by the fb helper. */
10631 BUG_ON(!set->mode && set->fb);
10632 BUG_ON(set->fb && set->num_connectors == 0);
10635 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
10636 set->crtc->base.id, set->fb->base.id,
10637 (int)set->num_connectors, set->x, set->y);
10639 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
10642 dev = set->crtc->dev;
10645 config = kzalloc(sizeof(*config), GFP_KERNEL);
10649 ret = intel_set_config_save_state(dev, config);
10653 save_set.crtc = set->crtc;
10654 save_set.mode = &set->crtc->mode;
10655 save_set.x = set->crtc->x;
10656 save_set.y = set->crtc->y;
10657 save_set.fb = set->crtc->primary->fb;
10659 /* Compute whether we need a full modeset, only an fb base update or no
10660 * change at all. In the future we might also check whether only the
10661 * mode changed, e.g. for LVDS where we only change the panel fitter in
10663 intel_set_config_compute_mode_changes(set, config);
10665 ret = intel_modeset_stage_output_state(dev, set, config);
10669 if (config->mode_changed) {
10670 ret = intel_set_mode(set->crtc, set->mode,
10671 set->x, set->y, set->fb);
10672 } else if (config->fb_changed) {
10673 intel_crtc_wait_for_pending_flips(set->crtc);
10675 ret = intel_pipe_set_base(set->crtc,
10676 set->x, set->y, set->fb);
10678 * In the fastboot case this may be our only check of the
10679 * state after boot. It would be better to only do it on
10680 * the first update, but we don't have a nice way of doing that
10681 * (and really, set_config isn't used much for high freq page
10682 * flipping, so increasing its cost here shouldn't be a big
10685 if (i915.fastboot && ret == 0)
10686 intel_modeset_check_state(set->crtc->dev);
10690 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
10691 set->crtc->base.id, ret);
10693 intel_set_config_restore_state(dev, config);
10696 * HACK: if the pipe was on, but we didn't have a framebuffer,
10697 * force the pipe off to avoid oopsing in the modeset code
10698 * due to fb==NULL. This should only happen during boot since
10699 * we don't yet reconstruct the FB from the hardware state.
10701 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
10702 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
10704 /* Try to restore the config */
10705 if (config->mode_changed &&
10706 intel_set_mode(save_set.crtc, save_set.mode,
10707 save_set.x, save_set.y, save_set.fb))
10708 DRM_ERROR("failed to restore config after modeset failure\n");
10712 intel_set_config_free(config);
10716 static const struct drm_crtc_funcs intel_crtc_funcs = {
10717 .cursor_set = intel_crtc_cursor_set,
10718 .cursor_move = intel_crtc_cursor_move,
10719 .gamma_set = intel_crtc_gamma_set,
10720 .set_config = intel_crtc_set_config,
10721 .destroy = intel_crtc_destroy,
10722 .page_flip = intel_crtc_page_flip,
10725 static void intel_cpu_pll_init(struct drm_device *dev)
10728 intel_ddi_pll_init(dev);
10731 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
10732 struct intel_shared_dpll *pll,
10733 struct intel_dpll_hw_state *hw_state)
10737 val = I915_READ(PCH_DPLL(pll->id));
10738 hw_state->dpll = val;
10739 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
10740 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
10742 return val & DPLL_VCO_ENABLE;
10745 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
10746 struct intel_shared_dpll *pll)
10748 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
10749 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
10752 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
10753 struct intel_shared_dpll *pll)
10755 /* PCH refclock must be enabled first */
10756 ibx_assert_pch_refclk_enabled(dev_priv);
10758 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10760 /* Wait for the clocks to stabilize. */
10761 POSTING_READ(PCH_DPLL(pll->id));
10764 /* The pixel multiplier can only be updated once the
10765 * DPLL is enabled and the clocks are stable.
10767 * So write it again.
10769 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10770 POSTING_READ(PCH_DPLL(pll->id));
10774 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
10775 struct intel_shared_dpll *pll)
10777 struct drm_device *dev = dev_priv->dev;
10778 struct intel_crtc *crtc;
10780 /* Make sure no transcoder isn't still depending on us. */
10781 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
10782 if (intel_crtc_to_shared_dpll(crtc) == pll)
10783 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
10786 I915_WRITE(PCH_DPLL(pll->id), 0);
10787 POSTING_READ(PCH_DPLL(pll->id));
10791 static char *ibx_pch_dpll_names[] = {
10796 static void ibx_pch_dpll_init(struct drm_device *dev)
10798 struct drm_i915_private *dev_priv = dev->dev_private;
10801 dev_priv->num_shared_dpll = 2;
10803 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10804 dev_priv->shared_dplls[i].id = i;
10805 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
10806 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
10807 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
10808 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
10809 dev_priv->shared_dplls[i].get_hw_state =
10810 ibx_pch_dpll_get_hw_state;
10814 static void intel_shared_dpll_init(struct drm_device *dev)
10816 struct drm_i915_private *dev_priv = dev->dev_private;
10818 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
10819 ibx_pch_dpll_init(dev);
10821 dev_priv->num_shared_dpll = 0;
10823 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
10826 static void intel_crtc_init(struct drm_device *dev, int pipe)
10828 struct drm_i915_private *dev_priv = dev->dev_private;
10829 struct intel_crtc *intel_crtc;
10832 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
10833 if (intel_crtc == NULL)
10836 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
10838 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
10839 for (i = 0; i < 256; i++) {
10840 intel_crtc->lut_r[i] = i;
10841 intel_crtc->lut_g[i] = i;
10842 intel_crtc->lut_b[i] = i;
10846 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
10847 * is hooked to plane B. Hence we want plane A feeding pipe B.
10849 intel_crtc->pipe = pipe;
10850 intel_crtc->plane = pipe;
10851 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
10852 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
10853 intel_crtc->plane = !pipe;
10856 init_waitqueue_head(&intel_crtc->vbl_wait);
10858 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
10859 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
10860 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
10861 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
10863 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
10866 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
10868 struct drm_encoder *encoder = connector->base.encoder;
10870 WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex));
10873 return INVALID_PIPE;
10875 return to_intel_crtc(encoder->crtc)->pipe;
10878 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
10879 struct drm_file *file)
10881 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
10882 struct drm_mode_object *drmmode_obj;
10883 struct intel_crtc *crtc;
10885 if (!drm_core_check_feature(dev, DRIVER_MODESET))
10888 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
10889 DRM_MODE_OBJECT_CRTC);
10891 if (!drmmode_obj) {
10892 DRM_ERROR("no such CRTC id\n");
10896 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
10897 pipe_from_crtc_id->pipe = crtc->pipe;
10902 static int intel_encoder_clones(struct intel_encoder *encoder)
10904 struct drm_device *dev = encoder->base.dev;
10905 struct intel_encoder *source_encoder;
10906 int index_mask = 0;
10909 list_for_each_entry(source_encoder,
10910 &dev->mode_config.encoder_list, base.head) {
10911 if (encoders_cloneable(encoder, source_encoder))
10912 index_mask |= (1 << entry);
10920 static bool has_edp_a(struct drm_device *dev)
10922 struct drm_i915_private *dev_priv = dev->dev_private;
10924 if (!IS_MOBILE(dev))
10927 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
10930 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
10936 const char *intel_output_name(int output)
10938 static const char *names[] = {
10939 [INTEL_OUTPUT_UNUSED] = "Unused",
10940 [INTEL_OUTPUT_ANALOG] = "Analog",
10941 [INTEL_OUTPUT_DVO] = "DVO",
10942 [INTEL_OUTPUT_SDVO] = "SDVO",
10943 [INTEL_OUTPUT_LVDS] = "LVDS",
10944 [INTEL_OUTPUT_TVOUT] = "TV",
10945 [INTEL_OUTPUT_HDMI] = "HDMI",
10946 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
10947 [INTEL_OUTPUT_EDP] = "eDP",
10948 [INTEL_OUTPUT_DSI] = "DSI",
10949 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
10952 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
10955 return names[output];
10958 static void intel_setup_outputs(struct drm_device *dev)
10960 struct drm_i915_private *dev_priv = dev->dev_private;
10961 struct intel_encoder *encoder;
10962 bool dpd_is_edp = false;
10964 intel_lvds_init(dev);
10966 if (!IS_ULT(dev) && !IS_CHERRYVIEW(dev))
10967 intel_crt_init(dev);
10969 if (HAS_DDI(dev)) {
10972 /* Haswell uses DDI functions to detect digital outputs */
10973 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
10974 /* DDI A only supports eDP */
10976 intel_ddi_init(dev, PORT_A);
10978 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
10980 found = I915_READ(SFUSE_STRAP);
10982 if (found & SFUSE_STRAP_DDIB_DETECTED)
10983 intel_ddi_init(dev, PORT_B);
10984 if (found & SFUSE_STRAP_DDIC_DETECTED)
10985 intel_ddi_init(dev, PORT_C);
10986 if (found & SFUSE_STRAP_DDID_DETECTED)
10987 intel_ddi_init(dev, PORT_D);
10988 } else if (HAS_PCH_SPLIT(dev)) {
10990 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
10992 if (has_edp_a(dev))
10993 intel_dp_init(dev, DP_A, PORT_A);
10995 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
10996 /* PCH SDVOB multiplex with HDMIB */
10997 found = intel_sdvo_init(dev, PCH_SDVOB, true);
10999 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
11000 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
11001 intel_dp_init(dev, PCH_DP_B, PORT_B);
11004 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
11005 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
11007 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
11008 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
11010 if (I915_READ(PCH_DP_C) & DP_DETECTED)
11011 intel_dp_init(dev, PCH_DP_C, PORT_C);
11013 if (I915_READ(PCH_DP_D) & DP_DETECTED)
11014 intel_dp_init(dev, PCH_DP_D, PORT_D);
11015 } else if (IS_VALLEYVIEW(dev)) {
11016 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
11017 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
11019 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
11020 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
11023 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
11024 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
11026 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
11027 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
11030 intel_dsi_init(dev);
11031 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
11032 bool found = false;
11034 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
11035 DRM_DEBUG_KMS("probing SDVOB\n");
11036 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
11037 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
11038 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
11039 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
11042 if (!found && SUPPORTS_INTEGRATED_DP(dev))
11043 intel_dp_init(dev, DP_B, PORT_B);
11046 /* Before G4X SDVOC doesn't have its own detect register */
11048 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
11049 DRM_DEBUG_KMS("probing SDVOC\n");
11050 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
11053 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
11055 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
11056 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
11057 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
11059 if (SUPPORTS_INTEGRATED_DP(dev))
11060 intel_dp_init(dev, DP_C, PORT_C);
11063 if (SUPPORTS_INTEGRATED_DP(dev) &&
11064 (I915_READ(DP_D) & DP_DETECTED))
11065 intel_dp_init(dev, DP_D, PORT_D);
11066 } else if (IS_GEN2(dev))
11067 intel_dvo_init(dev);
11069 if (SUPPORTS_TV(dev))
11070 intel_tv_init(dev);
11072 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
11073 encoder->base.possible_crtcs = encoder->crtc_mask;
11074 encoder->base.possible_clones =
11075 intel_encoder_clones(encoder);
11078 intel_init_pch_refclk(dev);
11080 drm_helper_move_panel_connectors_to_head(dev);
11083 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
11085 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11087 drm_framebuffer_cleanup(fb);
11088 WARN_ON(!intel_fb->obj->framebuffer_references--);
11089 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
11093 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
11094 struct drm_file *file,
11095 unsigned int *handle)
11097 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11098 struct drm_i915_gem_object *obj = intel_fb->obj;
11100 return drm_gem_handle_create(file, &obj->base, handle);
11103 static const struct drm_framebuffer_funcs intel_fb_funcs = {
11104 .destroy = intel_user_framebuffer_destroy,
11105 .create_handle = intel_user_framebuffer_create_handle,
11108 static int intel_framebuffer_init(struct drm_device *dev,
11109 struct intel_framebuffer *intel_fb,
11110 struct drm_mode_fb_cmd2 *mode_cmd,
11111 struct drm_i915_gem_object *obj)
11113 int aligned_height;
11117 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
11119 if (obj->tiling_mode == I915_TILING_Y) {
11120 DRM_DEBUG("hardware does not support tiling Y\n");
11124 if (mode_cmd->pitches[0] & 63) {
11125 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
11126 mode_cmd->pitches[0]);
11130 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
11131 pitch_limit = 32*1024;
11132 } else if (INTEL_INFO(dev)->gen >= 4) {
11133 if (obj->tiling_mode)
11134 pitch_limit = 16*1024;
11136 pitch_limit = 32*1024;
11137 } else if (INTEL_INFO(dev)->gen >= 3) {
11138 if (obj->tiling_mode)
11139 pitch_limit = 8*1024;
11141 pitch_limit = 16*1024;
11143 /* XXX DSPC is limited to 4k tiled */
11144 pitch_limit = 8*1024;
11146 if (mode_cmd->pitches[0] > pitch_limit) {
11147 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
11148 obj->tiling_mode ? "tiled" : "linear",
11149 mode_cmd->pitches[0], pitch_limit);
11153 if (obj->tiling_mode != I915_TILING_NONE &&
11154 mode_cmd->pitches[0] != obj->stride) {
11155 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
11156 mode_cmd->pitches[0], obj->stride);
11160 /* Reject formats not supported by any plane early. */
11161 switch (mode_cmd->pixel_format) {
11162 case DRM_FORMAT_C8:
11163 case DRM_FORMAT_RGB565:
11164 case DRM_FORMAT_XRGB8888:
11165 case DRM_FORMAT_ARGB8888:
11167 case DRM_FORMAT_XRGB1555:
11168 case DRM_FORMAT_ARGB1555:
11169 if (INTEL_INFO(dev)->gen > 3) {
11170 DRM_DEBUG("unsupported pixel format: %s\n",
11171 drm_get_format_name(mode_cmd->pixel_format));
11175 case DRM_FORMAT_XBGR8888:
11176 case DRM_FORMAT_ABGR8888:
11177 case DRM_FORMAT_XRGB2101010:
11178 case DRM_FORMAT_ARGB2101010:
11179 case DRM_FORMAT_XBGR2101010:
11180 case DRM_FORMAT_ABGR2101010:
11181 if (INTEL_INFO(dev)->gen < 4) {
11182 DRM_DEBUG("unsupported pixel format: %s\n",
11183 drm_get_format_name(mode_cmd->pixel_format));
11187 case DRM_FORMAT_YUYV:
11188 case DRM_FORMAT_UYVY:
11189 case DRM_FORMAT_YVYU:
11190 case DRM_FORMAT_VYUY:
11191 if (INTEL_INFO(dev)->gen < 5) {
11192 DRM_DEBUG("unsupported pixel format: %s\n",
11193 drm_get_format_name(mode_cmd->pixel_format));
11198 DRM_DEBUG("unsupported pixel format: %s\n",
11199 drm_get_format_name(mode_cmd->pixel_format));
11203 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
11204 if (mode_cmd->offsets[0] != 0)
11207 aligned_height = intel_align_height(dev, mode_cmd->height,
11209 /* FIXME drm helper for size checks (especially planar formats)? */
11210 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
11213 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
11214 intel_fb->obj = obj;
11215 intel_fb->obj->framebuffer_references++;
11217 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
11219 DRM_ERROR("framebuffer init failed %d\n", ret);
11226 static struct drm_framebuffer *
11227 intel_user_framebuffer_create(struct drm_device *dev,
11228 struct drm_file *filp,
11229 struct drm_mode_fb_cmd2 *mode_cmd)
11231 struct drm_i915_gem_object *obj;
11233 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
11234 mode_cmd->handles[0]));
11235 if (&obj->base == NULL)
11236 return ERR_PTR(-ENOENT);
11238 return intel_framebuffer_create(dev, mode_cmd, obj);
11241 #ifndef CONFIG_DRM_I915_FBDEV
11242 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
11247 static const struct drm_mode_config_funcs intel_mode_funcs = {
11248 .fb_create = intel_user_framebuffer_create,
11249 .output_poll_changed = intel_fbdev_output_poll_changed,
11252 /* Set up chip specific display functions */
11253 static void intel_init_display(struct drm_device *dev)
11255 struct drm_i915_private *dev_priv = dev->dev_private;
11257 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
11258 dev_priv->display.find_dpll = g4x_find_best_dpll;
11259 else if (IS_CHERRYVIEW(dev))
11260 dev_priv->display.find_dpll = chv_find_best_dpll;
11261 else if (IS_VALLEYVIEW(dev))
11262 dev_priv->display.find_dpll = vlv_find_best_dpll;
11263 else if (IS_PINEVIEW(dev))
11264 dev_priv->display.find_dpll = pnv_find_best_dpll;
11266 dev_priv->display.find_dpll = i9xx_find_best_dpll;
11268 if (HAS_DDI(dev)) {
11269 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
11270 dev_priv->display.get_plane_config = ironlake_get_plane_config;
11271 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
11272 dev_priv->display.crtc_enable = haswell_crtc_enable;
11273 dev_priv->display.crtc_disable = haswell_crtc_disable;
11274 dev_priv->display.off = haswell_crtc_off;
11275 dev_priv->display.update_primary_plane =
11276 ironlake_update_primary_plane;
11277 } else if (HAS_PCH_SPLIT(dev)) {
11278 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
11279 dev_priv->display.get_plane_config = ironlake_get_plane_config;
11280 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
11281 dev_priv->display.crtc_enable = ironlake_crtc_enable;
11282 dev_priv->display.crtc_disable = ironlake_crtc_disable;
11283 dev_priv->display.off = ironlake_crtc_off;
11284 dev_priv->display.update_primary_plane =
11285 ironlake_update_primary_plane;
11286 } else if (IS_VALLEYVIEW(dev)) {
11287 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11288 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11289 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11290 dev_priv->display.crtc_enable = valleyview_crtc_enable;
11291 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11292 dev_priv->display.off = i9xx_crtc_off;
11293 dev_priv->display.update_primary_plane =
11294 i9xx_update_primary_plane;
11296 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11297 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11298 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11299 dev_priv->display.crtc_enable = i9xx_crtc_enable;
11300 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11301 dev_priv->display.off = i9xx_crtc_off;
11302 dev_priv->display.update_primary_plane =
11303 i9xx_update_primary_plane;
11306 /* Returns the core display clock speed */
11307 if (IS_VALLEYVIEW(dev))
11308 dev_priv->display.get_display_clock_speed =
11309 valleyview_get_display_clock_speed;
11310 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
11311 dev_priv->display.get_display_clock_speed =
11312 i945_get_display_clock_speed;
11313 else if (IS_I915G(dev))
11314 dev_priv->display.get_display_clock_speed =
11315 i915_get_display_clock_speed;
11316 else if (IS_I945GM(dev) || IS_845G(dev))
11317 dev_priv->display.get_display_clock_speed =
11318 i9xx_misc_get_display_clock_speed;
11319 else if (IS_PINEVIEW(dev))
11320 dev_priv->display.get_display_clock_speed =
11321 pnv_get_display_clock_speed;
11322 else if (IS_I915GM(dev))
11323 dev_priv->display.get_display_clock_speed =
11324 i915gm_get_display_clock_speed;
11325 else if (IS_I865G(dev))
11326 dev_priv->display.get_display_clock_speed =
11327 i865_get_display_clock_speed;
11328 else if (IS_I85X(dev))
11329 dev_priv->display.get_display_clock_speed =
11330 i855_get_display_clock_speed;
11331 else /* 852, 830 */
11332 dev_priv->display.get_display_clock_speed =
11333 i830_get_display_clock_speed;
11335 if (HAS_PCH_SPLIT(dev)) {
11336 if (IS_GEN5(dev)) {
11337 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
11338 dev_priv->display.write_eld = ironlake_write_eld;
11339 } else if (IS_GEN6(dev)) {
11340 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
11341 dev_priv->display.write_eld = ironlake_write_eld;
11342 dev_priv->display.modeset_global_resources =
11343 snb_modeset_global_resources;
11344 } else if (IS_IVYBRIDGE(dev)) {
11345 /* FIXME: detect B0+ stepping and use auto training */
11346 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
11347 dev_priv->display.write_eld = ironlake_write_eld;
11348 dev_priv->display.modeset_global_resources =
11349 ivb_modeset_global_resources;
11350 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
11351 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
11352 dev_priv->display.write_eld = haswell_write_eld;
11353 dev_priv->display.modeset_global_resources =
11354 haswell_modeset_global_resources;
11356 } else if (IS_G4X(dev)) {
11357 dev_priv->display.write_eld = g4x_write_eld;
11358 } else if (IS_VALLEYVIEW(dev)) {
11359 dev_priv->display.modeset_global_resources =
11360 valleyview_modeset_global_resources;
11361 dev_priv->display.write_eld = ironlake_write_eld;
11364 /* Default just returns -ENODEV to indicate unsupported */
11365 dev_priv->display.queue_flip = intel_default_queue_flip;
11367 switch (INTEL_INFO(dev)->gen) {
11369 dev_priv->display.queue_flip = intel_gen2_queue_flip;
11373 dev_priv->display.queue_flip = intel_gen3_queue_flip;
11378 dev_priv->display.queue_flip = intel_gen4_queue_flip;
11382 dev_priv->display.queue_flip = intel_gen6_queue_flip;
11385 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
11386 dev_priv->display.queue_flip = intel_gen7_queue_flip;
11390 intel_panel_init_backlight_funcs(dev);
11394 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
11395 * resume, or other times. This quirk makes sure that's the case for
11396 * affected systems.
11398 static void quirk_pipea_force(struct drm_device *dev)
11400 struct drm_i915_private *dev_priv = dev->dev_private;
11402 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
11403 DRM_INFO("applying pipe a force quirk\n");
11407 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
11409 static void quirk_ssc_force_disable(struct drm_device *dev)
11411 struct drm_i915_private *dev_priv = dev->dev_private;
11412 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
11413 DRM_INFO("applying lvds SSC disable quirk\n");
11417 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
11420 static void quirk_invert_brightness(struct drm_device *dev)
11422 struct drm_i915_private *dev_priv = dev->dev_private;
11423 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
11424 DRM_INFO("applying inverted panel brightness quirk\n");
11427 struct intel_quirk {
11429 int subsystem_vendor;
11430 int subsystem_device;
11431 void (*hook)(struct drm_device *dev);
11434 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
11435 struct intel_dmi_quirk {
11436 void (*hook)(struct drm_device *dev);
11437 const struct dmi_system_id (*dmi_id_list)[];
11440 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
11442 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
11446 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
11448 .dmi_id_list = &(const struct dmi_system_id[]) {
11450 .callback = intel_dmi_reverse_brightness,
11451 .ident = "NCR Corporation",
11452 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
11453 DMI_MATCH(DMI_PRODUCT_NAME, ""),
11456 { } /* terminating entry */
11458 .hook = quirk_invert_brightness,
11462 static struct intel_quirk intel_quirks[] = {
11463 /* HP Mini needs pipe A force quirk (LP: #322104) */
11464 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
11466 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
11467 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
11469 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
11470 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
11472 /* 830 needs to leave pipe A & dpll A up */
11473 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
11475 /* Lenovo U160 cannot use SSC on LVDS */
11476 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
11478 /* Sony Vaio Y cannot use SSC on LVDS */
11479 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
11481 /* Acer Aspire 5734Z must invert backlight brightness */
11482 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
11484 /* Acer/eMachines G725 */
11485 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
11487 /* Acer/eMachines e725 */
11488 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
11490 /* Acer/Packard Bell NCL20 */
11491 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
11493 /* Acer Aspire 4736Z */
11494 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
11496 /* Acer Aspire 5336 */
11497 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
11500 static void intel_init_quirks(struct drm_device *dev)
11502 struct pci_dev *d = dev->pdev;
11505 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
11506 struct intel_quirk *q = &intel_quirks[i];
11508 if (d->device == q->device &&
11509 (d->subsystem_vendor == q->subsystem_vendor ||
11510 q->subsystem_vendor == PCI_ANY_ID) &&
11511 (d->subsystem_device == q->subsystem_device ||
11512 q->subsystem_device == PCI_ANY_ID))
11515 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
11516 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
11517 intel_dmi_quirks[i].hook(dev);
11521 /* Disable the VGA plane that we never use */
11522 static void i915_disable_vga(struct drm_device *dev)
11524 struct drm_i915_private *dev_priv = dev->dev_private;
11526 u32 vga_reg = i915_vgacntrl_reg(dev);
11528 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
11529 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
11530 outb(SR01, VGA_SR_INDEX);
11531 sr1 = inb(VGA_SR_DATA);
11532 outb(sr1 | 1<<5, VGA_SR_DATA);
11533 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
11536 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
11537 POSTING_READ(vga_reg);
11540 void intel_modeset_init_hw(struct drm_device *dev)
11542 intel_prepare_ddi(dev);
11544 intel_init_clock_gating(dev);
11546 intel_reset_dpio(dev);
11548 intel_enable_gt_powersave(dev);
11551 void intel_modeset_suspend_hw(struct drm_device *dev)
11553 intel_suspend_hw(dev);
11556 void intel_modeset_init(struct drm_device *dev)
11558 struct drm_i915_private *dev_priv = dev->dev_private;
11561 struct intel_crtc *crtc;
11563 drm_mode_config_init(dev);
11565 dev->mode_config.min_width = 0;
11566 dev->mode_config.min_height = 0;
11568 dev->mode_config.preferred_depth = 24;
11569 dev->mode_config.prefer_shadow = 1;
11571 dev->mode_config.funcs = &intel_mode_funcs;
11573 intel_init_quirks(dev);
11575 intel_init_pm(dev);
11577 if (INTEL_INFO(dev)->num_pipes == 0)
11580 intel_init_display(dev);
11582 if (IS_GEN2(dev)) {
11583 dev->mode_config.max_width = 2048;
11584 dev->mode_config.max_height = 2048;
11585 } else if (IS_GEN3(dev)) {
11586 dev->mode_config.max_width = 4096;
11587 dev->mode_config.max_height = 4096;
11589 dev->mode_config.max_width = 8192;
11590 dev->mode_config.max_height = 8192;
11593 if (IS_GEN2(dev)) {
11594 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
11595 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
11597 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
11598 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
11601 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
11603 DRM_DEBUG_KMS("%d display pipe%s available.\n",
11604 INTEL_INFO(dev)->num_pipes,
11605 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
11607 for_each_pipe(pipe) {
11608 intel_crtc_init(dev, pipe);
11609 for_each_sprite(pipe, sprite) {
11610 ret = intel_plane_init(dev, pipe, sprite);
11612 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
11613 pipe_name(pipe), sprite_name(pipe, sprite), ret);
11617 intel_init_dpio(dev);
11618 intel_reset_dpio(dev);
11620 intel_cpu_pll_init(dev);
11621 intel_shared_dpll_init(dev);
11623 /* Just disable it once at startup */
11624 i915_disable_vga(dev);
11625 intel_setup_outputs(dev);
11627 /* Just in case the BIOS is doing something questionable. */
11628 intel_disable_fbc(dev);
11630 mutex_lock(&dev->mode_config.mutex);
11631 intel_modeset_setup_hw_state(dev, false);
11632 mutex_unlock(&dev->mode_config.mutex);
11634 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11640 * Note that reserving the BIOS fb up front prevents us
11641 * from stuffing other stolen allocations like the ring
11642 * on top. This prevents some ugliness at boot time, and
11643 * can even allow for smooth boot transitions if the BIOS
11644 * fb is large enough for the active pipe configuration.
11646 if (dev_priv->display.get_plane_config) {
11647 dev_priv->display.get_plane_config(crtc,
11648 &crtc->plane_config);
11650 * If the fb is shared between multiple heads, we'll
11651 * just get the first one.
11653 intel_find_plane_obj(crtc, &crtc->plane_config);
11659 intel_connector_break_all_links(struct intel_connector *connector)
11661 connector->base.dpms = DRM_MODE_DPMS_OFF;
11662 connector->base.encoder = NULL;
11663 connector->encoder->connectors_active = false;
11664 connector->encoder->base.crtc = NULL;
11667 static void intel_enable_pipe_a(struct drm_device *dev)
11669 struct intel_connector *connector;
11670 struct drm_connector *crt = NULL;
11671 struct intel_load_detect_pipe load_detect_temp;
11673 /* We can't just switch on the pipe A, we need to set things up with a
11674 * proper mode and output configuration. As a gross hack, enable pipe A
11675 * by enabling the load detect pipe once. */
11676 list_for_each_entry(connector,
11677 &dev->mode_config.connector_list,
11679 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
11680 crt = &connector->base;
11688 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
11689 intel_release_load_detect_pipe(crt, &load_detect_temp);
11695 intel_check_plane_mapping(struct intel_crtc *crtc)
11697 struct drm_device *dev = crtc->base.dev;
11698 struct drm_i915_private *dev_priv = dev->dev_private;
11701 if (INTEL_INFO(dev)->num_pipes == 1)
11704 reg = DSPCNTR(!crtc->plane);
11705 val = I915_READ(reg);
11707 if ((val & DISPLAY_PLANE_ENABLE) &&
11708 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
11714 static void intel_sanitize_crtc(struct intel_crtc *crtc)
11716 struct drm_device *dev = crtc->base.dev;
11717 struct drm_i915_private *dev_priv = dev->dev_private;
11720 /* Clear any frame start delays used for debugging left by the BIOS */
11721 reg = PIPECONF(crtc->config.cpu_transcoder);
11722 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
11724 /* We need to sanitize the plane -> pipe mapping first because this will
11725 * disable the crtc (and hence change the state) if it is wrong. Note
11726 * that gen4+ has a fixed plane -> pipe mapping. */
11727 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
11728 struct intel_connector *connector;
11731 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
11732 crtc->base.base.id);
11734 /* Pipe has the wrong plane attached and the plane is active.
11735 * Temporarily change the plane mapping and disable everything
11737 plane = crtc->plane;
11738 crtc->plane = !plane;
11739 dev_priv->display.crtc_disable(&crtc->base);
11740 crtc->plane = plane;
11742 /* ... and break all links. */
11743 list_for_each_entry(connector, &dev->mode_config.connector_list,
11745 if (connector->encoder->base.crtc != &crtc->base)
11748 intel_connector_break_all_links(connector);
11751 WARN_ON(crtc->active);
11752 crtc->base.enabled = false;
11755 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
11756 crtc->pipe == PIPE_A && !crtc->active) {
11757 /* BIOS forgot to enable pipe A, this mostly happens after
11758 * resume. Force-enable the pipe to fix this, the update_dpms
11759 * call below we restore the pipe to the right state, but leave
11760 * the required bits on. */
11761 intel_enable_pipe_a(dev);
11764 /* Adjust the state of the output pipe according to whether we
11765 * have active connectors/encoders. */
11766 intel_crtc_update_dpms(&crtc->base);
11768 if (crtc->active != crtc->base.enabled) {
11769 struct intel_encoder *encoder;
11771 /* This can happen either due to bugs in the get_hw_state
11772 * functions or because the pipe is force-enabled due to the
11774 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
11775 crtc->base.base.id,
11776 crtc->base.enabled ? "enabled" : "disabled",
11777 crtc->active ? "enabled" : "disabled");
11779 crtc->base.enabled = crtc->active;
11781 /* Because we only establish the connector -> encoder ->
11782 * crtc links if something is active, this means the
11783 * crtc is now deactivated. Break the links. connector
11784 * -> encoder links are only establish when things are
11785 * actually up, hence no need to break them. */
11786 WARN_ON(crtc->active);
11788 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
11789 WARN_ON(encoder->connectors_active);
11790 encoder->base.crtc = NULL;
11793 if (crtc->active) {
11795 * We start out with underrun reporting disabled to avoid races.
11796 * For correct bookkeeping mark this on active crtcs.
11798 * No protection against concurrent access is required - at
11799 * worst a fifo underrun happens which also sets this to false.
11801 crtc->cpu_fifo_underrun_disabled = true;
11802 crtc->pch_fifo_underrun_disabled = true;
11806 static void intel_sanitize_encoder(struct intel_encoder *encoder)
11808 struct intel_connector *connector;
11809 struct drm_device *dev = encoder->base.dev;
11811 /* We need to check both for a crtc link (meaning that the
11812 * encoder is active and trying to read from a pipe) and the
11813 * pipe itself being active. */
11814 bool has_active_crtc = encoder->base.crtc &&
11815 to_intel_crtc(encoder->base.crtc)->active;
11817 if (encoder->connectors_active && !has_active_crtc) {
11818 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
11819 encoder->base.base.id,
11820 drm_get_encoder_name(&encoder->base));
11822 /* Connector is active, but has no active pipe. This is
11823 * fallout from our resume register restoring. Disable
11824 * the encoder manually again. */
11825 if (encoder->base.crtc) {
11826 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
11827 encoder->base.base.id,
11828 drm_get_encoder_name(&encoder->base));
11829 encoder->disable(encoder);
11832 /* Inconsistent output/port/pipe state happens presumably due to
11833 * a bug in one of the get_hw_state functions. Or someplace else
11834 * in our code, like the register restore mess on resume. Clamp
11835 * things to off as a safer default. */
11836 list_for_each_entry(connector,
11837 &dev->mode_config.connector_list,
11839 if (connector->encoder != encoder)
11842 intel_connector_break_all_links(connector);
11845 /* Enabled encoders without active connectors will be fixed in
11846 * the crtc fixup. */
11849 void i915_redisable_vga_power_on(struct drm_device *dev)
11851 struct drm_i915_private *dev_priv = dev->dev_private;
11852 u32 vga_reg = i915_vgacntrl_reg(dev);
11854 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
11855 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
11856 i915_disable_vga(dev);
11860 void i915_redisable_vga(struct drm_device *dev)
11862 struct drm_i915_private *dev_priv = dev->dev_private;
11864 /* This function can be called both from intel_modeset_setup_hw_state or
11865 * at a very early point in our resume sequence, where the power well
11866 * structures are not yet restored. Since this function is at a very
11867 * paranoid "someone might have enabled VGA while we were not looking"
11868 * level, just check if the power well is enabled instead of trying to
11869 * follow the "don't touch the power well if we don't need it" policy
11870 * the rest of the driver uses. */
11871 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
11874 i915_redisable_vga_power_on(dev);
11877 static bool primary_get_hw_state(struct intel_crtc *crtc)
11879 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
11884 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
11887 static void intel_modeset_readout_hw_state(struct drm_device *dev)
11889 struct drm_i915_private *dev_priv = dev->dev_private;
11891 struct intel_crtc *crtc;
11892 struct intel_encoder *encoder;
11893 struct intel_connector *connector;
11896 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11898 memset(&crtc->config, 0, sizeof(crtc->config));
11900 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
11902 crtc->active = dev_priv->display.get_pipe_config(crtc,
11905 crtc->base.enabled = crtc->active;
11906 crtc->primary_enabled = primary_get_hw_state(crtc);
11908 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
11909 crtc->base.base.id,
11910 crtc->active ? "enabled" : "disabled");
11913 /* FIXME: Smash this into the new shared dpll infrastructure. */
11915 intel_ddi_setup_hw_pll_state(dev);
11917 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11918 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11920 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
11922 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11924 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11927 pll->refcount = pll->active;
11929 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
11930 pll->name, pll->refcount, pll->on);
11933 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11937 if (encoder->get_hw_state(encoder, &pipe)) {
11938 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11939 encoder->base.crtc = &crtc->base;
11940 encoder->get_config(encoder, &crtc->config);
11942 encoder->base.crtc = NULL;
11945 encoder->connectors_active = false;
11946 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
11947 encoder->base.base.id,
11948 drm_get_encoder_name(&encoder->base),
11949 encoder->base.crtc ? "enabled" : "disabled",
11953 list_for_each_entry(connector, &dev->mode_config.connector_list,
11955 if (connector->get_hw_state(connector)) {
11956 connector->base.dpms = DRM_MODE_DPMS_ON;
11957 connector->encoder->connectors_active = true;
11958 connector->base.encoder = &connector->encoder->base;
11960 connector->base.dpms = DRM_MODE_DPMS_OFF;
11961 connector->base.encoder = NULL;
11963 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
11964 connector->base.base.id,
11965 drm_get_connector_name(&connector->base),
11966 connector->base.encoder ? "enabled" : "disabled");
11970 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
11971 * and i915 state tracking structures. */
11972 void intel_modeset_setup_hw_state(struct drm_device *dev,
11973 bool force_restore)
11975 struct drm_i915_private *dev_priv = dev->dev_private;
11977 struct intel_crtc *crtc;
11978 struct intel_encoder *encoder;
11981 intel_modeset_readout_hw_state(dev);
11984 * Now that we have the config, copy it to each CRTC struct
11985 * Note that this could go away if we move to using crtc_config
11986 * checking everywhere.
11988 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11990 if (crtc->active && i915.fastboot) {
11991 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
11992 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
11993 crtc->base.base.id);
11994 drm_mode_debug_printmodeline(&crtc->base.mode);
11998 /* HW state is read out, now we need to sanitize this mess. */
11999 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
12001 intel_sanitize_encoder(encoder);
12004 for_each_pipe(pipe) {
12005 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
12006 intel_sanitize_crtc(crtc);
12007 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
12010 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12011 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12013 if (!pll->on || pll->active)
12016 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
12018 pll->disable(dev_priv, pll);
12022 if (HAS_PCH_SPLIT(dev))
12023 ilk_wm_get_hw_state(dev);
12025 if (force_restore) {
12026 i915_redisable_vga(dev);
12029 * We need to use raw interfaces for restoring state to avoid
12030 * checking (bogus) intermediate states.
12032 for_each_pipe(pipe) {
12033 struct drm_crtc *crtc =
12034 dev_priv->pipe_to_crtc_mapping[pipe];
12036 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
12037 crtc->primary->fb);
12040 intel_modeset_update_staged_output_state(dev);
12043 intel_modeset_check_state(dev);
12046 void intel_modeset_gem_init(struct drm_device *dev)
12048 struct drm_crtc *c;
12049 struct intel_framebuffer *fb;
12051 mutex_lock(&dev->struct_mutex);
12052 intel_init_gt_powersave(dev);
12053 mutex_unlock(&dev->struct_mutex);
12055 intel_modeset_init_hw(dev);
12057 intel_setup_overlay(dev);
12060 * Make sure any fbs we allocated at startup are properly
12061 * pinned & fenced. When we do the allocation it's too early
12064 mutex_lock(&dev->struct_mutex);
12065 list_for_each_entry(c, &dev->mode_config.crtc_list, head) {
12066 if (!c->primary->fb)
12069 fb = to_intel_framebuffer(c->primary->fb);
12070 if (intel_pin_and_fence_fb_obj(dev, fb->obj, NULL)) {
12071 DRM_ERROR("failed to pin boot fb on pipe %d\n",
12072 to_intel_crtc(c)->pipe);
12073 drm_framebuffer_unreference(c->primary->fb);
12074 c->primary->fb = NULL;
12077 mutex_unlock(&dev->struct_mutex);
12080 void intel_connector_unregister(struct intel_connector *intel_connector)
12082 struct drm_connector *connector = &intel_connector->base;
12084 intel_panel_destroy_backlight(connector);
12085 drm_sysfs_connector_remove(connector);
12088 void intel_modeset_cleanup(struct drm_device *dev)
12090 struct drm_i915_private *dev_priv = dev->dev_private;
12091 struct drm_crtc *crtc;
12092 struct drm_connector *connector;
12095 * Interrupts and polling as the first thing to avoid creating havoc.
12096 * Too much stuff here (turning of rps, connectors, ...) would
12097 * experience fancy races otherwise.
12099 drm_irq_uninstall(dev);
12100 cancel_work_sync(&dev_priv->hotplug_work);
12102 * Due to the hpd irq storm handling the hotplug work can re-arm the
12103 * poll handlers. Hence disable polling after hpd handling is shut down.
12105 drm_kms_helper_poll_fini(dev);
12107 mutex_lock(&dev->struct_mutex);
12109 intel_unregister_dsm_handler();
12111 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
12112 /* Skip inactive CRTCs */
12113 if (!crtc->primary->fb)
12116 intel_increase_pllclock(crtc);
12119 intel_disable_fbc(dev);
12121 intel_disable_gt_powersave(dev);
12123 ironlake_teardown_rc6(dev);
12125 mutex_unlock(&dev->struct_mutex);
12127 /* flush any delayed tasks or pending work */
12128 flush_scheduled_work();
12130 /* destroy the backlight and sysfs files before encoders/connectors */
12131 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12132 struct intel_connector *intel_connector;
12134 intel_connector = to_intel_connector(connector);
12135 intel_connector->unregister(intel_connector);
12138 drm_mode_config_cleanup(dev);
12140 intel_cleanup_overlay(dev);
12142 mutex_lock(&dev->struct_mutex);
12143 intel_cleanup_gt_powersave(dev);
12144 mutex_unlock(&dev->struct_mutex);
12148 * Return which encoder is currently attached for connector.
12150 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
12152 return &intel_attached_encoder(connector)->base;
12155 void intel_connector_attach_encoder(struct intel_connector *connector,
12156 struct intel_encoder *encoder)
12158 connector->encoder = encoder;
12159 drm_mode_connector_attach_encoder(&connector->base,
12164 * set vga decode state - true == enable VGA decode
12166 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
12168 struct drm_i915_private *dev_priv = dev->dev_private;
12169 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
12172 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
12173 DRM_ERROR("failed to read control word\n");
12177 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
12181 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
12183 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
12185 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
12186 DRM_ERROR("failed to write control word\n");
12193 struct intel_display_error_state {
12195 u32 power_well_driver;
12197 int num_transcoders;
12199 struct intel_cursor_error_state {
12204 } cursor[I915_MAX_PIPES];
12206 struct intel_pipe_error_state {
12207 bool power_domain_on;
12210 } pipe[I915_MAX_PIPES];
12212 struct intel_plane_error_state {
12220 } plane[I915_MAX_PIPES];
12222 struct intel_transcoder_error_state {
12223 bool power_domain_on;
12224 enum transcoder cpu_transcoder;
12237 struct intel_display_error_state *
12238 intel_display_capture_error_state(struct drm_device *dev)
12240 struct drm_i915_private *dev_priv = dev->dev_private;
12241 struct intel_display_error_state *error;
12242 int transcoders[] = {
12250 if (INTEL_INFO(dev)->num_pipes == 0)
12253 error = kzalloc(sizeof(*error), GFP_ATOMIC);
12257 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
12258 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
12261 error->pipe[i].power_domain_on =
12262 intel_display_power_enabled_sw(dev_priv,
12263 POWER_DOMAIN_PIPE(i));
12264 if (!error->pipe[i].power_domain_on)
12267 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
12268 error->cursor[i].control = I915_READ(CURCNTR(i));
12269 error->cursor[i].position = I915_READ(CURPOS(i));
12270 error->cursor[i].base = I915_READ(CURBASE(i));
12272 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
12273 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
12274 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
12277 error->plane[i].control = I915_READ(DSPCNTR(i));
12278 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
12279 if (INTEL_INFO(dev)->gen <= 3) {
12280 error->plane[i].size = I915_READ(DSPSIZE(i));
12281 error->plane[i].pos = I915_READ(DSPPOS(i));
12283 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
12284 error->plane[i].addr = I915_READ(DSPADDR(i));
12285 if (INTEL_INFO(dev)->gen >= 4) {
12286 error->plane[i].surface = I915_READ(DSPSURF(i));
12287 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
12290 error->pipe[i].source = I915_READ(PIPESRC(i));
12292 if (!HAS_PCH_SPLIT(dev))
12293 error->pipe[i].stat = I915_READ(PIPESTAT(i));
12296 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
12297 if (HAS_DDI(dev_priv->dev))
12298 error->num_transcoders++; /* Account for eDP. */
12300 for (i = 0; i < error->num_transcoders; i++) {
12301 enum transcoder cpu_transcoder = transcoders[i];
12303 error->transcoder[i].power_domain_on =
12304 intel_display_power_enabled_sw(dev_priv,
12305 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
12306 if (!error->transcoder[i].power_domain_on)
12309 error->transcoder[i].cpu_transcoder = cpu_transcoder;
12311 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
12312 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
12313 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
12314 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
12315 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
12316 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
12317 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
12323 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
12326 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
12327 struct drm_device *dev,
12328 struct intel_display_error_state *error)
12335 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
12336 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
12337 err_printf(m, "PWR_WELL_CTL2: %08x\n",
12338 error->power_well_driver);
12340 err_printf(m, "Pipe [%d]:\n", i);
12341 err_printf(m, " Power: %s\n",
12342 error->pipe[i].power_domain_on ? "on" : "off");
12343 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
12344 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
12346 err_printf(m, "Plane [%d]:\n", i);
12347 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
12348 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
12349 if (INTEL_INFO(dev)->gen <= 3) {
12350 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
12351 err_printf(m, " POS: %08x\n", error->plane[i].pos);
12353 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
12354 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
12355 if (INTEL_INFO(dev)->gen >= 4) {
12356 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
12357 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
12360 err_printf(m, "Cursor [%d]:\n", i);
12361 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
12362 err_printf(m, " POS: %08x\n", error->cursor[i].position);
12363 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
12366 for (i = 0; i < error->num_transcoders; i++) {
12367 err_printf(m, "CPU transcoder: %c\n",
12368 transcoder_name(error->transcoder[i].cpu_transcoder));
12369 err_printf(m, " Power: %s\n",
12370 error->transcoder[i].power_domain_on ? "on" : "off");
12371 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
12372 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
12373 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
12374 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
12375 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
12376 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
12377 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);