2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
45 static void intel_increase_pllclock(struct drm_crtc *crtc);
46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
57 #define INTEL_P2_NUM 2
58 typedef struct intel_limit intel_limit_t;
60 intel_range_t dot, vco, n, m, m1, m2, p, p1;
65 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
68 intel_pch_rawclk(struct drm_device *dev)
70 struct drm_i915_private *dev_priv = dev->dev_private;
72 WARN_ON(!HAS_PCH_SPLIT(dev));
74 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
77 static inline u32 /* units of 100MHz */
78 intel_fdi_link_freq(struct drm_device *dev)
81 struct drm_i915_private *dev_priv = dev->dev_private;
82 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
87 static const intel_limit_t intel_limits_i8xx_dvo = {
88 .dot = { .min = 25000, .max = 350000 },
89 .vco = { .min = 930000, .max = 1400000 },
90 .n = { .min = 3, .max = 16 },
91 .m = { .min = 96, .max = 140 },
92 .m1 = { .min = 18, .max = 26 },
93 .m2 = { .min = 6, .max = 16 },
94 .p = { .min = 4, .max = 128 },
95 .p1 = { .min = 2, .max = 33 },
96 .p2 = { .dot_limit = 165000,
97 .p2_slow = 4, .p2_fast = 2 },
100 static const intel_limit_t intel_limits_i8xx_lvds = {
101 .dot = { .min = 25000, .max = 350000 },
102 .vco = { .min = 930000, .max = 1400000 },
103 .n = { .min = 3, .max = 16 },
104 .m = { .min = 96, .max = 140 },
105 .m1 = { .min = 18, .max = 26 },
106 .m2 = { .min = 6, .max = 16 },
107 .p = { .min = 4, .max = 128 },
108 .p1 = { .min = 1, .max = 6 },
109 .p2 = { .dot_limit = 165000,
110 .p2_slow = 14, .p2_fast = 7 },
113 static const intel_limit_t intel_limits_i9xx_sdvo = {
114 .dot = { .min = 20000, .max = 400000 },
115 .vco = { .min = 1400000, .max = 2800000 },
116 .n = { .min = 1, .max = 6 },
117 .m = { .min = 70, .max = 120 },
118 .m1 = { .min = 8, .max = 18 },
119 .m2 = { .min = 3, .max = 7 },
120 .p = { .min = 5, .max = 80 },
121 .p1 = { .min = 1, .max = 8 },
122 .p2 = { .dot_limit = 200000,
123 .p2_slow = 10, .p2_fast = 5 },
126 static const intel_limit_t intel_limits_i9xx_lvds = {
127 .dot = { .min = 20000, .max = 400000 },
128 .vco = { .min = 1400000, .max = 2800000 },
129 .n = { .min = 1, .max = 6 },
130 .m = { .min = 70, .max = 120 },
131 .m1 = { .min = 8, .max = 18 },
132 .m2 = { .min = 3, .max = 7 },
133 .p = { .min = 7, .max = 98 },
134 .p1 = { .min = 1, .max = 8 },
135 .p2 = { .dot_limit = 112000,
136 .p2_slow = 14, .p2_fast = 7 },
140 static const intel_limit_t intel_limits_g4x_sdvo = {
141 .dot = { .min = 25000, .max = 270000 },
142 .vco = { .min = 1750000, .max = 3500000},
143 .n = { .min = 1, .max = 4 },
144 .m = { .min = 104, .max = 138 },
145 .m1 = { .min = 17, .max = 23 },
146 .m2 = { .min = 5, .max = 11 },
147 .p = { .min = 10, .max = 30 },
148 .p1 = { .min = 1, .max = 3},
149 .p2 = { .dot_limit = 270000,
155 static const intel_limit_t intel_limits_g4x_hdmi = {
156 .dot = { .min = 22000, .max = 400000 },
157 .vco = { .min = 1750000, .max = 3500000},
158 .n = { .min = 1, .max = 4 },
159 .m = { .min = 104, .max = 138 },
160 .m1 = { .min = 16, .max = 23 },
161 .m2 = { .min = 5, .max = 11 },
162 .p = { .min = 5, .max = 80 },
163 .p1 = { .min = 1, .max = 8},
164 .p2 = { .dot_limit = 165000,
165 .p2_slow = 10, .p2_fast = 5 },
168 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
169 .dot = { .min = 20000, .max = 115000 },
170 .vco = { .min = 1750000, .max = 3500000 },
171 .n = { .min = 1, .max = 3 },
172 .m = { .min = 104, .max = 138 },
173 .m1 = { .min = 17, .max = 23 },
174 .m2 = { .min = 5, .max = 11 },
175 .p = { .min = 28, .max = 112 },
176 .p1 = { .min = 2, .max = 8 },
177 .p2 = { .dot_limit = 0,
178 .p2_slow = 14, .p2_fast = 14
182 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
183 .dot = { .min = 80000, .max = 224000 },
184 .vco = { .min = 1750000, .max = 3500000 },
185 .n = { .min = 1, .max = 3 },
186 .m = { .min = 104, .max = 138 },
187 .m1 = { .min = 17, .max = 23 },
188 .m2 = { .min = 5, .max = 11 },
189 .p = { .min = 14, .max = 42 },
190 .p1 = { .min = 2, .max = 6 },
191 .p2 = { .dot_limit = 0,
192 .p2_slow = 7, .p2_fast = 7
196 static const intel_limit_t intel_limits_pineview_sdvo = {
197 .dot = { .min = 20000, .max = 400000},
198 .vco = { .min = 1700000, .max = 3500000 },
199 /* Pineview's Ncounter is a ring counter */
200 .n = { .min = 3, .max = 6 },
201 .m = { .min = 2, .max = 256 },
202 /* Pineview only has one combined m divider, which we treat as m2. */
203 .m1 = { .min = 0, .max = 0 },
204 .m2 = { .min = 0, .max = 254 },
205 .p = { .min = 5, .max = 80 },
206 .p1 = { .min = 1, .max = 8 },
207 .p2 = { .dot_limit = 200000,
208 .p2_slow = 10, .p2_fast = 5 },
211 static const intel_limit_t intel_limits_pineview_lvds = {
212 .dot = { .min = 20000, .max = 400000 },
213 .vco = { .min = 1700000, .max = 3500000 },
214 .n = { .min = 3, .max = 6 },
215 .m = { .min = 2, .max = 256 },
216 .m1 = { .min = 0, .max = 0 },
217 .m2 = { .min = 0, .max = 254 },
218 .p = { .min = 7, .max = 112 },
219 .p1 = { .min = 1, .max = 8 },
220 .p2 = { .dot_limit = 112000,
221 .p2_slow = 14, .p2_fast = 14 },
224 /* Ironlake / Sandybridge
226 * We calculate clock using (register_value + 2) for N/M1/M2, so here
227 * the range value for them is (actual_value - 2).
229 static const intel_limit_t intel_limits_ironlake_dac = {
230 .dot = { .min = 25000, .max = 350000 },
231 .vco = { .min = 1760000, .max = 3510000 },
232 .n = { .min = 1, .max = 5 },
233 .m = { .min = 79, .max = 127 },
234 .m1 = { .min = 12, .max = 22 },
235 .m2 = { .min = 5, .max = 9 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8 },
238 .p2 = { .dot_limit = 225000,
239 .p2_slow = 10, .p2_fast = 5 },
242 static const intel_limit_t intel_limits_ironlake_single_lvds = {
243 .dot = { .min = 25000, .max = 350000 },
244 .vco = { .min = 1760000, .max = 3510000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 79, .max = 118 },
247 .m1 = { .min = 12, .max = 22 },
248 .m2 = { .min = 5, .max = 9 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 225000,
252 .p2_slow = 14, .p2_fast = 14 },
255 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
256 .dot = { .min = 25000, .max = 350000 },
257 .vco = { .min = 1760000, .max = 3510000 },
258 .n = { .min = 1, .max = 3 },
259 .m = { .min = 79, .max = 127 },
260 .m1 = { .min = 12, .max = 22 },
261 .m2 = { .min = 5, .max = 9 },
262 .p = { .min = 14, .max = 56 },
263 .p1 = { .min = 2, .max = 8 },
264 .p2 = { .dot_limit = 225000,
265 .p2_slow = 7, .p2_fast = 7 },
268 /* LVDS 100mhz refclk limits. */
269 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
270 .dot = { .min = 25000, .max = 350000 },
271 .vco = { .min = 1760000, .max = 3510000 },
272 .n = { .min = 1, .max = 2 },
273 .m = { .min = 79, .max = 126 },
274 .m1 = { .min = 12, .max = 22 },
275 .m2 = { .min = 5, .max = 9 },
276 .p = { .min = 28, .max = 112 },
277 .p1 = { .min = 2, .max = 8 },
278 .p2 = { .dot_limit = 225000,
279 .p2_slow = 14, .p2_fast = 14 },
282 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
283 .dot = { .min = 25000, .max = 350000 },
284 .vco = { .min = 1760000, .max = 3510000 },
285 .n = { .min = 1, .max = 3 },
286 .m = { .min = 79, .max = 126 },
287 .m1 = { .min = 12, .max = 22 },
288 .m2 = { .min = 5, .max = 9 },
289 .p = { .min = 14, .max = 42 },
290 .p1 = { .min = 2, .max = 6 },
291 .p2 = { .dot_limit = 225000,
292 .p2_slow = 7, .p2_fast = 7 },
295 static const intel_limit_t intel_limits_vlv_dac = {
296 .dot = { .min = 25000, .max = 270000 },
297 .vco = { .min = 4000000, .max = 6000000 },
298 .n = { .min = 1, .max = 7 },
299 .m = { .min = 22, .max = 450 }, /* guess */
300 .m1 = { .min = 2, .max = 3 },
301 .m2 = { .min = 11, .max = 156 },
302 .p = { .min = 10, .max = 30 },
303 .p1 = { .min = 1, .max = 3 },
304 .p2 = { .dot_limit = 270000,
305 .p2_slow = 2, .p2_fast = 20 },
308 static const intel_limit_t intel_limits_vlv_hdmi = {
309 .dot = { .min = 25000, .max = 270000 },
310 .vco = { .min = 4000000, .max = 6000000 },
311 .n = { .min = 1, .max = 7 },
312 .m = { .min = 60, .max = 300 }, /* guess */
313 .m1 = { .min = 2, .max = 3 },
314 .m2 = { .min = 11, .max = 156 },
315 .p = { .min = 10, .max = 30 },
316 .p1 = { .min = 2, .max = 3 },
317 .p2 = { .dot_limit = 270000,
318 .p2_slow = 2, .p2_fast = 20 },
321 static const intel_limit_t intel_limits_vlv_dp = {
322 .dot = { .min = 25000, .max = 270000 },
323 .vco = { .min = 4000000, .max = 6000000 },
324 .n = { .min = 1, .max = 7 },
325 .m = { .min = 22, .max = 450 },
326 .m1 = { .min = 2, .max = 3 },
327 .m2 = { .min = 11, .max = 156 },
328 .p = { .min = 10, .max = 30 },
329 .p1 = { .min = 1, .max = 3 },
330 .p2 = { .dot_limit = 270000,
331 .p2_slow = 2, .p2_fast = 20 },
334 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
337 struct drm_device *dev = crtc->dev;
338 const intel_limit_t *limit;
340 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
341 if (intel_is_dual_link_lvds(dev)) {
342 if (refclk == 100000)
343 limit = &intel_limits_ironlake_dual_lvds_100m;
345 limit = &intel_limits_ironlake_dual_lvds;
347 if (refclk == 100000)
348 limit = &intel_limits_ironlake_single_lvds_100m;
350 limit = &intel_limits_ironlake_single_lvds;
353 limit = &intel_limits_ironlake_dac;
358 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
360 struct drm_device *dev = crtc->dev;
361 const intel_limit_t *limit;
363 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
364 if (intel_is_dual_link_lvds(dev))
365 limit = &intel_limits_g4x_dual_channel_lvds;
367 limit = &intel_limits_g4x_single_channel_lvds;
368 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
369 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
370 limit = &intel_limits_g4x_hdmi;
371 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
372 limit = &intel_limits_g4x_sdvo;
373 } else /* The option is for other outputs */
374 limit = &intel_limits_i9xx_sdvo;
379 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
381 struct drm_device *dev = crtc->dev;
382 const intel_limit_t *limit;
384 if (HAS_PCH_SPLIT(dev))
385 limit = intel_ironlake_limit(crtc, refclk);
386 else if (IS_G4X(dev)) {
387 limit = intel_g4x_limit(crtc);
388 } else if (IS_PINEVIEW(dev)) {
389 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
390 limit = &intel_limits_pineview_lvds;
392 limit = &intel_limits_pineview_sdvo;
393 } else if (IS_VALLEYVIEW(dev)) {
394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
395 limit = &intel_limits_vlv_dac;
396 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
397 limit = &intel_limits_vlv_hdmi;
399 limit = &intel_limits_vlv_dp;
400 } else if (!IS_GEN2(dev)) {
401 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
402 limit = &intel_limits_i9xx_lvds;
404 limit = &intel_limits_i9xx_sdvo;
406 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
407 limit = &intel_limits_i8xx_lvds;
409 limit = &intel_limits_i8xx_dvo;
414 /* m1 is reserved as 0 in Pineview, n is a ring counter */
415 static void pineview_clock(int refclk, intel_clock_t *clock)
417 clock->m = clock->m2 + 2;
418 clock->p = clock->p1 * clock->p2;
419 clock->vco = refclk * clock->m / clock->n;
420 clock->dot = clock->vco / clock->p;
423 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
425 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
428 static void i9xx_clock(int refclk, intel_clock_t *clock)
430 clock->m = i9xx_dpll_compute_m(clock);
431 clock->p = clock->p1 * clock->p2;
432 clock->vco = refclk * clock->m / (clock->n + 2);
433 clock->dot = clock->vco / clock->p;
437 * Returns whether any output on the specified pipe is of the specified type
439 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
441 struct drm_device *dev = crtc->dev;
442 struct intel_encoder *encoder;
444 for_each_encoder_on_crtc(dev, crtc, encoder)
445 if (encoder->type == type)
451 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
453 * Returns whether the given set of divisors are valid for a given refclk with
454 * the given connectors.
457 static bool intel_PLL_is_valid(struct drm_device *dev,
458 const intel_limit_t *limit,
459 const intel_clock_t *clock)
461 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
462 INTELPllInvalid("p1 out of range\n");
463 if (clock->p < limit->p.min || limit->p.max < clock->p)
464 INTELPllInvalid("p out of range\n");
465 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
466 INTELPllInvalid("m2 out of range\n");
467 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
468 INTELPllInvalid("m1 out of range\n");
469 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
470 INTELPllInvalid("m1 <= m2\n");
471 if (clock->m < limit->m.min || limit->m.max < clock->m)
472 INTELPllInvalid("m out of range\n");
473 if (clock->n < limit->n.min || limit->n.max < clock->n)
474 INTELPllInvalid("n out of range\n");
475 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
476 INTELPllInvalid("vco out of range\n");
477 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
478 * connector, etc., rather than just a single range.
480 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
481 INTELPllInvalid("dot out of range\n");
487 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
488 int target, int refclk, intel_clock_t *match_clock,
489 intel_clock_t *best_clock)
491 struct drm_device *dev = crtc->dev;
495 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
497 * For LVDS just rely on its current settings for dual-channel.
498 * We haven't figured out how to reliably set up different
499 * single/dual channel state, if we even can.
501 if (intel_is_dual_link_lvds(dev))
502 clock.p2 = limit->p2.p2_fast;
504 clock.p2 = limit->p2.p2_slow;
506 if (target < limit->p2.dot_limit)
507 clock.p2 = limit->p2.p2_slow;
509 clock.p2 = limit->p2.p2_fast;
512 memset(best_clock, 0, sizeof(*best_clock));
514 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
516 for (clock.m2 = limit->m2.min;
517 clock.m2 <= limit->m2.max; clock.m2++) {
518 if (clock.m2 >= clock.m1)
520 for (clock.n = limit->n.min;
521 clock.n <= limit->n.max; clock.n++) {
522 for (clock.p1 = limit->p1.min;
523 clock.p1 <= limit->p1.max; clock.p1++) {
526 i9xx_clock(refclk, &clock);
527 if (!intel_PLL_is_valid(dev, limit,
531 clock.p != match_clock->p)
534 this_err = abs(clock.dot - target);
535 if (this_err < err) {
544 return (err != target);
548 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
549 int target, int refclk, intel_clock_t *match_clock,
550 intel_clock_t *best_clock)
552 struct drm_device *dev = crtc->dev;
556 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
558 * For LVDS just rely on its current settings for dual-channel.
559 * We haven't figured out how to reliably set up different
560 * single/dual channel state, if we even can.
562 if (intel_is_dual_link_lvds(dev))
563 clock.p2 = limit->p2.p2_fast;
565 clock.p2 = limit->p2.p2_slow;
567 if (target < limit->p2.dot_limit)
568 clock.p2 = limit->p2.p2_slow;
570 clock.p2 = limit->p2.p2_fast;
573 memset(best_clock, 0, sizeof(*best_clock));
575 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
577 for (clock.m2 = limit->m2.min;
578 clock.m2 <= limit->m2.max; clock.m2++) {
579 for (clock.n = limit->n.min;
580 clock.n <= limit->n.max; clock.n++) {
581 for (clock.p1 = limit->p1.min;
582 clock.p1 <= limit->p1.max; clock.p1++) {
585 pineview_clock(refclk, &clock);
586 if (!intel_PLL_is_valid(dev, limit,
590 clock.p != match_clock->p)
593 this_err = abs(clock.dot - target);
594 if (this_err < err) {
603 return (err != target);
607 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
608 int target, int refclk, intel_clock_t *match_clock,
609 intel_clock_t *best_clock)
611 struct drm_device *dev = crtc->dev;
615 /* approximately equals target * 0.00585 */
616 int err_most = (target >> 8) + (target >> 9);
619 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
620 if (intel_is_dual_link_lvds(dev))
621 clock.p2 = limit->p2.p2_fast;
623 clock.p2 = limit->p2.p2_slow;
625 if (target < limit->p2.dot_limit)
626 clock.p2 = limit->p2.p2_slow;
628 clock.p2 = limit->p2.p2_fast;
631 memset(best_clock, 0, sizeof(*best_clock));
632 max_n = limit->n.max;
633 /* based on hardware requirement, prefer smaller n to precision */
634 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
635 /* based on hardware requirement, prefere larger m1,m2 */
636 for (clock.m1 = limit->m1.max;
637 clock.m1 >= limit->m1.min; clock.m1--) {
638 for (clock.m2 = limit->m2.max;
639 clock.m2 >= limit->m2.min; clock.m2--) {
640 for (clock.p1 = limit->p1.max;
641 clock.p1 >= limit->p1.min; clock.p1--) {
644 i9xx_clock(refclk, &clock);
645 if (!intel_PLL_is_valid(dev, limit,
649 this_err = abs(clock.dot - target);
650 if (this_err < err_most) {
664 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
665 int target, int refclk, intel_clock_t *match_clock,
666 intel_clock_t *best_clock)
668 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
670 u32 updrate, minupdate, fracbits, p;
671 unsigned long bestppm, ppm, absppm;
675 dotclk = target * 1000;
678 fastclk = dotclk / (2*100);
682 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
683 bestm1 = bestm2 = bestp1 = bestp2 = 0;
685 /* based on hardware requirement, prefer smaller n to precision */
686 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
687 updrate = refclk / n;
688 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
689 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
693 /* based on hardware requirement, prefer bigger m1,m2 values */
694 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
695 m2 = (((2*(fastclk * p * n / m1 )) +
696 refclk) / (2*refclk));
699 if (vco >= limit->vco.min && vco < limit->vco.max) {
700 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
701 absppm = (ppm > 0) ? ppm : (-ppm);
702 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
706 if (absppm < bestppm - 10) {
723 best_clock->n = bestn;
724 best_clock->m1 = bestm1;
725 best_clock->m2 = bestm2;
726 best_clock->p1 = bestp1;
727 best_clock->p2 = bestp2;
732 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
735 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
738 return intel_crtc->config.cpu_transcoder;
741 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
743 struct drm_i915_private *dev_priv = dev->dev_private;
744 u32 frame, frame_reg = PIPEFRAME(pipe);
746 frame = I915_READ(frame_reg);
748 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
749 DRM_DEBUG_KMS("vblank wait timed out\n");
753 * intel_wait_for_vblank - wait for vblank on a given pipe
755 * @pipe: pipe to wait for
757 * Wait for vblank to occur on a given pipe. Needed for various bits of
760 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
762 struct drm_i915_private *dev_priv = dev->dev_private;
763 int pipestat_reg = PIPESTAT(pipe);
765 if (INTEL_INFO(dev)->gen >= 5) {
766 ironlake_wait_for_vblank(dev, pipe);
770 /* Clear existing vblank status. Note this will clear any other
771 * sticky status fields as well.
773 * This races with i915_driver_irq_handler() with the result
774 * that either function could miss a vblank event. Here it is not
775 * fatal, as we will either wait upon the next vblank interrupt or
776 * timeout. Generally speaking intel_wait_for_vblank() is only
777 * called during modeset at which time the GPU should be idle and
778 * should *not* be performing page flips and thus not waiting on
780 * Currently, the result of us stealing a vblank from the irq
781 * handler is that a single frame will be skipped during swapbuffers.
783 I915_WRITE(pipestat_reg,
784 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
786 /* Wait for vblank interrupt bit to set */
787 if (wait_for(I915_READ(pipestat_reg) &
788 PIPE_VBLANK_INTERRUPT_STATUS,
790 DRM_DEBUG_KMS("vblank wait timed out\n");
794 * intel_wait_for_pipe_off - wait for pipe to turn off
796 * @pipe: pipe to wait for
798 * After disabling a pipe, we can't wait for vblank in the usual way,
799 * spinning on the vblank interrupt status bit, since we won't actually
800 * see an interrupt when the pipe is disabled.
803 * wait for the pipe register state bit to turn off
806 * wait for the display line value to settle (it usually
807 * ends up stopping at the start of the next frame).
810 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
812 struct drm_i915_private *dev_priv = dev->dev_private;
813 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
816 if (INTEL_INFO(dev)->gen >= 4) {
817 int reg = PIPECONF(cpu_transcoder);
819 /* Wait for the Pipe State to go off */
820 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
822 WARN(1, "pipe_off wait timed out\n");
824 u32 last_line, line_mask;
825 int reg = PIPEDSL(pipe);
826 unsigned long timeout = jiffies + msecs_to_jiffies(100);
829 line_mask = DSL_LINEMASK_GEN2;
831 line_mask = DSL_LINEMASK_GEN3;
833 /* Wait for the display line to settle */
835 last_line = I915_READ(reg) & line_mask;
837 } while (((I915_READ(reg) & line_mask) != last_line) &&
838 time_after(timeout, jiffies));
839 if (time_after(jiffies, timeout))
840 WARN(1, "pipe_off wait timed out\n");
845 * ibx_digital_port_connected - is the specified port connected?
846 * @dev_priv: i915 private structure
847 * @port: the port to test
849 * Returns true if @port is connected, false otherwise.
851 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
852 struct intel_digital_port *port)
856 if (HAS_PCH_IBX(dev_priv->dev)) {
859 bit = SDE_PORTB_HOTPLUG;
862 bit = SDE_PORTC_HOTPLUG;
865 bit = SDE_PORTD_HOTPLUG;
873 bit = SDE_PORTB_HOTPLUG_CPT;
876 bit = SDE_PORTC_HOTPLUG_CPT;
879 bit = SDE_PORTD_HOTPLUG_CPT;
886 return I915_READ(SDEISR) & bit;
889 static const char *state_string(bool enabled)
891 return enabled ? "on" : "off";
894 /* Only for pre-ILK configs */
895 static void assert_pll(struct drm_i915_private *dev_priv,
896 enum pipe pipe, bool state)
903 val = I915_READ(reg);
904 cur_state = !!(val & DPLL_VCO_ENABLE);
905 WARN(cur_state != state,
906 "PLL state assertion failure (expected %s, current %s)\n",
907 state_string(state), state_string(cur_state));
909 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
910 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
912 static struct intel_shared_dpll *
913 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
915 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
917 if (crtc->config.shared_dpll < 0)
920 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
924 static void assert_shared_dpll(struct drm_i915_private *dev_priv,
925 struct intel_shared_dpll *pll,
929 struct intel_dpll_hw_state hw_state;
931 if (HAS_PCH_LPT(dev_priv->dev)) {
932 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
937 "asserting DPLL %s with no DPLL\n", state_string(state)))
940 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
941 WARN(cur_state != state,
942 "%s assertion failure (expected %s, current %s)\n",
943 pll->name, state_string(state), state_string(cur_state));
945 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
946 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
948 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
949 enum pipe pipe, bool state)
954 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
957 if (HAS_DDI(dev_priv->dev)) {
958 /* DDI does not have a specific FDI_TX register */
959 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
960 val = I915_READ(reg);
961 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
963 reg = FDI_TX_CTL(pipe);
964 val = I915_READ(reg);
965 cur_state = !!(val & FDI_TX_ENABLE);
967 WARN(cur_state != state,
968 "FDI TX state assertion failure (expected %s, current %s)\n",
969 state_string(state), state_string(cur_state));
971 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
972 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
974 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
975 enum pipe pipe, bool state)
981 reg = FDI_RX_CTL(pipe);
982 val = I915_READ(reg);
983 cur_state = !!(val & FDI_RX_ENABLE);
984 WARN(cur_state != state,
985 "FDI RX state assertion failure (expected %s, current %s)\n",
986 state_string(state), state_string(cur_state));
988 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
989 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
991 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
997 /* ILK FDI PLL is always enabled */
998 if (dev_priv->info->gen == 5)
1001 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1002 if (HAS_DDI(dev_priv->dev))
1005 reg = FDI_TX_CTL(pipe);
1006 val = I915_READ(reg);
1007 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1010 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1016 reg = FDI_RX_CTL(pipe);
1017 val = I915_READ(reg);
1018 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1021 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1024 int pp_reg, lvds_reg;
1026 enum pipe panel_pipe = PIPE_A;
1029 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1030 pp_reg = PCH_PP_CONTROL;
1031 lvds_reg = PCH_LVDS;
1033 pp_reg = PP_CONTROL;
1037 val = I915_READ(pp_reg);
1038 if (!(val & PANEL_POWER_ON) ||
1039 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1042 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1043 panel_pipe = PIPE_B;
1045 WARN(panel_pipe == pipe && locked,
1046 "panel assertion failure, pipe %c regs locked\n",
1050 void assert_pipe(struct drm_i915_private *dev_priv,
1051 enum pipe pipe, bool state)
1056 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1059 /* if we need the pipe A quirk it must be always on */
1060 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1063 if (!intel_display_power_enabled(dev_priv->dev,
1064 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1067 reg = PIPECONF(cpu_transcoder);
1068 val = I915_READ(reg);
1069 cur_state = !!(val & PIPECONF_ENABLE);
1072 WARN(cur_state != state,
1073 "pipe %c assertion failure (expected %s, current %s)\n",
1074 pipe_name(pipe), state_string(state), state_string(cur_state));
1077 static void assert_plane(struct drm_i915_private *dev_priv,
1078 enum plane plane, bool state)
1084 reg = DSPCNTR(plane);
1085 val = I915_READ(reg);
1086 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1087 WARN(cur_state != state,
1088 "plane %c assertion failure (expected %s, current %s)\n",
1089 plane_name(plane), state_string(state), state_string(cur_state));
1092 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1093 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1095 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1098 struct drm_device *dev = dev_priv->dev;
1103 /* Primary planes are fixed to pipes on gen4+ */
1104 if (INTEL_INFO(dev)->gen >= 4) {
1105 reg = DSPCNTR(pipe);
1106 val = I915_READ(reg);
1107 WARN((val & DISPLAY_PLANE_ENABLE),
1108 "plane %c assertion failure, should be disabled but not\n",
1113 /* Need to check both planes against the pipe */
1114 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
1116 val = I915_READ(reg);
1117 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1118 DISPPLANE_SEL_PIPE_SHIFT;
1119 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1120 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1121 plane_name(i), pipe_name(pipe));
1125 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1128 struct drm_device *dev = dev_priv->dev;
1132 if (IS_VALLEYVIEW(dev)) {
1133 for (i = 0; i < dev_priv->num_plane; i++) {
1134 reg = SPCNTR(pipe, i);
1135 val = I915_READ(reg);
1136 WARN((val & SP_ENABLE),
1137 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1138 sprite_name(pipe, i), pipe_name(pipe));
1140 } else if (INTEL_INFO(dev)->gen >= 7) {
1142 val = I915_READ(reg);
1143 WARN((val & SPRITE_ENABLE),
1144 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1145 plane_name(pipe), pipe_name(pipe));
1146 } else if (INTEL_INFO(dev)->gen >= 5) {
1147 reg = DVSCNTR(pipe);
1148 val = I915_READ(reg);
1149 WARN((val & DVS_ENABLE),
1150 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1151 plane_name(pipe), pipe_name(pipe));
1155 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1160 if (HAS_PCH_LPT(dev_priv->dev)) {
1161 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1165 val = I915_READ(PCH_DREF_CONTROL);
1166 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1167 DREF_SUPERSPREAD_SOURCE_MASK));
1168 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1171 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1178 reg = PCH_TRANSCONF(pipe);
1179 val = I915_READ(reg);
1180 enabled = !!(val & TRANS_ENABLE);
1182 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1186 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1187 enum pipe pipe, u32 port_sel, u32 val)
1189 if ((val & DP_PORT_EN) == 0)
1192 if (HAS_PCH_CPT(dev_priv->dev)) {
1193 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1194 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1195 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1198 if ((val & DP_PIPE_MASK) != (pipe << 30))
1204 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1205 enum pipe pipe, u32 val)
1207 if ((val & SDVO_ENABLE) == 0)
1210 if (HAS_PCH_CPT(dev_priv->dev)) {
1211 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1214 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1220 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1221 enum pipe pipe, u32 val)
1223 if ((val & LVDS_PORT_EN) == 0)
1226 if (HAS_PCH_CPT(dev_priv->dev)) {
1227 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1230 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1236 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1237 enum pipe pipe, u32 val)
1239 if ((val & ADPA_DAC_ENABLE) == 0)
1241 if (HAS_PCH_CPT(dev_priv->dev)) {
1242 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1245 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1251 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1252 enum pipe pipe, int reg, u32 port_sel)
1254 u32 val = I915_READ(reg);
1255 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1256 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1257 reg, pipe_name(pipe));
1259 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1260 && (val & DP_PIPEB_SELECT),
1261 "IBX PCH dp port still using transcoder B\n");
1264 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1265 enum pipe pipe, int reg)
1267 u32 val = I915_READ(reg);
1268 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1269 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1270 reg, pipe_name(pipe));
1272 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1273 && (val & SDVO_PIPE_B_SELECT),
1274 "IBX PCH hdmi port still using transcoder B\n");
1277 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1283 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1284 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1285 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1288 val = I915_READ(reg);
1289 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1290 "PCH VGA enabled on transcoder %c, should be disabled\n",
1294 val = I915_READ(reg);
1295 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1296 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1299 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1300 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1301 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1305 * intel_enable_pll - enable a PLL
1306 * @dev_priv: i915 private structure
1307 * @pipe: pipe PLL to enable
1309 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1310 * make sure the PLL reg is writable first though, since the panel write
1311 * protect mechanism may be enabled.
1313 * Note! This is for pre-ILK only.
1315 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1317 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1322 assert_pipe_disabled(dev_priv, pipe);
1324 /* No really, not for ILK+ */
1325 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1327 /* PLL is protected by panel, make sure we can write it */
1328 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1329 assert_panel_unlocked(dev_priv, pipe);
1332 val = I915_READ(reg);
1333 val |= DPLL_VCO_ENABLE;
1335 /* We do this three times for luck */
1336 I915_WRITE(reg, val);
1338 udelay(150); /* wait for warmup */
1339 I915_WRITE(reg, val);
1341 udelay(150); /* wait for warmup */
1342 I915_WRITE(reg, val);
1344 udelay(150); /* wait for warmup */
1348 * intel_disable_pll - disable a PLL
1349 * @dev_priv: i915 private structure
1350 * @pipe: pipe PLL to disable
1352 * Disable the PLL for @pipe, making sure the pipe is off first.
1354 * Note! This is for pre-ILK only.
1356 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1361 /* Don't disable pipe A or pipe A PLLs if needed */
1362 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1365 /* Make sure the pipe isn't still relying on us */
1366 assert_pipe_disabled(dev_priv, pipe);
1369 val = I915_READ(reg);
1370 val &= ~DPLL_VCO_ENABLE;
1371 I915_WRITE(reg, val);
1375 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1380 port_mask = DPLL_PORTB_READY_MASK;
1382 port_mask = DPLL_PORTC_READY_MASK;
1384 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1385 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1386 'B' + port, I915_READ(DPLL(0)));
1390 * ironlake_enable_shared_dpll - enable PCH PLL
1391 * @dev_priv: i915 private structure
1392 * @pipe: pipe PLL to enable
1394 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1395 * drives the transcoder clock.
1397 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1399 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1400 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1402 /* PCH PLLs only available on ILK, SNB and IVB */
1403 BUG_ON(dev_priv->info->gen < 5);
1404 if (WARN_ON(pll == NULL))
1407 if (WARN_ON(pll->refcount == 0))
1410 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1411 pll->name, pll->active, pll->on,
1412 crtc->base.base.id);
1414 if (pll->active++) {
1416 assert_shared_dpll_enabled(dev_priv, pll);
1421 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1422 pll->enable(dev_priv, pll);
1426 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1428 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1429 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1431 /* PCH only available on ILK+ */
1432 BUG_ON(dev_priv->info->gen < 5);
1433 if (WARN_ON(pll == NULL))
1436 if (WARN_ON(pll->refcount == 0))
1439 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1440 pll->name, pll->active, pll->on,
1441 crtc->base.base.id);
1443 if (WARN_ON(pll->active == 0)) {
1444 assert_shared_dpll_disabled(dev_priv, pll);
1448 assert_shared_dpll_enabled(dev_priv, pll);
1453 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1454 pll->disable(dev_priv, pll);
1458 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1461 struct drm_device *dev = dev_priv->dev;
1462 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1463 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1464 uint32_t reg, val, pipeconf_val;
1466 /* PCH only available on ILK+ */
1467 BUG_ON(dev_priv->info->gen < 5);
1469 /* Make sure PCH DPLL is enabled */
1470 assert_shared_dpll_enabled(dev_priv,
1471 intel_crtc_to_shared_dpll(intel_crtc));
1473 /* FDI must be feeding us bits for PCH ports */
1474 assert_fdi_tx_enabled(dev_priv, pipe);
1475 assert_fdi_rx_enabled(dev_priv, pipe);
1477 if (HAS_PCH_CPT(dev)) {
1478 /* Workaround: Set the timing override bit before enabling the
1479 * pch transcoder. */
1480 reg = TRANS_CHICKEN2(pipe);
1481 val = I915_READ(reg);
1482 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1483 I915_WRITE(reg, val);
1486 reg = PCH_TRANSCONF(pipe);
1487 val = I915_READ(reg);
1488 pipeconf_val = I915_READ(PIPECONF(pipe));
1490 if (HAS_PCH_IBX(dev_priv->dev)) {
1492 * make the BPC in transcoder be consistent with
1493 * that in pipeconf reg.
1495 val &= ~PIPECONF_BPC_MASK;
1496 val |= pipeconf_val & PIPECONF_BPC_MASK;
1499 val &= ~TRANS_INTERLACE_MASK;
1500 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1501 if (HAS_PCH_IBX(dev_priv->dev) &&
1502 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1503 val |= TRANS_LEGACY_INTERLACED_ILK;
1505 val |= TRANS_INTERLACED;
1507 val |= TRANS_PROGRESSIVE;
1509 I915_WRITE(reg, val | TRANS_ENABLE);
1510 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1511 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1514 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1515 enum transcoder cpu_transcoder)
1517 u32 val, pipeconf_val;
1519 /* PCH only available on ILK+ */
1520 BUG_ON(dev_priv->info->gen < 5);
1522 /* FDI must be feeding us bits for PCH ports */
1523 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1524 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1526 /* Workaround: set timing override bit. */
1527 val = I915_READ(_TRANSA_CHICKEN2);
1528 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1529 I915_WRITE(_TRANSA_CHICKEN2, val);
1532 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1534 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1535 PIPECONF_INTERLACED_ILK)
1536 val |= TRANS_INTERLACED;
1538 val |= TRANS_PROGRESSIVE;
1540 I915_WRITE(LPT_TRANSCONF, val);
1541 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1542 DRM_ERROR("Failed to enable PCH transcoder\n");
1545 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1548 struct drm_device *dev = dev_priv->dev;
1551 /* FDI relies on the transcoder */
1552 assert_fdi_tx_disabled(dev_priv, pipe);
1553 assert_fdi_rx_disabled(dev_priv, pipe);
1555 /* Ports must be off as well */
1556 assert_pch_ports_disabled(dev_priv, pipe);
1558 reg = PCH_TRANSCONF(pipe);
1559 val = I915_READ(reg);
1560 val &= ~TRANS_ENABLE;
1561 I915_WRITE(reg, val);
1562 /* wait for PCH transcoder off, transcoder state */
1563 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1564 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1566 if (!HAS_PCH_IBX(dev)) {
1567 /* Workaround: Clear the timing override chicken bit again. */
1568 reg = TRANS_CHICKEN2(pipe);
1569 val = I915_READ(reg);
1570 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1571 I915_WRITE(reg, val);
1575 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1579 val = I915_READ(LPT_TRANSCONF);
1580 val &= ~TRANS_ENABLE;
1581 I915_WRITE(LPT_TRANSCONF, val);
1582 /* wait for PCH transcoder off, transcoder state */
1583 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1584 DRM_ERROR("Failed to disable PCH transcoder\n");
1586 /* Workaround: clear timing override bit. */
1587 val = I915_READ(_TRANSA_CHICKEN2);
1588 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1589 I915_WRITE(_TRANSA_CHICKEN2, val);
1593 * intel_enable_pipe - enable a pipe, asserting requirements
1594 * @dev_priv: i915 private structure
1595 * @pipe: pipe to enable
1596 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1598 * Enable @pipe, making sure that various hardware specific requirements
1599 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1601 * @pipe should be %PIPE_A or %PIPE_B.
1603 * Will wait until the pipe is actually running (i.e. first vblank) before
1606 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1609 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1611 enum pipe pch_transcoder;
1615 assert_planes_disabled(dev_priv, pipe);
1616 assert_sprites_disabled(dev_priv, pipe);
1618 if (HAS_PCH_LPT(dev_priv->dev))
1619 pch_transcoder = TRANSCODER_A;
1621 pch_transcoder = pipe;
1624 * A pipe without a PLL won't actually be able to drive bits from
1625 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1628 if (!HAS_PCH_SPLIT(dev_priv->dev))
1629 assert_pll_enabled(dev_priv, pipe);
1632 /* if driving the PCH, we need FDI enabled */
1633 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1634 assert_fdi_tx_pll_enabled(dev_priv,
1635 (enum pipe) cpu_transcoder);
1637 /* FIXME: assert CPU port conditions for SNB+ */
1640 reg = PIPECONF(cpu_transcoder);
1641 val = I915_READ(reg);
1642 if (val & PIPECONF_ENABLE)
1645 I915_WRITE(reg, val | PIPECONF_ENABLE);
1646 intel_wait_for_vblank(dev_priv->dev, pipe);
1650 * intel_disable_pipe - disable a pipe, asserting requirements
1651 * @dev_priv: i915 private structure
1652 * @pipe: pipe to disable
1654 * Disable @pipe, making sure that various hardware specific requirements
1655 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1657 * @pipe should be %PIPE_A or %PIPE_B.
1659 * Will wait until the pipe has shut down before returning.
1661 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1664 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1670 * Make sure planes won't keep trying to pump pixels to us,
1671 * or we might hang the display.
1673 assert_planes_disabled(dev_priv, pipe);
1674 assert_sprites_disabled(dev_priv, pipe);
1676 /* Don't disable pipe A or pipe A PLLs if needed */
1677 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1680 reg = PIPECONF(cpu_transcoder);
1681 val = I915_READ(reg);
1682 if ((val & PIPECONF_ENABLE) == 0)
1685 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1686 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1690 * Plane regs are double buffered, going from enabled->disabled needs a
1691 * trigger in order to latch. The display address reg provides this.
1693 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1696 if (dev_priv->info->gen >= 4)
1697 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1699 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1703 * intel_enable_plane - enable a display plane on a given pipe
1704 * @dev_priv: i915 private structure
1705 * @plane: plane to enable
1706 * @pipe: pipe being fed
1708 * Enable @plane on @pipe, making sure that @pipe is running first.
1710 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1711 enum plane plane, enum pipe pipe)
1716 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1717 assert_pipe_enabled(dev_priv, pipe);
1719 reg = DSPCNTR(plane);
1720 val = I915_READ(reg);
1721 if (val & DISPLAY_PLANE_ENABLE)
1724 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1725 intel_flush_display_plane(dev_priv, plane);
1726 intel_wait_for_vblank(dev_priv->dev, pipe);
1730 * intel_disable_plane - disable a display plane
1731 * @dev_priv: i915 private structure
1732 * @plane: plane to disable
1733 * @pipe: pipe consuming the data
1735 * Disable @plane; should be an independent operation.
1737 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1738 enum plane plane, enum pipe pipe)
1743 reg = DSPCNTR(plane);
1744 val = I915_READ(reg);
1745 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1748 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1749 intel_flush_display_plane(dev_priv, plane);
1750 intel_wait_for_vblank(dev_priv->dev, pipe);
1753 static bool need_vtd_wa(struct drm_device *dev)
1755 #ifdef CONFIG_INTEL_IOMMU
1756 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1763 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1764 struct drm_i915_gem_object *obj,
1765 struct intel_ring_buffer *pipelined)
1767 struct drm_i915_private *dev_priv = dev->dev_private;
1771 switch (obj->tiling_mode) {
1772 case I915_TILING_NONE:
1773 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1774 alignment = 128 * 1024;
1775 else if (INTEL_INFO(dev)->gen >= 4)
1776 alignment = 4 * 1024;
1778 alignment = 64 * 1024;
1781 /* pin() will align the object as required by fence */
1785 /* Despite that we check this in framebuffer_init userspace can
1786 * screw us over and change the tiling after the fact. Only
1787 * pinned buffers can't change their tiling. */
1788 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1794 /* Note that the w/a also requires 64 PTE of padding following the
1795 * bo. We currently fill all unused PTE with the shadow page and so
1796 * we should always have valid PTE following the scanout preventing
1799 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1800 alignment = 256 * 1024;
1802 dev_priv->mm.interruptible = false;
1803 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1805 goto err_interruptible;
1807 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1808 * fence, whereas 965+ only requires a fence if using
1809 * framebuffer compression. For simplicity, we always install
1810 * a fence as the cost is not that onerous.
1812 ret = i915_gem_object_get_fence(obj);
1816 i915_gem_object_pin_fence(obj);
1818 dev_priv->mm.interruptible = true;
1822 i915_gem_object_unpin(obj);
1824 dev_priv->mm.interruptible = true;
1828 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1830 i915_gem_object_unpin_fence(obj);
1831 i915_gem_object_unpin(obj);
1834 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1835 * is assumed to be a power-of-two. */
1836 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1837 unsigned int tiling_mode,
1841 if (tiling_mode != I915_TILING_NONE) {
1842 unsigned int tile_rows, tiles;
1847 tiles = *x / (512/cpp);
1850 return tile_rows * pitch * 8 + tiles * 4096;
1852 unsigned int offset;
1854 offset = *y * pitch + *x * cpp;
1856 *x = (offset & 4095) / cpp;
1857 return offset & -4096;
1861 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1864 struct drm_device *dev = crtc->dev;
1865 struct drm_i915_private *dev_priv = dev->dev_private;
1866 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1867 struct intel_framebuffer *intel_fb;
1868 struct drm_i915_gem_object *obj;
1869 int plane = intel_crtc->plane;
1870 unsigned long linear_offset;
1879 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1883 intel_fb = to_intel_framebuffer(fb);
1884 obj = intel_fb->obj;
1886 reg = DSPCNTR(plane);
1887 dspcntr = I915_READ(reg);
1888 /* Mask out pixel format bits in case we change it */
1889 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1890 switch (fb->pixel_format) {
1892 dspcntr |= DISPPLANE_8BPP;
1894 case DRM_FORMAT_XRGB1555:
1895 case DRM_FORMAT_ARGB1555:
1896 dspcntr |= DISPPLANE_BGRX555;
1898 case DRM_FORMAT_RGB565:
1899 dspcntr |= DISPPLANE_BGRX565;
1901 case DRM_FORMAT_XRGB8888:
1902 case DRM_FORMAT_ARGB8888:
1903 dspcntr |= DISPPLANE_BGRX888;
1905 case DRM_FORMAT_XBGR8888:
1906 case DRM_FORMAT_ABGR8888:
1907 dspcntr |= DISPPLANE_RGBX888;
1909 case DRM_FORMAT_XRGB2101010:
1910 case DRM_FORMAT_ARGB2101010:
1911 dspcntr |= DISPPLANE_BGRX101010;
1913 case DRM_FORMAT_XBGR2101010:
1914 case DRM_FORMAT_ABGR2101010:
1915 dspcntr |= DISPPLANE_RGBX101010;
1921 if (INTEL_INFO(dev)->gen >= 4) {
1922 if (obj->tiling_mode != I915_TILING_NONE)
1923 dspcntr |= DISPPLANE_TILED;
1925 dspcntr &= ~DISPPLANE_TILED;
1929 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1931 I915_WRITE(reg, dspcntr);
1933 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1935 if (INTEL_INFO(dev)->gen >= 4) {
1936 intel_crtc->dspaddr_offset =
1937 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1938 fb->bits_per_pixel / 8,
1940 linear_offset -= intel_crtc->dspaddr_offset;
1942 intel_crtc->dspaddr_offset = linear_offset;
1945 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
1946 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
1947 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1948 if (INTEL_INFO(dev)->gen >= 4) {
1949 I915_MODIFY_DISPBASE(DSPSURF(plane),
1950 obj->gtt_offset + intel_crtc->dspaddr_offset);
1951 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1952 I915_WRITE(DSPLINOFF(plane), linear_offset);
1954 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
1960 static int ironlake_update_plane(struct drm_crtc *crtc,
1961 struct drm_framebuffer *fb, int x, int y)
1963 struct drm_device *dev = crtc->dev;
1964 struct drm_i915_private *dev_priv = dev->dev_private;
1965 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1966 struct intel_framebuffer *intel_fb;
1967 struct drm_i915_gem_object *obj;
1968 int plane = intel_crtc->plane;
1969 unsigned long linear_offset;
1979 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1983 intel_fb = to_intel_framebuffer(fb);
1984 obj = intel_fb->obj;
1986 reg = DSPCNTR(plane);
1987 dspcntr = I915_READ(reg);
1988 /* Mask out pixel format bits in case we change it */
1989 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1990 switch (fb->pixel_format) {
1992 dspcntr |= DISPPLANE_8BPP;
1994 case DRM_FORMAT_RGB565:
1995 dspcntr |= DISPPLANE_BGRX565;
1997 case DRM_FORMAT_XRGB8888:
1998 case DRM_FORMAT_ARGB8888:
1999 dspcntr |= DISPPLANE_BGRX888;
2001 case DRM_FORMAT_XBGR8888:
2002 case DRM_FORMAT_ABGR8888:
2003 dspcntr |= DISPPLANE_RGBX888;
2005 case DRM_FORMAT_XRGB2101010:
2006 case DRM_FORMAT_ARGB2101010:
2007 dspcntr |= DISPPLANE_BGRX101010;
2009 case DRM_FORMAT_XBGR2101010:
2010 case DRM_FORMAT_ABGR2101010:
2011 dspcntr |= DISPPLANE_RGBX101010;
2017 if (obj->tiling_mode != I915_TILING_NONE)
2018 dspcntr |= DISPPLANE_TILED;
2020 dspcntr &= ~DISPPLANE_TILED;
2023 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2025 I915_WRITE(reg, dspcntr);
2027 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2028 intel_crtc->dspaddr_offset =
2029 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2030 fb->bits_per_pixel / 8,
2032 linear_offset -= intel_crtc->dspaddr_offset;
2034 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2035 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2036 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2037 I915_MODIFY_DISPBASE(DSPSURF(plane),
2038 obj->gtt_offset + intel_crtc->dspaddr_offset);
2039 if (IS_HASWELL(dev)) {
2040 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2042 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2043 I915_WRITE(DSPLINOFF(plane), linear_offset);
2050 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2052 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2053 int x, int y, enum mode_set_atomic state)
2055 struct drm_device *dev = crtc->dev;
2056 struct drm_i915_private *dev_priv = dev->dev_private;
2058 if (dev_priv->display.disable_fbc)
2059 dev_priv->display.disable_fbc(dev);
2060 intel_increase_pllclock(crtc);
2062 return dev_priv->display.update_plane(crtc, fb, x, y);
2065 void intel_display_handle_reset(struct drm_device *dev)
2067 struct drm_i915_private *dev_priv = dev->dev_private;
2068 struct drm_crtc *crtc;
2071 * Flips in the rings have been nuked by the reset,
2072 * so complete all pending flips so that user space
2073 * will get its events and not get stuck.
2075 * Also update the base address of all primary
2076 * planes to the the last fb to make sure we're
2077 * showing the correct fb after a reset.
2079 * Need to make two loops over the crtcs so that we
2080 * don't try to grab a crtc mutex before the
2081 * pending_flip_queue really got woken up.
2084 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2085 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2086 enum plane plane = intel_crtc->plane;
2088 intel_prepare_page_flip(dev, plane);
2089 intel_finish_page_flip_plane(dev, plane);
2092 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2093 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2095 mutex_lock(&crtc->mutex);
2096 if (intel_crtc->active)
2097 dev_priv->display.update_plane(crtc, crtc->fb,
2099 mutex_unlock(&crtc->mutex);
2104 intel_finish_fb(struct drm_framebuffer *old_fb)
2106 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2107 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2108 bool was_interruptible = dev_priv->mm.interruptible;
2111 /* Big Hammer, we also need to ensure that any pending
2112 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2113 * current scanout is retired before unpinning the old
2116 * This should only fail upon a hung GPU, in which case we
2117 * can safely continue.
2119 dev_priv->mm.interruptible = false;
2120 ret = i915_gem_object_finish_gpu(obj);
2121 dev_priv->mm.interruptible = was_interruptible;
2126 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2128 struct drm_device *dev = crtc->dev;
2129 struct drm_i915_master_private *master_priv;
2130 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2132 if (!dev->primary->master)
2135 master_priv = dev->primary->master->driver_priv;
2136 if (!master_priv->sarea_priv)
2139 switch (intel_crtc->pipe) {
2141 master_priv->sarea_priv->pipeA_x = x;
2142 master_priv->sarea_priv->pipeA_y = y;
2145 master_priv->sarea_priv->pipeB_x = x;
2146 master_priv->sarea_priv->pipeB_y = y;
2154 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2155 struct drm_framebuffer *fb)
2157 struct drm_device *dev = crtc->dev;
2158 struct drm_i915_private *dev_priv = dev->dev_private;
2159 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2160 struct drm_framebuffer *old_fb;
2165 DRM_ERROR("No FB bound\n");
2169 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2170 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2171 plane_name(intel_crtc->plane),
2172 INTEL_INFO(dev)->num_pipes);
2176 mutex_lock(&dev->struct_mutex);
2177 ret = intel_pin_and_fence_fb_obj(dev,
2178 to_intel_framebuffer(fb)->obj,
2181 mutex_unlock(&dev->struct_mutex);
2182 DRM_ERROR("pin & fence failed\n");
2186 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2188 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2189 mutex_unlock(&dev->struct_mutex);
2190 DRM_ERROR("failed to update base address\n");
2200 if (intel_crtc->active && old_fb != fb)
2201 intel_wait_for_vblank(dev, intel_crtc->pipe);
2202 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2205 intel_update_fbc(dev);
2206 mutex_unlock(&dev->struct_mutex);
2208 intel_crtc_update_sarea_pos(crtc, x, y);
2213 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2215 struct drm_device *dev = crtc->dev;
2216 struct drm_i915_private *dev_priv = dev->dev_private;
2217 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2218 int pipe = intel_crtc->pipe;
2221 /* enable normal train */
2222 reg = FDI_TX_CTL(pipe);
2223 temp = I915_READ(reg);
2224 if (IS_IVYBRIDGE(dev)) {
2225 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2226 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2228 temp &= ~FDI_LINK_TRAIN_NONE;
2229 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2231 I915_WRITE(reg, temp);
2233 reg = FDI_RX_CTL(pipe);
2234 temp = I915_READ(reg);
2235 if (HAS_PCH_CPT(dev)) {
2236 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2237 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2239 temp &= ~FDI_LINK_TRAIN_NONE;
2240 temp |= FDI_LINK_TRAIN_NONE;
2242 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2244 /* wait one idle pattern time */
2248 /* IVB wants error correction enabled */
2249 if (IS_IVYBRIDGE(dev))
2250 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2251 FDI_FE_ERRC_ENABLE);
2254 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2256 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2259 static void ivb_modeset_global_resources(struct drm_device *dev)
2261 struct drm_i915_private *dev_priv = dev->dev_private;
2262 struct intel_crtc *pipe_B_crtc =
2263 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2264 struct intel_crtc *pipe_C_crtc =
2265 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2269 * When everything is off disable fdi C so that we could enable fdi B
2270 * with all lanes. Note that we don't care about enabled pipes without
2271 * an enabled pch encoder.
2273 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2274 !pipe_has_enabled_pch(pipe_C_crtc)) {
2275 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2276 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2278 temp = I915_READ(SOUTH_CHICKEN1);
2279 temp &= ~FDI_BC_BIFURCATION_SELECT;
2280 DRM_DEBUG_KMS("disabling fdi C rx\n");
2281 I915_WRITE(SOUTH_CHICKEN1, temp);
2285 /* The FDI link training functions for ILK/Ibexpeak. */
2286 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2288 struct drm_device *dev = crtc->dev;
2289 struct drm_i915_private *dev_priv = dev->dev_private;
2290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2291 int pipe = intel_crtc->pipe;
2292 int plane = intel_crtc->plane;
2293 u32 reg, temp, tries;
2295 /* FDI needs bits from pipe & plane first */
2296 assert_pipe_enabled(dev_priv, pipe);
2297 assert_plane_enabled(dev_priv, plane);
2299 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2301 reg = FDI_RX_IMR(pipe);
2302 temp = I915_READ(reg);
2303 temp &= ~FDI_RX_SYMBOL_LOCK;
2304 temp &= ~FDI_RX_BIT_LOCK;
2305 I915_WRITE(reg, temp);
2309 /* enable CPU FDI TX and PCH FDI RX */
2310 reg = FDI_TX_CTL(pipe);
2311 temp = I915_READ(reg);
2312 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2313 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2314 temp &= ~FDI_LINK_TRAIN_NONE;
2315 temp |= FDI_LINK_TRAIN_PATTERN_1;
2316 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2318 reg = FDI_RX_CTL(pipe);
2319 temp = I915_READ(reg);
2320 temp &= ~FDI_LINK_TRAIN_NONE;
2321 temp |= FDI_LINK_TRAIN_PATTERN_1;
2322 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2327 /* Ironlake workaround, enable clock pointer after FDI enable*/
2328 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2329 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2330 FDI_RX_PHASE_SYNC_POINTER_EN);
2332 reg = FDI_RX_IIR(pipe);
2333 for (tries = 0; tries < 5; tries++) {
2334 temp = I915_READ(reg);
2335 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2337 if ((temp & FDI_RX_BIT_LOCK)) {
2338 DRM_DEBUG_KMS("FDI train 1 done.\n");
2339 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2344 DRM_ERROR("FDI train 1 fail!\n");
2347 reg = FDI_TX_CTL(pipe);
2348 temp = I915_READ(reg);
2349 temp &= ~FDI_LINK_TRAIN_NONE;
2350 temp |= FDI_LINK_TRAIN_PATTERN_2;
2351 I915_WRITE(reg, temp);
2353 reg = FDI_RX_CTL(pipe);
2354 temp = I915_READ(reg);
2355 temp &= ~FDI_LINK_TRAIN_NONE;
2356 temp |= FDI_LINK_TRAIN_PATTERN_2;
2357 I915_WRITE(reg, temp);
2362 reg = FDI_RX_IIR(pipe);
2363 for (tries = 0; tries < 5; tries++) {
2364 temp = I915_READ(reg);
2365 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2367 if (temp & FDI_RX_SYMBOL_LOCK) {
2368 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2369 DRM_DEBUG_KMS("FDI train 2 done.\n");
2374 DRM_ERROR("FDI train 2 fail!\n");
2376 DRM_DEBUG_KMS("FDI train done\n");
2380 static const int snb_b_fdi_train_param[] = {
2381 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2382 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2383 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2384 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2387 /* The FDI link training functions for SNB/Cougarpoint. */
2388 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2390 struct drm_device *dev = crtc->dev;
2391 struct drm_i915_private *dev_priv = dev->dev_private;
2392 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2393 int pipe = intel_crtc->pipe;
2394 u32 reg, temp, i, retry;
2396 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2398 reg = FDI_RX_IMR(pipe);
2399 temp = I915_READ(reg);
2400 temp &= ~FDI_RX_SYMBOL_LOCK;
2401 temp &= ~FDI_RX_BIT_LOCK;
2402 I915_WRITE(reg, temp);
2407 /* enable CPU FDI TX and PCH FDI RX */
2408 reg = FDI_TX_CTL(pipe);
2409 temp = I915_READ(reg);
2410 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2411 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2412 temp &= ~FDI_LINK_TRAIN_NONE;
2413 temp |= FDI_LINK_TRAIN_PATTERN_1;
2414 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2416 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2417 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2419 I915_WRITE(FDI_RX_MISC(pipe),
2420 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2422 reg = FDI_RX_CTL(pipe);
2423 temp = I915_READ(reg);
2424 if (HAS_PCH_CPT(dev)) {
2425 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2426 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2428 temp &= ~FDI_LINK_TRAIN_NONE;
2429 temp |= FDI_LINK_TRAIN_PATTERN_1;
2431 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2436 for (i = 0; i < 4; i++) {
2437 reg = FDI_TX_CTL(pipe);
2438 temp = I915_READ(reg);
2439 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2440 temp |= snb_b_fdi_train_param[i];
2441 I915_WRITE(reg, temp);
2446 for (retry = 0; retry < 5; retry++) {
2447 reg = FDI_RX_IIR(pipe);
2448 temp = I915_READ(reg);
2449 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2450 if (temp & FDI_RX_BIT_LOCK) {
2451 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2452 DRM_DEBUG_KMS("FDI train 1 done.\n");
2461 DRM_ERROR("FDI train 1 fail!\n");
2464 reg = FDI_TX_CTL(pipe);
2465 temp = I915_READ(reg);
2466 temp &= ~FDI_LINK_TRAIN_NONE;
2467 temp |= FDI_LINK_TRAIN_PATTERN_2;
2469 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2471 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2473 I915_WRITE(reg, temp);
2475 reg = FDI_RX_CTL(pipe);
2476 temp = I915_READ(reg);
2477 if (HAS_PCH_CPT(dev)) {
2478 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2479 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2481 temp &= ~FDI_LINK_TRAIN_NONE;
2482 temp |= FDI_LINK_TRAIN_PATTERN_2;
2484 I915_WRITE(reg, temp);
2489 for (i = 0; i < 4; i++) {
2490 reg = FDI_TX_CTL(pipe);
2491 temp = I915_READ(reg);
2492 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2493 temp |= snb_b_fdi_train_param[i];
2494 I915_WRITE(reg, temp);
2499 for (retry = 0; retry < 5; retry++) {
2500 reg = FDI_RX_IIR(pipe);
2501 temp = I915_READ(reg);
2502 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2503 if (temp & FDI_RX_SYMBOL_LOCK) {
2504 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2505 DRM_DEBUG_KMS("FDI train 2 done.\n");
2514 DRM_ERROR("FDI train 2 fail!\n");
2516 DRM_DEBUG_KMS("FDI train done.\n");
2519 /* Manual link training for Ivy Bridge A0 parts */
2520 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2522 struct drm_device *dev = crtc->dev;
2523 struct drm_i915_private *dev_priv = dev->dev_private;
2524 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2525 int pipe = intel_crtc->pipe;
2528 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2530 reg = FDI_RX_IMR(pipe);
2531 temp = I915_READ(reg);
2532 temp &= ~FDI_RX_SYMBOL_LOCK;
2533 temp &= ~FDI_RX_BIT_LOCK;
2534 I915_WRITE(reg, temp);
2539 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2540 I915_READ(FDI_RX_IIR(pipe)));
2542 /* enable CPU FDI TX and PCH FDI RX */
2543 reg = FDI_TX_CTL(pipe);
2544 temp = I915_READ(reg);
2545 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2546 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2547 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2548 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2549 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2550 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2551 temp |= FDI_COMPOSITE_SYNC;
2552 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2554 I915_WRITE(FDI_RX_MISC(pipe),
2555 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2557 reg = FDI_RX_CTL(pipe);
2558 temp = I915_READ(reg);
2559 temp &= ~FDI_LINK_TRAIN_AUTO;
2560 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2561 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2562 temp |= FDI_COMPOSITE_SYNC;
2563 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2568 for (i = 0; i < 4; i++) {
2569 reg = FDI_TX_CTL(pipe);
2570 temp = I915_READ(reg);
2571 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2572 temp |= snb_b_fdi_train_param[i];
2573 I915_WRITE(reg, temp);
2578 reg = FDI_RX_IIR(pipe);
2579 temp = I915_READ(reg);
2580 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2582 if (temp & FDI_RX_BIT_LOCK ||
2583 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2584 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2585 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2590 DRM_ERROR("FDI train 1 fail!\n");
2593 reg = FDI_TX_CTL(pipe);
2594 temp = I915_READ(reg);
2595 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2596 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2597 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2598 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2599 I915_WRITE(reg, temp);
2601 reg = FDI_RX_CTL(pipe);
2602 temp = I915_READ(reg);
2603 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2604 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2605 I915_WRITE(reg, temp);
2610 for (i = 0; i < 4; i++) {
2611 reg = FDI_TX_CTL(pipe);
2612 temp = I915_READ(reg);
2613 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2614 temp |= snb_b_fdi_train_param[i];
2615 I915_WRITE(reg, temp);
2620 reg = FDI_RX_IIR(pipe);
2621 temp = I915_READ(reg);
2622 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2624 if (temp & FDI_RX_SYMBOL_LOCK) {
2625 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2626 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2631 DRM_ERROR("FDI train 2 fail!\n");
2633 DRM_DEBUG_KMS("FDI train done.\n");
2636 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2638 struct drm_device *dev = intel_crtc->base.dev;
2639 struct drm_i915_private *dev_priv = dev->dev_private;
2640 int pipe = intel_crtc->pipe;
2644 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2645 reg = FDI_RX_CTL(pipe);
2646 temp = I915_READ(reg);
2647 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2648 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2649 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2650 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2655 /* Switch from Rawclk to PCDclk */
2656 temp = I915_READ(reg);
2657 I915_WRITE(reg, temp | FDI_PCDCLK);
2662 /* Enable CPU FDI TX PLL, always on for Ironlake */
2663 reg = FDI_TX_CTL(pipe);
2664 temp = I915_READ(reg);
2665 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2666 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2673 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2675 struct drm_device *dev = intel_crtc->base.dev;
2676 struct drm_i915_private *dev_priv = dev->dev_private;
2677 int pipe = intel_crtc->pipe;
2680 /* Switch from PCDclk to Rawclk */
2681 reg = FDI_RX_CTL(pipe);
2682 temp = I915_READ(reg);
2683 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2685 /* Disable CPU FDI TX PLL */
2686 reg = FDI_TX_CTL(pipe);
2687 temp = I915_READ(reg);
2688 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2693 reg = FDI_RX_CTL(pipe);
2694 temp = I915_READ(reg);
2695 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2697 /* Wait for the clocks to turn off. */
2702 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2704 struct drm_device *dev = crtc->dev;
2705 struct drm_i915_private *dev_priv = dev->dev_private;
2706 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2707 int pipe = intel_crtc->pipe;
2710 /* disable CPU FDI tx and PCH FDI rx */
2711 reg = FDI_TX_CTL(pipe);
2712 temp = I915_READ(reg);
2713 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2716 reg = FDI_RX_CTL(pipe);
2717 temp = I915_READ(reg);
2718 temp &= ~(0x7 << 16);
2719 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2720 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2725 /* Ironlake workaround, disable clock pointer after downing FDI */
2726 if (HAS_PCH_IBX(dev)) {
2727 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2730 /* still set train pattern 1 */
2731 reg = FDI_TX_CTL(pipe);
2732 temp = I915_READ(reg);
2733 temp &= ~FDI_LINK_TRAIN_NONE;
2734 temp |= FDI_LINK_TRAIN_PATTERN_1;
2735 I915_WRITE(reg, temp);
2737 reg = FDI_RX_CTL(pipe);
2738 temp = I915_READ(reg);
2739 if (HAS_PCH_CPT(dev)) {
2740 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2741 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2743 temp &= ~FDI_LINK_TRAIN_NONE;
2744 temp |= FDI_LINK_TRAIN_PATTERN_1;
2746 /* BPC in FDI rx is consistent with that in PIPECONF */
2747 temp &= ~(0x07 << 16);
2748 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2749 I915_WRITE(reg, temp);
2755 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2757 struct drm_device *dev = crtc->dev;
2758 struct drm_i915_private *dev_priv = dev->dev_private;
2759 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2760 unsigned long flags;
2763 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2764 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2767 spin_lock_irqsave(&dev->event_lock, flags);
2768 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2769 spin_unlock_irqrestore(&dev->event_lock, flags);
2774 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2776 struct drm_device *dev = crtc->dev;
2777 struct drm_i915_private *dev_priv = dev->dev_private;
2779 if (crtc->fb == NULL)
2782 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2784 wait_event(dev_priv->pending_flip_queue,
2785 !intel_crtc_has_pending_flip(crtc));
2787 mutex_lock(&dev->struct_mutex);
2788 intel_finish_fb(crtc->fb);
2789 mutex_unlock(&dev->struct_mutex);
2792 /* Program iCLKIP clock to the desired frequency */
2793 static void lpt_program_iclkip(struct drm_crtc *crtc)
2795 struct drm_device *dev = crtc->dev;
2796 struct drm_i915_private *dev_priv = dev->dev_private;
2797 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2800 mutex_lock(&dev_priv->dpio_lock);
2802 /* It is necessary to ungate the pixclk gate prior to programming
2803 * the divisors, and gate it back when it is done.
2805 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2807 /* Disable SSCCTL */
2808 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2809 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2813 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2814 if (crtc->mode.clock == 20000) {
2819 /* The iCLK virtual clock root frequency is in MHz,
2820 * but the crtc->mode.clock in in KHz. To get the divisors,
2821 * it is necessary to divide one by another, so we
2822 * convert the virtual clock precision to KHz here for higher
2825 u32 iclk_virtual_root_freq = 172800 * 1000;
2826 u32 iclk_pi_range = 64;
2827 u32 desired_divisor, msb_divisor_value, pi_value;
2829 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2830 msb_divisor_value = desired_divisor / iclk_pi_range;
2831 pi_value = desired_divisor % iclk_pi_range;
2834 divsel = msb_divisor_value - 2;
2835 phaseinc = pi_value;
2838 /* This should not happen with any sane values */
2839 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2840 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2841 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2842 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2844 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2851 /* Program SSCDIVINTPHASE6 */
2852 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2853 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2854 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2855 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2856 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2857 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2858 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2859 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2861 /* Program SSCAUXDIV */
2862 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2863 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2864 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2865 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2867 /* Enable modulator and associated divider */
2868 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2869 temp &= ~SBI_SSCCTL_DISABLE;
2870 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2872 /* Wait for initialization time */
2875 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2877 mutex_unlock(&dev_priv->dpio_lock);
2880 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2881 enum pipe pch_transcoder)
2883 struct drm_device *dev = crtc->base.dev;
2884 struct drm_i915_private *dev_priv = dev->dev_private;
2885 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2887 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2888 I915_READ(HTOTAL(cpu_transcoder)));
2889 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2890 I915_READ(HBLANK(cpu_transcoder)));
2891 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2892 I915_READ(HSYNC(cpu_transcoder)));
2894 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2895 I915_READ(VTOTAL(cpu_transcoder)));
2896 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2897 I915_READ(VBLANK(cpu_transcoder)));
2898 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2899 I915_READ(VSYNC(cpu_transcoder)));
2900 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2901 I915_READ(VSYNCSHIFT(cpu_transcoder)));
2905 * Enable PCH resources required for PCH ports:
2907 * - FDI training & RX/TX
2908 * - update transcoder timings
2909 * - DP transcoding bits
2912 static void ironlake_pch_enable(struct drm_crtc *crtc)
2914 struct drm_device *dev = crtc->dev;
2915 struct drm_i915_private *dev_priv = dev->dev_private;
2916 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2917 int pipe = intel_crtc->pipe;
2920 assert_pch_transcoder_disabled(dev_priv, pipe);
2922 /* Write the TU size bits before fdi link training, so that error
2923 * detection works. */
2924 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2925 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2927 /* For PCH output, training FDI link */
2928 dev_priv->display.fdi_link_train(crtc);
2930 /* XXX: pch pll's can be enabled any time before we enable the PCH
2931 * transcoder, and we actually should do this to not upset any PCH
2932 * transcoder that already use the clock when we share it.
2934 * Note that enable_shared_dpll tries to do the right thing, but
2935 * get_shared_dpll unconditionally resets the pll - we need that to have
2936 * the right LVDS enable sequence. */
2937 ironlake_enable_shared_dpll(intel_crtc);
2939 if (HAS_PCH_CPT(dev)) {
2942 temp = I915_READ(PCH_DPLL_SEL);
2943 temp |= TRANS_DPLL_ENABLE(pipe);
2944 sel = TRANS_DPLLB_SEL(pipe);
2945 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
2949 I915_WRITE(PCH_DPLL_SEL, temp);
2952 /* set transcoder timing, panel must allow it */
2953 assert_panel_unlocked(dev_priv, pipe);
2954 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
2956 intel_fdi_normal_train(crtc);
2958 /* For PCH DP, enable TRANS_DP_CTL */
2959 if (HAS_PCH_CPT(dev) &&
2960 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2961 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2962 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
2963 reg = TRANS_DP_CTL(pipe);
2964 temp = I915_READ(reg);
2965 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2966 TRANS_DP_SYNC_MASK |
2968 temp |= (TRANS_DP_OUTPUT_ENABLE |
2969 TRANS_DP_ENH_FRAMING);
2970 temp |= bpc << 9; /* same format but at 11:9 */
2972 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2973 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2974 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2975 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2977 switch (intel_trans_dp_port_sel(crtc)) {
2979 temp |= TRANS_DP_PORT_SEL_B;
2982 temp |= TRANS_DP_PORT_SEL_C;
2985 temp |= TRANS_DP_PORT_SEL_D;
2991 I915_WRITE(reg, temp);
2994 ironlake_enable_pch_transcoder(dev_priv, pipe);
2997 static void lpt_pch_enable(struct drm_crtc *crtc)
2999 struct drm_device *dev = crtc->dev;
3000 struct drm_i915_private *dev_priv = dev->dev_private;
3001 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3002 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3004 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3006 lpt_program_iclkip(crtc);
3008 /* Set transcoder timing. */
3009 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3011 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3014 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3016 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3021 if (pll->refcount == 0) {
3022 WARN(1, "bad %s refcount\n", pll->name);
3026 if (--pll->refcount == 0) {
3028 WARN_ON(pll->active);
3031 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3034 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, u32 dpll, u32 fp)
3036 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3037 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3038 enum intel_dpll_id i;
3041 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3042 crtc->base.base.id, pll->name);
3043 intel_put_shared_dpll(crtc);
3046 if (HAS_PCH_IBX(dev_priv->dev)) {
3047 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3049 pll = &dev_priv->shared_dplls[i];
3051 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3052 crtc->base.base.id, pll->name);
3057 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3058 pll = &dev_priv->shared_dplls[i];
3060 /* Only want to check enabled timings first */
3061 if (pll->refcount == 0)
3064 if (dpll == (I915_READ(PCH_DPLL(pll->id)) & 0x7fffffff) &&
3065 fp == I915_READ(PCH_FP0(pll->id))) {
3066 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3068 pll->name, pll->refcount, pll->active);
3074 /* Ok no matching timings, maybe there's a free one? */
3075 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3076 pll = &dev_priv->shared_dplls[i];
3077 if (pll->refcount == 0) {
3078 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3079 crtc->base.base.id, pll->name);
3087 crtc->config.shared_dpll = i;
3088 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3089 pipe_name(crtc->pipe));
3091 if (pll->active == 0) {
3092 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3093 sizeof(pll->hw_state));
3095 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3097 assert_shared_dpll_disabled(dev_priv, pll);
3099 /* Wait for the clocks to stabilize before rewriting the regs */
3100 I915_WRITE(PCH_DPLL(pll->id), dpll & ~DPLL_VCO_ENABLE);
3101 POSTING_READ(PCH_DPLL(pll->id));
3104 I915_WRITE(PCH_FP0(pll->id), fp);
3105 I915_WRITE(PCH_DPLL(pll->id), dpll & ~DPLL_VCO_ENABLE);
3112 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3114 struct drm_i915_private *dev_priv = dev->dev_private;
3115 int dslreg = PIPEDSL(pipe);
3118 temp = I915_READ(dslreg);
3120 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3121 if (wait_for(I915_READ(dslreg) != temp, 5))
3122 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3126 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3128 struct drm_device *dev = crtc->base.dev;
3129 struct drm_i915_private *dev_priv = dev->dev_private;
3130 int pipe = crtc->pipe;
3132 if (crtc->config.pch_pfit.size) {
3133 /* Force use of hard-coded filter coefficients
3134 * as some pre-programmed values are broken,
3137 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3138 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3139 PF_PIPE_SEL_IVB(pipe));
3141 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3142 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3143 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3147 static void intel_enable_planes(struct drm_crtc *crtc)
3149 struct drm_device *dev = crtc->dev;
3150 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3151 struct intel_plane *intel_plane;
3153 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3154 if (intel_plane->pipe == pipe)
3155 intel_plane_restore(&intel_plane->base);
3158 static void intel_disable_planes(struct drm_crtc *crtc)
3160 struct drm_device *dev = crtc->dev;
3161 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3162 struct intel_plane *intel_plane;
3164 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3165 if (intel_plane->pipe == pipe)
3166 intel_plane_disable(&intel_plane->base);
3169 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3171 struct drm_device *dev = crtc->dev;
3172 struct drm_i915_private *dev_priv = dev->dev_private;
3173 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3174 struct intel_encoder *encoder;
3175 int pipe = intel_crtc->pipe;
3176 int plane = intel_crtc->plane;
3179 WARN_ON(!crtc->enabled);
3181 if (intel_crtc->active)
3184 intel_crtc->active = true;
3186 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3187 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3189 intel_update_watermarks(dev);
3191 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3192 temp = I915_READ(PCH_LVDS);
3193 if ((temp & LVDS_PORT_EN) == 0)
3194 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3198 if (intel_crtc->config.has_pch_encoder) {
3199 /* Note: FDI PLL enabling _must_ be done before we enable the
3200 * cpu pipes, hence this is separate from all the other fdi/pch
3202 ironlake_fdi_pll_enable(intel_crtc);
3204 assert_fdi_tx_disabled(dev_priv, pipe);
3205 assert_fdi_rx_disabled(dev_priv, pipe);
3208 for_each_encoder_on_crtc(dev, crtc, encoder)
3209 if (encoder->pre_enable)
3210 encoder->pre_enable(encoder);
3212 ironlake_pfit_enable(intel_crtc);
3215 * On ILK+ LUT must be loaded before the pipe is running but with
3218 intel_crtc_load_lut(crtc);
3220 intel_enable_pipe(dev_priv, pipe,
3221 intel_crtc->config.has_pch_encoder);
3222 intel_enable_plane(dev_priv, plane, pipe);
3223 intel_enable_planes(crtc);
3224 intel_crtc_update_cursor(crtc, true);
3226 if (intel_crtc->config.has_pch_encoder)
3227 ironlake_pch_enable(crtc);
3229 mutex_lock(&dev->struct_mutex);
3230 intel_update_fbc(dev);
3231 mutex_unlock(&dev->struct_mutex);
3233 for_each_encoder_on_crtc(dev, crtc, encoder)
3234 encoder->enable(encoder);
3236 if (HAS_PCH_CPT(dev))
3237 cpt_verify_modeset(dev, intel_crtc->pipe);
3240 * There seems to be a race in PCH platform hw (at least on some
3241 * outputs) where an enabled pipe still completes any pageflip right
3242 * away (as if the pipe is off) instead of waiting for vblank. As soon
3243 * as the first vblank happend, everything works as expected. Hence just
3244 * wait for one vblank before returning to avoid strange things
3247 intel_wait_for_vblank(dev, intel_crtc->pipe);
3250 /* IPS only exists on ULT machines and is tied to pipe A. */
3251 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3253 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3256 static void hsw_enable_ips(struct intel_crtc *crtc)
3258 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3260 if (!crtc->config.ips_enabled)
3263 /* We can only enable IPS after we enable a plane and wait for a vblank.
3264 * We guarantee that the plane is enabled by calling intel_enable_ips
3265 * only after intel_enable_plane. And intel_enable_plane already waits
3266 * for a vblank, so all we need to do here is to enable the IPS bit. */
3267 assert_plane_enabled(dev_priv, crtc->plane);
3268 I915_WRITE(IPS_CTL, IPS_ENABLE);
3271 static void hsw_disable_ips(struct intel_crtc *crtc)
3273 struct drm_device *dev = crtc->base.dev;
3274 struct drm_i915_private *dev_priv = dev->dev_private;
3276 if (!crtc->config.ips_enabled)
3279 assert_plane_enabled(dev_priv, crtc->plane);
3280 I915_WRITE(IPS_CTL, 0);
3282 /* We need to wait for a vblank before we can disable the plane. */
3283 intel_wait_for_vblank(dev, crtc->pipe);
3286 static void haswell_crtc_enable(struct drm_crtc *crtc)
3288 struct drm_device *dev = crtc->dev;
3289 struct drm_i915_private *dev_priv = dev->dev_private;
3290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3291 struct intel_encoder *encoder;
3292 int pipe = intel_crtc->pipe;
3293 int plane = intel_crtc->plane;
3295 WARN_ON(!crtc->enabled);
3297 if (intel_crtc->active)
3300 intel_crtc->active = true;
3302 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3303 if (intel_crtc->config.has_pch_encoder)
3304 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3306 intel_update_watermarks(dev);
3308 if (intel_crtc->config.has_pch_encoder)
3309 dev_priv->display.fdi_link_train(crtc);
3311 for_each_encoder_on_crtc(dev, crtc, encoder)
3312 if (encoder->pre_enable)
3313 encoder->pre_enable(encoder);
3315 intel_ddi_enable_pipe_clock(intel_crtc);
3317 ironlake_pfit_enable(intel_crtc);
3320 * On ILK+ LUT must be loaded before the pipe is running but with
3323 intel_crtc_load_lut(crtc);
3325 intel_ddi_set_pipe_settings(crtc);
3326 intel_ddi_enable_transcoder_func(crtc);
3328 intel_enable_pipe(dev_priv, pipe,
3329 intel_crtc->config.has_pch_encoder);
3330 intel_enable_plane(dev_priv, plane, pipe);
3331 intel_enable_planes(crtc);
3332 intel_crtc_update_cursor(crtc, true);
3334 hsw_enable_ips(intel_crtc);
3336 if (intel_crtc->config.has_pch_encoder)
3337 lpt_pch_enable(crtc);
3339 mutex_lock(&dev->struct_mutex);
3340 intel_update_fbc(dev);
3341 mutex_unlock(&dev->struct_mutex);
3343 for_each_encoder_on_crtc(dev, crtc, encoder)
3344 encoder->enable(encoder);
3347 * There seems to be a race in PCH platform hw (at least on some
3348 * outputs) where an enabled pipe still completes any pageflip right
3349 * away (as if the pipe is off) instead of waiting for vblank. As soon
3350 * as the first vblank happend, everything works as expected. Hence just
3351 * wait for one vblank before returning to avoid strange things
3354 intel_wait_for_vblank(dev, intel_crtc->pipe);
3357 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3359 struct drm_device *dev = crtc->base.dev;
3360 struct drm_i915_private *dev_priv = dev->dev_private;
3361 int pipe = crtc->pipe;
3363 /* To avoid upsetting the power well on haswell only disable the pfit if
3364 * it's in use. The hw state code will make sure we get this right. */
3365 if (crtc->config.pch_pfit.size) {
3366 I915_WRITE(PF_CTL(pipe), 0);
3367 I915_WRITE(PF_WIN_POS(pipe), 0);
3368 I915_WRITE(PF_WIN_SZ(pipe), 0);
3372 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3374 struct drm_device *dev = crtc->dev;
3375 struct drm_i915_private *dev_priv = dev->dev_private;
3376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3377 struct intel_encoder *encoder;
3378 int pipe = intel_crtc->pipe;
3379 int plane = intel_crtc->plane;
3383 if (!intel_crtc->active)
3386 for_each_encoder_on_crtc(dev, crtc, encoder)
3387 encoder->disable(encoder);
3389 intel_crtc_wait_for_pending_flips(crtc);
3390 drm_vblank_off(dev, pipe);
3392 if (dev_priv->cfb_plane == plane)
3393 intel_disable_fbc(dev);
3395 intel_crtc_update_cursor(crtc, false);
3396 intel_disable_planes(crtc);
3397 intel_disable_plane(dev_priv, plane, pipe);
3399 if (intel_crtc->config.has_pch_encoder)
3400 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3402 intel_disable_pipe(dev_priv, pipe);
3404 ironlake_pfit_disable(intel_crtc);
3406 for_each_encoder_on_crtc(dev, crtc, encoder)
3407 if (encoder->post_disable)
3408 encoder->post_disable(encoder);
3410 if (intel_crtc->config.has_pch_encoder) {
3411 ironlake_fdi_disable(crtc);
3413 ironlake_disable_pch_transcoder(dev_priv, pipe);
3414 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3416 if (HAS_PCH_CPT(dev)) {
3417 /* disable TRANS_DP_CTL */
3418 reg = TRANS_DP_CTL(pipe);
3419 temp = I915_READ(reg);
3420 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3421 TRANS_DP_PORT_SEL_MASK);
3422 temp |= TRANS_DP_PORT_SEL_NONE;
3423 I915_WRITE(reg, temp);
3425 /* disable DPLL_SEL */
3426 temp = I915_READ(PCH_DPLL_SEL);
3427 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3428 I915_WRITE(PCH_DPLL_SEL, temp);
3431 /* disable PCH DPLL */
3432 intel_disable_shared_dpll(intel_crtc);
3434 ironlake_fdi_pll_disable(intel_crtc);
3437 intel_crtc->active = false;
3438 intel_update_watermarks(dev);
3440 mutex_lock(&dev->struct_mutex);
3441 intel_update_fbc(dev);
3442 mutex_unlock(&dev->struct_mutex);
3445 static void haswell_crtc_disable(struct drm_crtc *crtc)
3447 struct drm_device *dev = crtc->dev;
3448 struct drm_i915_private *dev_priv = dev->dev_private;
3449 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3450 struct intel_encoder *encoder;
3451 int pipe = intel_crtc->pipe;
3452 int plane = intel_crtc->plane;
3453 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3455 if (!intel_crtc->active)
3458 for_each_encoder_on_crtc(dev, crtc, encoder)
3459 encoder->disable(encoder);
3461 intel_crtc_wait_for_pending_flips(crtc);
3462 drm_vblank_off(dev, pipe);
3464 /* FBC must be disabled before disabling the plane on HSW. */
3465 if (dev_priv->cfb_plane == plane)
3466 intel_disable_fbc(dev);
3468 hsw_disable_ips(intel_crtc);
3470 intel_crtc_update_cursor(crtc, false);
3471 intel_disable_planes(crtc);
3472 intel_disable_plane(dev_priv, plane, pipe);
3474 if (intel_crtc->config.has_pch_encoder)
3475 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3476 intel_disable_pipe(dev_priv, pipe);
3478 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3480 ironlake_pfit_disable(intel_crtc);
3482 intel_ddi_disable_pipe_clock(intel_crtc);
3484 for_each_encoder_on_crtc(dev, crtc, encoder)
3485 if (encoder->post_disable)
3486 encoder->post_disable(encoder);
3488 if (intel_crtc->config.has_pch_encoder) {
3489 lpt_disable_pch_transcoder(dev_priv);
3490 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3491 intel_ddi_fdi_disable(crtc);
3494 intel_crtc->active = false;
3495 intel_update_watermarks(dev);
3497 mutex_lock(&dev->struct_mutex);
3498 intel_update_fbc(dev);
3499 mutex_unlock(&dev->struct_mutex);
3502 static void ironlake_crtc_off(struct drm_crtc *crtc)
3504 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3505 intel_put_shared_dpll(intel_crtc);
3508 static void haswell_crtc_off(struct drm_crtc *crtc)
3510 intel_ddi_put_crtc_pll(crtc);
3513 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3515 if (!enable && intel_crtc->overlay) {
3516 struct drm_device *dev = intel_crtc->base.dev;
3517 struct drm_i915_private *dev_priv = dev->dev_private;
3519 mutex_lock(&dev->struct_mutex);
3520 dev_priv->mm.interruptible = false;
3521 (void) intel_overlay_switch_off(intel_crtc->overlay);
3522 dev_priv->mm.interruptible = true;
3523 mutex_unlock(&dev->struct_mutex);
3526 /* Let userspace switch the overlay on again. In most cases userspace
3527 * has to recompute where to put it anyway.
3532 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3533 * cursor plane briefly if not already running after enabling the display
3535 * This workaround avoids occasional blank screens when self refresh is
3539 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3541 u32 cntl = I915_READ(CURCNTR(pipe));
3543 if ((cntl & CURSOR_MODE) == 0) {
3544 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3546 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3547 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3548 intel_wait_for_vblank(dev_priv->dev, pipe);
3549 I915_WRITE(CURCNTR(pipe), cntl);
3550 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3551 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3555 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3557 struct drm_device *dev = crtc->base.dev;
3558 struct drm_i915_private *dev_priv = dev->dev_private;
3559 struct intel_crtc_config *pipe_config = &crtc->config;
3561 if (!crtc->config.gmch_pfit.control)
3565 * The panel fitter should only be adjusted whilst the pipe is disabled,
3566 * according to register description and PRM.
3568 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3569 assert_pipe_disabled(dev_priv, crtc->pipe);
3571 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3572 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3574 /* Border color in case we don't scale up to the full screen. Black by
3575 * default, change to something else for debugging. */
3576 I915_WRITE(BCLRPAT(crtc->pipe), 0);
3579 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3581 struct drm_device *dev = crtc->dev;
3582 struct drm_i915_private *dev_priv = dev->dev_private;
3583 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3584 struct intel_encoder *encoder;
3585 int pipe = intel_crtc->pipe;
3586 int plane = intel_crtc->plane;
3588 WARN_ON(!crtc->enabled);
3590 if (intel_crtc->active)
3593 intel_crtc->active = true;
3594 intel_update_watermarks(dev);
3596 mutex_lock(&dev_priv->dpio_lock);
3598 for_each_encoder_on_crtc(dev, crtc, encoder)
3599 if (encoder->pre_pll_enable)
3600 encoder->pre_pll_enable(encoder);
3602 intel_enable_pll(dev_priv, pipe);
3604 for_each_encoder_on_crtc(dev, crtc, encoder)
3605 if (encoder->pre_enable)
3606 encoder->pre_enable(encoder);
3608 /* VLV wants encoder enabling _before_ the pipe is up. */
3609 for_each_encoder_on_crtc(dev, crtc, encoder)
3610 encoder->enable(encoder);
3612 i9xx_pfit_enable(intel_crtc);
3614 intel_crtc_load_lut(crtc);
3616 intel_enable_pipe(dev_priv, pipe, false);
3617 intel_enable_plane(dev_priv, plane, pipe);
3618 intel_enable_planes(crtc);
3619 intel_crtc_update_cursor(crtc, true);
3621 intel_update_fbc(dev);
3623 mutex_unlock(&dev_priv->dpio_lock);
3626 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3628 struct drm_device *dev = crtc->dev;
3629 struct drm_i915_private *dev_priv = dev->dev_private;
3630 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3631 struct intel_encoder *encoder;
3632 int pipe = intel_crtc->pipe;
3633 int plane = intel_crtc->plane;
3635 WARN_ON(!crtc->enabled);
3637 if (intel_crtc->active)
3640 intel_crtc->active = true;
3641 intel_update_watermarks(dev);
3643 intel_enable_pll(dev_priv, pipe);
3645 for_each_encoder_on_crtc(dev, crtc, encoder)
3646 if (encoder->pre_enable)
3647 encoder->pre_enable(encoder);
3649 i9xx_pfit_enable(intel_crtc);
3651 intel_crtc_load_lut(crtc);
3653 intel_enable_pipe(dev_priv, pipe, false);
3654 intel_enable_plane(dev_priv, plane, pipe);
3655 intel_enable_planes(crtc);
3656 /* The fixup needs to happen before cursor is enabled */
3658 g4x_fixup_plane(dev_priv, pipe);
3659 intel_crtc_update_cursor(crtc, true);
3661 /* Give the overlay scaler a chance to enable if it's on this pipe */
3662 intel_crtc_dpms_overlay(intel_crtc, true);
3664 intel_update_fbc(dev);
3666 for_each_encoder_on_crtc(dev, crtc, encoder)
3667 encoder->enable(encoder);
3670 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3672 struct drm_device *dev = crtc->base.dev;
3673 struct drm_i915_private *dev_priv = dev->dev_private;
3675 if (!crtc->config.gmch_pfit.control)
3678 assert_pipe_disabled(dev_priv, crtc->pipe);
3680 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3681 I915_READ(PFIT_CONTROL));
3682 I915_WRITE(PFIT_CONTROL, 0);
3685 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3687 struct drm_device *dev = crtc->dev;
3688 struct drm_i915_private *dev_priv = dev->dev_private;
3689 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3690 struct intel_encoder *encoder;
3691 int pipe = intel_crtc->pipe;
3692 int plane = intel_crtc->plane;
3694 if (!intel_crtc->active)
3697 for_each_encoder_on_crtc(dev, crtc, encoder)
3698 encoder->disable(encoder);
3700 /* Give the overlay scaler a chance to disable if it's on this pipe */
3701 intel_crtc_wait_for_pending_flips(crtc);
3702 drm_vblank_off(dev, pipe);
3704 if (dev_priv->cfb_plane == plane)
3705 intel_disable_fbc(dev);
3707 intel_crtc_dpms_overlay(intel_crtc, false);
3708 intel_crtc_update_cursor(crtc, false);
3709 intel_disable_planes(crtc);
3710 intel_disable_plane(dev_priv, plane, pipe);
3712 intel_disable_pipe(dev_priv, pipe);
3714 i9xx_pfit_disable(intel_crtc);
3716 for_each_encoder_on_crtc(dev, crtc, encoder)
3717 if (encoder->post_disable)
3718 encoder->post_disable(encoder);
3720 intel_disable_pll(dev_priv, pipe);
3722 intel_crtc->active = false;
3723 intel_update_fbc(dev);
3724 intel_update_watermarks(dev);
3727 static void i9xx_crtc_off(struct drm_crtc *crtc)
3731 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3734 struct drm_device *dev = crtc->dev;
3735 struct drm_i915_master_private *master_priv;
3736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3737 int pipe = intel_crtc->pipe;
3739 if (!dev->primary->master)
3742 master_priv = dev->primary->master->driver_priv;
3743 if (!master_priv->sarea_priv)
3748 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3749 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3752 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3753 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3756 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3762 * Sets the power management mode of the pipe and plane.
3764 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3766 struct drm_device *dev = crtc->dev;
3767 struct drm_i915_private *dev_priv = dev->dev_private;
3768 struct intel_encoder *intel_encoder;
3769 bool enable = false;
3771 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3772 enable |= intel_encoder->connectors_active;
3775 dev_priv->display.crtc_enable(crtc);
3777 dev_priv->display.crtc_disable(crtc);
3779 intel_crtc_update_sarea(crtc, enable);
3782 static void intel_crtc_disable(struct drm_crtc *crtc)
3784 struct drm_device *dev = crtc->dev;
3785 struct drm_connector *connector;
3786 struct drm_i915_private *dev_priv = dev->dev_private;
3787 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3789 /* crtc should still be enabled when we disable it. */
3790 WARN_ON(!crtc->enabled);
3792 dev_priv->display.crtc_disable(crtc);
3793 intel_crtc->eld_vld = false;
3794 intel_crtc_update_sarea(crtc, false);
3795 dev_priv->display.off(crtc);
3797 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3798 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3801 mutex_lock(&dev->struct_mutex);
3802 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3803 mutex_unlock(&dev->struct_mutex);
3807 /* Update computed state. */
3808 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3809 if (!connector->encoder || !connector->encoder->crtc)
3812 if (connector->encoder->crtc != crtc)
3815 connector->dpms = DRM_MODE_DPMS_OFF;
3816 to_intel_encoder(connector->encoder)->connectors_active = false;
3820 void intel_modeset_disable(struct drm_device *dev)
3822 struct drm_crtc *crtc;
3824 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3826 intel_crtc_disable(crtc);
3830 void intel_encoder_destroy(struct drm_encoder *encoder)
3832 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3834 drm_encoder_cleanup(encoder);
3835 kfree(intel_encoder);
3838 /* Simple dpms helper for encodres with just one connector, no cloning and only
3839 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3840 * state of the entire output pipe. */
3841 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3843 if (mode == DRM_MODE_DPMS_ON) {
3844 encoder->connectors_active = true;
3846 intel_crtc_update_dpms(encoder->base.crtc);
3848 encoder->connectors_active = false;
3850 intel_crtc_update_dpms(encoder->base.crtc);
3854 /* Cross check the actual hw state with our own modeset state tracking (and it's
3855 * internal consistency). */
3856 static void intel_connector_check_state(struct intel_connector *connector)
3858 if (connector->get_hw_state(connector)) {
3859 struct intel_encoder *encoder = connector->encoder;
3860 struct drm_crtc *crtc;
3861 bool encoder_enabled;
3864 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3865 connector->base.base.id,
3866 drm_get_connector_name(&connector->base));
3868 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3869 "wrong connector dpms state\n");
3870 WARN(connector->base.encoder != &encoder->base,
3871 "active connector not linked to encoder\n");
3872 WARN(!encoder->connectors_active,
3873 "encoder->connectors_active not set\n");
3875 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3876 WARN(!encoder_enabled, "encoder not enabled\n");
3877 if (WARN_ON(!encoder->base.crtc))
3880 crtc = encoder->base.crtc;
3882 WARN(!crtc->enabled, "crtc not enabled\n");
3883 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3884 WARN(pipe != to_intel_crtc(crtc)->pipe,
3885 "encoder active on the wrong pipe\n");
3889 /* Even simpler default implementation, if there's really no special case to
3891 void intel_connector_dpms(struct drm_connector *connector, int mode)
3893 struct intel_encoder *encoder = intel_attached_encoder(connector);
3895 /* All the simple cases only support two dpms states. */
3896 if (mode != DRM_MODE_DPMS_ON)
3897 mode = DRM_MODE_DPMS_OFF;
3899 if (mode == connector->dpms)
3902 connector->dpms = mode;
3904 /* Only need to change hw state when actually enabled */
3905 if (encoder->base.crtc)
3906 intel_encoder_dpms(encoder, mode);
3908 WARN_ON(encoder->connectors_active != false);
3910 intel_modeset_check_state(connector->dev);
3913 /* Simple connector->get_hw_state implementation for encoders that support only
3914 * one connector and no cloning and hence the encoder state determines the state
3915 * of the connector. */
3916 bool intel_connector_get_hw_state(struct intel_connector *connector)
3919 struct intel_encoder *encoder = connector->encoder;
3921 return encoder->get_hw_state(encoder, &pipe);
3924 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3925 struct intel_crtc_config *pipe_config)
3927 struct drm_i915_private *dev_priv = dev->dev_private;
3928 struct intel_crtc *pipe_B_crtc =
3929 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3931 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3932 pipe_name(pipe), pipe_config->fdi_lanes);
3933 if (pipe_config->fdi_lanes > 4) {
3934 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3935 pipe_name(pipe), pipe_config->fdi_lanes);
3939 if (IS_HASWELL(dev)) {
3940 if (pipe_config->fdi_lanes > 2) {
3941 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3942 pipe_config->fdi_lanes);
3949 if (INTEL_INFO(dev)->num_pipes == 2)
3952 /* Ivybridge 3 pipe is really complicated */
3957 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
3958 pipe_config->fdi_lanes > 2) {
3959 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3960 pipe_name(pipe), pipe_config->fdi_lanes);
3965 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
3966 pipe_B_crtc->config.fdi_lanes <= 2) {
3967 if (pipe_config->fdi_lanes > 2) {
3968 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3969 pipe_name(pipe), pipe_config->fdi_lanes);
3973 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
3983 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
3984 struct intel_crtc_config *pipe_config)
3986 struct drm_device *dev = intel_crtc->base.dev;
3987 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
3988 int lane, link_bw, fdi_dotclock;
3989 bool setup_ok, needs_recompute = false;
3992 /* FDI is a binary signal running at ~2.7GHz, encoding
3993 * each output octet as 10 bits. The actual frequency
3994 * is stored as a divider into a 100MHz clock, and the
3995 * mode pixel clock is stored in units of 1KHz.
3996 * Hence the bw of each lane in terms of the mode signal
3999 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4001 fdi_dotclock = adjusted_mode->clock;
4002 fdi_dotclock /= pipe_config->pixel_multiplier;
4004 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4005 pipe_config->pipe_bpp);
4007 pipe_config->fdi_lanes = lane;
4009 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4010 link_bw, &pipe_config->fdi_m_n);
4012 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4013 intel_crtc->pipe, pipe_config);
4014 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4015 pipe_config->pipe_bpp -= 2*3;
4016 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4017 pipe_config->pipe_bpp);
4018 needs_recompute = true;
4019 pipe_config->bw_constrained = true;
4024 if (needs_recompute)
4027 return setup_ok ? 0 : -EINVAL;
4030 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4031 struct intel_crtc_config *pipe_config)
4033 pipe_config->ips_enabled = i915_enable_ips &&
4034 hsw_crtc_supports_ips(crtc) &&
4035 pipe_config->pipe_bpp == 24;
4038 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4039 struct intel_crtc_config *pipe_config)
4041 struct drm_device *dev = crtc->base.dev;
4042 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4044 if (HAS_PCH_SPLIT(dev)) {
4045 /* FDI link clock is fixed at 2.7G */
4046 if (pipe_config->requested_mode.clock * 3
4047 > IRONLAKE_FDI_FREQ * 4)
4051 /* All interlaced capable intel hw wants timings in frames. Note though
4052 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4053 * timings, so we need to be careful not to clobber these.*/
4054 if (!pipe_config->timings_set)
4055 drm_mode_set_crtcinfo(adjusted_mode, 0);
4057 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4058 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4060 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4061 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4064 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4065 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4066 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4067 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4069 pipe_config->pipe_bpp = 8*3;
4073 hsw_compute_ips_config(crtc, pipe_config);
4075 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4076 * clock survives for now. */
4077 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4078 pipe_config->shared_dpll = crtc->config.shared_dpll;
4080 if (pipe_config->has_pch_encoder)
4081 return ironlake_fdi_compute_config(crtc, pipe_config);
4086 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4088 return 400000; /* FIXME */
4091 static int i945_get_display_clock_speed(struct drm_device *dev)
4096 static int i915_get_display_clock_speed(struct drm_device *dev)
4101 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4106 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4110 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4112 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4115 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4116 case GC_DISPLAY_CLOCK_333_MHZ:
4119 case GC_DISPLAY_CLOCK_190_200_MHZ:
4125 static int i865_get_display_clock_speed(struct drm_device *dev)
4130 static int i855_get_display_clock_speed(struct drm_device *dev)
4133 /* Assume that the hardware is in the high speed state. This
4134 * should be the default.
4136 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4137 case GC_CLOCK_133_200:
4138 case GC_CLOCK_100_200:
4140 case GC_CLOCK_166_250:
4142 case GC_CLOCK_100_133:
4146 /* Shouldn't happen */
4150 static int i830_get_display_clock_speed(struct drm_device *dev)
4156 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4158 while (*num > DATA_LINK_M_N_MASK ||
4159 *den > DATA_LINK_M_N_MASK) {
4165 static void compute_m_n(unsigned int m, unsigned int n,
4166 uint32_t *ret_m, uint32_t *ret_n)
4168 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4169 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4170 intel_reduce_m_n_ratio(ret_m, ret_n);
4174 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4175 int pixel_clock, int link_clock,
4176 struct intel_link_m_n *m_n)
4180 compute_m_n(bits_per_pixel * pixel_clock,
4181 link_clock * nlanes * 8,
4182 &m_n->gmch_m, &m_n->gmch_n);
4184 compute_m_n(pixel_clock, link_clock,
4185 &m_n->link_m, &m_n->link_n);
4188 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4190 if (i915_panel_use_ssc >= 0)
4191 return i915_panel_use_ssc != 0;
4192 return dev_priv->vbt.lvds_use_ssc
4193 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4196 static int vlv_get_refclk(struct drm_crtc *crtc)
4198 struct drm_device *dev = crtc->dev;
4199 struct drm_i915_private *dev_priv = dev->dev_private;
4200 int refclk = 27000; /* for DP & HDMI */
4202 return 100000; /* only one validated so far */
4204 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4206 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4207 if (intel_panel_use_ssc(dev_priv))
4211 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4218 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4220 struct drm_device *dev = crtc->dev;
4221 struct drm_i915_private *dev_priv = dev->dev_private;
4224 if (IS_VALLEYVIEW(dev)) {
4225 refclk = vlv_get_refclk(crtc);
4226 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4227 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4228 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4229 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4231 } else if (!IS_GEN2(dev)) {
4240 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4242 return (1 << dpll->n) << 16 | dpll->m2;
4245 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4247 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4250 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4251 intel_clock_t *reduced_clock)
4253 struct drm_device *dev = crtc->base.dev;
4254 struct drm_i915_private *dev_priv = dev->dev_private;
4255 int pipe = crtc->pipe;
4258 if (IS_PINEVIEW(dev)) {
4259 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4261 fp2 = pnv_dpll_compute_fp(reduced_clock);
4263 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4265 fp2 = i9xx_dpll_compute_fp(reduced_clock);
4268 I915_WRITE(FP0(pipe), fp);
4270 crtc->lowfreq_avail = false;
4271 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4272 reduced_clock && i915_powersave) {
4273 I915_WRITE(FP1(pipe), fp2);
4274 crtc->lowfreq_avail = true;
4276 I915_WRITE(FP1(pipe), fp);
4280 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4285 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4286 * and set it to a reasonable value instead.
4288 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4289 reg_val &= 0xffffff00;
4290 reg_val |= 0x00000030;
4291 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4293 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4294 reg_val &= 0x8cffffff;
4295 reg_val = 0x8c000000;
4296 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4298 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4299 reg_val &= 0xffffff00;
4300 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4302 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4303 reg_val &= 0x00ffffff;
4304 reg_val |= 0xb0000000;
4305 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4308 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4309 struct intel_link_m_n *m_n)
4311 struct drm_device *dev = crtc->base.dev;
4312 struct drm_i915_private *dev_priv = dev->dev_private;
4313 int pipe = crtc->pipe;
4315 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4316 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4317 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4318 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4321 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4322 struct intel_link_m_n *m_n)
4324 struct drm_device *dev = crtc->base.dev;
4325 struct drm_i915_private *dev_priv = dev->dev_private;
4326 int pipe = crtc->pipe;
4327 enum transcoder transcoder = crtc->config.cpu_transcoder;
4329 if (INTEL_INFO(dev)->gen >= 5) {
4330 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4331 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4332 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4333 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4335 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4336 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4337 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4338 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4342 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4344 if (crtc->config.has_pch_encoder)
4345 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4347 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4350 static void vlv_update_pll(struct intel_crtc *crtc)
4352 struct drm_device *dev = crtc->base.dev;
4353 struct drm_i915_private *dev_priv = dev->dev_private;
4354 struct intel_encoder *encoder;
4355 int pipe = crtc->pipe;
4357 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4359 u32 coreclk, reg_val, dpll_md;
4361 mutex_lock(&dev_priv->dpio_lock);
4363 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4365 bestn = crtc->config.dpll.n;
4366 bestm1 = crtc->config.dpll.m1;
4367 bestm2 = crtc->config.dpll.m2;
4368 bestp1 = crtc->config.dpll.p1;
4369 bestp2 = crtc->config.dpll.p2;
4371 /* See eDP HDMI DPIO driver vbios notes doc */
4373 /* PLL B needs special handling */
4375 vlv_pllb_recal_opamp(dev_priv);
4377 /* Set up Tx target for periodic Rcomp update */
4378 vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4380 /* Disable target IRef on PLL */
4381 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4382 reg_val &= 0x00ffffff;
4383 vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4385 /* Disable fast lock */
4386 vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4388 /* Set idtafcrecal before PLL is enabled */
4389 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4390 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4391 mdiv |= ((bestn << DPIO_N_SHIFT));
4392 mdiv |= (1 << DPIO_K_SHIFT);
4395 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4396 * but we don't support that).
4397 * Note: don't use the DAC post divider as it seems unstable.
4399 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4400 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4402 mdiv |= DPIO_ENABLE_CALIBRATION;
4403 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4405 /* Set HBR and RBR LPF coefficients */
4406 if (crtc->config.port_clock == 162000 ||
4407 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4408 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4409 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4412 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4415 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4416 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4417 /* Use SSC source */
4419 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4422 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4424 } else { /* HDMI or VGA */
4425 /* Use bend source */
4427 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4430 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4434 coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4435 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4436 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4437 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4438 coreclk |= 0x01000000;
4439 vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4441 vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4443 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4444 if (encoder->pre_pll_enable)
4445 encoder->pre_pll_enable(encoder);
4447 /* Enable DPIO clock input */
4448 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4449 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4451 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4453 dpll |= DPLL_VCO_ENABLE;
4454 I915_WRITE(DPLL(pipe), dpll);
4455 POSTING_READ(DPLL(pipe));
4458 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4459 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4461 dpll_md = (crtc->config.pixel_multiplier - 1)
4462 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4463 I915_WRITE(DPLL_MD(pipe), dpll_md);
4464 POSTING_READ(DPLL_MD(pipe));
4466 if (crtc->config.has_dp_encoder)
4467 intel_dp_set_m_n(crtc);
4469 mutex_unlock(&dev_priv->dpio_lock);
4472 static void i9xx_update_pll(struct intel_crtc *crtc,
4473 intel_clock_t *reduced_clock,
4476 struct drm_device *dev = crtc->base.dev;
4477 struct drm_i915_private *dev_priv = dev->dev_private;
4478 struct intel_encoder *encoder;
4479 int pipe = crtc->pipe;
4482 struct dpll *clock = &crtc->config.dpll;
4484 i9xx_update_pll_dividers(crtc, reduced_clock);
4486 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4487 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4489 dpll = DPLL_VGA_MODE_DIS;
4491 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4492 dpll |= DPLLB_MODE_LVDS;
4494 dpll |= DPLLB_MODE_DAC_SERIAL;
4496 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4497 dpll |= (crtc->config.pixel_multiplier - 1)
4498 << SDVO_MULTIPLIER_SHIFT_HIRES;
4502 dpll |= DPLL_DVO_HIGH_SPEED;
4504 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4505 dpll |= DPLL_DVO_HIGH_SPEED;
4507 /* compute bitmask from p1 value */
4508 if (IS_PINEVIEW(dev))
4509 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4511 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4512 if (IS_G4X(dev) && reduced_clock)
4513 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4515 switch (clock->p2) {
4517 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4520 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4523 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4526 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4529 if (INTEL_INFO(dev)->gen >= 4)
4530 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4532 if (crtc->config.sdvo_tv_clock)
4533 dpll |= PLL_REF_INPUT_TVCLKINBC;
4534 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4535 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4536 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4538 dpll |= PLL_REF_INPUT_DREFCLK;
4540 dpll |= DPLL_VCO_ENABLE;
4541 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4542 POSTING_READ(DPLL(pipe));
4545 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4546 if (encoder->pre_pll_enable)
4547 encoder->pre_pll_enable(encoder);
4549 if (crtc->config.has_dp_encoder)
4550 intel_dp_set_m_n(crtc);
4552 I915_WRITE(DPLL(pipe), dpll);
4554 /* Wait for the clocks to stabilize. */
4555 POSTING_READ(DPLL(pipe));
4558 if (INTEL_INFO(dev)->gen >= 4) {
4559 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4560 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4561 I915_WRITE(DPLL_MD(pipe), dpll_md);
4563 /* The pixel multiplier can only be updated once the
4564 * DPLL is enabled and the clocks are stable.
4566 * So write it again.
4568 I915_WRITE(DPLL(pipe), dpll);
4572 static void i8xx_update_pll(struct intel_crtc *crtc,
4573 intel_clock_t *reduced_clock,
4576 struct drm_device *dev = crtc->base.dev;
4577 struct drm_i915_private *dev_priv = dev->dev_private;
4578 struct intel_encoder *encoder;
4579 int pipe = crtc->pipe;
4581 struct dpll *clock = &crtc->config.dpll;
4583 i9xx_update_pll_dividers(crtc, reduced_clock);
4585 dpll = DPLL_VGA_MODE_DIS;
4587 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4588 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4591 dpll |= PLL_P1_DIVIDE_BY_TWO;
4593 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4595 dpll |= PLL_P2_DIVIDE_BY_4;
4598 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4599 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4600 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4602 dpll |= PLL_REF_INPUT_DREFCLK;
4604 dpll |= DPLL_VCO_ENABLE;
4605 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4606 POSTING_READ(DPLL(pipe));
4609 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4610 if (encoder->pre_pll_enable)
4611 encoder->pre_pll_enable(encoder);
4613 I915_WRITE(DPLL(pipe), dpll);
4615 /* Wait for the clocks to stabilize. */
4616 POSTING_READ(DPLL(pipe));
4619 /* The pixel multiplier can only be updated once the
4620 * DPLL is enabled and the clocks are stable.
4622 * So write it again.
4624 I915_WRITE(DPLL(pipe), dpll);
4627 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4629 struct drm_device *dev = intel_crtc->base.dev;
4630 struct drm_i915_private *dev_priv = dev->dev_private;
4631 enum pipe pipe = intel_crtc->pipe;
4632 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4633 struct drm_display_mode *adjusted_mode =
4634 &intel_crtc->config.adjusted_mode;
4635 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4636 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4638 /* We need to be careful not to changed the adjusted mode, for otherwise
4639 * the hw state checker will get angry at the mismatch. */
4640 crtc_vtotal = adjusted_mode->crtc_vtotal;
4641 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4643 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4644 /* the chip adds 2 halflines automatically */
4646 crtc_vblank_end -= 1;
4647 vsyncshift = adjusted_mode->crtc_hsync_start
4648 - adjusted_mode->crtc_htotal / 2;
4653 if (INTEL_INFO(dev)->gen > 3)
4654 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4656 I915_WRITE(HTOTAL(cpu_transcoder),
4657 (adjusted_mode->crtc_hdisplay - 1) |
4658 ((adjusted_mode->crtc_htotal - 1) << 16));
4659 I915_WRITE(HBLANK(cpu_transcoder),
4660 (adjusted_mode->crtc_hblank_start - 1) |
4661 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4662 I915_WRITE(HSYNC(cpu_transcoder),
4663 (adjusted_mode->crtc_hsync_start - 1) |
4664 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4666 I915_WRITE(VTOTAL(cpu_transcoder),
4667 (adjusted_mode->crtc_vdisplay - 1) |
4668 ((crtc_vtotal - 1) << 16));
4669 I915_WRITE(VBLANK(cpu_transcoder),
4670 (adjusted_mode->crtc_vblank_start - 1) |
4671 ((crtc_vblank_end - 1) << 16));
4672 I915_WRITE(VSYNC(cpu_transcoder),
4673 (adjusted_mode->crtc_vsync_start - 1) |
4674 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4676 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4677 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4678 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4680 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4681 (pipe == PIPE_B || pipe == PIPE_C))
4682 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4684 /* pipesrc controls the size that is scaled from, which should
4685 * always be the user's requested size.
4687 I915_WRITE(PIPESRC(pipe),
4688 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4691 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4692 struct intel_crtc_config *pipe_config)
4694 struct drm_device *dev = crtc->base.dev;
4695 struct drm_i915_private *dev_priv = dev->dev_private;
4696 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4699 tmp = I915_READ(HTOTAL(cpu_transcoder));
4700 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4701 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4702 tmp = I915_READ(HBLANK(cpu_transcoder));
4703 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4704 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4705 tmp = I915_READ(HSYNC(cpu_transcoder));
4706 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4707 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4709 tmp = I915_READ(VTOTAL(cpu_transcoder));
4710 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4711 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4712 tmp = I915_READ(VBLANK(cpu_transcoder));
4713 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4714 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4715 tmp = I915_READ(VSYNC(cpu_transcoder));
4716 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4717 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4719 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4720 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4721 pipe_config->adjusted_mode.crtc_vtotal += 1;
4722 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4725 tmp = I915_READ(PIPESRC(crtc->pipe));
4726 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4727 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4730 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4732 struct drm_device *dev = intel_crtc->base.dev;
4733 struct drm_i915_private *dev_priv = dev->dev_private;
4738 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4739 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4742 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4745 if (intel_crtc->config.requested_mode.clock >
4746 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4747 pipeconf |= PIPECONF_DOUBLE_WIDE;
4750 /* only g4x and later have fancy bpc/dither controls */
4751 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4752 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4753 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4754 pipeconf |= PIPECONF_DITHER_EN |
4755 PIPECONF_DITHER_TYPE_SP;
4757 switch (intel_crtc->config.pipe_bpp) {
4759 pipeconf |= PIPECONF_6BPC;
4762 pipeconf |= PIPECONF_8BPC;
4765 pipeconf |= PIPECONF_10BPC;
4768 /* Case prevented by intel_choose_pipe_bpp_dither. */
4773 if (HAS_PIPE_CXSR(dev)) {
4774 if (intel_crtc->lowfreq_avail) {
4775 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4776 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4778 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4782 if (!IS_GEN2(dev) &&
4783 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4784 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4786 pipeconf |= PIPECONF_PROGRESSIVE;
4788 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4789 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4791 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4792 POSTING_READ(PIPECONF(intel_crtc->pipe));
4795 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4797 struct drm_framebuffer *fb)
4799 struct drm_device *dev = crtc->dev;
4800 struct drm_i915_private *dev_priv = dev->dev_private;
4801 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4802 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4803 int pipe = intel_crtc->pipe;
4804 int plane = intel_crtc->plane;
4805 int refclk, num_connectors = 0;
4806 intel_clock_t clock, reduced_clock;
4808 bool ok, has_reduced_clock = false;
4809 bool is_lvds = false;
4810 struct intel_encoder *encoder;
4811 const intel_limit_t *limit;
4814 for_each_encoder_on_crtc(dev, crtc, encoder) {
4815 switch (encoder->type) {
4816 case INTEL_OUTPUT_LVDS:
4824 refclk = i9xx_get_refclk(crtc, num_connectors);
4827 * Returns a set of divisors for the desired target clock with the given
4828 * refclk, or FALSE. The returned values represent the clock equation:
4829 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4831 limit = intel_limit(crtc, refclk);
4832 ok = dev_priv->display.find_dpll(limit, crtc,
4833 intel_crtc->config.port_clock,
4834 refclk, NULL, &clock);
4835 if (!ok && !intel_crtc->config.clock_set) {
4836 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4840 /* Ensure that the cursor is valid for the new mode before changing... */
4841 intel_crtc_update_cursor(crtc, true);
4843 if (is_lvds && dev_priv->lvds_downclock_avail) {
4845 * Ensure we match the reduced clock's P to the target clock.
4846 * If the clocks don't match, we can't switch the display clock
4847 * by using the FP0/FP1. In such case we will disable the LVDS
4848 * downclock feature.
4851 dev_priv->display.find_dpll(limit, crtc,
4852 dev_priv->lvds_downclock,
4856 /* Compat-code for transition, will disappear. */
4857 if (!intel_crtc->config.clock_set) {
4858 intel_crtc->config.dpll.n = clock.n;
4859 intel_crtc->config.dpll.m1 = clock.m1;
4860 intel_crtc->config.dpll.m2 = clock.m2;
4861 intel_crtc->config.dpll.p1 = clock.p1;
4862 intel_crtc->config.dpll.p2 = clock.p2;
4866 i8xx_update_pll(intel_crtc,
4867 has_reduced_clock ? &reduced_clock : NULL,
4869 else if (IS_VALLEYVIEW(dev))
4870 vlv_update_pll(intel_crtc);
4872 i9xx_update_pll(intel_crtc,
4873 has_reduced_clock ? &reduced_clock : NULL,
4876 /* Set up the display plane register */
4877 dspcntr = DISPPLANE_GAMMA_ENABLE;
4879 if (!IS_VALLEYVIEW(dev)) {
4881 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4883 dspcntr |= DISPPLANE_SEL_PIPE_B;
4886 intel_set_pipe_timings(intel_crtc);
4888 /* pipesrc and dspsize control the size that is scaled from,
4889 * which should always be the user's requested size.
4891 I915_WRITE(DSPSIZE(plane),
4892 ((mode->vdisplay - 1) << 16) |
4893 (mode->hdisplay - 1));
4894 I915_WRITE(DSPPOS(plane), 0);
4896 i9xx_set_pipeconf(intel_crtc);
4898 I915_WRITE(DSPCNTR(plane), dspcntr);
4899 POSTING_READ(DSPCNTR(plane));
4901 ret = intel_pipe_set_base(crtc, x, y, fb);
4903 intel_update_watermarks(dev);
4908 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4909 struct intel_crtc_config *pipe_config)
4911 struct drm_device *dev = crtc->base.dev;
4912 struct drm_i915_private *dev_priv = dev->dev_private;
4915 tmp = I915_READ(PFIT_CONTROL);
4917 if (INTEL_INFO(dev)->gen < 4) {
4918 if (crtc->pipe != PIPE_B)
4921 /* gen2/3 store dither state in pfit control, needs to match */
4922 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
4924 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4928 if (!(tmp & PFIT_ENABLE))
4931 pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
4932 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4933 if (INTEL_INFO(dev)->gen < 5)
4934 pipe_config->gmch_pfit.lvds_border_bits =
4935 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4938 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4939 struct intel_crtc_config *pipe_config)
4941 struct drm_device *dev = crtc->base.dev;
4942 struct drm_i915_private *dev_priv = dev->dev_private;
4945 pipe_config->cpu_transcoder = crtc->pipe;
4946 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
4948 tmp = I915_READ(PIPECONF(crtc->pipe));
4949 if (!(tmp & PIPECONF_ENABLE))
4952 intel_get_pipe_timings(crtc, pipe_config);
4954 i9xx_get_pfit_config(crtc, pipe_config);
4956 if (INTEL_INFO(dev)->gen >= 4) {
4957 tmp = I915_READ(DPLL_MD(crtc->pipe));
4958 pipe_config->pixel_multiplier =
4959 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
4960 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
4961 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4962 tmp = I915_READ(DPLL(crtc->pipe));
4963 pipe_config->pixel_multiplier =
4964 ((tmp & SDVO_MULTIPLIER_MASK)
4965 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
4967 /* Note that on i915G/GM the pixel multiplier is in the sdvo
4968 * port and will be fixed up in the encoder->get_config
4970 pipe_config->pixel_multiplier = 1;
4976 static void ironlake_init_pch_refclk(struct drm_device *dev)
4978 struct drm_i915_private *dev_priv = dev->dev_private;
4979 struct drm_mode_config *mode_config = &dev->mode_config;
4980 struct intel_encoder *encoder;
4982 bool has_lvds = false;
4983 bool has_cpu_edp = false;
4984 bool has_panel = false;
4985 bool has_ck505 = false;
4986 bool can_ssc = false;
4988 /* We need to take the global config into account */
4989 list_for_each_entry(encoder, &mode_config->encoder_list,
4991 switch (encoder->type) {
4992 case INTEL_OUTPUT_LVDS:
4996 case INTEL_OUTPUT_EDP:
4998 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5004 if (HAS_PCH_IBX(dev)) {
5005 has_ck505 = dev_priv->vbt.display_clock_mode;
5006 can_ssc = has_ck505;
5012 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5013 has_panel, has_lvds, has_ck505);
5015 /* Ironlake: try to setup display ref clock before DPLL
5016 * enabling. This is only under driver's control after
5017 * PCH B stepping, previous chipset stepping should be
5018 * ignoring this setting.
5020 val = I915_READ(PCH_DREF_CONTROL);
5022 /* As we must carefully and slowly disable/enable each source in turn,
5023 * compute the final state we want first and check if we need to
5024 * make any changes at all.
5027 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5029 final |= DREF_NONSPREAD_CK505_ENABLE;
5031 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5033 final &= ~DREF_SSC_SOURCE_MASK;
5034 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5035 final &= ~DREF_SSC1_ENABLE;
5038 final |= DREF_SSC_SOURCE_ENABLE;
5040 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5041 final |= DREF_SSC1_ENABLE;
5044 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5045 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5047 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5049 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5051 final |= DREF_SSC_SOURCE_DISABLE;
5052 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5058 /* Always enable nonspread source */
5059 val &= ~DREF_NONSPREAD_SOURCE_MASK;
5062 val |= DREF_NONSPREAD_CK505_ENABLE;
5064 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5067 val &= ~DREF_SSC_SOURCE_MASK;
5068 val |= DREF_SSC_SOURCE_ENABLE;
5070 /* SSC must be turned on before enabling the CPU output */
5071 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5072 DRM_DEBUG_KMS("Using SSC on panel\n");
5073 val |= DREF_SSC1_ENABLE;
5075 val &= ~DREF_SSC1_ENABLE;
5077 /* Get SSC going before enabling the outputs */
5078 I915_WRITE(PCH_DREF_CONTROL, val);
5079 POSTING_READ(PCH_DREF_CONTROL);
5082 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5084 /* Enable CPU source on CPU attached eDP */
5086 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5087 DRM_DEBUG_KMS("Using SSC on eDP\n");
5088 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5091 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5093 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5095 I915_WRITE(PCH_DREF_CONTROL, val);
5096 POSTING_READ(PCH_DREF_CONTROL);
5099 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5101 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5103 /* Turn off CPU output */
5104 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5106 I915_WRITE(PCH_DREF_CONTROL, val);
5107 POSTING_READ(PCH_DREF_CONTROL);
5110 /* Turn off the SSC source */
5111 val &= ~DREF_SSC_SOURCE_MASK;
5112 val |= DREF_SSC_SOURCE_DISABLE;
5115 val &= ~DREF_SSC1_ENABLE;
5117 I915_WRITE(PCH_DREF_CONTROL, val);
5118 POSTING_READ(PCH_DREF_CONTROL);
5122 BUG_ON(val != final);
5125 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5126 static void lpt_init_pch_refclk(struct drm_device *dev)
5128 struct drm_i915_private *dev_priv = dev->dev_private;
5129 struct drm_mode_config *mode_config = &dev->mode_config;
5130 struct intel_encoder *encoder;
5131 bool has_vga = false;
5132 bool is_sdv = false;
5135 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5136 switch (encoder->type) {
5137 case INTEL_OUTPUT_ANALOG:
5146 mutex_lock(&dev_priv->dpio_lock);
5148 /* XXX: Rip out SDV support once Haswell ships for real. */
5149 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5152 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5153 tmp &= ~SBI_SSCCTL_DISABLE;
5154 tmp |= SBI_SSCCTL_PATHALT;
5155 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5159 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5160 tmp &= ~SBI_SSCCTL_PATHALT;
5161 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5164 tmp = I915_READ(SOUTH_CHICKEN2);
5165 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5166 I915_WRITE(SOUTH_CHICKEN2, tmp);
5168 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5169 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5170 DRM_ERROR("FDI mPHY reset assert timeout\n");
5172 tmp = I915_READ(SOUTH_CHICKEN2);
5173 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5174 I915_WRITE(SOUTH_CHICKEN2, tmp);
5176 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5177 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5179 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5182 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5183 tmp &= ~(0xFF << 24);
5184 tmp |= (0x12 << 24);
5185 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5188 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5190 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5193 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5195 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5197 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5199 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5202 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5203 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5204 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5206 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5207 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5208 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5210 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5212 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5214 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5216 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5219 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5220 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5221 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5223 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5224 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5225 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5228 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5231 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5233 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5236 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5239 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5242 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5244 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5247 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5249 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5250 tmp &= ~(0xFF << 16);
5251 tmp |= (0x1C << 16);
5252 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5254 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5255 tmp &= ~(0xFF << 16);
5256 tmp |= (0x1C << 16);
5257 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5260 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5262 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5264 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5266 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5268 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5269 tmp &= ~(0xF << 28);
5271 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5273 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5274 tmp &= ~(0xF << 28);
5276 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5279 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5280 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5281 tmp |= SBI_DBUFF0_ENABLE;
5282 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5284 mutex_unlock(&dev_priv->dpio_lock);
5288 * Initialize reference clocks when the driver loads
5290 void intel_init_pch_refclk(struct drm_device *dev)
5292 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5293 ironlake_init_pch_refclk(dev);
5294 else if (HAS_PCH_LPT(dev))
5295 lpt_init_pch_refclk(dev);
5298 static int ironlake_get_refclk(struct drm_crtc *crtc)
5300 struct drm_device *dev = crtc->dev;
5301 struct drm_i915_private *dev_priv = dev->dev_private;
5302 struct intel_encoder *encoder;
5303 int num_connectors = 0;
5304 bool is_lvds = false;
5306 for_each_encoder_on_crtc(dev, crtc, encoder) {
5307 switch (encoder->type) {
5308 case INTEL_OUTPUT_LVDS:
5315 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5316 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5317 dev_priv->vbt.lvds_ssc_freq);
5318 return dev_priv->vbt.lvds_ssc_freq * 1000;
5324 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5326 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5327 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5328 int pipe = intel_crtc->pipe;
5333 switch (intel_crtc->config.pipe_bpp) {
5335 val |= PIPECONF_6BPC;
5338 val |= PIPECONF_8BPC;
5341 val |= PIPECONF_10BPC;
5344 val |= PIPECONF_12BPC;
5347 /* Case prevented by intel_choose_pipe_bpp_dither. */
5351 if (intel_crtc->config.dither)
5352 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5354 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5355 val |= PIPECONF_INTERLACED_ILK;
5357 val |= PIPECONF_PROGRESSIVE;
5359 if (intel_crtc->config.limited_color_range)
5360 val |= PIPECONF_COLOR_RANGE_SELECT;
5362 I915_WRITE(PIPECONF(pipe), val);
5363 POSTING_READ(PIPECONF(pipe));
5367 * Set up the pipe CSC unit.
5369 * Currently only full range RGB to limited range RGB conversion
5370 * is supported, but eventually this should handle various
5371 * RGB<->YCbCr scenarios as well.
5373 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5375 struct drm_device *dev = crtc->dev;
5376 struct drm_i915_private *dev_priv = dev->dev_private;
5377 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5378 int pipe = intel_crtc->pipe;
5379 uint16_t coeff = 0x7800; /* 1.0 */
5382 * TODO: Check what kind of values actually come out of the pipe
5383 * with these coeff/postoff values and adjust to get the best
5384 * accuracy. Perhaps we even need to take the bpc value into
5388 if (intel_crtc->config.limited_color_range)
5389 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5392 * GY/GU and RY/RU should be the other way around according
5393 * to BSpec, but reality doesn't agree. Just set them up in
5394 * a way that results in the correct picture.
5396 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5397 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5399 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5400 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5402 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5403 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5405 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5406 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5407 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5409 if (INTEL_INFO(dev)->gen > 6) {
5410 uint16_t postoff = 0;
5412 if (intel_crtc->config.limited_color_range)
5413 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5415 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5416 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5417 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5419 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5421 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5423 if (intel_crtc->config.limited_color_range)
5424 mode |= CSC_BLACK_SCREEN_OFFSET;
5426 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5430 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5432 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5433 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5434 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5439 if (intel_crtc->config.dither)
5440 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5442 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5443 val |= PIPECONF_INTERLACED_ILK;
5445 val |= PIPECONF_PROGRESSIVE;
5447 I915_WRITE(PIPECONF(cpu_transcoder), val);
5448 POSTING_READ(PIPECONF(cpu_transcoder));
5450 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5451 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
5454 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5455 intel_clock_t *clock,
5456 bool *has_reduced_clock,
5457 intel_clock_t *reduced_clock)
5459 struct drm_device *dev = crtc->dev;
5460 struct drm_i915_private *dev_priv = dev->dev_private;
5461 struct intel_encoder *intel_encoder;
5463 const intel_limit_t *limit;
5464 bool ret, is_lvds = false;
5466 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5467 switch (intel_encoder->type) {
5468 case INTEL_OUTPUT_LVDS:
5474 refclk = ironlake_get_refclk(crtc);
5477 * Returns a set of divisors for the desired target clock with the given
5478 * refclk, or FALSE. The returned values represent the clock equation:
5479 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5481 limit = intel_limit(crtc, refclk);
5482 ret = dev_priv->display.find_dpll(limit, crtc,
5483 to_intel_crtc(crtc)->config.port_clock,
5484 refclk, NULL, clock);
5488 if (is_lvds && dev_priv->lvds_downclock_avail) {
5490 * Ensure we match the reduced clock's P to the target clock.
5491 * If the clocks don't match, we can't switch the display clock
5492 * by using the FP0/FP1. In such case we will disable the LVDS
5493 * downclock feature.
5495 *has_reduced_clock =
5496 dev_priv->display.find_dpll(limit, crtc,
5497 dev_priv->lvds_downclock,
5505 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5507 struct drm_i915_private *dev_priv = dev->dev_private;
5510 temp = I915_READ(SOUTH_CHICKEN1);
5511 if (temp & FDI_BC_BIFURCATION_SELECT)
5514 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5515 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5517 temp |= FDI_BC_BIFURCATION_SELECT;
5518 DRM_DEBUG_KMS("enabling fdi C rx\n");
5519 I915_WRITE(SOUTH_CHICKEN1, temp);
5520 POSTING_READ(SOUTH_CHICKEN1);
5523 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5525 struct drm_device *dev = intel_crtc->base.dev;
5526 struct drm_i915_private *dev_priv = dev->dev_private;
5528 switch (intel_crtc->pipe) {
5532 if (intel_crtc->config.fdi_lanes > 2)
5533 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5535 cpt_enable_fdi_bc_bifurcation(dev);
5539 cpt_enable_fdi_bc_bifurcation(dev);
5547 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5550 * Account for spread spectrum to avoid
5551 * oversubscribing the link. Max center spread
5552 * is 2.5%; use 5% for safety's sake.
5554 u32 bps = target_clock * bpp * 21 / 20;
5555 return bps / (link_bw * 8) + 1;
5558 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5560 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5563 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5565 intel_clock_t *reduced_clock, u32 *fp2)
5567 struct drm_crtc *crtc = &intel_crtc->base;
5568 struct drm_device *dev = crtc->dev;
5569 struct drm_i915_private *dev_priv = dev->dev_private;
5570 struct intel_encoder *intel_encoder;
5572 int factor, num_connectors = 0;
5573 bool is_lvds = false, is_sdvo = false;
5575 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5576 switch (intel_encoder->type) {
5577 case INTEL_OUTPUT_LVDS:
5580 case INTEL_OUTPUT_SDVO:
5581 case INTEL_OUTPUT_HDMI:
5589 /* Enable autotuning of the PLL clock (if permissible) */
5592 if ((intel_panel_use_ssc(dev_priv) &&
5593 dev_priv->vbt.lvds_ssc_freq == 100) ||
5594 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5596 } else if (intel_crtc->config.sdvo_tv_clock)
5599 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5602 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5608 dpll |= DPLLB_MODE_LVDS;
5610 dpll |= DPLLB_MODE_DAC_SERIAL;
5612 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5613 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5616 dpll |= DPLL_DVO_HIGH_SPEED;
5617 if (intel_crtc->config.has_dp_encoder)
5618 dpll |= DPLL_DVO_HIGH_SPEED;
5620 /* compute bitmask from p1 value */
5621 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5623 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5625 switch (intel_crtc->config.dpll.p2) {
5627 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5630 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5633 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5636 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5640 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5641 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5643 dpll |= PLL_REF_INPUT_DREFCLK;
5645 return dpll | DPLL_VCO_ENABLE;
5648 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5650 struct drm_framebuffer *fb)
5652 struct drm_device *dev = crtc->dev;
5653 struct drm_i915_private *dev_priv = dev->dev_private;
5654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5655 int pipe = intel_crtc->pipe;
5656 int plane = intel_crtc->plane;
5657 int num_connectors = 0;
5658 intel_clock_t clock, reduced_clock;
5659 u32 dpll = 0, fp = 0, fp2 = 0;
5660 bool ok, has_reduced_clock = false;
5661 bool is_lvds = false;
5662 struct intel_encoder *encoder;
5663 struct intel_shared_dpll *pll;
5666 for_each_encoder_on_crtc(dev, crtc, encoder) {
5667 switch (encoder->type) {
5668 case INTEL_OUTPUT_LVDS:
5676 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5677 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5679 ok = ironlake_compute_clocks(crtc, &clock,
5680 &has_reduced_clock, &reduced_clock);
5681 if (!ok && !intel_crtc->config.clock_set) {
5682 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5685 /* Compat-code for transition, will disappear. */
5686 if (!intel_crtc->config.clock_set) {
5687 intel_crtc->config.dpll.n = clock.n;
5688 intel_crtc->config.dpll.m1 = clock.m1;
5689 intel_crtc->config.dpll.m2 = clock.m2;
5690 intel_crtc->config.dpll.p1 = clock.p1;
5691 intel_crtc->config.dpll.p2 = clock.p2;
5694 /* Ensure that the cursor is valid for the new mode before changing... */
5695 intel_crtc_update_cursor(crtc, true);
5697 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5698 if (intel_crtc->config.has_pch_encoder) {
5699 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5700 if (has_reduced_clock)
5701 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5703 dpll = ironlake_compute_dpll(intel_crtc,
5704 &fp, &reduced_clock,
5705 has_reduced_clock ? &fp2 : NULL);
5707 intel_crtc->config.dpll_hw_state.dpll = dpll;
5708 intel_crtc->config.dpll_hw_state.fp0 = fp;
5709 if (has_reduced_clock)
5710 intel_crtc->config.dpll_hw_state.fp1 = fp2;
5712 intel_crtc->config.dpll_hw_state.fp1 = fp;
5714 pll = intel_get_shared_dpll(intel_crtc, dpll, fp);
5716 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5721 intel_put_shared_dpll(intel_crtc);
5723 if (intel_crtc->config.has_dp_encoder)
5724 intel_dp_set_m_n(intel_crtc);
5726 for_each_encoder_on_crtc(dev, crtc, encoder)
5727 if (encoder->pre_pll_enable)
5728 encoder->pre_pll_enable(encoder);
5730 if (is_lvds && has_reduced_clock && i915_powersave)
5731 intel_crtc->lowfreq_avail = true;
5733 intel_crtc->lowfreq_avail = false;
5735 if (intel_crtc->config.has_pch_encoder) {
5736 pll = intel_crtc_to_shared_dpll(intel_crtc);
5738 I915_WRITE(PCH_DPLL(pll->id), dpll);
5740 /* Wait for the clocks to stabilize. */
5741 POSTING_READ(PCH_DPLL(pll->id));
5744 /* The pixel multiplier can only be updated once the
5745 * DPLL is enabled and the clocks are stable.
5747 * So write it again.
5749 I915_WRITE(PCH_DPLL(pll->id), dpll);
5751 if (has_reduced_clock)
5752 I915_WRITE(PCH_FP1(pll->id), fp2);
5754 I915_WRITE(PCH_FP1(pll->id), fp);
5757 intel_set_pipe_timings(intel_crtc);
5759 if (intel_crtc->config.has_pch_encoder) {
5760 intel_cpu_transcoder_set_m_n(intel_crtc,
5761 &intel_crtc->config.fdi_m_n);
5764 if (IS_IVYBRIDGE(dev))
5765 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5767 ironlake_set_pipeconf(crtc);
5769 /* Set up the display plane register */
5770 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5771 POSTING_READ(DSPCNTR(plane));
5773 ret = intel_pipe_set_base(crtc, x, y, fb);
5775 intel_update_watermarks(dev);
5780 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5781 struct intel_crtc_config *pipe_config)
5783 struct drm_device *dev = crtc->base.dev;
5784 struct drm_i915_private *dev_priv = dev->dev_private;
5785 enum transcoder transcoder = pipe_config->cpu_transcoder;
5787 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5788 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5789 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5791 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5792 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5793 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5796 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5797 struct intel_crtc_config *pipe_config)
5799 struct drm_device *dev = crtc->base.dev;
5800 struct drm_i915_private *dev_priv = dev->dev_private;
5803 tmp = I915_READ(PF_CTL(crtc->pipe));
5805 if (tmp & PF_ENABLE) {
5806 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5807 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5809 /* We currently do not free assignements of panel fitters on
5810 * ivb/hsw (since we don't use the higher upscaling modes which
5811 * differentiates them) so just WARN about this case for now. */
5813 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5814 PF_PIPE_SEL_IVB(crtc->pipe));
5819 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5820 struct intel_crtc_config *pipe_config)
5822 struct drm_device *dev = crtc->base.dev;
5823 struct drm_i915_private *dev_priv = dev->dev_private;
5826 pipe_config->cpu_transcoder = crtc->pipe;
5827 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5829 tmp = I915_READ(PIPECONF(crtc->pipe));
5830 if (!(tmp & PIPECONF_ENABLE))
5833 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5834 struct intel_shared_dpll *pll;
5836 pipe_config->has_pch_encoder = true;
5838 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5839 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5840 FDI_DP_PORT_WIDTH_SHIFT) + 1;
5842 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5844 /* XXX: Can't properly read out the pch dpll pixel multiplier
5845 * since we don't have state tracking for pch clocks yet. */
5846 pipe_config->pixel_multiplier = 1;
5848 if (HAS_PCH_IBX(dev_priv->dev)) {
5849 pipe_config->shared_dpll = crtc->pipe;
5851 tmp = I915_READ(PCH_DPLL_SEL);
5852 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5853 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5855 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5858 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5860 WARN_ON(!pll->get_hw_state(dev_priv, pll,
5861 &pipe_config->dpll_hw_state));
5863 pipe_config->pixel_multiplier = 1;
5866 intel_get_pipe_timings(crtc, pipe_config);
5868 ironlake_get_pfit_config(crtc, pipe_config);
5873 static void haswell_modeset_global_resources(struct drm_device *dev)
5875 bool enable = false;
5876 struct intel_crtc *crtc;
5878 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5879 if (!crtc->base.enabled)
5882 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5883 crtc->config.cpu_transcoder != TRANSCODER_EDP)
5887 intel_set_power_well(dev, enable);
5890 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5892 struct drm_framebuffer *fb)
5894 struct drm_device *dev = crtc->dev;
5895 struct drm_i915_private *dev_priv = dev->dev_private;
5896 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5897 int plane = intel_crtc->plane;
5900 if (!intel_ddi_pll_mode_set(crtc))
5903 /* Ensure that the cursor is valid for the new mode before changing... */
5904 intel_crtc_update_cursor(crtc, true);
5906 if (intel_crtc->config.has_dp_encoder)
5907 intel_dp_set_m_n(intel_crtc);
5909 intel_crtc->lowfreq_avail = false;
5911 intel_set_pipe_timings(intel_crtc);
5913 if (intel_crtc->config.has_pch_encoder) {
5914 intel_cpu_transcoder_set_m_n(intel_crtc,
5915 &intel_crtc->config.fdi_m_n);
5918 haswell_set_pipeconf(crtc);
5920 intel_set_pipe_csc(crtc);
5922 /* Set up the display plane register */
5923 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
5924 POSTING_READ(DSPCNTR(plane));
5926 ret = intel_pipe_set_base(crtc, x, y, fb);
5928 intel_update_watermarks(dev);
5933 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5934 struct intel_crtc_config *pipe_config)
5936 struct drm_device *dev = crtc->base.dev;
5937 struct drm_i915_private *dev_priv = dev->dev_private;
5938 enum intel_display_power_domain pfit_domain;
5941 pipe_config->cpu_transcoder = crtc->pipe;
5942 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5944 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5945 if (tmp & TRANS_DDI_FUNC_ENABLE) {
5946 enum pipe trans_edp_pipe;
5947 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
5949 WARN(1, "unknown pipe linked to edp transcoder\n");
5950 case TRANS_DDI_EDP_INPUT_A_ONOFF:
5951 case TRANS_DDI_EDP_INPUT_A_ON:
5952 trans_edp_pipe = PIPE_A;
5954 case TRANS_DDI_EDP_INPUT_B_ONOFF:
5955 trans_edp_pipe = PIPE_B;
5957 case TRANS_DDI_EDP_INPUT_C_ONOFF:
5958 trans_edp_pipe = PIPE_C;
5962 if (trans_edp_pipe == crtc->pipe)
5963 pipe_config->cpu_transcoder = TRANSCODER_EDP;
5966 if (!intel_display_power_enabled(dev,
5967 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
5970 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
5971 if (!(tmp & PIPECONF_ENABLE))
5975 * Haswell has only FDI/PCH transcoder A. It is which is connected to
5976 * DDI E. So just check whether this pipe is wired to DDI E and whether
5977 * the PCH transcoder is on.
5979 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
5980 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
5981 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
5982 pipe_config->has_pch_encoder = true;
5984 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
5985 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5986 FDI_DP_PORT_WIDTH_SHIFT) + 1;
5988 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5991 intel_get_pipe_timings(crtc, pipe_config);
5993 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
5994 if (intel_display_power_enabled(dev, pfit_domain))
5995 ironlake_get_pfit_config(crtc, pipe_config);
5997 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
5998 (I915_READ(IPS_CTL) & IPS_ENABLE);
6000 pipe_config->pixel_multiplier = 1;
6005 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6007 struct drm_framebuffer *fb)
6009 struct drm_device *dev = crtc->dev;
6010 struct drm_i915_private *dev_priv = dev->dev_private;
6011 struct drm_encoder_helper_funcs *encoder_funcs;
6012 struct intel_encoder *encoder;
6013 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6014 struct drm_display_mode *adjusted_mode =
6015 &intel_crtc->config.adjusted_mode;
6016 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6017 int pipe = intel_crtc->pipe;
6020 drm_vblank_pre_modeset(dev, pipe);
6022 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6024 drm_vblank_post_modeset(dev, pipe);
6029 for_each_encoder_on_crtc(dev, crtc, encoder) {
6030 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6031 encoder->base.base.id,
6032 drm_get_encoder_name(&encoder->base),
6033 mode->base.id, mode->name);
6034 if (encoder->mode_set) {
6035 encoder->mode_set(encoder);
6037 encoder_funcs = encoder->base.helper_private;
6038 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6045 static bool intel_eld_uptodate(struct drm_connector *connector,
6046 int reg_eldv, uint32_t bits_eldv,
6047 int reg_elda, uint32_t bits_elda,
6050 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6051 uint8_t *eld = connector->eld;
6054 i = I915_READ(reg_eldv);
6063 i = I915_READ(reg_elda);
6065 I915_WRITE(reg_elda, i);
6067 for (i = 0; i < eld[2]; i++)
6068 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6074 static void g4x_write_eld(struct drm_connector *connector,
6075 struct drm_crtc *crtc)
6077 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6078 uint8_t *eld = connector->eld;
6083 i = I915_READ(G4X_AUD_VID_DID);
6085 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6086 eldv = G4X_ELDV_DEVCL_DEVBLC;
6088 eldv = G4X_ELDV_DEVCTG;
6090 if (intel_eld_uptodate(connector,
6091 G4X_AUD_CNTL_ST, eldv,
6092 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6093 G4X_HDMIW_HDMIEDID))
6096 i = I915_READ(G4X_AUD_CNTL_ST);
6097 i &= ~(eldv | G4X_ELD_ADDR);
6098 len = (i >> 9) & 0x1f; /* ELD buffer size */
6099 I915_WRITE(G4X_AUD_CNTL_ST, i);
6104 len = min_t(uint8_t, eld[2], len);
6105 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6106 for (i = 0; i < len; i++)
6107 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6109 i = I915_READ(G4X_AUD_CNTL_ST);
6111 I915_WRITE(G4X_AUD_CNTL_ST, i);
6114 static void haswell_write_eld(struct drm_connector *connector,
6115 struct drm_crtc *crtc)
6117 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6118 uint8_t *eld = connector->eld;
6119 struct drm_device *dev = crtc->dev;
6120 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6124 int pipe = to_intel_crtc(crtc)->pipe;
6127 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6128 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6129 int aud_config = HSW_AUD_CFG(pipe);
6130 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6133 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6135 /* Audio output enable */
6136 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6137 tmp = I915_READ(aud_cntrl_st2);
6138 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6139 I915_WRITE(aud_cntrl_st2, tmp);
6141 /* Wait for 1 vertical blank */
6142 intel_wait_for_vblank(dev, pipe);
6144 /* Set ELD valid state */
6145 tmp = I915_READ(aud_cntrl_st2);
6146 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6147 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6148 I915_WRITE(aud_cntrl_st2, tmp);
6149 tmp = I915_READ(aud_cntrl_st2);
6150 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6152 /* Enable HDMI mode */
6153 tmp = I915_READ(aud_config);
6154 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6155 /* clear N_programing_enable and N_value_index */
6156 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6157 I915_WRITE(aud_config, tmp);
6159 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6161 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6162 intel_crtc->eld_vld = true;
6164 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6165 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6166 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6167 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6169 I915_WRITE(aud_config, 0);
6171 if (intel_eld_uptodate(connector,
6172 aud_cntrl_st2, eldv,
6173 aud_cntl_st, IBX_ELD_ADDRESS,
6177 i = I915_READ(aud_cntrl_st2);
6179 I915_WRITE(aud_cntrl_st2, i);
6184 i = I915_READ(aud_cntl_st);
6185 i &= ~IBX_ELD_ADDRESS;
6186 I915_WRITE(aud_cntl_st, i);
6187 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6188 DRM_DEBUG_DRIVER("port num:%d\n", i);
6190 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6191 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6192 for (i = 0; i < len; i++)
6193 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6195 i = I915_READ(aud_cntrl_st2);
6197 I915_WRITE(aud_cntrl_st2, i);
6201 static void ironlake_write_eld(struct drm_connector *connector,
6202 struct drm_crtc *crtc)
6204 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6205 uint8_t *eld = connector->eld;
6213 int pipe = to_intel_crtc(crtc)->pipe;
6215 if (HAS_PCH_IBX(connector->dev)) {
6216 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6217 aud_config = IBX_AUD_CFG(pipe);
6218 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6219 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6221 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6222 aud_config = CPT_AUD_CFG(pipe);
6223 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6224 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6227 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6229 i = I915_READ(aud_cntl_st);
6230 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6232 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6233 /* operate blindly on all ports */
6234 eldv = IBX_ELD_VALIDB;
6235 eldv |= IBX_ELD_VALIDB << 4;
6236 eldv |= IBX_ELD_VALIDB << 8;
6238 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6239 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6242 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6243 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6244 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6245 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6247 I915_WRITE(aud_config, 0);
6249 if (intel_eld_uptodate(connector,
6250 aud_cntrl_st2, eldv,
6251 aud_cntl_st, IBX_ELD_ADDRESS,
6255 i = I915_READ(aud_cntrl_st2);
6257 I915_WRITE(aud_cntrl_st2, i);
6262 i = I915_READ(aud_cntl_st);
6263 i &= ~IBX_ELD_ADDRESS;
6264 I915_WRITE(aud_cntl_st, i);
6266 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6267 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6268 for (i = 0; i < len; i++)
6269 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6271 i = I915_READ(aud_cntrl_st2);
6273 I915_WRITE(aud_cntrl_st2, i);
6276 void intel_write_eld(struct drm_encoder *encoder,
6277 struct drm_display_mode *mode)
6279 struct drm_crtc *crtc = encoder->crtc;
6280 struct drm_connector *connector;
6281 struct drm_device *dev = encoder->dev;
6282 struct drm_i915_private *dev_priv = dev->dev_private;
6284 connector = drm_select_eld(encoder, mode);
6288 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6290 drm_get_connector_name(connector),
6291 connector->encoder->base.id,
6292 drm_get_encoder_name(connector->encoder));
6294 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6296 if (dev_priv->display.write_eld)
6297 dev_priv->display.write_eld(connector, crtc);
6300 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6301 void intel_crtc_load_lut(struct drm_crtc *crtc)
6303 struct drm_device *dev = crtc->dev;
6304 struct drm_i915_private *dev_priv = dev->dev_private;
6305 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6306 enum pipe pipe = intel_crtc->pipe;
6307 int palreg = PALETTE(pipe);
6309 bool reenable_ips = false;
6311 /* The clocks have to be on to load the palette. */
6312 if (!crtc->enabled || !intel_crtc->active)
6315 if (!HAS_PCH_SPLIT(dev_priv->dev))
6316 assert_pll_enabled(dev_priv, pipe);
6318 /* use legacy palette for Ironlake */
6319 if (HAS_PCH_SPLIT(dev))
6320 palreg = LGC_PALETTE(pipe);
6322 /* Workaround : Do not read or write the pipe palette/gamma data while
6323 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6325 if (intel_crtc->config.ips_enabled &&
6326 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6327 GAMMA_MODE_MODE_SPLIT)) {
6328 hsw_disable_ips(intel_crtc);
6329 reenable_ips = true;
6332 for (i = 0; i < 256; i++) {
6333 I915_WRITE(palreg + 4 * i,
6334 (intel_crtc->lut_r[i] << 16) |
6335 (intel_crtc->lut_g[i] << 8) |
6336 intel_crtc->lut_b[i]);
6340 hsw_enable_ips(intel_crtc);
6343 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6345 struct drm_device *dev = crtc->dev;
6346 struct drm_i915_private *dev_priv = dev->dev_private;
6347 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6348 bool visible = base != 0;
6351 if (intel_crtc->cursor_visible == visible)
6354 cntl = I915_READ(_CURACNTR);
6356 /* On these chipsets we can only modify the base whilst
6357 * the cursor is disabled.
6359 I915_WRITE(_CURABASE, base);
6361 cntl &= ~(CURSOR_FORMAT_MASK);
6362 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6363 cntl |= CURSOR_ENABLE |
6364 CURSOR_GAMMA_ENABLE |
6367 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6368 I915_WRITE(_CURACNTR, cntl);
6370 intel_crtc->cursor_visible = visible;
6373 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6375 struct drm_device *dev = crtc->dev;
6376 struct drm_i915_private *dev_priv = dev->dev_private;
6377 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6378 int pipe = intel_crtc->pipe;
6379 bool visible = base != 0;
6381 if (intel_crtc->cursor_visible != visible) {
6382 uint32_t cntl = I915_READ(CURCNTR(pipe));
6384 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6385 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6386 cntl |= pipe << 28; /* Connect to correct pipe */
6388 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6389 cntl |= CURSOR_MODE_DISABLE;
6391 I915_WRITE(CURCNTR(pipe), cntl);
6393 intel_crtc->cursor_visible = visible;
6395 /* and commit changes on next vblank */
6396 I915_WRITE(CURBASE(pipe), base);
6399 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6401 struct drm_device *dev = crtc->dev;
6402 struct drm_i915_private *dev_priv = dev->dev_private;
6403 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6404 int pipe = intel_crtc->pipe;
6405 bool visible = base != 0;
6407 if (intel_crtc->cursor_visible != visible) {
6408 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6410 cntl &= ~CURSOR_MODE;
6411 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6413 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6414 cntl |= CURSOR_MODE_DISABLE;
6416 if (IS_HASWELL(dev))
6417 cntl |= CURSOR_PIPE_CSC_ENABLE;
6418 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6420 intel_crtc->cursor_visible = visible;
6422 /* and commit changes on next vblank */
6423 I915_WRITE(CURBASE_IVB(pipe), base);
6426 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6427 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6430 struct drm_device *dev = crtc->dev;
6431 struct drm_i915_private *dev_priv = dev->dev_private;
6432 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6433 int pipe = intel_crtc->pipe;
6434 int x = intel_crtc->cursor_x;
6435 int y = intel_crtc->cursor_y;
6441 if (on && crtc->enabled && crtc->fb) {
6442 base = intel_crtc->cursor_addr;
6443 if (x > (int) crtc->fb->width)
6446 if (y > (int) crtc->fb->height)
6452 if (x + intel_crtc->cursor_width < 0)
6455 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6458 pos |= x << CURSOR_X_SHIFT;
6461 if (y + intel_crtc->cursor_height < 0)
6464 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6467 pos |= y << CURSOR_Y_SHIFT;
6469 visible = base != 0;
6470 if (!visible && !intel_crtc->cursor_visible)
6473 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6474 I915_WRITE(CURPOS_IVB(pipe), pos);
6475 ivb_update_cursor(crtc, base);
6477 I915_WRITE(CURPOS(pipe), pos);
6478 if (IS_845G(dev) || IS_I865G(dev))
6479 i845_update_cursor(crtc, base);
6481 i9xx_update_cursor(crtc, base);
6485 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6486 struct drm_file *file,
6488 uint32_t width, uint32_t height)
6490 struct drm_device *dev = crtc->dev;
6491 struct drm_i915_private *dev_priv = dev->dev_private;
6492 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6493 struct drm_i915_gem_object *obj;
6497 /* if we want to turn off the cursor ignore width and height */
6499 DRM_DEBUG_KMS("cursor off\n");
6502 mutex_lock(&dev->struct_mutex);
6506 /* Currently we only support 64x64 cursors */
6507 if (width != 64 || height != 64) {
6508 DRM_ERROR("we currently only support 64x64 cursors\n");
6512 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6513 if (&obj->base == NULL)
6516 if (obj->base.size < width * height * 4) {
6517 DRM_ERROR("buffer is to small\n");
6522 /* we only need to pin inside GTT if cursor is non-phy */
6523 mutex_lock(&dev->struct_mutex);
6524 if (!dev_priv->info->cursor_needs_physical) {
6527 if (obj->tiling_mode) {
6528 DRM_ERROR("cursor cannot be tiled\n");
6533 /* Note that the w/a also requires 2 PTE of padding following
6534 * the bo. We currently fill all unused PTE with the shadow
6535 * page and so we should always have valid PTE following the
6536 * cursor preventing the VT-d warning.
6539 if (need_vtd_wa(dev))
6540 alignment = 64*1024;
6542 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6544 DRM_ERROR("failed to move cursor bo into the GTT\n");
6548 ret = i915_gem_object_put_fence(obj);
6550 DRM_ERROR("failed to release fence for cursor");
6554 addr = obj->gtt_offset;
6556 int align = IS_I830(dev) ? 16 * 1024 : 256;
6557 ret = i915_gem_attach_phys_object(dev, obj,
6558 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6561 DRM_ERROR("failed to attach phys object\n");
6564 addr = obj->phys_obj->handle->busaddr;
6568 I915_WRITE(CURSIZE, (height << 12) | width);
6571 if (intel_crtc->cursor_bo) {
6572 if (dev_priv->info->cursor_needs_physical) {
6573 if (intel_crtc->cursor_bo != obj)
6574 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6576 i915_gem_object_unpin(intel_crtc->cursor_bo);
6577 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6580 mutex_unlock(&dev->struct_mutex);
6582 intel_crtc->cursor_addr = addr;
6583 intel_crtc->cursor_bo = obj;
6584 intel_crtc->cursor_width = width;
6585 intel_crtc->cursor_height = height;
6587 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6591 i915_gem_object_unpin(obj);
6593 mutex_unlock(&dev->struct_mutex);
6595 drm_gem_object_unreference_unlocked(&obj->base);
6599 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6601 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6603 intel_crtc->cursor_x = x;
6604 intel_crtc->cursor_y = y;
6606 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6611 /** Sets the color ramps on behalf of RandR */
6612 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6613 u16 blue, int regno)
6615 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6617 intel_crtc->lut_r[regno] = red >> 8;
6618 intel_crtc->lut_g[regno] = green >> 8;
6619 intel_crtc->lut_b[regno] = blue >> 8;
6622 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6623 u16 *blue, int regno)
6625 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6627 *red = intel_crtc->lut_r[regno] << 8;
6628 *green = intel_crtc->lut_g[regno] << 8;
6629 *blue = intel_crtc->lut_b[regno] << 8;
6632 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6633 u16 *blue, uint32_t start, uint32_t size)
6635 int end = (start + size > 256) ? 256 : start + size, i;
6636 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6638 for (i = start; i < end; i++) {
6639 intel_crtc->lut_r[i] = red[i] >> 8;
6640 intel_crtc->lut_g[i] = green[i] >> 8;
6641 intel_crtc->lut_b[i] = blue[i] >> 8;
6644 intel_crtc_load_lut(crtc);
6647 /* VESA 640x480x72Hz mode to set on the pipe */
6648 static struct drm_display_mode load_detect_mode = {
6649 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6650 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6653 static struct drm_framebuffer *
6654 intel_framebuffer_create(struct drm_device *dev,
6655 struct drm_mode_fb_cmd2 *mode_cmd,
6656 struct drm_i915_gem_object *obj)
6658 struct intel_framebuffer *intel_fb;
6661 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6663 drm_gem_object_unreference_unlocked(&obj->base);
6664 return ERR_PTR(-ENOMEM);
6667 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6669 drm_gem_object_unreference_unlocked(&obj->base);
6671 return ERR_PTR(ret);
6674 return &intel_fb->base;
6678 intel_framebuffer_pitch_for_width(int width, int bpp)
6680 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6681 return ALIGN(pitch, 64);
6685 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6687 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6688 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6691 static struct drm_framebuffer *
6692 intel_framebuffer_create_for_mode(struct drm_device *dev,
6693 struct drm_display_mode *mode,
6696 struct drm_i915_gem_object *obj;
6697 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6699 obj = i915_gem_alloc_object(dev,
6700 intel_framebuffer_size_for_mode(mode, bpp));
6702 return ERR_PTR(-ENOMEM);
6704 mode_cmd.width = mode->hdisplay;
6705 mode_cmd.height = mode->vdisplay;
6706 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6708 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6710 return intel_framebuffer_create(dev, &mode_cmd, obj);
6713 static struct drm_framebuffer *
6714 mode_fits_in_fbdev(struct drm_device *dev,
6715 struct drm_display_mode *mode)
6717 struct drm_i915_private *dev_priv = dev->dev_private;
6718 struct drm_i915_gem_object *obj;
6719 struct drm_framebuffer *fb;
6721 if (dev_priv->fbdev == NULL)
6724 obj = dev_priv->fbdev->ifb.obj;
6728 fb = &dev_priv->fbdev->ifb.base;
6729 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6730 fb->bits_per_pixel))
6733 if (obj->base.size < mode->vdisplay * fb->pitches[0])
6739 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6740 struct drm_display_mode *mode,
6741 struct intel_load_detect_pipe *old)
6743 struct intel_crtc *intel_crtc;
6744 struct intel_encoder *intel_encoder =
6745 intel_attached_encoder(connector);
6746 struct drm_crtc *possible_crtc;
6747 struct drm_encoder *encoder = &intel_encoder->base;
6748 struct drm_crtc *crtc = NULL;
6749 struct drm_device *dev = encoder->dev;
6750 struct drm_framebuffer *fb;
6753 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6754 connector->base.id, drm_get_connector_name(connector),
6755 encoder->base.id, drm_get_encoder_name(encoder));
6758 * Algorithm gets a little messy:
6760 * - if the connector already has an assigned crtc, use it (but make
6761 * sure it's on first)
6763 * - try to find the first unused crtc that can drive this connector,
6764 * and use that if we find one
6767 /* See if we already have a CRTC for this connector */
6768 if (encoder->crtc) {
6769 crtc = encoder->crtc;
6771 mutex_lock(&crtc->mutex);
6773 old->dpms_mode = connector->dpms;
6774 old->load_detect_temp = false;
6776 /* Make sure the crtc and connector are running */
6777 if (connector->dpms != DRM_MODE_DPMS_ON)
6778 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6783 /* Find an unused one (if possible) */
6784 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6786 if (!(encoder->possible_crtcs & (1 << i)))
6788 if (!possible_crtc->enabled) {
6789 crtc = possible_crtc;
6795 * If we didn't find an unused CRTC, don't use any.
6798 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6802 mutex_lock(&crtc->mutex);
6803 intel_encoder->new_crtc = to_intel_crtc(crtc);
6804 to_intel_connector(connector)->new_encoder = intel_encoder;
6806 intel_crtc = to_intel_crtc(crtc);
6807 old->dpms_mode = connector->dpms;
6808 old->load_detect_temp = true;
6809 old->release_fb = NULL;
6812 mode = &load_detect_mode;
6814 /* We need a framebuffer large enough to accommodate all accesses
6815 * that the plane may generate whilst we perform load detection.
6816 * We can not rely on the fbcon either being present (we get called
6817 * during its initialisation to detect all boot displays, or it may
6818 * not even exist) or that it is large enough to satisfy the
6821 fb = mode_fits_in_fbdev(dev, mode);
6823 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6824 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6825 old->release_fb = fb;
6827 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6829 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6830 mutex_unlock(&crtc->mutex);
6834 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6835 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6836 if (old->release_fb)
6837 old->release_fb->funcs->destroy(old->release_fb);
6838 mutex_unlock(&crtc->mutex);
6842 /* let the connector get through one full cycle before testing */
6843 intel_wait_for_vblank(dev, intel_crtc->pipe);
6847 void intel_release_load_detect_pipe(struct drm_connector *connector,
6848 struct intel_load_detect_pipe *old)
6850 struct intel_encoder *intel_encoder =
6851 intel_attached_encoder(connector);
6852 struct drm_encoder *encoder = &intel_encoder->base;
6853 struct drm_crtc *crtc = encoder->crtc;
6855 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6856 connector->base.id, drm_get_connector_name(connector),
6857 encoder->base.id, drm_get_encoder_name(encoder));
6859 if (old->load_detect_temp) {
6860 to_intel_connector(connector)->new_encoder = NULL;
6861 intel_encoder->new_crtc = NULL;
6862 intel_set_mode(crtc, NULL, 0, 0, NULL);
6864 if (old->release_fb) {
6865 drm_framebuffer_unregister_private(old->release_fb);
6866 drm_framebuffer_unreference(old->release_fb);
6869 mutex_unlock(&crtc->mutex);
6873 /* Switch crtc and encoder back off if necessary */
6874 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6875 connector->funcs->dpms(connector, old->dpms_mode);
6877 mutex_unlock(&crtc->mutex);
6880 /* Returns the clock of the currently programmed mode of the given pipe. */
6881 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6883 struct drm_i915_private *dev_priv = dev->dev_private;
6884 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6885 int pipe = intel_crtc->pipe;
6886 u32 dpll = I915_READ(DPLL(pipe));
6888 intel_clock_t clock;
6890 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6891 fp = I915_READ(FP0(pipe));
6893 fp = I915_READ(FP1(pipe));
6895 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6896 if (IS_PINEVIEW(dev)) {
6897 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6898 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6900 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6901 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6904 if (!IS_GEN2(dev)) {
6905 if (IS_PINEVIEW(dev))
6906 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6907 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6909 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6910 DPLL_FPA01_P1_POST_DIV_SHIFT);
6912 switch (dpll & DPLL_MODE_MASK) {
6913 case DPLLB_MODE_DAC_SERIAL:
6914 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6917 case DPLLB_MODE_LVDS:
6918 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6922 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6923 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6927 if (IS_PINEVIEW(dev))
6928 pineview_clock(96000, &clock);
6930 i9xx_clock(96000, &clock);
6932 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6935 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6936 DPLL_FPA01_P1_POST_DIV_SHIFT);
6939 if ((dpll & PLL_REF_INPUT_MASK) ==
6940 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6941 /* XXX: might not be 66MHz */
6942 i9xx_clock(66000, &clock);
6944 i9xx_clock(48000, &clock);
6946 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6949 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6950 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6952 if (dpll & PLL_P2_DIVIDE_BY_4)
6957 i9xx_clock(48000, &clock);
6961 /* XXX: It would be nice to validate the clocks, but we can't reuse
6962 * i830PllIsValid() because it relies on the xf86_config connector
6963 * configuration being accurate, which it isn't necessarily.
6969 /** Returns the currently programmed mode of the given pipe. */
6970 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6971 struct drm_crtc *crtc)
6973 struct drm_i915_private *dev_priv = dev->dev_private;
6974 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6975 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6976 struct drm_display_mode *mode;
6977 int htot = I915_READ(HTOTAL(cpu_transcoder));
6978 int hsync = I915_READ(HSYNC(cpu_transcoder));
6979 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6980 int vsync = I915_READ(VSYNC(cpu_transcoder));
6982 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6986 mode->clock = intel_crtc_clock_get(dev, crtc);
6987 mode->hdisplay = (htot & 0xffff) + 1;
6988 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6989 mode->hsync_start = (hsync & 0xffff) + 1;
6990 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6991 mode->vdisplay = (vtot & 0xffff) + 1;
6992 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6993 mode->vsync_start = (vsync & 0xffff) + 1;
6994 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6996 drm_mode_set_name(mode);
7001 static void intel_increase_pllclock(struct drm_crtc *crtc)
7003 struct drm_device *dev = crtc->dev;
7004 drm_i915_private_t *dev_priv = dev->dev_private;
7005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7006 int pipe = intel_crtc->pipe;
7007 int dpll_reg = DPLL(pipe);
7010 if (HAS_PCH_SPLIT(dev))
7013 if (!dev_priv->lvds_downclock_avail)
7016 dpll = I915_READ(dpll_reg);
7017 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7018 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7020 assert_panel_unlocked(dev_priv, pipe);
7022 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7023 I915_WRITE(dpll_reg, dpll);
7024 intel_wait_for_vblank(dev, pipe);
7026 dpll = I915_READ(dpll_reg);
7027 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7028 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7032 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7034 struct drm_device *dev = crtc->dev;
7035 drm_i915_private_t *dev_priv = dev->dev_private;
7036 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7038 if (HAS_PCH_SPLIT(dev))
7041 if (!dev_priv->lvds_downclock_avail)
7045 * Since this is called by a timer, we should never get here in
7048 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7049 int pipe = intel_crtc->pipe;
7050 int dpll_reg = DPLL(pipe);
7053 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7055 assert_panel_unlocked(dev_priv, pipe);
7057 dpll = I915_READ(dpll_reg);
7058 dpll |= DISPLAY_RATE_SELECT_FPA1;
7059 I915_WRITE(dpll_reg, dpll);
7060 intel_wait_for_vblank(dev, pipe);
7061 dpll = I915_READ(dpll_reg);
7062 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7063 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7068 void intel_mark_busy(struct drm_device *dev)
7070 i915_update_gfx_val(dev->dev_private);
7073 void intel_mark_idle(struct drm_device *dev)
7075 struct drm_crtc *crtc;
7077 if (!i915_powersave)
7080 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7084 intel_decrease_pllclock(crtc);
7088 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7089 struct intel_ring_buffer *ring)
7091 struct drm_device *dev = obj->base.dev;
7092 struct drm_crtc *crtc;
7094 if (!i915_powersave)
7097 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7101 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7104 intel_increase_pllclock(crtc);
7105 if (ring && intel_fbc_enabled(dev))
7106 ring->fbc_dirty = true;
7110 static void intel_crtc_destroy(struct drm_crtc *crtc)
7112 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7113 struct drm_device *dev = crtc->dev;
7114 struct intel_unpin_work *work;
7115 unsigned long flags;
7117 spin_lock_irqsave(&dev->event_lock, flags);
7118 work = intel_crtc->unpin_work;
7119 intel_crtc->unpin_work = NULL;
7120 spin_unlock_irqrestore(&dev->event_lock, flags);
7123 cancel_work_sync(&work->work);
7127 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7129 drm_crtc_cleanup(crtc);
7134 static void intel_unpin_work_fn(struct work_struct *__work)
7136 struct intel_unpin_work *work =
7137 container_of(__work, struct intel_unpin_work, work);
7138 struct drm_device *dev = work->crtc->dev;
7140 mutex_lock(&dev->struct_mutex);
7141 intel_unpin_fb_obj(work->old_fb_obj);
7142 drm_gem_object_unreference(&work->pending_flip_obj->base);
7143 drm_gem_object_unreference(&work->old_fb_obj->base);
7145 intel_update_fbc(dev);
7146 mutex_unlock(&dev->struct_mutex);
7148 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7149 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7154 static void do_intel_finish_page_flip(struct drm_device *dev,
7155 struct drm_crtc *crtc)
7157 drm_i915_private_t *dev_priv = dev->dev_private;
7158 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7159 struct intel_unpin_work *work;
7160 unsigned long flags;
7162 /* Ignore early vblank irqs */
7163 if (intel_crtc == NULL)
7166 spin_lock_irqsave(&dev->event_lock, flags);
7167 work = intel_crtc->unpin_work;
7169 /* Ensure we don't miss a work->pending update ... */
7172 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7173 spin_unlock_irqrestore(&dev->event_lock, flags);
7177 /* and that the unpin work is consistent wrt ->pending. */
7180 intel_crtc->unpin_work = NULL;
7183 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7185 drm_vblank_put(dev, intel_crtc->pipe);
7187 spin_unlock_irqrestore(&dev->event_lock, flags);
7189 wake_up_all(&dev_priv->pending_flip_queue);
7191 queue_work(dev_priv->wq, &work->work);
7193 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7196 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7198 drm_i915_private_t *dev_priv = dev->dev_private;
7199 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7201 do_intel_finish_page_flip(dev, crtc);
7204 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7206 drm_i915_private_t *dev_priv = dev->dev_private;
7207 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7209 do_intel_finish_page_flip(dev, crtc);
7212 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7214 drm_i915_private_t *dev_priv = dev->dev_private;
7215 struct intel_crtc *intel_crtc =
7216 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7217 unsigned long flags;
7219 /* NB: An MMIO update of the plane base pointer will also
7220 * generate a page-flip completion irq, i.e. every modeset
7221 * is also accompanied by a spurious intel_prepare_page_flip().
7223 spin_lock_irqsave(&dev->event_lock, flags);
7224 if (intel_crtc->unpin_work)
7225 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7226 spin_unlock_irqrestore(&dev->event_lock, flags);
7229 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7231 /* Ensure that the work item is consistent when activating it ... */
7233 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7234 /* and that it is marked active as soon as the irq could fire. */
7238 static int intel_gen2_queue_flip(struct drm_device *dev,
7239 struct drm_crtc *crtc,
7240 struct drm_framebuffer *fb,
7241 struct drm_i915_gem_object *obj)
7243 struct drm_i915_private *dev_priv = dev->dev_private;
7244 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7246 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7249 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7253 ret = intel_ring_begin(ring, 6);
7257 /* Can't queue multiple flips, so wait for the previous
7258 * one to finish before executing the next.
7260 if (intel_crtc->plane)
7261 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7263 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7264 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7265 intel_ring_emit(ring, MI_NOOP);
7266 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7267 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7268 intel_ring_emit(ring, fb->pitches[0]);
7269 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7270 intel_ring_emit(ring, 0); /* aux display base address, unused */
7272 intel_mark_page_flip_active(intel_crtc);
7273 intel_ring_advance(ring);
7277 intel_unpin_fb_obj(obj);
7282 static int intel_gen3_queue_flip(struct drm_device *dev,
7283 struct drm_crtc *crtc,
7284 struct drm_framebuffer *fb,
7285 struct drm_i915_gem_object *obj)
7287 struct drm_i915_private *dev_priv = dev->dev_private;
7288 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7290 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7293 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7297 ret = intel_ring_begin(ring, 6);
7301 if (intel_crtc->plane)
7302 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7304 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7305 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7306 intel_ring_emit(ring, MI_NOOP);
7307 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7308 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7309 intel_ring_emit(ring, fb->pitches[0]);
7310 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7311 intel_ring_emit(ring, MI_NOOP);
7313 intel_mark_page_flip_active(intel_crtc);
7314 intel_ring_advance(ring);
7318 intel_unpin_fb_obj(obj);
7323 static int intel_gen4_queue_flip(struct drm_device *dev,
7324 struct drm_crtc *crtc,
7325 struct drm_framebuffer *fb,
7326 struct drm_i915_gem_object *obj)
7328 struct drm_i915_private *dev_priv = dev->dev_private;
7329 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7330 uint32_t pf, pipesrc;
7331 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7334 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7338 ret = intel_ring_begin(ring, 4);
7342 /* i965+ uses the linear or tiled offsets from the
7343 * Display Registers (which do not change across a page-flip)
7344 * so we need only reprogram the base address.
7346 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7347 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7348 intel_ring_emit(ring, fb->pitches[0]);
7349 intel_ring_emit(ring,
7350 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7353 /* XXX Enabling the panel-fitter across page-flip is so far
7354 * untested on non-native modes, so ignore it for now.
7355 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7358 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7359 intel_ring_emit(ring, pf | pipesrc);
7361 intel_mark_page_flip_active(intel_crtc);
7362 intel_ring_advance(ring);
7366 intel_unpin_fb_obj(obj);
7371 static int intel_gen6_queue_flip(struct drm_device *dev,
7372 struct drm_crtc *crtc,
7373 struct drm_framebuffer *fb,
7374 struct drm_i915_gem_object *obj)
7376 struct drm_i915_private *dev_priv = dev->dev_private;
7377 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7378 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7379 uint32_t pf, pipesrc;
7382 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7386 ret = intel_ring_begin(ring, 4);
7390 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7391 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7392 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7393 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7395 /* Contrary to the suggestions in the documentation,
7396 * "Enable Panel Fitter" does not seem to be required when page
7397 * flipping with a non-native mode, and worse causes a normal
7399 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7402 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7403 intel_ring_emit(ring, pf | pipesrc);
7405 intel_mark_page_flip_active(intel_crtc);
7406 intel_ring_advance(ring);
7410 intel_unpin_fb_obj(obj);
7416 * On gen7 we currently use the blit ring because (in early silicon at least)
7417 * the render ring doesn't give us interrpts for page flip completion, which
7418 * means clients will hang after the first flip is queued. Fortunately the
7419 * blit ring generates interrupts properly, so use it instead.
7421 static int intel_gen7_queue_flip(struct drm_device *dev,
7422 struct drm_crtc *crtc,
7423 struct drm_framebuffer *fb,
7424 struct drm_i915_gem_object *obj)
7426 struct drm_i915_private *dev_priv = dev->dev_private;
7427 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7428 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7429 uint32_t plane_bit = 0;
7432 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7436 switch(intel_crtc->plane) {
7438 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7441 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7444 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7447 WARN_ONCE(1, "unknown plane in flip command\n");
7452 ret = intel_ring_begin(ring, 4);
7456 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7457 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7458 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7459 intel_ring_emit(ring, (MI_NOOP));
7461 intel_mark_page_flip_active(intel_crtc);
7462 intel_ring_advance(ring);
7466 intel_unpin_fb_obj(obj);
7471 static int intel_default_queue_flip(struct drm_device *dev,
7472 struct drm_crtc *crtc,
7473 struct drm_framebuffer *fb,
7474 struct drm_i915_gem_object *obj)
7479 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7480 struct drm_framebuffer *fb,
7481 struct drm_pending_vblank_event *event)
7483 struct drm_device *dev = crtc->dev;
7484 struct drm_i915_private *dev_priv = dev->dev_private;
7485 struct drm_framebuffer *old_fb = crtc->fb;
7486 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7487 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7488 struct intel_unpin_work *work;
7489 unsigned long flags;
7492 /* Can't change pixel format via MI display flips. */
7493 if (fb->pixel_format != crtc->fb->pixel_format)
7497 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7498 * Note that pitch changes could also affect these register.
7500 if (INTEL_INFO(dev)->gen > 3 &&
7501 (fb->offsets[0] != crtc->fb->offsets[0] ||
7502 fb->pitches[0] != crtc->fb->pitches[0]))
7505 work = kzalloc(sizeof *work, GFP_KERNEL);
7509 work->event = event;
7511 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7512 INIT_WORK(&work->work, intel_unpin_work_fn);
7514 ret = drm_vblank_get(dev, intel_crtc->pipe);
7518 /* We borrow the event spin lock for protecting unpin_work */
7519 spin_lock_irqsave(&dev->event_lock, flags);
7520 if (intel_crtc->unpin_work) {
7521 spin_unlock_irqrestore(&dev->event_lock, flags);
7523 drm_vblank_put(dev, intel_crtc->pipe);
7525 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7528 intel_crtc->unpin_work = work;
7529 spin_unlock_irqrestore(&dev->event_lock, flags);
7531 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7532 flush_workqueue(dev_priv->wq);
7534 ret = i915_mutex_lock_interruptible(dev);
7538 /* Reference the objects for the scheduled work. */
7539 drm_gem_object_reference(&work->old_fb_obj->base);
7540 drm_gem_object_reference(&obj->base);
7544 work->pending_flip_obj = obj;
7546 work->enable_stall_check = true;
7548 atomic_inc(&intel_crtc->unpin_work_count);
7549 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7551 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7553 goto cleanup_pending;
7555 intel_disable_fbc(dev);
7556 intel_mark_fb_busy(obj, NULL);
7557 mutex_unlock(&dev->struct_mutex);
7559 trace_i915_flip_request(intel_crtc->plane, obj);
7564 atomic_dec(&intel_crtc->unpin_work_count);
7566 drm_gem_object_unreference(&work->old_fb_obj->base);
7567 drm_gem_object_unreference(&obj->base);
7568 mutex_unlock(&dev->struct_mutex);
7571 spin_lock_irqsave(&dev->event_lock, flags);
7572 intel_crtc->unpin_work = NULL;
7573 spin_unlock_irqrestore(&dev->event_lock, flags);
7575 drm_vblank_put(dev, intel_crtc->pipe);
7582 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7583 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7584 .load_lut = intel_crtc_load_lut,
7587 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7588 struct drm_crtc *crtc)
7590 struct drm_device *dev;
7591 struct drm_crtc *tmp;
7594 WARN(!crtc, "checking null crtc?\n");
7598 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7604 if (encoder->possible_crtcs & crtc_mask)
7610 * intel_modeset_update_staged_output_state
7612 * Updates the staged output configuration state, e.g. after we've read out the
7615 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7617 struct intel_encoder *encoder;
7618 struct intel_connector *connector;
7620 list_for_each_entry(connector, &dev->mode_config.connector_list,
7622 connector->new_encoder =
7623 to_intel_encoder(connector->base.encoder);
7626 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7629 to_intel_crtc(encoder->base.crtc);
7634 * intel_modeset_commit_output_state
7636 * This function copies the stage display pipe configuration to the real one.
7638 static void intel_modeset_commit_output_state(struct drm_device *dev)
7640 struct intel_encoder *encoder;
7641 struct intel_connector *connector;
7643 list_for_each_entry(connector, &dev->mode_config.connector_list,
7645 connector->base.encoder = &connector->new_encoder->base;
7648 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7650 encoder->base.crtc = &encoder->new_crtc->base;
7655 connected_sink_compute_bpp(struct intel_connector * connector,
7656 struct intel_crtc_config *pipe_config)
7658 int bpp = pipe_config->pipe_bpp;
7660 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7661 connector->base.base.id,
7662 drm_get_connector_name(&connector->base));
7664 /* Don't use an invalid EDID bpc value */
7665 if (connector->base.display_info.bpc &&
7666 connector->base.display_info.bpc * 3 < bpp) {
7667 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7668 bpp, connector->base.display_info.bpc*3);
7669 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7672 /* Clamp bpp to 8 on screens without EDID 1.4 */
7673 if (connector->base.display_info.bpc == 0 && bpp > 24) {
7674 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7676 pipe_config->pipe_bpp = 24;
7681 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7682 struct drm_framebuffer *fb,
7683 struct intel_crtc_config *pipe_config)
7685 struct drm_device *dev = crtc->base.dev;
7686 struct intel_connector *connector;
7689 switch (fb->pixel_format) {
7691 bpp = 8*3; /* since we go through a colormap */
7693 case DRM_FORMAT_XRGB1555:
7694 case DRM_FORMAT_ARGB1555:
7695 /* checked in intel_framebuffer_init already */
7696 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7698 case DRM_FORMAT_RGB565:
7699 bpp = 6*3; /* min is 18bpp */
7701 case DRM_FORMAT_XBGR8888:
7702 case DRM_FORMAT_ABGR8888:
7703 /* checked in intel_framebuffer_init already */
7704 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7706 case DRM_FORMAT_XRGB8888:
7707 case DRM_FORMAT_ARGB8888:
7710 case DRM_FORMAT_XRGB2101010:
7711 case DRM_FORMAT_ARGB2101010:
7712 case DRM_FORMAT_XBGR2101010:
7713 case DRM_FORMAT_ABGR2101010:
7714 /* checked in intel_framebuffer_init already */
7715 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7719 /* TODO: gen4+ supports 16 bpc floating point, too. */
7721 DRM_DEBUG_KMS("unsupported depth\n");
7725 pipe_config->pipe_bpp = bpp;
7727 /* Clamp display bpp to EDID value */
7728 list_for_each_entry(connector, &dev->mode_config.connector_list,
7730 if (!connector->new_encoder ||
7731 connector->new_encoder->new_crtc != crtc)
7734 connected_sink_compute_bpp(connector, pipe_config);
7740 static void intel_dump_pipe_config(struct intel_crtc *crtc,
7741 struct intel_crtc_config *pipe_config,
7742 const char *context)
7744 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7745 context, pipe_name(crtc->pipe));
7747 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7748 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7749 pipe_config->pipe_bpp, pipe_config->dither);
7750 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7751 pipe_config->has_pch_encoder,
7752 pipe_config->fdi_lanes,
7753 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7754 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7755 pipe_config->fdi_m_n.tu);
7756 DRM_DEBUG_KMS("requested mode:\n");
7757 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7758 DRM_DEBUG_KMS("adjusted mode:\n");
7759 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7760 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7761 pipe_config->gmch_pfit.control,
7762 pipe_config->gmch_pfit.pgm_ratios,
7763 pipe_config->gmch_pfit.lvds_border_bits);
7764 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7765 pipe_config->pch_pfit.pos,
7766 pipe_config->pch_pfit.size);
7767 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
7770 static bool check_encoder_cloning(struct drm_crtc *crtc)
7772 int num_encoders = 0;
7773 bool uncloneable_encoders = false;
7774 struct intel_encoder *encoder;
7776 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
7778 if (&encoder->new_crtc->base != crtc)
7782 if (!encoder->cloneable)
7783 uncloneable_encoders = true;
7786 return !(num_encoders > 1 && uncloneable_encoders);
7789 static struct intel_crtc_config *
7790 intel_modeset_pipe_config(struct drm_crtc *crtc,
7791 struct drm_framebuffer *fb,
7792 struct drm_display_mode *mode)
7794 struct drm_device *dev = crtc->dev;
7795 struct drm_encoder_helper_funcs *encoder_funcs;
7796 struct intel_encoder *encoder;
7797 struct intel_crtc_config *pipe_config;
7798 int plane_bpp, ret = -EINVAL;
7801 if (!check_encoder_cloning(crtc)) {
7802 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
7803 return ERR_PTR(-EINVAL);
7806 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7808 return ERR_PTR(-ENOMEM);
7810 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7811 drm_mode_copy(&pipe_config->requested_mode, mode);
7812 pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe;
7813 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7815 /* Compute a starting value for pipe_config->pipe_bpp taking the source
7816 * plane pixel format and any sink constraints into account. Returns the
7817 * source plane bpp so that dithering can be selected on mismatches
7818 * after encoders and crtc also have had their say. */
7819 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7825 /* Ensure the port clock defaults are reset when retrying. */
7826 pipe_config->port_clock = 0;
7827 pipe_config->pixel_multiplier = 1;
7829 /* Pass our mode to the connectors and the CRTC to give them a chance to
7830 * adjust it according to limitations or connector properties, and also
7831 * a chance to reject the mode entirely.
7833 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7836 if (&encoder->new_crtc->base != crtc)
7839 if (encoder->compute_config) {
7840 if (!(encoder->compute_config(encoder, pipe_config))) {
7841 DRM_DEBUG_KMS("Encoder config failure\n");
7848 encoder_funcs = encoder->base.helper_private;
7849 if (!(encoder_funcs->mode_fixup(&encoder->base,
7850 &pipe_config->requested_mode,
7851 &pipe_config->adjusted_mode))) {
7852 DRM_DEBUG_KMS("Encoder fixup failed\n");
7857 /* Set default port clock if not overwritten by the encoder. Needs to be
7858 * done afterwards in case the encoder adjusts the mode. */
7859 if (!pipe_config->port_clock)
7860 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
7862 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
7864 DRM_DEBUG_KMS("CRTC fixup failed\n");
7869 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7874 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7879 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7880 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7881 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7886 return ERR_PTR(ret);
7889 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7890 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7892 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7893 unsigned *prepare_pipes, unsigned *disable_pipes)
7895 struct intel_crtc *intel_crtc;
7896 struct drm_device *dev = crtc->dev;
7897 struct intel_encoder *encoder;
7898 struct intel_connector *connector;
7899 struct drm_crtc *tmp_crtc;
7901 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7903 /* Check which crtcs have changed outputs connected to them, these need
7904 * to be part of the prepare_pipes mask. We don't (yet) support global
7905 * modeset across multiple crtcs, so modeset_pipes will only have one
7906 * bit set at most. */
7907 list_for_each_entry(connector, &dev->mode_config.connector_list,
7909 if (connector->base.encoder == &connector->new_encoder->base)
7912 if (connector->base.encoder) {
7913 tmp_crtc = connector->base.encoder->crtc;
7915 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7918 if (connector->new_encoder)
7920 1 << connector->new_encoder->new_crtc->pipe;
7923 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7925 if (encoder->base.crtc == &encoder->new_crtc->base)
7928 if (encoder->base.crtc) {
7929 tmp_crtc = encoder->base.crtc;
7931 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7934 if (encoder->new_crtc)
7935 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7938 /* Check for any pipes that will be fully disabled ... */
7939 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7943 /* Don't try to disable disabled crtcs. */
7944 if (!intel_crtc->base.enabled)
7947 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7949 if (encoder->new_crtc == intel_crtc)
7954 *disable_pipes |= 1 << intel_crtc->pipe;
7958 /* set_mode is also used to update properties on life display pipes. */
7959 intel_crtc = to_intel_crtc(crtc);
7961 *prepare_pipes |= 1 << intel_crtc->pipe;
7964 * For simplicity do a full modeset on any pipe where the output routing
7965 * changed. We could be more clever, but that would require us to be
7966 * more careful with calling the relevant encoder->mode_set functions.
7969 *modeset_pipes = *prepare_pipes;
7971 /* ... and mask these out. */
7972 *modeset_pipes &= ~(*disable_pipes);
7973 *prepare_pipes &= ~(*disable_pipes);
7976 * HACK: We don't (yet) fully support global modesets. intel_set_config
7977 * obies this rule, but the modeset restore mode of
7978 * intel_modeset_setup_hw_state does not.
7980 *modeset_pipes &= 1 << intel_crtc->pipe;
7981 *prepare_pipes &= 1 << intel_crtc->pipe;
7983 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7984 *modeset_pipes, *prepare_pipes, *disable_pipes);
7987 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7989 struct drm_encoder *encoder;
7990 struct drm_device *dev = crtc->dev;
7992 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7993 if (encoder->crtc == crtc)
8000 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8002 struct intel_encoder *intel_encoder;
8003 struct intel_crtc *intel_crtc;
8004 struct drm_connector *connector;
8006 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8008 if (!intel_encoder->base.crtc)
8011 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8013 if (prepare_pipes & (1 << intel_crtc->pipe))
8014 intel_encoder->connectors_active = false;
8017 intel_modeset_commit_output_state(dev);
8019 /* Update computed state. */
8020 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8022 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8025 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8026 if (!connector->encoder || !connector->encoder->crtc)
8029 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8031 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8032 struct drm_property *dpms_property =
8033 dev->mode_config.dpms_property;
8035 connector->dpms = DRM_MODE_DPMS_ON;
8036 drm_object_property_set_value(&connector->base,
8040 intel_encoder = to_intel_encoder(connector->encoder);
8041 intel_encoder->connectors_active = true;
8047 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8048 list_for_each_entry((intel_crtc), \
8049 &(dev)->mode_config.crtc_list, \
8051 if (mask & (1 <<(intel_crtc)->pipe))
8054 intel_pipe_config_compare(struct drm_device *dev,
8055 struct intel_crtc_config *current_config,
8056 struct intel_crtc_config *pipe_config)
8058 #define PIPE_CONF_CHECK_X(name) \
8059 if (current_config->name != pipe_config->name) { \
8060 DRM_ERROR("mismatch in " #name " " \
8061 "(expected 0x%08x, found 0x%08x)\n", \
8062 current_config->name, \
8063 pipe_config->name); \
8067 #define PIPE_CONF_CHECK_I(name) \
8068 if (current_config->name != pipe_config->name) { \
8069 DRM_ERROR("mismatch in " #name " " \
8070 "(expected %i, found %i)\n", \
8071 current_config->name, \
8072 pipe_config->name); \
8076 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
8077 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8078 DRM_ERROR("mismatch in " #name " " \
8079 "(expected %i, found %i)\n", \
8080 current_config->name & (mask), \
8081 pipe_config->name & (mask)); \
8085 #define PIPE_CONF_QUIRK(quirk) \
8086 ((current_config->quirks | pipe_config->quirks) & (quirk))
8088 PIPE_CONF_CHECK_I(cpu_transcoder);
8090 PIPE_CONF_CHECK_I(has_pch_encoder);
8091 PIPE_CONF_CHECK_I(fdi_lanes);
8092 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8093 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8094 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8095 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8096 PIPE_CONF_CHECK_I(fdi_m_n.tu);
8098 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8099 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8100 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8101 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8102 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8103 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8105 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8106 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8107 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8108 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8109 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8110 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8112 if (!HAS_PCH_SPLIT(dev))
8113 PIPE_CONF_CHECK_I(pixel_multiplier);
8115 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8116 DRM_MODE_FLAG_INTERLACE);
8118 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8119 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8120 DRM_MODE_FLAG_PHSYNC);
8121 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8122 DRM_MODE_FLAG_NHSYNC);
8123 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8124 DRM_MODE_FLAG_PVSYNC);
8125 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8126 DRM_MODE_FLAG_NVSYNC);
8129 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8130 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8132 PIPE_CONF_CHECK_I(gmch_pfit.control);
8133 /* pfit ratios are autocomputed by the hw on gen4+ */
8134 if (INTEL_INFO(dev)->gen < 4)
8135 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8136 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8137 PIPE_CONF_CHECK_I(pch_pfit.pos);
8138 PIPE_CONF_CHECK_I(pch_pfit.size);
8140 PIPE_CONF_CHECK_I(ips_enabled);
8142 PIPE_CONF_CHECK_I(shared_dpll);
8143 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8144 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8145 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
8147 #undef PIPE_CONF_CHECK_X
8148 #undef PIPE_CONF_CHECK_I
8149 #undef PIPE_CONF_CHECK_FLAGS
8150 #undef PIPE_CONF_QUIRK
8156 check_connector_state(struct drm_device *dev)
8158 struct intel_connector *connector;
8160 list_for_each_entry(connector, &dev->mode_config.connector_list,
8162 /* This also checks the encoder/connector hw state with the
8163 * ->get_hw_state callbacks. */
8164 intel_connector_check_state(connector);
8166 WARN(&connector->new_encoder->base != connector->base.encoder,
8167 "connector's staged encoder doesn't match current encoder\n");
8172 check_encoder_state(struct drm_device *dev)
8174 struct intel_encoder *encoder;
8175 struct intel_connector *connector;
8177 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8179 bool enabled = false;
8180 bool active = false;
8181 enum pipe pipe, tracked_pipe;
8183 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8184 encoder->base.base.id,
8185 drm_get_encoder_name(&encoder->base));
8187 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8188 "encoder's stage crtc doesn't match current crtc\n");
8189 WARN(encoder->connectors_active && !encoder->base.crtc,
8190 "encoder's active_connectors set, but no crtc\n");
8192 list_for_each_entry(connector, &dev->mode_config.connector_list,
8194 if (connector->base.encoder != &encoder->base)
8197 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8200 WARN(!!encoder->base.crtc != enabled,
8201 "encoder's enabled state mismatch "
8202 "(expected %i, found %i)\n",
8203 !!encoder->base.crtc, enabled);
8204 WARN(active && !encoder->base.crtc,
8205 "active encoder with no crtc\n");
8207 WARN(encoder->connectors_active != active,
8208 "encoder's computed active state doesn't match tracked active state "
8209 "(expected %i, found %i)\n", active, encoder->connectors_active);
8211 active = encoder->get_hw_state(encoder, &pipe);
8212 WARN(active != encoder->connectors_active,
8213 "encoder's hw state doesn't match sw tracking "
8214 "(expected %i, found %i)\n",
8215 encoder->connectors_active, active);
8217 if (!encoder->base.crtc)
8220 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8221 WARN(active && pipe != tracked_pipe,
8222 "active encoder's pipe doesn't match"
8223 "(expected %i, found %i)\n",
8224 tracked_pipe, pipe);
8230 check_crtc_state(struct drm_device *dev)
8232 drm_i915_private_t *dev_priv = dev->dev_private;
8233 struct intel_crtc *crtc;
8234 struct intel_encoder *encoder;
8235 struct intel_crtc_config pipe_config;
8237 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8239 bool enabled = false;
8240 bool active = false;
8242 memset(&pipe_config, 0, sizeof(pipe_config));
8244 DRM_DEBUG_KMS("[CRTC:%d]\n",
8245 crtc->base.base.id);
8247 WARN(crtc->active && !crtc->base.enabled,
8248 "active crtc, but not enabled in sw tracking\n");
8250 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8252 if (encoder->base.crtc != &crtc->base)
8255 if (encoder->connectors_active)
8259 WARN(active != crtc->active,
8260 "crtc's computed active state doesn't match tracked active state "
8261 "(expected %i, found %i)\n", active, crtc->active);
8262 WARN(enabled != crtc->base.enabled,
8263 "crtc's computed enabled state doesn't match tracked enabled state "
8264 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8266 active = dev_priv->display.get_pipe_config(crtc,
8269 /* hw state is inconsistent with the pipe A quirk */
8270 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8271 active = crtc->active;
8273 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8275 if (encoder->base.crtc != &crtc->base)
8277 if (encoder->get_config)
8278 encoder->get_config(encoder, &pipe_config);
8281 WARN(crtc->active != active,
8282 "crtc active state doesn't match with hw state "
8283 "(expected %i, found %i)\n", crtc->active, active);
8286 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8287 WARN(1, "pipe state doesn't match!\n");
8288 intel_dump_pipe_config(crtc, &pipe_config,
8290 intel_dump_pipe_config(crtc, &crtc->config,
8297 check_shared_dpll_state(struct drm_device *dev)
8299 drm_i915_private_t *dev_priv = dev->dev_private;
8300 struct intel_crtc *crtc;
8301 struct intel_dpll_hw_state dpll_hw_state;
8304 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8305 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8306 int enabled_crtcs = 0, active_crtcs = 0;
8309 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8311 DRM_DEBUG_KMS("%s\n", pll->name);
8313 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8315 WARN(pll->active > pll->refcount,
8316 "more active pll users than references: %i vs %i\n",
8317 pll->active, pll->refcount);
8318 WARN(pll->active && !pll->on,
8319 "pll in active use but not on in sw tracking\n");
8320 WARN(pll->on != active,
8321 "pll on state mismatch (expected %i, found %i)\n",
8324 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8326 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8328 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8331 WARN(pll->active != active_crtcs,
8332 "pll active crtcs mismatch (expected %i, found %i)\n",
8333 pll->active, active_crtcs);
8334 WARN(pll->refcount != enabled_crtcs,
8335 "pll enabled crtcs mismatch (expected %i, found %i)\n",
8336 pll->refcount, enabled_crtcs);
8338 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8339 sizeof(dpll_hw_state)),
8340 "pll hw state mismatch\n");
8345 intel_modeset_check_state(struct drm_device *dev)
8347 check_connector_state(dev);
8348 check_encoder_state(dev);
8349 check_crtc_state(dev);
8350 check_shared_dpll_state(dev);
8353 static int __intel_set_mode(struct drm_crtc *crtc,
8354 struct drm_display_mode *mode,
8355 int x, int y, struct drm_framebuffer *fb)
8357 struct drm_device *dev = crtc->dev;
8358 drm_i915_private_t *dev_priv = dev->dev_private;
8359 struct drm_display_mode *saved_mode, *saved_hwmode;
8360 struct intel_crtc_config *pipe_config = NULL;
8361 struct intel_crtc *intel_crtc;
8362 unsigned disable_pipes, prepare_pipes, modeset_pipes;
8365 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
8368 saved_hwmode = saved_mode + 1;
8370 intel_modeset_affected_pipes(crtc, &modeset_pipes,
8371 &prepare_pipes, &disable_pipes);
8373 *saved_hwmode = crtc->hwmode;
8374 *saved_mode = crtc->mode;
8376 /* Hack: Because we don't (yet) support global modeset on multiple
8377 * crtcs, we don't keep track of the new mode for more than one crtc.
8378 * Hence simply check whether any bit is set in modeset_pipes in all the
8379 * pieces of code that are not yet converted to deal with mutliple crtcs
8380 * changing their mode at the same time. */
8381 if (modeset_pipes) {
8382 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8383 if (IS_ERR(pipe_config)) {
8384 ret = PTR_ERR(pipe_config);
8389 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8393 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8394 intel_crtc_disable(&intel_crtc->base);
8396 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8397 if (intel_crtc->base.enabled)
8398 dev_priv->display.crtc_disable(&intel_crtc->base);
8401 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8402 * to set it here already despite that we pass it down the callchain.
8404 if (modeset_pipes) {
8406 /* mode_set/enable/disable functions rely on a correct pipe
8408 to_intel_crtc(crtc)->config = *pipe_config;
8411 /* Only after disabling all output pipelines that will be changed can we
8412 * update the the output configuration. */
8413 intel_modeset_update_state(dev, prepare_pipes);
8415 if (dev_priv->display.modeset_global_resources)
8416 dev_priv->display.modeset_global_resources(dev);
8418 /* Set up the DPLL and any encoders state that needs to adjust or depend
8421 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8422 ret = intel_crtc_mode_set(&intel_crtc->base,
8428 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8429 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8430 dev_priv->display.crtc_enable(&intel_crtc->base);
8432 if (modeset_pipes) {
8433 /* Store real post-adjustment hardware mode. */
8434 crtc->hwmode = pipe_config->adjusted_mode;
8436 /* Calculate and store various constants which
8437 * are later needed by vblank and swap-completion
8438 * timestamping. They are derived from true hwmode.
8440 drm_calc_timestamping_constants(crtc);
8443 /* FIXME: add subpixel order */
8445 if (ret && crtc->enabled) {
8446 crtc->hwmode = *saved_hwmode;
8447 crtc->mode = *saved_mode;
8456 int intel_set_mode(struct drm_crtc *crtc,
8457 struct drm_display_mode *mode,
8458 int x, int y, struct drm_framebuffer *fb)
8462 ret = __intel_set_mode(crtc, mode, x, y, fb);
8465 intel_modeset_check_state(crtc->dev);
8470 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8472 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8475 #undef for_each_intel_crtc_masked
8477 static void intel_set_config_free(struct intel_set_config *config)
8482 kfree(config->save_connector_encoders);
8483 kfree(config->save_encoder_crtcs);
8487 static int intel_set_config_save_state(struct drm_device *dev,
8488 struct intel_set_config *config)
8490 struct drm_encoder *encoder;
8491 struct drm_connector *connector;
8494 config->save_encoder_crtcs =
8495 kcalloc(dev->mode_config.num_encoder,
8496 sizeof(struct drm_crtc *), GFP_KERNEL);
8497 if (!config->save_encoder_crtcs)
8500 config->save_connector_encoders =
8501 kcalloc(dev->mode_config.num_connector,
8502 sizeof(struct drm_encoder *), GFP_KERNEL);
8503 if (!config->save_connector_encoders)
8506 /* Copy data. Note that driver private data is not affected.
8507 * Should anything bad happen only the expected state is
8508 * restored, not the drivers personal bookkeeping.
8511 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8512 config->save_encoder_crtcs[count++] = encoder->crtc;
8516 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8517 config->save_connector_encoders[count++] = connector->encoder;
8523 static void intel_set_config_restore_state(struct drm_device *dev,
8524 struct intel_set_config *config)
8526 struct intel_encoder *encoder;
8527 struct intel_connector *connector;
8531 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8533 to_intel_crtc(config->save_encoder_crtcs[count++]);
8537 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8538 connector->new_encoder =
8539 to_intel_encoder(config->save_connector_encoders[count++]);
8544 is_crtc_connector_off(struct drm_crtc *crtc, struct drm_connector *connectors,
8549 for (i = 0; i < num_connectors; i++)
8550 if (connectors[i].encoder &&
8551 connectors[i].encoder->crtc == crtc &&
8552 connectors[i].dpms != DRM_MODE_DPMS_ON)
8559 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8560 struct intel_set_config *config)
8563 /* We should be able to check here if the fb has the same properties
8564 * and then just flip_or_move it */
8565 if (set->connectors != NULL &&
8566 is_crtc_connector_off(set->crtc, *set->connectors,
8567 set->num_connectors)) {
8568 config->mode_changed = true;
8569 } else if (set->crtc->fb != set->fb) {
8570 /* If we have no fb then treat it as a full mode set */
8571 if (set->crtc->fb == NULL) {
8572 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8573 config->mode_changed = true;
8574 } else if (set->fb == NULL) {
8575 config->mode_changed = true;
8576 } else if (set->fb->pixel_format !=
8577 set->crtc->fb->pixel_format) {
8578 config->mode_changed = true;
8580 config->fb_changed = true;
8584 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8585 config->fb_changed = true;
8587 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8588 DRM_DEBUG_KMS("modes are different, full mode set\n");
8589 drm_mode_debug_printmodeline(&set->crtc->mode);
8590 drm_mode_debug_printmodeline(set->mode);
8591 config->mode_changed = true;
8596 intel_modeset_stage_output_state(struct drm_device *dev,
8597 struct drm_mode_set *set,
8598 struct intel_set_config *config)
8600 struct drm_crtc *new_crtc;
8601 struct intel_connector *connector;
8602 struct intel_encoder *encoder;
8605 /* The upper layers ensure that we either disable a crtc or have a list
8606 * of connectors. For paranoia, double-check this. */
8607 WARN_ON(!set->fb && (set->num_connectors != 0));
8608 WARN_ON(set->fb && (set->num_connectors == 0));
8611 list_for_each_entry(connector, &dev->mode_config.connector_list,
8613 /* Otherwise traverse passed in connector list and get encoders
8615 for (ro = 0; ro < set->num_connectors; ro++) {
8616 if (set->connectors[ro] == &connector->base) {
8617 connector->new_encoder = connector->encoder;
8622 /* If we disable the crtc, disable all its connectors. Also, if
8623 * the connector is on the changing crtc but not on the new
8624 * connector list, disable it. */
8625 if ((!set->fb || ro == set->num_connectors) &&
8626 connector->base.encoder &&
8627 connector->base.encoder->crtc == set->crtc) {
8628 connector->new_encoder = NULL;
8630 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8631 connector->base.base.id,
8632 drm_get_connector_name(&connector->base));
8636 if (&connector->new_encoder->base != connector->base.encoder) {
8637 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8638 config->mode_changed = true;
8641 /* connector->new_encoder is now updated for all connectors. */
8643 /* Update crtc of enabled connectors. */
8645 list_for_each_entry(connector, &dev->mode_config.connector_list,
8647 if (!connector->new_encoder)
8650 new_crtc = connector->new_encoder->base.crtc;
8652 for (ro = 0; ro < set->num_connectors; ro++) {
8653 if (set->connectors[ro] == &connector->base)
8654 new_crtc = set->crtc;
8657 /* Make sure the new CRTC will work with the encoder */
8658 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8662 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8664 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8665 connector->base.base.id,
8666 drm_get_connector_name(&connector->base),
8670 /* Check for any encoders that needs to be disabled. */
8671 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8673 list_for_each_entry(connector,
8674 &dev->mode_config.connector_list,
8676 if (connector->new_encoder == encoder) {
8677 WARN_ON(!connector->new_encoder->new_crtc);
8682 encoder->new_crtc = NULL;
8684 /* Only now check for crtc changes so we don't miss encoders
8685 * that will be disabled. */
8686 if (&encoder->new_crtc->base != encoder->base.crtc) {
8687 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8688 config->mode_changed = true;
8691 /* Now we've also updated encoder->new_crtc for all encoders. */
8696 static int intel_crtc_set_config(struct drm_mode_set *set)
8698 struct drm_device *dev;
8699 struct drm_mode_set save_set;
8700 struct intel_set_config *config;
8705 BUG_ON(!set->crtc->helper_private);
8707 /* Enforce sane interface api - has been abused by the fb helper. */
8708 BUG_ON(!set->mode && set->fb);
8709 BUG_ON(set->fb && set->num_connectors == 0);
8712 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8713 set->crtc->base.id, set->fb->base.id,
8714 (int)set->num_connectors, set->x, set->y);
8716 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8719 dev = set->crtc->dev;
8722 config = kzalloc(sizeof(*config), GFP_KERNEL);
8726 ret = intel_set_config_save_state(dev, config);
8730 save_set.crtc = set->crtc;
8731 save_set.mode = &set->crtc->mode;
8732 save_set.x = set->crtc->x;
8733 save_set.y = set->crtc->y;
8734 save_set.fb = set->crtc->fb;
8736 /* Compute whether we need a full modeset, only an fb base update or no
8737 * change at all. In the future we might also check whether only the
8738 * mode changed, e.g. for LVDS where we only change the panel fitter in
8740 intel_set_config_compute_mode_changes(set, config);
8742 ret = intel_modeset_stage_output_state(dev, set, config);
8746 if (config->mode_changed) {
8747 ret = intel_set_mode(set->crtc, set->mode,
8748 set->x, set->y, set->fb);
8749 } else if (config->fb_changed) {
8750 intel_crtc_wait_for_pending_flips(set->crtc);
8752 ret = intel_pipe_set_base(set->crtc,
8753 set->x, set->y, set->fb);
8757 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
8758 set->crtc->base.id, ret);
8760 intel_set_config_restore_state(dev, config);
8762 /* Try to restore the config */
8763 if (config->mode_changed &&
8764 intel_set_mode(save_set.crtc, save_set.mode,
8765 save_set.x, save_set.y, save_set.fb))
8766 DRM_ERROR("failed to restore config after modeset failure\n");
8770 intel_set_config_free(config);
8774 static const struct drm_crtc_funcs intel_crtc_funcs = {
8775 .cursor_set = intel_crtc_cursor_set,
8776 .cursor_move = intel_crtc_cursor_move,
8777 .gamma_set = intel_crtc_gamma_set,
8778 .set_config = intel_crtc_set_config,
8779 .destroy = intel_crtc_destroy,
8780 .page_flip = intel_crtc_page_flip,
8783 static void intel_cpu_pll_init(struct drm_device *dev)
8786 intel_ddi_pll_init(dev);
8789 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
8790 struct intel_shared_dpll *pll,
8791 struct intel_dpll_hw_state *hw_state)
8795 val = I915_READ(PCH_DPLL(pll->id));
8796 hw_state->dpll = val;
8797 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
8798 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
8800 return val & DPLL_VCO_ENABLE;
8803 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
8804 struct intel_shared_dpll *pll)
8808 /* PCH refclock must be enabled first */
8809 assert_pch_refclk_enabled(dev_priv);
8811 reg = PCH_DPLL(pll->id);
8812 val = I915_READ(reg);
8813 val |= DPLL_VCO_ENABLE;
8814 I915_WRITE(reg, val);
8819 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
8820 struct intel_shared_dpll *pll)
8822 struct drm_device *dev = dev_priv->dev;
8823 struct intel_crtc *crtc;
8826 /* Make sure no transcoder isn't still depending on us. */
8827 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
8828 if (intel_crtc_to_shared_dpll(crtc) == pll)
8829 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
8832 reg = PCH_DPLL(pll->id);
8833 val = I915_READ(reg);
8834 val &= ~DPLL_VCO_ENABLE;
8835 I915_WRITE(reg, val);
8840 static char *ibx_pch_dpll_names[] = {
8845 static void ibx_pch_dpll_init(struct drm_device *dev)
8847 struct drm_i915_private *dev_priv = dev->dev_private;
8850 dev_priv->num_shared_dpll = 2;
8852 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8853 dev_priv->shared_dplls[i].id = i;
8854 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
8855 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
8856 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
8857 dev_priv->shared_dplls[i].get_hw_state =
8858 ibx_pch_dpll_get_hw_state;
8862 static void intel_shared_dpll_init(struct drm_device *dev)
8864 struct drm_i915_private *dev_priv = dev->dev_private;
8866 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8867 ibx_pch_dpll_init(dev);
8869 dev_priv->num_shared_dpll = 0;
8871 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
8872 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
8873 dev_priv->num_shared_dpll);
8876 static void intel_crtc_init(struct drm_device *dev, int pipe)
8878 drm_i915_private_t *dev_priv = dev->dev_private;
8879 struct intel_crtc *intel_crtc;
8882 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8883 if (intel_crtc == NULL)
8886 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8888 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8889 for (i = 0; i < 256; i++) {
8890 intel_crtc->lut_r[i] = i;
8891 intel_crtc->lut_g[i] = i;
8892 intel_crtc->lut_b[i] = i;
8895 /* Swap pipes & planes for FBC on pre-965 */
8896 intel_crtc->pipe = pipe;
8897 intel_crtc->plane = pipe;
8898 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8899 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8900 intel_crtc->plane = !pipe;
8903 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8904 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8905 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8906 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8908 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8911 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8912 struct drm_file *file)
8914 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8915 struct drm_mode_object *drmmode_obj;
8916 struct intel_crtc *crtc;
8918 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8921 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8922 DRM_MODE_OBJECT_CRTC);
8925 DRM_ERROR("no such CRTC id\n");
8929 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8930 pipe_from_crtc_id->pipe = crtc->pipe;
8935 static int intel_encoder_clones(struct intel_encoder *encoder)
8937 struct drm_device *dev = encoder->base.dev;
8938 struct intel_encoder *source_encoder;
8942 list_for_each_entry(source_encoder,
8943 &dev->mode_config.encoder_list, base.head) {
8945 if (encoder == source_encoder)
8946 index_mask |= (1 << entry);
8948 /* Intel hw has only one MUX where enocoders could be cloned. */
8949 if (encoder->cloneable && source_encoder->cloneable)
8950 index_mask |= (1 << entry);
8958 static bool has_edp_a(struct drm_device *dev)
8960 struct drm_i915_private *dev_priv = dev->dev_private;
8962 if (!IS_MOBILE(dev))
8965 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8969 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8975 static void intel_setup_outputs(struct drm_device *dev)
8977 struct drm_i915_private *dev_priv = dev->dev_private;
8978 struct intel_encoder *encoder;
8979 bool dpd_is_edp = false;
8981 intel_lvds_init(dev);
8984 intel_crt_init(dev);
8989 /* Haswell uses DDI functions to detect digital outputs */
8990 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8991 /* DDI A only supports eDP */
8993 intel_ddi_init(dev, PORT_A);
8995 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8997 found = I915_READ(SFUSE_STRAP);
8999 if (found & SFUSE_STRAP_DDIB_DETECTED)
9000 intel_ddi_init(dev, PORT_B);
9001 if (found & SFUSE_STRAP_DDIC_DETECTED)
9002 intel_ddi_init(dev, PORT_C);
9003 if (found & SFUSE_STRAP_DDID_DETECTED)
9004 intel_ddi_init(dev, PORT_D);
9005 } else if (HAS_PCH_SPLIT(dev)) {
9007 dpd_is_edp = intel_dpd_is_edp(dev);
9010 intel_dp_init(dev, DP_A, PORT_A);
9012 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
9013 /* PCH SDVOB multiplex with HDMIB */
9014 found = intel_sdvo_init(dev, PCH_SDVOB, true);
9016 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
9017 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
9018 intel_dp_init(dev, PCH_DP_B, PORT_B);
9021 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
9022 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
9024 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
9025 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
9027 if (I915_READ(PCH_DP_C) & DP_DETECTED)
9028 intel_dp_init(dev, PCH_DP_C, PORT_C);
9030 if (I915_READ(PCH_DP_D) & DP_DETECTED)
9031 intel_dp_init(dev, PCH_DP_D, PORT_D);
9032 } else if (IS_VALLEYVIEW(dev)) {
9033 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9034 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9035 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
9037 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
9038 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9040 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9041 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
9043 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
9046 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9047 DRM_DEBUG_KMS("probing SDVOB\n");
9048 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
9049 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9050 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9051 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
9054 if (!found && SUPPORTS_INTEGRATED_DP(dev))
9055 intel_dp_init(dev, DP_B, PORT_B);
9058 /* Before G4X SDVOC doesn't have its own detect register */
9060 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9061 DRM_DEBUG_KMS("probing SDVOC\n");
9062 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
9065 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
9067 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9068 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9069 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
9071 if (SUPPORTS_INTEGRATED_DP(dev))
9072 intel_dp_init(dev, DP_C, PORT_C);
9075 if (SUPPORTS_INTEGRATED_DP(dev) &&
9076 (I915_READ(DP_D) & DP_DETECTED))
9077 intel_dp_init(dev, DP_D, PORT_D);
9078 } else if (IS_GEN2(dev))
9079 intel_dvo_init(dev);
9081 if (SUPPORTS_TV(dev))
9084 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9085 encoder->base.possible_crtcs = encoder->crtc_mask;
9086 encoder->base.possible_clones =
9087 intel_encoder_clones(encoder);
9090 intel_init_pch_refclk(dev);
9092 drm_helper_move_panel_connectors_to_head(dev);
9095 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9097 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9099 drm_framebuffer_cleanup(fb);
9100 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
9105 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
9106 struct drm_file *file,
9107 unsigned int *handle)
9109 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9110 struct drm_i915_gem_object *obj = intel_fb->obj;
9112 return drm_gem_handle_create(file, &obj->base, handle);
9115 static const struct drm_framebuffer_funcs intel_fb_funcs = {
9116 .destroy = intel_user_framebuffer_destroy,
9117 .create_handle = intel_user_framebuffer_create_handle,
9120 int intel_framebuffer_init(struct drm_device *dev,
9121 struct intel_framebuffer *intel_fb,
9122 struct drm_mode_fb_cmd2 *mode_cmd,
9123 struct drm_i915_gem_object *obj)
9128 if (obj->tiling_mode == I915_TILING_Y) {
9129 DRM_DEBUG("hardware does not support tiling Y\n");
9133 if (mode_cmd->pitches[0] & 63) {
9134 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9135 mode_cmd->pitches[0]);
9139 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9140 pitch_limit = 32*1024;
9141 } else if (INTEL_INFO(dev)->gen >= 4) {
9142 if (obj->tiling_mode)
9143 pitch_limit = 16*1024;
9145 pitch_limit = 32*1024;
9146 } else if (INTEL_INFO(dev)->gen >= 3) {
9147 if (obj->tiling_mode)
9148 pitch_limit = 8*1024;
9150 pitch_limit = 16*1024;
9152 /* XXX DSPC is limited to 4k tiled */
9153 pitch_limit = 8*1024;
9155 if (mode_cmd->pitches[0] > pitch_limit) {
9156 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9157 obj->tiling_mode ? "tiled" : "linear",
9158 mode_cmd->pitches[0], pitch_limit);
9162 if (obj->tiling_mode != I915_TILING_NONE &&
9163 mode_cmd->pitches[0] != obj->stride) {
9164 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9165 mode_cmd->pitches[0], obj->stride);
9169 /* Reject formats not supported by any plane early. */
9170 switch (mode_cmd->pixel_format) {
9172 case DRM_FORMAT_RGB565:
9173 case DRM_FORMAT_XRGB8888:
9174 case DRM_FORMAT_ARGB8888:
9176 case DRM_FORMAT_XRGB1555:
9177 case DRM_FORMAT_ARGB1555:
9178 if (INTEL_INFO(dev)->gen > 3) {
9179 DRM_DEBUG("unsupported pixel format: %s\n",
9180 drm_get_format_name(mode_cmd->pixel_format));
9184 case DRM_FORMAT_XBGR8888:
9185 case DRM_FORMAT_ABGR8888:
9186 case DRM_FORMAT_XRGB2101010:
9187 case DRM_FORMAT_ARGB2101010:
9188 case DRM_FORMAT_XBGR2101010:
9189 case DRM_FORMAT_ABGR2101010:
9190 if (INTEL_INFO(dev)->gen < 4) {
9191 DRM_DEBUG("unsupported pixel format: %s\n",
9192 drm_get_format_name(mode_cmd->pixel_format));
9196 case DRM_FORMAT_YUYV:
9197 case DRM_FORMAT_UYVY:
9198 case DRM_FORMAT_YVYU:
9199 case DRM_FORMAT_VYUY:
9200 if (INTEL_INFO(dev)->gen < 5) {
9201 DRM_DEBUG("unsupported pixel format: %s\n",
9202 drm_get_format_name(mode_cmd->pixel_format));
9207 DRM_DEBUG("unsupported pixel format: %s\n",
9208 drm_get_format_name(mode_cmd->pixel_format));
9212 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9213 if (mode_cmd->offsets[0] != 0)
9216 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9217 intel_fb->obj = obj;
9219 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9221 DRM_ERROR("framebuffer init failed %d\n", ret);
9228 static struct drm_framebuffer *
9229 intel_user_framebuffer_create(struct drm_device *dev,
9230 struct drm_file *filp,
9231 struct drm_mode_fb_cmd2 *mode_cmd)
9233 struct drm_i915_gem_object *obj;
9235 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9236 mode_cmd->handles[0]));
9237 if (&obj->base == NULL)
9238 return ERR_PTR(-ENOENT);
9240 return intel_framebuffer_create(dev, mode_cmd, obj);
9243 static const struct drm_mode_config_funcs intel_mode_funcs = {
9244 .fb_create = intel_user_framebuffer_create,
9245 .output_poll_changed = intel_fb_output_poll_changed,
9248 /* Set up chip specific display functions */
9249 static void intel_init_display(struct drm_device *dev)
9251 struct drm_i915_private *dev_priv = dev->dev_private;
9253 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9254 dev_priv->display.find_dpll = g4x_find_best_dpll;
9255 else if (IS_VALLEYVIEW(dev))
9256 dev_priv->display.find_dpll = vlv_find_best_dpll;
9257 else if (IS_PINEVIEW(dev))
9258 dev_priv->display.find_dpll = pnv_find_best_dpll;
9260 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9263 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
9264 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
9265 dev_priv->display.crtc_enable = haswell_crtc_enable;
9266 dev_priv->display.crtc_disable = haswell_crtc_disable;
9267 dev_priv->display.off = haswell_crtc_off;
9268 dev_priv->display.update_plane = ironlake_update_plane;
9269 } else if (HAS_PCH_SPLIT(dev)) {
9270 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
9271 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9272 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9273 dev_priv->display.crtc_disable = ironlake_crtc_disable;
9274 dev_priv->display.off = ironlake_crtc_off;
9275 dev_priv->display.update_plane = ironlake_update_plane;
9276 } else if (IS_VALLEYVIEW(dev)) {
9277 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9278 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9279 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9280 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9281 dev_priv->display.off = i9xx_crtc_off;
9282 dev_priv->display.update_plane = i9xx_update_plane;
9284 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9285 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9286 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9287 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9288 dev_priv->display.off = i9xx_crtc_off;
9289 dev_priv->display.update_plane = i9xx_update_plane;
9292 /* Returns the core display clock speed */
9293 if (IS_VALLEYVIEW(dev))
9294 dev_priv->display.get_display_clock_speed =
9295 valleyview_get_display_clock_speed;
9296 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
9297 dev_priv->display.get_display_clock_speed =
9298 i945_get_display_clock_speed;
9299 else if (IS_I915G(dev))
9300 dev_priv->display.get_display_clock_speed =
9301 i915_get_display_clock_speed;
9302 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
9303 dev_priv->display.get_display_clock_speed =
9304 i9xx_misc_get_display_clock_speed;
9305 else if (IS_I915GM(dev))
9306 dev_priv->display.get_display_clock_speed =
9307 i915gm_get_display_clock_speed;
9308 else if (IS_I865G(dev))
9309 dev_priv->display.get_display_clock_speed =
9310 i865_get_display_clock_speed;
9311 else if (IS_I85X(dev))
9312 dev_priv->display.get_display_clock_speed =
9313 i855_get_display_clock_speed;
9315 dev_priv->display.get_display_clock_speed =
9316 i830_get_display_clock_speed;
9318 if (HAS_PCH_SPLIT(dev)) {
9320 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9321 dev_priv->display.write_eld = ironlake_write_eld;
9322 } else if (IS_GEN6(dev)) {
9323 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9324 dev_priv->display.write_eld = ironlake_write_eld;
9325 } else if (IS_IVYBRIDGE(dev)) {
9326 /* FIXME: detect B0+ stepping and use auto training */
9327 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9328 dev_priv->display.write_eld = ironlake_write_eld;
9329 dev_priv->display.modeset_global_resources =
9330 ivb_modeset_global_resources;
9331 } else if (IS_HASWELL(dev)) {
9332 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
9333 dev_priv->display.write_eld = haswell_write_eld;
9334 dev_priv->display.modeset_global_resources =
9335 haswell_modeset_global_resources;
9337 } else if (IS_G4X(dev)) {
9338 dev_priv->display.write_eld = g4x_write_eld;
9341 /* Default just returns -ENODEV to indicate unsupported */
9342 dev_priv->display.queue_flip = intel_default_queue_flip;
9344 switch (INTEL_INFO(dev)->gen) {
9346 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9350 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9355 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9359 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9362 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9368 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9369 * resume, or other times. This quirk makes sure that's the case for
9372 static void quirk_pipea_force(struct drm_device *dev)
9374 struct drm_i915_private *dev_priv = dev->dev_private;
9376 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9377 DRM_INFO("applying pipe a force quirk\n");
9381 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9383 static void quirk_ssc_force_disable(struct drm_device *dev)
9385 struct drm_i915_private *dev_priv = dev->dev_private;
9386 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9387 DRM_INFO("applying lvds SSC disable quirk\n");
9391 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9394 static void quirk_invert_brightness(struct drm_device *dev)
9396 struct drm_i915_private *dev_priv = dev->dev_private;
9397 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9398 DRM_INFO("applying inverted panel brightness quirk\n");
9401 struct intel_quirk {
9403 int subsystem_vendor;
9404 int subsystem_device;
9405 void (*hook)(struct drm_device *dev);
9408 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9409 struct intel_dmi_quirk {
9410 void (*hook)(struct drm_device *dev);
9411 const struct dmi_system_id (*dmi_id_list)[];
9414 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9416 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9420 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9422 .dmi_id_list = &(const struct dmi_system_id[]) {
9424 .callback = intel_dmi_reverse_brightness,
9425 .ident = "NCR Corporation",
9426 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9427 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9430 { } /* terminating entry */
9432 .hook = quirk_invert_brightness,
9436 static struct intel_quirk intel_quirks[] = {
9437 /* HP Mini needs pipe A force quirk (LP: #322104) */
9438 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9440 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9441 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9443 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9444 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9446 /* 830/845 need to leave pipe A & dpll A up */
9447 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9448 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9450 /* Lenovo U160 cannot use SSC on LVDS */
9451 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9453 /* Sony Vaio Y cannot use SSC on LVDS */
9454 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9456 /* Acer Aspire 5734Z must invert backlight brightness */
9457 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9459 /* Acer/eMachines G725 */
9460 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
9462 /* Acer/eMachines e725 */
9463 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
9465 /* Acer/Packard Bell NCL20 */
9466 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
9468 /* Acer Aspire 4736Z */
9469 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
9472 static void intel_init_quirks(struct drm_device *dev)
9474 struct pci_dev *d = dev->pdev;
9477 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9478 struct intel_quirk *q = &intel_quirks[i];
9480 if (d->device == q->device &&
9481 (d->subsystem_vendor == q->subsystem_vendor ||
9482 q->subsystem_vendor == PCI_ANY_ID) &&
9483 (d->subsystem_device == q->subsystem_device ||
9484 q->subsystem_device == PCI_ANY_ID))
9487 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9488 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9489 intel_dmi_quirks[i].hook(dev);
9493 /* Disable the VGA plane that we never use */
9494 static void i915_disable_vga(struct drm_device *dev)
9496 struct drm_i915_private *dev_priv = dev->dev_private;
9498 u32 vga_reg = i915_vgacntrl_reg(dev);
9500 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9501 outb(SR01, VGA_SR_INDEX);
9502 sr1 = inb(VGA_SR_DATA);
9503 outb(sr1 | 1<<5, VGA_SR_DATA);
9504 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9507 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9508 POSTING_READ(vga_reg);
9511 void intel_modeset_init_hw(struct drm_device *dev)
9513 intel_init_power_well(dev);
9515 intel_prepare_ddi(dev);
9517 intel_init_clock_gating(dev);
9519 mutex_lock(&dev->struct_mutex);
9520 intel_enable_gt_powersave(dev);
9521 mutex_unlock(&dev->struct_mutex);
9524 void intel_modeset_suspend_hw(struct drm_device *dev)
9526 intel_suspend_hw(dev);
9529 void intel_modeset_init(struct drm_device *dev)
9531 struct drm_i915_private *dev_priv = dev->dev_private;
9534 drm_mode_config_init(dev);
9536 dev->mode_config.min_width = 0;
9537 dev->mode_config.min_height = 0;
9539 dev->mode_config.preferred_depth = 24;
9540 dev->mode_config.prefer_shadow = 1;
9542 dev->mode_config.funcs = &intel_mode_funcs;
9544 intel_init_quirks(dev);
9548 if (INTEL_INFO(dev)->num_pipes == 0)
9551 intel_init_display(dev);
9554 dev->mode_config.max_width = 2048;
9555 dev->mode_config.max_height = 2048;
9556 } else if (IS_GEN3(dev)) {
9557 dev->mode_config.max_width = 4096;
9558 dev->mode_config.max_height = 4096;
9560 dev->mode_config.max_width = 8192;
9561 dev->mode_config.max_height = 8192;
9563 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
9565 DRM_DEBUG_KMS("%d display pipe%s available.\n",
9566 INTEL_INFO(dev)->num_pipes,
9567 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
9569 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
9570 intel_crtc_init(dev, i);
9571 for (j = 0; j < dev_priv->num_plane; j++) {
9572 ret = intel_plane_init(dev, i, j);
9574 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9575 pipe_name(i), sprite_name(i, j), ret);
9579 intel_cpu_pll_init(dev);
9580 intel_shared_dpll_init(dev);
9582 /* Just disable it once at startup */
9583 i915_disable_vga(dev);
9584 intel_setup_outputs(dev);
9586 /* Just in case the BIOS is doing something questionable. */
9587 intel_disable_fbc(dev);
9591 intel_connector_break_all_links(struct intel_connector *connector)
9593 connector->base.dpms = DRM_MODE_DPMS_OFF;
9594 connector->base.encoder = NULL;
9595 connector->encoder->connectors_active = false;
9596 connector->encoder->base.crtc = NULL;
9599 static void intel_enable_pipe_a(struct drm_device *dev)
9601 struct intel_connector *connector;
9602 struct drm_connector *crt = NULL;
9603 struct intel_load_detect_pipe load_detect_temp;
9605 /* We can't just switch on the pipe A, we need to set things up with a
9606 * proper mode and output configuration. As a gross hack, enable pipe A
9607 * by enabling the load detect pipe once. */
9608 list_for_each_entry(connector,
9609 &dev->mode_config.connector_list,
9611 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9612 crt = &connector->base;
9620 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9621 intel_release_load_detect_pipe(crt, &load_detect_temp);
9627 intel_check_plane_mapping(struct intel_crtc *crtc)
9629 struct drm_device *dev = crtc->base.dev;
9630 struct drm_i915_private *dev_priv = dev->dev_private;
9633 if (INTEL_INFO(dev)->num_pipes == 1)
9636 reg = DSPCNTR(!crtc->plane);
9637 val = I915_READ(reg);
9639 if ((val & DISPLAY_PLANE_ENABLE) &&
9640 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9646 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9648 struct drm_device *dev = crtc->base.dev;
9649 struct drm_i915_private *dev_priv = dev->dev_private;
9652 /* Clear any frame start delays used for debugging left by the BIOS */
9653 reg = PIPECONF(crtc->config.cpu_transcoder);
9654 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9656 /* We need to sanitize the plane -> pipe mapping first because this will
9657 * disable the crtc (and hence change the state) if it is wrong. Note
9658 * that gen4+ has a fixed plane -> pipe mapping. */
9659 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9660 struct intel_connector *connector;
9663 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9664 crtc->base.base.id);
9666 /* Pipe has the wrong plane attached and the plane is active.
9667 * Temporarily change the plane mapping and disable everything
9669 plane = crtc->plane;
9670 crtc->plane = !plane;
9671 dev_priv->display.crtc_disable(&crtc->base);
9672 crtc->plane = plane;
9674 /* ... and break all links. */
9675 list_for_each_entry(connector, &dev->mode_config.connector_list,
9677 if (connector->encoder->base.crtc != &crtc->base)
9680 intel_connector_break_all_links(connector);
9683 WARN_ON(crtc->active);
9684 crtc->base.enabled = false;
9687 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9688 crtc->pipe == PIPE_A && !crtc->active) {
9689 /* BIOS forgot to enable pipe A, this mostly happens after
9690 * resume. Force-enable the pipe to fix this, the update_dpms
9691 * call below we restore the pipe to the right state, but leave
9692 * the required bits on. */
9693 intel_enable_pipe_a(dev);
9696 /* Adjust the state of the output pipe according to whether we
9697 * have active connectors/encoders. */
9698 intel_crtc_update_dpms(&crtc->base);
9700 if (crtc->active != crtc->base.enabled) {
9701 struct intel_encoder *encoder;
9703 /* This can happen either due to bugs in the get_hw_state
9704 * functions or because the pipe is force-enabled due to the
9706 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9708 crtc->base.enabled ? "enabled" : "disabled",
9709 crtc->active ? "enabled" : "disabled");
9711 crtc->base.enabled = crtc->active;
9713 /* Because we only establish the connector -> encoder ->
9714 * crtc links if something is active, this means the
9715 * crtc is now deactivated. Break the links. connector
9716 * -> encoder links are only establish when things are
9717 * actually up, hence no need to break them. */
9718 WARN_ON(crtc->active);
9720 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9721 WARN_ON(encoder->connectors_active);
9722 encoder->base.crtc = NULL;
9727 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9729 struct intel_connector *connector;
9730 struct drm_device *dev = encoder->base.dev;
9732 /* We need to check both for a crtc link (meaning that the
9733 * encoder is active and trying to read from a pipe) and the
9734 * pipe itself being active. */
9735 bool has_active_crtc = encoder->base.crtc &&
9736 to_intel_crtc(encoder->base.crtc)->active;
9738 if (encoder->connectors_active && !has_active_crtc) {
9739 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9740 encoder->base.base.id,
9741 drm_get_encoder_name(&encoder->base));
9743 /* Connector is active, but has no active pipe. This is
9744 * fallout from our resume register restoring. Disable
9745 * the encoder manually again. */
9746 if (encoder->base.crtc) {
9747 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9748 encoder->base.base.id,
9749 drm_get_encoder_name(&encoder->base));
9750 encoder->disable(encoder);
9753 /* Inconsistent output/port/pipe state happens presumably due to
9754 * a bug in one of the get_hw_state functions. Or someplace else
9755 * in our code, like the register restore mess on resume. Clamp
9756 * things to off as a safer default. */
9757 list_for_each_entry(connector,
9758 &dev->mode_config.connector_list,
9760 if (connector->encoder != encoder)
9763 intel_connector_break_all_links(connector);
9766 /* Enabled encoders without active connectors will be fixed in
9767 * the crtc fixup. */
9770 void i915_redisable_vga(struct drm_device *dev)
9772 struct drm_i915_private *dev_priv = dev->dev_private;
9773 u32 vga_reg = i915_vgacntrl_reg(dev);
9775 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9776 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9777 i915_disable_vga(dev);
9781 static void intel_modeset_readout_hw_state(struct drm_device *dev)
9783 struct drm_i915_private *dev_priv = dev->dev_private;
9785 struct intel_crtc *crtc;
9786 struct intel_encoder *encoder;
9787 struct intel_connector *connector;
9790 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9792 memset(&crtc->config, 0, sizeof(crtc->config));
9794 crtc->active = dev_priv->display.get_pipe_config(crtc,
9797 crtc->base.enabled = crtc->active;
9799 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9801 crtc->active ? "enabled" : "disabled");
9804 /* FIXME: Smash this into the new shared dpll infrastructure. */
9806 intel_ddi_setup_hw_pll_state(dev);
9808 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9809 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9811 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
9813 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9815 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9818 pll->refcount = pll->active;
9820 DRM_DEBUG_KMS("%s hw state readout: refcount %i\n",
9821 pll->name, pll->refcount);
9824 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9828 if (encoder->get_hw_state(encoder, &pipe)) {
9829 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9830 encoder->base.crtc = &crtc->base;
9831 if (encoder->get_config)
9832 encoder->get_config(encoder, &crtc->config);
9834 encoder->base.crtc = NULL;
9837 encoder->connectors_active = false;
9838 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9839 encoder->base.base.id,
9840 drm_get_encoder_name(&encoder->base),
9841 encoder->base.crtc ? "enabled" : "disabled",
9845 list_for_each_entry(connector, &dev->mode_config.connector_list,
9847 if (connector->get_hw_state(connector)) {
9848 connector->base.dpms = DRM_MODE_DPMS_ON;
9849 connector->encoder->connectors_active = true;
9850 connector->base.encoder = &connector->encoder->base;
9852 connector->base.dpms = DRM_MODE_DPMS_OFF;
9853 connector->base.encoder = NULL;
9855 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9856 connector->base.base.id,
9857 drm_get_connector_name(&connector->base),
9858 connector->base.encoder ? "enabled" : "disabled");
9862 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9863 * and i915 state tracking structures. */
9864 void intel_modeset_setup_hw_state(struct drm_device *dev,
9867 struct drm_i915_private *dev_priv = dev->dev_private;
9869 struct drm_plane *plane;
9870 struct intel_crtc *crtc;
9871 struct intel_encoder *encoder;
9873 intel_modeset_readout_hw_state(dev);
9875 /* HW state is read out, now we need to sanitize this mess. */
9876 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9878 intel_sanitize_encoder(encoder);
9881 for_each_pipe(pipe) {
9882 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9883 intel_sanitize_crtc(crtc);
9884 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
9887 if (force_restore) {
9889 * We need to use raw interfaces for restoring state to avoid
9890 * checking (bogus) intermediate states.
9892 for_each_pipe(pipe) {
9893 struct drm_crtc *crtc =
9894 dev_priv->pipe_to_crtc_mapping[pipe];
9896 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9899 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9900 intel_plane_restore(plane);
9902 i915_redisable_vga(dev);
9904 intel_modeset_update_staged_output_state(dev);
9907 intel_modeset_check_state(dev);
9909 drm_mode_config_reset(dev);
9912 void intel_modeset_gem_init(struct drm_device *dev)
9914 intel_modeset_init_hw(dev);
9916 intel_setup_overlay(dev);
9918 intel_modeset_setup_hw_state(dev, false);
9921 void intel_modeset_cleanup(struct drm_device *dev)
9923 struct drm_i915_private *dev_priv = dev->dev_private;
9924 struct drm_crtc *crtc;
9925 struct intel_crtc *intel_crtc;
9928 * Interrupts and polling as the first thing to avoid creating havoc.
9929 * Too much stuff here (turning of rps, connectors, ...) would
9930 * experience fancy races otherwise.
9932 drm_irq_uninstall(dev);
9933 cancel_work_sync(&dev_priv->hotplug_work);
9935 * Due to the hpd irq storm handling the hotplug work can re-arm the
9936 * poll handlers. Hence disable polling after hpd handling is shut down.
9938 drm_kms_helper_poll_fini(dev);
9940 mutex_lock(&dev->struct_mutex);
9942 intel_unregister_dsm_handler();
9944 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9945 /* Skip inactive CRTCs */
9949 intel_crtc = to_intel_crtc(crtc);
9950 intel_increase_pllclock(crtc);
9953 intel_disable_fbc(dev);
9955 intel_disable_gt_powersave(dev);
9957 ironlake_teardown_rc6(dev);
9959 mutex_unlock(&dev->struct_mutex);
9961 /* flush any delayed tasks or pending work */
9962 flush_scheduled_work();
9964 /* destroy backlight, if any, before the connectors */
9965 intel_panel_destroy_backlight(dev);
9967 drm_mode_config_cleanup(dev);
9969 intel_cleanup_overlay(dev);
9973 * Return which encoder is currently attached for connector.
9975 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9977 return &intel_attached_encoder(connector)->base;
9980 void intel_connector_attach_encoder(struct intel_connector *connector,
9981 struct intel_encoder *encoder)
9983 connector->encoder = encoder;
9984 drm_mode_connector_attach_encoder(&connector->base,
9989 * set vga decode state - true == enable VGA decode
9991 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9993 struct drm_i915_private *dev_priv = dev->dev_private;
9996 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9998 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10000 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10001 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10005 #ifdef CONFIG_DEBUG_FS
10006 #include <linux/seq_file.h>
10008 struct intel_display_error_state {
10010 u32 power_well_driver;
10012 struct intel_cursor_error_state {
10017 } cursor[I915_MAX_PIPES];
10019 struct intel_pipe_error_state {
10020 enum transcoder cpu_transcoder;
10030 } pipe[I915_MAX_PIPES];
10032 struct intel_plane_error_state {
10040 } plane[I915_MAX_PIPES];
10043 struct intel_display_error_state *
10044 intel_display_capture_error_state(struct drm_device *dev)
10046 drm_i915_private_t *dev_priv = dev->dev_private;
10047 struct intel_display_error_state *error;
10048 enum transcoder cpu_transcoder;
10051 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10055 if (HAS_POWER_WELL(dev))
10056 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10059 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
10060 error->pipe[i].cpu_transcoder = cpu_transcoder;
10062 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10063 error->cursor[i].control = I915_READ(CURCNTR(i));
10064 error->cursor[i].position = I915_READ(CURPOS(i));
10065 error->cursor[i].base = I915_READ(CURBASE(i));
10067 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10068 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10069 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10072 error->plane[i].control = I915_READ(DSPCNTR(i));
10073 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
10074 if (INTEL_INFO(dev)->gen <= 3) {
10075 error->plane[i].size = I915_READ(DSPSIZE(i));
10076 error->plane[i].pos = I915_READ(DSPPOS(i));
10078 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10079 error->plane[i].addr = I915_READ(DSPADDR(i));
10080 if (INTEL_INFO(dev)->gen >= 4) {
10081 error->plane[i].surface = I915_READ(DSPSURF(i));
10082 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10085 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10086 error->pipe[i].source = I915_READ(PIPESRC(i));
10087 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10088 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10089 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10090 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10091 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10092 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
10095 /* In the code above we read the registers without checking if the power
10096 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10097 * prevent the next I915_WRITE from detecting it and printing an error
10099 if (HAS_POWER_WELL(dev))
10100 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
10105 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10108 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
10109 struct drm_device *dev,
10110 struct intel_display_error_state *error)
10114 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
10115 if (HAS_POWER_WELL(dev))
10116 err_printf(m, "PWR_WELL_CTL2: %08x\n",
10117 error->power_well_driver);
10119 err_printf(m, "Pipe [%d]:\n", i);
10120 err_printf(m, " CPU transcoder: %c\n",
10121 transcoder_name(error->pipe[i].cpu_transcoder));
10122 err_printf(m, " CONF: %08x\n", error->pipe[i].conf);
10123 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
10124 err_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
10125 err_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
10126 err_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
10127 err_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
10128 err_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
10129 err_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
10131 err_printf(m, "Plane [%d]:\n", i);
10132 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
10133 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
10134 if (INTEL_INFO(dev)->gen <= 3) {
10135 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
10136 err_printf(m, " POS: %08x\n", error->plane[i].pos);
10138 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10139 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
10140 if (INTEL_INFO(dev)->gen >= 4) {
10141 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
10142 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
10145 err_printf(m, "Cursor [%d]:\n", i);
10146 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
10147 err_printf(m, " POS: %08x\n", error->cursor[i].position);
10148 err_printf(m, " BASE: %08x\n", error->cursor[i].base);