drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 static void intel_increase_pllclock(struct drm_crtc *crtc);
  45 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  46
  47 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  48                                 struct intel_crtc_config *pipe_config);
  49 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  50                                    struct intel_crtc_config *pipe_config);
  51
  52 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  53                           int x, int y, struct drm_framebuffer *old_fb);
  54 static int intel_framebuffer_init(struct drm_device *dev,
  55                                   struct intel_framebuffer *ifb,
  56                                   struct drm_mode_fb_cmd2 *mode_cmd,
  57                                   struct drm_i915_gem_object *obj);
  58
  59 typedef struct {
  60         int     min, max;
  61 } intel_range_t;
  62
  63 typedef struct {
  64         int     dot_limit;
  65         int     p2_slow, p2_fast;
  66 } intel_p2_t;
  67
  68 typedef struct intel_limit intel_limit_t;
  69 struct intel_limit {
  70         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  71         intel_p2_t          p2;
  72 };
  73
  74 int
  75 intel_pch_rawclk(struct drm_device *dev)
  76 {
  77         struct drm_i915_private *dev_priv = dev->dev_private;
  78
  79         WARN_ON(!HAS_PCH_SPLIT(dev));
  80
  81         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  82 }
  83
  84 static inline u32 /* units of 100MHz */
  85 intel_fdi_link_freq(struct drm_device *dev)
  86 {
  87         if (IS_GEN5(dev)) {
  88                 struct drm_i915_private *dev_priv = dev->dev_private;
  89                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  90         } else
  91                 return 27;
  92 }
  93
  94 static const intel_limit_t intel_limits_i8xx_dac = {
  95         .dot = { .min = 25000, .max = 350000 },
  96         .vco = { .min = 908000, .max = 1512000 },
  97         .n = { .min = 2, .max = 16 },
  98         .m = { .min = 96, .max = 140 },
  99         .m1 = { .min = 18, .max = 26 },
 100         .m2 = { .min = 6, .max = 16 },
 101         .p = { .min = 4, .max = 128 },
 102         .p1 = { .min = 2, .max = 33 },
 103         .p2 = { .dot_limit = 165000,
 104                 .p2_slow = 4, .p2_fast = 2 },
 105 };
 106
 107 static const intel_limit_t intel_limits_i8xx_dvo = {
 108         .dot = { .min = 25000, .max = 350000 },
 109         .vco = { .min = 908000, .max = 1512000 },
 110         .n = { .min = 2, .max = 16 },
 111         .m = { .min = 96, .max = 140 },
 112         .m1 = { .min = 18, .max = 26 },
 113         .m2 = { .min = 6, .max = 16 },
 114         .p = { .min = 4, .max = 128 },
 115         .p1 = { .min = 2, .max = 33 },
 116         .p2 = { .dot_limit = 165000,
 117                 .p2_slow = 4, .p2_fast = 4 },
 118 };
 119
 120 static const intel_limit_t intel_limits_i8xx_lvds = {
 121         .dot = { .min = 25000, .max = 350000 },
 122         .vco = { .min = 908000, .max = 1512000 },
 123         .n = { .min = 2, .max = 16 },
 124         .m = { .min = 96, .max = 140 },
 125         .m1 = { .min = 18, .max = 26 },
 126         .m2 = { .min = 6, .max = 16 },
 127         .p = { .min = 4, .max = 128 },
 128         .p1 = { .min = 1, .max = 6 },
 129         .p2 = { .dot_limit = 165000,
 130                 .p2_slow = 14, .p2_fast = 7 },
 131 };
 132
 133 static const intel_limit_t intel_limits_i9xx_sdvo = {
 134         .dot = { .min = 20000, .max = 400000 },
 135         .vco = { .min = 1400000, .max = 2800000 },
 136         .n = { .min = 1, .max = 6 },
 137         .m = { .min = 70, .max = 120 },
 138         .m1 = { .min = 8, .max = 18 },
 139         .m2 = { .min = 3, .max = 7 },
 140         .p = { .min = 5, .max = 80 },
 141         .p1 = { .min = 1, .max = 8 },
 142         .p2 = { .dot_limit = 200000,
 143                 .p2_slow = 10, .p2_fast = 5 },
 144 };
 145
 146 static const intel_limit_t intel_limits_i9xx_lvds = {
 147         .dot = { .min = 20000, .max = 400000 },
 148         .vco = { .min = 1400000, .max = 2800000 },
 149         .n = { .min = 1, .max = 6 },
 150         .m = { .min = 70, .max = 120 },
 151         .m1 = { .min = 8, .max = 18 },
 152         .m2 = { .min = 3, .max = 7 },
 153         .p = { .min = 7, .max = 98 },
 154         .p1 = { .min = 1, .max = 8 },
 155         .p2 = { .dot_limit = 112000,
 156                 .p2_slow = 14, .p2_fast = 7 },
 157 };
 158
 159
 160 static const intel_limit_t intel_limits_g4x_sdvo = {
 161         .dot = { .min = 25000, .max = 270000 },
 162         .vco = { .min = 1750000, .max = 3500000},
 163         .n = { .min = 1, .max = 4 },
 164         .m = { .min = 104, .max = 138 },
 165         .m1 = { .min = 17, .max = 23 },
 166         .m2 = { .min = 5, .max = 11 },
 167         .p = { .min = 10, .max = 30 },
 168         .p1 = { .min = 1, .max = 3},
 169         .p2 = { .dot_limit = 270000,
 170                 .p2_slow = 10,
 171                 .p2_fast = 10
 172         },
 173 };
 174
 175 static const intel_limit_t intel_limits_g4x_hdmi = {
 176         .dot = { .min = 22000, .max = 400000 },
 177         .vco = { .min = 1750000, .max = 3500000},
 178         .n = { .min = 1, .max = 4 },
 179         .m = { .min = 104, .max = 138 },
 180         .m1 = { .min = 16, .max = 23 },
 181         .m2 = { .min = 5, .max = 11 },
 182         .p = { .min = 5, .max = 80 },
 183         .p1 = { .min = 1, .max = 8},
 184         .p2 = { .dot_limit = 165000,
 185                 .p2_slow = 10, .p2_fast = 5 },
 186 };
 187
 188 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 189         .dot = { .min = 20000, .max = 115000 },
 190         .vco = { .min = 1750000, .max = 3500000 },
 191         .n = { .min = 1, .max = 3 },
 192         .m = { .min = 104, .max = 138 },
 193         .m1 = { .min = 17, .max = 23 },
 194         .m2 = { .min = 5, .max = 11 },
 195         .p = { .min = 28, .max = 112 },
 196         .p1 = { .min = 2, .max = 8 },
 197         .p2 = { .dot_limit = 0,
 198                 .p2_slow = 14, .p2_fast = 14
 199         },
 200 };
 201
 202 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 203         .dot = { .min = 80000, .max = 224000 },
 204         .vco = { .min = 1750000, .max = 3500000 },
 205         .n = { .min = 1, .max = 3 },
 206         .m = { .min = 104, .max = 138 },
 207         .m1 = { .min = 17, .max = 23 },
 208         .m2 = { .min = 5, .max = 11 },
 209         .p = { .min = 14, .max = 42 },
 210         .p1 = { .min = 2, .max = 6 },
 211         .p2 = { .dot_limit = 0,
 212                 .p2_slow = 7, .p2_fast = 7
 213         },
 214 };
 215
 216 static const intel_limit_t intel_limits_pineview_sdvo = {
 217         .dot = { .min = 20000, .max = 400000},
 218         .vco = { .min = 1700000, .max = 3500000 },
 219         /* Pineview's Ncounter is a ring counter */
 220         .n = { .min = 3, .max = 6 },
 221         .m = { .min = 2, .max = 256 },
 222         /* Pineview only has one combined m divider, which we treat as m2. */
 223         .m1 = { .min = 0, .max = 0 },
 224         .m2 = { .min = 0, .max = 254 },
 225         .p = { .min = 5, .max = 80 },
 226         .p1 = { .min = 1, .max = 8 },
 227         .p2 = { .dot_limit = 200000,
 228                 .p2_slow = 10, .p2_fast = 5 },
 229 };
 230
 231 static const intel_limit_t intel_limits_pineview_lvds = {
 232         .dot = { .min = 20000, .max = 400000 },
 233         .vco = { .min = 1700000, .max = 3500000 },
 234         .n = { .min = 3, .max = 6 },
 235         .m = { .min = 2, .max = 256 },
 236         .m1 = { .min = 0, .max = 0 },
 237         .m2 = { .min = 0, .max = 254 },
 238         .p = { .min = 7, .max = 112 },
 239         .p1 = { .min = 1, .max = 8 },
 240         .p2 = { .dot_limit = 112000,
 241                 .p2_slow = 14, .p2_fast = 14 },
 242 };
 243
 244 /* Ironlake / Sandybridge
 245  *
 246  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 247  * the range value for them is (actual_value - 2).
 248  */
 249 static const intel_limit_t intel_limits_ironlake_dac = {
 250         .dot = { .min = 25000, .max = 350000 },
 251         .vco = { .min = 1760000, .max = 3510000 },
 252         .n = { .min = 1, .max = 5 },
 253         .m = { .min = 79, .max = 127 },
 254         .m1 = { .min = 12, .max = 22 },
 255         .m2 = { .min = 5, .max = 9 },
 256         .p = { .min = 5, .max = 80 },
 257         .p1 = { .min = 1, .max = 8 },
 258         .p2 = { .dot_limit = 225000,
 259                 .p2_slow = 10, .p2_fast = 5 },
 260 };
 261
 262 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 263         .dot = { .min = 25000, .max = 350000 },
 264         .vco = { .min = 1760000, .max = 3510000 },
 265         .n = { .min = 1, .max = 3 },
 266         .m = { .min = 79, .max = 118 },
 267         .m1 = { .min = 12, .max = 22 },
 268         .m2 = { .min = 5, .max = 9 },
 269         .p = { .min = 28, .max = 112 },
 270         .p1 = { .min = 2, .max = 8 },
 271         .p2 = { .dot_limit = 225000,
 272                 .p2_slow = 14, .p2_fast = 14 },
 273 };
 274
 275 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 276         .dot = { .min = 25000, .max = 350000 },
 277         .vco = { .min = 1760000, .max = 3510000 },
 278         .n = { .min = 1, .max = 3 },
 279         .m = { .min = 79, .max = 127 },
 280         .m1 = { .min = 12, .max = 22 },
 281         .m2 = { .min = 5, .max = 9 },
 282         .p = { .min = 14, .max = 56 },
 283         .p1 = { .min = 2, .max = 8 },
 284         .p2 = { .dot_limit = 225000,
 285                 .p2_slow = 7, .p2_fast = 7 },
 286 };
 287
 288 /* LVDS 100mhz refclk limits. */
 289 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 290         .dot = { .min = 25000, .max = 350000 },
 291         .vco = { .min = 1760000, .max = 3510000 },
 292         .n = { .min = 1, .max = 2 },
 293         .m = { .min = 79, .max = 126 },
 294         .m1 = { .min = 12, .max = 22 },
 295         .m2 = { .min = 5, .max = 9 },
 296         .p = { .min = 28, .max = 112 },
 297         .p1 = { .min = 2, .max = 8 },
 298         .p2 = { .dot_limit = 225000,
 299                 .p2_slow = 14, .p2_fast = 14 },
 300 };
 301
 302 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 303         .dot = { .min = 25000, .max = 350000 },
 304         .vco = { .min = 1760000, .max = 3510000 },
 305         .n = { .min = 1, .max = 3 },
 306         .m = { .min = 79, .max = 126 },
 307         .m1 = { .min = 12, .max = 22 },
 308         .m2 = { .min = 5, .max = 9 },
 309         .p = { .min = 14, .max = 42 },
 310         .p1 = { .min = 2, .max = 6 },
 311         .p2 = { .dot_limit = 225000,
 312                 .p2_slow = 7, .p2_fast = 7 },
 313 };
 314
 315 static const intel_limit_t intel_limits_vlv = {
 316          /*
 317           * These are the data rate limits (measured in fast clocks)
 318           * since those are the strictest limits we have. The fast
 319           * clock and actual rate limits are more relaxed, so checking
 320           * them would make no difference.
 321           */
 322         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 323         .vco = { .min = 4000000, .max = 6000000 },
 324         .n = { .min = 1, .max = 7 },
 325         .m1 = { .min = 2, .max = 3 },
 326         .m2 = { .min = 11, .max = 156 },
 327         .p1 = { .min = 2, .max = 3 },
 328         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 329 };
 330
 331 static void vlv_clock(int refclk, intel_clock_t *clock)
 332 {
 333         clock->m = clock->m1 * clock->m2;
 334         clock->p = clock->p1 * clock->p2;
 335         if (WARN_ON(clock->n == 0 || clock->p == 0))
 336                 return;
 337         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 338         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 339 }
 340
 341 /**
 342  * Returns whether any output on the specified pipe is of the specified type
 343  */
 344 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 345 {
 346         struct drm_device *dev = crtc->dev;
 347         struct intel_encoder *encoder;
 348
 349         for_each_encoder_on_crtc(dev, crtc, encoder)
 350                 if (encoder->type == type)
 351                         return true;
 352
 353         return false;
 354 }
 355
 356 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 357                                                 int refclk)
 358 {
 359         struct drm_device *dev = crtc->dev;
 360         const intel_limit_t *limit;
 361
 362         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 363                 if (intel_is_dual_link_lvds(dev)) {
 364                         if (refclk == 100000)
 365                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 366                         else
 367                                 limit = &intel_limits_ironlake_dual_lvds;
 368                 } else {
 369                         if (refclk == 100000)
 370                                 limit = &intel_limits_ironlake_single_lvds_100m;
 371                         else
 372                                 limit = &intel_limits_ironlake_single_lvds;
 373                 }
 374         } else
 375                 limit = &intel_limits_ironlake_dac;
 376
 377         return limit;
 378 }
 379
 380 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 381 {
 382         struct drm_device *dev = crtc->dev;
 383         const intel_limit_t *limit;
 384
 385         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 386                 if (intel_is_dual_link_lvds(dev))
 387                         limit = &intel_limits_g4x_dual_channel_lvds;
 388                 else
 389                         limit = &intel_limits_g4x_single_channel_lvds;
 390         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 391                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 392                 limit = &intel_limits_g4x_hdmi;
 393         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 394                 limit = &intel_limits_g4x_sdvo;
 395         } else /* The option is for other outputs */
 396                 limit = &intel_limits_i9xx_sdvo;
 397
 398         return limit;
 399 }
 400
 401 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 402 {
 403         struct drm_device *dev = crtc->dev;
 404         const intel_limit_t *limit;
 405
 406         if (HAS_PCH_SPLIT(dev))
 407                 limit = intel_ironlake_limit(crtc, refclk);
 408         else if (IS_G4X(dev)) {
 409                 limit = intel_g4x_limit(crtc);
 410         } else if (IS_PINEVIEW(dev)) {
 411                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 412                         limit = &intel_limits_pineview_lvds;
 413                 else
 414                         limit = &intel_limits_pineview_sdvo;
 415         } else if (IS_VALLEYVIEW(dev)) {
 416                 limit = &intel_limits_vlv;
 417         } else if (!IS_GEN2(dev)) {
 418                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 419                         limit = &intel_limits_i9xx_lvds;
 420                 else
 421                         limit = &intel_limits_i9xx_sdvo;
 422         } else {
 423                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 424                         limit = &intel_limits_i8xx_lvds;
 425                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 426                         limit = &intel_limits_i8xx_dvo;
 427                 else
 428                         limit = &intel_limits_i8xx_dac;
 429         }
 430         return limit;
 431 }
 432
 433 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 434 static void pineview_clock(int refclk, intel_clock_t *clock)
 435 {
 436         clock->m = clock->m2 + 2;
 437         clock->p = clock->p1 * clock->p2;
 438         if (WARN_ON(clock->n == 0 || clock->p == 0))
 439                 return;
 440         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 441         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 442 }
 443
 444 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 445 {
 446         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 447 }
 448
 449 static void i9xx_clock(int refclk, intel_clock_t *clock)
 450 {
 451         clock->m = i9xx_dpll_compute_m(clock);
 452         clock->p = clock->p1 * clock->p2;
 453         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 454                 return;
 455         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 456         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 457 }
 458
 459 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 460 /**
 461  * Returns whether the given set of divisors are valid for a given refclk with
 462  * the given connectors.
 463  */
 464
 465 static bool intel_PLL_is_valid(struct drm_device *dev,
 466                                const intel_limit_t *limit,
 467                                const intel_clock_t *clock)
 468 {
 469         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 470                 INTELPllInvalid("n out of range\n");
 471         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 472                 INTELPllInvalid("p1 out of range\n");
 473         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 474                 INTELPllInvalid("m2 out of range\n");
 475         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 476                 INTELPllInvalid("m1 out of range\n");
 477
 478         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 479                 if (clock->m1 <= clock->m2)
 480                         INTELPllInvalid("m1 <= m2\n");
 481
 482         if (!IS_VALLEYVIEW(dev)) {
 483                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 484                         INTELPllInvalid("p out of range\n");
 485                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 486                         INTELPllInvalid("m out of range\n");
 487         }
 488
 489         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 490                 INTELPllInvalid("vco out of range\n");
 491         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 492          * connector, etc., rather than just a single range.
 493          */
 494         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 495                 INTELPllInvalid("dot out of range\n");
 496
 497         return true;
 498 }
 499
 500 static bool
 501 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 502                     int target, int refclk, intel_clock_t *match_clock,
 503                     intel_clock_t *best_clock)
 504 {
 505         struct drm_device *dev = crtc->dev;
 506         intel_clock_t clock;
 507         int err = target;
 508
 509         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 510                 /*
 511                  * For LVDS just rely on its current settings for dual-channel.
 512                  * We haven't figured out how to reliably set up different
 513                  * single/dual channel state, if we even can.
 514                  */
 515                 if (intel_is_dual_link_lvds(dev))
 516                         clock.p2 = limit->p2.p2_fast;
 517                 else
 518                         clock.p2 = limit->p2.p2_slow;
 519         } else {
 520                 if (target < limit->p2.dot_limit)
 521                         clock.p2 = limit->p2.p2_slow;
 522                 else
 523                         clock.p2 = limit->p2.p2_fast;
 524         }
 525
 526         memset(best_clock, 0, sizeof(*best_clock));
 527
 528         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 529              clock.m1++) {
 530                 for (clock.m2 = limit->m2.min;
 531                      clock.m2 <= limit->m2.max; clock.m2++) {
 532                         if (clock.m2 >= clock.m1)
 533                                 break;
 534                         for (clock.n = limit->n.min;
 535                              clock.n <= limit->n.max; clock.n++) {
 536                                 for (clock.p1 = limit->p1.min;
 537                                         clock.p1 <= limit->p1.max; clock.p1++) {
 538                                         int this_err;
 539
 540                                         i9xx_clock(refclk, &clock);
 541                                         if (!intel_PLL_is_valid(dev, limit,
 542                                                                 &clock))
 543                                                 continue;
 544                                         if (match_clock &&
 545                                             clock.p != match_clock->p)
 546                                                 continue;
 547
 548                                         this_err = abs(clock.dot - target);
 549                                         if (this_err < err) {
 550                                                 *best_clock = clock;
 551                                                 err = this_err;
 552                                         }
 553                                 }
 554                         }
 555                 }
 556         }
 557
 558         return (err != target);
 559 }
 560
 561 static bool
 562 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 563                    int target, int refclk, intel_clock_t *match_clock,
 564                    intel_clock_t *best_clock)
 565 {
 566         struct drm_device *dev = crtc->dev;
 567         intel_clock_t clock;
 568         int err = target;
 569
 570         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 571                 /*
 572                  * For LVDS just rely on its current settings for dual-channel.
 573                  * We haven't figured out how to reliably set up different
 574                  * single/dual channel state, if we even can.
 575                  */
 576                 if (intel_is_dual_link_lvds(dev))
 577                         clock.p2 = limit->p2.p2_fast;
 578                 else
 579                         clock.p2 = limit->p2.p2_slow;
 580         } else {
 581                 if (target < limit->p2.dot_limit)
 582                         clock.p2 = limit->p2.p2_slow;
 583                 else
 584                         clock.p2 = limit->p2.p2_fast;
 585         }
 586
 587         memset(best_clock, 0, sizeof(*best_clock));
 588
 589         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 590              clock.m1++) {
 591                 for (clock.m2 = limit->m2.min;
 592                      clock.m2 <= limit->m2.max; clock.m2++) {
 593                         for (clock.n = limit->n.min;
 594                              clock.n <= limit->n.max; clock.n++) {
 595                                 for (clock.p1 = limit->p1.min;
 596                                         clock.p1 <= limit->p1.max; clock.p1++) {
 597                                         int this_err;
 598
 599                                         pineview_clock(refclk, &clock);
 600                                         if (!intel_PLL_is_valid(dev, limit,
 601                                                                 &clock))
 602                                                 continue;
 603                                         if (match_clock &&
 604                                             clock.p != match_clock->p)
 605                                                 continue;
 606
 607                                         this_err = abs(clock.dot - target);
 608                                         if (this_err < err) {
 609                                                 *best_clock = clock;
 610                                                 err = this_err;
 611                                         }
 612                                 }
 613                         }
 614                 }
 615         }
 616
 617         return (err != target);
 618 }
 619
 620 static bool
 621 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 622                    int target, int refclk, intel_clock_t *match_clock,
 623                    intel_clock_t *best_clock)
 624 {
 625         struct drm_device *dev = crtc->dev;
 626         intel_clock_t clock;
 627         int max_n;
 628         bool found;
 629         /* approximately equals target * 0.00585 */
 630         int err_most = (target >> 8) + (target >> 9);
 631         found = false;
 632
 633         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 634                 if (intel_is_dual_link_lvds(dev))
 635                         clock.p2 = limit->p2.p2_fast;
 636                 else
 637                         clock.p2 = limit->p2.p2_slow;
 638         } else {
 639                 if (target < limit->p2.dot_limit)
 640                         clock.p2 = limit->p2.p2_slow;
 641                 else
 642                         clock.p2 = limit->p2.p2_fast;
 643         }
 644
 645         memset(best_clock, 0, sizeof(*best_clock));
 646         max_n = limit->n.max;
 647         /* based on hardware requirement, prefer smaller n to precision */
 648         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 649                 /* based on hardware requirement, prefere larger m1,m2 */
 650                 for (clock.m1 = limit->m1.max;
 651                      clock.m1 >= limit->m1.min; clock.m1--) {
 652                         for (clock.m2 = limit->m2.max;
 653                              clock.m2 >= limit->m2.min; clock.m2--) {
 654                                 for (clock.p1 = limit->p1.max;
 655                                      clock.p1 >= limit->p1.min; clock.p1--) {
 656                                         int this_err;
 657
 658                                         i9xx_clock(refclk, &clock);
 659                                         if (!intel_PLL_is_valid(dev, limit,
 660                                                                 &clock))
 661                                                 continue;
 662
 663                                         this_err = abs(clock.dot - target);
 664                                         if (this_err < err_most) {
 665                                                 *best_clock = clock;
 666                                                 err_most = this_err;
 667                                                 max_n = clock.n;
 668                                                 found = true;
 669                                         }
 670                                 }
 671                         }
 672                 }
 673         }
 674         return found;
 675 }
 676
 677 static bool
 678 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 679                    int target, int refclk, intel_clock_t *match_clock,
 680                    intel_clock_t *best_clock)
 681 {
 682         struct drm_device *dev = crtc->dev;
 683         intel_clock_t clock;
 684         unsigned int bestppm = 1000000;
 685         /* min update 19.2 MHz */
 686         int max_n = min(limit->n.max, refclk / 19200);
 687         bool found = false;
 688
 689         target *= 5; /* fast clock */
 690
 691         memset(best_clock, 0, sizeof(*best_clock));
 692
 693         /* based on hardware requirement, prefer smaller n to precision */
 694         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 695                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 696                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 697                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 698                                 clock.p = clock.p1 * clock.p2;
 699                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 700                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 701                                         unsigned int ppm, diff;
 702
 703                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 704                                                                      refclk * clock.m1);
 705
 706                                         vlv_clock(refclk, &clock);
 707
 708                                         if (!intel_PLL_is_valid(dev, limit,
 709                                                                 &clock))
 710                                                 continue;
 711
 712                                         diff = abs(clock.dot - target);
 713                                         ppm = div_u64(1000000ULL * diff, target);
 714
 715                                         if (ppm < 100 && clock.p > best_clock->p) {
 716                                                 bestppm = 0;
 717                                                 *best_clock = clock;
 718                                                 found = true;
 719                                         }
 720
 721                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 722                                                 bestppm = ppm;
 723                                                 *best_clock = clock;
 724                                                 found = true;
 725                                         }
 726                                 }
 727                         }
 728                 }
 729         }
 730
 731         return found;
 732 }
 733
 734 bool intel_crtc_active(struct drm_crtc *crtc)
 735 {
 736         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 737
 738         /* Be paranoid as we can arrive here with only partial
 739          * state retrieved from the hardware during setup.
 740          *
 741          * We can ditch the adjusted_mode.crtc_clock check as soon
 742          * as Haswell has gained clock readout/fastboot support.
 743          *
 744          * We can ditch the crtc->primary->fb check as soon as we can
 745          * properly reconstruct framebuffers.
 746          */
 747         return intel_crtc->active && crtc->primary->fb &&
 748                 intel_crtc->config.adjusted_mode.crtc_clock;
 749 }
 750
 751 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 752                                              enum pipe pipe)
 753 {
 754         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 755         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 756
 757         return intel_crtc->config.cpu_transcoder;
 758 }
 759
 760 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
 761 {
 762         struct drm_i915_private *dev_priv = dev->dev_private;
 763         u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
 764
 765         frame = I915_READ(frame_reg);
 766
 767         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 768                 WARN(1, "vblank wait timed out\n");
 769 }
 770
 771 /**
 772  * intel_wait_for_vblank - wait for vblank on a given pipe
 773  * @dev: drm device
 774  * @pipe: pipe to wait for
 775  *
 776  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 777  * mode setting code.
 778  */
 779 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 780 {
 781         struct drm_i915_private *dev_priv = dev->dev_private;
 782         int pipestat_reg = PIPESTAT(pipe);
 783
 784         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 785                 g4x_wait_for_vblank(dev, pipe);
 786                 return;
 787         }
 788
 789         /* Clear existing vblank status. Note this will clear any other
 790          * sticky status fields as well.
 791          *
 792          * This races with i915_driver_irq_handler() with the result
 793          * that either function could miss a vblank event.  Here it is not
 794          * fatal, as we will either wait upon the next vblank interrupt or
 795          * timeout.  Generally speaking intel_wait_for_vblank() is only
 796          * called during modeset at which time the GPU should be idle and
 797          * should *not* be performing page flips and thus not waiting on
 798          * vblanks...
 799          * Currently, the result of us stealing a vblank from the irq
 800          * handler is that a single frame will be skipped during swapbuffers.
 801          */
 802         I915_WRITE(pipestat_reg,
 803                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 804
 805         /* Wait for vblank interrupt bit to set */
 806         if (wait_for(I915_READ(pipestat_reg) &
 807                      PIPE_VBLANK_INTERRUPT_STATUS,
 808                      50))
 809                 DRM_DEBUG_KMS("vblank wait timed out\n");
 810 }
 811
 812 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 813 {
 814         struct drm_i915_private *dev_priv = dev->dev_private;
 815         u32 reg = PIPEDSL(pipe);
 816         u32 line1, line2;
 817         u32 line_mask;
 818
 819         if (IS_GEN2(dev))
 820                 line_mask = DSL_LINEMASK_GEN2;
 821         else
 822                 line_mask = DSL_LINEMASK_GEN3;
 823
 824         line1 = I915_READ(reg) & line_mask;
 825         mdelay(5);
 826         line2 = I915_READ(reg) & line_mask;
 827
 828         return line1 == line2;
 829 }
 830
 831 /*
 832  * intel_wait_for_pipe_off - wait for pipe to turn off
 833  * @dev: drm device
 834  * @pipe: pipe to wait for
 835  *
 836  * After disabling a pipe, we can't wait for vblank in the usual way,
 837  * spinning on the vblank interrupt status bit, since we won't actually
 838  * see an interrupt when the pipe is disabled.
 839  *
 840  * On Gen4 and above:
 841  *   wait for the pipe register state bit to turn off
 842  *
 843  * Otherwise:
 844  *   wait for the display line value to settle (it usually
 845  *   ends up stopping at the start of the next frame).
 846  *
 847  */
 848 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 849 {
 850         struct drm_i915_private *dev_priv = dev->dev_private;
 851         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 852                                                                       pipe);
 853
 854         if (INTEL_INFO(dev)->gen >= 4) {
 855                 int reg = PIPECONF(cpu_transcoder);
 856
 857                 /* Wait for the Pipe State to go off */
 858                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 859                              100))
 860                         WARN(1, "pipe_off wait timed out\n");
 861         } else {
 862                 /* Wait for the display line to settle */
 863                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 864                         WARN(1, "pipe_off wait timed out\n");
 865         }
 866 }
 867
 868 /*
 869  * ibx_digital_port_connected - is the specified port connected?
 870  * @dev_priv: i915 private structure
 871  * @port: the port to test
 872  *
 873  * Returns true if @port is connected, false otherwise.
 874  */
 875 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 876                                 struct intel_digital_port *port)
 877 {
 878         u32 bit;
 879
 880         if (HAS_PCH_IBX(dev_priv->dev)) {
 881                 switch(port->port) {
 882                 case PORT_B:
 883                         bit = SDE_PORTB_HOTPLUG;
 884                         break;
 885                 case PORT_C:
 886                         bit = SDE_PORTC_HOTPLUG;
 887                         break;
 888                 case PORT_D:
 889                         bit = SDE_PORTD_HOTPLUG;
 890                         break;
 891                 default:
 892                         return true;
 893                 }
 894         } else {
 895                 switch(port->port) {
 896                 case PORT_B:
 897                         bit = SDE_PORTB_HOTPLUG_CPT;
 898                         break;
 899                 case PORT_C:
 900                         bit = SDE_PORTC_HOTPLUG_CPT;
 901                         break;
 902                 case PORT_D:
 903                         bit = SDE_PORTD_HOTPLUG_CPT;
 904                         break;
 905                 default:
 906                         return true;
 907                 }
 908         }
 909
 910         return I915_READ(SDEISR) & bit;
 911 }
 912
 913 static const char *state_string(bool enabled)
 914 {
 915         return enabled ? "on" : "off";
 916 }
 917
 918 /* Only for pre-ILK configs */
 919 void assert_pll(struct drm_i915_private *dev_priv,
 920                 enum pipe pipe, bool state)
 921 {
 922         int reg;
 923         u32 val;
 924         bool cur_state;
 925
 926         reg = DPLL(pipe);
 927         val = I915_READ(reg);
 928         cur_state = !!(val & DPLL_VCO_ENABLE);
 929         WARN(cur_state != state,
 930              "PLL state assertion failure (expected %s, current %s)\n",
 931              state_string(state), state_string(cur_state));
 932 }
 933
 934 /* XXX: the dsi pll is shared between MIPI DSI ports */
 935 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
 936 {
 937         u32 val;
 938         bool cur_state;
 939
 940         mutex_lock(&dev_priv->dpio_lock);
 941         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
 942         mutex_unlock(&dev_priv->dpio_lock);
 943
 944         cur_state = val & DSI_PLL_VCO_EN;
 945         WARN(cur_state != state,
 946              "DSI PLL state assertion failure (expected %s, current %s)\n",
 947              state_string(state), state_string(cur_state));
 948 }
 949 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
 950 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
 951
 952 struct intel_shared_dpll *
 953 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 954 {
 955         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 956
 957         if (crtc->config.shared_dpll < 0)
 958                 return NULL;
 959
 960         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
 961 }
 962
 963 /* For ILK+ */
 964 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 965                         struct intel_shared_dpll *pll,
 966                         bool state)
 967 {
 968         bool cur_state;
 969         struct intel_dpll_hw_state hw_state;
 970
 971         if (HAS_PCH_LPT(dev_priv->dev)) {
 972                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 973                 return;
 974         }
 975
 976         if (WARN (!pll,
 977                   "asserting DPLL %s with no DPLL\n", state_string(state)))
 978                 return;
 979
 980         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
 981         WARN(cur_state != state,
 982              "%s assertion failure (expected %s, current %s)\n",
 983              pll->name, state_string(state), state_string(cur_state));
 984 }
 985
 986 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 987                           enum pipe pipe, bool state)
 988 {
 989         int reg;
 990         u32 val;
 991         bool cur_state;
 992         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 993                                                                       pipe);
 994
 995         if (HAS_DDI(dev_priv->dev)) {
 996                 /* DDI does not have a specific FDI_TX register */
 997                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 998                 val = I915_READ(reg);
 999                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1000         } else {
1001                 reg = FDI_TX_CTL(pipe);
1002                 val = I915_READ(reg);
1003                 cur_state = !!(val & FDI_TX_ENABLE);
1004         }
1005         WARN(cur_state != state,
1006              "FDI TX state assertion failure (expected %s, current %s)\n",
1007              state_string(state), state_string(cur_state));
1008 }
1009 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1010 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1011
1012 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1013                           enum pipe pipe, bool state)
1014 {
1015         int reg;
1016         u32 val;
1017         bool cur_state;
1018
1019         reg = FDI_RX_CTL(pipe);
1020         val = I915_READ(reg);
1021         cur_state = !!(val & FDI_RX_ENABLE);
1022         WARN(cur_state != state,
1023              "FDI RX state assertion failure (expected %s, current %s)\n",
1024              state_string(state), state_string(cur_state));
1025 }
1026 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1027 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1028
1029 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1030                                       enum pipe pipe)
1031 {
1032         int reg;
1033         u32 val;
1034
1035         /* ILK FDI PLL is always enabled */
1036         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1037                 return;
1038
1039         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1040         if (HAS_DDI(dev_priv->dev))
1041                 return;
1042
1043         reg = FDI_TX_CTL(pipe);
1044         val = I915_READ(reg);
1045         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1046 }
1047
1048 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1049                        enum pipe pipe, bool state)
1050 {
1051         int reg;
1052         u32 val;
1053         bool cur_state;
1054
1055         reg = FDI_RX_CTL(pipe);
1056         val = I915_READ(reg);
1057         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1058         WARN(cur_state != state,
1059              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1060              state_string(state), state_string(cur_state));
1061 }
1062
1063 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1064                                   enum pipe pipe)
1065 {
1066         int pp_reg, lvds_reg;
1067         u32 val;
1068         enum pipe panel_pipe = PIPE_A;
1069         bool locked = true;
1070
1071         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1072                 pp_reg = PCH_PP_CONTROL;
1073                 lvds_reg = PCH_LVDS;
1074         } else {
1075                 pp_reg = PP_CONTROL;
1076                 lvds_reg = LVDS;
1077         }
1078
1079         val = I915_READ(pp_reg);
1080         if (!(val & PANEL_POWER_ON) ||
1081             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1082                 locked = false;
1083
1084         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1085                 panel_pipe = PIPE_B;
1086
1087         WARN(panel_pipe == pipe && locked,
1088              "panel assertion failure, pipe %c regs locked\n",
1089              pipe_name(pipe));
1090 }
1091
1092 static void assert_cursor(struct drm_i915_private *dev_priv,
1093                           enum pipe pipe, bool state)
1094 {
1095         struct drm_device *dev = dev_priv->dev;
1096         bool cur_state;
1097
1098         if (IS_845G(dev) || IS_I865G(dev))
1099                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1100         else if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev))
1101                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1102         else
1103                 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1104
1105         WARN(cur_state != state,
1106              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1107              pipe_name(pipe), state_string(state), state_string(cur_state));
1108 }
1109 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1110 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1111
1112 void assert_pipe(struct drm_i915_private *dev_priv,
1113                  enum pipe pipe, bool state)
1114 {
1115         int reg;
1116         u32 val;
1117         bool cur_state;
1118         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1119                                                                       pipe);
1120
1121         /* if we need the pipe A quirk it must be always on */
1122         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1123                 state = true;
1124
1125         if (!intel_display_power_enabled(dev_priv,
1126                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1127                 cur_state = false;
1128         } else {
1129                 reg = PIPECONF(cpu_transcoder);
1130                 val = I915_READ(reg);
1131                 cur_state = !!(val & PIPECONF_ENABLE);
1132         }
1133
1134         WARN(cur_state != state,
1135              "pipe %c assertion failure (expected %s, current %s)\n",
1136              pipe_name(pipe), state_string(state), state_string(cur_state));
1137 }
1138
1139 static void assert_plane(struct drm_i915_private *dev_priv,
1140                          enum plane plane, bool state)
1141 {
1142         int reg;
1143         u32 val;
1144         bool cur_state;
1145
1146         reg = DSPCNTR(plane);
1147         val = I915_READ(reg);
1148         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1149         WARN(cur_state != state,
1150              "plane %c assertion failure (expected %s, current %s)\n",
1151              plane_name(plane), state_string(state), state_string(cur_state));
1152 }
1153
1154 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1155 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1156
1157 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1158                                    enum pipe pipe)
1159 {
1160         struct drm_device *dev = dev_priv->dev;
1161         int reg, i;
1162         u32 val;
1163         int cur_pipe;
1164
1165         /* Primary planes are fixed to pipes on gen4+ */
1166         if (INTEL_INFO(dev)->gen >= 4) {
1167                 reg = DSPCNTR(pipe);
1168                 val = I915_READ(reg);
1169                 WARN(val & DISPLAY_PLANE_ENABLE,
1170                      "plane %c assertion failure, should be disabled but not\n",
1171                      plane_name(pipe));
1172                 return;
1173         }
1174
1175         /* Need to check both planes against the pipe */
1176         for_each_pipe(i) {
1177                 reg = DSPCNTR(i);
1178                 val = I915_READ(reg);
1179                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1180                         DISPPLANE_SEL_PIPE_SHIFT;
1181                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1182                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1183                      plane_name(i), pipe_name(pipe));
1184         }
1185 }
1186
1187 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1188                                     enum pipe pipe)
1189 {
1190         struct drm_device *dev = dev_priv->dev;
1191         int reg, sprite;
1192         u32 val;
1193
1194         if (IS_VALLEYVIEW(dev)) {
1195                 for_each_sprite(pipe, sprite) {
1196                         reg = SPCNTR(pipe, sprite);
1197                         val = I915_READ(reg);
1198                         WARN(val & SP_ENABLE,
1199                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1200                              sprite_name(pipe, sprite), pipe_name(pipe));
1201                 }
1202         } else if (INTEL_INFO(dev)->gen >= 7) {
1203                 reg = SPRCTL(pipe);
1204                 val = I915_READ(reg);
1205                 WARN(val & SPRITE_ENABLE,
1206                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1207                      plane_name(pipe), pipe_name(pipe));
1208         } else if (INTEL_INFO(dev)->gen >= 5) {
1209                 reg = DVSCNTR(pipe);
1210                 val = I915_READ(reg);
1211                 WARN(val & DVS_ENABLE,
1212                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1213                      plane_name(pipe), pipe_name(pipe));
1214         }
1215 }
1216
1217 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1218 {
1219         u32 val;
1220         bool enabled;
1221
1222         WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1223
1224         val = I915_READ(PCH_DREF_CONTROL);
1225         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1226                             DREF_SUPERSPREAD_SOURCE_MASK));
1227         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1228 }
1229
1230 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1231                                            enum pipe pipe)
1232 {
1233         int reg;
1234         u32 val;
1235         bool enabled;
1236
1237         reg = PCH_TRANSCONF(pipe);
1238         val = I915_READ(reg);
1239         enabled = !!(val & TRANS_ENABLE);
1240         WARN(enabled,
1241              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1242              pipe_name(pipe));
1243 }
1244
1245 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1246                             enum pipe pipe, u32 port_sel, u32 val)
1247 {
1248         if ((val & DP_PORT_EN) == 0)
1249                 return false;
1250
1251         if (HAS_PCH_CPT(dev_priv->dev)) {
1252                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1253                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1254                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1255                         return false;
1256         } else {
1257                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1258                         return false;
1259         }
1260         return true;
1261 }
1262
1263 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1264                               enum pipe pipe, u32 val)
1265 {
1266         if ((val & SDVO_ENABLE) == 0)
1267                 return false;
1268
1269         if (HAS_PCH_CPT(dev_priv->dev)) {
1270                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1271                         return false;
1272         } else {
1273                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1274                         return false;
1275         }
1276         return true;
1277 }
1278
1279 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1280                               enum pipe pipe, u32 val)
1281 {
1282         if ((val & LVDS_PORT_EN) == 0)
1283                 return false;
1284
1285         if (HAS_PCH_CPT(dev_priv->dev)) {
1286                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1287                         return false;
1288         } else {
1289                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1290                         return false;
1291         }
1292         return true;
1293 }
1294
1295 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1296                               enum pipe pipe, u32 val)
1297 {
1298         if ((val & ADPA_DAC_ENABLE) == 0)
1299                 return false;
1300         if (HAS_PCH_CPT(dev_priv->dev)) {
1301                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1302                         return false;
1303         } else {
1304                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1305                         return false;
1306         }
1307         return true;
1308 }
1309
1310 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1311                                    enum pipe pipe, int reg, u32 port_sel)
1312 {
1313         u32 val = I915_READ(reg);
1314         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1315              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1316              reg, pipe_name(pipe));
1317
1318         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1319              && (val & DP_PIPEB_SELECT),
1320              "IBX PCH dp port still using transcoder B\n");
1321 }
1322
1323 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1324                                      enum pipe pipe, int reg)
1325 {
1326         u32 val = I915_READ(reg);
1327         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1328              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1329              reg, pipe_name(pipe));
1330
1331         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1332              && (val & SDVO_PIPE_B_SELECT),
1333              "IBX PCH hdmi port still using transcoder B\n");
1334 }
1335
1336 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1337                                       enum pipe pipe)
1338 {
1339         int reg;
1340         u32 val;
1341
1342         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1343         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1344         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1345
1346         reg = PCH_ADPA;
1347         val = I915_READ(reg);
1348         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1349              "PCH VGA enabled on transcoder %c, should be disabled\n",
1350              pipe_name(pipe));
1351
1352         reg = PCH_LVDS;
1353         val = I915_READ(reg);
1354         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1355              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1356              pipe_name(pipe));
1357
1358         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1359         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1360         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1361 }
1362
1363 static void intel_init_dpio(struct drm_device *dev)
1364 {
1365         struct drm_i915_private *dev_priv = dev->dev_private;
1366
1367         if (!IS_VALLEYVIEW(dev))
1368                 return;
1369
1370         /*
1371          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1372          * CHV x1 PHY (DP/HDMI D)
1373          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1374          */
1375         if (IS_CHERRYVIEW(dev)) {
1376                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1377                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1378         } else {
1379                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1380         }
1381 }
1382
1383 static void intel_reset_dpio(struct drm_device *dev)
1384 {
1385         struct drm_i915_private *dev_priv = dev->dev_private;
1386
1387         if (!IS_VALLEYVIEW(dev))
1388                 return;
1389
1390         /*
1391          * Enable the CRI clock source so we can get at the display and the
1392          * reference clock for VGA hotplug / manual detection.
1393          */
1394         I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
1395                    DPLL_REFA_CLK_ENABLE_VLV |
1396                    DPLL_INTEGRATED_CRI_CLK_VLV);
1397
1398         /*
1399          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1400          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1401          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1402          *   b. The other bits such as sfr settings / modesel may all be set
1403          *      to 0.
1404          *
1405          * This should only be done on init and resume from S3 with both
1406          * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1407          */
1408         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1409 }
1410
1411 static void vlv_enable_pll(struct intel_crtc *crtc)
1412 {
1413         struct drm_device *dev = crtc->base.dev;
1414         struct drm_i915_private *dev_priv = dev->dev_private;
1415         int reg = DPLL(crtc->pipe);
1416         u32 dpll = crtc->config.dpll_hw_state.dpll;
1417
1418         assert_pipe_disabled(dev_priv, crtc->pipe);
1419
1420         /* No really, not for ILK+ */
1421         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1422
1423         /* PLL is protected by panel, make sure we can write it */
1424         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1425                 assert_panel_unlocked(dev_priv, crtc->pipe);
1426
1427         I915_WRITE(reg, dpll);
1428         POSTING_READ(reg);
1429         udelay(150);
1430
1431         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1432                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1433
1434         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1435         POSTING_READ(DPLL_MD(crtc->pipe));
1436
1437         /* We do this three times for luck */
1438         I915_WRITE(reg, dpll);
1439         POSTING_READ(reg);
1440         udelay(150); /* wait for warmup */
1441         I915_WRITE(reg, dpll);
1442         POSTING_READ(reg);
1443         udelay(150); /* wait for warmup */
1444         I915_WRITE(reg, dpll);
1445         POSTING_READ(reg);
1446         udelay(150); /* wait for warmup */
1447 }
1448
1449 static void i9xx_enable_pll(struct intel_crtc *crtc)
1450 {
1451         struct drm_device *dev = crtc->base.dev;
1452         struct drm_i915_private *dev_priv = dev->dev_private;
1453         int reg = DPLL(crtc->pipe);
1454         u32 dpll = crtc->config.dpll_hw_state.dpll;
1455
1456         assert_pipe_disabled(dev_priv, crtc->pipe);
1457
1458         /* No really, not for ILK+ */
1459         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1460
1461         /* PLL is protected by panel, make sure we can write it */
1462         if (IS_MOBILE(dev) && !IS_I830(dev))
1463                 assert_panel_unlocked(dev_priv, crtc->pipe);
1464
1465         I915_WRITE(reg, dpll);
1466
1467         /* Wait for the clocks to stabilize. */
1468         POSTING_READ(reg);
1469         udelay(150);
1470
1471         if (INTEL_INFO(dev)->gen >= 4) {
1472                 I915_WRITE(DPLL_MD(crtc->pipe),
1473                            crtc->config.dpll_hw_state.dpll_md);
1474         } else {
1475                 /* The pixel multiplier can only be updated once the
1476                  * DPLL is enabled and the clocks are stable.
1477                  *
1478                  * So write it again.
1479                  */
1480                 I915_WRITE(reg, dpll);
1481         }
1482
1483         /* We do this three times for luck */
1484         I915_WRITE(reg, dpll);
1485         POSTING_READ(reg);
1486         udelay(150); /* wait for warmup */
1487         I915_WRITE(reg, dpll);
1488         POSTING_READ(reg);
1489         udelay(150); /* wait for warmup */
1490         I915_WRITE(reg, dpll);
1491         POSTING_READ(reg);
1492         udelay(150); /* wait for warmup */
1493 }
1494
1495 /**
1496  * i9xx_disable_pll - disable a PLL
1497  * @dev_priv: i915 private structure
1498  * @pipe: pipe PLL to disable
1499  *
1500  * Disable the PLL for @pipe, making sure the pipe is off first.
1501  *
1502  * Note!  This is for pre-ILK only.
1503  */
1504 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1505 {
1506         /* Don't disable pipe A or pipe A PLLs if needed */
1507         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1508                 return;
1509
1510         /* Make sure the pipe isn't still relying on us */
1511         assert_pipe_disabled(dev_priv, pipe);
1512
1513         I915_WRITE(DPLL(pipe), 0);
1514         POSTING_READ(DPLL(pipe));
1515 }
1516
1517 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1518 {
1519         u32 val = 0;
1520
1521         /* Make sure the pipe isn't still relying on us */
1522         assert_pipe_disabled(dev_priv, pipe);
1523
1524         /*
1525          * Leave integrated clock source and reference clock enabled for pipe B.
1526          * The latter is needed for VGA hotplug / manual detection.
1527          */
1528         if (pipe == PIPE_B)
1529                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1530         I915_WRITE(DPLL(pipe), val);
1531         POSTING_READ(DPLL(pipe));
1532 }
1533
1534 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1535                 struct intel_digital_port *dport)
1536 {
1537         u32 port_mask;
1538
1539         switch (dport->port) {
1540         case PORT_B:
1541                 port_mask = DPLL_PORTB_READY_MASK;
1542                 break;
1543         case PORT_C:
1544                 port_mask = DPLL_PORTC_READY_MASK;
1545                 break;
1546         default:
1547                 BUG();
1548         }
1549
1550         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1551                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1552                      port_name(dport->port), I915_READ(DPLL(0)));
1553 }
1554
1555 /**
1556  * ironlake_enable_shared_dpll - enable PCH PLL
1557  * @dev_priv: i915 private structure
1558  * @pipe: pipe PLL to enable
1559  *
1560  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1561  * drives the transcoder clock.
1562  */
1563 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1564 {
1565         struct drm_device *dev = crtc->base.dev;
1566         struct drm_i915_private *dev_priv = dev->dev_private;
1567         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1568
1569         /* PCH PLLs only available on ILK, SNB and IVB */
1570         BUG_ON(INTEL_INFO(dev)->gen < 5);
1571         if (WARN_ON(pll == NULL))
1572                 return;
1573
1574         if (WARN_ON(pll->refcount == 0))
1575                 return;
1576
1577         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1578                       pll->name, pll->active, pll->on,
1579                       crtc->base.base.id);
1580
1581         if (pll->active++) {
1582                 WARN_ON(!pll->on);
1583                 assert_shared_dpll_enabled(dev_priv, pll);
1584                 return;
1585         }
1586         WARN_ON(pll->on);
1587
1588         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1589         pll->enable(dev_priv, pll);
1590         pll->on = true;
1591 }
1592
1593 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1594 {
1595         struct drm_device *dev = crtc->base.dev;
1596         struct drm_i915_private *dev_priv = dev->dev_private;
1597         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1598
1599         /* PCH only available on ILK+ */
1600         BUG_ON(INTEL_INFO(dev)->gen < 5);
1601         if (WARN_ON(pll == NULL))
1602                return;
1603
1604         if (WARN_ON(pll->refcount == 0))
1605                 return;
1606
1607         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1608                       pll->name, pll->active, pll->on,
1609                       crtc->base.base.id);
1610
1611         if (WARN_ON(pll->active == 0)) {
1612                 assert_shared_dpll_disabled(dev_priv, pll);
1613                 return;
1614         }
1615
1616         assert_shared_dpll_enabled(dev_priv, pll);
1617         WARN_ON(!pll->on);
1618         if (--pll->active)
1619                 return;
1620
1621         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1622         pll->disable(dev_priv, pll);
1623         pll->on = false;
1624 }
1625
1626 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1627                                            enum pipe pipe)
1628 {
1629         struct drm_device *dev = dev_priv->dev;
1630         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1631         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1632         uint32_t reg, val, pipeconf_val;
1633
1634         /* PCH only available on ILK+ */
1635         BUG_ON(INTEL_INFO(dev)->gen < 5);
1636
1637         /* Make sure PCH DPLL is enabled */
1638         assert_shared_dpll_enabled(dev_priv,
1639                                    intel_crtc_to_shared_dpll(intel_crtc));
1640
1641         /* FDI must be feeding us bits for PCH ports */
1642         assert_fdi_tx_enabled(dev_priv, pipe);
1643         assert_fdi_rx_enabled(dev_priv, pipe);
1644
1645         if (HAS_PCH_CPT(dev)) {
1646                 /* Workaround: Set the timing override bit before enabling the
1647                  * pch transcoder. */
1648                 reg = TRANS_CHICKEN2(pipe);
1649                 val = I915_READ(reg);
1650                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1651                 I915_WRITE(reg, val);
1652         }
1653
1654         reg = PCH_TRANSCONF(pipe);
1655         val = I915_READ(reg);
1656         pipeconf_val = I915_READ(PIPECONF(pipe));
1657
1658         if (HAS_PCH_IBX(dev_priv->dev)) {
1659                 /*
1660                  * make the BPC in transcoder be consistent with
1661                  * that in pipeconf reg.
1662                  */
1663                 val &= ~PIPECONF_BPC_MASK;
1664                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1665         }
1666
1667         val &= ~TRANS_INTERLACE_MASK;
1668         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1669                 if (HAS_PCH_IBX(dev_priv->dev) &&
1670                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1671                         val |= TRANS_LEGACY_INTERLACED_ILK;
1672                 else
1673                         val |= TRANS_INTERLACED;
1674         else
1675                 val |= TRANS_PROGRESSIVE;
1676
1677         I915_WRITE(reg, val | TRANS_ENABLE);
1678         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1679                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1680 }
1681
1682 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1683                                       enum transcoder cpu_transcoder)
1684 {
1685         u32 val, pipeconf_val;
1686
1687         /* PCH only available on ILK+ */
1688         BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1689
1690         /* FDI must be feeding us bits for PCH ports */
1691         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1692         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1693
1694         /* Workaround: set timing override bit. */
1695         val = I915_READ(_TRANSA_CHICKEN2);
1696         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1697         I915_WRITE(_TRANSA_CHICKEN2, val);
1698
1699         val = TRANS_ENABLE;
1700         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1701
1702         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1703             PIPECONF_INTERLACED_ILK)
1704                 val |= TRANS_INTERLACED;
1705         else
1706                 val |= TRANS_PROGRESSIVE;
1707
1708         I915_WRITE(LPT_TRANSCONF, val);
1709         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1710                 DRM_ERROR("Failed to enable PCH transcoder\n");
1711 }
1712
1713 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1714                                             enum pipe pipe)
1715 {
1716         struct drm_device *dev = dev_priv->dev;
1717         uint32_t reg, val;
1718
1719         /* FDI relies on the transcoder */
1720         assert_fdi_tx_disabled(dev_priv, pipe);
1721         assert_fdi_rx_disabled(dev_priv, pipe);
1722
1723         /* Ports must be off as well */
1724         assert_pch_ports_disabled(dev_priv, pipe);
1725
1726         reg = PCH_TRANSCONF(pipe);
1727         val = I915_READ(reg);
1728         val &= ~TRANS_ENABLE;
1729         I915_WRITE(reg, val);
1730         /* wait for PCH transcoder off, transcoder state */
1731         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1732                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1733
1734         if (!HAS_PCH_IBX(dev)) {
1735                 /* Workaround: Clear the timing override chicken bit again. */
1736                 reg = TRANS_CHICKEN2(pipe);
1737                 val = I915_READ(reg);
1738                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1739                 I915_WRITE(reg, val);
1740         }
1741 }
1742
1743 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1744 {
1745         u32 val;
1746
1747         val = I915_READ(LPT_TRANSCONF);
1748         val &= ~TRANS_ENABLE;
1749         I915_WRITE(LPT_TRANSCONF, val);
1750         /* wait for PCH transcoder off, transcoder state */
1751         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1752                 DRM_ERROR("Failed to disable PCH transcoder\n");
1753
1754         /* Workaround: clear timing override bit. */
1755         val = I915_READ(_TRANSA_CHICKEN2);
1756         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1757         I915_WRITE(_TRANSA_CHICKEN2, val);
1758 }
1759
1760 /**
1761  * intel_enable_pipe - enable a pipe, asserting requirements
1762  * @crtc: crtc responsible for the pipe
1763  *
1764  * Enable @crtc's pipe, making sure that various hardware specific requirements
1765  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1766  */
1767 static void intel_enable_pipe(struct intel_crtc *crtc)
1768 {
1769         struct drm_device *dev = crtc->base.dev;
1770         struct drm_i915_private *dev_priv = dev->dev_private;
1771         enum pipe pipe = crtc->pipe;
1772         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1773                                                                       pipe);
1774         enum pipe pch_transcoder;
1775         int reg;
1776         u32 val;
1777
1778         assert_planes_disabled(dev_priv, pipe);
1779         assert_cursor_disabled(dev_priv, pipe);
1780         assert_sprites_disabled(dev_priv, pipe);
1781
1782         if (HAS_PCH_LPT(dev_priv->dev))
1783                 pch_transcoder = TRANSCODER_A;
1784         else
1785                 pch_transcoder = pipe;
1786
1787         /*
1788          * A pipe without a PLL won't actually be able to drive bits from
1789          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1790          * need the check.
1791          */
1792         if (!HAS_PCH_SPLIT(dev_priv->dev))
1793                 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
1794                         assert_dsi_pll_enabled(dev_priv);
1795                 else
1796                         assert_pll_enabled(dev_priv, pipe);
1797         else {
1798                 if (crtc->config.has_pch_encoder) {
1799                         /* if driving the PCH, we need FDI enabled */
1800                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1801                         assert_fdi_tx_pll_enabled(dev_priv,
1802                                                   (enum pipe) cpu_transcoder);
1803                 }
1804                 /* FIXME: assert CPU port conditions for SNB+ */
1805         }
1806
1807         reg = PIPECONF(cpu_transcoder);
1808         val = I915_READ(reg);
1809         if (val & PIPECONF_ENABLE) {
1810                 WARN_ON(!(pipe == PIPE_A &&
1811                           dev_priv->quirks & QUIRK_PIPEA_FORCE));
1812                 return;
1813         }
1814
1815         I915_WRITE(reg, val | PIPECONF_ENABLE);
1816         POSTING_READ(reg);
1817 }
1818
1819 /**
1820  * intel_disable_pipe - disable a pipe, asserting requirements
1821  * @dev_priv: i915 private structure
1822  * @pipe: pipe to disable
1823  *
1824  * Disable @pipe, making sure that various hardware specific requirements
1825  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1826  *
1827  * @pipe should be %PIPE_A or %PIPE_B.
1828  *
1829  * Will wait until the pipe has shut down before returning.
1830  */
1831 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1832                                enum pipe pipe)
1833 {
1834         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1835                                                                       pipe);
1836         int reg;
1837         u32 val;
1838
1839         /*
1840          * Make sure planes won't keep trying to pump pixels to us,
1841          * or we might hang the display.
1842          */
1843         assert_planes_disabled(dev_priv, pipe);
1844         assert_cursor_disabled(dev_priv, pipe);
1845         assert_sprites_disabled(dev_priv, pipe);
1846
1847         /* Don't disable pipe A or pipe A PLLs if needed */
1848         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1849                 return;
1850
1851         reg = PIPECONF(cpu_transcoder);
1852         val = I915_READ(reg);
1853         if ((val & PIPECONF_ENABLE) == 0)
1854                 return;
1855
1856         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1857         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1858 }
1859
1860 /*
1861  * Plane regs are double buffered, going from enabled->disabled needs a
1862  * trigger in order to latch.  The display address reg provides this.
1863  */
1864 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1865                                enum plane plane)
1866 {
1867         struct drm_device *dev = dev_priv->dev;
1868         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1869
1870         I915_WRITE(reg, I915_READ(reg));
1871         POSTING_READ(reg);
1872 }
1873
1874 /**
1875  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
1876  * @dev_priv: i915 private structure
1877  * @plane: plane to enable
1878  * @pipe: pipe being fed
1879  *
1880  * Enable @plane on @pipe, making sure that @pipe is running first.
1881  */
1882 static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
1883                                           enum plane plane, enum pipe pipe)
1884 {
1885         struct intel_crtc *intel_crtc =
1886                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1887         int reg;
1888         u32 val;
1889
1890         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1891         assert_pipe_enabled(dev_priv, pipe);
1892
1893         if (intel_crtc->primary_enabled)
1894                 return;
1895
1896         intel_crtc->primary_enabled = true;
1897
1898         reg = DSPCNTR(plane);
1899         val = I915_READ(reg);
1900         WARN_ON(val & DISPLAY_PLANE_ENABLE);
1901
1902         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1903         intel_flush_primary_plane(dev_priv, plane);
1904         intel_wait_for_vblank(dev_priv->dev, pipe);
1905 }
1906
1907 /**
1908  * intel_disable_primary_hw_plane - disable the primary hardware plane
1909  * @dev_priv: i915 private structure
1910  * @plane: plane to disable
1911  * @pipe: pipe consuming the data
1912  *
1913  * Disable @plane; should be an independent operation.
1914  */
1915 static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
1916                                            enum plane plane, enum pipe pipe)
1917 {
1918         struct intel_crtc *intel_crtc =
1919                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1920         int reg;
1921         u32 val;
1922
1923         if (!intel_crtc->primary_enabled)
1924                 return;
1925
1926         intel_crtc->primary_enabled = false;
1927
1928         reg = DSPCNTR(plane);
1929         val = I915_READ(reg);
1930         WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0);
1931
1932         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1933         intel_flush_primary_plane(dev_priv, plane);
1934         intel_wait_for_vblank(dev_priv->dev, pipe);
1935 }
1936
1937 static bool need_vtd_wa(struct drm_device *dev)
1938 {
1939 #ifdef CONFIG_INTEL_IOMMU
1940         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1941                 return true;
1942 #endif
1943         return false;
1944 }
1945
1946 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
1947 {
1948         int tile_height;
1949
1950         tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
1951         return ALIGN(height, tile_height);
1952 }
1953
1954 int
1955 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1956                            struct drm_i915_gem_object *obj,
1957                            struct intel_ring_buffer *pipelined)
1958 {
1959         struct drm_i915_private *dev_priv = dev->dev_private;
1960         u32 alignment;
1961         int ret;
1962
1963         switch (obj->tiling_mode) {
1964         case I915_TILING_NONE:
1965                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1966                         alignment = 128 * 1024;
1967                 else if (INTEL_INFO(dev)->gen >= 4)
1968                         alignment = 4 * 1024;
1969                 else
1970                         alignment = 64 * 1024;
1971                 break;
1972         case I915_TILING_X:
1973                 /* pin() will align the object as required by fence */
1974                 alignment = 0;
1975                 break;
1976         case I915_TILING_Y:
1977                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
1978                 return -EINVAL;
1979         default:
1980                 BUG();
1981         }
1982
1983         /* Note that the w/a also requires 64 PTE of padding following the
1984          * bo. We currently fill all unused PTE with the shadow page and so
1985          * we should always have valid PTE following the scanout preventing
1986          * the VT-d warning.
1987          */
1988         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1989                 alignment = 256 * 1024;
1990
1991         dev_priv->mm.interruptible = false;
1992         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1993         if (ret)
1994                 goto err_interruptible;
1995
1996         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1997          * fence, whereas 965+ only requires a fence if using
1998          * framebuffer compression.  For simplicity, we always install
1999          * a fence as the cost is not that onerous.
2000          */
2001         ret = i915_gem_object_get_fence(obj);
2002         if (ret)
2003                 goto err_unpin;
2004
2005         i915_gem_object_pin_fence(obj);
2006
2007         dev_priv->mm.interruptible = true;
2008         return 0;
2009
2010 err_unpin:
2011         i915_gem_object_unpin_from_display_plane(obj);
2012 err_interruptible:
2013         dev_priv->mm.interruptible = true;
2014         return ret;
2015 }
2016
2017 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2018 {
2019         i915_gem_object_unpin_fence(obj);
2020         i915_gem_object_unpin_from_display_plane(obj);
2021 }
2022
2023 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2024  * is assumed to be a power-of-two. */
2025 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2026                                              unsigned int tiling_mode,
2027                                              unsigned int cpp,
2028                                              unsigned int pitch)
2029 {
2030         if (tiling_mode != I915_TILING_NONE) {
2031                 unsigned int tile_rows, tiles;
2032
2033                 tile_rows = *y / 8;
2034                 *y %= 8;
2035
2036                 tiles = *x / (512/cpp);
2037                 *x %= 512/cpp;
2038
2039                 return tile_rows * pitch * 8 + tiles * 4096;
2040         } else {
2041                 unsigned int offset;
2042
2043                 offset = *y * pitch + *x * cpp;
2044                 *y = 0;
2045                 *x = (offset & 4095) / cpp;
2046                 return offset & -4096;
2047         }
2048 }
2049
2050 int intel_format_to_fourcc(int format)
2051 {
2052         switch (format) {
2053         case DISPPLANE_8BPP:
2054                 return DRM_FORMAT_C8;
2055         case DISPPLANE_BGRX555:
2056                 return DRM_FORMAT_XRGB1555;
2057         case DISPPLANE_BGRX565:
2058                 return DRM_FORMAT_RGB565;
2059         default:
2060         case DISPPLANE_BGRX888:
2061                 return DRM_FORMAT_XRGB8888;
2062         case DISPPLANE_RGBX888:
2063                 return DRM_FORMAT_XBGR8888;
2064         case DISPPLANE_BGRX101010:
2065                 return DRM_FORMAT_XRGB2101010;
2066         case DISPPLANE_RGBX101010:
2067                 return DRM_FORMAT_XBGR2101010;
2068         }
2069 }
2070
2071 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2072                                   struct intel_plane_config *plane_config)
2073 {
2074         struct drm_device *dev = crtc->base.dev;
2075         struct drm_i915_gem_object *obj = NULL;
2076         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2077         u32 base = plane_config->base;
2078
2079         if (plane_config->size == 0)
2080                 return false;
2081
2082         obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2083                                                              plane_config->size);
2084         if (!obj)
2085                 return false;
2086
2087         if (plane_config->tiled) {
2088                 obj->tiling_mode = I915_TILING_X;
2089                 obj->stride = crtc->base.primary->fb->pitches[0];
2090         }
2091
2092         mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2093         mode_cmd.width = crtc->base.primary->fb->width;
2094         mode_cmd.height = crtc->base.primary->fb->height;
2095         mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2096
2097         mutex_lock(&dev->struct_mutex);
2098
2099         if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2100                                    &mode_cmd, obj)) {
2101                 DRM_DEBUG_KMS("intel fb init failed\n");
2102                 goto out_unref_obj;
2103         }
2104
2105         mutex_unlock(&dev->struct_mutex);
2106
2107         DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2108         return true;
2109
2110 out_unref_obj:
2111         drm_gem_object_unreference(&obj->base);
2112         mutex_unlock(&dev->struct_mutex);
2113         return false;
2114 }
2115
2116 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2117                                  struct intel_plane_config *plane_config)
2118 {
2119         struct drm_device *dev = intel_crtc->base.dev;
2120         struct drm_crtc *c;
2121         struct intel_crtc *i;
2122         struct intel_framebuffer *fb;
2123
2124         if (!intel_crtc->base.primary->fb)
2125                 return;
2126
2127         if (intel_alloc_plane_obj(intel_crtc, plane_config))
2128                 return;
2129
2130         kfree(intel_crtc->base.primary->fb);
2131         intel_crtc->base.primary->fb = NULL;
2132
2133         /*
2134          * Failed to alloc the obj, check to see if we should share
2135          * an fb with another CRTC instead
2136          */
2137         list_for_each_entry(c, &dev->mode_config.crtc_list, head) {
2138                 i = to_intel_crtc(c);
2139
2140                 if (c == &intel_crtc->base)
2141                         continue;
2142
2143                 if (!i->active || !c->primary->fb)
2144                         continue;
2145
2146                 fb = to_intel_framebuffer(c->primary->fb);
2147                 if (i915_gem_obj_ggtt_offset(fb->obj) == plane_config->base) {
2148                         drm_framebuffer_reference(c->primary->fb);
2149                         intel_crtc->base.primary->fb = c->primary->fb;
2150                         break;
2151                 }
2152         }
2153 }
2154
2155 static int i9xx_update_primary_plane(struct drm_crtc *crtc,
2156                                      struct drm_framebuffer *fb,
2157                                      int x, int y)
2158 {
2159         struct drm_device *dev = crtc->dev;
2160         struct drm_i915_private *dev_priv = dev->dev_private;
2161         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2162         struct intel_framebuffer *intel_fb;
2163         struct drm_i915_gem_object *obj;
2164         int plane = intel_crtc->plane;
2165         unsigned long linear_offset;
2166         u32 dspcntr;
2167         u32 reg;
2168
2169         intel_fb = to_intel_framebuffer(fb);
2170         obj = intel_fb->obj;
2171
2172         reg = DSPCNTR(plane);
2173         dspcntr = I915_READ(reg);
2174         /* Mask out pixel format bits in case we change it */
2175         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2176         switch (fb->pixel_format) {
2177         case DRM_FORMAT_C8:
2178                 dspcntr |= DISPPLANE_8BPP;
2179                 break;
2180         case DRM_FORMAT_XRGB1555:
2181         case DRM_FORMAT_ARGB1555:
2182                 dspcntr |= DISPPLANE_BGRX555;
2183                 break;
2184         case DRM_FORMAT_RGB565:
2185                 dspcntr |= DISPPLANE_BGRX565;
2186                 break;
2187         case DRM_FORMAT_XRGB8888:
2188         case DRM_FORMAT_ARGB8888:
2189                 dspcntr |= DISPPLANE_BGRX888;
2190                 break;
2191         case DRM_FORMAT_XBGR8888:
2192         case DRM_FORMAT_ABGR8888:
2193                 dspcntr |= DISPPLANE_RGBX888;
2194                 break;
2195         case DRM_FORMAT_XRGB2101010:
2196         case DRM_FORMAT_ARGB2101010:
2197                 dspcntr |= DISPPLANE_BGRX101010;
2198                 break;
2199         case DRM_FORMAT_XBGR2101010:
2200         case DRM_FORMAT_ABGR2101010:
2201                 dspcntr |= DISPPLANE_RGBX101010;
2202                 break;
2203         default:
2204                 BUG();
2205         }
2206
2207         if (INTEL_INFO(dev)->gen >= 4) {
2208                 if (obj->tiling_mode != I915_TILING_NONE)
2209                         dspcntr |= DISPPLANE_TILED;
2210                 else
2211                         dspcntr &= ~DISPPLANE_TILED;
2212         }
2213
2214         if (IS_G4X(dev))
2215                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2216
2217         I915_WRITE(reg, dspcntr);
2218
2219         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2220
2221         if (INTEL_INFO(dev)->gen >= 4) {
2222                 intel_crtc->dspaddr_offset =
2223                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2224                                                        fb->bits_per_pixel / 8,
2225                                                        fb->pitches[0]);
2226                 linear_offset -= intel_crtc->dspaddr_offset;
2227         } else {
2228                 intel_crtc->dspaddr_offset = linear_offset;
2229         }
2230
2231         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2232                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2233                       fb->pitches[0]);
2234         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2235         if (INTEL_INFO(dev)->gen >= 4) {
2236                 I915_WRITE(DSPSURF(plane),
2237                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2238                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2239                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2240         } else
2241                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2242         POSTING_READ(reg);
2243
2244         return 0;
2245 }
2246
2247 static int ironlake_update_primary_plane(struct drm_crtc *crtc,
2248                                          struct drm_framebuffer *fb,
2249                                          int x, int y)
2250 {
2251         struct drm_device *dev = crtc->dev;
2252         struct drm_i915_private *dev_priv = dev->dev_private;
2253         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2254         struct intel_framebuffer *intel_fb;
2255         struct drm_i915_gem_object *obj;
2256         int plane = intel_crtc->plane;
2257         unsigned long linear_offset;
2258         u32 dspcntr;
2259         u32 reg;
2260
2261         intel_fb = to_intel_framebuffer(fb);
2262         obj = intel_fb->obj;
2263
2264         reg = DSPCNTR(plane);
2265         dspcntr = I915_READ(reg);
2266         /* Mask out pixel format bits in case we change it */
2267         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2268         switch (fb->pixel_format) {
2269         case DRM_FORMAT_C8:
2270                 dspcntr |= DISPPLANE_8BPP;
2271                 break;
2272         case DRM_FORMAT_RGB565:
2273                 dspcntr |= DISPPLANE_BGRX565;
2274                 break;
2275         case DRM_FORMAT_XRGB8888:
2276         case DRM_FORMAT_ARGB8888:
2277                 dspcntr |= DISPPLANE_BGRX888;
2278                 break;
2279         case DRM_FORMAT_XBGR8888:
2280         case DRM_FORMAT_ABGR8888:
2281                 dspcntr |= DISPPLANE_RGBX888;
2282                 break;
2283         case DRM_FORMAT_XRGB2101010:
2284         case DRM_FORMAT_ARGB2101010:
2285                 dspcntr |= DISPPLANE_BGRX101010;
2286                 break;
2287         case DRM_FORMAT_XBGR2101010:
2288         case DRM_FORMAT_ABGR2101010:
2289                 dspcntr |= DISPPLANE_RGBX101010;
2290                 break;
2291         default:
2292                 BUG();
2293         }
2294
2295         if (obj->tiling_mode != I915_TILING_NONE)
2296                 dspcntr |= DISPPLANE_TILED;
2297         else
2298                 dspcntr &= ~DISPPLANE_TILED;
2299
2300         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2301                 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2302         else
2303                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2304
2305         I915_WRITE(reg, dspcntr);
2306
2307         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2308         intel_crtc->dspaddr_offset =
2309                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2310                                                fb->bits_per_pixel / 8,
2311                                                fb->pitches[0]);
2312         linear_offset -= intel_crtc->dspaddr_offset;
2313
2314         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2315                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2316                       fb->pitches[0]);
2317         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2318         I915_WRITE(DSPSURF(plane),
2319                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2320         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2321                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2322         } else {
2323                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2324                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2325         }
2326         POSTING_READ(reg);
2327
2328         return 0;
2329 }
2330
2331 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2332 static int
2333 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2334                            int x, int y, enum mode_set_atomic state)
2335 {
2336         struct drm_device *dev = crtc->dev;
2337         struct drm_i915_private *dev_priv = dev->dev_private;
2338
2339         if (dev_priv->display.disable_fbc)
2340                 dev_priv->display.disable_fbc(dev);
2341         intel_increase_pllclock(crtc);
2342
2343         return dev_priv->display.update_primary_plane(crtc, fb, x, y);
2344 }
2345
2346 void intel_display_handle_reset(struct drm_device *dev)
2347 {
2348         struct drm_i915_private *dev_priv = dev->dev_private;
2349         struct drm_crtc *crtc;
2350
2351         /*
2352          * Flips in the rings have been nuked by the reset,
2353          * so complete all pending flips so that user space
2354          * will get its events and not get stuck.
2355          *
2356          * Also update the base address of all primary
2357          * planes to the the last fb to make sure we're
2358          * showing the correct fb after a reset.
2359          *
2360          * Need to make two loops over the crtcs so that we
2361          * don't try to grab a crtc mutex before the
2362          * pending_flip_queue really got woken up.
2363          */
2364
2365         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2366                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2367                 enum plane plane = intel_crtc->plane;
2368
2369                 intel_prepare_page_flip(dev, plane);
2370                 intel_finish_page_flip_plane(dev, plane);
2371         }
2372
2373         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2374                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2375
2376                 mutex_lock(&crtc->mutex);
2377                 /*
2378                  * FIXME: Once we have proper support for primary planes (and
2379                  * disabling them without disabling the entire crtc) allow again
2380                  * a NULL crtc->primary->fb.
2381                  */
2382                 if (intel_crtc->active && crtc->primary->fb)
2383                         dev_priv->display.update_primary_plane(crtc,
2384                                                                crtc->primary->fb,
2385                                                                crtc->x,
2386                                                                crtc->y);
2387                 mutex_unlock(&crtc->mutex);
2388         }
2389 }
2390
2391 static int
2392 intel_finish_fb(struct drm_framebuffer *old_fb)
2393 {
2394         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2395         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2396         bool was_interruptible = dev_priv->mm.interruptible;
2397         int ret;
2398
2399         /* Big Hammer, we also need to ensure that any pending
2400          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2401          * current scanout is retired before unpinning the old
2402          * framebuffer.
2403          *
2404          * This should only fail upon a hung GPU, in which case we
2405          * can safely continue.
2406          */
2407         dev_priv->mm.interruptible = false;
2408         ret = i915_gem_object_finish_gpu(obj);
2409         dev_priv->mm.interruptible = was_interruptible;
2410
2411         return ret;
2412 }
2413
2414 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2415 {
2416         struct drm_device *dev = crtc->dev;
2417         struct drm_i915_private *dev_priv = dev->dev_private;
2418         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2419         unsigned long flags;
2420         bool pending;
2421
2422         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2423             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2424                 return false;
2425
2426         spin_lock_irqsave(&dev->event_lock, flags);
2427         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2428         spin_unlock_irqrestore(&dev->event_lock, flags);
2429
2430         return pending;
2431 }
2432
2433 static int
2434 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2435                     struct drm_framebuffer *fb)
2436 {
2437         struct drm_device *dev = crtc->dev;
2438         struct drm_i915_private *dev_priv = dev->dev_private;
2439         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2440         struct drm_framebuffer *old_fb;
2441         int ret;
2442
2443         if (intel_crtc_has_pending_flip(crtc)) {
2444                 DRM_ERROR("pipe is still busy with an old pageflip\n");
2445                 return -EBUSY;
2446         }
2447
2448         /* no fb bound */
2449         if (!fb) {
2450                 DRM_ERROR("No FB bound\n");
2451                 return 0;
2452         }
2453
2454         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2455                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2456                           plane_name(intel_crtc->plane),
2457                           INTEL_INFO(dev)->num_pipes);
2458                 return -EINVAL;
2459         }
2460
2461         mutex_lock(&dev->struct_mutex);
2462         ret = intel_pin_and_fence_fb_obj(dev,
2463                                          to_intel_framebuffer(fb)->obj,
2464                                          NULL);
2465         mutex_unlock(&dev->struct_mutex);
2466         if (ret != 0) {
2467                 DRM_ERROR("pin & fence failed\n");
2468                 return ret;
2469         }
2470
2471         /*
2472          * Update pipe size and adjust fitter if needed: the reason for this is
2473          * that in compute_mode_changes we check the native mode (not the pfit
2474          * mode) to see if we can flip rather than do a full mode set. In the
2475          * fastboot case, we'll flip, but if we don't update the pipesrc and
2476          * pfit state, we'll end up with a big fb scanned out into the wrong
2477          * sized surface.
2478          *
2479          * To fix this properly, we need to hoist the checks up into
2480          * compute_mode_changes (or above), check the actual pfit state and
2481          * whether the platform allows pfit disable with pipe active, and only
2482          * then update the pipesrc and pfit state, even on the flip path.
2483          */
2484         if (i915.fastboot) {
2485                 const struct drm_display_mode *adjusted_mode =
2486                         &intel_crtc->config.adjusted_mode;
2487
2488                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2489                            ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2490                            (adjusted_mode->crtc_vdisplay - 1));
2491                 if (!intel_crtc->config.pch_pfit.enabled &&
2492                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2493                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2494                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2495                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2496                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2497                 }
2498                 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2499                 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2500         }
2501
2502         ret = dev_priv->display.update_primary_plane(crtc, fb, x, y);
2503         if (ret) {
2504                 mutex_lock(&dev->struct_mutex);
2505                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2506                 mutex_unlock(&dev->struct_mutex);
2507                 DRM_ERROR("failed to update base address\n");
2508                 return ret;
2509         }
2510
2511         old_fb = crtc->primary->fb;
2512         crtc->primary->fb = fb;
2513         crtc->x = x;
2514         crtc->y = y;
2515
2516         if (old_fb) {
2517                 if (intel_crtc->active && old_fb != fb)
2518                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2519                 mutex_lock(&dev->struct_mutex);
2520                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2521                 mutex_unlock(&dev->struct_mutex);
2522         }
2523
2524         mutex_lock(&dev->struct_mutex);
2525         intel_update_fbc(dev);
2526         intel_edp_psr_update(dev);
2527         mutex_unlock(&dev->struct_mutex);
2528
2529         return 0;
2530 }
2531
2532 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2533 {
2534         struct drm_device *dev = crtc->dev;
2535         struct drm_i915_private *dev_priv = dev->dev_private;
2536         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2537         int pipe = intel_crtc->pipe;
2538         u32 reg, temp;
2539
2540         /* enable normal train */
2541         reg = FDI_TX_CTL(pipe);
2542         temp = I915_READ(reg);
2543         if (IS_IVYBRIDGE(dev)) {
2544                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2545                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2546         } else {
2547                 temp &= ~FDI_LINK_TRAIN_NONE;
2548                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2549         }
2550         I915_WRITE(reg, temp);
2551
2552         reg = FDI_RX_CTL(pipe);
2553         temp = I915_READ(reg);
2554         if (HAS_PCH_CPT(dev)) {
2555                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2556                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2557         } else {
2558                 temp &= ~FDI_LINK_TRAIN_NONE;
2559                 temp |= FDI_LINK_TRAIN_NONE;
2560         }
2561         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2562
2563         /* wait one idle pattern time */
2564         POSTING_READ(reg);
2565         udelay(1000);
2566
2567         /* IVB wants error correction enabled */
2568         if (IS_IVYBRIDGE(dev))
2569                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2570                            FDI_FE_ERRC_ENABLE);
2571 }
2572
2573 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2574 {
2575         return crtc->base.enabled && crtc->active &&
2576                 crtc->config.has_pch_encoder;
2577 }
2578
2579 static void ivb_modeset_global_resources(struct drm_device *dev)
2580 {
2581         struct drm_i915_private *dev_priv = dev->dev_private;
2582         struct intel_crtc *pipe_B_crtc =
2583                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2584         struct intel_crtc *pipe_C_crtc =
2585                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2586         uint32_t temp;
2587
2588         /*
2589          * When everything is off disable fdi C so that we could enable fdi B
2590          * with all lanes. Note that we don't care about enabled pipes without
2591          * an enabled pch encoder.
2592          */
2593         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2594             !pipe_has_enabled_pch(pipe_C_crtc)) {
2595                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2596                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2597
2598                 temp = I915_READ(SOUTH_CHICKEN1);
2599                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2600                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2601                 I915_WRITE(SOUTH_CHICKEN1, temp);
2602         }
2603 }
2604
2605 /* The FDI link training functions for ILK/Ibexpeak. */
2606 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2607 {
2608         struct drm_device *dev = crtc->dev;
2609         struct drm_i915_private *dev_priv = dev->dev_private;
2610         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2611         int pipe = intel_crtc->pipe;
2612         u32 reg, temp, tries;
2613
2614         /* FDI needs bits from pipe first */
2615         assert_pipe_enabled(dev_priv, pipe);
2616
2617         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2618            for train result */
2619         reg = FDI_RX_IMR(pipe);
2620         temp = I915_READ(reg);
2621         temp &= ~FDI_RX_SYMBOL_LOCK;
2622         temp &= ~FDI_RX_BIT_LOCK;
2623         I915_WRITE(reg, temp);
2624         I915_READ(reg);
2625         udelay(150);
2626
2627         /* enable CPU FDI TX and PCH FDI RX */
2628         reg = FDI_TX_CTL(pipe);
2629         temp = I915_READ(reg);
2630         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2631         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2632         temp &= ~FDI_LINK_TRAIN_NONE;
2633         temp |= FDI_LINK_TRAIN_PATTERN_1;
2634         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2635
2636         reg = FDI_RX_CTL(pipe);
2637         temp = I915_READ(reg);
2638         temp &= ~FDI_LINK_TRAIN_NONE;
2639         temp |= FDI_LINK_TRAIN_PATTERN_1;
2640         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2641
2642         POSTING_READ(reg);
2643         udelay(150);
2644
2645         /* Ironlake workaround, enable clock pointer after FDI enable*/
2646         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2647         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2648                    FDI_RX_PHASE_SYNC_POINTER_EN);
2649
2650         reg = FDI_RX_IIR(pipe);
2651         for (tries = 0; tries < 5; tries++) {
2652                 temp = I915_READ(reg);
2653                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2654
2655                 if ((temp & FDI_RX_BIT_LOCK)) {
2656                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2657                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2658                         break;
2659                 }
2660         }
2661         if (tries == 5)
2662                 DRM_ERROR("FDI train 1 fail!\n");
2663
2664         /* Train 2 */
2665         reg = FDI_TX_CTL(pipe);
2666         temp = I915_READ(reg);
2667         temp &= ~FDI_LINK_TRAIN_NONE;
2668         temp |= FDI_LINK_TRAIN_PATTERN_2;
2669         I915_WRITE(reg, temp);
2670
2671         reg = FDI_RX_CTL(pipe);
2672         temp = I915_READ(reg);
2673         temp &= ~FDI_LINK_TRAIN_NONE;
2674         temp |= FDI_LINK_TRAIN_PATTERN_2;
2675         I915_WRITE(reg, temp);
2676
2677         POSTING_READ(reg);
2678         udelay(150);
2679
2680         reg = FDI_RX_IIR(pipe);
2681         for (tries = 0; tries < 5; tries++) {
2682                 temp = I915_READ(reg);
2683                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2684
2685                 if (temp & FDI_RX_SYMBOL_LOCK) {
2686                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2687                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2688                         break;
2689                 }
2690         }
2691         if (tries == 5)
2692                 DRM_ERROR("FDI train 2 fail!\n");
2693
2694         DRM_DEBUG_KMS("FDI train done\n");
2695
2696 }
2697
2698 static const int snb_b_fdi_train_param[] = {
2699         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2700         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2701         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2702         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2703 };
2704
2705 /* The FDI link training functions for SNB/Cougarpoint. */
2706 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2707 {
2708         struct drm_device *dev = crtc->dev;
2709         struct drm_i915_private *dev_priv = dev->dev_private;
2710         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2711         int pipe = intel_crtc->pipe;
2712         u32 reg, temp, i, retry;
2713
2714         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2715            for train result */
2716         reg = FDI_RX_IMR(pipe);
2717         temp = I915_READ(reg);
2718         temp &= ~FDI_RX_SYMBOL_LOCK;
2719         temp &= ~FDI_RX_BIT_LOCK;
2720         I915_WRITE(reg, temp);
2721
2722         POSTING_READ(reg);
2723         udelay(150);
2724
2725         /* enable CPU FDI TX and PCH FDI RX */
2726         reg = FDI_TX_CTL(pipe);
2727         temp = I915_READ(reg);
2728         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2729         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2730         temp &= ~FDI_LINK_TRAIN_NONE;
2731         temp |= FDI_LINK_TRAIN_PATTERN_1;
2732         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2733         /* SNB-B */
2734         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2735         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2736
2737         I915_WRITE(FDI_RX_MISC(pipe),
2738                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2739
2740         reg = FDI_RX_CTL(pipe);
2741         temp = I915_READ(reg);
2742         if (HAS_PCH_CPT(dev)) {
2743                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2744                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2745         } else {
2746                 temp &= ~FDI_LINK_TRAIN_NONE;
2747                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2748         }
2749         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2750
2751         POSTING_READ(reg);
2752         udelay(150);
2753
2754         for (i = 0; i < 4; i++) {
2755                 reg = FDI_TX_CTL(pipe);
2756                 temp = I915_READ(reg);
2757                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2758                 temp |= snb_b_fdi_train_param[i];
2759                 I915_WRITE(reg, temp);
2760
2761                 POSTING_READ(reg);
2762                 udelay(500);
2763
2764                 for (retry = 0; retry < 5; retry++) {
2765                         reg = FDI_RX_IIR(pipe);
2766                         temp = I915_READ(reg);
2767                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2768                         if (temp & FDI_RX_BIT_LOCK) {
2769                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2770                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2771                                 break;
2772                         }
2773                         udelay(50);
2774                 }
2775                 if (retry < 5)
2776                         break;
2777         }
2778         if (i == 4)
2779                 DRM_ERROR("FDI train 1 fail!\n");
2780
2781         /* Train 2 */
2782         reg = FDI_TX_CTL(pipe);
2783         temp = I915_READ(reg);
2784         temp &= ~FDI_LINK_TRAIN_NONE;
2785         temp |= FDI_LINK_TRAIN_PATTERN_2;
2786         if (IS_GEN6(dev)) {
2787                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2788                 /* SNB-B */
2789                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2790         }
2791         I915_WRITE(reg, temp);
2792
2793         reg = FDI_RX_CTL(pipe);
2794         temp = I915_READ(reg);
2795         if (HAS_PCH_CPT(dev)) {
2796                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2797                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2798         } else {
2799                 temp &= ~FDI_LINK_TRAIN_NONE;
2800                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2801         }
2802         I915_WRITE(reg, temp);
2803
2804         POSTING_READ(reg);
2805         udelay(150);
2806
2807         for (i = 0; i < 4; i++) {
2808                 reg = FDI_TX_CTL(pipe);
2809                 temp = I915_READ(reg);
2810                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2811                 temp |= snb_b_fdi_train_param[i];
2812                 I915_WRITE(reg, temp);
2813
2814                 POSTING_READ(reg);
2815                 udelay(500);
2816
2817                 for (retry = 0; retry < 5; retry++) {
2818                         reg = FDI_RX_IIR(pipe);
2819                         temp = I915_READ(reg);
2820                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2821                         if (temp & FDI_RX_SYMBOL_LOCK) {
2822                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2823                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2824                                 break;
2825                         }
2826                         udelay(50);
2827                 }
2828                 if (retry < 5)
2829                         break;
2830         }
2831         if (i == 4)
2832                 DRM_ERROR("FDI train 2 fail!\n");
2833
2834         DRM_DEBUG_KMS("FDI train done.\n");
2835 }
2836
2837 /* Manual link training for Ivy Bridge A0 parts */
2838 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2839 {
2840         struct drm_device *dev = crtc->dev;
2841         struct drm_i915_private *dev_priv = dev->dev_private;
2842         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2843         int pipe = intel_crtc->pipe;
2844         u32 reg, temp, i, j;
2845
2846         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2847            for train result */
2848         reg = FDI_RX_IMR(pipe);
2849         temp = I915_READ(reg);
2850         temp &= ~FDI_RX_SYMBOL_LOCK;
2851         temp &= ~FDI_RX_BIT_LOCK;
2852         I915_WRITE(reg, temp);
2853
2854         POSTING_READ(reg);
2855         udelay(150);
2856
2857         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2858                       I915_READ(FDI_RX_IIR(pipe)));
2859
2860         /* Try each vswing and preemphasis setting twice before moving on */
2861         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2862                 /* disable first in case we need to retry */
2863                 reg = FDI_TX_CTL(pipe);
2864                 temp = I915_READ(reg);
2865                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2866                 temp &= ~FDI_TX_ENABLE;
2867                 I915_WRITE(reg, temp);
2868
2869                 reg = FDI_RX_CTL(pipe);
2870                 temp = I915_READ(reg);
2871                 temp &= ~FDI_LINK_TRAIN_AUTO;
2872                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2873                 temp &= ~FDI_RX_ENABLE;
2874                 I915_WRITE(reg, temp);
2875
2876                 /* enable CPU FDI TX and PCH FDI RX */
2877                 reg = FDI_TX_CTL(pipe);
2878                 temp = I915_READ(reg);
2879                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2880                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2881                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2882                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2883                 temp |= snb_b_fdi_train_param[j/2];
2884                 temp |= FDI_COMPOSITE_SYNC;
2885                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2886
2887                 I915_WRITE(FDI_RX_MISC(pipe),
2888                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2889
2890                 reg = FDI_RX_CTL(pipe);
2891                 temp = I915_READ(reg);
2892                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2893                 temp |= FDI_COMPOSITE_SYNC;
2894                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2895
2896                 POSTING_READ(reg);
2897                 udelay(1); /* should be 0.5us */
2898
2899                 for (i = 0; i < 4; i++) {
2900                         reg = FDI_RX_IIR(pipe);
2901                         temp = I915_READ(reg);
2902                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2903
2904                         if (temp & FDI_RX_BIT_LOCK ||
2905                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2906                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2907                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2908                                               i);
2909                                 break;
2910                         }
2911                         udelay(1); /* should be 0.5us */
2912                 }
2913                 if (i == 4) {
2914                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2915                         continue;
2916                 }
2917
2918                 /* Train 2 */
2919                 reg = FDI_TX_CTL(pipe);
2920                 temp = I915_READ(reg);
2921                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2922                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2923                 I915_WRITE(reg, temp);
2924
2925                 reg = FDI_RX_CTL(pipe);
2926                 temp = I915_READ(reg);
2927                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2928                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2929                 I915_WRITE(reg, temp);
2930
2931                 POSTING_READ(reg);
2932                 udelay(2); /* should be 1.5us */
2933
2934                 for (i = 0; i < 4; i++) {
2935                         reg = FDI_RX_IIR(pipe);
2936                         temp = I915_READ(reg);
2937                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2938
2939                         if (temp & FDI_RX_SYMBOL_LOCK ||
2940                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2941                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2942                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2943                                               i);
2944                                 goto train_done;
2945                         }
2946                         udelay(2); /* should be 1.5us */
2947                 }
2948                 if (i == 4)
2949                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2950         }
2951
2952 train_done:
2953         DRM_DEBUG_KMS("FDI train done.\n");
2954 }
2955
2956 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2957 {
2958         struct drm_device *dev = intel_crtc->base.dev;
2959         struct drm_i915_private *dev_priv = dev->dev_private;
2960         int pipe = intel_crtc->pipe;
2961         u32 reg, temp;
2962
2963
2964         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2965         reg = FDI_RX_CTL(pipe);
2966         temp = I915_READ(reg);
2967         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2968         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2969         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2970         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2971
2972         POSTING_READ(reg);
2973         udelay(200);
2974
2975         /* Switch from Rawclk to PCDclk */
2976         temp = I915_READ(reg);
2977         I915_WRITE(reg, temp | FDI_PCDCLK);
2978
2979         POSTING_READ(reg);
2980         udelay(200);
2981
2982         /* Enable CPU FDI TX PLL, always on for Ironlake */
2983         reg = FDI_TX_CTL(pipe);
2984         temp = I915_READ(reg);
2985         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2986                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2987
2988                 POSTING_READ(reg);
2989                 udelay(100);
2990         }
2991 }
2992
2993 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2994 {
2995         struct drm_device *dev = intel_crtc->base.dev;
2996         struct drm_i915_private *dev_priv = dev->dev_private;
2997         int pipe = intel_crtc->pipe;
2998         u32 reg, temp;
2999
3000         /* Switch from PCDclk to Rawclk */
3001         reg = FDI_RX_CTL(pipe);
3002         temp = I915_READ(reg);
3003         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3004
3005         /* Disable CPU FDI TX PLL */
3006         reg = FDI_TX_CTL(pipe);
3007         temp = I915_READ(reg);
3008         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3009
3010         POSTING_READ(reg);
3011         udelay(100);
3012
3013         reg = FDI_RX_CTL(pipe);
3014         temp = I915_READ(reg);
3015         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3016
3017         /* Wait for the clocks to turn off. */
3018         POSTING_READ(reg);
3019         udelay(100);
3020 }
3021
3022 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3023 {
3024         struct drm_device *dev = crtc->dev;
3025         struct drm_i915_private *dev_priv = dev->dev_private;
3026         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3027         int pipe = intel_crtc->pipe;
3028         u32 reg, temp;
3029
3030         /* disable CPU FDI tx and PCH FDI rx */
3031         reg = FDI_TX_CTL(pipe);
3032         temp = I915_READ(reg);
3033         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3034         POSTING_READ(reg);
3035
3036         reg = FDI_RX_CTL(pipe);
3037         temp = I915_READ(reg);
3038         temp &= ~(0x7 << 16);
3039         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3040         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3041
3042         POSTING_READ(reg);
3043         udelay(100);
3044
3045         /* Ironlake workaround, disable clock pointer after downing FDI */
3046         if (HAS_PCH_IBX(dev)) {
3047                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3048         }
3049
3050         /* still set train pattern 1 */
3051         reg = FDI_TX_CTL(pipe);
3052         temp = I915_READ(reg);
3053         temp &= ~FDI_LINK_TRAIN_NONE;
3054         temp |= FDI_LINK_TRAIN_PATTERN_1;
3055         I915_WRITE(reg, temp);
3056
3057         reg = FDI_RX_CTL(pipe);
3058         temp = I915_READ(reg);
3059         if (HAS_PCH_CPT(dev)) {
3060                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3061                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3062         } else {
3063                 temp &= ~FDI_LINK_TRAIN_NONE;
3064                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3065         }
3066         /* BPC in FDI rx is consistent with that in PIPECONF */
3067         temp &= ~(0x07 << 16);
3068         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3069         I915_WRITE(reg, temp);
3070
3071         POSTING_READ(reg);
3072         udelay(100);
3073 }
3074
3075 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3076 {
3077         struct intel_crtc *crtc;
3078
3079         /* Note that we don't need to be called with mode_config.lock here
3080          * as our list of CRTC objects is static for the lifetime of the
3081          * device and so cannot disappear as we iterate. Similarly, we can
3082          * happily treat the predicates as racy, atomic checks as userspace
3083          * cannot claim and pin a new fb without at least acquring the
3084          * struct_mutex and so serialising with us.
3085          */
3086         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3087                 if (atomic_read(&crtc->unpin_work_count) == 0)
3088                         continue;
3089
3090                 if (crtc->unpin_work)
3091                         intel_wait_for_vblank(dev, crtc->pipe);
3092
3093                 return true;
3094         }
3095
3096         return false;
3097 }
3098
3099 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3100 {
3101         struct drm_device *dev = crtc->dev;
3102         struct drm_i915_private *dev_priv = dev->dev_private;
3103
3104         if (crtc->primary->fb == NULL)
3105                 return;
3106
3107         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3108
3109         wait_event(dev_priv->pending_flip_queue,
3110                    !intel_crtc_has_pending_flip(crtc));
3111
3112         mutex_lock(&dev->struct_mutex);
3113         intel_finish_fb(crtc->primary->fb);
3114         mutex_unlock(&dev->struct_mutex);
3115 }
3116
3117 /* Program iCLKIP clock to the desired frequency */
3118 static void lpt_program_iclkip(struct drm_crtc *crtc)
3119 {
3120         struct drm_device *dev = crtc->dev;
3121         struct drm_i915_private *dev_priv = dev->dev_private;
3122         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3123         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3124         u32 temp;
3125
3126         mutex_lock(&dev_priv->dpio_lock);
3127
3128         /* It is necessary to ungate the pixclk gate prior to programming
3129          * the divisors, and gate it back when it is done.
3130          */
3131         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3132
3133         /* Disable SSCCTL */
3134         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3135                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3136                                 SBI_SSCCTL_DISABLE,
3137                         SBI_ICLK);
3138
3139         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3140         if (clock == 20000) {
3141                 auxdiv = 1;
3142                 divsel = 0x41;
3143                 phaseinc = 0x20;
3144         } else {
3145                 /* The iCLK virtual clock root frequency is in MHz,
3146                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3147                  * divisors, it is necessary to divide one by another, so we
3148                  * convert the virtual clock precision to KHz here for higher
3149                  * precision.
3150                  */
3151                 u32 iclk_virtual_root_freq = 172800 * 1000;
3152                 u32 iclk_pi_range = 64;
3153                 u32 desired_divisor, msb_divisor_value, pi_value;
3154
3155                 desired_divisor = (iclk_virtual_root_freq / clock);
3156                 msb_divisor_value = desired_divisor / iclk_pi_range;
3157                 pi_value = desired_divisor % iclk_pi_range;
3158
3159                 auxdiv = 0;
3160                 divsel = msb_divisor_value - 2;
3161                 phaseinc = pi_value;
3162         }
3163
3164         /* This should not happen with any sane values */
3165         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3166                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3167         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3168                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3169
3170         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3171                         clock,
3172                         auxdiv,
3173                         divsel,
3174                         phasedir,
3175                         phaseinc);
3176
3177         /* Program SSCDIVINTPHASE6 */
3178         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3179         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3180         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3181         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3182         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3183         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3184         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3185         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3186
3187         /* Program SSCAUXDIV */
3188         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3189         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3190         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3191         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3192
3193         /* Enable modulator and associated divider */
3194         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3195         temp &= ~SBI_SSCCTL_DISABLE;
3196         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3197
3198         /* Wait for initialization time */
3199         udelay(24);
3200
3201         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3202
3203         mutex_unlock(&dev_priv->dpio_lock);
3204 }
3205
3206 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3207                                                 enum pipe pch_transcoder)
3208 {
3209         struct drm_device *dev = crtc->base.dev;
3210         struct drm_i915_private *dev_priv = dev->dev_private;
3211         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3212
3213         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3214                    I915_READ(HTOTAL(cpu_transcoder)));
3215         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3216                    I915_READ(HBLANK(cpu_transcoder)));
3217         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3218                    I915_READ(HSYNC(cpu_transcoder)));
3219
3220         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3221                    I915_READ(VTOTAL(cpu_transcoder)));
3222         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3223                    I915_READ(VBLANK(cpu_transcoder)));
3224         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3225                    I915_READ(VSYNC(cpu_transcoder)));
3226         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3227                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3228 }
3229
3230 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3231 {
3232         struct drm_i915_private *dev_priv = dev->dev_private;
3233         uint32_t temp;
3234
3235         temp = I915_READ(SOUTH_CHICKEN1);
3236         if (temp & FDI_BC_BIFURCATION_SELECT)
3237                 return;
3238
3239         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3240         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3241
3242         temp |= FDI_BC_BIFURCATION_SELECT;
3243         DRM_DEBUG_KMS("enabling fdi C rx\n");
3244         I915_WRITE(SOUTH_CHICKEN1, temp);
3245         POSTING_READ(SOUTH_CHICKEN1);
3246 }
3247
3248 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3249 {
3250         struct drm_device *dev = intel_crtc->base.dev;
3251         struct drm_i915_private *dev_priv = dev->dev_private;
3252
3253         switch (intel_crtc->pipe) {
3254         case PIPE_A:
3255                 break;
3256         case PIPE_B:
3257                 if (intel_crtc->config.fdi_lanes > 2)
3258                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3259                 else
3260                         cpt_enable_fdi_bc_bifurcation(dev);
3261
3262                 break;
3263         case PIPE_C:
3264                 cpt_enable_fdi_bc_bifurcation(dev);
3265
3266                 break;
3267         default:
3268                 BUG();
3269         }
3270 }
3271
3272 /*
3273  * Enable PCH resources required for PCH ports:
3274  *   - PCH PLLs
3275  *   - FDI training & RX/TX
3276  *   - update transcoder timings
3277  *   - DP transcoding bits
3278  *   - transcoder
3279  */
3280 static void ironlake_pch_enable(struct drm_crtc *crtc)
3281 {
3282         struct drm_device *dev = crtc->dev;
3283         struct drm_i915_private *dev_priv = dev->dev_private;
3284         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3285         int pipe = intel_crtc->pipe;
3286         u32 reg, temp;
3287
3288         assert_pch_transcoder_disabled(dev_priv, pipe);
3289
3290         if (IS_IVYBRIDGE(dev))
3291                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3292
3293         /* Write the TU size bits before fdi link training, so that error
3294          * detection works. */
3295         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3296                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3297
3298         /* For PCH output, training FDI link */
3299         dev_priv->display.fdi_link_train(crtc);
3300
3301         /* We need to program the right clock selection before writing the pixel
3302          * mutliplier into the DPLL. */
3303         if (HAS_PCH_CPT(dev)) {
3304                 u32 sel;
3305
3306                 temp = I915_READ(PCH_DPLL_SEL);
3307                 temp |= TRANS_DPLL_ENABLE(pipe);
3308                 sel = TRANS_DPLLB_SEL(pipe);
3309                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3310                         temp |= sel;
3311                 else
3312                         temp &= ~sel;
3313                 I915_WRITE(PCH_DPLL_SEL, temp);
3314         }
3315
3316         /* XXX: pch pll's can be enabled any time before we enable the PCH
3317          * transcoder, and we actually should do this to not upset any PCH
3318          * transcoder that already use the clock when we share it.
3319          *
3320          * Note that enable_shared_dpll tries to do the right thing, but
3321          * get_shared_dpll unconditionally resets the pll - we need that to have
3322          * the right LVDS enable sequence. */
3323         ironlake_enable_shared_dpll(intel_crtc);
3324
3325         /* set transcoder timing, panel must allow it */
3326         assert_panel_unlocked(dev_priv, pipe);
3327         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3328
3329         intel_fdi_normal_train(crtc);
3330
3331         /* For PCH DP, enable TRANS_DP_CTL */
3332         if (HAS_PCH_CPT(dev) &&
3333             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3334              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3335                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3336                 reg = TRANS_DP_CTL(pipe);
3337                 temp = I915_READ(reg);
3338                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3339                           TRANS_DP_SYNC_MASK |
3340                           TRANS_DP_BPC_MASK);
3341                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3342                          TRANS_DP_ENH_FRAMING);
3343                 temp |= bpc << 9; /* same format but at 11:9 */
3344
3345                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3346                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3347                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3348                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3349
3350                 switch (intel_trans_dp_port_sel(crtc)) {
3351                 case PCH_DP_B:
3352                         temp |= TRANS_DP_PORT_SEL_B;
3353                         break;
3354                 case PCH_DP_C:
3355                         temp |= TRANS_DP_PORT_SEL_C;
3356                         break;
3357                 case PCH_DP_D:
3358                         temp |= TRANS_DP_PORT_SEL_D;
3359                         break;
3360                 default:
3361                         BUG();
3362                 }
3363
3364                 I915_WRITE(reg, temp);
3365         }
3366
3367         ironlake_enable_pch_transcoder(dev_priv, pipe);
3368 }
3369
3370 static void lpt_pch_enable(struct drm_crtc *crtc)
3371 {
3372         struct drm_device *dev = crtc->dev;
3373         struct drm_i915_private *dev_priv = dev->dev_private;
3374         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3375         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3376
3377         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3378
3379         lpt_program_iclkip(crtc);
3380
3381         /* Set transcoder timing. */
3382         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3383
3384         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3385 }
3386
3387 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3388 {
3389         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3390
3391         if (pll == NULL)
3392                 return;
3393
3394         if (pll->refcount == 0) {
3395                 WARN(1, "bad %s refcount\n", pll->name);
3396                 return;
3397         }
3398
3399         if (--pll->refcount == 0) {
3400                 WARN_ON(pll->on);
3401                 WARN_ON(pll->active);
3402         }
3403
3404         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3405 }
3406
3407 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3408 {
3409         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3410         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3411         enum intel_dpll_id i;
3412
3413         if (pll) {
3414                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3415                               crtc->base.base.id, pll->name);
3416                 intel_put_shared_dpll(crtc);
3417         }
3418
3419         if (HAS_PCH_IBX(dev_priv->dev)) {
3420                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3421                 i = (enum intel_dpll_id) crtc->pipe;
3422                 pll = &dev_priv->shared_dplls[i];
3423
3424                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3425                               crtc->base.base.id, pll->name);
3426
3427                 goto found;
3428         }
3429
3430         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3431                 pll = &dev_priv->shared_dplls[i];
3432
3433                 /* Only want to check enabled timings first */
3434                 if (pll->refcount == 0)
3435                         continue;
3436
3437                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3438                            sizeof(pll->hw_state)) == 0) {
3439                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3440                                       crtc->base.base.id,
3441                                       pll->name, pll->refcount, pll->active);
3442
3443                         goto found;
3444                 }
3445         }
3446
3447         /* Ok no matching timings, maybe there's a free one? */
3448         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3449                 pll = &dev_priv->shared_dplls[i];
3450                 if (pll->refcount == 0) {
3451                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3452                                       crtc->base.base.id, pll->name);
3453                         goto found;
3454                 }
3455         }
3456
3457         return NULL;
3458
3459 found:
3460         crtc->config.shared_dpll = i;
3461         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3462                          pipe_name(crtc->pipe));
3463
3464         if (pll->active == 0) {
3465                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3466                        sizeof(pll->hw_state));
3467
3468                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3469                 WARN_ON(pll->on);
3470                 assert_shared_dpll_disabled(dev_priv, pll);
3471
3472                 pll->mode_set(dev_priv, pll);
3473         }
3474         pll->refcount++;
3475
3476         return pll;
3477 }
3478
3479 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3480 {
3481         struct drm_i915_private *dev_priv = dev->dev_private;
3482         int dslreg = PIPEDSL(pipe);
3483         u32 temp;
3484
3485         temp = I915_READ(dslreg);
3486         udelay(500);
3487         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3488                 if (wait_for(I915_READ(dslreg) != temp, 5))
3489                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3490         }
3491 }
3492
3493 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3494 {
3495         struct drm_device *dev = crtc->base.dev;
3496         struct drm_i915_private *dev_priv = dev->dev_private;
3497         int pipe = crtc->pipe;
3498
3499         if (crtc->config.pch_pfit.enabled) {
3500                 /* Force use of hard-coded filter coefficients
3501                  * as some pre-programmed values are broken,
3502                  * e.g. x201.
3503                  */
3504                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3505                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3506                                                  PF_PIPE_SEL_IVB(pipe));
3507                 else
3508                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3509                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3510                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3511         }
3512 }
3513
3514 static void intel_enable_planes(struct drm_crtc *crtc)
3515 {
3516         struct drm_device *dev = crtc->dev;
3517         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3518         struct drm_plane *plane;
3519         struct intel_plane *intel_plane;
3520
3521         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3522                 intel_plane = to_intel_plane(plane);
3523                 if (intel_plane->pipe == pipe)
3524                         intel_plane_restore(&intel_plane->base);
3525         }
3526 }
3527
3528 static void intel_disable_planes(struct drm_crtc *crtc)
3529 {
3530         struct drm_device *dev = crtc->dev;
3531         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3532         struct drm_plane *plane;
3533         struct intel_plane *intel_plane;
3534
3535         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3536                 intel_plane = to_intel_plane(plane);
3537                 if (intel_plane->pipe == pipe)
3538                         intel_plane_disable(&intel_plane->base);
3539         }
3540 }
3541
3542 void hsw_enable_ips(struct intel_crtc *crtc)
3543 {
3544         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3545
3546         if (!crtc->config.ips_enabled)
3547                 return;
3548
3549         /* We can only enable IPS after we enable a plane and wait for a vblank.
3550          * We guarantee that the plane is enabled by calling intel_enable_ips
3551          * only after intel_enable_plane. And intel_enable_plane already waits
3552          * for a vblank, so all we need to do here is to enable the IPS bit. */
3553         assert_plane_enabled(dev_priv, crtc->plane);
3554         if (IS_BROADWELL(crtc->base.dev)) {
3555                 mutex_lock(&dev_priv->rps.hw_lock);
3556                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3557                 mutex_unlock(&dev_priv->rps.hw_lock);
3558                 /* Quoting Art Runyan: "its not safe to expect any particular
3559                  * value in IPS_CTL bit 31 after enabling IPS through the
3560                  * mailbox." Moreover, the mailbox may return a bogus state,
3561                  * so we need to just enable it and continue on.
3562                  */
3563         } else {
3564                 I915_WRITE(IPS_CTL, IPS_ENABLE);
3565                 /* The bit only becomes 1 in the next vblank, so this wait here
3566                  * is essentially intel_wait_for_vblank. If we don't have this
3567                  * and don't wait for vblanks until the end of crtc_enable, then
3568                  * the HW state readout code will complain that the expected
3569                  * IPS_CTL value is not the one we read. */
3570                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3571                         DRM_ERROR("Timed out waiting for IPS enable\n");
3572         }
3573 }
3574
3575 void hsw_disable_ips(struct intel_crtc *crtc)
3576 {
3577         struct drm_device *dev = crtc->base.dev;
3578         struct drm_i915_private *dev_priv = dev->dev_private;
3579
3580         if (!crtc->config.ips_enabled)
3581                 return;
3582
3583         assert_plane_enabled(dev_priv, crtc->plane);
3584         if (IS_BROADWELL(dev)) {
3585                 mutex_lock(&dev_priv->rps.hw_lock);
3586                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3587                 mutex_unlock(&dev_priv->rps.hw_lock);
3588                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3589                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3590                         DRM_ERROR("Timed out waiting for IPS disable\n");
3591         } else {
3592                 I915_WRITE(IPS_CTL, 0);
3593                 POSTING_READ(IPS_CTL);
3594         }
3595
3596         /* We need to wait for a vblank before we can disable the plane. */
3597         intel_wait_for_vblank(dev, crtc->pipe);
3598 }
3599
3600 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3601 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3602 {
3603         struct drm_device *dev = crtc->dev;
3604         struct drm_i915_private *dev_priv = dev->dev_private;
3605         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3606         enum pipe pipe = intel_crtc->pipe;
3607         int palreg = PALETTE(pipe);
3608         int i;
3609         bool reenable_ips = false;
3610
3611         /* The clocks have to be on to load the palette. */
3612         if (!crtc->enabled || !intel_crtc->active)
3613                 return;
3614
3615         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3616                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3617                         assert_dsi_pll_enabled(dev_priv);
3618                 else
3619                         assert_pll_enabled(dev_priv, pipe);
3620         }
3621
3622         /* use legacy palette for Ironlake */
3623         if (HAS_PCH_SPLIT(dev))
3624                 palreg = LGC_PALETTE(pipe);
3625
3626         /* Workaround : Do not read or write the pipe palette/gamma data while
3627          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3628          */
3629         if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3630             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3631              GAMMA_MODE_MODE_SPLIT)) {
3632                 hsw_disable_ips(intel_crtc);
3633                 reenable_ips = true;
3634         }
3635
3636         for (i = 0; i < 256; i++) {
3637                 I915_WRITE(palreg + 4 * i,
3638                            (intel_crtc->lut_r[i] << 16) |
3639                            (intel_crtc->lut_g[i] << 8) |
3640                            intel_crtc->lut_b[i]);
3641         }
3642
3643         if (reenable_ips)
3644                 hsw_enable_ips(intel_crtc);
3645 }
3646
3647 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3648 {
3649         if (!enable && intel_crtc->overlay) {
3650                 struct drm_device *dev = intel_crtc->base.dev;
3651                 struct drm_i915_private *dev_priv = dev->dev_private;
3652
3653                 mutex_lock(&dev->struct_mutex);
3654                 dev_priv->mm.interruptible = false;
3655                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3656                 dev_priv->mm.interruptible = true;
3657                 mutex_unlock(&dev->struct_mutex);
3658         }
3659
3660         /* Let userspace switch the overlay on again. In most cases userspace
3661          * has to recompute where to put it anyway.
3662          */
3663 }
3664
3665 /**
3666  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3667  * cursor plane briefly if not already running after enabling the display
3668  * plane.
3669  * This workaround avoids occasional blank screens when self refresh is
3670  * enabled.
3671  */
3672 static void
3673 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3674 {
3675         u32 cntl = I915_READ(CURCNTR(pipe));
3676
3677         if ((cntl & CURSOR_MODE) == 0) {
3678                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3679
3680                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3681                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3682                 intel_wait_for_vblank(dev_priv->dev, pipe);
3683                 I915_WRITE(CURCNTR(pipe), cntl);
3684                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3685                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3686         }
3687 }
3688
3689 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
3690 {
3691         struct drm_device *dev = crtc->dev;
3692         struct drm_i915_private *dev_priv = dev->dev_private;
3693         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3694         int pipe = intel_crtc->pipe;
3695         int plane = intel_crtc->plane;
3696
3697         intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3698         intel_enable_planes(crtc);
3699         /* The fixup needs to happen before cursor is enabled */
3700         if (IS_G4X(dev))
3701                 g4x_fixup_plane(dev_priv, pipe);
3702         intel_crtc_update_cursor(crtc, true);
3703         intel_crtc_dpms_overlay(intel_crtc, true);
3704
3705         hsw_enable_ips(intel_crtc);
3706
3707         mutex_lock(&dev->struct_mutex);
3708         intel_update_fbc(dev);
3709         mutex_unlock(&dev->struct_mutex);
3710 }
3711
3712 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
3713 {
3714         struct drm_device *dev = crtc->dev;
3715         struct drm_i915_private *dev_priv = dev->dev_private;
3716         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3717         int pipe = intel_crtc->pipe;
3718         int plane = intel_crtc->plane;
3719
3720         intel_crtc_wait_for_pending_flips(crtc);
3721         drm_vblank_off(dev, pipe);
3722
3723         if (dev_priv->fbc.plane == plane)
3724                 intel_disable_fbc(dev);
3725
3726         hsw_disable_ips(intel_crtc);
3727
3728         intel_crtc_dpms_overlay(intel_crtc, false);
3729         intel_crtc_update_cursor(crtc, false);
3730         intel_disable_planes(crtc);
3731         intel_disable_primary_hw_plane(dev_priv, plane, pipe);
3732 }
3733
3734 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3735 {
3736         struct drm_device *dev = crtc->dev;
3737         struct drm_i915_private *dev_priv = dev->dev_private;
3738         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3739         struct intel_encoder *encoder;
3740         int pipe = intel_crtc->pipe;
3741
3742         WARN_ON(!crtc->enabled);
3743
3744         if (intel_crtc->active)
3745                 return;
3746
3747         intel_crtc->active = true;
3748
3749         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3750         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3751
3752         for_each_encoder_on_crtc(dev, crtc, encoder)
3753                 if (encoder->pre_enable)
3754                         encoder->pre_enable(encoder);
3755
3756         if (intel_crtc->config.has_pch_encoder) {
3757                 /* Note: FDI PLL enabling _must_ be done before we enable the
3758                  * cpu pipes, hence this is separate from all the other fdi/pch
3759                  * enabling. */
3760                 ironlake_fdi_pll_enable(intel_crtc);
3761         } else {
3762                 assert_fdi_tx_disabled(dev_priv, pipe);
3763                 assert_fdi_rx_disabled(dev_priv, pipe);
3764         }
3765
3766         ironlake_pfit_enable(intel_crtc);
3767
3768         /*
3769          * On ILK+ LUT must be loaded before the pipe is running but with
3770          * clocks enabled
3771          */
3772         intel_crtc_load_lut(crtc);
3773
3774         intel_update_watermarks(crtc);
3775         intel_enable_pipe(intel_crtc);
3776
3777         if (intel_crtc->config.has_pch_encoder)
3778                 ironlake_pch_enable(crtc);
3779
3780         for_each_encoder_on_crtc(dev, crtc, encoder)
3781                 encoder->enable(encoder);
3782
3783         if (HAS_PCH_CPT(dev))
3784                 cpt_verify_modeset(dev, intel_crtc->pipe);
3785
3786         intel_crtc_enable_planes(crtc);
3787
3788         /*
3789          * There seems to be a race in PCH platform hw (at least on some
3790          * outputs) where an enabled pipe still completes any pageflip right
3791          * away (as if the pipe is off) instead of waiting for vblank. As soon
3792          * as the first vblank happend, everything works as expected. Hence just
3793          * wait for one vblank before returning to avoid strange things
3794          * happening.
3795          */
3796         intel_wait_for_vblank(dev, intel_crtc->pipe);
3797 }
3798
3799 /* IPS only exists on ULT machines and is tied to pipe A. */
3800 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3801 {
3802         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3803 }
3804
3805 /*
3806  * This implements the workaround described in the "notes" section of the mode
3807  * set sequence documentation. When going from no pipes or single pipe to
3808  * multiple pipes, and planes are enabled after the pipe, we need to wait at
3809  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3810  */
3811 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3812 {
3813         struct drm_device *dev = crtc->base.dev;
3814         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3815
3816         /* We want to get the other_active_crtc only if there's only 1 other
3817          * active crtc. */
3818         list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3819                 if (!crtc_it->active || crtc_it == crtc)
3820                         continue;
3821
3822                 if (other_active_crtc)
3823                         return;
3824
3825                 other_active_crtc = crtc_it;
3826         }
3827         if (!other_active_crtc)
3828                 return;
3829
3830         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3831         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3832 }
3833
3834 static void haswell_crtc_enable(struct drm_crtc *crtc)
3835 {
3836         struct drm_device *dev = crtc->dev;
3837         struct drm_i915_private *dev_priv = dev->dev_private;
3838         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3839         struct intel_encoder *encoder;
3840         int pipe = intel_crtc->pipe;
3841
3842         WARN_ON(!crtc->enabled);
3843
3844         if (intel_crtc->active)
3845                 return;
3846
3847         intel_crtc->active = true;
3848
3849         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3850         if (intel_crtc->config.has_pch_encoder)
3851                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3852
3853         if (intel_crtc->config.has_pch_encoder)
3854                 dev_priv->display.fdi_link_train(crtc);
3855
3856         for_each_encoder_on_crtc(dev, crtc, encoder)
3857                 if (encoder->pre_enable)
3858                         encoder->pre_enable(encoder);
3859
3860         intel_ddi_enable_pipe_clock(intel_crtc);
3861
3862         ironlake_pfit_enable(intel_crtc);
3863
3864         /*
3865          * On ILK+ LUT must be loaded before the pipe is running but with
3866          * clocks enabled
3867          */
3868         intel_crtc_load_lut(crtc);
3869
3870         intel_ddi_set_pipe_settings(crtc);
3871         intel_ddi_enable_transcoder_func(crtc);
3872
3873         intel_update_watermarks(crtc);
3874         intel_enable_pipe(intel_crtc);
3875
3876         if (intel_crtc->config.has_pch_encoder)
3877                 lpt_pch_enable(crtc);
3878
3879         for_each_encoder_on_crtc(dev, crtc, encoder) {
3880                 encoder->enable(encoder);
3881                 intel_opregion_notify_encoder(encoder, true);
3882         }
3883
3884         /* If we change the relative order between pipe/planes enabling, we need
3885          * to change the workaround. */
3886         haswell_mode_set_planes_workaround(intel_crtc);
3887         intel_crtc_enable_planes(crtc);
3888 }
3889
3890 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3891 {
3892         struct drm_device *dev = crtc->base.dev;
3893         struct drm_i915_private *dev_priv = dev->dev_private;
3894         int pipe = crtc->pipe;
3895
3896         /* To avoid upsetting the power well on haswell only disable the pfit if
3897          * it's in use. The hw state code will make sure we get this right. */
3898         if (crtc->config.pch_pfit.enabled) {
3899                 I915_WRITE(PF_CTL(pipe), 0);
3900                 I915_WRITE(PF_WIN_POS(pipe), 0);
3901                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3902         }
3903 }
3904
3905 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3906 {
3907         struct drm_device *dev = crtc->dev;
3908         struct drm_i915_private *dev_priv = dev->dev_private;
3909         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3910         struct intel_encoder *encoder;
3911         int pipe = intel_crtc->pipe;
3912         u32 reg, temp;
3913
3914         if (!intel_crtc->active)
3915                 return;
3916
3917         intel_crtc_disable_planes(crtc);
3918
3919         for_each_encoder_on_crtc(dev, crtc, encoder)
3920                 encoder->disable(encoder);
3921
3922         if (intel_crtc->config.has_pch_encoder)
3923                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3924
3925         intel_disable_pipe(dev_priv, pipe);
3926
3927         ironlake_pfit_disable(intel_crtc);
3928
3929         for_each_encoder_on_crtc(dev, crtc, encoder)
3930                 if (encoder->post_disable)
3931                         encoder->post_disable(encoder);
3932
3933         if (intel_crtc->config.has_pch_encoder) {
3934                 ironlake_fdi_disable(crtc);
3935
3936                 ironlake_disable_pch_transcoder(dev_priv, pipe);
3937                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3938
3939                 if (HAS_PCH_CPT(dev)) {
3940                         /* disable TRANS_DP_CTL */
3941                         reg = TRANS_DP_CTL(pipe);
3942                         temp = I915_READ(reg);
3943                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3944                                   TRANS_DP_PORT_SEL_MASK);
3945                         temp |= TRANS_DP_PORT_SEL_NONE;
3946                         I915_WRITE(reg, temp);
3947
3948                         /* disable DPLL_SEL */
3949                         temp = I915_READ(PCH_DPLL_SEL);
3950                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3951                         I915_WRITE(PCH_DPLL_SEL, temp);
3952                 }
3953
3954                 /* disable PCH DPLL */
3955                 intel_disable_shared_dpll(intel_crtc);
3956
3957                 ironlake_fdi_pll_disable(intel_crtc);
3958         }
3959
3960         intel_crtc->active = false;
3961         intel_update_watermarks(crtc);
3962
3963         mutex_lock(&dev->struct_mutex);
3964         intel_update_fbc(dev);
3965         mutex_unlock(&dev->struct_mutex);
3966 }
3967
3968 static void haswell_crtc_disable(struct drm_crtc *crtc)
3969 {
3970         struct drm_device *dev = crtc->dev;
3971         struct drm_i915_private *dev_priv = dev->dev_private;
3972         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3973         struct intel_encoder *encoder;
3974         int pipe = intel_crtc->pipe;
3975         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3976
3977         if (!intel_crtc->active)
3978                 return;
3979
3980         intel_crtc_disable_planes(crtc);
3981
3982         for_each_encoder_on_crtc(dev, crtc, encoder) {
3983                 intel_opregion_notify_encoder(encoder, false);
3984                 encoder->disable(encoder);
3985         }
3986
3987         if (intel_crtc->config.has_pch_encoder)
3988                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3989         intel_disable_pipe(dev_priv, pipe);
3990
3991         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3992
3993         ironlake_pfit_disable(intel_crtc);
3994
3995         intel_ddi_disable_pipe_clock(intel_crtc);
3996
3997         for_each_encoder_on_crtc(dev, crtc, encoder)
3998                 if (encoder->post_disable)
3999                         encoder->post_disable(encoder);
4000
4001         if (intel_crtc->config.has_pch_encoder) {
4002                 lpt_disable_pch_transcoder(dev_priv);
4003                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4004                 intel_ddi_fdi_disable(crtc);
4005         }
4006
4007         intel_crtc->active = false;
4008         intel_update_watermarks(crtc);
4009
4010         mutex_lock(&dev->struct_mutex);
4011         intel_update_fbc(dev);
4012         mutex_unlock(&dev->struct_mutex);
4013 }
4014
4015 static void ironlake_crtc_off(struct drm_crtc *crtc)
4016 {
4017         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4018         intel_put_shared_dpll(intel_crtc);
4019 }
4020
4021 static void haswell_crtc_off(struct drm_crtc *crtc)
4022 {
4023         intel_ddi_put_crtc_pll(crtc);
4024 }
4025
4026 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4027 {
4028         struct drm_device *dev = crtc->base.dev;
4029         struct drm_i915_private *dev_priv = dev->dev_private;
4030         struct intel_crtc_config *pipe_config = &crtc->config;
4031
4032         if (!crtc->config.gmch_pfit.control)
4033                 return;
4034
4035         /*
4036          * The panel fitter should only be adjusted whilst the pipe is disabled,
4037          * according to register description and PRM.
4038          */
4039         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4040         assert_pipe_disabled(dev_priv, crtc->pipe);
4041
4042         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4043         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4044
4045         /* Border color in case we don't scale up to the full screen. Black by
4046          * default, change to something else for debugging. */
4047         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4048 }
4049
4050 #define for_each_power_domain(domain, mask)                             \
4051         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4052                 if ((1 << (domain)) & (mask))
4053
4054 enum intel_display_power_domain
4055 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4056 {
4057         struct drm_device *dev = intel_encoder->base.dev;
4058         struct intel_digital_port *intel_dig_port;
4059
4060         switch (intel_encoder->type) {
4061         case INTEL_OUTPUT_UNKNOWN:
4062                 /* Only DDI platforms should ever use this output type */
4063                 WARN_ON_ONCE(!HAS_DDI(dev));
4064         case INTEL_OUTPUT_DISPLAYPORT:
4065         case INTEL_OUTPUT_HDMI:
4066         case INTEL_OUTPUT_EDP:
4067                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4068                 switch (intel_dig_port->port) {
4069                 case PORT_A:
4070                         return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4071                 case PORT_B:
4072                         return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4073                 case PORT_C:
4074                         return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4075                 case PORT_D:
4076                         return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4077                 default:
4078                         WARN_ON_ONCE(1);
4079                         return POWER_DOMAIN_PORT_OTHER;
4080                 }
4081         case INTEL_OUTPUT_ANALOG:
4082                 return POWER_DOMAIN_PORT_CRT;
4083         case INTEL_OUTPUT_DSI:
4084                 return POWER_DOMAIN_PORT_DSI;
4085         default:
4086                 return POWER_DOMAIN_PORT_OTHER;
4087         }
4088 }
4089
4090 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4091 {
4092         struct drm_device *dev = crtc->dev;
4093         struct intel_encoder *intel_encoder;
4094         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4095         enum pipe pipe = intel_crtc->pipe;
4096         bool pfit_enabled = intel_crtc->config.pch_pfit.enabled;
4097         unsigned long mask;
4098         enum transcoder transcoder;
4099
4100         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4101
4102         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4103         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4104         if (pfit_enabled)
4105                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4106
4107         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4108                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4109
4110         return mask;
4111 }
4112
4113 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4114                                   bool enable)
4115 {
4116         if (dev_priv->power_domains.init_power_on == enable)
4117                 return;
4118
4119         if (enable)
4120                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4121         else
4122                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4123
4124         dev_priv->power_domains.init_power_on = enable;
4125 }
4126
4127 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4128 {
4129         struct drm_i915_private *dev_priv = dev->dev_private;
4130         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4131         struct intel_crtc *crtc;
4132
4133         /*
4134          * First get all needed power domains, then put all unneeded, to avoid
4135          * any unnecessary toggling of the power wells.
4136          */
4137         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
4138                 enum intel_display_power_domain domain;
4139
4140                 if (!crtc->base.enabled)
4141                         continue;
4142
4143                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4144
4145                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4146                         intel_display_power_get(dev_priv, domain);
4147         }
4148
4149         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
4150                 enum intel_display_power_domain domain;
4151
4152                 for_each_power_domain(domain, crtc->enabled_power_domains)
4153                         intel_display_power_put(dev_priv, domain);
4154
4155                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4156         }
4157
4158         intel_display_set_init_power(dev_priv, false);
4159 }
4160
4161 int valleyview_get_vco(struct drm_i915_private *dev_priv)
4162 {
4163         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4164
4165         /* Obtain SKU information */
4166         mutex_lock(&dev_priv->dpio_lock);
4167         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4168                 CCK_FUSE_HPLL_FREQ_MASK;
4169         mutex_unlock(&dev_priv->dpio_lock);
4170
4171         return vco_freq[hpll_freq];
4172 }
4173
4174 /* Adjust CDclk dividers to allow high res or save power if possible */
4175 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4176 {
4177         struct drm_i915_private *dev_priv = dev->dev_private;
4178         u32 val, cmd;
4179
4180         WARN_ON(valleyview_cur_cdclk(dev_priv) != dev_priv->vlv_cdclk_freq);
4181         dev_priv->vlv_cdclk_freq = cdclk;
4182
4183         if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
4184                 cmd = 2;
4185         else if (cdclk == 266)
4186                 cmd = 1;
4187         else
4188                 cmd = 0;
4189
4190         mutex_lock(&dev_priv->rps.hw_lock);
4191         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4192         val &= ~DSPFREQGUAR_MASK;
4193         val |= (cmd << DSPFREQGUAR_SHIFT);
4194         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4195         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4196                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4197                      50)) {
4198                 DRM_ERROR("timed out waiting for CDclk change\n");
4199         }
4200         mutex_unlock(&dev_priv->rps.hw_lock);
4201
4202         if (cdclk == 400) {
4203                 u32 divider, vco;
4204
4205                 vco = valleyview_get_vco(dev_priv);
4206                 divider = ((vco << 1) / cdclk) - 1;
4207
4208                 mutex_lock(&dev_priv->dpio_lock);
4209                 /* adjust cdclk divider */
4210                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4211                 val &= ~0xf;
4212                 val |= divider;
4213                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4214                 mutex_unlock(&dev_priv->dpio_lock);
4215         }
4216
4217         mutex_lock(&dev_priv->dpio_lock);
4218         /* adjust self-refresh exit latency value */
4219         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4220         val &= ~0x7f;
4221
4222         /*
4223          * For high bandwidth configs, we set a higher latency in the bunit
4224          * so that the core display fetch happens in time to avoid underruns.
4225          */
4226         if (cdclk == 400)
4227                 val |= 4500 / 250; /* 4.5 usec */
4228         else
4229                 val |= 3000 / 250; /* 3.0 usec */
4230         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4231         mutex_unlock(&dev_priv->dpio_lock);
4232
4233         /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4234         intel_i2c_reset(dev);
4235 }
4236
4237 int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4238 {
4239         int cur_cdclk, vco;
4240         int divider;
4241
4242         vco = valleyview_get_vco(dev_priv);
4243
4244         mutex_lock(&dev_priv->dpio_lock);
4245         divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4246         mutex_unlock(&dev_priv->dpio_lock);
4247
4248         divider &= 0xf;
4249
4250         cur_cdclk = (vco << 1) / (divider + 1);
4251
4252         return cur_cdclk;
4253 }
4254
4255 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4256                                  int max_pixclk)
4257 {
4258         /*
4259          * Really only a few cases to deal with, as only 4 CDclks are supported:
4260          *   200MHz
4261          *   267MHz
4262          *   320MHz
4263          *   400MHz
4264          * So we check to see whether we're above 90% of the lower bin and
4265          * adjust if needed.
4266          */
4267         if (max_pixclk > 288000) {
4268                 return 400;
4269         } else if (max_pixclk > 240000) {
4270                 return 320;
4271         } else
4272                 return 266;
4273         /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4274 }
4275
4276 /* compute the max pixel clock for new configuration */
4277 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4278 {
4279         struct drm_device *dev = dev_priv->dev;
4280         struct intel_crtc *intel_crtc;
4281         int max_pixclk = 0;
4282
4283         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4284                             base.head) {
4285                 if (intel_crtc->new_enabled)
4286                         max_pixclk = max(max_pixclk,
4287                                          intel_crtc->new_config->adjusted_mode.crtc_clock);
4288         }
4289
4290         return max_pixclk;
4291 }
4292
4293 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4294                                             unsigned *prepare_pipes)
4295 {
4296         struct drm_i915_private *dev_priv = dev->dev_private;
4297         struct intel_crtc *intel_crtc;
4298         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4299
4300         if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4301             dev_priv->vlv_cdclk_freq)
4302                 return;
4303
4304         /* disable/enable all currently active pipes while we change cdclk */
4305         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4306                             base.head)
4307                 if (intel_crtc->base.enabled)
4308                         *prepare_pipes |= (1 << intel_crtc->pipe);
4309 }
4310
4311 static void valleyview_modeset_global_resources(struct drm_device *dev)
4312 {
4313         struct drm_i915_private *dev_priv = dev->dev_private;
4314         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4315         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4316
4317         if (req_cdclk != dev_priv->vlv_cdclk_freq)
4318                 valleyview_set_cdclk(dev, req_cdclk);
4319         modeset_update_crtc_power_domains(dev);
4320 }
4321
4322 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4323 {
4324         struct drm_device *dev = crtc->dev;
4325         struct drm_i915_private *dev_priv = dev->dev_private;
4326         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4327         struct intel_encoder *encoder;
4328         int pipe = intel_crtc->pipe;
4329         bool is_dsi;
4330
4331         WARN_ON(!crtc->enabled);
4332
4333         if (intel_crtc->active)
4334                 return;
4335
4336         intel_crtc->active = true;
4337
4338         for_each_encoder_on_crtc(dev, crtc, encoder)
4339                 if (encoder->pre_pll_enable)
4340                         encoder->pre_pll_enable(encoder);
4341
4342         is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4343
4344         if (!is_dsi)
4345                 vlv_enable_pll(intel_crtc);
4346
4347         for_each_encoder_on_crtc(dev, crtc, encoder)
4348                 if (encoder->pre_enable)
4349                         encoder->pre_enable(encoder);
4350
4351         i9xx_pfit_enable(intel_crtc);
4352
4353         intel_crtc_load_lut(crtc);
4354
4355         intel_update_watermarks(crtc);
4356         intel_enable_pipe(intel_crtc);
4357         intel_wait_for_vblank(dev_priv->dev, pipe);
4358         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4359
4360         intel_crtc_enable_planes(crtc);
4361
4362         for_each_encoder_on_crtc(dev, crtc, encoder)
4363                 encoder->enable(encoder);
4364 }
4365
4366 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4367 {
4368         struct drm_device *dev = crtc->dev;
4369         struct drm_i915_private *dev_priv = dev->dev_private;
4370         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4371         struct intel_encoder *encoder;
4372         int pipe = intel_crtc->pipe;
4373
4374         WARN_ON(!crtc->enabled);
4375
4376         if (intel_crtc->active)
4377                 return;
4378
4379         intel_crtc->active = true;
4380
4381         for_each_encoder_on_crtc(dev, crtc, encoder)
4382                 if (encoder->pre_enable)
4383                         encoder->pre_enable(encoder);
4384
4385         i9xx_enable_pll(intel_crtc);
4386
4387         i9xx_pfit_enable(intel_crtc);
4388
4389         intel_crtc_load_lut(crtc);
4390
4391         intel_update_watermarks(crtc);
4392         intel_enable_pipe(intel_crtc);
4393         intel_wait_for_vblank(dev_priv->dev, pipe);
4394         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4395
4396         intel_crtc_enable_planes(crtc);
4397
4398         for_each_encoder_on_crtc(dev, crtc, encoder)
4399                 encoder->enable(encoder);
4400 }
4401
4402 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4403 {
4404         struct drm_device *dev = crtc->base.dev;
4405         struct drm_i915_private *dev_priv = dev->dev_private;
4406
4407         if (!crtc->config.gmch_pfit.control)
4408                 return;
4409
4410         assert_pipe_disabled(dev_priv, crtc->pipe);
4411
4412         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4413                          I915_READ(PFIT_CONTROL));
4414         I915_WRITE(PFIT_CONTROL, 0);
4415 }
4416
4417 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4418 {
4419         struct drm_device *dev = crtc->dev;
4420         struct drm_i915_private *dev_priv = dev->dev_private;
4421         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4422         struct intel_encoder *encoder;
4423         int pipe = intel_crtc->pipe;
4424
4425         if (!intel_crtc->active)
4426                 return;
4427
4428         for_each_encoder_on_crtc(dev, crtc, encoder)
4429                 encoder->disable(encoder);
4430
4431         intel_crtc_disable_planes(crtc);
4432
4433         intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4434         intel_disable_pipe(dev_priv, pipe);
4435
4436         i9xx_pfit_disable(intel_crtc);
4437
4438         for_each_encoder_on_crtc(dev, crtc, encoder)
4439                 if (encoder->post_disable)
4440                         encoder->post_disable(encoder);
4441
4442         if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
4443                 vlv_disable_pll(dev_priv, pipe);
4444         else if (!IS_VALLEYVIEW(dev))
4445                 i9xx_disable_pll(dev_priv, pipe);
4446
4447         intel_crtc->active = false;
4448         intel_update_watermarks(crtc);
4449
4450         intel_update_fbc(dev);
4451 }
4452
4453 static void i9xx_crtc_off(struct drm_crtc *crtc)
4454 {
4455 }
4456
4457 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4458                                     bool enabled)
4459 {
4460         struct drm_device *dev = crtc->dev;
4461         struct drm_i915_master_private *master_priv;
4462         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4463         int pipe = intel_crtc->pipe;
4464
4465         if (!dev->primary->master)
4466                 return;
4467
4468         master_priv = dev->primary->master->driver_priv;
4469         if (!master_priv->sarea_priv)
4470                 return;
4471
4472         switch (pipe) {
4473         case 0:
4474                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4475                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4476                 break;
4477         case 1:
4478                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4479                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4480                 break;
4481         default:
4482                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4483                 break;
4484         }
4485 }
4486
4487 /**
4488  * Sets the power management mode of the pipe and plane.
4489  */
4490 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4491 {
4492         struct drm_device *dev = crtc->dev;
4493         struct drm_i915_private *dev_priv = dev->dev_private;
4494         struct intel_encoder *intel_encoder;
4495         bool enable = false;
4496
4497         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4498                 enable |= intel_encoder->connectors_active;
4499
4500         if (enable)
4501                 dev_priv->display.crtc_enable(crtc);
4502         else
4503                 dev_priv->display.crtc_disable(crtc);
4504
4505         intel_crtc_update_sarea(crtc, enable);
4506 }
4507
4508 static void intel_crtc_disable(struct drm_crtc *crtc)
4509 {
4510         struct drm_device *dev = crtc->dev;
4511         struct drm_connector *connector;
4512         struct drm_i915_private *dev_priv = dev->dev_private;
4513         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4514
4515         /* crtc should still be enabled when we disable it. */
4516         WARN_ON(!crtc->enabled);
4517
4518         dev_priv->display.crtc_disable(crtc);
4519         intel_crtc->eld_vld = false;
4520         intel_crtc_update_sarea(crtc, false);
4521         dev_priv->display.off(crtc);
4522
4523         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4524         assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4525         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4526
4527         if (crtc->primary->fb) {
4528                 mutex_lock(&dev->struct_mutex);
4529                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->primary->fb)->obj);
4530                 mutex_unlock(&dev->struct_mutex);
4531                 crtc->primary->fb = NULL;
4532         }
4533
4534         /* Update computed state. */
4535         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4536                 if (!connector->encoder || !connector->encoder->crtc)
4537                         continue;
4538
4539                 if (connector->encoder->crtc != crtc)
4540                         continue;
4541
4542                 connector->dpms = DRM_MODE_DPMS_OFF;
4543                 to_intel_encoder(connector->encoder)->connectors_active = false;
4544         }
4545 }
4546
4547 void intel_encoder_destroy(struct drm_encoder *encoder)
4548 {
4549         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4550
4551         drm_encoder_cleanup(encoder);
4552         kfree(intel_encoder);
4553 }
4554
4555 /* Simple dpms helper for encoders with just one connector, no cloning and only
4556  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4557  * state of the entire output pipe. */
4558 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4559 {
4560         if (mode == DRM_MODE_DPMS_ON) {
4561                 encoder->connectors_active = true;
4562
4563                 intel_crtc_update_dpms(encoder->base.crtc);
4564         } else {
4565                 encoder->connectors_active = false;
4566
4567                 intel_crtc_update_dpms(encoder->base.crtc);
4568         }
4569 }
4570
4571 /* Cross check the actual hw state with our own modeset state tracking (and it's
4572  * internal consistency). */
4573 static void intel_connector_check_state(struct intel_connector *connector)
4574 {
4575         if (connector->get_hw_state(connector)) {
4576                 struct intel_encoder *encoder = connector->encoder;
4577                 struct drm_crtc *crtc;
4578                 bool encoder_enabled;
4579                 enum pipe pipe;
4580
4581                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4582                               connector->base.base.id,
4583                               drm_get_connector_name(&connector->base));
4584
4585                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4586                      "wrong connector dpms state\n");
4587                 WARN(connector->base.encoder != &encoder->base,
4588                      "active connector not linked to encoder\n");
4589                 WARN(!encoder->connectors_active,
4590                      "encoder->connectors_active not set\n");
4591
4592                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4593                 WARN(!encoder_enabled, "encoder not enabled\n");
4594                 if (WARN_ON(!encoder->base.crtc))
4595                         return;
4596
4597                 crtc = encoder->base.crtc;
4598
4599                 WARN(!crtc->enabled, "crtc not enabled\n");
4600                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4601                 WARN(pipe != to_intel_crtc(crtc)->pipe,
4602                      "encoder active on the wrong pipe\n");
4603         }
4604 }
4605
4606 /* Even simpler default implementation, if there's really no special case to
4607  * consider. */
4608 void intel_connector_dpms(struct drm_connector *connector, int mode)
4609 {
4610         /* All the simple cases only support two dpms states. */
4611         if (mode != DRM_MODE_DPMS_ON)
4612                 mode = DRM_MODE_DPMS_OFF;
4613
4614         if (mode == connector->dpms)
4615                 return;
4616
4617         connector->dpms = mode;
4618
4619         /* Only need to change hw state when actually enabled */
4620         if (connector->encoder)
4621                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
4622
4623         intel_modeset_check_state(connector->dev);
4624 }
4625
4626 /* Simple connector->get_hw_state implementation for encoders that support only
4627  * one connector and no cloning and hence the encoder state determines the state
4628  * of the connector. */
4629 bool intel_connector_get_hw_state(struct intel_connector *connector)
4630 {
4631         enum pipe pipe = 0;
4632         struct intel_encoder *encoder = connector->encoder;
4633
4634         return encoder->get_hw_state(encoder, &pipe);
4635 }
4636
4637 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4638                                      struct intel_crtc_config *pipe_config)
4639 {
4640         struct drm_i915_private *dev_priv = dev->dev_private;
4641         struct intel_crtc *pipe_B_crtc =
4642                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4643
4644         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4645                       pipe_name(pipe), pipe_config->fdi_lanes);
4646         if (pipe_config->fdi_lanes > 4) {
4647                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4648                               pipe_name(pipe), pipe_config->fdi_lanes);
4649                 return false;
4650         }
4651
4652         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4653                 if (pipe_config->fdi_lanes > 2) {
4654                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4655                                       pipe_config->fdi_lanes);
4656                         return false;
4657                 } else {
4658                         return true;
4659                 }
4660         }
4661
4662         if (INTEL_INFO(dev)->num_pipes == 2)
4663                 return true;
4664
4665         /* Ivybridge 3 pipe is really complicated */
4666         switch (pipe) {
4667         case PIPE_A:
4668                 return true;
4669         case PIPE_B:
4670                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4671                     pipe_config->fdi_lanes > 2) {
4672                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4673                                       pipe_name(pipe), pipe_config->fdi_lanes);
4674                         return false;
4675                 }
4676                 return true;
4677         case PIPE_C:
4678                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4679                     pipe_B_crtc->config.fdi_lanes <= 2) {
4680                         if (pipe_config->fdi_lanes > 2) {
4681                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4682                                               pipe_name(pipe), pipe_config->fdi_lanes);
4683                                 return false;
4684                         }
4685                 } else {
4686                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4687                         return false;
4688                 }
4689                 return true;
4690         default:
4691                 BUG();
4692         }
4693 }
4694
4695 #define RETRY 1
4696 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4697                                        struct intel_crtc_config *pipe_config)
4698 {
4699         struct drm_device *dev = intel_crtc->base.dev;
4700         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4701         int lane, link_bw, fdi_dotclock;
4702         bool setup_ok, needs_recompute = false;
4703
4704 retry:
4705         /* FDI is a binary signal running at ~2.7GHz, encoding
4706          * each output octet as 10 bits. The actual frequency
4707          * is stored as a divider into a 100MHz clock, and the
4708          * mode pixel clock is stored in units of 1KHz.
4709          * Hence the bw of each lane in terms of the mode signal
4710          * is:
4711          */
4712         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4713
4714         fdi_dotclock = adjusted_mode->crtc_clock;
4715
4716         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4717                                            pipe_config->pipe_bpp);
4718
4719         pipe_config->fdi_lanes = lane;
4720
4721         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4722                                link_bw, &pipe_config->fdi_m_n);
4723
4724         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4725                                             intel_crtc->pipe, pipe_config);
4726         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4727                 pipe_config->pipe_bpp -= 2*3;
4728                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4729                               pipe_config->pipe_bpp);
4730                 needs_recompute = true;
4731                 pipe_config->bw_constrained = true;
4732
4733                 goto retry;
4734         }
4735
4736         if (needs_recompute)
4737                 return RETRY;
4738
4739         return setup_ok ? 0 : -EINVAL;
4740 }
4741
4742 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4743                                    struct intel_crtc_config *pipe_config)
4744 {
4745         pipe_config->ips_enabled = i915.enable_ips &&
4746                                    hsw_crtc_supports_ips(crtc) &&
4747                                    pipe_config->pipe_bpp <= 24;
4748 }
4749
4750 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4751                                      struct intel_crtc_config *pipe_config)
4752 {
4753         struct drm_device *dev = crtc->base.dev;
4754         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4755
4756         /* FIXME should check pixel clock limits on all platforms */
4757         if (INTEL_INFO(dev)->gen < 4) {
4758                 struct drm_i915_private *dev_priv = dev->dev_private;
4759                 int clock_limit =
4760                         dev_priv->display.get_display_clock_speed(dev);
4761
4762                 /*
4763                  * Enable pixel doubling when the dot clock
4764                  * is > 90% of the (display) core speed.
4765                  *
4766                  * GDG double wide on either pipe,
4767                  * otherwise pipe A only.
4768                  */
4769                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4770                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
4771                         clock_limit *= 2;
4772                         pipe_config->double_wide = true;
4773                 }
4774
4775                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
4776                         return -EINVAL;
4777         }
4778
4779         /*
4780          * Pipe horizontal size must be even in:
4781          * - DVO ganged mode
4782          * - LVDS dual channel mode
4783          * - Double wide pipe
4784          */
4785         if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4786              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4787                 pipe_config->pipe_src_w &= ~1;
4788
4789         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4790          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4791          */
4792         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4793                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4794                 return -EINVAL;
4795
4796         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4797                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4798         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4799                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4800                  * for lvds. */
4801                 pipe_config->pipe_bpp = 8*3;
4802         }
4803
4804         if (HAS_IPS(dev))
4805                 hsw_compute_ips_config(crtc, pipe_config);
4806
4807         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4808          * clock survives for now. */
4809         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4810                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4811
4812         if (pipe_config->has_pch_encoder)
4813                 return ironlake_fdi_compute_config(crtc, pipe_config);
4814
4815         return 0;
4816 }
4817
4818 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4819 {
4820         return 400000; /* FIXME */
4821 }
4822
4823 static int i945_get_display_clock_speed(struct drm_device *dev)
4824 {
4825         return 400000;
4826 }
4827
4828 static int i915_get_display_clock_speed(struct drm_device *dev)
4829 {
4830         return 333000;
4831 }
4832
4833 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4834 {
4835         return 200000;
4836 }
4837
4838 static int pnv_get_display_clock_speed(struct drm_device *dev)
4839 {
4840         u16 gcfgc = 0;
4841
4842         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4843
4844         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4845         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4846                 return 267000;
4847         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4848                 return 333000;
4849         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4850                 return 444000;
4851         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4852                 return 200000;
4853         default:
4854                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4855         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4856                 return 133000;
4857         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4858                 return 167000;
4859         }
4860 }
4861
4862 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4863 {
4864         u16 gcfgc = 0;
4865
4866         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4867
4868         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4869                 return 133000;
4870         else {
4871                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4872                 case GC_DISPLAY_CLOCK_333_MHZ:
4873                         return 333000;
4874                 default:
4875                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4876                         return 190000;
4877                 }
4878         }
4879 }
4880
4881 static int i865_get_display_clock_speed(struct drm_device *dev)
4882 {
4883         return 266000;
4884 }
4885
4886 static int i855_get_display_clock_speed(struct drm_device *dev)
4887 {
4888         u16 hpllcc = 0;
4889         /* Assume that the hardware is in the high speed state.  This
4890          * should be the default.
4891          */
4892         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4893         case GC_CLOCK_133_200:
4894         case GC_CLOCK_100_200:
4895                 return 200000;
4896         case GC_CLOCK_166_250:
4897                 return 250000;
4898         case GC_CLOCK_100_133:
4899                 return 133000;
4900         }
4901
4902         /* Shouldn't happen */
4903         return 0;
4904 }
4905
4906 static int i830_get_display_clock_speed(struct drm_device *dev)
4907 {
4908         return 133000;
4909 }
4910
4911 static void
4912 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4913 {
4914         while (*num > DATA_LINK_M_N_MASK ||
4915                *den > DATA_LINK_M_N_MASK) {
4916                 *num >>= 1;
4917                 *den >>= 1;
4918         }
4919 }
4920
4921 static void compute_m_n(unsigned int m, unsigned int n,
4922                         uint32_t *ret_m, uint32_t *ret_n)
4923 {
4924         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4925         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4926         intel_reduce_m_n_ratio(ret_m, ret_n);
4927 }
4928
4929 void
4930 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4931                        int pixel_clock, int link_clock,
4932                        struct intel_link_m_n *m_n)
4933 {
4934         m_n->tu = 64;
4935
4936         compute_m_n(bits_per_pixel * pixel_clock,
4937                     link_clock * nlanes * 8,
4938                     &m_n->gmch_m, &m_n->gmch_n);
4939
4940         compute_m_n(pixel_clock, link_clock,
4941                     &m_n->link_m, &m_n->link_n);
4942 }
4943
4944 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4945 {
4946         if (i915.panel_use_ssc >= 0)
4947                 return i915.panel_use_ssc != 0;
4948         return dev_priv->vbt.lvds_use_ssc
4949                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4950 }
4951
4952 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4953 {
4954         struct drm_device *dev = crtc->dev;
4955         struct drm_i915_private *dev_priv = dev->dev_private;
4956         int refclk;
4957
4958         if (IS_VALLEYVIEW(dev)) {
4959                 refclk = 100000;
4960         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4961             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4962                 refclk = dev_priv->vbt.lvds_ssc_freq;
4963                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
4964         } else if (!IS_GEN2(dev)) {
4965                 refclk = 96000;
4966         } else {
4967                 refclk = 48000;
4968         }
4969
4970         return refclk;
4971 }
4972
4973 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4974 {
4975         return (1 << dpll->n) << 16 | dpll->m2;
4976 }
4977
4978 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4979 {
4980         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4981 }
4982
4983 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4984                                      intel_clock_t *reduced_clock)
4985 {
4986         struct drm_device *dev = crtc->base.dev;
4987         struct drm_i915_private *dev_priv = dev->dev_private;
4988         int pipe = crtc->pipe;
4989         u32 fp, fp2 = 0;
4990
4991         if (IS_PINEVIEW(dev)) {
4992                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4993                 if (reduced_clock)
4994                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4995         } else {
4996                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4997                 if (reduced_clock)
4998                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4999         }
5000
5001         I915_WRITE(FP0(pipe), fp);
5002         crtc->config.dpll_hw_state.fp0 = fp;
5003
5004         crtc->lowfreq_avail = false;
5005         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5006             reduced_clock && i915.powersave) {
5007                 I915_WRITE(FP1(pipe), fp2);
5008                 crtc->config.dpll_hw_state.fp1 = fp2;
5009                 crtc->lowfreq_avail = true;
5010         } else {
5011                 I915_WRITE(FP1(pipe), fp);
5012                 crtc->config.dpll_hw_state.fp1 = fp;
5013         }
5014 }
5015
5016 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5017                 pipe)
5018 {
5019         u32 reg_val;
5020
5021         /*
5022          * PLLB opamp always calibrates to max value of 0x3f, force enable it
5023          * and set it to a reasonable value instead.
5024          */
5025         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5026         reg_val &= 0xffffff00;
5027         reg_val |= 0x00000030;
5028         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5029
5030         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5031         reg_val &= 0x8cffffff;
5032         reg_val = 0x8c000000;
5033         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5034
5035         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5036         reg_val &= 0xffffff00;
5037         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5038
5039         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5040         reg_val &= 0x00ffffff;
5041         reg_val |= 0xb0000000;
5042         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5043 }
5044
5045 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5046                                          struct intel_link_m_n *m_n)
5047 {
5048         struct drm_device *dev = crtc->base.dev;
5049         struct drm_i915_private *dev_priv = dev->dev_private;
5050         int pipe = crtc->pipe;
5051
5052         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5053         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5054         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5055         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5056 }
5057
5058 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5059                                          struct intel_link_m_n *m_n)
5060 {
5061         struct drm_device *dev = crtc->base.dev;
5062         struct drm_i915_private *dev_priv = dev->dev_private;
5063         int pipe = crtc->pipe;
5064         enum transcoder transcoder = crtc->config.cpu_transcoder;
5065
5066         if (INTEL_INFO(dev)->gen >= 5) {
5067                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5068                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5069                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5070                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5071         } else {
5072                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5073                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5074                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5075                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5076         }
5077 }
5078
5079 static void intel_dp_set_m_n(struct intel_crtc *crtc)
5080 {
5081         if (crtc->config.has_pch_encoder)
5082                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5083         else
5084                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5085 }
5086
5087 static void vlv_update_pll(struct intel_crtc *crtc)
5088 {
5089         struct drm_device *dev = crtc->base.dev;
5090         struct drm_i915_private *dev_priv = dev->dev_private;
5091         int pipe = crtc->pipe;
5092         u32 dpll, mdiv;
5093         u32 bestn, bestm1, bestm2, bestp1, bestp2;
5094         u32 coreclk, reg_val, dpll_md;
5095
5096         mutex_lock(&dev_priv->dpio_lock);
5097
5098         bestn = crtc->config.dpll.n;
5099         bestm1 = crtc->config.dpll.m1;
5100         bestm2 = crtc->config.dpll.m2;
5101         bestp1 = crtc->config.dpll.p1;
5102         bestp2 = crtc->config.dpll.p2;
5103
5104         /* See eDP HDMI DPIO driver vbios notes doc */
5105
5106         /* PLL B needs special handling */
5107         if (pipe)
5108                 vlv_pllb_recal_opamp(dev_priv, pipe);
5109
5110         /* Set up Tx target for periodic Rcomp update */
5111         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5112
5113         /* Disable target IRef on PLL */
5114         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5115         reg_val &= 0x00ffffff;
5116         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5117
5118         /* Disable fast lock */
5119         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5120
5121         /* Set idtafcrecal before PLL is enabled */
5122         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5123         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5124         mdiv |= ((bestn << DPIO_N_SHIFT));
5125         mdiv |= (1 << DPIO_K_SHIFT);
5126
5127         /*
5128          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5129          * but we don't support that).
5130          * Note: don't use the DAC post divider as it seems unstable.
5131          */
5132         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5133         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5134
5135         mdiv |= DPIO_ENABLE_CALIBRATION;
5136         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5137
5138         /* Set HBR and RBR LPF coefficients */
5139         if (crtc->config.port_clock == 162000 ||
5140             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5141             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5142                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5143                                  0x009f0003);
5144         else
5145                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5146                                  0x00d0000f);
5147
5148         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5149             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5150                 /* Use SSC source */
5151                 if (!pipe)
5152                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5153                                          0x0df40000);
5154                 else
5155                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5156                                          0x0df70000);
5157         } else { /* HDMI or VGA */
5158                 /* Use bend source */
5159                 if (!pipe)
5160                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5161                                          0x0df70000);
5162                 else
5163                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5164                                          0x0df40000);
5165         }
5166
5167         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5168         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5169         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5170             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5171                 coreclk |= 0x01000000;
5172         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5173
5174         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5175
5176         /*
5177          * Enable DPIO clock input. We should never disable the reference
5178          * clock for pipe B, since VGA hotplug / manual detection depends
5179          * on it.
5180          */
5181         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5182                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5183         /* We should never disable this, set it here for state tracking */
5184         if (pipe == PIPE_B)
5185                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5186         dpll |= DPLL_VCO_ENABLE;
5187         crtc->config.dpll_hw_state.dpll = dpll;
5188
5189         dpll_md = (crtc->config.pixel_multiplier - 1)
5190                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5191         crtc->config.dpll_hw_state.dpll_md = dpll_md;
5192
5193         mutex_unlock(&dev_priv->dpio_lock);
5194 }
5195
5196 static void i9xx_update_pll(struct intel_crtc *crtc,
5197                             intel_clock_t *reduced_clock,
5198                             int num_connectors)
5199 {
5200         struct drm_device *dev = crtc->base.dev;
5201         struct drm_i915_private *dev_priv = dev->dev_private;
5202         u32 dpll;
5203         bool is_sdvo;
5204         struct dpll *clock = &crtc->config.dpll;
5205
5206         i9xx_update_pll_dividers(crtc, reduced_clock);
5207
5208         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5209                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5210
5211         dpll = DPLL_VGA_MODE_DIS;
5212
5213         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5214                 dpll |= DPLLB_MODE_LVDS;
5215         else
5216                 dpll |= DPLLB_MODE_DAC_SERIAL;
5217
5218         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5219                 dpll |= (crtc->config.pixel_multiplier - 1)
5220                         << SDVO_MULTIPLIER_SHIFT_HIRES;
5221         }
5222
5223         if (is_sdvo)
5224                 dpll |= DPLL_SDVO_HIGH_SPEED;
5225
5226         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5227                 dpll |= DPLL_SDVO_HIGH_SPEED;
5228
5229         /* compute bitmask from p1 value */
5230         if (IS_PINEVIEW(dev))
5231                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5232         else {
5233                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5234                 if (IS_G4X(dev) && reduced_clock)
5235                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5236         }
5237         switch (clock->p2) {
5238         case 5:
5239                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5240                 break;
5241         case 7:
5242                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5243                 break;
5244         case 10:
5245                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5246                 break;
5247         case 14:
5248                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5249                 break;
5250         }
5251         if (INTEL_INFO(dev)->gen >= 4)
5252                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5253
5254         if (crtc->config.sdvo_tv_clock)
5255                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5256         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5257                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5258                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5259         else
5260                 dpll |= PLL_REF_INPUT_DREFCLK;
5261
5262         dpll |= DPLL_VCO_ENABLE;
5263         crtc->config.dpll_hw_state.dpll = dpll;
5264
5265         if (INTEL_INFO(dev)->gen >= 4) {
5266                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5267                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5268                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5269         }
5270 }
5271
5272 static void i8xx_update_pll(struct intel_crtc *crtc,
5273                             intel_clock_t *reduced_clock,
5274                             int num_connectors)
5275 {
5276         struct drm_device *dev = crtc->base.dev;
5277         struct drm_i915_private *dev_priv = dev->dev_private;
5278         u32 dpll;
5279         struct dpll *clock = &crtc->config.dpll;
5280
5281         i9xx_update_pll_dividers(crtc, reduced_clock);
5282
5283         dpll = DPLL_VGA_MODE_DIS;
5284
5285         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5286                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5287         } else {
5288                 if (clock->p1 == 2)
5289                         dpll |= PLL_P1_DIVIDE_BY_TWO;
5290                 else
5291                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5292                 if (clock->p2 == 4)
5293                         dpll |= PLL_P2_DIVIDE_BY_4;
5294         }
5295
5296         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5297                 dpll |= DPLL_DVO_2X_MODE;
5298
5299         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5300                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5301                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5302         else
5303                 dpll |= PLL_REF_INPUT_DREFCLK;
5304
5305         dpll |= DPLL_VCO_ENABLE;
5306         crtc->config.dpll_hw_state.dpll = dpll;
5307 }
5308
5309 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5310 {
5311         struct drm_device *dev = intel_crtc->base.dev;
5312         struct drm_i915_private *dev_priv = dev->dev_private;
5313         enum pipe pipe = intel_crtc->pipe;
5314         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5315         struct drm_display_mode *adjusted_mode =
5316                 &intel_crtc->config.adjusted_mode;
5317         uint32_t crtc_vtotal, crtc_vblank_end;
5318         int vsyncshift = 0;
5319
5320         /* We need to be careful not to changed the adjusted mode, for otherwise
5321          * the hw state checker will get angry at the mismatch. */
5322         crtc_vtotal = adjusted_mode->crtc_vtotal;
5323         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5324
5325         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5326                 /* the chip adds 2 halflines automatically */
5327                 crtc_vtotal -= 1;
5328                 crtc_vblank_end -= 1;
5329
5330                 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5331                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5332                 else
5333                         vsyncshift = adjusted_mode->crtc_hsync_start -
5334                                 adjusted_mode->crtc_htotal / 2;
5335                 if (vsyncshift < 0)
5336                         vsyncshift += adjusted_mode->crtc_htotal;
5337         }
5338
5339         if (INTEL_INFO(dev)->gen > 3)
5340                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5341
5342         I915_WRITE(HTOTAL(cpu_transcoder),
5343                    (adjusted_mode->crtc_hdisplay - 1) |
5344                    ((adjusted_mode->crtc_htotal - 1) << 16));
5345         I915_WRITE(HBLANK(cpu_transcoder),
5346                    (adjusted_mode->crtc_hblank_start - 1) |
5347                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5348         I915_WRITE(HSYNC(cpu_transcoder),
5349                    (adjusted_mode->crtc_hsync_start - 1) |
5350                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5351
5352         I915_WRITE(VTOTAL(cpu_transcoder),
5353                    (adjusted_mode->crtc_vdisplay - 1) |
5354                    ((crtc_vtotal - 1) << 16));
5355         I915_WRITE(VBLANK(cpu_transcoder),
5356                    (adjusted_mode->crtc_vblank_start - 1) |
5357                    ((crtc_vblank_end - 1) << 16));
5358         I915_WRITE(VSYNC(cpu_transcoder),
5359                    (adjusted_mode->crtc_vsync_start - 1) |
5360                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5361
5362         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5363          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5364          * documented on the DDI_FUNC_CTL register description, EDP Input Select
5365          * bits. */
5366         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5367             (pipe == PIPE_B || pipe == PIPE_C))
5368                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5369
5370         /* pipesrc controls the size that is scaled from, which should
5371          * always be the user's requested size.
5372          */
5373         I915_WRITE(PIPESRC(pipe),
5374                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
5375                    (intel_crtc->config.pipe_src_h - 1));
5376 }
5377
5378 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5379                                    struct intel_crtc_config *pipe_config)
5380 {
5381         struct drm_device *dev = crtc->base.dev;
5382         struct drm_i915_private *dev_priv = dev->dev_private;
5383         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5384         uint32_t tmp;
5385
5386         tmp = I915_READ(HTOTAL(cpu_transcoder));
5387         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5388         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5389         tmp = I915_READ(HBLANK(cpu_transcoder));
5390         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5391         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5392         tmp = I915_READ(HSYNC(cpu_transcoder));
5393         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5394         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5395
5396         tmp = I915_READ(VTOTAL(cpu_transcoder));
5397         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5398         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5399         tmp = I915_READ(VBLANK(cpu_transcoder));
5400         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5401         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5402         tmp = I915_READ(VSYNC(cpu_transcoder));
5403         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5404         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5405
5406         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5407                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5408                 pipe_config->adjusted_mode.crtc_vtotal += 1;
5409                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5410         }
5411
5412         tmp = I915_READ(PIPESRC(crtc->pipe));
5413         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5414         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5415
5416         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5417         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5418 }
5419
5420 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5421                                  struct intel_crtc_config *pipe_config)
5422 {
5423         mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5424         mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5425         mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5426         mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5427
5428         mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5429         mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5430         mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5431         mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5432
5433         mode->flags = pipe_config->adjusted_mode.flags;
5434
5435         mode->clock = pipe_config->adjusted_mode.crtc_clock;
5436         mode->flags |= pipe_config->adjusted_mode.flags;
5437 }
5438
5439 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5440 {
5441         struct drm_device *dev = intel_crtc->base.dev;
5442         struct drm_i915_private *dev_priv = dev->dev_private;
5443         uint32_t pipeconf;
5444
5445         pipeconf = 0;
5446
5447         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5448             I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5449                 pipeconf |= PIPECONF_ENABLE;
5450
5451         if (intel_crtc->config.double_wide)
5452                 pipeconf |= PIPECONF_DOUBLE_WIDE;
5453
5454         /* only g4x and later have fancy bpc/dither controls */
5455         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5456                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5457                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5458                         pipeconf |= PIPECONF_DITHER_EN |
5459                                     PIPECONF_DITHER_TYPE_SP;
5460
5461                 switch (intel_crtc->config.pipe_bpp) {
5462                 case 18:
5463                         pipeconf |= PIPECONF_6BPC;
5464                         break;
5465                 case 24:
5466                         pipeconf |= PIPECONF_8BPC;
5467                         break;
5468                 case 30:
5469                         pipeconf |= PIPECONF_10BPC;
5470                         break;
5471                 default:
5472                         /* Case prevented by intel_choose_pipe_bpp_dither. */
5473                         BUG();
5474                 }
5475         }
5476
5477         if (HAS_PIPE_CXSR(dev)) {
5478                 if (intel_crtc->lowfreq_avail) {
5479                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5480                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5481                 } else {
5482                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5483                 }
5484         }
5485
5486         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
5487                 if (INTEL_INFO(dev)->gen < 4 ||
5488                     intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5489                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5490                 else
5491                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
5492         } else
5493                 pipeconf |= PIPECONF_PROGRESSIVE;
5494
5495         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5496                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5497
5498         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5499         POSTING_READ(PIPECONF(intel_crtc->pipe));
5500 }
5501
5502 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5503                               int x, int y,
5504                               struct drm_framebuffer *fb)
5505 {
5506         struct drm_device *dev = crtc->dev;
5507         struct drm_i915_private *dev_priv = dev->dev_private;
5508         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5509         int pipe = intel_crtc->pipe;
5510         int plane = intel_crtc->plane;
5511         int refclk, num_connectors = 0;
5512         intel_clock_t clock, reduced_clock;
5513         u32 dspcntr;
5514         bool ok, has_reduced_clock = false;
5515         bool is_lvds = false, is_dsi = false;
5516         struct intel_encoder *encoder;
5517         const intel_limit_t *limit;
5518         int ret;
5519
5520         for_each_encoder_on_crtc(dev, crtc, encoder) {
5521                 switch (encoder->type) {
5522                 case INTEL_OUTPUT_LVDS:
5523                         is_lvds = true;
5524                         break;
5525                 case INTEL_OUTPUT_DSI:
5526                         is_dsi = true;
5527                         break;
5528                 }
5529
5530                 num_connectors++;
5531         }
5532
5533         if (is_dsi)
5534                 goto skip_dpll;
5535
5536         if (!intel_crtc->config.clock_set) {
5537                 refclk = i9xx_get_refclk(crtc, num_connectors);
5538
5539                 /*
5540                  * Returns a set of divisors for the desired target clock with
5541                  * the given refclk, or FALSE.  The returned values represent
5542                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5543                  * 2) / p1 / p2.
5544                  */
5545                 limit = intel_limit(crtc, refclk);
5546                 ok = dev_priv->display.find_dpll(limit, crtc,
5547                                                  intel_crtc->config.port_clock,
5548                                                  refclk, NULL, &clock);
5549                 if (!ok) {
5550                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5551                         return -EINVAL;
5552                 }
5553
5554                 if (is_lvds && dev_priv->lvds_downclock_avail) {
5555                         /*
5556                          * Ensure we match the reduced clock's P to the target
5557                          * clock.  If the clocks don't match, we can't switch
5558                          * the display clock by using the FP0/FP1. In such case
5559                          * we will disable the LVDS downclock feature.
5560                          */
5561                         has_reduced_clock =
5562                                 dev_priv->display.find_dpll(limit, crtc,
5563                                                             dev_priv->lvds_downclock,
5564                                                             refclk, &clock,
5565                                                             &reduced_clock);
5566                 }
5567                 /* Compat-code for transition, will disappear. */
5568                 intel_crtc->config.dpll.n = clock.n;
5569                 intel_crtc->config.dpll.m1 = clock.m1;
5570                 intel_crtc->config.dpll.m2 = clock.m2;
5571                 intel_crtc->config.dpll.p1 = clock.p1;
5572                 intel_crtc->config.dpll.p2 = clock.p2;
5573         }
5574
5575         if (IS_GEN2(dev)) {
5576                 i8xx_update_pll(intel_crtc,
5577                                 has_reduced_clock ? &reduced_clock : NULL,
5578                                 num_connectors);
5579         } else if (IS_VALLEYVIEW(dev)) {
5580                 vlv_update_pll(intel_crtc);
5581         } else {
5582                 i9xx_update_pll(intel_crtc,
5583                                 has_reduced_clock ? &reduced_clock : NULL,
5584                                 num_connectors);
5585         }
5586
5587 skip_dpll:
5588         /* Set up the display plane register */
5589         dspcntr = DISPPLANE_GAMMA_ENABLE;
5590
5591         if (!IS_VALLEYVIEW(dev)) {
5592                 if (pipe == 0)
5593                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5594                 else
5595                         dspcntr |= DISPPLANE_SEL_PIPE_B;
5596         }
5597
5598         if (intel_crtc->config.has_dp_encoder)
5599                 intel_dp_set_m_n(intel_crtc);
5600
5601         intel_set_pipe_timings(intel_crtc);
5602
5603         /* pipesrc and dspsize control the size that is scaled from,
5604          * which should always be the user's requested size.
5605          */
5606         I915_WRITE(DSPSIZE(plane),
5607                    ((intel_crtc->config.pipe_src_h - 1) << 16) |
5608                    (intel_crtc->config.pipe_src_w - 1));
5609         I915_WRITE(DSPPOS(plane), 0);
5610
5611         i9xx_set_pipeconf(intel_crtc);
5612
5613         I915_WRITE(DSPCNTR(plane), dspcntr);
5614         POSTING_READ(DSPCNTR(plane));
5615
5616         ret = intel_pipe_set_base(crtc, x, y, fb);
5617
5618         return ret;
5619 }
5620
5621 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5622                                  struct intel_crtc_config *pipe_config)
5623 {
5624         struct drm_device *dev = crtc->base.dev;
5625         struct drm_i915_private *dev_priv = dev->dev_private;
5626         uint32_t tmp;
5627
5628         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
5629                 return;
5630
5631         tmp = I915_READ(PFIT_CONTROL);
5632         if (!(tmp & PFIT_ENABLE))
5633                 return;
5634
5635         /* Check whether the pfit is attached to our pipe. */
5636         if (INTEL_INFO(dev)->gen < 4) {
5637                 if (crtc->pipe != PIPE_B)
5638                         return;
5639         } else {
5640                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5641                         return;
5642         }
5643
5644         pipe_config->gmch_pfit.control = tmp;
5645         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5646         if (INTEL_INFO(dev)->gen < 5)
5647                 pipe_config->gmch_pfit.lvds_border_bits =
5648                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5649 }
5650
5651 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5652                                struct intel_crtc_config *pipe_config)
5653 {
5654         struct drm_device *dev = crtc->base.dev;
5655         struct drm_i915_private *dev_priv = dev->dev_private;
5656         int pipe = pipe_config->cpu_transcoder;
5657         intel_clock_t clock;
5658         u32 mdiv;
5659         int refclk = 100000;
5660
5661         mutex_lock(&dev_priv->dpio_lock);
5662         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
5663         mutex_unlock(&dev_priv->dpio_lock);
5664
5665         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5666         clock.m2 = mdiv & DPIO_M2DIV_MASK;
5667         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5668         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5669         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5670
5671         vlv_clock(refclk, &clock);
5672
5673         /* clock.dot is the fast clock */
5674         pipe_config->port_clock = clock.dot / 5;
5675 }
5676
5677 static void i9xx_get_plane_config(struct intel_crtc *crtc,
5678                                   struct intel_plane_config *plane_config)
5679 {
5680         struct drm_device *dev = crtc->base.dev;
5681         struct drm_i915_private *dev_priv = dev->dev_private;
5682         u32 val, base, offset;
5683         int pipe = crtc->pipe, plane = crtc->plane;
5684         int fourcc, pixel_format;
5685         int aligned_height;
5686
5687         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
5688         if (!crtc->base.primary->fb) {
5689                 DRM_DEBUG_KMS("failed to alloc fb\n");
5690                 return;
5691         }
5692
5693         val = I915_READ(DSPCNTR(plane));
5694
5695         if (INTEL_INFO(dev)->gen >= 4)
5696                 if (val & DISPPLANE_TILED)
5697                         plane_config->tiled = true;
5698
5699         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
5700         fourcc = intel_format_to_fourcc(pixel_format);
5701         crtc->base.primary->fb->pixel_format = fourcc;
5702         crtc->base.primary->fb->bits_per_pixel =
5703                 drm_format_plane_cpp(fourcc, 0) * 8;
5704
5705         if (INTEL_INFO(dev)->gen >= 4) {
5706                 if (plane_config->tiled)
5707                         offset = I915_READ(DSPTILEOFF(plane));
5708                 else
5709                         offset = I915_READ(DSPLINOFF(plane));
5710                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
5711         } else {
5712                 base = I915_READ(DSPADDR(plane));
5713         }
5714         plane_config->base = base;
5715
5716         val = I915_READ(PIPESRC(pipe));
5717         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
5718         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
5719
5720         val = I915_READ(DSPSTRIDE(pipe));
5721         crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
5722
5723         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
5724                                             plane_config->tiled);
5725
5726         plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
5727                                    aligned_height, PAGE_SIZE);
5728
5729         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
5730                       pipe, plane, crtc->base.primary->fb->width,
5731                       crtc->base.primary->fb->height,
5732                       crtc->base.primary->fb->bits_per_pixel, base,
5733                       crtc->base.primary->fb->pitches[0],
5734                       plane_config->size);
5735
5736 }
5737
5738 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5739                                  struct intel_crtc_config *pipe_config)
5740 {
5741         struct drm_device *dev = crtc->base.dev;
5742         struct drm_i915_private *dev_priv = dev->dev_private;
5743         uint32_t tmp;
5744
5745         if (!intel_display_power_enabled(dev_priv,
5746                                          POWER_DOMAIN_PIPE(crtc->pipe)))
5747                 return false;
5748
5749         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5750         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5751
5752         tmp = I915_READ(PIPECONF(crtc->pipe));
5753         if (!(tmp & PIPECONF_ENABLE))
5754                 return false;
5755
5756         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5757                 switch (tmp & PIPECONF_BPC_MASK) {
5758                 case PIPECONF_6BPC:
5759                         pipe_config->pipe_bpp = 18;
5760                         break;
5761                 case PIPECONF_8BPC:
5762                         pipe_config->pipe_bpp = 24;
5763                         break;
5764                 case PIPECONF_10BPC:
5765                         pipe_config->pipe_bpp = 30;
5766                         break;
5767                 default:
5768                         break;
5769                 }
5770         }
5771
5772         if (INTEL_INFO(dev)->gen < 4)
5773                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5774
5775         intel_get_pipe_timings(crtc, pipe_config);
5776
5777         i9xx_get_pfit_config(crtc, pipe_config);
5778
5779         if (INTEL_INFO(dev)->gen >= 4) {
5780                 tmp = I915_READ(DPLL_MD(crtc->pipe));
5781                 pipe_config->pixel_multiplier =
5782                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5783                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5784                 pipe_config->dpll_hw_state.dpll_md = tmp;
5785         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5786                 tmp = I915_READ(DPLL(crtc->pipe));
5787                 pipe_config->pixel_multiplier =
5788                         ((tmp & SDVO_MULTIPLIER_MASK)
5789                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5790         } else {
5791                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5792                  * port and will be fixed up in the encoder->get_config
5793                  * function. */
5794                 pipe_config->pixel_multiplier = 1;
5795         }
5796         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5797         if (!IS_VALLEYVIEW(dev)) {
5798                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5799                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5800         } else {
5801                 /* Mask out read-only status bits. */
5802                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5803                                                      DPLL_PORTC_READY_MASK |
5804                                                      DPLL_PORTB_READY_MASK);
5805         }
5806
5807         if (IS_VALLEYVIEW(dev))
5808                 vlv_crtc_clock_get(crtc, pipe_config);
5809         else
5810                 i9xx_crtc_clock_get(crtc, pipe_config);
5811
5812         return true;
5813 }
5814
5815 static void ironlake_init_pch_refclk(struct drm_device *dev)
5816 {
5817         struct drm_i915_private *dev_priv = dev->dev_private;
5818         struct drm_mode_config *mode_config = &dev->mode_config;
5819         struct intel_encoder *encoder;
5820         u32 val, final;
5821         bool has_lvds = false;
5822         bool has_cpu_edp = false;
5823         bool has_panel = false;
5824         bool has_ck505 = false;
5825         bool can_ssc = false;
5826
5827         /* We need to take the global config into account */
5828         list_for_each_entry(encoder, &mode_config->encoder_list,
5829                             base.head) {
5830                 switch (encoder->type) {
5831                 case INTEL_OUTPUT_LVDS:
5832                         has_panel = true;
5833                         has_lvds = true;
5834                         break;
5835                 case INTEL_OUTPUT_EDP:
5836                         has_panel = true;
5837                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5838                                 has_cpu_edp = true;
5839                         break;
5840                 }
5841         }
5842
5843         if (HAS_PCH_IBX(dev)) {
5844                 has_ck505 = dev_priv->vbt.display_clock_mode;
5845                 can_ssc = has_ck505;
5846         } else {
5847                 has_ck505 = false;
5848                 can_ssc = true;
5849         }
5850
5851         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5852                       has_panel, has_lvds, has_ck505);
5853
5854         /* Ironlake: try to setup display ref clock before DPLL
5855          * enabling. This is only under driver's control after
5856          * PCH B stepping, previous chipset stepping should be
5857          * ignoring this setting.
5858          */
5859         val = I915_READ(PCH_DREF_CONTROL);
5860
5861         /* As we must carefully and slowly disable/enable each source in turn,
5862          * compute the final state we want first and check if we need to
5863          * make any changes at all.
5864          */
5865         final = val;
5866         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5867         if (has_ck505)
5868                 final |= DREF_NONSPREAD_CK505_ENABLE;
5869         else
5870                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5871
5872         final &= ~DREF_SSC_SOURCE_MASK;
5873         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5874         final &= ~DREF_SSC1_ENABLE;
5875
5876         if (has_panel) {
5877                 final |= DREF_SSC_SOURCE_ENABLE;
5878
5879                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5880                         final |= DREF_SSC1_ENABLE;
5881
5882                 if (has_cpu_edp) {
5883                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5884                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5885                         else
5886                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5887                 } else
5888                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5889         } else {
5890                 final |= DREF_SSC_SOURCE_DISABLE;
5891                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5892         }
5893
5894         if (final == val)
5895                 return;
5896
5897         /* Always enable nonspread source */
5898         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5899
5900         if (has_ck505)
5901                 val |= DREF_NONSPREAD_CK505_ENABLE;
5902         else
5903                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5904
5905         if (has_panel) {
5906                 val &= ~DREF_SSC_SOURCE_MASK;
5907                 val |= DREF_SSC_SOURCE_ENABLE;
5908
5909                 /* SSC must be turned on before enabling the CPU output  */
5910                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5911                         DRM_DEBUG_KMS("Using SSC on panel\n");
5912                         val |= DREF_SSC1_ENABLE;
5913                 } else
5914                         val &= ~DREF_SSC1_ENABLE;
5915
5916                 /* Get SSC going before enabling the outputs */
5917                 I915_WRITE(PCH_DREF_CONTROL, val);
5918                 POSTING_READ(PCH_DREF_CONTROL);
5919                 udelay(200);
5920
5921                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5922
5923                 /* Enable CPU source on CPU attached eDP */
5924                 if (has_cpu_edp) {
5925                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5926                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5927                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5928                         }
5929                         else
5930                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5931                 } else
5932                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5933
5934                 I915_WRITE(PCH_DREF_CONTROL, val);
5935                 POSTING_READ(PCH_DREF_CONTROL);
5936                 udelay(200);
5937         } else {
5938                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5939
5940                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5941
5942                 /* Turn off CPU output */
5943                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5944
5945                 I915_WRITE(PCH_DREF_CONTROL, val);
5946                 POSTING_READ(PCH_DREF_CONTROL);
5947                 udelay(200);
5948
5949                 /* Turn off the SSC source */
5950                 val &= ~DREF_SSC_SOURCE_MASK;
5951                 val |= DREF_SSC_SOURCE_DISABLE;
5952
5953                 /* Turn off SSC1 */
5954                 val &= ~DREF_SSC1_ENABLE;
5955
5956                 I915_WRITE(PCH_DREF_CONTROL, val);
5957                 POSTING_READ(PCH_DREF_CONTROL);
5958                 udelay(200);
5959         }
5960
5961         BUG_ON(val != final);
5962 }
5963
5964 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5965 {
5966         uint32_t tmp;
5967
5968         tmp = I915_READ(SOUTH_CHICKEN2);
5969         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5970         I915_WRITE(SOUTH_CHICKEN2, tmp);
5971
5972         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5973                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5974                 DRM_ERROR("FDI mPHY reset assert timeout\n");
5975
5976         tmp = I915_READ(SOUTH_CHICKEN2);
5977         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5978         I915_WRITE(SOUTH_CHICKEN2, tmp);
5979
5980         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5981                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5982                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5983 }
5984
5985 /* WaMPhyProgramming:hsw */
5986 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5987 {
5988         uint32_t tmp;
5989
5990         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5991         tmp &= ~(0xFF << 24);
5992         tmp |= (0x12 << 24);
5993         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5994
5995         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5996         tmp |= (1 << 11);
5997         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5998
5999         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6000         tmp |= (1 << 11);
6001         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6002
6003         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6004         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6005         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6006
6007         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6008         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6009         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6010
6011         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6012         tmp &= ~(7 << 13);
6013         tmp |= (5 << 13);
6014         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6015
6016         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6017         tmp &= ~(7 << 13);
6018         tmp |= (5 << 13);
6019         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6020
6021         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6022         tmp &= ~0xFF;
6023         tmp |= 0x1C;
6024         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6025
6026         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6027         tmp &= ~0xFF;
6028         tmp |= 0x1C;
6029         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6030
6031         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6032         tmp &= ~(0xFF << 16);
6033         tmp |= (0x1C << 16);
6034         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6035
6036         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6037         tmp &= ~(0xFF << 16);
6038         tmp |= (0x1C << 16);
6039         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6040
6041         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6042         tmp |= (1 << 27);
6043         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6044
6045         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6046         tmp |= (1 << 27);
6047         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6048
6049         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6050         tmp &= ~(0xF << 28);
6051         tmp |= (4 << 28);
6052         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6053
6054         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6055         tmp &= ~(0xF << 28);
6056         tmp |= (4 << 28);
6057         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6058 }
6059
6060 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6061  * Programming" based on the parameters passed:
6062  * - Sequence to enable CLKOUT_DP
6063  * - Sequence to enable CLKOUT_DP without spread
6064  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6065  */
6066 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6067                                  bool with_fdi)
6068 {
6069         struct drm_i915_private *dev_priv = dev->dev_private;
6070         uint32_t reg, tmp;
6071
6072         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6073                 with_spread = true;
6074         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6075                  with_fdi, "LP PCH doesn't have FDI\n"))
6076                 with_fdi = false;
6077
6078         mutex_lock(&dev_priv->dpio_lock);
6079
6080         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6081         tmp &= ~SBI_SSCCTL_DISABLE;
6082         tmp |= SBI_SSCCTL_PATHALT;
6083         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6084
6085         udelay(24);
6086
6087         if (with_spread) {
6088                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6089                 tmp &= ~SBI_SSCCTL_PATHALT;
6090                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6091
6092                 if (with_fdi) {
6093                         lpt_reset_fdi_mphy(dev_priv);
6094                         lpt_program_fdi_mphy(dev_priv);
6095                 }
6096         }
6097
6098         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6099                SBI_GEN0 : SBI_DBUFF0;
6100         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6101         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6102         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6103
6104         mutex_unlock(&dev_priv->dpio_lock);
6105 }
6106
6107 /* Sequence to disable CLKOUT_DP */
6108 static void lpt_disable_clkout_dp(struct drm_device *dev)
6109 {
6110         struct drm_i915_private *dev_priv = dev->dev_private;
6111         uint32_t reg, tmp;
6112
6113         mutex_lock(&dev_priv->dpio_lock);
6114
6115         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6116                SBI_GEN0 : SBI_DBUFF0;
6117         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6118         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6119         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6120
6121         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6122         if (!(tmp & SBI_SSCCTL_DISABLE)) {
6123                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6124                         tmp |= SBI_SSCCTL_PATHALT;
6125                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6126                         udelay(32);
6127                 }
6128                 tmp |= SBI_SSCCTL_DISABLE;
6129                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6130         }
6131
6132         mutex_unlock(&dev_priv->dpio_lock);
6133 }
6134
6135 static void lpt_init_pch_refclk(struct drm_device *dev)
6136 {
6137         struct drm_mode_config *mode_config = &dev->mode_config;
6138         struct intel_encoder *encoder;
6139         bool has_vga = false;
6140
6141         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
6142                 switch (encoder->type) {
6143                 case INTEL_OUTPUT_ANALOG:
6144                         has_vga = true;
6145                         break;
6146                 }
6147         }
6148
6149         if (has_vga)
6150                 lpt_enable_clkout_dp(dev, true, true);
6151         else
6152                 lpt_disable_clkout_dp(dev);
6153 }
6154
6155 /*
6156  * Initialize reference clocks when the driver loads
6157  */
6158 void intel_init_pch_refclk(struct drm_device *dev)
6159 {
6160         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6161                 ironlake_init_pch_refclk(dev);
6162         else if (HAS_PCH_LPT(dev))
6163                 lpt_init_pch_refclk(dev);
6164 }
6165
6166 static int ironlake_get_refclk(struct drm_crtc *crtc)
6167 {
6168         struct drm_device *dev = crtc->dev;
6169         struct drm_i915_private *dev_priv = dev->dev_private;
6170         struct intel_encoder *encoder;
6171         int num_connectors = 0;
6172         bool is_lvds = false;
6173
6174         for_each_encoder_on_crtc(dev, crtc, encoder) {
6175                 switch (encoder->type) {
6176                 case INTEL_OUTPUT_LVDS:
6177                         is_lvds = true;
6178                         break;
6179                 }
6180                 num_connectors++;
6181         }
6182
6183         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6184                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6185                               dev_priv->vbt.lvds_ssc_freq);
6186                 return dev_priv->vbt.lvds_ssc_freq;
6187         }
6188
6189         return 120000;
6190 }
6191
6192 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6193 {
6194         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6195         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6196         int pipe = intel_crtc->pipe;
6197         uint32_t val;
6198
6199         val = 0;
6200
6201         switch (intel_crtc->config.pipe_bpp) {
6202         case 18:
6203                 val |= PIPECONF_6BPC;
6204                 break;
6205         case 24:
6206                 val |= PIPECONF_8BPC;
6207                 break;
6208         case 30:
6209                 val |= PIPECONF_10BPC;
6210                 break;
6211         case 36:
6212                 val |= PIPECONF_12BPC;
6213                 break;
6214         default:
6215                 /* Case prevented by intel_choose_pipe_bpp_dither. */
6216                 BUG();
6217         }
6218
6219         if (intel_crtc->config.dither)
6220                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6221
6222         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6223                 val |= PIPECONF_INTERLACED_ILK;
6224         else
6225                 val |= PIPECONF_PROGRESSIVE;
6226
6227         if (intel_crtc->config.limited_color_range)
6228                 val |= PIPECONF_COLOR_RANGE_SELECT;
6229
6230         I915_WRITE(PIPECONF(pipe), val);
6231         POSTING_READ(PIPECONF(pipe));
6232 }
6233
6234 /*
6235  * Set up the pipe CSC unit.
6236  *
6237  * Currently only full range RGB to limited range RGB conversion
6238  * is supported, but eventually this should handle various
6239  * RGB<->YCbCr scenarios as well.
6240  */
6241 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6242 {
6243         struct drm_device *dev = crtc->dev;
6244         struct drm_i915_private *dev_priv = dev->dev_private;
6245         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6246         int pipe = intel_crtc->pipe;
6247         uint16_t coeff = 0x7800; /* 1.0 */
6248
6249         /*
6250          * TODO: Check what kind of values actually come out of the pipe
6251          * with these coeff/postoff values and adjust to get the best
6252          * accuracy. Perhaps we even need to take the bpc value into
6253          * consideration.
6254          */
6255
6256         if (intel_crtc->config.limited_color_range)
6257                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6258
6259         /*
6260          * GY/GU and RY/RU should be the other way around according
6261          * to BSpec, but reality doesn't agree. Just set them up in
6262          * a way that results in the correct picture.
6263          */
6264         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6265         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6266
6267         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6268         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6269
6270         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6271         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6272
6273         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6274         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6275         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6276
6277         if (INTEL_INFO(dev)->gen > 6) {
6278                 uint16_t postoff = 0;
6279
6280                 if (intel_crtc->config.limited_color_range)
6281                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
6282
6283                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6284                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6285                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6286
6287                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6288         } else {
6289                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6290
6291                 if (intel_crtc->config.limited_color_range)
6292                         mode |= CSC_BLACK_SCREEN_OFFSET;
6293
6294                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6295         }
6296 }
6297
6298 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6299 {
6300         struct drm_device *dev = crtc->dev;
6301         struct drm_i915_private *dev_priv = dev->dev_private;
6302         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6303         enum pipe pipe = intel_crtc->pipe;
6304         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6305         uint32_t val;
6306
6307         val = 0;
6308
6309         if (IS_HASWELL(dev) && intel_crtc->config.dither)
6310                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6311
6312         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6313                 val |= PIPECONF_INTERLACED_ILK;
6314         else
6315                 val |= PIPECONF_PROGRESSIVE;
6316
6317         I915_WRITE(PIPECONF(cpu_transcoder), val);
6318         POSTING_READ(PIPECONF(cpu_transcoder));
6319
6320         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6321         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6322
6323         if (IS_BROADWELL(dev)) {
6324                 val = 0;
6325
6326                 switch (intel_crtc->config.pipe_bpp) {
6327                 case 18:
6328                         val |= PIPEMISC_DITHER_6_BPC;
6329                         break;
6330                 case 24:
6331                         val |= PIPEMISC_DITHER_8_BPC;
6332                         break;
6333                 case 30:
6334                         val |= PIPEMISC_DITHER_10_BPC;
6335                         break;
6336                 case 36:
6337                         val |= PIPEMISC_DITHER_12_BPC;
6338                         break;
6339                 default:
6340                         /* Case prevented by pipe_config_set_bpp. */
6341                         BUG();
6342                 }
6343
6344                 if (intel_crtc->config.dither)
6345                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6346
6347                 I915_WRITE(PIPEMISC(pipe), val);
6348         }
6349 }
6350
6351 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6352                                     intel_clock_t *clock,
6353                                     bool *has_reduced_clock,
6354                                     intel_clock_t *reduced_clock)
6355 {
6356         struct drm_device *dev = crtc->dev;
6357         struct drm_i915_private *dev_priv = dev->dev_private;
6358         struct intel_encoder *intel_encoder;
6359         int refclk;
6360         const intel_limit_t *limit;
6361         bool ret, is_lvds = false;
6362
6363         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6364                 switch (intel_encoder->type) {
6365                 case INTEL_OUTPUT_LVDS:
6366                         is_lvds = true;
6367                         break;
6368                 }
6369         }
6370
6371         refclk = ironlake_get_refclk(crtc);
6372
6373         /*
6374          * Returns a set of divisors for the desired target clock with the given
6375          * refclk, or FALSE.  The returned values represent the clock equation:
6376          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6377          */
6378         limit = intel_limit(crtc, refclk);
6379         ret = dev_priv->display.find_dpll(limit, crtc,
6380                                           to_intel_crtc(crtc)->config.port_clock,
6381                                           refclk, NULL, clock);
6382         if (!ret)
6383                 return false;
6384
6385         if (is_lvds && dev_priv->lvds_downclock_avail) {
6386                 /*
6387                  * Ensure we match the reduced clock's P to the target clock.
6388                  * If the clocks don't match, we can't switch the display clock
6389                  * by using the FP0/FP1. In such case we will disable the LVDS
6390                  * downclock feature.
6391                 */
6392                 *has_reduced_clock =
6393                         dev_priv->display.find_dpll(limit, crtc,
6394                                                     dev_priv->lvds_downclock,
6395                                                     refclk, clock,
6396                                                     reduced_clock);
6397         }
6398
6399         return true;
6400 }
6401
6402 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6403 {
6404         /*
6405          * Account for spread spectrum to avoid
6406          * oversubscribing the link. Max center spread
6407          * is 2.5%; use 5% for safety's sake.
6408          */
6409         u32 bps = target_clock * bpp * 21 / 20;
6410         return DIV_ROUND_UP(bps, link_bw * 8);
6411 }
6412
6413 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6414 {
6415         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6416 }
6417
6418 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6419                                       u32 *fp,
6420                                       intel_clock_t *reduced_clock, u32 *fp2)
6421 {
6422         struct drm_crtc *crtc = &intel_crtc->base;
6423         struct drm_device *dev = crtc->dev;
6424         struct drm_i915_private *dev_priv = dev->dev_private;
6425         struct intel_encoder *intel_encoder;
6426         uint32_t dpll;
6427         int factor, num_connectors = 0;
6428         bool is_lvds = false, is_sdvo = false;
6429
6430         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6431                 switch (intel_encoder->type) {
6432                 case INTEL_OUTPUT_LVDS:
6433                         is_lvds = true;
6434                         break;
6435                 case INTEL_OUTPUT_SDVO:
6436                 case INTEL_OUTPUT_HDMI:
6437                         is_sdvo = true;
6438                         break;
6439                 }
6440
6441                 num_connectors++;
6442         }
6443
6444         /* Enable autotuning of the PLL clock (if permissible) */
6445         factor = 21;
6446         if (is_lvds) {
6447                 if ((intel_panel_use_ssc(dev_priv) &&
6448                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
6449                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6450                         factor = 25;
6451         } else if (intel_crtc->config.sdvo_tv_clock)
6452                 factor = 20;
6453
6454         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6455                 *fp |= FP_CB_TUNE;
6456
6457         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6458                 *fp2 |= FP_CB_TUNE;
6459
6460         dpll = 0;
6461
6462         if (is_lvds)
6463                 dpll |= DPLLB_MODE_LVDS;
6464         else
6465                 dpll |= DPLLB_MODE_DAC_SERIAL;
6466
6467         dpll |= (intel_crtc->config.pixel_multiplier - 1)
6468                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6469
6470         if (is_sdvo)
6471                 dpll |= DPLL_SDVO_HIGH_SPEED;
6472         if (intel_crtc->config.has_dp_encoder)
6473                 dpll |= DPLL_SDVO_HIGH_SPEED;
6474
6475         /* compute bitmask from p1 value */
6476         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6477         /* also FPA1 */
6478         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6479
6480         switch (intel_crtc->config.dpll.p2) {
6481         case 5:
6482                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6483                 break;
6484         case 7:
6485                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6486                 break;
6487         case 10:
6488                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6489                 break;
6490         case 14:
6491                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6492                 break;
6493         }
6494
6495         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6496                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6497         else
6498                 dpll |= PLL_REF_INPUT_DREFCLK;
6499
6500         return dpll | DPLL_VCO_ENABLE;
6501 }
6502
6503 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
6504                                   int x, int y,
6505                                   struct drm_framebuffer *fb)
6506 {
6507         struct drm_device *dev = crtc->dev;
6508         struct drm_i915_private *dev_priv = dev->dev_private;
6509         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6510         int pipe = intel_crtc->pipe;
6511         int plane = intel_crtc->plane;
6512         int num_connectors = 0;
6513         intel_clock_t clock, reduced_clock;
6514         u32 dpll = 0, fp = 0, fp2 = 0;
6515         bool ok, has_reduced_clock = false;
6516         bool is_lvds = false;
6517         struct intel_encoder *encoder;
6518         struct intel_shared_dpll *pll;
6519         int ret;
6520
6521         for_each_encoder_on_crtc(dev, crtc, encoder) {
6522                 switch (encoder->type) {
6523                 case INTEL_OUTPUT_LVDS:
6524                         is_lvds = true;
6525                         break;
6526                 }
6527
6528                 num_connectors++;
6529         }
6530
6531         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6532              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6533
6534         ok = ironlake_compute_clocks(crtc, &clock,
6535                                      &has_reduced_clock, &reduced_clock);
6536         if (!ok && !intel_crtc->config.clock_set) {
6537                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6538                 return -EINVAL;
6539         }
6540         /* Compat-code for transition, will disappear. */
6541         if (!intel_crtc->config.clock_set) {
6542                 intel_crtc->config.dpll.n = clock.n;
6543                 intel_crtc->config.dpll.m1 = clock.m1;
6544                 intel_crtc->config.dpll.m2 = clock.m2;
6545                 intel_crtc->config.dpll.p1 = clock.p1;
6546                 intel_crtc->config.dpll.p2 = clock.p2;
6547         }
6548
6549         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6550         if (intel_crtc->config.has_pch_encoder) {
6551                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6552                 if (has_reduced_clock)
6553                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6554
6555                 dpll = ironlake_compute_dpll(intel_crtc,
6556                                              &fp, &reduced_clock,
6557                                              has_reduced_clock ? &fp2 : NULL);
6558
6559                 intel_crtc->config.dpll_hw_state.dpll = dpll;
6560                 intel_crtc->config.dpll_hw_state.fp0 = fp;
6561                 if (has_reduced_clock)
6562                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
6563                 else
6564                         intel_crtc->config.dpll_hw_state.fp1 = fp;
6565
6566                 pll = intel_get_shared_dpll(intel_crtc);
6567                 if (pll == NULL) {
6568                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6569                                          pipe_name(pipe));
6570                         return -EINVAL;
6571                 }
6572         } else
6573                 intel_put_shared_dpll(intel_crtc);
6574
6575         if (intel_crtc->config.has_dp_encoder)
6576                 intel_dp_set_m_n(intel_crtc);
6577
6578         if (is_lvds && has_reduced_clock && i915.powersave)
6579                 intel_crtc->lowfreq_avail = true;
6580         else
6581                 intel_crtc->lowfreq_avail = false;
6582
6583         intel_set_pipe_timings(intel_crtc);
6584
6585         if (intel_crtc->config.has_pch_encoder) {
6586                 intel_cpu_transcoder_set_m_n(intel_crtc,
6587                                              &intel_crtc->config.fdi_m_n);
6588         }
6589
6590         ironlake_set_pipeconf(crtc);
6591
6592         /* Set up the display plane register */
6593         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
6594         POSTING_READ(DSPCNTR(plane));
6595
6596         ret = intel_pipe_set_base(crtc, x, y, fb);
6597
6598         return ret;
6599 }
6600
6601 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6602                                          struct intel_link_m_n *m_n)
6603 {
6604         struct drm_device *dev = crtc->base.dev;
6605         struct drm_i915_private *dev_priv = dev->dev_private;
6606         enum pipe pipe = crtc->pipe;
6607
6608         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6609         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6610         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6611                 & ~TU_SIZE_MASK;
6612         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6613         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6614                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6615 }
6616
6617 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6618                                          enum transcoder transcoder,
6619                                          struct intel_link_m_n *m_n)
6620 {
6621         struct drm_device *dev = crtc->base.dev;
6622         struct drm_i915_private *dev_priv = dev->dev_private;
6623         enum pipe pipe = crtc->pipe;
6624
6625         if (INTEL_INFO(dev)->gen >= 5) {
6626                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6627                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6628                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6629                         & ~TU_SIZE_MASK;
6630                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6631                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6632                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6633         } else {
6634                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6635                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6636                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6637                         & ~TU_SIZE_MASK;
6638                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6639                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6640                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6641         }
6642 }
6643
6644 void intel_dp_get_m_n(struct intel_crtc *crtc,
6645                       struct intel_crtc_config *pipe_config)
6646 {
6647         if (crtc->config.has_pch_encoder)
6648                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6649         else
6650                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6651                                              &pipe_config->dp_m_n);
6652 }
6653
6654 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6655                                         struct intel_crtc_config *pipe_config)
6656 {
6657         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6658                                      &pipe_config->fdi_m_n);
6659 }
6660
6661 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6662                                      struct intel_crtc_config *pipe_config)
6663 {
6664         struct drm_device *dev = crtc->base.dev;
6665         struct drm_i915_private *dev_priv = dev->dev_private;
6666         uint32_t tmp;
6667
6668         tmp = I915_READ(PF_CTL(crtc->pipe));
6669
6670         if (tmp & PF_ENABLE) {
6671                 pipe_config->pch_pfit.enabled = true;
6672                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6673                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
6674
6675                 /* We currently do not free assignements of panel fitters on
6676                  * ivb/hsw (since we don't use the higher upscaling modes which
6677                  * differentiates them) so just WARN about this case for now. */
6678                 if (IS_GEN7(dev)) {
6679                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6680                                 PF_PIPE_SEL_IVB(crtc->pipe));
6681                 }
6682         }
6683 }
6684
6685 static void ironlake_get_plane_config(struct intel_crtc *crtc,
6686                                       struct intel_plane_config *plane_config)
6687 {
6688         struct drm_device *dev = crtc->base.dev;
6689         struct drm_i915_private *dev_priv = dev->dev_private;
6690         u32 val, base, offset;
6691         int pipe = crtc->pipe, plane = crtc->plane;
6692         int fourcc, pixel_format;
6693         int aligned_height;
6694
6695         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6696         if (!crtc->base.primary->fb) {
6697                 DRM_DEBUG_KMS("failed to alloc fb\n");
6698                 return;
6699         }
6700
6701         val = I915_READ(DSPCNTR(plane));
6702
6703         if (INTEL_INFO(dev)->gen >= 4)
6704                 if (val & DISPPLANE_TILED)
6705                         plane_config->tiled = true;
6706
6707         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6708         fourcc = intel_format_to_fourcc(pixel_format);
6709         crtc->base.primary->fb->pixel_format = fourcc;
6710         crtc->base.primary->fb->bits_per_pixel =
6711                 drm_format_plane_cpp(fourcc, 0) * 8;
6712
6713         base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6714         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6715                 offset = I915_READ(DSPOFFSET(plane));
6716         } else {
6717                 if (plane_config->tiled)
6718                         offset = I915_READ(DSPTILEOFF(plane));
6719                 else
6720                         offset = I915_READ(DSPLINOFF(plane));
6721         }
6722         plane_config->base = base;
6723
6724         val = I915_READ(PIPESRC(pipe));
6725         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6726         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6727
6728         val = I915_READ(DSPSTRIDE(pipe));
6729         crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
6730
6731         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6732                                             plane_config->tiled);
6733
6734         plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
6735                                    aligned_height, PAGE_SIZE);
6736
6737         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6738                       pipe, plane, crtc->base.primary->fb->width,
6739                       crtc->base.primary->fb->height,
6740                       crtc->base.primary->fb->bits_per_pixel, base,
6741                       crtc->base.primary->fb->pitches[0],
6742                       plane_config->size);
6743 }
6744
6745 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6746                                      struct intel_crtc_config *pipe_config)
6747 {
6748         struct drm_device *dev = crtc->base.dev;
6749         struct drm_i915_private *dev_priv = dev->dev_private;
6750         uint32_t tmp;
6751
6752         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6753         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6754
6755         tmp = I915_READ(PIPECONF(crtc->pipe));
6756         if (!(tmp & PIPECONF_ENABLE))
6757                 return false;
6758
6759         switch (tmp & PIPECONF_BPC_MASK) {
6760         case PIPECONF_6BPC:
6761                 pipe_config->pipe_bpp = 18;
6762                 break;
6763         case PIPECONF_8BPC:
6764                 pipe_config->pipe_bpp = 24;
6765                 break;
6766         case PIPECONF_10BPC:
6767                 pipe_config->pipe_bpp = 30;
6768                 break;
6769         case PIPECONF_12BPC:
6770                 pipe_config->pipe_bpp = 36;
6771                 break;
6772         default:
6773                 break;
6774         }
6775
6776         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
6777                 struct intel_shared_dpll *pll;
6778
6779                 pipe_config->has_pch_encoder = true;
6780
6781                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6782                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6783                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6784
6785                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6786
6787                 if (HAS_PCH_IBX(dev_priv->dev)) {
6788                         pipe_config->shared_dpll =
6789                                 (enum intel_dpll_id) crtc->pipe;
6790                 } else {
6791                         tmp = I915_READ(PCH_DPLL_SEL);
6792                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6793                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6794                         else
6795                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6796                 }
6797
6798                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6799
6800                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6801                                            &pipe_config->dpll_hw_state));
6802
6803                 tmp = pipe_config->dpll_hw_state.dpll;
6804                 pipe_config->pixel_multiplier =
6805                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6806                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6807
6808                 ironlake_pch_clock_get(crtc, pipe_config);
6809         } else {
6810                 pipe_config->pixel_multiplier = 1;
6811         }
6812
6813         intel_get_pipe_timings(crtc, pipe_config);
6814
6815         ironlake_get_pfit_config(crtc, pipe_config);
6816
6817         return true;
6818 }
6819
6820 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6821 {
6822         struct drm_device *dev = dev_priv->dev;
6823         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6824         struct intel_crtc *crtc;
6825
6826         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6827                 WARN(crtc->active, "CRTC for pipe %c enabled\n",
6828                      pipe_name(crtc->pipe));
6829
6830         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6831         WARN(plls->spll_refcount, "SPLL enabled\n");
6832         WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6833         WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6834         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6835         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6836              "CPU PWM1 enabled\n");
6837         WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6838              "CPU PWM2 enabled\n");
6839         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6840              "PCH PWM1 enabled\n");
6841         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6842              "Utility pin enabled\n");
6843         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6844
6845         /*
6846          * In theory we can still leave IRQs enabled, as long as only the HPD
6847          * interrupts remain enabled. We used to check for that, but since it's
6848          * gen-specific and since we only disable LCPLL after we fully disable
6849          * the interrupts, the check below should be enough.
6850          */
6851         WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n");
6852 }
6853
6854 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
6855 {
6856         struct drm_device *dev = dev_priv->dev;
6857
6858         if (IS_HASWELL(dev)) {
6859                 mutex_lock(&dev_priv->rps.hw_lock);
6860                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
6861                                             val))
6862                         DRM_ERROR("Failed to disable D_COMP\n");
6863                 mutex_unlock(&dev_priv->rps.hw_lock);
6864         } else {
6865                 I915_WRITE(D_COMP, val);
6866         }
6867         POSTING_READ(D_COMP);
6868 }
6869
6870 /*
6871  * This function implements pieces of two sequences from BSpec:
6872  * - Sequence for display software to disable LCPLL
6873  * - Sequence for display software to allow package C8+
6874  * The steps implemented here are just the steps that actually touch the LCPLL
6875  * register. Callers should take care of disabling all the display engine
6876  * functions, doing the mode unset, fixing interrupts, etc.
6877  */
6878 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6879                               bool switch_to_fclk, bool allow_power_down)
6880 {
6881         uint32_t val;
6882
6883         assert_can_disable_lcpll(dev_priv);
6884
6885         val = I915_READ(LCPLL_CTL);
6886
6887         if (switch_to_fclk) {
6888                 val |= LCPLL_CD_SOURCE_FCLK;
6889                 I915_WRITE(LCPLL_CTL, val);
6890
6891                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6892                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
6893                         DRM_ERROR("Switching to FCLK failed\n");
6894
6895                 val = I915_READ(LCPLL_CTL);
6896         }
6897
6898         val |= LCPLL_PLL_DISABLE;
6899         I915_WRITE(LCPLL_CTL, val);
6900         POSTING_READ(LCPLL_CTL);
6901
6902         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6903                 DRM_ERROR("LCPLL still locked\n");
6904
6905         val = I915_READ(D_COMP);
6906         val |= D_COMP_COMP_DISABLE;
6907         hsw_write_dcomp(dev_priv, val);
6908         ndelay(100);
6909
6910         if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6911                 DRM_ERROR("D_COMP RCOMP still in progress\n");
6912
6913         if (allow_power_down) {
6914                 val = I915_READ(LCPLL_CTL);
6915                 val |= LCPLL_POWER_DOWN_ALLOW;
6916                 I915_WRITE(LCPLL_CTL, val);
6917                 POSTING_READ(LCPLL_CTL);
6918         }
6919 }
6920
6921 /*
6922  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6923  * source.
6924  */
6925 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6926 {
6927         uint32_t val;
6928         unsigned long irqflags;
6929
6930         val = I915_READ(LCPLL_CTL);
6931
6932         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6933                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6934                 return;
6935
6936         /*
6937          * Make sure we're not on PC8 state before disabling PC8, otherwise
6938          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
6939          *
6940          * The other problem is that hsw_restore_lcpll() is called as part of
6941          * the runtime PM resume sequence, so we can't just call
6942          * gen6_gt_force_wake_get() because that function calls
6943          * intel_runtime_pm_get(), and we can't change the runtime PM refcount
6944          * while we are on the resume sequence. So to solve this problem we have
6945          * to call special forcewake code that doesn't touch runtime PM and
6946          * doesn't enable the forcewake delayed work.
6947          */
6948         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
6949         if (dev_priv->uncore.forcewake_count++ == 0)
6950                 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
6951         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
6952
6953         if (val & LCPLL_POWER_DOWN_ALLOW) {
6954                 val &= ~LCPLL_POWER_DOWN_ALLOW;
6955                 I915_WRITE(LCPLL_CTL, val);
6956                 POSTING_READ(LCPLL_CTL);
6957         }
6958
6959         val = I915_READ(D_COMP);
6960         val |= D_COMP_COMP_FORCE;
6961         val &= ~D_COMP_COMP_DISABLE;
6962         hsw_write_dcomp(dev_priv, val);
6963
6964         val = I915_READ(LCPLL_CTL);
6965         val &= ~LCPLL_PLL_DISABLE;
6966         I915_WRITE(LCPLL_CTL, val);
6967
6968         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6969                 DRM_ERROR("LCPLL not locked yet\n");
6970
6971         if (val & LCPLL_CD_SOURCE_FCLK) {
6972                 val = I915_READ(LCPLL_CTL);
6973                 val &= ~LCPLL_CD_SOURCE_FCLK;
6974                 I915_WRITE(LCPLL_CTL, val);
6975
6976                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6977                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6978                         DRM_ERROR("Switching back to LCPLL failed\n");
6979         }
6980
6981         /* See the big comment above. */
6982         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
6983         if (--dev_priv->uncore.forcewake_count == 0)
6984                 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
6985         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
6986 }
6987
6988 /*
6989  * Package states C8 and deeper are really deep PC states that can only be
6990  * reached when all the devices on the system allow it, so even if the graphics
6991  * device allows PC8+, it doesn't mean the system will actually get to these
6992  * states. Our driver only allows PC8+ when going into runtime PM.
6993  *
6994  * The requirements for PC8+ are that all the outputs are disabled, the power
6995  * well is disabled and most interrupts are disabled, and these are also
6996  * requirements for runtime PM. When these conditions are met, we manually do
6997  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
6998  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
6999  * hang the machine.
7000  *
7001  * When we really reach PC8 or deeper states (not just when we allow it) we lose
7002  * the state of some registers, so when we come back from PC8+ we need to
7003  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7004  * need to take care of the registers kept by RC6. Notice that this happens even
7005  * if we don't put the device in PCI D3 state (which is what currently happens
7006  * because of the runtime PM support).
7007  *
7008  * For more, read "Display Sequences for Package C8" on the hardware
7009  * documentation.
7010  */
7011 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7012 {
7013         struct drm_device *dev = dev_priv->dev;
7014         uint32_t val;
7015
7016         DRM_DEBUG_KMS("Enabling package C8+\n");
7017
7018         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7019                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7020                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7021                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7022         }
7023
7024         lpt_disable_clkout_dp(dev);
7025         hsw_disable_lcpll(dev_priv, true, true);
7026 }
7027
7028 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7029 {
7030         struct drm_device *dev = dev_priv->dev;
7031         uint32_t val;
7032
7033         DRM_DEBUG_KMS("Disabling package C8+\n");
7034
7035         hsw_restore_lcpll(dev_priv);
7036         lpt_init_pch_refclk(dev);
7037
7038         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7039                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7040                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7041                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7042         }
7043
7044         intel_prepare_ddi(dev);
7045 }
7046
7047 static void snb_modeset_global_resources(struct drm_device *dev)
7048 {
7049         modeset_update_crtc_power_domains(dev);
7050 }
7051
7052 static void haswell_modeset_global_resources(struct drm_device *dev)
7053 {
7054         modeset_update_crtc_power_domains(dev);
7055 }
7056
7057 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7058                                  int x, int y,
7059                                  struct drm_framebuffer *fb)
7060 {
7061         struct drm_device *dev = crtc->dev;
7062         struct drm_i915_private *dev_priv = dev->dev_private;
7063         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7064         int plane = intel_crtc->plane;
7065         int ret;
7066
7067         if (!intel_ddi_pll_select(intel_crtc))
7068                 return -EINVAL;
7069         intel_ddi_pll_enable(intel_crtc);
7070
7071         if (intel_crtc->config.has_dp_encoder)
7072                 intel_dp_set_m_n(intel_crtc);
7073
7074         intel_crtc->lowfreq_avail = false;
7075
7076         intel_set_pipe_timings(intel_crtc);
7077
7078         if (intel_crtc->config.has_pch_encoder) {
7079                 intel_cpu_transcoder_set_m_n(intel_crtc,
7080                                              &intel_crtc->config.fdi_m_n);
7081         }
7082
7083         haswell_set_pipeconf(crtc);
7084
7085         intel_set_pipe_csc(crtc);
7086
7087         /* Set up the display plane register */
7088         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
7089         POSTING_READ(DSPCNTR(plane));
7090
7091         ret = intel_pipe_set_base(crtc, x, y, fb);
7092
7093         return ret;
7094 }
7095
7096 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7097                                     struct intel_crtc_config *pipe_config)
7098 {
7099         struct drm_device *dev = crtc->base.dev;
7100         struct drm_i915_private *dev_priv = dev->dev_private;
7101         enum intel_display_power_domain pfit_domain;
7102         uint32_t tmp;
7103
7104         if (!intel_display_power_enabled(dev_priv,
7105                                          POWER_DOMAIN_PIPE(crtc->pipe)))
7106                 return false;
7107
7108         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7109         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7110
7111         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7112         if (tmp & TRANS_DDI_FUNC_ENABLE) {
7113                 enum pipe trans_edp_pipe;
7114                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7115                 default:
7116                         WARN(1, "unknown pipe linked to edp transcoder\n");
7117                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7118                 case TRANS_DDI_EDP_INPUT_A_ON:
7119                         trans_edp_pipe = PIPE_A;
7120                         break;
7121                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7122                         trans_edp_pipe = PIPE_B;
7123                         break;
7124                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7125                         trans_edp_pipe = PIPE_C;
7126                         break;
7127                 }
7128
7129                 if (trans_edp_pipe == crtc->pipe)
7130                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
7131         }
7132
7133         if (!intel_display_power_enabled(dev_priv,
7134                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7135                 return false;
7136
7137         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7138         if (!(tmp & PIPECONF_ENABLE))
7139                 return false;
7140
7141         /*
7142          * Haswell has only FDI/PCH transcoder A. It is which is connected to
7143          * DDI E. So just check whether this pipe is wired to DDI E and whether
7144          * the PCH transcoder is on.
7145          */
7146         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7147         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
7148             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7149                 pipe_config->has_pch_encoder = true;
7150
7151                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7152                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7153                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7154
7155                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7156         }
7157
7158         intel_get_pipe_timings(crtc, pipe_config);
7159
7160         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7161         if (intel_display_power_enabled(dev_priv, pfit_domain))
7162                 ironlake_get_pfit_config(crtc, pipe_config);
7163
7164         if (IS_HASWELL(dev))
7165                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7166                         (I915_READ(IPS_CTL) & IPS_ENABLE);
7167
7168         pipe_config->pixel_multiplier = 1;
7169
7170         return true;
7171 }
7172
7173 static int intel_crtc_mode_set(struct drm_crtc *crtc,
7174                                int x, int y,
7175                                struct drm_framebuffer *fb)
7176 {
7177         struct drm_device *dev = crtc->dev;
7178         struct drm_i915_private *dev_priv = dev->dev_private;
7179         struct intel_encoder *encoder;
7180         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7181         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
7182         int pipe = intel_crtc->pipe;
7183         int ret;
7184
7185         drm_vblank_pre_modeset(dev, pipe);
7186
7187         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
7188
7189         drm_vblank_post_modeset(dev, pipe);
7190
7191         if (ret != 0)
7192                 return ret;
7193
7194         for_each_encoder_on_crtc(dev, crtc, encoder) {
7195                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7196                         encoder->base.base.id,
7197                         drm_get_encoder_name(&encoder->base),
7198                         mode->base.id, mode->name);
7199
7200                 if (encoder->mode_set)
7201                         encoder->mode_set(encoder);
7202         }
7203
7204         return 0;
7205 }
7206
7207 static struct {
7208         int clock;
7209         u32 config;
7210 } hdmi_audio_clock[] = {
7211         { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7212         { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7213         { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7214         { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7215         { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7216         { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7217         { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7218         { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7219         { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7220         { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7221 };
7222
7223 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7224 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7225 {
7226         int i;
7227
7228         for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7229                 if (mode->clock == hdmi_audio_clock[i].clock)
7230                         break;
7231         }
7232
7233         if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7234                 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7235                 i = 1;
7236         }
7237
7238         DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7239                       hdmi_audio_clock[i].clock,
7240                       hdmi_audio_clock[i].config);
7241
7242         return hdmi_audio_clock[i].config;
7243 }
7244
7245 static bool intel_eld_uptodate(struct drm_connector *connector,
7246                                int reg_eldv, uint32_t bits_eldv,
7247                                int reg_elda, uint32_t bits_elda,
7248                                int reg_edid)
7249 {
7250         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7251         uint8_t *eld = connector->eld;
7252         uint32_t i;
7253
7254         i = I915_READ(reg_eldv);
7255         i &= bits_eldv;
7256
7257         if (!eld[0])
7258                 return !i;
7259
7260         if (!i)
7261                 return false;
7262
7263         i = I915_READ(reg_elda);
7264         i &= ~bits_elda;
7265         I915_WRITE(reg_elda, i);
7266
7267         for (i = 0; i < eld[2]; i++)
7268                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7269                         return false;
7270
7271         return true;
7272 }
7273
7274 static void g4x_write_eld(struct drm_connector *connector,
7275                           struct drm_crtc *crtc,
7276                           struct drm_display_mode *mode)
7277 {
7278         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7279         uint8_t *eld = connector->eld;
7280         uint32_t eldv;
7281         uint32_t len;
7282         uint32_t i;
7283
7284         i = I915_READ(G4X_AUD_VID_DID);
7285
7286         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7287                 eldv = G4X_ELDV_DEVCL_DEVBLC;
7288         else
7289                 eldv = G4X_ELDV_DEVCTG;
7290
7291         if (intel_eld_uptodate(connector,
7292                                G4X_AUD_CNTL_ST, eldv,
7293                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7294                                G4X_HDMIW_HDMIEDID))
7295                 return;
7296
7297         i = I915_READ(G4X_AUD_CNTL_ST);
7298         i &= ~(eldv | G4X_ELD_ADDR);
7299         len = (i >> 9) & 0x1f;          /* ELD buffer size */
7300         I915_WRITE(G4X_AUD_CNTL_ST, i);
7301
7302         if (!eld[0])
7303                 return;
7304
7305         len = min_t(uint8_t, eld[2], len);
7306         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7307         for (i = 0; i < len; i++)
7308                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7309
7310         i = I915_READ(G4X_AUD_CNTL_ST);
7311         i |= eldv;
7312         I915_WRITE(G4X_AUD_CNTL_ST, i);
7313 }
7314
7315 static void haswell_write_eld(struct drm_connector *connector,
7316                               struct drm_crtc *crtc,
7317                               struct drm_display_mode *mode)
7318 {
7319         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7320         uint8_t *eld = connector->eld;
7321         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7322         uint32_t eldv;
7323         uint32_t i;
7324         int len;
7325         int pipe = to_intel_crtc(crtc)->pipe;
7326         int tmp;
7327
7328         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7329         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7330         int aud_config = HSW_AUD_CFG(pipe);
7331         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7332
7333         /* Audio output enable */
7334         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7335         tmp = I915_READ(aud_cntrl_st2);
7336         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7337         I915_WRITE(aud_cntrl_st2, tmp);
7338         POSTING_READ(aud_cntrl_st2);
7339
7340         assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
7341
7342         /* Set ELD valid state */
7343         tmp = I915_READ(aud_cntrl_st2);
7344         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7345         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7346         I915_WRITE(aud_cntrl_st2, tmp);
7347         tmp = I915_READ(aud_cntrl_st2);
7348         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7349
7350         /* Enable HDMI mode */
7351         tmp = I915_READ(aud_config);
7352         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7353         /* clear N_programing_enable and N_value_index */
7354         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7355         I915_WRITE(aud_config, tmp);
7356
7357         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7358
7359         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7360         intel_crtc->eld_vld = true;
7361
7362         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7363                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7364                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7365                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7366         } else {
7367                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7368         }
7369
7370         if (intel_eld_uptodate(connector,
7371                                aud_cntrl_st2, eldv,
7372                                aud_cntl_st, IBX_ELD_ADDRESS,
7373                                hdmiw_hdmiedid))
7374                 return;
7375
7376         i = I915_READ(aud_cntrl_st2);
7377         i &= ~eldv;
7378         I915_WRITE(aud_cntrl_st2, i);
7379
7380         if (!eld[0])
7381                 return;
7382
7383         i = I915_READ(aud_cntl_st);
7384         i &= ~IBX_ELD_ADDRESS;
7385         I915_WRITE(aud_cntl_st, i);
7386         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
7387         DRM_DEBUG_DRIVER("port num:%d\n", i);
7388
7389         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7390         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7391         for (i = 0; i < len; i++)
7392                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7393
7394         i = I915_READ(aud_cntrl_st2);
7395         i |= eldv;
7396         I915_WRITE(aud_cntrl_st2, i);
7397
7398 }
7399
7400 static void ironlake_write_eld(struct drm_connector *connector,
7401                                struct drm_crtc *crtc,
7402                                struct drm_display_mode *mode)
7403 {
7404         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7405         uint8_t *eld = connector->eld;
7406         uint32_t eldv;
7407         uint32_t i;
7408         int len;
7409         int hdmiw_hdmiedid;
7410         int aud_config;
7411         int aud_cntl_st;
7412         int aud_cntrl_st2;
7413         int pipe = to_intel_crtc(crtc)->pipe;
7414
7415         if (HAS_PCH_IBX(connector->dev)) {
7416                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7417                 aud_config = IBX_AUD_CFG(pipe);
7418                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7419                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7420         } else if (IS_VALLEYVIEW(connector->dev)) {
7421                 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7422                 aud_config = VLV_AUD_CFG(pipe);
7423                 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7424                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7425         } else {
7426                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7427                 aud_config = CPT_AUD_CFG(pipe);
7428                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7429                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7430         }
7431
7432         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7433
7434         if (IS_VALLEYVIEW(connector->dev))  {
7435                 struct intel_encoder *intel_encoder;
7436                 struct intel_digital_port *intel_dig_port;
7437
7438                 intel_encoder = intel_attached_encoder(connector);
7439                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7440                 i = intel_dig_port->port;
7441         } else {
7442                 i = I915_READ(aud_cntl_st);
7443                 i = (i >> 29) & DIP_PORT_SEL_MASK;
7444                 /* DIP_Port_Select, 0x1 = PortB */
7445         }
7446
7447         if (!i) {
7448                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7449                 /* operate blindly on all ports */
7450                 eldv = IBX_ELD_VALIDB;
7451                 eldv |= IBX_ELD_VALIDB << 4;
7452                 eldv |= IBX_ELD_VALIDB << 8;
7453         } else {
7454                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7455                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7456         }
7457
7458         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7459                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7460                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7461                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7462         } else {
7463                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7464         }
7465
7466         if (intel_eld_uptodate(connector,
7467                                aud_cntrl_st2, eldv,
7468                                aud_cntl_st, IBX_ELD_ADDRESS,
7469                                hdmiw_hdmiedid))
7470                 return;
7471
7472         i = I915_READ(aud_cntrl_st2);
7473         i &= ~eldv;
7474         I915_WRITE(aud_cntrl_st2, i);
7475
7476         if (!eld[0])
7477                 return;
7478
7479         i = I915_READ(aud_cntl_st);
7480         i &= ~IBX_ELD_ADDRESS;
7481         I915_WRITE(aud_cntl_st, i);
7482
7483         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7484         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7485         for (i = 0; i < len; i++)
7486                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7487
7488         i = I915_READ(aud_cntrl_st2);
7489         i |= eldv;
7490         I915_WRITE(aud_cntrl_st2, i);
7491 }
7492
7493 void intel_write_eld(struct drm_encoder *encoder,
7494                      struct drm_display_mode *mode)
7495 {
7496         struct drm_crtc *crtc = encoder->crtc;
7497         struct drm_connector *connector;
7498         struct drm_device *dev = encoder->dev;
7499         struct drm_i915_private *dev_priv = dev->dev_private;
7500
7501         connector = drm_select_eld(encoder, mode);
7502         if (!connector)
7503                 return;
7504
7505         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7506                          connector->base.id,
7507                          drm_get_connector_name(connector),
7508                          connector->encoder->base.id,
7509                          drm_get_encoder_name(connector->encoder));
7510
7511         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7512
7513         if (dev_priv->display.write_eld)
7514                 dev_priv->display.write_eld(connector, crtc, mode);
7515 }
7516
7517 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7518 {
7519         struct drm_device *dev = crtc->dev;
7520         struct drm_i915_private *dev_priv = dev->dev_private;
7521         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7522         bool visible = base != 0;
7523         u32 cntl;
7524
7525         if (intel_crtc->cursor_visible == visible)
7526                 return;
7527
7528         cntl = I915_READ(_CURACNTR);
7529         if (visible) {
7530                 /* On these chipsets we can only modify the base whilst
7531                  * the cursor is disabled.
7532                  */
7533                 I915_WRITE(_CURABASE, base);
7534
7535                 cntl &= ~(CURSOR_FORMAT_MASK);
7536                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7537                 cntl |= CURSOR_ENABLE |
7538                         CURSOR_GAMMA_ENABLE |
7539                         CURSOR_FORMAT_ARGB;
7540         } else
7541                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
7542         I915_WRITE(_CURACNTR, cntl);
7543
7544         intel_crtc->cursor_visible = visible;
7545 }
7546
7547 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7548 {
7549         struct drm_device *dev = crtc->dev;
7550         struct drm_i915_private *dev_priv = dev->dev_private;
7551         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7552         int pipe = intel_crtc->pipe;
7553         bool visible = base != 0;
7554
7555         if (intel_crtc->cursor_visible != visible) {
7556                 int16_t width = intel_crtc->cursor_width;
7557                 uint32_t cntl = I915_READ(CURCNTR(pipe));
7558                 if (base) {
7559                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7560                         cntl |= MCURSOR_GAMMA_ENABLE;
7561
7562                         switch (width) {
7563                         case 64:
7564                                 cntl |= CURSOR_MODE_64_ARGB_AX;
7565                                 break;
7566                         case 128:
7567                                 cntl |= CURSOR_MODE_128_ARGB_AX;
7568                                 break;
7569                         case 256:
7570                                 cntl |= CURSOR_MODE_256_ARGB_AX;
7571                                 break;
7572                         default:
7573                                 WARN_ON(1);
7574                                 return;
7575                         }
7576                         cntl |= pipe << 28; /* Connect to correct pipe */
7577                 } else {
7578                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7579                         cntl |= CURSOR_MODE_DISABLE;
7580                 }
7581                 I915_WRITE(CURCNTR(pipe), cntl);
7582
7583                 intel_crtc->cursor_visible = visible;
7584         }
7585         /* and commit changes on next vblank */
7586         POSTING_READ(CURCNTR(pipe));
7587         I915_WRITE(CURBASE(pipe), base);
7588         POSTING_READ(CURBASE(pipe));
7589 }
7590
7591 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7592 {
7593         struct drm_device *dev = crtc->dev;
7594         struct drm_i915_private *dev_priv = dev->dev_private;
7595         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7596         int pipe = intel_crtc->pipe;
7597         bool visible = base != 0;
7598
7599         if (intel_crtc->cursor_visible != visible) {
7600                 int16_t width = intel_crtc->cursor_width;
7601                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7602                 if (base) {
7603                         cntl &= ~CURSOR_MODE;
7604                         cntl |= MCURSOR_GAMMA_ENABLE;
7605                         switch (width) {
7606                         case 64:
7607                                 cntl |= CURSOR_MODE_64_ARGB_AX;
7608                                 break;
7609                         case 128:
7610                                 cntl |= CURSOR_MODE_128_ARGB_AX;
7611                                 break;
7612                         case 256:
7613                                 cntl |= CURSOR_MODE_256_ARGB_AX;
7614                                 break;
7615                         default:
7616                                 WARN_ON(1);
7617                                 return;
7618                         }
7619                 } else {
7620                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7621                         cntl |= CURSOR_MODE_DISABLE;
7622                 }
7623                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7624                         cntl |= CURSOR_PIPE_CSC_ENABLE;
7625                         cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7626                 }
7627                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7628
7629                 intel_crtc->cursor_visible = visible;
7630         }
7631         /* and commit changes on next vblank */
7632         POSTING_READ(CURCNTR_IVB(pipe));
7633         I915_WRITE(CURBASE_IVB(pipe), base);
7634         POSTING_READ(CURBASE_IVB(pipe));
7635 }
7636
7637 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7638 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7639                                      bool on)
7640 {
7641         struct drm_device *dev = crtc->dev;
7642         struct drm_i915_private *dev_priv = dev->dev_private;
7643         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7644         int pipe = intel_crtc->pipe;
7645         int x = intel_crtc->cursor_x;
7646         int y = intel_crtc->cursor_y;
7647         u32 base = 0, pos = 0;
7648         bool visible;
7649
7650         if (on)
7651                 base = intel_crtc->cursor_addr;
7652
7653         if (x >= intel_crtc->config.pipe_src_w)
7654                 base = 0;
7655
7656         if (y >= intel_crtc->config.pipe_src_h)
7657                 base = 0;
7658
7659         if (x < 0) {
7660                 if (x + intel_crtc->cursor_width <= 0)
7661                         base = 0;
7662
7663                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7664                 x = -x;
7665         }
7666         pos |= x << CURSOR_X_SHIFT;
7667
7668         if (y < 0) {
7669                 if (y + intel_crtc->cursor_height <= 0)
7670                         base = 0;
7671
7672                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7673                 y = -y;
7674         }
7675         pos |= y << CURSOR_Y_SHIFT;
7676
7677         visible = base != 0;
7678         if (!visible && !intel_crtc->cursor_visible)
7679                 return;
7680
7681         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7682                 I915_WRITE(CURPOS_IVB(pipe), pos);
7683                 ivb_update_cursor(crtc, base);
7684         } else {
7685                 I915_WRITE(CURPOS(pipe), pos);
7686                 if (IS_845G(dev) || IS_I865G(dev))
7687                         i845_update_cursor(crtc, base);
7688                 else
7689                         i9xx_update_cursor(crtc, base);
7690         }
7691 }
7692
7693 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
7694                                  struct drm_file *file,
7695                                  uint32_t handle,
7696                                  uint32_t width, uint32_t height)
7697 {
7698         struct drm_device *dev = crtc->dev;
7699         struct drm_i915_private *dev_priv = dev->dev_private;
7700         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7701         struct drm_i915_gem_object *obj;
7702         unsigned old_width;
7703         uint32_t addr;
7704         int ret;
7705
7706         /* if we want to turn off the cursor ignore width and height */
7707         if (!handle) {
7708                 DRM_DEBUG_KMS("cursor off\n");
7709                 addr = 0;
7710                 obj = NULL;
7711                 mutex_lock(&dev->struct_mutex);
7712                 goto finish;
7713         }
7714
7715         /* Check for which cursor types we support */
7716         if (!((width == 64 && height == 64) ||
7717                         (width == 128 && height == 128 && !IS_GEN2(dev)) ||
7718                         (width == 256 && height == 256 && !IS_GEN2(dev)))) {
7719                 DRM_DEBUG("Cursor dimension not supported\n");
7720                 return -EINVAL;
7721         }
7722
7723         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
7724         if (&obj->base == NULL)
7725                 return -ENOENT;
7726
7727         if (obj->base.size < width * height * 4) {
7728                 DRM_DEBUG_KMS("buffer is to small\n");
7729                 ret = -ENOMEM;
7730                 goto fail;
7731         }
7732
7733         /* we only need to pin inside GTT if cursor is non-phy */
7734         mutex_lock(&dev->struct_mutex);
7735         if (!INTEL_INFO(dev)->cursor_needs_physical) {
7736                 unsigned alignment;
7737
7738                 if (obj->tiling_mode) {
7739                         DRM_DEBUG_KMS("cursor cannot be tiled\n");
7740                         ret = -EINVAL;
7741                         goto fail_locked;
7742                 }
7743
7744                 /* Note that the w/a also requires 2 PTE of padding following
7745                  * the bo. We currently fill all unused PTE with the shadow
7746                  * page and so we should always have valid PTE following the
7747                  * cursor preventing the VT-d warning.
7748                  */
7749                 alignment = 0;
7750                 if (need_vtd_wa(dev))
7751                         alignment = 64*1024;
7752
7753                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
7754                 if (ret) {
7755                         DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
7756                         goto fail_locked;
7757                 }
7758
7759                 ret = i915_gem_object_put_fence(obj);
7760                 if (ret) {
7761                         DRM_DEBUG_KMS("failed to release fence for cursor");
7762                         goto fail_unpin;
7763                 }
7764
7765                 addr = i915_gem_obj_ggtt_offset(obj);
7766         } else {
7767                 int align = IS_I830(dev) ? 16 * 1024 : 256;
7768                 ret = i915_gem_attach_phys_object(dev, obj,
7769                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7770                                                   align);
7771                 if (ret) {
7772                         DRM_DEBUG_KMS("failed to attach phys object\n");
7773                         goto fail_locked;
7774                 }
7775                 addr = obj->phys_obj->handle->busaddr;
7776         }
7777
7778         if (IS_GEN2(dev))
7779                 I915_WRITE(CURSIZE, (height << 12) | width);
7780
7781  finish:
7782         if (intel_crtc->cursor_bo) {
7783                 if (INTEL_INFO(dev)->cursor_needs_physical) {
7784                         if (intel_crtc->cursor_bo != obj)
7785                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7786                 } else
7787                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
7788                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
7789         }
7790
7791         mutex_unlock(&dev->struct_mutex);
7792
7793         old_width = intel_crtc->cursor_width;
7794
7795         intel_crtc->cursor_addr = addr;
7796         intel_crtc->cursor_bo = obj;
7797         intel_crtc->cursor_width = width;
7798         intel_crtc->cursor_height = height;
7799
7800         if (intel_crtc->active) {
7801                 if (old_width != width)
7802                         intel_update_watermarks(crtc);
7803                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7804         }
7805
7806         return 0;
7807 fail_unpin:
7808         i915_gem_object_unpin_from_display_plane(obj);
7809 fail_locked:
7810         mutex_unlock(&dev->struct_mutex);
7811 fail:
7812         drm_gem_object_unreference_unlocked(&obj->base);
7813         return ret;
7814 }
7815
7816 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7817 {
7818         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7819
7820         intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
7821         intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
7822
7823         if (intel_crtc->active)
7824                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7825
7826         return 0;
7827 }
7828
7829 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7830                                  u16 *blue, uint32_t start, uint32_t size)
7831 {
7832         int end = (start + size > 256) ? 256 : start + size, i;
7833         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7834
7835         for (i = start; i < end; i++) {
7836                 intel_crtc->lut_r[i] = red[i] >> 8;
7837                 intel_crtc->lut_g[i] = green[i] >> 8;
7838                 intel_crtc->lut_b[i] = blue[i] >> 8;
7839         }
7840
7841         intel_crtc_load_lut(crtc);
7842 }
7843
7844 /* VESA 640x480x72Hz mode to set on the pipe */
7845 static struct drm_display_mode load_detect_mode = {
7846         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7847                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7848 };
7849
7850 struct drm_framebuffer *
7851 __intel_framebuffer_create(struct drm_device *dev,
7852                            struct drm_mode_fb_cmd2 *mode_cmd,
7853                            struct drm_i915_gem_object *obj)
7854 {
7855         struct intel_framebuffer *intel_fb;
7856         int ret;
7857
7858         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7859         if (!intel_fb) {
7860                 drm_gem_object_unreference_unlocked(&obj->base);
7861                 return ERR_PTR(-ENOMEM);
7862         }
7863
7864         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7865         if (ret)
7866                 goto err;
7867
7868         return &intel_fb->base;
7869 err:
7870         drm_gem_object_unreference_unlocked(&obj->base);
7871         kfree(intel_fb);
7872
7873         return ERR_PTR(ret);
7874 }
7875
7876 static struct drm_framebuffer *
7877 intel_framebuffer_create(struct drm_device *dev,
7878                          struct drm_mode_fb_cmd2 *mode_cmd,
7879                          struct drm_i915_gem_object *obj)
7880 {
7881         struct drm_framebuffer *fb;
7882         int ret;
7883
7884         ret = i915_mutex_lock_interruptible(dev);
7885         if (ret)
7886                 return ERR_PTR(ret);
7887         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
7888         mutex_unlock(&dev->struct_mutex);
7889
7890         return fb;
7891 }
7892
7893 static u32
7894 intel_framebuffer_pitch_for_width(int width, int bpp)
7895 {
7896         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7897         return ALIGN(pitch, 64);
7898 }
7899
7900 static u32
7901 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7902 {
7903         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7904         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7905 }
7906
7907 static struct drm_framebuffer *
7908 intel_framebuffer_create_for_mode(struct drm_device *dev,
7909                                   struct drm_display_mode *mode,
7910                                   int depth, int bpp)
7911 {
7912         struct drm_i915_gem_object *obj;
7913         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
7914
7915         obj = i915_gem_alloc_object(dev,
7916                                     intel_framebuffer_size_for_mode(mode, bpp));
7917         if (obj == NULL)
7918                 return ERR_PTR(-ENOMEM);
7919
7920         mode_cmd.width = mode->hdisplay;
7921         mode_cmd.height = mode->vdisplay;
7922         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7923                                                                 bpp);
7924         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7925
7926         return intel_framebuffer_create(dev, &mode_cmd, obj);
7927 }
7928
7929 static struct drm_framebuffer *
7930 mode_fits_in_fbdev(struct drm_device *dev,
7931                    struct drm_display_mode *mode)
7932 {
7933 #ifdef CONFIG_DRM_I915_FBDEV
7934         struct drm_i915_private *dev_priv = dev->dev_private;
7935         struct drm_i915_gem_object *obj;
7936         struct drm_framebuffer *fb;
7937
7938         if (!dev_priv->fbdev)
7939                 return NULL;
7940
7941         if (!dev_priv->fbdev->fb)
7942                 return NULL;
7943
7944         obj = dev_priv->fbdev->fb->obj;
7945         BUG_ON(!obj);
7946
7947         fb = &dev_priv->fbdev->fb->base;
7948         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7949                                                                fb->bits_per_pixel))
7950                 return NULL;
7951
7952         if (obj->base.size < mode->vdisplay * fb->pitches[0])
7953                 return NULL;
7954
7955         return fb;
7956 #else
7957         return NULL;
7958 #endif
7959 }
7960
7961 bool intel_get_load_detect_pipe(struct drm_connector *connector,
7962                                 struct drm_display_mode *mode,
7963                                 struct intel_load_detect_pipe *old)
7964 {
7965         struct intel_crtc *intel_crtc;
7966         struct intel_encoder *intel_encoder =
7967                 intel_attached_encoder(connector);
7968         struct drm_crtc *possible_crtc;
7969         struct drm_encoder *encoder = &intel_encoder->base;
7970         struct drm_crtc *crtc = NULL;
7971         struct drm_device *dev = encoder->dev;
7972         struct drm_framebuffer *fb;
7973         int i = -1;
7974
7975         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7976                       connector->base.id, drm_get_connector_name(connector),
7977                       encoder->base.id, drm_get_encoder_name(encoder));
7978
7979         /*
7980          * Algorithm gets a little messy:
7981          *
7982          *   - if the connector already has an assigned crtc, use it (but make
7983          *     sure it's on first)
7984          *
7985          *   - try to find the first unused crtc that can drive this connector,
7986          *     and use that if we find one
7987          */
7988
7989         /* See if we already have a CRTC for this connector */
7990         if (encoder->crtc) {
7991                 crtc = encoder->crtc;
7992
7993                 mutex_lock(&crtc->mutex);
7994
7995                 old->dpms_mode = connector->dpms;
7996                 old->load_detect_temp = false;
7997
7998                 /* Make sure the crtc and connector are running */
7999                 if (connector->dpms != DRM_MODE_DPMS_ON)
8000                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8001
8002                 return true;
8003         }
8004
8005         /* Find an unused one (if possible) */
8006         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
8007                 i++;
8008                 if (!(encoder->possible_crtcs & (1 << i)))
8009                         continue;
8010                 if (!possible_crtc->enabled) {
8011                         crtc = possible_crtc;
8012                         break;
8013                 }
8014         }
8015
8016         /*
8017          * If we didn't find an unused CRTC, don't use any.
8018          */
8019         if (!crtc) {
8020                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8021                 return false;
8022         }
8023
8024         mutex_lock(&crtc->mutex);
8025         intel_encoder->new_crtc = to_intel_crtc(crtc);
8026         to_intel_connector(connector)->new_encoder = intel_encoder;
8027
8028         intel_crtc = to_intel_crtc(crtc);
8029         intel_crtc->new_enabled = true;
8030         intel_crtc->new_config = &intel_crtc->config;
8031         old->dpms_mode = connector->dpms;
8032         old->load_detect_temp = true;
8033         old->release_fb = NULL;
8034
8035         if (!mode)
8036                 mode = &load_detect_mode;
8037
8038         /* We need a framebuffer large enough to accommodate all accesses
8039          * that the plane may generate whilst we perform load detection.
8040          * We can not rely on the fbcon either being present (we get called
8041          * during its initialisation to detect all boot displays, or it may
8042          * not even exist) or that it is large enough to satisfy the
8043          * requested mode.
8044          */
8045         fb = mode_fits_in_fbdev(dev, mode);
8046         if (fb == NULL) {
8047                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8048                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8049                 old->release_fb = fb;
8050         } else
8051                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8052         if (IS_ERR(fb)) {
8053                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8054                 goto fail;
8055         }
8056
8057         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8058                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8059                 if (old->release_fb)
8060                         old->release_fb->funcs->destroy(old->release_fb);
8061                 goto fail;
8062         }
8063
8064         /* let the connector get through one full cycle before testing */
8065         intel_wait_for_vblank(dev, intel_crtc->pipe);
8066         return true;
8067
8068  fail:
8069         intel_crtc->new_enabled = crtc->enabled;
8070         if (intel_crtc->new_enabled)
8071                 intel_crtc->new_config = &intel_crtc->config;
8072         else
8073                 intel_crtc->new_config = NULL;
8074         mutex_unlock(&crtc->mutex);
8075         return false;
8076 }
8077
8078 void intel_release_load_detect_pipe(struct drm_connector *connector,
8079                                     struct intel_load_detect_pipe *old)
8080 {
8081         struct intel_encoder *intel_encoder =
8082                 intel_attached_encoder(connector);
8083         struct drm_encoder *encoder = &intel_encoder->base;
8084         struct drm_crtc *crtc = encoder->crtc;
8085         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8086
8087         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8088                       connector->base.id, drm_get_connector_name(connector),
8089                       encoder->base.id, drm_get_encoder_name(encoder));
8090
8091         if (old->load_detect_temp) {
8092                 to_intel_connector(connector)->new_encoder = NULL;
8093                 intel_encoder->new_crtc = NULL;
8094                 intel_crtc->new_enabled = false;
8095                 intel_crtc->new_config = NULL;
8096                 intel_set_mode(crtc, NULL, 0, 0, NULL);
8097
8098                 if (old->release_fb) {
8099                         drm_framebuffer_unregister_private(old->release_fb);
8100                         drm_framebuffer_unreference(old->release_fb);
8101                 }
8102
8103                 mutex_unlock(&crtc->mutex);
8104                 return;
8105         }
8106
8107         /* Switch crtc and encoder back off if necessary */
8108         if (old->dpms_mode != DRM_MODE_DPMS_ON)
8109                 connector->funcs->dpms(connector, old->dpms_mode);
8110
8111         mutex_unlock(&crtc->mutex);
8112 }
8113
8114 static int i9xx_pll_refclk(struct drm_device *dev,
8115                            const struct intel_crtc_config *pipe_config)
8116 {
8117         struct drm_i915_private *dev_priv = dev->dev_private;
8118         u32 dpll = pipe_config->dpll_hw_state.dpll;
8119
8120         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8121                 return dev_priv->vbt.lvds_ssc_freq;
8122         else if (HAS_PCH_SPLIT(dev))
8123                 return 120000;
8124         else if (!IS_GEN2(dev))
8125                 return 96000;
8126         else
8127                 return 48000;
8128 }
8129
8130 /* Returns the clock of the currently programmed mode of the given pipe. */
8131 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8132                                 struct intel_crtc_config *pipe_config)
8133 {
8134         struct drm_device *dev = crtc->base.dev;
8135         struct drm_i915_private *dev_priv = dev->dev_private;
8136         int pipe = pipe_config->cpu_transcoder;
8137         u32 dpll = pipe_config->dpll_hw_state.dpll;
8138         u32 fp;
8139         intel_clock_t clock;
8140         int refclk = i9xx_pll_refclk(dev, pipe_config);
8141
8142         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8143                 fp = pipe_config->dpll_hw_state.fp0;
8144         else
8145                 fp = pipe_config->dpll_hw_state.fp1;
8146
8147         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8148         if (IS_PINEVIEW(dev)) {
8149                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8150                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8151         } else {
8152                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8153                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8154         }
8155
8156         if (!IS_GEN2(dev)) {
8157                 if (IS_PINEVIEW(dev))
8158                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8159                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8160                 else
8161                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8162                                DPLL_FPA01_P1_POST_DIV_SHIFT);
8163
8164                 switch (dpll & DPLL_MODE_MASK) {
8165                 case DPLLB_MODE_DAC_SERIAL:
8166                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8167                                 5 : 10;
8168                         break;
8169                 case DPLLB_MODE_LVDS:
8170                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8171                                 7 : 14;
8172                         break;
8173                 default:
8174                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8175                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
8176                         return;
8177                 }
8178
8179                 if (IS_PINEVIEW(dev))
8180                         pineview_clock(refclk, &clock);
8181                 else
8182                         i9xx_clock(refclk, &clock);
8183         } else {
8184                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8185                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8186
8187                 if (is_lvds) {
8188                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8189                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
8190
8191                         if (lvds & LVDS_CLKB_POWER_UP)
8192                                 clock.p2 = 7;
8193                         else
8194                                 clock.p2 = 14;
8195                 } else {
8196                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
8197                                 clock.p1 = 2;
8198                         else {
8199                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8200                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8201                         }
8202                         if (dpll & PLL_P2_DIVIDE_BY_4)
8203                                 clock.p2 = 4;
8204                         else
8205                                 clock.p2 = 2;
8206                 }
8207
8208                 i9xx_clock(refclk, &clock);
8209         }
8210
8211         /*
8212          * This value includes pixel_multiplier. We will use
8213          * port_clock to compute adjusted_mode.crtc_clock in the
8214          * encoder's get_config() function.
8215          */
8216         pipe_config->port_clock = clock.dot;
8217 }
8218
8219 int intel_dotclock_calculate(int link_freq,
8220                              const struct intel_link_m_n *m_n)
8221 {
8222         /*
8223          * The calculation for the data clock is:
8224          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8225          * But we want to avoid losing precison if possible, so:
8226          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8227          *
8228          * and the link clock is simpler:
8229          * link_clock = (m * link_clock) / n
8230          */
8231
8232         if (!m_n->link_n)
8233                 return 0;
8234
8235         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8236 }
8237
8238 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8239                                    struct intel_crtc_config *pipe_config)
8240 {
8241         struct drm_device *dev = crtc->base.dev;
8242
8243         /* read out port_clock from the DPLL */
8244         i9xx_crtc_clock_get(crtc, pipe_config);
8245
8246         /*
8247          * This value does not include pixel_multiplier.
8248          * We will check that port_clock and adjusted_mode.crtc_clock
8249          * agree once we know their relationship in the encoder's
8250          * get_config() function.
8251          */
8252         pipe_config->adjusted_mode.crtc_clock =
8253                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8254                                          &pipe_config->fdi_m_n);
8255 }
8256
8257 /** Returns the currently programmed mode of the given pipe. */
8258 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8259                                              struct drm_crtc *crtc)
8260 {
8261         struct drm_i915_private *dev_priv = dev->dev_private;
8262         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8263         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8264         struct drm_display_mode *mode;
8265         struct intel_crtc_config pipe_config;
8266         int htot = I915_READ(HTOTAL(cpu_transcoder));
8267         int hsync = I915_READ(HSYNC(cpu_transcoder));
8268         int vtot = I915_READ(VTOTAL(cpu_transcoder));
8269         int vsync = I915_READ(VSYNC(cpu_transcoder));
8270         enum pipe pipe = intel_crtc->pipe;
8271
8272         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8273         if (!mode)
8274                 return NULL;
8275
8276         /*
8277          * Construct a pipe_config sufficient for getting the clock info
8278          * back out of crtc_clock_get.
8279          *
8280          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8281          * to use a real value here instead.
8282          */
8283         pipe_config.cpu_transcoder = (enum transcoder) pipe;
8284         pipe_config.pixel_multiplier = 1;
8285         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8286         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8287         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8288         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8289
8290         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8291         mode->hdisplay = (htot & 0xffff) + 1;
8292         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8293         mode->hsync_start = (hsync & 0xffff) + 1;
8294         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8295         mode->vdisplay = (vtot & 0xffff) + 1;
8296         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8297         mode->vsync_start = (vsync & 0xffff) + 1;
8298         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8299
8300         drm_mode_set_name(mode);
8301
8302         return mode;
8303 }
8304
8305 static void intel_increase_pllclock(struct drm_crtc *crtc)
8306 {
8307         struct drm_device *dev = crtc->dev;
8308         struct drm_i915_private *dev_priv = dev->dev_private;
8309         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8310         int pipe = intel_crtc->pipe;
8311         int dpll_reg = DPLL(pipe);
8312         int dpll;
8313
8314         if (HAS_PCH_SPLIT(dev))
8315                 return;
8316
8317         if (!dev_priv->lvds_downclock_avail)
8318                 return;
8319
8320         dpll = I915_READ(dpll_reg);
8321         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8322                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8323
8324                 assert_panel_unlocked(dev_priv, pipe);
8325
8326                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8327                 I915_WRITE(dpll_reg, dpll);
8328                 intel_wait_for_vblank(dev, pipe);
8329
8330                 dpll = I915_READ(dpll_reg);
8331                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8332                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8333         }
8334 }
8335
8336 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8337 {
8338         struct drm_device *dev = crtc->dev;
8339         struct drm_i915_private *dev_priv = dev->dev_private;
8340         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8341
8342         if (HAS_PCH_SPLIT(dev))
8343                 return;
8344
8345         if (!dev_priv->lvds_downclock_avail)
8346                 return;
8347
8348         /*
8349          * Since this is called by a timer, we should never get here in
8350          * the manual case.
8351          */
8352         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8353                 int pipe = intel_crtc->pipe;
8354                 int dpll_reg = DPLL(pipe);
8355                 int dpll;
8356
8357                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8358
8359                 assert_panel_unlocked(dev_priv, pipe);
8360
8361                 dpll = I915_READ(dpll_reg);
8362                 dpll |= DISPLAY_RATE_SELECT_FPA1;
8363                 I915_WRITE(dpll_reg, dpll);
8364                 intel_wait_for_vblank(dev, pipe);
8365                 dpll = I915_READ(dpll_reg);
8366                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8367                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8368         }
8369
8370 }
8371
8372 void intel_mark_busy(struct drm_device *dev)
8373 {
8374         struct drm_i915_private *dev_priv = dev->dev_private;
8375
8376         if (dev_priv->mm.busy)
8377                 return;
8378
8379         intel_runtime_pm_get(dev_priv);
8380         i915_update_gfx_val(dev_priv);
8381         dev_priv->mm.busy = true;
8382 }
8383
8384 void intel_mark_idle(struct drm_device *dev)
8385 {
8386         struct drm_i915_private *dev_priv = dev->dev_private;
8387         struct drm_crtc *crtc;
8388
8389         if (!dev_priv->mm.busy)
8390                 return;
8391
8392         dev_priv->mm.busy = false;
8393
8394         if (!i915.powersave)
8395                 goto out;
8396
8397         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8398                 if (!crtc->primary->fb)
8399                         continue;
8400
8401                 intel_decrease_pllclock(crtc);
8402         }
8403
8404         if (INTEL_INFO(dev)->gen >= 6)
8405                 gen6_rps_idle(dev->dev_private);
8406
8407 out:
8408         intel_runtime_pm_put(dev_priv);
8409 }
8410
8411 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
8412                         struct intel_ring_buffer *ring)
8413 {
8414         struct drm_device *dev = obj->base.dev;
8415         struct drm_crtc *crtc;
8416
8417         if (!i915.powersave)
8418                 return;
8419
8420         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8421                 if (!crtc->primary->fb)
8422                         continue;
8423
8424                 if (to_intel_framebuffer(crtc->primary->fb)->obj != obj)
8425                         continue;
8426
8427                 intel_increase_pllclock(crtc);
8428                 if (ring && intel_fbc_enabled(dev))
8429                         ring->fbc_dirty = true;
8430         }
8431 }
8432
8433 static void intel_crtc_destroy(struct drm_crtc *crtc)
8434 {
8435         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8436         struct drm_device *dev = crtc->dev;
8437         struct intel_unpin_work *work;
8438         unsigned long flags;
8439
8440         spin_lock_irqsave(&dev->event_lock, flags);
8441         work = intel_crtc->unpin_work;
8442         intel_crtc->unpin_work = NULL;
8443         spin_unlock_irqrestore(&dev->event_lock, flags);
8444
8445         if (work) {
8446                 cancel_work_sync(&work->work);
8447                 kfree(work);
8448         }
8449
8450         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
8451
8452         drm_crtc_cleanup(crtc);
8453
8454         kfree(intel_crtc);
8455 }
8456
8457 static void intel_unpin_work_fn(struct work_struct *__work)
8458 {
8459         struct intel_unpin_work *work =
8460                 container_of(__work, struct intel_unpin_work, work);
8461         struct drm_device *dev = work->crtc->dev;
8462
8463         mutex_lock(&dev->struct_mutex);
8464         intel_unpin_fb_obj(work->old_fb_obj);
8465         drm_gem_object_unreference(&work->pending_flip_obj->base);
8466         drm_gem_object_unreference(&work->old_fb_obj->base);
8467
8468         intel_update_fbc(dev);
8469         mutex_unlock(&dev->struct_mutex);
8470
8471         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8472         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8473
8474         kfree(work);
8475 }
8476
8477 static void do_intel_finish_page_flip(struct drm_device *dev,
8478                                       struct drm_crtc *crtc)
8479 {
8480         struct drm_i915_private *dev_priv = dev->dev_private;
8481         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8482         struct intel_unpin_work *work;
8483         unsigned long flags;
8484
8485         /* Ignore early vblank irqs */
8486         if (intel_crtc == NULL)
8487                 return;
8488
8489         spin_lock_irqsave(&dev->event_lock, flags);
8490         work = intel_crtc->unpin_work;
8491
8492         /* Ensure we don't miss a work->pending update ... */
8493         smp_rmb();
8494
8495         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8496                 spin_unlock_irqrestore(&dev->event_lock, flags);
8497                 return;
8498         }
8499
8500         /* and that the unpin work is consistent wrt ->pending. */
8501         smp_rmb();
8502
8503         intel_crtc->unpin_work = NULL;
8504
8505         if (work->event)
8506                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
8507
8508         drm_vblank_put(dev, intel_crtc->pipe);
8509
8510         spin_unlock_irqrestore(&dev->event_lock, flags);
8511
8512         wake_up_all(&dev_priv->pending_flip_queue);
8513
8514         queue_work(dev_priv->wq, &work->work);
8515
8516         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
8517 }
8518
8519 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8520 {
8521         struct drm_i915_private *dev_priv = dev->dev_private;
8522         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8523
8524         do_intel_finish_page_flip(dev, crtc);
8525 }
8526
8527 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8528 {
8529         struct drm_i915_private *dev_priv = dev->dev_private;
8530         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8531
8532         do_intel_finish_page_flip(dev, crtc);
8533 }
8534
8535 void intel_prepare_page_flip(struct drm_device *dev, int plane)
8536 {
8537         struct drm_i915_private *dev_priv = dev->dev_private;
8538         struct intel_crtc *intel_crtc =
8539                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8540         unsigned long flags;
8541
8542         /* NB: An MMIO update of the plane base pointer will also
8543          * generate a page-flip completion irq, i.e. every modeset
8544          * is also accompanied by a spurious intel_prepare_page_flip().
8545          */
8546         spin_lock_irqsave(&dev->event_lock, flags);
8547         if (intel_crtc->unpin_work)
8548                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
8549         spin_unlock_irqrestore(&dev->event_lock, flags);
8550 }
8551
8552 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8553 {
8554         /* Ensure that the work item is consistent when activating it ... */
8555         smp_wmb();
8556         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8557         /* and that it is marked active as soon as the irq could fire. */
8558         smp_wmb();
8559 }
8560
8561 static int intel_gen2_queue_flip(struct drm_device *dev,
8562                                  struct drm_crtc *crtc,
8563                                  struct drm_framebuffer *fb,
8564                                  struct drm_i915_gem_object *obj,
8565                                  uint32_t flags)
8566 {
8567         struct drm_i915_private *dev_priv = dev->dev_private;
8568         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8569         u32 flip_mask;
8570         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8571         int ret;
8572
8573         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8574         if (ret)
8575                 goto err;
8576
8577         ret = intel_ring_begin(ring, 6);
8578         if (ret)
8579                 goto err_unpin;
8580
8581         /* Can't queue multiple flips, so wait for the previous
8582          * one to finish before executing the next.
8583          */
8584         if (intel_crtc->plane)
8585                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8586         else
8587                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8588         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8589         intel_ring_emit(ring, MI_NOOP);
8590         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8591                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8592         intel_ring_emit(ring, fb->pitches[0]);
8593         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8594         intel_ring_emit(ring, 0); /* aux display base address, unused */
8595
8596         intel_mark_page_flip_active(intel_crtc);
8597         __intel_ring_advance(ring);
8598         return 0;
8599
8600 err_unpin:
8601         intel_unpin_fb_obj(obj);
8602 err:
8603         return ret;
8604 }
8605
8606 static int intel_gen3_queue_flip(struct drm_device *dev,
8607                                  struct drm_crtc *crtc,
8608                                  struct drm_framebuffer *fb,
8609                                  struct drm_i915_gem_object *obj,
8610                                  uint32_t flags)
8611 {
8612         struct drm_i915_private *dev_priv = dev->dev_private;
8613         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8614         u32 flip_mask;
8615         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8616         int ret;
8617
8618         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8619         if (ret)
8620                 goto err;
8621
8622         ret = intel_ring_begin(ring, 6);
8623         if (ret)
8624                 goto err_unpin;
8625
8626         if (intel_crtc->plane)
8627                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8628         else
8629                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8630         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8631         intel_ring_emit(ring, MI_NOOP);
8632         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8633                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8634         intel_ring_emit(ring, fb->pitches[0]);
8635         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8636         intel_ring_emit(ring, MI_NOOP);
8637
8638         intel_mark_page_flip_active(intel_crtc);
8639         __intel_ring_advance(ring);
8640         return 0;
8641
8642 err_unpin:
8643         intel_unpin_fb_obj(obj);
8644 err:
8645         return ret;
8646 }
8647
8648 static int intel_gen4_queue_flip(struct drm_device *dev,
8649                                  struct drm_crtc *crtc,
8650                                  struct drm_framebuffer *fb,
8651                                  struct drm_i915_gem_object *obj,
8652                                  uint32_t flags)
8653 {
8654         struct drm_i915_private *dev_priv = dev->dev_private;
8655         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8656         uint32_t pf, pipesrc;
8657         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8658         int ret;
8659
8660         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8661         if (ret)
8662                 goto err;
8663
8664         ret = intel_ring_begin(ring, 4);
8665         if (ret)
8666                 goto err_unpin;
8667
8668         /* i965+ uses the linear or tiled offsets from the
8669          * Display Registers (which do not change across a page-flip)
8670          * so we need only reprogram the base address.
8671          */
8672         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8673                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8674         intel_ring_emit(ring, fb->pitches[0]);
8675         intel_ring_emit(ring,
8676                         (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
8677                         obj->tiling_mode);
8678
8679         /* XXX Enabling the panel-fitter across page-flip is so far
8680          * untested on non-native modes, so ignore it for now.
8681          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8682          */
8683         pf = 0;
8684         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8685         intel_ring_emit(ring, pf | pipesrc);
8686
8687         intel_mark_page_flip_active(intel_crtc);
8688         __intel_ring_advance(ring);
8689         return 0;
8690
8691 err_unpin:
8692         intel_unpin_fb_obj(obj);
8693 err:
8694         return ret;
8695 }
8696
8697 static int intel_gen6_queue_flip(struct drm_device *dev,
8698                                  struct drm_crtc *crtc,
8699                                  struct drm_framebuffer *fb,
8700                                  struct drm_i915_gem_object *obj,
8701                                  uint32_t flags)
8702 {
8703         struct drm_i915_private *dev_priv = dev->dev_private;
8704         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8705         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8706         uint32_t pf, pipesrc;
8707         int ret;
8708
8709         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8710         if (ret)
8711                 goto err;
8712
8713         ret = intel_ring_begin(ring, 4);
8714         if (ret)
8715                 goto err_unpin;
8716
8717         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8718                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8719         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
8720         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8721
8722         /* Contrary to the suggestions in the documentation,
8723          * "Enable Panel Fitter" does not seem to be required when page
8724          * flipping with a non-native mode, and worse causes a normal
8725          * modeset to fail.
8726          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8727          */
8728         pf = 0;
8729         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8730         intel_ring_emit(ring, pf | pipesrc);
8731
8732         intel_mark_page_flip_active(intel_crtc);
8733         __intel_ring_advance(ring);
8734         return 0;
8735
8736 err_unpin:
8737         intel_unpin_fb_obj(obj);
8738 err:
8739         return ret;
8740 }
8741
8742 static int intel_gen7_queue_flip(struct drm_device *dev,
8743                                  struct drm_crtc *crtc,
8744                                  struct drm_framebuffer *fb,
8745                                  struct drm_i915_gem_object *obj,
8746                                  uint32_t flags)
8747 {
8748         struct drm_i915_private *dev_priv = dev->dev_private;
8749         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8750         struct intel_ring_buffer *ring;
8751         uint32_t plane_bit = 0;
8752         int len, ret;
8753
8754         ring = obj->ring;
8755         if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
8756                 ring = &dev_priv->ring[BCS];
8757
8758         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8759         if (ret)
8760                 goto err;
8761
8762         switch(intel_crtc->plane) {
8763         case PLANE_A:
8764                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8765                 break;
8766         case PLANE_B:
8767                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8768                 break;
8769         case PLANE_C:
8770                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8771                 break;
8772         default:
8773                 WARN_ONCE(1, "unknown plane in flip command\n");
8774                 ret = -ENODEV;
8775                 goto err_unpin;
8776         }
8777
8778         len = 4;
8779         if (ring->id == RCS) {
8780                 len += 6;
8781                 /*
8782                  * On Gen 8, SRM is now taking an extra dword to accommodate
8783                  * 48bits addresses, and we need a NOOP for the batch size to
8784                  * stay even.
8785                  */
8786                 if (IS_GEN8(dev))
8787                         len += 2;
8788         }
8789
8790         /*
8791          * BSpec MI_DISPLAY_FLIP for IVB:
8792          * "The full packet must be contained within the same cache line."
8793          *
8794          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
8795          * cacheline, if we ever start emitting more commands before
8796          * the MI_DISPLAY_FLIP we may need to first emit everything else,
8797          * then do the cacheline alignment, and finally emit the
8798          * MI_DISPLAY_FLIP.
8799          */
8800         ret = intel_ring_cacheline_align(ring);
8801         if (ret)
8802                 goto err_unpin;
8803
8804         ret = intel_ring_begin(ring, len);
8805         if (ret)
8806                 goto err_unpin;
8807
8808         /* Unmask the flip-done completion message. Note that the bspec says that
8809          * we should do this for both the BCS and RCS, and that we must not unmask
8810          * more than one flip event at any time (or ensure that one flip message
8811          * can be sent by waiting for flip-done prior to queueing new flips).
8812          * Experimentation says that BCS works despite DERRMR masking all
8813          * flip-done completion events and that unmasking all planes at once
8814          * for the RCS also doesn't appear to drop events. Setting the DERRMR
8815          * to zero does lead to lockups within MI_DISPLAY_FLIP.
8816          */
8817         if (ring->id == RCS) {
8818                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8819                 intel_ring_emit(ring, DERRMR);
8820                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8821                                         DERRMR_PIPEB_PRI_FLIP_DONE |
8822                                         DERRMR_PIPEC_PRI_FLIP_DONE));
8823                 if (IS_GEN8(dev))
8824                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
8825                                               MI_SRM_LRM_GLOBAL_GTT);
8826                 else
8827                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
8828                                               MI_SRM_LRM_GLOBAL_GTT);
8829                 intel_ring_emit(ring, DERRMR);
8830                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8831                 if (IS_GEN8(dev)) {
8832                         intel_ring_emit(ring, 0);
8833                         intel_ring_emit(ring, MI_NOOP);
8834                 }
8835         }
8836
8837         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
8838         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
8839         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8840         intel_ring_emit(ring, (MI_NOOP));
8841
8842         intel_mark_page_flip_active(intel_crtc);
8843         __intel_ring_advance(ring);
8844         return 0;
8845
8846 err_unpin:
8847         intel_unpin_fb_obj(obj);
8848 err:
8849         return ret;
8850 }
8851
8852 static int intel_default_queue_flip(struct drm_device *dev,
8853                                     struct drm_crtc *crtc,
8854                                     struct drm_framebuffer *fb,
8855                                     struct drm_i915_gem_object *obj,
8856                                     uint32_t flags)
8857 {
8858         return -ENODEV;
8859 }
8860
8861 static int intel_crtc_page_flip(struct drm_crtc *crtc,
8862                                 struct drm_framebuffer *fb,
8863                                 struct drm_pending_vblank_event *event,
8864                                 uint32_t page_flip_flags)
8865 {
8866         struct drm_device *dev = crtc->dev;
8867         struct drm_i915_private *dev_priv = dev->dev_private;
8868         struct drm_framebuffer *old_fb = crtc->primary->fb;
8869         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
8870         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8871         struct intel_unpin_work *work;
8872         unsigned long flags;
8873         int ret;
8874
8875         /* Can't change pixel format via MI display flips. */
8876         if (fb->pixel_format != crtc->primary->fb->pixel_format)
8877                 return -EINVAL;
8878
8879         /*
8880          * TILEOFF/LINOFF registers can't be changed via MI display flips.
8881          * Note that pitch changes could also affect these register.
8882          */
8883         if (INTEL_INFO(dev)->gen > 3 &&
8884             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
8885              fb->pitches[0] != crtc->primary->fb->pitches[0]))
8886                 return -EINVAL;
8887
8888         if (i915_terminally_wedged(&dev_priv->gpu_error))
8889                 goto out_hang;
8890
8891         work = kzalloc(sizeof(*work), GFP_KERNEL);
8892         if (work == NULL)
8893                 return -ENOMEM;
8894
8895         work->event = event;
8896         work->crtc = crtc;
8897         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
8898         INIT_WORK(&work->work, intel_unpin_work_fn);
8899
8900         ret = drm_vblank_get(dev, intel_crtc->pipe);
8901         if (ret)
8902                 goto free_work;
8903
8904         /* We borrow the event spin lock for protecting unpin_work */
8905         spin_lock_irqsave(&dev->event_lock, flags);
8906         if (intel_crtc->unpin_work) {
8907                 spin_unlock_irqrestore(&dev->event_lock, flags);
8908                 kfree(work);
8909                 drm_vblank_put(dev, intel_crtc->pipe);
8910
8911                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8912                 return -EBUSY;
8913         }
8914         intel_crtc->unpin_work = work;
8915         spin_unlock_irqrestore(&dev->event_lock, flags);
8916
8917         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8918                 flush_workqueue(dev_priv->wq);
8919
8920         ret = i915_mutex_lock_interruptible(dev);
8921         if (ret)
8922                 goto cleanup;
8923
8924         /* Reference the objects for the scheduled work. */
8925         drm_gem_object_reference(&work->old_fb_obj->base);
8926         drm_gem_object_reference(&obj->base);
8927
8928         crtc->primary->fb = fb;
8929
8930         work->pending_flip_obj = obj;
8931
8932         work->enable_stall_check = true;
8933
8934         atomic_inc(&intel_crtc->unpin_work_count);
8935         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
8936
8937         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8938         if (ret)
8939                 goto cleanup_pending;
8940
8941         intel_disable_fbc(dev);
8942         intel_mark_fb_busy(obj, NULL);
8943         mutex_unlock(&dev->struct_mutex);
8944
8945         trace_i915_flip_request(intel_crtc->plane, obj);
8946
8947         return 0;
8948
8949 cleanup_pending:
8950         atomic_dec(&intel_crtc->unpin_work_count);
8951         crtc->primary->fb = old_fb;
8952         drm_gem_object_unreference(&work->old_fb_obj->base);
8953         drm_gem_object_unreference(&obj->base);
8954         mutex_unlock(&dev->struct_mutex);
8955
8956 cleanup:
8957         spin_lock_irqsave(&dev->event_lock, flags);
8958         intel_crtc->unpin_work = NULL;
8959         spin_unlock_irqrestore(&dev->event_lock, flags);
8960
8961         drm_vblank_put(dev, intel_crtc->pipe);
8962 free_work:
8963         kfree(work);
8964
8965         if (ret == -EIO) {
8966 out_hang:
8967                 intel_crtc_wait_for_pending_flips(crtc);
8968                 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
8969                 if (ret == 0 && event)
8970                         drm_send_vblank_event(dev, intel_crtc->pipe, event);
8971         }
8972         return ret;
8973 }
8974
8975 static struct drm_crtc_helper_funcs intel_helper_funcs = {
8976         .mode_set_base_atomic = intel_pipe_set_base_atomic,
8977         .load_lut = intel_crtc_load_lut,
8978 };
8979
8980 /**
8981  * intel_modeset_update_staged_output_state
8982  *
8983  * Updates the staged output configuration state, e.g. after we've read out the
8984  * current hw state.
8985  */
8986 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
8987 {
8988         struct intel_crtc *crtc;
8989         struct intel_encoder *encoder;
8990         struct intel_connector *connector;
8991
8992         list_for_each_entry(connector, &dev->mode_config.connector_list,
8993                             base.head) {
8994                 connector->new_encoder =
8995                         to_intel_encoder(connector->base.encoder);
8996         }
8997
8998         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8999                             base.head) {
9000                 encoder->new_crtc =
9001                         to_intel_crtc(encoder->base.crtc);
9002         }
9003
9004         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9005                             base.head) {
9006                 crtc->new_enabled = crtc->base.enabled;
9007
9008                 if (crtc->new_enabled)
9009                         crtc->new_config = &crtc->config;
9010                 else
9011                         crtc->new_config = NULL;
9012         }
9013 }
9014
9015 /**
9016  * intel_modeset_commit_output_state
9017  *
9018  * This function copies the stage display pipe configuration to the real one.
9019  */
9020 static void intel_modeset_commit_output_state(struct drm_device *dev)
9021 {
9022         struct intel_crtc *crtc;
9023         struct intel_encoder *encoder;
9024         struct intel_connector *connector;
9025
9026         list_for_each_entry(connector, &dev->mode_config.connector_list,
9027                             base.head) {
9028                 connector->base.encoder = &connector->new_encoder->base;
9029         }
9030
9031         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9032                             base.head) {
9033                 encoder->base.crtc = &encoder->new_crtc->base;
9034         }
9035
9036         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9037                             base.head) {
9038                 crtc->base.enabled = crtc->new_enabled;
9039         }
9040 }
9041
9042 static void
9043 connected_sink_compute_bpp(struct intel_connector * connector,
9044                            struct intel_crtc_config *pipe_config)
9045 {
9046         int bpp = pipe_config->pipe_bpp;
9047
9048         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9049                 connector->base.base.id,
9050                 drm_get_connector_name(&connector->base));
9051
9052         /* Don't use an invalid EDID bpc value */
9053         if (connector->base.display_info.bpc &&
9054             connector->base.display_info.bpc * 3 < bpp) {
9055                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9056                               bpp, connector->base.display_info.bpc*3);
9057                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9058         }
9059
9060         /* Clamp bpp to 8 on screens without EDID 1.4 */
9061         if (connector->base.display_info.bpc == 0 && bpp > 24) {
9062                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9063                               bpp);
9064                 pipe_config->pipe_bpp = 24;
9065         }
9066 }
9067
9068 static int
9069 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9070                           struct drm_framebuffer *fb,
9071                           struct intel_crtc_config *pipe_config)
9072 {
9073         struct drm_device *dev = crtc->base.dev;
9074         struct intel_connector *connector;
9075         int bpp;
9076
9077         switch (fb->pixel_format) {
9078         case DRM_FORMAT_C8:
9079                 bpp = 8*3; /* since we go through a colormap */
9080                 break;
9081         case DRM_FORMAT_XRGB1555:
9082         case DRM_FORMAT_ARGB1555:
9083                 /* checked in intel_framebuffer_init already */
9084                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9085                         return -EINVAL;
9086         case DRM_FORMAT_RGB565:
9087                 bpp = 6*3; /* min is 18bpp */
9088                 break;
9089         case DRM_FORMAT_XBGR8888:
9090         case DRM_FORMAT_ABGR8888:
9091                 /* checked in intel_framebuffer_init already */
9092                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9093                         return -EINVAL;
9094         case DRM_FORMAT_XRGB8888:
9095         case DRM_FORMAT_ARGB8888:
9096                 bpp = 8*3;
9097                 break;
9098         case DRM_FORMAT_XRGB2101010:
9099         case DRM_FORMAT_ARGB2101010:
9100         case DRM_FORMAT_XBGR2101010:
9101         case DRM_FORMAT_ABGR2101010:
9102                 /* checked in intel_framebuffer_init already */
9103                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9104                         return -EINVAL;
9105                 bpp = 10*3;
9106                 break;
9107         /* TODO: gen4+ supports 16 bpc floating point, too. */
9108         default:
9109                 DRM_DEBUG_KMS("unsupported depth\n");
9110                 return -EINVAL;
9111         }
9112
9113         pipe_config->pipe_bpp = bpp;
9114
9115         /* Clamp display bpp to EDID value */
9116         list_for_each_entry(connector, &dev->mode_config.connector_list,
9117                             base.head) {
9118                 if (!connector->new_encoder ||
9119                     connector->new_encoder->new_crtc != crtc)
9120                         continue;
9121
9122                 connected_sink_compute_bpp(connector, pipe_config);
9123         }
9124
9125         return bpp;
9126 }
9127
9128 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9129 {
9130         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9131                         "type: 0x%x flags: 0x%x\n",
9132                 mode->crtc_clock,
9133                 mode->crtc_hdisplay, mode->crtc_hsync_start,
9134                 mode->crtc_hsync_end, mode->crtc_htotal,
9135                 mode->crtc_vdisplay, mode->crtc_vsync_start,
9136                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9137 }
9138
9139 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9140                                    struct intel_crtc_config *pipe_config,
9141                                    const char *context)
9142 {
9143         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9144                       context, pipe_name(crtc->pipe));
9145
9146         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9147         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9148                       pipe_config->pipe_bpp, pipe_config->dither);
9149         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9150                       pipe_config->has_pch_encoder,
9151                       pipe_config->fdi_lanes,
9152                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9153                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9154                       pipe_config->fdi_m_n.tu);
9155         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9156                       pipe_config->has_dp_encoder,
9157                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9158                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9159                       pipe_config->dp_m_n.tu);
9160         DRM_DEBUG_KMS("requested mode:\n");
9161         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9162         DRM_DEBUG_KMS("adjusted mode:\n");
9163         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9164         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9165         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9166         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9167                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9168         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9169                       pipe_config->gmch_pfit.control,
9170                       pipe_config->gmch_pfit.pgm_ratios,
9171                       pipe_config->gmch_pfit.lvds_border_bits);
9172         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9173                       pipe_config->pch_pfit.pos,
9174                       pipe_config->pch_pfit.size,
9175                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9176         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9177         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
9178 }
9179
9180 static bool encoders_cloneable(const struct intel_encoder *a,
9181                                const struct intel_encoder *b)
9182 {
9183         /* masks could be asymmetric, so check both ways */
9184         return a == b || (a->cloneable & (1 << b->type) &&
9185                           b->cloneable & (1 << a->type));
9186 }
9187
9188 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9189                                          struct intel_encoder *encoder)
9190 {
9191         struct drm_device *dev = crtc->base.dev;
9192         struct intel_encoder *source_encoder;
9193
9194         list_for_each_entry(source_encoder,
9195                             &dev->mode_config.encoder_list, base.head) {
9196                 if (source_encoder->new_crtc != crtc)
9197                         continue;
9198
9199                 if (!encoders_cloneable(encoder, source_encoder))
9200                         return false;
9201         }
9202
9203         return true;
9204 }
9205
9206 static bool check_encoder_cloning(struct intel_crtc *crtc)
9207 {
9208         struct drm_device *dev = crtc->base.dev;
9209         struct intel_encoder *encoder;
9210
9211         list_for_each_entry(encoder,
9212                             &dev->mode_config.encoder_list, base.head) {
9213                 if (encoder->new_crtc != crtc)
9214                         continue;
9215
9216                 if (!check_single_encoder_cloning(crtc, encoder))
9217                         return false;
9218         }
9219
9220         return true;
9221 }
9222
9223 static struct intel_crtc_config *
9224 intel_modeset_pipe_config(struct drm_crtc *crtc,
9225                           struct drm_framebuffer *fb,
9226                           struct drm_display_mode *mode)
9227 {
9228         struct drm_device *dev = crtc->dev;
9229         struct intel_encoder *encoder;
9230         struct intel_crtc_config *pipe_config;
9231         int plane_bpp, ret = -EINVAL;
9232         bool retry = true;
9233
9234         if (!check_encoder_cloning(to_intel_crtc(crtc))) {
9235                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
9236                 return ERR_PTR(-EINVAL);
9237         }
9238
9239         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9240         if (!pipe_config)
9241                 return ERR_PTR(-ENOMEM);
9242
9243         drm_mode_copy(&pipe_config->adjusted_mode, mode);
9244         drm_mode_copy(&pipe_config->requested_mode, mode);
9245
9246         pipe_config->cpu_transcoder =
9247                 (enum transcoder) to_intel_crtc(crtc)->pipe;
9248         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9249
9250         /*
9251          * Sanitize sync polarity flags based on requested ones. If neither
9252          * positive or negative polarity is requested, treat this as meaning
9253          * negative polarity.
9254          */
9255         if (!(pipe_config->adjusted_mode.flags &
9256               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
9257                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
9258
9259         if (!(pipe_config->adjusted_mode.flags &
9260               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
9261                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
9262
9263         /* Compute a starting value for pipe_config->pipe_bpp taking the source
9264          * plane pixel format and any sink constraints into account. Returns the
9265          * source plane bpp so that dithering can be selected on mismatches
9266          * after encoders and crtc also have had their say. */
9267         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
9268                                               fb, pipe_config);
9269         if (plane_bpp < 0)
9270                 goto fail;
9271
9272         /*
9273          * Determine the real pipe dimensions. Note that stereo modes can
9274          * increase the actual pipe size due to the frame doubling and
9275          * insertion of additional space for blanks between the frame. This
9276          * is stored in the crtc timings. We use the requested mode to do this
9277          * computation to clearly distinguish it from the adjusted mode, which
9278          * can be changed by the connectors in the below retry loop.
9279          */
9280         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
9281         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
9282         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
9283
9284 encoder_retry:
9285         /* Ensure the port clock defaults are reset when retrying. */
9286         pipe_config->port_clock = 0;
9287         pipe_config->pixel_multiplier = 1;
9288
9289         /* Fill in default crtc timings, allow encoders to overwrite them. */
9290         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
9291
9292         /* Pass our mode to the connectors and the CRTC to give them a chance to
9293          * adjust it according to limitations or connector properties, and also
9294          * a chance to reject the mode entirely.
9295          */
9296         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9297                             base.head) {
9298
9299                 if (&encoder->new_crtc->base != crtc)
9300                         continue;
9301
9302                 if (!(encoder->compute_config(encoder, pipe_config))) {
9303                         DRM_DEBUG_KMS("Encoder config failure\n");
9304                         goto fail;
9305                 }
9306         }
9307
9308         /* Set default port clock if not overwritten by the encoder. Needs to be
9309          * done afterwards in case the encoder adjusts the mode. */
9310         if (!pipe_config->port_clock)
9311                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
9312                         * pipe_config->pixel_multiplier;
9313
9314         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
9315         if (ret < 0) {
9316                 DRM_DEBUG_KMS("CRTC fixup failed\n");
9317                 goto fail;
9318         }
9319
9320         if (ret == RETRY) {
9321                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
9322                         ret = -EINVAL;
9323                         goto fail;
9324                 }
9325
9326                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9327                 retry = false;
9328                 goto encoder_retry;
9329         }
9330
9331         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
9332         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9333                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
9334
9335         return pipe_config;
9336 fail:
9337         kfree(pipe_config);
9338         return ERR_PTR(ret);
9339 }
9340
9341 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
9342  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9343 static void
9344 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
9345                              unsigned *prepare_pipes, unsigned *disable_pipes)
9346 {
9347         struct intel_crtc *intel_crtc;
9348         struct drm_device *dev = crtc->dev;
9349         struct intel_encoder *encoder;
9350         struct intel_connector *connector;
9351         struct drm_crtc *tmp_crtc;
9352
9353         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
9354
9355         /* Check which crtcs have changed outputs connected to them, these need
9356          * to be part of the prepare_pipes mask. We don't (yet) support global
9357          * modeset across multiple crtcs, so modeset_pipes will only have one
9358          * bit set at most. */
9359         list_for_each_entry(connector, &dev->mode_config.connector_list,
9360                             base.head) {
9361                 if (connector->base.encoder == &connector->new_encoder->base)
9362                         continue;
9363
9364                 if (connector->base.encoder) {
9365                         tmp_crtc = connector->base.encoder->crtc;
9366
9367                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9368                 }
9369
9370                 if (connector->new_encoder)
9371                         *prepare_pipes |=
9372                                 1 << connector->new_encoder->new_crtc->pipe;
9373         }
9374
9375         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9376                             base.head) {
9377                 if (encoder->base.crtc == &encoder->new_crtc->base)
9378                         continue;
9379
9380                 if (encoder->base.crtc) {
9381                         tmp_crtc = encoder->base.crtc;
9382
9383                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9384                 }
9385
9386                 if (encoder->new_crtc)
9387                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
9388         }
9389
9390         /* Check for pipes that will be enabled/disabled ... */
9391         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9392                             base.head) {
9393                 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
9394                         continue;
9395
9396                 if (!intel_crtc->new_enabled)
9397                         *disable_pipes |= 1 << intel_crtc->pipe;
9398                 else
9399                         *prepare_pipes |= 1 << intel_crtc->pipe;
9400         }
9401
9402
9403         /* set_mode is also used to update properties on life display pipes. */
9404         intel_crtc = to_intel_crtc(crtc);
9405         if (intel_crtc->new_enabled)
9406                 *prepare_pipes |= 1 << intel_crtc->pipe;
9407
9408         /*
9409          * For simplicity do a full modeset on any pipe where the output routing
9410          * changed. We could be more clever, but that would require us to be
9411          * more careful with calling the relevant encoder->mode_set functions.
9412          */
9413         if (*prepare_pipes)
9414                 *modeset_pipes = *prepare_pipes;
9415
9416         /* ... and mask these out. */
9417         *modeset_pipes &= ~(*disable_pipes);
9418         *prepare_pipes &= ~(*disable_pipes);
9419
9420         /*
9421          * HACK: We don't (yet) fully support global modesets. intel_set_config
9422          * obies this rule, but the modeset restore mode of
9423          * intel_modeset_setup_hw_state does not.
9424          */
9425         *modeset_pipes &= 1 << intel_crtc->pipe;
9426         *prepare_pipes &= 1 << intel_crtc->pipe;
9427
9428         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9429                       *modeset_pipes, *prepare_pipes, *disable_pipes);
9430 }
9431
9432 static bool intel_crtc_in_use(struct drm_crtc *crtc)
9433 {
9434         struct drm_encoder *encoder;
9435         struct drm_device *dev = crtc->dev;
9436
9437         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
9438                 if (encoder->crtc == crtc)
9439                         return true;
9440
9441         return false;
9442 }
9443
9444 static void
9445 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
9446 {
9447         struct intel_encoder *intel_encoder;
9448         struct intel_crtc *intel_crtc;
9449         struct drm_connector *connector;
9450
9451         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
9452                             base.head) {
9453                 if (!intel_encoder->base.crtc)
9454                         continue;
9455
9456                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
9457
9458                 if (prepare_pipes & (1 << intel_crtc->pipe))
9459                         intel_encoder->connectors_active = false;
9460         }
9461
9462         intel_modeset_commit_output_state(dev);
9463
9464         /* Double check state. */
9465         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9466                             base.head) {
9467                 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
9468                 WARN_ON(intel_crtc->new_config &&
9469                         intel_crtc->new_config != &intel_crtc->config);
9470                 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
9471         }
9472
9473         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9474                 if (!connector->encoder || !connector->encoder->crtc)
9475                         continue;
9476
9477                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
9478
9479                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
9480                         struct drm_property *dpms_property =
9481                                 dev->mode_config.dpms_property;
9482
9483                         connector->dpms = DRM_MODE_DPMS_ON;
9484                         drm_object_property_set_value(&connector->base,
9485                                                          dpms_property,
9486                                                          DRM_MODE_DPMS_ON);
9487
9488                         intel_encoder = to_intel_encoder(connector->encoder);
9489                         intel_encoder->connectors_active = true;
9490                 }
9491         }
9492
9493 }
9494
9495 static bool intel_fuzzy_clock_check(int clock1, int clock2)
9496 {
9497         int diff;
9498
9499         if (clock1 == clock2)
9500                 return true;
9501
9502         if (!clock1 || !clock2)
9503                 return false;
9504
9505         diff = abs(clock1 - clock2);
9506
9507         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
9508                 return true;
9509
9510         return false;
9511 }
9512
9513 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9514         list_for_each_entry((intel_crtc), \
9515                             &(dev)->mode_config.crtc_list, \
9516                             base.head) \
9517                 if (mask & (1 <<(intel_crtc)->pipe))
9518
9519 static bool
9520 intel_pipe_config_compare(struct drm_device *dev,
9521                           struct intel_crtc_config *current_config,
9522                           struct intel_crtc_config *pipe_config)
9523 {
9524 #define PIPE_CONF_CHECK_X(name) \
9525         if (current_config->name != pipe_config->name) { \
9526                 DRM_ERROR("mismatch in " #name " " \
9527                           "(expected 0x%08x, found 0x%08x)\n", \
9528                           current_config->name, \
9529                           pipe_config->name); \
9530                 return false; \
9531         }
9532
9533 #define PIPE_CONF_CHECK_I(name) \
9534         if (current_config->name != pipe_config->name) { \
9535                 DRM_ERROR("mismatch in " #name " " \
9536                           "(expected %i, found %i)\n", \
9537                           current_config->name, \
9538                           pipe_config->name); \
9539                 return false; \
9540         }
9541
9542 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
9543         if ((current_config->name ^ pipe_config->name) & (mask)) { \
9544                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
9545                           "(expected %i, found %i)\n", \
9546                           current_config->name & (mask), \
9547                           pipe_config->name & (mask)); \
9548                 return false; \
9549         }
9550
9551 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9552         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9553                 DRM_ERROR("mismatch in " #name " " \
9554                           "(expected %i, found %i)\n", \
9555                           current_config->name, \
9556                           pipe_config->name); \
9557                 return false; \
9558         }
9559
9560 #define PIPE_CONF_QUIRK(quirk)  \
9561         ((current_config->quirks | pipe_config->quirks) & (quirk))
9562
9563         PIPE_CONF_CHECK_I(cpu_transcoder);
9564
9565         PIPE_CONF_CHECK_I(has_pch_encoder);
9566         PIPE_CONF_CHECK_I(fdi_lanes);
9567         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9568         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9569         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9570         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9571         PIPE_CONF_CHECK_I(fdi_m_n.tu);
9572
9573         PIPE_CONF_CHECK_I(has_dp_encoder);
9574         PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9575         PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9576         PIPE_CONF_CHECK_I(dp_m_n.link_m);
9577         PIPE_CONF_CHECK_I(dp_m_n.link_n);
9578         PIPE_CONF_CHECK_I(dp_m_n.tu);
9579
9580         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9581         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9582         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9583         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9584         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9585         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9586
9587         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9588         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9589         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9590         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9591         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9592         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9593
9594         PIPE_CONF_CHECK_I(pixel_multiplier);
9595
9596         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9597                               DRM_MODE_FLAG_INTERLACE);
9598
9599         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9600                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9601                                       DRM_MODE_FLAG_PHSYNC);
9602                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9603                                       DRM_MODE_FLAG_NHSYNC);
9604                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9605                                       DRM_MODE_FLAG_PVSYNC);
9606                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9607                                       DRM_MODE_FLAG_NVSYNC);
9608         }
9609
9610         PIPE_CONF_CHECK_I(pipe_src_w);
9611         PIPE_CONF_CHECK_I(pipe_src_h);
9612
9613         /*
9614          * FIXME: BIOS likes to set up a cloned config with lvds+external
9615          * screen. Since we don't yet re-compute the pipe config when moving
9616          * just the lvds port away to another pipe the sw tracking won't match.
9617          *
9618          * Proper atomic modesets with recomputed global state will fix this.
9619          * Until then just don't check gmch state for inherited modes.
9620          */
9621         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
9622                 PIPE_CONF_CHECK_I(gmch_pfit.control);
9623                 /* pfit ratios are autocomputed by the hw on gen4+ */
9624                 if (INTEL_INFO(dev)->gen < 4)
9625                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9626                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9627         }
9628
9629         PIPE_CONF_CHECK_I(pch_pfit.enabled);
9630         if (current_config->pch_pfit.enabled) {
9631                 PIPE_CONF_CHECK_I(pch_pfit.pos);
9632                 PIPE_CONF_CHECK_I(pch_pfit.size);
9633         }
9634
9635         /* BDW+ don't expose a synchronous way to read the state */
9636         if (IS_HASWELL(dev))
9637                 PIPE_CONF_CHECK_I(ips_enabled);
9638
9639         PIPE_CONF_CHECK_I(double_wide);
9640
9641         PIPE_CONF_CHECK_I(shared_dpll);
9642         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
9643         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
9644         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
9645         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
9646
9647         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
9648                 PIPE_CONF_CHECK_I(pipe_bpp);
9649
9650         PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
9651         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
9652
9653 #undef PIPE_CONF_CHECK_X
9654 #undef PIPE_CONF_CHECK_I
9655 #undef PIPE_CONF_CHECK_FLAGS
9656 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
9657 #undef PIPE_CONF_QUIRK
9658
9659         return true;
9660 }
9661
9662 static void
9663 check_connector_state(struct drm_device *dev)
9664 {
9665         struct intel_connector *connector;
9666
9667         list_for_each_entry(connector, &dev->mode_config.connector_list,
9668                             base.head) {
9669                 /* This also checks the encoder/connector hw state with the
9670                  * ->get_hw_state callbacks. */
9671                 intel_connector_check_state(connector);
9672
9673                 WARN(&connector->new_encoder->base != connector->base.encoder,
9674                      "connector's staged encoder doesn't match current encoder\n");
9675         }
9676 }
9677
9678 static void
9679 check_encoder_state(struct drm_device *dev)
9680 {
9681         struct intel_encoder *encoder;
9682         struct intel_connector *connector;
9683
9684         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9685                             base.head) {
9686                 bool enabled = false;
9687                 bool active = false;
9688                 enum pipe pipe, tracked_pipe;
9689
9690                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
9691                               encoder->base.base.id,
9692                               drm_get_encoder_name(&encoder->base));
9693
9694                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
9695                      "encoder's stage crtc doesn't match current crtc\n");
9696                 WARN(encoder->connectors_active && !encoder->base.crtc,
9697                      "encoder's active_connectors set, but no crtc\n");
9698
9699                 list_for_each_entry(connector, &dev->mode_config.connector_list,
9700                                     base.head) {
9701                         if (connector->base.encoder != &encoder->base)
9702                                 continue;
9703                         enabled = true;
9704                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
9705                                 active = true;
9706                 }
9707                 WARN(!!encoder->base.crtc != enabled,
9708                      "encoder's enabled state mismatch "
9709                      "(expected %i, found %i)\n",
9710                      !!encoder->base.crtc, enabled);
9711                 WARN(active && !encoder->base.crtc,
9712                      "active encoder with no crtc\n");
9713
9714                 WARN(encoder->connectors_active != active,
9715                      "encoder's computed active state doesn't match tracked active state "
9716                      "(expected %i, found %i)\n", active, encoder->connectors_active);
9717
9718                 active = encoder->get_hw_state(encoder, &pipe);
9719                 WARN(active != encoder->connectors_active,
9720                      "encoder's hw state doesn't match sw tracking "
9721                      "(expected %i, found %i)\n",
9722                      encoder->connectors_active, active);
9723
9724                 if (!encoder->base.crtc)
9725                         continue;
9726
9727                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9728                 WARN(active && pipe != tracked_pipe,
9729                      "active encoder's pipe doesn't match"
9730                      "(expected %i, found %i)\n",
9731                      tracked_pipe, pipe);
9732
9733         }
9734 }
9735
9736 static void
9737 check_crtc_state(struct drm_device *dev)
9738 {
9739         struct drm_i915_private *dev_priv = dev->dev_private;
9740         struct intel_crtc *crtc;
9741         struct intel_encoder *encoder;
9742         struct intel_crtc_config pipe_config;
9743
9744         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9745                             base.head) {
9746                 bool enabled = false;
9747                 bool active = false;
9748
9749                 memset(&pipe_config, 0, sizeof(pipe_config));
9750
9751                 DRM_DEBUG_KMS("[CRTC:%d]\n",
9752                               crtc->base.base.id);
9753
9754                 WARN(crtc->active && !crtc->base.enabled,
9755                      "active crtc, but not enabled in sw tracking\n");
9756
9757                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9758                                     base.head) {
9759                         if (encoder->base.crtc != &crtc->base)
9760                                 continue;
9761                         enabled = true;
9762                         if (encoder->connectors_active)
9763                                 active = true;
9764                 }
9765
9766                 WARN(active != crtc->active,
9767                      "crtc's computed active state doesn't match tracked active state "
9768                      "(expected %i, found %i)\n", active, crtc->active);
9769                 WARN(enabled != crtc->base.enabled,
9770                      "crtc's computed enabled state doesn't match tracked enabled state "
9771                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9772
9773                 active = dev_priv->display.get_pipe_config(crtc,
9774                                                            &pipe_config);
9775
9776                 /* hw state is inconsistent with the pipe A quirk */
9777                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9778                         active = crtc->active;
9779
9780                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9781                                     base.head) {
9782                         enum pipe pipe;
9783                         if (encoder->base.crtc != &crtc->base)
9784                                 continue;
9785                         if (encoder->get_hw_state(encoder, &pipe))
9786                                 encoder->get_config(encoder, &pipe_config);
9787                 }
9788
9789                 WARN(crtc->active != active,
9790                      "crtc active state doesn't match with hw state "
9791                      "(expected %i, found %i)\n", crtc->active, active);
9792
9793                 if (active &&
9794                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9795                         WARN(1, "pipe state doesn't match!\n");
9796                         intel_dump_pipe_config(crtc, &pipe_config,
9797                                                "[hw state]");
9798                         intel_dump_pipe_config(crtc, &crtc->config,
9799                                                "[sw state]");
9800                 }
9801         }
9802 }
9803
9804 static void
9805 check_shared_dpll_state(struct drm_device *dev)
9806 {
9807         struct drm_i915_private *dev_priv = dev->dev_private;
9808         struct intel_crtc *crtc;
9809         struct intel_dpll_hw_state dpll_hw_state;
9810         int i;
9811
9812         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9813                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9814                 int enabled_crtcs = 0, active_crtcs = 0;
9815                 bool active;
9816
9817                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9818
9819                 DRM_DEBUG_KMS("%s\n", pll->name);
9820
9821                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9822
9823                 WARN(pll->active > pll->refcount,
9824                      "more active pll users than references: %i vs %i\n",
9825                      pll->active, pll->refcount);
9826                 WARN(pll->active && !pll->on,
9827                      "pll in active use but not on in sw tracking\n");
9828                 WARN(pll->on && !pll->active,
9829                      "pll in on but not on in use in sw tracking\n");
9830                 WARN(pll->on != active,
9831                      "pll on state mismatch (expected %i, found %i)\n",
9832                      pll->on, active);
9833
9834                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9835                                     base.head) {
9836                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9837                                 enabled_crtcs++;
9838                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9839                                 active_crtcs++;
9840                 }
9841                 WARN(pll->active != active_crtcs,
9842                      "pll active crtcs mismatch (expected %i, found %i)\n",
9843                      pll->active, active_crtcs);
9844                 WARN(pll->refcount != enabled_crtcs,
9845                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
9846                      pll->refcount, enabled_crtcs);
9847
9848                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9849                                        sizeof(dpll_hw_state)),
9850                      "pll hw state mismatch\n");
9851         }
9852 }
9853
9854 void
9855 intel_modeset_check_state(struct drm_device *dev)
9856 {
9857         check_connector_state(dev);
9858         check_encoder_state(dev);
9859         check_crtc_state(dev);
9860         check_shared_dpll_state(dev);
9861 }
9862
9863 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9864                                      int dotclock)
9865 {
9866         /*
9867          * FDI already provided one idea for the dotclock.
9868          * Yell if the encoder disagrees.
9869          */
9870         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
9871              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9872              pipe_config->adjusted_mode.crtc_clock, dotclock);
9873 }
9874
9875 static int __intel_set_mode(struct drm_crtc *crtc,
9876                             struct drm_display_mode *mode,
9877                             int x, int y, struct drm_framebuffer *fb)
9878 {
9879         struct drm_device *dev = crtc->dev;
9880         struct drm_i915_private *dev_priv = dev->dev_private;
9881         struct drm_display_mode *saved_mode;
9882         struct intel_crtc_config *pipe_config = NULL;
9883         struct intel_crtc *intel_crtc;
9884         unsigned disable_pipes, prepare_pipes, modeset_pipes;
9885         int ret = 0;
9886
9887         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
9888         if (!saved_mode)
9889                 return -ENOMEM;
9890
9891         intel_modeset_affected_pipes(crtc, &modeset_pipes,
9892                                      &prepare_pipes, &disable_pipes);
9893
9894         *saved_mode = crtc->mode;
9895
9896         /* Hack: Because we don't (yet) support global modeset on multiple
9897          * crtcs, we don't keep track of the new mode for more than one crtc.
9898          * Hence simply check whether any bit is set in modeset_pipes in all the
9899          * pieces of code that are not yet converted to deal with mutliple crtcs
9900          * changing their mode at the same time. */
9901         if (modeset_pipes) {
9902                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
9903                 if (IS_ERR(pipe_config)) {
9904                         ret = PTR_ERR(pipe_config);
9905                         pipe_config = NULL;
9906
9907                         goto out;
9908                 }
9909                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9910                                        "[modeset]");
9911                 to_intel_crtc(crtc)->new_config = pipe_config;
9912         }
9913
9914         /*
9915          * See if the config requires any additional preparation, e.g.
9916          * to adjust global state with pipes off.  We need to do this
9917          * here so we can get the modeset_pipe updated config for the new
9918          * mode set on this crtc.  For other crtcs we need to use the
9919          * adjusted_mode bits in the crtc directly.
9920          */
9921         if (IS_VALLEYVIEW(dev)) {
9922                 valleyview_modeset_global_pipes(dev, &prepare_pipes);
9923
9924                 /* may have added more to prepare_pipes than we should */
9925                 prepare_pipes &= ~disable_pipes;
9926         }
9927
9928         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9929                 intel_crtc_disable(&intel_crtc->base);
9930
9931         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9932                 if (intel_crtc->base.enabled)
9933                         dev_priv->display.crtc_disable(&intel_crtc->base);
9934         }
9935
9936         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9937          * to set it here already despite that we pass it down the callchain.
9938          */
9939         if (modeset_pipes) {
9940                 crtc->mode = *mode;
9941                 /* mode_set/enable/disable functions rely on a correct pipe
9942                  * config. */
9943                 to_intel_crtc(crtc)->config = *pipe_config;
9944                 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
9945
9946                 /*
9947                  * Calculate and store various constants which
9948                  * are later needed by vblank and swap-completion
9949                  * timestamping. They are derived from true hwmode.
9950                  */
9951                 drm_calc_timestamping_constants(crtc,
9952                                                 &pipe_config->adjusted_mode);
9953         }
9954
9955         /* Only after disabling all output pipelines that will be changed can we
9956          * update the the output configuration. */
9957         intel_modeset_update_state(dev, prepare_pipes);
9958
9959         if (dev_priv->display.modeset_global_resources)
9960                 dev_priv->display.modeset_global_resources(dev);
9961
9962         /* Set up the DPLL and any encoders state that needs to adjust or depend
9963          * on the DPLL.
9964          */
9965         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
9966                 ret = intel_crtc_mode_set(&intel_crtc->base,
9967                                           x, y, fb);
9968                 if (ret)
9969                         goto done;
9970         }
9971
9972         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9973         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9974                 dev_priv->display.crtc_enable(&intel_crtc->base);
9975
9976         /* FIXME: add subpixel order */
9977 done:
9978         if (ret && crtc->enabled)
9979                 crtc->mode = *saved_mode;
9980
9981 out:
9982         kfree(pipe_config);
9983         kfree(saved_mode);
9984         return ret;
9985 }
9986
9987 static int intel_set_mode(struct drm_crtc *crtc,
9988                           struct drm_display_mode *mode,
9989                           int x, int y, struct drm_framebuffer *fb)
9990 {
9991         int ret;
9992
9993         ret = __intel_set_mode(crtc, mode, x, y, fb);
9994
9995         if (ret == 0)
9996                 intel_modeset_check_state(crtc->dev);
9997
9998         return ret;
9999 }
10000
10001 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10002 {
10003         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10004 }
10005
10006 #undef for_each_intel_crtc_masked
10007
10008 static void intel_set_config_free(struct intel_set_config *config)
10009 {
10010         if (!config)
10011                 return;
10012
10013         kfree(config->save_connector_encoders);
10014         kfree(config->save_encoder_crtcs);
10015         kfree(config->save_crtc_enabled);
10016         kfree(config);
10017 }
10018
10019 static int intel_set_config_save_state(struct drm_device *dev,
10020                                        struct intel_set_config *config)
10021 {
10022         struct drm_crtc *crtc;
10023         struct drm_encoder *encoder;
10024         struct drm_connector *connector;
10025         int count;
10026
10027         config->save_crtc_enabled =
10028                 kcalloc(dev->mode_config.num_crtc,
10029                         sizeof(bool), GFP_KERNEL);
10030         if (!config->save_crtc_enabled)
10031                 return -ENOMEM;
10032
10033         config->save_encoder_crtcs =
10034                 kcalloc(dev->mode_config.num_encoder,
10035                         sizeof(struct drm_crtc *), GFP_KERNEL);
10036         if (!config->save_encoder_crtcs)
10037                 return -ENOMEM;
10038
10039         config->save_connector_encoders =
10040                 kcalloc(dev->mode_config.num_connector,
10041                         sizeof(struct drm_encoder *), GFP_KERNEL);
10042         if (!config->save_connector_encoders)
10043                 return -ENOMEM;
10044
10045         /* Copy data. Note that driver private data is not affected.
10046          * Should anything bad happen only the expected state is
10047          * restored, not the drivers personal bookkeeping.
10048          */
10049         count = 0;
10050         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10051                 config->save_crtc_enabled[count++] = crtc->enabled;
10052         }
10053
10054         count = 0;
10055         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10056                 config->save_encoder_crtcs[count++] = encoder->crtc;
10057         }
10058
10059         count = 0;
10060         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10061                 config->save_connector_encoders[count++] = connector->encoder;
10062         }
10063
10064         return 0;
10065 }
10066
10067 static void intel_set_config_restore_state(struct drm_device *dev,
10068                                            struct intel_set_config *config)
10069 {
10070         struct intel_crtc *crtc;
10071         struct intel_encoder *encoder;
10072         struct intel_connector *connector;
10073         int count;
10074
10075         count = 0;
10076         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
10077                 crtc->new_enabled = config->save_crtc_enabled[count++];
10078
10079                 if (crtc->new_enabled)
10080                         crtc->new_config = &crtc->config;
10081                 else
10082                         crtc->new_config = NULL;
10083         }
10084
10085         count = 0;
10086         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10087                 encoder->new_crtc =
10088                         to_intel_crtc(config->save_encoder_crtcs[count++]);
10089         }
10090
10091         count = 0;
10092         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10093                 connector->new_encoder =
10094                         to_intel_encoder(config->save_connector_encoders[count++]);
10095         }
10096 }
10097
10098 static bool
10099 is_crtc_connector_off(struct drm_mode_set *set)
10100 {
10101         int i;
10102
10103         if (set->num_connectors == 0)
10104                 return false;
10105
10106         if (WARN_ON(set->connectors == NULL))
10107                 return false;
10108
10109         for (i = 0; i < set->num_connectors; i++)
10110                 if (set->connectors[i]->encoder &&
10111                     set->connectors[i]->encoder->crtc == set->crtc &&
10112                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
10113                         return true;
10114
10115         return false;
10116 }
10117
10118 static void
10119 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
10120                                       struct intel_set_config *config)
10121 {
10122
10123         /* We should be able to check here if the fb has the same properties
10124          * and then just flip_or_move it */
10125         if (is_crtc_connector_off(set)) {
10126                 config->mode_changed = true;
10127         } else if (set->crtc->primary->fb != set->fb) {
10128                 /* If we have no fb then treat it as a full mode set */
10129                 if (set->crtc->primary->fb == NULL) {
10130                         struct intel_crtc *intel_crtc =
10131                                 to_intel_crtc(set->crtc);
10132
10133                         if (intel_crtc->active && i915.fastboot) {
10134                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
10135                                 config->fb_changed = true;
10136                         } else {
10137                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
10138                                 config->mode_changed = true;
10139                         }
10140                 } else if (set->fb == NULL) {
10141                         config->mode_changed = true;
10142                 } else if (set->fb->pixel_format !=
10143                            set->crtc->primary->fb->pixel_format) {
10144                         config->mode_changed = true;
10145                 } else {
10146                         config->fb_changed = true;
10147                 }
10148         }
10149
10150         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
10151                 config->fb_changed = true;
10152
10153         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
10154                 DRM_DEBUG_KMS("modes are different, full mode set\n");
10155                 drm_mode_debug_printmodeline(&set->crtc->mode);
10156                 drm_mode_debug_printmodeline(set->mode);
10157                 config->mode_changed = true;
10158         }
10159
10160         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
10161                         set->crtc->base.id, config->mode_changed, config->fb_changed);
10162 }
10163
10164 static int
10165 intel_modeset_stage_output_state(struct drm_device *dev,
10166                                  struct drm_mode_set *set,
10167                                  struct intel_set_config *config)
10168 {
10169         struct intel_connector *connector;
10170         struct intel_encoder *encoder;
10171         struct intel_crtc *crtc;
10172         int ro;
10173
10174         /* The upper layers ensure that we either disable a crtc or have a list
10175          * of connectors. For paranoia, double-check this. */
10176         WARN_ON(!set->fb && (set->num_connectors != 0));
10177         WARN_ON(set->fb && (set->num_connectors == 0));
10178
10179         list_for_each_entry(connector, &dev->mode_config.connector_list,
10180                             base.head) {
10181                 /* Otherwise traverse passed in connector list and get encoders
10182                  * for them. */
10183                 for (ro = 0; ro < set->num_connectors; ro++) {
10184                         if (set->connectors[ro] == &connector->base) {
10185                                 connector->new_encoder = connector->encoder;
10186                                 break;
10187                         }
10188                 }
10189
10190                 /* If we disable the crtc, disable all its connectors. Also, if
10191                  * the connector is on the changing crtc but not on the new
10192                  * connector list, disable it. */
10193                 if ((!set->fb || ro == set->num_connectors) &&
10194                     connector->base.encoder &&
10195                     connector->base.encoder->crtc == set->crtc) {
10196                         connector->new_encoder = NULL;
10197
10198                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
10199                                 connector->base.base.id,
10200                                 drm_get_connector_name(&connector->base));
10201                 }
10202
10203
10204                 if (&connector->new_encoder->base != connector->base.encoder) {
10205                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
10206                         config->mode_changed = true;
10207                 }
10208         }
10209         /* connector->new_encoder is now updated for all connectors. */
10210
10211         /* Update crtc of enabled connectors. */
10212         list_for_each_entry(connector, &dev->mode_config.connector_list,
10213                             base.head) {
10214                 struct drm_crtc *new_crtc;
10215
10216                 if (!connector->new_encoder)
10217                         continue;
10218
10219                 new_crtc = connector->new_encoder->base.crtc;
10220
10221                 for (ro = 0; ro < set->num_connectors; ro++) {
10222                         if (set->connectors[ro] == &connector->base)
10223                                 new_crtc = set->crtc;
10224                 }
10225
10226                 /* Make sure the new CRTC will work with the encoder */
10227                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
10228                                          new_crtc)) {
10229                         return -EINVAL;
10230                 }
10231                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
10232
10233                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
10234                         connector->base.base.id,
10235                         drm_get_connector_name(&connector->base),
10236                         new_crtc->base.id);
10237         }
10238
10239         /* Check for any encoders that needs to be disabled. */
10240         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10241                             base.head) {
10242                 int num_connectors = 0;
10243                 list_for_each_entry(connector,
10244                                     &dev->mode_config.connector_list,
10245                                     base.head) {
10246                         if (connector->new_encoder == encoder) {
10247                                 WARN_ON(!connector->new_encoder->new_crtc);
10248                                 num_connectors++;
10249                         }
10250                 }
10251
10252                 if (num_connectors == 0)
10253                         encoder->new_crtc = NULL;
10254                 else if (num_connectors > 1)
10255                         return -EINVAL;
10256
10257                 /* Only now check for crtc changes so we don't miss encoders
10258                  * that will be disabled. */
10259                 if (&encoder->new_crtc->base != encoder->base.crtc) {
10260                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
10261                         config->mode_changed = true;
10262                 }
10263         }
10264         /* Now we've also updated encoder->new_crtc for all encoders. */
10265
10266         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10267                             base.head) {
10268                 crtc->new_enabled = false;
10269
10270                 list_for_each_entry(encoder,
10271                                     &dev->mode_config.encoder_list,
10272                                     base.head) {
10273                         if (encoder->new_crtc == crtc) {
10274                                 crtc->new_enabled = true;
10275                                 break;
10276                         }
10277                 }
10278
10279                 if (crtc->new_enabled != crtc->base.enabled) {
10280                         DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
10281                                       crtc->new_enabled ? "en" : "dis");
10282                         config->mode_changed = true;
10283                 }
10284
10285                 if (crtc->new_enabled)
10286                         crtc->new_config = &crtc->config;
10287                 else
10288                         crtc->new_config = NULL;
10289         }
10290
10291         return 0;
10292 }
10293
10294 static void disable_crtc_nofb(struct intel_crtc *crtc)
10295 {
10296         struct drm_device *dev = crtc->base.dev;
10297         struct intel_encoder *encoder;
10298         struct intel_connector *connector;
10299
10300         DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
10301                       pipe_name(crtc->pipe));
10302
10303         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10304                 if (connector->new_encoder &&
10305                     connector->new_encoder->new_crtc == crtc)
10306                         connector->new_encoder = NULL;
10307         }
10308
10309         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10310                 if (encoder->new_crtc == crtc)
10311                         encoder->new_crtc = NULL;
10312         }
10313
10314         crtc->new_enabled = false;
10315         crtc->new_config = NULL;
10316 }
10317
10318 static int intel_crtc_set_config(struct drm_mode_set *set)
10319 {
10320         struct drm_device *dev;
10321         struct drm_mode_set save_set;
10322         struct intel_set_config *config;
10323         int ret;
10324
10325         BUG_ON(!set);
10326         BUG_ON(!set->crtc);
10327         BUG_ON(!set->crtc->helper_private);
10328
10329         /* Enforce sane interface api - has been abused by the fb helper. */
10330         BUG_ON(!set->mode && set->fb);
10331         BUG_ON(set->fb && set->num_connectors == 0);
10332
10333         if (set->fb) {
10334                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
10335                                 set->crtc->base.id, set->fb->base.id,
10336                                 (int)set->num_connectors, set->x, set->y);
10337         } else {
10338                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
10339         }
10340
10341         dev = set->crtc->dev;
10342
10343         ret = -ENOMEM;
10344         config = kzalloc(sizeof(*config), GFP_KERNEL);
10345         if (!config)
10346                 goto out_config;
10347
10348         ret = intel_set_config_save_state(dev, config);
10349         if (ret)
10350                 goto out_config;
10351
10352         save_set.crtc = set->crtc;
10353         save_set.mode = &set->crtc->mode;
10354         save_set.x = set->crtc->x;
10355         save_set.y = set->crtc->y;
10356         save_set.fb = set->crtc->primary->fb;
10357
10358         /* Compute whether we need a full modeset, only an fb base update or no
10359          * change at all. In the future we might also check whether only the
10360          * mode changed, e.g. for LVDS where we only change the panel fitter in
10361          * such cases. */
10362         intel_set_config_compute_mode_changes(set, config);
10363
10364         ret = intel_modeset_stage_output_state(dev, set, config);
10365         if (ret)
10366                 goto fail;
10367
10368         if (config->mode_changed) {
10369                 ret = intel_set_mode(set->crtc, set->mode,
10370                                      set->x, set->y, set->fb);
10371         } else if (config->fb_changed) {
10372                 intel_crtc_wait_for_pending_flips(set->crtc);
10373
10374                 ret = intel_pipe_set_base(set->crtc,
10375                                           set->x, set->y, set->fb);
10376                 /*
10377                  * In the fastboot case this may be our only check of the
10378                  * state after boot.  It would be better to only do it on
10379                  * the first update, but we don't have a nice way of doing that
10380                  * (and really, set_config isn't used much for high freq page
10381                  * flipping, so increasing its cost here shouldn't be a big
10382                  * deal).
10383                  */
10384                 if (i915.fastboot && ret == 0)
10385                         intel_modeset_check_state(set->crtc->dev);
10386         }
10387
10388         if (ret) {
10389                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
10390                               set->crtc->base.id, ret);
10391 fail:
10392                 intel_set_config_restore_state(dev, config);
10393
10394                 /*
10395                  * HACK: if the pipe was on, but we didn't have a framebuffer,
10396                  * force the pipe off to avoid oopsing in the modeset code
10397                  * due to fb==NULL. This should only happen during boot since
10398                  * we don't yet reconstruct the FB from the hardware state.
10399                  */
10400                 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
10401                         disable_crtc_nofb(to_intel_crtc(save_set.crtc));
10402
10403                 /* Try to restore the config */
10404                 if (config->mode_changed &&
10405                     intel_set_mode(save_set.crtc, save_set.mode,
10406                                    save_set.x, save_set.y, save_set.fb))
10407                         DRM_ERROR("failed to restore config after modeset failure\n");
10408         }
10409
10410 out_config:
10411         intel_set_config_free(config);
10412         return ret;
10413 }
10414
10415 static const struct drm_crtc_funcs intel_crtc_funcs = {
10416         .cursor_set = intel_crtc_cursor_set,
10417         .cursor_move = intel_crtc_cursor_move,
10418         .gamma_set = intel_crtc_gamma_set,
10419         .set_config = intel_crtc_set_config,
10420         .destroy = intel_crtc_destroy,
10421         .page_flip = intel_crtc_page_flip,
10422 };
10423
10424 static void intel_cpu_pll_init(struct drm_device *dev)
10425 {
10426         if (HAS_DDI(dev))
10427                 intel_ddi_pll_init(dev);
10428 }
10429
10430 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
10431                                       struct intel_shared_dpll *pll,
10432                                       struct intel_dpll_hw_state *hw_state)
10433 {
10434         uint32_t val;
10435
10436         val = I915_READ(PCH_DPLL(pll->id));
10437         hw_state->dpll = val;
10438         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
10439         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
10440
10441         return val & DPLL_VCO_ENABLE;
10442 }
10443
10444 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
10445                                   struct intel_shared_dpll *pll)
10446 {
10447         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
10448         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
10449 }
10450
10451 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
10452                                 struct intel_shared_dpll *pll)
10453 {
10454         /* PCH refclock must be enabled first */
10455         ibx_assert_pch_refclk_enabled(dev_priv);
10456
10457         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10458
10459         /* Wait for the clocks to stabilize. */
10460         POSTING_READ(PCH_DPLL(pll->id));
10461         udelay(150);
10462
10463         /* The pixel multiplier can only be updated once the
10464          * DPLL is enabled and the clocks are stable.
10465          *
10466          * So write it again.
10467          */
10468         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10469         POSTING_READ(PCH_DPLL(pll->id));
10470         udelay(200);
10471 }
10472
10473 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
10474                                  struct intel_shared_dpll *pll)
10475 {
10476         struct drm_device *dev = dev_priv->dev;
10477         struct intel_crtc *crtc;
10478
10479         /* Make sure no transcoder isn't still depending on us. */
10480         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
10481                 if (intel_crtc_to_shared_dpll(crtc) == pll)
10482                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
10483         }
10484
10485         I915_WRITE(PCH_DPLL(pll->id), 0);
10486         POSTING_READ(PCH_DPLL(pll->id));
10487         udelay(200);
10488 }
10489
10490 static char *ibx_pch_dpll_names[] = {
10491         "PCH DPLL A",
10492         "PCH DPLL B",
10493 };
10494
10495 static void ibx_pch_dpll_init(struct drm_device *dev)
10496 {
10497         struct drm_i915_private *dev_priv = dev->dev_private;
10498         int i;
10499
10500         dev_priv->num_shared_dpll = 2;
10501
10502         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10503                 dev_priv->shared_dplls[i].id = i;
10504                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
10505                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
10506                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
10507                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
10508                 dev_priv->shared_dplls[i].get_hw_state =
10509                         ibx_pch_dpll_get_hw_state;
10510         }
10511 }
10512
10513 static void intel_shared_dpll_init(struct drm_device *dev)
10514 {
10515         struct drm_i915_private *dev_priv = dev->dev_private;
10516
10517         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
10518                 ibx_pch_dpll_init(dev);
10519         else
10520                 dev_priv->num_shared_dpll = 0;
10521
10522         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
10523 }
10524
10525 static void intel_crtc_init(struct drm_device *dev, int pipe)
10526 {
10527         struct drm_i915_private *dev_priv = dev->dev_private;
10528         struct intel_crtc *intel_crtc;
10529         int i;
10530
10531         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
10532         if (intel_crtc == NULL)
10533                 return;
10534
10535         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
10536
10537         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
10538         for (i = 0; i < 256; i++) {
10539                 intel_crtc->lut_r[i] = i;
10540                 intel_crtc->lut_g[i] = i;
10541                 intel_crtc->lut_b[i] = i;
10542         }
10543
10544         /*
10545          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
10546          * is hooked to plane B. Hence we want plane A feeding pipe B.
10547          */
10548         intel_crtc->pipe = pipe;
10549         intel_crtc->plane = pipe;
10550         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
10551                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
10552                 intel_crtc->plane = !pipe;
10553         }
10554
10555         init_waitqueue_head(&intel_crtc->vbl_wait);
10556
10557         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
10558                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
10559         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
10560         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
10561
10562         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
10563 }
10564
10565 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
10566 {
10567         struct drm_encoder *encoder = connector->base.encoder;
10568
10569         WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex));
10570
10571         if (!encoder)
10572                 return INVALID_PIPE;
10573
10574         return to_intel_crtc(encoder->crtc)->pipe;
10575 }
10576
10577 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
10578                                 struct drm_file *file)
10579 {
10580         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
10581         struct drm_mode_object *drmmode_obj;
10582         struct intel_crtc *crtc;
10583
10584         if (!drm_core_check_feature(dev, DRIVER_MODESET))
10585                 return -ENODEV;
10586
10587         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
10588                         DRM_MODE_OBJECT_CRTC);
10589
10590         if (!drmmode_obj) {
10591                 DRM_ERROR("no such CRTC id\n");
10592                 return -ENOENT;
10593         }
10594
10595         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
10596         pipe_from_crtc_id->pipe = crtc->pipe;
10597
10598         return 0;
10599 }
10600
10601 static int intel_encoder_clones(struct intel_encoder *encoder)
10602 {
10603         struct drm_device *dev = encoder->base.dev;
10604         struct intel_encoder *source_encoder;
10605         int index_mask = 0;
10606         int entry = 0;
10607
10608         list_for_each_entry(source_encoder,
10609                             &dev->mode_config.encoder_list, base.head) {
10610                 if (encoders_cloneable(encoder, source_encoder))
10611                         index_mask |= (1 << entry);
10612
10613                 entry++;
10614         }
10615
10616         return index_mask;
10617 }
10618
10619 static bool has_edp_a(struct drm_device *dev)
10620 {
10621         struct drm_i915_private *dev_priv = dev->dev_private;
10622
10623         if (!IS_MOBILE(dev))
10624                 return false;
10625
10626         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
10627                 return false;
10628
10629         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
10630                 return false;
10631
10632         return true;
10633 }
10634
10635 const char *intel_output_name(int output)
10636 {
10637         static const char *names[] = {
10638                 [INTEL_OUTPUT_UNUSED] = "Unused",
10639                 [INTEL_OUTPUT_ANALOG] = "Analog",
10640                 [INTEL_OUTPUT_DVO] = "DVO",
10641                 [INTEL_OUTPUT_SDVO] = "SDVO",
10642                 [INTEL_OUTPUT_LVDS] = "LVDS",
10643                 [INTEL_OUTPUT_TVOUT] = "TV",
10644                 [INTEL_OUTPUT_HDMI] = "HDMI",
10645                 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
10646                 [INTEL_OUTPUT_EDP] = "eDP",
10647                 [INTEL_OUTPUT_DSI] = "DSI",
10648                 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
10649         };
10650
10651         if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
10652                 return "Invalid";
10653
10654         return names[output];
10655 }
10656
10657 static void intel_setup_outputs(struct drm_device *dev)
10658 {
10659         struct drm_i915_private *dev_priv = dev->dev_private;
10660         struct intel_encoder *encoder;
10661         bool dpd_is_edp = false;
10662
10663         intel_lvds_init(dev);
10664
10665         if (!IS_ULT(dev))
10666                 intel_crt_init(dev);
10667
10668         if (HAS_DDI(dev)) {
10669                 int found;
10670
10671                 /* Haswell uses DDI functions to detect digital outputs */
10672                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
10673                 /* DDI A only supports eDP */
10674                 if (found)
10675                         intel_ddi_init(dev, PORT_A);
10676
10677                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
10678                  * register */
10679                 found = I915_READ(SFUSE_STRAP);
10680
10681                 if (found & SFUSE_STRAP_DDIB_DETECTED)
10682                         intel_ddi_init(dev, PORT_B);
10683                 if (found & SFUSE_STRAP_DDIC_DETECTED)
10684                         intel_ddi_init(dev, PORT_C);
10685                 if (found & SFUSE_STRAP_DDID_DETECTED)
10686                         intel_ddi_init(dev, PORT_D);
10687         } else if (HAS_PCH_SPLIT(dev)) {
10688                 int found;
10689                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
10690
10691                 if (has_edp_a(dev))
10692                         intel_dp_init(dev, DP_A, PORT_A);
10693
10694                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
10695                         /* PCH SDVOB multiplex with HDMIB */
10696                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
10697                         if (!found)
10698                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
10699                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
10700                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
10701                 }
10702
10703                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
10704                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
10705
10706                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
10707                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
10708
10709                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
10710                         intel_dp_init(dev, PCH_DP_C, PORT_C);
10711
10712                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
10713                         intel_dp_init(dev, PCH_DP_D, PORT_D);
10714         } else if (IS_VALLEYVIEW(dev)) {
10715                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
10716                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
10717                                         PORT_B);
10718                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
10719                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
10720                 }
10721
10722                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
10723                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
10724                                         PORT_C);
10725                         if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
10726                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
10727                 }
10728
10729                 intel_dsi_init(dev);
10730         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
10731                 bool found = false;
10732
10733                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10734                         DRM_DEBUG_KMS("probing SDVOB\n");
10735                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
10736                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
10737                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
10738                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
10739                         }
10740
10741                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
10742                                 intel_dp_init(dev, DP_B, PORT_B);
10743                 }
10744
10745                 /* Before G4X SDVOC doesn't have its own detect register */
10746
10747                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10748                         DRM_DEBUG_KMS("probing SDVOC\n");
10749                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
10750                 }
10751
10752                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
10753
10754                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
10755                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
10756                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
10757                         }
10758                         if (SUPPORTS_INTEGRATED_DP(dev))
10759                                 intel_dp_init(dev, DP_C, PORT_C);
10760                 }
10761
10762                 if (SUPPORTS_INTEGRATED_DP(dev) &&
10763                     (I915_READ(DP_D) & DP_DETECTED))
10764                         intel_dp_init(dev, DP_D, PORT_D);
10765         } else if (IS_GEN2(dev))
10766                 intel_dvo_init(dev);
10767
10768         if (SUPPORTS_TV(dev))
10769                 intel_tv_init(dev);
10770
10771         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10772                 encoder->base.possible_crtcs = encoder->crtc_mask;
10773                 encoder->base.possible_clones =
10774                         intel_encoder_clones(encoder);
10775         }
10776
10777         intel_init_pch_refclk(dev);
10778
10779         drm_helper_move_panel_connectors_to_head(dev);
10780 }
10781
10782 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
10783 {
10784         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10785
10786         drm_framebuffer_cleanup(fb);
10787         WARN_ON(!intel_fb->obj->framebuffer_references--);
10788         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
10789         kfree(intel_fb);
10790 }
10791
10792 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
10793                                                 struct drm_file *file,
10794                                                 unsigned int *handle)
10795 {
10796         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10797         struct drm_i915_gem_object *obj = intel_fb->obj;
10798
10799         return drm_gem_handle_create(file, &obj->base, handle);
10800 }
10801
10802 static const struct drm_framebuffer_funcs intel_fb_funcs = {
10803         .destroy = intel_user_framebuffer_destroy,
10804         .create_handle = intel_user_framebuffer_create_handle,
10805 };
10806
10807 static int intel_framebuffer_init(struct drm_device *dev,
10808                                   struct intel_framebuffer *intel_fb,
10809                                   struct drm_mode_fb_cmd2 *mode_cmd,
10810                                   struct drm_i915_gem_object *obj)
10811 {
10812         int aligned_height;
10813         int pitch_limit;
10814         int ret;
10815
10816         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
10817
10818         if (obj->tiling_mode == I915_TILING_Y) {
10819                 DRM_DEBUG("hardware does not support tiling Y\n");
10820                 return -EINVAL;
10821         }
10822
10823         if (mode_cmd->pitches[0] & 63) {
10824                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
10825                           mode_cmd->pitches[0]);
10826                 return -EINVAL;
10827         }
10828
10829         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
10830                 pitch_limit = 32*1024;
10831         } else if (INTEL_INFO(dev)->gen >= 4) {
10832                 if (obj->tiling_mode)
10833                         pitch_limit = 16*1024;
10834                 else
10835                         pitch_limit = 32*1024;
10836         } else if (INTEL_INFO(dev)->gen >= 3) {
10837                 if (obj->tiling_mode)
10838                         pitch_limit = 8*1024;
10839                 else
10840                         pitch_limit = 16*1024;
10841         } else
10842                 /* XXX DSPC is limited to 4k tiled */
10843                 pitch_limit = 8*1024;
10844
10845         if (mode_cmd->pitches[0] > pitch_limit) {
10846                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10847                           obj->tiling_mode ? "tiled" : "linear",
10848                           mode_cmd->pitches[0], pitch_limit);
10849                 return -EINVAL;
10850         }
10851
10852         if (obj->tiling_mode != I915_TILING_NONE &&
10853             mode_cmd->pitches[0] != obj->stride) {
10854                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10855                           mode_cmd->pitches[0], obj->stride);
10856                 return -EINVAL;
10857         }
10858
10859         /* Reject formats not supported by any plane early. */
10860         switch (mode_cmd->pixel_format) {
10861         case DRM_FORMAT_C8:
10862         case DRM_FORMAT_RGB565:
10863         case DRM_FORMAT_XRGB8888:
10864         case DRM_FORMAT_ARGB8888:
10865                 break;
10866         case DRM_FORMAT_XRGB1555:
10867         case DRM_FORMAT_ARGB1555:
10868                 if (INTEL_INFO(dev)->gen > 3) {
10869                         DRM_DEBUG("unsupported pixel format: %s\n",
10870                                   drm_get_format_name(mode_cmd->pixel_format));
10871                         return -EINVAL;
10872                 }
10873                 break;
10874         case DRM_FORMAT_XBGR8888:
10875         case DRM_FORMAT_ABGR8888:
10876         case DRM_FORMAT_XRGB2101010:
10877         case DRM_FORMAT_ARGB2101010:
10878         case DRM_FORMAT_XBGR2101010:
10879         case DRM_FORMAT_ABGR2101010:
10880                 if (INTEL_INFO(dev)->gen < 4) {
10881                         DRM_DEBUG("unsupported pixel format: %s\n",
10882                                   drm_get_format_name(mode_cmd->pixel_format));
10883                         return -EINVAL;
10884                 }
10885                 break;
10886         case DRM_FORMAT_YUYV:
10887         case DRM_FORMAT_UYVY:
10888         case DRM_FORMAT_YVYU:
10889         case DRM_FORMAT_VYUY:
10890                 if (INTEL_INFO(dev)->gen < 5) {
10891                         DRM_DEBUG("unsupported pixel format: %s\n",
10892                                   drm_get_format_name(mode_cmd->pixel_format));
10893                         return -EINVAL;
10894                 }
10895                 break;
10896         default:
10897                 DRM_DEBUG("unsupported pixel format: %s\n",
10898                           drm_get_format_name(mode_cmd->pixel_format));
10899                 return -EINVAL;
10900         }
10901
10902         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10903         if (mode_cmd->offsets[0] != 0)
10904                 return -EINVAL;
10905
10906         aligned_height = intel_align_height(dev, mode_cmd->height,
10907                                             obj->tiling_mode);
10908         /* FIXME drm helper for size checks (especially planar formats)? */
10909         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
10910                 return -EINVAL;
10911
10912         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
10913         intel_fb->obj = obj;
10914         intel_fb->obj->framebuffer_references++;
10915
10916         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
10917         if (ret) {
10918                 DRM_ERROR("framebuffer init failed %d\n", ret);
10919                 return ret;
10920         }
10921
10922         return 0;
10923 }
10924
10925 static struct drm_framebuffer *
10926 intel_user_framebuffer_create(struct drm_device *dev,
10927                               struct drm_file *filp,
10928                               struct drm_mode_fb_cmd2 *mode_cmd)
10929 {
10930         struct drm_i915_gem_object *obj;
10931
10932         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10933                                                 mode_cmd->handles[0]));
10934         if (&obj->base == NULL)
10935                 return ERR_PTR(-ENOENT);
10936
10937         return intel_framebuffer_create(dev, mode_cmd, obj);
10938 }
10939
10940 #ifndef CONFIG_DRM_I915_FBDEV
10941 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
10942 {
10943 }
10944 #endif
10945
10946 static const struct drm_mode_config_funcs intel_mode_funcs = {
10947         .fb_create = intel_user_framebuffer_create,
10948         .output_poll_changed = intel_fbdev_output_poll_changed,
10949 };
10950
10951 /* Set up chip specific display functions */
10952 static void intel_init_display(struct drm_device *dev)
10953 {
10954         struct drm_i915_private *dev_priv = dev->dev_private;
10955
10956         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10957                 dev_priv->display.find_dpll = g4x_find_best_dpll;
10958         else if (IS_VALLEYVIEW(dev))
10959                 dev_priv->display.find_dpll = vlv_find_best_dpll;
10960         else if (IS_PINEVIEW(dev))
10961                 dev_priv->display.find_dpll = pnv_find_best_dpll;
10962         else
10963                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10964
10965         if (HAS_DDI(dev)) {
10966                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
10967                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
10968                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
10969                 dev_priv->display.crtc_enable = haswell_crtc_enable;
10970                 dev_priv->display.crtc_disable = haswell_crtc_disable;
10971                 dev_priv->display.off = haswell_crtc_off;
10972                 dev_priv->display.update_primary_plane =
10973                         ironlake_update_primary_plane;
10974         } else if (HAS_PCH_SPLIT(dev)) {
10975                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
10976                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
10977                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
10978                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10979                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
10980                 dev_priv->display.off = ironlake_crtc_off;
10981                 dev_priv->display.update_primary_plane =
10982                         ironlake_update_primary_plane;
10983         } else if (IS_VALLEYVIEW(dev)) {
10984                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10985                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
10986                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10987                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
10988                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10989                 dev_priv->display.off = i9xx_crtc_off;
10990                 dev_priv->display.update_primary_plane =
10991                         i9xx_update_primary_plane;
10992         } else {
10993                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10994                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
10995                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10996                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
10997                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10998                 dev_priv->display.off = i9xx_crtc_off;
10999                 dev_priv->display.update_primary_plane =
11000                         i9xx_update_primary_plane;
11001         }
11002
11003         /* Returns the core display clock speed */
11004         if (IS_VALLEYVIEW(dev))
11005                 dev_priv->display.get_display_clock_speed =
11006                         valleyview_get_display_clock_speed;
11007         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
11008                 dev_priv->display.get_display_clock_speed =
11009                         i945_get_display_clock_speed;
11010         else if (IS_I915G(dev))
11011                 dev_priv->display.get_display_clock_speed =
11012                         i915_get_display_clock_speed;
11013         else if (IS_I945GM(dev) || IS_845G(dev))
11014                 dev_priv->display.get_display_clock_speed =
11015                         i9xx_misc_get_display_clock_speed;
11016         else if (IS_PINEVIEW(dev))
11017                 dev_priv->display.get_display_clock_speed =
11018                         pnv_get_display_clock_speed;
11019         else if (IS_I915GM(dev))
11020                 dev_priv->display.get_display_clock_speed =
11021                         i915gm_get_display_clock_speed;
11022         else if (IS_I865G(dev))
11023                 dev_priv->display.get_display_clock_speed =
11024                         i865_get_display_clock_speed;
11025         else if (IS_I85X(dev))
11026                 dev_priv->display.get_display_clock_speed =
11027                         i855_get_display_clock_speed;
11028         else /* 852, 830 */
11029                 dev_priv->display.get_display_clock_speed =
11030                         i830_get_display_clock_speed;
11031
11032         if (HAS_PCH_SPLIT(dev)) {
11033                 if (IS_GEN5(dev)) {
11034                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
11035                         dev_priv->display.write_eld = ironlake_write_eld;
11036                 } else if (IS_GEN6(dev)) {
11037                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
11038                         dev_priv->display.write_eld = ironlake_write_eld;
11039                         dev_priv->display.modeset_global_resources =
11040                                 snb_modeset_global_resources;
11041                 } else if (IS_IVYBRIDGE(dev)) {
11042                         /* FIXME: detect B0+ stepping and use auto training */
11043                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
11044                         dev_priv->display.write_eld = ironlake_write_eld;
11045                         dev_priv->display.modeset_global_resources =
11046                                 ivb_modeset_global_resources;
11047                 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
11048                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
11049                         dev_priv->display.write_eld = haswell_write_eld;
11050                         dev_priv->display.modeset_global_resources =
11051                                 haswell_modeset_global_resources;
11052                 }
11053         } else if (IS_G4X(dev)) {
11054                 dev_priv->display.write_eld = g4x_write_eld;
11055         } else if (IS_VALLEYVIEW(dev)) {
11056                 dev_priv->display.modeset_global_resources =
11057                         valleyview_modeset_global_resources;
11058                 dev_priv->display.write_eld = ironlake_write_eld;
11059         }
11060
11061         /* Default just returns -ENODEV to indicate unsupported */
11062         dev_priv->display.queue_flip = intel_default_queue_flip;
11063
11064         switch (INTEL_INFO(dev)->gen) {
11065         case 2:
11066                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
11067                 break;
11068
11069         case 3:
11070                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
11071                 break;
11072
11073         case 4:
11074         case 5:
11075                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
11076                 break;
11077
11078         case 6:
11079                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
11080                 break;
11081         case 7:
11082         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
11083                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
11084                 break;
11085         }
11086
11087         intel_panel_init_backlight_funcs(dev);
11088 }
11089
11090 /*
11091  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
11092  * resume, or other times.  This quirk makes sure that's the case for
11093  * affected systems.
11094  */
11095 static void quirk_pipea_force(struct drm_device *dev)
11096 {
11097         struct drm_i915_private *dev_priv = dev->dev_private;
11098
11099         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
11100         DRM_INFO("applying pipe a force quirk\n");
11101 }
11102
11103 /*
11104  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
11105  */
11106 static void quirk_ssc_force_disable(struct drm_device *dev)
11107 {
11108         struct drm_i915_private *dev_priv = dev->dev_private;
11109         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
11110         DRM_INFO("applying lvds SSC disable quirk\n");
11111 }
11112
11113 /*
11114  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
11115  * brightness value
11116  */
11117 static void quirk_invert_brightness(struct drm_device *dev)
11118 {
11119         struct drm_i915_private *dev_priv = dev->dev_private;
11120         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
11121         DRM_INFO("applying inverted panel brightness quirk\n");
11122 }
11123
11124 struct intel_quirk {
11125         int device;
11126         int subsystem_vendor;
11127         int subsystem_device;
11128         void (*hook)(struct drm_device *dev);
11129 };
11130
11131 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
11132 struct intel_dmi_quirk {
11133         void (*hook)(struct drm_device *dev);
11134         const struct dmi_system_id (*dmi_id_list)[];
11135 };
11136
11137 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
11138 {
11139         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
11140         return 1;
11141 }
11142
11143 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
11144         {
11145                 .dmi_id_list = &(const struct dmi_system_id[]) {
11146                         {
11147                                 .callback = intel_dmi_reverse_brightness,
11148                                 .ident = "NCR Corporation",
11149                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
11150                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
11151                                 },
11152                         },
11153                         { }  /* terminating entry */
11154                 },
11155                 .hook = quirk_invert_brightness,
11156         },
11157 };
11158
11159 static struct intel_quirk intel_quirks[] = {
11160         /* HP Mini needs pipe A force quirk (LP: #322104) */
11161         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
11162
11163         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
11164         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
11165
11166         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
11167         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
11168
11169         /* 830 needs to leave pipe A & dpll A up */
11170         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
11171
11172         /* Lenovo U160 cannot use SSC on LVDS */
11173         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
11174
11175         /* Sony Vaio Y cannot use SSC on LVDS */
11176         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
11177
11178         /* Acer Aspire 5734Z must invert backlight brightness */
11179         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
11180
11181         /* Acer/eMachines G725 */
11182         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
11183
11184         /* Acer/eMachines e725 */
11185         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
11186
11187         /* Acer/Packard Bell NCL20 */
11188         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
11189
11190         /* Acer Aspire 4736Z */
11191         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
11192
11193         /* Acer Aspire 5336 */
11194         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
11195 };
11196
11197 static void intel_init_quirks(struct drm_device *dev)
11198 {
11199         struct pci_dev *d = dev->pdev;
11200         int i;
11201
11202         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
11203                 struct intel_quirk *q = &intel_quirks[i];
11204
11205                 if (d->device == q->device &&
11206                     (d->subsystem_vendor == q->subsystem_vendor ||
11207                      q->subsystem_vendor == PCI_ANY_ID) &&
11208                     (d->subsystem_device == q->subsystem_device ||
11209                      q->subsystem_device == PCI_ANY_ID))
11210                         q->hook(dev);
11211         }
11212         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
11213                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
11214                         intel_dmi_quirks[i].hook(dev);
11215         }
11216 }
11217
11218 /* Disable the VGA plane that we never use */
11219 static void i915_disable_vga(struct drm_device *dev)
11220 {
11221         struct drm_i915_private *dev_priv = dev->dev_private;
11222         u8 sr1;
11223         u32 vga_reg = i915_vgacntrl_reg(dev);
11224
11225         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
11226         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
11227         outb(SR01, VGA_SR_INDEX);
11228         sr1 = inb(VGA_SR_DATA);
11229         outb(sr1 | 1<<5, VGA_SR_DATA);
11230         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
11231         udelay(300);
11232
11233         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
11234         POSTING_READ(vga_reg);
11235 }
11236
11237 void intel_modeset_init_hw(struct drm_device *dev)
11238 {
11239         intel_prepare_ddi(dev);
11240
11241         intel_init_clock_gating(dev);
11242
11243         intel_reset_dpio(dev);
11244
11245         intel_enable_gt_powersave(dev);
11246 }
11247
11248 void intel_modeset_suspend_hw(struct drm_device *dev)
11249 {
11250         intel_suspend_hw(dev);
11251 }
11252
11253 void intel_modeset_init(struct drm_device *dev)
11254 {
11255         struct drm_i915_private *dev_priv = dev->dev_private;
11256         int sprite, ret;
11257         enum pipe pipe;
11258         struct intel_crtc *crtc;
11259
11260         drm_mode_config_init(dev);
11261
11262         dev->mode_config.min_width = 0;
11263         dev->mode_config.min_height = 0;
11264
11265         dev->mode_config.preferred_depth = 24;
11266         dev->mode_config.prefer_shadow = 1;
11267
11268         dev->mode_config.funcs = &intel_mode_funcs;
11269
11270         intel_init_quirks(dev);
11271
11272         intel_init_pm(dev);
11273
11274         if (INTEL_INFO(dev)->num_pipes == 0)
11275                 return;
11276
11277         intel_init_display(dev);
11278
11279         if (IS_GEN2(dev)) {
11280                 dev->mode_config.max_width = 2048;
11281                 dev->mode_config.max_height = 2048;
11282         } else if (IS_GEN3(dev)) {
11283                 dev->mode_config.max_width = 4096;
11284                 dev->mode_config.max_height = 4096;
11285         } else {
11286                 dev->mode_config.max_width = 8192;
11287                 dev->mode_config.max_height = 8192;
11288         }
11289
11290         if (IS_GEN2(dev)) {
11291                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
11292                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
11293         } else {
11294                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
11295                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
11296         }
11297
11298         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
11299
11300         DRM_DEBUG_KMS("%d display pipe%s available.\n",
11301                       INTEL_INFO(dev)->num_pipes,
11302                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
11303
11304         for_each_pipe(pipe) {
11305                 intel_crtc_init(dev, pipe);
11306                 for_each_sprite(pipe, sprite) {
11307                         ret = intel_plane_init(dev, pipe, sprite);
11308                         if (ret)
11309                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
11310                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
11311                 }
11312         }
11313
11314         intel_init_dpio(dev);
11315         intel_reset_dpio(dev);
11316
11317         intel_cpu_pll_init(dev);
11318         intel_shared_dpll_init(dev);
11319
11320         /* Just disable it once at startup */
11321         i915_disable_vga(dev);
11322         intel_setup_outputs(dev);
11323
11324         /* Just in case the BIOS is doing something questionable. */
11325         intel_disable_fbc(dev);
11326
11327         mutex_lock(&dev->mode_config.mutex);
11328         intel_modeset_setup_hw_state(dev, false);
11329         mutex_unlock(&dev->mode_config.mutex);
11330
11331         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11332                             base.head) {
11333                 if (!crtc->active)
11334                         continue;
11335
11336                 /*
11337                  * Note that reserving the BIOS fb up front prevents us
11338                  * from stuffing other stolen allocations like the ring
11339                  * on top.  This prevents some ugliness at boot time, and
11340                  * can even allow for smooth boot transitions if the BIOS
11341                  * fb is large enough for the active pipe configuration.
11342                  */
11343                 if (dev_priv->display.get_plane_config) {
11344                         dev_priv->display.get_plane_config(crtc,
11345                                                            &crtc->plane_config);
11346                         /*
11347                          * If the fb is shared between multiple heads, we'll
11348                          * just get the first one.
11349                          */
11350                         intel_find_plane_obj(crtc, &crtc->plane_config);
11351                 }
11352         }
11353 }
11354
11355 static void
11356 intel_connector_break_all_links(struct intel_connector *connector)
11357 {
11358         connector->base.dpms = DRM_MODE_DPMS_OFF;
11359         connector->base.encoder = NULL;
11360         connector->encoder->connectors_active = false;
11361         connector->encoder->base.crtc = NULL;
11362 }
11363
11364 static void intel_enable_pipe_a(struct drm_device *dev)
11365 {
11366         struct intel_connector *connector;
11367         struct drm_connector *crt = NULL;
11368         struct intel_load_detect_pipe load_detect_temp;
11369
11370         /* We can't just switch on the pipe A, we need to set things up with a
11371          * proper mode and output configuration. As a gross hack, enable pipe A
11372          * by enabling the load detect pipe once. */
11373         list_for_each_entry(connector,
11374                             &dev->mode_config.connector_list,
11375                             base.head) {
11376                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
11377                         crt = &connector->base;
11378                         break;
11379                 }
11380         }
11381
11382         if (!crt)
11383                 return;
11384
11385         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
11386                 intel_release_load_detect_pipe(crt, &load_detect_temp);
11387
11388
11389 }
11390
11391 static bool
11392 intel_check_plane_mapping(struct intel_crtc *crtc)
11393 {
11394         struct drm_device *dev = crtc->base.dev;
11395         struct drm_i915_private *dev_priv = dev->dev_private;
11396         u32 reg, val;
11397
11398         if (INTEL_INFO(dev)->num_pipes == 1)
11399                 return true;
11400
11401         reg = DSPCNTR(!crtc->plane);
11402         val = I915_READ(reg);
11403
11404         if ((val & DISPLAY_PLANE_ENABLE) &&
11405             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
11406                 return false;
11407
11408         return true;
11409 }
11410
11411 static void intel_sanitize_crtc(struct intel_crtc *crtc)
11412 {
11413         struct drm_device *dev = crtc->base.dev;
11414         struct drm_i915_private *dev_priv = dev->dev_private;
11415         u32 reg;
11416
11417         /* Clear any frame start delays used for debugging left by the BIOS */
11418         reg = PIPECONF(crtc->config.cpu_transcoder);
11419         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
11420
11421         /* We need to sanitize the plane -> pipe mapping first because this will
11422          * disable the crtc (and hence change the state) if it is wrong. Note
11423          * that gen4+ has a fixed plane -> pipe mapping.  */
11424         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
11425                 struct intel_connector *connector;
11426                 bool plane;
11427
11428                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
11429                               crtc->base.base.id);
11430
11431                 /* Pipe has the wrong plane attached and the plane is active.
11432                  * Temporarily change the plane mapping and disable everything
11433                  * ...  */
11434                 plane = crtc->plane;
11435                 crtc->plane = !plane;
11436                 dev_priv->display.crtc_disable(&crtc->base);
11437                 crtc->plane = plane;
11438
11439                 /* ... and break all links. */
11440                 list_for_each_entry(connector, &dev->mode_config.connector_list,
11441                                     base.head) {
11442                         if (connector->encoder->base.crtc != &crtc->base)
11443                                 continue;
11444
11445                         intel_connector_break_all_links(connector);
11446                 }
11447
11448                 WARN_ON(crtc->active);
11449                 crtc->base.enabled = false;
11450         }
11451
11452         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
11453             crtc->pipe == PIPE_A && !crtc->active) {
11454                 /* BIOS forgot to enable pipe A, this mostly happens after
11455                  * resume. Force-enable the pipe to fix this, the update_dpms
11456                  * call below we restore the pipe to the right state, but leave
11457                  * the required bits on. */
11458                 intel_enable_pipe_a(dev);
11459         }
11460
11461         /* Adjust the state of the output pipe according to whether we
11462          * have active connectors/encoders. */
11463         intel_crtc_update_dpms(&crtc->base);
11464
11465         if (crtc->active != crtc->base.enabled) {
11466                 struct intel_encoder *encoder;
11467
11468                 /* This can happen either due to bugs in the get_hw_state
11469                  * functions or because the pipe is force-enabled due to the
11470                  * pipe A quirk. */
11471                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
11472                               crtc->base.base.id,
11473                               crtc->base.enabled ? "enabled" : "disabled",
11474                               crtc->active ? "enabled" : "disabled");
11475
11476                 crtc->base.enabled = crtc->active;
11477
11478                 /* Because we only establish the connector -> encoder ->
11479                  * crtc links if something is active, this means the
11480                  * crtc is now deactivated. Break the links. connector
11481                  * -> encoder links are only establish when things are
11482                  *  actually up, hence no need to break them. */
11483                 WARN_ON(crtc->active);
11484
11485                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
11486                         WARN_ON(encoder->connectors_active);
11487                         encoder->base.crtc = NULL;
11488                 }
11489         }
11490         if (crtc->active) {
11491                 /*
11492                  * We start out with underrun reporting disabled to avoid races.
11493                  * For correct bookkeeping mark this on active crtcs.
11494                  *
11495                  * No protection against concurrent access is required - at
11496                  * worst a fifo underrun happens which also sets this to false.
11497                  */
11498                 crtc->cpu_fifo_underrun_disabled = true;
11499                 crtc->pch_fifo_underrun_disabled = true;
11500         }
11501 }
11502
11503 static void intel_sanitize_encoder(struct intel_encoder *encoder)
11504 {
11505         struct intel_connector *connector;
11506         struct drm_device *dev = encoder->base.dev;
11507
11508         /* We need to check both for a crtc link (meaning that the
11509          * encoder is active and trying to read from a pipe) and the
11510          * pipe itself being active. */
11511         bool has_active_crtc = encoder->base.crtc &&
11512                 to_intel_crtc(encoder->base.crtc)->active;
11513
11514         if (encoder->connectors_active && !has_active_crtc) {
11515                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
11516                               encoder->base.base.id,
11517                               drm_get_encoder_name(&encoder->base));
11518
11519                 /* Connector is active, but has no active pipe. This is
11520                  * fallout from our resume register restoring. Disable
11521                  * the encoder manually again. */
11522                 if (encoder->base.crtc) {
11523                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
11524                                       encoder->base.base.id,
11525                                       drm_get_encoder_name(&encoder->base));
11526                         encoder->disable(encoder);
11527                 }
11528
11529                 /* Inconsistent output/port/pipe state happens presumably due to
11530                  * a bug in one of the get_hw_state functions. Or someplace else
11531                  * in our code, like the register restore mess on resume. Clamp
11532                  * things to off as a safer default. */
11533                 list_for_each_entry(connector,
11534                                     &dev->mode_config.connector_list,
11535                                     base.head) {
11536                         if (connector->encoder != encoder)
11537                                 continue;
11538
11539                         intel_connector_break_all_links(connector);
11540                 }
11541         }
11542         /* Enabled encoders without active connectors will be fixed in
11543          * the crtc fixup. */
11544 }
11545
11546 void i915_redisable_vga_power_on(struct drm_device *dev)
11547 {
11548         struct drm_i915_private *dev_priv = dev->dev_private;
11549         u32 vga_reg = i915_vgacntrl_reg(dev);
11550
11551         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
11552                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
11553                 i915_disable_vga(dev);
11554         }
11555 }
11556
11557 void i915_redisable_vga(struct drm_device *dev)
11558 {
11559         struct drm_i915_private *dev_priv = dev->dev_private;
11560
11561         /* This function can be called both from intel_modeset_setup_hw_state or
11562          * at a very early point in our resume sequence, where the power well
11563          * structures are not yet restored. Since this function is at a very
11564          * paranoid "someone might have enabled VGA while we were not looking"
11565          * level, just check if the power well is enabled instead of trying to
11566          * follow the "don't touch the power well if we don't need it" policy
11567          * the rest of the driver uses. */
11568         if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
11569                 return;
11570
11571         i915_redisable_vga_power_on(dev);
11572 }
11573
11574 static bool primary_get_hw_state(struct intel_crtc *crtc)
11575 {
11576         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
11577
11578         if (!crtc->active)
11579                 return false;
11580
11581         return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
11582 }
11583
11584 static void intel_modeset_readout_hw_state(struct drm_device *dev)
11585 {
11586         struct drm_i915_private *dev_priv = dev->dev_private;
11587         enum pipe pipe;
11588         struct intel_crtc *crtc;
11589         struct intel_encoder *encoder;
11590         struct intel_connector *connector;
11591         int i;
11592
11593         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11594                             base.head) {
11595                 memset(&crtc->config, 0, sizeof(crtc->config));
11596
11597                 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
11598
11599                 crtc->active = dev_priv->display.get_pipe_config(crtc,
11600                                                                  &crtc->config);
11601
11602                 crtc->base.enabled = crtc->active;
11603                 crtc->primary_enabled = primary_get_hw_state(crtc);
11604
11605                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
11606                               crtc->base.base.id,
11607                               crtc->active ? "enabled" : "disabled");
11608         }
11609
11610         /* FIXME: Smash this into the new shared dpll infrastructure. */
11611         if (HAS_DDI(dev))
11612                 intel_ddi_setup_hw_pll_state(dev);
11613
11614         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11615                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11616
11617                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
11618                 pll->active = 0;
11619                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11620                                     base.head) {
11621                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11622                                 pll->active++;
11623                 }
11624                 pll->refcount = pll->active;
11625
11626                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
11627                               pll->name, pll->refcount, pll->on);
11628         }
11629
11630         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11631                             base.head) {
11632                 pipe = 0;
11633
11634                 if (encoder->get_hw_state(encoder, &pipe)) {
11635                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11636                         encoder->base.crtc = &crtc->base;
11637                         encoder->get_config(encoder, &crtc->config);
11638                 } else {
11639                         encoder->base.crtc = NULL;
11640                 }
11641
11642                 encoder->connectors_active = false;
11643                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
11644                               encoder->base.base.id,
11645                               drm_get_encoder_name(&encoder->base),
11646                               encoder->base.crtc ? "enabled" : "disabled",
11647                               pipe_name(pipe));
11648         }
11649
11650         list_for_each_entry(connector, &dev->mode_config.connector_list,
11651                             base.head) {
11652                 if (connector->get_hw_state(connector)) {
11653                         connector->base.dpms = DRM_MODE_DPMS_ON;
11654                         connector->encoder->connectors_active = true;
11655                         connector->base.encoder = &connector->encoder->base;
11656                 } else {
11657                         connector->base.dpms = DRM_MODE_DPMS_OFF;
11658                         connector->base.encoder = NULL;
11659                 }
11660                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
11661                               connector->base.base.id,
11662                               drm_get_connector_name(&connector->base),
11663                               connector->base.encoder ? "enabled" : "disabled");
11664         }
11665 }
11666
11667 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
11668  * and i915 state tracking structures. */
11669 void intel_modeset_setup_hw_state(struct drm_device *dev,
11670                                   bool force_restore)
11671 {
11672         struct drm_i915_private *dev_priv = dev->dev_private;
11673         enum pipe pipe;
11674         struct intel_crtc *crtc;
11675         struct intel_encoder *encoder;
11676         int i;
11677
11678         intel_modeset_readout_hw_state(dev);
11679
11680         /*
11681          * Now that we have the config, copy it to each CRTC struct
11682          * Note that this could go away if we move to using crtc_config
11683          * checking everywhere.
11684          */
11685         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11686                             base.head) {
11687                 if (crtc->active && i915.fastboot) {
11688                         intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
11689                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
11690                                       crtc->base.base.id);
11691                         drm_mode_debug_printmodeline(&crtc->base.mode);
11692                 }
11693         }
11694
11695         /* HW state is read out, now we need to sanitize this mess. */
11696         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11697                             base.head) {
11698                 intel_sanitize_encoder(encoder);
11699         }
11700
11701         for_each_pipe(pipe) {
11702                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11703                 intel_sanitize_crtc(crtc);
11704                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
11705         }
11706
11707         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11708                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11709
11710                 if (!pll->on || pll->active)
11711                         continue;
11712
11713                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
11714
11715                 pll->disable(dev_priv, pll);
11716                 pll->on = false;
11717         }
11718
11719         if (HAS_PCH_SPLIT(dev))
11720                 ilk_wm_get_hw_state(dev);
11721
11722         if (force_restore) {
11723                 i915_redisable_vga(dev);
11724
11725                 /*
11726                  * We need to use raw interfaces for restoring state to avoid
11727                  * checking (bogus) intermediate states.
11728                  */
11729                 for_each_pipe(pipe) {
11730                         struct drm_crtc *crtc =
11731                                 dev_priv->pipe_to_crtc_mapping[pipe];
11732
11733                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
11734                                          crtc->primary->fb);
11735                 }
11736         } else {
11737                 intel_modeset_update_staged_output_state(dev);
11738         }
11739
11740         intel_modeset_check_state(dev);
11741 }
11742
11743 void intel_modeset_gem_init(struct drm_device *dev)
11744 {
11745         struct drm_crtc *c;
11746         struct intel_framebuffer *fb;
11747
11748         mutex_lock(&dev->struct_mutex);
11749         intel_init_gt_powersave(dev);
11750         mutex_unlock(&dev->struct_mutex);
11751
11752         intel_modeset_init_hw(dev);
11753
11754         intel_setup_overlay(dev);
11755
11756         /*
11757          * Make sure any fbs we allocated at startup are properly
11758          * pinned & fenced.  When we do the allocation it's too early
11759          * for this.
11760          */
11761         mutex_lock(&dev->struct_mutex);
11762         list_for_each_entry(c, &dev->mode_config.crtc_list, head) {
11763                 if (!c->primary->fb)
11764                         continue;
11765
11766                 fb = to_intel_framebuffer(c->primary->fb);
11767                 if (intel_pin_and_fence_fb_obj(dev, fb->obj, NULL)) {
11768                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
11769                                   to_intel_crtc(c)->pipe);
11770                         drm_framebuffer_unreference(c->primary->fb);
11771                         c->primary->fb = NULL;
11772                 }
11773         }
11774         mutex_unlock(&dev->struct_mutex);
11775 }
11776
11777 void intel_connector_unregister(struct intel_connector *intel_connector)
11778 {
11779         struct drm_connector *connector = &intel_connector->base;
11780
11781         intel_panel_destroy_backlight(connector);
11782         drm_sysfs_connector_remove(connector);
11783 }
11784
11785 void intel_modeset_cleanup(struct drm_device *dev)
11786 {
11787         struct drm_i915_private *dev_priv = dev->dev_private;
11788         struct drm_crtc *crtc;
11789         struct drm_connector *connector;
11790
11791         /*
11792          * Interrupts and polling as the first thing to avoid creating havoc.
11793          * Too much stuff here (turning of rps, connectors, ...) would
11794          * experience fancy races otherwise.
11795          */
11796         drm_irq_uninstall(dev);
11797         cancel_work_sync(&dev_priv->hotplug_work);
11798         /*
11799          * Due to the hpd irq storm handling the hotplug work can re-arm the
11800          * poll handlers. Hence disable polling after hpd handling is shut down.
11801          */
11802         drm_kms_helper_poll_fini(dev);
11803
11804         mutex_lock(&dev->struct_mutex);
11805
11806         intel_unregister_dsm_handler();
11807
11808         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
11809                 /* Skip inactive CRTCs */
11810                 if (!crtc->primary->fb)
11811                         continue;
11812
11813                 intel_increase_pllclock(crtc);
11814         }
11815
11816         intel_disable_fbc(dev);
11817
11818         intel_disable_gt_powersave(dev);
11819
11820         ironlake_teardown_rc6(dev);
11821
11822         mutex_unlock(&dev->struct_mutex);
11823
11824         /* flush any delayed tasks or pending work */
11825         flush_scheduled_work();
11826
11827         /* destroy the backlight and sysfs files before encoders/connectors */
11828         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11829                 struct intel_connector *intel_connector;
11830
11831                 intel_connector = to_intel_connector(connector);
11832                 intel_connector->unregister(intel_connector);
11833         }
11834
11835         drm_mode_config_cleanup(dev);
11836
11837         intel_cleanup_overlay(dev);
11838
11839         mutex_lock(&dev->struct_mutex);
11840         intel_cleanup_gt_powersave(dev);
11841         mutex_unlock(&dev->struct_mutex);
11842 }
11843
11844 /*
11845  * Return which encoder is currently attached for connector.
11846  */
11847 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
11848 {
11849         return &intel_attached_encoder(connector)->base;
11850 }
11851
11852 void intel_connector_attach_encoder(struct intel_connector *connector,
11853                                     struct intel_encoder *encoder)
11854 {
11855         connector->encoder = encoder;
11856         drm_mode_connector_attach_encoder(&connector->base,
11857                                           &encoder->base);
11858 }
11859
11860 /*
11861  * set vga decode state - true == enable VGA decode
11862  */
11863 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
11864 {
11865         struct drm_i915_private *dev_priv = dev->dev_private;
11866         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
11867         u16 gmch_ctrl;
11868
11869         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
11870                 DRM_ERROR("failed to read control word\n");
11871                 return -EIO;
11872         }
11873
11874         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
11875                 return 0;
11876
11877         if (state)
11878                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
11879         else
11880                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
11881
11882         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
11883                 DRM_ERROR("failed to write control word\n");
11884                 return -EIO;
11885         }
11886
11887         return 0;
11888 }
11889
11890 struct intel_display_error_state {
11891
11892         u32 power_well_driver;
11893
11894         int num_transcoders;
11895
11896         struct intel_cursor_error_state {
11897                 u32 control;
11898                 u32 position;
11899                 u32 base;
11900                 u32 size;
11901         } cursor[I915_MAX_PIPES];
11902
11903         struct intel_pipe_error_state {
11904                 bool power_domain_on;
11905                 u32 source;
11906                 u32 stat;
11907         } pipe[I915_MAX_PIPES];
11908
11909         struct intel_plane_error_state {
11910                 u32 control;
11911                 u32 stride;
11912                 u32 size;
11913                 u32 pos;
11914                 u32 addr;
11915                 u32 surface;
11916                 u32 tile_offset;
11917         } plane[I915_MAX_PIPES];
11918
11919         struct intel_transcoder_error_state {
11920                 bool power_domain_on;
11921                 enum transcoder cpu_transcoder;
11922
11923                 u32 conf;
11924
11925                 u32 htotal;
11926                 u32 hblank;
11927                 u32 hsync;
11928                 u32 vtotal;
11929                 u32 vblank;
11930                 u32 vsync;
11931         } transcoder[4];
11932 };
11933
11934 struct intel_display_error_state *
11935 intel_display_capture_error_state(struct drm_device *dev)
11936 {
11937         struct drm_i915_private *dev_priv = dev->dev_private;
11938         struct intel_display_error_state *error;
11939         int transcoders[] = {
11940                 TRANSCODER_A,
11941                 TRANSCODER_B,
11942                 TRANSCODER_C,
11943                 TRANSCODER_EDP,
11944         };
11945         int i;
11946
11947         if (INTEL_INFO(dev)->num_pipes == 0)
11948                 return NULL;
11949
11950         error = kzalloc(sizeof(*error), GFP_ATOMIC);
11951         if (error == NULL)
11952                 return NULL;
11953
11954         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
11955                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
11956
11957         for_each_pipe(i) {
11958                 error->pipe[i].power_domain_on =
11959                         intel_display_power_enabled_sw(dev_priv,
11960                                                        POWER_DOMAIN_PIPE(i));
11961                 if (!error->pipe[i].power_domain_on)
11962                         continue;
11963
11964                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
11965                         error->cursor[i].control = I915_READ(CURCNTR(i));
11966                         error->cursor[i].position = I915_READ(CURPOS(i));
11967                         error->cursor[i].base = I915_READ(CURBASE(i));
11968                 } else {
11969                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
11970                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
11971                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
11972                 }
11973
11974                 error->plane[i].control = I915_READ(DSPCNTR(i));
11975                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
11976                 if (INTEL_INFO(dev)->gen <= 3) {
11977                         error->plane[i].size = I915_READ(DSPSIZE(i));
11978                         error->plane[i].pos = I915_READ(DSPPOS(i));
11979                 }
11980                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11981                         error->plane[i].addr = I915_READ(DSPADDR(i));
11982                 if (INTEL_INFO(dev)->gen >= 4) {
11983                         error->plane[i].surface = I915_READ(DSPSURF(i));
11984                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
11985                 }
11986
11987                 error->pipe[i].source = I915_READ(PIPESRC(i));
11988
11989                 if (!HAS_PCH_SPLIT(dev))
11990                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
11991         }
11992
11993         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
11994         if (HAS_DDI(dev_priv->dev))
11995                 error->num_transcoders++; /* Account for eDP. */
11996
11997         for (i = 0; i < error->num_transcoders; i++) {
11998                 enum transcoder cpu_transcoder = transcoders[i];
11999
12000                 error->transcoder[i].power_domain_on =
12001                         intel_display_power_enabled_sw(dev_priv,
12002                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
12003                 if (!error->transcoder[i].power_domain_on)
12004                         continue;
12005
12006                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
12007
12008                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
12009                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
12010                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
12011                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
12012                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
12013                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
12014                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
12015         }
12016
12017         return error;
12018 }
12019
12020 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
12021
12022 void
12023 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
12024                                 struct drm_device *dev,
12025                                 struct intel_display_error_state *error)
12026 {
12027         int i;
12028
12029         if (!error)
12030                 return;
12031
12032         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
12033         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
12034                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
12035                            error->power_well_driver);
12036         for_each_pipe(i) {
12037                 err_printf(m, "Pipe [%d]:\n", i);
12038                 err_printf(m, "  Power: %s\n",
12039                            error->pipe[i].power_domain_on ? "on" : "off");
12040                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
12041                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
12042
12043                 err_printf(m, "Plane [%d]:\n", i);
12044                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
12045                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
12046                 if (INTEL_INFO(dev)->gen <= 3) {
12047                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
12048                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
12049                 }
12050                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
12051                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
12052                 if (INTEL_INFO(dev)->gen >= 4) {
12053                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
12054                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
12055                 }
12056
12057                 err_printf(m, "Cursor [%d]:\n", i);
12058                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
12059                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
12060                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
12061         }
12062
12063         for (i = 0; i < error->num_transcoders; i++) {
12064                 err_printf(m, "CPU transcoder: %c\n",
12065                            transcoder_name(error->transcoder[i].cpu_transcoder));
12066                 err_printf(m, "  Power: %s\n",
12067                            error->transcoder[i].power_domain_on ? "on" : "off");
12068                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
12069                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
12070                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
12071                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
12072                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
12073                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
12074                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
12075         }
12076 }