drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 #define DIV_ROUND_CLOSEST_ULL(ll, d)    \
  45         ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
  46
  47 static void intel_increase_pllclock(struct drm_crtc *crtc);
  48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  49
  50 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  51                                 struct intel_crtc_config *pipe_config);
  52 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  53                                    struct intel_crtc_config *pipe_config);
  54
  55 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  56                           int x, int y, struct drm_framebuffer *old_fb);
  57 static int intel_framebuffer_init(struct drm_device *dev,
  58                                   struct intel_framebuffer *ifb,
  59                                   struct drm_mode_fb_cmd2 *mode_cmd,
  60                                   struct drm_i915_gem_object *obj);
  61 static void intel_dp_set_m_n(struct intel_crtc *crtc);
  62 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  63 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  64 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  65                                          struct intel_link_m_n *m_n);
  66 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
  67 static void haswell_set_pipeconf(struct drm_crtc *crtc);
  68 static void intel_set_pipe_csc(struct drm_crtc *crtc);
  69 static void vlv_prepare_pll(struct intel_crtc *crtc);
  70
  71 typedef struct {
  72         int     min, max;
  73 } intel_range_t;
  74
  75 typedef struct {
  76         int     dot_limit;
  77         int     p2_slow, p2_fast;
  78 } intel_p2_t;
  79
  80 typedef struct intel_limit intel_limit_t;
  81 struct intel_limit {
  82         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  83         intel_p2_t          p2;
  84 };
  85
  86 int
  87 intel_pch_rawclk(struct drm_device *dev)
  88 {
  89         struct drm_i915_private *dev_priv = dev->dev_private;
  90
  91         WARN_ON(!HAS_PCH_SPLIT(dev));
  92
  93         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  94 }
  95
  96 static inline u32 /* units of 100MHz */
  97 intel_fdi_link_freq(struct drm_device *dev)
  98 {
  99         if (IS_GEN5(dev)) {
 100                 struct drm_i915_private *dev_priv = dev->dev_private;
 101                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 102         } else
 103                 return 27;
 104 }
 105
 106 static const intel_limit_t intel_limits_i8xx_dac = {
 107         .dot = { .min = 25000, .max = 350000 },
 108         .vco = { .min = 908000, .max = 1512000 },
 109         .n = { .min = 2, .max = 16 },
 110         .m = { .min = 96, .max = 140 },
 111         .m1 = { .min = 18, .max = 26 },
 112         .m2 = { .min = 6, .max = 16 },
 113         .p = { .min = 4, .max = 128 },
 114         .p1 = { .min = 2, .max = 33 },
 115         .p2 = { .dot_limit = 165000,
 116                 .p2_slow = 4, .p2_fast = 2 },
 117 };
 118
 119 static const intel_limit_t intel_limits_i8xx_dvo = {
 120         .dot = { .min = 25000, .max = 350000 },
 121         .vco = { .min = 908000, .max = 1512000 },
 122         .n = { .min = 2, .max = 16 },
 123         .m = { .min = 96, .max = 140 },
 124         .m1 = { .min = 18, .max = 26 },
 125         .m2 = { .min = 6, .max = 16 },
 126         .p = { .min = 4, .max = 128 },
 127         .p1 = { .min = 2, .max = 33 },
 128         .p2 = { .dot_limit = 165000,
 129                 .p2_slow = 4, .p2_fast = 4 },
 130 };
 131
 132 static const intel_limit_t intel_limits_i8xx_lvds = {
 133         .dot = { .min = 25000, .max = 350000 },
 134         .vco = { .min = 908000, .max = 1512000 },
 135         .n = { .min = 2, .max = 16 },
 136         .m = { .min = 96, .max = 140 },
 137         .m1 = { .min = 18, .max = 26 },
 138         .m2 = { .min = 6, .max = 16 },
 139         .p = { .min = 4, .max = 128 },
 140         .p1 = { .min = 1, .max = 6 },
 141         .p2 = { .dot_limit = 165000,
 142                 .p2_slow = 14, .p2_fast = 7 },
 143 };
 144
 145 static const intel_limit_t intel_limits_i9xx_sdvo = {
 146         .dot = { .min = 20000, .max = 400000 },
 147         .vco = { .min = 1400000, .max = 2800000 },
 148         .n = { .min = 1, .max = 6 },
 149         .m = { .min = 70, .max = 120 },
 150         .m1 = { .min = 8, .max = 18 },
 151         .m2 = { .min = 3, .max = 7 },
 152         .p = { .min = 5, .max = 80 },
 153         .p1 = { .min = 1, .max = 8 },
 154         .p2 = { .dot_limit = 200000,
 155                 .p2_slow = 10, .p2_fast = 5 },
 156 };
 157
 158 static const intel_limit_t intel_limits_i9xx_lvds = {
 159         .dot = { .min = 20000, .max = 400000 },
 160         .vco = { .min = 1400000, .max = 2800000 },
 161         .n = { .min = 1, .max = 6 },
 162         .m = { .min = 70, .max = 120 },
 163         .m1 = { .min = 8, .max = 18 },
 164         .m2 = { .min = 3, .max = 7 },
 165         .p = { .min = 7, .max = 98 },
 166         .p1 = { .min = 1, .max = 8 },
 167         .p2 = { .dot_limit = 112000,
 168                 .p2_slow = 14, .p2_fast = 7 },
 169 };
 170
 171
 172 static const intel_limit_t intel_limits_g4x_sdvo = {
 173         .dot = { .min = 25000, .max = 270000 },
 174         .vco = { .min = 1750000, .max = 3500000},
 175         .n = { .min = 1, .max = 4 },
 176         .m = { .min = 104, .max = 138 },
 177         .m1 = { .min = 17, .max = 23 },
 178         .m2 = { .min = 5, .max = 11 },
 179         .p = { .min = 10, .max = 30 },
 180         .p1 = { .min = 1, .max = 3},
 181         .p2 = { .dot_limit = 270000,
 182                 .p2_slow = 10,
 183                 .p2_fast = 10
 184         },
 185 };
 186
 187 static const intel_limit_t intel_limits_g4x_hdmi = {
 188         .dot = { .min = 22000, .max = 400000 },
 189         .vco = { .min = 1750000, .max = 3500000},
 190         .n = { .min = 1, .max = 4 },
 191         .m = { .min = 104, .max = 138 },
 192         .m1 = { .min = 16, .max = 23 },
 193         .m2 = { .min = 5, .max = 11 },
 194         .p = { .min = 5, .max = 80 },
 195         .p1 = { .min = 1, .max = 8},
 196         .p2 = { .dot_limit = 165000,
 197                 .p2_slow = 10, .p2_fast = 5 },
 198 };
 199
 200 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 201         .dot = { .min = 20000, .max = 115000 },
 202         .vco = { .min = 1750000, .max = 3500000 },
 203         .n = { .min = 1, .max = 3 },
 204         .m = { .min = 104, .max = 138 },
 205         .m1 = { .min = 17, .max = 23 },
 206         .m2 = { .min = 5, .max = 11 },
 207         .p = { .min = 28, .max = 112 },
 208         .p1 = { .min = 2, .max = 8 },
 209         .p2 = { .dot_limit = 0,
 210                 .p2_slow = 14, .p2_fast = 14
 211         },
 212 };
 213
 214 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 215         .dot = { .min = 80000, .max = 224000 },
 216         .vco = { .min = 1750000, .max = 3500000 },
 217         .n = { .min = 1, .max = 3 },
 218         .m = { .min = 104, .max = 138 },
 219         .m1 = { .min = 17, .max = 23 },
 220         .m2 = { .min = 5, .max = 11 },
 221         .p = { .min = 14, .max = 42 },
 222         .p1 = { .min = 2, .max = 6 },
 223         .p2 = { .dot_limit = 0,
 224                 .p2_slow = 7, .p2_fast = 7
 225         },
 226 };
 227
 228 static const intel_limit_t intel_limits_pineview_sdvo = {
 229         .dot = { .min = 20000, .max = 400000},
 230         .vco = { .min = 1700000, .max = 3500000 },
 231         /* Pineview's Ncounter is a ring counter */
 232         .n = { .min = 3, .max = 6 },
 233         .m = { .min = 2, .max = 256 },
 234         /* Pineview only has one combined m divider, which we treat as m2. */
 235         .m1 = { .min = 0, .max = 0 },
 236         .m2 = { .min = 0, .max = 254 },
 237         .p = { .min = 5, .max = 80 },
 238         .p1 = { .min = 1, .max = 8 },
 239         .p2 = { .dot_limit = 200000,
 240                 .p2_slow = 10, .p2_fast = 5 },
 241 };
 242
 243 static const intel_limit_t intel_limits_pineview_lvds = {
 244         .dot = { .min = 20000, .max = 400000 },
 245         .vco = { .min = 1700000, .max = 3500000 },
 246         .n = { .min = 3, .max = 6 },
 247         .m = { .min = 2, .max = 256 },
 248         .m1 = { .min = 0, .max = 0 },
 249         .m2 = { .min = 0, .max = 254 },
 250         .p = { .min = 7, .max = 112 },
 251         .p1 = { .min = 1, .max = 8 },
 252         .p2 = { .dot_limit = 112000,
 253                 .p2_slow = 14, .p2_fast = 14 },
 254 };
 255
 256 /* Ironlake / Sandybridge
 257  *
 258  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 259  * the range value for them is (actual_value - 2).
 260  */
 261 static const intel_limit_t intel_limits_ironlake_dac = {
 262         .dot = { .min = 25000, .max = 350000 },
 263         .vco = { .min = 1760000, .max = 3510000 },
 264         .n = { .min = 1, .max = 5 },
 265         .m = { .min = 79, .max = 127 },
 266         .m1 = { .min = 12, .max = 22 },
 267         .m2 = { .min = 5, .max = 9 },
 268         .p = { .min = 5, .max = 80 },
 269         .p1 = { .min = 1, .max = 8 },
 270         .p2 = { .dot_limit = 225000,
 271                 .p2_slow = 10, .p2_fast = 5 },
 272 };
 273
 274 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 275         .dot = { .min = 25000, .max = 350000 },
 276         .vco = { .min = 1760000, .max = 3510000 },
 277         .n = { .min = 1, .max = 3 },
 278         .m = { .min = 79, .max = 118 },
 279         .m1 = { .min = 12, .max = 22 },
 280         .m2 = { .min = 5, .max = 9 },
 281         .p = { .min = 28, .max = 112 },
 282         .p1 = { .min = 2, .max = 8 },
 283         .p2 = { .dot_limit = 225000,
 284                 .p2_slow = 14, .p2_fast = 14 },
 285 };
 286
 287 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 288         .dot = { .min = 25000, .max = 350000 },
 289         .vco = { .min = 1760000, .max = 3510000 },
 290         .n = { .min = 1, .max = 3 },
 291         .m = { .min = 79, .max = 127 },
 292         .m1 = { .min = 12, .max = 22 },
 293         .m2 = { .min = 5, .max = 9 },
 294         .p = { .min = 14, .max = 56 },
 295         .p1 = { .min = 2, .max = 8 },
 296         .p2 = { .dot_limit = 225000,
 297                 .p2_slow = 7, .p2_fast = 7 },
 298 };
 299
 300 /* LVDS 100mhz refclk limits. */
 301 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 302         .dot = { .min = 25000, .max = 350000 },
 303         .vco = { .min = 1760000, .max = 3510000 },
 304         .n = { .min = 1, .max = 2 },
 305         .m = { .min = 79, .max = 126 },
 306         .m1 = { .min = 12, .max = 22 },
 307         .m2 = { .min = 5, .max = 9 },
 308         .p = { .min = 28, .max = 112 },
 309         .p1 = { .min = 2, .max = 8 },
 310         .p2 = { .dot_limit = 225000,
 311                 .p2_slow = 14, .p2_fast = 14 },
 312 };
 313
 314 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 315         .dot = { .min = 25000, .max = 350000 },
 316         .vco = { .min = 1760000, .max = 3510000 },
 317         .n = { .min = 1, .max = 3 },
 318         .m = { .min = 79, .max = 126 },
 319         .m1 = { .min = 12, .max = 22 },
 320         .m2 = { .min = 5, .max = 9 },
 321         .p = { .min = 14, .max = 42 },
 322         .p1 = { .min = 2, .max = 6 },
 323         .p2 = { .dot_limit = 225000,
 324                 .p2_slow = 7, .p2_fast = 7 },
 325 };
 326
 327 static const intel_limit_t intel_limits_vlv = {
 328          /*
 329           * These are the data rate limits (measured in fast clocks)
 330           * since those are the strictest limits we have. The fast
 331           * clock and actual rate limits are more relaxed, so checking
 332           * them would make no difference.
 333           */
 334         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 335         .vco = { .min = 4000000, .max = 6000000 },
 336         .n = { .min = 1, .max = 7 },
 337         .m1 = { .min = 2, .max = 3 },
 338         .m2 = { .min = 11, .max = 156 },
 339         .p1 = { .min = 2, .max = 3 },
 340         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 341 };
 342
 343 static const intel_limit_t intel_limits_chv = {
 344         /*
 345          * These are the data rate limits (measured in fast clocks)
 346          * since those are the strictest limits we have.  The fast
 347          * clock and actual rate limits are more relaxed, so checking
 348          * them would make no difference.
 349          */
 350         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 351         .vco = { .min = 4860000, .max = 6700000 },
 352         .n = { .min = 1, .max = 1 },
 353         .m1 = { .min = 2, .max = 2 },
 354         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 355         .p1 = { .min = 2, .max = 4 },
 356         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 357 };
 358
 359 static void vlv_clock(int refclk, intel_clock_t *clock)
 360 {
 361         clock->m = clock->m1 * clock->m2;
 362         clock->p = clock->p1 * clock->p2;
 363         if (WARN_ON(clock->n == 0 || clock->p == 0))
 364                 return;
 365         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 366         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 367 }
 368
 369 /**
 370  * Returns whether any output on the specified pipe is of the specified type
 371  */
 372 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 373 {
 374         struct drm_device *dev = crtc->dev;
 375         struct intel_encoder *encoder;
 376
 377         for_each_encoder_on_crtc(dev, crtc, encoder)
 378                 if (encoder->type == type)
 379                         return true;
 380
 381         return false;
 382 }
 383
 384 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 385                                                 int refclk)
 386 {
 387         struct drm_device *dev = crtc->dev;
 388         const intel_limit_t *limit;
 389
 390         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 391                 if (intel_is_dual_link_lvds(dev)) {
 392                         if (refclk == 100000)
 393                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 394                         else
 395                                 limit = &intel_limits_ironlake_dual_lvds;
 396                 } else {
 397                         if (refclk == 100000)
 398                                 limit = &intel_limits_ironlake_single_lvds_100m;
 399                         else
 400                                 limit = &intel_limits_ironlake_single_lvds;
 401                 }
 402         } else
 403                 limit = &intel_limits_ironlake_dac;
 404
 405         return limit;
 406 }
 407
 408 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 409 {
 410         struct drm_device *dev = crtc->dev;
 411         const intel_limit_t *limit;
 412
 413         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 414                 if (intel_is_dual_link_lvds(dev))
 415                         limit = &intel_limits_g4x_dual_channel_lvds;
 416                 else
 417                         limit = &intel_limits_g4x_single_channel_lvds;
 418         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 419                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 420                 limit = &intel_limits_g4x_hdmi;
 421         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 422                 limit = &intel_limits_g4x_sdvo;
 423         } else /* The option is for other outputs */
 424                 limit = &intel_limits_i9xx_sdvo;
 425
 426         return limit;
 427 }
 428
 429 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 430 {
 431         struct drm_device *dev = crtc->dev;
 432         const intel_limit_t *limit;
 433
 434         if (HAS_PCH_SPLIT(dev))
 435                 limit = intel_ironlake_limit(crtc, refclk);
 436         else if (IS_G4X(dev)) {
 437                 limit = intel_g4x_limit(crtc);
 438         } else if (IS_PINEVIEW(dev)) {
 439                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 440                         limit = &intel_limits_pineview_lvds;
 441                 else
 442                         limit = &intel_limits_pineview_sdvo;
 443         } else if (IS_CHERRYVIEW(dev)) {
 444                 limit = &intel_limits_chv;
 445         } else if (IS_VALLEYVIEW(dev)) {
 446                 limit = &intel_limits_vlv;
 447         } else if (!IS_GEN2(dev)) {
 448                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 449                         limit = &intel_limits_i9xx_lvds;
 450                 else
 451                         limit = &intel_limits_i9xx_sdvo;
 452         } else {
 453                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 454                         limit = &intel_limits_i8xx_lvds;
 455                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 456                         limit = &intel_limits_i8xx_dvo;
 457                 else
 458                         limit = &intel_limits_i8xx_dac;
 459         }
 460         return limit;
 461 }
 462
 463 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 464 static void pineview_clock(int refclk, intel_clock_t *clock)
 465 {
 466         clock->m = clock->m2 + 2;
 467         clock->p = clock->p1 * clock->p2;
 468         if (WARN_ON(clock->n == 0 || clock->p == 0))
 469                 return;
 470         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 471         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 472 }
 473
 474 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 475 {
 476         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 477 }
 478
 479 static void i9xx_clock(int refclk, intel_clock_t *clock)
 480 {
 481         clock->m = i9xx_dpll_compute_m(clock);
 482         clock->p = clock->p1 * clock->p2;
 483         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 484                 return;
 485         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 486         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 487 }
 488
 489 static void chv_clock(int refclk, intel_clock_t *clock)
 490 {
 491         clock->m = clock->m1 * clock->m2;
 492         clock->p = clock->p1 * clock->p2;
 493         if (WARN_ON(clock->n == 0 || clock->p == 0))
 494                 return;
 495         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 496                         clock->n << 22);
 497         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 498 }
 499
 500 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 501 /**
 502  * Returns whether the given set of divisors are valid for a given refclk with
 503  * the given connectors.
 504  */
 505
 506 static bool intel_PLL_is_valid(struct drm_device *dev,
 507                                const intel_limit_t *limit,
 508                                const intel_clock_t *clock)
 509 {
 510         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 511                 INTELPllInvalid("n out of range\n");
 512         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 513                 INTELPllInvalid("p1 out of range\n");
 514         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 515                 INTELPllInvalid("m2 out of range\n");
 516         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 517                 INTELPllInvalid("m1 out of range\n");
 518
 519         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 520                 if (clock->m1 <= clock->m2)
 521                         INTELPllInvalid("m1 <= m2\n");
 522
 523         if (!IS_VALLEYVIEW(dev)) {
 524                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 525                         INTELPllInvalid("p out of range\n");
 526                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 527                         INTELPllInvalid("m out of range\n");
 528         }
 529
 530         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 531                 INTELPllInvalid("vco out of range\n");
 532         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 533          * connector, etc., rather than just a single range.
 534          */
 535         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 536                 INTELPllInvalid("dot out of range\n");
 537
 538         return true;
 539 }
 540
 541 static bool
 542 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 543                     int target, int refclk, intel_clock_t *match_clock,
 544                     intel_clock_t *best_clock)
 545 {
 546         struct drm_device *dev = crtc->dev;
 547         intel_clock_t clock;
 548         int err = target;
 549
 550         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 551                 /*
 552                  * For LVDS just rely on its current settings for dual-channel.
 553                  * We haven't figured out how to reliably set up different
 554                  * single/dual channel state, if we even can.
 555                  */
 556                 if (intel_is_dual_link_lvds(dev))
 557                         clock.p2 = limit->p2.p2_fast;
 558                 else
 559                         clock.p2 = limit->p2.p2_slow;
 560         } else {
 561                 if (target < limit->p2.dot_limit)
 562                         clock.p2 = limit->p2.p2_slow;
 563                 else
 564                         clock.p2 = limit->p2.p2_fast;
 565         }
 566
 567         memset(best_clock, 0, sizeof(*best_clock));
 568
 569         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 570              clock.m1++) {
 571                 for (clock.m2 = limit->m2.min;
 572                      clock.m2 <= limit->m2.max; clock.m2++) {
 573                         if (clock.m2 >= clock.m1)
 574                                 break;
 575                         for (clock.n = limit->n.min;
 576                              clock.n <= limit->n.max; clock.n++) {
 577                                 for (clock.p1 = limit->p1.min;
 578                                         clock.p1 <= limit->p1.max; clock.p1++) {
 579                                         int this_err;
 580
 581                                         i9xx_clock(refclk, &clock);
 582                                         if (!intel_PLL_is_valid(dev, limit,
 583                                                                 &clock))
 584                                                 continue;
 585                                         if (match_clock &&
 586                                             clock.p != match_clock->p)
 587                                                 continue;
 588
 589                                         this_err = abs(clock.dot - target);
 590                                         if (this_err < err) {
 591                                                 *best_clock = clock;
 592                                                 err = this_err;
 593                                         }
 594                                 }
 595                         }
 596                 }
 597         }
 598
 599         return (err != target);
 600 }
 601
 602 static bool
 603 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 604                    int target, int refclk, intel_clock_t *match_clock,
 605                    intel_clock_t *best_clock)
 606 {
 607         struct drm_device *dev = crtc->dev;
 608         intel_clock_t clock;
 609         int err = target;
 610
 611         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 612                 /*
 613                  * For LVDS just rely on its current settings for dual-channel.
 614                  * We haven't figured out how to reliably set up different
 615                  * single/dual channel state, if we even can.
 616                  */
 617                 if (intel_is_dual_link_lvds(dev))
 618                         clock.p2 = limit->p2.p2_fast;
 619                 else
 620                         clock.p2 = limit->p2.p2_slow;
 621         } else {
 622                 if (target < limit->p2.dot_limit)
 623                         clock.p2 = limit->p2.p2_slow;
 624                 else
 625                         clock.p2 = limit->p2.p2_fast;
 626         }
 627
 628         memset(best_clock, 0, sizeof(*best_clock));
 629
 630         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 631              clock.m1++) {
 632                 for (clock.m2 = limit->m2.min;
 633                      clock.m2 <= limit->m2.max; clock.m2++) {
 634                         for (clock.n = limit->n.min;
 635                              clock.n <= limit->n.max; clock.n++) {
 636                                 for (clock.p1 = limit->p1.min;
 637                                         clock.p1 <= limit->p1.max; clock.p1++) {
 638                                         int this_err;
 639
 640                                         pineview_clock(refclk, &clock);
 641                                         if (!intel_PLL_is_valid(dev, limit,
 642                                                                 &clock))
 643                                                 continue;
 644                                         if (match_clock &&
 645                                             clock.p != match_clock->p)
 646                                                 continue;
 647
 648                                         this_err = abs(clock.dot - target);
 649                                         if (this_err < err) {
 650                                                 *best_clock = clock;
 651                                                 err = this_err;
 652                                         }
 653                                 }
 654                         }
 655                 }
 656         }
 657
 658         return (err != target);
 659 }
 660
 661 static bool
 662 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 663                    int target, int refclk, intel_clock_t *match_clock,
 664                    intel_clock_t *best_clock)
 665 {
 666         struct drm_device *dev = crtc->dev;
 667         intel_clock_t clock;
 668         int max_n;
 669         bool found;
 670         /* approximately equals target * 0.00585 */
 671         int err_most = (target >> 8) + (target >> 9);
 672         found = false;
 673
 674         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 675                 if (intel_is_dual_link_lvds(dev))
 676                         clock.p2 = limit->p2.p2_fast;
 677                 else
 678                         clock.p2 = limit->p2.p2_slow;
 679         } else {
 680                 if (target < limit->p2.dot_limit)
 681                         clock.p2 = limit->p2.p2_slow;
 682                 else
 683                         clock.p2 = limit->p2.p2_fast;
 684         }
 685
 686         memset(best_clock, 0, sizeof(*best_clock));
 687         max_n = limit->n.max;
 688         /* based on hardware requirement, prefer smaller n to precision */
 689         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 690                 /* based on hardware requirement, prefere larger m1,m2 */
 691                 for (clock.m1 = limit->m1.max;
 692                      clock.m1 >= limit->m1.min; clock.m1--) {
 693                         for (clock.m2 = limit->m2.max;
 694                              clock.m2 >= limit->m2.min; clock.m2--) {
 695                                 for (clock.p1 = limit->p1.max;
 696                                      clock.p1 >= limit->p1.min; clock.p1--) {
 697                                         int this_err;
 698
 699                                         i9xx_clock(refclk, &clock);
 700                                         if (!intel_PLL_is_valid(dev, limit,
 701                                                                 &clock))
 702                                                 continue;
 703
 704                                         this_err = abs(clock.dot - target);
 705                                         if (this_err < err_most) {
 706                                                 *best_clock = clock;
 707                                                 err_most = this_err;
 708                                                 max_n = clock.n;
 709                                                 found = true;
 710                                         }
 711                                 }
 712                         }
 713                 }
 714         }
 715         return found;
 716 }
 717
 718 static bool
 719 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 720                    int target, int refclk, intel_clock_t *match_clock,
 721                    intel_clock_t *best_clock)
 722 {
 723         struct drm_device *dev = crtc->dev;
 724         intel_clock_t clock;
 725         unsigned int bestppm = 1000000;
 726         /* min update 19.2 MHz */
 727         int max_n = min(limit->n.max, refclk / 19200);
 728         bool found = false;
 729
 730         target *= 5; /* fast clock */
 731
 732         memset(best_clock, 0, sizeof(*best_clock));
 733
 734         /* based on hardware requirement, prefer smaller n to precision */
 735         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 736                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 737                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 738                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 739                                 clock.p = clock.p1 * clock.p2;
 740                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 741                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 742                                         unsigned int ppm, diff;
 743
 744                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 745                                                                      refclk * clock.m1);
 746
 747                                         vlv_clock(refclk, &clock);
 748
 749                                         if (!intel_PLL_is_valid(dev, limit,
 750                                                                 &clock))
 751                                                 continue;
 752
 753                                         diff = abs(clock.dot - target);
 754                                         ppm = div_u64(1000000ULL * diff, target);
 755
 756                                         if (ppm < 100 && clock.p > best_clock->p) {
 757                                                 bestppm = 0;
 758                                                 *best_clock = clock;
 759                                                 found = true;
 760                                         }
 761
 762                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 763                                                 bestppm = ppm;
 764                                                 *best_clock = clock;
 765                                                 found = true;
 766                                         }
 767                                 }
 768                         }
 769                 }
 770         }
 771
 772         return found;
 773 }
 774
 775 static bool
 776 chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 777                    int target, int refclk, intel_clock_t *match_clock,
 778                    intel_clock_t *best_clock)
 779 {
 780         struct drm_device *dev = crtc->dev;
 781         intel_clock_t clock;
 782         uint64_t m2;
 783         int found = false;
 784
 785         memset(best_clock, 0, sizeof(*best_clock));
 786
 787         /*
 788          * Based on hardware doc, the n always set to 1, and m1 always
 789          * set to 2.  If requires to support 200Mhz refclk, we need to
 790          * revisit this because n may not 1 anymore.
 791          */
 792         clock.n = 1, clock.m1 = 2;
 793         target *= 5;    /* fast clock */
 794
 795         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 796                 for (clock.p2 = limit->p2.p2_fast;
 797                                 clock.p2 >= limit->p2.p2_slow;
 798                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 799
 800                         clock.p = clock.p1 * clock.p2;
 801
 802                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 803                                         clock.n) << 22, refclk * clock.m1);
 804
 805                         if (m2 > INT_MAX/clock.m1)
 806                                 continue;
 807
 808                         clock.m2 = m2;
 809
 810                         chv_clock(refclk, &clock);
 811
 812                         if (!intel_PLL_is_valid(dev, limit, &clock))
 813                                 continue;
 814
 815                         /* based on hardware requirement, prefer bigger p
 816                          */
 817                         if (clock.p > best_clock->p) {
 818                                 *best_clock = clock;
 819                                 found = true;
 820                         }
 821                 }
 822         }
 823
 824         return found;
 825 }
 826
 827 bool intel_crtc_active(struct drm_crtc *crtc)
 828 {
 829         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 830
 831         /* Be paranoid as we can arrive here with only partial
 832          * state retrieved from the hardware during setup.
 833          *
 834          * We can ditch the adjusted_mode.crtc_clock check as soon
 835          * as Haswell has gained clock readout/fastboot support.
 836          *
 837          * We can ditch the crtc->primary->fb check as soon as we can
 838          * properly reconstruct framebuffers.
 839          */
 840         return intel_crtc->active && crtc->primary->fb &&
 841                 intel_crtc->config.adjusted_mode.crtc_clock;
 842 }
 843
 844 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 845                                              enum pipe pipe)
 846 {
 847         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 848         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 849
 850         return intel_crtc->config.cpu_transcoder;
 851 }
 852
 853 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
 854 {
 855         struct drm_i915_private *dev_priv = dev->dev_private;
 856         u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
 857
 858         frame = I915_READ(frame_reg);
 859
 860         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 861                 WARN(1, "vblank wait timed out\n");
 862 }
 863
 864 /**
 865  * intel_wait_for_vblank - wait for vblank on a given pipe
 866  * @dev: drm device
 867  * @pipe: pipe to wait for
 868  *
 869  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 870  * mode setting code.
 871  */
 872 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 873 {
 874         struct drm_i915_private *dev_priv = dev->dev_private;
 875         int pipestat_reg = PIPESTAT(pipe);
 876
 877         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 878                 g4x_wait_for_vblank(dev, pipe);
 879                 return;
 880         }
 881
 882         /* Clear existing vblank status. Note this will clear any other
 883          * sticky status fields as well.
 884          *
 885          * This races with i915_driver_irq_handler() with the result
 886          * that either function could miss a vblank event.  Here it is not
 887          * fatal, as we will either wait upon the next vblank interrupt or
 888          * timeout.  Generally speaking intel_wait_for_vblank() is only
 889          * called during modeset at which time the GPU should be idle and
 890          * should *not* be performing page flips and thus not waiting on
 891          * vblanks...
 892          * Currently, the result of us stealing a vblank from the irq
 893          * handler is that a single frame will be skipped during swapbuffers.
 894          */
 895         I915_WRITE(pipestat_reg,
 896                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 897
 898         /* Wait for vblank interrupt bit to set */
 899         if (wait_for(I915_READ(pipestat_reg) &
 900                      PIPE_VBLANK_INTERRUPT_STATUS,
 901                      50))
 902                 DRM_DEBUG_KMS("vblank wait timed out\n");
 903 }
 904
 905 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 906 {
 907         struct drm_i915_private *dev_priv = dev->dev_private;
 908         u32 reg = PIPEDSL(pipe);
 909         u32 line1, line2;
 910         u32 line_mask;
 911
 912         if (IS_GEN2(dev))
 913                 line_mask = DSL_LINEMASK_GEN2;
 914         else
 915                 line_mask = DSL_LINEMASK_GEN3;
 916
 917         line1 = I915_READ(reg) & line_mask;
 918         mdelay(5);
 919         line2 = I915_READ(reg) & line_mask;
 920
 921         return line1 == line2;
 922 }
 923
 924 /*
 925  * intel_wait_for_pipe_off - wait for pipe to turn off
 926  * @dev: drm device
 927  * @pipe: pipe to wait for
 928  *
 929  * After disabling a pipe, we can't wait for vblank in the usual way,
 930  * spinning on the vblank interrupt status bit, since we won't actually
 931  * see an interrupt when the pipe is disabled.
 932  *
 933  * On Gen4 and above:
 934  *   wait for the pipe register state bit to turn off
 935  *
 936  * Otherwise:
 937  *   wait for the display line value to settle (it usually
 938  *   ends up stopping at the start of the next frame).
 939  *
 940  */
 941 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 942 {
 943         struct drm_i915_private *dev_priv = dev->dev_private;
 944         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 945                                                                       pipe);
 946
 947         if (INTEL_INFO(dev)->gen >= 4) {
 948                 int reg = PIPECONF(cpu_transcoder);
 949
 950                 /* Wait for the Pipe State to go off */
 951                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 952                              100))
 953                         WARN(1, "pipe_off wait timed out\n");
 954         } else {
 955                 /* Wait for the display line to settle */
 956                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 957                         WARN(1, "pipe_off wait timed out\n");
 958         }
 959 }
 960
 961 /*
 962  * ibx_digital_port_connected - is the specified port connected?
 963  * @dev_priv: i915 private structure
 964  * @port: the port to test
 965  *
 966  * Returns true if @port is connected, false otherwise.
 967  */
 968 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 969                                 struct intel_digital_port *port)
 970 {
 971         u32 bit;
 972
 973         if (HAS_PCH_IBX(dev_priv->dev)) {
 974                 switch (port->port) {
 975                 case PORT_B:
 976                         bit = SDE_PORTB_HOTPLUG;
 977                         break;
 978                 case PORT_C:
 979                         bit = SDE_PORTC_HOTPLUG;
 980                         break;
 981                 case PORT_D:
 982                         bit = SDE_PORTD_HOTPLUG;
 983                         break;
 984                 default:
 985                         return true;
 986                 }
 987         } else {
 988                 switch (port->port) {
 989                 case PORT_B:
 990                         bit = SDE_PORTB_HOTPLUG_CPT;
 991                         break;
 992                 case PORT_C:
 993                         bit = SDE_PORTC_HOTPLUG_CPT;
 994                         break;
 995                 case PORT_D:
 996                         bit = SDE_PORTD_HOTPLUG_CPT;
 997                         break;
 998                 default:
 999                         return true;
1000                 }
1001         }
1002
1003         return I915_READ(SDEISR) & bit;
1004 }
1005
1006 static const char *state_string(bool enabled)
1007 {
1008         return enabled ? "on" : "off";
1009 }
1010
1011 /* Only for pre-ILK configs */
1012 void assert_pll(struct drm_i915_private *dev_priv,
1013                 enum pipe pipe, bool state)
1014 {
1015         int reg;
1016         u32 val;
1017         bool cur_state;
1018
1019         reg = DPLL(pipe);
1020         val = I915_READ(reg);
1021         cur_state = !!(val & DPLL_VCO_ENABLE);
1022         WARN(cur_state != state,
1023              "PLL state assertion failure (expected %s, current %s)\n",
1024              state_string(state), state_string(cur_state));
1025 }
1026
1027 /* XXX: the dsi pll is shared between MIPI DSI ports */
1028 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1029 {
1030         u32 val;
1031         bool cur_state;
1032
1033         mutex_lock(&dev_priv->dpio_lock);
1034         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1035         mutex_unlock(&dev_priv->dpio_lock);
1036
1037         cur_state = val & DSI_PLL_VCO_EN;
1038         WARN(cur_state != state,
1039              "DSI PLL state assertion failure (expected %s, current %s)\n",
1040              state_string(state), state_string(cur_state));
1041 }
1042 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1043 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1044
1045 struct intel_shared_dpll *
1046 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1047 {
1048         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1049
1050         if (crtc->config.shared_dpll < 0)
1051                 return NULL;
1052
1053         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1054 }
1055
1056 /* For ILK+ */
1057 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1058                         struct intel_shared_dpll *pll,
1059                         bool state)
1060 {
1061         bool cur_state;
1062         struct intel_dpll_hw_state hw_state;
1063
1064         if (HAS_PCH_LPT(dev_priv->dev)) {
1065                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1066                 return;
1067         }
1068
1069         if (WARN (!pll,
1070                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1071                 return;
1072
1073         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1074         WARN(cur_state != state,
1075              "%s assertion failure (expected %s, current %s)\n",
1076              pll->name, state_string(state), state_string(cur_state));
1077 }
1078
1079 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1080                           enum pipe pipe, bool state)
1081 {
1082         int reg;
1083         u32 val;
1084         bool cur_state;
1085         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1086                                                                       pipe);
1087
1088         if (HAS_DDI(dev_priv->dev)) {
1089                 /* DDI does not have a specific FDI_TX register */
1090                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1091                 val = I915_READ(reg);
1092                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1093         } else {
1094                 reg = FDI_TX_CTL(pipe);
1095                 val = I915_READ(reg);
1096                 cur_state = !!(val & FDI_TX_ENABLE);
1097         }
1098         WARN(cur_state != state,
1099              "FDI TX state assertion failure (expected %s, current %s)\n",
1100              state_string(state), state_string(cur_state));
1101 }
1102 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1103 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1104
1105 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1106                           enum pipe pipe, bool state)
1107 {
1108         int reg;
1109         u32 val;
1110         bool cur_state;
1111
1112         reg = FDI_RX_CTL(pipe);
1113         val = I915_READ(reg);
1114         cur_state = !!(val & FDI_RX_ENABLE);
1115         WARN(cur_state != state,
1116              "FDI RX state assertion failure (expected %s, current %s)\n",
1117              state_string(state), state_string(cur_state));
1118 }
1119 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1120 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1121
1122 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1123                                       enum pipe pipe)
1124 {
1125         int reg;
1126         u32 val;
1127
1128         /* ILK FDI PLL is always enabled */
1129         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1130                 return;
1131
1132         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1133         if (HAS_DDI(dev_priv->dev))
1134                 return;
1135
1136         reg = FDI_TX_CTL(pipe);
1137         val = I915_READ(reg);
1138         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1139 }
1140
1141 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1142                        enum pipe pipe, bool state)
1143 {
1144         int reg;
1145         u32 val;
1146         bool cur_state;
1147
1148         reg = FDI_RX_CTL(pipe);
1149         val = I915_READ(reg);
1150         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1151         WARN(cur_state != state,
1152              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1153              state_string(state), state_string(cur_state));
1154 }
1155
1156 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1157                                   enum pipe pipe)
1158 {
1159         int pp_reg, lvds_reg;
1160         u32 val;
1161         enum pipe panel_pipe = PIPE_A;
1162         bool locked = true;
1163
1164         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1165                 pp_reg = PCH_PP_CONTROL;
1166                 lvds_reg = PCH_LVDS;
1167         } else {
1168                 pp_reg = PP_CONTROL;
1169                 lvds_reg = LVDS;
1170         }
1171
1172         val = I915_READ(pp_reg);
1173         if (!(val & PANEL_POWER_ON) ||
1174             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1175                 locked = false;
1176
1177         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1178                 panel_pipe = PIPE_B;
1179
1180         WARN(panel_pipe == pipe && locked,
1181              "panel assertion failure, pipe %c regs locked\n",
1182              pipe_name(pipe));
1183 }
1184
1185 static void assert_cursor(struct drm_i915_private *dev_priv,
1186                           enum pipe pipe, bool state)
1187 {
1188         struct drm_device *dev = dev_priv->dev;
1189         bool cur_state;
1190
1191         if (IS_845G(dev) || IS_I865G(dev))
1192                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1193         else
1194                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1195
1196         WARN(cur_state != state,
1197              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1198              pipe_name(pipe), state_string(state), state_string(cur_state));
1199 }
1200 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1201 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1202
1203 void assert_pipe(struct drm_i915_private *dev_priv,
1204                  enum pipe pipe, bool state)
1205 {
1206         int reg;
1207         u32 val;
1208         bool cur_state;
1209         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1210                                                                       pipe);
1211
1212         /* if we need the pipe A quirk it must be always on */
1213         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1214                 state = true;
1215
1216         if (!intel_display_power_enabled(dev_priv,
1217                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1218                 cur_state = false;
1219         } else {
1220                 reg = PIPECONF(cpu_transcoder);
1221                 val = I915_READ(reg);
1222                 cur_state = !!(val & PIPECONF_ENABLE);
1223         }
1224
1225         WARN(cur_state != state,
1226              "pipe %c assertion failure (expected %s, current %s)\n",
1227              pipe_name(pipe), state_string(state), state_string(cur_state));
1228 }
1229
1230 static void assert_plane(struct drm_i915_private *dev_priv,
1231                          enum plane plane, bool state)
1232 {
1233         int reg;
1234         u32 val;
1235         bool cur_state;
1236
1237         reg = DSPCNTR(plane);
1238         val = I915_READ(reg);
1239         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1240         WARN(cur_state != state,
1241              "plane %c assertion failure (expected %s, current %s)\n",
1242              plane_name(plane), state_string(state), state_string(cur_state));
1243 }
1244
1245 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1246 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1247
1248 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1249                                    enum pipe pipe)
1250 {
1251         struct drm_device *dev = dev_priv->dev;
1252         int reg, i;
1253         u32 val;
1254         int cur_pipe;
1255
1256         /* Primary planes are fixed to pipes on gen4+ */
1257         if (INTEL_INFO(dev)->gen >= 4) {
1258                 reg = DSPCNTR(pipe);
1259                 val = I915_READ(reg);
1260                 WARN(val & DISPLAY_PLANE_ENABLE,
1261                      "plane %c assertion failure, should be disabled but not\n",
1262                      plane_name(pipe));
1263                 return;
1264         }
1265
1266         /* Need to check both planes against the pipe */
1267         for_each_pipe(i) {
1268                 reg = DSPCNTR(i);
1269                 val = I915_READ(reg);
1270                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1271                         DISPPLANE_SEL_PIPE_SHIFT;
1272                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1273                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1274                      plane_name(i), pipe_name(pipe));
1275         }
1276 }
1277
1278 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1279                                     enum pipe pipe)
1280 {
1281         struct drm_device *dev = dev_priv->dev;
1282         int reg, sprite;
1283         u32 val;
1284
1285         if (IS_VALLEYVIEW(dev)) {
1286                 for_each_sprite(pipe, sprite) {
1287                         reg = SPCNTR(pipe, sprite);
1288                         val = I915_READ(reg);
1289                         WARN(val & SP_ENABLE,
1290                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1291                              sprite_name(pipe, sprite), pipe_name(pipe));
1292                 }
1293         } else if (INTEL_INFO(dev)->gen >= 7) {
1294                 reg = SPRCTL(pipe);
1295                 val = I915_READ(reg);
1296                 WARN(val & SPRITE_ENABLE,
1297                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1298                      plane_name(pipe), pipe_name(pipe));
1299         } else if (INTEL_INFO(dev)->gen >= 5) {
1300                 reg = DVSCNTR(pipe);
1301                 val = I915_READ(reg);
1302                 WARN(val & DVS_ENABLE,
1303                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1304                      plane_name(pipe), pipe_name(pipe));
1305         }
1306 }
1307
1308 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1309 {
1310         u32 val;
1311         bool enabled;
1312
1313         WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1314
1315         val = I915_READ(PCH_DREF_CONTROL);
1316         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1317                             DREF_SUPERSPREAD_SOURCE_MASK));
1318         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1319 }
1320
1321 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1322                                            enum pipe pipe)
1323 {
1324         int reg;
1325         u32 val;
1326         bool enabled;
1327
1328         reg = PCH_TRANSCONF(pipe);
1329         val = I915_READ(reg);
1330         enabled = !!(val & TRANS_ENABLE);
1331         WARN(enabled,
1332              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1333              pipe_name(pipe));
1334 }
1335
1336 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1337                             enum pipe pipe, u32 port_sel, u32 val)
1338 {
1339         if ((val & DP_PORT_EN) == 0)
1340                 return false;
1341
1342         if (HAS_PCH_CPT(dev_priv->dev)) {
1343                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1344                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1345                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1346                         return false;
1347         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1348                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1349                         return false;
1350         } else {
1351                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1352                         return false;
1353         }
1354         return true;
1355 }
1356
1357 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1358                               enum pipe pipe, u32 val)
1359 {
1360         if ((val & SDVO_ENABLE) == 0)
1361                 return false;
1362
1363         if (HAS_PCH_CPT(dev_priv->dev)) {
1364                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1365                         return false;
1366         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1367                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1368                         return false;
1369         } else {
1370                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1371                         return false;
1372         }
1373         return true;
1374 }
1375
1376 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1377                               enum pipe pipe, u32 val)
1378 {
1379         if ((val & LVDS_PORT_EN) == 0)
1380                 return false;
1381
1382         if (HAS_PCH_CPT(dev_priv->dev)) {
1383                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1384                         return false;
1385         } else {
1386                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1387                         return false;
1388         }
1389         return true;
1390 }
1391
1392 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1393                               enum pipe pipe, u32 val)
1394 {
1395         if ((val & ADPA_DAC_ENABLE) == 0)
1396                 return false;
1397         if (HAS_PCH_CPT(dev_priv->dev)) {
1398                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1399                         return false;
1400         } else {
1401                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1402                         return false;
1403         }
1404         return true;
1405 }
1406
1407 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1408                                    enum pipe pipe, int reg, u32 port_sel)
1409 {
1410         u32 val = I915_READ(reg);
1411         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1412              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1413              reg, pipe_name(pipe));
1414
1415         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1416              && (val & DP_PIPEB_SELECT),
1417              "IBX PCH dp port still using transcoder B\n");
1418 }
1419
1420 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1421                                      enum pipe pipe, int reg)
1422 {
1423         u32 val = I915_READ(reg);
1424         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1425              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1426              reg, pipe_name(pipe));
1427
1428         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1429              && (val & SDVO_PIPE_B_SELECT),
1430              "IBX PCH hdmi port still using transcoder B\n");
1431 }
1432
1433 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1434                                       enum pipe pipe)
1435 {
1436         int reg;
1437         u32 val;
1438
1439         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1440         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1441         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1442
1443         reg = PCH_ADPA;
1444         val = I915_READ(reg);
1445         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1446              "PCH VGA enabled on transcoder %c, should be disabled\n",
1447              pipe_name(pipe));
1448
1449         reg = PCH_LVDS;
1450         val = I915_READ(reg);
1451         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1452              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1453              pipe_name(pipe));
1454
1455         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1456         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1457         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1458 }
1459
1460 static void intel_init_dpio(struct drm_device *dev)
1461 {
1462         struct drm_i915_private *dev_priv = dev->dev_private;
1463
1464         if (!IS_VALLEYVIEW(dev))
1465                 return;
1466
1467         /*
1468          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1469          * CHV x1 PHY (DP/HDMI D)
1470          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1471          */
1472         if (IS_CHERRYVIEW(dev)) {
1473                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1474                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1475         } else {
1476                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1477         }
1478 }
1479
1480 static void intel_reset_dpio(struct drm_device *dev)
1481 {
1482         struct drm_i915_private *dev_priv = dev->dev_private;
1483
1484         if (!IS_VALLEYVIEW(dev))
1485                 return;
1486
1487         /*
1488          * Enable the CRI clock source so we can get at the display and the
1489          * reference clock for VGA hotplug / manual detection.
1490          */
1491         I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
1492                    DPLL_REFA_CLK_ENABLE_VLV |
1493                    DPLL_INTEGRATED_CRI_CLK_VLV);
1494
1495         if (IS_CHERRYVIEW(dev)) {
1496                 enum dpio_phy phy;
1497                 u32 val;
1498
1499                 for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) {
1500                         /* Poll for phypwrgood signal */
1501                         if (wait_for(I915_READ(DISPLAY_PHY_STATUS) &
1502                                                 PHY_POWERGOOD(phy), 1))
1503                                 DRM_ERROR("Display PHY %d is not power up\n", phy);
1504
1505                         /*
1506                          * Deassert common lane reset for PHY.
1507                          *
1508                          * This should only be done on init and resume from S3
1509                          * with both PLLs disabled, or we risk losing DPIO and
1510                          * PLL synchronization.
1511                          */
1512                         val = I915_READ(DISPLAY_PHY_CONTROL);
1513                         I915_WRITE(DISPLAY_PHY_CONTROL,
1514                                 PHY_COM_LANE_RESET_DEASSERT(phy, val));
1515                 }
1516
1517         } else {
1518                 /*
1519                  * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1520                  *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1521                  *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1522                  *   b. The other bits such as sfr settings / modesel may all
1523                  *      be set to 0.
1524                  *
1525                  * This should only be done on init and resume from S3 with
1526                  * both PLLs disabled, or we risk losing DPIO and PLL
1527                  * synchronization.
1528                  */
1529                 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1530         }
1531 }
1532
1533 static void vlv_enable_pll(struct intel_crtc *crtc)
1534 {
1535         struct drm_device *dev = crtc->base.dev;
1536         struct drm_i915_private *dev_priv = dev->dev_private;
1537         int reg = DPLL(crtc->pipe);
1538         u32 dpll = crtc->config.dpll_hw_state.dpll;
1539
1540         assert_pipe_disabled(dev_priv, crtc->pipe);
1541
1542         /* No really, not for ILK+ */
1543         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1544
1545         /* PLL is protected by panel, make sure we can write it */
1546         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1547                 assert_panel_unlocked(dev_priv, crtc->pipe);
1548
1549         I915_WRITE(reg, dpll);
1550         POSTING_READ(reg);
1551         udelay(150);
1552
1553         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1554                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1555
1556         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1557         POSTING_READ(DPLL_MD(crtc->pipe));
1558
1559         /* We do this three times for luck */
1560         I915_WRITE(reg, dpll);
1561         POSTING_READ(reg);
1562         udelay(150); /* wait for warmup */
1563         I915_WRITE(reg, dpll);
1564         POSTING_READ(reg);
1565         udelay(150); /* wait for warmup */
1566         I915_WRITE(reg, dpll);
1567         POSTING_READ(reg);
1568         udelay(150); /* wait for warmup */
1569 }
1570
1571 static void chv_enable_pll(struct intel_crtc *crtc)
1572 {
1573         struct drm_device *dev = crtc->base.dev;
1574         struct drm_i915_private *dev_priv = dev->dev_private;
1575         int pipe = crtc->pipe;
1576         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1577         u32 tmp;
1578
1579         assert_pipe_disabled(dev_priv, crtc->pipe);
1580
1581         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1582
1583         mutex_lock(&dev_priv->dpio_lock);
1584
1585         /* Enable back the 10bit clock to display controller */
1586         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1587         tmp |= DPIO_DCLKP_EN;
1588         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1589
1590         /*
1591          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1592          */
1593         udelay(1);
1594
1595         /* Enable PLL */
1596         I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
1597
1598         /* Check PLL is locked */
1599         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1600                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1601
1602         /* not sure when this should be written */
1603         I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
1604         POSTING_READ(DPLL_MD(pipe));
1605
1606         /* Deassert soft data lane reset*/
1607         tmp = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(port));
1608         tmp |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1609         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), tmp);
1610
1611         mutex_unlock(&dev_priv->dpio_lock);
1612 }
1613
1614 static void i9xx_enable_pll(struct intel_crtc *crtc)
1615 {
1616         struct drm_device *dev = crtc->base.dev;
1617         struct drm_i915_private *dev_priv = dev->dev_private;
1618         int reg = DPLL(crtc->pipe);
1619         u32 dpll = crtc->config.dpll_hw_state.dpll;
1620
1621         assert_pipe_disabled(dev_priv, crtc->pipe);
1622
1623         /* No really, not for ILK+ */
1624         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1625
1626         /* PLL is protected by panel, make sure we can write it */
1627         if (IS_MOBILE(dev) && !IS_I830(dev))
1628                 assert_panel_unlocked(dev_priv, crtc->pipe);
1629
1630         I915_WRITE(reg, dpll);
1631
1632         /* Wait for the clocks to stabilize. */
1633         POSTING_READ(reg);
1634         udelay(150);
1635
1636         if (INTEL_INFO(dev)->gen >= 4) {
1637                 I915_WRITE(DPLL_MD(crtc->pipe),
1638                            crtc->config.dpll_hw_state.dpll_md);
1639         } else {
1640                 /* The pixel multiplier can only be updated once the
1641                  * DPLL is enabled and the clocks are stable.
1642                  *
1643                  * So write it again.
1644                  */
1645                 I915_WRITE(reg, dpll);
1646         }
1647
1648         /* We do this three times for luck */
1649         I915_WRITE(reg, dpll);
1650         POSTING_READ(reg);
1651         udelay(150); /* wait for warmup */
1652         I915_WRITE(reg, dpll);
1653         POSTING_READ(reg);
1654         udelay(150); /* wait for warmup */
1655         I915_WRITE(reg, dpll);
1656         POSTING_READ(reg);
1657         udelay(150); /* wait for warmup */
1658 }
1659
1660 /**
1661  * i9xx_disable_pll - disable a PLL
1662  * @dev_priv: i915 private structure
1663  * @pipe: pipe PLL to disable
1664  *
1665  * Disable the PLL for @pipe, making sure the pipe is off first.
1666  *
1667  * Note!  This is for pre-ILK only.
1668  */
1669 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1670 {
1671         /* Don't disable pipe A or pipe A PLLs if needed */
1672         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1673                 return;
1674
1675         /* Make sure the pipe isn't still relying on us */
1676         assert_pipe_disabled(dev_priv, pipe);
1677
1678         I915_WRITE(DPLL(pipe), 0);
1679         POSTING_READ(DPLL(pipe));
1680 }
1681
1682 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1683 {
1684         u32 val = 0;
1685
1686         /* Make sure the pipe isn't still relying on us */
1687         assert_pipe_disabled(dev_priv, pipe);
1688
1689         /*
1690          * Leave integrated clock source and reference clock enabled for pipe B.
1691          * The latter is needed for VGA hotplug / manual detection.
1692          */
1693         if (pipe == PIPE_B)
1694                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1695         I915_WRITE(DPLL(pipe), val);
1696         POSTING_READ(DPLL(pipe));
1697
1698 }
1699
1700 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1701 {
1702         u32 val;
1703
1704         /* Make sure the pipe isn't still relying on us */
1705         assert_pipe_disabled(dev_priv, pipe);
1706
1707         /* Set PLL en = 0 */
1708         val = DPLL_SSC_REF_CLOCK_CHV;
1709         if (pipe != PIPE_A)
1710                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1711         I915_WRITE(DPLL(pipe), val);
1712         POSTING_READ(DPLL(pipe));
1713 }
1714
1715 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1716                 struct intel_digital_port *dport)
1717 {
1718         u32 port_mask;
1719         int dpll_reg;
1720
1721         switch (dport->port) {
1722         case PORT_B:
1723                 port_mask = DPLL_PORTB_READY_MASK;
1724                 dpll_reg = DPLL(0);
1725                 break;
1726         case PORT_C:
1727                 port_mask = DPLL_PORTC_READY_MASK;
1728                 dpll_reg = DPLL(0);
1729                 break;
1730         case PORT_D:
1731                 port_mask = DPLL_PORTD_READY_MASK;
1732                 dpll_reg = DPIO_PHY_STATUS;
1733                 break;
1734         default:
1735                 BUG();
1736         }
1737
1738         if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1739                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1740                      port_name(dport->port), I915_READ(dpll_reg));
1741 }
1742
1743 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1744 {
1745         struct drm_device *dev = crtc->base.dev;
1746         struct drm_i915_private *dev_priv = dev->dev_private;
1747         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1748
1749         WARN_ON(!pll->refcount);
1750         if (pll->active == 0) {
1751                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1752                 WARN_ON(pll->on);
1753                 assert_shared_dpll_disabled(dev_priv, pll);
1754
1755                 pll->mode_set(dev_priv, pll);
1756         }
1757 }
1758
1759 /**
1760  * intel_enable_shared_dpll - enable PCH PLL
1761  * @dev_priv: i915 private structure
1762  * @pipe: pipe PLL to enable
1763  *
1764  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1765  * drives the transcoder clock.
1766  */
1767 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1768 {
1769         struct drm_device *dev = crtc->base.dev;
1770         struct drm_i915_private *dev_priv = dev->dev_private;
1771         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1772
1773         if (WARN_ON(pll == NULL))
1774                 return;
1775
1776         if (WARN_ON(pll->refcount == 0))
1777                 return;
1778
1779         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1780                       pll->name, pll->active, pll->on,
1781                       crtc->base.base.id);
1782
1783         if (pll->active++) {
1784                 WARN_ON(!pll->on);
1785                 assert_shared_dpll_enabled(dev_priv, pll);
1786                 return;
1787         }
1788         WARN_ON(pll->on);
1789
1790         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1791         pll->enable(dev_priv, pll);
1792         pll->on = true;
1793 }
1794
1795 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1796 {
1797         struct drm_device *dev = crtc->base.dev;
1798         struct drm_i915_private *dev_priv = dev->dev_private;
1799         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1800
1801         /* PCH only available on ILK+ */
1802         BUG_ON(INTEL_INFO(dev)->gen < 5);
1803         if (WARN_ON(pll == NULL))
1804                return;
1805
1806         if (WARN_ON(pll->refcount == 0))
1807                 return;
1808
1809         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1810                       pll->name, pll->active, pll->on,
1811                       crtc->base.base.id);
1812
1813         if (WARN_ON(pll->active == 0)) {
1814                 assert_shared_dpll_disabled(dev_priv, pll);
1815                 return;
1816         }
1817
1818         assert_shared_dpll_enabled(dev_priv, pll);
1819         WARN_ON(!pll->on);
1820         if (--pll->active)
1821                 return;
1822
1823         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1824         pll->disable(dev_priv, pll);
1825         pll->on = false;
1826 }
1827
1828 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1829                                            enum pipe pipe)
1830 {
1831         struct drm_device *dev = dev_priv->dev;
1832         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1833         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1834         uint32_t reg, val, pipeconf_val;
1835
1836         /* PCH only available on ILK+ */
1837         BUG_ON(INTEL_INFO(dev)->gen < 5);
1838
1839         /* Make sure PCH DPLL is enabled */
1840         assert_shared_dpll_enabled(dev_priv,
1841                                    intel_crtc_to_shared_dpll(intel_crtc));
1842
1843         /* FDI must be feeding us bits for PCH ports */
1844         assert_fdi_tx_enabled(dev_priv, pipe);
1845         assert_fdi_rx_enabled(dev_priv, pipe);
1846
1847         if (HAS_PCH_CPT(dev)) {
1848                 /* Workaround: Set the timing override bit before enabling the
1849                  * pch transcoder. */
1850                 reg = TRANS_CHICKEN2(pipe);
1851                 val = I915_READ(reg);
1852                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1853                 I915_WRITE(reg, val);
1854         }
1855
1856         reg = PCH_TRANSCONF(pipe);
1857         val = I915_READ(reg);
1858         pipeconf_val = I915_READ(PIPECONF(pipe));
1859
1860         if (HAS_PCH_IBX(dev_priv->dev)) {
1861                 /*
1862                  * make the BPC in transcoder be consistent with
1863                  * that in pipeconf reg.
1864                  */
1865                 val &= ~PIPECONF_BPC_MASK;
1866                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1867         }
1868
1869         val &= ~TRANS_INTERLACE_MASK;
1870         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1871                 if (HAS_PCH_IBX(dev_priv->dev) &&
1872                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1873                         val |= TRANS_LEGACY_INTERLACED_ILK;
1874                 else
1875                         val |= TRANS_INTERLACED;
1876         else
1877                 val |= TRANS_PROGRESSIVE;
1878
1879         I915_WRITE(reg, val | TRANS_ENABLE);
1880         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1881                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1882 }
1883
1884 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1885                                       enum transcoder cpu_transcoder)
1886 {
1887         u32 val, pipeconf_val;
1888
1889         /* PCH only available on ILK+ */
1890         BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1891
1892         /* FDI must be feeding us bits for PCH ports */
1893         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1894         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1895
1896         /* Workaround: set timing override bit. */
1897         val = I915_READ(_TRANSA_CHICKEN2);
1898         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1899         I915_WRITE(_TRANSA_CHICKEN2, val);
1900
1901         val = TRANS_ENABLE;
1902         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1903
1904         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1905             PIPECONF_INTERLACED_ILK)
1906                 val |= TRANS_INTERLACED;
1907         else
1908                 val |= TRANS_PROGRESSIVE;
1909
1910         I915_WRITE(LPT_TRANSCONF, val);
1911         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1912                 DRM_ERROR("Failed to enable PCH transcoder\n");
1913 }
1914
1915 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1916                                             enum pipe pipe)
1917 {
1918         struct drm_device *dev = dev_priv->dev;
1919         uint32_t reg, val;
1920
1921         /* FDI relies on the transcoder */
1922         assert_fdi_tx_disabled(dev_priv, pipe);
1923         assert_fdi_rx_disabled(dev_priv, pipe);
1924
1925         /* Ports must be off as well */
1926         assert_pch_ports_disabled(dev_priv, pipe);
1927
1928         reg = PCH_TRANSCONF(pipe);
1929         val = I915_READ(reg);
1930         val &= ~TRANS_ENABLE;
1931         I915_WRITE(reg, val);
1932         /* wait for PCH transcoder off, transcoder state */
1933         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1934                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1935
1936         if (!HAS_PCH_IBX(dev)) {
1937                 /* Workaround: Clear the timing override chicken bit again. */
1938                 reg = TRANS_CHICKEN2(pipe);
1939                 val = I915_READ(reg);
1940                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1941                 I915_WRITE(reg, val);
1942         }
1943 }
1944
1945 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1946 {
1947         u32 val;
1948
1949         val = I915_READ(LPT_TRANSCONF);
1950         val &= ~TRANS_ENABLE;
1951         I915_WRITE(LPT_TRANSCONF, val);
1952         /* wait for PCH transcoder off, transcoder state */
1953         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1954                 DRM_ERROR("Failed to disable PCH transcoder\n");
1955
1956         /* Workaround: clear timing override bit. */
1957         val = I915_READ(_TRANSA_CHICKEN2);
1958         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1959         I915_WRITE(_TRANSA_CHICKEN2, val);
1960 }
1961
1962 /**
1963  * intel_enable_pipe - enable a pipe, asserting requirements
1964  * @crtc: crtc responsible for the pipe
1965  *
1966  * Enable @crtc's pipe, making sure that various hardware specific requirements
1967  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1968  */
1969 static void intel_enable_pipe(struct intel_crtc *crtc)
1970 {
1971         struct drm_device *dev = crtc->base.dev;
1972         struct drm_i915_private *dev_priv = dev->dev_private;
1973         enum pipe pipe = crtc->pipe;
1974         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1975                                                                       pipe);
1976         enum pipe pch_transcoder;
1977         int reg;
1978         u32 val;
1979
1980         assert_planes_disabled(dev_priv, pipe);
1981         assert_cursor_disabled(dev_priv, pipe);
1982         assert_sprites_disabled(dev_priv, pipe);
1983
1984         if (HAS_PCH_LPT(dev_priv->dev))
1985                 pch_transcoder = TRANSCODER_A;
1986         else
1987                 pch_transcoder = pipe;
1988
1989         /*
1990          * A pipe without a PLL won't actually be able to drive bits from
1991          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1992          * need the check.
1993          */
1994         if (!HAS_PCH_SPLIT(dev_priv->dev))
1995                 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
1996                         assert_dsi_pll_enabled(dev_priv);
1997                 else
1998                         assert_pll_enabled(dev_priv, pipe);
1999         else {
2000                 if (crtc->config.has_pch_encoder) {
2001                         /* if driving the PCH, we need FDI enabled */
2002                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2003                         assert_fdi_tx_pll_enabled(dev_priv,
2004                                                   (enum pipe) cpu_transcoder);
2005                 }
2006                 /* FIXME: assert CPU port conditions for SNB+ */
2007         }
2008
2009         reg = PIPECONF(cpu_transcoder);
2010         val = I915_READ(reg);
2011         if (val & PIPECONF_ENABLE) {
2012                 WARN_ON(!(pipe == PIPE_A &&
2013                           dev_priv->quirks & QUIRK_PIPEA_FORCE));
2014                 return;
2015         }
2016
2017         I915_WRITE(reg, val | PIPECONF_ENABLE);
2018         POSTING_READ(reg);
2019 }
2020
2021 /**
2022  * intel_disable_pipe - disable a pipe, asserting requirements
2023  * @dev_priv: i915 private structure
2024  * @pipe: pipe to disable
2025  *
2026  * Disable @pipe, making sure that various hardware specific requirements
2027  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
2028  *
2029  * @pipe should be %PIPE_A or %PIPE_B.
2030  *
2031  * Will wait until the pipe has shut down before returning.
2032  */
2033 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
2034                                enum pipe pipe)
2035 {
2036         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2037                                                                       pipe);
2038         int reg;
2039         u32 val;
2040
2041         /*
2042          * Make sure planes won't keep trying to pump pixels to us,
2043          * or we might hang the display.
2044          */
2045         assert_planes_disabled(dev_priv, pipe);
2046         assert_cursor_disabled(dev_priv, pipe);
2047         assert_sprites_disabled(dev_priv, pipe);
2048
2049         /* Don't disable pipe A or pipe A PLLs if needed */
2050         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2051                 return;
2052
2053         reg = PIPECONF(cpu_transcoder);
2054         val = I915_READ(reg);
2055         if ((val & PIPECONF_ENABLE) == 0)
2056                 return;
2057
2058         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
2059         intel_wait_for_pipe_off(dev_priv->dev, pipe);
2060 }
2061
2062 /*
2063  * Plane regs are double buffered, going from enabled->disabled needs a
2064  * trigger in order to latch.  The display address reg provides this.
2065  */
2066 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2067                                enum plane plane)
2068 {
2069         struct drm_device *dev = dev_priv->dev;
2070         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2071
2072         I915_WRITE(reg, I915_READ(reg));
2073         POSTING_READ(reg);
2074 }
2075
2076 /**
2077  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2078  * @dev_priv: i915 private structure
2079  * @plane: plane to enable
2080  * @pipe: pipe being fed
2081  *
2082  * Enable @plane on @pipe, making sure that @pipe is running first.
2083  */
2084 static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
2085                                           enum plane plane, enum pipe pipe)
2086 {
2087         struct intel_crtc *intel_crtc =
2088                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2089         int reg;
2090         u32 val;
2091
2092         /* If the pipe isn't enabled, we can't pump pixels and may hang */
2093         assert_pipe_enabled(dev_priv, pipe);
2094
2095         if (intel_crtc->primary_enabled)
2096                 return;
2097
2098         intel_crtc->primary_enabled = true;
2099
2100         reg = DSPCNTR(plane);
2101         val = I915_READ(reg);
2102         WARN_ON(val & DISPLAY_PLANE_ENABLE);
2103
2104         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
2105         intel_flush_primary_plane(dev_priv, plane);
2106         intel_wait_for_vblank(dev_priv->dev, pipe);
2107 }
2108
2109 /**
2110  * intel_disable_primary_hw_plane - disable the primary hardware plane
2111  * @dev_priv: i915 private structure
2112  * @plane: plane to disable
2113  * @pipe: pipe consuming the data
2114  *
2115  * Disable @plane; should be an independent operation.
2116  */
2117 static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
2118                                            enum plane plane, enum pipe pipe)
2119 {
2120         struct intel_crtc *intel_crtc =
2121                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2122         int reg;
2123         u32 val;
2124
2125         if (!intel_crtc->primary_enabled)
2126                 return;
2127
2128         intel_crtc->primary_enabled = false;
2129
2130         reg = DSPCNTR(plane);
2131         val = I915_READ(reg);
2132         WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0);
2133
2134         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
2135         intel_flush_primary_plane(dev_priv, plane);
2136         intel_wait_for_vblank(dev_priv->dev, pipe);
2137 }
2138
2139 static bool need_vtd_wa(struct drm_device *dev)
2140 {
2141 #ifdef CONFIG_INTEL_IOMMU
2142         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2143                 return true;
2144 #endif
2145         return false;
2146 }
2147
2148 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2149 {
2150         int tile_height;
2151
2152         tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2153         return ALIGN(height, tile_height);
2154 }
2155
2156 int
2157 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2158                            struct drm_i915_gem_object *obj,
2159                            struct intel_ring_buffer *pipelined)
2160 {
2161         struct drm_i915_private *dev_priv = dev->dev_private;
2162         u32 alignment;
2163         int ret;
2164
2165         switch (obj->tiling_mode) {
2166         case I915_TILING_NONE:
2167                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2168                         alignment = 128 * 1024;
2169                 else if (INTEL_INFO(dev)->gen >= 4)
2170                         alignment = 4 * 1024;
2171                 else
2172                         alignment = 64 * 1024;
2173                 break;
2174         case I915_TILING_X:
2175                 /* pin() will align the object as required by fence */
2176                 alignment = 0;
2177                 break;
2178         case I915_TILING_Y:
2179                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2180                 return -EINVAL;
2181         default:
2182                 BUG();
2183         }
2184
2185         /* Note that the w/a also requires 64 PTE of padding following the
2186          * bo. We currently fill all unused PTE with the shadow page and so
2187          * we should always have valid PTE following the scanout preventing
2188          * the VT-d warning.
2189          */
2190         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2191                 alignment = 256 * 1024;
2192
2193         dev_priv->mm.interruptible = false;
2194         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2195         if (ret)
2196                 goto err_interruptible;
2197
2198         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2199          * fence, whereas 965+ only requires a fence if using
2200          * framebuffer compression.  For simplicity, we always install
2201          * a fence as the cost is not that onerous.
2202          */
2203         ret = i915_gem_object_get_fence(obj);
2204         if (ret)
2205                 goto err_unpin;
2206
2207         i915_gem_object_pin_fence(obj);
2208
2209         dev_priv->mm.interruptible = true;
2210         return 0;
2211
2212 err_unpin:
2213         i915_gem_object_unpin_from_display_plane(obj);
2214 err_interruptible:
2215         dev_priv->mm.interruptible = true;
2216         return ret;
2217 }
2218
2219 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2220 {
2221         i915_gem_object_unpin_fence(obj);
2222         i915_gem_object_unpin_from_display_plane(obj);
2223 }
2224
2225 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2226  * is assumed to be a power-of-two. */
2227 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2228                                              unsigned int tiling_mode,
2229                                              unsigned int cpp,
2230                                              unsigned int pitch)
2231 {
2232         if (tiling_mode != I915_TILING_NONE) {
2233                 unsigned int tile_rows, tiles;
2234
2235                 tile_rows = *y / 8;
2236                 *y %= 8;
2237
2238                 tiles = *x / (512/cpp);
2239                 *x %= 512/cpp;
2240
2241                 return tile_rows * pitch * 8 + tiles * 4096;
2242         } else {
2243                 unsigned int offset;
2244
2245                 offset = *y * pitch + *x * cpp;
2246                 *y = 0;
2247                 *x = (offset & 4095) / cpp;
2248                 return offset & -4096;
2249         }
2250 }
2251
2252 int intel_format_to_fourcc(int format)
2253 {
2254         switch (format) {
2255         case DISPPLANE_8BPP:
2256                 return DRM_FORMAT_C8;
2257         case DISPPLANE_BGRX555:
2258                 return DRM_FORMAT_XRGB1555;
2259         case DISPPLANE_BGRX565:
2260                 return DRM_FORMAT_RGB565;
2261         default:
2262         case DISPPLANE_BGRX888:
2263                 return DRM_FORMAT_XRGB8888;
2264         case DISPPLANE_RGBX888:
2265                 return DRM_FORMAT_XBGR8888;
2266         case DISPPLANE_BGRX101010:
2267                 return DRM_FORMAT_XRGB2101010;
2268         case DISPPLANE_RGBX101010:
2269                 return DRM_FORMAT_XBGR2101010;
2270         }
2271 }
2272
2273 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2274                                   struct intel_plane_config *plane_config)
2275 {
2276         struct drm_device *dev = crtc->base.dev;
2277         struct drm_i915_gem_object *obj = NULL;
2278         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2279         u32 base = plane_config->base;
2280
2281         if (plane_config->size == 0)
2282                 return false;
2283
2284         obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2285                                                              plane_config->size);
2286         if (!obj)
2287                 return false;
2288
2289         if (plane_config->tiled) {
2290                 obj->tiling_mode = I915_TILING_X;
2291                 obj->stride = crtc->base.primary->fb->pitches[0];
2292         }
2293
2294         mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2295         mode_cmd.width = crtc->base.primary->fb->width;
2296         mode_cmd.height = crtc->base.primary->fb->height;
2297         mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2298
2299         mutex_lock(&dev->struct_mutex);
2300
2301         if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2302                                    &mode_cmd, obj)) {
2303                 DRM_DEBUG_KMS("intel fb init failed\n");
2304                 goto out_unref_obj;
2305         }
2306
2307         mutex_unlock(&dev->struct_mutex);
2308
2309         DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2310         return true;
2311
2312 out_unref_obj:
2313         drm_gem_object_unreference(&obj->base);
2314         mutex_unlock(&dev->struct_mutex);
2315         return false;
2316 }
2317
2318 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2319                                  struct intel_plane_config *plane_config)
2320 {
2321         struct drm_device *dev = intel_crtc->base.dev;
2322         struct drm_crtc *c;
2323         struct intel_crtc *i;
2324         struct intel_framebuffer *fb;
2325
2326         if (!intel_crtc->base.primary->fb)
2327                 return;
2328
2329         if (intel_alloc_plane_obj(intel_crtc, plane_config))
2330                 return;
2331
2332         kfree(intel_crtc->base.primary->fb);
2333         intel_crtc->base.primary->fb = NULL;
2334
2335         /*
2336          * Failed to alloc the obj, check to see if we should share
2337          * an fb with another CRTC instead
2338          */
2339         for_each_crtc(dev, c) {
2340                 i = to_intel_crtc(c);
2341
2342                 if (c == &intel_crtc->base)
2343                         continue;
2344
2345                 if (!i->active || !c->primary->fb)
2346                         continue;
2347
2348                 fb = to_intel_framebuffer(c->primary->fb);
2349                 if (i915_gem_obj_ggtt_offset(fb->obj) == plane_config->base) {
2350                         drm_framebuffer_reference(c->primary->fb);
2351                         intel_crtc->base.primary->fb = c->primary->fb;
2352                         break;
2353                 }
2354         }
2355 }
2356
2357 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2358                                       struct drm_framebuffer *fb,
2359                                       int x, int y)
2360 {
2361         struct drm_device *dev = crtc->dev;
2362         struct drm_i915_private *dev_priv = dev->dev_private;
2363         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2364         struct intel_framebuffer *intel_fb;
2365         struct drm_i915_gem_object *obj;
2366         int plane = intel_crtc->plane;
2367         unsigned long linear_offset;
2368         u32 dspcntr;
2369         u32 reg;
2370
2371         intel_fb = to_intel_framebuffer(fb);
2372         obj = intel_fb->obj;
2373
2374         reg = DSPCNTR(plane);
2375         dspcntr = I915_READ(reg);
2376         /* Mask out pixel format bits in case we change it */
2377         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2378         switch (fb->pixel_format) {
2379         case DRM_FORMAT_C8:
2380                 dspcntr |= DISPPLANE_8BPP;
2381                 break;
2382         case DRM_FORMAT_XRGB1555:
2383         case DRM_FORMAT_ARGB1555:
2384                 dspcntr |= DISPPLANE_BGRX555;
2385                 break;
2386         case DRM_FORMAT_RGB565:
2387                 dspcntr |= DISPPLANE_BGRX565;
2388                 break;
2389         case DRM_FORMAT_XRGB8888:
2390         case DRM_FORMAT_ARGB8888:
2391                 dspcntr |= DISPPLANE_BGRX888;
2392                 break;
2393         case DRM_FORMAT_XBGR8888:
2394         case DRM_FORMAT_ABGR8888:
2395                 dspcntr |= DISPPLANE_RGBX888;
2396                 break;
2397         case DRM_FORMAT_XRGB2101010:
2398         case DRM_FORMAT_ARGB2101010:
2399                 dspcntr |= DISPPLANE_BGRX101010;
2400                 break;
2401         case DRM_FORMAT_XBGR2101010:
2402         case DRM_FORMAT_ABGR2101010:
2403                 dspcntr |= DISPPLANE_RGBX101010;
2404                 break;
2405         default:
2406                 BUG();
2407         }
2408
2409         if (INTEL_INFO(dev)->gen >= 4) {
2410                 if (obj->tiling_mode != I915_TILING_NONE)
2411                         dspcntr |= DISPPLANE_TILED;
2412                 else
2413                         dspcntr &= ~DISPPLANE_TILED;
2414         }
2415
2416         if (IS_G4X(dev))
2417                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2418
2419         I915_WRITE(reg, dspcntr);
2420
2421         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2422
2423         if (INTEL_INFO(dev)->gen >= 4) {
2424                 intel_crtc->dspaddr_offset =
2425                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2426                                                        fb->bits_per_pixel / 8,
2427                                                        fb->pitches[0]);
2428                 linear_offset -= intel_crtc->dspaddr_offset;
2429         } else {
2430                 intel_crtc->dspaddr_offset = linear_offset;
2431         }
2432
2433         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2434                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2435                       fb->pitches[0]);
2436         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2437         if (INTEL_INFO(dev)->gen >= 4) {
2438                 I915_WRITE(DSPSURF(plane),
2439                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2440                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2441                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2442         } else
2443                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2444         POSTING_READ(reg);
2445 }
2446
2447 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2448                                           struct drm_framebuffer *fb,
2449                                           int x, int y)
2450 {
2451         struct drm_device *dev = crtc->dev;
2452         struct drm_i915_private *dev_priv = dev->dev_private;
2453         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2454         struct intel_framebuffer *intel_fb;
2455         struct drm_i915_gem_object *obj;
2456         int plane = intel_crtc->plane;
2457         unsigned long linear_offset;
2458         u32 dspcntr;
2459         u32 reg;
2460
2461         intel_fb = to_intel_framebuffer(fb);
2462         obj = intel_fb->obj;
2463
2464         reg = DSPCNTR(plane);
2465         dspcntr = I915_READ(reg);
2466         /* Mask out pixel format bits in case we change it */
2467         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2468         switch (fb->pixel_format) {
2469         case DRM_FORMAT_C8:
2470                 dspcntr |= DISPPLANE_8BPP;
2471                 break;
2472         case DRM_FORMAT_RGB565:
2473                 dspcntr |= DISPPLANE_BGRX565;
2474                 break;
2475         case DRM_FORMAT_XRGB8888:
2476         case DRM_FORMAT_ARGB8888:
2477                 dspcntr |= DISPPLANE_BGRX888;
2478                 break;
2479         case DRM_FORMAT_XBGR8888:
2480         case DRM_FORMAT_ABGR8888:
2481                 dspcntr |= DISPPLANE_RGBX888;
2482                 break;
2483         case DRM_FORMAT_XRGB2101010:
2484         case DRM_FORMAT_ARGB2101010:
2485                 dspcntr |= DISPPLANE_BGRX101010;
2486                 break;
2487         case DRM_FORMAT_XBGR2101010:
2488         case DRM_FORMAT_ABGR2101010:
2489                 dspcntr |= DISPPLANE_RGBX101010;
2490                 break;
2491         default:
2492                 BUG();
2493         }
2494
2495         if (obj->tiling_mode != I915_TILING_NONE)
2496                 dspcntr |= DISPPLANE_TILED;
2497         else
2498                 dspcntr &= ~DISPPLANE_TILED;
2499
2500         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2501                 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2502         else
2503                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2504
2505         I915_WRITE(reg, dspcntr);
2506
2507         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2508         intel_crtc->dspaddr_offset =
2509                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2510                                                fb->bits_per_pixel / 8,
2511                                                fb->pitches[0]);
2512         linear_offset -= intel_crtc->dspaddr_offset;
2513
2514         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2515                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2516                       fb->pitches[0]);
2517         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2518         I915_WRITE(DSPSURF(plane),
2519                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2520         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2521                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2522         } else {
2523                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2524                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2525         }
2526         POSTING_READ(reg);
2527 }
2528
2529 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2530 static int
2531 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2532                            int x, int y, enum mode_set_atomic state)
2533 {
2534         struct drm_device *dev = crtc->dev;
2535         struct drm_i915_private *dev_priv = dev->dev_private;
2536
2537         if (dev_priv->display.disable_fbc)
2538                 dev_priv->display.disable_fbc(dev);
2539         intel_increase_pllclock(crtc);
2540
2541         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2542
2543         return 0;
2544 }
2545
2546 void intel_display_handle_reset(struct drm_device *dev)
2547 {
2548         struct drm_i915_private *dev_priv = dev->dev_private;
2549         struct drm_crtc *crtc;
2550
2551         /*
2552          * Flips in the rings have been nuked by the reset,
2553          * so complete all pending flips so that user space
2554          * will get its events and not get stuck.
2555          *
2556          * Also update the base address of all primary
2557          * planes to the the last fb to make sure we're
2558          * showing the correct fb after a reset.
2559          *
2560          * Need to make two loops over the crtcs so that we
2561          * don't try to grab a crtc mutex before the
2562          * pending_flip_queue really got woken up.
2563          */
2564
2565         for_each_crtc(dev, crtc) {
2566                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2567                 enum plane plane = intel_crtc->plane;
2568
2569                 intel_prepare_page_flip(dev, plane);
2570                 intel_finish_page_flip_plane(dev, plane);
2571         }
2572
2573         for_each_crtc(dev, crtc) {
2574                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2575
2576                 mutex_lock(&crtc->mutex);
2577                 /*
2578                  * FIXME: Once we have proper support for primary planes (and
2579                  * disabling them without disabling the entire crtc) allow again
2580                  * a NULL crtc->primary->fb.
2581                  */
2582                 if (intel_crtc->active && crtc->primary->fb)
2583                         dev_priv->display.update_primary_plane(crtc,
2584                                                                crtc->primary->fb,
2585                                                                crtc->x,
2586                                                                crtc->y);
2587                 mutex_unlock(&crtc->mutex);
2588         }
2589 }
2590
2591 static int
2592 intel_finish_fb(struct drm_framebuffer *old_fb)
2593 {
2594         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2595         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2596         bool was_interruptible = dev_priv->mm.interruptible;
2597         int ret;
2598
2599         /* Big Hammer, we also need to ensure that any pending
2600          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2601          * current scanout is retired before unpinning the old
2602          * framebuffer.
2603          *
2604          * This should only fail upon a hung GPU, in which case we
2605          * can safely continue.
2606          */
2607         dev_priv->mm.interruptible = false;
2608         ret = i915_gem_object_finish_gpu(obj);
2609         dev_priv->mm.interruptible = was_interruptible;
2610
2611         return ret;
2612 }
2613
2614 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2615 {
2616         struct drm_device *dev = crtc->dev;
2617         struct drm_i915_private *dev_priv = dev->dev_private;
2618         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2619         unsigned long flags;
2620         bool pending;
2621
2622         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2623             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2624                 return false;
2625
2626         spin_lock_irqsave(&dev->event_lock, flags);
2627         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2628         spin_unlock_irqrestore(&dev->event_lock, flags);
2629
2630         return pending;
2631 }
2632
2633 static int
2634 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2635                     struct drm_framebuffer *fb)
2636 {
2637         struct drm_device *dev = crtc->dev;
2638         struct drm_i915_private *dev_priv = dev->dev_private;
2639         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2640         struct drm_framebuffer *old_fb;
2641         int ret;
2642
2643         if (intel_crtc_has_pending_flip(crtc)) {
2644                 DRM_ERROR("pipe is still busy with an old pageflip\n");
2645                 return -EBUSY;
2646         }
2647
2648         /* no fb bound */
2649         if (!fb) {
2650                 DRM_ERROR("No FB bound\n");
2651                 return 0;
2652         }
2653
2654         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2655                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2656                           plane_name(intel_crtc->plane),
2657                           INTEL_INFO(dev)->num_pipes);
2658                 return -EINVAL;
2659         }
2660
2661         mutex_lock(&dev->struct_mutex);
2662         ret = intel_pin_and_fence_fb_obj(dev,
2663                                          to_intel_framebuffer(fb)->obj,
2664                                          NULL);
2665         mutex_unlock(&dev->struct_mutex);
2666         if (ret != 0) {
2667                 DRM_ERROR("pin & fence failed\n");
2668                 return ret;
2669         }
2670
2671         /*
2672          * Update pipe size and adjust fitter if needed: the reason for this is
2673          * that in compute_mode_changes we check the native mode (not the pfit
2674          * mode) to see if we can flip rather than do a full mode set. In the
2675          * fastboot case, we'll flip, but if we don't update the pipesrc and
2676          * pfit state, we'll end up with a big fb scanned out into the wrong
2677          * sized surface.
2678          *
2679          * To fix this properly, we need to hoist the checks up into
2680          * compute_mode_changes (or above), check the actual pfit state and
2681          * whether the platform allows pfit disable with pipe active, and only
2682          * then update the pipesrc and pfit state, even on the flip path.
2683          */
2684         if (i915.fastboot) {
2685                 const struct drm_display_mode *adjusted_mode =
2686                         &intel_crtc->config.adjusted_mode;
2687
2688                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2689                            ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2690                            (adjusted_mode->crtc_vdisplay - 1));
2691                 if (!intel_crtc->config.pch_pfit.enabled &&
2692                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2693                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2694                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2695                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2696                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2697                 }
2698                 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2699                 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2700         }
2701
2702         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2703
2704         old_fb = crtc->primary->fb;
2705         crtc->primary->fb = fb;
2706         crtc->x = x;
2707         crtc->y = y;
2708
2709         if (old_fb) {
2710                 if (intel_crtc->active && old_fb != fb)
2711                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2712                 mutex_lock(&dev->struct_mutex);
2713                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2714                 mutex_unlock(&dev->struct_mutex);
2715         }
2716
2717         mutex_lock(&dev->struct_mutex);
2718         intel_update_fbc(dev);
2719         intel_edp_psr_update(dev);
2720         mutex_unlock(&dev->struct_mutex);
2721
2722         return 0;
2723 }
2724
2725 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2726 {
2727         struct drm_device *dev = crtc->dev;
2728         struct drm_i915_private *dev_priv = dev->dev_private;
2729         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2730         int pipe = intel_crtc->pipe;
2731         u32 reg, temp;
2732
2733         /* enable normal train */
2734         reg = FDI_TX_CTL(pipe);
2735         temp = I915_READ(reg);
2736         if (IS_IVYBRIDGE(dev)) {
2737                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2738                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2739         } else {
2740                 temp &= ~FDI_LINK_TRAIN_NONE;
2741                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2742         }
2743         I915_WRITE(reg, temp);
2744
2745         reg = FDI_RX_CTL(pipe);
2746         temp = I915_READ(reg);
2747         if (HAS_PCH_CPT(dev)) {
2748                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2749                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2750         } else {
2751                 temp &= ~FDI_LINK_TRAIN_NONE;
2752                 temp |= FDI_LINK_TRAIN_NONE;
2753         }
2754         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2755
2756         /* wait one idle pattern time */
2757         POSTING_READ(reg);
2758         udelay(1000);
2759
2760         /* IVB wants error correction enabled */
2761         if (IS_IVYBRIDGE(dev))
2762                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2763                            FDI_FE_ERRC_ENABLE);
2764 }
2765
2766 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2767 {
2768         return crtc->base.enabled && crtc->active &&
2769                 crtc->config.has_pch_encoder;
2770 }
2771
2772 static void ivb_modeset_global_resources(struct drm_device *dev)
2773 {
2774         struct drm_i915_private *dev_priv = dev->dev_private;
2775         struct intel_crtc *pipe_B_crtc =
2776                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2777         struct intel_crtc *pipe_C_crtc =
2778                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2779         uint32_t temp;
2780
2781         /*
2782          * When everything is off disable fdi C so that we could enable fdi B
2783          * with all lanes. Note that we don't care about enabled pipes without
2784          * an enabled pch encoder.
2785          */
2786         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2787             !pipe_has_enabled_pch(pipe_C_crtc)) {
2788                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2789                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2790
2791                 temp = I915_READ(SOUTH_CHICKEN1);
2792                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2793                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2794                 I915_WRITE(SOUTH_CHICKEN1, temp);
2795         }
2796 }
2797
2798 /* The FDI link training functions for ILK/Ibexpeak. */
2799 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2800 {
2801         struct drm_device *dev = crtc->dev;
2802         struct drm_i915_private *dev_priv = dev->dev_private;
2803         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2804         int pipe = intel_crtc->pipe;
2805         u32 reg, temp, tries;
2806
2807         /* FDI needs bits from pipe first */
2808         assert_pipe_enabled(dev_priv, pipe);
2809
2810         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2811            for train result */
2812         reg = FDI_RX_IMR(pipe);
2813         temp = I915_READ(reg);
2814         temp &= ~FDI_RX_SYMBOL_LOCK;
2815         temp &= ~FDI_RX_BIT_LOCK;
2816         I915_WRITE(reg, temp);
2817         I915_READ(reg);
2818         udelay(150);
2819
2820         /* enable CPU FDI TX and PCH FDI RX */
2821         reg = FDI_TX_CTL(pipe);
2822         temp = I915_READ(reg);
2823         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2824         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2825         temp &= ~FDI_LINK_TRAIN_NONE;
2826         temp |= FDI_LINK_TRAIN_PATTERN_1;
2827         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2828
2829         reg = FDI_RX_CTL(pipe);
2830         temp = I915_READ(reg);
2831         temp &= ~FDI_LINK_TRAIN_NONE;
2832         temp |= FDI_LINK_TRAIN_PATTERN_1;
2833         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2834
2835         POSTING_READ(reg);
2836         udelay(150);
2837
2838         /* Ironlake workaround, enable clock pointer after FDI enable*/
2839         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2840         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2841                    FDI_RX_PHASE_SYNC_POINTER_EN);
2842
2843         reg = FDI_RX_IIR(pipe);
2844         for (tries = 0; tries < 5; tries++) {
2845                 temp = I915_READ(reg);
2846                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2847
2848                 if ((temp & FDI_RX_BIT_LOCK)) {
2849                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2850                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2851                         break;
2852                 }
2853         }
2854         if (tries == 5)
2855                 DRM_ERROR("FDI train 1 fail!\n");
2856
2857         /* Train 2 */
2858         reg = FDI_TX_CTL(pipe);
2859         temp = I915_READ(reg);
2860         temp &= ~FDI_LINK_TRAIN_NONE;
2861         temp |= FDI_LINK_TRAIN_PATTERN_2;
2862         I915_WRITE(reg, temp);
2863
2864         reg = FDI_RX_CTL(pipe);
2865         temp = I915_READ(reg);
2866         temp &= ~FDI_LINK_TRAIN_NONE;
2867         temp |= FDI_LINK_TRAIN_PATTERN_2;
2868         I915_WRITE(reg, temp);
2869
2870         POSTING_READ(reg);
2871         udelay(150);
2872
2873         reg = FDI_RX_IIR(pipe);
2874         for (tries = 0; tries < 5; tries++) {
2875                 temp = I915_READ(reg);
2876                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2877
2878                 if (temp & FDI_RX_SYMBOL_LOCK) {
2879                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2880                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2881                         break;
2882                 }
2883         }
2884         if (tries == 5)
2885                 DRM_ERROR("FDI train 2 fail!\n");
2886
2887         DRM_DEBUG_KMS("FDI train done\n");
2888
2889 }
2890
2891 static const int snb_b_fdi_train_param[] = {
2892         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2893         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2894         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2895         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2896 };
2897
2898 /* The FDI link training functions for SNB/Cougarpoint. */
2899 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2900 {
2901         struct drm_device *dev = crtc->dev;
2902         struct drm_i915_private *dev_priv = dev->dev_private;
2903         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2904         int pipe = intel_crtc->pipe;
2905         u32 reg, temp, i, retry;
2906
2907         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2908            for train result */
2909         reg = FDI_RX_IMR(pipe);
2910         temp = I915_READ(reg);
2911         temp &= ~FDI_RX_SYMBOL_LOCK;
2912         temp &= ~FDI_RX_BIT_LOCK;
2913         I915_WRITE(reg, temp);
2914
2915         POSTING_READ(reg);
2916         udelay(150);
2917
2918         /* enable CPU FDI TX and PCH FDI RX */
2919         reg = FDI_TX_CTL(pipe);
2920         temp = I915_READ(reg);
2921         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2922         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2923         temp &= ~FDI_LINK_TRAIN_NONE;
2924         temp |= FDI_LINK_TRAIN_PATTERN_1;
2925         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2926         /* SNB-B */
2927         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2928         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2929
2930         I915_WRITE(FDI_RX_MISC(pipe),
2931                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2932
2933         reg = FDI_RX_CTL(pipe);
2934         temp = I915_READ(reg);
2935         if (HAS_PCH_CPT(dev)) {
2936                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2937                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2938         } else {
2939                 temp &= ~FDI_LINK_TRAIN_NONE;
2940                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2941         }
2942         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2943
2944         POSTING_READ(reg);
2945         udelay(150);
2946
2947         for (i = 0; i < 4; i++) {
2948                 reg = FDI_TX_CTL(pipe);
2949                 temp = I915_READ(reg);
2950                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2951                 temp |= snb_b_fdi_train_param[i];
2952                 I915_WRITE(reg, temp);
2953
2954                 POSTING_READ(reg);
2955                 udelay(500);
2956
2957                 for (retry = 0; retry < 5; retry++) {
2958                         reg = FDI_RX_IIR(pipe);
2959                         temp = I915_READ(reg);
2960                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2961                         if (temp & FDI_RX_BIT_LOCK) {
2962                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2963                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2964                                 break;
2965                         }
2966                         udelay(50);
2967                 }
2968                 if (retry < 5)
2969                         break;
2970         }
2971         if (i == 4)
2972                 DRM_ERROR("FDI train 1 fail!\n");
2973
2974         /* Train 2 */
2975         reg = FDI_TX_CTL(pipe);
2976         temp = I915_READ(reg);
2977         temp &= ~FDI_LINK_TRAIN_NONE;
2978         temp |= FDI_LINK_TRAIN_PATTERN_2;
2979         if (IS_GEN6(dev)) {
2980                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2981                 /* SNB-B */
2982                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2983         }
2984         I915_WRITE(reg, temp);
2985
2986         reg = FDI_RX_CTL(pipe);
2987         temp = I915_READ(reg);
2988         if (HAS_PCH_CPT(dev)) {
2989                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2990                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2991         } else {
2992                 temp &= ~FDI_LINK_TRAIN_NONE;
2993                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2994         }
2995         I915_WRITE(reg, temp);
2996
2997         POSTING_READ(reg);
2998         udelay(150);
2999
3000         for (i = 0; i < 4; i++) {
3001                 reg = FDI_TX_CTL(pipe);
3002                 temp = I915_READ(reg);
3003                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3004                 temp |= snb_b_fdi_train_param[i];
3005                 I915_WRITE(reg, temp);
3006
3007                 POSTING_READ(reg);
3008                 udelay(500);
3009
3010                 for (retry = 0; retry < 5; retry++) {
3011                         reg = FDI_RX_IIR(pipe);
3012                         temp = I915_READ(reg);
3013                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3014                         if (temp & FDI_RX_SYMBOL_LOCK) {
3015                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3016                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3017                                 break;
3018                         }
3019                         udelay(50);
3020                 }
3021                 if (retry < 5)
3022                         break;
3023         }
3024         if (i == 4)
3025                 DRM_ERROR("FDI train 2 fail!\n");
3026
3027         DRM_DEBUG_KMS("FDI train done.\n");
3028 }
3029
3030 /* Manual link training for Ivy Bridge A0 parts */
3031 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3032 {
3033         struct drm_device *dev = crtc->dev;
3034         struct drm_i915_private *dev_priv = dev->dev_private;
3035         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3036         int pipe = intel_crtc->pipe;
3037         u32 reg, temp, i, j;
3038
3039         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3040            for train result */
3041         reg = FDI_RX_IMR(pipe);
3042         temp = I915_READ(reg);
3043         temp &= ~FDI_RX_SYMBOL_LOCK;
3044         temp &= ~FDI_RX_BIT_LOCK;
3045         I915_WRITE(reg, temp);
3046
3047         POSTING_READ(reg);
3048         udelay(150);
3049
3050         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3051                       I915_READ(FDI_RX_IIR(pipe)));
3052
3053         /* Try each vswing and preemphasis setting twice before moving on */
3054         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3055                 /* disable first in case we need to retry */
3056                 reg = FDI_TX_CTL(pipe);
3057                 temp = I915_READ(reg);
3058                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3059                 temp &= ~FDI_TX_ENABLE;
3060                 I915_WRITE(reg, temp);
3061
3062                 reg = FDI_RX_CTL(pipe);
3063                 temp = I915_READ(reg);
3064                 temp &= ~FDI_LINK_TRAIN_AUTO;
3065                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3066                 temp &= ~FDI_RX_ENABLE;
3067                 I915_WRITE(reg, temp);
3068
3069                 /* enable CPU FDI TX and PCH FDI RX */
3070                 reg = FDI_TX_CTL(pipe);
3071                 temp = I915_READ(reg);
3072                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3073                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3074                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3075                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3076                 temp |= snb_b_fdi_train_param[j/2];
3077                 temp |= FDI_COMPOSITE_SYNC;
3078                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3079
3080                 I915_WRITE(FDI_RX_MISC(pipe),
3081                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3082
3083                 reg = FDI_RX_CTL(pipe);
3084                 temp = I915_READ(reg);
3085                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3086                 temp |= FDI_COMPOSITE_SYNC;
3087                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3088
3089                 POSTING_READ(reg);
3090                 udelay(1); /* should be 0.5us */
3091
3092                 for (i = 0; i < 4; i++) {
3093                         reg = FDI_RX_IIR(pipe);
3094                         temp = I915_READ(reg);
3095                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3096
3097                         if (temp & FDI_RX_BIT_LOCK ||
3098                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3099                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3100                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3101                                               i);
3102                                 break;
3103                         }
3104                         udelay(1); /* should be 0.5us */
3105                 }
3106                 if (i == 4) {
3107                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3108                         continue;
3109                 }
3110
3111                 /* Train 2 */
3112                 reg = FDI_TX_CTL(pipe);
3113                 temp = I915_READ(reg);
3114                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3115                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3116                 I915_WRITE(reg, temp);
3117
3118                 reg = FDI_RX_CTL(pipe);
3119                 temp = I915_READ(reg);
3120                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3121                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3122                 I915_WRITE(reg, temp);
3123
3124                 POSTING_READ(reg);
3125                 udelay(2); /* should be 1.5us */
3126
3127                 for (i = 0; i < 4; i++) {
3128                         reg = FDI_RX_IIR(pipe);
3129                         temp = I915_READ(reg);
3130                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3131
3132                         if (temp & FDI_RX_SYMBOL_LOCK ||
3133                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3134                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3135                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3136                                               i);
3137                                 goto train_done;
3138                         }
3139                         udelay(2); /* should be 1.5us */
3140                 }
3141                 if (i == 4)
3142                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3143         }
3144
3145 train_done:
3146         DRM_DEBUG_KMS("FDI train done.\n");
3147 }
3148
3149 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3150 {
3151         struct drm_device *dev = intel_crtc->base.dev;
3152         struct drm_i915_private *dev_priv = dev->dev_private;
3153         int pipe = intel_crtc->pipe;
3154         u32 reg, temp;
3155
3156
3157         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3158         reg = FDI_RX_CTL(pipe);
3159         temp = I915_READ(reg);
3160         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3161         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3162         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3163         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3164
3165         POSTING_READ(reg);
3166         udelay(200);
3167
3168         /* Switch from Rawclk to PCDclk */
3169         temp = I915_READ(reg);
3170         I915_WRITE(reg, temp | FDI_PCDCLK);
3171
3172         POSTING_READ(reg);
3173         udelay(200);
3174
3175         /* Enable CPU FDI TX PLL, always on for Ironlake */
3176         reg = FDI_TX_CTL(pipe);
3177         temp = I915_READ(reg);
3178         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3179                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3180
3181                 POSTING_READ(reg);
3182                 udelay(100);
3183         }
3184 }
3185
3186 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3187 {
3188         struct drm_device *dev = intel_crtc->base.dev;
3189         struct drm_i915_private *dev_priv = dev->dev_private;
3190         int pipe = intel_crtc->pipe;
3191         u32 reg, temp;
3192
3193         /* Switch from PCDclk to Rawclk */
3194         reg = FDI_RX_CTL(pipe);
3195         temp = I915_READ(reg);
3196         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3197
3198         /* Disable CPU FDI TX PLL */
3199         reg = FDI_TX_CTL(pipe);
3200         temp = I915_READ(reg);
3201         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3202
3203         POSTING_READ(reg);
3204         udelay(100);
3205
3206         reg = FDI_RX_CTL(pipe);
3207         temp = I915_READ(reg);
3208         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3209
3210         /* Wait for the clocks to turn off. */
3211         POSTING_READ(reg);
3212         udelay(100);
3213 }
3214
3215 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3216 {
3217         struct drm_device *dev = crtc->dev;
3218         struct drm_i915_private *dev_priv = dev->dev_private;
3219         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3220         int pipe = intel_crtc->pipe;
3221         u32 reg, temp;
3222
3223         /* disable CPU FDI tx and PCH FDI rx */
3224         reg = FDI_TX_CTL(pipe);
3225         temp = I915_READ(reg);
3226         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3227         POSTING_READ(reg);
3228
3229         reg = FDI_RX_CTL(pipe);
3230         temp = I915_READ(reg);
3231         temp &= ~(0x7 << 16);
3232         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3233         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3234
3235         POSTING_READ(reg);
3236         udelay(100);
3237
3238         /* Ironlake workaround, disable clock pointer after downing FDI */
3239         if (HAS_PCH_IBX(dev))
3240                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3241
3242         /* still set train pattern 1 */
3243         reg = FDI_TX_CTL(pipe);
3244         temp = I915_READ(reg);
3245         temp &= ~FDI_LINK_TRAIN_NONE;
3246         temp |= FDI_LINK_TRAIN_PATTERN_1;
3247         I915_WRITE(reg, temp);
3248
3249         reg = FDI_RX_CTL(pipe);
3250         temp = I915_READ(reg);
3251         if (HAS_PCH_CPT(dev)) {
3252                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3253                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3254         } else {
3255                 temp &= ~FDI_LINK_TRAIN_NONE;
3256                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3257         }
3258         /* BPC in FDI rx is consistent with that in PIPECONF */
3259         temp &= ~(0x07 << 16);
3260         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3261         I915_WRITE(reg, temp);
3262
3263         POSTING_READ(reg);
3264         udelay(100);
3265 }
3266
3267 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3268 {
3269         struct intel_crtc *crtc;
3270
3271         /* Note that we don't need to be called with mode_config.lock here
3272          * as our list of CRTC objects is static for the lifetime of the
3273          * device and so cannot disappear as we iterate. Similarly, we can
3274          * happily treat the predicates as racy, atomic checks as userspace
3275          * cannot claim and pin a new fb without at least acquring the
3276          * struct_mutex and so serialising with us.
3277          */
3278         for_each_intel_crtc(dev, crtc) {
3279                 if (atomic_read(&crtc->unpin_work_count) == 0)
3280                         continue;
3281
3282                 if (crtc->unpin_work)
3283                         intel_wait_for_vblank(dev, crtc->pipe);
3284
3285                 return true;
3286         }
3287
3288         return false;
3289 }
3290
3291 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3292 {
3293         struct drm_device *dev = crtc->dev;
3294         struct drm_i915_private *dev_priv = dev->dev_private;
3295
3296         if (crtc->primary->fb == NULL)
3297                 return;
3298
3299         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3300
3301         WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3302                                    !intel_crtc_has_pending_flip(crtc),
3303                                    60*HZ) == 0);
3304
3305         mutex_lock(&dev->struct_mutex);
3306         intel_finish_fb(crtc->primary->fb);
3307         mutex_unlock(&dev->struct_mutex);
3308 }
3309
3310 /* Program iCLKIP clock to the desired frequency */
3311 static void lpt_program_iclkip(struct drm_crtc *crtc)
3312 {
3313         struct drm_device *dev = crtc->dev;
3314         struct drm_i915_private *dev_priv = dev->dev_private;
3315         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3316         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3317         u32 temp;
3318
3319         mutex_lock(&dev_priv->dpio_lock);
3320
3321         /* It is necessary to ungate the pixclk gate prior to programming
3322          * the divisors, and gate it back when it is done.
3323          */
3324         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3325
3326         /* Disable SSCCTL */
3327         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3328                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3329                                 SBI_SSCCTL_DISABLE,
3330                         SBI_ICLK);
3331
3332         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3333         if (clock == 20000) {
3334                 auxdiv = 1;
3335                 divsel = 0x41;
3336                 phaseinc = 0x20;
3337         } else {
3338                 /* The iCLK virtual clock root frequency is in MHz,
3339                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3340                  * divisors, it is necessary to divide one by another, so we
3341                  * convert the virtual clock precision to KHz here for higher
3342                  * precision.
3343                  */
3344                 u32 iclk_virtual_root_freq = 172800 * 1000;
3345                 u32 iclk_pi_range = 64;
3346                 u32 desired_divisor, msb_divisor_value, pi_value;
3347
3348                 desired_divisor = (iclk_virtual_root_freq / clock);
3349                 msb_divisor_value = desired_divisor / iclk_pi_range;
3350                 pi_value = desired_divisor % iclk_pi_range;
3351
3352                 auxdiv = 0;
3353                 divsel = msb_divisor_value - 2;
3354                 phaseinc = pi_value;
3355         }
3356
3357         /* This should not happen with any sane values */
3358         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3359                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3360         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3361                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3362
3363         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3364                         clock,
3365                         auxdiv,
3366                         divsel,
3367                         phasedir,
3368                         phaseinc);
3369
3370         /* Program SSCDIVINTPHASE6 */
3371         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3372         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3373         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3374         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3375         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3376         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3377         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3378         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3379
3380         /* Program SSCAUXDIV */
3381         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3382         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3383         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3384         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3385
3386         /* Enable modulator and associated divider */
3387         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3388         temp &= ~SBI_SSCCTL_DISABLE;
3389         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3390
3391         /* Wait for initialization time */
3392         udelay(24);
3393
3394         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3395
3396         mutex_unlock(&dev_priv->dpio_lock);
3397 }
3398
3399 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3400                                                 enum pipe pch_transcoder)
3401 {
3402         struct drm_device *dev = crtc->base.dev;
3403         struct drm_i915_private *dev_priv = dev->dev_private;
3404         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3405
3406         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3407                    I915_READ(HTOTAL(cpu_transcoder)));
3408         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3409                    I915_READ(HBLANK(cpu_transcoder)));
3410         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3411                    I915_READ(HSYNC(cpu_transcoder)));
3412
3413         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3414                    I915_READ(VTOTAL(cpu_transcoder)));
3415         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3416                    I915_READ(VBLANK(cpu_transcoder)));
3417         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3418                    I915_READ(VSYNC(cpu_transcoder)));
3419         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3420                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3421 }
3422
3423 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3424 {
3425         struct drm_i915_private *dev_priv = dev->dev_private;
3426         uint32_t temp;
3427
3428         temp = I915_READ(SOUTH_CHICKEN1);
3429         if (temp & FDI_BC_BIFURCATION_SELECT)
3430                 return;
3431
3432         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3433         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3434
3435         temp |= FDI_BC_BIFURCATION_SELECT;
3436         DRM_DEBUG_KMS("enabling fdi C rx\n");
3437         I915_WRITE(SOUTH_CHICKEN1, temp);
3438         POSTING_READ(SOUTH_CHICKEN1);
3439 }
3440
3441 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3442 {
3443         struct drm_device *dev = intel_crtc->base.dev;
3444         struct drm_i915_private *dev_priv = dev->dev_private;
3445
3446         switch (intel_crtc->pipe) {
3447         case PIPE_A:
3448                 break;
3449         case PIPE_B:
3450                 if (intel_crtc->config.fdi_lanes > 2)
3451                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3452                 else
3453                         cpt_enable_fdi_bc_bifurcation(dev);
3454
3455                 break;
3456         case PIPE_C:
3457                 cpt_enable_fdi_bc_bifurcation(dev);
3458
3459                 break;
3460         default:
3461                 BUG();
3462         }
3463 }
3464
3465 /*
3466  * Enable PCH resources required for PCH ports:
3467  *   - PCH PLLs
3468  *   - FDI training & RX/TX
3469  *   - update transcoder timings
3470  *   - DP transcoding bits
3471  *   - transcoder
3472  */
3473 static void ironlake_pch_enable(struct drm_crtc *crtc)
3474 {
3475         struct drm_device *dev = crtc->dev;
3476         struct drm_i915_private *dev_priv = dev->dev_private;
3477         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3478         int pipe = intel_crtc->pipe;
3479         u32 reg, temp;
3480
3481         assert_pch_transcoder_disabled(dev_priv, pipe);
3482
3483         if (IS_IVYBRIDGE(dev))
3484                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3485
3486         /* Write the TU size bits before fdi link training, so that error
3487          * detection works. */
3488         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3489                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3490
3491         /* For PCH output, training FDI link */
3492         dev_priv->display.fdi_link_train(crtc);
3493
3494         /* We need to program the right clock selection before writing the pixel
3495          * mutliplier into the DPLL. */
3496         if (HAS_PCH_CPT(dev)) {
3497                 u32 sel;
3498
3499                 temp = I915_READ(PCH_DPLL_SEL);
3500                 temp |= TRANS_DPLL_ENABLE(pipe);
3501                 sel = TRANS_DPLLB_SEL(pipe);
3502                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3503                         temp |= sel;
3504                 else
3505                         temp &= ~sel;
3506                 I915_WRITE(PCH_DPLL_SEL, temp);
3507         }
3508
3509         /* XXX: pch pll's can be enabled any time before we enable the PCH
3510          * transcoder, and we actually should do this to not upset any PCH
3511          * transcoder that already use the clock when we share it.
3512          *
3513          * Note that enable_shared_dpll tries to do the right thing, but
3514          * get_shared_dpll unconditionally resets the pll - we need that to have
3515          * the right LVDS enable sequence. */
3516         intel_enable_shared_dpll(intel_crtc);
3517
3518         /* set transcoder timing, panel must allow it */
3519         assert_panel_unlocked(dev_priv, pipe);
3520         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3521
3522         intel_fdi_normal_train(crtc);
3523
3524         /* For PCH DP, enable TRANS_DP_CTL */
3525         if (HAS_PCH_CPT(dev) &&
3526             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3527              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3528                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3529                 reg = TRANS_DP_CTL(pipe);
3530                 temp = I915_READ(reg);
3531                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3532                           TRANS_DP_SYNC_MASK |
3533                           TRANS_DP_BPC_MASK);
3534                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3535                          TRANS_DP_ENH_FRAMING);
3536                 temp |= bpc << 9; /* same format but at 11:9 */
3537
3538                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3539                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3540                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3541                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3542
3543                 switch (intel_trans_dp_port_sel(crtc)) {
3544                 case PCH_DP_B:
3545                         temp |= TRANS_DP_PORT_SEL_B;
3546                         break;
3547                 case PCH_DP_C:
3548                         temp |= TRANS_DP_PORT_SEL_C;
3549                         break;
3550                 case PCH_DP_D:
3551                         temp |= TRANS_DP_PORT_SEL_D;
3552                         break;
3553                 default:
3554                         BUG();
3555                 }
3556
3557                 I915_WRITE(reg, temp);
3558         }
3559
3560         ironlake_enable_pch_transcoder(dev_priv, pipe);
3561 }
3562
3563 static void lpt_pch_enable(struct drm_crtc *crtc)
3564 {
3565         struct drm_device *dev = crtc->dev;
3566         struct drm_i915_private *dev_priv = dev->dev_private;
3567         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3568         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3569
3570         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3571
3572         lpt_program_iclkip(crtc);
3573
3574         /* Set transcoder timing. */
3575         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3576
3577         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3578 }
3579
3580 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3581 {
3582         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3583
3584         if (pll == NULL)
3585                 return;
3586
3587         if (pll->refcount == 0) {
3588                 WARN(1, "bad %s refcount\n", pll->name);
3589                 return;
3590         }
3591
3592         if (--pll->refcount == 0) {
3593                 WARN_ON(pll->on);
3594                 WARN_ON(pll->active);
3595         }
3596
3597         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3598 }
3599
3600 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3601 {
3602         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3603         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3604         enum intel_dpll_id i;
3605
3606         if (pll) {
3607                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3608                               crtc->base.base.id, pll->name);
3609                 intel_put_shared_dpll(crtc);
3610         }
3611
3612         if (HAS_PCH_IBX(dev_priv->dev)) {
3613                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3614                 i = (enum intel_dpll_id) crtc->pipe;
3615                 pll = &dev_priv->shared_dplls[i];
3616
3617                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3618                               crtc->base.base.id, pll->name);
3619
3620                 WARN_ON(pll->refcount);
3621
3622                 goto found;
3623         }
3624
3625         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3626                 pll = &dev_priv->shared_dplls[i];
3627
3628                 /* Only want to check enabled timings first */
3629                 if (pll->refcount == 0)
3630                         continue;
3631
3632                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3633                            sizeof(pll->hw_state)) == 0) {
3634                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3635                                       crtc->base.base.id,
3636                                       pll->name, pll->refcount, pll->active);
3637
3638                         goto found;
3639                 }
3640         }
3641
3642         /* Ok no matching timings, maybe there's a free one? */
3643         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3644                 pll = &dev_priv->shared_dplls[i];
3645                 if (pll->refcount == 0) {
3646                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3647                                       crtc->base.base.id, pll->name);
3648                         goto found;
3649                 }
3650         }
3651
3652         return NULL;
3653
3654 found:
3655         if (pll->refcount == 0)
3656                 pll->hw_state = crtc->config.dpll_hw_state;
3657
3658         crtc->config.shared_dpll = i;
3659         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3660                          pipe_name(crtc->pipe));
3661
3662         pll->refcount++;
3663
3664         return pll;
3665 }
3666
3667 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3668 {
3669         struct drm_i915_private *dev_priv = dev->dev_private;
3670         int dslreg = PIPEDSL(pipe);
3671         u32 temp;
3672
3673         temp = I915_READ(dslreg);
3674         udelay(500);
3675         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3676                 if (wait_for(I915_READ(dslreg) != temp, 5))
3677                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3678         }
3679 }
3680
3681 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3682 {
3683         struct drm_device *dev = crtc->base.dev;
3684         struct drm_i915_private *dev_priv = dev->dev_private;
3685         int pipe = crtc->pipe;
3686
3687         if (crtc->config.pch_pfit.enabled) {
3688                 /* Force use of hard-coded filter coefficients
3689                  * as some pre-programmed values are broken,
3690                  * e.g. x201.
3691                  */
3692                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3693                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3694                                                  PF_PIPE_SEL_IVB(pipe));
3695                 else
3696                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3697                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3698                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3699         }
3700 }
3701
3702 static void intel_enable_planes(struct drm_crtc *crtc)
3703 {
3704         struct drm_device *dev = crtc->dev;
3705         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3706         struct drm_plane *plane;
3707         struct intel_plane *intel_plane;
3708
3709         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3710                 intel_plane = to_intel_plane(plane);
3711                 if (intel_plane->pipe == pipe)
3712                         intel_plane_restore(&intel_plane->base);
3713         }
3714 }
3715
3716 static void intel_disable_planes(struct drm_crtc *crtc)
3717 {
3718         struct drm_device *dev = crtc->dev;
3719         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3720         struct drm_plane *plane;
3721         struct intel_plane *intel_plane;
3722
3723         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3724                 intel_plane = to_intel_plane(plane);
3725                 if (intel_plane->pipe == pipe)
3726                         intel_plane_disable(&intel_plane->base);
3727         }
3728 }
3729
3730 void hsw_enable_ips(struct intel_crtc *crtc)
3731 {
3732         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3733
3734         if (!crtc->config.ips_enabled)
3735                 return;
3736
3737         /* We can only enable IPS after we enable a plane and wait for a vblank.
3738          * We guarantee that the plane is enabled by calling intel_enable_ips
3739          * only after intel_enable_plane. And intel_enable_plane already waits
3740          * for a vblank, so all we need to do here is to enable the IPS bit. */
3741         assert_plane_enabled(dev_priv, crtc->plane);
3742         if (IS_BROADWELL(crtc->base.dev)) {
3743                 mutex_lock(&dev_priv->rps.hw_lock);
3744                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3745                 mutex_unlock(&dev_priv->rps.hw_lock);
3746                 /* Quoting Art Runyan: "its not safe to expect any particular
3747                  * value in IPS_CTL bit 31 after enabling IPS through the
3748                  * mailbox." Moreover, the mailbox may return a bogus state,
3749                  * so we need to just enable it and continue on.
3750                  */
3751         } else {
3752                 I915_WRITE(IPS_CTL, IPS_ENABLE);
3753                 /* The bit only becomes 1 in the next vblank, so this wait here
3754                  * is essentially intel_wait_for_vblank. If we don't have this
3755                  * and don't wait for vblanks until the end of crtc_enable, then
3756                  * the HW state readout code will complain that the expected
3757                  * IPS_CTL value is not the one we read. */
3758                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3759                         DRM_ERROR("Timed out waiting for IPS enable\n");
3760         }
3761 }
3762
3763 void hsw_disable_ips(struct intel_crtc *crtc)
3764 {
3765         struct drm_device *dev = crtc->base.dev;
3766         struct drm_i915_private *dev_priv = dev->dev_private;
3767
3768         if (!crtc->config.ips_enabled)
3769                 return;
3770
3771         assert_plane_enabled(dev_priv, crtc->plane);
3772         if (IS_BROADWELL(dev)) {
3773                 mutex_lock(&dev_priv->rps.hw_lock);
3774                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3775                 mutex_unlock(&dev_priv->rps.hw_lock);
3776                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3777                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3778                         DRM_ERROR("Timed out waiting for IPS disable\n");
3779         } else {
3780                 I915_WRITE(IPS_CTL, 0);
3781                 POSTING_READ(IPS_CTL);
3782         }
3783
3784         /* We need to wait for a vblank before we can disable the plane. */
3785         intel_wait_for_vblank(dev, crtc->pipe);
3786 }
3787
3788 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3789 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3790 {
3791         struct drm_device *dev = crtc->dev;
3792         struct drm_i915_private *dev_priv = dev->dev_private;
3793         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3794         enum pipe pipe = intel_crtc->pipe;
3795         int palreg = PALETTE(pipe);
3796         int i;
3797         bool reenable_ips = false;
3798
3799         /* The clocks have to be on to load the palette. */
3800         if (!crtc->enabled || !intel_crtc->active)
3801                 return;
3802
3803         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3804                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3805                         assert_dsi_pll_enabled(dev_priv);
3806                 else
3807                         assert_pll_enabled(dev_priv, pipe);
3808         }
3809
3810         /* use legacy palette for Ironlake */
3811         if (HAS_PCH_SPLIT(dev))
3812                 palreg = LGC_PALETTE(pipe);
3813
3814         /* Workaround : Do not read or write the pipe palette/gamma data while
3815          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3816          */
3817         if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3818             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3819              GAMMA_MODE_MODE_SPLIT)) {
3820                 hsw_disable_ips(intel_crtc);
3821                 reenable_ips = true;
3822         }
3823
3824         for (i = 0; i < 256; i++) {
3825                 I915_WRITE(palreg + 4 * i,
3826                            (intel_crtc->lut_r[i] << 16) |
3827                            (intel_crtc->lut_g[i] << 8) |
3828                            intel_crtc->lut_b[i]);
3829         }
3830
3831         if (reenable_ips)
3832                 hsw_enable_ips(intel_crtc);
3833 }
3834
3835 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3836 {
3837         if (!enable && intel_crtc->overlay) {
3838                 struct drm_device *dev = intel_crtc->base.dev;
3839                 struct drm_i915_private *dev_priv = dev->dev_private;
3840
3841                 mutex_lock(&dev->struct_mutex);
3842                 dev_priv->mm.interruptible = false;
3843                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3844                 dev_priv->mm.interruptible = true;
3845                 mutex_unlock(&dev->struct_mutex);
3846         }
3847
3848         /* Let userspace switch the overlay on again. In most cases userspace
3849          * has to recompute where to put it anyway.
3850          */
3851 }
3852
3853 /**
3854  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3855  * cursor plane briefly if not already running after enabling the display
3856  * plane.
3857  * This workaround avoids occasional blank screens when self refresh is
3858  * enabled.
3859  */
3860 static void
3861 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3862 {
3863         u32 cntl = I915_READ(CURCNTR(pipe));
3864
3865         if ((cntl & CURSOR_MODE) == 0) {
3866                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3867
3868                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3869                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3870                 intel_wait_for_vblank(dev_priv->dev, pipe);
3871                 I915_WRITE(CURCNTR(pipe), cntl);
3872                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3873                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3874         }
3875 }
3876
3877 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
3878 {
3879         struct drm_device *dev = crtc->dev;
3880         struct drm_i915_private *dev_priv = dev->dev_private;
3881         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3882         int pipe = intel_crtc->pipe;
3883         int plane = intel_crtc->plane;
3884
3885         intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3886         intel_enable_planes(crtc);
3887         /* The fixup needs to happen before cursor is enabled */
3888         if (IS_G4X(dev))
3889                 g4x_fixup_plane(dev_priv, pipe);
3890         intel_crtc_update_cursor(crtc, true);
3891         intel_crtc_dpms_overlay(intel_crtc, true);
3892
3893         hsw_enable_ips(intel_crtc);
3894
3895         mutex_lock(&dev->struct_mutex);
3896         intel_update_fbc(dev);
3897         intel_edp_psr_update(dev);
3898         mutex_unlock(&dev->struct_mutex);
3899 }
3900
3901 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
3902 {
3903         struct drm_device *dev = crtc->dev;
3904         struct drm_i915_private *dev_priv = dev->dev_private;
3905         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3906         int pipe = intel_crtc->pipe;
3907         int plane = intel_crtc->plane;
3908
3909         intel_crtc_wait_for_pending_flips(crtc);
3910         drm_vblank_off(dev, pipe);
3911
3912         if (dev_priv->fbc.plane == plane)
3913                 intel_disable_fbc(dev);
3914
3915         hsw_disable_ips(intel_crtc);
3916
3917         intel_crtc_dpms_overlay(intel_crtc, false);
3918         intel_crtc_update_cursor(crtc, false);
3919         intel_disable_planes(crtc);
3920         intel_disable_primary_hw_plane(dev_priv, plane, pipe);
3921 }
3922
3923 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3924 {
3925         struct drm_device *dev = crtc->dev;
3926         struct drm_i915_private *dev_priv = dev->dev_private;
3927         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3928         struct intel_encoder *encoder;
3929         int pipe = intel_crtc->pipe;
3930         enum plane plane = intel_crtc->plane;
3931
3932         WARN_ON(!crtc->enabled);
3933
3934         if (intel_crtc->active)
3935                 return;
3936
3937         if (intel_crtc->config.has_pch_encoder)
3938                 intel_prepare_shared_dpll(intel_crtc);
3939
3940         if (intel_crtc->config.has_dp_encoder)
3941                 intel_dp_set_m_n(intel_crtc);
3942
3943         intel_set_pipe_timings(intel_crtc);
3944
3945         if (intel_crtc->config.has_pch_encoder) {
3946                 intel_cpu_transcoder_set_m_n(intel_crtc,
3947                                              &intel_crtc->config.fdi_m_n);
3948         }
3949
3950         ironlake_set_pipeconf(crtc);
3951
3952         /* Set up the display plane register */
3953         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
3954         POSTING_READ(DSPCNTR(plane));
3955
3956         dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
3957                                                crtc->x, crtc->y);
3958
3959         intel_crtc->active = true;
3960
3961         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3962         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3963
3964         for_each_encoder_on_crtc(dev, crtc, encoder)
3965                 if (encoder->pre_enable)
3966                         encoder->pre_enable(encoder);
3967
3968         if (intel_crtc->config.has_pch_encoder) {
3969                 /* Note: FDI PLL enabling _must_ be done before we enable the
3970                  * cpu pipes, hence this is separate from all the other fdi/pch
3971                  * enabling. */
3972                 ironlake_fdi_pll_enable(intel_crtc);
3973         } else {
3974                 assert_fdi_tx_disabled(dev_priv, pipe);
3975                 assert_fdi_rx_disabled(dev_priv, pipe);
3976         }
3977
3978         ironlake_pfit_enable(intel_crtc);
3979
3980         /*
3981          * On ILK+ LUT must be loaded before the pipe is running but with
3982          * clocks enabled
3983          */
3984         intel_crtc_load_lut(crtc);
3985
3986         intel_update_watermarks(crtc);
3987         intel_enable_pipe(intel_crtc);
3988
3989         if (intel_crtc->config.has_pch_encoder)
3990                 ironlake_pch_enable(crtc);
3991
3992         for_each_encoder_on_crtc(dev, crtc, encoder)
3993                 encoder->enable(encoder);
3994
3995         if (HAS_PCH_CPT(dev))
3996                 cpt_verify_modeset(dev, intel_crtc->pipe);
3997
3998         intel_crtc_enable_planes(crtc);
3999
4000         /*
4001          * There seems to be a race in PCH platform hw (at least on some
4002          * outputs) where an enabled pipe still completes any pageflip right
4003          * away (as if the pipe is off) instead of waiting for vblank. As soon
4004          * as the first vblank happend, everything works as expected. Hence just
4005          * wait for one vblank before returning to avoid strange things
4006          * happening.
4007          */
4008         intel_wait_for_vblank(dev, intel_crtc->pipe);
4009 }
4010
4011 /* IPS only exists on ULT machines and is tied to pipe A. */
4012 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4013 {
4014         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4015 }
4016
4017 /*
4018  * This implements the workaround described in the "notes" section of the mode
4019  * set sequence documentation. When going from no pipes or single pipe to
4020  * multiple pipes, and planes are enabled after the pipe, we need to wait at
4021  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4022  */
4023 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4024 {
4025         struct drm_device *dev = crtc->base.dev;
4026         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4027
4028         /* We want to get the other_active_crtc only if there's only 1 other
4029          * active crtc. */
4030         for_each_intel_crtc(dev, crtc_it) {
4031                 if (!crtc_it->active || crtc_it == crtc)
4032                         continue;
4033
4034                 if (other_active_crtc)
4035                         return;
4036
4037                 other_active_crtc = crtc_it;
4038         }
4039         if (!other_active_crtc)
4040                 return;
4041
4042         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4043         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4044 }
4045
4046 static void haswell_crtc_enable(struct drm_crtc *crtc)
4047 {
4048         struct drm_device *dev = crtc->dev;
4049         struct drm_i915_private *dev_priv = dev->dev_private;
4050         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4051         struct intel_encoder *encoder;
4052         int pipe = intel_crtc->pipe;
4053         enum plane plane = intel_crtc->plane;
4054
4055         WARN_ON(!crtc->enabled);
4056
4057         if (intel_crtc->active)
4058                 return;
4059
4060         if (intel_crtc->config.has_dp_encoder)
4061                 intel_dp_set_m_n(intel_crtc);
4062
4063         intel_set_pipe_timings(intel_crtc);
4064
4065         if (intel_crtc->config.has_pch_encoder) {
4066                 intel_cpu_transcoder_set_m_n(intel_crtc,
4067                                              &intel_crtc->config.fdi_m_n);
4068         }
4069
4070         haswell_set_pipeconf(crtc);
4071
4072         intel_set_pipe_csc(crtc);
4073
4074         /* Set up the display plane register */
4075         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
4076         POSTING_READ(DSPCNTR(plane));
4077
4078         dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4079                                                crtc->x, crtc->y);
4080
4081         intel_crtc->active = true;
4082
4083         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4084         if (intel_crtc->config.has_pch_encoder)
4085                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4086
4087         if (intel_crtc->config.has_pch_encoder)
4088                 dev_priv->display.fdi_link_train(crtc);
4089
4090         for_each_encoder_on_crtc(dev, crtc, encoder)
4091                 if (encoder->pre_enable)
4092                         encoder->pre_enable(encoder);
4093
4094         intel_ddi_enable_pipe_clock(intel_crtc);
4095
4096         ironlake_pfit_enable(intel_crtc);
4097
4098         /*
4099          * On ILK+ LUT must be loaded before the pipe is running but with
4100          * clocks enabled
4101          */
4102         intel_crtc_load_lut(crtc);
4103
4104         intel_ddi_set_pipe_settings(crtc);
4105         intel_ddi_enable_transcoder_func(crtc);
4106
4107         intel_update_watermarks(crtc);
4108         intel_enable_pipe(intel_crtc);
4109
4110         if (intel_crtc->config.has_pch_encoder)
4111                 lpt_pch_enable(crtc);
4112
4113         for_each_encoder_on_crtc(dev, crtc, encoder) {
4114                 encoder->enable(encoder);
4115                 intel_opregion_notify_encoder(encoder, true);
4116         }
4117
4118         /* If we change the relative order between pipe/planes enabling, we need
4119          * to change the workaround. */
4120         haswell_mode_set_planes_workaround(intel_crtc);
4121         intel_crtc_enable_planes(crtc);
4122 }
4123
4124 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4125 {
4126         struct drm_device *dev = crtc->base.dev;
4127         struct drm_i915_private *dev_priv = dev->dev_private;
4128         int pipe = crtc->pipe;
4129
4130         /* To avoid upsetting the power well on haswell only disable the pfit if
4131          * it's in use. The hw state code will make sure we get this right. */
4132         if (crtc->config.pch_pfit.enabled) {
4133                 I915_WRITE(PF_CTL(pipe), 0);
4134                 I915_WRITE(PF_WIN_POS(pipe), 0);
4135                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4136         }
4137 }
4138
4139 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4140 {
4141         struct drm_device *dev = crtc->dev;
4142         struct drm_i915_private *dev_priv = dev->dev_private;
4143         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4144         struct intel_encoder *encoder;
4145         int pipe = intel_crtc->pipe;
4146         u32 reg, temp;
4147
4148         if (!intel_crtc->active)
4149                 return;
4150
4151         intel_crtc_disable_planes(crtc);
4152
4153         for_each_encoder_on_crtc(dev, crtc, encoder)
4154                 encoder->disable(encoder);
4155
4156         if (intel_crtc->config.has_pch_encoder)
4157                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4158
4159         intel_disable_pipe(dev_priv, pipe);
4160
4161         ironlake_pfit_disable(intel_crtc);
4162
4163         for_each_encoder_on_crtc(dev, crtc, encoder)
4164                 if (encoder->post_disable)
4165                         encoder->post_disable(encoder);
4166
4167         if (intel_crtc->config.has_pch_encoder) {
4168                 ironlake_fdi_disable(crtc);
4169
4170                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4171                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4172
4173                 if (HAS_PCH_CPT(dev)) {
4174                         /* disable TRANS_DP_CTL */
4175                         reg = TRANS_DP_CTL(pipe);
4176                         temp = I915_READ(reg);
4177                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4178                                   TRANS_DP_PORT_SEL_MASK);
4179                         temp |= TRANS_DP_PORT_SEL_NONE;
4180                         I915_WRITE(reg, temp);
4181
4182                         /* disable DPLL_SEL */
4183                         temp = I915_READ(PCH_DPLL_SEL);
4184                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4185                         I915_WRITE(PCH_DPLL_SEL, temp);
4186                 }
4187
4188                 /* disable PCH DPLL */
4189                 intel_disable_shared_dpll(intel_crtc);
4190
4191                 ironlake_fdi_pll_disable(intel_crtc);
4192         }
4193
4194         intel_crtc->active = false;
4195         intel_update_watermarks(crtc);
4196
4197         mutex_lock(&dev->struct_mutex);
4198         intel_update_fbc(dev);
4199         intel_edp_psr_update(dev);
4200         mutex_unlock(&dev->struct_mutex);
4201 }
4202
4203 static void haswell_crtc_disable(struct drm_crtc *crtc)
4204 {
4205         struct drm_device *dev = crtc->dev;
4206         struct drm_i915_private *dev_priv = dev->dev_private;
4207         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4208         struct intel_encoder *encoder;
4209         int pipe = intel_crtc->pipe;
4210         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4211
4212         if (!intel_crtc->active)
4213                 return;
4214
4215         intel_crtc_disable_planes(crtc);
4216
4217         for_each_encoder_on_crtc(dev, crtc, encoder) {
4218                 intel_opregion_notify_encoder(encoder, false);
4219                 encoder->disable(encoder);
4220         }
4221
4222         if (intel_crtc->config.has_pch_encoder)
4223                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4224         intel_disable_pipe(dev_priv, pipe);
4225
4226         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4227
4228         ironlake_pfit_disable(intel_crtc);
4229
4230         intel_ddi_disable_pipe_clock(intel_crtc);
4231
4232         for_each_encoder_on_crtc(dev, crtc, encoder)
4233                 if (encoder->post_disable)
4234                         encoder->post_disable(encoder);
4235
4236         if (intel_crtc->config.has_pch_encoder) {
4237                 lpt_disable_pch_transcoder(dev_priv);
4238                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4239                 intel_ddi_fdi_disable(crtc);
4240         }
4241
4242         intel_crtc->active = false;
4243         intel_update_watermarks(crtc);
4244
4245         mutex_lock(&dev->struct_mutex);
4246         intel_update_fbc(dev);
4247         intel_edp_psr_update(dev);
4248         mutex_unlock(&dev->struct_mutex);
4249 }
4250
4251 static void ironlake_crtc_off(struct drm_crtc *crtc)
4252 {
4253         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4254         intel_put_shared_dpll(intel_crtc);
4255 }
4256
4257 static void haswell_crtc_off(struct drm_crtc *crtc)
4258 {
4259         intel_ddi_put_crtc_pll(crtc);
4260 }
4261
4262 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4263 {
4264         struct drm_device *dev = crtc->base.dev;
4265         struct drm_i915_private *dev_priv = dev->dev_private;
4266         struct intel_crtc_config *pipe_config = &crtc->config;
4267
4268         if (!crtc->config.gmch_pfit.control)
4269                 return;
4270
4271         /*
4272          * The panel fitter should only be adjusted whilst the pipe is disabled,
4273          * according to register description and PRM.
4274          */
4275         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4276         assert_pipe_disabled(dev_priv, crtc->pipe);
4277
4278         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4279         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4280
4281         /* Border color in case we don't scale up to the full screen. Black by
4282          * default, change to something else for debugging. */
4283         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4284 }
4285
4286 #define for_each_power_domain(domain, mask)                             \
4287         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4288                 if ((1 << (domain)) & (mask))
4289
4290 enum intel_display_power_domain
4291 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4292 {
4293         struct drm_device *dev = intel_encoder->base.dev;
4294         struct intel_digital_port *intel_dig_port;
4295
4296         switch (intel_encoder->type) {
4297         case INTEL_OUTPUT_UNKNOWN:
4298                 /* Only DDI platforms should ever use this output type */
4299                 WARN_ON_ONCE(!HAS_DDI(dev));
4300         case INTEL_OUTPUT_DISPLAYPORT:
4301         case INTEL_OUTPUT_HDMI:
4302         case INTEL_OUTPUT_EDP:
4303                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4304                 switch (intel_dig_port->port) {
4305                 case PORT_A:
4306                         return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4307                 case PORT_B:
4308                         return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4309                 case PORT_C:
4310                         return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4311                 case PORT_D:
4312                         return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4313                 default:
4314                         WARN_ON_ONCE(1);
4315                         return POWER_DOMAIN_PORT_OTHER;
4316                 }
4317         case INTEL_OUTPUT_ANALOG:
4318                 return POWER_DOMAIN_PORT_CRT;
4319         case INTEL_OUTPUT_DSI:
4320                 return POWER_DOMAIN_PORT_DSI;
4321         default:
4322                 return POWER_DOMAIN_PORT_OTHER;
4323         }
4324 }
4325
4326 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4327 {
4328         struct drm_device *dev = crtc->dev;
4329         struct intel_encoder *intel_encoder;
4330         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4331         enum pipe pipe = intel_crtc->pipe;
4332         bool pfit_enabled = intel_crtc->config.pch_pfit.enabled;
4333         unsigned long mask;
4334         enum transcoder transcoder;
4335
4336         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4337
4338         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4339         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4340         if (pfit_enabled)
4341                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4342
4343         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4344                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4345
4346         return mask;
4347 }
4348
4349 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4350                                   bool enable)
4351 {
4352         if (dev_priv->power_domains.init_power_on == enable)
4353                 return;
4354
4355         if (enable)
4356                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4357         else
4358                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4359
4360         dev_priv->power_domains.init_power_on = enable;
4361 }
4362
4363 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4364 {
4365         struct drm_i915_private *dev_priv = dev->dev_private;
4366         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4367         struct intel_crtc *crtc;
4368
4369         /*
4370          * First get all needed power domains, then put all unneeded, to avoid
4371          * any unnecessary toggling of the power wells.
4372          */
4373         for_each_intel_crtc(dev, crtc) {
4374                 enum intel_display_power_domain domain;
4375
4376                 if (!crtc->base.enabled)
4377                         continue;
4378
4379                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4380
4381                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4382                         intel_display_power_get(dev_priv, domain);
4383         }
4384
4385         for_each_intel_crtc(dev, crtc) {
4386                 enum intel_display_power_domain domain;
4387
4388                 for_each_power_domain(domain, crtc->enabled_power_domains)
4389                         intel_display_power_put(dev_priv, domain);
4390
4391                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4392         }
4393
4394         intel_display_set_init_power(dev_priv, false);
4395 }
4396
4397 int valleyview_get_vco(struct drm_i915_private *dev_priv)
4398 {
4399         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4400
4401         /* Obtain SKU information */
4402         mutex_lock(&dev_priv->dpio_lock);
4403         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4404                 CCK_FUSE_HPLL_FREQ_MASK;
4405         mutex_unlock(&dev_priv->dpio_lock);
4406
4407         return vco_freq[hpll_freq];
4408 }
4409
4410 /* Adjust CDclk dividers to allow high res or save power if possible */
4411 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4412 {
4413         struct drm_i915_private *dev_priv = dev->dev_private;
4414         u32 val, cmd;
4415
4416         WARN_ON(valleyview_cur_cdclk(dev_priv) != dev_priv->vlv_cdclk_freq);
4417         dev_priv->vlv_cdclk_freq = cdclk;
4418
4419         if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
4420                 cmd = 2;
4421         else if (cdclk == 266)
4422                 cmd = 1;
4423         else
4424                 cmd = 0;
4425
4426         mutex_lock(&dev_priv->rps.hw_lock);
4427         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4428         val &= ~DSPFREQGUAR_MASK;
4429         val |= (cmd << DSPFREQGUAR_SHIFT);
4430         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4431         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4432                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4433                      50)) {
4434                 DRM_ERROR("timed out waiting for CDclk change\n");
4435         }
4436         mutex_unlock(&dev_priv->rps.hw_lock);
4437
4438         if (cdclk == 400) {
4439                 u32 divider, vco;
4440
4441                 vco = valleyview_get_vco(dev_priv);
4442                 divider = ((vco << 1) / cdclk) - 1;
4443
4444                 mutex_lock(&dev_priv->dpio_lock);
4445                 /* adjust cdclk divider */
4446                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4447                 val &= ~0xf;
4448                 val |= divider;
4449                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4450                 mutex_unlock(&dev_priv->dpio_lock);
4451         }
4452
4453         mutex_lock(&dev_priv->dpio_lock);
4454         /* adjust self-refresh exit latency value */
4455         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4456         val &= ~0x7f;
4457
4458         /*
4459          * For high bandwidth configs, we set a higher latency in the bunit
4460          * so that the core display fetch happens in time to avoid underruns.
4461          */
4462         if (cdclk == 400)
4463                 val |= 4500 / 250; /* 4.5 usec */
4464         else
4465                 val |= 3000 / 250; /* 3.0 usec */
4466         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4467         mutex_unlock(&dev_priv->dpio_lock);
4468
4469         /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4470         intel_i2c_reset(dev);
4471 }
4472
4473 int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4474 {
4475         int cur_cdclk, vco;
4476         int divider;
4477
4478         vco = valleyview_get_vco(dev_priv);
4479
4480         mutex_lock(&dev_priv->dpio_lock);
4481         divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4482         mutex_unlock(&dev_priv->dpio_lock);
4483
4484         divider &= 0xf;
4485
4486         cur_cdclk = (vco << 1) / (divider + 1);
4487
4488         return cur_cdclk;
4489 }
4490
4491 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4492                                  int max_pixclk)
4493 {
4494         /*
4495          * Really only a few cases to deal with, as only 4 CDclks are supported:
4496          *   200MHz
4497          *   267MHz
4498          *   320MHz
4499          *   400MHz
4500          * So we check to see whether we're above 90% of the lower bin and
4501          * adjust if needed.
4502          */
4503         if (max_pixclk > 288000) {
4504                 return 400;
4505         } else if (max_pixclk > 240000) {
4506                 return 320;
4507         } else
4508                 return 266;
4509         /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4510 }
4511
4512 /* compute the max pixel clock for new configuration */
4513 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4514 {
4515         struct drm_device *dev = dev_priv->dev;
4516         struct intel_crtc *intel_crtc;
4517         int max_pixclk = 0;
4518
4519         for_each_intel_crtc(dev, intel_crtc) {
4520                 if (intel_crtc->new_enabled)
4521                         max_pixclk = max(max_pixclk,
4522                                          intel_crtc->new_config->adjusted_mode.crtc_clock);
4523         }
4524
4525         return max_pixclk;
4526 }
4527
4528 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4529                                             unsigned *prepare_pipes)
4530 {
4531         struct drm_i915_private *dev_priv = dev->dev_private;
4532         struct intel_crtc *intel_crtc;
4533         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4534
4535         if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4536             dev_priv->vlv_cdclk_freq)
4537                 return;
4538
4539         /* disable/enable all currently active pipes while we change cdclk */
4540         for_each_intel_crtc(dev, intel_crtc)
4541                 if (intel_crtc->base.enabled)
4542                         *prepare_pipes |= (1 << intel_crtc->pipe);
4543 }
4544
4545 static void valleyview_modeset_global_resources(struct drm_device *dev)
4546 {
4547         struct drm_i915_private *dev_priv = dev->dev_private;
4548         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4549         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4550
4551         if (req_cdclk != dev_priv->vlv_cdclk_freq)
4552                 valleyview_set_cdclk(dev, req_cdclk);
4553         modeset_update_crtc_power_domains(dev);
4554 }
4555
4556 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4557 {
4558         struct drm_device *dev = crtc->dev;
4559         struct drm_i915_private *dev_priv = dev->dev_private;
4560         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4561         struct intel_encoder *encoder;
4562         int pipe = intel_crtc->pipe;
4563         int plane = intel_crtc->plane;
4564         bool is_dsi;
4565         u32 dspcntr;
4566
4567         WARN_ON(!crtc->enabled);
4568
4569         if (intel_crtc->active)
4570                 return;
4571
4572         vlv_prepare_pll(intel_crtc);
4573
4574         /* Set up the display plane register */
4575         dspcntr = DISPPLANE_GAMMA_ENABLE;
4576
4577         if (intel_crtc->config.has_dp_encoder)
4578                 intel_dp_set_m_n(intel_crtc);
4579
4580         intel_set_pipe_timings(intel_crtc);
4581
4582         /* pipesrc and dspsize control the size that is scaled from,
4583          * which should always be the user's requested size.
4584          */
4585         I915_WRITE(DSPSIZE(plane),
4586                    ((intel_crtc->config.pipe_src_h - 1) << 16) |
4587                    (intel_crtc->config.pipe_src_w - 1));
4588         I915_WRITE(DSPPOS(plane), 0);
4589
4590         i9xx_set_pipeconf(intel_crtc);
4591
4592         I915_WRITE(DSPCNTR(plane), dspcntr);
4593         POSTING_READ(DSPCNTR(plane));
4594
4595         dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4596                                                crtc->x, crtc->y);
4597
4598         intel_crtc->active = true;
4599
4600         for_each_encoder_on_crtc(dev, crtc, encoder)
4601                 if (encoder->pre_pll_enable)
4602                         encoder->pre_pll_enable(encoder);
4603
4604         is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4605
4606         if (!is_dsi) {
4607                 if (IS_CHERRYVIEW(dev))
4608                         chv_enable_pll(intel_crtc);
4609                 else
4610                         vlv_enable_pll(intel_crtc);
4611         }
4612
4613         for_each_encoder_on_crtc(dev, crtc, encoder)
4614                 if (encoder->pre_enable)
4615                         encoder->pre_enable(encoder);
4616
4617         i9xx_pfit_enable(intel_crtc);
4618
4619         intel_crtc_load_lut(crtc);
4620
4621         intel_update_watermarks(crtc);
4622         intel_enable_pipe(intel_crtc);
4623         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4624
4625         for_each_encoder_on_crtc(dev, crtc, encoder)
4626                 encoder->enable(encoder);
4627
4628         intel_crtc_enable_planes(crtc);
4629 }
4630
4631 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4632 {
4633         struct drm_device *dev = crtc->base.dev;
4634         struct drm_i915_private *dev_priv = dev->dev_private;
4635
4636         I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4637         I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4638 }
4639
4640 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4641 {
4642         struct drm_device *dev = crtc->dev;
4643         struct drm_i915_private *dev_priv = dev->dev_private;
4644         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4645         struct intel_encoder *encoder;
4646         int pipe = intel_crtc->pipe;
4647         int plane = intel_crtc->plane;
4648         u32 dspcntr;
4649
4650         WARN_ON(!crtc->enabled);
4651
4652         if (intel_crtc->active)
4653                 return;
4654
4655         i9xx_set_pll_dividers(intel_crtc);
4656
4657         /* Set up the display plane register */
4658         dspcntr = DISPPLANE_GAMMA_ENABLE;
4659
4660         if (pipe == 0)
4661                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4662         else
4663                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4664
4665         if (intel_crtc->config.has_dp_encoder)
4666                 intel_dp_set_m_n(intel_crtc);
4667
4668         intel_set_pipe_timings(intel_crtc);
4669
4670         /* pipesrc and dspsize control the size that is scaled from,
4671          * which should always be the user's requested size.
4672          */
4673         I915_WRITE(DSPSIZE(plane),
4674                    ((intel_crtc->config.pipe_src_h - 1) << 16) |
4675                    (intel_crtc->config.pipe_src_w - 1));
4676         I915_WRITE(DSPPOS(plane), 0);
4677
4678         i9xx_set_pipeconf(intel_crtc);
4679
4680         I915_WRITE(DSPCNTR(plane), dspcntr);
4681         POSTING_READ(DSPCNTR(plane));
4682
4683         dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4684                                                crtc->x, crtc->y);
4685
4686         intel_crtc->active = true;
4687
4688         for_each_encoder_on_crtc(dev, crtc, encoder)
4689                 if (encoder->pre_enable)
4690                         encoder->pre_enable(encoder);
4691
4692         i9xx_enable_pll(intel_crtc);
4693
4694         i9xx_pfit_enable(intel_crtc);
4695
4696         intel_crtc_load_lut(crtc);
4697
4698         intel_update_watermarks(crtc);
4699         intel_enable_pipe(intel_crtc);
4700         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4701
4702         for_each_encoder_on_crtc(dev, crtc, encoder)
4703                 encoder->enable(encoder);
4704
4705         intel_crtc_enable_planes(crtc);
4706 }
4707
4708 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4709 {
4710         struct drm_device *dev = crtc->base.dev;
4711         struct drm_i915_private *dev_priv = dev->dev_private;
4712
4713         if (!crtc->config.gmch_pfit.control)
4714                 return;
4715
4716         assert_pipe_disabled(dev_priv, crtc->pipe);
4717
4718         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4719                          I915_READ(PFIT_CONTROL));
4720         I915_WRITE(PFIT_CONTROL, 0);
4721 }
4722
4723 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4724 {
4725         struct drm_device *dev = crtc->dev;
4726         struct drm_i915_private *dev_priv = dev->dev_private;
4727         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4728         struct intel_encoder *encoder;
4729         int pipe = intel_crtc->pipe;
4730
4731         if (!intel_crtc->active)
4732                 return;
4733
4734         intel_crtc_disable_planes(crtc);
4735
4736         for_each_encoder_on_crtc(dev, crtc, encoder)
4737                 encoder->disable(encoder);
4738
4739         intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4740         intel_disable_pipe(dev_priv, pipe);
4741
4742         i9xx_pfit_disable(intel_crtc);
4743
4744         for_each_encoder_on_crtc(dev, crtc, encoder)
4745                 if (encoder->post_disable)
4746                         encoder->post_disable(encoder);
4747
4748         if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4749                 if (IS_CHERRYVIEW(dev))
4750                         chv_disable_pll(dev_priv, pipe);
4751                 else if (IS_VALLEYVIEW(dev))
4752                         vlv_disable_pll(dev_priv, pipe);
4753                 else
4754                         i9xx_disable_pll(dev_priv, pipe);
4755         }
4756
4757         intel_crtc->active = false;
4758         intel_update_watermarks(crtc);
4759
4760         mutex_lock(&dev->struct_mutex);
4761         intel_update_fbc(dev);
4762         intel_edp_psr_update(dev);
4763         mutex_unlock(&dev->struct_mutex);
4764 }
4765
4766 static void i9xx_crtc_off(struct drm_crtc *crtc)
4767 {
4768 }
4769
4770 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4771                                     bool enabled)
4772 {
4773         struct drm_device *dev = crtc->dev;
4774         struct drm_i915_master_private *master_priv;
4775         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4776         int pipe = intel_crtc->pipe;
4777
4778         if (!dev->primary->master)
4779                 return;
4780
4781         master_priv = dev->primary->master->driver_priv;
4782         if (!master_priv->sarea_priv)
4783                 return;
4784
4785         switch (pipe) {
4786         case 0:
4787                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4788                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4789                 break;
4790         case 1:
4791                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4792                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4793                 break;
4794         default:
4795                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4796                 break;
4797         }
4798 }
4799
4800 /**
4801  * Sets the power management mode of the pipe and plane.
4802  */
4803 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4804 {
4805         struct drm_device *dev = crtc->dev;
4806         struct drm_i915_private *dev_priv = dev->dev_private;
4807         struct intel_encoder *intel_encoder;
4808         bool enable = false;
4809
4810         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4811                 enable |= intel_encoder->connectors_active;
4812
4813         if (enable)
4814                 dev_priv->display.crtc_enable(crtc);
4815         else
4816                 dev_priv->display.crtc_disable(crtc);
4817
4818         intel_crtc_update_sarea(crtc, enable);
4819 }
4820
4821 static void intel_crtc_disable(struct drm_crtc *crtc)
4822 {
4823         struct drm_device *dev = crtc->dev;
4824         struct drm_connector *connector;
4825         struct drm_i915_private *dev_priv = dev->dev_private;
4826
4827         /* crtc should still be enabled when we disable it. */
4828         WARN_ON(!crtc->enabled);
4829
4830         dev_priv->display.crtc_disable(crtc);
4831         intel_crtc_update_sarea(crtc, false);
4832         dev_priv->display.off(crtc);
4833
4834         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4835         assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4836         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4837
4838         if (crtc->primary->fb) {
4839                 mutex_lock(&dev->struct_mutex);
4840                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->primary->fb)->obj);
4841                 mutex_unlock(&dev->struct_mutex);
4842                 crtc->primary->fb = NULL;
4843         }
4844
4845         /* Update computed state. */
4846         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4847                 if (!connector->encoder || !connector->encoder->crtc)
4848                         continue;
4849
4850                 if (connector->encoder->crtc != crtc)
4851                         continue;
4852
4853                 connector->dpms = DRM_MODE_DPMS_OFF;
4854                 to_intel_encoder(connector->encoder)->connectors_active = false;
4855         }
4856 }
4857
4858 void intel_encoder_destroy(struct drm_encoder *encoder)
4859 {
4860         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4861
4862         drm_encoder_cleanup(encoder);
4863         kfree(intel_encoder);
4864 }
4865
4866 /* Simple dpms helper for encoders with just one connector, no cloning and only
4867  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4868  * state of the entire output pipe. */
4869 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4870 {
4871         if (mode == DRM_MODE_DPMS_ON) {
4872                 encoder->connectors_active = true;
4873
4874                 intel_crtc_update_dpms(encoder->base.crtc);
4875         } else {
4876                 encoder->connectors_active = false;
4877
4878                 intel_crtc_update_dpms(encoder->base.crtc);
4879         }
4880 }
4881
4882 /* Cross check the actual hw state with our own modeset state tracking (and it's
4883  * internal consistency). */
4884 static void intel_connector_check_state(struct intel_connector *connector)
4885 {
4886         if (connector->get_hw_state(connector)) {
4887                 struct intel_encoder *encoder = connector->encoder;
4888                 struct drm_crtc *crtc;
4889                 bool encoder_enabled;
4890                 enum pipe pipe;
4891
4892                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4893                               connector->base.base.id,
4894                               drm_get_connector_name(&connector->base));
4895
4896                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4897                      "wrong connector dpms state\n");
4898                 WARN(connector->base.encoder != &encoder->base,
4899                      "active connector not linked to encoder\n");
4900                 WARN(!encoder->connectors_active,
4901                      "encoder->connectors_active not set\n");
4902
4903                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4904                 WARN(!encoder_enabled, "encoder not enabled\n");
4905                 if (WARN_ON(!encoder->base.crtc))
4906                         return;
4907
4908                 crtc = encoder->base.crtc;
4909
4910                 WARN(!crtc->enabled, "crtc not enabled\n");
4911                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4912                 WARN(pipe != to_intel_crtc(crtc)->pipe,
4913                      "encoder active on the wrong pipe\n");
4914         }
4915 }
4916
4917 /* Even simpler default implementation, if there's really no special case to
4918  * consider. */
4919 void intel_connector_dpms(struct drm_connector *connector, int mode)
4920 {
4921         /* All the simple cases only support two dpms states. */
4922         if (mode != DRM_MODE_DPMS_ON)
4923                 mode = DRM_MODE_DPMS_OFF;
4924
4925         if (mode == connector->dpms)
4926                 return;
4927
4928         connector->dpms = mode;
4929
4930         /* Only need to change hw state when actually enabled */
4931         if (connector->encoder)
4932                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
4933
4934         intel_modeset_check_state(connector->dev);
4935 }
4936
4937 /* Simple connector->get_hw_state implementation for encoders that support only
4938  * one connector and no cloning and hence the encoder state determines the state
4939  * of the connector. */
4940 bool intel_connector_get_hw_state(struct intel_connector *connector)
4941 {
4942         enum pipe pipe = 0;
4943         struct intel_encoder *encoder = connector->encoder;
4944
4945         return encoder->get_hw_state(encoder, &pipe);
4946 }
4947
4948 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4949                                      struct intel_crtc_config *pipe_config)
4950 {
4951         struct drm_i915_private *dev_priv = dev->dev_private;
4952         struct intel_crtc *pipe_B_crtc =
4953                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4954
4955         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4956                       pipe_name(pipe), pipe_config->fdi_lanes);
4957         if (pipe_config->fdi_lanes > 4) {
4958                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4959                               pipe_name(pipe), pipe_config->fdi_lanes);
4960                 return false;
4961         }
4962
4963         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4964                 if (pipe_config->fdi_lanes > 2) {
4965                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4966                                       pipe_config->fdi_lanes);
4967                         return false;
4968                 } else {
4969                         return true;
4970                 }
4971         }
4972
4973         if (INTEL_INFO(dev)->num_pipes == 2)
4974                 return true;
4975
4976         /* Ivybridge 3 pipe is really complicated */
4977         switch (pipe) {
4978         case PIPE_A:
4979                 return true;
4980         case PIPE_B:
4981                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4982                     pipe_config->fdi_lanes > 2) {
4983                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4984                                       pipe_name(pipe), pipe_config->fdi_lanes);
4985                         return false;
4986                 }
4987                 return true;
4988         case PIPE_C:
4989                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4990                     pipe_B_crtc->config.fdi_lanes <= 2) {
4991                         if (pipe_config->fdi_lanes > 2) {
4992                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4993                                               pipe_name(pipe), pipe_config->fdi_lanes);
4994                                 return false;
4995                         }
4996                 } else {
4997                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4998                         return false;
4999                 }
5000                 return true;
5001         default:
5002                 BUG();
5003         }
5004 }
5005
5006 #define RETRY 1
5007 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5008                                        struct intel_crtc_config *pipe_config)
5009 {
5010         struct drm_device *dev = intel_crtc->base.dev;
5011         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5012         int lane, link_bw, fdi_dotclock;
5013         bool setup_ok, needs_recompute = false;
5014
5015 retry:
5016         /* FDI is a binary signal running at ~2.7GHz, encoding
5017          * each output octet as 10 bits. The actual frequency
5018          * is stored as a divider into a 100MHz clock, and the
5019          * mode pixel clock is stored in units of 1KHz.
5020          * Hence the bw of each lane in terms of the mode signal
5021          * is:
5022          */
5023         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5024
5025         fdi_dotclock = adjusted_mode->crtc_clock;
5026
5027         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5028                                            pipe_config->pipe_bpp);
5029
5030         pipe_config->fdi_lanes = lane;
5031
5032         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5033                                link_bw, &pipe_config->fdi_m_n);
5034
5035         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5036                                             intel_crtc->pipe, pipe_config);
5037         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5038                 pipe_config->pipe_bpp -= 2*3;
5039                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5040                               pipe_config->pipe_bpp);
5041                 needs_recompute = true;
5042                 pipe_config->bw_constrained = true;
5043
5044                 goto retry;
5045         }
5046
5047         if (needs_recompute)
5048                 return RETRY;
5049
5050         return setup_ok ? 0 : -EINVAL;
5051 }
5052
5053 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5054                                    struct intel_crtc_config *pipe_config)
5055 {
5056         pipe_config->ips_enabled = i915.enable_ips &&
5057                                    hsw_crtc_supports_ips(crtc) &&
5058                                    pipe_config->pipe_bpp <= 24;
5059 }
5060
5061 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5062                                      struct intel_crtc_config *pipe_config)
5063 {
5064         struct drm_device *dev = crtc->base.dev;
5065         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5066
5067         /* FIXME should check pixel clock limits on all platforms */
5068         if (INTEL_INFO(dev)->gen < 4) {
5069                 struct drm_i915_private *dev_priv = dev->dev_private;
5070                 int clock_limit =
5071                         dev_priv->display.get_display_clock_speed(dev);
5072
5073                 /*
5074                  * Enable pixel doubling when the dot clock
5075                  * is > 90% of the (display) core speed.
5076                  *
5077                  * GDG double wide on either pipe,
5078                  * otherwise pipe A only.
5079                  */
5080                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5081                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5082                         clock_limit *= 2;
5083                         pipe_config->double_wide = true;
5084                 }
5085
5086                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5087                         return -EINVAL;
5088         }
5089
5090         /*
5091          * Pipe horizontal size must be even in:
5092          * - DVO ganged mode
5093          * - LVDS dual channel mode
5094          * - Double wide pipe
5095          */
5096         if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5097              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5098                 pipe_config->pipe_src_w &= ~1;
5099
5100         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5101          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5102          */
5103         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5104                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5105                 return -EINVAL;
5106
5107         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5108                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5109         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5110                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5111                  * for lvds. */
5112                 pipe_config->pipe_bpp = 8*3;
5113         }
5114
5115         if (HAS_IPS(dev))
5116                 hsw_compute_ips_config(crtc, pipe_config);
5117
5118         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
5119          * clock survives for now. */
5120         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5121                 pipe_config->shared_dpll = crtc->config.shared_dpll;
5122
5123         if (pipe_config->has_pch_encoder)
5124                 return ironlake_fdi_compute_config(crtc, pipe_config);
5125
5126         return 0;
5127 }
5128
5129 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5130 {
5131         return 400000; /* FIXME */
5132 }
5133
5134 static int i945_get_display_clock_speed(struct drm_device *dev)
5135 {
5136         return 400000;
5137 }
5138
5139 static int i915_get_display_clock_speed(struct drm_device *dev)
5140 {
5141         return 333000;
5142 }
5143
5144 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5145 {
5146         return 200000;
5147 }
5148
5149 static int pnv_get_display_clock_speed(struct drm_device *dev)
5150 {
5151         u16 gcfgc = 0;
5152
5153         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5154
5155         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5156         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5157                 return 267000;
5158         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5159                 return 333000;
5160         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5161                 return 444000;
5162         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5163                 return 200000;
5164         default:
5165                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5166         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5167                 return 133000;
5168         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5169                 return 167000;
5170         }
5171 }
5172
5173 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5174 {
5175         u16 gcfgc = 0;
5176
5177         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5178
5179         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5180                 return 133000;
5181         else {
5182                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5183                 case GC_DISPLAY_CLOCK_333_MHZ:
5184                         return 333000;
5185                 default:
5186                 case GC_DISPLAY_CLOCK_190_200_MHZ:
5187                         return 190000;
5188                 }
5189         }
5190 }
5191
5192 static int i865_get_display_clock_speed(struct drm_device *dev)
5193 {
5194         return 266000;
5195 }
5196
5197 static int i855_get_display_clock_speed(struct drm_device *dev)
5198 {
5199         u16 hpllcc = 0;
5200         /* Assume that the hardware is in the high speed state.  This
5201          * should be the default.
5202          */
5203         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5204         case GC_CLOCK_133_200:
5205         case GC_CLOCK_100_200:
5206                 return 200000;
5207         case GC_CLOCK_166_250:
5208                 return 250000;
5209         case GC_CLOCK_100_133:
5210                 return 133000;
5211         }
5212
5213         /* Shouldn't happen */
5214         return 0;
5215 }
5216
5217 static int i830_get_display_clock_speed(struct drm_device *dev)
5218 {
5219         return 133000;
5220 }
5221
5222 static void
5223 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5224 {
5225         while (*num > DATA_LINK_M_N_MASK ||
5226                *den > DATA_LINK_M_N_MASK) {
5227                 *num >>= 1;
5228                 *den >>= 1;
5229         }
5230 }
5231
5232 static void compute_m_n(unsigned int m, unsigned int n,
5233                         uint32_t *ret_m, uint32_t *ret_n)
5234 {
5235         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5236         *ret_m = div_u64((uint64_t) m * *ret_n, n);
5237         intel_reduce_m_n_ratio(ret_m, ret_n);
5238 }
5239
5240 void
5241 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5242                        int pixel_clock, int link_clock,
5243                        struct intel_link_m_n *m_n)
5244 {
5245         m_n->tu = 64;
5246
5247         compute_m_n(bits_per_pixel * pixel_clock,
5248                     link_clock * nlanes * 8,
5249                     &m_n->gmch_m, &m_n->gmch_n);
5250
5251         compute_m_n(pixel_clock, link_clock,
5252                     &m_n->link_m, &m_n->link_n);
5253 }
5254
5255 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5256 {
5257         if (i915.panel_use_ssc >= 0)
5258                 return i915.panel_use_ssc != 0;
5259         return dev_priv->vbt.lvds_use_ssc
5260                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5261 }
5262
5263 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5264 {
5265         struct drm_device *dev = crtc->dev;
5266         struct drm_i915_private *dev_priv = dev->dev_private;
5267         int refclk;
5268
5269         if (IS_VALLEYVIEW(dev)) {
5270                 refclk = 100000;
5271         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5272             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5273                 refclk = dev_priv->vbt.lvds_ssc_freq;
5274                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5275         } else if (!IS_GEN2(dev)) {
5276                 refclk = 96000;
5277         } else {
5278                 refclk = 48000;
5279         }
5280
5281         return refclk;
5282 }
5283
5284 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5285 {
5286         return (1 << dpll->n) << 16 | dpll->m2;
5287 }
5288
5289 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5290 {
5291         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5292 }
5293
5294 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5295                                      intel_clock_t *reduced_clock)
5296 {
5297         struct drm_device *dev = crtc->base.dev;
5298         u32 fp, fp2 = 0;
5299
5300         if (IS_PINEVIEW(dev)) {
5301                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5302                 if (reduced_clock)
5303                         fp2 = pnv_dpll_compute_fp(reduced_clock);
5304         } else {
5305                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5306                 if (reduced_clock)
5307                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
5308         }
5309
5310         crtc->config.dpll_hw_state.fp0 = fp;
5311
5312         crtc->lowfreq_avail = false;
5313         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5314             reduced_clock && i915.powersave) {
5315                 crtc->config.dpll_hw_state.fp1 = fp2;
5316                 crtc->lowfreq_avail = true;
5317         } else {
5318                 crtc->config.dpll_hw_state.fp1 = fp;
5319         }
5320 }
5321
5322 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5323                 pipe)
5324 {
5325         u32 reg_val;
5326
5327         /*
5328          * PLLB opamp always calibrates to max value of 0x3f, force enable it
5329          * and set it to a reasonable value instead.
5330          */
5331         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5332         reg_val &= 0xffffff00;
5333         reg_val |= 0x00000030;
5334         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5335
5336         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5337         reg_val &= 0x8cffffff;
5338         reg_val = 0x8c000000;
5339         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5340
5341         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5342         reg_val &= 0xffffff00;
5343         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5344
5345         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5346         reg_val &= 0x00ffffff;
5347         reg_val |= 0xb0000000;
5348         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5349 }
5350
5351 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5352                                          struct intel_link_m_n *m_n)
5353 {
5354         struct drm_device *dev = crtc->base.dev;
5355         struct drm_i915_private *dev_priv = dev->dev_private;
5356         int pipe = crtc->pipe;
5357
5358         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5359         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5360         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5361         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5362 }
5363
5364 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5365                                          struct intel_link_m_n *m_n)
5366 {
5367         struct drm_device *dev = crtc->base.dev;
5368         struct drm_i915_private *dev_priv = dev->dev_private;
5369         int pipe = crtc->pipe;
5370         enum transcoder transcoder = crtc->config.cpu_transcoder;
5371
5372         if (INTEL_INFO(dev)->gen >= 5) {
5373                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5374                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5375                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5376                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5377         } else {
5378                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5379                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5380                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5381                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5382         }
5383 }
5384
5385 static void intel_dp_set_m_n(struct intel_crtc *crtc)
5386 {
5387         if (crtc->config.has_pch_encoder)
5388                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5389         else
5390                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5391 }
5392
5393 static void vlv_update_pll(struct intel_crtc *crtc)
5394 {
5395         u32 dpll, dpll_md;
5396
5397         /*
5398          * Enable DPIO clock input. We should never disable the reference
5399          * clock for pipe B, since VGA hotplug / manual detection depends
5400          * on it.
5401          */
5402         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5403                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5404         /* We should never disable this, set it here for state tracking */
5405         if (crtc->pipe == PIPE_B)
5406                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5407         dpll |= DPLL_VCO_ENABLE;
5408         crtc->config.dpll_hw_state.dpll = dpll;
5409
5410         dpll_md = (crtc->config.pixel_multiplier - 1)
5411                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5412         crtc->config.dpll_hw_state.dpll_md = dpll_md;
5413 }
5414
5415 static void vlv_prepare_pll(struct intel_crtc *crtc)
5416 {
5417         struct drm_device *dev = crtc->base.dev;
5418         struct drm_i915_private *dev_priv = dev->dev_private;
5419         int pipe = crtc->pipe;
5420         u32 mdiv;
5421         u32 bestn, bestm1, bestm2, bestp1, bestp2;
5422         u32 coreclk, reg_val;
5423
5424         mutex_lock(&dev_priv->dpio_lock);
5425
5426         bestn = crtc->config.dpll.n;
5427         bestm1 = crtc->config.dpll.m1;
5428         bestm2 = crtc->config.dpll.m2;
5429         bestp1 = crtc->config.dpll.p1;
5430         bestp2 = crtc->config.dpll.p2;
5431
5432         /* See eDP HDMI DPIO driver vbios notes doc */
5433
5434         /* PLL B needs special handling */
5435         if (pipe == PIPE_B)
5436                 vlv_pllb_recal_opamp(dev_priv, pipe);
5437
5438         /* Set up Tx target for periodic Rcomp update */
5439         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5440
5441         /* Disable target IRef on PLL */
5442         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5443         reg_val &= 0x00ffffff;
5444         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5445
5446         /* Disable fast lock */
5447         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5448
5449         /* Set idtafcrecal before PLL is enabled */
5450         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5451         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5452         mdiv |= ((bestn << DPIO_N_SHIFT));
5453         mdiv |= (1 << DPIO_K_SHIFT);
5454
5455         /*
5456          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5457          * but we don't support that).
5458          * Note: don't use the DAC post divider as it seems unstable.
5459          */
5460         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5461         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5462
5463         mdiv |= DPIO_ENABLE_CALIBRATION;
5464         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5465
5466         /* Set HBR and RBR LPF coefficients */
5467         if (crtc->config.port_clock == 162000 ||
5468             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5469             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5470                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5471                                  0x009f0003);
5472         else
5473                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5474                                  0x00d0000f);
5475
5476         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5477             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5478                 /* Use SSC source */
5479                 if (pipe == PIPE_A)
5480                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5481                                          0x0df40000);
5482                 else
5483                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5484                                          0x0df70000);
5485         } else { /* HDMI or VGA */
5486                 /* Use bend source */
5487                 if (pipe == PIPE_A)
5488                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5489                                          0x0df70000);
5490                 else
5491                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5492                                          0x0df40000);
5493         }
5494
5495         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5496         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5497         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5498             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5499                 coreclk |= 0x01000000;
5500         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5501
5502         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5503         mutex_unlock(&dev_priv->dpio_lock);
5504 }
5505
5506 static void chv_update_pll(struct intel_crtc *crtc)
5507 {
5508         struct drm_device *dev = crtc->base.dev;
5509         struct drm_i915_private *dev_priv = dev->dev_private;
5510         int pipe = crtc->pipe;
5511         int dpll_reg = DPLL(crtc->pipe);
5512         enum dpio_channel port = vlv_pipe_to_channel(pipe);
5513         u32 val, loopfilter, intcoeff;
5514         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5515         int refclk;
5516
5517         crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5518                 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5519                 DPLL_VCO_ENABLE;
5520         if (pipe != PIPE_A)
5521                 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5522
5523         crtc->config.dpll_hw_state.dpll_md =
5524                 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5525
5526         bestn = crtc->config.dpll.n;
5527         bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5528         bestm1 = crtc->config.dpll.m1;
5529         bestm2 = crtc->config.dpll.m2 >> 22;
5530         bestp1 = crtc->config.dpll.p1;
5531         bestp2 = crtc->config.dpll.p2;
5532
5533         /*
5534          * Enable Refclk and SSC
5535          */
5536         I915_WRITE(dpll_reg,
5537                    crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5538
5539         mutex_lock(&dev_priv->dpio_lock);
5540
5541         /* Propagate soft reset to data lane reset */
5542         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(port));
5543         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
5544         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), val);
5545
5546         /* Disable 10bit clock to display controller */
5547         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
5548         val &= ~DPIO_DCLKP_EN;
5549         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
5550
5551         /* p1 and p2 divider */
5552         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5553                         5 << DPIO_CHV_S1_DIV_SHIFT |
5554                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5555                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5556                         1 << DPIO_CHV_K_DIV_SHIFT);
5557
5558         /* Feedback post-divider - m2 */
5559         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5560
5561         /* Feedback refclk divider - n and m1 */
5562         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5563                         DPIO_CHV_M1_DIV_BY_2 |
5564                         1 << DPIO_CHV_N_DIV_SHIFT);
5565
5566         /* M2 fraction division */
5567         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5568
5569         /* M2 fraction division enable */
5570         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5571                        DPIO_CHV_FRAC_DIV_EN |
5572                        (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5573
5574         /* Loop filter */
5575         refclk = i9xx_get_refclk(&crtc->base, 0);
5576         loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5577                 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5578         if (refclk == 100000)
5579                 intcoeff = 11;
5580         else if (refclk == 38400)
5581                 intcoeff = 10;
5582         else
5583                 intcoeff = 9;
5584         loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5585         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5586
5587         /* AFC Recal */
5588         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5589                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5590                         DPIO_AFC_RECAL);
5591
5592         mutex_unlock(&dev_priv->dpio_lock);
5593 }
5594
5595 static void i9xx_update_pll(struct intel_crtc *crtc,
5596                             intel_clock_t *reduced_clock,
5597                             int num_connectors)
5598 {
5599         struct drm_device *dev = crtc->base.dev;
5600         struct drm_i915_private *dev_priv = dev->dev_private;
5601         u32 dpll;
5602         bool is_sdvo;
5603         struct dpll *clock = &crtc->config.dpll;
5604
5605         i9xx_update_pll_dividers(crtc, reduced_clock);
5606
5607         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5608                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5609
5610         dpll = DPLL_VGA_MODE_DIS;
5611
5612         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5613                 dpll |= DPLLB_MODE_LVDS;
5614         else
5615                 dpll |= DPLLB_MODE_DAC_SERIAL;
5616
5617         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5618                 dpll |= (crtc->config.pixel_multiplier - 1)
5619                         << SDVO_MULTIPLIER_SHIFT_HIRES;
5620         }
5621
5622         if (is_sdvo)
5623                 dpll |= DPLL_SDVO_HIGH_SPEED;
5624
5625         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5626                 dpll |= DPLL_SDVO_HIGH_SPEED;
5627
5628         /* compute bitmask from p1 value */
5629         if (IS_PINEVIEW(dev))
5630                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5631         else {
5632                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5633                 if (IS_G4X(dev) && reduced_clock)
5634                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5635         }
5636         switch (clock->p2) {
5637         case 5:
5638                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5639                 break;
5640         case 7:
5641                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5642                 break;
5643         case 10:
5644                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5645                 break;
5646         case 14:
5647                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5648                 break;
5649         }
5650         if (INTEL_INFO(dev)->gen >= 4)
5651                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5652
5653         if (crtc->config.sdvo_tv_clock)
5654                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5655         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5656                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5657                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5658         else
5659                 dpll |= PLL_REF_INPUT_DREFCLK;
5660
5661         dpll |= DPLL_VCO_ENABLE;
5662         crtc->config.dpll_hw_state.dpll = dpll;
5663
5664         if (INTEL_INFO(dev)->gen >= 4) {
5665                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5666                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5667                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5668         }
5669 }
5670
5671 static void i8xx_update_pll(struct intel_crtc *crtc,
5672                             intel_clock_t *reduced_clock,
5673                             int num_connectors)
5674 {
5675         struct drm_device *dev = crtc->base.dev;
5676         struct drm_i915_private *dev_priv = dev->dev_private;
5677         u32 dpll;
5678         struct dpll *clock = &crtc->config.dpll;
5679
5680         i9xx_update_pll_dividers(crtc, reduced_clock);
5681
5682         dpll = DPLL_VGA_MODE_DIS;
5683
5684         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5685                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5686         } else {
5687                 if (clock->p1 == 2)
5688                         dpll |= PLL_P1_DIVIDE_BY_TWO;
5689                 else
5690                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5691                 if (clock->p2 == 4)
5692                         dpll |= PLL_P2_DIVIDE_BY_4;
5693         }
5694
5695         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5696                 dpll |= DPLL_DVO_2X_MODE;
5697
5698         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5699                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5700                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5701         else
5702                 dpll |= PLL_REF_INPUT_DREFCLK;
5703
5704         dpll |= DPLL_VCO_ENABLE;
5705         crtc->config.dpll_hw_state.dpll = dpll;
5706 }
5707
5708 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5709 {
5710         struct drm_device *dev = intel_crtc->base.dev;
5711         struct drm_i915_private *dev_priv = dev->dev_private;
5712         enum pipe pipe = intel_crtc->pipe;
5713         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5714         struct drm_display_mode *adjusted_mode =
5715                 &intel_crtc->config.adjusted_mode;
5716         uint32_t crtc_vtotal, crtc_vblank_end;
5717         int vsyncshift = 0;
5718
5719         /* We need to be careful not to changed the adjusted mode, for otherwise
5720          * the hw state checker will get angry at the mismatch. */
5721         crtc_vtotal = adjusted_mode->crtc_vtotal;
5722         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5723
5724         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5725                 /* the chip adds 2 halflines automatically */
5726                 crtc_vtotal -= 1;
5727                 crtc_vblank_end -= 1;
5728
5729                 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5730                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5731                 else
5732                         vsyncshift = adjusted_mode->crtc_hsync_start -
5733                                 adjusted_mode->crtc_htotal / 2;
5734                 if (vsyncshift < 0)
5735                         vsyncshift += adjusted_mode->crtc_htotal;
5736         }
5737
5738         if (INTEL_INFO(dev)->gen > 3)
5739                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5740
5741         I915_WRITE(HTOTAL(cpu_transcoder),
5742                    (adjusted_mode->crtc_hdisplay - 1) |
5743                    ((adjusted_mode->crtc_htotal - 1) << 16));
5744         I915_WRITE(HBLANK(cpu_transcoder),
5745                    (adjusted_mode->crtc_hblank_start - 1) |
5746                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5747         I915_WRITE(HSYNC(cpu_transcoder),
5748                    (adjusted_mode->crtc_hsync_start - 1) |
5749                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5750
5751         I915_WRITE(VTOTAL(cpu_transcoder),
5752                    (adjusted_mode->crtc_vdisplay - 1) |
5753                    ((crtc_vtotal - 1) << 16));
5754         I915_WRITE(VBLANK(cpu_transcoder),
5755                    (adjusted_mode->crtc_vblank_start - 1) |
5756                    ((crtc_vblank_end - 1) << 16));
5757         I915_WRITE(VSYNC(cpu_transcoder),
5758                    (adjusted_mode->crtc_vsync_start - 1) |
5759                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5760
5761         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5762          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5763          * documented on the DDI_FUNC_CTL register description, EDP Input Select
5764          * bits. */
5765         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5766             (pipe == PIPE_B || pipe == PIPE_C))
5767                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5768
5769         /* pipesrc controls the size that is scaled from, which should
5770          * always be the user's requested size.
5771          */
5772         I915_WRITE(PIPESRC(pipe),
5773                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
5774                    (intel_crtc->config.pipe_src_h - 1));
5775 }
5776
5777 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5778                                    struct intel_crtc_config *pipe_config)
5779 {
5780         struct drm_device *dev = crtc->base.dev;
5781         struct drm_i915_private *dev_priv = dev->dev_private;
5782         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5783         uint32_t tmp;
5784
5785         tmp = I915_READ(HTOTAL(cpu_transcoder));
5786         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5787         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5788         tmp = I915_READ(HBLANK(cpu_transcoder));
5789         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5790         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5791         tmp = I915_READ(HSYNC(cpu_transcoder));
5792         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5793         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5794
5795         tmp = I915_READ(VTOTAL(cpu_transcoder));
5796         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5797         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5798         tmp = I915_READ(VBLANK(cpu_transcoder));
5799         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5800         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5801         tmp = I915_READ(VSYNC(cpu_transcoder));
5802         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5803         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5804
5805         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5806                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5807                 pipe_config->adjusted_mode.crtc_vtotal += 1;
5808                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5809         }
5810
5811         tmp = I915_READ(PIPESRC(crtc->pipe));
5812         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5813         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5814
5815         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5816         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5817 }
5818
5819 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5820                                  struct intel_crtc_config *pipe_config)
5821 {
5822         mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5823         mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5824         mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5825         mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5826
5827         mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5828         mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5829         mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5830         mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5831
5832         mode->flags = pipe_config->adjusted_mode.flags;
5833
5834         mode->clock = pipe_config->adjusted_mode.crtc_clock;
5835         mode->flags |= pipe_config->adjusted_mode.flags;
5836 }
5837
5838 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5839 {
5840         struct drm_device *dev = intel_crtc->base.dev;
5841         struct drm_i915_private *dev_priv = dev->dev_private;
5842         uint32_t pipeconf;
5843
5844         pipeconf = 0;
5845
5846         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5847             I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5848                 pipeconf |= PIPECONF_ENABLE;
5849
5850         if (intel_crtc->config.double_wide)
5851                 pipeconf |= PIPECONF_DOUBLE_WIDE;
5852
5853         /* only g4x and later have fancy bpc/dither controls */
5854         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5855                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5856                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5857                         pipeconf |= PIPECONF_DITHER_EN |
5858                                     PIPECONF_DITHER_TYPE_SP;
5859
5860                 switch (intel_crtc->config.pipe_bpp) {
5861                 case 18:
5862                         pipeconf |= PIPECONF_6BPC;
5863                         break;
5864                 case 24:
5865                         pipeconf |= PIPECONF_8BPC;
5866                         break;
5867                 case 30:
5868                         pipeconf |= PIPECONF_10BPC;
5869                         break;
5870                 default:
5871                         /* Case prevented by intel_choose_pipe_bpp_dither. */
5872                         BUG();
5873                 }
5874         }
5875
5876         if (HAS_PIPE_CXSR(dev)) {
5877                 if (intel_crtc->lowfreq_avail) {
5878                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5879                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5880                 } else {
5881                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5882                 }
5883         }
5884
5885         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
5886                 if (INTEL_INFO(dev)->gen < 4 ||
5887                     intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5888                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5889                 else
5890                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
5891         } else
5892                 pipeconf |= PIPECONF_PROGRESSIVE;
5893
5894         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5895                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5896
5897         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5898         POSTING_READ(PIPECONF(intel_crtc->pipe));
5899 }
5900
5901 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5902                               int x, int y,
5903                               struct drm_framebuffer *fb)
5904 {
5905         struct drm_device *dev = crtc->dev;
5906         struct drm_i915_private *dev_priv = dev->dev_private;
5907         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5908         int refclk, num_connectors = 0;
5909         intel_clock_t clock, reduced_clock;
5910         bool ok, has_reduced_clock = false;
5911         bool is_lvds = false, is_dsi = false;
5912         struct intel_encoder *encoder;
5913         const intel_limit_t *limit;
5914
5915         for_each_encoder_on_crtc(dev, crtc, encoder) {
5916                 switch (encoder->type) {
5917                 case INTEL_OUTPUT_LVDS:
5918                         is_lvds = true;
5919                         break;
5920                 case INTEL_OUTPUT_DSI:
5921                         is_dsi = true;
5922                         break;
5923                 }
5924
5925                 num_connectors++;
5926         }
5927
5928         if (is_dsi)
5929                 return 0;
5930
5931         if (!intel_crtc->config.clock_set) {
5932                 refclk = i9xx_get_refclk(crtc, num_connectors);
5933
5934                 /*
5935                  * Returns a set of divisors for the desired target clock with
5936                  * the given refclk, or FALSE.  The returned values represent
5937                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5938                  * 2) / p1 / p2.
5939                  */
5940                 limit = intel_limit(crtc, refclk);
5941                 ok = dev_priv->display.find_dpll(limit, crtc,
5942                                                  intel_crtc->config.port_clock,
5943                                                  refclk, NULL, &clock);
5944                 if (!ok) {
5945                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5946                         return -EINVAL;
5947                 }
5948
5949                 if (is_lvds && dev_priv->lvds_downclock_avail) {
5950                         /*
5951                          * Ensure we match the reduced clock's P to the target
5952                          * clock.  If the clocks don't match, we can't switch
5953                          * the display clock by using the FP0/FP1. In such case
5954                          * we will disable the LVDS downclock feature.
5955                          */
5956                         has_reduced_clock =
5957                                 dev_priv->display.find_dpll(limit, crtc,
5958                                                             dev_priv->lvds_downclock,
5959                                                             refclk, &clock,
5960                                                             &reduced_clock);
5961                 }
5962                 /* Compat-code for transition, will disappear. */
5963                 intel_crtc->config.dpll.n = clock.n;
5964                 intel_crtc->config.dpll.m1 = clock.m1;
5965                 intel_crtc->config.dpll.m2 = clock.m2;
5966                 intel_crtc->config.dpll.p1 = clock.p1;
5967                 intel_crtc->config.dpll.p2 = clock.p2;
5968         }
5969
5970         if (IS_GEN2(dev)) {
5971                 i8xx_update_pll(intel_crtc,
5972                                 has_reduced_clock ? &reduced_clock : NULL,
5973                                 num_connectors);
5974         } else if (IS_CHERRYVIEW(dev)) {
5975                 chv_update_pll(intel_crtc);
5976         } else if (IS_VALLEYVIEW(dev)) {
5977                 vlv_update_pll(intel_crtc);
5978         } else {
5979                 i9xx_update_pll(intel_crtc,
5980                                 has_reduced_clock ? &reduced_clock : NULL,
5981                                 num_connectors);
5982         }
5983
5984         return 0;
5985 }
5986
5987 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5988                                  struct intel_crtc_config *pipe_config)
5989 {
5990         struct drm_device *dev = crtc->base.dev;
5991         struct drm_i915_private *dev_priv = dev->dev_private;
5992         uint32_t tmp;
5993
5994         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
5995                 return;
5996
5997         tmp = I915_READ(PFIT_CONTROL);
5998         if (!(tmp & PFIT_ENABLE))
5999                 return;
6000
6001         /* Check whether the pfit is attached to our pipe. */
6002         if (INTEL_INFO(dev)->gen < 4) {
6003                 if (crtc->pipe != PIPE_B)
6004                         return;
6005         } else {
6006                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6007                         return;
6008         }
6009
6010         pipe_config->gmch_pfit.control = tmp;
6011         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6012         if (INTEL_INFO(dev)->gen < 5)
6013                 pipe_config->gmch_pfit.lvds_border_bits =
6014                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6015 }
6016
6017 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6018                                struct intel_crtc_config *pipe_config)
6019 {
6020         struct drm_device *dev = crtc->base.dev;
6021         struct drm_i915_private *dev_priv = dev->dev_private;
6022         int pipe = pipe_config->cpu_transcoder;
6023         intel_clock_t clock;
6024         u32 mdiv;
6025         int refclk = 100000;
6026
6027         mutex_lock(&dev_priv->dpio_lock);
6028         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6029         mutex_unlock(&dev_priv->dpio_lock);
6030
6031         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6032         clock.m2 = mdiv & DPIO_M2DIV_MASK;
6033         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6034         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6035         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6036
6037         vlv_clock(refclk, &clock);
6038
6039         /* clock.dot is the fast clock */
6040         pipe_config->port_clock = clock.dot / 5;
6041 }
6042
6043 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6044                                   struct intel_plane_config *plane_config)
6045 {
6046         struct drm_device *dev = crtc->base.dev;
6047         struct drm_i915_private *dev_priv = dev->dev_private;
6048         u32 val, base, offset;
6049         int pipe = crtc->pipe, plane = crtc->plane;
6050         int fourcc, pixel_format;
6051         int aligned_height;
6052
6053         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6054         if (!crtc->base.primary->fb) {
6055                 DRM_DEBUG_KMS("failed to alloc fb\n");
6056                 return;
6057         }
6058
6059         val = I915_READ(DSPCNTR(plane));
6060
6061         if (INTEL_INFO(dev)->gen >= 4)
6062                 if (val & DISPPLANE_TILED)
6063                         plane_config->tiled = true;
6064
6065         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6066         fourcc = intel_format_to_fourcc(pixel_format);
6067         crtc->base.primary->fb->pixel_format = fourcc;
6068         crtc->base.primary->fb->bits_per_pixel =
6069                 drm_format_plane_cpp(fourcc, 0) * 8;
6070
6071         if (INTEL_INFO(dev)->gen >= 4) {
6072                 if (plane_config->tiled)
6073                         offset = I915_READ(DSPTILEOFF(plane));
6074                 else
6075                         offset = I915_READ(DSPLINOFF(plane));
6076                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6077         } else {
6078                 base = I915_READ(DSPADDR(plane));
6079         }
6080         plane_config->base = base;
6081
6082         val = I915_READ(PIPESRC(pipe));
6083         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6084         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6085
6086         val = I915_READ(DSPSTRIDE(pipe));
6087         crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
6088
6089         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6090                                             plane_config->tiled);
6091
6092         plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
6093                                    aligned_height, PAGE_SIZE);
6094
6095         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6096                       pipe, plane, crtc->base.primary->fb->width,
6097                       crtc->base.primary->fb->height,
6098                       crtc->base.primary->fb->bits_per_pixel, base,
6099                       crtc->base.primary->fb->pitches[0],
6100                       plane_config->size);
6101
6102 }
6103
6104 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6105                                struct intel_crtc_config *pipe_config)
6106 {
6107         struct drm_device *dev = crtc->base.dev;
6108         struct drm_i915_private *dev_priv = dev->dev_private;
6109         int pipe = pipe_config->cpu_transcoder;
6110         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6111         intel_clock_t clock;
6112         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6113         int refclk = 100000;
6114
6115         mutex_lock(&dev_priv->dpio_lock);
6116         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6117         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6118         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6119         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6120         mutex_unlock(&dev_priv->dpio_lock);
6121
6122         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6123         clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6124         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6125         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6126         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6127
6128         chv_clock(refclk, &clock);
6129
6130         /* clock.dot is the fast clock */
6131         pipe_config->port_clock = clock.dot / 5;
6132 }
6133
6134 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6135                                  struct intel_crtc_config *pipe_config)
6136 {
6137         struct drm_device *dev = crtc->base.dev;
6138         struct drm_i915_private *dev_priv = dev->dev_private;
6139         uint32_t tmp;
6140
6141         if (!intel_display_power_enabled(dev_priv,
6142                                          POWER_DOMAIN_PIPE(crtc->pipe)))
6143                 return false;
6144
6145         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6146         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6147
6148         tmp = I915_READ(PIPECONF(crtc->pipe));
6149         if (!(tmp & PIPECONF_ENABLE))
6150                 return false;
6151
6152         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6153                 switch (tmp & PIPECONF_BPC_MASK) {
6154                 case PIPECONF_6BPC:
6155                         pipe_config->pipe_bpp = 18;
6156                         break;
6157                 case PIPECONF_8BPC:
6158                         pipe_config->pipe_bpp = 24;
6159                         break;
6160                 case PIPECONF_10BPC:
6161                         pipe_config->pipe_bpp = 30;
6162                         break;
6163                 default:
6164                         break;
6165                 }
6166         }
6167
6168         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6169                 pipe_config->limited_color_range = true;
6170
6171         if (INTEL_INFO(dev)->gen < 4)
6172                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6173
6174         intel_get_pipe_timings(crtc, pipe_config);
6175
6176         i9xx_get_pfit_config(crtc, pipe_config);
6177
6178         if (INTEL_INFO(dev)->gen >= 4) {
6179                 tmp = I915_READ(DPLL_MD(crtc->pipe));
6180                 pipe_config->pixel_multiplier =
6181                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6182                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6183                 pipe_config->dpll_hw_state.dpll_md = tmp;
6184         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6185                 tmp = I915_READ(DPLL(crtc->pipe));
6186                 pipe_config->pixel_multiplier =
6187                         ((tmp & SDVO_MULTIPLIER_MASK)
6188                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6189         } else {
6190                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6191                  * port and will be fixed up in the encoder->get_config
6192                  * function. */
6193                 pipe_config->pixel_multiplier = 1;
6194         }
6195         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6196         if (!IS_VALLEYVIEW(dev)) {
6197                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6198                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6199         } else {
6200                 /* Mask out read-only status bits. */
6201                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6202                                                      DPLL_PORTC_READY_MASK |
6203                                                      DPLL_PORTB_READY_MASK);
6204         }
6205
6206         if (IS_CHERRYVIEW(dev))
6207                 chv_crtc_clock_get(crtc, pipe_config);
6208         else if (IS_VALLEYVIEW(dev))
6209                 vlv_crtc_clock_get(crtc, pipe_config);
6210         else
6211                 i9xx_crtc_clock_get(crtc, pipe_config);
6212
6213         return true;
6214 }
6215
6216 static void ironlake_init_pch_refclk(struct drm_device *dev)
6217 {
6218         struct drm_i915_private *dev_priv = dev->dev_private;
6219         struct drm_mode_config *mode_config = &dev->mode_config;
6220         struct intel_encoder *encoder;
6221         u32 val, final;
6222         bool has_lvds = false;
6223         bool has_cpu_edp = false;
6224         bool has_panel = false;
6225         bool has_ck505 = false;
6226         bool can_ssc = false;
6227
6228         /* We need to take the global config into account */
6229         list_for_each_entry(encoder, &mode_config->encoder_list,
6230                             base.head) {
6231                 switch (encoder->type) {
6232                 case INTEL_OUTPUT_LVDS:
6233                         has_panel = true;
6234                         has_lvds = true;
6235                         break;
6236                 case INTEL_OUTPUT_EDP:
6237                         has_panel = true;
6238                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6239                                 has_cpu_edp = true;
6240                         break;
6241                 }
6242         }
6243
6244         if (HAS_PCH_IBX(dev)) {
6245                 has_ck505 = dev_priv->vbt.display_clock_mode;
6246                 can_ssc = has_ck505;
6247         } else {
6248                 has_ck505 = false;
6249                 can_ssc = true;
6250         }
6251
6252         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6253                       has_panel, has_lvds, has_ck505);
6254
6255         /* Ironlake: try to setup display ref clock before DPLL
6256          * enabling. This is only under driver's control after
6257          * PCH B stepping, previous chipset stepping should be
6258          * ignoring this setting.
6259          */
6260         val = I915_READ(PCH_DREF_CONTROL);
6261
6262         /* As we must carefully and slowly disable/enable each source in turn,
6263          * compute the final state we want first and check if we need to
6264          * make any changes at all.
6265          */
6266         final = val;
6267         final &= ~DREF_NONSPREAD_SOURCE_MASK;
6268         if (has_ck505)
6269                 final |= DREF_NONSPREAD_CK505_ENABLE;
6270         else
6271                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6272
6273         final &= ~DREF_SSC_SOURCE_MASK;
6274         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6275         final &= ~DREF_SSC1_ENABLE;
6276
6277         if (has_panel) {
6278                 final |= DREF_SSC_SOURCE_ENABLE;
6279
6280                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6281                         final |= DREF_SSC1_ENABLE;
6282
6283                 if (has_cpu_edp) {
6284                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
6285                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6286                         else
6287                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6288                 } else
6289                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6290         } else {
6291                 final |= DREF_SSC_SOURCE_DISABLE;
6292                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6293         }
6294
6295         if (final == val)
6296                 return;
6297
6298         /* Always enable nonspread source */
6299         val &= ~DREF_NONSPREAD_SOURCE_MASK;
6300
6301         if (has_ck505)
6302                 val |= DREF_NONSPREAD_CK505_ENABLE;
6303         else
6304                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6305
6306         if (has_panel) {
6307                 val &= ~DREF_SSC_SOURCE_MASK;
6308                 val |= DREF_SSC_SOURCE_ENABLE;
6309
6310                 /* SSC must be turned on before enabling the CPU output  */
6311                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6312                         DRM_DEBUG_KMS("Using SSC on panel\n");
6313                         val |= DREF_SSC1_ENABLE;
6314                 } else
6315                         val &= ~DREF_SSC1_ENABLE;
6316
6317                 /* Get SSC going before enabling the outputs */
6318                 I915_WRITE(PCH_DREF_CONTROL, val);
6319                 POSTING_READ(PCH_DREF_CONTROL);
6320                 udelay(200);
6321
6322                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6323
6324                 /* Enable CPU source on CPU attached eDP */
6325                 if (has_cpu_edp) {
6326                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6327                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
6328                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6329                         } else
6330                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6331                 } else
6332                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6333
6334                 I915_WRITE(PCH_DREF_CONTROL, val);
6335                 POSTING_READ(PCH_DREF_CONTROL);
6336                 udelay(200);
6337         } else {
6338                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6339
6340                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6341
6342                 /* Turn off CPU output */
6343                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6344
6345                 I915_WRITE(PCH_DREF_CONTROL, val);
6346                 POSTING_READ(PCH_DREF_CONTROL);
6347                 udelay(200);
6348
6349                 /* Turn off the SSC source */
6350                 val &= ~DREF_SSC_SOURCE_MASK;
6351                 val |= DREF_SSC_SOURCE_DISABLE;
6352
6353                 /* Turn off SSC1 */
6354                 val &= ~DREF_SSC1_ENABLE;
6355
6356                 I915_WRITE(PCH_DREF_CONTROL, val);
6357                 POSTING_READ(PCH_DREF_CONTROL);
6358                 udelay(200);
6359         }
6360
6361         BUG_ON(val != final);
6362 }
6363
6364 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6365 {
6366         uint32_t tmp;
6367
6368         tmp = I915_READ(SOUTH_CHICKEN2);
6369         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6370         I915_WRITE(SOUTH_CHICKEN2, tmp);
6371
6372         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6373                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6374                 DRM_ERROR("FDI mPHY reset assert timeout\n");
6375
6376         tmp = I915_READ(SOUTH_CHICKEN2);
6377         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6378         I915_WRITE(SOUTH_CHICKEN2, tmp);
6379
6380         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6381                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6382                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6383 }
6384
6385 /* WaMPhyProgramming:hsw */
6386 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6387 {
6388         uint32_t tmp;
6389
6390         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6391         tmp &= ~(0xFF << 24);
6392         tmp |= (0x12 << 24);
6393         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6394
6395         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6396         tmp |= (1 << 11);
6397         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6398
6399         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6400         tmp |= (1 << 11);
6401         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6402
6403         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6404         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6405         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6406
6407         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6408         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6409         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6410
6411         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6412         tmp &= ~(7 << 13);
6413         tmp |= (5 << 13);
6414         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6415
6416         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6417         tmp &= ~(7 << 13);
6418         tmp |= (5 << 13);
6419         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6420
6421         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6422         tmp &= ~0xFF;
6423         tmp |= 0x1C;
6424         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6425
6426         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6427         tmp &= ~0xFF;
6428         tmp |= 0x1C;
6429         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6430
6431         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6432         tmp &= ~(0xFF << 16);
6433         tmp |= (0x1C << 16);
6434         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6435
6436         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6437         tmp &= ~(0xFF << 16);
6438         tmp |= (0x1C << 16);
6439         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6440
6441         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6442         tmp |= (1 << 27);
6443         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6444
6445         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6446         tmp |= (1 << 27);
6447         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6448
6449         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6450         tmp &= ~(0xF << 28);
6451         tmp |= (4 << 28);
6452         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6453
6454         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6455         tmp &= ~(0xF << 28);
6456         tmp |= (4 << 28);
6457         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6458 }
6459
6460 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6461  * Programming" based on the parameters passed:
6462  * - Sequence to enable CLKOUT_DP
6463  * - Sequence to enable CLKOUT_DP without spread
6464  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6465  */
6466 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6467                                  bool with_fdi)
6468 {
6469         struct drm_i915_private *dev_priv = dev->dev_private;
6470         uint32_t reg, tmp;
6471
6472         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6473                 with_spread = true;
6474         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6475                  with_fdi, "LP PCH doesn't have FDI\n"))
6476                 with_fdi = false;
6477
6478         mutex_lock(&dev_priv->dpio_lock);
6479
6480         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6481         tmp &= ~SBI_SSCCTL_DISABLE;
6482         tmp |= SBI_SSCCTL_PATHALT;
6483         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6484
6485         udelay(24);
6486
6487         if (with_spread) {
6488                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6489                 tmp &= ~SBI_SSCCTL_PATHALT;
6490                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6491
6492                 if (with_fdi) {
6493                         lpt_reset_fdi_mphy(dev_priv);
6494                         lpt_program_fdi_mphy(dev_priv);
6495                 }
6496         }
6497
6498         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6499                SBI_GEN0 : SBI_DBUFF0;
6500         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6501         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6502         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6503
6504         mutex_unlock(&dev_priv->dpio_lock);
6505 }
6506
6507 /* Sequence to disable CLKOUT_DP */
6508 static void lpt_disable_clkout_dp(struct drm_device *dev)
6509 {
6510         struct drm_i915_private *dev_priv = dev->dev_private;
6511         uint32_t reg, tmp;
6512
6513         mutex_lock(&dev_priv->dpio_lock);
6514
6515         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6516                SBI_GEN0 : SBI_DBUFF0;
6517         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6518         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6519         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6520
6521         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6522         if (!(tmp & SBI_SSCCTL_DISABLE)) {
6523                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6524                         tmp |= SBI_SSCCTL_PATHALT;
6525                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6526                         udelay(32);
6527                 }
6528                 tmp |= SBI_SSCCTL_DISABLE;
6529                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6530         }
6531
6532         mutex_unlock(&dev_priv->dpio_lock);
6533 }
6534
6535 static void lpt_init_pch_refclk(struct drm_device *dev)
6536 {
6537         struct drm_mode_config *mode_config = &dev->mode_config;
6538         struct intel_encoder *encoder;
6539         bool has_vga = false;
6540
6541         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
6542                 switch (encoder->type) {
6543                 case INTEL_OUTPUT_ANALOG:
6544                         has_vga = true;
6545                         break;
6546                 }
6547         }
6548
6549         if (has_vga)
6550                 lpt_enable_clkout_dp(dev, true, true);
6551         else
6552                 lpt_disable_clkout_dp(dev);
6553 }
6554
6555 /*
6556  * Initialize reference clocks when the driver loads
6557  */
6558 void intel_init_pch_refclk(struct drm_device *dev)
6559 {
6560         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6561                 ironlake_init_pch_refclk(dev);
6562         else if (HAS_PCH_LPT(dev))
6563                 lpt_init_pch_refclk(dev);
6564 }
6565
6566 static int ironlake_get_refclk(struct drm_crtc *crtc)
6567 {
6568         struct drm_device *dev = crtc->dev;
6569         struct drm_i915_private *dev_priv = dev->dev_private;
6570         struct intel_encoder *encoder;
6571         int num_connectors = 0;
6572         bool is_lvds = false;
6573
6574         for_each_encoder_on_crtc(dev, crtc, encoder) {
6575                 switch (encoder->type) {
6576                 case INTEL_OUTPUT_LVDS:
6577                         is_lvds = true;
6578                         break;
6579                 }
6580                 num_connectors++;
6581         }
6582
6583         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6584                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6585                               dev_priv->vbt.lvds_ssc_freq);
6586                 return dev_priv->vbt.lvds_ssc_freq;
6587         }
6588
6589         return 120000;
6590 }
6591
6592 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6593 {
6594         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6595         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6596         int pipe = intel_crtc->pipe;
6597         uint32_t val;
6598
6599         val = 0;
6600
6601         switch (intel_crtc->config.pipe_bpp) {
6602         case 18:
6603                 val |= PIPECONF_6BPC;
6604                 break;
6605         case 24:
6606                 val |= PIPECONF_8BPC;
6607                 break;
6608         case 30:
6609                 val |= PIPECONF_10BPC;
6610                 break;
6611         case 36:
6612                 val |= PIPECONF_12BPC;
6613                 break;
6614         default:
6615                 /* Case prevented by intel_choose_pipe_bpp_dither. */
6616                 BUG();
6617         }
6618
6619         if (intel_crtc->config.dither)
6620                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6621
6622         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6623                 val |= PIPECONF_INTERLACED_ILK;
6624         else
6625                 val |= PIPECONF_PROGRESSIVE;
6626
6627         if (intel_crtc->config.limited_color_range)
6628                 val |= PIPECONF_COLOR_RANGE_SELECT;
6629
6630         I915_WRITE(PIPECONF(pipe), val);
6631         POSTING_READ(PIPECONF(pipe));
6632 }
6633
6634 /*
6635  * Set up the pipe CSC unit.
6636  *
6637  * Currently only full range RGB to limited range RGB conversion
6638  * is supported, but eventually this should handle various
6639  * RGB<->YCbCr scenarios as well.
6640  */
6641 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6642 {
6643         struct drm_device *dev = crtc->dev;
6644         struct drm_i915_private *dev_priv = dev->dev_private;
6645         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6646         int pipe = intel_crtc->pipe;
6647         uint16_t coeff = 0x7800; /* 1.0 */
6648
6649         /*
6650          * TODO: Check what kind of values actually come out of the pipe
6651          * with these coeff/postoff values and adjust to get the best
6652          * accuracy. Perhaps we even need to take the bpc value into
6653          * consideration.
6654          */
6655
6656         if (intel_crtc->config.limited_color_range)
6657                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6658
6659         /*
6660          * GY/GU and RY/RU should be the other way around according
6661          * to BSpec, but reality doesn't agree. Just set them up in
6662          * a way that results in the correct picture.
6663          */
6664         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6665         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6666
6667         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6668         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6669
6670         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6671         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6672
6673         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6674         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6675         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6676
6677         if (INTEL_INFO(dev)->gen > 6) {
6678                 uint16_t postoff = 0;
6679
6680                 if (intel_crtc->config.limited_color_range)
6681                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
6682
6683                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6684                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6685                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6686
6687                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6688         } else {
6689                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6690
6691                 if (intel_crtc->config.limited_color_range)
6692                         mode |= CSC_BLACK_SCREEN_OFFSET;
6693
6694                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6695         }
6696 }
6697
6698 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6699 {
6700         struct drm_device *dev = crtc->dev;
6701         struct drm_i915_private *dev_priv = dev->dev_private;
6702         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6703         enum pipe pipe = intel_crtc->pipe;
6704         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6705         uint32_t val;
6706
6707         val = 0;
6708
6709         if (IS_HASWELL(dev) && intel_crtc->config.dither)
6710                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6711
6712         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6713                 val |= PIPECONF_INTERLACED_ILK;
6714         else
6715                 val |= PIPECONF_PROGRESSIVE;
6716
6717         I915_WRITE(PIPECONF(cpu_transcoder), val);
6718         POSTING_READ(PIPECONF(cpu_transcoder));
6719
6720         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6721         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6722
6723         if (IS_BROADWELL(dev)) {
6724                 val = 0;
6725
6726                 switch (intel_crtc->config.pipe_bpp) {
6727                 case 18:
6728                         val |= PIPEMISC_DITHER_6_BPC;
6729                         break;
6730                 case 24:
6731                         val |= PIPEMISC_DITHER_8_BPC;
6732                         break;
6733                 case 30:
6734                         val |= PIPEMISC_DITHER_10_BPC;
6735                         break;
6736                 case 36:
6737                         val |= PIPEMISC_DITHER_12_BPC;
6738                         break;
6739                 default:
6740                         /* Case prevented by pipe_config_set_bpp. */
6741                         BUG();
6742                 }
6743
6744                 if (intel_crtc->config.dither)
6745                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6746
6747                 I915_WRITE(PIPEMISC(pipe), val);
6748         }
6749 }
6750
6751 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6752                                     intel_clock_t *clock,
6753                                     bool *has_reduced_clock,
6754                                     intel_clock_t *reduced_clock)
6755 {
6756         struct drm_device *dev = crtc->dev;
6757         struct drm_i915_private *dev_priv = dev->dev_private;
6758         struct intel_encoder *intel_encoder;
6759         int refclk;
6760         const intel_limit_t *limit;
6761         bool ret, is_lvds = false;
6762
6763         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6764                 switch (intel_encoder->type) {
6765                 case INTEL_OUTPUT_LVDS:
6766                         is_lvds = true;
6767                         break;
6768                 }
6769         }
6770
6771         refclk = ironlake_get_refclk(crtc);
6772
6773         /*
6774          * Returns a set of divisors for the desired target clock with the given
6775          * refclk, or FALSE.  The returned values represent the clock equation:
6776          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6777          */
6778         limit = intel_limit(crtc, refclk);
6779         ret = dev_priv->display.find_dpll(limit, crtc,
6780                                           to_intel_crtc(crtc)->config.port_clock,
6781                                           refclk, NULL, clock);
6782         if (!ret)
6783                 return false;
6784
6785         if (is_lvds && dev_priv->lvds_downclock_avail) {
6786                 /*
6787                  * Ensure we match the reduced clock's P to the target clock.
6788                  * If the clocks don't match, we can't switch the display clock
6789                  * by using the FP0/FP1. In such case we will disable the LVDS
6790                  * downclock feature.
6791                 */
6792                 *has_reduced_clock =
6793                         dev_priv->display.find_dpll(limit, crtc,
6794                                                     dev_priv->lvds_downclock,
6795                                                     refclk, clock,
6796                                                     reduced_clock);
6797         }
6798
6799         return true;
6800 }
6801
6802 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6803 {
6804         /*
6805          * Account for spread spectrum to avoid
6806          * oversubscribing the link. Max center spread
6807          * is 2.5%; use 5% for safety's sake.
6808          */
6809         u32 bps = target_clock * bpp * 21 / 20;
6810         return DIV_ROUND_UP(bps, link_bw * 8);
6811 }
6812
6813 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6814 {
6815         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6816 }
6817
6818 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6819                                       u32 *fp,
6820                                       intel_clock_t *reduced_clock, u32 *fp2)
6821 {
6822         struct drm_crtc *crtc = &intel_crtc->base;
6823         struct drm_device *dev = crtc->dev;
6824         struct drm_i915_private *dev_priv = dev->dev_private;
6825         struct intel_encoder *intel_encoder;
6826         uint32_t dpll;
6827         int factor, num_connectors = 0;
6828         bool is_lvds = false, is_sdvo = false;
6829
6830         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6831                 switch (intel_encoder->type) {
6832                 case INTEL_OUTPUT_LVDS:
6833                         is_lvds = true;
6834                         break;
6835                 case INTEL_OUTPUT_SDVO:
6836                 case INTEL_OUTPUT_HDMI:
6837                         is_sdvo = true;
6838                         break;
6839                 }
6840
6841                 num_connectors++;
6842         }
6843
6844         /* Enable autotuning of the PLL clock (if permissible) */
6845         factor = 21;
6846         if (is_lvds) {
6847                 if ((intel_panel_use_ssc(dev_priv) &&
6848                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
6849                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6850                         factor = 25;
6851         } else if (intel_crtc->config.sdvo_tv_clock)
6852                 factor = 20;
6853
6854         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6855                 *fp |= FP_CB_TUNE;
6856
6857         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6858                 *fp2 |= FP_CB_TUNE;
6859
6860         dpll = 0;
6861
6862         if (is_lvds)
6863                 dpll |= DPLLB_MODE_LVDS;
6864         else
6865                 dpll |= DPLLB_MODE_DAC_SERIAL;
6866
6867         dpll |= (intel_crtc->config.pixel_multiplier - 1)
6868                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6869
6870         if (is_sdvo)
6871                 dpll |= DPLL_SDVO_HIGH_SPEED;
6872         if (intel_crtc->config.has_dp_encoder)
6873                 dpll |= DPLL_SDVO_HIGH_SPEED;
6874
6875         /* compute bitmask from p1 value */
6876         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6877         /* also FPA1 */
6878         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6879
6880         switch (intel_crtc->config.dpll.p2) {
6881         case 5:
6882                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6883                 break;
6884         case 7:
6885                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6886                 break;
6887         case 10:
6888                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6889                 break;
6890         case 14:
6891                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6892                 break;
6893         }
6894
6895         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6896                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6897         else
6898                 dpll |= PLL_REF_INPUT_DREFCLK;
6899
6900         return dpll | DPLL_VCO_ENABLE;
6901 }
6902
6903 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
6904                                   int x, int y,
6905                                   struct drm_framebuffer *fb)
6906 {
6907         struct drm_device *dev = crtc->dev;
6908         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6909         int num_connectors = 0;
6910         intel_clock_t clock, reduced_clock;
6911         u32 dpll = 0, fp = 0, fp2 = 0;
6912         bool ok, has_reduced_clock = false;
6913         bool is_lvds = false;
6914         struct intel_encoder *encoder;
6915         struct intel_shared_dpll *pll;
6916
6917         for_each_encoder_on_crtc(dev, crtc, encoder) {
6918                 switch (encoder->type) {
6919                 case INTEL_OUTPUT_LVDS:
6920                         is_lvds = true;
6921                         break;
6922                 }
6923
6924                 num_connectors++;
6925         }
6926
6927         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6928              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6929
6930         ok = ironlake_compute_clocks(crtc, &clock,
6931                                      &has_reduced_clock, &reduced_clock);
6932         if (!ok && !intel_crtc->config.clock_set) {
6933                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6934                 return -EINVAL;
6935         }
6936         /* Compat-code for transition, will disappear. */
6937         if (!intel_crtc->config.clock_set) {
6938                 intel_crtc->config.dpll.n = clock.n;
6939                 intel_crtc->config.dpll.m1 = clock.m1;
6940                 intel_crtc->config.dpll.m2 = clock.m2;
6941                 intel_crtc->config.dpll.p1 = clock.p1;
6942                 intel_crtc->config.dpll.p2 = clock.p2;
6943         }
6944
6945         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6946         if (intel_crtc->config.has_pch_encoder) {
6947                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6948                 if (has_reduced_clock)
6949                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6950
6951                 dpll = ironlake_compute_dpll(intel_crtc,
6952                                              &fp, &reduced_clock,
6953                                              has_reduced_clock ? &fp2 : NULL);
6954
6955                 intel_crtc->config.dpll_hw_state.dpll = dpll;
6956                 intel_crtc->config.dpll_hw_state.fp0 = fp;
6957                 if (has_reduced_clock)
6958                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
6959                 else
6960                         intel_crtc->config.dpll_hw_state.fp1 = fp;
6961
6962                 pll = intel_get_shared_dpll(intel_crtc);
6963                 if (pll == NULL) {
6964                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6965                                          pipe_name(intel_crtc->pipe));
6966                         return -EINVAL;
6967                 }
6968         } else
6969                 intel_put_shared_dpll(intel_crtc);
6970
6971         if (is_lvds && has_reduced_clock && i915.powersave)
6972                 intel_crtc->lowfreq_avail = true;
6973         else
6974                 intel_crtc->lowfreq_avail = false;
6975
6976         return 0;
6977 }
6978
6979 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6980                                          struct intel_link_m_n *m_n)
6981 {
6982         struct drm_device *dev = crtc->base.dev;
6983         struct drm_i915_private *dev_priv = dev->dev_private;
6984         enum pipe pipe = crtc->pipe;
6985
6986         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6987         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6988         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6989                 & ~TU_SIZE_MASK;
6990         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6991         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6992                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6993 }
6994
6995 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6996                                          enum transcoder transcoder,
6997                                          struct intel_link_m_n *m_n)
6998 {
6999         struct drm_device *dev = crtc->base.dev;
7000         struct drm_i915_private *dev_priv = dev->dev_private;
7001         enum pipe pipe = crtc->pipe;
7002
7003         if (INTEL_INFO(dev)->gen >= 5) {
7004                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7005                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7006                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7007                         & ~TU_SIZE_MASK;
7008                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7009                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7010                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7011         } else {
7012                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7013                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7014                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7015                         & ~TU_SIZE_MASK;
7016                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7017                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7018                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7019         }
7020 }
7021
7022 void intel_dp_get_m_n(struct intel_crtc *crtc,
7023                       struct intel_crtc_config *pipe_config)
7024 {
7025         if (crtc->config.has_pch_encoder)
7026                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7027         else
7028                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7029                                              &pipe_config->dp_m_n);
7030 }
7031
7032 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7033                                         struct intel_crtc_config *pipe_config)
7034 {
7035         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7036                                      &pipe_config->fdi_m_n);
7037 }
7038
7039 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7040                                      struct intel_crtc_config *pipe_config)
7041 {
7042         struct drm_device *dev = crtc->base.dev;
7043         struct drm_i915_private *dev_priv = dev->dev_private;
7044         uint32_t tmp;
7045
7046         tmp = I915_READ(PF_CTL(crtc->pipe));
7047
7048         if (tmp & PF_ENABLE) {
7049                 pipe_config->pch_pfit.enabled = true;
7050                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7051                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7052
7053                 /* We currently do not free assignements of panel fitters on
7054                  * ivb/hsw (since we don't use the higher upscaling modes which
7055                  * differentiates them) so just WARN about this case for now. */
7056                 if (IS_GEN7(dev)) {
7057                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7058                                 PF_PIPE_SEL_IVB(crtc->pipe));
7059                 }
7060         }
7061 }
7062
7063 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7064                                       struct intel_plane_config *plane_config)
7065 {
7066         struct drm_device *dev = crtc->base.dev;
7067         struct drm_i915_private *dev_priv = dev->dev_private;
7068         u32 val, base, offset;
7069         int pipe = crtc->pipe, plane = crtc->plane;
7070         int fourcc, pixel_format;
7071         int aligned_height;
7072
7073         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7074         if (!crtc->base.primary->fb) {
7075                 DRM_DEBUG_KMS("failed to alloc fb\n");
7076                 return;
7077         }
7078
7079         val = I915_READ(DSPCNTR(plane));
7080
7081         if (INTEL_INFO(dev)->gen >= 4)
7082                 if (val & DISPPLANE_TILED)
7083                         plane_config->tiled = true;
7084
7085         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7086         fourcc = intel_format_to_fourcc(pixel_format);
7087         crtc->base.primary->fb->pixel_format = fourcc;
7088         crtc->base.primary->fb->bits_per_pixel =
7089                 drm_format_plane_cpp(fourcc, 0) * 8;
7090
7091         base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7092         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7093                 offset = I915_READ(DSPOFFSET(plane));
7094         } else {
7095                 if (plane_config->tiled)
7096                         offset = I915_READ(DSPTILEOFF(plane));
7097                 else
7098                         offset = I915_READ(DSPLINOFF(plane));
7099         }
7100         plane_config->base = base;
7101
7102         val = I915_READ(PIPESRC(pipe));
7103         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7104         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7105
7106         val = I915_READ(DSPSTRIDE(pipe));
7107         crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
7108
7109         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7110                                             plane_config->tiled);
7111
7112         plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
7113                                    aligned_height, PAGE_SIZE);
7114
7115         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7116                       pipe, plane, crtc->base.primary->fb->width,
7117                       crtc->base.primary->fb->height,
7118                       crtc->base.primary->fb->bits_per_pixel, base,
7119                       crtc->base.primary->fb->pitches[0],
7120                       plane_config->size);
7121 }
7122
7123 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7124                                      struct intel_crtc_config *pipe_config)
7125 {
7126         struct drm_device *dev = crtc->base.dev;
7127         struct drm_i915_private *dev_priv = dev->dev_private;
7128         uint32_t tmp;
7129
7130         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7131         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7132
7133         tmp = I915_READ(PIPECONF(crtc->pipe));
7134         if (!(tmp & PIPECONF_ENABLE))
7135                 return false;
7136
7137         switch (tmp & PIPECONF_BPC_MASK) {
7138         case PIPECONF_6BPC:
7139                 pipe_config->pipe_bpp = 18;
7140                 break;
7141         case PIPECONF_8BPC:
7142                 pipe_config->pipe_bpp = 24;
7143                 break;
7144         case PIPECONF_10BPC:
7145                 pipe_config->pipe_bpp = 30;
7146                 break;
7147         case PIPECONF_12BPC:
7148                 pipe_config->pipe_bpp = 36;
7149                 break;
7150         default:
7151                 break;
7152         }
7153
7154         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7155                 pipe_config->limited_color_range = true;
7156
7157         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7158                 struct intel_shared_dpll *pll;
7159
7160                 pipe_config->has_pch_encoder = true;
7161
7162                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7163                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7164                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7165
7166                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7167
7168                 if (HAS_PCH_IBX(dev_priv->dev)) {
7169                         pipe_config->shared_dpll =
7170                                 (enum intel_dpll_id) crtc->pipe;
7171                 } else {
7172                         tmp = I915_READ(PCH_DPLL_SEL);
7173                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7174                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7175                         else
7176                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7177                 }
7178
7179                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7180
7181                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7182                                            &pipe_config->dpll_hw_state));
7183
7184                 tmp = pipe_config->dpll_hw_state.dpll;
7185                 pipe_config->pixel_multiplier =
7186                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7187                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7188
7189                 ironlake_pch_clock_get(crtc, pipe_config);
7190         } else {
7191                 pipe_config->pixel_multiplier = 1;
7192         }
7193
7194         intel_get_pipe_timings(crtc, pipe_config);
7195
7196         ironlake_get_pfit_config(crtc, pipe_config);
7197
7198         return true;
7199 }
7200
7201 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7202 {
7203         struct drm_device *dev = dev_priv->dev;
7204         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
7205         struct intel_crtc *crtc;
7206
7207         for_each_intel_crtc(dev, crtc)
7208                 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7209                      pipe_name(crtc->pipe));
7210
7211         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7212         WARN(plls->spll_refcount, "SPLL enabled\n");
7213         WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
7214         WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
7215         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7216         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7217              "CPU PWM1 enabled\n");
7218         WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7219              "CPU PWM2 enabled\n");
7220         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7221              "PCH PWM1 enabled\n");
7222         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7223              "Utility pin enabled\n");
7224         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7225
7226         /*
7227          * In theory we can still leave IRQs enabled, as long as only the HPD
7228          * interrupts remain enabled. We used to check for that, but since it's
7229          * gen-specific and since we only disable LCPLL after we fully disable
7230          * the interrupts, the check below should be enough.
7231          */
7232         WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n");
7233 }
7234
7235 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7236 {
7237         struct drm_device *dev = dev_priv->dev;
7238
7239         if (IS_HASWELL(dev)) {
7240                 mutex_lock(&dev_priv->rps.hw_lock);
7241                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7242                                             val))
7243                         DRM_ERROR("Failed to disable D_COMP\n");
7244                 mutex_unlock(&dev_priv->rps.hw_lock);
7245         } else {
7246                 I915_WRITE(D_COMP, val);
7247         }
7248         POSTING_READ(D_COMP);
7249 }
7250
7251 /*
7252  * This function implements pieces of two sequences from BSpec:
7253  * - Sequence for display software to disable LCPLL
7254  * - Sequence for display software to allow package C8+
7255  * The steps implemented here are just the steps that actually touch the LCPLL
7256  * register. Callers should take care of disabling all the display engine
7257  * functions, doing the mode unset, fixing interrupts, etc.
7258  */
7259 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7260                               bool switch_to_fclk, bool allow_power_down)
7261 {
7262         uint32_t val;
7263
7264         assert_can_disable_lcpll(dev_priv);
7265
7266         val = I915_READ(LCPLL_CTL);
7267
7268         if (switch_to_fclk) {
7269                 val |= LCPLL_CD_SOURCE_FCLK;
7270                 I915_WRITE(LCPLL_CTL, val);
7271
7272                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7273                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
7274                         DRM_ERROR("Switching to FCLK failed\n");
7275
7276                 val = I915_READ(LCPLL_CTL);
7277         }
7278
7279         val |= LCPLL_PLL_DISABLE;
7280         I915_WRITE(LCPLL_CTL, val);
7281         POSTING_READ(LCPLL_CTL);
7282
7283         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7284                 DRM_ERROR("LCPLL still locked\n");
7285
7286         val = I915_READ(D_COMP);
7287         val |= D_COMP_COMP_DISABLE;
7288         hsw_write_dcomp(dev_priv, val);
7289         ndelay(100);
7290
7291         if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
7292                 DRM_ERROR("D_COMP RCOMP still in progress\n");
7293
7294         if (allow_power_down) {
7295                 val = I915_READ(LCPLL_CTL);
7296                 val |= LCPLL_POWER_DOWN_ALLOW;
7297                 I915_WRITE(LCPLL_CTL, val);
7298                 POSTING_READ(LCPLL_CTL);
7299         }
7300 }
7301
7302 /*
7303  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7304  * source.
7305  */
7306 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7307 {
7308         uint32_t val;
7309         unsigned long irqflags;
7310
7311         val = I915_READ(LCPLL_CTL);
7312
7313         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7314                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7315                 return;
7316
7317         /*
7318          * Make sure we're not on PC8 state before disabling PC8, otherwise
7319          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7320          *
7321          * The other problem is that hsw_restore_lcpll() is called as part of
7322          * the runtime PM resume sequence, so we can't just call
7323          * gen6_gt_force_wake_get() because that function calls
7324          * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7325          * while we are on the resume sequence. So to solve this problem we have
7326          * to call special forcewake code that doesn't touch runtime PM and
7327          * doesn't enable the forcewake delayed work.
7328          */
7329         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7330         if (dev_priv->uncore.forcewake_count++ == 0)
7331                 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7332         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7333
7334         if (val & LCPLL_POWER_DOWN_ALLOW) {
7335                 val &= ~LCPLL_POWER_DOWN_ALLOW;
7336                 I915_WRITE(LCPLL_CTL, val);
7337                 POSTING_READ(LCPLL_CTL);
7338         }
7339
7340         val = I915_READ(D_COMP);
7341         val |= D_COMP_COMP_FORCE;
7342         val &= ~D_COMP_COMP_DISABLE;
7343         hsw_write_dcomp(dev_priv, val);
7344
7345         val = I915_READ(LCPLL_CTL);
7346         val &= ~LCPLL_PLL_DISABLE;
7347         I915_WRITE(LCPLL_CTL, val);
7348
7349         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7350                 DRM_ERROR("LCPLL not locked yet\n");
7351
7352         if (val & LCPLL_CD_SOURCE_FCLK) {
7353                 val = I915_READ(LCPLL_CTL);
7354                 val &= ~LCPLL_CD_SOURCE_FCLK;
7355                 I915_WRITE(LCPLL_CTL, val);
7356
7357                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7358                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7359                         DRM_ERROR("Switching back to LCPLL failed\n");
7360         }
7361
7362         /* See the big comment above. */
7363         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7364         if (--dev_priv->uncore.forcewake_count == 0)
7365                 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7366         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7367 }
7368
7369 /*
7370  * Package states C8 and deeper are really deep PC states that can only be
7371  * reached when all the devices on the system allow it, so even if the graphics
7372  * device allows PC8+, it doesn't mean the system will actually get to these
7373  * states. Our driver only allows PC8+ when going into runtime PM.
7374  *
7375  * The requirements for PC8+ are that all the outputs are disabled, the power
7376  * well is disabled and most interrupts are disabled, and these are also
7377  * requirements for runtime PM. When these conditions are met, we manually do
7378  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7379  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7380  * hang the machine.
7381  *
7382  * When we really reach PC8 or deeper states (not just when we allow it) we lose
7383  * the state of some registers, so when we come back from PC8+ we need to
7384  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7385  * need to take care of the registers kept by RC6. Notice that this happens even
7386  * if we don't put the device in PCI D3 state (which is what currently happens
7387  * because of the runtime PM support).
7388  *
7389  * For more, read "Display Sequences for Package C8" on the hardware
7390  * documentation.
7391  */
7392 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7393 {
7394         struct drm_device *dev = dev_priv->dev;
7395         uint32_t val;
7396
7397         DRM_DEBUG_KMS("Enabling package C8+\n");
7398
7399         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7400                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7401                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7402                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7403         }
7404
7405         lpt_disable_clkout_dp(dev);
7406         hsw_disable_lcpll(dev_priv, true, true);
7407 }
7408
7409 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7410 {
7411         struct drm_device *dev = dev_priv->dev;
7412         uint32_t val;
7413
7414         DRM_DEBUG_KMS("Disabling package C8+\n");
7415
7416         hsw_restore_lcpll(dev_priv);
7417         lpt_init_pch_refclk(dev);
7418
7419         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7420                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7421                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7422                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7423         }
7424
7425         intel_prepare_ddi(dev);
7426 }
7427
7428 static void snb_modeset_global_resources(struct drm_device *dev)
7429 {
7430         modeset_update_crtc_power_domains(dev);
7431 }
7432
7433 static void haswell_modeset_global_resources(struct drm_device *dev)
7434 {
7435         modeset_update_crtc_power_domains(dev);
7436 }
7437
7438 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7439                                  int x, int y,
7440                                  struct drm_framebuffer *fb)
7441 {
7442         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7443
7444         if (!intel_ddi_pll_select(intel_crtc))
7445                 return -EINVAL;
7446         intel_ddi_pll_enable(intel_crtc);
7447
7448         intel_crtc->lowfreq_avail = false;
7449
7450         return 0;
7451 }
7452
7453 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7454                                     struct intel_crtc_config *pipe_config)
7455 {
7456         struct drm_device *dev = crtc->base.dev;
7457         struct drm_i915_private *dev_priv = dev->dev_private;
7458         enum intel_display_power_domain pfit_domain;
7459         uint32_t tmp;
7460
7461         if (!intel_display_power_enabled(dev_priv,
7462                                          POWER_DOMAIN_PIPE(crtc->pipe)))
7463                 return false;
7464
7465         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7466         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7467
7468         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7469         if (tmp & TRANS_DDI_FUNC_ENABLE) {
7470                 enum pipe trans_edp_pipe;
7471                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7472                 default:
7473                         WARN(1, "unknown pipe linked to edp transcoder\n");
7474                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7475                 case TRANS_DDI_EDP_INPUT_A_ON:
7476                         trans_edp_pipe = PIPE_A;
7477                         break;
7478                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7479                         trans_edp_pipe = PIPE_B;
7480                         break;
7481                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7482                         trans_edp_pipe = PIPE_C;
7483                         break;
7484                 }
7485
7486                 if (trans_edp_pipe == crtc->pipe)
7487                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
7488         }
7489
7490         if (!intel_display_power_enabled(dev_priv,
7491                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7492                 return false;
7493
7494         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7495         if (!(tmp & PIPECONF_ENABLE))
7496                 return false;
7497
7498         /*
7499          * Haswell has only FDI/PCH transcoder A. It is which is connected to
7500          * DDI E. So just check whether this pipe is wired to DDI E and whether
7501          * the PCH transcoder is on.
7502          */
7503         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7504         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
7505             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7506                 pipe_config->has_pch_encoder = true;
7507
7508                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7509                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7510                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7511
7512                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7513         }
7514
7515         intel_get_pipe_timings(crtc, pipe_config);
7516
7517         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7518         if (intel_display_power_enabled(dev_priv, pfit_domain))
7519                 ironlake_get_pfit_config(crtc, pipe_config);
7520
7521         if (IS_HASWELL(dev))
7522                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7523                         (I915_READ(IPS_CTL) & IPS_ENABLE);
7524
7525         pipe_config->pixel_multiplier = 1;
7526
7527         return true;
7528 }
7529
7530 static struct {
7531         int clock;
7532         u32 config;
7533 } hdmi_audio_clock[] = {
7534         { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7535         { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7536         { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7537         { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7538         { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7539         { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7540         { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7541         { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7542         { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7543         { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7544 };
7545
7546 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7547 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7548 {
7549         int i;
7550
7551         for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7552                 if (mode->clock == hdmi_audio_clock[i].clock)
7553                         break;
7554         }
7555
7556         if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7557                 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7558                 i = 1;
7559         }
7560
7561         DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7562                       hdmi_audio_clock[i].clock,
7563                       hdmi_audio_clock[i].config);
7564
7565         return hdmi_audio_clock[i].config;
7566 }
7567
7568 static bool intel_eld_uptodate(struct drm_connector *connector,
7569                                int reg_eldv, uint32_t bits_eldv,
7570                                int reg_elda, uint32_t bits_elda,
7571                                int reg_edid)
7572 {
7573         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7574         uint8_t *eld = connector->eld;
7575         uint32_t i;
7576
7577         i = I915_READ(reg_eldv);
7578         i &= bits_eldv;
7579
7580         if (!eld[0])
7581                 return !i;
7582
7583         if (!i)
7584                 return false;
7585
7586         i = I915_READ(reg_elda);
7587         i &= ~bits_elda;
7588         I915_WRITE(reg_elda, i);
7589
7590         for (i = 0; i < eld[2]; i++)
7591                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7592                         return false;
7593
7594         return true;
7595 }
7596
7597 static void g4x_write_eld(struct drm_connector *connector,
7598                           struct drm_crtc *crtc,
7599                           struct drm_display_mode *mode)
7600 {
7601         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7602         uint8_t *eld = connector->eld;
7603         uint32_t eldv;
7604         uint32_t len;
7605         uint32_t i;
7606
7607         i = I915_READ(G4X_AUD_VID_DID);
7608
7609         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7610                 eldv = G4X_ELDV_DEVCL_DEVBLC;
7611         else
7612                 eldv = G4X_ELDV_DEVCTG;
7613
7614         if (intel_eld_uptodate(connector,
7615                                G4X_AUD_CNTL_ST, eldv,
7616                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7617                                G4X_HDMIW_HDMIEDID))
7618                 return;
7619
7620         i = I915_READ(G4X_AUD_CNTL_ST);
7621         i &= ~(eldv | G4X_ELD_ADDR);
7622         len = (i >> 9) & 0x1f;          /* ELD buffer size */
7623         I915_WRITE(G4X_AUD_CNTL_ST, i);
7624
7625         if (!eld[0])
7626                 return;
7627
7628         len = min_t(uint8_t, eld[2], len);
7629         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7630         for (i = 0; i < len; i++)
7631                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7632
7633         i = I915_READ(G4X_AUD_CNTL_ST);
7634         i |= eldv;
7635         I915_WRITE(G4X_AUD_CNTL_ST, i);
7636 }
7637
7638 static void haswell_write_eld(struct drm_connector *connector,
7639                               struct drm_crtc *crtc,
7640                               struct drm_display_mode *mode)
7641 {
7642         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7643         uint8_t *eld = connector->eld;
7644         uint32_t eldv;
7645         uint32_t i;
7646         int len;
7647         int pipe = to_intel_crtc(crtc)->pipe;
7648         int tmp;
7649
7650         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7651         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7652         int aud_config = HSW_AUD_CFG(pipe);
7653         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7654
7655         /* Audio output enable */
7656         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7657         tmp = I915_READ(aud_cntrl_st2);
7658         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7659         I915_WRITE(aud_cntrl_st2, tmp);
7660         POSTING_READ(aud_cntrl_st2);
7661
7662         assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
7663
7664         /* Set ELD valid state */
7665         tmp = I915_READ(aud_cntrl_st2);
7666         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7667         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7668         I915_WRITE(aud_cntrl_st2, tmp);
7669         tmp = I915_READ(aud_cntrl_st2);
7670         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7671
7672         /* Enable HDMI mode */
7673         tmp = I915_READ(aud_config);
7674         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7675         /* clear N_programing_enable and N_value_index */
7676         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7677         I915_WRITE(aud_config, tmp);
7678
7679         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7680
7681         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7682
7683         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7684                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7685                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7686                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7687         } else {
7688                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7689         }
7690
7691         if (intel_eld_uptodate(connector,
7692                                aud_cntrl_st2, eldv,
7693                                aud_cntl_st, IBX_ELD_ADDRESS,
7694                                hdmiw_hdmiedid))
7695                 return;
7696
7697         i = I915_READ(aud_cntrl_st2);
7698         i &= ~eldv;
7699         I915_WRITE(aud_cntrl_st2, i);
7700
7701         if (!eld[0])
7702                 return;
7703
7704         i = I915_READ(aud_cntl_st);
7705         i &= ~IBX_ELD_ADDRESS;
7706         I915_WRITE(aud_cntl_st, i);
7707         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
7708         DRM_DEBUG_DRIVER("port num:%d\n", i);
7709
7710         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7711         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7712         for (i = 0; i < len; i++)
7713                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7714
7715         i = I915_READ(aud_cntrl_st2);
7716         i |= eldv;
7717         I915_WRITE(aud_cntrl_st2, i);
7718
7719 }
7720
7721 static void ironlake_write_eld(struct drm_connector *connector,
7722                                struct drm_crtc *crtc,
7723                                struct drm_display_mode *mode)
7724 {
7725         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7726         uint8_t *eld = connector->eld;
7727         uint32_t eldv;
7728         uint32_t i;
7729         int len;
7730         int hdmiw_hdmiedid;
7731         int aud_config;
7732         int aud_cntl_st;
7733         int aud_cntrl_st2;
7734         int pipe = to_intel_crtc(crtc)->pipe;
7735
7736         if (HAS_PCH_IBX(connector->dev)) {
7737                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7738                 aud_config = IBX_AUD_CFG(pipe);
7739                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7740                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7741         } else if (IS_VALLEYVIEW(connector->dev)) {
7742                 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7743                 aud_config = VLV_AUD_CFG(pipe);
7744                 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7745                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7746         } else {
7747                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7748                 aud_config = CPT_AUD_CFG(pipe);
7749                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7750                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7751         }
7752
7753         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7754
7755         if (IS_VALLEYVIEW(connector->dev))  {
7756                 struct intel_encoder *intel_encoder;
7757                 struct intel_digital_port *intel_dig_port;
7758
7759                 intel_encoder = intel_attached_encoder(connector);
7760                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7761                 i = intel_dig_port->port;
7762         } else {
7763                 i = I915_READ(aud_cntl_st);
7764                 i = (i >> 29) & DIP_PORT_SEL_MASK;
7765                 /* DIP_Port_Select, 0x1 = PortB */
7766         }
7767
7768         if (!i) {
7769                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7770                 /* operate blindly on all ports */
7771                 eldv = IBX_ELD_VALIDB;
7772                 eldv |= IBX_ELD_VALIDB << 4;
7773                 eldv |= IBX_ELD_VALIDB << 8;
7774         } else {
7775                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7776                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7777         }
7778
7779         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7780                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7781                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7782                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7783         } else {
7784                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7785         }
7786
7787         if (intel_eld_uptodate(connector,
7788                                aud_cntrl_st2, eldv,
7789                                aud_cntl_st, IBX_ELD_ADDRESS,
7790                                hdmiw_hdmiedid))
7791                 return;
7792
7793         i = I915_READ(aud_cntrl_st2);
7794         i &= ~eldv;
7795         I915_WRITE(aud_cntrl_st2, i);
7796
7797         if (!eld[0])
7798                 return;
7799
7800         i = I915_READ(aud_cntl_st);
7801         i &= ~IBX_ELD_ADDRESS;
7802         I915_WRITE(aud_cntl_st, i);
7803
7804         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7805         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7806         for (i = 0; i < len; i++)
7807                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7808
7809         i = I915_READ(aud_cntrl_st2);
7810         i |= eldv;
7811         I915_WRITE(aud_cntrl_st2, i);
7812 }
7813
7814 void intel_write_eld(struct drm_encoder *encoder,
7815                      struct drm_display_mode *mode)
7816 {
7817         struct drm_crtc *crtc = encoder->crtc;
7818         struct drm_connector *connector;
7819         struct drm_device *dev = encoder->dev;
7820         struct drm_i915_private *dev_priv = dev->dev_private;
7821
7822         connector = drm_select_eld(encoder, mode);
7823         if (!connector)
7824                 return;
7825
7826         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7827                          connector->base.id,
7828                          drm_get_connector_name(connector),
7829                          connector->encoder->base.id,
7830                          drm_get_encoder_name(connector->encoder));
7831
7832         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7833
7834         if (dev_priv->display.write_eld)
7835                 dev_priv->display.write_eld(connector, crtc, mode);
7836 }
7837
7838 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7839 {
7840         struct drm_device *dev = crtc->dev;
7841         struct drm_i915_private *dev_priv = dev->dev_private;
7842         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7843         bool visible = base != 0;
7844         u32 cntl;
7845
7846         if (intel_crtc->cursor_visible == visible)
7847                 return;
7848
7849         cntl = I915_READ(_CURACNTR);
7850         if (visible) {
7851                 /* On these chipsets we can only modify the base whilst
7852                  * the cursor is disabled.
7853                  */
7854                 I915_WRITE(_CURABASE, base);
7855
7856                 cntl &= ~(CURSOR_FORMAT_MASK);
7857                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7858                 cntl |= CURSOR_ENABLE |
7859                         CURSOR_GAMMA_ENABLE |
7860                         CURSOR_FORMAT_ARGB;
7861         } else
7862                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
7863         I915_WRITE(_CURACNTR, cntl);
7864
7865         intel_crtc->cursor_visible = visible;
7866 }
7867
7868 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7869 {
7870         struct drm_device *dev = crtc->dev;
7871         struct drm_i915_private *dev_priv = dev->dev_private;
7872         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7873         int pipe = intel_crtc->pipe;
7874         bool visible = base != 0;
7875
7876         if (intel_crtc->cursor_visible != visible) {
7877                 int16_t width = intel_crtc->cursor_width;
7878                 uint32_t cntl = I915_READ(CURCNTR(pipe));
7879                 if (base) {
7880                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7881                         cntl |= MCURSOR_GAMMA_ENABLE;
7882
7883                         switch (width) {
7884                         case 64:
7885                                 cntl |= CURSOR_MODE_64_ARGB_AX;
7886                                 break;
7887                         case 128:
7888                                 cntl |= CURSOR_MODE_128_ARGB_AX;
7889                                 break;
7890                         case 256:
7891                                 cntl |= CURSOR_MODE_256_ARGB_AX;
7892                                 break;
7893                         default:
7894                                 WARN_ON(1);
7895                                 return;
7896                         }
7897                         cntl |= pipe << 28; /* Connect to correct pipe */
7898                 } else {
7899                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7900                         cntl |= CURSOR_MODE_DISABLE;
7901                 }
7902                 I915_WRITE(CURCNTR(pipe), cntl);
7903
7904                 intel_crtc->cursor_visible = visible;
7905         }
7906         /* and commit changes on next vblank */
7907         POSTING_READ(CURCNTR(pipe));
7908         I915_WRITE(CURBASE(pipe), base);
7909         POSTING_READ(CURBASE(pipe));
7910 }
7911
7912 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7913 {
7914         struct drm_device *dev = crtc->dev;
7915         struct drm_i915_private *dev_priv = dev->dev_private;
7916         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7917         int pipe = intel_crtc->pipe;
7918         bool visible = base != 0;
7919
7920         if (intel_crtc->cursor_visible != visible) {
7921                 int16_t width = intel_crtc->cursor_width;
7922                 uint32_t cntl = I915_READ(CURCNTR(pipe));
7923                 if (base) {
7924                         cntl &= ~CURSOR_MODE;
7925                         cntl |= MCURSOR_GAMMA_ENABLE;
7926                         switch (width) {
7927                         case 64:
7928                                 cntl |= CURSOR_MODE_64_ARGB_AX;
7929                                 break;
7930                         case 128:
7931                                 cntl |= CURSOR_MODE_128_ARGB_AX;
7932                                 break;
7933                         case 256:
7934                                 cntl |= CURSOR_MODE_256_ARGB_AX;
7935                                 break;
7936                         default:
7937                                 WARN_ON(1);
7938                                 return;
7939                         }
7940                 } else {
7941                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7942                         cntl |= CURSOR_MODE_DISABLE;
7943                 }
7944                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7945                         cntl |= CURSOR_PIPE_CSC_ENABLE;
7946                         cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7947                 }
7948                 I915_WRITE(CURCNTR(pipe), cntl);
7949
7950                 intel_crtc->cursor_visible = visible;
7951         }
7952         /* and commit changes on next vblank */
7953         POSTING_READ(CURCNTR(pipe));
7954         I915_WRITE(CURBASE(pipe), base);
7955         POSTING_READ(CURBASE(pipe));
7956 }
7957
7958 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7959 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7960                                      bool on)
7961 {
7962         struct drm_device *dev = crtc->dev;
7963         struct drm_i915_private *dev_priv = dev->dev_private;
7964         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7965         int pipe = intel_crtc->pipe;
7966         int x = intel_crtc->cursor_x;
7967         int y = intel_crtc->cursor_y;
7968         u32 base = 0, pos = 0;
7969         bool visible;
7970
7971         if (on)
7972                 base = intel_crtc->cursor_addr;
7973
7974         if (x >= intel_crtc->config.pipe_src_w)
7975                 base = 0;
7976
7977         if (y >= intel_crtc->config.pipe_src_h)
7978                 base = 0;
7979
7980         if (x < 0) {
7981                 if (x + intel_crtc->cursor_width <= 0)
7982                         base = 0;
7983
7984                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7985                 x = -x;
7986         }
7987         pos |= x << CURSOR_X_SHIFT;
7988
7989         if (y < 0) {
7990                 if (y + intel_crtc->cursor_height <= 0)
7991                         base = 0;
7992
7993                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7994                 y = -y;
7995         }
7996         pos |= y << CURSOR_Y_SHIFT;
7997
7998         visible = base != 0;
7999         if (!visible && !intel_crtc->cursor_visible)
8000                 return;
8001
8002         I915_WRITE(CURPOS(pipe), pos);
8003
8004         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev))
8005                 ivb_update_cursor(crtc, base);
8006         else if (IS_845G(dev) || IS_I865G(dev))
8007                 i845_update_cursor(crtc, base);
8008         else
8009                 i9xx_update_cursor(crtc, base);
8010 }
8011
8012 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
8013                                  struct drm_file *file,
8014                                  uint32_t handle,
8015                                  uint32_t width, uint32_t height)
8016 {
8017         struct drm_device *dev = crtc->dev;
8018         struct drm_i915_private *dev_priv = dev->dev_private;
8019         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8020         struct drm_i915_gem_object *obj;
8021         unsigned old_width;
8022         uint32_t addr;
8023         int ret;
8024
8025         /* if we want to turn off the cursor ignore width and height */
8026         if (!handle) {
8027                 DRM_DEBUG_KMS("cursor off\n");
8028                 addr = 0;
8029                 obj = NULL;
8030                 mutex_lock(&dev->struct_mutex);
8031                 goto finish;
8032         }
8033
8034         /* Check for which cursor types we support */
8035         if (!((width == 64 && height == 64) ||
8036                         (width == 128 && height == 128 && !IS_GEN2(dev)) ||
8037                         (width == 256 && height == 256 && !IS_GEN2(dev)))) {
8038                 DRM_DEBUG("Cursor dimension not supported\n");
8039                 return -EINVAL;
8040         }
8041
8042         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
8043         if (&obj->base == NULL)
8044                 return -ENOENT;
8045
8046         if (obj->base.size < width * height * 4) {
8047                 DRM_DEBUG_KMS("buffer is to small\n");
8048                 ret = -ENOMEM;
8049                 goto fail;
8050         }
8051
8052         /* we only need to pin inside GTT if cursor is non-phy */
8053         mutex_lock(&dev->struct_mutex);
8054         if (!INTEL_INFO(dev)->cursor_needs_physical) {
8055                 unsigned alignment;
8056
8057                 if (obj->tiling_mode) {
8058                         DRM_DEBUG_KMS("cursor cannot be tiled\n");
8059                         ret = -EINVAL;
8060                         goto fail_locked;
8061                 }
8062
8063                 /* Note that the w/a also requires 2 PTE of padding following
8064                  * the bo. We currently fill all unused PTE with the shadow
8065                  * page and so we should always have valid PTE following the
8066                  * cursor preventing the VT-d warning.
8067                  */
8068                 alignment = 0;
8069                 if (need_vtd_wa(dev))
8070                         alignment = 64*1024;
8071
8072                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8073                 if (ret) {
8074                         DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8075                         goto fail_locked;
8076                 }
8077
8078                 ret = i915_gem_object_put_fence(obj);
8079                 if (ret) {
8080                         DRM_DEBUG_KMS("failed to release fence for cursor");
8081                         goto fail_unpin;
8082                 }
8083
8084                 addr = i915_gem_obj_ggtt_offset(obj);
8085         } else {
8086                 int align = IS_I830(dev) ? 16 * 1024 : 256;
8087                 ret = i915_gem_attach_phys_object(dev, obj,
8088                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
8089                                                   align);
8090                 if (ret) {
8091                         DRM_DEBUG_KMS("failed to attach phys object\n");
8092                         goto fail_locked;
8093                 }
8094                 addr = obj->phys_obj->handle->busaddr;
8095         }
8096
8097         if (IS_GEN2(dev))
8098                 I915_WRITE(CURSIZE, (height << 12) | width);
8099
8100  finish:
8101         if (intel_crtc->cursor_bo) {
8102                 if (INTEL_INFO(dev)->cursor_needs_physical) {
8103                         if (intel_crtc->cursor_bo != obj)
8104                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
8105                 } else
8106                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8107                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
8108         }
8109
8110         mutex_unlock(&dev->struct_mutex);
8111
8112         old_width = intel_crtc->cursor_width;
8113
8114         intel_crtc->cursor_addr = addr;
8115         intel_crtc->cursor_bo = obj;
8116         intel_crtc->cursor_width = width;
8117         intel_crtc->cursor_height = height;
8118
8119         if (intel_crtc->active) {
8120                 if (old_width != width)
8121                         intel_update_watermarks(crtc);
8122                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8123         }
8124
8125         return 0;
8126 fail_unpin:
8127         i915_gem_object_unpin_from_display_plane(obj);
8128 fail_locked:
8129         mutex_unlock(&dev->struct_mutex);
8130 fail:
8131         drm_gem_object_unreference_unlocked(&obj->base);
8132         return ret;
8133 }
8134
8135 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
8136 {
8137         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8138
8139         intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
8140         intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
8141
8142         if (intel_crtc->active)
8143                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8144
8145         return 0;
8146 }
8147
8148 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8149                                  u16 *blue, uint32_t start, uint32_t size)
8150 {
8151         int end = (start + size > 256) ? 256 : start + size, i;
8152         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8153
8154         for (i = start; i < end; i++) {
8155                 intel_crtc->lut_r[i] = red[i] >> 8;
8156                 intel_crtc->lut_g[i] = green[i] >> 8;
8157                 intel_crtc->lut_b[i] = blue[i] >> 8;
8158         }
8159
8160         intel_crtc_load_lut(crtc);
8161 }
8162
8163 /* VESA 640x480x72Hz mode to set on the pipe */
8164 static struct drm_display_mode load_detect_mode = {
8165         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8166                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8167 };
8168
8169 struct drm_framebuffer *
8170 __intel_framebuffer_create(struct drm_device *dev,
8171                            struct drm_mode_fb_cmd2 *mode_cmd,
8172                            struct drm_i915_gem_object *obj)
8173 {
8174         struct intel_framebuffer *intel_fb;
8175         int ret;
8176
8177         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8178         if (!intel_fb) {
8179                 drm_gem_object_unreference_unlocked(&obj->base);
8180                 return ERR_PTR(-ENOMEM);
8181         }
8182
8183         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8184         if (ret)
8185                 goto err;
8186
8187         return &intel_fb->base;
8188 err:
8189         drm_gem_object_unreference_unlocked(&obj->base);
8190         kfree(intel_fb);
8191
8192         return ERR_PTR(ret);
8193 }
8194
8195 static struct drm_framebuffer *
8196 intel_framebuffer_create(struct drm_device *dev,
8197                          struct drm_mode_fb_cmd2 *mode_cmd,
8198                          struct drm_i915_gem_object *obj)
8199 {
8200         struct drm_framebuffer *fb;
8201         int ret;
8202
8203         ret = i915_mutex_lock_interruptible(dev);
8204         if (ret)
8205                 return ERR_PTR(ret);
8206         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8207         mutex_unlock(&dev->struct_mutex);
8208
8209         return fb;
8210 }
8211
8212 static u32
8213 intel_framebuffer_pitch_for_width(int width, int bpp)
8214 {
8215         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8216         return ALIGN(pitch, 64);
8217 }
8218
8219 static u32
8220 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8221 {
8222         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8223         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
8224 }
8225
8226 static struct drm_framebuffer *
8227 intel_framebuffer_create_for_mode(struct drm_device *dev,
8228                                   struct drm_display_mode *mode,
8229                                   int depth, int bpp)
8230 {
8231         struct drm_i915_gem_object *obj;
8232         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8233
8234         obj = i915_gem_alloc_object(dev,
8235                                     intel_framebuffer_size_for_mode(mode, bpp));
8236         if (obj == NULL)
8237                 return ERR_PTR(-ENOMEM);
8238
8239         mode_cmd.width = mode->hdisplay;
8240         mode_cmd.height = mode->vdisplay;
8241         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8242                                                                 bpp);
8243         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8244
8245         return intel_framebuffer_create(dev, &mode_cmd, obj);
8246 }
8247
8248 static struct drm_framebuffer *
8249 mode_fits_in_fbdev(struct drm_device *dev,
8250                    struct drm_display_mode *mode)
8251 {
8252 #ifdef CONFIG_DRM_I915_FBDEV
8253         struct drm_i915_private *dev_priv = dev->dev_private;
8254         struct drm_i915_gem_object *obj;
8255         struct drm_framebuffer *fb;
8256
8257         if (!dev_priv->fbdev)
8258                 return NULL;
8259
8260         if (!dev_priv->fbdev->fb)
8261                 return NULL;
8262
8263         obj = dev_priv->fbdev->fb->obj;
8264         BUG_ON(!obj);
8265
8266         fb = &dev_priv->fbdev->fb->base;
8267         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8268                                                                fb->bits_per_pixel))
8269                 return NULL;
8270
8271         if (obj->base.size < mode->vdisplay * fb->pitches[0])
8272                 return NULL;
8273
8274         return fb;
8275 #else
8276         return NULL;
8277 #endif
8278 }
8279
8280 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8281                                 struct drm_display_mode *mode,
8282                                 struct intel_load_detect_pipe *old)
8283 {
8284         struct intel_crtc *intel_crtc;
8285         struct intel_encoder *intel_encoder =
8286                 intel_attached_encoder(connector);
8287         struct drm_crtc *possible_crtc;
8288         struct drm_encoder *encoder = &intel_encoder->base;
8289         struct drm_crtc *crtc = NULL;
8290         struct drm_device *dev = encoder->dev;
8291         struct drm_framebuffer *fb;
8292         int i = -1;
8293
8294         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8295                       connector->base.id, drm_get_connector_name(connector),
8296                       encoder->base.id, drm_get_encoder_name(encoder));
8297
8298         /*
8299          * Algorithm gets a little messy:
8300          *
8301          *   - if the connector already has an assigned crtc, use it (but make
8302          *     sure it's on first)
8303          *
8304          *   - try to find the first unused crtc that can drive this connector,
8305          *     and use that if we find one
8306          */
8307
8308         /* See if we already have a CRTC for this connector */
8309         if (encoder->crtc) {
8310                 crtc = encoder->crtc;
8311
8312                 mutex_lock(&crtc->mutex);
8313
8314                 old->dpms_mode = connector->dpms;
8315                 old->load_detect_temp = false;
8316
8317                 /* Make sure the crtc and connector are running */
8318                 if (connector->dpms != DRM_MODE_DPMS_ON)
8319                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8320
8321                 return true;
8322         }
8323
8324         /* Find an unused one (if possible) */
8325         for_each_crtc(dev, possible_crtc) {
8326                 i++;
8327                 if (!(encoder->possible_crtcs & (1 << i)))
8328                         continue;
8329                 if (!possible_crtc->enabled) {
8330                         crtc = possible_crtc;
8331                         break;
8332                 }
8333         }
8334
8335         /*
8336          * If we didn't find an unused CRTC, don't use any.
8337          */
8338         if (!crtc) {
8339                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8340                 return false;
8341         }
8342
8343         mutex_lock(&crtc->mutex);
8344         intel_encoder->new_crtc = to_intel_crtc(crtc);
8345         to_intel_connector(connector)->new_encoder = intel_encoder;
8346
8347         intel_crtc = to_intel_crtc(crtc);
8348         intel_crtc->new_enabled = true;
8349         intel_crtc->new_config = &intel_crtc->config;
8350         old->dpms_mode = connector->dpms;
8351         old->load_detect_temp = true;
8352         old->release_fb = NULL;
8353
8354         if (!mode)
8355                 mode = &load_detect_mode;
8356
8357         /* We need a framebuffer large enough to accommodate all accesses
8358          * that the plane may generate whilst we perform load detection.
8359          * We can not rely on the fbcon either being present (we get called
8360          * during its initialisation to detect all boot displays, or it may
8361          * not even exist) or that it is large enough to satisfy the
8362          * requested mode.
8363          */
8364         fb = mode_fits_in_fbdev(dev, mode);
8365         if (fb == NULL) {
8366                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8367                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8368                 old->release_fb = fb;
8369         } else
8370                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8371         if (IS_ERR(fb)) {
8372                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8373                 goto fail;
8374         }
8375
8376         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8377                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8378                 if (old->release_fb)
8379                         old->release_fb->funcs->destroy(old->release_fb);
8380                 goto fail;
8381         }
8382
8383         /* let the connector get through one full cycle before testing */
8384         intel_wait_for_vblank(dev, intel_crtc->pipe);
8385         return true;
8386
8387  fail:
8388         intel_crtc->new_enabled = crtc->enabled;
8389         if (intel_crtc->new_enabled)
8390                 intel_crtc->new_config = &intel_crtc->config;
8391         else
8392                 intel_crtc->new_config = NULL;
8393         mutex_unlock(&crtc->mutex);
8394         return false;
8395 }
8396
8397 void intel_release_load_detect_pipe(struct drm_connector *connector,
8398                                     struct intel_load_detect_pipe *old)
8399 {
8400         struct intel_encoder *intel_encoder =
8401                 intel_attached_encoder(connector);
8402         struct drm_encoder *encoder = &intel_encoder->base;
8403         struct drm_crtc *crtc = encoder->crtc;
8404         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8405
8406         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8407                       connector->base.id, drm_get_connector_name(connector),
8408                       encoder->base.id, drm_get_encoder_name(encoder));
8409
8410         if (old->load_detect_temp) {
8411                 to_intel_connector(connector)->new_encoder = NULL;
8412                 intel_encoder->new_crtc = NULL;
8413                 intel_crtc->new_enabled = false;
8414                 intel_crtc->new_config = NULL;
8415                 intel_set_mode(crtc, NULL, 0, 0, NULL);
8416
8417                 if (old->release_fb) {
8418                         drm_framebuffer_unregister_private(old->release_fb);
8419                         drm_framebuffer_unreference(old->release_fb);
8420                 }
8421
8422                 mutex_unlock(&crtc->mutex);
8423                 return;
8424         }
8425
8426         /* Switch crtc and encoder back off if necessary */
8427         if (old->dpms_mode != DRM_MODE_DPMS_ON)
8428                 connector->funcs->dpms(connector, old->dpms_mode);
8429
8430         mutex_unlock(&crtc->mutex);
8431 }
8432
8433 static int i9xx_pll_refclk(struct drm_device *dev,
8434                            const struct intel_crtc_config *pipe_config)
8435 {
8436         struct drm_i915_private *dev_priv = dev->dev_private;
8437         u32 dpll = pipe_config->dpll_hw_state.dpll;
8438
8439         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8440                 return dev_priv->vbt.lvds_ssc_freq;
8441         else if (HAS_PCH_SPLIT(dev))
8442                 return 120000;
8443         else if (!IS_GEN2(dev))
8444                 return 96000;
8445         else
8446                 return 48000;
8447 }
8448
8449 /* Returns the clock of the currently programmed mode of the given pipe. */
8450 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8451                                 struct intel_crtc_config *pipe_config)
8452 {
8453         struct drm_device *dev = crtc->base.dev;
8454         struct drm_i915_private *dev_priv = dev->dev_private;
8455         int pipe = pipe_config->cpu_transcoder;
8456         u32 dpll = pipe_config->dpll_hw_state.dpll;
8457         u32 fp;
8458         intel_clock_t clock;
8459         int refclk = i9xx_pll_refclk(dev, pipe_config);
8460
8461         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8462                 fp = pipe_config->dpll_hw_state.fp0;
8463         else
8464                 fp = pipe_config->dpll_hw_state.fp1;
8465
8466         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8467         if (IS_PINEVIEW(dev)) {
8468                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8469                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8470         } else {
8471                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8472                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8473         }
8474
8475         if (!IS_GEN2(dev)) {
8476                 if (IS_PINEVIEW(dev))
8477                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8478                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8479                 else
8480                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8481                                DPLL_FPA01_P1_POST_DIV_SHIFT);
8482
8483                 switch (dpll & DPLL_MODE_MASK) {
8484                 case DPLLB_MODE_DAC_SERIAL:
8485                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8486                                 5 : 10;
8487                         break;
8488                 case DPLLB_MODE_LVDS:
8489                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8490                                 7 : 14;
8491                         break;
8492                 default:
8493                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8494                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
8495                         return;
8496                 }
8497
8498                 if (IS_PINEVIEW(dev))
8499                         pineview_clock(refclk, &clock);
8500                 else
8501                         i9xx_clock(refclk, &clock);
8502         } else {
8503                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8504                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8505
8506                 if (is_lvds) {
8507                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8508                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
8509
8510                         if (lvds & LVDS_CLKB_POWER_UP)
8511                                 clock.p2 = 7;
8512                         else
8513                                 clock.p2 = 14;
8514                 } else {
8515                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
8516                                 clock.p1 = 2;
8517                         else {
8518                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8519                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8520                         }
8521                         if (dpll & PLL_P2_DIVIDE_BY_4)
8522                                 clock.p2 = 4;
8523                         else
8524                                 clock.p2 = 2;
8525                 }
8526
8527                 i9xx_clock(refclk, &clock);
8528         }
8529
8530         /*
8531          * This value includes pixel_multiplier. We will use
8532          * port_clock to compute adjusted_mode.crtc_clock in the
8533          * encoder's get_config() function.
8534          */
8535         pipe_config->port_clock = clock.dot;
8536 }
8537
8538 int intel_dotclock_calculate(int link_freq,
8539                              const struct intel_link_m_n *m_n)
8540 {
8541         /*
8542          * The calculation for the data clock is:
8543          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8544          * But we want to avoid losing precison if possible, so:
8545          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8546          *
8547          * and the link clock is simpler:
8548          * link_clock = (m * link_clock) / n
8549          */
8550
8551         if (!m_n->link_n)
8552                 return 0;
8553
8554         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8555 }
8556
8557 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8558                                    struct intel_crtc_config *pipe_config)
8559 {
8560         struct drm_device *dev = crtc->base.dev;
8561
8562         /* read out port_clock from the DPLL */
8563         i9xx_crtc_clock_get(crtc, pipe_config);
8564
8565         /*
8566          * This value does not include pixel_multiplier.
8567          * We will check that port_clock and adjusted_mode.crtc_clock
8568          * agree once we know their relationship in the encoder's
8569          * get_config() function.
8570          */
8571         pipe_config->adjusted_mode.crtc_clock =
8572                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8573                                          &pipe_config->fdi_m_n);
8574 }
8575
8576 /** Returns the currently programmed mode of the given pipe. */
8577 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8578                                              struct drm_crtc *crtc)
8579 {
8580         struct drm_i915_private *dev_priv = dev->dev_private;
8581         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8582         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8583         struct drm_display_mode *mode;
8584         struct intel_crtc_config pipe_config;
8585         int htot = I915_READ(HTOTAL(cpu_transcoder));
8586         int hsync = I915_READ(HSYNC(cpu_transcoder));
8587         int vtot = I915_READ(VTOTAL(cpu_transcoder));
8588         int vsync = I915_READ(VSYNC(cpu_transcoder));
8589         enum pipe pipe = intel_crtc->pipe;
8590
8591         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8592         if (!mode)
8593                 return NULL;
8594
8595         /*
8596          * Construct a pipe_config sufficient for getting the clock info
8597          * back out of crtc_clock_get.
8598          *
8599          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8600          * to use a real value here instead.
8601          */
8602         pipe_config.cpu_transcoder = (enum transcoder) pipe;
8603         pipe_config.pixel_multiplier = 1;
8604         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8605         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8606         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8607         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8608
8609         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8610         mode->hdisplay = (htot & 0xffff) + 1;
8611         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8612         mode->hsync_start = (hsync & 0xffff) + 1;
8613         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8614         mode->vdisplay = (vtot & 0xffff) + 1;
8615         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8616         mode->vsync_start = (vsync & 0xffff) + 1;
8617         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8618
8619         drm_mode_set_name(mode);
8620
8621         return mode;
8622 }
8623
8624 static void intel_increase_pllclock(struct drm_crtc *crtc)
8625 {
8626         struct drm_device *dev = crtc->dev;
8627         struct drm_i915_private *dev_priv = dev->dev_private;
8628         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8629         int pipe = intel_crtc->pipe;
8630         int dpll_reg = DPLL(pipe);
8631         int dpll;
8632
8633         if (HAS_PCH_SPLIT(dev))
8634                 return;
8635
8636         if (!dev_priv->lvds_downclock_avail)
8637                 return;
8638
8639         dpll = I915_READ(dpll_reg);
8640         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8641                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8642
8643                 assert_panel_unlocked(dev_priv, pipe);
8644
8645                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8646                 I915_WRITE(dpll_reg, dpll);
8647                 intel_wait_for_vblank(dev, pipe);
8648
8649                 dpll = I915_READ(dpll_reg);
8650                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8651                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8652         }
8653 }
8654
8655 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8656 {
8657         struct drm_device *dev = crtc->dev;
8658         struct drm_i915_private *dev_priv = dev->dev_private;
8659         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8660
8661         if (HAS_PCH_SPLIT(dev))
8662                 return;
8663
8664         if (!dev_priv->lvds_downclock_avail)
8665                 return;
8666
8667         /*
8668          * Since this is called by a timer, we should never get here in
8669          * the manual case.
8670          */
8671         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8672                 int pipe = intel_crtc->pipe;
8673                 int dpll_reg = DPLL(pipe);
8674                 int dpll;
8675
8676                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8677
8678                 assert_panel_unlocked(dev_priv, pipe);
8679
8680                 dpll = I915_READ(dpll_reg);
8681                 dpll |= DISPLAY_RATE_SELECT_FPA1;
8682                 I915_WRITE(dpll_reg, dpll);
8683                 intel_wait_for_vblank(dev, pipe);
8684                 dpll = I915_READ(dpll_reg);
8685                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8686                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8687         }
8688
8689 }
8690
8691 void intel_mark_busy(struct drm_device *dev)
8692 {
8693         struct drm_i915_private *dev_priv = dev->dev_private;
8694
8695         if (dev_priv->mm.busy)
8696                 return;
8697
8698         intel_runtime_pm_get(dev_priv);
8699         i915_update_gfx_val(dev_priv);
8700         dev_priv->mm.busy = true;
8701 }
8702
8703 void intel_mark_idle(struct drm_device *dev)
8704 {
8705         struct drm_i915_private *dev_priv = dev->dev_private;
8706         struct drm_crtc *crtc;
8707
8708         if (!dev_priv->mm.busy)
8709                 return;
8710
8711         dev_priv->mm.busy = false;
8712
8713         if (!i915.powersave)
8714                 goto out;
8715
8716         for_each_crtc(dev, crtc) {
8717                 if (!crtc->primary->fb)
8718                         continue;
8719
8720                 intel_decrease_pllclock(crtc);
8721         }
8722
8723         if (INTEL_INFO(dev)->gen >= 6)
8724                 gen6_rps_idle(dev->dev_private);
8725
8726 out:
8727         intel_runtime_pm_put(dev_priv);
8728 }
8729
8730 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
8731                         struct intel_ring_buffer *ring)
8732 {
8733         struct drm_device *dev = obj->base.dev;
8734         struct drm_crtc *crtc;
8735
8736         if (!i915.powersave)
8737                 return;
8738
8739         for_each_crtc(dev, crtc) {
8740                 if (!crtc->primary->fb)
8741                         continue;
8742
8743                 if (to_intel_framebuffer(crtc->primary->fb)->obj != obj)
8744                         continue;
8745
8746                 intel_increase_pllclock(crtc);
8747                 if (ring && intel_fbc_enabled(dev))
8748                         ring->fbc_dirty = true;
8749         }
8750 }
8751
8752 static void intel_crtc_destroy(struct drm_crtc *crtc)
8753 {
8754         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8755         struct drm_device *dev = crtc->dev;
8756         struct intel_unpin_work *work;
8757         unsigned long flags;
8758
8759         spin_lock_irqsave(&dev->event_lock, flags);
8760         work = intel_crtc->unpin_work;
8761         intel_crtc->unpin_work = NULL;
8762         spin_unlock_irqrestore(&dev->event_lock, flags);
8763
8764         if (work) {
8765                 cancel_work_sync(&work->work);
8766                 kfree(work);
8767         }
8768
8769         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
8770
8771         drm_crtc_cleanup(crtc);
8772
8773         kfree(intel_crtc);
8774 }
8775
8776 static void intel_unpin_work_fn(struct work_struct *__work)
8777 {
8778         struct intel_unpin_work *work =
8779                 container_of(__work, struct intel_unpin_work, work);
8780         struct drm_device *dev = work->crtc->dev;
8781
8782         mutex_lock(&dev->struct_mutex);
8783         intel_unpin_fb_obj(work->old_fb_obj);
8784         drm_gem_object_unreference(&work->pending_flip_obj->base);
8785         drm_gem_object_unreference(&work->old_fb_obj->base);
8786
8787         intel_update_fbc(dev);
8788         mutex_unlock(&dev->struct_mutex);
8789
8790         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8791         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8792
8793         kfree(work);
8794 }
8795
8796 static void do_intel_finish_page_flip(struct drm_device *dev,
8797                                       struct drm_crtc *crtc)
8798 {
8799         struct drm_i915_private *dev_priv = dev->dev_private;
8800         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8801         struct intel_unpin_work *work;
8802         unsigned long flags;
8803
8804         /* Ignore early vblank irqs */
8805         if (intel_crtc == NULL)
8806                 return;
8807
8808         spin_lock_irqsave(&dev->event_lock, flags);
8809         work = intel_crtc->unpin_work;
8810
8811         /* Ensure we don't miss a work->pending update ... */
8812         smp_rmb();
8813
8814         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8815                 spin_unlock_irqrestore(&dev->event_lock, flags);
8816                 return;
8817         }
8818
8819         /* and that the unpin work is consistent wrt ->pending. */
8820         smp_rmb();
8821
8822         intel_crtc->unpin_work = NULL;
8823
8824         if (work->event)
8825                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
8826
8827         drm_vblank_put(dev, intel_crtc->pipe);
8828
8829         spin_unlock_irqrestore(&dev->event_lock, flags);
8830
8831         wake_up_all(&dev_priv->pending_flip_queue);
8832
8833         queue_work(dev_priv->wq, &work->work);
8834
8835         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
8836 }
8837
8838 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8839 {
8840         struct drm_i915_private *dev_priv = dev->dev_private;
8841         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8842
8843         do_intel_finish_page_flip(dev, crtc);
8844 }
8845
8846 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8847 {
8848         struct drm_i915_private *dev_priv = dev->dev_private;
8849         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8850
8851         do_intel_finish_page_flip(dev, crtc);
8852 }
8853
8854 void intel_prepare_page_flip(struct drm_device *dev, int plane)
8855 {
8856         struct drm_i915_private *dev_priv = dev->dev_private;
8857         struct intel_crtc *intel_crtc =
8858                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8859         unsigned long flags;
8860
8861         /* NB: An MMIO update of the plane base pointer will also
8862          * generate a page-flip completion irq, i.e. every modeset
8863          * is also accompanied by a spurious intel_prepare_page_flip().
8864          */
8865         spin_lock_irqsave(&dev->event_lock, flags);
8866         if (intel_crtc->unpin_work)
8867                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
8868         spin_unlock_irqrestore(&dev->event_lock, flags);
8869 }
8870
8871 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8872 {
8873         /* Ensure that the work item is consistent when activating it ... */
8874         smp_wmb();
8875         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8876         /* and that it is marked active as soon as the irq could fire. */
8877         smp_wmb();
8878 }
8879
8880 static int intel_gen2_queue_flip(struct drm_device *dev,
8881                                  struct drm_crtc *crtc,
8882                                  struct drm_framebuffer *fb,
8883                                  struct drm_i915_gem_object *obj,
8884                                  uint32_t flags)
8885 {
8886         struct drm_i915_private *dev_priv = dev->dev_private;
8887         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8888         u32 flip_mask;
8889         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8890         int ret;
8891
8892         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8893         if (ret)
8894                 goto err;
8895
8896         ret = intel_ring_begin(ring, 6);
8897         if (ret)
8898                 goto err_unpin;
8899
8900         /* Can't queue multiple flips, so wait for the previous
8901          * one to finish before executing the next.
8902          */
8903         if (intel_crtc->plane)
8904                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8905         else
8906                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8907         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8908         intel_ring_emit(ring, MI_NOOP);
8909         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8910                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8911         intel_ring_emit(ring, fb->pitches[0]);
8912         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8913         intel_ring_emit(ring, 0); /* aux display base address, unused */
8914
8915         intel_mark_page_flip_active(intel_crtc);
8916         __intel_ring_advance(ring);
8917         return 0;
8918
8919 err_unpin:
8920         intel_unpin_fb_obj(obj);
8921 err:
8922         return ret;
8923 }
8924
8925 static int intel_gen3_queue_flip(struct drm_device *dev,
8926                                  struct drm_crtc *crtc,
8927                                  struct drm_framebuffer *fb,
8928                                  struct drm_i915_gem_object *obj,
8929                                  uint32_t flags)
8930 {
8931         struct drm_i915_private *dev_priv = dev->dev_private;
8932         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8933         u32 flip_mask;
8934         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8935         int ret;
8936
8937         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8938         if (ret)
8939                 goto err;
8940
8941         ret = intel_ring_begin(ring, 6);
8942         if (ret)
8943                 goto err_unpin;
8944
8945         if (intel_crtc->plane)
8946                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8947         else
8948                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8949         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8950         intel_ring_emit(ring, MI_NOOP);
8951         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8952                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8953         intel_ring_emit(ring, fb->pitches[0]);
8954         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8955         intel_ring_emit(ring, MI_NOOP);
8956
8957         intel_mark_page_flip_active(intel_crtc);
8958         __intel_ring_advance(ring);
8959         return 0;
8960
8961 err_unpin:
8962         intel_unpin_fb_obj(obj);
8963 err:
8964         return ret;
8965 }
8966
8967 static int intel_gen4_queue_flip(struct drm_device *dev,
8968                                  struct drm_crtc *crtc,
8969                                  struct drm_framebuffer *fb,
8970                                  struct drm_i915_gem_object *obj,
8971                                  uint32_t flags)
8972 {
8973         struct drm_i915_private *dev_priv = dev->dev_private;
8974         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8975         uint32_t pf, pipesrc;
8976         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8977         int ret;
8978
8979         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8980         if (ret)
8981                 goto err;
8982
8983         ret = intel_ring_begin(ring, 4);
8984         if (ret)
8985                 goto err_unpin;
8986
8987         /* i965+ uses the linear or tiled offsets from the
8988          * Display Registers (which do not change across a page-flip)
8989          * so we need only reprogram the base address.
8990          */
8991         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8992                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8993         intel_ring_emit(ring, fb->pitches[0]);
8994         intel_ring_emit(ring,
8995                         (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
8996                         obj->tiling_mode);
8997
8998         /* XXX Enabling the panel-fitter across page-flip is so far
8999          * untested on non-native modes, so ignore it for now.
9000          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9001          */
9002         pf = 0;
9003         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9004         intel_ring_emit(ring, pf | pipesrc);
9005
9006         intel_mark_page_flip_active(intel_crtc);
9007         __intel_ring_advance(ring);
9008         return 0;
9009
9010 err_unpin:
9011         intel_unpin_fb_obj(obj);
9012 err:
9013         return ret;
9014 }
9015
9016 static int intel_gen6_queue_flip(struct drm_device *dev,
9017                                  struct drm_crtc *crtc,
9018                                  struct drm_framebuffer *fb,
9019                                  struct drm_i915_gem_object *obj,
9020                                  uint32_t flags)
9021 {
9022         struct drm_i915_private *dev_priv = dev->dev_private;
9023         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9024         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
9025         uint32_t pf, pipesrc;
9026         int ret;
9027
9028         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9029         if (ret)
9030                 goto err;
9031
9032         ret = intel_ring_begin(ring, 4);
9033         if (ret)
9034                 goto err_unpin;
9035
9036         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9037                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9038         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9039         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
9040
9041         /* Contrary to the suggestions in the documentation,
9042          * "Enable Panel Fitter" does not seem to be required when page
9043          * flipping with a non-native mode, and worse causes a normal
9044          * modeset to fail.
9045          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9046          */
9047         pf = 0;
9048         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9049         intel_ring_emit(ring, pf | pipesrc);
9050
9051         intel_mark_page_flip_active(intel_crtc);
9052         __intel_ring_advance(ring);
9053         return 0;
9054
9055 err_unpin:
9056         intel_unpin_fb_obj(obj);
9057 err:
9058         return ret;
9059 }
9060
9061 static int intel_gen7_queue_flip(struct drm_device *dev,
9062                                  struct drm_crtc *crtc,
9063                                  struct drm_framebuffer *fb,
9064                                  struct drm_i915_gem_object *obj,
9065                                  uint32_t flags)
9066 {
9067         struct drm_i915_private *dev_priv = dev->dev_private;
9068         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9069         struct intel_ring_buffer *ring;
9070         uint32_t plane_bit = 0;
9071         int len, ret;
9072
9073         ring = obj->ring;
9074         if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
9075                 ring = &dev_priv->ring[BCS];
9076
9077         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9078         if (ret)
9079                 goto err;
9080
9081         switch (intel_crtc->plane) {
9082         case PLANE_A:
9083                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9084                 break;
9085         case PLANE_B:
9086                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9087                 break;
9088         case PLANE_C:
9089                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9090                 break;
9091         default:
9092                 WARN_ONCE(1, "unknown plane in flip command\n");
9093                 ret = -ENODEV;
9094                 goto err_unpin;
9095         }
9096
9097         len = 4;
9098         if (ring->id == RCS) {
9099                 len += 6;
9100                 /*
9101                  * On Gen 8, SRM is now taking an extra dword to accommodate
9102                  * 48bits addresses, and we need a NOOP for the batch size to
9103                  * stay even.
9104                  */
9105                 if (IS_GEN8(dev))
9106                         len += 2;
9107         }
9108
9109         /*
9110          * BSpec MI_DISPLAY_FLIP for IVB:
9111          * "The full packet must be contained within the same cache line."
9112          *
9113          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9114          * cacheline, if we ever start emitting more commands before
9115          * the MI_DISPLAY_FLIP we may need to first emit everything else,
9116          * then do the cacheline alignment, and finally emit the
9117          * MI_DISPLAY_FLIP.
9118          */
9119         ret = intel_ring_cacheline_align(ring);
9120         if (ret)
9121                 goto err_unpin;
9122
9123         ret = intel_ring_begin(ring, len);
9124         if (ret)
9125                 goto err_unpin;
9126
9127         /* Unmask the flip-done completion message. Note that the bspec says that
9128          * we should do this for both the BCS and RCS, and that we must not unmask
9129          * more than one flip event at any time (or ensure that one flip message
9130          * can be sent by waiting for flip-done prior to queueing new flips).
9131          * Experimentation says that BCS works despite DERRMR masking all
9132          * flip-done completion events and that unmasking all planes at once
9133          * for the RCS also doesn't appear to drop events. Setting the DERRMR
9134          * to zero does lead to lockups within MI_DISPLAY_FLIP.
9135          */
9136         if (ring->id == RCS) {
9137                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9138                 intel_ring_emit(ring, DERRMR);
9139                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9140                                         DERRMR_PIPEB_PRI_FLIP_DONE |
9141                                         DERRMR_PIPEC_PRI_FLIP_DONE));
9142                 if (IS_GEN8(dev))
9143                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9144                                               MI_SRM_LRM_GLOBAL_GTT);
9145                 else
9146                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9147                                               MI_SRM_LRM_GLOBAL_GTT);
9148                 intel_ring_emit(ring, DERRMR);
9149                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9150                 if (IS_GEN8(dev)) {
9151                         intel_ring_emit(ring, 0);
9152                         intel_ring_emit(ring, MI_NOOP);
9153                 }
9154         }
9155
9156         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9157         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9158         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
9159         intel_ring_emit(ring, (MI_NOOP));
9160
9161         intel_mark_page_flip_active(intel_crtc);
9162         __intel_ring_advance(ring);
9163         return 0;
9164
9165 err_unpin:
9166         intel_unpin_fb_obj(obj);
9167 err:
9168         return ret;
9169 }
9170
9171 static int intel_default_queue_flip(struct drm_device *dev,
9172                                     struct drm_crtc *crtc,
9173                                     struct drm_framebuffer *fb,
9174                                     struct drm_i915_gem_object *obj,
9175                                     uint32_t flags)
9176 {
9177         return -ENODEV;
9178 }
9179
9180 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9181                                 struct drm_framebuffer *fb,
9182                                 struct drm_pending_vblank_event *event,
9183                                 uint32_t page_flip_flags)
9184 {
9185         struct drm_device *dev = crtc->dev;
9186         struct drm_i915_private *dev_priv = dev->dev_private;
9187         struct drm_framebuffer *old_fb = crtc->primary->fb;
9188         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
9189         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9190         struct intel_unpin_work *work;
9191         unsigned long flags;
9192         int ret;
9193
9194         /* Can't change pixel format via MI display flips. */
9195         if (fb->pixel_format != crtc->primary->fb->pixel_format)
9196                 return -EINVAL;
9197
9198         /*
9199          * TILEOFF/LINOFF registers can't be changed via MI display flips.
9200          * Note that pitch changes could also affect these register.
9201          */
9202         if (INTEL_INFO(dev)->gen > 3 &&
9203             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9204              fb->pitches[0] != crtc->primary->fb->pitches[0]))
9205                 return -EINVAL;
9206
9207         if (i915_terminally_wedged(&dev_priv->gpu_error))
9208                 goto out_hang;
9209
9210         work = kzalloc(sizeof(*work), GFP_KERNEL);
9211         if (work == NULL)
9212                 return -ENOMEM;
9213
9214         work->event = event;
9215         work->crtc = crtc;
9216         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
9217         INIT_WORK(&work->work, intel_unpin_work_fn);
9218
9219         ret = drm_vblank_get(dev, intel_crtc->pipe);
9220         if (ret)
9221                 goto free_work;
9222
9223         /* We borrow the event spin lock for protecting unpin_work */
9224         spin_lock_irqsave(&dev->event_lock, flags);
9225         if (intel_crtc->unpin_work) {
9226                 spin_unlock_irqrestore(&dev->event_lock, flags);
9227                 kfree(work);
9228                 drm_vblank_put(dev, intel_crtc->pipe);
9229
9230                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9231                 return -EBUSY;
9232         }
9233         intel_crtc->unpin_work = work;
9234         spin_unlock_irqrestore(&dev->event_lock, flags);
9235
9236         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9237                 flush_workqueue(dev_priv->wq);
9238
9239         ret = i915_mutex_lock_interruptible(dev);
9240         if (ret)
9241                 goto cleanup;
9242
9243         /* Reference the objects for the scheduled work. */
9244         drm_gem_object_reference(&work->old_fb_obj->base);
9245         drm_gem_object_reference(&obj->base);
9246
9247         crtc->primary->fb = fb;
9248
9249         work->pending_flip_obj = obj;
9250
9251         work->enable_stall_check = true;
9252
9253         atomic_inc(&intel_crtc->unpin_work_count);
9254         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9255
9256         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
9257         if (ret)
9258                 goto cleanup_pending;
9259
9260         intel_disable_fbc(dev);
9261         intel_mark_fb_busy(obj, NULL);
9262         mutex_unlock(&dev->struct_mutex);
9263
9264         trace_i915_flip_request(intel_crtc->plane, obj);
9265
9266         return 0;
9267
9268 cleanup_pending:
9269         atomic_dec(&intel_crtc->unpin_work_count);
9270         crtc->primary->fb = old_fb;
9271         drm_gem_object_unreference(&work->old_fb_obj->base);
9272         drm_gem_object_unreference(&obj->base);
9273         mutex_unlock(&dev->struct_mutex);
9274
9275 cleanup:
9276         spin_lock_irqsave(&dev->event_lock, flags);
9277         intel_crtc->unpin_work = NULL;
9278         spin_unlock_irqrestore(&dev->event_lock, flags);
9279
9280         drm_vblank_put(dev, intel_crtc->pipe);
9281 free_work:
9282         kfree(work);
9283
9284         if (ret == -EIO) {
9285 out_hang:
9286                 intel_crtc_wait_for_pending_flips(crtc);
9287                 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9288                 if (ret == 0 && event)
9289                         drm_send_vblank_event(dev, intel_crtc->pipe, event);
9290         }
9291         return ret;
9292 }
9293
9294 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9295         .mode_set_base_atomic = intel_pipe_set_base_atomic,
9296         .load_lut = intel_crtc_load_lut,
9297 };
9298
9299 /**
9300  * intel_modeset_update_staged_output_state
9301  *
9302  * Updates the staged output configuration state, e.g. after we've read out the
9303  * current hw state.
9304  */
9305 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9306 {
9307         struct intel_crtc *crtc;
9308         struct intel_encoder *encoder;
9309         struct intel_connector *connector;
9310
9311         list_for_each_entry(connector, &dev->mode_config.connector_list,
9312                             base.head) {
9313                 connector->new_encoder =
9314                         to_intel_encoder(connector->base.encoder);
9315         }
9316
9317         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9318                             base.head) {
9319                 encoder->new_crtc =
9320                         to_intel_crtc(encoder->base.crtc);
9321         }
9322
9323         for_each_intel_crtc(dev, crtc) {
9324                 crtc->new_enabled = crtc->base.enabled;
9325
9326                 if (crtc->new_enabled)
9327                         crtc->new_config = &crtc->config;
9328                 else
9329                         crtc->new_config = NULL;
9330         }
9331 }
9332
9333 /**
9334  * intel_modeset_commit_output_state
9335  *
9336  * This function copies the stage display pipe configuration to the real one.
9337  */
9338 static void intel_modeset_commit_output_state(struct drm_device *dev)
9339 {
9340         struct intel_crtc *crtc;
9341         struct intel_encoder *encoder;
9342         struct intel_connector *connector;
9343
9344         list_for_each_entry(connector, &dev->mode_config.connector_list,
9345                             base.head) {
9346                 connector->base.encoder = &connector->new_encoder->base;
9347         }
9348
9349         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9350                             base.head) {
9351                 encoder->base.crtc = &encoder->new_crtc->base;
9352         }
9353
9354         for_each_intel_crtc(dev, crtc) {
9355                 crtc->base.enabled = crtc->new_enabled;
9356         }
9357 }
9358
9359 static void
9360 connected_sink_compute_bpp(struct intel_connector *connector,
9361                            struct intel_crtc_config *pipe_config)
9362 {
9363         int bpp = pipe_config->pipe_bpp;
9364
9365         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9366                 connector->base.base.id,
9367                 drm_get_connector_name(&connector->base));
9368
9369         /* Don't use an invalid EDID bpc value */
9370         if (connector->base.display_info.bpc &&
9371             connector->base.display_info.bpc * 3 < bpp) {
9372                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9373                               bpp, connector->base.display_info.bpc*3);
9374                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9375         }
9376
9377         /* Clamp bpp to 8 on screens without EDID 1.4 */
9378         if (connector->base.display_info.bpc == 0 && bpp > 24) {
9379                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9380                               bpp);
9381                 pipe_config->pipe_bpp = 24;
9382         }
9383 }
9384
9385 static int
9386 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9387                           struct drm_framebuffer *fb,
9388                           struct intel_crtc_config *pipe_config)
9389 {
9390         struct drm_device *dev = crtc->base.dev;
9391         struct intel_connector *connector;
9392         int bpp;
9393
9394         switch (fb->pixel_format) {
9395         case DRM_FORMAT_C8:
9396                 bpp = 8*3; /* since we go through a colormap */
9397                 break;
9398         case DRM_FORMAT_XRGB1555:
9399         case DRM_FORMAT_ARGB1555:
9400                 /* checked in intel_framebuffer_init already */
9401                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9402                         return -EINVAL;
9403         case DRM_FORMAT_RGB565:
9404                 bpp = 6*3; /* min is 18bpp */
9405                 break;
9406         case DRM_FORMAT_XBGR8888:
9407         case DRM_FORMAT_ABGR8888:
9408                 /* checked in intel_framebuffer_init already */
9409                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9410                         return -EINVAL;
9411         case DRM_FORMAT_XRGB8888:
9412         case DRM_FORMAT_ARGB8888:
9413                 bpp = 8*3;
9414                 break;
9415         case DRM_FORMAT_XRGB2101010:
9416         case DRM_FORMAT_ARGB2101010:
9417         case DRM_FORMAT_XBGR2101010:
9418         case DRM_FORMAT_ABGR2101010:
9419                 /* checked in intel_framebuffer_init already */
9420                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9421                         return -EINVAL;
9422                 bpp = 10*3;
9423                 break;
9424         /* TODO: gen4+ supports 16 bpc floating point, too. */
9425         default:
9426                 DRM_DEBUG_KMS("unsupported depth\n");
9427                 return -EINVAL;
9428         }
9429
9430         pipe_config->pipe_bpp = bpp;
9431
9432         /* Clamp display bpp to EDID value */
9433         list_for_each_entry(connector, &dev->mode_config.connector_list,
9434                             base.head) {
9435                 if (!connector->new_encoder ||
9436                     connector->new_encoder->new_crtc != crtc)
9437                         continue;
9438
9439                 connected_sink_compute_bpp(connector, pipe_config);
9440         }
9441
9442         return bpp;
9443 }
9444
9445 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9446 {
9447         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9448                         "type: 0x%x flags: 0x%x\n",
9449                 mode->crtc_clock,
9450                 mode->crtc_hdisplay, mode->crtc_hsync_start,
9451                 mode->crtc_hsync_end, mode->crtc_htotal,
9452                 mode->crtc_vdisplay, mode->crtc_vsync_start,
9453                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9454 }
9455
9456 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9457                                    struct intel_crtc_config *pipe_config,
9458                                    const char *context)
9459 {
9460         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9461                       context, pipe_name(crtc->pipe));
9462
9463         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9464         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9465                       pipe_config->pipe_bpp, pipe_config->dither);
9466         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9467                       pipe_config->has_pch_encoder,
9468                       pipe_config->fdi_lanes,
9469                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9470                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9471                       pipe_config->fdi_m_n.tu);
9472         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9473                       pipe_config->has_dp_encoder,
9474                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9475                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9476                       pipe_config->dp_m_n.tu);
9477         DRM_DEBUG_KMS("requested mode:\n");
9478         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9479         DRM_DEBUG_KMS("adjusted mode:\n");
9480         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9481         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9482         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9483         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9484                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9485         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9486                       pipe_config->gmch_pfit.control,
9487                       pipe_config->gmch_pfit.pgm_ratios,
9488                       pipe_config->gmch_pfit.lvds_border_bits);
9489         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9490                       pipe_config->pch_pfit.pos,
9491                       pipe_config->pch_pfit.size,
9492                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9493         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9494         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
9495 }
9496
9497 static bool encoders_cloneable(const struct intel_encoder *a,
9498                                const struct intel_encoder *b)
9499 {
9500         /* masks could be asymmetric, so check both ways */
9501         return a == b || (a->cloneable & (1 << b->type) &&
9502                           b->cloneable & (1 << a->type));
9503 }
9504
9505 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9506                                          struct intel_encoder *encoder)
9507 {
9508         struct drm_device *dev = crtc->base.dev;
9509         struct intel_encoder *source_encoder;
9510
9511         list_for_each_entry(source_encoder,
9512                             &dev->mode_config.encoder_list, base.head) {
9513                 if (source_encoder->new_crtc != crtc)
9514                         continue;
9515
9516                 if (!encoders_cloneable(encoder, source_encoder))
9517                         return false;
9518         }
9519
9520         return true;
9521 }
9522
9523 static bool check_encoder_cloning(struct intel_crtc *crtc)
9524 {
9525         struct drm_device *dev = crtc->base.dev;
9526         struct intel_encoder *encoder;
9527
9528         list_for_each_entry(encoder,
9529                             &dev->mode_config.encoder_list, base.head) {
9530                 if (encoder->new_crtc != crtc)
9531                         continue;
9532
9533                 if (!check_single_encoder_cloning(crtc, encoder))
9534                         return false;
9535         }
9536
9537         return true;
9538 }
9539
9540 static struct intel_crtc_config *
9541 intel_modeset_pipe_config(struct drm_crtc *crtc,
9542                           struct drm_framebuffer *fb,
9543                           struct drm_display_mode *mode)
9544 {
9545         struct drm_device *dev = crtc->dev;
9546         struct intel_encoder *encoder;
9547         struct intel_crtc_config *pipe_config;
9548         int plane_bpp, ret = -EINVAL;
9549         bool retry = true;
9550
9551         if (!check_encoder_cloning(to_intel_crtc(crtc))) {
9552                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
9553                 return ERR_PTR(-EINVAL);
9554         }
9555
9556         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9557         if (!pipe_config)
9558                 return ERR_PTR(-ENOMEM);
9559
9560         drm_mode_copy(&pipe_config->adjusted_mode, mode);
9561         drm_mode_copy(&pipe_config->requested_mode, mode);
9562
9563         pipe_config->cpu_transcoder =
9564                 (enum transcoder) to_intel_crtc(crtc)->pipe;
9565         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9566
9567         /*
9568          * Sanitize sync polarity flags based on requested ones. If neither
9569          * positive or negative polarity is requested, treat this as meaning
9570          * negative polarity.
9571          */
9572         if (!(pipe_config->adjusted_mode.flags &
9573               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
9574                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
9575
9576         if (!(pipe_config->adjusted_mode.flags &
9577               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
9578                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
9579
9580         /* Compute a starting value for pipe_config->pipe_bpp taking the source
9581          * plane pixel format and any sink constraints into account. Returns the
9582          * source plane bpp so that dithering can be selected on mismatches
9583          * after encoders and crtc also have had their say. */
9584         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
9585                                               fb, pipe_config);
9586         if (plane_bpp < 0)
9587                 goto fail;
9588
9589         /*
9590          * Determine the real pipe dimensions. Note that stereo modes can
9591          * increase the actual pipe size due to the frame doubling and
9592          * insertion of additional space for blanks between the frame. This
9593          * is stored in the crtc timings. We use the requested mode to do this
9594          * computation to clearly distinguish it from the adjusted mode, which
9595          * can be changed by the connectors in the below retry loop.
9596          */
9597         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
9598         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
9599         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
9600
9601 encoder_retry:
9602         /* Ensure the port clock defaults are reset when retrying. */
9603         pipe_config->port_clock = 0;
9604         pipe_config->pixel_multiplier = 1;
9605
9606         /* Fill in default crtc timings, allow encoders to overwrite them. */
9607         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
9608
9609         /* Pass our mode to the connectors and the CRTC to give them a chance to
9610          * adjust it according to limitations or connector properties, and also
9611          * a chance to reject the mode entirely.
9612          */
9613         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9614                             base.head) {
9615
9616                 if (&encoder->new_crtc->base != crtc)
9617                         continue;
9618
9619                 if (!(encoder->compute_config(encoder, pipe_config))) {
9620                         DRM_DEBUG_KMS("Encoder config failure\n");
9621                         goto fail;
9622                 }
9623         }
9624
9625         /* Set default port clock if not overwritten by the encoder. Needs to be
9626          * done afterwards in case the encoder adjusts the mode. */
9627         if (!pipe_config->port_clock)
9628                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
9629                         * pipe_config->pixel_multiplier;
9630
9631         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
9632         if (ret < 0) {
9633                 DRM_DEBUG_KMS("CRTC fixup failed\n");
9634                 goto fail;
9635         }
9636
9637         if (ret == RETRY) {
9638                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
9639                         ret = -EINVAL;
9640                         goto fail;
9641                 }
9642
9643                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9644                 retry = false;
9645                 goto encoder_retry;
9646         }
9647
9648         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
9649         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9650                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
9651
9652         return pipe_config;
9653 fail:
9654         kfree(pipe_config);
9655         return ERR_PTR(ret);
9656 }
9657
9658 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
9659  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9660 static void
9661 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
9662                              unsigned *prepare_pipes, unsigned *disable_pipes)
9663 {
9664         struct intel_crtc *intel_crtc;
9665         struct drm_device *dev = crtc->dev;
9666         struct intel_encoder *encoder;
9667         struct intel_connector *connector;
9668         struct drm_crtc *tmp_crtc;
9669
9670         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
9671
9672         /* Check which crtcs have changed outputs connected to them, these need
9673          * to be part of the prepare_pipes mask. We don't (yet) support global
9674          * modeset across multiple crtcs, so modeset_pipes will only have one
9675          * bit set at most. */
9676         list_for_each_entry(connector, &dev->mode_config.connector_list,
9677                             base.head) {
9678                 if (connector->base.encoder == &connector->new_encoder->base)
9679                         continue;
9680
9681                 if (connector->base.encoder) {
9682                         tmp_crtc = connector->base.encoder->crtc;
9683
9684                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9685                 }
9686
9687                 if (connector->new_encoder)
9688                         *prepare_pipes |=
9689                                 1 << connector->new_encoder->new_crtc->pipe;
9690         }
9691
9692         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9693                             base.head) {
9694                 if (encoder->base.crtc == &encoder->new_crtc->base)
9695                         continue;
9696
9697                 if (encoder->base.crtc) {
9698                         tmp_crtc = encoder->base.crtc;
9699
9700                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9701                 }
9702
9703                 if (encoder->new_crtc)
9704                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
9705         }
9706
9707         /* Check for pipes that will be enabled/disabled ... */
9708         for_each_intel_crtc(dev, intel_crtc) {
9709                 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
9710                         continue;
9711
9712                 if (!intel_crtc->new_enabled)
9713                         *disable_pipes |= 1 << intel_crtc->pipe;
9714                 else
9715                         *prepare_pipes |= 1 << intel_crtc->pipe;
9716         }
9717
9718
9719         /* set_mode is also used to update properties on life display pipes. */
9720         intel_crtc = to_intel_crtc(crtc);
9721         if (intel_crtc->new_enabled)
9722                 *prepare_pipes |= 1 << intel_crtc->pipe;
9723
9724         /*
9725          * For simplicity do a full modeset on any pipe where the output routing
9726          * changed. We could be more clever, but that would require us to be
9727          * more careful with calling the relevant encoder->mode_set functions.
9728          */
9729         if (*prepare_pipes)
9730                 *modeset_pipes = *prepare_pipes;
9731
9732         /* ... and mask these out. */
9733         *modeset_pipes &= ~(*disable_pipes);
9734         *prepare_pipes &= ~(*disable_pipes);
9735
9736         /*
9737          * HACK: We don't (yet) fully support global modesets. intel_set_config
9738          * obies this rule, but the modeset restore mode of
9739          * intel_modeset_setup_hw_state does not.
9740          */
9741         *modeset_pipes &= 1 << intel_crtc->pipe;
9742         *prepare_pipes &= 1 << intel_crtc->pipe;
9743
9744         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9745                       *modeset_pipes, *prepare_pipes, *disable_pipes);
9746 }
9747
9748 static bool intel_crtc_in_use(struct drm_crtc *crtc)
9749 {
9750         struct drm_encoder *encoder;
9751         struct drm_device *dev = crtc->dev;
9752
9753         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
9754                 if (encoder->crtc == crtc)
9755                         return true;
9756
9757         return false;
9758 }
9759
9760 static void
9761 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
9762 {
9763         struct intel_encoder *intel_encoder;
9764         struct intel_crtc *intel_crtc;
9765         struct drm_connector *connector;
9766
9767         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
9768                             base.head) {
9769                 if (!intel_encoder->base.crtc)
9770                         continue;
9771
9772                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
9773
9774                 if (prepare_pipes & (1 << intel_crtc->pipe))
9775                         intel_encoder->connectors_active = false;
9776         }
9777
9778         intel_modeset_commit_output_state(dev);
9779
9780         /* Double check state. */
9781         for_each_intel_crtc(dev, intel_crtc) {
9782                 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
9783                 WARN_ON(intel_crtc->new_config &&
9784                         intel_crtc->new_config != &intel_crtc->config);
9785                 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
9786         }
9787
9788         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9789                 if (!connector->encoder || !connector->encoder->crtc)
9790                         continue;
9791
9792                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
9793
9794                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
9795                         struct drm_property *dpms_property =
9796                                 dev->mode_config.dpms_property;
9797
9798                         connector->dpms = DRM_MODE_DPMS_ON;
9799                         drm_object_property_set_value(&connector->base,
9800                                                          dpms_property,
9801                                                          DRM_MODE_DPMS_ON);
9802
9803                         intel_encoder = to_intel_encoder(connector->encoder);
9804                         intel_encoder->connectors_active = true;
9805                 }
9806         }
9807
9808 }
9809
9810 static bool intel_fuzzy_clock_check(int clock1, int clock2)
9811 {
9812         int diff;
9813
9814         if (clock1 == clock2)
9815                 return true;
9816
9817         if (!clock1 || !clock2)
9818                 return false;
9819
9820         diff = abs(clock1 - clock2);
9821
9822         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
9823                 return true;
9824
9825         return false;
9826 }
9827
9828 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9829         list_for_each_entry((intel_crtc), \
9830                             &(dev)->mode_config.crtc_list, \
9831                             base.head) \
9832                 if (mask & (1 <<(intel_crtc)->pipe))
9833
9834 static bool
9835 intel_pipe_config_compare(struct drm_device *dev,
9836                           struct intel_crtc_config *current_config,
9837                           struct intel_crtc_config *pipe_config)
9838 {
9839 #define PIPE_CONF_CHECK_X(name) \
9840         if (current_config->name != pipe_config->name) { \
9841                 DRM_ERROR("mismatch in " #name " " \
9842                           "(expected 0x%08x, found 0x%08x)\n", \
9843                           current_config->name, \
9844                           pipe_config->name); \
9845                 return false; \
9846         }
9847
9848 #define PIPE_CONF_CHECK_I(name) \
9849         if (current_config->name != pipe_config->name) { \
9850                 DRM_ERROR("mismatch in " #name " " \
9851                           "(expected %i, found %i)\n", \
9852                           current_config->name, \
9853                           pipe_config->name); \
9854                 return false; \
9855         }
9856
9857 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
9858         if ((current_config->name ^ pipe_config->name) & (mask)) { \
9859                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
9860                           "(expected %i, found %i)\n", \
9861                           current_config->name & (mask), \
9862                           pipe_config->name & (mask)); \
9863                 return false; \
9864         }
9865
9866 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9867         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9868                 DRM_ERROR("mismatch in " #name " " \
9869                           "(expected %i, found %i)\n", \
9870                           current_config->name, \
9871                           pipe_config->name); \
9872                 return false; \
9873         }
9874
9875 #define PIPE_CONF_QUIRK(quirk)  \
9876         ((current_config->quirks | pipe_config->quirks) & (quirk))
9877
9878         PIPE_CONF_CHECK_I(cpu_transcoder);
9879
9880         PIPE_CONF_CHECK_I(has_pch_encoder);
9881         PIPE_CONF_CHECK_I(fdi_lanes);
9882         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9883         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9884         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9885         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9886         PIPE_CONF_CHECK_I(fdi_m_n.tu);
9887
9888         PIPE_CONF_CHECK_I(has_dp_encoder);
9889         PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9890         PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9891         PIPE_CONF_CHECK_I(dp_m_n.link_m);
9892         PIPE_CONF_CHECK_I(dp_m_n.link_n);
9893         PIPE_CONF_CHECK_I(dp_m_n.tu);
9894
9895         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9896         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9897         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9898         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9899         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9900         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9901
9902         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9903         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9904         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9905         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9906         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9907         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9908
9909         PIPE_CONF_CHECK_I(pixel_multiplier);
9910         PIPE_CONF_CHECK_I(has_hdmi_sink);
9911         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
9912             IS_VALLEYVIEW(dev))
9913                 PIPE_CONF_CHECK_I(limited_color_range);
9914
9915         PIPE_CONF_CHECK_I(has_audio);
9916
9917         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9918                               DRM_MODE_FLAG_INTERLACE);
9919
9920         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9921                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9922                                       DRM_MODE_FLAG_PHSYNC);
9923                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9924                                       DRM_MODE_FLAG_NHSYNC);
9925                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9926                                       DRM_MODE_FLAG_PVSYNC);
9927                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9928                                       DRM_MODE_FLAG_NVSYNC);
9929         }
9930
9931         PIPE_CONF_CHECK_I(pipe_src_w);
9932         PIPE_CONF_CHECK_I(pipe_src_h);
9933
9934         /*
9935          * FIXME: BIOS likes to set up a cloned config with lvds+external
9936          * screen. Since we don't yet re-compute the pipe config when moving
9937          * just the lvds port away to another pipe the sw tracking won't match.
9938          *
9939          * Proper atomic modesets with recomputed global state will fix this.
9940          * Until then just don't check gmch state for inherited modes.
9941          */
9942         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
9943                 PIPE_CONF_CHECK_I(gmch_pfit.control);
9944                 /* pfit ratios are autocomputed by the hw on gen4+ */
9945                 if (INTEL_INFO(dev)->gen < 4)
9946                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9947                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9948         }
9949
9950         PIPE_CONF_CHECK_I(pch_pfit.enabled);
9951         if (current_config->pch_pfit.enabled) {
9952                 PIPE_CONF_CHECK_I(pch_pfit.pos);
9953                 PIPE_CONF_CHECK_I(pch_pfit.size);
9954         }
9955
9956         /* BDW+ don't expose a synchronous way to read the state */
9957         if (IS_HASWELL(dev))
9958                 PIPE_CONF_CHECK_I(ips_enabled);
9959
9960         PIPE_CONF_CHECK_I(double_wide);
9961
9962         PIPE_CONF_CHECK_I(shared_dpll);
9963         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
9964         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
9965         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
9966         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
9967
9968         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
9969                 PIPE_CONF_CHECK_I(pipe_bpp);
9970
9971         PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
9972         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
9973
9974 #undef PIPE_CONF_CHECK_X
9975 #undef PIPE_CONF_CHECK_I
9976 #undef PIPE_CONF_CHECK_FLAGS
9977 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
9978 #undef PIPE_CONF_QUIRK
9979
9980         return true;
9981 }
9982
9983 static void
9984 check_connector_state(struct drm_device *dev)
9985 {
9986         struct intel_connector *connector;
9987
9988         list_for_each_entry(connector, &dev->mode_config.connector_list,
9989                             base.head) {
9990                 /* This also checks the encoder/connector hw state with the
9991                  * ->get_hw_state callbacks. */
9992                 intel_connector_check_state(connector);
9993
9994                 WARN(&connector->new_encoder->base != connector->base.encoder,
9995                      "connector's staged encoder doesn't match current encoder\n");
9996         }
9997 }
9998
9999 static void
10000 check_encoder_state(struct drm_device *dev)
10001 {
10002         struct intel_encoder *encoder;
10003         struct intel_connector *connector;
10004
10005         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10006                             base.head) {
10007                 bool enabled = false;
10008                 bool active = false;
10009                 enum pipe pipe, tracked_pipe;
10010
10011                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10012                               encoder->base.base.id,
10013                               drm_get_encoder_name(&encoder->base));
10014
10015                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10016                      "encoder's stage crtc doesn't match current crtc\n");
10017                 WARN(encoder->connectors_active && !encoder->base.crtc,
10018                      "encoder's active_connectors set, but no crtc\n");
10019
10020                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10021                                     base.head) {
10022                         if (connector->base.encoder != &encoder->base)
10023                                 continue;
10024                         enabled = true;
10025                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10026                                 active = true;
10027                 }
10028                 WARN(!!encoder->base.crtc != enabled,
10029                      "encoder's enabled state mismatch "
10030                      "(expected %i, found %i)\n",
10031                      !!encoder->base.crtc, enabled);
10032                 WARN(active && !encoder->base.crtc,
10033                      "active encoder with no crtc\n");
10034
10035                 WARN(encoder->connectors_active != active,
10036                      "encoder's computed active state doesn't match tracked active state "
10037                      "(expected %i, found %i)\n", active, encoder->connectors_active);
10038
10039                 active = encoder->get_hw_state(encoder, &pipe);
10040                 WARN(active != encoder->connectors_active,
10041                      "encoder's hw state doesn't match sw tracking "
10042                      "(expected %i, found %i)\n",
10043                      encoder->connectors_active, active);
10044
10045                 if (!encoder->base.crtc)
10046                         continue;
10047
10048                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10049                 WARN(active && pipe != tracked_pipe,
10050                      "active encoder's pipe doesn't match"
10051                      "(expected %i, found %i)\n",
10052                      tracked_pipe, pipe);
10053
10054         }
10055 }
10056
10057 static void
10058 check_crtc_state(struct drm_device *dev)
10059 {
10060         struct drm_i915_private *dev_priv = dev->dev_private;
10061         struct intel_crtc *crtc;
10062         struct intel_encoder *encoder;
10063         struct intel_crtc_config pipe_config;
10064
10065         for_each_intel_crtc(dev, crtc) {
10066                 bool enabled = false;
10067                 bool active = false;
10068
10069                 memset(&pipe_config, 0, sizeof(pipe_config));
10070
10071                 DRM_DEBUG_KMS("[CRTC:%d]\n",
10072                               crtc->base.base.id);
10073
10074                 WARN(crtc->active && !crtc->base.enabled,
10075                      "active crtc, but not enabled in sw tracking\n");
10076
10077                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10078                                     base.head) {
10079                         if (encoder->base.crtc != &crtc->base)
10080                                 continue;
10081                         enabled = true;
10082                         if (encoder->connectors_active)
10083                                 active = true;
10084                 }
10085
10086                 WARN(active != crtc->active,
10087                      "crtc's computed active state doesn't match tracked active state "
10088                      "(expected %i, found %i)\n", active, crtc->active);
10089                 WARN(enabled != crtc->base.enabled,
10090                      "crtc's computed enabled state doesn't match tracked enabled state "
10091                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10092
10093                 active = dev_priv->display.get_pipe_config(crtc,
10094                                                            &pipe_config);
10095
10096                 /* hw state is inconsistent with the pipe A quirk */
10097                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
10098                         active = crtc->active;
10099
10100                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10101                                     base.head) {
10102                         enum pipe pipe;
10103                         if (encoder->base.crtc != &crtc->base)
10104                                 continue;
10105                         if (encoder->get_hw_state(encoder, &pipe))
10106                                 encoder->get_config(encoder, &pipe_config);
10107                 }
10108
10109                 WARN(crtc->active != active,
10110                      "crtc active state doesn't match with hw state "
10111                      "(expected %i, found %i)\n", crtc->active, active);
10112
10113                 if (active &&
10114                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10115                         WARN(1, "pipe state doesn't match!\n");
10116                         intel_dump_pipe_config(crtc, &pipe_config,
10117                                                "[hw state]");
10118                         intel_dump_pipe_config(crtc, &crtc->config,
10119                                                "[sw state]");
10120                 }
10121         }
10122 }
10123
10124 static void
10125 check_shared_dpll_state(struct drm_device *dev)
10126 {
10127         struct drm_i915_private *dev_priv = dev->dev_private;
10128         struct intel_crtc *crtc;
10129         struct intel_dpll_hw_state dpll_hw_state;
10130         int i;
10131
10132         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10133                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10134                 int enabled_crtcs = 0, active_crtcs = 0;
10135                 bool active;
10136
10137                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10138
10139                 DRM_DEBUG_KMS("%s\n", pll->name);
10140
10141                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10142
10143                 WARN(pll->active > pll->refcount,
10144                      "more active pll users than references: %i vs %i\n",
10145                      pll->active, pll->refcount);
10146                 WARN(pll->active && !pll->on,
10147                      "pll in active use but not on in sw tracking\n");
10148                 WARN(pll->on && !pll->active,
10149                      "pll in on but not on in use in sw tracking\n");
10150                 WARN(pll->on != active,
10151                      "pll on state mismatch (expected %i, found %i)\n",
10152                      pll->on, active);
10153
10154                 for_each_intel_crtc(dev, crtc) {
10155                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10156                                 enabled_crtcs++;
10157                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10158                                 active_crtcs++;
10159                 }
10160                 WARN(pll->active != active_crtcs,
10161                      "pll active crtcs mismatch (expected %i, found %i)\n",
10162                      pll->active, active_crtcs);
10163                 WARN(pll->refcount != enabled_crtcs,
10164                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
10165                      pll->refcount, enabled_crtcs);
10166
10167                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10168                                        sizeof(dpll_hw_state)),
10169                      "pll hw state mismatch\n");
10170         }
10171 }
10172
10173 void
10174 intel_modeset_check_state(struct drm_device *dev)
10175 {
10176         check_connector_state(dev);
10177         check_encoder_state(dev);
10178         check_crtc_state(dev);
10179         check_shared_dpll_state(dev);
10180 }
10181
10182 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10183                                      int dotclock)
10184 {
10185         /*
10186          * FDI already provided one idea for the dotclock.
10187          * Yell if the encoder disagrees.
10188          */
10189         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10190              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10191              pipe_config->adjusted_mode.crtc_clock, dotclock);
10192 }
10193
10194 static int __intel_set_mode(struct drm_crtc *crtc,
10195                             struct drm_display_mode *mode,
10196                             int x, int y, struct drm_framebuffer *fb)
10197 {
10198         struct drm_device *dev = crtc->dev;
10199         struct drm_i915_private *dev_priv = dev->dev_private;
10200         struct drm_display_mode *saved_mode;
10201         struct intel_crtc_config *pipe_config = NULL;
10202         struct intel_crtc *intel_crtc;
10203         unsigned disable_pipes, prepare_pipes, modeset_pipes;
10204         int ret = 0;
10205
10206         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10207         if (!saved_mode)
10208                 return -ENOMEM;
10209
10210         intel_modeset_affected_pipes(crtc, &modeset_pipes,
10211                                      &prepare_pipes, &disable_pipes);
10212
10213         *saved_mode = crtc->mode;
10214
10215         /* Hack: Because we don't (yet) support global modeset on multiple
10216          * crtcs, we don't keep track of the new mode for more than one crtc.
10217          * Hence simply check whether any bit is set in modeset_pipes in all the
10218          * pieces of code that are not yet converted to deal with mutliple crtcs
10219          * changing their mode at the same time. */
10220         if (modeset_pipes) {
10221                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10222                 if (IS_ERR(pipe_config)) {
10223                         ret = PTR_ERR(pipe_config);
10224                         pipe_config = NULL;
10225
10226                         goto out;
10227                 }
10228                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10229                                        "[modeset]");
10230                 to_intel_crtc(crtc)->new_config = pipe_config;
10231         }
10232
10233         /*
10234          * See if the config requires any additional preparation, e.g.
10235          * to adjust global state with pipes off.  We need to do this
10236          * here so we can get the modeset_pipe updated config for the new
10237          * mode set on this crtc.  For other crtcs we need to use the
10238          * adjusted_mode bits in the crtc directly.
10239          */
10240         if (IS_VALLEYVIEW(dev)) {
10241                 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10242
10243                 /* may have added more to prepare_pipes than we should */
10244                 prepare_pipes &= ~disable_pipes;
10245         }
10246
10247         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10248                 intel_crtc_disable(&intel_crtc->base);
10249
10250         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10251                 if (intel_crtc->base.enabled)
10252                         dev_priv->display.crtc_disable(&intel_crtc->base);
10253         }
10254
10255         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10256          * to set it here already despite that we pass it down the callchain.
10257          */
10258         if (modeset_pipes) {
10259                 crtc->mode = *mode;
10260                 /* mode_set/enable/disable functions rely on a correct pipe
10261                  * config. */
10262                 to_intel_crtc(crtc)->config = *pipe_config;
10263                 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10264
10265                 /*
10266                  * Calculate and store various constants which
10267                  * are later needed by vblank and swap-completion
10268                  * timestamping. They are derived from true hwmode.
10269                  */
10270                 drm_calc_timestamping_constants(crtc,
10271                                                 &pipe_config->adjusted_mode);
10272         }
10273
10274         /* Only after disabling all output pipelines that will be changed can we
10275          * update the the output configuration. */
10276         intel_modeset_update_state(dev, prepare_pipes);
10277
10278         if (dev_priv->display.modeset_global_resources)
10279                 dev_priv->display.modeset_global_resources(dev);
10280
10281         /* Set up the DPLL and any encoders state that needs to adjust or depend
10282          * on the DPLL.
10283          */
10284         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10285                 struct drm_framebuffer *old_fb;
10286
10287                 mutex_lock(&dev->struct_mutex);
10288                 ret = intel_pin_and_fence_fb_obj(dev,
10289                                                  to_intel_framebuffer(fb)->obj,
10290                                                  NULL);
10291                 if (ret != 0) {
10292                         DRM_ERROR("pin & fence failed\n");
10293                         mutex_unlock(&dev->struct_mutex);
10294                         goto done;
10295                 }
10296                 old_fb = crtc->primary->fb;
10297                 if (old_fb)
10298                         intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
10299                 mutex_unlock(&dev->struct_mutex);
10300
10301                 crtc->primary->fb = fb;
10302                 crtc->x = x;
10303                 crtc->y = y;
10304
10305                 ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
10306                                                       x, y, fb);
10307                 if (ret)
10308                         goto done;
10309         }
10310
10311         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10312         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
10313                 dev_priv->display.crtc_enable(&intel_crtc->base);
10314
10315         /* FIXME: add subpixel order */
10316 done:
10317         if (ret && crtc->enabled)
10318                 crtc->mode = *saved_mode;
10319
10320 out:
10321         kfree(pipe_config);
10322         kfree(saved_mode);
10323         return ret;
10324 }
10325
10326 static int intel_set_mode(struct drm_crtc *crtc,
10327                           struct drm_display_mode *mode,
10328                           int x, int y, struct drm_framebuffer *fb)
10329 {
10330         int ret;
10331
10332         ret = __intel_set_mode(crtc, mode, x, y, fb);
10333
10334         if (ret == 0)
10335                 intel_modeset_check_state(crtc->dev);
10336
10337         return ret;
10338 }
10339
10340 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10341 {
10342         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10343 }
10344
10345 #undef for_each_intel_crtc_masked
10346
10347 static void intel_set_config_free(struct intel_set_config *config)
10348 {
10349         if (!config)
10350                 return;
10351
10352         kfree(config->save_connector_encoders);
10353         kfree(config->save_encoder_crtcs);
10354         kfree(config->save_crtc_enabled);
10355         kfree(config);
10356 }
10357
10358 static int intel_set_config_save_state(struct drm_device *dev,
10359                                        struct intel_set_config *config)
10360 {
10361         struct drm_crtc *crtc;
10362         struct drm_encoder *encoder;
10363         struct drm_connector *connector;
10364         int count;
10365
10366         config->save_crtc_enabled =
10367                 kcalloc(dev->mode_config.num_crtc,
10368                         sizeof(bool), GFP_KERNEL);
10369         if (!config->save_crtc_enabled)
10370                 return -ENOMEM;
10371
10372         config->save_encoder_crtcs =
10373                 kcalloc(dev->mode_config.num_encoder,
10374                         sizeof(struct drm_crtc *), GFP_KERNEL);
10375         if (!config->save_encoder_crtcs)
10376                 return -ENOMEM;
10377
10378         config->save_connector_encoders =
10379                 kcalloc(dev->mode_config.num_connector,
10380                         sizeof(struct drm_encoder *), GFP_KERNEL);
10381         if (!config->save_connector_encoders)
10382                 return -ENOMEM;
10383
10384         /* Copy data. Note that driver private data is not affected.
10385          * Should anything bad happen only the expected state is
10386          * restored, not the drivers personal bookkeeping.
10387          */
10388         count = 0;
10389         for_each_crtc(dev, crtc) {
10390                 config->save_crtc_enabled[count++] = crtc->enabled;
10391         }
10392
10393         count = 0;
10394         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10395                 config->save_encoder_crtcs[count++] = encoder->crtc;
10396         }
10397
10398         count = 0;
10399         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10400                 config->save_connector_encoders[count++] = connector->encoder;
10401         }
10402
10403         return 0;
10404 }
10405
10406 static void intel_set_config_restore_state(struct drm_device *dev,
10407                                            struct intel_set_config *config)
10408 {
10409         struct intel_crtc *crtc;
10410         struct intel_encoder *encoder;
10411         struct intel_connector *connector;
10412         int count;
10413
10414         count = 0;
10415         for_each_intel_crtc(dev, crtc) {
10416                 crtc->new_enabled = config->save_crtc_enabled[count++];
10417
10418                 if (crtc->new_enabled)
10419                         crtc->new_config = &crtc->config;
10420                 else
10421                         crtc->new_config = NULL;
10422         }
10423
10424         count = 0;
10425         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10426                 encoder->new_crtc =
10427                         to_intel_crtc(config->save_encoder_crtcs[count++]);
10428         }
10429
10430         count = 0;
10431         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10432                 connector->new_encoder =
10433                         to_intel_encoder(config->save_connector_encoders[count++]);
10434         }
10435 }
10436
10437 static bool
10438 is_crtc_connector_off(struct drm_mode_set *set)
10439 {
10440         int i;
10441
10442         if (set->num_connectors == 0)
10443                 return false;
10444
10445         if (WARN_ON(set->connectors == NULL))
10446                 return false;
10447
10448         for (i = 0; i < set->num_connectors; i++)
10449                 if (set->connectors[i]->encoder &&
10450                     set->connectors[i]->encoder->crtc == set->crtc &&
10451                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
10452                         return true;
10453
10454         return false;
10455 }
10456
10457 static void
10458 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
10459                                       struct intel_set_config *config)
10460 {
10461
10462         /* We should be able to check here if the fb has the same properties
10463          * and then just flip_or_move it */
10464         if (is_crtc_connector_off(set)) {
10465                 config->mode_changed = true;
10466         } else if (set->crtc->primary->fb != set->fb) {
10467                 /* If we have no fb then treat it as a full mode set */
10468                 if (set->crtc->primary->fb == NULL) {
10469                         struct intel_crtc *intel_crtc =
10470                                 to_intel_crtc(set->crtc);
10471
10472                         if (intel_crtc->active && i915.fastboot) {
10473                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
10474                                 config->fb_changed = true;
10475                         } else {
10476                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
10477                                 config->mode_changed = true;
10478                         }
10479                 } else if (set->fb == NULL) {
10480                         config->mode_changed = true;
10481                 } else if (set->fb->pixel_format !=
10482                            set->crtc->primary->fb->pixel_format) {
10483                         config->mode_changed = true;
10484                 } else {
10485                         config->fb_changed = true;
10486                 }
10487         }
10488
10489         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
10490                 config->fb_changed = true;
10491
10492         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
10493                 DRM_DEBUG_KMS("modes are different, full mode set\n");
10494                 drm_mode_debug_printmodeline(&set->crtc->mode);
10495                 drm_mode_debug_printmodeline(set->mode);
10496                 config->mode_changed = true;
10497         }
10498
10499         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
10500                         set->crtc->base.id, config->mode_changed, config->fb_changed);
10501 }
10502
10503 static int
10504 intel_modeset_stage_output_state(struct drm_device *dev,
10505                                  struct drm_mode_set *set,
10506                                  struct intel_set_config *config)
10507 {
10508         struct intel_connector *connector;
10509         struct intel_encoder *encoder;
10510         struct intel_crtc *crtc;
10511         int ro;
10512
10513         /* The upper layers ensure that we either disable a crtc or have a list
10514          * of connectors. For paranoia, double-check this. */
10515         WARN_ON(!set->fb && (set->num_connectors != 0));
10516         WARN_ON(set->fb && (set->num_connectors == 0));
10517
10518         list_for_each_entry(connector, &dev->mode_config.connector_list,
10519                             base.head) {
10520                 /* Otherwise traverse passed in connector list and get encoders
10521                  * for them. */
10522                 for (ro = 0; ro < set->num_connectors; ro++) {
10523                         if (set->connectors[ro] == &connector->base) {
10524                                 connector->new_encoder = connector->encoder;
10525                                 break;
10526                         }
10527                 }
10528
10529                 /* If we disable the crtc, disable all its connectors. Also, if
10530                  * the connector is on the changing crtc but not on the new
10531                  * connector list, disable it. */
10532                 if ((!set->fb || ro == set->num_connectors) &&
10533                     connector->base.encoder &&
10534                     connector->base.encoder->crtc == set->crtc) {
10535                         connector->new_encoder = NULL;
10536
10537                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
10538                                 connector->base.base.id,
10539                                 drm_get_connector_name(&connector->base));
10540                 }
10541
10542
10543                 if (&connector->new_encoder->base != connector->base.encoder) {
10544                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
10545                         config->mode_changed = true;
10546                 }
10547         }
10548         /* connector->new_encoder is now updated for all connectors. */
10549
10550         /* Update crtc of enabled connectors. */
10551         list_for_each_entry(connector, &dev->mode_config.connector_list,
10552                             base.head) {
10553                 struct drm_crtc *new_crtc;
10554
10555                 if (!connector->new_encoder)
10556                         continue;
10557
10558                 new_crtc = connector->new_encoder->base.crtc;
10559
10560                 for (ro = 0; ro < set->num_connectors; ro++) {
10561                         if (set->connectors[ro] == &connector->base)
10562                                 new_crtc = set->crtc;
10563                 }
10564
10565                 /* Make sure the new CRTC will work with the encoder */
10566                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
10567                                          new_crtc)) {
10568                         return -EINVAL;
10569                 }
10570                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
10571
10572                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
10573                         connector->base.base.id,
10574                         drm_get_connector_name(&connector->base),
10575                         new_crtc->base.id);
10576         }
10577
10578         /* Check for any encoders that needs to be disabled. */
10579         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10580                             base.head) {
10581                 int num_connectors = 0;
10582                 list_for_each_entry(connector,
10583                                     &dev->mode_config.connector_list,
10584                                     base.head) {
10585                         if (connector->new_encoder == encoder) {
10586                                 WARN_ON(!connector->new_encoder->new_crtc);
10587                                 num_connectors++;
10588                         }
10589                 }
10590
10591                 if (num_connectors == 0)
10592                         encoder->new_crtc = NULL;
10593                 else if (num_connectors > 1)
10594                         return -EINVAL;
10595
10596                 /* Only now check for crtc changes so we don't miss encoders
10597                  * that will be disabled. */
10598                 if (&encoder->new_crtc->base != encoder->base.crtc) {
10599                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
10600                         config->mode_changed = true;
10601                 }
10602         }
10603         /* Now we've also updated encoder->new_crtc for all encoders. */
10604
10605         for_each_intel_crtc(dev, crtc) {
10606                 crtc->new_enabled = false;
10607
10608                 list_for_each_entry(encoder,
10609                                     &dev->mode_config.encoder_list,
10610                                     base.head) {
10611                         if (encoder->new_crtc == crtc) {
10612                                 crtc->new_enabled = true;
10613                                 break;
10614                         }
10615                 }
10616
10617                 if (crtc->new_enabled != crtc->base.enabled) {
10618                         DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
10619                                       crtc->new_enabled ? "en" : "dis");
10620                         config->mode_changed = true;
10621                 }
10622
10623                 if (crtc->new_enabled)
10624                         crtc->new_config = &crtc->config;
10625                 else
10626                         crtc->new_config = NULL;
10627         }
10628
10629         return 0;
10630 }
10631
10632 static void disable_crtc_nofb(struct intel_crtc *crtc)
10633 {
10634         struct drm_device *dev = crtc->base.dev;
10635         struct intel_encoder *encoder;
10636         struct intel_connector *connector;
10637
10638         DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
10639                       pipe_name(crtc->pipe));
10640
10641         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10642                 if (connector->new_encoder &&
10643                     connector->new_encoder->new_crtc == crtc)
10644                         connector->new_encoder = NULL;
10645         }
10646
10647         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10648                 if (encoder->new_crtc == crtc)
10649                         encoder->new_crtc = NULL;
10650         }
10651
10652         crtc->new_enabled = false;
10653         crtc->new_config = NULL;
10654 }
10655
10656 static int intel_crtc_set_config(struct drm_mode_set *set)
10657 {
10658         struct drm_device *dev;
10659         struct drm_mode_set save_set;
10660         struct intel_set_config *config;
10661         int ret;
10662
10663         BUG_ON(!set);
10664         BUG_ON(!set->crtc);
10665         BUG_ON(!set->crtc->helper_private);
10666
10667         /* Enforce sane interface api - has been abused by the fb helper. */
10668         BUG_ON(!set->mode && set->fb);
10669         BUG_ON(set->fb && set->num_connectors == 0);
10670
10671         if (set->fb) {
10672                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
10673                                 set->crtc->base.id, set->fb->base.id,
10674                                 (int)set->num_connectors, set->x, set->y);
10675         } else {
10676                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
10677         }
10678
10679         dev = set->crtc->dev;
10680
10681         ret = -ENOMEM;
10682         config = kzalloc(sizeof(*config), GFP_KERNEL);
10683         if (!config)
10684                 goto out_config;
10685
10686         ret = intel_set_config_save_state(dev, config);
10687         if (ret)
10688                 goto out_config;
10689
10690         save_set.crtc = set->crtc;
10691         save_set.mode = &set->crtc->mode;
10692         save_set.x = set->crtc->x;
10693         save_set.y = set->crtc->y;
10694         save_set.fb = set->crtc->primary->fb;
10695
10696         /* Compute whether we need a full modeset, only an fb base update or no
10697          * change at all. In the future we might also check whether only the
10698          * mode changed, e.g. for LVDS where we only change the panel fitter in
10699          * such cases. */
10700         intel_set_config_compute_mode_changes(set, config);
10701
10702         ret = intel_modeset_stage_output_state(dev, set, config);
10703         if (ret)
10704                 goto fail;
10705
10706         if (config->mode_changed) {
10707                 ret = intel_set_mode(set->crtc, set->mode,
10708                                      set->x, set->y, set->fb);
10709         } else if (config->fb_changed) {
10710                 intel_crtc_wait_for_pending_flips(set->crtc);
10711
10712                 ret = intel_pipe_set_base(set->crtc,
10713                                           set->x, set->y, set->fb);
10714                 /*
10715                  * In the fastboot case this may be our only check of the
10716                  * state after boot.  It would be better to only do it on
10717                  * the first update, but we don't have a nice way of doing that
10718                  * (and really, set_config isn't used much for high freq page
10719                  * flipping, so increasing its cost here shouldn't be a big
10720                  * deal).
10721                  */
10722                 if (i915.fastboot && ret == 0)
10723                         intel_modeset_check_state(set->crtc->dev);
10724         }
10725
10726         if (ret) {
10727                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
10728                               set->crtc->base.id, ret);
10729 fail:
10730                 intel_set_config_restore_state(dev, config);
10731
10732                 /*
10733                  * HACK: if the pipe was on, but we didn't have a framebuffer,
10734                  * force the pipe off to avoid oopsing in the modeset code
10735                  * due to fb==NULL. This should only happen during boot since
10736                  * we don't yet reconstruct the FB from the hardware state.
10737                  */
10738                 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
10739                         disable_crtc_nofb(to_intel_crtc(save_set.crtc));
10740
10741                 /* Try to restore the config */
10742                 if (config->mode_changed &&
10743                     intel_set_mode(save_set.crtc, save_set.mode,
10744                                    save_set.x, save_set.y, save_set.fb))
10745                         DRM_ERROR("failed to restore config after modeset failure\n");
10746         }
10747
10748 out_config:
10749         intel_set_config_free(config);
10750         return ret;
10751 }
10752
10753 static const struct drm_crtc_funcs intel_crtc_funcs = {
10754         .cursor_set = intel_crtc_cursor_set,
10755         .cursor_move = intel_crtc_cursor_move,
10756         .gamma_set = intel_crtc_gamma_set,
10757         .set_config = intel_crtc_set_config,
10758         .destroy = intel_crtc_destroy,
10759         .page_flip = intel_crtc_page_flip,
10760 };
10761
10762 static void intel_cpu_pll_init(struct drm_device *dev)
10763 {
10764         if (HAS_DDI(dev))
10765                 intel_ddi_pll_init(dev);
10766 }
10767
10768 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
10769                                       struct intel_shared_dpll *pll,
10770                                       struct intel_dpll_hw_state *hw_state)
10771 {
10772         uint32_t val;
10773
10774         val = I915_READ(PCH_DPLL(pll->id));
10775         hw_state->dpll = val;
10776         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
10777         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
10778
10779         return val & DPLL_VCO_ENABLE;
10780 }
10781
10782 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
10783                                   struct intel_shared_dpll *pll)
10784 {
10785         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
10786         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
10787 }
10788
10789 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
10790                                 struct intel_shared_dpll *pll)
10791 {
10792         /* PCH refclock must be enabled first */
10793         ibx_assert_pch_refclk_enabled(dev_priv);
10794
10795         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10796
10797         /* Wait for the clocks to stabilize. */
10798         POSTING_READ(PCH_DPLL(pll->id));
10799         udelay(150);
10800
10801         /* The pixel multiplier can only be updated once the
10802          * DPLL is enabled and the clocks are stable.
10803          *
10804          * So write it again.
10805          */
10806         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10807         POSTING_READ(PCH_DPLL(pll->id));
10808         udelay(200);
10809 }
10810
10811 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
10812                                  struct intel_shared_dpll *pll)
10813 {
10814         struct drm_device *dev = dev_priv->dev;
10815         struct intel_crtc *crtc;
10816
10817         /* Make sure no transcoder isn't still depending on us. */
10818         for_each_intel_crtc(dev, crtc) {
10819                 if (intel_crtc_to_shared_dpll(crtc) == pll)
10820                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
10821         }
10822
10823         I915_WRITE(PCH_DPLL(pll->id), 0);
10824         POSTING_READ(PCH_DPLL(pll->id));
10825         udelay(200);
10826 }
10827
10828 static char *ibx_pch_dpll_names[] = {
10829         "PCH DPLL A",
10830         "PCH DPLL B",
10831 };
10832
10833 static void ibx_pch_dpll_init(struct drm_device *dev)
10834 {
10835         struct drm_i915_private *dev_priv = dev->dev_private;
10836         int i;
10837
10838         dev_priv->num_shared_dpll = 2;
10839
10840         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10841                 dev_priv->shared_dplls[i].id = i;
10842                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
10843                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
10844                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
10845                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
10846                 dev_priv->shared_dplls[i].get_hw_state =
10847                         ibx_pch_dpll_get_hw_state;
10848         }
10849 }
10850
10851 static void intel_shared_dpll_init(struct drm_device *dev)
10852 {
10853         struct drm_i915_private *dev_priv = dev->dev_private;
10854
10855         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
10856                 ibx_pch_dpll_init(dev);
10857         else
10858                 dev_priv->num_shared_dpll = 0;
10859
10860         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
10861 }
10862
10863 static void intel_crtc_init(struct drm_device *dev, int pipe)
10864 {
10865         struct drm_i915_private *dev_priv = dev->dev_private;
10866         struct intel_crtc *intel_crtc;
10867         int i;
10868
10869         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
10870         if (intel_crtc == NULL)
10871                 return;
10872
10873         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
10874
10875         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
10876         for (i = 0; i < 256; i++) {
10877                 intel_crtc->lut_r[i] = i;
10878                 intel_crtc->lut_g[i] = i;
10879                 intel_crtc->lut_b[i] = i;
10880         }
10881
10882         /*
10883          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
10884          * is hooked to plane B. Hence we want plane A feeding pipe B.
10885          */
10886         intel_crtc->pipe = pipe;
10887         intel_crtc->plane = pipe;
10888         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
10889                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
10890                 intel_crtc->plane = !pipe;
10891         }
10892
10893         init_waitqueue_head(&intel_crtc->vbl_wait);
10894
10895         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
10896                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
10897         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
10898         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
10899
10900         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
10901 }
10902
10903 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
10904 {
10905         struct drm_encoder *encoder = connector->base.encoder;
10906
10907         WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex));
10908
10909         if (!encoder)
10910                 return INVALID_PIPE;
10911
10912         return to_intel_crtc(encoder->crtc)->pipe;
10913 }
10914
10915 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
10916                                 struct drm_file *file)
10917 {
10918         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
10919         struct drm_mode_object *drmmode_obj;
10920         struct intel_crtc *crtc;
10921
10922         if (!drm_core_check_feature(dev, DRIVER_MODESET))
10923                 return -ENODEV;
10924
10925         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
10926                         DRM_MODE_OBJECT_CRTC);
10927
10928         if (!drmmode_obj) {
10929                 DRM_ERROR("no such CRTC id\n");
10930                 return -ENOENT;
10931         }
10932
10933         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
10934         pipe_from_crtc_id->pipe = crtc->pipe;
10935
10936         return 0;
10937 }
10938
10939 static int intel_encoder_clones(struct intel_encoder *encoder)
10940 {
10941         struct drm_device *dev = encoder->base.dev;
10942         struct intel_encoder *source_encoder;
10943         int index_mask = 0;
10944         int entry = 0;
10945
10946         list_for_each_entry(source_encoder,
10947                             &dev->mode_config.encoder_list, base.head) {
10948                 if (encoders_cloneable(encoder, source_encoder))
10949                         index_mask |= (1 << entry);
10950
10951                 entry++;
10952         }
10953
10954         return index_mask;
10955 }
10956
10957 static bool has_edp_a(struct drm_device *dev)
10958 {
10959         struct drm_i915_private *dev_priv = dev->dev_private;
10960
10961         if (!IS_MOBILE(dev))
10962                 return false;
10963
10964         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
10965                 return false;
10966
10967         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
10968                 return false;
10969
10970         return true;
10971 }
10972
10973 const char *intel_output_name(int output)
10974 {
10975         static const char *names[] = {
10976                 [INTEL_OUTPUT_UNUSED] = "Unused",
10977                 [INTEL_OUTPUT_ANALOG] = "Analog",
10978                 [INTEL_OUTPUT_DVO] = "DVO",
10979                 [INTEL_OUTPUT_SDVO] = "SDVO",
10980                 [INTEL_OUTPUT_LVDS] = "LVDS",
10981                 [INTEL_OUTPUT_TVOUT] = "TV",
10982                 [INTEL_OUTPUT_HDMI] = "HDMI",
10983                 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
10984                 [INTEL_OUTPUT_EDP] = "eDP",
10985                 [INTEL_OUTPUT_DSI] = "DSI",
10986                 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
10987         };
10988
10989         if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
10990                 return "Invalid";
10991
10992         return names[output];
10993 }
10994
10995 static void intel_setup_outputs(struct drm_device *dev)
10996 {
10997         struct drm_i915_private *dev_priv = dev->dev_private;
10998         struct intel_encoder *encoder;
10999         bool dpd_is_edp = false;
11000
11001         intel_lvds_init(dev);
11002
11003         if (!IS_ULT(dev) && !IS_CHERRYVIEW(dev))
11004                 intel_crt_init(dev);
11005
11006         if (HAS_DDI(dev)) {
11007                 int found;
11008
11009                 /* Haswell uses DDI functions to detect digital outputs */
11010                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
11011                 /* DDI A only supports eDP */
11012                 if (found)
11013                         intel_ddi_init(dev, PORT_A);
11014
11015                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
11016                  * register */
11017                 found = I915_READ(SFUSE_STRAP);
11018
11019                 if (found & SFUSE_STRAP_DDIB_DETECTED)
11020                         intel_ddi_init(dev, PORT_B);
11021                 if (found & SFUSE_STRAP_DDIC_DETECTED)
11022                         intel_ddi_init(dev, PORT_C);
11023                 if (found & SFUSE_STRAP_DDID_DETECTED)
11024                         intel_ddi_init(dev, PORT_D);
11025         } else if (HAS_PCH_SPLIT(dev)) {
11026                 int found;
11027                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
11028
11029                 if (has_edp_a(dev))
11030                         intel_dp_init(dev, DP_A, PORT_A);
11031
11032                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
11033                         /* PCH SDVOB multiplex with HDMIB */
11034                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
11035                         if (!found)
11036                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
11037                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
11038                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
11039                 }
11040
11041                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
11042                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
11043
11044                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
11045                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
11046
11047                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
11048                         intel_dp_init(dev, PCH_DP_C, PORT_C);
11049
11050                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
11051                         intel_dp_init(dev, PCH_DP_D, PORT_D);
11052         } else if (IS_VALLEYVIEW(dev)) {
11053                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
11054                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
11055                                         PORT_B);
11056                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
11057                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
11058                 }
11059
11060                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
11061                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
11062                                         PORT_C);
11063                         if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
11064                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
11065                 }
11066
11067                 if (IS_CHERRYVIEW(dev)) {
11068                         if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) {
11069                                 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
11070                                                 PORT_D);
11071                                 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
11072                                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
11073                         }
11074                 }
11075
11076                 intel_dsi_init(dev);
11077         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
11078                 bool found = false;
11079
11080                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
11081                         DRM_DEBUG_KMS("probing SDVOB\n");
11082                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
11083                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
11084                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
11085                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
11086                         }
11087
11088                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
11089                                 intel_dp_init(dev, DP_B, PORT_B);
11090                 }
11091
11092                 /* Before G4X SDVOC doesn't have its own detect register */
11093
11094                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
11095                         DRM_DEBUG_KMS("probing SDVOC\n");
11096                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
11097                 }
11098
11099                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
11100
11101                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
11102                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
11103                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
11104                         }
11105                         if (SUPPORTS_INTEGRATED_DP(dev))
11106                                 intel_dp_init(dev, DP_C, PORT_C);
11107                 }
11108
11109                 if (SUPPORTS_INTEGRATED_DP(dev) &&
11110                     (I915_READ(DP_D) & DP_DETECTED))
11111                         intel_dp_init(dev, DP_D, PORT_D);
11112         } else if (IS_GEN2(dev))
11113                 intel_dvo_init(dev);
11114
11115         if (SUPPORTS_TV(dev))
11116                 intel_tv_init(dev);
11117
11118         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
11119                 encoder->base.possible_crtcs = encoder->crtc_mask;
11120                 encoder->base.possible_clones =
11121                         intel_encoder_clones(encoder);
11122         }
11123
11124         intel_init_pch_refclk(dev);
11125
11126         drm_helper_move_panel_connectors_to_head(dev);
11127 }
11128
11129 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
11130 {
11131         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11132
11133         drm_framebuffer_cleanup(fb);
11134         WARN_ON(!intel_fb->obj->framebuffer_references--);
11135         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
11136         kfree(intel_fb);
11137 }
11138
11139 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
11140                                                 struct drm_file *file,
11141                                                 unsigned int *handle)
11142 {
11143         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11144         struct drm_i915_gem_object *obj = intel_fb->obj;
11145
11146         return drm_gem_handle_create(file, &obj->base, handle);
11147 }
11148
11149 static const struct drm_framebuffer_funcs intel_fb_funcs = {
11150         .destroy = intel_user_framebuffer_destroy,
11151         .create_handle = intel_user_framebuffer_create_handle,
11152 };
11153
11154 static int intel_framebuffer_init(struct drm_device *dev,
11155                                   struct intel_framebuffer *intel_fb,
11156                                   struct drm_mode_fb_cmd2 *mode_cmd,
11157                                   struct drm_i915_gem_object *obj)
11158 {
11159         int aligned_height;
11160         int pitch_limit;
11161         int ret;
11162
11163         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
11164
11165         if (obj->tiling_mode == I915_TILING_Y) {
11166                 DRM_DEBUG("hardware does not support tiling Y\n");
11167                 return -EINVAL;
11168         }
11169
11170         if (mode_cmd->pitches[0] & 63) {
11171                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
11172                           mode_cmd->pitches[0]);
11173                 return -EINVAL;
11174         }
11175
11176         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
11177                 pitch_limit = 32*1024;
11178         } else if (INTEL_INFO(dev)->gen >= 4) {
11179                 if (obj->tiling_mode)
11180                         pitch_limit = 16*1024;
11181                 else
11182                         pitch_limit = 32*1024;
11183         } else if (INTEL_INFO(dev)->gen >= 3) {
11184                 if (obj->tiling_mode)
11185                         pitch_limit = 8*1024;
11186                 else
11187                         pitch_limit = 16*1024;
11188         } else
11189                 /* XXX DSPC is limited to 4k tiled */
11190                 pitch_limit = 8*1024;
11191
11192         if (mode_cmd->pitches[0] > pitch_limit) {
11193                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
11194                           obj->tiling_mode ? "tiled" : "linear",
11195                           mode_cmd->pitches[0], pitch_limit);
11196                 return -EINVAL;
11197         }
11198
11199         if (obj->tiling_mode != I915_TILING_NONE &&
11200             mode_cmd->pitches[0] != obj->stride) {
11201                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
11202                           mode_cmd->pitches[0], obj->stride);
11203                 return -EINVAL;
11204         }
11205
11206         /* Reject formats not supported by any plane early. */
11207         switch (mode_cmd->pixel_format) {
11208         case DRM_FORMAT_C8:
11209         case DRM_FORMAT_RGB565:
11210         case DRM_FORMAT_XRGB8888:
11211         case DRM_FORMAT_ARGB8888:
11212                 break;
11213         case DRM_FORMAT_XRGB1555:
11214         case DRM_FORMAT_ARGB1555:
11215                 if (INTEL_INFO(dev)->gen > 3) {
11216                         DRM_DEBUG("unsupported pixel format: %s\n",
11217                                   drm_get_format_name(mode_cmd->pixel_format));
11218                         return -EINVAL;
11219                 }
11220                 break;
11221         case DRM_FORMAT_XBGR8888:
11222         case DRM_FORMAT_ABGR8888:
11223         case DRM_FORMAT_XRGB2101010:
11224         case DRM_FORMAT_ARGB2101010:
11225         case DRM_FORMAT_XBGR2101010:
11226         case DRM_FORMAT_ABGR2101010:
11227                 if (INTEL_INFO(dev)->gen < 4) {
11228                         DRM_DEBUG("unsupported pixel format: %s\n",
11229                                   drm_get_format_name(mode_cmd->pixel_format));
11230                         return -EINVAL;
11231                 }
11232                 break;
11233         case DRM_FORMAT_YUYV:
11234         case DRM_FORMAT_UYVY:
11235         case DRM_FORMAT_YVYU:
11236         case DRM_FORMAT_VYUY:
11237                 if (INTEL_INFO(dev)->gen < 5) {
11238                         DRM_DEBUG("unsupported pixel format: %s\n",
11239                                   drm_get_format_name(mode_cmd->pixel_format));
11240                         return -EINVAL;
11241                 }
11242                 break;
11243         default:
11244                 DRM_DEBUG("unsupported pixel format: %s\n",
11245                           drm_get_format_name(mode_cmd->pixel_format));
11246                 return -EINVAL;
11247         }
11248
11249         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
11250         if (mode_cmd->offsets[0] != 0)
11251                 return -EINVAL;
11252
11253         aligned_height = intel_align_height(dev, mode_cmd->height,
11254                                             obj->tiling_mode);
11255         /* FIXME drm helper for size checks (especially planar formats)? */
11256         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
11257                 return -EINVAL;
11258
11259         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
11260         intel_fb->obj = obj;
11261         intel_fb->obj->framebuffer_references++;
11262
11263         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
11264         if (ret) {
11265                 DRM_ERROR("framebuffer init failed %d\n", ret);
11266                 return ret;
11267         }
11268
11269         return 0;
11270 }
11271
11272 static struct drm_framebuffer *
11273 intel_user_framebuffer_create(struct drm_device *dev,
11274                               struct drm_file *filp,
11275                               struct drm_mode_fb_cmd2 *mode_cmd)
11276 {
11277         struct drm_i915_gem_object *obj;
11278
11279         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
11280                                                 mode_cmd->handles[0]));
11281         if (&obj->base == NULL)
11282                 return ERR_PTR(-ENOENT);
11283
11284         return intel_framebuffer_create(dev, mode_cmd, obj);
11285 }
11286
11287 #ifndef CONFIG_DRM_I915_FBDEV
11288 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
11289 {
11290 }
11291 #endif
11292
11293 static const struct drm_mode_config_funcs intel_mode_funcs = {
11294         .fb_create = intel_user_framebuffer_create,
11295         .output_poll_changed = intel_fbdev_output_poll_changed,
11296 };
11297
11298 /* Set up chip specific display functions */
11299 static void intel_init_display(struct drm_device *dev)
11300 {
11301         struct drm_i915_private *dev_priv = dev->dev_private;
11302
11303         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
11304                 dev_priv->display.find_dpll = g4x_find_best_dpll;
11305         else if (IS_CHERRYVIEW(dev))
11306                 dev_priv->display.find_dpll = chv_find_best_dpll;
11307         else if (IS_VALLEYVIEW(dev))
11308                 dev_priv->display.find_dpll = vlv_find_best_dpll;
11309         else if (IS_PINEVIEW(dev))
11310                 dev_priv->display.find_dpll = pnv_find_best_dpll;
11311         else
11312                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
11313
11314         if (HAS_DDI(dev)) {
11315                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
11316                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
11317                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
11318                 dev_priv->display.crtc_enable = haswell_crtc_enable;
11319                 dev_priv->display.crtc_disable = haswell_crtc_disable;
11320                 dev_priv->display.off = haswell_crtc_off;
11321                 dev_priv->display.update_primary_plane =
11322                         ironlake_update_primary_plane;
11323         } else if (HAS_PCH_SPLIT(dev)) {
11324                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
11325                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
11326                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
11327                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
11328                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
11329                 dev_priv->display.off = ironlake_crtc_off;
11330                 dev_priv->display.update_primary_plane =
11331                         ironlake_update_primary_plane;
11332         } else if (IS_VALLEYVIEW(dev)) {
11333                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11334                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11335                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11336                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
11337                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11338                 dev_priv->display.off = i9xx_crtc_off;
11339                 dev_priv->display.update_primary_plane =
11340                         i9xx_update_primary_plane;
11341         } else {
11342                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11343                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11344                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11345                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
11346                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11347                 dev_priv->display.off = i9xx_crtc_off;
11348                 dev_priv->display.update_primary_plane =
11349                         i9xx_update_primary_plane;
11350         }
11351
11352         /* Returns the core display clock speed */
11353         if (IS_VALLEYVIEW(dev))
11354                 dev_priv->display.get_display_clock_speed =
11355                         valleyview_get_display_clock_speed;
11356         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
11357                 dev_priv->display.get_display_clock_speed =
11358                         i945_get_display_clock_speed;
11359         else if (IS_I915G(dev))
11360                 dev_priv->display.get_display_clock_speed =
11361                         i915_get_display_clock_speed;
11362         else if (IS_I945GM(dev) || IS_845G(dev))
11363                 dev_priv->display.get_display_clock_speed =
11364                         i9xx_misc_get_display_clock_speed;
11365         else if (IS_PINEVIEW(dev))
11366                 dev_priv->display.get_display_clock_speed =
11367                         pnv_get_display_clock_speed;
11368         else if (IS_I915GM(dev))
11369                 dev_priv->display.get_display_clock_speed =
11370                         i915gm_get_display_clock_speed;
11371         else if (IS_I865G(dev))
11372                 dev_priv->display.get_display_clock_speed =
11373                         i865_get_display_clock_speed;
11374         else if (IS_I85X(dev))
11375                 dev_priv->display.get_display_clock_speed =
11376                         i855_get_display_clock_speed;
11377         else /* 852, 830 */
11378                 dev_priv->display.get_display_clock_speed =
11379                         i830_get_display_clock_speed;
11380
11381         if (HAS_PCH_SPLIT(dev)) {
11382                 if (IS_GEN5(dev)) {
11383                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
11384                         dev_priv->display.write_eld = ironlake_write_eld;
11385                 } else if (IS_GEN6(dev)) {
11386                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
11387                         dev_priv->display.write_eld = ironlake_write_eld;
11388                         dev_priv->display.modeset_global_resources =
11389                                 snb_modeset_global_resources;
11390                 } else if (IS_IVYBRIDGE(dev)) {
11391                         /* FIXME: detect B0+ stepping and use auto training */
11392                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
11393                         dev_priv->display.write_eld = ironlake_write_eld;
11394                         dev_priv->display.modeset_global_resources =
11395                                 ivb_modeset_global_resources;
11396                 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
11397                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
11398                         dev_priv->display.write_eld = haswell_write_eld;
11399                         dev_priv->display.modeset_global_resources =
11400                                 haswell_modeset_global_resources;
11401                 }
11402         } else if (IS_G4X(dev)) {
11403                 dev_priv->display.write_eld = g4x_write_eld;
11404         } else if (IS_VALLEYVIEW(dev)) {
11405                 dev_priv->display.modeset_global_resources =
11406                         valleyview_modeset_global_resources;
11407                 dev_priv->display.write_eld = ironlake_write_eld;
11408         }
11409
11410         /* Default just returns -ENODEV to indicate unsupported */
11411         dev_priv->display.queue_flip = intel_default_queue_flip;
11412
11413         switch (INTEL_INFO(dev)->gen) {
11414         case 2:
11415                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
11416                 break;
11417
11418         case 3:
11419                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
11420                 break;
11421
11422         case 4:
11423         case 5:
11424                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
11425                 break;
11426
11427         case 6:
11428                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
11429                 break;
11430         case 7:
11431         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
11432                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
11433                 break;
11434         }
11435
11436         intel_panel_init_backlight_funcs(dev);
11437 }
11438
11439 /*
11440  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
11441  * resume, or other times.  This quirk makes sure that's the case for
11442  * affected systems.
11443  */
11444 static void quirk_pipea_force(struct drm_device *dev)
11445 {
11446         struct drm_i915_private *dev_priv = dev->dev_private;
11447
11448         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
11449         DRM_INFO("applying pipe a force quirk\n");
11450 }
11451
11452 /*
11453  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
11454  */
11455 static void quirk_ssc_force_disable(struct drm_device *dev)
11456 {
11457         struct drm_i915_private *dev_priv = dev->dev_private;
11458         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
11459         DRM_INFO("applying lvds SSC disable quirk\n");
11460 }
11461
11462 /*
11463  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
11464  * brightness value
11465  */
11466 static void quirk_invert_brightness(struct drm_device *dev)
11467 {
11468         struct drm_i915_private *dev_priv = dev->dev_private;
11469         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
11470         DRM_INFO("applying inverted panel brightness quirk\n");
11471 }
11472
11473 struct intel_quirk {
11474         int device;
11475         int subsystem_vendor;
11476         int subsystem_device;
11477         void (*hook)(struct drm_device *dev);
11478 };
11479
11480 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
11481 struct intel_dmi_quirk {
11482         void (*hook)(struct drm_device *dev);
11483         const struct dmi_system_id (*dmi_id_list)[];
11484 };
11485
11486 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
11487 {
11488         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
11489         return 1;
11490 }
11491
11492 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
11493         {
11494                 .dmi_id_list = &(const struct dmi_system_id[]) {
11495                         {
11496                                 .callback = intel_dmi_reverse_brightness,
11497                                 .ident = "NCR Corporation",
11498                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
11499                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
11500                                 },
11501                         },
11502                         { }  /* terminating entry */
11503                 },
11504                 .hook = quirk_invert_brightness,
11505         },
11506 };
11507
11508 static struct intel_quirk intel_quirks[] = {
11509         /* HP Mini needs pipe A force quirk (LP: #322104) */
11510         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
11511
11512         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
11513         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
11514
11515         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
11516         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
11517
11518         /* 830 needs to leave pipe A & dpll A up */
11519         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
11520
11521         /* Lenovo U160 cannot use SSC on LVDS */
11522         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
11523
11524         /* Sony Vaio Y cannot use SSC on LVDS */
11525         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
11526
11527         /* Acer Aspire 5734Z must invert backlight brightness */
11528         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
11529
11530         /* Acer/eMachines G725 */
11531         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
11532
11533         /* Acer/eMachines e725 */
11534         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
11535
11536         /* Acer/Packard Bell NCL20 */
11537         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
11538
11539         /* Acer Aspire 4736Z */
11540         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
11541
11542         /* Acer Aspire 5336 */
11543         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
11544 };
11545
11546 static void intel_init_quirks(struct drm_device *dev)
11547 {
11548         struct pci_dev *d = dev->pdev;
11549         int i;
11550
11551         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
11552                 struct intel_quirk *q = &intel_quirks[i];
11553
11554                 if (d->device == q->device &&
11555                     (d->subsystem_vendor == q->subsystem_vendor ||
11556                      q->subsystem_vendor == PCI_ANY_ID) &&
11557                     (d->subsystem_device == q->subsystem_device ||
11558                      q->subsystem_device == PCI_ANY_ID))
11559                         q->hook(dev);
11560         }
11561         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
11562                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
11563                         intel_dmi_quirks[i].hook(dev);
11564         }
11565 }
11566
11567 /* Disable the VGA plane that we never use */
11568 static void i915_disable_vga(struct drm_device *dev)
11569 {
11570         struct drm_i915_private *dev_priv = dev->dev_private;
11571         u8 sr1;
11572         u32 vga_reg = i915_vgacntrl_reg(dev);
11573
11574         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
11575         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
11576         outb(SR01, VGA_SR_INDEX);
11577         sr1 = inb(VGA_SR_DATA);
11578         outb(sr1 | 1<<5, VGA_SR_DATA);
11579         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
11580         udelay(300);
11581
11582         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
11583         POSTING_READ(vga_reg);
11584 }
11585
11586 void intel_modeset_init_hw(struct drm_device *dev)
11587 {
11588         intel_prepare_ddi(dev);
11589
11590         intel_init_clock_gating(dev);
11591
11592         intel_reset_dpio(dev);
11593
11594         intel_enable_gt_powersave(dev);
11595 }
11596
11597 void intel_modeset_suspend_hw(struct drm_device *dev)
11598 {
11599         intel_suspend_hw(dev);
11600 }
11601
11602 void intel_modeset_init(struct drm_device *dev)
11603 {
11604         struct drm_i915_private *dev_priv = dev->dev_private;
11605         int sprite, ret;
11606         enum pipe pipe;
11607         struct intel_crtc *crtc;
11608
11609         drm_mode_config_init(dev);
11610
11611         dev->mode_config.min_width = 0;
11612         dev->mode_config.min_height = 0;
11613
11614         dev->mode_config.preferred_depth = 24;
11615         dev->mode_config.prefer_shadow = 1;
11616
11617         dev->mode_config.funcs = &intel_mode_funcs;
11618
11619         intel_init_quirks(dev);
11620
11621         intel_init_pm(dev);
11622
11623         if (INTEL_INFO(dev)->num_pipes == 0)
11624                 return;
11625
11626         intel_init_display(dev);
11627
11628         if (IS_GEN2(dev)) {
11629                 dev->mode_config.max_width = 2048;
11630                 dev->mode_config.max_height = 2048;
11631         } else if (IS_GEN3(dev)) {
11632                 dev->mode_config.max_width = 4096;
11633                 dev->mode_config.max_height = 4096;
11634         } else {
11635                 dev->mode_config.max_width = 8192;
11636                 dev->mode_config.max_height = 8192;
11637         }
11638
11639         if (IS_GEN2(dev)) {
11640                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
11641                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
11642         } else {
11643                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
11644                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
11645         }
11646
11647         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
11648
11649         DRM_DEBUG_KMS("%d display pipe%s available.\n",
11650                       INTEL_INFO(dev)->num_pipes,
11651                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
11652
11653         for_each_pipe(pipe) {
11654                 intel_crtc_init(dev, pipe);
11655                 for_each_sprite(pipe, sprite) {
11656                         ret = intel_plane_init(dev, pipe, sprite);
11657                         if (ret)
11658                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
11659                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
11660                 }
11661         }
11662
11663         intel_init_dpio(dev);
11664         intel_reset_dpio(dev);
11665
11666         intel_cpu_pll_init(dev);
11667         intel_shared_dpll_init(dev);
11668
11669         /* Just disable it once at startup */
11670         i915_disable_vga(dev);
11671         intel_setup_outputs(dev);
11672
11673         /* Just in case the BIOS is doing something questionable. */
11674         intel_disable_fbc(dev);
11675
11676         mutex_lock(&dev->mode_config.mutex);
11677         intel_modeset_setup_hw_state(dev, false);
11678         mutex_unlock(&dev->mode_config.mutex);
11679
11680         for_each_intel_crtc(dev, crtc) {
11681                 if (!crtc->active)
11682                         continue;
11683
11684                 /*
11685                  * Note that reserving the BIOS fb up front prevents us
11686                  * from stuffing other stolen allocations like the ring
11687                  * on top.  This prevents some ugliness at boot time, and
11688                  * can even allow for smooth boot transitions if the BIOS
11689                  * fb is large enough for the active pipe configuration.
11690                  */
11691                 if (dev_priv->display.get_plane_config) {
11692                         dev_priv->display.get_plane_config(crtc,
11693                                                            &crtc->plane_config);
11694                         /*
11695                          * If the fb is shared between multiple heads, we'll
11696                          * just get the first one.
11697                          */
11698                         intel_find_plane_obj(crtc, &crtc->plane_config);
11699                 }
11700         }
11701 }
11702
11703 static void
11704 intel_connector_break_all_links(struct intel_connector *connector)
11705 {
11706         connector->base.dpms = DRM_MODE_DPMS_OFF;
11707         connector->base.encoder = NULL;
11708         connector->encoder->connectors_active = false;
11709         connector->encoder->base.crtc = NULL;
11710 }
11711
11712 static void intel_enable_pipe_a(struct drm_device *dev)
11713 {
11714         struct intel_connector *connector;
11715         struct drm_connector *crt = NULL;
11716         struct intel_load_detect_pipe load_detect_temp;
11717
11718         /* We can't just switch on the pipe A, we need to set things up with a
11719          * proper mode and output configuration. As a gross hack, enable pipe A
11720          * by enabling the load detect pipe once. */
11721         list_for_each_entry(connector,
11722                             &dev->mode_config.connector_list,
11723                             base.head) {
11724                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
11725                         crt = &connector->base;
11726                         break;
11727                 }
11728         }
11729
11730         if (!crt)
11731                 return;
11732
11733         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
11734                 intel_release_load_detect_pipe(crt, &load_detect_temp);
11735
11736
11737 }
11738
11739 static bool
11740 intel_check_plane_mapping(struct intel_crtc *crtc)
11741 {
11742         struct drm_device *dev = crtc->base.dev;
11743         struct drm_i915_private *dev_priv = dev->dev_private;
11744         u32 reg, val;
11745
11746         if (INTEL_INFO(dev)->num_pipes == 1)
11747                 return true;
11748
11749         reg = DSPCNTR(!crtc->plane);
11750         val = I915_READ(reg);
11751
11752         if ((val & DISPLAY_PLANE_ENABLE) &&
11753             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
11754                 return false;
11755
11756         return true;
11757 }
11758
11759 static void intel_sanitize_crtc(struct intel_crtc *crtc)
11760 {
11761         struct drm_device *dev = crtc->base.dev;
11762         struct drm_i915_private *dev_priv = dev->dev_private;
11763         u32 reg;
11764
11765         /* Clear any frame start delays used for debugging left by the BIOS */
11766         reg = PIPECONF(crtc->config.cpu_transcoder);
11767         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
11768
11769         /* We need to sanitize the plane -> pipe mapping first because this will
11770          * disable the crtc (and hence change the state) if it is wrong. Note
11771          * that gen4+ has a fixed plane -> pipe mapping.  */
11772         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
11773                 struct intel_connector *connector;
11774                 bool plane;
11775
11776                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
11777                               crtc->base.base.id);
11778
11779                 /* Pipe has the wrong plane attached and the plane is active.
11780                  * Temporarily change the plane mapping and disable everything
11781                  * ...  */
11782                 plane = crtc->plane;
11783                 crtc->plane = !plane;
11784                 dev_priv->display.crtc_disable(&crtc->base);
11785                 crtc->plane = plane;
11786
11787                 /* ... and break all links. */
11788                 list_for_each_entry(connector, &dev->mode_config.connector_list,
11789                                     base.head) {
11790                         if (connector->encoder->base.crtc != &crtc->base)
11791                                 continue;
11792
11793                         intel_connector_break_all_links(connector);
11794                 }
11795
11796                 WARN_ON(crtc->active);
11797                 crtc->base.enabled = false;
11798         }
11799
11800         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
11801             crtc->pipe == PIPE_A && !crtc->active) {
11802                 /* BIOS forgot to enable pipe A, this mostly happens after
11803                  * resume. Force-enable the pipe to fix this, the update_dpms
11804                  * call below we restore the pipe to the right state, but leave
11805                  * the required bits on. */
11806                 intel_enable_pipe_a(dev);
11807         }
11808
11809         /* Adjust the state of the output pipe according to whether we
11810          * have active connectors/encoders. */
11811         intel_crtc_update_dpms(&crtc->base);
11812
11813         if (crtc->active != crtc->base.enabled) {
11814                 struct intel_encoder *encoder;
11815
11816                 /* This can happen either due to bugs in the get_hw_state
11817                  * functions or because the pipe is force-enabled due to the
11818                  * pipe A quirk. */
11819                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
11820                               crtc->base.base.id,
11821                               crtc->base.enabled ? "enabled" : "disabled",
11822                               crtc->active ? "enabled" : "disabled");
11823
11824                 crtc->base.enabled = crtc->active;
11825
11826                 /* Because we only establish the connector -> encoder ->
11827                  * crtc links if something is active, this means the
11828                  * crtc is now deactivated. Break the links. connector
11829                  * -> encoder links are only establish when things are
11830                  *  actually up, hence no need to break them. */
11831                 WARN_ON(crtc->active);
11832
11833                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
11834                         WARN_ON(encoder->connectors_active);
11835                         encoder->base.crtc = NULL;
11836                 }
11837         }
11838         if (crtc->active) {
11839                 /*
11840                  * We start out with underrun reporting disabled to avoid races.
11841                  * For correct bookkeeping mark this on active crtcs.
11842                  *
11843                  * No protection against concurrent access is required - at
11844                  * worst a fifo underrun happens which also sets this to false.
11845                  */
11846                 crtc->cpu_fifo_underrun_disabled = true;
11847                 crtc->pch_fifo_underrun_disabled = true;
11848         }
11849 }
11850
11851 static void intel_sanitize_encoder(struct intel_encoder *encoder)
11852 {
11853         struct intel_connector *connector;
11854         struct drm_device *dev = encoder->base.dev;
11855
11856         /* We need to check both for a crtc link (meaning that the
11857          * encoder is active and trying to read from a pipe) and the
11858          * pipe itself being active. */
11859         bool has_active_crtc = encoder->base.crtc &&
11860                 to_intel_crtc(encoder->base.crtc)->active;
11861
11862         if (encoder->connectors_active && !has_active_crtc) {
11863                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
11864                               encoder->base.base.id,
11865                               drm_get_encoder_name(&encoder->base));
11866
11867                 /* Connector is active, but has no active pipe. This is
11868                  * fallout from our resume register restoring. Disable
11869                  * the encoder manually again. */
11870                 if (encoder->base.crtc) {
11871                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
11872                                       encoder->base.base.id,
11873                                       drm_get_encoder_name(&encoder->base));
11874                         encoder->disable(encoder);
11875                 }
11876
11877                 /* Inconsistent output/port/pipe state happens presumably due to
11878                  * a bug in one of the get_hw_state functions. Or someplace else
11879                  * in our code, like the register restore mess on resume. Clamp
11880                  * things to off as a safer default. */
11881                 list_for_each_entry(connector,
11882                                     &dev->mode_config.connector_list,
11883                                     base.head) {
11884                         if (connector->encoder != encoder)
11885                                 continue;
11886
11887                         intel_connector_break_all_links(connector);
11888                 }
11889         }
11890         /* Enabled encoders without active connectors will be fixed in
11891          * the crtc fixup. */
11892 }
11893
11894 void i915_redisable_vga_power_on(struct drm_device *dev)
11895 {
11896         struct drm_i915_private *dev_priv = dev->dev_private;
11897         u32 vga_reg = i915_vgacntrl_reg(dev);
11898
11899         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
11900                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
11901                 i915_disable_vga(dev);
11902         }
11903 }
11904
11905 void i915_redisable_vga(struct drm_device *dev)
11906 {
11907         struct drm_i915_private *dev_priv = dev->dev_private;
11908
11909         /* This function can be called both from intel_modeset_setup_hw_state or
11910          * at a very early point in our resume sequence, where the power well
11911          * structures are not yet restored. Since this function is at a very
11912          * paranoid "someone might have enabled VGA while we were not looking"
11913          * level, just check if the power well is enabled instead of trying to
11914          * follow the "don't touch the power well if we don't need it" policy
11915          * the rest of the driver uses. */
11916         if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
11917                 return;
11918
11919         i915_redisable_vga_power_on(dev);
11920 }
11921
11922 static bool primary_get_hw_state(struct intel_crtc *crtc)
11923 {
11924         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
11925
11926         if (!crtc->active)
11927                 return false;
11928
11929         return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
11930 }
11931
11932 static void intel_modeset_readout_hw_state(struct drm_device *dev)
11933 {
11934         struct drm_i915_private *dev_priv = dev->dev_private;
11935         enum pipe pipe;
11936         struct intel_crtc *crtc;
11937         struct intel_encoder *encoder;
11938         struct intel_connector *connector;
11939         int i;
11940
11941         for_each_intel_crtc(dev, crtc) {
11942                 memset(&crtc->config, 0, sizeof(crtc->config));
11943
11944                 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
11945
11946                 crtc->active = dev_priv->display.get_pipe_config(crtc,
11947                                                                  &crtc->config);
11948
11949                 crtc->base.enabled = crtc->active;
11950                 crtc->primary_enabled = primary_get_hw_state(crtc);
11951
11952                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
11953                               crtc->base.base.id,
11954                               crtc->active ? "enabled" : "disabled");
11955         }
11956
11957         /* FIXME: Smash this into the new shared dpll infrastructure. */
11958         if (HAS_DDI(dev))
11959                 intel_ddi_setup_hw_pll_state(dev);
11960
11961         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11962                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11963
11964                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
11965                 pll->active = 0;
11966                 for_each_intel_crtc(dev, crtc) {
11967                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11968                                 pll->active++;
11969                 }
11970                 pll->refcount = pll->active;
11971
11972                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
11973                               pll->name, pll->refcount, pll->on);
11974         }
11975
11976         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11977                             base.head) {
11978                 pipe = 0;
11979
11980                 if (encoder->get_hw_state(encoder, &pipe)) {
11981                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11982                         encoder->base.crtc = &crtc->base;
11983                         encoder->get_config(encoder, &crtc->config);
11984                 } else {
11985                         encoder->base.crtc = NULL;
11986                 }
11987
11988                 encoder->connectors_active = false;
11989                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
11990                               encoder->base.base.id,
11991                               drm_get_encoder_name(&encoder->base),
11992                               encoder->base.crtc ? "enabled" : "disabled",
11993                               pipe_name(pipe));
11994         }
11995
11996         list_for_each_entry(connector, &dev->mode_config.connector_list,
11997                             base.head) {
11998                 if (connector->get_hw_state(connector)) {
11999                         connector->base.dpms = DRM_MODE_DPMS_ON;
12000                         connector->encoder->connectors_active = true;
12001                         connector->base.encoder = &connector->encoder->base;
12002                 } else {
12003                         connector->base.dpms = DRM_MODE_DPMS_OFF;
12004                         connector->base.encoder = NULL;
12005                 }
12006                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
12007                               connector->base.base.id,
12008                               drm_get_connector_name(&connector->base),
12009                               connector->base.encoder ? "enabled" : "disabled");
12010         }
12011 }
12012
12013 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
12014  * and i915 state tracking structures. */
12015 void intel_modeset_setup_hw_state(struct drm_device *dev,
12016                                   bool force_restore)
12017 {
12018         struct drm_i915_private *dev_priv = dev->dev_private;
12019         enum pipe pipe;
12020         struct intel_crtc *crtc;
12021         struct intel_encoder *encoder;
12022         int i;
12023
12024         intel_modeset_readout_hw_state(dev);
12025
12026         /*
12027          * Now that we have the config, copy it to each CRTC struct
12028          * Note that this could go away if we move to using crtc_config
12029          * checking everywhere.
12030          */
12031         for_each_intel_crtc(dev, crtc) {
12032                 if (crtc->active && i915.fastboot) {
12033                         intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
12034                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
12035                                       crtc->base.base.id);
12036                         drm_mode_debug_printmodeline(&crtc->base.mode);
12037                 }
12038         }
12039
12040         /* HW state is read out, now we need to sanitize this mess. */
12041         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
12042                             base.head) {
12043                 intel_sanitize_encoder(encoder);
12044         }
12045
12046         for_each_pipe(pipe) {
12047                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
12048                 intel_sanitize_crtc(crtc);
12049                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
12050         }
12051
12052         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12053                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12054
12055                 if (!pll->on || pll->active)
12056                         continue;
12057
12058                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
12059
12060                 pll->disable(dev_priv, pll);
12061                 pll->on = false;
12062         }
12063
12064         if (HAS_PCH_SPLIT(dev))
12065                 ilk_wm_get_hw_state(dev);
12066
12067         if (force_restore) {
12068                 i915_redisable_vga(dev);
12069
12070                 /*
12071                  * We need to use raw interfaces for restoring state to avoid
12072                  * checking (bogus) intermediate states.
12073                  */
12074                 for_each_pipe(pipe) {
12075                         struct drm_crtc *crtc =
12076                                 dev_priv->pipe_to_crtc_mapping[pipe];
12077
12078                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
12079                                          crtc->primary->fb);
12080                 }
12081         } else {
12082                 intel_modeset_update_staged_output_state(dev);
12083         }
12084
12085         intel_modeset_check_state(dev);
12086 }
12087
12088 void intel_modeset_gem_init(struct drm_device *dev)
12089 {
12090         struct drm_crtc *c;
12091         struct intel_framebuffer *fb;
12092
12093         mutex_lock(&dev->struct_mutex);
12094         intel_init_gt_powersave(dev);
12095         mutex_unlock(&dev->struct_mutex);
12096
12097         intel_modeset_init_hw(dev);
12098
12099         intel_setup_overlay(dev);
12100
12101         /*
12102          * Make sure any fbs we allocated at startup are properly
12103          * pinned & fenced.  When we do the allocation it's too early
12104          * for this.
12105          */
12106         mutex_lock(&dev->struct_mutex);
12107         for_each_crtc(dev, c) {
12108                 if (!c->primary->fb)
12109                         continue;
12110
12111                 fb = to_intel_framebuffer(c->primary->fb);
12112                 if (intel_pin_and_fence_fb_obj(dev, fb->obj, NULL)) {
12113                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
12114                                   to_intel_crtc(c)->pipe);
12115                         drm_framebuffer_unreference(c->primary->fb);
12116                         c->primary->fb = NULL;
12117                 }
12118         }
12119         mutex_unlock(&dev->struct_mutex);
12120 }
12121
12122 void intel_connector_unregister(struct intel_connector *intel_connector)
12123 {
12124         struct drm_connector *connector = &intel_connector->base;
12125
12126         intel_panel_destroy_backlight(connector);
12127         drm_sysfs_connector_remove(connector);
12128 }
12129
12130 void intel_modeset_cleanup(struct drm_device *dev)
12131 {
12132         struct drm_i915_private *dev_priv = dev->dev_private;
12133         struct drm_crtc *crtc;
12134         struct drm_connector *connector;
12135
12136         /*
12137          * Interrupts and polling as the first thing to avoid creating havoc.
12138          * Too much stuff here (turning of rps, connectors, ...) would
12139          * experience fancy races otherwise.
12140          */
12141         drm_irq_uninstall(dev);
12142         cancel_work_sync(&dev_priv->hotplug_work);
12143         /*
12144          * Due to the hpd irq storm handling the hotplug work can re-arm the
12145          * poll handlers. Hence disable polling after hpd handling is shut down.
12146          */
12147         drm_kms_helper_poll_fini(dev);
12148
12149         mutex_lock(&dev->struct_mutex);
12150
12151         intel_unregister_dsm_handler();
12152
12153         for_each_crtc(dev, crtc) {
12154                 /* Skip inactive CRTCs */
12155                 if (!crtc->primary->fb)
12156                         continue;
12157
12158                 intel_increase_pllclock(crtc);
12159         }
12160
12161         intel_disable_fbc(dev);
12162
12163         intel_disable_gt_powersave(dev);
12164
12165         ironlake_teardown_rc6(dev);
12166
12167         mutex_unlock(&dev->struct_mutex);
12168
12169         /* flush any delayed tasks or pending work */
12170         flush_scheduled_work();
12171
12172         /* destroy the backlight and sysfs files before encoders/connectors */
12173         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12174                 struct intel_connector *intel_connector;
12175
12176                 intel_connector = to_intel_connector(connector);
12177                 intel_connector->unregister(intel_connector);
12178         }
12179
12180         drm_mode_config_cleanup(dev);
12181
12182         intel_cleanup_overlay(dev);
12183
12184         mutex_lock(&dev->struct_mutex);
12185         intel_cleanup_gt_powersave(dev);
12186         mutex_unlock(&dev->struct_mutex);
12187 }
12188
12189 /*
12190  * Return which encoder is currently attached for connector.
12191  */
12192 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
12193 {
12194         return &intel_attached_encoder(connector)->base;
12195 }
12196
12197 void intel_connector_attach_encoder(struct intel_connector *connector,
12198                                     struct intel_encoder *encoder)
12199 {
12200         connector->encoder = encoder;
12201         drm_mode_connector_attach_encoder(&connector->base,
12202                                           &encoder->base);
12203 }
12204
12205 /*
12206  * set vga decode state - true == enable VGA decode
12207  */
12208 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
12209 {
12210         struct drm_i915_private *dev_priv = dev->dev_private;
12211         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
12212         u16 gmch_ctrl;
12213
12214         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
12215                 DRM_ERROR("failed to read control word\n");
12216                 return -EIO;
12217         }
12218
12219         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
12220                 return 0;
12221
12222         if (state)
12223                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
12224         else
12225                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
12226
12227         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
12228                 DRM_ERROR("failed to write control word\n");
12229                 return -EIO;
12230         }
12231
12232         return 0;
12233 }
12234
12235 struct intel_display_error_state {
12236
12237         u32 power_well_driver;
12238
12239         int num_transcoders;
12240
12241         struct intel_cursor_error_state {
12242                 u32 control;
12243                 u32 position;
12244                 u32 base;
12245                 u32 size;
12246         } cursor[I915_MAX_PIPES];
12247
12248         struct intel_pipe_error_state {
12249                 bool power_domain_on;
12250                 u32 source;
12251                 u32 stat;
12252         } pipe[I915_MAX_PIPES];
12253
12254         struct intel_plane_error_state {
12255                 u32 control;
12256                 u32 stride;
12257                 u32 size;
12258                 u32 pos;
12259                 u32 addr;
12260                 u32 surface;
12261                 u32 tile_offset;
12262         } plane[I915_MAX_PIPES];
12263
12264         struct intel_transcoder_error_state {
12265                 bool power_domain_on;
12266                 enum transcoder cpu_transcoder;
12267
12268                 u32 conf;
12269
12270                 u32 htotal;
12271                 u32 hblank;
12272                 u32 hsync;
12273                 u32 vtotal;
12274                 u32 vblank;
12275                 u32 vsync;
12276         } transcoder[4];
12277 };
12278
12279 struct intel_display_error_state *
12280 intel_display_capture_error_state(struct drm_device *dev)
12281 {
12282         struct drm_i915_private *dev_priv = dev->dev_private;
12283         struct intel_display_error_state *error;
12284         int transcoders[] = {
12285                 TRANSCODER_A,
12286                 TRANSCODER_B,
12287                 TRANSCODER_C,
12288                 TRANSCODER_EDP,
12289         };
12290         int i;
12291
12292         if (INTEL_INFO(dev)->num_pipes == 0)
12293                 return NULL;
12294
12295         error = kzalloc(sizeof(*error), GFP_ATOMIC);
12296         if (error == NULL)
12297                 return NULL;
12298
12299         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
12300                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
12301
12302         for_each_pipe(i) {
12303                 error->pipe[i].power_domain_on =
12304                         intel_display_power_enabled_sw(dev_priv,
12305                                                        POWER_DOMAIN_PIPE(i));
12306                 if (!error->pipe[i].power_domain_on)
12307                         continue;
12308
12309                 error->cursor[i].control = I915_READ(CURCNTR(i));
12310                 error->cursor[i].position = I915_READ(CURPOS(i));
12311                 error->cursor[i].base = I915_READ(CURBASE(i));
12312
12313                 error->plane[i].control = I915_READ(DSPCNTR(i));
12314                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
12315                 if (INTEL_INFO(dev)->gen <= 3) {
12316                         error->plane[i].size = I915_READ(DSPSIZE(i));
12317                         error->plane[i].pos = I915_READ(DSPPOS(i));
12318                 }
12319                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
12320                         error->plane[i].addr = I915_READ(DSPADDR(i));
12321                 if (INTEL_INFO(dev)->gen >= 4) {
12322                         error->plane[i].surface = I915_READ(DSPSURF(i));
12323                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
12324                 }
12325
12326                 error->pipe[i].source = I915_READ(PIPESRC(i));
12327
12328                 if (!HAS_PCH_SPLIT(dev))
12329                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
12330         }
12331
12332         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
12333         if (HAS_DDI(dev_priv->dev))
12334                 error->num_transcoders++; /* Account for eDP. */
12335
12336         for (i = 0; i < error->num_transcoders; i++) {
12337                 enum transcoder cpu_transcoder = transcoders[i];
12338
12339                 error->transcoder[i].power_domain_on =
12340                         intel_display_power_enabled_sw(dev_priv,
12341                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
12342                 if (!error->transcoder[i].power_domain_on)
12343                         continue;
12344
12345                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
12346
12347                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
12348                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
12349                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
12350                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
12351                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
12352                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
12353                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
12354         }
12355
12356         return error;
12357 }
12358
12359 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
12360
12361 void
12362 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
12363                                 struct drm_device *dev,
12364                                 struct intel_display_error_state *error)
12365 {
12366         int i;
12367
12368         if (!error)
12369                 return;
12370
12371         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
12372         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
12373                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
12374                            error->power_well_driver);
12375         for_each_pipe(i) {
12376                 err_printf(m, "Pipe [%d]:\n", i);
12377                 err_printf(m, "  Power: %s\n",
12378                            error->pipe[i].power_domain_on ? "on" : "off");
12379                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
12380                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
12381
12382                 err_printf(m, "Plane [%d]:\n", i);
12383                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
12384                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
12385                 if (INTEL_INFO(dev)->gen <= 3) {
12386                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
12387                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
12388                 }
12389                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
12390                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
12391                 if (INTEL_INFO(dev)->gen >= 4) {
12392                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
12393                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
12394                 }
12395
12396                 err_printf(m, "Cursor [%d]:\n", i);
12397                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
12398                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
12399                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
12400         }
12401
12402         for (i = 0; i < error->num_transcoders; i++) {
12403                 err_printf(m, "CPU transcoder: %c\n",
12404                            transcoder_name(error->transcoder[i].cpu_transcoder));
12405                 err_printf(m, "  Power: %s\n",
12406                            error->transcoder[i].power_domain_on ? "on" : "off");
12407                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
12408                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
12409                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
12410                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
12411                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
12412                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
12413                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
12414         }
12415 }