drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 #define DIV_ROUND_CLOSEST_ULL(ll, d)    \
  45         ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
  46
  47 static void intel_increase_pllclock(struct drm_crtc *crtc);
  48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  49
  50 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  51                                 struct intel_crtc_config *pipe_config);
  52 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  53                                    struct intel_crtc_config *pipe_config);
  54
  55 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  56                           int x, int y, struct drm_framebuffer *old_fb);
  57 static int intel_framebuffer_init(struct drm_device *dev,
  58                                   struct intel_framebuffer *ifb,
  59                                   struct drm_mode_fb_cmd2 *mode_cmd,
  60                                   struct drm_i915_gem_object *obj);
  61 static void intel_dp_set_m_n(struct intel_crtc *crtc);
  62 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  63 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  64 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  65                                          struct intel_link_m_n *m_n);
  66 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
  67 static void haswell_set_pipeconf(struct drm_crtc *crtc);
  68 static void intel_set_pipe_csc(struct drm_crtc *crtc);
  69 static void vlv_prepare_pll(struct intel_crtc *crtc);
  70
  71 typedef struct {
  72         int     min, max;
  73 } intel_range_t;
  74
  75 typedef struct {
  76         int     dot_limit;
  77         int     p2_slow, p2_fast;
  78 } intel_p2_t;
  79
  80 typedef struct intel_limit intel_limit_t;
  81 struct intel_limit {
  82         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  83         intel_p2_t          p2;
  84 };
  85
  86 int
  87 intel_pch_rawclk(struct drm_device *dev)
  88 {
  89         struct drm_i915_private *dev_priv = dev->dev_private;
  90
  91         WARN_ON(!HAS_PCH_SPLIT(dev));
  92
  93         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  94 }
  95
  96 static inline u32 /* units of 100MHz */
  97 intel_fdi_link_freq(struct drm_device *dev)
  98 {
  99         if (IS_GEN5(dev)) {
 100                 struct drm_i915_private *dev_priv = dev->dev_private;
 101                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 102         } else
 103                 return 27;
 104 }
 105
 106 static const intel_limit_t intel_limits_i8xx_dac = {
 107         .dot = { .min = 25000, .max = 350000 },
 108         .vco = { .min = 908000, .max = 1512000 },
 109         .n = { .min = 2, .max = 16 },
 110         .m = { .min = 96, .max = 140 },
 111         .m1 = { .min = 18, .max = 26 },
 112         .m2 = { .min = 6, .max = 16 },
 113         .p = { .min = 4, .max = 128 },
 114         .p1 = { .min = 2, .max = 33 },
 115         .p2 = { .dot_limit = 165000,
 116                 .p2_slow = 4, .p2_fast = 2 },
 117 };
 118
 119 static const intel_limit_t intel_limits_i8xx_dvo = {
 120         .dot = { .min = 25000, .max = 350000 },
 121         .vco = { .min = 908000, .max = 1512000 },
 122         .n = { .min = 2, .max = 16 },
 123         .m = { .min = 96, .max = 140 },
 124         .m1 = { .min = 18, .max = 26 },
 125         .m2 = { .min = 6, .max = 16 },
 126         .p = { .min = 4, .max = 128 },
 127         .p1 = { .min = 2, .max = 33 },
 128         .p2 = { .dot_limit = 165000,
 129                 .p2_slow = 4, .p2_fast = 4 },
 130 };
 131
 132 static const intel_limit_t intel_limits_i8xx_lvds = {
 133         .dot = { .min = 25000, .max = 350000 },
 134         .vco = { .min = 908000, .max = 1512000 },
 135         .n = { .min = 2, .max = 16 },
 136         .m = { .min = 96, .max = 140 },
 137         .m1 = { .min = 18, .max = 26 },
 138         .m2 = { .min = 6, .max = 16 },
 139         .p = { .min = 4, .max = 128 },
 140         .p1 = { .min = 1, .max = 6 },
 141         .p2 = { .dot_limit = 165000,
 142                 .p2_slow = 14, .p2_fast = 7 },
 143 };
 144
 145 static const intel_limit_t intel_limits_i9xx_sdvo = {
 146         .dot = { .min = 20000, .max = 400000 },
 147         .vco = { .min = 1400000, .max = 2800000 },
 148         .n = { .min = 1, .max = 6 },
 149         .m = { .min = 70, .max = 120 },
 150         .m1 = { .min = 8, .max = 18 },
 151         .m2 = { .min = 3, .max = 7 },
 152         .p = { .min = 5, .max = 80 },
 153         .p1 = { .min = 1, .max = 8 },
 154         .p2 = { .dot_limit = 200000,
 155                 .p2_slow = 10, .p2_fast = 5 },
 156 };
 157
 158 static const intel_limit_t intel_limits_i9xx_lvds = {
 159         .dot = { .min = 20000, .max = 400000 },
 160         .vco = { .min = 1400000, .max = 2800000 },
 161         .n = { .min = 1, .max = 6 },
 162         .m = { .min = 70, .max = 120 },
 163         .m1 = { .min = 8, .max = 18 },
 164         .m2 = { .min = 3, .max = 7 },
 165         .p = { .min = 7, .max = 98 },
 166         .p1 = { .min = 1, .max = 8 },
 167         .p2 = { .dot_limit = 112000,
 168                 .p2_slow = 14, .p2_fast = 7 },
 169 };
 170
 171
 172 static const intel_limit_t intel_limits_g4x_sdvo = {
 173         .dot = { .min = 25000, .max = 270000 },
 174         .vco = { .min = 1750000, .max = 3500000},
 175         .n = { .min = 1, .max = 4 },
 176         .m = { .min = 104, .max = 138 },
 177         .m1 = { .min = 17, .max = 23 },
 178         .m2 = { .min = 5, .max = 11 },
 179         .p = { .min = 10, .max = 30 },
 180         .p1 = { .min = 1, .max = 3},
 181         .p2 = { .dot_limit = 270000,
 182                 .p2_slow = 10,
 183                 .p2_fast = 10
 184         },
 185 };
 186
 187 static const intel_limit_t intel_limits_g4x_hdmi = {
 188         .dot = { .min = 22000, .max = 400000 },
 189         .vco = { .min = 1750000, .max = 3500000},
 190         .n = { .min = 1, .max = 4 },
 191         .m = { .min = 104, .max = 138 },
 192         .m1 = { .min = 16, .max = 23 },
 193         .m2 = { .min = 5, .max = 11 },
 194         .p = { .min = 5, .max = 80 },
 195         .p1 = { .min = 1, .max = 8},
 196         .p2 = { .dot_limit = 165000,
 197                 .p2_slow = 10, .p2_fast = 5 },
 198 };
 199
 200 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 201         .dot = { .min = 20000, .max = 115000 },
 202         .vco = { .min = 1750000, .max = 3500000 },
 203         .n = { .min = 1, .max = 3 },
 204         .m = { .min = 104, .max = 138 },
 205         .m1 = { .min = 17, .max = 23 },
 206         .m2 = { .min = 5, .max = 11 },
 207         .p = { .min = 28, .max = 112 },
 208         .p1 = { .min = 2, .max = 8 },
 209         .p2 = { .dot_limit = 0,
 210                 .p2_slow = 14, .p2_fast = 14
 211         },
 212 };
 213
 214 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 215         .dot = { .min = 80000, .max = 224000 },
 216         .vco = { .min = 1750000, .max = 3500000 },
 217         .n = { .min = 1, .max = 3 },
 218         .m = { .min = 104, .max = 138 },
 219         .m1 = { .min = 17, .max = 23 },
 220         .m2 = { .min = 5, .max = 11 },
 221         .p = { .min = 14, .max = 42 },
 222         .p1 = { .min = 2, .max = 6 },
 223         .p2 = { .dot_limit = 0,
 224                 .p2_slow = 7, .p2_fast = 7
 225         },
 226 };
 227
 228 static const intel_limit_t intel_limits_pineview_sdvo = {
 229         .dot = { .min = 20000, .max = 400000},
 230         .vco = { .min = 1700000, .max = 3500000 },
 231         /* Pineview's Ncounter is a ring counter */
 232         .n = { .min = 3, .max = 6 },
 233         .m = { .min = 2, .max = 256 },
 234         /* Pineview only has one combined m divider, which we treat as m2. */
 235         .m1 = { .min = 0, .max = 0 },
 236         .m2 = { .min = 0, .max = 254 },
 237         .p = { .min = 5, .max = 80 },
 238         .p1 = { .min = 1, .max = 8 },
 239         .p2 = { .dot_limit = 200000,
 240                 .p2_slow = 10, .p2_fast = 5 },
 241 };
 242
 243 static const intel_limit_t intel_limits_pineview_lvds = {
 244         .dot = { .min = 20000, .max = 400000 },
 245         .vco = { .min = 1700000, .max = 3500000 },
 246         .n = { .min = 3, .max = 6 },
 247         .m = { .min = 2, .max = 256 },
 248         .m1 = { .min = 0, .max = 0 },
 249         .m2 = { .min = 0, .max = 254 },
 250         .p = { .min = 7, .max = 112 },
 251         .p1 = { .min = 1, .max = 8 },
 252         .p2 = { .dot_limit = 112000,
 253                 .p2_slow = 14, .p2_fast = 14 },
 254 };
 255
 256 /* Ironlake / Sandybridge
 257  *
 258  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 259  * the range value for them is (actual_value - 2).
 260  */
 261 static const intel_limit_t intel_limits_ironlake_dac = {
 262         .dot = { .min = 25000, .max = 350000 },
 263         .vco = { .min = 1760000, .max = 3510000 },
 264         .n = { .min = 1, .max = 5 },
 265         .m = { .min = 79, .max = 127 },
 266         .m1 = { .min = 12, .max = 22 },
 267         .m2 = { .min = 5, .max = 9 },
 268         .p = { .min = 5, .max = 80 },
 269         .p1 = { .min = 1, .max = 8 },
 270         .p2 = { .dot_limit = 225000,
 271                 .p2_slow = 10, .p2_fast = 5 },
 272 };
 273
 274 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 275         .dot = { .min = 25000, .max = 350000 },
 276         .vco = { .min = 1760000, .max = 3510000 },
 277         .n = { .min = 1, .max = 3 },
 278         .m = { .min = 79, .max = 118 },
 279         .m1 = { .min = 12, .max = 22 },
 280         .m2 = { .min = 5, .max = 9 },
 281         .p = { .min = 28, .max = 112 },
 282         .p1 = { .min = 2, .max = 8 },
 283         .p2 = { .dot_limit = 225000,
 284                 .p2_slow = 14, .p2_fast = 14 },
 285 };
 286
 287 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 288         .dot = { .min = 25000, .max = 350000 },
 289         .vco = { .min = 1760000, .max = 3510000 },
 290         .n = { .min = 1, .max = 3 },
 291         .m = { .min = 79, .max = 127 },
 292         .m1 = { .min = 12, .max = 22 },
 293         .m2 = { .min = 5, .max = 9 },
 294         .p = { .min = 14, .max = 56 },
 295         .p1 = { .min = 2, .max = 8 },
 296         .p2 = { .dot_limit = 225000,
 297                 .p2_slow = 7, .p2_fast = 7 },
 298 };
 299
 300 /* LVDS 100mhz refclk limits. */
 301 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 302         .dot = { .min = 25000, .max = 350000 },
 303         .vco = { .min = 1760000, .max = 3510000 },
 304         .n = { .min = 1, .max = 2 },
 305         .m = { .min = 79, .max = 126 },
 306         .m1 = { .min = 12, .max = 22 },
 307         .m2 = { .min = 5, .max = 9 },
 308         .p = { .min = 28, .max = 112 },
 309         .p1 = { .min = 2, .max = 8 },
 310         .p2 = { .dot_limit = 225000,
 311                 .p2_slow = 14, .p2_fast = 14 },
 312 };
 313
 314 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 315         .dot = { .min = 25000, .max = 350000 },
 316         .vco = { .min = 1760000, .max = 3510000 },
 317         .n = { .min = 1, .max = 3 },
 318         .m = { .min = 79, .max = 126 },
 319         .m1 = { .min = 12, .max = 22 },
 320         .m2 = { .min = 5, .max = 9 },
 321         .p = { .min = 14, .max = 42 },
 322         .p1 = { .min = 2, .max = 6 },
 323         .p2 = { .dot_limit = 225000,
 324                 .p2_slow = 7, .p2_fast = 7 },
 325 };
 326
 327 static const intel_limit_t intel_limits_vlv = {
 328          /*
 329           * These are the data rate limits (measured in fast clocks)
 330           * since those are the strictest limits we have. The fast
 331           * clock and actual rate limits are more relaxed, so checking
 332           * them would make no difference.
 333           */
 334         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 335         .vco = { .min = 4000000, .max = 6000000 },
 336         .n = { .min = 1, .max = 7 },
 337         .m1 = { .min = 2, .max = 3 },
 338         .m2 = { .min = 11, .max = 156 },
 339         .p1 = { .min = 2, .max = 3 },
 340         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 341 };
 342
 343 static const intel_limit_t intel_limits_chv = {
 344         /*
 345          * These are the data rate limits (measured in fast clocks)
 346          * since those are the strictest limits we have.  The fast
 347          * clock and actual rate limits are more relaxed, so checking
 348          * them would make no difference.
 349          */
 350         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 351         .vco = { .min = 4860000, .max = 6700000 },
 352         .n = { .min = 1, .max = 1 },
 353         .m1 = { .min = 2, .max = 2 },
 354         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 355         .p1 = { .min = 2, .max = 4 },
 356         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 357 };
 358
 359 static void vlv_clock(int refclk, intel_clock_t *clock)
 360 {
 361         clock->m = clock->m1 * clock->m2;
 362         clock->p = clock->p1 * clock->p2;
 363         if (WARN_ON(clock->n == 0 || clock->p == 0))
 364                 return;
 365         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 366         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 367 }
 368
 369 /**
 370  * Returns whether any output on the specified pipe is of the specified type
 371  */
 372 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 373 {
 374         struct drm_device *dev = crtc->dev;
 375         struct intel_encoder *encoder;
 376
 377         for_each_encoder_on_crtc(dev, crtc, encoder)
 378                 if (encoder->type == type)
 379                         return true;
 380
 381         return false;
 382 }
 383
 384 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 385                                                 int refclk)
 386 {
 387         struct drm_device *dev = crtc->dev;
 388         const intel_limit_t *limit;
 389
 390         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 391                 if (intel_is_dual_link_lvds(dev)) {
 392                         if (refclk == 100000)
 393                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 394                         else
 395                                 limit = &intel_limits_ironlake_dual_lvds;
 396                 } else {
 397                         if (refclk == 100000)
 398                                 limit = &intel_limits_ironlake_single_lvds_100m;
 399                         else
 400                                 limit = &intel_limits_ironlake_single_lvds;
 401                 }
 402         } else
 403                 limit = &intel_limits_ironlake_dac;
 404
 405         return limit;
 406 }
 407
 408 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 409 {
 410         struct drm_device *dev = crtc->dev;
 411         const intel_limit_t *limit;
 412
 413         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 414                 if (intel_is_dual_link_lvds(dev))
 415                         limit = &intel_limits_g4x_dual_channel_lvds;
 416                 else
 417                         limit = &intel_limits_g4x_single_channel_lvds;
 418         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 419                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 420                 limit = &intel_limits_g4x_hdmi;
 421         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 422                 limit = &intel_limits_g4x_sdvo;
 423         } else /* The option is for other outputs */
 424                 limit = &intel_limits_i9xx_sdvo;
 425
 426         return limit;
 427 }
 428
 429 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 430 {
 431         struct drm_device *dev = crtc->dev;
 432         const intel_limit_t *limit;
 433
 434         if (HAS_PCH_SPLIT(dev))
 435                 limit = intel_ironlake_limit(crtc, refclk);
 436         else if (IS_G4X(dev)) {
 437                 limit = intel_g4x_limit(crtc);
 438         } else if (IS_PINEVIEW(dev)) {
 439                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 440                         limit = &intel_limits_pineview_lvds;
 441                 else
 442                         limit = &intel_limits_pineview_sdvo;
 443         } else if (IS_CHERRYVIEW(dev)) {
 444                 limit = &intel_limits_chv;
 445         } else if (IS_VALLEYVIEW(dev)) {
 446                 limit = &intel_limits_vlv;
 447         } else if (!IS_GEN2(dev)) {
 448                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 449                         limit = &intel_limits_i9xx_lvds;
 450                 else
 451                         limit = &intel_limits_i9xx_sdvo;
 452         } else {
 453                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 454                         limit = &intel_limits_i8xx_lvds;
 455                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 456                         limit = &intel_limits_i8xx_dvo;
 457                 else
 458                         limit = &intel_limits_i8xx_dac;
 459         }
 460         return limit;
 461 }
 462
 463 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 464 static void pineview_clock(int refclk, intel_clock_t *clock)
 465 {
 466         clock->m = clock->m2 + 2;
 467         clock->p = clock->p1 * clock->p2;
 468         if (WARN_ON(clock->n == 0 || clock->p == 0))
 469                 return;
 470         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 471         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 472 }
 473
 474 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 475 {
 476         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 477 }
 478
 479 static void i9xx_clock(int refclk, intel_clock_t *clock)
 480 {
 481         clock->m = i9xx_dpll_compute_m(clock);
 482         clock->p = clock->p1 * clock->p2;
 483         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 484                 return;
 485         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 486         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 487 }
 488
 489 static void chv_clock(int refclk, intel_clock_t *clock)
 490 {
 491         clock->m = clock->m1 * clock->m2;
 492         clock->p = clock->p1 * clock->p2;
 493         if (WARN_ON(clock->n == 0 || clock->p == 0))
 494                 return;
 495         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 496                         clock->n << 22);
 497         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 498 }
 499
 500 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 501 /**
 502  * Returns whether the given set of divisors are valid for a given refclk with
 503  * the given connectors.
 504  */
 505
 506 static bool intel_PLL_is_valid(struct drm_device *dev,
 507                                const intel_limit_t *limit,
 508                                const intel_clock_t *clock)
 509 {
 510         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 511                 INTELPllInvalid("n out of range\n");
 512         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 513                 INTELPllInvalid("p1 out of range\n");
 514         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 515                 INTELPllInvalid("m2 out of range\n");
 516         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 517                 INTELPllInvalid("m1 out of range\n");
 518
 519         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 520                 if (clock->m1 <= clock->m2)
 521                         INTELPllInvalid("m1 <= m2\n");
 522
 523         if (!IS_VALLEYVIEW(dev)) {
 524                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 525                         INTELPllInvalid("p out of range\n");
 526                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 527                         INTELPllInvalid("m out of range\n");
 528         }
 529
 530         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 531                 INTELPllInvalid("vco out of range\n");
 532         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 533          * connector, etc., rather than just a single range.
 534          */
 535         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 536                 INTELPllInvalid("dot out of range\n");
 537
 538         return true;
 539 }
 540
 541 static bool
 542 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 543                     int target, int refclk, intel_clock_t *match_clock,
 544                     intel_clock_t *best_clock)
 545 {
 546         struct drm_device *dev = crtc->dev;
 547         intel_clock_t clock;
 548         int err = target;
 549
 550         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 551                 /*
 552                  * For LVDS just rely on its current settings for dual-channel.
 553                  * We haven't figured out how to reliably set up different
 554                  * single/dual channel state, if we even can.
 555                  */
 556                 if (intel_is_dual_link_lvds(dev))
 557                         clock.p2 = limit->p2.p2_fast;
 558                 else
 559                         clock.p2 = limit->p2.p2_slow;
 560         } else {
 561                 if (target < limit->p2.dot_limit)
 562                         clock.p2 = limit->p2.p2_slow;
 563                 else
 564                         clock.p2 = limit->p2.p2_fast;
 565         }
 566
 567         memset(best_clock, 0, sizeof(*best_clock));
 568
 569         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 570              clock.m1++) {
 571                 for (clock.m2 = limit->m2.min;
 572                      clock.m2 <= limit->m2.max; clock.m2++) {
 573                         if (clock.m2 >= clock.m1)
 574                                 break;
 575                         for (clock.n = limit->n.min;
 576                              clock.n <= limit->n.max; clock.n++) {
 577                                 for (clock.p1 = limit->p1.min;
 578                                         clock.p1 <= limit->p1.max; clock.p1++) {
 579                                         int this_err;
 580
 581                                         i9xx_clock(refclk, &clock);
 582                                         if (!intel_PLL_is_valid(dev, limit,
 583                                                                 &clock))
 584                                                 continue;
 585                                         if (match_clock &&
 586                                             clock.p != match_clock->p)
 587                                                 continue;
 588
 589                                         this_err = abs(clock.dot - target);
 590                                         if (this_err < err) {
 591                                                 *best_clock = clock;
 592                                                 err = this_err;
 593                                         }
 594                                 }
 595                         }
 596                 }
 597         }
 598
 599         return (err != target);
 600 }
 601
 602 static bool
 603 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 604                    int target, int refclk, intel_clock_t *match_clock,
 605                    intel_clock_t *best_clock)
 606 {
 607         struct drm_device *dev = crtc->dev;
 608         intel_clock_t clock;
 609         int err = target;
 610
 611         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 612                 /*
 613                  * For LVDS just rely on its current settings for dual-channel.
 614                  * We haven't figured out how to reliably set up different
 615                  * single/dual channel state, if we even can.
 616                  */
 617                 if (intel_is_dual_link_lvds(dev))
 618                         clock.p2 = limit->p2.p2_fast;
 619                 else
 620                         clock.p2 = limit->p2.p2_slow;
 621         } else {
 622                 if (target < limit->p2.dot_limit)
 623                         clock.p2 = limit->p2.p2_slow;
 624                 else
 625                         clock.p2 = limit->p2.p2_fast;
 626         }
 627
 628         memset(best_clock, 0, sizeof(*best_clock));
 629
 630         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 631              clock.m1++) {
 632                 for (clock.m2 = limit->m2.min;
 633                      clock.m2 <= limit->m2.max; clock.m2++) {
 634                         for (clock.n = limit->n.min;
 635                              clock.n <= limit->n.max; clock.n++) {
 636                                 for (clock.p1 = limit->p1.min;
 637                                         clock.p1 <= limit->p1.max; clock.p1++) {
 638                                         int this_err;
 639
 640                                         pineview_clock(refclk, &clock);
 641                                         if (!intel_PLL_is_valid(dev, limit,
 642                                                                 &clock))
 643                                                 continue;
 644                                         if (match_clock &&
 645                                             clock.p != match_clock->p)
 646                                                 continue;
 647
 648                                         this_err = abs(clock.dot - target);
 649                                         if (this_err < err) {
 650                                                 *best_clock = clock;
 651                                                 err = this_err;
 652                                         }
 653                                 }
 654                         }
 655                 }
 656         }
 657
 658         return (err != target);
 659 }
 660
 661 static bool
 662 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 663                    int target, int refclk, intel_clock_t *match_clock,
 664                    intel_clock_t *best_clock)
 665 {
 666         struct drm_device *dev = crtc->dev;
 667         intel_clock_t clock;
 668         int max_n;
 669         bool found;
 670         /* approximately equals target * 0.00585 */
 671         int err_most = (target >> 8) + (target >> 9);
 672         found = false;
 673
 674         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 675                 if (intel_is_dual_link_lvds(dev))
 676                         clock.p2 = limit->p2.p2_fast;
 677                 else
 678                         clock.p2 = limit->p2.p2_slow;
 679         } else {
 680                 if (target < limit->p2.dot_limit)
 681                         clock.p2 = limit->p2.p2_slow;
 682                 else
 683                         clock.p2 = limit->p2.p2_fast;
 684         }
 685
 686         memset(best_clock, 0, sizeof(*best_clock));
 687         max_n = limit->n.max;
 688         /* based on hardware requirement, prefer smaller n to precision */
 689         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 690                 /* based on hardware requirement, prefere larger m1,m2 */
 691                 for (clock.m1 = limit->m1.max;
 692                      clock.m1 >= limit->m1.min; clock.m1--) {
 693                         for (clock.m2 = limit->m2.max;
 694                              clock.m2 >= limit->m2.min; clock.m2--) {
 695                                 for (clock.p1 = limit->p1.max;
 696                                      clock.p1 >= limit->p1.min; clock.p1--) {
 697                                         int this_err;
 698
 699                                         i9xx_clock(refclk, &clock);
 700                                         if (!intel_PLL_is_valid(dev, limit,
 701                                                                 &clock))
 702                                                 continue;
 703
 704                                         this_err = abs(clock.dot - target);
 705                                         if (this_err < err_most) {
 706                                                 *best_clock = clock;
 707                                                 err_most = this_err;
 708                                                 max_n = clock.n;
 709                                                 found = true;
 710                                         }
 711                                 }
 712                         }
 713                 }
 714         }
 715         return found;
 716 }
 717
 718 static bool
 719 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 720                    int target, int refclk, intel_clock_t *match_clock,
 721                    intel_clock_t *best_clock)
 722 {
 723         struct drm_device *dev = crtc->dev;
 724         intel_clock_t clock;
 725         unsigned int bestppm = 1000000;
 726         /* min update 19.2 MHz */
 727         int max_n = min(limit->n.max, refclk / 19200);
 728         bool found = false;
 729
 730         target *= 5; /* fast clock */
 731
 732         memset(best_clock, 0, sizeof(*best_clock));
 733
 734         /* based on hardware requirement, prefer smaller n to precision */
 735         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 736                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 737                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 738                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 739                                 clock.p = clock.p1 * clock.p2;
 740                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 741                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 742                                         unsigned int ppm, diff;
 743
 744                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 745                                                                      refclk * clock.m1);
 746
 747                                         vlv_clock(refclk, &clock);
 748
 749                                         if (!intel_PLL_is_valid(dev, limit,
 750                                                                 &clock))
 751                                                 continue;
 752
 753                                         diff = abs(clock.dot - target);
 754                                         ppm = div_u64(1000000ULL * diff, target);
 755
 756                                         if (ppm < 100 && clock.p > best_clock->p) {
 757                                                 bestppm = 0;
 758                                                 *best_clock = clock;
 759                                                 found = true;
 760                                         }
 761
 762                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 763                                                 bestppm = ppm;
 764                                                 *best_clock = clock;
 765                                                 found = true;
 766                                         }
 767                                 }
 768                         }
 769                 }
 770         }
 771
 772         return found;
 773 }
 774
 775 static bool
 776 chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 777                    int target, int refclk, intel_clock_t *match_clock,
 778                    intel_clock_t *best_clock)
 779 {
 780         struct drm_device *dev = crtc->dev;
 781         intel_clock_t clock;
 782         uint64_t m2;
 783         int found = false;
 784
 785         memset(best_clock, 0, sizeof(*best_clock));
 786
 787         /*
 788          * Based on hardware doc, the n always set to 1, and m1 always
 789          * set to 2.  If requires to support 200Mhz refclk, we need to
 790          * revisit this because n may not 1 anymore.
 791          */
 792         clock.n = 1, clock.m1 = 2;
 793         target *= 5;    /* fast clock */
 794
 795         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 796                 for (clock.p2 = limit->p2.p2_fast;
 797                                 clock.p2 >= limit->p2.p2_slow;
 798                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 799
 800                         clock.p = clock.p1 * clock.p2;
 801
 802                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 803                                         clock.n) << 22, refclk * clock.m1);
 804
 805                         if (m2 > INT_MAX/clock.m1)
 806                                 continue;
 807
 808                         clock.m2 = m2;
 809
 810                         chv_clock(refclk, &clock);
 811
 812                         if (!intel_PLL_is_valid(dev, limit, &clock))
 813                                 continue;
 814
 815                         /* based on hardware requirement, prefer bigger p
 816                          */
 817                         if (clock.p > best_clock->p) {
 818                                 *best_clock = clock;
 819                                 found = true;
 820                         }
 821                 }
 822         }
 823
 824         return found;
 825 }
 826
 827 bool intel_crtc_active(struct drm_crtc *crtc)
 828 {
 829         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 830
 831         /* Be paranoid as we can arrive here with only partial
 832          * state retrieved from the hardware during setup.
 833          *
 834          * We can ditch the adjusted_mode.crtc_clock check as soon
 835          * as Haswell has gained clock readout/fastboot support.
 836          *
 837          * We can ditch the crtc->primary->fb check as soon as we can
 838          * properly reconstruct framebuffers.
 839          */
 840         return intel_crtc->active && crtc->primary->fb &&
 841                 intel_crtc->config.adjusted_mode.crtc_clock;
 842 }
 843
 844 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 845                                              enum pipe pipe)
 846 {
 847         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 848         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 849
 850         return intel_crtc->config.cpu_transcoder;
 851 }
 852
 853 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
 854 {
 855         struct drm_i915_private *dev_priv = dev->dev_private;
 856         u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
 857
 858         frame = I915_READ(frame_reg);
 859
 860         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 861                 WARN(1, "vblank wait timed out\n");
 862 }
 863
 864 /**
 865  * intel_wait_for_vblank - wait for vblank on a given pipe
 866  * @dev: drm device
 867  * @pipe: pipe to wait for
 868  *
 869  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 870  * mode setting code.
 871  */
 872 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 873 {
 874         struct drm_i915_private *dev_priv = dev->dev_private;
 875         int pipestat_reg = PIPESTAT(pipe);
 876
 877         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 878                 g4x_wait_for_vblank(dev, pipe);
 879                 return;
 880         }
 881
 882         /* Clear existing vblank status. Note this will clear any other
 883          * sticky status fields as well.
 884          *
 885          * This races with i915_driver_irq_handler() with the result
 886          * that either function could miss a vblank event.  Here it is not
 887          * fatal, as we will either wait upon the next vblank interrupt or
 888          * timeout.  Generally speaking intel_wait_for_vblank() is only
 889          * called during modeset at which time the GPU should be idle and
 890          * should *not* be performing page flips and thus not waiting on
 891          * vblanks...
 892          * Currently, the result of us stealing a vblank from the irq
 893          * handler is that a single frame will be skipped during swapbuffers.
 894          */
 895         I915_WRITE(pipestat_reg,
 896                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 897
 898         /* Wait for vblank interrupt bit to set */
 899         if (wait_for(I915_READ(pipestat_reg) &
 900                      PIPE_VBLANK_INTERRUPT_STATUS,
 901                      50))
 902                 DRM_DEBUG_KMS("vblank wait timed out\n");
 903 }
 904
 905 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 906 {
 907         struct drm_i915_private *dev_priv = dev->dev_private;
 908         u32 reg = PIPEDSL(pipe);
 909         u32 line1, line2;
 910         u32 line_mask;
 911
 912         if (IS_GEN2(dev))
 913                 line_mask = DSL_LINEMASK_GEN2;
 914         else
 915                 line_mask = DSL_LINEMASK_GEN3;
 916
 917         line1 = I915_READ(reg) & line_mask;
 918         mdelay(5);
 919         line2 = I915_READ(reg) & line_mask;
 920
 921         return line1 == line2;
 922 }
 923
 924 /*
 925  * intel_wait_for_pipe_off - wait for pipe to turn off
 926  * @dev: drm device
 927  * @pipe: pipe to wait for
 928  *
 929  * After disabling a pipe, we can't wait for vblank in the usual way,
 930  * spinning on the vblank interrupt status bit, since we won't actually
 931  * see an interrupt when the pipe is disabled.
 932  *
 933  * On Gen4 and above:
 934  *   wait for the pipe register state bit to turn off
 935  *
 936  * Otherwise:
 937  *   wait for the display line value to settle (it usually
 938  *   ends up stopping at the start of the next frame).
 939  *
 940  */
 941 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 942 {
 943         struct drm_i915_private *dev_priv = dev->dev_private;
 944         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 945                                                                       pipe);
 946
 947         if (INTEL_INFO(dev)->gen >= 4) {
 948                 int reg = PIPECONF(cpu_transcoder);
 949
 950                 /* Wait for the Pipe State to go off */
 951                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 952                              100))
 953                         WARN(1, "pipe_off wait timed out\n");
 954         } else {
 955                 /* Wait for the display line to settle */
 956                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 957                         WARN(1, "pipe_off wait timed out\n");
 958         }
 959 }
 960
 961 /*
 962  * ibx_digital_port_connected - is the specified port connected?
 963  * @dev_priv: i915 private structure
 964  * @port: the port to test
 965  *
 966  * Returns true if @port is connected, false otherwise.
 967  */
 968 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 969                                 struct intel_digital_port *port)
 970 {
 971         u32 bit;
 972
 973         if (HAS_PCH_IBX(dev_priv->dev)) {
 974                 switch (port->port) {
 975                 case PORT_B:
 976                         bit = SDE_PORTB_HOTPLUG;
 977                         break;
 978                 case PORT_C:
 979                         bit = SDE_PORTC_HOTPLUG;
 980                         break;
 981                 case PORT_D:
 982                         bit = SDE_PORTD_HOTPLUG;
 983                         break;
 984                 default:
 985                         return true;
 986                 }
 987         } else {
 988                 switch (port->port) {
 989                 case PORT_B:
 990                         bit = SDE_PORTB_HOTPLUG_CPT;
 991                         break;
 992                 case PORT_C:
 993                         bit = SDE_PORTC_HOTPLUG_CPT;
 994                         break;
 995                 case PORT_D:
 996                         bit = SDE_PORTD_HOTPLUG_CPT;
 997                         break;
 998                 default:
 999                         return true;
1000                 }
1001         }
1002
1003         return I915_READ(SDEISR) & bit;
1004 }
1005
1006 static const char *state_string(bool enabled)
1007 {
1008         return enabled ? "on" : "off";
1009 }
1010
1011 /* Only for pre-ILK configs */
1012 void assert_pll(struct drm_i915_private *dev_priv,
1013                 enum pipe pipe, bool state)
1014 {
1015         int reg;
1016         u32 val;
1017         bool cur_state;
1018
1019         reg = DPLL(pipe);
1020         val = I915_READ(reg);
1021         cur_state = !!(val & DPLL_VCO_ENABLE);
1022         WARN(cur_state != state,
1023              "PLL state assertion failure (expected %s, current %s)\n",
1024              state_string(state), state_string(cur_state));
1025 }
1026
1027 /* XXX: the dsi pll is shared between MIPI DSI ports */
1028 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1029 {
1030         u32 val;
1031         bool cur_state;
1032
1033         mutex_lock(&dev_priv->dpio_lock);
1034         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1035         mutex_unlock(&dev_priv->dpio_lock);
1036
1037         cur_state = val & DSI_PLL_VCO_EN;
1038         WARN(cur_state != state,
1039              "DSI PLL state assertion failure (expected %s, current %s)\n",
1040              state_string(state), state_string(cur_state));
1041 }
1042 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1043 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1044
1045 struct intel_shared_dpll *
1046 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1047 {
1048         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1049
1050         if (crtc->config.shared_dpll < 0)
1051                 return NULL;
1052
1053         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1054 }
1055
1056 /* For ILK+ */
1057 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1058                         struct intel_shared_dpll *pll,
1059                         bool state)
1060 {
1061         bool cur_state;
1062         struct intel_dpll_hw_state hw_state;
1063
1064         if (HAS_PCH_LPT(dev_priv->dev)) {
1065                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1066                 return;
1067         }
1068
1069         if (WARN (!pll,
1070                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1071                 return;
1072
1073         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1074         WARN(cur_state != state,
1075              "%s assertion failure (expected %s, current %s)\n",
1076              pll->name, state_string(state), state_string(cur_state));
1077 }
1078
1079 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1080                           enum pipe pipe, bool state)
1081 {
1082         int reg;
1083         u32 val;
1084         bool cur_state;
1085         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1086                                                                       pipe);
1087
1088         if (HAS_DDI(dev_priv->dev)) {
1089                 /* DDI does not have a specific FDI_TX register */
1090                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1091                 val = I915_READ(reg);
1092                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1093         } else {
1094                 reg = FDI_TX_CTL(pipe);
1095                 val = I915_READ(reg);
1096                 cur_state = !!(val & FDI_TX_ENABLE);
1097         }
1098         WARN(cur_state != state,
1099              "FDI TX state assertion failure (expected %s, current %s)\n",
1100              state_string(state), state_string(cur_state));
1101 }
1102 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1103 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1104
1105 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1106                           enum pipe pipe, bool state)
1107 {
1108         int reg;
1109         u32 val;
1110         bool cur_state;
1111
1112         reg = FDI_RX_CTL(pipe);
1113         val = I915_READ(reg);
1114         cur_state = !!(val & FDI_RX_ENABLE);
1115         WARN(cur_state != state,
1116              "FDI RX state assertion failure (expected %s, current %s)\n",
1117              state_string(state), state_string(cur_state));
1118 }
1119 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1120 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1121
1122 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1123                                       enum pipe pipe)
1124 {
1125         int reg;
1126         u32 val;
1127
1128         /* ILK FDI PLL is always enabled */
1129         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1130                 return;
1131
1132         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1133         if (HAS_DDI(dev_priv->dev))
1134                 return;
1135
1136         reg = FDI_TX_CTL(pipe);
1137         val = I915_READ(reg);
1138         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1139 }
1140
1141 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1142                        enum pipe pipe, bool state)
1143 {
1144         int reg;
1145         u32 val;
1146         bool cur_state;
1147
1148         reg = FDI_RX_CTL(pipe);
1149         val = I915_READ(reg);
1150         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1151         WARN(cur_state != state,
1152              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1153              state_string(state), state_string(cur_state));
1154 }
1155
1156 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1157                                   enum pipe pipe)
1158 {
1159         int pp_reg, lvds_reg;
1160         u32 val;
1161         enum pipe panel_pipe = PIPE_A;
1162         bool locked = true;
1163
1164         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1165                 pp_reg = PCH_PP_CONTROL;
1166                 lvds_reg = PCH_LVDS;
1167         } else {
1168                 pp_reg = PP_CONTROL;
1169                 lvds_reg = LVDS;
1170         }
1171
1172         val = I915_READ(pp_reg);
1173         if (!(val & PANEL_POWER_ON) ||
1174             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1175                 locked = false;
1176
1177         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1178                 panel_pipe = PIPE_B;
1179
1180         WARN(panel_pipe == pipe && locked,
1181              "panel assertion failure, pipe %c regs locked\n",
1182              pipe_name(pipe));
1183 }
1184
1185 static void assert_cursor(struct drm_i915_private *dev_priv,
1186                           enum pipe pipe, bool state)
1187 {
1188         struct drm_device *dev = dev_priv->dev;
1189         bool cur_state;
1190
1191         if (IS_845G(dev) || IS_I865G(dev))
1192                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1193         else if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev))
1194                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1195         else
1196                 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1197
1198         WARN(cur_state != state,
1199              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1200              pipe_name(pipe), state_string(state), state_string(cur_state));
1201 }
1202 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1203 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1204
1205 void assert_pipe(struct drm_i915_private *dev_priv,
1206                  enum pipe pipe, bool state)
1207 {
1208         int reg;
1209         u32 val;
1210         bool cur_state;
1211         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1212                                                                       pipe);
1213
1214         /* if we need the pipe A quirk it must be always on */
1215         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1216                 state = true;
1217
1218         if (!intel_display_power_enabled(dev_priv,
1219                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1220                 cur_state = false;
1221         } else {
1222                 reg = PIPECONF(cpu_transcoder);
1223                 val = I915_READ(reg);
1224                 cur_state = !!(val & PIPECONF_ENABLE);
1225         }
1226
1227         WARN(cur_state != state,
1228              "pipe %c assertion failure (expected %s, current %s)\n",
1229              pipe_name(pipe), state_string(state), state_string(cur_state));
1230 }
1231
1232 static void assert_plane(struct drm_i915_private *dev_priv,
1233                          enum plane plane, bool state)
1234 {
1235         int reg;
1236         u32 val;
1237         bool cur_state;
1238
1239         reg = DSPCNTR(plane);
1240         val = I915_READ(reg);
1241         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1242         WARN(cur_state != state,
1243              "plane %c assertion failure (expected %s, current %s)\n",
1244              plane_name(plane), state_string(state), state_string(cur_state));
1245 }
1246
1247 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1248 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1249
1250 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1251                                    enum pipe pipe)
1252 {
1253         struct drm_device *dev = dev_priv->dev;
1254         int reg, i;
1255         u32 val;
1256         int cur_pipe;
1257
1258         /* Primary planes are fixed to pipes on gen4+ */
1259         if (INTEL_INFO(dev)->gen >= 4) {
1260                 reg = DSPCNTR(pipe);
1261                 val = I915_READ(reg);
1262                 WARN(val & DISPLAY_PLANE_ENABLE,
1263                      "plane %c assertion failure, should be disabled but not\n",
1264                      plane_name(pipe));
1265                 return;
1266         }
1267
1268         /* Need to check both planes against the pipe */
1269         for_each_pipe(i) {
1270                 reg = DSPCNTR(i);
1271                 val = I915_READ(reg);
1272                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1273                         DISPPLANE_SEL_PIPE_SHIFT;
1274                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1275                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1276                      plane_name(i), pipe_name(pipe));
1277         }
1278 }
1279
1280 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1281                                     enum pipe pipe)
1282 {
1283         struct drm_device *dev = dev_priv->dev;
1284         int reg, sprite;
1285         u32 val;
1286
1287         if (IS_VALLEYVIEW(dev)) {
1288                 for_each_sprite(pipe, sprite) {
1289                         reg = SPCNTR(pipe, sprite);
1290                         val = I915_READ(reg);
1291                         WARN(val & SP_ENABLE,
1292                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1293                              sprite_name(pipe, sprite), pipe_name(pipe));
1294                 }
1295         } else if (INTEL_INFO(dev)->gen >= 7) {
1296                 reg = SPRCTL(pipe);
1297                 val = I915_READ(reg);
1298                 WARN(val & SPRITE_ENABLE,
1299                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1300                      plane_name(pipe), pipe_name(pipe));
1301         } else if (INTEL_INFO(dev)->gen >= 5) {
1302                 reg = DVSCNTR(pipe);
1303                 val = I915_READ(reg);
1304                 WARN(val & DVS_ENABLE,
1305                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1306                      plane_name(pipe), pipe_name(pipe));
1307         }
1308 }
1309
1310 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1311 {
1312         u32 val;
1313         bool enabled;
1314
1315         WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1316
1317         val = I915_READ(PCH_DREF_CONTROL);
1318         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1319                             DREF_SUPERSPREAD_SOURCE_MASK));
1320         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1321 }
1322
1323 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1324                                            enum pipe pipe)
1325 {
1326         int reg;
1327         u32 val;
1328         bool enabled;
1329
1330         reg = PCH_TRANSCONF(pipe);
1331         val = I915_READ(reg);
1332         enabled = !!(val & TRANS_ENABLE);
1333         WARN(enabled,
1334              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1335              pipe_name(pipe));
1336 }
1337
1338 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1339                             enum pipe pipe, u32 port_sel, u32 val)
1340 {
1341         if ((val & DP_PORT_EN) == 0)
1342                 return false;
1343
1344         if (HAS_PCH_CPT(dev_priv->dev)) {
1345                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1346                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1347                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1348                         return false;
1349         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1350                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1351                         return false;
1352         } else {
1353                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1354                         return false;
1355         }
1356         return true;
1357 }
1358
1359 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1360                               enum pipe pipe, u32 val)
1361 {
1362         if ((val & SDVO_ENABLE) == 0)
1363                 return false;
1364
1365         if (HAS_PCH_CPT(dev_priv->dev)) {
1366                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1367                         return false;
1368         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1369                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1370                         return false;
1371         } else {
1372                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1373                         return false;
1374         }
1375         return true;
1376 }
1377
1378 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1379                               enum pipe pipe, u32 val)
1380 {
1381         if ((val & LVDS_PORT_EN) == 0)
1382                 return false;
1383
1384         if (HAS_PCH_CPT(dev_priv->dev)) {
1385                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1386                         return false;
1387         } else {
1388                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1389                         return false;
1390         }
1391         return true;
1392 }
1393
1394 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1395                               enum pipe pipe, u32 val)
1396 {
1397         if ((val & ADPA_DAC_ENABLE) == 0)
1398                 return false;
1399         if (HAS_PCH_CPT(dev_priv->dev)) {
1400                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1401                         return false;
1402         } else {
1403                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1404                         return false;
1405         }
1406         return true;
1407 }
1408
1409 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1410                                    enum pipe pipe, int reg, u32 port_sel)
1411 {
1412         u32 val = I915_READ(reg);
1413         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1414              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1415              reg, pipe_name(pipe));
1416
1417         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1418              && (val & DP_PIPEB_SELECT),
1419              "IBX PCH dp port still using transcoder B\n");
1420 }
1421
1422 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1423                                      enum pipe pipe, int reg)
1424 {
1425         u32 val = I915_READ(reg);
1426         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1427              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1428              reg, pipe_name(pipe));
1429
1430         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1431              && (val & SDVO_PIPE_B_SELECT),
1432              "IBX PCH hdmi port still using transcoder B\n");
1433 }
1434
1435 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1436                                       enum pipe pipe)
1437 {
1438         int reg;
1439         u32 val;
1440
1441         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1442         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1443         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1444
1445         reg = PCH_ADPA;
1446         val = I915_READ(reg);
1447         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1448              "PCH VGA enabled on transcoder %c, should be disabled\n",
1449              pipe_name(pipe));
1450
1451         reg = PCH_LVDS;
1452         val = I915_READ(reg);
1453         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1454              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1455              pipe_name(pipe));
1456
1457         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1458         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1459         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1460 }
1461
1462 static void intel_init_dpio(struct drm_device *dev)
1463 {
1464         struct drm_i915_private *dev_priv = dev->dev_private;
1465
1466         if (!IS_VALLEYVIEW(dev))
1467                 return;
1468
1469         /*
1470          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1471          * CHV x1 PHY (DP/HDMI D)
1472          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1473          */
1474         if (IS_CHERRYVIEW(dev)) {
1475                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1476                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1477         } else {
1478                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1479         }
1480 }
1481
1482 static void intel_reset_dpio(struct drm_device *dev)
1483 {
1484         struct drm_i915_private *dev_priv = dev->dev_private;
1485
1486         if (!IS_VALLEYVIEW(dev))
1487                 return;
1488
1489         /*
1490          * Enable the CRI clock source so we can get at the display and the
1491          * reference clock for VGA hotplug / manual detection.
1492          */
1493         I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
1494                    DPLL_REFA_CLK_ENABLE_VLV |
1495                    DPLL_INTEGRATED_CRI_CLK_VLV);
1496
1497         if (IS_CHERRYVIEW(dev)) {
1498                 enum dpio_phy phy;
1499                 u32 val;
1500
1501                 for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) {
1502                         /* Poll for phypwrgood signal */
1503                         if (wait_for(I915_READ(DISPLAY_PHY_STATUS) &
1504                                                 PHY_POWERGOOD(phy), 1))
1505                                 DRM_ERROR("Display PHY %d is not power up\n", phy);
1506
1507                         /*
1508                          * Deassert common lane reset for PHY.
1509                          *
1510                          * This should only be done on init and resume from S3
1511                          * with both PLLs disabled, or we risk losing DPIO and
1512                          * PLL synchronization.
1513                          */
1514                         val = I915_READ(DISPLAY_PHY_CONTROL);
1515                         I915_WRITE(DISPLAY_PHY_CONTROL,
1516                                 PHY_COM_LANE_RESET_DEASSERT(phy, val));
1517                 }
1518
1519         } else {
1520                 /*
1521                  * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1522                  *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1523                  *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1524                  *   b. The other bits such as sfr settings / modesel may all
1525                  *      be set to 0.
1526                  *
1527                  * This should only be done on init and resume from S3 with
1528                  * both PLLs disabled, or we risk losing DPIO and PLL
1529                  * synchronization.
1530                  */
1531                 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1532         }
1533 }
1534
1535 static void vlv_enable_pll(struct intel_crtc *crtc)
1536 {
1537         struct drm_device *dev = crtc->base.dev;
1538         struct drm_i915_private *dev_priv = dev->dev_private;
1539         int reg = DPLL(crtc->pipe);
1540         u32 dpll = crtc->config.dpll_hw_state.dpll;
1541
1542         assert_pipe_disabled(dev_priv, crtc->pipe);
1543
1544         /* No really, not for ILK+ */
1545         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1546
1547         /* PLL is protected by panel, make sure we can write it */
1548         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1549                 assert_panel_unlocked(dev_priv, crtc->pipe);
1550
1551         I915_WRITE(reg, dpll);
1552         POSTING_READ(reg);
1553         udelay(150);
1554
1555         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1556                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1557
1558         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1559         POSTING_READ(DPLL_MD(crtc->pipe));
1560
1561         /* We do this three times for luck */
1562         I915_WRITE(reg, dpll);
1563         POSTING_READ(reg);
1564         udelay(150); /* wait for warmup */
1565         I915_WRITE(reg, dpll);
1566         POSTING_READ(reg);
1567         udelay(150); /* wait for warmup */
1568         I915_WRITE(reg, dpll);
1569         POSTING_READ(reg);
1570         udelay(150); /* wait for warmup */
1571 }
1572
1573 static void chv_enable_pll(struct intel_crtc *crtc)
1574 {
1575         struct drm_device *dev = crtc->base.dev;
1576         struct drm_i915_private *dev_priv = dev->dev_private;
1577         int pipe = crtc->pipe;
1578         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1579         int dpll = DPLL(crtc->pipe);
1580         u32 tmp;
1581
1582         assert_pipe_disabled(dev_priv, crtc->pipe);
1583
1584         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1585
1586         mutex_lock(&dev_priv->dpio_lock);
1587
1588         /* Enable back the 10bit clock to display controller */
1589         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1590         tmp |= DPIO_DCLKP_EN;
1591         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1592
1593         /*
1594          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1595          */
1596         udelay(1);
1597
1598         /* Enable PLL */
1599         tmp = I915_READ(dpll);
1600         tmp |= DPLL_VCO_ENABLE;
1601         I915_WRITE(dpll, tmp);
1602
1603         /* Check PLL is locked */
1604         if (wait_for(((I915_READ(dpll) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1605                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1606
1607         /* Deassert soft data lane reset*/
1608         tmp = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(port));
1609         tmp |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1610         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), tmp);
1611
1612
1613         mutex_unlock(&dev_priv->dpio_lock);
1614 }
1615
1616 static void i9xx_enable_pll(struct intel_crtc *crtc)
1617 {
1618         struct drm_device *dev = crtc->base.dev;
1619         struct drm_i915_private *dev_priv = dev->dev_private;
1620         int reg = DPLL(crtc->pipe);
1621         u32 dpll = crtc->config.dpll_hw_state.dpll;
1622
1623         assert_pipe_disabled(dev_priv, crtc->pipe);
1624
1625         /* No really, not for ILK+ */
1626         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1627
1628         /* PLL is protected by panel, make sure we can write it */
1629         if (IS_MOBILE(dev) && !IS_I830(dev))
1630                 assert_panel_unlocked(dev_priv, crtc->pipe);
1631
1632         I915_WRITE(reg, dpll);
1633
1634         /* Wait for the clocks to stabilize. */
1635         POSTING_READ(reg);
1636         udelay(150);
1637
1638         if (INTEL_INFO(dev)->gen >= 4) {
1639                 I915_WRITE(DPLL_MD(crtc->pipe),
1640                            crtc->config.dpll_hw_state.dpll_md);
1641         } else {
1642                 /* The pixel multiplier can only be updated once the
1643                  * DPLL is enabled and the clocks are stable.
1644                  *
1645                  * So write it again.
1646                  */
1647                 I915_WRITE(reg, dpll);
1648         }
1649
1650         /* We do this three times for luck */
1651         I915_WRITE(reg, dpll);
1652         POSTING_READ(reg);
1653         udelay(150); /* wait for warmup */
1654         I915_WRITE(reg, dpll);
1655         POSTING_READ(reg);
1656         udelay(150); /* wait for warmup */
1657         I915_WRITE(reg, dpll);
1658         POSTING_READ(reg);
1659         udelay(150); /* wait for warmup */
1660 }
1661
1662 /**
1663  * i9xx_disable_pll - disable a PLL
1664  * @dev_priv: i915 private structure
1665  * @pipe: pipe PLL to disable
1666  *
1667  * Disable the PLL for @pipe, making sure the pipe is off first.
1668  *
1669  * Note!  This is for pre-ILK only.
1670  */
1671 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1672 {
1673         /* Don't disable pipe A or pipe A PLLs if needed */
1674         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1675                 return;
1676
1677         /* Make sure the pipe isn't still relying on us */
1678         assert_pipe_disabled(dev_priv, pipe);
1679
1680         I915_WRITE(DPLL(pipe), 0);
1681         POSTING_READ(DPLL(pipe));
1682 }
1683
1684 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1685 {
1686         u32 val = 0;
1687
1688         /* Make sure the pipe isn't still relying on us */
1689         assert_pipe_disabled(dev_priv, pipe);
1690
1691         /*
1692          * Leave integrated clock source and reference clock enabled for pipe B.
1693          * The latter is needed for VGA hotplug / manual detection.
1694          */
1695         if (pipe == PIPE_B)
1696                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1697         I915_WRITE(DPLL(pipe), val);
1698         POSTING_READ(DPLL(pipe));
1699
1700 }
1701
1702 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1703 {
1704         int dpll = DPLL(pipe);
1705         u32 val;
1706
1707         /* Set PLL en = 0 */
1708         val = I915_READ(dpll);
1709         val &= ~DPLL_VCO_ENABLE;
1710         I915_WRITE(dpll, val);
1711
1712 }
1713
1714 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1715                 struct intel_digital_port *dport)
1716 {
1717         u32 port_mask;
1718         int dpll_reg;
1719
1720         switch (dport->port) {
1721         case PORT_B:
1722                 port_mask = DPLL_PORTB_READY_MASK;
1723                 dpll_reg = DPLL(0);
1724                 break;
1725         case PORT_C:
1726                 port_mask = DPLL_PORTC_READY_MASK;
1727                 dpll_reg = DPLL(0);
1728                 break;
1729         case PORT_D:
1730                 port_mask = DPLL_PORTD_READY_MASK;
1731                 dpll_reg = DPIO_PHY_STATUS;
1732                 break;
1733         default:
1734                 BUG();
1735         }
1736
1737         if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1738                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1739                      port_name(dport->port), I915_READ(dpll_reg));
1740 }
1741
1742 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1743 {
1744         struct drm_device *dev = crtc->base.dev;
1745         struct drm_i915_private *dev_priv = dev->dev_private;
1746         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1747
1748         WARN_ON(!pll->refcount);
1749         if (pll->active == 0) {
1750                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1751                 WARN_ON(pll->on);
1752                 assert_shared_dpll_disabled(dev_priv, pll);
1753
1754                 pll->mode_set(dev_priv, pll);
1755         }
1756 }
1757
1758 /**
1759  * ironlake_enable_shared_dpll - enable PCH PLL
1760  * @dev_priv: i915 private structure
1761  * @pipe: pipe PLL to enable
1762  *
1763  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1764  * drives the transcoder clock.
1765  */
1766 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1767 {
1768         struct drm_device *dev = crtc->base.dev;
1769         struct drm_i915_private *dev_priv = dev->dev_private;
1770         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1771
1772         /* PCH PLLs only available on ILK, SNB and IVB */
1773         BUG_ON(INTEL_INFO(dev)->gen < 5);
1774         if (WARN_ON(pll == NULL))
1775                 return;
1776
1777         if (WARN_ON(pll->refcount == 0))
1778                 return;
1779
1780         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1781                       pll->name, pll->active, pll->on,
1782                       crtc->base.base.id);
1783
1784         if (pll->active++) {
1785                 WARN_ON(!pll->on);
1786                 assert_shared_dpll_enabled(dev_priv, pll);
1787                 return;
1788         }
1789         WARN_ON(pll->on);
1790
1791         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1792         pll->enable(dev_priv, pll);
1793         pll->on = true;
1794 }
1795
1796 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1797 {
1798         struct drm_device *dev = crtc->base.dev;
1799         struct drm_i915_private *dev_priv = dev->dev_private;
1800         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1801
1802         /* PCH only available on ILK+ */
1803         BUG_ON(INTEL_INFO(dev)->gen < 5);
1804         if (WARN_ON(pll == NULL))
1805                return;
1806
1807         if (WARN_ON(pll->refcount == 0))
1808                 return;
1809
1810         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1811                       pll->name, pll->active, pll->on,
1812                       crtc->base.base.id);
1813
1814         if (WARN_ON(pll->active == 0)) {
1815                 assert_shared_dpll_disabled(dev_priv, pll);
1816                 return;
1817         }
1818
1819         assert_shared_dpll_enabled(dev_priv, pll);
1820         WARN_ON(!pll->on);
1821         if (--pll->active)
1822                 return;
1823
1824         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1825         pll->disable(dev_priv, pll);
1826         pll->on = false;
1827 }
1828
1829 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1830                                            enum pipe pipe)
1831 {
1832         struct drm_device *dev = dev_priv->dev;
1833         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1834         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1835         uint32_t reg, val, pipeconf_val;
1836
1837         /* PCH only available on ILK+ */
1838         BUG_ON(INTEL_INFO(dev)->gen < 5);
1839
1840         /* Make sure PCH DPLL is enabled */
1841         assert_shared_dpll_enabled(dev_priv,
1842                                    intel_crtc_to_shared_dpll(intel_crtc));
1843
1844         /* FDI must be feeding us bits for PCH ports */
1845         assert_fdi_tx_enabled(dev_priv, pipe);
1846         assert_fdi_rx_enabled(dev_priv, pipe);
1847
1848         if (HAS_PCH_CPT(dev)) {
1849                 /* Workaround: Set the timing override bit before enabling the
1850                  * pch transcoder. */
1851                 reg = TRANS_CHICKEN2(pipe);
1852                 val = I915_READ(reg);
1853                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1854                 I915_WRITE(reg, val);
1855         }
1856
1857         reg = PCH_TRANSCONF(pipe);
1858         val = I915_READ(reg);
1859         pipeconf_val = I915_READ(PIPECONF(pipe));
1860
1861         if (HAS_PCH_IBX(dev_priv->dev)) {
1862                 /*
1863                  * make the BPC in transcoder be consistent with
1864                  * that in pipeconf reg.
1865                  */
1866                 val &= ~PIPECONF_BPC_MASK;
1867                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1868         }
1869
1870         val &= ~TRANS_INTERLACE_MASK;
1871         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1872                 if (HAS_PCH_IBX(dev_priv->dev) &&
1873                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1874                         val |= TRANS_LEGACY_INTERLACED_ILK;
1875                 else
1876                         val |= TRANS_INTERLACED;
1877         else
1878                 val |= TRANS_PROGRESSIVE;
1879
1880         I915_WRITE(reg, val | TRANS_ENABLE);
1881         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1882                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1883 }
1884
1885 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1886                                       enum transcoder cpu_transcoder)
1887 {
1888         u32 val, pipeconf_val;
1889
1890         /* PCH only available on ILK+ */
1891         BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1892
1893         /* FDI must be feeding us bits for PCH ports */
1894         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1895         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1896
1897         /* Workaround: set timing override bit. */
1898         val = I915_READ(_TRANSA_CHICKEN2);
1899         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1900         I915_WRITE(_TRANSA_CHICKEN2, val);
1901
1902         val = TRANS_ENABLE;
1903         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1904
1905         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1906             PIPECONF_INTERLACED_ILK)
1907                 val |= TRANS_INTERLACED;
1908         else
1909                 val |= TRANS_PROGRESSIVE;
1910
1911         I915_WRITE(LPT_TRANSCONF, val);
1912         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1913                 DRM_ERROR("Failed to enable PCH transcoder\n");
1914 }
1915
1916 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1917                                             enum pipe pipe)
1918 {
1919         struct drm_device *dev = dev_priv->dev;
1920         uint32_t reg, val;
1921
1922         /* FDI relies on the transcoder */
1923         assert_fdi_tx_disabled(dev_priv, pipe);
1924         assert_fdi_rx_disabled(dev_priv, pipe);
1925
1926         /* Ports must be off as well */
1927         assert_pch_ports_disabled(dev_priv, pipe);
1928
1929         reg = PCH_TRANSCONF(pipe);
1930         val = I915_READ(reg);
1931         val &= ~TRANS_ENABLE;
1932         I915_WRITE(reg, val);
1933         /* wait for PCH transcoder off, transcoder state */
1934         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1935                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1936
1937         if (!HAS_PCH_IBX(dev)) {
1938                 /* Workaround: Clear the timing override chicken bit again. */
1939                 reg = TRANS_CHICKEN2(pipe);
1940                 val = I915_READ(reg);
1941                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1942                 I915_WRITE(reg, val);
1943         }
1944 }
1945
1946 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1947 {
1948         u32 val;
1949
1950         val = I915_READ(LPT_TRANSCONF);
1951         val &= ~TRANS_ENABLE;
1952         I915_WRITE(LPT_TRANSCONF, val);
1953         /* wait for PCH transcoder off, transcoder state */
1954         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1955                 DRM_ERROR("Failed to disable PCH transcoder\n");
1956
1957         /* Workaround: clear timing override bit. */
1958         val = I915_READ(_TRANSA_CHICKEN2);
1959         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1960         I915_WRITE(_TRANSA_CHICKEN2, val);
1961 }
1962
1963 /**
1964  * intel_enable_pipe - enable a pipe, asserting requirements
1965  * @crtc: crtc responsible for the pipe
1966  *
1967  * Enable @crtc's pipe, making sure that various hardware specific requirements
1968  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1969  */
1970 static void intel_enable_pipe(struct intel_crtc *crtc)
1971 {
1972         struct drm_device *dev = crtc->base.dev;
1973         struct drm_i915_private *dev_priv = dev->dev_private;
1974         enum pipe pipe = crtc->pipe;
1975         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1976                                                                       pipe);
1977         enum pipe pch_transcoder;
1978         int reg;
1979         u32 val;
1980
1981         assert_planes_disabled(dev_priv, pipe);
1982         assert_cursor_disabled(dev_priv, pipe);
1983         assert_sprites_disabled(dev_priv, pipe);
1984
1985         if (HAS_PCH_LPT(dev_priv->dev))
1986                 pch_transcoder = TRANSCODER_A;
1987         else
1988                 pch_transcoder = pipe;
1989
1990         /*
1991          * A pipe without a PLL won't actually be able to drive bits from
1992          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1993          * need the check.
1994          */
1995         if (!HAS_PCH_SPLIT(dev_priv->dev))
1996                 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
1997                         assert_dsi_pll_enabled(dev_priv);
1998                 else
1999                         assert_pll_enabled(dev_priv, pipe);
2000         else {
2001                 if (crtc->config.has_pch_encoder) {
2002                         /* if driving the PCH, we need FDI enabled */
2003                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2004                         assert_fdi_tx_pll_enabled(dev_priv,
2005                                                   (enum pipe) cpu_transcoder);
2006                 }
2007                 /* FIXME: assert CPU port conditions for SNB+ */
2008         }
2009
2010         reg = PIPECONF(cpu_transcoder);
2011         val = I915_READ(reg);
2012         if (val & PIPECONF_ENABLE) {
2013                 WARN_ON(!(pipe == PIPE_A &&
2014                           dev_priv->quirks & QUIRK_PIPEA_FORCE));
2015                 return;
2016         }
2017
2018         I915_WRITE(reg, val | PIPECONF_ENABLE);
2019         POSTING_READ(reg);
2020 }
2021
2022 /**
2023  * intel_disable_pipe - disable a pipe, asserting requirements
2024  * @dev_priv: i915 private structure
2025  * @pipe: pipe to disable
2026  *
2027  * Disable @pipe, making sure that various hardware specific requirements
2028  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
2029  *
2030  * @pipe should be %PIPE_A or %PIPE_B.
2031  *
2032  * Will wait until the pipe has shut down before returning.
2033  */
2034 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
2035                                enum pipe pipe)
2036 {
2037         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2038                                                                       pipe);
2039         int reg;
2040         u32 val;
2041
2042         /*
2043          * Make sure planes won't keep trying to pump pixels to us,
2044          * or we might hang the display.
2045          */
2046         assert_planes_disabled(dev_priv, pipe);
2047         assert_cursor_disabled(dev_priv, pipe);
2048         assert_sprites_disabled(dev_priv, pipe);
2049
2050         /* Don't disable pipe A or pipe A PLLs if needed */
2051         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2052                 return;
2053
2054         reg = PIPECONF(cpu_transcoder);
2055         val = I915_READ(reg);
2056         if ((val & PIPECONF_ENABLE) == 0)
2057                 return;
2058
2059         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
2060         intel_wait_for_pipe_off(dev_priv->dev, pipe);
2061 }
2062
2063 /*
2064  * Plane regs are double buffered, going from enabled->disabled needs a
2065  * trigger in order to latch.  The display address reg provides this.
2066  */
2067 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2068                                enum plane plane)
2069 {
2070         struct drm_device *dev = dev_priv->dev;
2071         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2072
2073         I915_WRITE(reg, I915_READ(reg));
2074         POSTING_READ(reg);
2075 }
2076
2077 /**
2078  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2079  * @dev_priv: i915 private structure
2080  * @plane: plane to enable
2081  * @pipe: pipe being fed
2082  *
2083  * Enable @plane on @pipe, making sure that @pipe is running first.
2084  */
2085 static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
2086                                           enum plane plane, enum pipe pipe)
2087 {
2088         struct intel_crtc *intel_crtc =
2089                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2090         int reg;
2091         u32 val;
2092
2093         /* If the pipe isn't enabled, we can't pump pixels and may hang */
2094         assert_pipe_enabled(dev_priv, pipe);
2095
2096         if (intel_crtc->primary_enabled)
2097                 return;
2098
2099         intel_crtc->primary_enabled = true;
2100
2101         reg = DSPCNTR(plane);
2102         val = I915_READ(reg);
2103         WARN_ON(val & DISPLAY_PLANE_ENABLE);
2104
2105         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
2106         intel_flush_primary_plane(dev_priv, plane);
2107         intel_wait_for_vblank(dev_priv->dev, pipe);
2108 }
2109
2110 /**
2111  * intel_disable_primary_hw_plane - disable the primary hardware plane
2112  * @dev_priv: i915 private structure
2113  * @plane: plane to disable
2114  * @pipe: pipe consuming the data
2115  *
2116  * Disable @plane; should be an independent operation.
2117  */
2118 static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
2119                                            enum plane plane, enum pipe pipe)
2120 {
2121         struct intel_crtc *intel_crtc =
2122                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2123         int reg;
2124         u32 val;
2125
2126         if (!intel_crtc->primary_enabled)
2127                 return;
2128
2129         intel_crtc->primary_enabled = false;
2130
2131         reg = DSPCNTR(plane);
2132         val = I915_READ(reg);
2133         WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0);
2134
2135         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
2136         intel_flush_primary_plane(dev_priv, plane);
2137         intel_wait_for_vblank(dev_priv->dev, pipe);
2138 }
2139
2140 static bool need_vtd_wa(struct drm_device *dev)
2141 {
2142 #ifdef CONFIG_INTEL_IOMMU
2143         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2144                 return true;
2145 #endif
2146         return false;
2147 }
2148
2149 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2150 {
2151         int tile_height;
2152
2153         tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2154         return ALIGN(height, tile_height);
2155 }
2156
2157 int
2158 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2159                            struct drm_i915_gem_object *obj,
2160                            struct intel_ring_buffer *pipelined)
2161 {
2162         struct drm_i915_private *dev_priv = dev->dev_private;
2163         u32 alignment;
2164         int ret;
2165
2166         switch (obj->tiling_mode) {
2167         case I915_TILING_NONE:
2168                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2169                         alignment = 128 * 1024;
2170                 else if (INTEL_INFO(dev)->gen >= 4)
2171                         alignment = 4 * 1024;
2172                 else
2173                         alignment = 64 * 1024;
2174                 break;
2175         case I915_TILING_X:
2176                 /* pin() will align the object as required by fence */
2177                 alignment = 0;
2178                 break;
2179         case I915_TILING_Y:
2180                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2181                 return -EINVAL;
2182         default:
2183                 BUG();
2184         }
2185
2186         /* Note that the w/a also requires 64 PTE of padding following the
2187          * bo. We currently fill all unused PTE with the shadow page and so
2188          * we should always have valid PTE following the scanout preventing
2189          * the VT-d warning.
2190          */
2191         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2192                 alignment = 256 * 1024;
2193
2194         dev_priv->mm.interruptible = false;
2195         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2196         if (ret)
2197                 goto err_interruptible;
2198
2199         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2200          * fence, whereas 965+ only requires a fence if using
2201          * framebuffer compression.  For simplicity, we always install
2202          * a fence as the cost is not that onerous.
2203          */
2204         ret = i915_gem_object_get_fence(obj);
2205         if (ret)
2206                 goto err_unpin;
2207
2208         i915_gem_object_pin_fence(obj);
2209
2210         dev_priv->mm.interruptible = true;
2211         return 0;
2212
2213 err_unpin:
2214         i915_gem_object_unpin_from_display_plane(obj);
2215 err_interruptible:
2216         dev_priv->mm.interruptible = true;
2217         return ret;
2218 }
2219
2220 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2221 {
2222         i915_gem_object_unpin_fence(obj);
2223         i915_gem_object_unpin_from_display_plane(obj);
2224 }
2225
2226 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2227  * is assumed to be a power-of-two. */
2228 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2229                                              unsigned int tiling_mode,
2230                                              unsigned int cpp,
2231                                              unsigned int pitch)
2232 {
2233         if (tiling_mode != I915_TILING_NONE) {
2234                 unsigned int tile_rows, tiles;
2235
2236                 tile_rows = *y / 8;
2237                 *y %= 8;
2238
2239                 tiles = *x / (512/cpp);
2240                 *x %= 512/cpp;
2241
2242                 return tile_rows * pitch * 8 + tiles * 4096;
2243         } else {
2244                 unsigned int offset;
2245
2246                 offset = *y * pitch + *x * cpp;
2247                 *y = 0;
2248                 *x = (offset & 4095) / cpp;
2249                 return offset & -4096;
2250         }
2251 }
2252
2253 int intel_format_to_fourcc(int format)
2254 {
2255         switch (format) {
2256         case DISPPLANE_8BPP:
2257                 return DRM_FORMAT_C8;
2258         case DISPPLANE_BGRX555:
2259                 return DRM_FORMAT_XRGB1555;
2260         case DISPPLANE_BGRX565:
2261                 return DRM_FORMAT_RGB565;
2262         default:
2263         case DISPPLANE_BGRX888:
2264                 return DRM_FORMAT_XRGB8888;
2265         case DISPPLANE_RGBX888:
2266                 return DRM_FORMAT_XBGR8888;
2267         case DISPPLANE_BGRX101010:
2268                 return DRM_FORMAT_XRGB2101010;
2269         case DISPPLANE_RGBX101010:
2270                 return DRM_FORMAT_XBGR2101010;
2271         }
2272 }
2273
2274 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2275                                   struct intel_plane_config *plane_config)
2276 {
2277         struct drm_device *dev = crtc->base.dev;
2278         struct drm_i915_gem_object *obj = NULL;
2279         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2280         u32 base = plane_config->base;
2281
2282         if (plane_config->size == 0)
2283                 return false;
2284
2285         obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2286                                                              plane_config->size);
2287         if (!obj)
2288                 return false;
2289
2290         if (plane_config->tiled) {
2291                 obj->tiling_mode = I915_TILING_X;
2292                 obj->stride = crtc->base.primary->fb->pitches[0];
2293         }
2294
2295         mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2296         mode_cmd.width = crtc->base.primary->fb->width;
2297         mode_cmd.height = crtc->base.primary->fb->height;
2298         mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2299
2300         mutex_lock(&dev->struct_mutex);
2301
2302         if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2303                                    &mode_cmd, obj)) {
2304                 DRM_DEBUG_KMS("intel fb init failed\n");
2305                 goto out_unref_obj;
2306         }
2307
2308         mutex_unlock(&dev->struct_mutex);
2309
2310         DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2311         return true;
2312
2313 out_unref_obj:
2314         drm_gem_object_unreference(&obj->base);
2315         mutex_unlock(&dev->struct_mutex);
2316         return false;
2317 }
2318
2319 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2320                                  struct intel_plane_config *plane_config)
2321 {
2322         struct drm_device *dev = intel_crtc->base.dev;
2323         struct drm_crtc *c;
2324         struct intel_crtc *i;
2325         struct intel_framebuffer *fb;
2326
2327         if (!intel_crtc->base.primary->fb)
2328                 return;
2329
2330         if (intel_alloc_plane_obj(intel_crtc, plane_config))
2331                 return;
2332
2333         kfree(intel_crtc->base.primary->fb);
2334         intel_crtc->base.primary->fb = NULL;
2335
2336         /*
2337          * Failed to alloc the obj, check to see if we should share
2338          * an fb with another CRTC instead
2339          */
2340         for_each_crtc(dev, c) {
2341                 i = to_intel_crtc(c);
2342
2343                 if (c == &intel_crtc->base)
2344                         continue;
2345
2346                 if (!i->active || !c->primary->fb)
2347                         continue;
2348
2349                 fb = to_intel_framebuffer(c->primary->fb);
2350                 if (i915_gem_obj_ggtt_offset(fb->obj) == plane_config->base) {
2351                         drm_framebuffer_reference(c->primary->fb);
2352                         intel_crtc->base.primary->fb = c->primary->fb;
2353                         break;
2354                 }
2355         }
2356 }
2357
2358 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2359                                       struct drm_framebuffer *fb,
2360                                       int x, int y)
2361 {
2362         struct drm_device *dev = crtc->dev;
2363         struct drm_i915_private *dev_priv = dev->dev_private;
2364         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2365         struct intel_framebuffer *intel_fb;
2366         struct drm_i915_gem_object *obj;
2367         int plane = intel_crtc->plane;
2368         unsigned long linear_offset;
2369         u32 dspcntr;
2370         u32 reg;
2371
2372         intel_fb = to_intel_framebuffer(fb);
2373         obj = intel_fb->obj;
2374
2375         reg = DSPCNTR(plane);
2376         dspcntr = I915_READ(reg);
2377         /* Mask out pixel format bits in case we change it */
2378         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2379         switch (fb->pixel_format) {
2380         case DRM_FORMAT_C8:
2381                 dspcntr |= DISPPLANE_8BPP;
2382                 break;
2383         case DRM_FORMAT_XRGB1555:
2384         case DRM_FORMAT_ARGB1555:
2385                 dspcntr |= DISPPLANE_BGRX555;
2386                 break;
2387         case DRM_FORMAT_RGB565:
2388                 dspcntr |= DISPPLANE_BGRX565;
2389                 break;
2390         case DRM_FORMAT_XRGB8888:
2391         case DRM_FORMAT_ARGB8888:
2392                 dspcntr |= DISPPLANE_BGRX888;
2393                 break;
2394         case DRM_FORMAT_XBGR8888:
2395         case DRM_FORMAT_ABGR8888:
2396                 dspcntr |= DISPPLANE_RGBX888;
2397                 break;
2398         case DRM_FORMAT_XRGB2101010:
2399         case DRM_FORMAT_ARGB2101010:
2400                 dspcntr |= DISPPLANE_BGRX101010;
2401                 break;
2402         case DRM_FORMAT_XBGR2101010:
2403         case DRM_FORMAT_ABGR2101010:
2404                 dspcntr |= DISPPLANE_RGBX101010;
2405                 break;
2406         default:
2407                 BUG();
2408         }
2409
2410         if (INTEL_INFO(dev)->gen >= 4) {
2411                 if (obj->tiling_mode != I915_TILING_NONE)
2412                         dspcntr |= DISPPLANE_TILED;
2413                 else
2414                         dspcntr &= ~DISPPLANE_TILED;
2415         }
2416
2417         if (IS_G4X(dev))
2418                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2419
2420         I915_WRITE(reg, dspcntr);
2421
2422         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2423
2424         if (INTEL_INFO(dev)->gen >= 4) {
2425                 intel_crtc->dspaddr_offset =
2426                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2427                                                        fb->bits_per_pixel / 8,
2428                                                        fb->pitches[0]);
2429                 linear_offset -= intel_crtc->dspaddr_offset;
2430         } else {
2431                 intel_crtc->dspaddr_offset = linear_offset;
2432         }
2433
2434         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2435                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2436                       fb->pitches[0]);
2437         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2438         if (INTEL_INFO(dev)->gen >= 4) {
2439                 I915_WRITE(DSPSURF(plane),
2440                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2441                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2442                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2443         } else
2444                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2445         POSTING_READ(reg);
2446 }
2447
2448 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2449                                           struct drm_framebuffer *fb,
2450                                           int x, int y)
2451 {
2452         struct drm_device *dev = crtc->dev;
2453         struct drm_i915_private *dev_priv = dev->dev_private;
2454         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2455         struct intel_framebuffer *intel_fb;
2456         struct drm_i915_gem_object *obj;
2457         int plane = intel_crtc->plane;
2458         unsigned long linear_offset;
2459         u32 dspcntr;
2460         u32 reg;
2461
2462         intel_fb = to_intel_framebuffer(fb);
2463         obj = intel_fb->obj;
2464
2465         reg = DSPCNTR(plane);
2466         dspcntr = I915_READ(reg);
2467         /* Mask out pixel format bits in case we change it */
2468         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2469         switch (fb->pixel_format) {
2470         case DRM_FORMAT_C8:
2471                 dspcntr |= DISPPLANE_8BPP;
2472                 break;
2473         case DRM_FORMAT_RGB565:
2474                 dspcntr |= DISPPLANE_BGRX565;
2475                 break;
2476         case DRM_FORMAT_XRGB8888:
2477         case DRM_FORMAT_ARGB8888:
2478                 dspcntr |= DISPPLANE_BGRX888;
2479                 break;
2480         case DRM_FORMAT_XBGR8888:
2481         case DRM_FORMAT_ABGR8888:
2482                 dspcntr |= DISPPLANE_RGBX888;
2483                 break;
2484         case DRM_FORMAT_XRGB2101010:
2485         case DRM_FORMAT_ARGB2101010:
2486                 dspcntr |= DISPPLANE_BGRX101010;
2487                 break;
2488         case DRM_FORMAT_XBGR2101010:
2489         case DRM_FORMAT_ABGR2101010:
2490                 dspcntr |= DISPPLANE_RGBX101010;
2491                 break;
2492         default:
2493                 BUG();
2494         }
2495
2496         if (obj->tiling_mode != I915_TILING_NONE)
2497                 dspcntr |= DISPPLANE_TILED;
2498         else
2499                 dspcntr &= ~DISPPLANE_TILED;
2500
2501         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2502                 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2503         else
2504                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2505
2506         I915_WRITE(reg, dspcntr);
2507
2508         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2509         intel_crtc->dspaddr_offset =
2510                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2511                                                fb->bits_per_pixel / 8,
2512                                                fb->pitches[0]);
2513         linear_offset -= intel_crtc->dspaddr_offset;
2514
2515         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2516                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2517                       fb->pitches[0]);
2518         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2519         I915_WRITE(DSPSURF(plane),
2520                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2521         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2522                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2523         } else {
2524                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2525                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2526         }
2527         POSTING_READ(reg);
2528 }
2529
2530 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2531 static int
2532 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2533                            int x, int y, enum mode_set_atomic state)
2534 {
2535         struct drm_device *dev = crtc->dev;
2536         struct drm_i915_private *dev_priv = dev->dev_private;
2537
2538         if (dev_priv->display.disable_fbc)
2539                 dev_priv->display.disable_fbc(dev);
2540         intel_increase_pllclock(crtc);
2541
2542         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2543
2544         return 0;
2545 }
2546
2547 void intel_display_handle_reset(struct drm_device *dev)
2548 {
2549         struct drm_i915_private *dev_priv = dev->dev_private;
2550         struct drm_crtc *crtc;
2551
2552         /*
2553          * Flips in the rings have been nuked by the reset,
2554          * so complete all pending flips so that user space
2555          * will get its events and not get stuck.
2556          *
2557          * Also update the base address of all primary
2558          * planes to the the last fb to make sure we're
2559          * showing the correct fb after a reset.
2560          *
2561          * Need to make two loops over the crtcs so that we
2562          * don't try to grab a crtc mutex before the
2563          * pending_flip_queue really got woken up.
2564          */
2565
2566         for_each_crtc(dev, crtc) {
2567                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2568                 enum plane plane = intel_crtc->plane;
2569
2570                 intel_prepare_page_flip(dev, plane);
2571                 intel_finish_page_flip_plane(dev, plane);
2572         }
2573
2574         for_each_crtc(dev, crtc) {
2575                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2576
2577                 mutex_lock(&crtc->mutex);
2578                 /*
2579                  * FIXME: Once we have proper support for primary planes (and
2580                  * disabling them without disabling the entire crtc) allow again
2581                  * a NULL crtc->primary->fb.
2582                  */
2583                 if (intel_crtc->active && crtc->primary->fb)
2584                         dev_priv->display.update_primary_plane(crtc,
2585                                                                crtc->primary->fb,
2586                                                                crtc->x,
2587                                                                crtc->y);
2588                 mutex_unlock(&crtc->mutex);
2589         }
2590 }
2591
2592 static int
2593 intel_finish_fb(struct drm_framebuffer *old_fb)
2594 {
2595         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2596         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2597         bool was_interruptible = dev_priv->mm.interruptible;
2598         int ret;
2599
2600         /* Big Hammer, we also need to ensure that any pending
2601          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2602          * current scanout is retired before unpinning the old
2603          * framebuffer.
2604          *
2605          * This should only fail upon a hung GPU, in which case we
2606          * can safely continue.
2607          */
2608         dev_priv->mm.interruptible = false;
2609         ret = i915_gem_object_finish_gpu(obj);
2610         dev_priv->mm.interruptible = was_interruptible;
2611
2612         return ret;
2613 }
2614
2615 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2616 {
2617         struct drm_device *dev = crtc->dev;
2618         struct drm_i915_private *dev_priv = dev->dev_private;
2619         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2620         unsigned long flags;
2621         bool pending;
2622
2623         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2624             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2625                 return false;
2626
2627         spin_lock_irqsave(&dev->event_lock, flags);
2628         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2629         spin_unlock_irqrestore(&dev->event_lock, flags);
2630
2631         return pending;
2632 }
2633
2634 static int
2635 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2636                     struct drm_framebuffer *fb)
2637 {
2638         struct drm_device *dev = crtc->dev;
2639         struct drm_i915_private *dev_priv = dev->dev_private;
2640         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2641         struct drm_framebuffer *old_fb;
2642         int ret;
2643
2644         if (intel_crtc_has_pending_flip(crtc)) {
2645                 DRM_ERROR("pipe is still busy with an old pageflip\n");
2646                 return -EBUSY;
2647         }
2648
2649         /* no fb bound */
2650         if (!fb) {
2651                 DRM_ERROR("No FB bound\n");
2652                 return 0;
2653         }
2654
2655         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2656                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2657                           plane_name(intel_crtc->plane),
2658                           INTEL_INFO(dev)->num_pipes);
2659                 return -EINVAL;
2660         }
2661
2662         mutex_lock(&dev->struct_mutex);
2663         ret = intel_pin_and_fence_fb_obj(dev,
2664                                          to_intel_framebuffer(fb)->obj,
2665                                          NULL);
2666         mutex_unlock(&dev->struct_mutex);
2667         if (ret != 0) {
2668                 DRM_ERROR("pin & fence failed\n");
2669                 return ret;
2670         }
2671
2672         /*
2673          * Update pipe size and adjust fitter if needed: the reason for this is
2674          * that in compute_mode_changes we check the native mode (not the pfit
2675          * mode) to see if we can flip rather than do a full mode set. In the
2676          * fastboot case, we'll flip, but if we don't update the pipesrc and
2677          * pfit state, we'll end up with a big fb scanned out into the wrong
2678          * sized surface.
2679          *
2680          * To fix this properly, we need to hoist the checks up into
2681          * compute_mode_changes (or above), check the actual pfit state and
2682          * whether the platform allows pfit disable with pipe active, and only
2683          * then update the pipesrc and pfit state, even on the flip path.
2684          */
2685         if (i915.fastboot) {
2686                 const struct drm_display_mode *adjusted_mode =
2687                         &intel_crtc->config.adjusted_mode;
2688
2689                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2690                            ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2691                            (adjusted_mode->crtc_vdisplay - 1));
2692                 if (!intel_crtc->config.pch_pfit.enabled &&
2693                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2694                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2695                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2696                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2697                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2698                 }
2699                 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2700                 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2701         }
2702
2703         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2704
2705         old_fb = crtc->primary->fb;
2706         crtc->primary->fb = fb;
2707         crtc->x = x;
2708         crtc->y = y;
2709
2710         if (old_fb) {
2711                 if (intel_crtc->active && old_fb != fb)
2712                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2713                 mutex_lock(&dev->struct_mutex);
2714                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2715                 mutex_unlock(&dev->struct_mutex);
2716         }
2717
2718         mutex_lock(&dev->struct_mutex);
2719         intel_update_fbc(dev);
2720         intel_edp_psr_update(dev);
2721         mutex_unlock(&dev->struct_mutex);
2722
2723         return 0;
2724 }
2725
2726 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2727 {
2728         struct drm_device *dev = crtc->dev;
2729         struct drm_i915_private *dev_priv = dev->dev_private;
2730         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2731         int pipe = intel_crtc->pipe;
2732         u32 reg, temp;
2733
2734         /* enable normal train */
2735         reg = FDI_TX_CTL(pipe);
2736         temp = I915_READ(reg);
2737         if (IS_IVYBRIDGE(dev)) {
2738                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2739                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2740         } else {
2741                 temp &= ~FDI_LINK_TRAIN_NONE;
2742                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2743         }
2744         I915_WRITE(reg, temp);
2745
2746         reg = FDI_RX_CTL(pipe);
2747         temp = I915_READ(reg);
2748         if (HAS_PCH_CPT(dev)) {
2749                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2750                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2751         } else {
2752                 temp &= ~FDI_LINK_TRAIN_NONE;
2753                 temp |= FDI_LINK_TRAIN_NONE;
2754         }
2755         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2756
2757         /* wait one idle pattern time */
2758         POSTING_READ(reg);
2759         udelay(1000);
2760
2761         /* IVB wants error correction enabled */
2762         if (IS_IVYBRIDGE(dev))
2763                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2764                            FDI_FE_ERRC_ENABLE);
2765 }
2766
2767 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2768 {
2769         return crtc->base.enabled && crtc->active &&
2770                 crtc->config.has_pch_encoder;
2771 }
2772
2773 static void ivb_modeset_global_resources(struct drm_device *dev)
2774 {
2775         struct drm_i915_private *dev_priv = dev->dev_private;
2776         struct intel_crtc *pipe_B_crtc =
2777                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2778         struct intel_crtc *pipe_C_crtc =
2779                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2780         uint32_t temp;
2781
2782         /*
2783          * When everything is off disable fdi C so that we could enable fdi B
2784          * with all lanes. Note that we don't care about enabled pipes without
2785          * an enabled pch encoder.
2786          */
2787         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2788             !pipe_has_enabled_pch(pipe_C_crtc)) {
2789                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2790                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2791
2792                 temp = I915_READ(SOUTH_CHICKEN1);
2793                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2794                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2795                 I915_WRITE(SOUTH_CHICKEN1, temp);
2796         }
2797 }
2798
2799 /* The FDI link training functions for ILK/Ibexpeak. */
2800 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2801 {
2802         struct drm_device *dev = crtc->dev;
2803         struct drm_i915_private *dev_priv = dev->dev_private;
2804         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2805         int pipe = intel_crtc->pipe;
2806         u32 reg, temp, tries;
2807
2808         /* FDI needs bits from pipe first */
2809         assert_pipe_enabled(dev_priv, pipe);
2810
2811         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2812            for train result */
2813         reg = FDI_RX_IMR(pipe);
2814         temp = I915_READ(reg);
2815         temp &= ~FDI_RX_SYMBOL_LOCK;
2816         temp &= ~FDI_RX_BIT_LOCK;
2817         I915_WRITE(reg, temp);
2818         I915_READ(reg);
2819         udelay(150);
2820
2821         /* enable CPU FDI TX and PCH FDI RX */
2822         reg = FDI_TX_CTL(pipe);
2823         temp = I915_READ(reg);
2824         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2825         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2826         temp &= ~FDI_LINK_TRAIN_NONE;
2827         temp |= FDI_LINK_TRAIN_PATTERN_1;
2828         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2829
2830         reg = FDI_RX_CTL(pipe);
2831         temp = I915_READ(reg);
2832         temp &= ~FDI_LINK_TRAIN_NONE;
2833         temp |= FDI_LINK_TRAIN_PATTERN_1;
2834         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2835
2836         POSTING_READ(reg);
2837         udelay(150);
2838
2839         /* Ironlake workaround, enable clock pointer after FDI enable*/
2840         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2841         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2842                    FDI_RX_PHASE_SYNC_POINTER_EN);
2843
2844         reg = FDI_RX_IIR(pipe);
2845         for (tries = 0; tries < 5; tries++) {
2846                 temp = I915_READ(reg);
2847                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2848
2849                 if ((temp & FDI_RX_BIT_LOCK)) {
2850                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2851                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2852                         break;
2853                 }
2854         }
2855         if (tries == 5)
2856                 DRM_ERROR("FDI train 1 fail!\n");
2857
2858         /* Train 2 */
2859         reg = FDI_TX_CTL(pipe);
2860         temp = I915_READ(reg);
2861         temp &= ~FDI_LINK_TRAIN_NONE;
2862         temp |= FDI_LINK_TRAIN_PATTERN_2;
2863         I915_WRITE(reg, temp);
2864
2865         reg = FDI_RX_CTL(pipe);
2866         temp = I915_READ(reg);
2867         temp &= ~FDI_LINK_TRAIN_NONE;
2868         temp |= FDI_LINK_TRAIN_PATTERN_2;
2869         I915_WRITE(reg, temp);
2870
2871         POSTING_READ(reg);
2872         udelay(150);
2873
2874         reg = FDI_RX_IIR(pipe);
2875         for (tries = 0; tries < 5; tries++) {
2876                 temp = I915_READ(reg);
2877                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2878
2879                 if (temp & FDI_RX_SYMBOL_LOCK) {
2880                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2881                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2882                         break;
2883                 }
2884         }
2885         if (tries == 5)
2886                 DRM_ERROR("FDI train 2 fail!\n");
2887
2888         DRM_DEBUG_KMS("FDI train done\n");
2889
2890 }
2891
2892 static const int snb_b_fdi_train_param[] = {
2893         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2894         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2895         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2896         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2897 };
2898
2899 /* The FDI link training functions for SNB/Cougarpoint. */
2900 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2901 {
2902         struct drm_device *dev = crtc->dev;
2903         struct drm_i915_private *dev_priv = dev->dev_private;
2904         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2905         int pipe = intel_crtc->pipe;
2906         u32 reg, temp, i, retry;
2907
2908         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2909            for train result */
2910         reg = FDI_RX_IMR(pipe);
2911         temp = I915_READ(reg);
2912         temp &= ~FDI_RX_SYMBOL_LOCK;
2913         temp &= ~FDI_RX_BIT_LOCK;
2914         I915_WRITE(reg, temp);
2915
2916         POSTING_READ(reg);
2917         udelay(150);
2918
2919         /* enable CPU FDI TX and PCH FDI RX */
2920         reg = FDI_TX_CTL(pipe);
2921         temp = I915_READ(reg);
2922         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2923         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2924         temp &= ~FDI_LINK_TRAIN_NONE;
2925         temp |= FDI_LINK_TRAIN_PATTERN_1;
2926         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2927         /* SNB-B */
2928         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2929         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2930
2931         I915_WRITE(FDI_RX_MISC(pipe),
2932                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2933
2934         reg = FDI_RX_CTL(pipe);
2935         temp = I915_READ(reg);
2936         if (HAS_PCH_CPT(dev)) {
2937                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2938                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2939         } else {
2940                 temp &= ~FDI_LINK_TRAIN_NONE;
2941                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2942         }
2943         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2944
2945         POSTING_READ(reg);
2946         udelay(150);
2947
2948         for (i = 0; i < 4; i++) {
2949                 reg = FDI_TX_CTL(pipe);
2950                 temp = I915_READ(reg);
2951                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2952                 temp |= snb_b_fdi_train_param[i];
2953                 I915_WRITE(reg, temp);
2954
2955                 POSTING_READ(reg);
2956                 udelay(500);
2957
2958                 for (retry = 0; retry < 5; retry++) {
2959                         reg = FDI_RX_IIR(pipe);
2960                         temp = I915_READ(reg);
2961                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2962                         if (temp & FDI_RX_BIT_LOCK) {
2963                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2964                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2965                                 break;
2966                         }
2967                         udelay(50);
2968                 }
2969                 if (retry < 5)
2970                         break;
2971         }
2972         if (i == 4)
2973                 DRM_ERROR("FDI train 1 fail!\n");
2974
2975         /* Train 2 */
2976         reg = FDI_TX_CTL(pipe);
2977         temp = I915_READ(reg);
2978         temp &= ~FDI_LINK_TRAIN_NONE;
2979         temp |= FDI_LINK_TRAIN_PATTERN_2;
2980         if (IS_GEN6(dev)) {
2981                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2982                 /* SNB-B */
2983                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2984         }
2985         I915_WRITE(reg, temp);
2986
2987         reg = FDI_RX_CTL(pipe);
2988         temp = I915_READ(reg);
2989         if (HAS_PCH_CPT(dev)) {
2990                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2991                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2992         } else {
2993                 temp &= ~FDI_LINK_TRAIN_NONE;
2994                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2995         }
2996         I915_WRITE(reg, temp);
2997
2998         POSTING_READ(reg);
2999         udelay(150);
3000
3001         for (i = 0; i < 4; i++) {
3002                 reg = FDI_TX_CTL(pipe);
3003                 temp = I915_READ(reg);
3004                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3005                 temp |= snb_b_fdi_train_param[i];
3006                 I915_WRITE(reg, temp);
3007
3008                 POSTING_READ(reg);
3009                 udelay(500);
3010
3011                 for (retry = 0; retry < 5; retry++) {
3012                         reg = FDI_RX_IIR(pipe);
3013                         temp = I915_READ(reg);
3014                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3015                         if (temp & FDI_RX_SYMBOL_LOCK) {
3016                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3017                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3018                                 break;
3019                         }
3020                         udelay(50);
3021                 }
3022                 if (retry < 5)
3023                         break;
3024         }
3025         if (i == 4)
3026                 DRM_ERROR("FDI train 2 fail!\n");
3027
3028         DRM_DEBUG_KMS("FDI train done.\n");
3029 }
3030
3031 /* Manual link training for Ivy Bridge A0 parts */
3032 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3033 {
3034         struct drm_device *dev = crtc->dev;
3035         struct drm_i915_private *dev_priv = dev->dev_private;
3036         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3037         int pipe = intel_crtc->pipe;
3038         u32 reg, temp, i, j;
3039
3040         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3041            for train result */
3042         reg = FDI_RX_IMR(pipe);
3043         temp = I915_READ(reg);
3044         temp &= ~FDI_RX_SYMBOL_LOCK;
3045         temp &= ~FDI_RX_BIT_LOCK;
3046         I915_WRITE(reg, temp);
3047
3048         POSTING_READ(reg);
3049         udelay(150);
3050
3051         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3052                       I915_READ(FDI_RX_IIR(pipe)));
3053
3054         /* Try each vswing and preemphasis setting twice before moving on */
3055         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3056                 /* disable first in case we need to retry */
3057                 reg = FDI_TX_CTL(pipe);
3058                 temp = I915_READ(reg);
3059                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3060                 temp &= ~FDI_TX_ENABLE;
3061                 I915_WRITE(reg, temp);
3062
3063                 reg = FDI_RX_CTL(pipe);
3064                 temp = I915_READ(reg);
3065                 temp &= ~FDI_LINK_TRAIN_AUTO;
3066                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3067                 temp &= ~FDI_RX_ENABLE;
3068                 I915_WRITE(reg, temp);
3069
3070                 /* enable CPU FDI TX and PCH FDI RX */
3071                 reg = FDI_TX_CTL(pipe);
3072                 temp = I915_READ(reg);
3073                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3074                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3075                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3076                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3077                 temp |= snb_b_fdi_train_param[j/2];
3078                 temp |= FDI_COMPOSITE_SYNC;
3079                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3080
3081                 I915_WRITE(FDI_RX_MISC(pipe),
3082                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3083
3084                 reg = FDI_RX_CTL(pipe);
3085                 temp = I915_READ(reg);
3086                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3087                 temp |= FDI_COMPOSITE_SYNC;
3088                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3089
3090                 POSTING_READ(reg);
3091                 udelay(1); /* should be 0.5us */
3092
3093                 for (i = 0; i < 4; i++) {
3094                         reg = FDI_RX_IIR(pipe);
3095                         temp = I915_READ(reg);
3096                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3097
3098                         if (temp & FDI_RX_BIT_LOCK ||
3099                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3100                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3101                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3102                                               i);
3103                                 break;
3104                         }
3105                         udelay(1); /* should be 0.5us */
3106                 }
3107                 if (i == 4) {
3108                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3109                         continue;
3110                 }
3111
3112                 /* Train 2 */
3113                 reg = FDI_TX_CTL(pipe);
3114                 temp = I915_READ(reg);
3115                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3116                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3117                 I915_WRITE(reg, temp);
3118
3119                 reg = FDI_RX_CTL(pipe);
3120                 temp = I915_READ(reg);
3121                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3122                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3123                 I915_WRITE(reg, temp);
3124
3125                 POSTING_READ(reg);
3126                 udelay(2); /* should be 1.5us */
3127
3128                 for (i = 0; i < 4; i++) {
3129                         reg = FDI_RX_IIR(pipe);
3130                         temp = I915_READ(reg);
3131                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3132
3133                         if (temp & FDI_RX_SYMBOL_LOCK ||
3134                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3135                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3136                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3137                                               i);
3138                                 goto train_done;
3139                         }
3140                         udelay(2); /* should be 1.5us */
3141                 }
3142                 if (i == 4)
3143                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3144         }
3145
3146 train_done:
3147         DRM_DEBUG_KMS("FDI train done.\n");
3148 }
3149
3150 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3151 {
3152         struct drm_device *dev = intel_crtc->base.dev;
3153         struct drm_i915_private *dev_priv = dev->dev_private;
3154         int pipe = intel_crtc->pipe;
3155         u32 reg, temp;
3156
3157
3158         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3159         reg = FDI_RX_CTL(pipe);
3160         temp = I915_READ(reg);
3161         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3162         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3163         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3164         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3165
3166         POSTING_READ(reg);
3167         udelay(200);
3168
3169         /* Switch from Rawclk to PCDclk */
3170         temp = I915_READ(reg);
3171         I915_WRITE(reg, temp | FDI_PCDCLK);
3172
3173         POSTING_READ(reg);
3174         udelay(200);
3175
3176         /* Enable CPU FDI TX PLL, always on for Ironlake */
3177         reg = FDI_TX_CTL(pipe);
3178         temp = I915_READ(reg);
3179         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3180                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3181
3182                 POSTING_READ(reg);
3183                 udelay(100);
3184         }
3185 }
3186
3187 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3188 {
3189         struct drm_device *dev = intel_crtc->base.dev;
3190         struct drm_i915_private *dev_priv = dev->dev_private;
3191         int pipe = intel_crtc->pipe;
3192         u32 reg, temp;
3193
3194         /* Switch from PCDclk to Rawclk */
3195         reg = FDI_RX_CTL(pipe);
3196         temp = I915_READ(reg);
3197         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3198
3199         /* Disable CPU FDI TX PLL */
3200         reg = FDI_TX_CTL(pipe);
3201         temp = I915_READ(reg);
3202         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3203
3204         POSTING_READ(reg);
3205         udelay(100);
3206
3207         reg = FDI_RX_CTL(pipe);
3208         temp = I915_READ(reg);
3209         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3210
3211         /* Wait for the clocks to turn off. */
3212         POSTING_READ(reg);
3213         udelay(100);
3214 }
3215
3216 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3217 {
3218         struct drm_device *dev = crtc->dev;
3219         struct drm_i915_private *dev_priv = dev->dev_private;
3220         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3221         int pipe = intel_crtc->pipe;
3222         u32 reg, temp;
3223
3224         /* disable CPU FDI tx and PCH FDI rx */
3225         reg = FDI_TX_CTL(pipe);
3226         temp = I915_READ(reg);
3227         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3228         POSTING_READ(reg);
3229
3230         reg = FDI_RX_CTL(pipe);
3231         temp = I915_READ(reg);
3232         temp &= ~(0x7 << 16);
3233         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3234         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3235
3236         POSTING_READ(reg);
3237         udelay(100);
3238
3239         /* Ironlake workaround, disable clock pointer after downing FDI */
3240         if (HAS_PCH_IBX(dev))
3241                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3242
3243         /* still set train pattern 1 */
3244         reg = FDI_TX_CTL(pipe);
3245         temp = I915_READ(reg);
3246         temp &= ~FDI_LINK_TRAIN_NONE;
3247         temp |= FDI_LINK_TRAIN_PATTERN_1;
3248         I915_WRITE(reg, temp);
3249
3250         reg = FDI_RX_CTL(pipe);
3251         temp = I915_READ(reg);
3252         if (HAS_PCH_CPT(dev)) {
3253                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3254                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3255         } else {
3256                 temp &= ~FDI_LINK_TRAIN_NONE;
3257                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3258         }
3259         /* BPC in FDI rx is consistent with that in PIPECONF */
3260         temp &= ~(0x07 << 16);
3261         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3262         I915_WRITE(reg, temp);
3263
3264         POSTING_READ(reg);
3265         udelay(100);
3266 }
3267
3268 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3269 {
3270         struct intel_crtc *crtc;
3271
3272         /* Note that we don't need to be called with mode_config.lock here
3273          * as our list of CRTC objects is static for the lifetime of the
3274          * device and so cannot disappear as we iterate. Similarly, we can
3275          * happily treat the predicates as racy, atomic checks as userspace
3276          * cannot claim and pin a new fb without at least acquring the
3277          * struct_mutex and so serialising with us.
3278          */
3279         for_each_intel_crtc(dev, crtc) {
3280                 if (atomic_read(&crtc->unpin_work_count) == 0)
3281                         continue;
3282
3283                 if (crtc->unpin_work)
3284                         intel_wait_for_vblank(dev, crtc->pipe);
3285
3286                 return true;
3287         }
3288
3289         return false;
3290 }
3291
3292 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3293 {
3294         struct drm_device *dev = crtc->dev;
3295         struct drm_i915_private *dev_priv = dev->dev_private;
3296
3297         if (crtc->primary->fb == NULL)
3298                 return;
3299
3300         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3301
3302         WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3303                                    !intel_crtc_has_pending_flip(crtc),
3304                                    60*HZ) == 0);
3305
3306         mutex_lock(&dev->struct_mutex);
3307         intel_finish_fb(crtc->primary->fb);
3308         mutex_unlock(&dev->struct_mutex);
3309 }
3310
3311 /* Program iCLKIP clock to the desired frequency */
3312 static void lpt_program_iclkip(struct drm_crtc *crtc)
3313 {
3314         struct drm_device *dev = crtc->dev;
3315         struct drm_i915_private *dev_priv = dev->dev_private;
3316         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3317         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3318         u32 temp;
3319
3320         mutex_lock(&dev_priv->dpio_lock);
3321
3322         /* It is necessary to ungate the pixclk gate prior to programming
3323          * the divisors, and gate it back when it is done.
3324          */
3325         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3326
3327         /* Disable SSCCTL */
3328         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3329                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3330                                 SBI_SSCCTL_DISABLE,
3331                         SBI_ICLK);
3332
3333         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3334         if (clock == 20000) {
3335                 auxdiv = 1;
3336                 divsel = 0x41;
3337                 phaseinc = 0x20;
3338         } else {
3339                 /* The iCLK virtual clock root frequency is in MHz,
3340                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3341                  * divisors, it is necessary to divide one by another, so we
3342                  * convert the virtual clock precision to KHz here for higher
3343                  * precision.
3344                  */
3345                 u32 iclk_virtual_root_freq = 172800 * 1000;
3346                 u32 iclk_pi_range = 64;
3347                 u32 desired_divisor, msb_divisor_value, pi_value;
3348
3349                 desired_divisor = (iclk_virtual_root_freq / clock);
3350                 msb_divisor_value = desired_divisor / iclk_pi_range;
3351                 pi_value = desired_divisor % iclk_pi_range;
3352
3353                 auxdiv = 0;
3354                 divsel = msb_divisor_value - 2;
3355                 phaseinc = pi_value;
3356         }
3357
3358         /* This should not happen with any sane values */
3359         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3360                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3361         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3362                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3363
3364         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3365                         clock,
3366                         auxdiv,
3367                         divsel,
3368                         phasedir,
3369                         phaseinc);
3370
3371         /* Program SSCDIVINTPHASE6 */
3372         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3373         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3374         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3375         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3376         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3377         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3378         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3379         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3380
3381         /* Program SSCAUXDIV */
3382         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3383         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3384         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3385         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3386
3387         /* Enable modulator and associated divider */
3388         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3389         temp &= ~SBI_SSCCTL_DISABLE;
3390         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3391
3392         /* Wait for initialization time */
3393         udelay(24);
3394
3395         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3396
3397         mutex_unlock(&dev_priv->dpio_lock);
3398 }
3399
3400 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3401                                                 enum pipe pch_transcoder)
3402 {
3403         struct drm_device *dev = crtc->base.dev;
3404         struct drm_i915_private *dev_priv = dev->dev_private;
3405         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3406
3407         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3408                    I915_READ(HTOTAL(cpu_transcoder)));
3409         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3410                    I915_READ(HBLANK(cpu_transcoder)));
3411         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3412                    I915_READ(HSYNC(cpu_transcoder)));
3413
3414         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3415                    I915_READ(VTOTAL(cpu_transcoder)));
3416         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3417                    I915_READ(VBLANK(cpu_transcoder)));
3418         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3419                    I915_READ(VSYNC(cpu_transcoder)));
3420         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3421                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3422 }
3423
3424 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3425 {
3426         struct drm_i915_private *dev_priv = dev->dev_private;
3427         uint32_t temp;
3428
3429         temp = I915_READ(SOUTH_CHICKEN1);
3430         if (temp & FDI_BC_BIFURCATION_SELECT)
3431                 return;
3432
3433         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3434         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3435
3436         temp |= FDI_BC_BIFURCATION_SELECT;
3437         DRM_DEBUG_KMS("enabling fdi C rx\n");
3438         I915_WRITE(SOUTH_CHICKEN1, temp);
3439         POSTING_READ(SOUTH_CHICKEN1);
3440 }
3441
3442 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3443 {
3444         struct drm_device *dev = intel_crtc->base.dev;
3445         struct drm_i915_private *dev_priv = dev->dev_private;
3446
3447         switch (intel_crtc->pipe) {
3448         case PIPE_A:
3449                 break;
3450         case PIPE_B:
3451                 if (intel_crtc->config.fdi_lanes > 2)
3452                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3453                 else
3454                         cpt_enable_fdi_bc_bifurcation(dev);
3455
3456                 break;
3457         case PIPE_C:
3458                 cpt_enable_fdi_bc_bifurcation(dev);
3459
3460                 break;
3461         default:
3462                 BUG();
3463         }
3464 }
3465
3466 /*
3467  * Enable PCH resources required for PCH ports:
3468  *   - PCH PLLs
3469  *   - FDI training & RX/TX
3470  *   - update transcoder timings
3471  *   - DP transcoding bits
3472  *   - transcoder
3473  */
3474 static void ironlake_pch_enable(struct drm_crtc *crtc)
3475 {
3476         struct drm_device *dev = crtc->dev;
3477         struct drm_i915_private *dev_priv = dev->dev_private;
3478         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3479         int pipe = intel_crtc->pipe;
3480         u32 reg, temp;
3481
3482         assert_pch_transcoder_disabled(dev_priv, pipe);
3483
3484         if (IS_IVYBRIDGE(dev))
3485                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3486
3487         /* Write the TU size bits before fdi link training, so that error
3488          * detection works. */
3489         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3490                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3491
3492         /* For PCH output, training FDI link */
3493         dev_priv->display.fdi_link_train(crtc);
3494
3495         /* We need to program the right clock selection before writing the pixel
3496          * mutliplier into the DPLL. */
3497         if (HAS_PCH_CPT(dev)) {
3498                 u32 sel;
3499
3500                 temp = I915_READ(PCH_DPLL_SEL);
3501                 temp |= TRANS_DPLL_ENABLE(pipe);
3502                 sel = TRANS_DPLLB_SEL(pipe);
3503                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3504                         temp |= sel;
3505                 else
3506                         temp &= ~sel;
3507                 I915_WRITE(PCH_DPLL_SEL, temp);
3508         }
3509
3510         /* XXX: pch pll's can be enabled any time before we enable the PCH
3511          * transcoder, and we actually should do this to not upset any PCH
3512          * transcoder that already use the clock when we share it.
3513          *
3514          * Note that enable_shared_dpll tries to do the right thing, but
3515          * get_shared_dpll unconditionally resets the pll - we need that to have
3516          * the right LVDS enable sequence. */
3517         ironlake_enable_shared_dpll(intel_crtc);
3518
3519         /* set transcoder timing, panel must allow it */
3520         assert_panel_unlocked(dev_priv, pipe);
3521         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3522
3523         intel_fdi_normal_train(crtc);
3524
3525         /* For PCH DP, enable TRANS_DP_CTL */
3526         if (HAS_PCH_CPT(dev) &&
3527             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3528              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3529                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3530                 reg = TRANS_DP_CTL(pipe);
3531                 temp = I915_READ(reg);
3532                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3533                           TRANS_DP_SYNC_MASK |
3534                           TRANS_DP_BPC_MASK);
3535                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3536                          TRANS_DP_ENH_FRAMING);
3537                 temp |= bpc << 9; /* same format but at 11:9 */
3538
3539                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3540                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3541                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3542                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3543
3544                 switch (intel_trans_dp_port_sel(crtc)) {
3545                 case PCH_DP_B:
3546                         temp |= TRANS_DP_PORT_SEL_B;
3547                         break;
3548                 case PCH_DP_C:
3549                         temp |= TRANS_DP_PORT_SEL_C;
3550                         break;
3551                 case PCH_DP_D:
3552                         temp |= TRANS_DP_PORT_SEL_D;
3553                         break;
3554                 default:
3555                         BUG();
3556                 }
3557
3558                 I915_WRITE(reg, temp);
3559         }
3560
3561         ironlake_enable_pch_transcoder(dev_priv, pipe);
3562 }
3563
3564 static void lpt_pch_enable(struct drm_crtc *crtc)
3565 {
3566         struct drm_device *dev = crtc->dev;
3567         struct drm_i915_private *dev_priv = dev->dev_private;
3568         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3569         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3570
3571         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3572
3573         lpt_program_iclkip(crtc);
3574
3575         /* Set transcoder timing. */
3576         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3577
3578         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3579 }
3580
3581 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3582 {
3583         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3584
3585         if (pll == NULL)
3586                 return;
3587
3588         if (pll->refcount == 0) {
3589                 WARN(1, "bad %s refcount\n", pll->name);
3590                 return;
3591         }
3592
3593         if (--pll->refcount == 0) {
3594                 WARN_ON(pll->on);
3595                 WARN_ON(pll->active);
3596         }
3597
3598         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3599 }
3600
3601 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3602 {
3603         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3604         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3605         enum intel_dpll_id i;
3606
3607         if (pll) {
3608                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3609                               crtc->base.base.id, pll->name);
3610                 intel_put_shared_dpll(crtc);
3611         }
3612
3613         if (HAS_PCH_IBX(dev_priv->dev)) {
3614                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3615                 i = (enum intel_dpll_id) crtc->pipe;
3616                 pll = &dev_priv->shared_dplls[i];
3617
3618                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3619                               crtc->base.base.id, pll->name);
3620
3621                 WARN_ON(pll->refcount);
3622
3623                 goto found;
3624         }
3625
3626         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3627                 pll = &dev_priv->shared_dplls[i];
3628
3629                 /* Only want to check enabled timings first */
3630                 if (pll->refcount == 0)
3631                         continue;
3632
3633                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3634                            sizeof(pll->hw_state)) == 0) {
3635                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3636                                       crtc->base.base.id,
3637                                       pll->name, pll->refcount, pll->active);
3638
3639                         goto found;
3640                 }
3641         }
3642
3643         /* Ok no matching timings, maybe there's a free one? */
3644         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3645                 pll = &dev_priv->shared_dplls[i];
3646                 if (pll->refcount == 0) {
3647                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3648                                       crtc->base.base.id, pll->name);
3649                         goto found;
3650                 }
3651         }
3652
3653         return NULL;
3654
3655 found:
3656         if (pll->refcount == 0)
3657                 pll->hw_state = crtc->config.dpll_hw_state;
3658
3659         crtc->config.shared_dpll = i;
3660         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3661                          pipe_name(crtc->pipe));
3662
3663         pll->refcount++;
3664
3665         return pll;
3666 }
3667
3668 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3669 {
3670         struct drm_i915_private *dev_priv = dev->dev_private;
3671         int dslreg = PIPEDSL(pipe);
3672         u32 temp;
3673
3674         temp = I915_READ(dslreg);
3675         udelay(500);
3676         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3677                 if (wait_for(I915_READ(dslreg) != temp, 5))
3678                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3679         }
3680 }
3681
3682 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3683 {
3684         struct drm_device *dev = crtc->base.dev;
3685         struct drm_i915_private *dev_priv = dev->dev_private;
3686         int pipe = crtc->pipe;
3687
3688         if (crtc->config.pch_pfit.enabled) {
3689                 /* Force use of hard-coded filter coefficients
3690                  * as some pre-programmed values are broken,
3691                  * e.g. x201.
3692                  */
3693                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3694                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3695                                                  PF_PIPE_SEL_IVB(pipe));
3696                 else
3697                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3698                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3699                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3700         }
3701 }
3702
3703 static void intel_enable_planes(struct drm_crtc *crtc)
3704 {
3705         struct drm_device *dev = crtc->dev;
3706         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3707         struct drm_plane *plane;
3708         struct intel_plane *intel_plane;
3709
3710         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3711                 intel_plane = to_intel_plane(plane);
3712                 if (intel_plane->pipe == pipe)
3713                         intel_plane_restore(&intel_plane->base);
3714         }
3715 }
3716
3717 static void intel_disable_planes(struct drm_crtc *crtc)
3718 {
3719         struct drm_device *dev = crtc->dev;
3720         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3721         struct drm_plane *plane;
3722         struct intel_plane *intel_plane;
3723
3724         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3725                 intel_plane = to_intel_plane(plane);
3726                 if (intel_plane->pipe == pipe)
3727                         intel_plane_disable(&intel_plane->base);
3728         }
3729 }
3730
3731 void hsw_enable_ips(struct intel_crtc *crtc)
3732 {
3733         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3734
3735         if (!crtc->config.ips_enabled)
3736                 return;
3737
3738         /* We can only enable IPS after we enable a plane and wait for a vblank.
3739          * We guarantee that the plane is enabled by calling intel_enable_ips
3740          * only after intel_enable_plane. And intel_enable_plane already waits
3741          * for a vblank, so all we need to do here is to enable the IPS bit. */
3742         assert_plane_enabled(dev_priv, crtc->plane);
3743         if (IS_BROADWELL(crtc->base.dev)) {
3744                 mutex_lock(&dev_priv->rps.hw_lock);
3745                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3746                 mutex_unlock(&dev_priv->rps.hw_lock);
3747                 /* Quoting Art Runyan: "its not safe to expect any particular
3748                  * value in IPS_CTL bit 31 after enabling IPS through the
3749                  * mailbox." Moreover, the mailbox may return a bogus state,
3750                  * so we need to just enable it and continue on.
3751                  */
3752         } else {
3753                 I915_WRITE(IPS_CTL, IPS_ENABLE);
3754                 /* The bit only becomes 1 in the next vblank, so this wait here
3755                  * is essentially intel_wait_for_vblank. If we don't have this
3756                  * and don't wait for vblanks until the end of crtc_enable, then
3757                  * the HW state readout code will complain that the expected
3758                  * IPS_CTL value is not the one we read. */
3759                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3760                         DRM_ERROR("Timed out waiting for IPS enable\n");
3761         }
3762 }
3763
3764 void hsw_disable_ips(struct intel_crtc *crtc)
3765 {
3766         struct drm_device *dev = crtc->base.dev;
3767         struct drm_i915_private *dev_priv = dev->dev_private;
3768
3769         if (!crtc->config.ips_enabled)
3770                 return;
3771
3772         assert_plane_enabled(dev_priv, crtc->plane);
3773         if (IS_BROADWELL(dev)) {
3774                 mutex_lock(&dev_priv->rps.hw_lock);
3775                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3776                 mutex_unlock(&dev_priv->rps.hw_lock);
3777                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3778                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3779                         DRM_ERROR("Timed out waiting for IPS disable\n");
3780         } else {
3781                 I915_WRITE(IPS_CTL, 0);
3782                 POSTING_READ(IPS_CTL);
3783         }
3784
3785         /* We need to wait for a vblank before we can disable the plane. */
3786         intel_wait_for_vblank(dev, crtc->pipe);
3787 }
3788
3789 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3790 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3791 {
3792         struct drm_device *dev = crtc->dev;
3793         struct drm_i915_private *dev_priv = dev->dev_private;
3794         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3795         enum pipe pipe = intel_crtc->pipe;
3796         int palreg = PALETTE(pipe);
3797         int i;
3798         bool reenable_ips = false;
3799
3800         /* The clocks have to be on to load the palette. */
3801         if (!crtc->enabled || !intel_crtc->active)
3802                 return;
3803
3804         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3805                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3806                         assert_dsi_pll_enabled(dev_priv);
3807                 else
3808                         assert_pll_enabled(dev_priv, pipe);
3809         }
3810
3811         /* use legacy palette for Ironlake */
3812         if (HAS_PCH_SPLIT(dev))
3813                 palreg = LGC_PALETTE(pipe);
3814
3815         /* Workaround : Do not read or write the pipe palette/gamma data while
3816          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3817          */
3818         if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3819             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3820              GAMMA_MODE_MODE_SPLIT)) {
3821                 hsw_disable_ips(intel_crtc);
3822                 reenable_ips = true;
3823         }
3824
3825         for (i = 0; i < 256; i++) {
3826                 I915_WRITE(palreg + 4 * i,
3827                            (intel_crtc->lut_r[i] << 16) |
3828                            (intel_crtc->lut_g[i] << 8) |
3829                            intel_crtc->lut_b[i]);
3830         }
3831
3832         if (reenable_ips)
3833                 hsw_enable_ips(intel_crtc);
3834 }
3835
3836 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3837 {
3838         if (!enable && intel_crtc->overlay) {
3839                 struct drm_device *dev = intel_crtc->base.dev;
3840                 struct drm_i915_private *dev_priv = dev->dev_private;
3841
3842                 mutex_lock(&dev->struct_mutex);
3843                 dev_priv->mm.interruptible = false;
3844                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3845                 dev_priv->mm.interruptible = true;
3846                 mutex_unlock(&dev->struct_mutex);
3847         }
3848
3849         /* Let userspace switch the overlay on again. In most cases userspace
3850          * has to recompute where to put it anyway.
3851          */
3852 }
3853
3854 /**
3855  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3856  * cursor plane briefly if not already running after enabling the display
3857  * plane.
3858  * This workaround avoids occasional blank screens when self refresh is
3859  * enabled.
3860  */
3861 static void
3862 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3863 {
3864         u32 cntl = I915_READ(CURCNTR(pipe));
3865
3866         if ((cntl & CURSOR_MODE) == 0) {
3867                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3868
3869                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3870                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3871                 intel_wait_for_vblank(dev_priv->dev, pipe);
3872                 I915_WRITE(CURCNTR(pipe), cntl);
3873                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3874                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3875         }
3876 }
3877
3878 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
3879 {
3880         struct drm_device *dev = crtc->dev;
3881         struct drm_i915_private *dev_priv = dev->dev_private;
3882         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3883         int pipe = intel_crtc->pipe;
3884         int plane = intel_crtc->plane;
3885
3886         intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3887         intel_enable_planes(crtc);
3888         /* The fixup needs to happen before cursor is enabled */
3889         if (IS_G4X(dev))
3890                 g4x_fixup_plane(dev_priv, pipe);
3891         intel_crtc_update_cursor(crtc, true);
3892         intel_crtc_dpms_overlay(intel_crtc, true);
3893
3894         hsw_enable_ips(intel_crtc);
3895
3896         mutex_lock(&dev->struct_mutex);
3897         intel_update_fbc(dev);
3898         intel_edp_psr_update(dev);
3899         mutex_unlock(&dev->struct_mutex);
3900 }
3901
3902 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
3903 {
3904         struct drm_device *dev = crtc->dev;
3905         struct drm_i915_private *dev_priv = dev->dev_private;
3906         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3907         int pipe = intel_crtc->pipe;
3908         int plane = intel_crtc->plane;
3909
3910         intel_crtc_wait_for_pending_flips(crtc);
3911         drm_vblank_off(dev, pipe);
3912
3913         if (dev_priv->fbc.plane == plane)
3914                 intel_disable_fbc(dev);
3915
3916         hsw_disable_ips(intel_crtc);
3917
3918         intel_crtc_dpms_overlay(intel_crtc, false);
3919         intel_crtc_update_cursor(crtc, false);
3920         intel_disable_planes(crtc);
3921         intel_disable_primary_hw_plane(dev_priv, plane, pipe);
3922 }
3923
3924 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3925 {
3926         struct drm_device *dev = crtc->dev;
3927         struct drm_i915_private *dev_priv = dev->dev_private;
3928         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3929         struct intel_encoder *encoder;
3930         int pipe = intel_crtc->pipe;
3931         enum plane plane = intel_crtc->plane;
3932
3933         WARN_ON(!crtc->enabled);
3934
3935         if (intel_crtc->active)
3936                 return;
3937
3938         if (intel_crtc->config.has_pch_encoder)
3939                 intel_prepare_shared_dpll(intel_crtc);
3940
3941         if (intel_crtc->config.has_dp_encoder)
3942                 intel_dp_set_m_n(intel_crtc);
3943
3944         intel_set_pipe_timings(intel_crtc);
3945
3946         if (intel_crtc->config.has_pch_encoder) {
3947                 intel_cpu_transcoder_set_m_n(intel_crtc,
3948                                              &intel_crtc->config.fdi_m_n);
3949         }
3950
3951         ironlake_set_pipeconf(crtc);
3952
3953         /* Set up the display plane register */
3954         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
3955         POSTING_READ(DSPCNTR(plane));
3956
3957         dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
3958                                                crtc->x, crtc->y);
3959
3960         intel_crtc->active = true;
3961
3962         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3963         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3964
3965         for_each_encoder_on_crtc(dev, crtc, encoder)
3966                 if (encoder->pre_enable)
3967                         encoder->pre_enable(encoder);
3968
3969         if (intel_crtc->config.has_pch_encoder) {
3970                 /* Note: FDI PLL enabling _must_ be done before we enable the
3971                  * cpu pipes, hence this is separate from all the other fdi/pch
3972                  * enabling. */
3973                 ironlake_fdi_pll_enable(intel_crtc);
3974         } else {
3975                 assert_fdi_tx_disabled(dev_priv, pipe);
3976                 assert_fdi_rx_disabled(dev_priv, pipe);
3977         }
3978
3979         ironlake_pfit_enable(intel_crtc);
3980
3981         /*
3982          * On ILK+ LUT must be loaded before the pipe is running but with
3983          * clocks enabled
3984          */
3985         intel_crtc_load_lut(crtc);
3986
3987         intel_update_watermarks(crtc);
3988         intel_enable_pipe(intel_crtc);
3989
3990         if (intel_crtc->config.has_pch_encoder)
3991                 ironlake_pch_enable(crtc);
3992
3993         for_each_encoder_on_crtc(dev, crtc, encoder)
3994                 encoder->enable(encoder);
3995
3996         if (HAS_PCH_CPT(dev))
3997                 cpt_verify_modeset(dev, intel_crtc->pipe);
3998
3999         intel_crtc_enable_planes(crtc);
4000
4001         /*
4002          * There seems to be a race in PCH platform hw (at least on some
4003          * outputs) where an enabled pipe still completes any pageflip right
4004          * away (as if the pipe is off) instead of waiting for vblank. As soon
4005          * as the first vblank happend, everything works as expected. Hence just
4006          * wait for one vblank before returning to avoid strange things
4007          * happening.
4008          */
4009         intel_wait_for_vblank(dev, intel_crtc->pipe);
4010 }
4011
4012 /* IPS only exists on ULT machines and is tied to pipe A. */
4013 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4014 {
4015         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4016 }
4017
4018 /*
4019  * This implements the workaround described in the "notes" section of the mode
4020  * set sequence documentation. When going from no pipes or single pipe to
4021  * multiple pipes, and planes are enabled after the pipe, we need to wait at
4022  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4023  */
4024 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4025 {
4026         struct drm_device *dev = crtc->base.dev;
4027         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4028
4029         /* We want to get the other_active_crtc only if there's only 1 other
4030          * active crtc. */
4031         for_each_intel_crtc(dev, crtc_it) {
4032                 if (!crtc_it->active || crtc_it == crtc)
4033                         continue;
4034
4035                 if (other_active_crtc)
4036                         return;
4037
4038                 other_active_crtc = crtc_it;
4039         }
4040         if (!other_active_crtc)
4041                 return;
4042
4043         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4044         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4045 }
4046
4047 static void haswell_crtc_enable(struct drm_crtc *crtc)
4048 {
4049         struct drm_device *dev = crtc->dev;
4050         struct drm_i915_private *dev_priv = dev->dev_private;
4051         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4052         struct intel_encoder *encoder;
4053         int pipe = intel_crtc->pipe;
4054         enum plane plane = intel_crtc->plane;
4055
4056         WARN_ON(!crtc->enabled);
4057
4058         if (intel_crtc->active)
4059                 return;
4060
4061         if (intel_crtc->config.has_dp_encoder)
4062                 intel_dp_set_m_n(intel_crtc);
4063
4064         intel_set_pipe_timings(intel_crtc);
4065
4066         if (intel_crtc->config.has_pch_encoder) {
4067                 intel_cpu_transcoder_set_m_n(intel_crtc,
4068                                              &intel_crtc->config.fdi_m_n);
4069         }
4070
4071         haswell_set_pipeconf(crtc);
4072
4073         intel_set_pipe_csc(crtc);
4074
4075         /* Set up the display plane register */
4076         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
4077         POSTING_READ(DSPCNTR(plane));
4078
4079         dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4080                                                crtc->x, crtc->y);
4081
4082         intel_crtc->active = true;
4083
4084         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4085         if (intel_crtc->config.has_pch_encoder)
4086                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4087
4088         if (intel_crtc->config.has_pch_encoder)
4089                 dev_priv->display.fdi_link_train(crtc);
4090
4091         for_each_encoder_on_crtc(dev, crtc, encoder)
4092                 if (encoder->pre_enable)
4093                         encoder->pre_enable(encoder);
4094
4095         intel_ddi_enable_pipe_clock(intel_crtc);
4096
4097         ironlake_pfit_enable(intel_crtc);
4098
4099         /*
4100          * On ILK+ LUT must be loaded before the pipe is running but with
4101          * clocks enabled
4102          */
4103         intel_crtc_load_lut(crtc);
4104
4105         intel_ddi_set_pipe_settings(crtc);
4106         intel_ddi_enable_transcoder_func(crtc);
4107
4108         intel_update_watermarks(crtc);
4109         intel_enable_pipe(intel_crtc);
4110
4111         if (intel_crtc->config.has_pch_encoder)
4112                 lpt_pch_enable(crtc);
4113
4114         for_each_encoder_on_crtc(dev, crtc, encoder) {
4115                 encoder->enable(encoder);
4116                 intel_opregion_notify_encoder(encoder, true);
4117         }
4118
4119         /* If we change the relative order between pipe/planes enabling, we need
4120          * to change the workaround. */
4121         haswell_mode_set_planes_workaround(intel_crtc);
4122         intel_crtc_enable_planes(crtc);
4123 }
4124
4125 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4126 {
4127         struct drm_device *dev = crtc->base.dev;
4128         struct drm_i915_private *dev_priv = dev->dev_private;
4129         int pipe = crtc->pipe;
4130
4131         /* To avoid upsetting the power well on haswell only disable the pfit if
4132          * it's in use. The hw state code will make sure we get this right. */
4133         if (crtc->config.pch_pfit.enabled) {
4134                 I915_WRITE(PF_CTL(pipe), 0);
4135                 I915_WRITE(PF_WIN_POS(pipe), 0);
4136                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4137         }
4138 }
4139
4140 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4141 {
4142         struct drm_device *dev = crtc->dev;
4143         struct drm_i915_private *dev_priv = dev->dev_private;
4144         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4145         struct intel_encoder *encoder;
4146         int pipe = intel_crtc->pipe;
4147         u32 reg, temp;
4148
4149         if (!intel_crtc->active)
4150                 return;
4151
4152         intel_crtc_disable_planes(crtc);
4153
4154         for_each_encoder_on_crtc(dev, crtc, encoder)
4155                 encoder->disable(encoder);
4156
4157         if (intel_crtc->config.has_pch_encoder)
4158                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4159
4160         intel_disable_pipe(dev_priv, pipe);
4161
4162         ironlake_pfit_disable(intel_crtc);
4163
4164         for_each_encoder_on_crtc(dev, crtc, encoder)
4165                 if (encoder->post_disable)
4166                         encoder->post_disable(encoder);
4167
4168         if (intel_crtc->config.has_pch_encoder) {
4169                 ironlake_fdi_disable(crtc);
4170
4171                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4172                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4173
4174                 if (HAS_PCH_CPT(dev)) {
4175                         /* disable TRANS_DP_CTL */
4176                         reg = TRANS_DP_CTL(pipe);
4177                         temp = I915_READ(reg);
4178                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4179                                   TRANS_DP_PORT_SEL_MASK);
4180                         temp |= TRANS_DP_PORT_SEL_NONE;
4181                         I915_WRITE(reg, temp);
4182
4183                         /* disable DPLL_SEL */
4184                         temp = I915_READ(PCH_DPLL_SEL);
4185                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4186                         I915_WRITE(PCH_DPLL_SEL, temp);
4187                 }
4188
4189                 /* disable PCH DPLL */
4190                 intel_disable_shared_dpll(intel_crtc);
4191
4192                 ironlake_fdi_pll_disable(intel_crtc);
4193         }
4194
4195         intel_crtc->active = false;
4196         intel_update_watermarks(crtc);
4197
4198         mutex_lock(&dev->struct_mutex);
4199         intel_update_fbc(dev);
4200         intel_edp_psr_update(dev);
4201         mutex_unlock(&dev->struct_mutex);
4202 }
4203
4204 static void haswell_crtc_disable(struct drm_crtc *crtc)
4205 {
4206         struct drm_device *dev = crtc->dev;
4207         struct drm_i915_private *dev_priv = dev->dev_private;
4208         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4209         struct intel_encoder *encoder;
4210         int pipe = intel_crtc->pipe;
4211         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4212
4213         if (!intel_crtc->active)
4214                 return;
4215
4216         intel_crtc_disable_planes(crtc);
4217
4218         for_each_encoder_on_crtc(dev, crtc, encoder) {
4219                 intel_opregion_notify_encoder(encoder, false);
4220                 encoder->disable(encoder);
4221         }
4222
4223         if (intel_crtc->config.has_pch_encoder)
4224                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4225         intel_disable_pipe(dev_priv, pipe);
4226
4227         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4228
4229         ironlake_pfit_disable(intel_crtc);
4230
4231         intel_ddi_disable_pipe_clock(intel_crtc);
4232
4233         for_each_encoder_on_crtc(dev, crtc, encoder)
4234                 if (encoder->post_disable)
4235                         encoder->post_disable(encoder);
4236
4237         if (intel_crtc->config.has_pch_encoder) {
4238                 lpt_disable_pch_transcoder(dev_priv);
4239                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4240                 intel_ddi_fdi_disable(crtc);
4241         }
4242
4243         intel_crtc->active = false;
4244         intel_update_watermarks(crtc);
4245
4246         mutex_lock(&dev->struct_mutex);
4247         intel_update_fbc(dev);
4248         intel_edp_psr_update(dev);
4249         mutex_unlock(&dev->struct_mutex);
4250 }
4251
4252 static void ironlake_crtc_off(struct drm_crtc *crtc)
4253 {
4254         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4255         intel_put_shared_dpll(intel_crtc);
4256 }
4257
4258 static void haswell_crtc_off(struct drm_crtc *crtc)
4259 {
4260         intel_ddi_put_crtc_pll(crtc);
4261 }
4262
4263 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4264 {
4265         struct drm_device *dev = crtc->base.dev;
4266         struct drm_i915_private *dev_priv = dev->dev_private;
4267         struct intel_crtc_config *pipe_config = &crtc->config;
4268
4269         if (!crtc->config.gmch_pfit.control)
4270                 return;
4271
4272         /*
4273          * The panel fitter should only be adjusted whilst the pipe is disabled,
4274          * according to register description and PRM.
4275          */
4276         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4277         assert_pipe_disabled(dev_priv, crtc->pipe);
4278
4279         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4280         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4281
4282         /* Border color in case we don't scale up to the full screen. Black by
4283          * default, change to something else for debugging. */
4284         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4285 }
4286
4287 #define for_each_power_domain(domain, mask)                             \
4288         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4289                 if ((1 << (domain)) & (mask))
4290
4291 enum intel_display_power_domain
4292 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4293 {
4294         struct drm_device *dev = intel_encoder->base.dev;
4295         struct intel_digital_port *intel_dig_port;
4296
4297         switch (intel_encoder->type) {
4298         case INTEL_OUTPUT_UNKNOWN:
4299                 /* Only DDI platforms should ever use this output type */
4300                 WARN_ON_ONCE(!HAS_DDI(dev));
4301         case INTEL_OUTPUT_DISPLAYPORT:
4302         case INTEL_OUTPUT_HDMI:
4303         case INTEL_OUTPUT_EDP:
4304                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4305                 switch (intel_dig_port->port) {
4306                 case PORT_A:
4307                         return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4308                 case PORT_B:
4309                         return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4310                 case PORT_C:
4311                         return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4312                 case PORT_D:
4313                         return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4314                 default:
4315                         WARN_ON_ONCE(1);
4316                         return POWER_DOMAIN_PORT_OTHER;
4317                 }
4318         case INTEL_OUTPUT_ANALOG:
4319                 return POWER_DOMAIN_PORT_CRT;
4320         case INTEL_OUTPUT_DSI:
4321                 return POWER_DOMAIN_PORT_DSI;
4322         default:
4323                 return POWER_DOMAIN_PORT_OTHER;
4324         }
4325 }
4326
4327 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4328 {
4329         struct drm_device *dev = crtc->dev;
4330         struct intel_encoder *intel_encoder;
4331         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4332         enum pipe pipe = intel_crtc->pipe;
4333         bool pfit_enabled = intel_crtc->config.pch_pfit.enabled;
4334         unsigned long mask;
4335         enum transcoder transcoder;
4336
4337         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4338
4339         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4340         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4341         if (pfit_enabled)
4342                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4343
4344         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4345                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4346
4347         return mask;
4348 }
4349
4350 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4351                                   bool enable)
4352 {
4353         if (dev_priv->power_domains.init_power_on == enable)
4354                 return;
4355
4356         if (enable)
4357                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4358         else
4359                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4360
4361         dev_priv->power_domains.init_power_on = enable;
4362 }
4363
4364 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4365 {
4366         struct drm_i915_private *dev_priv = dev->dev_private;
4367         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4368         struct intel_crtc *crtc;
4369
4370         /*
4371          * First get all needed power domains, then put all unneeded, to avoid
4372          * any unnecessary toggling of the power wells.
4373          */
4374         for_each_intel_crtc(dev, crtc) {
4375                 enum intel_display_power_domain domain;
4376
4377                 if (!crtc->base.enabled)
4378                         continue;
4379
4380                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4381
4382                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4383                         intel_display_power_get(dev_priv, domain);
4384         }
4385
4386         for_each_intel_crtc(dev, crtc) {
4387                 enum intel_display_power_domain domain;
4388
4389                 for_each_power_domain(domain, crtc->enabled_power_domains)
4390                         intel_display_power_put(dev_priv, domain);
4391
4392                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4393         }
4394
4395         intel_display_set_init_power(dev_priv, false);
4396 }
4397
4398 int valleyview_get_vco(struct drm_i915_private *dev_priv)
4399 {
4400         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4401
4402         /* Obtain SKU information */
4403         mutex_lock(&dev_priv->dpio_lock);
4404         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4405                 CCK_FUSE_HPLL_FREQ_MASK;
4406         mutex_unlock(&dev_priv->dpio_lock);
4407
4408         return vco_freq[hpll_freq];
4409 }
4410
4411 /* Adjust CDclk dividers to allow high res or save power if possible */
4412 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4413 {
4414         struct drm_i915_private *dev_priv = dev->dev_private;
4415         u32 val, cmd;
4416
4417         WARN_ON(valleyview_cur_cdclk(dev_priv) != dev_priv->vlv_cdclk_freq);
4418         dev_priv->vlv_cdclk_freq = cdclk;
4419
4420         if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
4421                 cmd = 2;
4422         else if (cdclk == 266)
4423                 cmd = 1;
4424         else
4425                 cmd = 0;
4426
4427         mutex_lock(&dev_priv->rps.hw_lock);
4428         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4429         val &= ~DSPFREQGUAR_MASK;
4430         val |= (cmd << DSPFREQGUAR_SHIFT);
4431         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4432         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4433                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4434                      50)) {
4435                 DRM_ERROR("timed out waiting for CDclk change\n");
4436         }
4437         mutex_unlock(&dev_priv->rps.hw_lock);
4438
4439         if (cdclk == 400) {
4440                 u32 divider, vco;
4441
4442                 vco = valleyview_get_vco(dev_priv);
4443                 divider = ((vco << 1) / cdclk) - 1;
4444
4445                 mutex_lock(&dev_priv->dpio_lock);
4446                 /* adjust cdclk divider */
4447                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4448                 val &= ~0xf;
4449                 val |= divider;
4450                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4451                 mutex_unlock(&dev_priv->dpio_lock);
4452         }
4453
4454         mutex_lock(&dev_priv->dpio_lock);
4455         /* adjust self-refresh exit latency value */
4456         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4457         val &= ~0x7f;
4458
4459         /*
4460          * For high bandwidth configs, we set a higher latency in the bunit
4461          * so that the core display fetch happens in time to avoid underruns.
4462          */
4463         if (cdclk == 400)
4464                 val |= 4500 / 250; /* 4.5 usec */
4465         else
4466                 val |= 3000 / 250; /* 3.0 usec */
4467         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4468         mutex_unlock(&dev_priv->dpio_lock);
4469
4470         /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4471         intel_i2c_reset(dev);
4472 }
4473
4474 int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4475 {
4476         int cur_cdclk, vco;
4477         int divider;
4478
4479         vco = valleyview_get_vco(dev_priv);
4480
4481         mutex_lock(&dev_priv->dpio_lock);
4482         divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4483         mutex_unlock(&dev_priv->dpio_lock);
4484
4485         divider &= 0xf;
4486
4487         cur_cdclk = (vco << 1) / (divider + 1);
4488
4489         return cur_cdclk;
4490 }
4491
4492 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4493                                  int max_pixclk)
4494 {
4495         /*
4496          * Really only a few cases to deal with, as only 4 CDclks are supported:
4497          *   200MHz
4498          *   267MHz
4499          *   320MHz
4500          *   400MHz
4501          * So we check to see whether we're above 90% of the lower bin and
4502          * adjust if needed.
4503          */
4504         if (max_pixclk > 288000) {
4505                 return 400;
4506         } else if (max_pixclk > 240000) {
4507                 return 320;
4508         } else
4509                 return 266;
4510         /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4511 }
4512
4513 /* compute the max pixel clock for new configuration */
4514 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4515 {
4516         struct drm_device *dev = dev_priv->dev;
4517         struct intel_crtc *intel_crtc;
4518         int max_pixclk = 0;
4519
4520         for_each_intel_crtc(dev, intel_crtc) {
4521                 if (intel_crtc->new_enabled)
4522                         max_pixclk = max(max_pixclk,
4523                                          intel_crtc->new_config->adjusted_mode.crtc_clock);
4524         }
4525
4526         return max_pixclk;
4527 }
4528
4529 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4530                                             unsigned *prepare_pipes)
4531 {
4532         struct drm_i915_private *dev_priv = dev->dev_private;
4533         struct intel_crtc *intel_crtc;
4534         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4535
4536         if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4537             dev_priv->vlv_cdclk_freq)
4538                 return;
4539
4540         /* disable/enable all currently active pipes while we change cdclk */
4541         for_each_intel_crtc(dev, intel_crtc)
4542                 if (intel_crtc->base.enabled)
4543                         *prepare_pipes |= (1 << intel_crtc->pipe);
4544 }
4545
4546 static void valleyview_modeset_global_resources(struct drm_device *dev)
4547 {
4548         struct drm_i915_private *dev_priv = dev->dev_private;
4549         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4550         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4551
4552         if (req_cdclk != dev_priv->vlv_cdclk_freq)
4553                 valleyview_set_cdclk(dev, req_cdclk);
4554         modeset_update_crtc_power_domains(dev);
4555 }
4556
4557 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4558 {
4559         struct drm_device *dev = crtc->dev;
4560         struct drm_i915_private *dev_priv = dev->dev_private;
4561         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4562         struct intel_encoder *encoder;
4563         int pipe = intel_crtc->pipe;
4564         int plane = intel_crtc->plane;
4565         bool is_dsi;
4566         u32 dspcntr;
4567
4568         WARN_ON(!crtc->enabled);
4569
4570         if (intel_crtc->active)
4571                 return;
4572
4573         vlv_prepare_pll(intel_crtc);
4574
4575         /* Set up the display plane register */
4576         dspcntr = DISPPLANE_GAMMA_ENABLE;
4577
4578         if (intel_crtc->config.has_dp_encoder)
4579                 intel_dp_set_m_n(intel_crtc);
4580
4581         intel_set_pipe_timings(intel_crtc);
4582
4583         /* pipesrc and dspsize control the size that is scaled from,
4584          * which should always be the user's requested size.
4585          */
4586         I915_WRITE(DSPSIZE(plane),
4587                    ((intel_crtc->config.pipe_src_h - 1) << 16) |
4588                    (intel_crtc->config.pipe_src_w - 1));
4589         I915_WRITE(DSPPOS(plane), 0);
4590
4591         i9xx_set_pipeconf(intel_crtc);
4592
4593         I915_WRITE(DSPCNTR(plane), dspcntr);
4594         POSTING_READ(DSPCNTR(plane));
4595
4596         dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4597                                                crtc->x, crtc->y);
4598
4599         intel_crtc->active = true;
4600
4601         for_each_encoder_on_crtc(dev, crtc, encoder)
4602                 if (encoder->pre_pll_enable)
4603                         encoder->pre_pll_enable(encoder);
4604
4605         is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4606
4607         if (!is_dsi) {
4608                 if (IS_CHERRYVIEW(dev))
4609                         chv_enable_pll(intel_crtc);
4610                 else
4611                         vlv_enable_pll(intel_crtc);
4612         }
4613
4614         for_each_encoder_on_crtc(dev, crtc, encoder)
4615                 if (encoder->pre_enable)
4616                         encoder->pre_enable(encoder);
4617
4618         i9xx_pfit_enable(intel_crtc);
4619
4620         intel_crtc_load_lut(crtc);
4621
4622         intel_update_watermarks(crtc);
4623         intel_enable_pipe(intel_crtc);
4624         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4625
4626         for_each_encoder_on_crtc(dev, crtc, encoder)
4627                 encoder->enable(encoder);
4628
4629         intel_crtc_enable_planes(crtc);
4630 }
4631
4632 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4633 {
4634         struct drm_device *dev = crtc->base.dev;
4635         struct drm_i915_private *dev_priv = dev->dev_private;
4636
4637         I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4638         I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4639 }
4640
4641 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4642 {
4643         struct drm_device *dev = crtc->dev;
4644         struct drm_i915_private *dev_priv = dev->dev_private;
4645         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4646         struct intel_encoder *encoder;
4647         int pipe = intel_crtc->pipe;
4648         int plane = intel_crtc->plane;
4649         u32 dspcntr;
4650
4651         WARN_ON(!crtc->enabled);
4652
4653         if (intel_crtc->active)
4654                 return;
4655
4656         i9xx_set_pll_dividers(intel_crtc);
4657
4658         /* Set up the display plane register */
4659         dspcntr = DISPPLANE_GAMMA_ENABLE;
4660
4661         if (pipe == 0)
4662                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4663         else
4664                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4665
4666         if (intel_crtc->config.has_dp_encoder)
4667                 intel_dp_set_m_n(intel_crtc);
4668
4669         intel_set_pipe_timings(intel_crtc);
4670
4671         /* pipesrc and dspsize control the size that is scaled from,
4672          * which should always be the user's requested size.
4673          */
4674         I915_WRITE(DSPSIZE(plane),
4675                    ((intel_crtc->config.pipe_src_h - 1) << 16) |
4676                    (intel_crtc->config.pipe_src_w - 1));
4677         I915_WRITE(DSPPOS(plane), 0);
4678
4679         i9xx_set_pipeconf(intel_crtc);
4680
4681         I915_WRITE(DSPCNTR(plane), dspcntr);
4682         POSTING_READ(DSPCNTR(plane));
4683
4684         dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4685                                                crtc->x, crtc->y);
4686
4687         intel_crtc->active = true;
4688
4689         for_each_encoder_on_crtc(dev, crtc, encoder)
4690                 if (encoder->pre_enable)
4691                         encoder->pre_enable(encoder);
4692
4693         i9xx_enable_pll(intel_crtc);
4694
4695         i9xx_pfit_enable(intel_crtc);
4696
4697         intel_crtc_load_lut(crtc);
4698
4699         intel_update_watermarks(crtc);
4700         intel_enable_pipe(intel_crtc);
4701         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4702
4703         for_each_encoder_on_crtc(dev, crtc, encoder)
4704                 encoder->enable(encoder);
4705
4706         intel_crtc_enable_planes(crtc);
4707 }
4708
4709 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4710 {
4711         struct drm_device *dev = crtc->base.dev;
4712         struct drm_i915_private *dev_priv = dev->dev_private;
4713
4714         if (!crtc->config.gmch_pfit.control)
4715                 return;
4716
4717         assert_pipe_disabled(dev_priv, crtc->pipe);
4718
4719         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4720                          I915_READ(PFIT_CONTROL));
4721         I915_WRITE(PFIT_CONTROL, 0);
4722 }
4723
4724 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4725 {
4726         struct drm_device *dev = crtc->dev;
4727         struct drm_i915_private *dev_priv = dev->dev_private;
4728         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4729         struct intel_encoder *encoder;
4730         int pipe = intel_crtc->pipe;
4731
4732         if (!intel_crtc->active)
4733                 return;
4734
4735         intel_crtc_disable_planes(crtc);
4736
4737         for_each_encoder_on_crtc(dev, crtc, encoder)
4738                 encoder->disable(encoder);
4739
4740         intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4741         intel_disable_pipe(dev_priv, pipe);
4742
4743         i9xx_pfit_disable(intel_crtc);
4744
4745         for_each_encoder_on_crtc(dev, crtc, encoder)
4746                 if (encoder->post_disable)
4747                         encoder->post_disable(encoder);
4748
4749         if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4750                 if (IS_CHERRYVIEW(dev))
4751                         chv_disable_pll(dev_priv, pipe);
4752                 else if (IS_VALLEYVIEW(dev))
4753                         vlv_disable_pll(dev_priv, pipe);
4754                 else
4755                         i9xx_disable_pll(dev_priv, pipe);
4756         }
4757
4758         intel_crtc->active = false;
4759         intel_update_watermarks(crtc);
4760
4761         mutex_lock(&dev->struct_mutex);
4762         intel_update_fbc(dev);
4763         intel_edp_psr_update(dev);
4764         mutex_unlock(&dev->struct_mutex);
4765 }
4766
4767 static void i9xx_crtc_off(struct drm_crtc *crtc)
4768 {
4769 }
4770
4771 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4772                                     bool enabled)
4773 {
4774         struct drm_device *dev = crtc->dev;
4775         struct drm_i915_master_private *master_priv;
4776         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4777         int pipe = intel_crtc->pipe;
4778
4779         if (!dev->primary->master)
4780                 return;
4781
4782         master_priv = dev->primary->master->driver_priv;
4783         if (!master_priv->sarea_priv)
4784                 return;
4785
4786         switch (pipe) {
4787         case 0:
4788                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4789                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4790                 break;
4791         case 1:
4792                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4793                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4794                 break;
4795         default:
4796                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4797                 break;
4798         }
4799 }
4800
4801 /**
4802  * Sets the power management mode of the pipe and plane.
4803  */
4804 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4805 {
4806         struct drm_device *dev = crtc->dev;
4807         struct drm_i915_private *dev_priv = dev->dev_private;
4808         struct intel_encoder *intel_encoder;
4809         bool enable = false;
4810
4811         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4812                 enable |= intel_encoder->connectors_active;
4813
4814         if (enable)
4815                 dev_priv->display.crtc_enable(crtc);
4816         else
4817                 dev_priv->display.crtc_disable(crtc);
4818
4819         intel_crtc_update_sarea(crtc, enable);
4820 }
4821
4822 static void intel_crtc_disable(struct drm_crtc *crtc)
4823 {
4824         struct drm_device *dev = crtc->dev;
4825         struct drm_connector *connector;
4826         struct drm_i915_private *dev_priv = dev->dev_private;
4827
4828         /* crtc should still be enabled when we disable it. */
4829         WARN_ON(!crtc->enabled);
4830
4831         dev_priv->display.crtc_disable(crtc);
4832         intel_crtc_update_sarea(crtc, false);
4833         dev_priv->display.off(crtc);
4834
4835         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4836         assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4837         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4838
4839         if (crtc->primary->fb) {
4840                 mutex_lock(&dev->struct_mutex);
4841                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->primary->fb)->obj);
4842                 mutex_unlock(&dev->struct_mutex);
4843                 crtc->primary->fb = NULL;
4844         }
4845
4846         /* Update computed state. */
4847         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4848                 if (!connector->encoder || !connector->encoder->crtc)
4849                         continue;
4850
4851                 if (connector->encoder->crtc != crtc)
4852                         continue;
4853
4854                 connector->dpms = DRM_MODE_DPMS_OFF;
4855                 to_intel_encoder(connector->encoder)->connectors_active = false;
4856         }
4857 }
4858
4859 void intel_encoder_destroy(struct drm_encoder *encoder)
4860 {
4861         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4862
4863         drm_encoder_cleanup(encoder);
4864         kfree(intel_encoder);
4865 }
4866
4867 /* Simple dpms helper for encoders with just one connector, no cloning and only
4868  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4869  * state of the entire output pipe. */
4870 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4871 {
4872         if (mode == DRM_MODE_DPMS_ON) {
4873                 encoder->connectors_active = true;
4874
4875                 intel_crtc_update_dpms(encoder->base.crtc);
4876         } else {
4877                 encoder->connectors_active = false;
4878
4879                 intel_crtc_update_dpms(encoder->base.crtc);
4880         }
4881 }
4882
4883 /* Cross check the actual hw state with our own modeset state tracking (and it's
4884  * internal consistency). */
4885 static void intel_connector_check_state(struct intel_connector *connector)
4886 {
4887         if (connector->get_hw_state(connector)) {
4888                 struct intel_encoder *encoder = connector->encoder;
4889                 struct drm_crtc *crtc;
4890                 bool encoder_enabled;
4891                 enum pipe pipe;
4892
4893                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4894                               connector->base.base.id,
4895                               drm_get_connector_name(&connector->base));
4896
4897                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4898                      "wrong connector dpms state\n");
4899                 WARN(connector->base.encoder != &encoder->base,
4900                      "active connector not linked to encoder\n");
4901                 WARN(!encoder->connectors_active,
4902                      "encoder->connectors_active not set\n");
4903
4904                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4905                 WARN(!encoder_enabled, "encoder not enabled\n");
4906                 if (WARN_ON(!encoder->base.crtc))
4907                         return;
4908
4909                 crtc = encoder->base.crtc;
4910
4911                 WARN(!crtc->enabled, "crtc not enabled\n");
4912                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4913                 WARN(pipe != to_intel_crtc(crtc)->pipe,
4914                      "encoder active on the wrong pipe\n");
4915         }
4916 }
4917
4918 /* Even simpler default implementation, if there's really no special case to
4919  * consider. */
4920 void intel_connector_dpms(struct drm_connector *connector, int mode)
4921 {
4922         /* All the simple cases only support two dpms states. */
4923         if (mode != DRM_MODE_DPMS_ON)
4924                 mode = DRM_MODE_DPMS_OFF;
4925
4926         if (mode == connector->dpms)
4927                 return;
4928
4929         connector->dpms = mode;
4930
4931         /* Only need to change hw state when actually enabled */
4932         if (connector->encoder)
4933                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
4934
4935         intel_modeset_check_state(connector->dev);
4936 }
4937
4938 /* Simple connector->get_hw_state implementation for encoders that support only
4939  * one connector and no cloning and hence the encoder state determines the state
4940  * of the connector. */
4941 bool intel_connector_get_hw_state(struct intel_connector *connector)
4942 {
4943         enum pipe pipe = 0;
4944         struct intel_encoder *encoder = connector->encoder;
4945
4946         return encoder->get_hw_state(encoder, &pipe);
4947 }
4948
4949 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4950                                      struct intel_crtc_config *pipe_config)
4951 {
4952         struct drm_i915_private *dev_priv = dev->dev_private;
4953         struct intel_crtc *pipe_B_crtc =
4954                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4955
4956         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4957                       pipe_name(pipe), pipe_config->fdi_lanes);
4958         if (pipe_config->fdi_lanes > 4) {
4959                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4960                               pipe_name(pipe), pipe_config->fdi_lanes);
4961                 return false;
4962         }
4963
4964         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4965                 if (pipe_config->fdi_lanes > 2) {
4966                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4967                                       pipe_config->fdi_lanes);
4968                         return false;
4969                 } else {
4970                         return true;
4971                 }
4972         }
4973
4974         if (INTEL_INFO(dev)->num_pipes == 2)
4975                 return true;
4976
4977         /* Ivybridge 3 pipe is really complicated */
4978         switch (pipe) {
4979         case PIPE_A:
4980                 return true;
4981         case PIPE_B:
4982                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4983                     pipe_config->fdi_lanes > 2) {
4984                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4985                                       pipe_name(pipe), pipe_config->fdi_lanes);
4986                         return false;
4987                 }
4988                 return true;
4989         case PIPE_C:
4990                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4991                     pipe_B_crtc->config.fdi_lanes <= 2) {
4992                         if (pipe_config->fdi_lanes > 2) {
4993                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4994                                               pipe_name(pipe), pipe_config->fdi_lanes);
4995                                 return false;
4996                         }
4997                 } else {
4998                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4999                         return false;
5000                 }
5001                 return true;
5002         default:
5003                 BUG();
5004         }
5005 }
5006
5007 #define RETRY 1
5008 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5009                                        struct intel_crtc_config *pipe_config)
5010 {
5011         struct drm_device *dev = intel_crtc->base.dev;
5012         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5013         int lane, link_bw, fdi_dotclock;
5014         bool setup_ok, needs_recompute = false;
5015
5016 retry:
5017         /* FDI is a binary signal running at ~2.7GHz, encoding
5018          * each output octet as 10 bits. The actual frequency
5019          * is stored as a divider into a 100MHz clock, and the
5020          * mode pixel clock is stored in units of 1KHz.
5021          * Hence the bw of each lane in terms of the mode signal
5022          * is:
5023          */
5024         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5025
5026         fdi_dotclock = adjusted_mode->crtc_clock;
5027
5028         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5029                                            pipe_config->pipe_bpp);
5030
5031         pipe_config->fdi_lanes = lane;
5032
5033         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5034                                link_bw, &pipe_config->fdi_m_n);
5035
5036         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5037                                             intel_crtc->pipe, pipe_config);
5038         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5039                 pipe_config->pipe_bpp -= 2*3;
5040                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5041                               pipe_config->pipe_bpp);
5042                 needs_recompute = true;
5043                 pipe_config->bw_constrained = true;
5044
5045                 goto retry;
5046         }
5047
5048         if (needs_recompute)
5049                 return RETRY;
5050
5051         return setup_ok ? 0 : -EINVAL;
5052 }
5053
5054 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5055                                    struct intel_crtc_config *pipe_config)
5056 {
5057         pipe_config->ips_enabled = i915.enable_ips &&
5058                                    hsw_crtc_supports_ips(crtc) &&
5059                                    pipe_config->pipe_bpp <= 24;
5060 }
5061
5062 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5063                                      struct intel_crtc_config *pipe_config)
5064 {
5065         struct drm_device *dev = crtc->base.dev;
5066         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5067
5068         /* FIXME should check pixel clock limits on all platforms */
5069         if (INTEL_INFO(dev)->gen < 4) {
5070                 struct drm_i915_private *dev_priv = dev->dev_private;
5071                 int clock_limit =
5072                         dev_priv->display.get_display_clock_speed(dev);
5073
5074                 /*
5075                  * Enable pixel doubling when the dot clock
5076                  * is > 90% of the (display) core speed.
5077                  *
5078                  * GDG double wide on either pipe,
5079                  * otherwise pipe A only.
5080                  */
5081                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5082                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5083                         clock_limit *= 2;
5084                         pipe_config->double_wide = true;
5085                 }
5086
5087                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5088                         return -EINVAL;
5089         }
5090
5091         /*
5092          * Pipe horizontal size must be even in:
5093          * - DVO ganged mode
5094          * - LVDS dual channel mode
5095          * - Double wide pipe
5096          */
5097         if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5098              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5099                 pipe_config->pipe_src_w &= ~1;
5100
5101         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5102          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5103          */
5104         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5105                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5106                 return -EINVAL;
5107
5108         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5109                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5110         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5111                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5112                  * for lvds. */
5113                 pipe_config->pipe_bpp = 8*3;
5114         }
5115
5116         if (HAS_IPS(dev))
5117                 hsw_compute_ips_config(crtc, pipe_config);
5118
5119         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
5120          * clock survives for now. */
5121         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5122                 pipe_config->shared_dpll = crtc->config.shared_dpll;
5123
5124         if (pipe_config->has_pch_encoder)
5125                 return ironlake_fdi_compute_config(crtc, pipe_config);
5126
5127         return 0;
5128 }
5129
5130 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5131 {
5132         return 400000; /* FIXME */
5133 }
5134
5135 static int i945_get_display_clock_speed(struct drm_device *dev)
5136 {
5137         return 400000;
5138 }
5139
5140 static int i915_get_display_clock_speed(struct drm_device *dev)
5141 {
5142         return 333000;
5143 }
5144
5145 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5146 {
5147         return 200000;
5148 }
5149
5150 static int pnv_get_display_clock_speed(struct drm_device *dev)
5151 {
5152         u16 gcfgc = 0;
5153
5154         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5155
5156         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5157         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5158                 return 267000;
5159         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5160                 return 333000;
5161         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5162                 return 444000;
5163         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5164                 return 200000;
5165         default:
5166                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5167         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5168                 return 133000;
5169         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5170                 return 167000;
5171         }
5172 }
5173
5174 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5175 {
5176         u16 gcfgc = 0;
5177
5178         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5179
5180         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5181                 return 133000;
5182         else {
5183                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5184                 case GC_DISPLAY_CLOCK_333_MHZ:
5185                         return 333000;
5186                 default:
5187                 case GC_DISPLAY_CLOCK_190_200_MHZ:
5188                         return 190000;
5189                 }
5190         }
5191 }
5192
5193 static int i865_get_display_clock_speed(struct drm_device *dev)
5194 {
5195         return 266000;
5196 }
5197
5198 static int i855_get_display_clock_speed(struct drm_device *dev)
5199 {
5200         u16 hpllcc = 0;
5201         /* Assume that the hardware is in the high speed state.  This
5202          * should be the default.
5203          */
5204         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5205         case GC_CLOCK_133_200:
5206         case GC_CLOCK_100_200:
5207                 return 200000;
5208         case GC_CLOCK_166_250:
5209                 return 250000;
5210         case GC_CLOCK_100_133:
5211                 return 133000;
5212         }
5213
5214         /* Shouldn't happen */
5215         return 0;
5216 }
5217
5218 static int i830_get_display_clock_speed(struct drm_device *dev)
5219 {
5220         return 133000;
5221 }
5222
5223 static void
5224 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5225 {
5226         while (*num > DATA_LINK_M_N_MASK ||
5227                *den > DATA_LINK_M_N_MASK) {
5228                 *num >>= 1;
5229                 *den >>= 1;
5230         }
5231 }
5232
5233 static void compute_m_n(unsigned int m, unsigned int n,
5234                         uint32_t *ret_m, uint32_t *ret_n)
5235 {
5236         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5237         *ret_m = div_u64((uint64_t) m * *ret_n, n);
5238         intel_reduce_m_n_ratio(ret_m, ret_n);
5239 }
5240
5241 void
5242 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5243                        int pixel_clock, int link_clock,
5244                        struct intel_link_m_n *m_n)
5245 {
5246         m_n->tu = 64;
5247
5248         compute_m_n(bits_per_pixel * pixel_clock,
5249                     link_clock * nlanes * 8,
5250                     &m_n->gmch_m, &m_n->gmch_n);
5251
5252         compute_m_n(pixel_clock, link_clock,
5253                     &m_n->link_m, &m_n->link_n);
5254 }
5255
5256 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5257 {
5258         if (i915.panel_use_ssc >= 0)
5259                 return i915.panel_use_ssc != 0;
5260         return dev_priv->vbt.lvds_use_ssc
5261                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5262 }
5263
5264 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5265 {
5266         struct drm_device *dev = crtc->dev;
5267         struct drm_i915_private *dev_priv = dev->dev_private;
5268         int refclk;
5269
5270         if (IS_VALLEYVIEW(dev)) {
5271                 refclk = 100000;
5272         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5273             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5274                 refclk = dev_priv->vbt.lvds_ssc_freq;
5275                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5276         } else if (!IS_GEN2(dev)) {
5277                 refclk = 96000;
5278         } else {
5279                 refclk = 48000;
5280         }
5281
5282         return refclk;
5283 }
5284
5285 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5286 {
5287         return (1 << dpll->n) << 16 | dpll->m2;
5288 }
5289
5290 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5291 {
5292         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5293 }
5294
5295 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5296                                      intel_clock_t *reduced_clock)
5297 {
5298         struct drm_device *dev = crtc->base.dev;
5299         u32 fp, fp2 = 0;
5300
5301         if (IS_PINEVIEW(dev)) {
5302                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5303                 if (reduced_clock)
5304                         fp2 = pnv_dpll_compute_fp(reduced_clock);
5305         } else {
5306                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5307                 if (reduced_clock)
5308                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
5309         }
5310
5311         crtc->config.dpll_hw_state.fp0 = fp;
5312
5313         crtc->lowfreq_avail = false;
5314         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5315             reduced_clock && i915.powersave) {
5316                 crtc->config.dpll_hw_state.fp1 = fp2;
5317                 crtc->lowfreq_avail = true;
5318         } else {
5319                 crtc->config.dpll_hw_state.fp1 = fp;
5320         }
5321 }
5322
5323 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5324                 pipe)
5325 {
5326         u32 reg_val;
5327
5328         /*
5329          * PLLB opamp always calibrates to max value of 0x3f, force enable it
5330          * and set it to a reasonable value instead.
5331          */
5332         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5333         reg_val &= 0xffffff00;
5334         reg_val |= 0x00000030;
5335         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5336
5337         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5338         reg_val &= 0x8cffffff;
5339         reg_val = 0x8c000000;
5340         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5341
5342         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5343         reg_val &= 0xffffff00;
5344         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5345
5346         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5347         reg_val &= 0x00ffffff;
5348         reg_val |= 0xb0000000;
5349         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5350 }
5351
5352 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5353                                          struct intel_link_m_n *m_n)
5354 {
5355         struct drm_device *dev = crtc->base.dev;
5356         struct drm_i915_private *dev_priv = dev->dev_private;
5357         int pipe = crtc->pipe;
5358
5359         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5360         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5361         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5362         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5363 }
5364
5365 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5366                                          struct intel_link_m_n *m_n)
5367 {
5368         struct drm_device *dev = crtc->base.dev;
5369         struct drm_i915_private *dev_priv = dev->dev_private;
5370         int pipe = crtc->pipe;
5371         enum transcoder transcoder = crtc->config.cpu_transcoder;
5372
5373         if (INTEL_INFO(dev)->gen >= 5) {
5374                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5375                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5376                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5377                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5378         } else {
5379                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5380                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5381                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5382                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5383         }
5384 }
5385
5386 static void intel_dp_set_m_n(struct intel_crtc *crtc)
5387 {
5388         if (crtc->config.has_pch_encoder)
5389                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5390         else
5391                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5392 }
5393
5394 static void vlv_update_pll(struct intel_crtc *crtc)
5395 {
5396         u32 dpll, dpll_md;
5397
5398         /*
5399          * Enable DPIO clock input. We should never disable the reference
5400          * clock for pipe B, since VGA hotplug / manual detection depends
5401          * on it.
5402          */
5403         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5404                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5405         /* We should never disable this, set it here for state tracking */
5406         if (crtc->pipe == PIPE_B)
5407                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5408         dpll |= DPLL_VCO_ENABLE;
5409         crtc->config.dpll_hw_state.dpll = dpll;
5410
5411         dpll_md = (crtc->config.pixel_multiplier - 1)
5412                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5413         crtc->config.dpll_hw_state.dpll_md = dpll_md;
5414 }
5415
5416 static void vlv_prepare_pll(struct intel_crtc *crtc)
5417 {
5418         struct drm_device *dev = crtc->base.dev;
5419         struct drm_i915_private *dev_priv = dev->dev_private;
5420         int pipe = crtc->pipe;
5421         u32 mdiv;
5422         u32 bestn, bestm1, bestm2, bestp1, bestp2;
5423         u32 coreclk, reg_val;
5424
5425         mutex_lock(&dev_priv->dpio_lock);
5426
5427         bestn = crtc->config.dpll.n;
5428         bestm1 = crtc->config.dpll.m1;
5429         bestm2 = crtc->config.dpll.m2;
5430         bestp1 = crtc->config.dpll.p1;
5431         bestp2 = crtc->config.dpll.p2;
5432
5433         /* See eDP HDMI DPIO driver vbios notes doc */
5434
5435         /* PLL B needs special handling */
5436         if (pipe == PIPE_B)
5437                 vlv_pllb_recal_opamp(dev_priv, pipe);
5438
5439         /* Set up Tx target for periodic Rcomp update */
5440         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5441
5442         /* Disable target IRef on PLL */
5443         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5444         reg_val &= 0x00ffffff;
5445         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5446
5447         /* Disable fast lock */
5448         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5449
5450         /* Set idtafcrecal before PLL is enabled */
5451         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5452         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5453         mdiv |= ((bestn << DPIO_N_SHIFT));
5454         mdiv |= (1 << DPIO_K_SHIFT);
5455
5456         /*
5457          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5458          * but we don't support that).
5459          * Note: don't use the DAC post divider as it seems unstable.
5460          */
5461         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5462         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5463
5464         mdiv |= DPIO_ENABLE_CALIBRATION;
5465         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5466
5467         /* Set HBR and RBR LPF coefficients */
5468         if (crtc->config.port_clock == 162000 ||
5469             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5470             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5471                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5472                                  0x009f0003);
5473         else
5474                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5475                                  0x00d0000f);
5476
5477         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5478             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5479                 /* Use SSC source */
5480                 if (pipe == PIPE_A)
5481                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5482                                          0x0df40000);
5483                 else
5484                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5485                                          0x0df70000);
5486         } else { /* HDMI or VGA */
5487                 /* Use bend source */
5488                 if (pipe == PIPE_A)
5489                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5490                                          0x0df70000);
5491                 else
5492                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5493                                          0x0df40000);
5494         }
5495
5496         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5497         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5498         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5499             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5500                 coreclk |= 0x01000000;
5501         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5502
5503         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5504         mutex_unlock(&dev_priv->dpio_lock);
5505 }
5506
5507 static void chv_update_pll(struct intel_crtc *crtc)
5508 {
5509         struct drm_device *dev = crtc->base.dev;
5510         struct drm_i915_private *dev_priv = dev->dev_private;
5511         int pipe = crtc->pipe;
5512         int dpll_reg = DPLL(crtc->pipe);
5513         enum dpio_channel port = vlv_pipe_to_channel(pipe);
5514         u32 val, loopfilter, intcoeff;
5515         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5516         int refclk;
5517
5518         mutex_lock(&dev_priv->dpio_lock);
5519
5520         bestn = crtc->config.dpll.n;
5521         bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5522         bestm1 = crtc->config.dpll.m1;
5523         bestm2 = crtc->config.dpll.m2 >> 22;
5524         bestp1 = crtc->config.dpll.p1;
5525         bestp2 = crtc->config.dpll.p2;
5526
5527         /*
5528          * Enable Refclk and SSC
5529          */
5530         val = I915_READ(dpll_reg);
5531         val |= (DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV);
5532         I915_WRITE(dpll_reg, val);
5533
5534         /* Propagate soft reset to data lane reset */
5535         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(port));
5536         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
5537         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), val);
5538
5539         /* Disable 10bit clock to display controller */
5540         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
5541         val &= ~DPIO_DCLKP_EN;
5542         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
5543
5544         /* p1 and p2 divider */
5545         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5546                         5 << DPIO_CHV_S1_DIV_SHIFT |
5547                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5548                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5549                         1 << DPIO_CHV_K_DIV_SHIFT);
5550
5551         /* Feedback post-divider - m2 */
5552         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5553
5554         /* Feedback refclk divider - n and m1 */
5555         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5556                         DPIO_CHV_M1_DIV_BY_2 |
5557                         1 << DPIO_CHV_N_DIV_SHIFT);
5558
5559         /* M2 fraction division */
5560         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5561
5562         /* M2 fraction division enable */
5563         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5564                        DPIO_CHV_FRAC_DIV_EN |
5565                        (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5566
5567         /* Loop filter */
5568         refclk = i9xx_get_refclk(&crtc->base, 0);
5569         loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5570                 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5571         if (refclk == 100000)
5572                 intcoeff = 11;
5573         else if (refclk == 38400)
5574                 intcoeff = 10;
5575         else
5576                 intcoeff = 9;
5577         loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5578         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5579
5580         /* AFC Recal */
5581         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5582                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5583                         DPIO_AFC_RECAL);
5584
5585         mutex_unlock(&dev_priv->dpio_lock);
5586 }
5587
5588 static void i9xx_update_pll(struct intel_crtc *crtc,
5589                             intel_clock_t *reduced_clock,
5590                             int num_connectors)
5591 {
5592         struct drm_device *dev = crtc->base.dev;
5593         struct drm_i915_private *dev_priv = dev->dev_private;
5594         u32 dpll;
5595         bool is_sdvo;
5596         struct dpll *clock = &crtc->config.dpll;
5597
5598         i9xx_update_pll_dividers(crtc, reduced_clock);
5599
5600         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5601                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5602
5603         dpll = DPLL_VGA_MODE_DIS;
5604
5605         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5606                 dpll |= DPLLB_MODE_LVDS;
5607         else
5608                 dpll |= DPLLB_MODE_DAC_SERIAL;
5609
5610         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5611                 dpll |= (crtc->config.pixel_multiplier - 1)
5612                         << SDVO_MULTIPLIER_SHIFT_HIRES;
5613         }
5614
5615         if (is_sdvo)
5616                 dpll |= DPLL_SDVO_HIGH_SPEED;
5617
5618         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5619                 dpll |= DPLL_SDVO_HIGH_SPEED;
5620
5621         /* compute bitmask from p1 value */
5622         if (IS_PINEVIEW(dev))
5623                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5624         else {
5625                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5626                 if (IS_G4X(dev) && reduced_clock)
5627                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5628         }
5629         switch (clock->p2) {
5630         case 5:
5631                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5632                 break;
5633         case 7:
5634                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5635                 break;
5636         case 10:
5637                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5638                 break;
5639         case 14:
5640                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5641                 break;
5642         }
5643         if (INTEL_INFO(dev)->gen >= 4)
5644                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5645
5646         if (crtc->config.sdvo_tv_clock)
5647                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5648         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5649                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5650                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5651         else
5652                 dpll |= PLL_REF_INPUT_DREFCLK;
5653
5654         dpll |= DPLL_VCO_ENABLE;
5655         crtc->config.dpll_hw_state.dpll = dpll;
5656
5657         if (INTEL_INFO(dev)->gen >= 4) {
5658                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5659                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5660                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5661         }
5662 }
5663
5664 static void i8xx_update_pll(struct intel_crtc *crtc,
5665                             intel_clock_t *reduced_clock,
5666                             int num_connectors)
5667 {
5668         struct drm_device *dev = crtc->base.dev;
5669         struct drm_i915_private *dev_priv = dev->dev_private;
5670         u32 dpll;
5671         struct dpll *clock = &crtc->config.dpll;
5672
5673         i9xx_update_pll_dividers(crtc, reduced_clock);
5674
5675         dpll = DPLL_VGA_MODE_DIS;
5676
5677         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5678                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5679         } else {
5680                 if (clock->p1 == 2)
5681                         dpll |= PLL_P1_DIVIDE_BY_TWO;
5682                 else
5683                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5684                 if (clock->p2 == 4)
5685                         dpll |= PLL_P2_DIVIDE_BY_4;
5686         }
5687
5688         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5689                 dpll |= DPLL_DVO_2X_MODE;
5690
5691         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5692                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5693                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5694         else
5695                 dpll |= PLL_REF_INPUT_DREFCLK;
5696
5697         dpll |= DPLL_VCO_ENABLE;
5698         crtc->config.dpll_hw_state.dpll = dpll;
5699 }
5700
5701 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5702 {
5703         struct drm_device *dev = intel_crtc->base.dev;
5704         struct drm_i915_private *dev_priv = dev->dev_private;
5705         enum pipe pipe = intel_crtc->pipe;
5706         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5707         struct drm_display_mode *adjusted_mode =
5708                 &intel_crtc->config.adjusted_mode;
5709         uint32_t crtc_vtotal, crtc_vblank_end;
5710         int vsyncshift = 0;
5711
5712         /* We need to be careful not to changed the adjusted mode, for otherwise
5713          * the hw state checker will get angry at the mismatch. */
5714         crtc_vtotal = adjusted_mode->crtc_vtotal;
5715         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5716
5717         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5718                 /* the chip adds 2 halflines automatically */
5719                 crtc_vtotal -= 1;
5720                 crtc_vblank_end -= 1;
5721
5722                 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5723                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5724                 else
5725                         vsyncshift = adjusted_mode->crtc_hsync_start -
5726                                 adjusted_mode->crtc_htotal / 2;
5727                 if (vsyncshift < 0)
5728                         vsyncshift += adjusted_mode->crtc_htotal;
5729         }
5730
5731         if (INTEL_INFO(dev)->gen > 3)
5732                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5733
5734         I915_WRITE(HTOTAL(cpu_transcoder),
5735                    (adjusted_mode->crtc_hdisplay - 1) |
5736                    ((adjusted_mode->crtc_htotal - 1) << 16));
5737         I915_WRITE(HBLANK(cpu_transcoder),
5738                    (adjusted_mode->crtc_hblank_start - 1) |
5739                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5740         I915_WRITE(HSYNC(cpu_transcoder),
5741                    (adjusted_mode->crtc_hsync_start - 1) |
5742                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5743
5744         I915_WRITE(VTOTAL(cpu_transcoder),
5745                    (adjusted_mode->crtc_vdisplay - 1) |
5746                    ((crtc_vtotal - 1) << 16));
5747         I915_WRITE(VBLANK(cpu_transcoder),
5748                    (adjusted_mode->crtc_vblank_start - 1) |
5749                    ((crtc_vblank_end - 1) << 16));
5750         I915_WRITE(VSYNC(cpu_transcoder),
5751                    (adjusted_mode->crtc_vsync_start - 1) |
5752                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5753
5754         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5755          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5756          * documented on the DDI_FUNC_CTL register description, EDP Input Select
5757          * bits. */
5758         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5759             (pipe == PIPE_B || pipe == PIPE_C))
5760                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5761
5762         /* pipesrc controls the size that is scaled from, which should
5763          * always be the user's requested size.
5764          */
5765         I915_WRITE(PIPESRC(pipe),
5766                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
5767                    (intel_crtc->config.pipe_src_h - 1));
5768 }
5769
5770 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5771                                    struct intel_crtc_config *pipe_config)
5772 {
5773         struct drm_device *dev = crtc->base.dev;
5774         struct drm_i915_private *dev_priv = dev->dev_private;
5775         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5776         uint32_t tmp;
5777
5778         tmp = I915_READ(HTOTAL(cpu_transcoder));
5779         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5780         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5781         tmp = I915_READ(HBLANK(cpu_transcoder));
5782         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5783         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5784         tmp = I915_READ(HSYNC(cpu_transcoder));
5785         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5786         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5787
5788         tmp = I915_READ(VTOTAL(cpu_transcoder));
5789         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5790         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5791         tmp = I915_READ(VBLANK(cpu_transcoder));
5792         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5793         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5794         tmp = I915_READ(VSYNC(cpu_transcoder));
5795         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5796         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5797
5798         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5799                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5800                 pipe_config->adjusted_mode.crtc_vtotal += 1;
5801                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5802         }
5803
5804         tmp = I915_READ(PIPESRC(crtc->pipe));
5805         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5806         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5807
5808         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5809         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5810 }
5811
5812 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5813                                  struct intel_crtc_config *pipe_config)
5814 {
5815         mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5816         mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5817         mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5818         mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5819
5820         mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5821         mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5822         mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5823         mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5824
5825         mode->flags = pipe_config->adjusted_mode.flags;
5826
5827         mode->clock = pipe_config->adjusted_mode.crtc_clock;
5828         mode->flags |= pipe_config->adjusted_mode.flags;
5829 }
5830
5831 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5832 {
5833         struct drm_device *dev = intel_crtc->base.dev;
5834         struct drm_i915_private *dev_priv = dev->dev_private;
5835         uint32_t pipeconf;
5836
5837         pipeconf = 0;
5838
5839         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5840             I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5841                 pipeconf |= PIPECONF_ENABLE;
5842
5843         if (intel_crtc->config.double_wide)
5844                 pipeconf |= PIPECONF_DOUBLE_WIDE;
5845
5846         /* only g4x and later have fancy bpc/dither controls */
5847         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5848                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5849                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5850                         pipeconf |= PIPECONF_DITHER_EN |
5851                                     PIPECONF_DITHER_TYPE_SP;
5852
5853                 switch (intel_crtc->config.pipe_bpp) {
5854                 case 18:
5855                         pipeconf |= PIPECONF_6BPC;
5856                         break;
5857                 case 24:
5858                         pipeconf |= PIPECONF_8BPC;
5859                         break;
5860                 case 30:
5861                         pipeconf |= PIPECONF_10BPC;
5862                         break;
5863                 default:
5864                         /* Case prevented by intel_choose_pipe_bpp_dither. */
5865                         BUG();
5866                 }
5867         }
5868
5869         if (HAS_PIPE_CXSR(dev)) {
5870                 if (intel_crtc->lowfreq_avail) {
5871                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5872                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5873                 } else {
5874                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5875                 }
5876         }
5877
5878         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
5879                 if (INTEL_INFO(dev)->gen < 4 ||
5880                     intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5881                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5882                 else
5883                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
5884         } else
5885                 pipeconf |= PIPECONF_PROGRESSIVE;
5886
5887         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5888                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5889
5890         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5891         POSTING_READ(PIPECONF(intel_crtc->pipe));
5892 }
5893
5894 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5895                               int x, int y,
5896                               struct drm_framebuffer *fb)
5897 {
5898         struct drm_device *dev = crtc->dev;
5899         struct drm_i915_private *dev_priv = dev->dev_private;
5900         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5901         int refclk, num_connectors = 0;
5902         intel_clock_t clock, reduced_clock;
5903         bool ok, has_reduced_clock = false;
5904         bool is_lvds = false, is_dsi = false;
5905         struct intel_encoder *encoder;
5906         const intel_limit_t *limit;
5907
5908         for_each_encoder_on_crtc(dev, crtc, encoder) {
5909                 switch (encoder->type) {
5910                 case INTEL_OUTPUT_LVDS:
5911                         is_lvds = true;
5912                         break;
5913                 case INTEL_OUTPUT_DSI:
5914                         is_dsi = true;
5915                         break;
5916                 }
5917
5918                 num_connectors++;
5919         }
5920
5921         if (is_dsi)
5922                 return 0;
5923
5924         if (!intel_crtc->config.clock_set) {
5925                 refclk = i9xx_get_refclk(crtc, num_connectors);
5926
5927                 /*
5928                  * Returns a set of divisors for the desired target clock with
5929                  * the given refclk, or FALSE.  The returned values represent
5930                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5931                  * 2) / p1 / p2.
5932                  */
5933                 limit = intel_limit(crtc, refclk);
5934                 ok = dev_priv->display.find_dpll(limit, crtc,
5935                                                  intel_crtc->config.port_clock,
5936                                                  refclk, NULL, &clock);
5937                 if (!ok) {
5938                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5939                         return -EINVAL;
5940                 }
5941
5942                 if (is_lvds && dev_priv->lvds_downclock_avail) {
5943                         /*
5944                          * Ensure we match the reduced clock's P to the target
5945                          * clock.  If the clocks don't match, we can't switch
5946                          * the display clock by using the FP0/FP1. In such case
5947                          * we will disable the LVDS downclock feature.
5948                          */
5949                         has_reduced_clock =
5950                                 dev_priv->display.find_dpll(limit, crtc,
5951                                                             dev_priv->lvds_downclock,
5952                                                             refclk, &clock,
5953                                                             &reduced_clock);
5954                 }
5955                 /* Compat-code for transition, will disappear. */
5956                 intel_crtc->config.dpll.n = clock.n;
5957                 intel_crtc->config.dpll.m1 = clock.m1;
5958                 intel_crtc->config.dpll.m2 = clock.m2;
5959                 intel_crtc->config.dpll.p1 = clock.p1;
5960                 intel_crtc->config.dpll.p2 = clock.p2;
5961         }
5962
5963         if (IS_GEN2(dev)) {
5964                 i8xx_update_pll(intel_crtc,
5965                                 has_reduced_clock ? &reduced_clock : NULL,
5966                                 num_connectors);
5967         } else if (IS_CHERRYVIEW(dev)) {
5968                 chv_update_pll(intel_crtc);
5969         } else if (IS_VALLEYVIEW(dev)) {
5970                 vlv_update_pll(intel_crtc);
5971         } else {
5972                 i9xx_update_pll(intel_crtc,
5973                                 has_reduced_clock ? &reduced_clock : NULL,
5974                                 num_connectors);
5975         }
5976
5977         return 0;
5978 }
5979
5980 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5981                                  struct intel_crtc_config *pipe_config)
5982 {
5983         struct drm_device *dev = crtc->base.dev;
5984         struct drm_i915_private *dev_priv = dev->dev_private;
5985         uint32_t tmp;
5986
5987         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
5988                 return;
5989
5990         tmp = I915_READ(PFIT_CONTROL);
5991         if (!(tmp & PFIT_ENABLE))
5992                 return;
5993
5994         /* Check whether the pfit is attached to our pipe. */
5995         if (INTEL_INFO(dev)->gen < 4) {
5996                 if (crtc->pipe != PIPE_B)
5997                         return;
5998         } else {
5999                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6000                         return;
6001         }
6002
6003         pipe_config->gmch_pfit.control = tmp;
6004         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6005         if (INTEL_INFO(dev)->gen < 5)
6006                 pipe_config->gmch_pfit.lvds_border_bits =
6007                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6008 }
6009
6010 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6011                                struct intel_crtc_config *pipe_config)
6012 {
6013         struct drm_device *dev = crtc->base.dev;
6014         struct drm_i915_private *dev_priv = dev->dev_private;
6015         int pipe = pipe_config->cpu_transcoder;
6016         intel_clock_t clock;
6017         u32 mdiv;
6018         int refclk = 100000;
6019
6020         mutex_lock(&dev_priv->dpio_lock);
6021         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6022         mutex_unlock(&dev_priv->dpio_lock);
6023
6024         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6025         clock.m2 = mdiv & DPIO_M2DIV_MASK;
6026         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6027         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6028         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6029
6030         vlv_clock(refclk, &clock);
6031
6032         /* clock.dot is the fast clock */
6033         pipe_config->port_clock = clock.dot / 5;
6034 }
6035
6036 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6037                                   struct intel_plane_config *plane_config)
6038 {
6039         struct drm_device *dev = crtc->base.dev;
6040         struct drm_i915_private *dev_priv = dev->dev_private;
6041         u32 val, base, offset;
6042         int pipe = crtc->pipe, plane = crtc->plane;
6043         int fourcc, pixel_format;
6044         int aligned_height;
6045
6046         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6047         if (!crtc->base.primary->fb) {
6048                 DRM_DEBUG_KMS("failed to alloc fb\n");
6049                 return;
6050         }
6051
6052         val = I915_READ(DSPCNTR(plane));
6053
6054         if (INTEL_INFO(dev)->gen >= 4)
6055                 if (val & DISPPLANE_TILED)
6056                         plane_config->tiled = true;
6057
6058         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6059         fourcc = intel_format_to_fourcc(pixel_format);
6060         crtc->base.primary->fb->pixel_format = fourcc;
6061         crtc->base.primary->fb->bits_per_pixel =
6062                 drm_format_plane_cpp(fourcc, 0) * 8;
6063
6064         if (INTEL_INFO(dev)->gen >= 4) {
6065                 if (plane_config->tiled)
6066                         offset = I915_READ(DSPTILEOFF(plane));
6067                 else
6068                         offset = I915_READ(DSPLINOFF(plane));
6069                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6070         } else {
6071                 base = I915_READ(DSPADDR(plane));
6072         }
6073         plane_config->base = base;
6074
6075         val = I915_READ(PIPESRC(pipe));
6076         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6077         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6078
6079         val = I915_READ(DSPSTRIDE(pipe));
6080         crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
6081
6082         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6083                                             plane_config->tiled);
6084
6085         plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
6086                                    aligned_height, PAGE_SIZE);
6087
6088         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6089                       pipe, plane, crtc->base.primary->fb->width,
6090                       crtc->base.primary->fb->height,
6091                       crtc->base.primary->fb->bits_per_pixel, base,
6092                       crtc->base.primary->fb->pitches[0],
6093                       plane_config->size);
6094
6095 }
6096
6097 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6098                                struct intel_crtc_config *pipe_config)
6099 {
6100         struct drm_device *dev = crtc->base.dev;
6101         struct drm_i915_private *dev_priv = dev->dev_private;
6102         int pipe = pipe_config->cpu_transcoder;
6103         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6104         intel_clock_t clock;
6105         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6106         int refclk = 100000;
6107
6108         mutex_lock(&dev_priv->dpio_lock);
6109         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6110         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6111         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6112         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6113         mutex_unlock(&dev_priv->dpio_lock);
6114
6115         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6116         clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6117         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6118         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6119         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6120
6121         chv_clock(refclk, &clock);
6122
6123         /* clock.dot is the fast clock */
6124         pipe_config->port_clock = clock.dot / 5;
6125 }
6126
6127 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6128                                  struct intel_crtc_config *pipe_config)
6129 {
6130         struct drm_device *dev = crtc->base.dev;
6131         struct drm_i915_private *dev_priv = dev->dev_private;
6132         uint32_t tmp;
6133
6134         if (!intel_display_power_enabled(dev_priv,
6135                                          POWER_DOMAIN_PIPE(crtc->pipe)))
6136                 return false;
6137
6138         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6139         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6140
6141         tmp = I915_READ(PIPECONF(crtc->pipe));
6142         if (!(tmp & PIPECONF_ENABLE))
6143                 return false;
6144
6145         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6146                 switch (tmp & PIPECONF_BPC_MASK) {
6147                 case PIPECONF_6BPC:
6148                         pipe_config->pipe_bpp = 18;
6149                         break;
6150                 case PIPECONF_8BPC:
6151                         pipe_config->pipe_bpp = 24;
6152                         break;
6153                 case PIPECONF_10BPC:
6154                         pipe_config->pipe_bpp = 30;
6155                         break;
6156                 default:
6157                         break;
6158                 }
6159         }
6160
6161         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6162                 pipe_config->limited_color_range = true;
6163
6164         if (INTEL_INFO(dev)->gen < 4)
6165                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6166
6167         intel_get_pipe_timings(crtc, pipe_config);
6168
6169         i9xx_get_pfit_config(crtc, pipe_config);
6170
6171         if (INTEL_INFO(dev)->gen >= 4) {
6172                 tmp = I915_READ(DPLL_MD(crtc->pipe));
6173                 pipe_config->pixel_multiplier =
6174                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6175                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6176                 pipe_config->dpll_hw_state.dpll_md = tmp;
6177         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6178                 tmp = I915_READ(DPLL(crtc->pipe));
6179                 pipe_config->pixel_multiplier =
6180                         ((tmp & SDVO_MULTIPLIER_MASK)
6181                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6182         } else {
6183                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6184                  * port and will be fixed up in the encoder->get_config
6185                  * function. */
6186                 pipe_config->pixel_multiplier = 1;
6187         }
6188         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6189         if (!IS_VALLEYVIEW(dev)) {
6190                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6191                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6192         } else {
6193                 /* Mask out read-only status bits. */
6194                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6195                                                      DPLL_PORTC_READY_MASK |
6196                                                      DPLL_PORTB_READY_MASK);
6197         }
6198
6199         if (IS_CHERRYVIEW(dev))
6200                 chv_crtc_clock_get(crtc, pipe_config);
6201         else if (IS_VALLEYVIEW(dev))
6202                 vlv_crtc_clock_get(crtc, pipe_config);
6203         else
6204                 i9xx_crtc_clock_get(crtc, pipe_config);
6205
6206         return true;
6207 }
6208
6209 static void ironlake_init_pch_refclk(struct drm_device *dev)
6210 {
6211         struct drm_i915_private *dev_priv = dev->dev_private;
6212         struct drm_mode_config *mode_config = &dev->mode_config;
6213         struct intel_encoder *encoder;
6214         u32 val, final;
6215         bool has_lvds = false;
6216         bool has_cpu_edp = false;
6217         bool has_panel = false;
6218         bool has_ck505 = false;
6219         bool can_ssc = false;
6220
6221         /* We need to take the global config into account */
6222         list_for_each_entry(encoder, &mode_config->encoder_list,
6223                             base.head) {
6224                 switch (encoder->type) {
6225                 case INTEL_OUTPUT_LVDS:
6226                         has_panel = true;
6227                         has_lvds = true;
6228                         break;
6229                 case INTEL_OUTPUT_EDP:
6230                         has_panel = true;
6231                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6232                                 has_cpu_edp = true;
6233                         break;
6234                 }
6235         }
6236
6237         if (HAS_PCH_IBX(dev)) {
6238                 has_ck505 = dev_priv->vbt.display_clock_mode;
6239                 can_ssc = has_ck505;
6240         } else {
6241                 has_ck505 = false;
6242                 can_ssc = true;
6243         }
6244
6245         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6246                       has_panel, has_lvds, has_ck505);
6247
6248         /* Ironlake: try to setup display ref clock before DPLL
6249          * enabling. This is only under driver's control after
6250          * PCH B stepping, previous chipset stepping should be
6251          * ignoring this setting.
6252          */
6253         val = I915_READ(PCH_DREF_CONTROL);
6254
6255         /* As we must carefully and slowly disable/enable each source in turn,
6256          * compute the final state we want first and check if we need to
6257          * make any changes at all.
6258          */
6259         final = val;
6260         final &= ~DREF_NONSPREAD_SOURCE_MASK;
6261         if (has_ck505)
6262                 final |= DREF_NONSPREAD_CK505_ENABLE;
6263         else
6264                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6265
6266         final &= ~DREF_SSC_SOURCE_MASK;
6267         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6268         final &= ~DREF_SSC1_ENABLE;
6269
6270         if (has_panel) {
6271                 final |= DREF_SSC_SOURCE_ENABLE;
6272
6273                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6274                         final |= DREF_SSC1_ENABLE;
6275
6276                 if (has_cpu_edp) {
6277                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
6278                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6279                         else
6280                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6281                 } else
6282                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6283         } else {
6284                 final |= DREF_SSC_SOURCE_DISABLE;
6285                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6286         }
6287
6288         if (final == val)
6289                 return;
6290
6291         /* Always enable nonspread source */
6292         val &= ~DREF_NONSPREAD_SOURCE_MASK;
6293
6294         if (has_ck505)
6295                 val |= DREF_NONSPREAD_CK505_ENABLE;
6296         else
6297                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6298
6299         if (has_panel) {
6300                 val &= ~DREF_SSC_SOURCE_MASK;
6301                 val |= DREF_SSC_SOURCE_ENABLE;
6302
6303                 /* SSC must be turned on before enabling the CPU output  */
6304                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6305                         DRM_DEBUG_KMS("Using SSC on panel\n");
6306                         val |= DREF_SSC1_ENABLE;
6307                 } else
6308                         val &= ~DREF_SSC1_ENABLE;
6309
6310                 /* Get SSC going before enabling the outputs */
6311                 I915_WRITE(PCH_DREF_CONTROL, val);
6312                 POSTING_READ(PCH_DREF_CONTROL);
6313                 udelay(200);
6314
6315                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6316
6317                 /* Enable CPU source on CPU attached eDP */
6318                 if (has_cpu_edp) {
6319                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6320                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
6321                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6322                         } else
6323                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6324                 } else
6325                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6326
6327                 I915_WRITE(PCH_DREF_CONTROL, val);
6328                 POSTING_READ(PCH_DREF_CONTROL);
6329                 udelay(200);
6330         } else {
6331                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6332
6333                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6334
6335                 /* Turn off CPU output */
6336                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6337
6338                 I915_WRITE(PCH_DREF_CONTROL, val);
6339                 POSTING_READ(PCH_DREF_CONTROL);
6340                 udelay(200);
6341
6342                 /* Turn off the SSC source */
6343                 val &= ~DREF_SSC_SOURCE_MASK;
6344                 val |= DREF_SSC_SOURCE_DISABLE;
6345
6346                 /* Turn off SSC1 */
6347                 val &= ~DREF_SSC1_ENABLE;
6348
6349                 I915_WRITE(PCH_DREF_CONTROL, val);
6350                 POSTING_READ(PCH_DREF_CONTROL);
6351                 udelay(200);
6352         }
6353
6354         BUG_ON(val != final);
6355 }
6356
6357 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6358 {
6359         uint32_t tmp;
6360
6361         tmp = I915_READ(SOUTH_CHICKEN2);
6362         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6363         I915_WRITE(SOUTH_CHICKEN2, tmp);
6364
6365         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6366                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6367                 DRM_ERROR("FDI mPHY reset assert timeout\n");
6368
6369         tmp = I915_READ(SOUTH_CHICKEN2);
6370         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6371         I915_WRITE(SOUTH_CHICKEN2, tmp);
6372
6373         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6374                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6375                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6376 }
6377
6378 /* WaMPhyProgramming:hsw */
6379 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6380 {
6381         uint32_t tmp;
6382
6383         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6384         tmp &= ~(0xFF << 24);
6385         tmp |= (0x12 << 24);
6386         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6387
6388         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6389         tmp |= (1 << 11);
6390         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6391
6392         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6393         tmp |= (1 << 11);
6394         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6395
6396         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6397         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6398         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6399
6400         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6401         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6402         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6403
6404         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6405         tmp &= ~(7 << 13);
6406         tmp |= (5 << 13);
6407         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6408
6409         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6410         tmp &= ~(7 << 13);
6411         tmp |= (5 << 13);
6412         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6413
6414         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6415         tmp &= ~0xFF;
6416         tmp |= 0x1C;
6417         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6418
6419         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6420         tmp &= ~0xFF;
6421         tmp |= 0x1C;
6422         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6423
6424         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6425         tmp &= ~(0xFF << 16);
6426         tmp |= (0x1C << 16);
6427         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6428
6429         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6430         tmp &= ~(0xFF << 16);
6431         tmp |= (0x1C << 16);
6432         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6433
6434         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6435         tmp |= (1 << 27);
6436         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6437
6438         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6439         tmp |= (1 << 27);
6440         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6441
6442         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6443         tmp &= ~(0xF << 28);
6444         tmp |= (4 << 28);
6445         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6446
6447         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6448         tmp &= ~(0xF << 28);
6449         tmp |= (4 << 28);
6450         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6451 }
6452
6453 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6454  * Programming" based on the parameters passed:
6455  * - Sequence to enable CLKOUT_DP
6456  * - Sequence to enable CLKOUT_DP without spread
6457  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6458  */
6459 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6460                                  bool with_fdi)
6461 {
6462         struct drm_i915_private *dev_priv = dev->dev_private;
6463         uint32_t reg, tmp;
6464
6465         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6466                 with_spread = true;
6467         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6468                  with_fdi, "LP PCH doesn't have FDI\n"))
6469                 with_fdi = false;
6470
6471         mutex_lock(&dev_priv->dpio_lock);
6472
6473         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6474         tmp &= ~SBI_SSCCTL_DISABLE;
6475         tmp |= SBI_SSCCTL_PATHALT;
6476         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6477
6478         udelay(24);
6479
6480         if (with_spread) {
6481                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6482                 tmp &= ~SBI_SSCCTL_PATHALT;
6483                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6484
6485                 if (with_fdi) {
6486                         lpt_reset_fdi_mphy(dev_priv);
6487                         lpt_program_fdi_mphy(dev_priv);
6488                 }
6489         }
6490
6491         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6492                SBI_GEN0 : SBI_DBUFF0;
6493         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6494         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6495         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6496
6497         mutex_unlock(&dev_priv->dpio_lock);
6498 }
6499
6500 /* Sequence to disable CLKOUT_DP */
6501 static void lpt_disable_clkout_dp(struct drm_device *dev)
6502 {
6503         struct drm_i915_private *dev_priv = dev->dev_private;
6504         uint32_t reg, tmp;
6505
6506         mutex_lock(&dev_priv->dpio_lock);
6507
6508         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6509                SBI_GEN0 : SBI_DBUFF0;
6510         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6511         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6512         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6513
6514         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6515         if (!(tmp & SBI_SSCCTL_DISABLE)) {
6516                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6517                         tmp |= SBI_SSCCTL_PATHALT;
6518                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6519                         udelay(32);
6520                 }
6521                 tmp |= SBI_SSCCTL_DISABLE;
6522                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6523         }
6524
6525         mutex_unlock(&dev_priv->dpio_lock);
6526 }
6527
6528 static void lpt_init_pch_refclk(struct drm_device *dev)
6529 {
6530         struct drm_mode_config *mode_config = &dev->mode_config;
6531         struct intel_encoder *encoder;
6532         bool has_vga = false;
6533
6534         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
6535                 switch (encoder->type) {
6536                 case INTEL_OUTPUT_ANALOG:
6537                         has_vga = true;
6538                         break;
6539                 }
6540         }
6541
6542         if (has_vga)
6543                 lpt_enable_clkout_dp(dev, true, true);
6544         else
6545                 lpt_disable_clkout_dp(dev);
6546 }
6547
6548 /*
6549  * Initialize reference clocks when the driver loads
6550  */
6551 void intel_init_pch_refclk(struct drm_device *dev)
6552 {
6553         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6554                 ironlake_init_pch_refclk(dev);
6555         else if (HAS_PCH_LPT(dev))
6556                 lpt_init_pch_refclk(dev);
6557 }
6558
6559 static int ironlake_get_refclk(struct drm_crtc *crtc)
6560 {
6561         struct drm_device *dev = crtc->dev;
6562         struct drm_i915_private *dev_priv = dev->dev_private;
6563         struct intel_encoder *encoder;
6564         int num_connectors = 0;
6565         bool is_lvds = false;
6566
6567         for_each_encoder_on_crtc(dev, crtc, encoder) {
6568                 switch (encoder->type) {
6569                 case INTEL_OUTPUT_LVDS:
6570                         is_lvds = true;
6571                         break;
6572                 }
6573                 num_connectors++;
6574         }
6575
6576         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6577                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6578                               dev_priv->vbt.lvds_ssc_freq);
6579                 return dev_priv->vbt.lvds_ssc_freq;
6580         }
6581
6582         return 120000;
6583 }
6584
6585 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6586 {
6587         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6588         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6589         int pipe = intel_crtc->pipe;
6590         uint32_t val;
6591
6592         val = 0;
6593
6594         switch (intel_crtc->config.pipe_bpp) {
6595         case 18:
6596                 val |= PIPECONF_6BPC;
6597                 break;
6598         case 24:
6599                 val |= PIPECONF_8BPC;
6600                 break;
6601         case 30:
6602                 val |= PIPECONF_10BPC;
6603                 break;
6604         case 36:
6605                 val |= PIPECONF_12BPC;
6606                 break;
6607         default:
6608                 /* Case prevented by intel_choose_pipe_bpp_dither. */
6609                 BUG();
6610         }
6611
6612         if (intel_crtc->config.dither)
6613                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6614
6615         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6616                 val |= PIPECONF_INTERLACED_ILK;
6617         else
6618                 val |= PIPECONF_PROGRESSIVE;
6619
6620         if (intel_crtc->config.limited_color_range)
6621                 val |= PIPECONF_COLOR_RANGE_SELECT;
6622
6623         I915_WRITE(PIPECONF(pipe), val);
6624         POSTING_READ(PIPECONF(pipe));
6625 }
6626
6627 /*
6628  * Set up the pipe CSC unit.
6629  *
6630  * Currently only full range RGB to limited range RGB conversion
6631  * is supported, but eventually this should handle various
6632  * RGB<->YCbCr scenarios as well.
6633  */
6634 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6635 {
6636         struct drm_device *dev = crtc->dev;
6637         struct drm_i915_private *dev_priv = dev->dev_private;
6638         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6639         int pipe = intel_crtc->pipe;
6640         uint16_t coeff = 0x7800; /* 1.0 */
6641
6642         /*
6643          * TODO: Check what kind of values actually come out of the pipe
6644          * with these coeff/postoff values and adjust to get the best
6645          * accuracy. Perhaps we even need to take the bpc value into
6646          * consideration.
6647          */
6648
6649         if (intel_crtc->config.limited_color_range)
6650                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6651
6652         /*
6653          * GY/GU and RY/RU should be the other way around according
6654          * to BSpec, but reality doesn't agree. Just set them up in
6655          * a way that results in the correct picture.
6656          */
6657         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6658         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6659
6660         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6661         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6662
6663         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6664         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6665
6666         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6667         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6668         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6669
6670         if (INTEL_INFO(dev)->gen > 6) {
6671                 uint16_t postoff = 0;
6672
6673                 if (intel_crtc->config.limited_color_range)
6674                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
6675
6676                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6677                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6678                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6679
6680                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6681         } else {
6682                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6683
6684                 if (intel_crtc->config.limited_color_range)
6685                         mode |= CSC_BLACK_SCREEN_OFFSET;
6686
6687                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6688         }
6689 }
6690
6691 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6692 {
6693         struct drm_device *dev = crtc->dev;
6694         struct drm_i915_private *dev_priv = dev->dev_private;
6695         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6696         enum pipe pipe = intel_crtc->pipe;
6697         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6698         uint32_t val;
6699
6700         val = 0;
6701
6702         if (IS_HASWELL(dev) && intel_crtc->config.dither)
6703                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6704
6705         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6706                 val |= PIPECONF_INTERLACED_ILK;
6707         else
6708                 val |= PIPECONF_PROGRESSIVE;
6709
6710         I915_WRITE(PIPECONF(cpu_transcoder), val);
6711         POSTING_READ(PIPECONF(cpu_transcoder));
6712
6713         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6714         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6715
6716         if (IS_BROADWELL(dev)) {
6717                 val = 0;
6718
6719                 switch (intel_crtc->config.pipe_bpp) {
6720                 case 18:
6721                         val |= PIPEMISC_DITHER_6_BPC;
6722                         break;
6723                 case 24:
6724                         val |= PIPEMISC_DITHER_8_BPC;
6725                         break;
6726                 case 30:
6727                         val |= PIPEMISC_DITHER_10_BPC;
6728                         break;
6729                 case 36:
6730                         val |= PIPEMISC_DITHER_12_BPC;
6731                         break;
6732                 default:
6733                         /* Case prevented by pipe_config_set_bpp. */
6734                         BUG();
6735                 }
6736
6737                 if (intel_crtc->config.dither)
6738                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6739
6740                 I915_WRITE(PIPEMISC(pipe), val);
6741         }
6742 }
6743
6744 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6745                                     intel_clock_t *clock,
6746                                     bool *has_reduced_clock,
6747                                     intel_clock_t *reduced_clock)
6748 {
6749         struct drm_device *dev = crtc->dev;
6750         struct drm_i915_private *dev_priv = dev->dev_private;
6751         struct intel_encoder *intel_encoder;
6752         int refclk;
6753         const intel_limit_t *limit;
6754         bool ret, is_lvds = false;
6755
6756         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6757                 switch (intel_encoder->type) {
6758                 case INTEL_OUTPUT_LVDS:
6759                         is_lvds = true;
6760                         break;
6761                 }
6762         }
6763
6764         refclk = ironlake_get_refclk(crtc);
6765
6766         /*
6767          * Returns a set of divisors for the desired target clock with the given
6768          * refclk, or FALSE.  The returned values represent the clock equation:
6769          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6770          */
6771         limit = intel_limit(crtc, refclk);
6772         ret = dev_priv->display.find_dpll(limit, crtc,
6773                                           to_intel_crtc(crtc)->config.port_clock,
6774                                           refclk, NULL, clock);
6775         if (!ret)
6776                 return false;
6777
6778         if (is_lvds && dev_priv->lvds_downclock_avail) {
6779                 /*
6780                  * Ensure we match the reduced clock's P to the target clock.
6781                  * If the clocks don't match, we can't switch the display clock
6782                  * by using the FP0/FP1. In such case we will disable the LVDS
6783                  * downclock feature.
6784                 */
6785                 *has_reduced_clock =
6786                         dev_priv->display.find_dpll(limit, crtc,
6787                                                     dev_priv->lvds_downclock,
6788                                                     refclk, clock,
6789                                                     reduced_clock);
6790         }
6791
6792         return true;
6793 }
6794
6795 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6796 {
6797         /*
6798          * Account for spread spectrum to avoid
6799          * oversubscribing the link. Max center spread
6800          * is 2.5%; use 5% for safety's sake.
6801          */
6802         u32 bps = target_clock * bpp * 21 / 20;
6803         return DIV_ROUND_UP(bps, link_bw * 8);
6804 }
6805
6806 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6807 {
6808         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6809 }
6810
6811 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6812                                       u32 *fp,
6813                                       intel_clock_t *reduced_clock, u32 *fp2)
6814 {
6815         struct drm_crtc *crtc = &intel_crtc->base;
6816         struct drm_device *dev = crtc->dev;
6817         struct drm_i915_private *dev_priv = dev->dev_private;
6818         struct intel_encoder *intel_encoder;
6819         uint32_t dpll;
6820         int factor, num_connectors = 0;
6821         bool is_lvds = false, is_sdvo = false;
6822
6823         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6824                 switch (intel_encoder->type) {
6825                 case INTEL_OUTPUT_LVDS:
6826                         is_lvds = true;
6827                         break;
6828                 case INTEL_OUTPUT_SDVO:
6829                 case INTEL_OUTPUT_HDMI:
6830                         is_sdvo = true;
6831                         break;
6832                 }
6833
6834                 num_connectors++;
6835         }
6836
6837         /* Enable autotuning of the PLL clock (if permissible) */
6838         factor = 21;
6839         if (is_lvds) {
6840                 if ((intel_panel_use_ssc(dev_priv) &&
6841                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
6842                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6843                         factor = 25;
6844         } else if (intel_crtc->config.sdvo_tv_clock)
6845                 factor = 20;
6846
6847         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6848                 *fp |= FP_CB_TUNE;
6849
6850         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6851                 *fp2 |= FP_CB_TUNE;
6852
6853         dpll = 0;
6854
6855         if (is_lvds)
6856                 dpll |= DPLLB_MODE_LVDS;
6857         else
6858                 dpll |= DPLLB_MODE_DAC_SERIAL;
6859
6860         dpll |= (intel_crtc->config.pixel_multiplier - 1)
6861                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6862
6863         if (is_sdvo)
6864                 dpll |= DPLL_SDVO_HIGH_SPEED;
6865         if (intel_crtc->config.has_dp_encoder)
6866                 dpll |= DPLL_SDVO_HIGH_SPEED;
6867
6868         /* compute bitmask from p1 value */
6869         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6870         /* also FPA1 */
6871         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6872
6873         switch (intel_crtc->config.dpll.p2) {
6874         case 5:
6875                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6876                 break;
6877         case 7:
6878                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6879                 break;
6880         case 10:
6881                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6882                 break;
6883         case 14:
6884                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6885                 break;
6886         }
6887
6888         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6889                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6890         else
6891                 dpll |= PLL_REF_INPUT_DREFCLK;
6892
6893         return dpll | DPLL_VCO_ENABLE;
6894 }
6895
6896 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
6897                                   int x, int y,
6898                                   struct drm_framebuffer *fb)
6899 {
6900         struct drm_device *dev = crtc->dev;
6901         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6902         int num_connectors = 0;
6903         intel_clock_t clock, reduced_clock;
6904         u32 dpll = 0, fp = 0, fp2 = 0;
6905         bool ok, has_reduced_clock = false;
6906         bool is_lvds = false;
6907         struct intel_encoder *encoder;
6908         struct intel_shared_dpll *pll;
6909
6910         for_each_encoder_on_crtc(dev, crtc, encoder) {
6911                 switch (encoder->type) {
6912                 case INTEL_OUTPUT_LVDS:
6913                         is_lvds = true;
6914                         break;
6915                 }
6916
6917                 num_connectors++;
6918         }
6919
6920         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6921              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6922
6923         ok = ironlake_compute_clocks(crtc, &clock,
6924                                      &has_reduced_clock, &reduced_clock);
6925         if (!ok && !intel_crtc->config.clock_set) {
6926                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6927                 return -EINVAL;
6928         }
6929         /* Compat-code for transition, will disappear. */
6930         if (!intel_crtc->config.clock_set) {
6931                 intel_crtc->config.dpll.n = clock.n;
6932                 intel_crtc->config.dpll.m1 = clock.m1;
6933                 intel_crtc->config.dpll.m2 = clock.m2;
6934                 intel_crtc->config.dpll.p1 = clock.p1;
6935                 intel_crtc->config.dpll.p2 = clock.p2;
6936         }
6937
6938         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6939         if (intel_crtc->config.has_pch_encoder) {
6940                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6941                 if (has_reduced_clock)
6942                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6943
6944                 dpll = ironlake_compute_dpll(intel_crtc,
6945                                              &fp, &reduced_clock,
6946                                              has_reduced_clock ? &fp2 : NULL);
6947
6948                 intel_crtc->config.dpll_hw_state.dpll = dpll;
6949                 intel_crtc->config.dpll_hw_state.fp0 = fp;
6950                 if (has_reduced_clock)
6951                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
6952                 else
6953                         intel_crtc->config.dpll_hw_state.fp1 = fp;
6954
6955                 pll = intel_get_shared_dpll(intel_crtc);
6956                 if (pll == NULL) {
6957                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6958                                          pipe_name(intel_crtc->pipe));
6959                         return -EINVAL;
6960                 }
6961         } else
6962                 intel_put_shared_dpll(intel_crtc);
6963
6964         if (is_lvds && has_reduced_clock && i915.powersave)
6965                 intel_crtc->lowfreq_avail = true;
6966         else
6967                 intel_crtc->lowfreq_avail = false;
6968
6969         return 0;
6970 }
6971
6972 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6973                                          struct intel_link_m_n *m_n)
6974 {
6975         struct drm_device *dev = crtc->base.dev;
6976         struct drm_i915_private *dev_priv = dev->dev_private;
6977         enum pipe pipe = crtc->pipe;
6978
6979         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6980         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6981         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6982                 & ~TU_SIZE_MASK;
6983         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6984         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6985                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6986 }
6987
6988 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6989                                          enum transcoder transcoder,
6990                                          struct intel_link_m_n *m_n)
6991 {
6992         struct drm_device *dev = crtc->base.dev;
6993         struct drm_i915_private *dev_priv = dev->dev_private;
6994         enum pipe pipe = crtc->pipe;
6995
6996         if (INTEL_INFO(dev)->gen >= 5) {
6997                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6998                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6999                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7000                         & ~TU_SIZE_MASK;
7001                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7002                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7003                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7004         } else {
7005                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7006                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7007                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7008                         & ~TU_SIZE_MASK;
7009                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7010                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7011                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7012         }
7013 }
7014
7015 void intel_dp_get_m_n(struct intel_crtc *crtc,
7016                       struct intel_crtc_config *pipe_config)
7017 {
7018         if (crtc->config.has_pch_encoder)
7019                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7020         else
7021                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7022                                              &pipe_config->dp_m_n);
7023 }
7024
7025 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7026                                         struct intel_crtc_config *pipe_config)
7027 {
7028         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7029                                      &pipe_config->fdi_m_n);
7030 }
7031
7032 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7033                                      struct intel_crtc_config *pipe_config)
7034 {
7035         struct drm_device *dev = crtc->base.dev;
7036         struct drm_i915_private *dev_priv = dev->dev_private;
7037         uint32_t tmp;
7038
7039         tmp = I915_READ(PF_CTL(crtc->pipe));
7040
7041         if (tmp & PF_ENABLE) {
7042                 pipe_config->pch_pfit.enabled = true;
7043                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7044                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7045
7046                 /* We currently do not free assignements of panel fitters on
7047                  * ivb/hsw (since we don't use the higher upscaling modes which
7048                  * differentiates them) so just WARN about this case for now. */
7049                 if (IS_GEN7(dev)) {
7050                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7051                                 PF_PIPE_SEL_IVB(crtc->pipe));
7052                 }
7053         }
7054 }
7055
7056 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7057                                       struct intel_plane_config *plane_config)
7058 {
7059         struct drm_device *dev = crtc->base.dev;
7060         struct drm_i915_private *dev_priv = dev->dev_private;
7061         u32 val, base, offset;
7062         int pipe = crtc->pipe, plane = crtc->plane;
7063         int fourcc, pixel_format;
7064         int aligned_height;
7065
7066         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7067         if (!crtc->base.primary->fb) {
7068                 DRM_DEBUG_KMS("failed to alloc fb\n");
7069                 return;
7070         }
7071
7072         val = I915_READ(DSPCNTR(plane));
7073
7074         if (INTEL_INFO(dev)->gen >= 4)
7075                 if (val & DISPPLANE_TILED)
7076                         plane_config->tiled = true;
7077
7078         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7079         fourcc = intel_format_to_fourcc(pixel_format);
7080         crtc->base.primary->fb->pixel_format = fourcc;
7081         crtc->base.primary->fb->bits_per_pixel =
7082                 drm_format_plane_cpp(fourcc, 0) * 8;
7083
7084         base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7085         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7086                 offset = I915_READ(DSPOFFSET(plane));
7087         } else {
7088                 if (plane_config->tiled)
7089                         offset = I915_READ(DSPTILEOFF(plane));
7090                 else
7091                         offset = I915_READ(DSPLINOFF(plane));
7092         }
7093         plane_config->base = base;
7094
7095         val = I915_READ(PIPESRC(pipe));
7096         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7097         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7098
7099         val = I915_READ(DSPSTRIDE(pipe));
7100         crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
7101
7102         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7103                                             plane_config->tiled);
7104
7105         plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
7106                                    aligned_height, PAGE_SIZE);
7107
7108         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7109                       pipe, plane, crtc->base.primary->fb->width,
7110                       crtc->base.primary->fb->height,
7111                       crtc->base.primary->fb->bits_per_pixel, base,
7112                       crtc->base.primary->fb->pitches[0],
7113                       plane_config->size);
7114 }
7115
7116 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7117                                      struct intel_crtc_config *pipe_config)
7118 {
7119         struct drm_device *dev = crtc->base.dev;
7120         struct drm_i915_private *dev_priv = dev->dev_private;
7121         uint32_t tmp;
7122
7123         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7124         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7125
7126         tmp = I915_READ(PIPECONF(crtc->pipe));
7127         if (!(tmp & PIPECONF_ENABLE))
7128                 return false;
7129
7130         switch (tmp & PIPECONF_BPC_MASK) {
7131         case PIPECONF_6BPC:
7132                 pipe_config->pipe_bpp = 18;
7133                 break;
7134         case PIPECONF_8BPC:
7135                 pipe_config->pipe_bpp = 24;
7136                 break;
7137         case PIPECONF_10BPC:
7138                 pipe_config->pipe_bpp = 30;
7139                 break;
7140         case PIPECONF_12BPC:
7141                 pipe_config->pipe_bpp = 36;
7142                 break;
7143         default:
7144                 break;
7145         }
7146
7147         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7148                 pipe_config->limited_color_range = true;
7149
7150         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7151                 struct intel_shared_dpll *pll;
7152
7153                 pipe_config->has_pch_encoder = true;
7154
7155                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7156                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7157                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7158
7159                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7160
7161                 if (HAS_PCH_IBX(dev_priv->dev)) {
7162                         pipe_config->shared_dpll =
7163                                 (enum intel_dpll_id) crtc->pipe;
7164                 } else {
7165                         tmp = I915_READ(PCH_DPLL_SEL);
7166                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7167                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7168                         else
7169                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7170                 }
7171
7172                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7173
7174                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7175                                            &pipe_config->dpll_hw_state));
7176
7177                 tmp = pipe_config->dpll_hw_state.dpll;
7178                 pipe_config->pixel_multiplier =
7179                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7180                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7181
7182                 ironlake_pch_clock_get(crtc, pipe_config);
7183         } else {
7184                 pipe_config->pixel_multiplier = 1;
7185         }
7186
7187         intel_get_pipe_timings(crtc, pipe_config);
7188
7189         ironlake_get_pfit_config(crtc, pipe_config);
7190
7191         return true;
7192 }
7193
7194 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7195 {
7196         struct drm_device *dev = dev_priv->dev;
7197         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
7198         struct intel_crtc *crtc;
7199
7200         for_each_intel_crtc(dev, crtc)
7201                 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7202                      pipe_name(crtc->pipe));
7203
7204         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7205         WARN(plls->spll_refcount, "SPLL enabled\n");
7206         WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
7207         WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
7208         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7209         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7210              "CPU PWM1 enabled\n");
7211         WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7212              "CPU PWM2 enabled\n");
7213         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7214              "PCH PWM1 enabled\n");
7215         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7216              "Utility pin enabled\n");
7217         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7218
7219         /*
7220          * In theory we can still leave IRQs enabled, as long as only the HPD
7221          * interrupts remain enabled. We used to check for that, but since it's
7222          * gen-specific and since we only disable LCPLL after we fully disable
7223          * the interrupts, the check below should be enough.
7224          */
7225         WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n");
7226 }
7227
7228 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7229 {
7230         struct drm_device *dev = dev_priv->dev;
7231
7232         if (IS_HASWELL(dev)) {
7233                 mutex_lock(&dev_priv->rps.hw_lock);
7234                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7235                                             val))
7236                         DRM_ERROR("Failed to disable D_COMP\n");
7237                 mutex_unlock(&dev_priv->rps.hw_lock);
7238         } else {
7239                 I915_WRITE(D_COMP, val);
7240         }
7241         POSTING_READ(D_COMP);
7242 }
7243
7244 /*
7245  * This function implements pieces of two sequences from BSpec:
7246  * - Sequence for display software to disable LCPLL
7247  * - Sequence for display software to allow package C8+
7248  * The steps implemented here are just the steps that actually touch the LCPLL
7249  * register. Callers should take care of disabling all the display engine
7250  * functions, doing the mode unset, fixing interrupts, etc.
7251  */
7252 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7253                               bool switch_to_fclk, bool allow_power_down)
7254 {
7255         uint32_t val;
7256
7257         assert_can_disable_lcpll(dev_priv);
7258
7259         val = I915_READ(LCPLL_CTL);
7260
7261         if (switch_to_fclk) {
7262                 val |= LCPLL_CD_SOURCE_FCLK;
7263                 I915_WRITE(LCPLL_CTL, val);
7264
7265                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7266                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
7267                         DRM_ERROR("Switching to FCLK failed\n");
7268
7269                 val = I915_READ(LCPLL_CTL);
7270         }
7271
7272         val |= LCPLL_PLL_DISABLE;
7273         I915_WRITE(LCPLL_CTL, val);
7274         POSTING_READ(LCPLL_CTL);
7275
7276         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7277                 DRM_ERROR("LCPLL still locked\n");
7278
7279         val = I915_READ(D_COMP);
7280         val |= D_COMP_COMP_DISABLE;
7281         hsw_write_dcomp(dev_priv, val);
7282         ndelay(100);
7283
7284         if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
7285                 DRM_ERROR("D_COMP RCOMP still in progress\n");
7286
7287         if (allow_power_down) {
7288                 val = I915_READ(LCPLL_CTL);
7289                 val |= LCPLL_POWER_DOWN_ALLOW;
7290                 I915_WRITE(LCPLL_CTL, val);
7291                 POSTING_READ(LCPLL_CTL);
7292         }
7293 }
7294
7295 /*
7296  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7297  * source.
7298  */
7299 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7300 {
7301         uint32_t val;
7302         unsigned long irqflags;
7303
7304         val = I915_READ(LCPLL_CTL);
7305
7306         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7307                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7308                 return;
7309
7310         /*
7311          * Make sure we're not on PC8 state before disabling PC8, otherwise
7312          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7313          *
7314          * The other problem is that hsw_restore_lcpll() is called as part of
7315          * the runtime PM resume sequence, so we can't just call
7316          * gen6_gt_force_wake_get() because that function calls
7317          * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7318          * while we are on the resume sequence. So to solve this problem we have
7319          * to call special forcewake code that doesn't touch runtime PM and
7320          * doesn't enable the forcewake delayed work.
7321          */
7322         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7323         if (dev_priv->uncore.forcewake_count++ == 0)
7324                 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7325         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7326
7327         if (val & LCPLL_POWER_DOWN_ALLOW) {
7328                 val &= ~LCPLL_POWER_DOWN_ALLOW;
7329                 I915_WRITE(LCPLL_CTL, val);
7330                 POSTING_READ(LCPLL_CTL);
7331         }
7332
7333         val = I915_READ(D_COMP);
7334         val |= D_COMP_COMP_FORCE;
7335         val &= ~D_COMP_COMP_DISABLE;
7336         hsw_write_dcomp(dev_priv, val);
7337
7338         val = I915_READ(LCPLL_CTL);
7339         val &= ~LCPLL_PLL_DISABLE;
7340         I915_WRITE(LCPLL_CTL, val);
7341
7342         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7343                 DRM_ERROR("LCPLL not locked yet\n");
7344
7345         if (val & LCPLL_CD_SOURCE_FCLK) {
7346                 val = I915_READ(LCPLL_CTL);
7347                 val &= ~LCPLL_CD_SOURCE_FCLK;
7348                 I915_WRITE(LCPLL_CTL, val);
7349
7350                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7351                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7352                         DRM_ERROR("Switching back to LCPLL failed\n");
7353         }
7354
7355         /* See the big comment above. */
7356         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7357         if (--dev_priv->uncore.forcewake_count == 0)
7358                 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7359         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7360 }
7361
7362 /*
7363  * Package states C8 and deeper are really deep PC states that can only be
7364  * reached when all the devices on the system allow it, so even if the graphics
7365  * device allows PC8+, it doesn't mean the system will actually get to these
7366  * states. Our driver only allows PC8+ when going into runtime PM.
7367  *
7368  * The requirements for PC8+ are that all the outputs are disabled, the power
7369  * well is disabled and most interrupts are disabled, and these are also
7370  * requirements for runtime PM. When these conditions are met, we manually do
7371  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7372  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7373  * hang the machine.
7374  *
7375  * When we really reach PC8 or deeper states (not just when we allow it) we lose
7376  * the state of some registers, so when we come back from PC8+ we need to
7377  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7378  * need to take care of the registers kept by RC6. Notice that this happens even
7379  * if we don't put the device in PCI D3 state (which is what currently happens
7380  * because of the runtime PM support).
7381  *
7382  * For more, read "Display Sequences for Package C8" on the hardware
7383  * documentation.
7384  */
7385 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7386 {
7387         struct drm_device *dev = dev_priv->dev;
7388         uint32_t val;
7389
7390         DRM_DEBUG_KMS("Enabling package C8+\n");
7391
7392         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7393                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7394                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7395                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7396         }
7397
7398         lpt_disable_clkout_dp(dev);
7399         hsw_disable_lcpll(dev_priv, true, true);
7400 }
7401
7402 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7403 {
7404         struct drm_device *dev = dev_priv->dev;
7405         uint32_t val;
7406
7407         DRM_DEBUG_KMS("Disabling package C8+\n");
7408
7409         hsw_restore_lcpll(dev_priv);
7410         lpt_init_pch_refclk(dev);
7411
7412         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7413                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7414                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7415                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7416         }
7417
7418         intel_prepare_ddi(dev);
7419 }
7420
7421 static void snb_modeset_global_resources(struct drm_device *dev)
7422 {
7423         modeset_update_crtc_power_domains(dev);
7424 }
7425
7426 static void haswell_modeset_global_resources(struct drm_device *dev)
7427 {
7428         modeset_update_crtc_power_domains(dev);
7429 }
7430
7431 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7432                                  int x, int y,
7433                                  struct drm_framebuffer *fb)
7434 {
7435         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7436
7437         if (!intel_ddi_pll_select(intel_crtc))
7438                 return -EINVAL;
7439         intel_ddi_pll_enable(intel_crtc);
7440
7441         intel_crtc->lowfreq_avail = false;
7442
7443         return 0;
7444 }
7445
7446 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7447                                     struct intel_crtc_config *pipe_config)
7448 {
7449         struct drm_device *dev = crtc->base.dev;
7450         struct drm_i915_private *dev_priv = dev->dev_private;
7451         enum intel_display_power_domain pfit_domain;
7452         uint32_t tmp;
7453
7454         if (!intel_display_power_enabled(dev_priv,
7455                                          POWER_DOMAIN_PIPE(crtc->pipe)))
7456                 return false;
7457
7458         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7459         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7460
7461         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7462         if (tmp & TRANS_DDI_FUNC_ENABLE) {
7463                 enum pipe trans_edp_pipe;
7464                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7465                 default:
7466                         WARN(1, "unknown pipe linked to edp transcoder\n");
7467                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7468                 case TRANS_DDI_EDP_INPUT_A_ON:
7469                         trans_edp_pipe = PIPE_A;
7470                         break;
7471                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7472                         trans_edp_pipe = PIPE_B;
7473                         break;
7474                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7475                         trans_edp_pipe = PIPE_C;
7476                         break;
7477                 }
7478
7479                 if (trans_edp_pipe == crtc->pipe)
7480                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
7481         }
7482
7483         if (!intel_display_power_enabled(dev_priv,
7484                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7485                 return false;
7486
7487         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7488         if (!(tmp & PIPECONF_ENABLE))
7489                 return false;
7490
7491         /*
7492          * Haswell has only FDI/PCH transcoder A. It is which is connected to
7493          * DDI E. So just check whether this pipe is wired to DDI E and whether
7494          * the PCH transcoder is on.
7495          */
7496         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7497         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
7498             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7499                 pipe_config->has_pch_encoder = true;
7500
7501                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7502                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7503                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7504
7505                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7506         }
7507
7508         intel_get_pipe_timings(crtc, pipe_config);
7509
7510         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7511         if (intel_display_power_enabled(dev_priv, pfit_domain))
7512                 ironlake_get_pfit_config(crtc, pipe_config);
7513
7514         if (IS_HASWELL(dev))
7515                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7516                         (I915_READ(IPS_CTL) & IPS_ENABLE);
7517
7518         pipe_config->pixel_multiplier = 1;
7519
7520         return true;
7521 }
7522
7523 static struct {
7524         int clock;
7525         u32 config;
7526 } hdmi_audio_clock[] = {
7527         { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7528         { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7529         { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7530         { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7531         { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7532         { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7533         { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7534         { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7535         { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7536         { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7537 };
7538
7539 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7540 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7541 {
7542         int i;
7543
7544         for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7545                 if (mode->clock == hdmi_audio_clock[i].clock)
7546                         break;
7547         }
7548
7549         if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7550                 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7551                 i = 1;
7552         }
7553
7554         DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7555                       hdmi_audio_clock[i].clock,
7556                       hdmi_audio_clock[i].config);
7557
7558         return hdmi_audio_clock[i].config;
7559 }
7560
7561 static bool intel_eld_uptodate(struct drm_connector *connector,
7562                                int reg_eldv, uint32_t bits_eldv,
7563                                int reg_elda, uint32_t bits_elda,
7564                                int reg_edid)
7565 {
7566         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7567         uint8_t *eld = connector->eld;
7568         uint32_t i;
7569
7570         i = I915_READ(reg_eldv);
7571         i &= bits_eldv;
7572
7573         if (!eld[0])
7574                 return !i;
7575
7576         if (!i)
7577                 return false;
7578
7579         i = I915_READ(reg_elda);
7580         i &= ~bits_elda;
7581         I915_WRITE(reg_elda, i);
7582
7583         for (i = 0; i < eld[2]; i++)
7584                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7585                         return false;
7586
7587         return true;
7588 }
7589
7590 static void g4x_write_eld(struct drm_connector *connector,
7591                           struct drm_crtc *crtc,
7592                           struct drm_display_mode *mode)
7593 {
7594         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7595         uint8_t *eld = connector->eld;
7596         uint32_t eldv;
7597         uint32_t len;
7598         uint32_t i;
7599
7600         i = I915_READ(G4X_AUD_VID_DID);
7601
7602         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7603                 eldv = G4X_ELDV_DEVCL_DEVBLC;
7604         else
7605                 eldv = G4X_ELDV_DEVCTG;
7606
7607         if (intel_eld_uptodate(connector,
7608                                G4X_AUD_CNTL_ST, eldv,
7609                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7610                                G4X_HDMIW_HDMIEDID))
7611                 return;
7612
7613         i = I915_READ(G4X_AUD_CNTL_ST);
7614         i &= ~(eldv | G4X_ELD_ADDR);
7615         len = (i >> 9) & 0x1f;          /* ELD buffer size */
7616         I915_WRITE(G4X_AUD_CNTL_ST, i);
7617
7618         if (!eld[0])
7619                 return;
7620
7621         len = min_t(uint8_t, eld[2], len);
7622         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7623         for (i = 0; i < len; i++)
7624                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7625
7626         i = I915_READ(G4X_AUD_CNTL_ST);
7627         i |= eldv;
7628         I915_WRITE(G4X_AUD_CNTL_ST, i);
7629 }
7630
7631 static void haswell_write_eld(struct drm_connector *connector,
7632                               struct drm_crtc *crtc,
7633                               struct drm_display_mode *mode)
7634 {
7635         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7636         uint8_t *eld = connector->eld;
7637         uint32_t eldv;
7638         uint32_t i;
7639         int len;
7640         int pipe = to_intel_crtc(crtc)->pipe;
7641         int tmp;
7642
7643         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7644         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7645         int aud_config = HSW_AUD_CFG(pipe);
7646         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7647
7648         /* Audio output enable */
7649         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7650         tmp = I915_READ(aud_cntrl_st2);
7651         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7652         I915_WRITE(aud_cntrl_st2, tmp);
7653         POSTING_READ(aud_cntrl_st2);
7654
7655         assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
7656
7657         /* Set ELD valid state */
7658         tmp = I915_READ(aud_cntrl_st2);
7659         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7660         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7661         I915_WRITE(aud_cntrl_st2, tmp);
7662         tmp = I915_READ(aud_cntrl_st2);
7663         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7664
7665         /* Enable HDMI mode */
7666         tmp = I915_READ(aud_config);
7667         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7668         /* clear N_programing_enable and N_value_index */
7669         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7670         I915_WRITE(aud_config, tmp);
7671
7672         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7673
7674         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7675
7676         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7677                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7678                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7679                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7680         } else {
7681                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7682         }
7683
7684         if (intel_eld_uptodate(connector,
7685                                aud_cntrl_st2, eldv,
7686                                aud_cntl_st, IBX_ELD_ADDRESS,
7687                                hdmiw_hdmiedid))
7688                 return;
7689
7690         i = I915_READ(aud_cntrl_st2);
7691         i &= ~eldv;
7692         I915_WRITE(aud_cntrl_st2, i);
7693
7694         if (!eld[0])
7695                 return;
7696
7697         i = I915_READ(aud_cntl_st);
7698         i &= ~IBX_ELD_ADDRESS;
7699         I915_WRITE(aud_cntl_st, i);
7700         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
7701         DRM_DEBUG_DRIVER("port num:%d\n", i);
7702
7703         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7704         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7705         for (i = 0; i < len; i++)
7706                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7707
7708         i = I915_READ(aud_cntrl_st2);
7709         i |= eldv;
7710         I915_WRITE(aud_cntrl_st2, i);
7711
7712 }
7713
7714 static void ironlake_write_eld(struct drm_connector *connector,
7715                                struct drm_crtc *crtc,
7716                                struct drm_display_mode *mode)
7717 {
7718         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7719         uint8_t *eld = connector->eld;
7720         uint32_t eldv;
7721         uint32_t i;
7722         int len;
7723         int hdmiw_hdmiedid;
7724         int aud_config;
7725         int aud_cntl_st;
7726         int aud_cntrl_st2;
7727         int pipe = to_intel_crtc(crtc)->pipe;
7728
7729         if (HAS_PCH_IBX(connector->dev)) {
7730                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7731                 aud_config = IBX_AUD_CFG(pipe);
7732                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7733                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7734         } else if (IS_VALLEYVIEW(connector->dev)) {
7735                 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7736                 aud_config = VLV_AUD_CFG(pipe);
7737                 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7738                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7739         } else {
7740                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7741                 aud_config = CPT_AUD_CFG(pipe);
7742                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7743                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7744         }
7745
7746         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7747
7748         if (IS_VALLEYVIEW(connector->dev))  {
7749                 struct intel_encoder *intel_encoder;
7750                 struct intel_digital_port *intel_dig_port;
7751
7752                 intel_encoder = intel_attached_encoder(connector);
7753                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7754                 i = intel_dig_port->port;
7755         } else {
7756                 i = I915_READ(aud_cntl_st);
7757                 i = (i >> 29) & DIP_PORT_SEL_MASK;
7758                 /* DIP_Port_Select, 0x1 = PortB */
7759         }
7760
7761         if (!i) {
7762                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7763                 /* operate blindly on all ports */
7764                 eldv = IBX_ELD_VALIDB;
7765                 eldv |= IBX_ELD_VALIDB << 4;
7766                 eldv |= IBX_ELD_VALIDB << 8;
7767         } else {
7768                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7769                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7770         }
7771
7772         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7773                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7774                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7775                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7776         } else {
7777                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7778         }
7779
7780         if (intel_eld_uptodate(connector,
7781                                aud_cntrl_st2, eldv,
7782                                aud_cntl_st, IBX_ELD_ADDRESS,
7783                                hdmiw_hdmiedid))
7784                 return;
7785
7786         i = I915_READ(aud_cntrl_st2);
7787         i &= ~eldv;
7788         I915_WRITE(aud_cntrl_st2, i);
7789
7790         if (!eld[0])
7791                 return;
7792
7793         i = I915_READ(aud_cntl_st);
7794         i &= ~IBX_ELD_ADDRESS;
7795         I915_WRITE(aud_cntl_st, i);
7796
7797         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7798         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7799         for (i = 0; i < len; i++)
7800                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7801
7802         i = I915_READ(aud_cntrl_st2);
7803         i |= eldv;
7804         I915_WRITE(aud_cntrl_st2, i);
7805 }
7806
7807 void intel_write_eld(struct drm_encoder *encoder,
7808                      struct drm_display_mode *mode)
7809 {
7810         struct drm_crtc *crtc = encoder->crtc;
7811         struct drm_connector *connector;
7812         struct drm_device *dev = encoder->dev;
7813         struct drm_i915_private *dev_priv = dev->dev_private;
7814
7815         connector = drm_select_eld(encoder, mode);
7816         if (!connector)
7817                 return;
7818
7819         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7820                          connector->base.id,
7821                          drm_get_connector_name(connector),
7822                          connector->encoder->base.id,
7823                          drm_get_encoder_name(connector->encoder));
7824
7825         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7826
7827         if (dev_priv->display.write_eld)
7828                 dev_priv->display.write_eld(connector, crtc, mode);
7829 }
7830
7831 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7832 {
7833         struct drm_device *dev = crtc->dev;
7834         struct drm_i915_private *dev_priv = dev->dev_private;
7835         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7836         bool visible = base != 0;
7837         u32 cntl;
7838
7839         if (intel_crtc->cursor_visible == visible)
7840                 return;
7841
7842         cntl = I915_READ(_CURACNTR);
7843         if (visible) {
7844                 /* On these chipsets we can only modify the base whilst
7845                  * the cursor is disabled.
7846                  */
7847                 I915_WRITE(_CURABASE, base);
7848
7849                 cntl &= ~(CURSOR_FORMAT_MASK);
7850                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7851                 cntl |= CURSOR_ENABLE |
7852                         CURSOR_GAMMA_ENABLE |
7853                         CURSOR_FORMAT_ARGB;
7854         } else
7855                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
7856         I915_WRITE(_CURACNTR, cntl);
7857
7858         intel_crtc->cursor_visible = visible;
7859 }
7860
7861 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7862 {
7863         struct drm_device *dev = crtc->dev;
7864         struct drm_i915_private *dev_priv = dev->dev_private;
7865         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7866         int pipe = intel_crtc->pipe;
7867         bool visible = base != 0;
7868
7869         if (intel_crtc->cursor_visible != visible) {
7870                 int16_t width = intel_crtc->cursor_width;
7871                 uint32_t cntl = I915_READ(CURCNTR(pipe));
7872                 if (base) {
7873                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7874                         cntl |= MCURSOR_GAMMA_ENABLE;
7875
7876                         switch (width) {
7877                         case 64:
7878                                 cntl |= CURSOR_MODE_64_ARGB_AX;
7879                                 break;
7880                         case 128:
7881                                 cntl |= CURSOR_MODE_128_ARGB_AX;
7882                                 break;
7883                         case 256:
7884                                 cntl |= CURSOR_MODE_256_ARGB_AX;
7885                                 break;
7886                         default:
7887                                 WARN_ON(1);
7888                                 return;
7889                         }
7890                         cntl |= pipe << 28; /* Connect to correct pipe */
7891                 } else {
7892                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7893                         cntl |= CURSOR_MODE_DISABLE;
7894                 }
7895                 I915_WRITE(CURCNTR(pipe), cntl);
7896
7897                 intel_crtc->cursor_visible = visible;
7898         }
7899         /* and commit changes on next vblank */
7900         POSTING_READ(CURCNTR(pipe));
7901         I915_WRITE(CURBASE(pipe), base);
7902         POSTING_READ(CURBASE(pipe));
7903 }
7904
7905 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7906 {
7907         struct drm_device *dev = crtc->dev;
7908         struct drm_i915_private *dev_priv = dev->dev_private;
7909         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7910         int pipe = intel_crtc->pipe;
7911         bool visible = base != 0;
7912
7913         if (intel_crtc->cursor_visible != visible) {
7914                 int16_t width = intel_crtc->cursor_width;
7915                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7916                 if (base) {
7917                         cntl &= ~CURSOR_MODE;
7918                         cntl |= MCURSOR_GAMMA_ENABLE;
7919                         switch (width) {
7920                         case 64:
7921                                 cntl |= CURSOR_MODE_64_ARGB_AX;
7922                                 break;
7923                         case 128:
7924                                 cntl |= CURSOR_MODE_128_ARGB_AX;
7925                                 break;
7926                         case 256:
7927                                 cntl |= CURSOR_MODE_256_ARGB_AX;
7928                                 break;
7929                         default:
7930                                 WARN_ON(1);
7931                                 return;
7932                         }
7933                 } else {
7934                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7935                         cntl |= CURSOR_MODE_DISABLE;
7936                 }
7937                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7938                         cntl |= CURSOR_PIPE_CSC_ENABLE;
7939                         cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7940                 }
7941                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7942
7943                 intel_crtc->cursor_visible = visible;
7944         }
7945         /* and commit changes on next vblank */
7946         POSTING_READ(CURCNTR_IVB(pipe));
7947         I915_WRITE(CURBASE_IVB(pipe), base);
7948         POSTING_READ(CURBASE_IVB(pipe));
7949 }
7950
7951 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7952 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7953                                      bool on)
7954 {
7955         struct drm_device *dev = crtc->dev;
7956         struct drm_i915_private *dev_priv = dev->dev_private;
7957         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7958         int pipe = intel_crtc->pipe;
7959         int x = intel_crtc->cursor_x;
7960         int y = intel_crtc->cursor_y;
7961         u32 base = 0, pos = 0;
7962         bool visible;
7963
7964         if (on)
7965                 base = intel_crtc->cursor_addr;
7966
7967         if (x >= intel_crtc->config.pipe_src_w)
7968                 base = 0;
7969
7970         if (y >= intel_crtc->config.pipe_src_h)
7971                 base = 0;
7972
7973         if (x < 0) {
7974                 if (x + intel_crtc->cursor_width <= 0)
7975                         base = 0;
7976
7977                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7978                 x = -x;
7979         }
7980         pos |= x << CURSOR_X_SHIFT;
7981
7982         if (y < 0) {
7983                 if (y + intel_crtc->cursor_height <= 0)
7984                         base = 0;
7985
7986                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7987                 y = -y;
7988         }
7989         pos |= y << CURSOR_Y_SHIFT;
7990
7991         visible = base != 0;
7992         if (!visible && !intel_crtc->cursor_visible)
7993                 return;
7994
7995         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7996                 I915_WRITE(CURPOS_IVB(pipe), pos);
7997                 ivb_update_cursor(crtc, base);
7998         } else {
7999                 I915_WRITE(CURPOS(pipe), pos);
8000                 if (IS_845G(dev) || IS_I865G(dev))
8001                         i845_update_cursor(crtc, base);
8002                 else
8003                         i9xx_update_cursor(crtc, base);
8004         }
8005 }
8006
8007 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
8008                                  struct drm_file *file,
8009                                  uint32_t handle,
8010                                  uint32_t width, uint32_t height)
8011 {
8012         struct drm_device *dev = crtc->dev;
8013         struct drm_i915_private *dev_priv = dev->dev_private;
8014         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8015         struct drm_i915_gem_object *obj;
8016         unsigned old_width;
8017         uint32_t addr;
8018         int ret;
8019
8020         /* if we want to turn off the cursor ignore width and height */
8021         if (!handle) {
8022                 DRM_DEBUG_KMS("cursor off\n");
8023                 addr = 0;
8024                 obj = NULL;
8025                 mutex_lock(&dev->struct_mutex);
8026                 goto finish;
8027         }
8028
8029         /* Check for which cursor types we support */
8030         if (!((width == 64 && height == 64) ||
8031                         (width == 128 && height == 128 && !IS_GEN2(dev)) ||
8032                         (width == 256 && height == 256 && !IS_GEN2(dev)))) {
8033                 DRM_DEBUG("Cursor dimension not supported\n");
8034                 return -EINVAL;
8035         }
8036
8037         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
8038         if (&obj->base == NULL)
8039                 return -ENOENT;
8040
8041         if (obj->base.size < width * height * 4) {
8042                 DRM_DEBUG_KMS("buffer is to small\n");
8043                 ret = -ENOMEM;
8044                 goto fail;
8045         }
8046
8047         /* we only need to pin inside GTT if cursor is non-phy */
8048         mutex_lock(&dev->struct_mutex);
8049         if (!INTEL_INFO(dev)->cursor_needs_physical) {
8050                 unsigned alignment;
8051
8052                 if (obj->tiling_mode) {
8053                         DRM_DEBUG_KMS("cursor cannot be tiled\n");
8054                         ret = -EINVAL;
8055                         goto fail_locked;
8056                 }
8057
8058                 /* Note that the w/a also requires 2 PTE of padding following
8059                  * the bo. We currently fill all unused PTE with the shadow
8060                  * page and so we should always have valid PTE following the
8061                  * cursor preventing the VT-d warning.
8062                  */
8063                 alignment = 0;
8064                 if (need_vtd_wa(dev))
8065                         alignment = 64*1024;
8066
8067                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8068                 if (ret) {
8069                         DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8070                         goto fail_locked;
8071                 }
8072
8073                 ret = i915_gem_object_put_fence(obj);
8074                 if (ret) {
8075                         DRM_DEBUG_KMS("failed to release fence for cursor");
8076                         goto fail_unpin;
8077                 }
8078
8079                 addr = i915_gem_obj_ggtt_offset(obj);
8080         } else {
8081                 int align = IS_I830(dev) ? 16 * 1024 : 256;
8082                 ret = i915_gem_attach_phys_object(dev, obj,
8083                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
8084                                                   align);
8085                 if (ret) {
8086                         DRM_DEBUG_KMS("failed to attach phys object\n");
8087                         goto fail_locked;
8088                 }
8089                 addr = obj->phys_obj->handle->busaddr;
8090         }
8091
8092         if (IS_GEN2(dev))
8093                 I915_WRITE(CURSIZE, (height << 12) | width);
8094
8095  finish:
8096         if (intel_crtc->cursor_bo) {
8097                 if (INTEL_INFO(dev)->cursor_needs_physical) {
8098                         if (intel_crtc->cursor_bo != obj)
8099                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
8100                 } else
8101                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8102                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
8103         }
8104
8105         mutex_unlock(&dev->struct_mutex);
8106
8107         old_width = intel_crtc->cursor_width;
8108
8109         intel_crtc->cursor_addr = addr;
8110         intel_crtc->cursor_bo = obj;
8111         intel_crtc->cursor_width = width;
8112         intel_crtc->cursor_height = height;
8113
8114         if (intel_crtc->active) {
8115                 if (old_width != width)
8116                         intel_update_watermarks(crtc);
8117                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8118         }
8119
8120         return 0;
8121 fail_unpin:
8122         i915_gem_object_unpin_from_display_plane(obj);
8123 fail_locked:
8124         mutex_unlock(&dev->struct_mutex);
8125 fail:
8126         drm_gem_object_unreference_unlocked(&obj->base);
8127         return ret;
8128 }
8129
8130 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
8131 {
8132         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8133
8134         intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
8135         intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
8136
8137         if (intel_crtc->active)
8138                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8139
8140         return 0;
8141 }
8142
8143 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8144                                  u16 *blue, uint32_t start, uint32_t size)
8145 {
8146         int end = (start + size > 256) ? 256 : start + size, i;
8147         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8148
8149         for (i = start; i < end; i++) {
8150                 intel_crtc->lut_r[i] = red[i] >> 8;
8151                 intel_crtc->lut_g[i] = green[i] >> 8;
8152                 intel_crtc->lut_b[i] = blue[i] >> 8;
8153         }
8154
8155         intel_crtc_load_lut(crtc);
8156 }
8157
8158 /* VESA 640x480x72Hz mode to set on the pipe */
8159 static struct drm_display_mode load_detect_mode = {
8160         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8161                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8162 };
8163
8164 struct drm_framebuffer *
8165 __intel_framebuffer_create(struct drm_device *dev,
8166                            struct drm_mode_fb_cmd2 *mode_cmd,
8167                            struct drm_i915_gem_object *obj)
8168 {
8169         struct intel_framebuffer *intel_fb;
8170         int ret;
8171
8172         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8173         if (!intel_fb) {
8174                 drm_gem_object_unreference_unlocked(&obj->base);
8175                 return ERR_PTR(-ENOMEM);
8176         }
8177
8178         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8179         if (ret)
8180                 goto err;
8181
8182         return &intel_fb->base;
8183 err:
8184         drm_gem_object_unreference_unlocked(&obj->base);
8185         kfree(intel_fb);
8186
8187         return ERR_PTR(ret);
8188 }
8189
8190 static struct drm_framebuffer *
8191 intel_framebuffer_create(struct drm_device *dev,
8192                          struct drm_mode_fb_cmd2 *mode_cmd,
8193                          struct drm_i915_gem_object *obj)
8194 {
8195         struct drm_framebuffer *fb;
8196         int ret;
8197
8198         ret = i915_mutex_lock_interruptible(dev);
8199         if (ret)
8200                 return ERR_PTR(ret);
8201         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8202         mutex_unlock(&dev->struct_mutex);
8203
8204         return fb;
8205 }
8206
8207 static u32
8208 intel_framebuffer_pitch_for_width(int width, int bpp)
8209 {
8210         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8211         return ALIGN(pitch, 64);
8212 }
8213
8214 static u32
8215 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8216 {
8217         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8218         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
8219 }
8220
8221 static struct drm_framebuffer *
8222 intel_framebuffer_create_for_mode(struct drm_device *dev,
8223                                   struct drm_display_mode *mode,
8224                                   int depth, int bpp)
8225 {
8226         struct drm_i915_gem_object *obj;
8227         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8228
8229         obj = i915_gem_alloc_object(dev,
8230                                     intel_framebuffer_size_for_mode(mode, bpp));
8231         if (obj == NULL)
8232                 return ERR_PTR(-ENOMEM);
8233
8234         mode_cmd.width = mode->hdisplay;
8235         mode_cmd.height = mode->vdisplay;
8236         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8237                                                                 bpp);
8238         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8239
8240         return intel_framebuffer_create(dev, &mode_cmd, obj);
8241 }
8242
8243 static struct drm_framebuffer *
8244 mode_fits_in_fbdev(struct drm_device *dev,
8245                    struct drm_display_mode *mode)
8246 {
8247 #ifdef CONFIG_DRM_I915_FBDEV
8248         struct drm_i915_private *dev_priv = dev->dev_private;
8249         struct drm_i915_gem_object *obj;
8250         struct drm_framebuffer *fb;
8251
8252         if (!dev_priv->fbdev)
8253                 return NULL;
8254
8255         if (!dev_priv->fbdev->fb)
8256                 return NULL;
8257
8258         obj = dev_priv->fbdev->fb->obj;
8259         BUG_ON(!obj);
8260
8261         fb = &dev_priv->fbdev->fb->base;
8262         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8263                                                                fb->bits_per_pixel))
8264                 return NULL;
8265
8266         if (obj->base.size < mode->vdisplay * fb->pitches[0])
8267                 return NULL;
8268
8269         return fb;
8270 #else
8271         return NULL;
8272 #endif
8273 }
8274
8275 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8276                                 struct drm_display_mode *mode,
8277                                 struct intel_load_detect_pipe *old)
8278 {
8279         struct intel_crtc *intel_crtc;
8280         struct intel_encoder *intel_encoder =
8281                 intel_attached_encoder(connector);
8282         struct drm_crtc *possible_crtc;
8283         struct drm_encoder *encoder = &intel_encoder->base;
8284         struct drm_crtc *crtc = NULL;
8285         struct drm_device *dev = encoder->dev;
8286         struct drm_framebuffer *fb;
8287         int i = -1;
8288
8289         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8290                       connector->base.id, drm_get_connector_name(connector),
8291                       encoder->base.id, drm_get_encoder_name(encoder));
8292
8293         /*
8294          * Algorithm gets a little messy:
8295          *
8296          *   - if the connector already has an assigned crtc, use it (but make
8297          *     sure it's on first)
8298          *
8299          *   - try to find the first unused crtc that can drive this connector,
8300          *     and use that if we find one
8301          */
8302
8303         /* See if we already have a CRTC for this connector */
8304         if (encoder->crtc) {
8305                 crtc = encoder->crtc;
8306
8307                 mutex_lock(&crtc->mutex);
8308
8309                 old->dpms_mode = connector->dpms;
8310                 old->load_detect_temp = false;
8311
8312                 /* Make sure the crtc and connector are running */
8313                 if (connector->dpms != DRM_MODE_DPMS_ON)
8314                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8315
8316                 return true;
8317         }
8318
8319         /* Find an unused one (if possible) */
8320         for_each_crtc(dev, possible_crtc) {
8321                 i++;
8322                 if (!(encoder->possible_crtcs & (1 << i)))
8323                         continue;
8324                 if (!possible_crtc->enabled) {
8325                         crtc = possible_crtc;
8326                         break;
8327                 }
8328         }
8329
8330         /*
8331          * If we didn't find an unused CRTC, don't use any.
8332          */
8333         if (!crtc) {
8334                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8335                 return false;
8336         }
8337
8338         mutex_lock(&crtc->mutex);
8339         intel_encoder->new_crtc = to_intel_crtc(crtc);
8340         to_intel_connector(connector)->new_encoder = intel_encoder;
8341
8342         intel_crtc = to_intel_crtc(crtc);
8343         intel_crtc->new_enabled = true;
8344         intel_crtc->new_config = &intel_crtc->config;
8345         old->dpms_mode = connector->dpms;
8346         old->load_detect_temp = true;
8347         old->release_fb = NULL;
8348
8349         if (!mode)
8350                 mode = &load_detect_mode;
8351
8352         /* We need a framebuffer large enough to accommodate all accesses
8353          * that the plane may generate whilst we perform load detection.
8354          * We can not rely on the fbcon either being present (we get called
8355          * during its initialisation to detect all boot displays, or it may
8356          * not even exist) or that it is large enough to satisfy the
8357          * requested mode.
8358          */
8359         fb = mode_fits_in_fbdev(dev, mode);
8360         if (fb == NULL) {
8361                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8362                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8363                 old->release_fb = fb;
8364         } else
8365                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8366         if (IS_ERR(fb)) {
8367                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8368                 goto fail;
8369         }
8370
8371         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8372                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8373                 if (old->release_fb)
8374                         old->release_fb->funcs->destroy(old->release_fb);
8375                 goto fail;
8376         }
8377
8378         /* let the connector get through one full cycle before testing */
8379         intel_wait_for_vblank(dev, intel_crtc->pipe);
8380         return true;
8381
8382  fail:
8383         intel_crtc->new_enabled = crtc->enabled;
8384         if (intel_crtc->new_enabled)
8385                 intel_crtc->new_config = &intel_crtc->config;
8386         else
8387                 intel_crtc->new_config = NULL;
8388         mutex_unlock(&crtc->mutex);
8389         return false;
8390 }
8391
8392 void intel_release_load_detect_pipe(struct drm_connector *connector,
8393                                     struct intel_load_detect_pipe *old)
8394 {
8395         struct intel_encoder *intel_encoder =
8396                 intel_attached_encoder(connector);
8397         struct drm_encoder *encoder = &intel_encoder->base;
8398         struct drm_crtc *crtc = encoder->crtc;
8399         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8400
8401         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8402                       connector->base.id, drm_get_connector_name(connector),
8403                       encoder->base.id, drm_get_encoder_name(encoder));
8404
8405         if (old->load_detect_temp) {
8406                 to_intel_connector(connector)->new_encoder = NULL;
8407                 intel_encoder->new_crtc = NULL;
8408                 intel_crtc->new_enabled = false;
8409                 intel_crtc->new_config = NULL;
8410                 intel_set_mode(crtc, NULL, 0, 0, NULL);
8411
8412                 if (old->release_fb) {
8413                         drm_framebuffer_unregister_private(old->release_fb);
8414                         drm_framebuffer_unreference(old->release_fb);
8415                 }
8416
8417                 mutex_unlock(&crtc->mutex);
8418                 return;
8419         }
8420
8421         /* Switch crtc and encoder back off if necessary */
8422         if (old->dpms_mode != DRM_MODE_DPMS_ON)
8423                 connector->funcs->dpms(connector, old->dpms_mode);
8424
8425         mutex_unlock(&crtc->mutex);
8426 }
8427
8428 static int i9xx_pll_refclk(struct drm_device *dev,
8429                            const struct intel_crtc_config *pipe_config)
8430 {
8431         struct drm_i915_private *dev_priv = dev->dev_private;
8432         u32 dpll = pipe_config->dpll_hw_state.dpll;
8433
8434         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8435                 return dev_priv->vbt.lvds_ssc_freq;
8436         else if (HAS_PCH_SPLIT(dev))
8437                 return 120000;
8438         else if (!IS_GEN2(dev))
8439                 return 96000;
8440         else
8441                 return 48000;
8442 }
8443
8444 /* Returns the clock of the currently programmed mode of the given pipe. */
8445 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8446                                 struct intel_crtc_config *pipe_config)
8447 {
8448         struct drm_device *dev = crtc->base.dev;
8449         struct drm_i915_private *dev_priv = dev->dev_private;
8450         int pipe = pipe_config->cpu_transcoder;
8451         u32 dpll = pipe_config->dpll_hw_state.dpll;
8452         u32 fp;
8453         intel_clock_t clock;
8454         int refclk = i9xx_pll_refclk(dev, pipe_config);
8455
8456         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8457                 fp = pipe_config->dpll_hw_state.fp0;
8458         else
8459                 fp = pipe_config->dpll_hw_state.fp1;
8460
8461         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8462         if (IS_PINEVIEW(dev)) {
8463                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8464                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8465         } else {
8466                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8467                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8468         }
8469
8470         if (!IS_GEN2(dev)) {
8471                 if (IS_PINEVIEW(dev))
8472                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8473                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8474                 else
8475                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8476                                DPLL_FPA01_P1_POST_DIV_SHIFT);
8477
8478                 switch (dpll & DPLL_MODE_MASK) {
8479                 case DPLLB_MODE_DAC_SERIAL:
8480                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8481                                 5 : 10;
8482                         break;
8483                 case DPLLB_MODE_LVDS:
8484                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8485                                 7 : 14;
8486                         break;
8487                 default:
8488                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8489                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
8490                         return;
8491                 }
8492
8493                 if (IS_PINEVIEW(dev))
8494                         pineview_clock(refclk, &clock);
8495                 else
8496                         i9xx_clock(refclk, &clock);
8497         } else {
8498                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8499                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8500
8501                 if (is_lvds) {
8502                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8503                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
8504
8505                         if (lvds & LVDS_CLKB_POWER_UP)
8506                                 clock.p2 = 7;
8507                         else
8508                                 clock.p2 = 14;
8509                 } else {
8510                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
8511                                 clock.p1 = 2;
8512                         else {
8513                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8514                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8515                         }
8516                         if (dpll & PLL_P2_DIVIDE_BY_4)
8517                                 clock.p2 = 4;
8518                         else
8519                                 clock.p2 = 2;
8520                 }
8521
8522                 i9xx_clock(refclk, &clock);
8523         }
8524
8525         /*
8526          * This value includes pixel_multiplier. We will use
8527          * port_clock to compute adjusted_mode.crtc_clock in the
8528          * encoder's get_config() function.
8529          */
8530         pipe_config->port_clock = clock.dot;
8531 }
8532
8533 int intel_dotclock_calculate(int link_freq,
8534                              const struct intel_link_m_n *m_n)
8535 {
8536         /*
8537          * The calculation for the data clock is:
8538          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8539          * But we want to avoid losing precison if possible, so:
8540          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8541          *
8542          * and the link clock is simpler:
8543          * link_clock = (m * link_clock) / n
8544          */
8545
8546         if (!m_n->link_n)
8547                 return 0;
8548
8549         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8550 }
8551
8552 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8553                                    struct intel_crtc_config *pipe_config)
8554 {
8555         struct drm_device *dev = crtc->base.dev;
8556
8557         /* read out port_clock from the DPLL */
8558         i9xx_crtc_clock_get(crtc, pipe_config);
8559
8560         /*
8561          * This value does not include pixel_multiplier.
8562          * We will check that port_clock and adjusted_mode.crtc_clock
8563          * agree once we know their relationship in the encoder's
8564          * get_config() function.
8565          */
8566         pipe_config->adjusted_mode.crtc_clock =
8567                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8568                                          &pipe_config->fdi_m_n);
8569 }
8570
8571 /** Returns the currently programmed mode of the given pipe. */
8572 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8573                                              struct drm_crtc *crtc)
8574 {
8575         struct drm_i915_private *dev_priv = dev->dev_private;
8576         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8577         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8578         struct drm_display_mode *mode;
8579         struct intel_crtc_config pipe_config;
8580         int htot = I915_READ(HTOTAL(cpu_transcoder));
8581         int hsync = I915_READ(HSYNC(cpu_transcoder));
8582         int vtot = I915_READ(VTOTAL(cpu_transcoder));
8583         int vsync = I915_READ(VSYNC(cpu_transcoder));
8584         enum pipe pipe = intel_crtc->pipe;
8585
8586         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8587         if (!mode)
8588                 return NULL;
8589
8590         /*
8591          * Construct a pipe_config sufficient for getting the clock info
8592          * back out of crtc_clock_get.
8593          *
8594          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8595          * to use a real value here instead.
8596          */
8597         pipe_config.cpu_transcoder = (enum transcoder) pipe;
8598         pipe_config.pixel_multiplier = 1;
8599         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8600         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8601         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8602         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8603
8604         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8605         mode->hdisplay = (htot & 0xffff) + 1;
8606         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8607         mode->hsync_start = (hsync & 0xffff) + 1;
8608         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8609         mode->vdisplay = (vtot & 0xffff) + 1;
8610         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8611         mode->vsync_start = (vsync & 0xffff) + 1;
8612         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8613
8614         drm_mode_set_name(mode);
8615
8616         return mode;
8617 }
8618
8619 static void intel_increase_pllclock(struct drm_crtc *crtc)
8620 {
8621         struct drm_device *dev = crtc->dev;
8622         struct drm_i915_private *dev_priv = dev->dev_private;
8623         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8624         int pipe = intel_crtc->pipe;
8625         int dpll_reg = DPLL(pipe);
8626         int dpll;
8627
8628         if (HAS_PCH_SPLIT(dev))
8629                 return;
8630
8631         if (!dev_priv->lvds_downclock_avail)
8632                 return;
8633
8634         dpll = I915_READ(dpll_reg);
8635         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8636                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8637
8638                 assert_panel_unlocked(dev_priv, pipe);
8639
8640                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8641                 I915_WRITE(dpll_reg, dpll);
8642                 intel_wait_for_vblank(dev, pipe);
8643
8644                 dpll = I915_READ(dpll_reg);
8645                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8646                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8647         }
8648 }
8649
8650 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8651 {
8652         struct drm_device *dev = crtc->dev;
8653         struct drm_i915_private *dev_priv = dev->dev_private;
8654         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8655
8656         if (HAS_PCH_SPLIT(dev))
8657                 return;
8658
8659         if (!dev_priv->lvds_downclock_avail)
8660                 return;
8661
8662         /*
8663          * Since this is called by a timer, we should never get here in
8664          * the manual case.
8665          */
8666         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8667                 int pipe = intel_crtc->pipe;
8668                 int dpll_reg = DPLL(pipe);
8669                 int dpll;
8670
8671                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8672
8673                 assert_panel_unlocked(dev_priv, pipe);
8674
8675                 dpll = I915_READ(dpll_reg);
8676                 dpll |= DISPLAY_RATE_SELECT_FPA1;
8677                 I915_WRITE(dpll_reg, dpll);
8678                 intel_wait_for_vblank(dev, pipe);
8679                 dpll = I915_READ(dpll_reg);
8680                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8681                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8682         }
8683
8684 }
8685
8686 void intel_mark_busy(struct drm_device *dev)
8687 {
8688         struct drm_i915_private *dev_priv = dev->dev_private;
8689
8690         if (dev_priv->mm.busy)
8691                 return;
8692
8693         intel_runtime_pm_get(dev_priv);
8694         i915_update_gfx_val(dev_priv);
8695         dev_priv->mm.busy = true;
8696 }
8697
8698 void intel_mark_idle(struct drm_device *dev)
8699 {
8700         struct drm_i915_private *dev_priv = dev->dev_private;
8701         struct drm_crtc *crtc;
8702
8703         if (!dev_priv->mm.busy)
8704                 return;
8705
8706         dev_priv->mm.busy = false;
8707
8708         if (!i915.powersave)
8709                 goto out;
8710
8711         for_each_crtc(dev, crtc) {
8712                 if (!crtc->primary->fb)
8713                         continue;
8714
8715                 intel_decrease_pllclock(crtc);
8716         }
8717
8718         if (INTEL_INFO(dev)->gen >= 6)
8719                 gen6_rps_idle(dev->dev_private);
8720
8721 out:
8722         intel_runtime_pm_put(dev_priv);
8723 }
8724
8725 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
8726                         struct intel_ring_buffer *ring)
8727 {
8728         struct drm_device *dev = obj->base.dev;
8729         struct drm_crtc *crtc;
8730
8731         if (!i915.powersave)
8732                 return;
8733
8734         for_each_crtc(dev, crtc) {
8735                 if (!crtc->primary->fb)
8736                         continue;
8737
8738                 if (to_intel_framebuffer(crtc->primary->fb)->obj != obj)
8739                         continue;
8740
8741                 intel_increase_pllclock(crtc);
8742                 if (ring && intel_fbc_enabled(dev))
8743                         ring->fbc_dirty = true;
8744         }
8745 }
8746
8747 static void intel_crtc_destroy(struct drm_crtc *crtc)
8748 {
8749         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8750         struct drm_device *dev = crtc->dev;
8751         struct intel_unpin_work *work;
8752         unsigned long flags;
8753
8754         spin_lock_irqsave(&dev->event_lock, flags);
8755         work = intel_crtc->unpin_work;
8756         intel_crtc->unpin_work = NULL;
8757         spin_unlock_irqrestore(&dev->event_lock, flags);
8758
8759         if (work) {
8760                 cancel_work_sync(&work->work);
8761                 kfree(work);
8762         }
8763
8764         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
8765
8766         drm_crtc_cleanup(crtc);
8767
8768         kfree(intel_crtc);
8769 }
8770
8771 static void intel_unpin_work_fn(struct work_struct *__work)
8772 {
8773         struct intel_unpin_work *work =
8774                 container_of(__work, struct intel_unpin_work, work);
8775         struct drm_device *dev = work->crtc->dev;
8776
8777         mutex_lock(&dev->struct_mutex);
8778         intel_unpin_fb_obj(work->old_fb_obj);
8779         drm_gem_object_unreference(&work->pending_flip_obj->base);
8780         drm_gem_object_unreference(&work->old_fb_obj->base);
8781
8782         intel_update_fbc(dev);
8783         mutex_unlock(&dev->struct_mutex);
8784
8785         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8786         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8787
8788         kfree(work);
8789 }
8790
8791 static void do_intel_finish_page_flip(struct drm_device *dev,
8792                                       struct drm_crtc *crtc)
8793 {
8794         struct drm_i915_private *dev_priv = dev->dev_private;
8795         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8796         struct intel_unpin_work *work;
8797         unsigned long flags;
8798
8799         /* Ignore early vblank irqs */
8800         if (intel_crtc == NULL)
8801                 return;
8802
8803         spin_lock_irqsave(&dev->event_lock, flags);
8804         work = intel_crtc->unpin_work;
8805
8806         /* Ensure we don't miss a work->pending update ... */
8807         smp_rmb();
8808
8809         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8810                 spin_unlock_irqrestore(&dev->event_lock, flags);
8811                 return;
8812         }
8813
8814         /* and that the unpin work is consistent wrt ->pending. */
8815         smp_rmb();
8816
8817         intel_crtc->unpin_work = NULL;
8818
8819         if (work->event)
8820                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
8821
8822         drm_vblank_put(dev, intel_crtc->pipe);
8823
8824         spin_unlock_irqrestore(&dev->event_lock, flags);
8825
8826         wake_up_all(&dev_priv->pending_flip_queue);
8827
8828         queue_work(dev_priv->wq, &work->work);
8829
8830         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
8831 }
8832
8833 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8834 {
8835         struct drm_i915_private *dev_priv = dev->dev_private;
8836         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8837
8838         do_intel_finish_page_flip(dev, crtc);
8839 }
8840
8841 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8842 {
8843         struct drm_i915_private *dev_priv = dev->dev_private;
8844         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8845
8846         do_intel_finish_page_flip(dev, crtc);
8847 }
8848
8849 void intel_prepare_page_flip(struct drm_device *dev, int plane)
8850 {
8851         struct drm_i915_private *dev_priv = dev->dev_private;
8852         struct intel_crtc *intel_crtc =
8853                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8854         unsigned long flags;
8855
8856         /* NB: An MMIO update of the plane base pointer will also
8857          * generate a page-flip completion irq, i.e. every modeset
8858          * is also accompanied by a spurious intel_prepare_page_flip().
8859          */
8860         spin_lock_irqsave(&dev->event_lock, flags);
8861         if (intel_crtc->unpin_work)
8862                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
8863         spin_unlock_irqrestore(&dev->event_lock, flags);
8864 }
8865
8866 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8867 {
8868         /* Ensure that the work item is consistent when activating it ... */
8869         smp_wmb();
8870         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8871         /* and that it is marked active as soon as the irq could fire. */
8872         smp_wmb();
8873 }
8874
8875 static int intel_gen2_queue_flip(struct drm_device *dev,
8876                                  struct drm_crtc *crtc,
8877                                  struct drm_framebuffer *fb,
8878                                  struct drm_i915_gem_object *obj,
8879                                  uint32_t flags)
8880 {
8881         struct drm_i915_private *dev_priv = dev->dev_private;
8882         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8883         u32 flip_mask;
8884         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8885         int ret;
8886
8887         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8888         if (ret)
8889                 goto err;
8890
8891         ret = intel_ring_begin(ring, 6);
8892         if (ret)
8893                 goto err_unpin;
8894
8895         /* Can't queue multiple flips, so wait for the previous
8896          * one to finish before executing the next.
8897          */
8898         if (intel_crtc->plane)
8899                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8900         else
8901                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8902         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8903         intel_ring_emit(ring, MI_NOOP);
8904         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8905                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8906         intel_ring_emit(ring, fb->pitches[0]);
8907         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8908         intel_ring_emit(ring, 0); /* aux display base address, unused */
8909
8910         intel_mark_page_flip_active(intel_crtc);
8911         __intel_ring_advance(ring);
8912         return 0;
8913
8914 err_unpin:
8915         intel_unpin_fb_obj(obj);
8916 err:
8917         return ret;
8918 }
8919
8920 static int intel_gen3_queue_flip(struct drm_device *dev,
8921                                  struct drm_crtc *crtc,
8922                                  struct drm_framebuffer *fb,
8923                                  struct drm_i915_gem_object *obj,
8924                                  uint32_t flags)
8925 {
8926         struct drm_i915_private *dev_priv = dev->dev_private;
8927         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8928         u32 flip_mask;
8929         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8930         int ret;
8931
8932         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8933         if (ret)
8934                 goto err;
8935
8936         ret = intel_ring_begin(ring, 6);
8937         if (ret)
8938                 goto err_unpin;
8939
8940         if (intel_crtc->plane)
8941                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8942         else
8943                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8944         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8945         intel_ring_emit(ring, MI_NOOP);
8946         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8947                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8948         intel_ring_emit(ring, fb->pitches[0]);
8949         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8950         intel_ring_emit(ring, MI_NOOP);
8951
8952         intel_mark_page_flip_active(intel_crtc);
8953         __intel_ring_advance(ring);
8954         return 0;
8955
8956 err_unpin:
8957         intel_unpin_fb_obj(obj);
8958 err:
8959         return ret;
8960 }
8961
8962 static int intel_gen4_queue_flip(struct drm_device *dev,
8963                                  struct drm_crtc *crtc,
8964                                  struct drm_framebuffer *fb,
8965                                  struct drm_i915_gem_object *obj,
8966                                  uint32_t flags)
8967 {
8968         struct drm_i915_private *dev_priv = dev->dev_private;
8969         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8970         uint32_t pf, pipesrc;
8971         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8972         int ret;
8973
8974         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8975         if (ret)
8976                 goto err;
8977
8978         ret = intel_ring_begin(ring, 4);
8979         if (ret)
8980                 goto err_unpin;
8981
8982         /* i965+ uses the linear or tiled offsets from the
8983          * Display Registers (which do not change across a page-flip)
8984          * so we need only reprogram the base address.
8985          */
8986         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8987                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8988         intel_ring_emit(ring, fb->pitches[0]);
8989         intel_ring_emit(ring,
8990                         (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
8991                         obj->tiling_mode);
8992
8993         /* XXX Enabling the panel-fitter across page-flip is so far
8994          * untested on non-native modes, so ignore it for now.
8995          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8996          */
8997         pf = 0;
8998         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8999         intel_ring_emit(ring, pf | pipesrc);
9000
9001         intel_mark_page_flip_active(intel_crtc);
9002         __intel_ring_advance(ring);
9003         return 0;
9004
9005 err_unpin:
9006         intel_unpin_fb_obj(obj);
9007 err:
9008         return ret;
9009 }
9010
9011 static int intel_gen6_queue_flip(struct drm_device *dev,
9012                                  struct drm_crtc *crtc,
9013                                  struct drm_framebuffer *fb,
9014                                  struct drm_i915_gem_object *obj,
9015                                  uint32_t flags)
9016 {
9017         struct drm_i915_private *dev_priv = dev->dev_private;
9018         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9019         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
9020         uint32_t pf, pipesrc;
9021         int ret;
9022
9023         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9024         if (ret)
9025                 goto err;
9026
9027         ret = intel_ring_begin(ring, 4);
9028         if (ret)
9029                 goto err_unpin;
9030
9031         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9032                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9033         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9034         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
9035
9036         /* Contrary to the suggestions in the documentation,
9037          * "Enable Panel Fitter" does not seem to be required when page
9038          * flipping with a non-native mode, and worse causes a normal
9039          * modeset to fail.
9040          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9041          */
9042         pf = 0;
9043         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9044         intel_ring_emit(ring, pf | pipesrc);
9045
9046         intel_mark_page_flip_active(intel_crtc);
9047         __intel_ring_advance(ring);
9048         return 0;
9049
9050 err_unpin:
9051         intel_unpin_fb_obj(obj);
9052 err:
9053         return ret;
9054 }
9055
9056 static int intel_gen7_queue_flip(struct drm_device *dev,
9057                                  struct drm_crtc *crtc,
9058                                  struct drm_framebuffer *fb,
9059                                  struct drm_i915_gem_object *obj,
9060                                  uint32_t flags)
9061 {
9062         struct drm_i915_private *dev_priv = dev->dev_private;
9063         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9064         struct intel_ring_buffer *ring;
9065         uint32_t plane_bit = 0;
9066         int len, ret;
9067
9068         ring = obj->ring;
9069         if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
9070                 ring = &dev_priv->ring[BCS];
9071
9072         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9073         if (ret)
9074                 goto err;
9075
9076         switch (intel_crtc->plane) {
9077         case PLANE_A:
9078                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9079                 break;
9080         case PLANE_B:
9081                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9082                 break;
9083         case PLANE_C:
9084                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9085                 break;
9086         default:
9087                 WARN_ONCE(1, "unknown plane in flip command\n");
9088                 ret = -ENODEV;
9089                 goto err_unpin;
9090         }
9091
9092         len = 4;
9093         if (ring->id == RCS) {
9094                 len += 6;
9095                 /*
9096                  * On Gen 8, SRM is now taking an extra dword to accommodate
9097                  * 48bits addresses, and we need a NOOP for the batch size to
9098                  * stay even.
9099                  */
9100                 if (IS_GEN8(dev))
9101                         len += 2;
9102         }
9103
9104         /*
9105          * BSpec MI_DISPLAY_FLIP for IVB:
9106          * "The full packet must be contained within the same cache line."
9107          *
9108          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9109          * cacheline, if we ever start emitting more commands before
9110          * the MI_DISPLAY_FLIP we may need to first emit everything else,
9111          * then do the cacheline alignment, and finally emit the
9112          * MI_DISPLAY_FLIP.
9113          */
9114         ret = intel_ring_cacheline_align(ring);
9115         if (ret)
9116                 goto err_unpin;
9117
9118         ret = intel_ring_begin(ring, len);
9119         if (ret)
9120                 goto err_unpin;
9121
9122         /* Unmask the flip-done completion message. Note that the bspec says that
9123          * we should do this for both the BCS and RCS, and that we must not unmask
9124          * more than one flip event at any time (or ensure that one flip message
9125          * can be sent by waiting for flip-done prior to queueing new flips).
9126          * Experimentation says that BCS works despite DERRMR masking all
9127          * flip-done completion events and that unmasking all planes at once
9128          * for the RCS also doesn't appear to drop events. Setting the DERRMR
9129          * to zero does lead to lockups within MI_DISPLAY_FLIP.
9130          */
9131         if (ring->id == RCS) {
9132                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9133                 intel_ring_emit(ring, DERRMR);
9134                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9135                                         DERRMR_PIPEB_PRI_FLIP_DONE |
9136                                         DERRMR_PIPEC_PRI_FLIP_DONE));
9137                 if (IS_GEN8(dev))
9138                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9139                                               MI_SRM_LRM_GLOBAL_GTT);
9140                 else
9141                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9142                                               MI_SRM_LRM_GLOBAL_GTT);
9143                 intel_ring_emit(ring, DERRMR);
9144                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9145                 if (IS_GEN8(dev)) {
9146                         intel_ring_emit(ring, 0);
9147                         intel_ring_emit(ring, MI_NOOP);
9148                 }
9149         }
9150
9151         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9152         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9153         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
9154         intel_ring_emit(ring, (MI_NOOP));
9155
9156         intel_mark_page_flip_active(intel_crtc);
9157         __intel_ring_advance(ring);
9158         return 0;
9159
9160 err_unpin:
9161         intel_unpin_fb_obj(obj);
9162 err:
9163         return ret;
9164 }
9165
9166 static int intel_default_queue_flip(struct drm_device *dev,
9167                                     struct drm_crtc *crtc,
9168                                     struct drm_framebuffer *fb,
9169                                     struct drm_i915_gem_object *obj,
9170                                     uint32_t flags)
9171 {
9172         return -ENODEV;
9173 }
9174
9175 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9176                                 struct drm_framebuffer *fb,
9177                                 struct drm_pending_vblank_event *event,
9178                                 uint32_t page_flip_flags)
9179 {
9180         struct drm_device *dev = crtc->dev;
9181         struct drm_i915_private *dev_priv = dev->dev_private;
9182         struct drm_framebuffer *old_fb = crtc->primary->fb;
9183         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
9184         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9185         struct intel_unpin_work *work;
9186         unsigned long flags;
9187         int ret;
9188
9189         /* Can't change pixel format via MI display flips. */
9190         if (fb->pixel_format != crtc->primary->fb->pixel_format)
9191                 return -EINVAL;
9192
9193         /*
9194          * TILEOFF/LINOFF registers can't be changed via MI display flips.
9195          * Note that pitch changes could also affect these register.
9196          */
9197         if (INTEL_INFO(dev)->gen > 3 &&
9198             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9199              fb->pitches[0] != crtc->primary->fb->pitches[0]))
9200                 return -EINVAL;
9201
9202         if (i915_terminally_wedged(&dev_priv->gpu_error))
9203                 goto out_hang;
9204
9205         work = kzalloc(sizeof(*work), GFP_KERNEL);
9206         if (work == NULL)
9207                 return -ENOMEM;
9208
9209         work->event = event;
9210         work->crtc = crtc;
9211         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
9212         INIT_WORK(&work->work, intel_unpin_work_fn);
9213
9214         ret = drm_vblank_get(dev, intel_crtc->pipe);
9215         if (ret)
9216                 goto free_work;
9217
9218         /* We borrow the event spin lock for protecting unpin_work */
9219         spin_lock_irqsave(&dev->event_lock, flags);
9220         if (intel_crtc->unpin_work) {
9221                 spin_unlock_irqrestore(&dev->event_lock, flags);
9222                 kfree(work);
9223                 drm_vblank_put(dev, intel_crtc->pipe);
9224
9225                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9226                 return -EBUSY;
9227         }
9228         intel_crtc->unpin_work = work;
9229         spin_unlock_irqrestore(&dev->event_lock, flags);
9230
9231         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9232                 flush_workqueue(dev_priv->wq);
9233
9234         ret = i915_mutex_lock_interruptible(dev);
9235         if (ret)
9236                 goto cleanup;
9237
9238         /* Reference the objects for the scheduled work. */
9239         drm_gem_object_reference(&work->old_fb_obj->base);
9240         drm_gem_object_reference(&obj->base);
9241
9242         crtc->primary->fb = fb;
9243
9244         work->pending_flip_obj = obj;
9245
9246         work->enable_stall_check = true;
9247
9248         atomic_inc(&intel_crtc->unpin_work_count);
9249         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9250
9251         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
9252         if (ret)
9253                 goto cleanup_pending;
9254
9255         intel_disable_fbc(dev);
9256         intel_mark_fb_busy(obj, NULL);
9257         mutex_unlock(&dev->struct_mutex);
9258
9259         trace_i915_flip_request(intel_crtc->plane, obj);
9260
9261         return 0;
9262
9263 cleanup_pending:
9264         atomic_dec(&intel_crtc->unpin_work_count);
9265         crtc->primary->fb = old_fb;
9266         drm_gem_object_unreference(&work->old_fb_obj->base);
9267         drm_gem_object_unreference(&obj->base);
9268         mutex_unlock(&dev->struct_mutex);
9269
9270 cleanup:
9271         spin_lock_irqsave(&dev->event_lock, flags);
9272         intel_crtc->unpin_work = NULL;
9273         spin_unlock_irqrestore(&dev->event_lock, flags);
9274
9275         drm_vblank_put(dev, intel_crtc->pipe);
9276 free_work:
9277         kfree(work);
9278
9279         if (ret == -EIO) {
9280 out_hang:
9281                 intel_crtc_wait_for_pending_flips(crtc);
9282                 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9283                 if (ret == 0 && event)
9284                         drm_send_vblank_event(dev, intel_crtc->pipe, event);
9285         }
9286         return ret;
9287 }
9288
9289 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9290         .mode_set_base_atomic = intel_pipe_set_base_atomic,
9291         .load_lut = intel_crtc_load_lut,
9292 };
9293
9294 /**
9295  * intel_modeset_update_staged_output_state
9296  *
9297  * Updates the staged output configuration state, e.g. after we've read out the
9298  * current hw state.
9299  */
9300 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9301 {
9302         struct intel_crtc *crtc;
9303         struct intel_encoder *encoder;
9304         struct intel_connector *connector;
9305
9306         list_for_each_entry(connector, &dev->mode_config.connector_list,
9307                             base.head) {
9308                 connector->new_encoder =
9309                         to_intel_encoder(connector->base.encoder);
9310         }
9311
9312         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9313                             base.head) {
9314                 encoder->new_crtc =
9315                         to_intel_crtc(encoder->base.crtc);
9316         }
9317
9318         for_each_intel_crtc(dev, crtc) {
9319                 crtc->new_enabled = crtc->base.enabled;
9320
9321                 if (crtc->new_enabled)
9322                         crtc->new_config = &crtc->config;
9323                 else
9324                         crtc->new_config = NULL;
9325         }
9326 }
9327
9328 /**
9329  * intel_modeset_commit_output_state
9330  *
9331  * This function copies the stage display pipe configuration to the real one.
9332  */
9333 static void intel_modeset_commit_output_state(struct drm_device *dev)
9334 {
9335         struct intel_crtc *crtc;
9336         struct intel_encoder *encoder;
9337         struct intel_connector *connector;
9338
9339         list_for_each_entry(connector, &dev->mode_config.connector_list,
9340                             base.head) {
9341                 connector->base.encoder = &connector->new_encoder->base;
9342         }
9343
9344         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9345                             base.head) {
9346                 encoder->base.crtc = &encoder->new_crtc->base;
9347         }
9348
9349         for_each_intel_crtc(dev, crtc) {
9350                 crtc->base.enabled = crtc->new_enabled;
9351         }
9352 }
9353
9354 static void
9355 connected_sink_compute_bpp(struct intel_connector *connector,
9356                            struct intel_crtc_config *pipe_config)
9357 {
9358         int bpp = pipe_config->pipe_bpp;
9359
9360         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9361                 connector->base.base.id,
9362                 drm_get_connector_name(&connector->base));
9363
9364         /* Don't use an invalid EDID bpc value */
9365         if (connector->base.display_info.bpc &&
9366             connector->base.display_info.bpc * 3 < bpp) {
9367                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9368                               bpp, connector->base.display_info.bpc*3);
9369                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9370         }
9371
9372         /* Clamp bpp to 8 on screens without EDID 1.4 */
9373         if (connector->base.display_info.bpc == 0 && bpp > 24) {
9374                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9375                               bpp);
9376                 pipe_config->pipe_bpp = 24;
9377         }
9378 }
9379
9380 static int
9381 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9382                           struct drm_framebuffer *fb,
9383                           struct intel_crtc_config *pipe_config)
9384 {
9385         struct drm_device *dev = crtc->base.dev;
9386         struct intel_connector *connector;
9387         int bpp;
9388
9389         switch (fb->pixel_format) {
9390         case DRM_FORMAT_C8:
9391                 bpp = 8*3; /* since we go through a colormap */
9392                 break;
9393         case DRM_FORMAT_XRGB1555:
9394         case DRM_FORMAT_ARGB1555:
9395                 /* checked in intel_framebuffer_init already */
9396                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9397                         return -EINVAL;
9398         case DRM_FORMAT_RGB565:
9399                 bpp = 6*3; /* min is 18bpp */
9400                 break;
9401         case DRM_FORMAT_XBGR8888:
9402         case DRM_FORMAT_ABGR8888:
9403                 /* checked in intel_framebuffer_init already */
9404                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9405                         return -EINVAL;
9406         case DRM_FORMAT_XRGB8888:
9407         case DRM_FORMAT_ARGB8888:
9408                 bpp = 8*3;
9409                 break;
9410         case DRM_FORMAT_XRGB2101010:
9411         case DRM_FORMAT_ARGB2101010:
9412         case DRM_FORMAT_XBGR2101010:
9413         case DRM_FORMAT_ABGR2101010:
9414                 /* checked in intel_framebuffer_init already */
9415                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9416                         return -EINVAL;
9417                 bpp = 10*3;
9418                 break;
9419         /* TODO: gen4+ supports 16 bpc floating point, too. */
9420         default:
9421                 DRM_DEBUG_KMS("unsupported depth\n");
9422                 return -EINVAL;
9423         }
9424
9425         pipe_config->pipe_bpp = bpp;
9426
9427         /* Clamp display bpp to EDID value */
9428         list_for_each_entry(connector, &dev->mode_config.connector_list,
9429                             base.head) {
9430                 if (!connector->new_encoder ||
9431                     connector->new_encoder->new_crtc != crtc)
9432                         continue;
9433
9434                 connected_sink_compute_bpp(connector, pipe_config);
9435         }
9436
9437         return bpp;
9438 }
9439
9440 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9441 {
9442         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9443                         "type: 0x%x flags: 0x%x\n",
9444                 mode->crtc_clock,
9445                 mode->crtc_hdisplay, mode->crtc_hsync_start,
9446                 mode->crtc_hsync_end, mode->crtc_htotal,
9447                 mode->crtc_vdisplay, mode->crtc_vsync_start,
9448                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9449 }
9450
9451 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9452                                    struct intel_crtc_config *pipe_config,
9453                                    const char *context)
9454 {
9455         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9456                       context, pipe_name(crtc->pipe));
9457
9458         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9459         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9460                       pipe_config->pipe_bpp, pipe_config->dither);
9461         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9462                       pipe_config->has_pch_encoder,
9463                       pipe_config->fdi_lanes,
9464                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9465                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9466                       pipe_config->fdi_m_n.tu);
9467         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9468                       pipe_config->has_dp_encoder,
9469                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9470                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9471                       pipe_config->dp_m_n.tu);
9472         DRM_DEBUG_KMS("requested mode:\n");
9473         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9474         DRM_DEBUG_KMS("adjusted mode:\n");
9475         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9476         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9477         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9478         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9479                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9480         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9481                       pipe_config->gmch_pfit.control,
9482                       pipe_config->gmch_pfit.pgm_ratios,
9483                       pipe_config->gmch_pfit.lvds_border_bits);
9484         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9485                       pipe_config->pch_pfit.pos,
9486                       pipe_config->pch_pfit.size,
9487                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9488         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9489         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
9490 }
9491
9492 static bool encoders_cloneable(const struct intel_encoder *a,
9493                                const struct intel_encoder *b)
9494 {
9495         /* masks could be asymmetric, so check both ways */
9496         return a == b || (a->cloneable & (1 << b->type) &&
9497                           b->cloneable & (1 << a->type));
9498 }
9499
9500 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9501                                          struct intel_encoder *encoder)
9502 {
9503         struct drm_device *dev = crtc->base.dev;
9504         struct intel_encoder *source_encoder;
9505
9506         list_for_each_entry(source_encoder,
9507                             &dev->mode_config.encoder_list, base.head) {
9508                 if (source_encoder->new_crtc != crtc)
9509                         continue;
9510
9511                 if (!encoders_cloneable(encoder, source_encoder))
9512                         return false;
9513         }
9514
9515         return true;
9516 }
9517
9518 static bool check_encoder_cloning(struct intel_crtc *crtc)
9519 {
9520         struct drm_device *dev = crtc->base.dev;
9521         struct intel_encoder *encoder;
9522
9523         list_for_each_entry(encoder,
9524                             &dev->mode_config.encoder_list, base.head) {
9525                 if (encoder->new_crtc != crtc)
9526                         continue;
9527
9528                 if (!check_single_encoder_cloning(crtc, encoder))
9529                         return false;
9530         }
9531
9532         return true;
9533 }
9534
9535 static struct intel_crtc_config *
9536 intel_modeset_pipe_config(struct drm_crtc *crtc,
9537                           struct drm_framebuffer *fb,
9538                           struct drm_display_mode *mode)
9539 {
9540         struct drm_device *dev = crtc->dev;
9541         struct intel_encoder *encoder;
9542         struct intel_crtc_config *pipe_config;
9543         int plane_bpp, ret = -EINVAL;
9544         bool retry = true;
9545
9546         if (!check_encoder_cloning(to_intel_crtc(crtc))) {
9547                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
9548                 return ERR_PTR(-EINVAL);
9549         }
9550
9551         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9552         if (!pipe_config)
9553                 return ERR_PTR(-ENOMEM);
9554
9555         drm_mode_copy(&pipe_config->adjusted_mode, mode);
9556         drm_mode_copy(&pipe_config->requested_mode, mode);
9557
9558         pipe_config->cpu_transcoder =
9559                 (enum transcoder) to_intel_crtc(crtc)->pipe;
9560         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9561
9562         /*
9563          * Sanitize sync polarity flags based on requested ones. If neither
9564          * positive or negative polarity is requested, treat this as meaning
9565          * negative polarity.
9566          */
9567         if (!(pipe_config->adjusted_mode.flags &
9568               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
9569                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
9570
9571         if (!(pipe_config->adjusted_mode.flags &
9572               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
9573                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
9574
9575         /* Compute a starting value for pipe_config->pipe_bpp taking the source
9576          * plane pixel format and any sink constraints into account. Returns the
9577          * source plane bpp so that dithering can be selected on mismatches
9578          * after encoders and crtc also have had their say. */
9579         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
9580                                               fb, pipe_config);
9581         if (plane_bpp < 0)
9582                 goto fail;
9583
9584         /*
9585          * Determine the real pipe dimensions. Note that stereo modes can
9586          * increase the actual pipe size due to the frame doubling and
9587          * insertion of additional space for blanks between the frame. This
9588          * is stored in the crtc timings. We use the requested mode to do this
9589          * computation to clearly distinguish it from the adjusted mode, which
9590          * can be changed by the connectors in the below retry loop.
9591          */
9592         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
9593         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
9594         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
9595
9596 encoder_retry:
9597         /* Ensure the port clock defaults are reset when retrying. */
9598         pipe_config->port_clock = 0;
9599         pipe_config->pixel_multiplier = 1;
9600
9601         /* Fill in default crtc timings, allow encoders to overwrite them. */
9602         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
9603
9604         /* Pass our mode to the connectors and the CRTC to give them a chance to
9605          * adjust it according to limitations or connector properties, and also
9606          * a chance to reject the mode entirely.
9607          */
9608         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9609                             base.head) {
9610
9611                 if (&encoder->new_crtc->base != crtc)
9612                         continue;
9613
9614                 if (!(encoder->compute_config(encoder, pipe_config))) {
9615                         DRM_DEBUG_KMS("Encoder config failure\n");
9616                         goto fail;
9617                 }
9618         }
9619
9620         /* Set default port clock if not overwritten by the encoder. Needs to be
9621          * done afterwards in case the encoder adjusts the mode. */
9622         if (!pipe_config->port_clock)
9623                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
9624                         * pipe_config->pixel_multiplier;
9625
9626         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
9627         if (ret < 0) {
9628                 DRM_DEBUG_KMS("CRTC fixup failed\n");
9629                 goto fail;
9630         }
9631
9632         if (ret == RETRY) {
9633                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
9634                         ret = -EINVAL;
9635                         goto fail;
9636                 }
9637
9638                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9639                 retry = false;
9640                 goto encoder_retry;
9641         }
9642
9643         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
9644         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9645                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
9646
9647         return pipe_config;
9648 fail:
9649         kfree(pipe_config);
9650         return ERR_PTR(ret);
9651 }
9652
9653 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
9654  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9655 static void
9656 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
9657                              unsigned *prepare_pipes, unsigned *disable_pipes)
9658 {
9659         struct intel_crtc *intel_crtc;
9660         struct drm_device *dev = crtc->dev;
9661         struct intel_encoder *encoder;
9662         struct intel_connector *connector;
9663         struct drm_crtc *tmp_crtc;
9664
9665         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
9666
9667         /* Check which crtcs have changed outputs connected to them, these need
9668          * to be part of the prepare_pipes mask. We don't (yet) support global
9669          * modeset across multiple crtcs, so modeset_pipes will only have one
9670          * bit set at most. */
9671         list_for_each_entry(connector, &dev->mode_config.connector_list,
9672                             base.head) {
9673                 if (connector->base.encoder == &connector->new_encoder->base)
9674                         continue;
9675
9676                 if (connector->base.encoder) {
9677                         tmp_crtc = connector->base.encoder->crtc;
9678
9679                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9680                 }
9681
9682                 if (connector->new_encoder)
9683                         *prepare_pipes |=
9684                                 1 << connector->new_encoder->new_crtc->pipe;
9685         }
9686
9687         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9688                             base.head) {
9689                 if (encoder->base.crtc == &encoder->new_crtc->base)
9690                         continue;
9691
9692                 if (encoder->base.crtc) {
9693                         tmp_crtc = encoder->base.crtc;
9694
9695                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9696                 }
9697
9698                 if (encoder->new_crtc)
9699                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
9700         }
9701
9702         /* Check for pipes that will be enabled/disabled ... */
9703         for_each_intel_crtc(dev, intel_crtc) {
9704                 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
9705                         continue;
9706
9707                 if (!intel_crtc->new_enabled)
9708                         *disable_pipes |= 1 << intel_crtc->pipe;
9709                 else
9710                         *prepare_pipes |= 1 << intel_crtc->pipe;
9711         }
9712
9713
9714         /* set_mode is also used to update properties on life display pipes. */
9715         intel_crtc = to_intel_crtc(crtc);
9716         if (intel_crtc->new_enabled)
9717                 *prepare_pipes |= 1 << intel_crtc->pipe;
9718
9719         /*
9720          * For simplicity do a full modeset on any pipe where the output routing
9721          * changed. We could be more clever, but that would require us to be
9722          * more careful with calling the relevant encoder->mode_set functions.
9723          */
9724         if (*prepare_pipes)
9725                 *modeset_pipes = *prepare_pipes;
9726
9727         /* ... and mask these out. */
9728         *modeset_pipes &= ~(*disable_pipes);
9729         *prepare_pipes &= ~(*disable_pipes);
9730
9731         /*
9732          * HACK: We don't (yet) fully support global modesets. intel_set_config
9733          * obies this rule, but the modeset restore mode of
9734          * intel_modeset_setup_hw_state does not.
9735          */
9736         *modeset_pipes &= 1 << intel_crtc->pipe;
9737         *prepare_pipes &= 1 << intel_crtc->pipe;
9738
9739         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9740                       *modeset_pipes, *prepare_pipes, *disable_pipes);
9741 }
9742
9743 static bool intel_crtc_in_use(struct drm_crtc *crtc)
9744 {
9745         struct drm_encoder *encoder;
9746         struct drm_device *dev = crtc->dev;
9747
9748         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
9749                 if (encoder->crtc == crtc)
9750                         return true;
9751
9752         return false;
9753 }
9754
9755 static void
9756 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
9757 {
9758         struct intel_encoder *intel_encoder;
9759         struct intel_crtc *intel_crtc;
9760         struct drm_connector *connector;
9761
9762         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
9763                             base.head) {
9764                 if (!intel_encoder->base.crtc)
9765                         continue;
9766
9767                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
9768
9769                 if (prepare_pipes & (1 << intel_crtc->pipe))
9770                         intel_encoder->connectors_active = false;
9771         }
9772
9773         intel_modeset_commit_output_state(dev);
9774
9775         /* Double check state. */
9776         for_each_intel_crtc(dev, intel_crtc) {
9777                 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
9778                 WARN_ON(intel_crtc->new_config &&
9779                         intel_crtc->new_config != &intel_crtc->config);
9780                 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
9781         }
9782
9783         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9784                 if (!connector->encoder || !connector->encoder->crtc)
9785                         continue;
9786
9787                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
9788
9789                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
9790                         struct drm_property *dpms_property =
9791                                 dev->mode_config.dpms_property;
9792
9793                         connector->dpms = DRM_MODE_DPMS_ON;
9794                         drm_object_property_set_value(&connector->base,
9795                                                          dpms_property,
9796                                                          DRM_MODE_DPMS_ON);
9797
9798                         intel_encoder = to_intel_encoder(connector->encoder);
9799                         intel_encoder->connectors_active = true;
9800                 }
9801         }
9802
9803 }
9804
9805 static bool intel_fuzzy_clock_check(int clock1, int clock2)
9806 {
9807         int diff;
9808
9809         if (clock1 == clock2)
9810                 return true;
9811
9812         if (!clock1 || !clock2)
9813                 return false;
9814
9815         diff = abs(clock1 - clock2);
9816
9817         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
9818                 return true;
9819
9820         return false;
9821 }
9822
9823 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9824         list_for_each_entry((intel_crtc), \
9825                             &(dev)->mode_config.crtc_list, \
9826                             base.head) \
9827                 if (mask & (1 <<(intel_crtc)->pipe))
9828
9829 static bool
9830 intel_pipe_config_compare(struct drm_device *dev,
9831                           struct intel_crtc_config *current_config,
9832                           struct intel_crtc_config *pipe_config)
9833 {
9834 #define PIPE_CONF_CHECK_X(name) \
9835         if (current_config->name != pipe_config->name) { \
9836                 DRM_ERROR("mismatch in " #name " " \
9837                           "(expected 0x%08x, found 0x%08x)\n", \
9838                           current_config->name, \
9839                           pipe_config->name); \
9840                 return false; \
9841         }
9842
9843 #define PIPE_CONF_CHECK_I(name) \
9844         if (current_config->name != pipe_config->name) { \
9845                 DRM_ERROR("mismatch in " #name " " \
9846                           "(expected %i, found %i)\n", \
9847                           current_config->name, \
9848                           pipe_config->name); \
9849                 return false; \
9850         }
9851
9852 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
9853         if ((current_config->name ^ pipe_config->name) & (mask)) { \
9854                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
9855                           "(expected %i, found %i)\n", \
9856                           current_config->name & (mask), \
9857                           pipe_config->name & (mask)); \
9858                 return false; \
9859         }
9860
9861 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9862         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9863                 DRM_ERROR("mismatch in " #name " " \
9864                           "(expected %i, found %i)\n", \
9865                           current_config->name, \
9866                           pipe_config->name); \
9867                 return false; \
9868         }
9869
9870 #define PIPE_CONF_QUIRK(quirk)  \
9871         ((current_config->quirks | pipe_config->quirks) & (quirk))
9872
9873         PIPE_CONF_CHECK_I(cpu_transcoder);
9874
9875         PIPE_CONF_CHECK_I(has_pch_encoder);
9876         PIPE_CONF_CHECK_I(fdi_lanes);
9877         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9878         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9879         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9880         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9881         PIPE_CONF_CHECK_I(fdi_m_n.tu);
9882
9883         PIPE_CONF_CHECK_I(has_dp_encoder);
9884         PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9885         PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9886         PIPE_CONF_CHECK_I(dp_m_n.link_m);
9887         PIPE_CONF_CHECK_I(dp_m_n.link_n);
9888         PIPE_CONF_CHECK_I(dp_m_n.tu);
9889
9890         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9891         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9892         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9893         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9894         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9895         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9896
9897         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9898         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9899         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9900         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9901         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9902         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9903
9904         PIPE_CONF_CHECK_I(pixel_multiplier);
9905         PIPE_CONF_CHECK_I(has_hdmi_sink);
9906         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
9907             IS_VALLEYVIEW(dev))
9908                 PIPE_CONF_CHECK_I(limited_color_range);
9909
9910         PIPE_CONF_CHECK_I(has_audio);
9911
9912         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9913                               DRM_MODE_FLAG_INTERLACE);
9914
9915         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9916                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9917                                       DRM_MODE_FLAG_PHSYNC);
9918                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9919                                       DRM_MODE_FLAG_NHSYNC);
9920                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9921                                       DRM_MODE_FLAG_PVSYNC);
9922                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9923                                       DRM_MODE_FLAG_NVSYNC);
9924         }
9925
9926         PIPE_CONF_CHECK_I(pipe_src_w);
9927         PIPE_CONF_CHECK_I(pipe_src_h);
9928
9929         /*
9930          * FIXME: BIOS likes to set up a cloned config with lvds+external
9931          * screen. Since we don't yet re-compute the pipe config when moving
9932          * just the lvds port away to another pipe the sw tracking won't match.
9933          *
9934          * Proper atomic modesets with recomputed global state will fix this.
9935          * Until then just don't check gmch state for inherited modes.
9936          */
9937         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
9938                 PIPE_CONF_CHECK_I(gmch_pfit.control);
9939                 /* pfit ratios are autocomputed by the hw on gen4+ */
9940                 if (INTEL_INFO(dev)->gen < 4)
9941                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9942                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9943         }
9944
9945         PIPE_CONF_CHECK_I(pch_pfit.enabled);
9946         if (current_config->pch_pfit.enabled) {
9947                 PIPE_CONF_CHECK_I(pch_pfit.pos);
9948                 PIPE_CONF_CHECK_I(pch_pfit.size);
9949         }
9950
9951         /* BDW+ don't expose a synchronous way to read the state */
9952         if (IS_HASWELL(dev))
9953                 PIPE_CONF_CHECK_I(ips_enabled);
9954
9955         PIPE_CONF_CHECK_I(double_wide);
9956
9957         PIPE_CONF_CHECK_I(shared_dpll);
9958         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
9959         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
9960         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
9961         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
9962
9963         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
9964                 PIPE_CONF_CHECK_I(pipe_bpp);
9965
9966         PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
9967         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
9968
9969 #undef PIPE_CONF_CHECK_X
9970 #undef PIPE_CONF_CHECK_I
9971 #undef PIPE_CONF_CHECK_FLAGS
9972 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
9973 #undef PIPE_CONF_QUIRK
9974
9975         return true;
9976 }
9977
9978 static void
9979 check_connector_state(struct drm_device *dev)
9980 {
9981         struct intel_connector *connector;
9982
9983         list_for_each_entry(connector, &dev->mode_config.connector_list,
9984                             base.head) {
9985                 /* This also checks the encoder/connector hw state with the
9986                  * ->get_hw_state callbacks. */
9987                 intel_connector_check_state(connector);
9988
9989                 WARN(&connector->new_encoder->base != connector->base.encoder,
9990                      "connector's staged encoder doesn't match current encoder\n");
9991         }
9992 }
9993
9994 static void
9995 check_encoder_state(struct drm_device *dev)
9996 {
9997         struct intel_encoder *encoder;
9998         struct intel_connector *connector;
9999
10000         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10001                             base.head) {
10002                 bool enabled = false;
10003                 bool active = false;
10004                 enum pipe pipe, tracked_pipe;
10005
10006                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10007                               encoder->base.base.id,
10008                               drm_get_encoder_name(&encoder->base));
10009
10010                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10011                      "encoder's stage crtc doesn't match current crtc\n");
10012                 WARN(encoder->connectors_active && !encoder->base.crtc,
10013                      "encoder's active_connectors set, but no crtc\n");
10014
10015                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10016                                     base.head) {
10017                         if (connector->base.encoder != &encoder->base)
10018                                 continue;
10019                         enabled = true;
10020                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10021                                 active = true;
10022                 }
10023                 WARN(!!encoder->base.crtc != enabled,
10024                      "encoder's enabled state mismatch "
10025                      "(expected %i, found %i)\n",
10026                      !!encoder->base.crtc, enabled);
10027                 WARN(active && !encoder->base.crtc,
10028                      "active encoder with no crtc\n");
10029
10030                 WARN(encoder->connectors_active != active,
10031                      "encoder's computed active state doesn't match tracked active state "
10032                      "(expected %i, found %i)\n", active, encoder->connectors_active);
10033
10034                 active = encoder->get_hw_state(encoder, &pipe);
10035                 WARN(active != encoder->connectors_active,
10036                      "encoder's hw state doesn't match sw tracking "
10037                      "(expected %i, found %i)\n",
10038                      encoder->connectors_active, active);
10039
10040                 if (!encoder->base.crtc)
10041                         continue;
10042
10043                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10044                 WARN(active && pipe != tracked_pipe,
10045                      "active encoder's pipe doesn't match"
10046                      "(expected %i, found %i)\n",
10047                      tracked_pipe, pipe);
10048
10049         }
10050 }
10051
10052 static void
10053 check_crtc_state(struct drm_device *dev)
10054 {
10055         struct drm_i915_private *dev_priv = dev->dev_private;
10056         struct intel_crtc *crtc;
10057         struct intel_encoder *encoder;
10058         struct intel_crtc_config pipe_config;
10059
10060         for_each_intel_crtc(dev, crtc) {
10061                 bool enabled = false;
10062                 bool active = false;
10063
10064                 memset(&pipe_config, 0, sizeof(pipe_config));
10065
10066                 DRM_DEBUG_KMS("[CRTC:%d]\n",
10067                               crtc->base.base.id);
10068
10069                 WARN(crtc->active && !crtc->base.enabled,
10070                      "active crtc, but not enabled in sw tracking\n");
10071
10072                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10073                                     base.head) {
10074                         if (encoder->base.crtc != &crtc->base)
10075                                 continue;
10076                         enabled = true;
10077                         if (encoder->connectors_active)
10078                                 active = true;
10079                 }
10080
10081                 WARN(active != crtc->active,
10082                      "crtc's computed active state doesn't match tracked active state "
10083                      "(expected %i, found %i)\n", active, crtc->active);
10084                 WARN(enabled != crtc->base.enabled,
10085                      "crtc's computed enabled state doesn't match tracked enabled state "
10086                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10087
10088                 active = dev_priv->display.get_pipe_config(crtc,
10089                                                            &pipe_config);
10090
10091                 /* hw state is inconsistent with the pipe A quirk */
10092                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
10093                         active = crtc->active;
10094
10095                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10096                                     base.head) {
10097                         enum pipe pipe;
10098                         if (encoder->base.crtc != &crtc->base)
10099                                 continue;
10100                         if (encoder->get_hw_state(encoder, &pipe))
10101                                 encoder->get_config(encoder, &pipe_config);
10102                 }
10103
10104                 WARN(crtc->active != active,
10105                      "crtc active state doesn't match with hw state "
10106                      "(expected %i, found %i)\n", crtc->active, active);
10107
10108                 if (active &&
10109                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10110                         WARN(1, "pipe state doesn't match!\n");
10111                         intel_dump_pipe_config(crtc, &pipe_config,
10112                                                "[hw state]");
10113                         intel_dump_pipe_config(crtc, &crtc->config,
10114                                                "[sw state]");
10115                 }
10116         }
10117 }
10118
10119 static void
10120 check_shared_dpll_state(struct drm_device *dev)
10121 {
10122         struct drm_i915_private *dev_priv = dev->dev_private;
10123         struct intel_crtc *crtc;
10124         struct intel_dpll_hw_state dpll_hw_state;
10125         int i;
10126
10127         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10128                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10129                 int enabled_crtcs = 0, active_crtcs = 0;
10130                 bool active;
10131
10132                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10133
10134                 DRM_DEBUG_KMS("%s\n", pll->name);
10135
10136                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10137
10138                 WARN(pll->active > pll->refcount,
10139                      "more active pll users than references: %i vs %i\n",
10140                      pll->active, pll->refcount);
10141                 WARN(pll->active && !pll->on,
10142                      "pll in active use but not on in sw tracking\n");
10143                 WARN(pll->on && !pll->active,
10144                      "pll in on but not on in use in sw tracking\n");
10145                 WARN(pll->on != active,
10146                      "pll on state mismatch (expected %i, found %i)\n",
10147                      pll->on, active);
10148
10149                 for_each_intel_crtc(dev, crtc) {
10150                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10151                                 enabled_crtcs++;
10152                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10153                                 active_crtcs++;
10154                 }
10155                 WARN(pll->active != active_crtcs,
10156                      "pll active crtcs mismatch (expected %i, found %i)\n",
10157                      pll->active, active_crtcs);
10158                 WARN(pll->refcount != enabled_crtcs,
10159                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
10160                      pll->refcount, enabled_crtcs);
10161
10162                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10163                                        sizeof(dpll_hw_state)),
10164                      "pll hw state mismatch\n");
10165         }
10166 }
10167
10168 void
10169 intel_modeset_check_state(struct drm_device *dev)
10170 {
10171         check_connector_state(dev);
10172         check_encoder_state(dev);
10173         check_crtc_state(dev);
10174         check_shared_dpll_state(dev);
10175 }
10176
10177 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10178                                      int dotclock)
10179 {
10180         /*
10181          * FDI already provided one idea for the dotclock.
10182          * Yell if the encoder disagrees.
10183          */
10184         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10185              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10186              pipe_config->adjusted_mode.crtc_clock, dotclock);
10187 }
10188
10189 static int __intel_set_mode(struct drm_crtc *crtc,
10190                             struct drm_display_mode *mode,
10191                             int x, int y, struct drm_framebuffer *fb)
10192 {
10193         struct drm_device *dev = crtc->dev;
10194         struct drm_i915_private *dev_priv = dev->dev_private;
10195         struct drm_display_mode *saved_mode;
10196         struct intel_crtc_config *pipe_config = NULL;
10197         struct intel_crtc *intel_crtc;
10198         unsigned disable_pipes, prepare_pipes, modeset_pipes;
10199         int ret = 0;
10200
10201         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10202         if (!saved_mode)
10203                 return -ENOMEM;
10204
10205         intel_modeset_affected_pipes(crtc, &modeset_pipes,
10206                                      &prepare_pipes, &disable_pipes);
10207
10208         *saved_mode = crtc->mode;
10209
10210         /* Hack: Because we don't (yet) support global modeset on multiple
10211          * crtcs, we don't keep track of the new mode for more than one crtc.
10212          * Hence simply check whether any bit is set in modeset_pipes in all the
10213          * pieces of code that are not yet converted to deal with mutliple crtcs
10214          * changing their mode at the same time. */
10215         if (modeset_pipes) {
10216                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10217                 if (IS_ERR(pipe_config)) {
10218                         ret = PTR_ERR(pipe_config);
10219                         pipe_config = NULL;
10220
10221                         goto out;
10222                 }
10223                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10224                                        "[modeset]");
10225                 to_intel_crtc(crtc)->new_config = pipe_config;
10226         }
10227
10228         /*
10229          * See if the config requires any additional preparation, e.g.
10230          * to adjust global state with pipes off.  We need to do this
10231          * here so we can get the modeset_pipe updated config for the new
10232          * mode set on this crtc.  For other crtcs we need to use the
10233          * adjusted_mode bits in the crtc directly.
10234          */
10235         if (IS_VALLEYVIEW(dev)) {
10236                 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10237
10238                 /* may have added more to prepare_pipes than we should */
10239                 prepare_pipes &= ~disable_pipes;
10240         }
10241
10242         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10243                 intel_crtc_disable(&intel_crtc->base);
10244
10245         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10246                 if (intel_crtc->base.enabled)
10247                         dev_priv->display.crtc_disable(&intel_crtc->base);
10248         }
10249
10250         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10251          * to set it here already despite that we pass it down the callchain.
10252          */
10253         if (modeset_pipes) {
10254                 crtc->mode = *mode;
10255                 /* mode_set/enable/disable functions rely on a correct pipe
10256                  * config. */
10257                 to_intel_crtc(crtc)->config = *pipe_config;
10258                 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10259
10260                 /*
10261                  * Calculate and store various constants which
10262                  * are later needed by vblank and swap-completion
10263                  * timestamping. They are derived from true hwmode.
10264                  */
10265                 drm_calc_timestamping_constants(crtc,
10266                                                 &pipe_config->adjusted_mode);
10267         }
10268
10269         /* Only after disabling all output pipelines that will be changed can we
10270          * update the the output configuration. */
10271         intel_modeset_update_state(dev, prepare_pipes);
10272
10273         if (dev_priv->display.modeset_global_resources)
10274                 dev_priv->display.modeset_global_resources(dev);
10275
10276         /* Set up the DPLL and any encoders state that needs to adjust or depend
10277          * on the DPLL.
10278          */
10279         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10280                 struct drm_framebuffer *old_fb;
10281
10282                 mutex_lock(&dev->struct_mutex);
10283                 ret = intel_pin_and_fence_fb_obj(dev,
10284                                                  to_intel_framebuffer(fb)->obj,
10285                                                  NULL);
10286                 if (ret != 0) {
10287                         DRM_ERROR("pin & fence failed\n");
10288                         mutex_unlock(&dev->struct_mutex);
10289                         goto done;
10290                 }
10291                 old_fb = crtc->primary->fb;
10292                 if (old_fb)
10293                         intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
10294                 mutex_unlock(&dev->struct_mutex);
10295
10296                 crtc->primary->fb = fb;
10297                 crtc->x = x;
10298                 crtc->y = y;
10299
10300                 ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
10301                                                       x, y, fb);
10302                 if (ret)
10303                         goto done;
10304         }
10305
10306         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10307         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
10308                 dev_priv->display.crtc_enable(&intel_crtc->base);
10309
10310         /* FIXME: add subpixel order */
10311 done:
10312         if (ret && crtc->enabled)
10313                 crtc->mode = *saved_mode;
10314
10315 out:
10316         kfree(pipe_config);
10317         kfree(saved_mode);
10318         return ret;
10319 }
10320
10321 static int intel_set_mode(struct drm_crtc *crtc,
10322                           struct drm_display_mode *mode,
10323                           int x, int y, struct drm_framebuffer *fb)
10324 {
10325         int ret;
10326
10327         ret = __intel_set_mode(crtc, mode, x, y, fb);
10328
10329         if (ret == 0)
10330                 intel_modeset_check_state(crtc->dev);
10331
10332         return ret;
10333 }
10334
10335 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10336 {
10337         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10338 }
10339
10340 #undef for_each_intel_crtc_masked
10341
10342 static void intel_set_config_free(struct intel_set_config *config)
10343 {
10344         if (!config)
10345                 return;
10346
10347         kfree(config->save_connector_encoders);
10348         kfree(config->save_encoder_crtcs);
10349         kfree(config->save_crtc_enabled);
10350         kfree(config);
10351 }
10352
10353 static int intel_set_config_save_state(struct drm_device *dev,
10354                                        struct intel_set_config *config)
10355 {
10356         struct drm_crtc *crtc;
10357         struct drm_encoder *encoder;
10358         struct drm_connector *connector;
10359         int count;
10360
10361         config->save_crtc_enabled =
10362                 kcalloc(dev->mode_config.num_crtc,
10363                         sizeof(bool), GFP_KERNEL);
10364         if (!config->save_crtc_enabled)
10365                 return -ENOMEM;
10366
10367         config->save_encoder_crtcs =
10368                 kcalloc(dev->mode_config.num_encoder,
10369                         sizeof(struct drm_crtc *), GFP_KERNEL);
10370         if (!config->save_encoder_crtcs)
10371                 return -ENOMEM;
10372
10373         config->save_connector_encoders =
10374                 kcalloc(dev->mode_config.num_connector,
10375                         sizeof(struct drm_encoder *), GFP_KERNEL);
10376         if (!config->save_connector_encoders)
10377                 return -ENOMEM;
10378
10379         /* Copy data. Note that driver private data is not affected.
10380          * Should anything bad happen only the expected state is
10381          * restored, not the drivers personal bookkeeping.
10382          */
10383         count = 0;
10384         for_each_crtc(dev, crtc) {
10385                 config->save_crtc_enabled[count++] = crtc->enabled;
10386         }
10387
10388         count = 0;
10389         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10390                 config->save_encoder_crtcs[count++] = encoder->crtc;
10391         }
10392
10393         count = 0;
10394         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10395                 config->save_connector_encoders[count++] = connector->encoder;
10396         }
10397
10398         return 0;
10399 }
10400
10401 static void intel_set_config_restore_state(struct drm_device *dev,
10402                                            struct intel_set_config *config)
10403 {
10404         struct intel_crtc *crtc;
10405         struct intel_encoder *encoder;
10406         struct intel_connector *connector;
10407         int count;
10408
10409         count = 0;
10410         for_each_intel_crtc(dev, crtc) {
10411                 crtc->new_enabled = config->save_crtc_enabled[count++];
10412
10413                 if (crtc->new_enabled)
10414                         crtc->new_config = &crtc->config;
10415                 else
10416                         crtc->new_config = NULL;
10417         }
10418
10419         count = 0;
10420         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10421                 encoder->new_crtc =
10422                         to_intel_crtc(config->save_encoder_crtcs[count++]);
10423         }
10424
10425         count = 0;
10426         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10427                 connector->new_encoder =
10428                         to_intel_encoder(config->save_connector_encoders[count++]);
10429         }
10430 }
10431
10432 static bool
10433 is_crtc_connector_off(struct drm_mode_set *set)
10434 {
10435         int i;
10436
10437         if (set->num_connectors == 0)
10438                 return false;
10439
10440         if (WARN_ON(set->connectors == NULL))
10441                 return false;
10442
10443         for (i = 0; i < set->num_connectors; i++)
10444                 if (set->connectors[i]->encoder &&
10445                     set->connectors[i]->encoder->crtc == set->crtc &&
10446                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
10447                         return true;
10448
10449         return false;
10450 }
10451
10452 static void
10453 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
10454                                       struct intel_set_config *config)
10455 {
10456
10457         /* We should be able to check here if the fb has the same properties
10458          * and then just flip_or_move it */
10459         if (is_crtc_connector_off(set)) {
10460                 config->mode_changed = true;
10461         } else if (set->crtc->primary->fb != set->fb) {
10462                 /* If we have no fb then treat it as a full mode set */
10463                 if (set->crtc->primary->fb == NULL) {
10464                         struct intel_crtc *intel_crtc =
10465                                 to_intel_crtc(set->crtc);
10466
10467                         if (intel_crtc->active && i915.fastboot) {
10468                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
10469                                 config->fb_changed = true;
10470                         } else {
10471                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
10472                                 config->mode_changed = true;
10473                         }
10474                 } else if (set->fb == NULL) {
10475                         config->mode_changed = true;
10476                 } else if (set->fb->pixel_format !=
10477                            set->crtc->primary->fb->pixel_format) {
10478                         config->mode_changed = true;
10479                 } else {
10480                         config->fb_changed = true;
10481                 }
10482         }
10483
10484         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
10485                 config->fb_changed = true;
10486
10487         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
10488                 DRM_DEBUG_KMS("modes are different, full mode set\n");
10489                 drm_mode_debug_printmodeline(&set->crtc->mode);
10490                 drm_mode_debug_printmodeline(set->mode);
10491                 config->mode_changed = true;
10492         }
10493
10494         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
10495                         set->crtc->base.id, config->mode_changed, config->fb_changed);
10496 }
10497
10498 static int
10499 intel_modeset_stage_output_state(struct drm_device *dev,
10500                                  struct drm_mode_set *set,
10501                                  struct intel_set_config *config)
10502 {
10503         struct intel_connector *connector;
10504         struct intel_encoder *encoder;
10505         struct intel_crtc *crtc;
10506         int ro;
10507
10508         /* The upper layers ensure that we either disable a crtc or have a list
10509          * of connectors. For paranoia, double-check this. */
10510         WARN_ON(!set->fb && (set->num_connectors != 0));
10511         WARN_ON(set->fb && (set->num_connectors == 0));
10512
10513         list_for_each_entry(connector, &dev->mode_config.connector_list,
10514                             base.head) {
10515                 /* Otherwise traverse passed in connector list and get encoders
10516                  * for them. */
10517                 for (ro = 0; ro < set->num_connectors; ro++) {
10518                         if (set->connectors[ro] == &connector->base) {
10519                                 connector->new_encoder = connector->encoder;
10520                                 break;
10521                         }
10522                 }
10523
10524                 /* If we disable the crtc, disable all its connectors. Also, if
10525                  * the connector is on the changing crtc but not on the new
10526                  * connector list, disable it. */
10527                 if ((!set->fb || ro == set->num_connectors) &&
10528                     connector->base.encoder &&
10529                     connector->base.encoder->crtc == set->crtc) {
10530                         connector->new_encoder = NULL;
10531
10532                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
10533                                 connector->base.base.id,
10534                                 drm_get_connector_name(&connector->base));
10535                 }
10536
10537
10538                 if (&connector->new_encoder->base != connector->base.encoder) {
10539                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
10540                         config->mode_changed = true;
10541                 }
10542         }
10543         /* connector->new_encoder is now updated for all connectors. */
10544
10545         /* Update crtc of enabled connectors. */
10546         list_for_each_entry(connector, &dev->mode_config.connector_list,
10547                             base.head) {
10548                 struct drm_crtc *new_crtc;
10549
10550                 if (!connector->new_encoder)
10551                         continue;
10552
10553                 new_crtc = connector->new_encoder->base.crtc;
10554
10555                 for (ro = 0; ro < set->num_connectors; ro++) {
10556                         if (set->connectors[ro] == &connector->base)
10557                                 new_crtc = set->crtc;
10558                 }
10559
10560                 /* Make sure the new CRTC will work with the encoder */
10561                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
10562                                          new_crtc)) {
10563                         return -EINVAL;
10564                 }
10565                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
10566
10567                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
10568                         connector->base.base.id,
10569                         drm_get_connector_name(&connector->base),
10570                         new_crtc->base.id);
10571         }
10572
10573         /* Check for any encoders that needs to be disabled. */
10574         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10575                             base.head) {
10576                 int num_connectors = 0;
10577                 list_for_each_entry(connector,
10578                                     &dev->mode_config.connector_list,
10579                                     base.head) {
10580                         if (connector->new_encoder == encoder) {
10581                                 WARN_ON(!connector->new_encoder->new_crtc);
10582                                 num_connectors++;
10583                         }
10584                 }
10585
10586                 if (num_connectors == 0)
10587                         encoder->new_crtc = NULL;
10588                 else if (num_connectors > 1)
10589                         return -EINVAL;
10590
10591                 /* Only now check for crtc changes so we don't miss encoders
10592                  * that will be disabled. */
10593                 if (&encoder->new_crtc->base != encoder->base.crtc) {
10594                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
10595                         config->mode_changed = true;
10596                 }
10597         }
10598         /* Now we've also updated encoder->new_crtc for all encoders. */
10599
10600         for_each_intel_crtc(dev, crtc) {
10601                 crtc->new_enabled = false;
10602
10603                 list_for_each_entry(encoder,
10604                                     &dev->mode_config.encoder_list,
10605                                     base.head) {
10606                         if (encoder->new_crtc == crtc) {
10607                                 crtc->new_enabled = true;
10608                                 break;
10609                         }
10610                 }
10611
10612                 if (crtc->new_enabled != crtc->base.enabled) {
10613                         DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
10614                                       crtc->new_enabled ? "en" : "dis");
10615                         config->mode_changed = true;
10616                 }
10617
10618                 if (crtc->new_enabled)
10619                         crtc->new_config = &crtc->config;
10620                 else
10621                         crtc->new_config = NULL;
10622         }
10623
10624         return 0;
10625 }
10626
10627 static void disable_crtc_nofb(struct intel_crtc *crtc)
10628 {
10629         struct drm_device *dev = crtc->base.dev;
10630         struct intel_encoder *encoder;
10631         struct intel_connector *connector;
10632
10633         DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
10634                       pipe_name(crtc->pipe));
10635
10636         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10637                 if (connector->new_encoder &&
10638                     connector->new_encoder->new_crtc == crtc)
10639                         connector->new_encoder = NULL;
10640         }
10641
10642         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10643                 if (encoder->new_crtc == crtc)
10644                         encoder->new_crtc = NULL;
10645         }
10646
10647         crtc->new_enabled = false;
10648         crtc->new_config = NULL;
10649 }
10650
10651 static int intel_crtc_set_config(struct drm_mode_set *set)
10652 {
10653         struct drm_device *dev;
10654         struct drm_mode_set save_set;
10655         struct intel_set_config *config;
10656         int ret;
10657
10658         BUG_ON(!set);
10659         BUG_ON(!set->crtc);
10660         BUG_ON(!set->crtc->helper_private);
10661
10662         /* Enforce sane interface api - has been abused by the fb helper. */
10663         BUG_ON(!set->mode && set->fb);
10664         BUG_ON(set->fb && set->num_connectors == 0);
10665
10666         if (set->fb) {
10667                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
10668                                 set->crtc->base.id, set->fb->base.id,
10669                                 (int)set->num_connectors, set->x, set->y);
10670         } else {
10671                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
10672         }
10673
10674         dev = set->crtc->dev;
10675
10676         ret = -ENOMEM;
10677         config = kzalloc(sizeof(*config), GFP_KERNEL);
10678         if (!config)
10679                 goto out_config;
10680
10681         ret = intel_set_config_save_state(dev, config);
10682         if (ret)
10683                 goto out_config;
10684
10685         save_set.crtc = set->crtc;
10686         save_set.mode = &set->crtc->mode;
10687         save_set.x = set->crtc->x;
10688         save_set.y = set->crtc->y;
10689         save_set.fb = set->crtc->primary->fb;
10690
10691         /* Compute whether we need a full modeset, only an fb base update or no
10692          * change at all. In the future we might also check whether only the
10693          * mode changed, e.g. for LVDS where we only change the panel fitter in
10694          * such cases. */
10695         intel_set_config_compute_mode_changes(set, config);
10696
10697         ret = intel_modeset_stage_output_state(dev, set, config);
10698         if (ret)
10699                 goto fail;
10700
10701         if (config->mode_changed) {
10702                 ret = intel_set_mode(set->crtc, set->mode,
10703                                      set->x, set->y, set->fb);
10704         } else if (config->fb_changed) {
10705                 intel_crtc_wait_for_pending_flips(set->crtc);
10706
10707                 ret = intel_pipe_set_base(set->crtc,
10708                                           set->x, set->y, set->fb);
10709                 /*
10710                  * In the fastboot case this may be our only check of the
10711                  * state after boot.  It would be better to only do it on
10712                  * the first update, but we don't have a nice way of doing that
10713                  * (and really, set_config isn't used much for high freq page
10714                  * flipping, so increasing its cost here shouldn't be a big
10715                  * deal).
10716                  */
10717                 if (i915.fastboot && ret == 0)
10718                         intel_modeset_check_state(set->crtc->dev);
10719         }
10720
10721         if (ret) {
10722                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
10723                               set->crtc->base.id, ret);
10724 fail:
10725                 intel_set_config_restore_state(dev, config);
10726
10727                 /*
10728                  * HACK: if the pipe was on, but we didn't have a framebuffer,
10729                  * force the pipe off to avoid oopsing in the modeset code
10730                  * due to fb==NULL. This should only happen during boot since
10731                  * we don't yet reconstruct the FB from the hardware state.
10732                  */
10733                 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
10734                         disable_crtc_nofb(to_intel_crtc(save_set.crtc));
10735
10736                 /* Try to restore the config */
10737                 if (config->mode_changed &&
10738                     intel_set_mode(save_set.crtc, save_set.mode,
10739                                    save_set.x, save_set.y, save_set.fb))
10740                         DRM_ERROR("failed to restore config after modeset failure\n");
10741         }
10742
10743 out_config:
10744         intel_set_config_free(config);
10745         return ret;
10746 }
10747
10748 static const struct drm_crtc_funcs intel_crtc_funcs = {
10749         .cursor_set = intel_crtc_cursor_set,
10750         .cursor_move = intel_crtc_cursor_move,
10751         .gamma_set = intel_crtc_gamma_set,
10752         .set_config = intel_crtc_set_config,
10753         .destroy = intel_crtc_destroy,
10754         .page_flip = intel_crtc_page_flip,
10755 };
10756
10757 static void intel_cpu_pll_init(struct drm_device *dev)
10758 {
10759         if (HAS_DDI(dev))
10760                 intel_ddi_pll_init(dev);
10761 }
10762
10763 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
10764                                       struct intel_shared_dpll *pll,
10765                                       struct intel_dpll_hw_state *hw_state)
10766 {
10767         uint32_t val;
10768
10769         val = I915_READ(PCH_DPLL(pll->id));
10770         hw_state->dpll = val;
10771         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
10772         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
10773
10774         return val & DPLL_VCO_ENABLE;
10775 }
10776
10777 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
10778                                   struct intel_shared_dpll *pll)
10779 {
10780         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
10781         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
10782 }
10783
10784 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
10785                                 struct intel_shared_dpll *pll)
10786 {
10787         /* PCH refclock must be enabled first */
10788         ibx_assert_pch_refclk_enabled(dev_priv);
10789
10790         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10791
10792         /* Wait for the clocks to stabilize. */
10793         POSTING_READ(PCH_DPLL(pll->id));
10794         udelay(150);
10795
10796         /* The pixel multiplier can only be updated once the
10797          * DPLL is enabled and the clocks are stable.
10798          *
10799          * So write it again.
10800          */
10801         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10802         POSTING_READ(PCH_DPLL(pll->id));
10803         udelay(200);
10804 }
10805
10806 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
10807                                  struct intel_shared_dpll *pll)
10808 {
10809         struct drm_device *dev = dev_priv->dev;
10810         struct intel_crtc *crtc;
10811
10812         /* Make sure no transcoder isn't still depending on us. */
10813         for_each_intel_crtc(dev, crtc) {
10814                 if (intel_crtc_to_shared_dpll(crtc) == pll)
10815                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
10816         }
10817
10818         I915_WRITE(PCH_DPLL(pll->id), 0);
10819         POSTING_READ(PCH_DPLL(pll->id));
10820         udelay(200);
10821 }
10822
10823 static char *ibx_pch_dpll_names[] = {
10824         "PCH DPLL A",
10825         "PCH DPLL B",
10826 };
10827
10828 static void ibx_pch_dpll_init(struct drm_device *dev)
10829 {
10830         struct drm_i915_private *dev_priv = dev->dev_private;
10831         int i;
10832
10833         dev_priv->num_shared_dpll = 2;
10834
10835         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10836                 dev_priv->shared_dplls[i].id = i;
10837                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
10838                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
10839                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
10840                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
10841                 dev_priv->shared_dplls[i].get_hw_state =
10842                         ibx_pch_dpll_get_hw_state;
10843         }
10844 }
10845
10846 static void intel_shared_dpll_init(struct drm_device *dev)
10847 {
10848         struct drm_i915_private *dev_priv = dev->dev_private;
10849
10850         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
10851                 ibx_pch_dpll_init(dev);
10852         else
10853                 dev_priv->num_shared_dpll = 0;
10854
10855         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
10856 }
10857
10858 static void intel_crtc_init(struct drm_device *dev, int pipe)
10859 {
10860         struct drm_i915_private *dev_priv = dev->dev_private;
10861         struct intel_crtc *intel_crtc;
10862         int i;
10863
10864         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
10865         if (intel_crtc == NULL)
10866                 return;
10867
10868         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
10869
10870         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
10871         for (i = 0; i < 256; i++) {
10872                 intel_crtc->lut_r[i] = i;
10873                 intel_crtc->lut_g[i] = i;
10874                 intel_crtc->lut_b[i] = i;
10875         }
10876
10877         /*
10878          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
10879          * is hooked to plane B. Hence we want plane A feeding pipe B.
10880          */
10881         intel_crtc->pipe = pipe;
10882         intel_crtc->plane = pipe;
10883         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
10884                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
10885                 intel_crtc->plane = !pipe;
10886         }
10887
10888         init_waitqueue_head(&intel_crtc->vbl_wait);
10889
10890         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
10891                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
10892         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
10893         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
10894
10895         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
10896 }
10897
10898 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
10899 {
10900         struct drm_encoder *encoder = connector->base.encoder;
10901
10902         WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex));
10903
10904         if (!encoder)
10905                 return INVALID_PIPE;
10906
10907         return to_intel_crtc(encoder->crtc)->pipe;
10908 }
10909
10910 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
10911                                 struct drm_file *file)
10912 {
10913         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
10914         struct drm_mode_object *drmmode_obj;
10915         struct intel_crtc *crtc;
10916
10917         if (!drm_core_check_feature(dev, DRIVER_MODESET))
10918                 return -ENODEV;
10919
10920         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
10921                         DRM_MODE_OBJECT_CRTC);
10922
10923         if (!drmmode_obj) {
10924                 DRM_ERROR("no such CRTC id\n");
10925                 return -ENOENT;
10926         }
10927
10928         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
10929         pipe_from_crtc_id->pipe = crtc->pipe;
10930
10931         return 0;
10932 }
10933
10934 static int intel_encoder_clones(struct intel_encoder *encoder)
10935 {
10936         struct drm_device *dev = encoder->base.dev;
10937         struct intel_encoder *source_encoder;
10938         int index_mask = 0;
10939         int entry = 0;
10940
10941         list_for_each_entry(source_encoder,
10942                             &dev->mode_config.encoder_list, base.head) {
10943                 if (encoders_cloneable(encoder, source_encoder))
10944                         index_mask |= (1 << entry);
10945
10946                 entry++;
10947         }
10948
10949         return index_mask;
10950 }
10951
10952 static bool has_edp_a(struct drm_device *dev)
10953 {
10954         struct drm_i915_private *dev_priv = dev->dev_private;
10955
10956         if (!IS_MOBILE(dev))
10957                 return false;
10958
10959         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
10960                 return false;
10961
10962         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
10963                 return false;
10964
10965         return true;
10966 }
10967
10968 const char *intel_output_name(int output)
10969 {
10970         static const char *names[] = {
10971                 [INTEL_OUTPUT_UNUSED] = "Unused",
10972                 [INTEL_OUTPUT_ANALOG] = "Analog",
10973                 [INTEL_OUTPUT_DVO] = "DVO",
10974                 [INTEL_OUTPUT_SDVO] = "SDVO",
10975                 [INTEL_OUTPUT_LVDS] = "LVDS",
10976                 [INTEL_OUTPUT_TVOUT] = "TV",
10977                 [INTEL_OUTPUT_HDMI] = "HDMI",
10978                 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
10979                 [INTEL_OUTPUT_EDP] = "eDP",
10980                 [INTEL_OUTPUT_DSI] = "DSI",
10981                 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
10982         };
10983
10984         if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
10985                 return "Invalid";
10986
10987         return names[output];
10988 }
10989
10990 static void intel_setup_outputs(struct drm_device *dev)
10991 {
10992         struct drm_i915_private *dev_priv = dev->dev_private;
10993         struct intel_encoder *encoder;
10994         bool dpd_is_edp = false;
10995
10996         intel_lvds_init(dev);
10997
10998         if (!IS_ULT(dev) && !IS_CHERRYVIEW(dev))
10999                 intel_crt_init(dev);
11000
11001         if (HAS_DDI(dev)) {
11002                 int found;
11003
11004                 /* Haswell uses DDI functions to detect digital outputs */
11005                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
11006                 /* DDI A only supports eDP */
11007                 if (found)
11008                         intel_ddi_init(dev, PORT_A);
11009
11010                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
11011                  * register */
11012                 found = I915_READ(SFUSE_STRAP);
11013
11014                 if (found & SFUSE_STRAP_DDIB_DETECTED)
11015                         intel_ddi_init(dev, PORT_B);
11016                 if (found & SFUSE_STRAP_DDIC_DETECTED)
11017                         intel_ddi_init(dev, PORT_C);
11018                 if (found & SFUSE_STRAP_DDID_DETECTED)
11019                         intel_ddi_init(dev, PORT_D);
11020         } else if (HAS_PCH_SPLIT(dev)) {
11021                 int found;
11022                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
11023
11024                 if (has_edp_a(dev))
11025                         intel_dp_init(dev, DP_A, PORT_A);
11026
11027                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
11028                         /* PCH SDVOB multiplex with HDMIB */
11029                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
11030                         if (!found)
11031                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
11032                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
11033                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
11034                 }
11035
11036                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
11037                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
11038
11039                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
11040                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
11041
11042                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
11043                         intel_dp_init(dev, PCH_DP_C, PORT_C);
11044
11045                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
11046                         intel_dp_init(dev, PCH_DP_D, PORT_D);
11047         } else if (IS_VALLEYVIEW(dev)) {
11048                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
11049                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
11050                                         PORT_B);
11051                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
11052                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
11053                 }
11054
11055                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
11056                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
11057                                         PORT_C);
11058                         if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
11059                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
11060                 }
11061
11062                 intel_dsi_init(dev);
11063         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
11064                 bool found = false;
11065
11066                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
11067                         DRM_DEBUG_KMS("probing SDVOB\n");
11068                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
11069                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
11070                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
11071                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
11072                         }
11073
11074                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
11075                                 intel_dp_init(dev, DP_B, PORT_B);
11076                 }
11077
11078                 /* Before G4X SDVOC doesn't have its own detect register */
11079
11080                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
11081                         DRM_DEBUG_KMS("probing SDVOC\n");
11082                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
11083                 }
11084
11085                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
11086
11087                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
11088                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
11089                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
11090                         }
11091                         if (SUPPORTS_INTEGRATED_DP(dev))
11092                                 intel_dp_init(dev, DP_C, PORT_C);
11093                 }
11094
11095                 if (SUPPORTS_INTEGRATED_DP(dev) &&
11096                     (I915_READ(DP_D) & DP_DETECTED))
11097                         intel_dp_init(dev, DP_D, PORT_D);
11098         } else if (IS_GEN2(dev))
11099                 intel_dvo_init(dev);
11100
11101         if (SUPPORTS_TV(dev))
11102                 intel_tv_init(dev);
11103
11104         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
11105                 encoder->base.possible_crtcs = encoder->crtc_mask;
11106                 encoder->base.possible_clones =
11107                         intel_encoder_clones(encoder);
11108         }
11109
11110         intel_init_pch_refclk(dev);
11111
11112         drm_helper_move_panel_connectors_to_head(dev);
11113 }
11114
11115 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
11116 {
11117         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11118
11119         drm_framebuffer_cleanup(fb);
11120         WARN_ON(!intel_fb->obj->framebuffer_references--);
11121         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
11122         kfree(intel_fb);
11123 }
11124
11125 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
11126                                                 struct drm_file *file,
11127                                                 unsigned int *handle)
11128 {
11129         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11130         struct drm_i915_gem_object *obj = intel_fb->obj;
11131
11132         return drm_gem_handle_create(file, &obj->base, handle);
11133 }
11134
11135 static const struct drm_framebuffer_funcs intel_fb_funcs = {
11136         .destroy = intel_user_framebuffer_destroy,
11137         .create_handle = intel_user_framebuffer_create_handle,
11138 };
11139
11140 static int intel_framebuffer_init(struct drm_device *dev,
11141                                   struct intel_framebuffer *intel_fb,
11142                                   struct drm_mode_fb_cmd2 *mode_cmd,
11143                                   struct drm_i915_gem_object *obj)
11144 {
11145         int aligned_height;
11146         int pitch_limit;
11147         int ret;
11148
11149         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
11150
11151         if (obj->tiling_mode == I915_TILING_Y) {
11152                 DRM_DEBUG("hardware does not support tiling Y\n");
11153                 return -EINVAL;
11154         }
11155
11156         if (mode_cmd->pitches[0] & 63) {
11157                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
11158                           mode_cmd->pitches[0]);
11159                 return -EINVAL;
11160         }
11161
11162         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
11163                 pitch_limit = 32*1024;
11164         } else if (INTEL_INFO(dev)->gen >= 4) {
11165                 if (obj->tiling_mode)
11166                         pitch_limit = 16*1024;
11167                 else
11168                         pitch_limit = 32*1024;
11169         } else if (INTEL_INFO(dev)->gen >= 3) {
11170                 if (obj->tiling_mode)
11171                         pitch_limit = 8*1024;
11172                 else
11173                         pitch_limit = 16*1024;
11174         } else
11175                 /* XXX DSPC is limited to 4k tiled */
11176                 pitch_limit = 8*1024;
11177
11178         if (mode_cmd->pitches[0] > pitch_limit) {
11179                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
11180                           obj->tiling_mode ? "tiled" : "linear",
11181                           mode_cmd->pitches[0], pitch_limit);
11182                 return -EINVAL;
11183         }
11184
11185         if (obj->tiling_mode != I915_TILING_NONE &&
11186             mode_cmd->pitches[0] != obj->stride) {
11187                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
11188                           mode_cmd->pitches[0], obj->stride);
11189                 return -EINVAL;
11190         }
11191
11192         /* Reject formats not supported by any plane early. */
11193         switch (mode_cmd->pixel_format) {
11194         case DRM_FORMAT_C8:
11195         case DRM_FORMAT_RGB565:
11196         case DRM_FORMAT_XRGB8888:
11197         case DRM_FORMAT_ARGB8888:
11198                 break;
11199         case DRM_FORMAT_XRGB1555:
11200         case DRM_FORMAT_ARGB1555:
11201                 if (INTEL_INFO(dev)->gen > 3) {
11202                         DRM_DEBUG("unsupported pixel format: %s\n",
11203                                   drm_get_format_name(mode_cmd->pixel_format));
11204                         return -EINVAL;
11205                 }
11206                 break;
11207         case DRM_FORMAT_XBGR8888:
11208         case DRM_FORMAT_ABGR8888:
11209         case DRM_FORMAT_XRGB2101010:
11210         case DRM_FORMAT_ARGB2101010:
11211         case DRM_FORMAT_XBGR2101010:
11212         case DRM_FORMAT_ABGR2101010:
11213                 if (INTEL_INFO(dev)->gen < 4) {
11214                         DRM_DEBUG("unsupported pixel format: %s\n",
11215                                   drm_get_format_name(mode_cmd->pixel_format));
11216                         return -EINVAL;
11217                 }
11218                 break;
11219         case DRM_FORMAT_YUYV:
11220         case DRM_FORMAT_UYVY:
11221         case DRM_FORMAT_YVYU:
11222         case DRM_FORMAT_VYUY:
11223                 if (INTEL_INFO(dev)->gen < 5) {
11224                         DRM_DEBUG("unsupported pixel format: %s\n",
11225                                   drm_get_format_name(mode_cmd->pixel_format));
11226                         return -EINVAL;
11227                 }
11228                 break;
11229         default:
11230                 DRM_DEBUG("unsupported pixel format: %s\n",
11231                           drm_get_format_name(mode_cmd->pixel_format));
11232                 return -EINVAL;
11233         }
11234
11235         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
11236         if (mode_cmd->offsets[0] != 0)
11237                 return -EINVAL;
11238
11239         aligned_height = intel_align_height(dev, mode_cmd->height,
11240                                             obj->tiling_mode);
11241         /* FIXME drm helper for size checks (especially planar formats)? */
11242         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
11243                 return -EINVAL;
11244
11245         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
11246         intel_fb->obj = obj;
11247         intel_fb->obj->framebuffer_references++;
11248
11249         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
11250         if (ret) {
11251                 DRM_ERROR("framebuffer init failed %d\n", ret);
11252                 return ret;
11253         }
11254
11255         return 0;
11256 }
11257
11258 static struct drm_framebuffer *
11259 intel_user_framebuffer_create(struct drm_device *dev,
11260                               struct drm_file *filp,
11261                               struct drm_mode_fb_cmd2 *mode_cmd)
11262 {
11263         struct drm_i915_gem_object *obj;
11264
11265         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
11266                                                 mode_cmd->handles[0]));
11267         if (&obj->base == NULL)
11268                 return ERR_PTR(-ENOENT);
11269
11270         return intel_framebuffer_create(dev, mode_cmd, obj);
11271 }
11272
11273 #ifndef CONFIG_DRM_I915_FBDEV
11274 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
11275 {
11276 }
11277 #endif
11278
11279 static const struct drm_mode_config_funcs intel_mode_funcs = {
11280         .fb_create = intel_user_framebuffer_create,
11281         .output_poll_changed = intel_fbdev_output_poll_changed,
11282 };
11283
11284 /* Set up chip specific display functions */
11285 static void intel_init_display(struct drm_device *dev)
11286 {
11287         struct drm_i915_private *dev_priv = dev->dev_private;
11288
11289         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
11290                 dev_priv->display.find_dpll = g4x_find_best_dpll;
11291         else if (IS_CHERRYVIEW(dev))
11292                 dev_priv->display.find_dpll = chv_find_best_dpll;
11293         else if (IS_VALLEYVIEW(dev))
11294                 dev_priv->display.find_dpll = vlv_find_best_dpll;
11295         else if (IS_PINEVIEW(dev))
11296                 dev_priv->display.find_dpll = pnv_find_best_dpll;
11297         else
11298                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
11299
11300         if (HAS_DDI(dev)) {
11301                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
11302                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
11303                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
11304                 dev_priv->display.crtc_enable = haswell_crtc_enable;
11305                 dev_priv->display.crtc_disable = haswell_crtc_disable;
11306                 dev_priv->display.off = haswell_crtc_off;
11307                 dev_priv->display.update_primary_plane =
11308                         ironlake_update_primary_plane;
11309         } else if (HAS_PCH_SPLIT(dev)) {
11310                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
11311                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
11312                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
11313                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
11314                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
11315                 dev_priv->display.off = ironlake_crtc_off;
11316                 dev_priv->display.update_primary_plane =
11317                         ironlake_update_primary_plane;
11318         } else if (IS_VALLEYVIEW(dev)) {
11319                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11320                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11321                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11322                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
11323                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11324                 dev_priv->display.off = i9xx_crtc_off;
11325                 dev_priv->display.update_primary_plane =
11326                         i9xx_update_primary_plane;
11327         } else {
11328                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11329                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11330                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11331                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
11332                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11333                 dev_priv->display.off = i9xx_crtc_off;
11334                 dev_priv->display.update_primary_plane =
11335                         i9xx_update_primary_plane;
11336         }
11337
11338         /* Returns the core display clock speed */
11339         if (IS_VALLEYVIEW(dev))
11340                 dev_priv->display.get_display_clock_speed =
11341                         valleyview_get_display_clock_speed;
11342         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
11343                 dev_priv->display.get_display_clock_speed =
11344                         i945_get_display_clock_speed;
11345         else if (IS_I915G(dev))
11346                 dev_priv->display.get_display_clock_speed =
11347                         i915_get_display_clock_speed;
11348         else if (IS_I945GM(dev) || IS_845G(dev))
11349                 dev_priv->display.get_display_clock_speed =
11350                         i9xx_misc_get_display_clock_speed;
11351         else if (IS_PINEVIEW(dev))
11352                 dev_priv->display.get_display_clock_speed =
11353                         pnv_get_display_clock_speed;
11354         else if (IS_I915GM(dev))
11355                 dev_priv->display.get_display_clock_speed =
11356                         i915gm_get_display_clock_speed;
11357         else if (IS_I865G(dev))
11358                 dev_priv->display.get_display_clock_speed =
11359                         i865_get_display_clock_speed;
11360         else if (IS_I85X(dev))
11361                 dev_priv->display.get_display_clock_speed =
11362                         i855_get_display_clock_speed;
11363         else /* 852, 830 */
11364                 dev_priv->display.get_display_clock_speed =
11365                         i830_get_display_clock_speed;
11366
11367         if (HAS_PCH_SPLIT(dev)) {
11368                 if (IS_GEN5(dev)) {
11369                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
11370                         dev_priv->display.write_eld = ironlake_write_eld;
11371                 } else if (IS_GEN6(dev)) {
11372                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
11373                         dev_priv->display.write_eld = ironlake_write_eld;
11374                         dev_priv->display.modeset_global_resources =
11375                                 snb_modeset_global_resources;
11376                 } else if (IS_IVYBRIDGE(dev)) {
11377                         /* FIXME: detect B0+ stepping and use auto training */
11378                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
11379                         dev_priv->display.write_eld = ironlake_write_eld;
11380                         dev_priv->display.modeset_global_resources =
11381                                 ivb_modeset_global_resources;
11382                 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
11383                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
11384                         dev_priv->display.write_eld = haswell_write_eld;
11385                         dev_priv->display.modeset_global_resources =
11386                                 haswell_modeset_global_resources;
11387                 }
11388         } else if (IS_G4X(dev)) {
11389                 dev_priv->display.write_eld = g4x_write_eld;
11390         } else if (IS_VALLEYVIEW(dev)) {
11391                 dev_priv->display.modeset_global_resources =
11392                         valleyview_modeset_global_resources;
11393                 dev_priv->display.write_eld = ironlake_write_eld;
11394         }
11395
11396         /* Default just returns -ENODEV to indicate unsupported */
11397         dev_priv->display.queue_flip = intel_default_queue_flip;
11398
11399         switch (INTEL_INFO(dev)->gen) {
11400         case 2:
11401                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
11402                 break;
11403
11404         case 3:
11405                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
11406                 break;
11407
11408         case 4:
11409         case 5:
11410                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
11411                 break;
11412
11413         case 6:
11414                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
11415                 break;
11416         case 7:
11417         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
11418                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
11419                 break;
11420         }
11421
11422         intel_panel_init_backlight_funcs(dev);
11423 }
11424
11425 /*
11426  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
11427  * resume, or other times.  This quirk makes sure that's the case for
11428  * affected systems.
11429  */
11430 static void quirk_pipea_force(struct drm_device *dev)
11431 {
11432         struct drm_i915_private *dev_priv = dev->dev_private;
11433
11434         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
11435         DRM_INFO("applying pipe a force quirk\n");
11436 }
11437
11438 /*
11439  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
11440  */
11441 static void quirk_ssc_force_disable(struct drm_device *dev)
11442 {
11443         struct drm_i915_private *dev_priv = dev->dev_private;
11444         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
11445         DRM_INFO("applying lvds SSC disable quirk\n");
11446 }
11447
11448 /*
11449  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
11450  * brightness value
11451  */
11452 static void quirk_invert_brightness(struct drm_device *dev)
11453 {
11454         struct drm_i915_private *dev_priv = dev->dev_private;
11455         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
11456         DRM_INFO("applying inverted panel brightness quirk\n");
11457 }
11458
11459 struct intel_quirk {
11460         int device;
11461         int subsystem_vendor;
11462         int subsystem_device;
11463         void (*hook)(struct drm_device *dev);
11464 };
11465
11466 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
11467 struct intel_dmi_quirk {
11468         void (*hook)(struct drm_device *dev);
11469         const struct dmi_system_id (*dmi_id_list)[];
11470 };
11471
11472 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
11473 {
11474         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
11475         return 1;
11476 }
11477
11478 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
11479         {
11480                 .dmi_id_list = &(const struct dmi_system_id[]) {
11481                         {
11482                                 .callback = intel_dmi_reverse_brightness,
11483                                 .ident = "NCR Corporation",
11484                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
11485                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
11486                                 },
11487                         },
11488                         { }  /* terminating entry */
11489                 },
11490                 .hook = quirk_invert_brightness,
11491         },
11492 };
11493
11494 static struct intel_quirk intel_quirks[] = {
11495         /* HP Mini needs pipe A force quirk (LP: #322104) */
11496         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
11497
11498         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
11499         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
11500
11501         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
11502         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
11503
11504         /* 830 needs to leave pipe A & dpll A up */
11505         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
11506
11507         /* Lenovo U160 cannot use SSC on LVDS */
11508         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
11509
11510         /* Sony Vaio Y cannot use SSC on LVDS */
11511         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
11512
11513         /* Acer Aspire 5734Z must invert backlight brightness */
11514         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
11515
11516         /* Acer/eMachines G725 */
11517         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
11518
11519         /* Acer/eMachines e725 */
11520         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
11521
11522         /* Acer/Packard Bell NCL20 */
11523         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
11524
11525         /* Acer Aspire 4736Z */
11526         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
11527
11528         /* Acer Aspire 5336 */
11529         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
11530 };
11531
11532 static void intel_init_quirks(struct drm_device *dev)
11533 {
11534         struct pci_dev *d = dev->pdev;
11535         int i;
11536
11537         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
11538                 struct intel_quirk *q = &intel_quirks[i];
11539
11540                 if (d->device == q->device &&
11541                     (d->subsystem_vendor == q->subsystem_vendor ||
11542                      q->subsystem_vendor == PCI_ANY_ID) &&
11543                     (d->subsystem_device == q->subsystem_device ||
11544                      q->subsystem_device == PCI_ANY_ID))
11545                         q->hook(dev);
11546         }
11547         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
11548                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
11549                         intel_dmi_quirks[i].hook(dev);
11550         }
11551 }
11552
11553 /* Disable the VGA plane that we never use */
11554 static void i915_disable_vga(struct drm_device *dev)
11555 {
11556         struct drm_i915_private *dev_priv = dev->dev_private;
11557         u8 sr1;
11558         u32 vga_reg = i915_vgacntrl_reg(dev);
11559
11560         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
11561         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
11562         outb(SR01, VGA_SR_INDEX);
11563         sr1 = inb(VGA_SR_DATA);
11564         outb(sr1 | 1<<5, VGA_SR_DATA);
11565         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
11566         udelay(300);
11567
11568         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
11569         POSTING_READ(vga_reg);
11570 }
11571
11572 void intel_modeset_init_hw(struct drm_device *dev)
11573 {
11574         intel_prepare_ddi(dev);
11575
11576         intel_init_clock_gating(dev);
11577
11578         intel_reset_dpio(dev);
11579
11580         intel_enable_gt_powersave(dev);
11581 }
11582
11583 void intel_modeset_suspend_hw(struct drm_device *dev)
11584 {
11585         intel_suspend_hw(dev);
11586 }
11587
11588 void intel_modeset_init(struct drm_device *dev)
11589 {
11590         struct drm_i915_private *dev_priv = dev->dev_private;
11591         int sprite, ret;
11592         enum pipe pipe;
11593         struct intel_crtc *crtc;
11594
11595         drm_mode_config_init(dev);
11596
11597         dev->mode_config.min_width = 0;
11598         dev->mode_config.min_height = 0;
11599
11600         dev->mode_config.preferred_depth = 24;
11601         dev->mode_config.prefer_shadow = 1;
11602
11603         dev->mode_config.funcs = &intel_mode_funcs;
11604
11605         intel_init_quirks(dev);
11606
11607         intel_init_pm(dev);
11608
11609         if (INTEL_INFO(dev)->num_pipes == 0)
11610                 return;
11611
11612         intel_init_display(dev);
11613
11614         if (IS_GEN2(dev)) {
11615                 dev->mode_config.max_width = 2048;
11616                 dev->mode_config.max_height = 2048;
11617         } else if (IS_GEN3(dev)) {
11618                 dev->mode_config.max_width = 4096;
11619                 dev->mode_config.max_height = 4096;
11620         } else {
11621                 dev->mode_config.max_width = 8192;
11622                 dev->mode_config.max_height = 8192;
11623         }
11624
11625         if (IS_GEN2(dev)) {
11626                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
11627                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
11628         } else {
11629                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
11630                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
11631         }
11632
11633         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
11634
11635         DRM_DEBUG_KMS("%d display pipe%s available.\n",
11636                       INTEL_INFO(dev)->num_pipes,
11637                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
11638
11639         for_each_pipe(pipe) {
11640                 intel_crtc_init(dev, pipe);
11641                 for_each_sprite(pipe, sprite) {
11642                         ret = intel_plane_init(dev, pipe, sprite);
11643                         if (ret)
11644                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
11645                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
11646                 }
11647         }
11648
11649         intel_init_dpio(dev);
11650         intel_reset_dpio(dev);
11651
11652         intel_cpu_pll_init(dev);
11653         intel_shared_dpll_init(dev);
11654
11655         /* Just disable it once at startup */
11656         i915_disable_vga(dev);
11657         intel_setup_outputs(dev);
11658
11659         /* Just in case the BIOS is doing something questionable. */
11660         intel_disable_fbc(dev);
11661
11662         mutex_lock(&dev->mode_config.mutex);
11663         intel_modeset_setup_hw_state(dev, false);
11664         mutex_unlock(&dev->mode_config.mutex);
11665
11666         for_each_intel_crtc(dev, crtc) {
11667                 if (!crtc->active)
11668                         continue;
11669
11670                 /*
11671                  * Note that reserving the BIOS fb up front prevents us
11672                  * from stuffing other stolen allocations like the ring
11673                  * on top.  This prevents some ugliness at boot time, and
11674                  * can even allow for smooth boot transitions if the BIOS
11675                  * fb is large enough for the active pipe configuration.
11676                  */
11677                 if (dev_priv->display.get_plane_config) {
11678                         dev_priv->display.get_plane_config(crtc,
11679                                                            &crtc->plane_config);
11680                         /*
11681                          * If the fb is shared between multiple heads, we'll
11682                          * just get the first one.
11683                          */
11684                         intel_find_plane_obj(crtc, &crtc->plane_config);
11685                 }
11686         }
11687 }
11688
11689 static void
11690 intel_connector_break_all_links(struct intel_connector *connector)
11691 {
11692         connector->base.dpms = DRM_MODE_DPMS_OFF;
11693         connector->base.encoder = NULL;
11694         connector->encoder->connectors_active = false;
11695         connector->encoder->base.crtc = NULL;
11696 }
11697
11698 static void intel_enable_pipe_a(struct drm_device *dev)
11699 {
11700         struct intel_connector *connector;
11701         struct drm_connector *crt = NULL;
11702         struct intel_load_detect_pipe load_detect_temp;
11703
11704         /* We can't just switch on the pipe A, we need to set things up with a
11705          * proper mode and output configuration. As a gross hack, enable pipe A
11706          * by enabling the load detect pipe once. */
11707         list_for_each_entry(connector,
11708                             &dev->mode_config.connector_list,
11709                             base.head) {
11710                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
11711                         crt = &connector->base;
11712                         break;
11713                 }
11714         }
11715
11716         if (!crt)
11717                 return;
11718
11719         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
11720                 intel_release_load_detect_pipe(crt, &load_detect_temp);
11721
11722
11723 }
11724
11725 static bool
11726 intel_check_plane_mapping(struct intel_crtc *crtc)
11727 {
11728         struct drm_device *dev = crtc->base.dev;
11729         struct drm_i915_private *dev_priv = dev->dev_private;
11730         u32 reg, val;
11731
11732         if (INTEL_INFO(dev)->num_pipes == 1)
11733                 return true;
11734
11735         reg = DSPCNTR(!crtc->plane);
11736         val = I915_READ(reg);
11737
11738         if ((val & DISPLAY_PLANE_ENABLE) &&
11739             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
11740                 return false;
11741
11742         return true;
11743 }
11744
11745 static void intel_sanitize_crtc(struct intel_crtc *crtc)
11746 {
11747         struct drm_device *dev = crtc->base.dev;
11748         struct drm_i915_private *dev_priv = dev->dev_private;
11749         u32 reg;
11750
11751         /* Clear any frame start delays used for debugging left by the BIOS */
11752         reg = PIPECONF(crtc->config.cpu_transcoder);
11753         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
11754
11755         /* We need to sanitize the plane -> pipe mapping first because this will
11756          * disable the crtc (and hence change the state) if it is wrong. Note
11757          * that gen4+ has a fixed plane -> pipe mapping.  */
11758         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
11759                 struct intel_connector *connector;
11760                 bool plane;
11761
11762                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
11763                               crtc->base.base.id);
11764
11765                 /* Pipe has the wrong plane attached and the plane is active.
11766                  * Temporarily change the plane mapping and disable everything
11767                  * ...  */
11768                 plane = crtc->plane;
11769                 crtc->plane = !plane;
11770                 dev_priv->display.crtc_disable(&crtc->base);
11771                 crtc->plane = plane;
11772
11773                 /* ... and break all links. */
11774                 list_for_each_entry(connector, &dev->mode_config.connector_list,
11775                                     base.head) {
11776                         if (connector->encoder->base.crtc != &crtc->base)
11777                                 continue;
11778
11779                         intel_connector_break_all_links(connector);
11780                 }
11781
11782                 WARN_ON(crtc->active);
11783                 crtc->base.enabled = false;
11784         }
11785
11786         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
11787             crtc->pipe == PIPE_A && !crtc->active) {
11788                 /* BIOS forgot to enable pipe A, this mostly happens after
11789                  * resume. Force-enable the pipe to fix this, the update_dpms
11790                  * call below we restore the pipe to the right state, but leave
11791                  * the required bits on. */
11792                 intel_enable_pipe_a(dev);
11793         }
11794
11795         /* Adjust the state of the output pipe according to whether we
11796          * have active connectors/encoders. */
11797         intel_crtc_update_dpms(&crtc->base);
11798
11799         if (crtc->active != crtc->base.enabled) {
11800                 struct intel_encoder *encoder;
11801
11802                 /* This can happen either due to bugs in the get_hw_state
11803                  * functions or because the pipe is force-enabled due to the
11804                  * pipe A quirk. */
11805                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
11806                               crtc->base.base.id,
11807                               crtc->base.enabled ? "enabled" : "disabled",
11808                               crtc->active ? "enabled" : "disabled");
11809
11810                 crtc->base.enabled = crtc->active;
11811
11812                 /* Because we only establish the connector -> encoder ->
11813                  * crtc links if something is active, this means the
11814                  * crtc is now deactivated. Break the links. connector
11815                  * -> encoder links are only establish when things are
11816                  *  actually up, hence no need to break them. */
11817                 WARN_ON(crtc->active);
11818
11819                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
11820                         WARN_ON(encoder->connectors_active);
11821                         encoder->base.crtc = NULL;
11822                 }
11823         }
11824         if (crtc->active) {
11825                 /*
11826                  * We start out with underrun reporting disabled to avoid races.
11827                  * For correct bookkeeping mark this on active crtcs.
11828                  *
11829                  * No protection against concurrent access is required - at
11830                  * worst a fifo underrun happens which also sets this to false.
11831                  */
11832                 crtc->cpu_fifo_underrun_disabled = true;
11833                 crtc->pch_fifo_underrun_disabled = true;
11834         }
11835 }
11836
11837 static void intel_sanitize_encoder(struct intel_encoder *encoder)
11838 {
11839         struct intel_connector *connector;
11840         struct drm_device *dev = encoder->base.dev;
11841
11842         /* We need to check both for a crtc link (meaning that the
11843          * encoder is active and trying to read from a pipe) and the
11844          * pipe itself being active. */
11845         bool has_active_crtc = encoder->base.crtc &&
11846                 to_intel_crtc(encoder->base.crtc)->active;
11847
11848         if (encoder->connectors_active && !has_active_crtc) {
11849                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
11850                               encoder->base.base.id,
11851                               drm_get_encoder_name(&encoder->base));
11852
11853                 /* Connector is active, but has no active pipe. This is
11854                  * fallout from our resume register restoring. Disable
11855                  * the encoder manually again. */
11856                 if (encoder->base.crtc) {
11857                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
11858                                       encoder->base.base.id,
11859                                       drm_get_encoder_name(&encoder->base));
11860                         encoder->disable(encoder);
11861                 }
11862
11863                 /* Inconsistent output/port/pipe state happens presumably due to
11864                  * a bug in one of the get_hw_state functions. Or someplace else
11865                  * in our code, like the register restore mess on resume. Clamp
11866                  * things to off as a safer default. */
11867                 list_for_each_entry(connector,
11868                                     &dev->mode_config.connector_list,
11869                                     base.head) {
11870                         if (connector->encoder != encoder)
11871                                 continue;
11872
11873                         intel_connector_break_all_links(connector);
11874                 }
11875         }
11876         /* Enabled encoders without active connectors will be fixed in
11877          * the crtc fixup. */
11878 }
11879
11880 void i915_redisable_vga_power_on(struct drm_device *dev)
11881 {
11882         struct drm_i915_private *dev_priv = dev->dev_private;
11883         u32 vga_reg = i915_vgacntrl_reg(dev);
11884
11885         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
11886                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
11887                 i915_disable_vga(dev);
11888         }
11889 }
11890
11891 void i915_redisable_vga(struct drm_device *dev)
11892 {
11893         struct drm_i915_private *dev_priv = dev->dev_private;
11894
11895         /* This function can be called both from intel_modeset_setup_hw_state or
11896          * at a very early point in our resume sequence, where the power well
11897          * structures are not yet restored. Since this function is at a very
11898          * paranoid "someone might have enabled VGA while we were not looking"
11899          * level, just check if the power well is enabled instead of trying to
11900          * follow the "don't touch the power well if we don't need it" policy
11901          * the rest of the driver uses. */
11902         if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
11903                 return;
11904
11905         i915_redisable_vga_power_on(dev);
11906 }
11907
11908 static bool primary_get_hw_state(struct intel_crtc *crtc)
11909 {
11910         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
11911
11912         if (!crtc->active)
11913                 return false;
11914
11915         return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
11916 }
11917
11918 static void intel_modeset_readout_hw_state(struct drm_device *dev)
11919 {
11920         struct drm_i915_private *dev_priv = dev->dev_private;
11921         enum pipe pipe;
11922         struct intel_crtc *crtc;
11923         struct intel_encoder *encoder;
11924         struct intel_connector *connector;
11925         int i;
11926
11927         for_each_intel_crtc(dev, crtc) {
11928                 memset(&crtc->config, 0, sizeof(crtc->config));
11929
11930                 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
11931
11932                 crtc->active = dev_priv->display.get_pipe_config(crtc,
11933                                                                  &crtc->config);
11934
11935                 crtc->base.enabled = crtc->active;
11936                 crtc->primary_enabled = primary_get_hw_state(crtc);
11937
11938                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
11939                               crtc->base.base.id,
11940                               crtc->active ? "enabled" : "disabled");
11941         }
11942
11943         /* FIXME: Smash this into the new shared dpll infrastructure. */
11944         if (HAS_DDI(dev))
11945                 intel_ddi_setup_hw_pll_state(dev);
11946
11947         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11948                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11949
11950                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
11951                 pll->active = 0;
11952                 for_each_intel_crtc(dev, crtc) {
11953                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11954                                 pll->active++;
11955                 }
11956                 pll->refcount = pll->active;
11957
11958                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
11959                               pll->name, pll->refcount, pll->on);
11960         }
11961
11962         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11963                             base.head) {
11964                 pipe = 0;
11965
11966                 if (encoder->get_hw_state(encoder, &pipe)) {
11967                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11968                         encoder->base.crtc = &crtc->base;
11969                         encoder->get_config(encoder, &crtc->config);
11970                 } else {
11971                         encoder->base.crtc = NULL;
11972                 }
11973
11974                 encoder->connectors_active = false;
11975                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
11976                               encoder->base.base.id,
11977                               drm_get_encoder_name(&encoder->base),
11978                               encoder->base.crtc ? "enabled" : "disabled",
11979                               pipe_name(pipe));
11980         }
11981
11982         list_for_each_entry(connector, &dev->mode_config.connector_list,
11983                             base.head) {
11984                 if (connector->get_hw_state(connector)) {
11985                         connector->base.dpms = DRM_MODE_DPMS_ON;
11986                         connector->encoder->connectors_active = true;
11987                         connector->base.encoder = &connector->encoder->base;
11988                 } else {
11989                         connector->base.dpms = DRM_MODE_DPMS_OFF;
11990                         connector->base.encoder = NULL;
11991                 }
11992                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
11993                               connector->base.base.id,
11994                               drm_get_connector_name(&connector->base),
11995                               connector->base.encoder ? "enabled" : "disabled");
11996         }
11997 }
11998
11999 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
12000  * and i915 state tracking structures. */
12001 void intel_modeset_setup_hw_state(struct drm_device *dev,
12002                                   bool force_restore)
12003 {
12004         struct drm_i915_private *dev_priv = dev->dev_private;
12005         enum pipe pipe;
12006         struct intel_crtc *crtc;
12007         struct intel_encoder *encoder;
12008         int i;
12009
12010         intel_modeset_readout_hw_state(dev);
12011
12012         /*
12013          * Now that we have the config, copy it to each CRTC struct
12014          * Note that this could go away if we move to using crtc_config
12015          * checking everywhere.
12016          */
12017         for_each_intel_crtc(dev, crtc) {
12018                 if (crtc->active && i915.fastboot) {
12019                         intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
12020                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
12021                                       crtc->base.base.id);
12022                         drm_mode_debug_printmodeline(&crtc->base.mode);
12023                 }
12024         }
12025
12026         /* HW state is read out, now we need to sanitize this mess. */
12027         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
12028                             base.head) {
12029                 intel_sanitize_encoder(encoder);
12030         }
12031
12032         for_each_pipe(pipe) {
12033                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
12034                 intel_sanitize_crtc(crtc);
12035                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
12036         }
12037
12038         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12039                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12040
12041                 if (!pll->on || pll->active)
12042                         continue;
12043
12044                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
12045
12046                 pll->disable(dev_priv, pll);
12047                 pll->on = false;
12048         }
12049
12050         if (HAS_PCH_SPLIT(dev))
12051                 ilk_wm_get_hw_state(dev);
12052
12053         if (force_restore) {
12054                 i915_redisable_vga(dev);
12055
12056                 /*
12057                  * We need to use raw interfaces for restoring state to avoid
12058                  * checking (bogus) intermediate states.
12059                  */
12060                 for_each_pipe(pipe) {
12061                         struct drm_crtc *crtc =
12062                                 dev_priv->pipe_to_crtc_mapping[pipe];
12063
12064                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
12065                                          crtc->primary->fb);
12066                 }
12067         } else {
12068                 intel_modeset_update_staged_output_state(dev);
12069         }
12070
12071         intel_modeset_check_state(dev);
12072 }
12073
12074 void intel_modeset_gem_init(struct drm_device *dev)
12075 {
12076         struct drm_crtc *c;
12077         struct intel_framebuffer *fb;
12078
12079         mutex_lock(&dev->struct_mutex);
12080         intel_init_gt_powersave(dev);
12081         mutex_unlock(&dev->struct_mutex);
12082
12083         intel_modeset_init_hw(dev);
12084
12085         intel_setup_overlay(dev);
12086
12087         /*
12088          * Make sure any fbs we allocated at startup are properly
12089          * pinned & fenced.  When we do the allocation it's too early
12090          * for this.
12091          */
12092         mutex_lock(&dev->struct_mutex);
12093         for_each_crtc(dev, c) {
12094                 if (!c->primary->fb)
12095                         continue;
12096
12097                 fb = to_intel_framebuffer(c->primary->fb);
12098                 if (intel_pin_and_fence_fb_obj(dev, fb->obj, NULL)) {
12099                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
12100                                   to_intel_crtc(c)->pipe);
12101                         drm_framebuffer_unreference(c->primary->fb);
12102                         c->primary->fb = NULL;
12103                 }
12104         }
12105         mutex_unlock(&dev->struct_mutex);
12106 }
12107
12108 void intel_connector_unregister(struct intel_connector *intel_connector)
12109 {
12110         struct drm_connector *connector = &intel_connector->base;
12111
12112         intel_panel_destroy_backlight(connector);
12113         drm_sysfs_connector_remove(connector);
12114 }
12115
12116 void intel_modeset_cleanup(struct drm_device *dev)
12117 {
12118         struct drm_i915_private *dev_priv = dev->dev_private;
12119         struct drm_crtc *crtc;
12120         struct drm_connector *connector;
12121
12122         /*
12123          * Interrupts and polling as the first thing to avoid creating havoc.
12124          * Too much stuff here (turning of rps, connectors, ...) would
12125          * experience fancy races otherwise.
12126          */
12127         drm_irq_uninstall(dev);
12128         cancel_work_sync(&dev_priv->hotplug_work);
12129         /*
12130          * Due to the hpd irq storm handling the hotplug work can re-arm the
12131          * poll handlers. Hence disable polling after hpd handling is shut down.
12132          */
12133         drm_kms_helper_poll_fini(dev);
12134
12135         mutex_lock(&dev->struct_mutex);
12136
12137         intel_unregister_dsm_handler();
12138
12139         for_each_crtc(dev, crtc) {
12140                 /* Skip inactive CRTCs */
12141                 if (!crtc->primary->fb)
12142                         continue;
12143
12144                 intel_increase_pllclock(crtc);
12145         }
12146
12147         intel_disable_fbc(dev);
12148
12149         intel_disable_gt_powersave(dev);
12150
12151         ironlake_teardown_rc6(dev);
12152
12153         mutex_unlock(&dev->struct_mutex);
12154
12155         /* flush any delayed tasks or pending work */
12156         flush_scheduled_work();
12157
12158         /* destroy the backlight and sysfs files before encoders/connectors */
12159         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12160                 struct intel_connector *intel_connector;
12161
12162                 intel_connector = to_intel_connector(connector);
12163                 intel_connector->unregister(intel_connector);
12164         }
12165
12166         drm_mode_config_cleanup(dev);
12167
12168         intel_cleanup_overlay(dev);
12169
12170         mutex_lock(&dev->struct_mutex);
12171         intel_cleanup_gt_powersave(dev);
12172         mutex_unlock(&dev->struct_mutex);
12173 }
12174
12175 /*
12176  * Return which encoder is currently attached for connector.
12177  */
12178 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
12179 {
12180         return &intel_attached_encoder(connector)->base;
12181 }
12182
12183 void intel_connector_attach_encoder(struct intel_connector *connector,
12184                                     struct intel_encoder *encoder)
12185 {
12186         connector->encoder = encoder;
12187         drm_mode_connector_attach_encoder(&connector->base,
12188                                           &encoder->base);
12189 }
12190
12191 /*
12192  * set vga decode state - true == enable VGA decode
12193  */
12194 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
12195 {
12196         struct drm_i915_private *dev_priv = dev->dev_private;
12197         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
12198         u16 gmch_ctrl;
12199
12200         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
12201                 DRM_ERROR("failed to read control word\n");
12202                 return -EIO;
12203         }
12204
12205         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
12206                 return 0;
12207
12208         if (state)
12209                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
12210         else
12211                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
12212
12213         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
12214                 DRM_ERROR("failed to write control word\n");
12215                 return -EIO;
12216         }
12217
12218         return 0;
12219 }
12220
12221 struct intel_display_error_state {
12222
12223         u32 power_well_driver;
12224
12225         int num_transcoders;
12226
12227         struct intel_cursor_error_state {
12228                 u32 control;
12229                 u32 position;
12230                 u32 base;
12231                 u32 size;
12232         } cursor[I915_MAX_PIPES];
12233
12234         struct intel_pipe_error_state {
12235                 bool power_domain_on;
12236                 u32 source;
12237                 u32 stat;
12238         } pipe[I915_MAX_PIPES];
12239
12240         struct intel_plane_error_state {
12241                 u32 control;
12242                 u32 stride;
12243                 u32 size;
12244                 u32 pos;
12245                 u32 addr;
12246                 u32 surface;
12247                 u32 tile_offset;
12248         } plane[I915_MAX_PIPES];
12249
12250         struct intel_transcoder_error_state {
12251                 bool power_domain_on;
12252                 enum transcoder cpu_transcoder;
12253
12254                 u32 conf;
12255
12256                 u32 htotal;
12257                 u32 hblank;
12258                 u32 hsync;
12259                 u32 vtotal;
12260                 u32 vblank;
12261                 u32 vsync;
12262         } transcoder[4];
12263 };
12264
12265 struct intel_display_error_state *
12266 intel_display_capture_error_state(struct drm_device *dev)
12267 {
12268         struct drm_i915_private *dev_priv = dev->dev_private;
12269         struct intel_display_error_state *error;
12270         int transcoders[] = {
12271                 TRANSCODER_A,
12272                 TRANSCODER_B,
12273                 TRANSCODER_C,
12274                 TRANSCODER_EDP,
12275         };
12276         int i;
12277
12278         if (INTEL_INFO(dev)->num_pipes == 0)
12279                 return NULL;
12280
12281         error = kzalloc(sizeof(*error), GFP_ATOMIC);
12282         if (error == NULL)
12283                 return NULL;
12284
12285         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
12286                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
12287
12288         for_each_pipe(i) {
12289                 error->pipe[i].power_domain_on =
12290                         intel_display_power_enabled_sw(dev_priv,
12291                                                        POWER_DOMAIN_PIPE(i));
12292                 if (!error->pipe[i].power_domain_on)
12293                         continue;
12294
12295                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
12296                         error->cursor[i].control = I915_READ(CURCNTR(i));
12297                         error->cursor[i].position = I915_READ(CURPOS(i));
12298                         error->cursor[i].base = I915_READ(CURBASE(i));
12299                 } else {
12300                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
12301                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
12302                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
12303                 }
12304
12305                 error->plane[i].control = I915_READ(DSPCNTR(i));
12306                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
12307                 if (INTEL_INFO(dev)->gen <= 3) {
12308                         error->plane[i].size = I915_READ(DSPSIZE(i));
12309                         error->plane[i].pos = I915_READ(DSPPOS(i));
12310                 }
12311                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
12312                         error->plane[i].addr = I915_READ(DSPADDR(i));
12313                 if (INTEL_INFO(dev)->gen >= 4) {
12314                         error->plane[i].surface = I915_READ(DSPSURF(i));
12315                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
12316                 }
12317
12318                 error->pipe[i].source = I915_READ(PIPESRC(i));
12319
12320                 if (!HAS_PCH_SPLIT(dev))
12321                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
12322         }
12323
12324         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
12325         if (HAS_DDI(dev_priv->dev))
12326                 error->num_transcoders++; /* Account for eDP. */
12327
12328         for (i = 0; i < error->num_transcoders; i++) {
12329                 enum transcoder cpu_transcoder = transcoders[i];
12330
12331                 error->transcoder[i].power_domain_on =
12332                         intel_display_power_enabled_sw(dev_priv,
12333                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
12334                 if (!error->transcoder[i].power_domain_on)
12335                         continue;
12336
12337                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
12338
12339                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
12340                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
12341                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
12342                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
12343                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
12344                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
12345                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
12346         }
12347
12348         return error;
12349 }
12350
12351 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
12352
12353 void
12354 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
12355                                 struct drm_device *dev,
12356                                 struct intel_display_error_state *error)
12357 {
12358         int i;
12359
12360         if (!error)
12361                 return;
12362
12363         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
12364         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
12365                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
12366                            error->power_well_driver);
12367         for_each_pipe(i) {
12368                 err_printf(m, "Pipe [%d]:\n", i);
12369                 err_printf(m, "  Power: %s\n",
12370                            error->pipe[i].power_domain_on ? "on" : "off");
12371                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
12372                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
12373
12374                 err_printf(m, "Plane [%d]:\n", i);
12375                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
12376                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
12377                 if (INTEL_INFO(dev)->gen <= 3) {
12378                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
12379                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
12380                 }
12381                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
12382                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
12383                 if (INTEL_INFO(dev)->gen >= 4) {
12384                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
12385                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
12386                 }
12387
12388                 err_printf(m, "Cursor [%d]:\n", i);
12389                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
12390                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
12391                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
12392         }
12393
12394         for (i = 0; i < error->num_transcoders; i++) {
12395                 err_printf(m, "CPU transcoder: %c\n",
12396                            transcoder_name(error->transcoder[i].cpu_transcoder));
12397                 err_printf(m, "  Power: %s\n",
12398                            error->transcoder[i].power_domain_on ? "on" : "off");
12399                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
12400                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
12401                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
12402                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
12403                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
12404                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
12405                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
12406         }
12407 }