drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_atomic.h>
  41 #include <drm/drm_atomic_helper.h>
  42 #include <drm/drm_dp_helper.h>
  43 #include <drm/drm_crtc_helper.h>
  44 #include <drm/drm_plane_helper.h>
  45 #include <drm/drm_rect.h>
  46 #include <linux/dma_remapping.h>
  47
  48 /* Primary plane formats for gen <= 3 */
  49 static const uint32_t i8xx_primary_formats[] = {
  50         DRM_FORMAT_C8,
  51         DRM_FORMAT_RGB565,
  52         DRM_FORMAT_XRGB1555,
  53         DRM_FORMAT_XRGB8888,
  54 };
  55
  56 /* Primary plane formats for gen >= 4 */
  57 static const uint32_t i965_primary_formats[] = {
  58         DRM_FORMAT_C8,
  59         DRM_FORMAT_RGB565,
  60         DRM_FORMAT_XRGB8888,
  61         DRM_FORMAT_XBGR8888,
  62         DRM_FORMAT_XRGB2101010,
  63         DRM_FORMAT_XBGR2101010,
  64 };
  65
  66 static const uint32_t skl_primary_formats[] = {
  67         DRM_FORMAT_C8,
  68         DRM_FORMAT_RGB565,
  69         DRM_FORMAT_XRGB8888,
  70         DRM_FORMAT_XBGR8888,
  71         DRM_FORMAT_ARGB8888,
  72         DRM_FORMAT_ABGR8888,
  73         DRM_FORMAT_XRGB2101010,
  74         DRM_FORMAT_XBGR2101010,
  75         DRM_FORMAT_YUYV,
  76         DRM_FORMAT_YVYU,
  77         DRM_FORMAT_UYVY,
  78         DRM_FORMAT_VYUY,
  79 };
  80
  81 /* Cursor formats */
  82 static const uint32_t intel_cursor_formats[] = {
  83         DRM_FORMAT_ARGB8888,
  84 };
  85
  86 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  87
  88 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  89                                 struct intel_crtc_state *pipe_config);
  90 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  91                                    struct intel_crtc_state *pipe_config);
  92
  93 static int intel_framebuffer_init(struct drm_device *dev,
  94                                   struct intel_framebuffer *ifb,
  95                                   struct drm_mode_fb_cmd2 *mode_cmd,
  96                                   struct drm_i915_gem_object *obj);
  97 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  98 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  99 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 100                                          struct intel_link_m_n *m_n,
 101                                          struct intel_link_m_n *m2_n2);
 102 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 103 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 104 static void intel_set_pipe_csc(struct drm_crtc *crtc);
 105 static void vlv_prepare_pll(struct intel_crtc *crtc,
 106                             const struct intel_crtc_state *pipe_config);
 107 static void chv_prepare_pll(struct intel_crtc *crtc,
 108                             const struct intel_crtc_state *pipe_config);
 109 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 110 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 111 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 112         struct intel_crtc_state *crtc_state);
 113 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
 114                            int num_connectors);
 115 static void skylake_pfit_enable(struct intel_crtc *crtc);
 116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 118 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 119
 120 typedef struct {
 121         int     min, max;
 122 } intel_range_t;
 123
 124 typedef struct {
 125         int     dot_limit;
 126         int     p2_slow, p2_fast;
 127 } intel_p2_t;
 128
 129 typedef struct intel_limit intel_limit_t;
 130 struct intel_limit {
 131         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 132         intel_p2_t          p2;
 133 };
 134
 135 int
 136 intel_pch_rawclk(struct drm_device *dev)
 137 {
 138         struct drm_i915_private *dev_priv = dev->dev_private;
 139
 140         WARN_ON(!HAS_PCH_SPLIT(dev));
 141
 142         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 143 }
 144
 145 /* hrawclock is 1/4 the FSB frequency */
 146 int intel_hrawclk(struct drm_device *dev)
 147 {
 148         struct drm_i915_private *dev_priv = dev->dev_private;
 149         uint32_t clkcfg;
 150
 151         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 152         if (IS_VALLEYVIEW(dev))
 153                 return 200;
 154
 155         clkcfg = I915_READ(CLKCFG);
 156         switch (clkcfg & CLKCFG_FSB_MASK) {
 157         case CLKCFG_FSB_400:
 158                 return 100;
 159         case CLKCFG_FSB_533:
 160                 return 133;
 161         case CLKCFG_FSB_667:
 162                 return 166;
 163         case CLKCFG_FSB_800:
 164                 return 200;
 165         case CLKCFG_FSB_1067:
 166                 return 266;
 167         case CLKCFG_FSB_1333:
 168                 return 333;
 169         /* these two are just a guess; one of them might be right */
 170         case CLKCFG_FSB_1600:
 171         case CLKCFG_FSB_1600_ALT:
 172                 return 400;
 173         default:
 174                 return 133;
 175         }
 176 }
 177
 178 static inline u32 /* units of 100MHz */
 179 intel_fdi_link_freq(struct drm_device *dev)
 180 {
 181         if (IS_GEN5(dev)) {
 182                 struct drm_i915_private *dev_priv = dev->dev_private;
 183                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 184         } else
 185                 return 27;
 186 }
 187
 188 static const intel_limit_t intel_limits_i8xx_dac = {
 189         .dot = { .min = 25000, .max = 350000 },
 190         .vco = { .min = 908000, .max = 1512000 },
 191         .n = { .min = 2, .max = 16 },
 192         .m = { .min = 96, .max = 140 },
 193         .m1 = { .min = 18, .max = 26 },
 194         .m2 = { .min = 6, .max = 16 },
 195         .p = { .min = 4, .max = 128 },
 196         .p1 = { .min = 2, .max = 33 },
 197         .p2 = { .dot_limit = 165000,
 198                 .p2_slow = 4, .p2_fast = 2 },
 199 };
 200
 201 static const intel_limit_t intel_limits_i8xx_dvo = {
 202         .dot = { .min = 25000, .max = 350000 },
 203         .vco = { .min = 908000, .max = 1512000 },
 204         .n = { .min = 2, .max = 16 },
 205         .m = { .min = 96, .max = 140 },
 206         .m1 = { .min = 18, .max = 26 },
 207         .m2 = { .min = 6, .max = 16 },
 208         .p = { .min = 4, .max = 128 },
 209         .p1 = { .min = 2, .max = 33 },
 210         .p2 = { .dot_limit = 165000,
 211                 .p2_slow = 4, .p2_fast = 4 },
 212 };
 213
 214 static const intel_limit_t intel_limits_i8xx_lvds = {
 215         .dot = { .min = 25000, .max = 350000 },
 216         .vco = { .min = 908000, .max = 1512000 },
 217         .n = { .min = 2, .max = 16 },
 218         .m = { .min = 96, .max = 140 },
 219         .m1 = { .min = 18, .max = 26 },
 220         .m2 = { .min = 6, .max = 16 },
 221         .p = { .min = 4, .max = 128 },
 222         .p1 = { .min = 1, .max = 6 },
 223         .p2 = { .dot_limit = 165000,
 224                 .p2_slow = 14, .p2_fast = 7 },
 225 };
 226
 227 static const intel_limit_t intel_limits_i9xx_sdvo = {
 228         .dot = { .min = 20000, .max = 400000 },
 229         .vco = { .min = 1400000, .max = 2800000 },
 230         .n = { .min = 1, .max = 6 },
 231         .m = { .min = 70, .max = 120 },
 232         .m1 = { .min = 8, .max = 18 },
 233         .m2 = { .min = 3, .max = 7 },
 234         .p = { .min = 5, .max = 80 },
 235         .p1 = { .min = 1, .max = 8 },
 236         .p2 = { .dot_limit = 200000,
 237                 .p2_slow = 10, .p2_fast = 5 },
 238 };
 239
 240 static const intel_limit_t intel_limits_i9xx_lvds = {
 241         .dot = { .min = 20000, .max = 400000 },
 242         .vco = { .min = 1400000, .max = 2800000 },
 243         .n = { .min = 1, .max = 6 },
 244         .m = { .min = 70, .max = 120 },
 245         .m1 = { .min = 8, .max = 18 },
 246         .m2 = { .min = 3, .max = 7 },
 247         .p = { .min = 7, .max = 98 },
 248         .p1 = { .min = 1, .max = 8 },
 249         .p2 = { .dot_limit = 112000,
 250                 .p2_slow = 14, .p2_fast = 7 },
 251 };
 252
 253
 254 static const intel_limit_t intel_limits_g4x_sdvo = {
 255         .dot = { .min = 25000, .max = 270000 },
 256         .vco = { .min = 1750000, .max = 3500000},
 257         .n = { .min = 1, .max = 4 },
 258         .m = { .min = 104, .max = 138 },
 259         .m1 = { .min = 17, .max = 23 },
 260         .m2 = { .min = 5, .max = 11 },
 261         .p = { .min = 10, .max = 30 },
 262         .p1 = { .min = 1, .max = 3},
 263         .p2 = { .dot_limit = 270000,
 264                 .p2_slow = 10,
 265                 .p2_fast = 10
 266         },
 267 };
 268
 269 static const intel_limit_t intel_limits_g4x_hdmi = {
 270         .dot = { .min = 22000, .max = 400000 },
 271         .vco = { .min = 1750000, .max = 3500000},
 272         .n = { .min = 1, .max = 4 },
 273         .m = { .min = 104, .max = 138 },
 274         .m1 = { .min = 16, .max = 23 },
 275         .m2 = { .min = 5, .max = 11 },
 276         .p = { .min = 5, .max = 80 },
 277         .p1 = { .min = 1, .max = 8},
 278         .p2 = { .dot_limit = 165000,
 279                 .p2_slow = 10, .p2_fast = 5 },
 280 };
 281
 282 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 283         .dot = { .min = 20000, .max = 115000 },
 284         .vco = { .min = 1750000, .max = 3500000 },
 285         .n = { .min = 1, .max = 3 },
 286         .m = { .min = 104, .max = 138 },
 287         .m1 = { .min = 17, .max = 23 },
 288         .m2 = { .min = 5, .max = 11 },
 289         .p = { .min = 28, .max = 112 },
 290         .p1 = { .min = 2, .max = 8 },
 291         .p2 = { .dot_limit = 0,
 292                 .p2_slow = 14, .p2_fast = 14
 293         },
 294 };
 295
 296 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 297         .dot = { .min = 80000, .max = 224000 },
 298         .vco = { .min = 1750000, .max = 3500000 },
 299         .n = { .min = 1, .max = 3 },
 300         .m = { .min = 104, .max = 138 },
 301         .m1 = { .min = 17, .max = 23 },
 302         .m2 = { .min = 5, .max = 11 },
 303         .p = { .min = 14, .max = 42 },
 304         .p1 = { .min = 2, .max = 6 },
 305         .p2 = { .dot_limit = 0,
 306                 .p2_slow = 7, .p2_fast = 7
 307         },
 308 };
 309
 310 static const intel_limit_t intel_limits_pineview_sdvo = {
 311         .dot = { .min = 20000, .max = 400000},
 312         .vco = { .min = 1700000, .max = 3500000 },
 313         /* Pineview's Ncounter is a ring counter */
 314         .n = { .min = 3, .max = 6 },
 315         .m = { .min = 2, .max = 256 },
 316         /* Pineview only has one combined m divider, which we treat as m2. */
 317         .m1 = { .min = 0, .max = 0 },
 318         .m2 = { .min = 0, .max = 254 },
 319         .p = { .min = 5, .max = 80 },
 320         .p1 = { .min = 1, .max = 8 },
 321         .p2 = { .dot_limit = 200000,
 322                 .p2_slow = 10, .p2_fast = 5 },
 323 };
 324
 325 static const intel_limit_t intel_limits_pineview_lvds = {
 326         .dot = { .min = 20000, .max = 400000 },
 327         .vco = { .min = 1700000, .max = 3500000 },
 328         .n = { .min = 3, .max = 6 },
 329         .m = { .min = 2, .max = 256 },
 330         .m1 = { .min = 0, .max = 0 },
 331         .m2 = { .min = 0, .max = 254 },
 332         .p = { .min = 7, .max = 112 },
 333         .p1 = { .min = 1, .max = 8 },
 334         .p2 = { .dot_limit = 112000,
 335                 .p2_slow = 14, .p2_fast = 14 },
 336 };
 337
 338 /* Ironlake / Sandybridge
 339  *
 340  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 341  * the range value for them is (actual_value - 2).
 342  */
 343 static const intel_limit_t intel_limits_ironlake_dac = {
 344         .dot = { .min = 25000, .max = 350000 },
 345         .vco = { .min = 1760000, .max = 3510000 },
 346         .n = { .min = 1, .max = 5 },
 347         .m = { .min = 79, .max = 127 },
 348         .m1 = { .min = 12, .max = 22 },
 349         .m2 = { .min = 5, .max = 9 },
 350         .p = { .min = 5, .max = 80 },
 351         .p1 = { .min = 1, .max = 8 },
 352         .p2 = { .dot_limit = 225000,
 353                 .p2_slow = 10, .p2_fast = 5 },
 354 };
 355
 356 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 357         .dot = { .min = 25000, .max = 350000 },
 358         .vco = { .min = 1760000, .max = 3510000 },
 359         .n = { .min = 1, .max = 3 },
 360         .m = { .min = 79, .max = 118 },
 361         .m1 = { .min = 12, .max = 22 },
 362         .m2 = { .min = 5, .max = 9 },
 363         .p = { .min = 28, .max = 112 },
 364         .p1 = { .min = 2, .max = 8 },
 365         .p2 = { .dot_limit = 225000,
 366                 .p2_slow = 14, .p2_fast = 14 },
 367 };
 368
 369 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 370         .dot = { .min = 25000, .max = 350000 },
 371         .vco = { .min = 1760000, .max = 3510000 },
 372         .n = { .min = 1, .max = 3 },
 373         .m = { .min = 79, .max = 127 },
 374         .m1 = { .min = 12, .max = 22 },
 375         .m2 = { .min = 5, .max = 9 },
 376         .p = { .min = 14, .max = 56 },
 377         .p1 = { .min = 2, .max = 8 },
 378         .p2 = { .dot_limit = 225000,
 379                 .p2_slow = 7, .p2_fast = 7 },
 380 };
 381
 382 /* LVDS 100mhz refclk limits. */
 383 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 384         .dot = { .min = 25000, .max = 350000 },
 385         .vco = { .min = 1760000, .max = 3510000 },
 386         .n = { .min = 1, .max = 2 },
 387         .m = { .min = 79, .max = 126 },
 388         .m1 = { .min = 12, .max = 22 },
 389         .m2 = { .min = 5, .max = 9 },
 390         .p = { .min = 28, .max = 112 },
 391         .p1 = { .min = 2, .max = 8 },
 392         .p2 = { .dot_limit = 225000,
 393                 .p2_slow = 14, .p2_fast = 14 },
 394 };
 395
 396 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 397         .dot = { .min = 25000, .max = 350000 },
 398         .vco = { .min = 1760000, .max = 3510000 },
 399         .n = { .min = 1, .max = 3 },
 400         .m = { .min = 79, .max = 126 },
 401         .m1 = { .min = 12, .max = 22 },
 402         .m2 = { .min = 5, .max = 9 },
 403         .p = { .min = 14, .max = 42 },
 404         .p1 = { .min = 2, .max = 6 },
 405         .p2 = { .dot_limit = 225000,
 406                 .p2_slow = 7, .p2_fast = 7 },
 407 };
 408
 409 static const intel_limit_t intel_limits_vlv = {
 410          /*
 411           * These are the data rate limits (measured in fast clocks)
 412           * since those are the strictest limits we have. The fast
 413           * clock and actual rate limits are more relaxed, so checking
 414           * them would make no difference.
 415           */
 416         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 417         .vco = { .min = 4000000, .max = 6000000 },
 418         .n = { .min = 1, .max = 7 },
 419         .m1 = { .min = 2, .max = 3 },
 420         .m2 = { .min = 11, .max = 156 },
 421         .p1 = { .min = 2, .max = 3 },
 422         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 423 };
 424
 425 static const intel_limit_t intel_limits_chv = {
 426         /*
 427          * These are the data rate limits (measured in fast clocks)
 428          * since those are the strictest limits we have.  The fast
 429          * clock and actual rate limits are more relaxed, so checking
 430          * them would make no difference.
 431          */
 432         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 433         .vco = { .min = 4800000, .max = 6480000 },
 434         .n = { .min = 1, .max = 1 },
 435         .m1 = { .min = 2, .max = 2 },
 436         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 437         .p1 = { .min = 2, .max = 4 },
 438         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 439 };
 440
 441 static const intel_limit_t intel_limits_bxt = {
 442         /* FIXME: find real dot limits */
 443         .dot = { .min = 0, .max = INT_MAX },
 444         .vco = { .min = 4800000, .max = 6700000 },
 445         .n = { .min = 1, .max = 1 },
 446         .m1 = { .min = 2, .max = 2 },
 447         /* FIXME: find real m2 limits */
 448         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 449         .p1 = { .min = 2, .max = 4 },
 450         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 451 };
 452
 453 static bool
 454 needs_modeset(struct drm_crtc_state *state)
 455 {
 456         return drm_atomic_crtc_needs_modeset(state);
 457 }
 458
 459 /**
 460  * Returns whether any output on the specified pipe is of the specified type
 461  */
 462 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 463 {
 464         struct drm_device *dev = crtc->base.dev;
 465         struct intel_encoder *encoder;
 466
 467         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 468                 if (encoder->type == type)
 469                         return true;
 470
 471         return false;
 472 }
 473
 474 /**
 475  * Returns whether any output on the specified pipe will have the specified
 476  * type after a staged modeset is complete, i.e., the same as
 477  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 478  * encoder->crtc.
 479  */
 480 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
 481                                       int type)
 482 {
 483         struct drm_atomic_state *state = crtc_state->base.state;
 484         struct drm_connector *connector;
 485         struct drm_connector_state *connector_state;
 486         struct intel_encoder *encoder;
 487         int i, num_connectors = 0;
 488
 489         for_each_connector_in_state(state, connector, connector_state, i) {
 490                 if (connector_state->crtc != crtc_state->base.crtc)
 491                         continue;
 492
 493                 num_connectors++;
 494
 495                 encoder = to_intel_encoder(connector_state->best_encoder);
 496                 if (encoder->type == type)
 497                         return true;
 498         }
 499
 500         WARN_ON(num_connectors == 0);
 501
 502         return false;
 503 }
 504
 505 static const intel_limit_t *
 506 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
 507 {
 508         struct drm_device *dev = crtc_state->base.crtc->dev;
 509         const intel_limit_t *limit;
 510
 511         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 512                 if (intel_is_dual_link_lvds(dev)) {
 513                         if (refclk == 100000)
 514                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 515                         else
 516                                 limit = &intel_limits_ironlake_dual_lvds;
 517                 } else {
 518                         if (refclk == 100000)
 519                                 limit = &intel_limits_ironlake_single_lvds_100m;
 520                         else
 521                                 limit = &intel_limits_ironlake_single_lvds;
 522                 }
 523         } else
 524                 limit = &intel_limits_ironlake_dac;
 525
 526         return limit;
 527 }
 528
 529 static const intel_limit_t *
 530 intel_g4x_limit(struct intel_crtc_state *crtc_state)
 531 {
 532         struct drm_device *dev = crtc_state->base.crtc->dev;
 533         const intel_limit_t *limit;
 534
 535         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 536                 if (intel_is_dual_link_lvds(dev))
 537                         limit = &intel_limits_g4x_dual_channel_lvds;
 538                 else
 539                         limit = &intel_limits_g4x_single_channel_lvds;
 540         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
 541                    intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
 542                 limit = &intel_limits_g4x_hdmi;
 543         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
 544                 limit = &intel_limits_g4x_sdvo;
 545         } else /* The option is for other outputs */
 546                 limit = &intel_limits_i9xx_sdvo;
 547
 548         return limit;
 549 }
 550
 551 static const intel_limit_t *
 552 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
 553 {
 554         struct drm_device *dev = crtc_state->base.crtc->dev;
 555         const intel_limit_t *limit;
 556
 557         if (IS_BROXTON(dev))
 558                 limit = &intel_limits_bxt;
 559         else if (HAS_PCH_SPLIT(dev))
 560                 limit = intel_ironlake_limit(crtc_state, refclk);
 561         else if (IS_G4X(dev)) {
 562                 limit = intel_g4x_limit(crtc_state);
 563         } else if (IS_PINEVIEW(dev)) {
 564                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 565                         limit = &intel_limits_pineview_lvds;
 566                 else
 567                         limit = &intel_limits_pineview_sdvo;
 568         } else if (IS_CHERRYVIEW(dev)) {
 569                 limit = &intel_limits_chv;
 570         } else if (IS_VALLEYVIEW(dev)) {
 571                 limit = &intel_limits_vlv;
 572         } else if (!IS_GEN2(dev)) {
 573                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 574                         limit = &intel_limits_i9xx_lvds;
 575                 else
 576                         limit = &intel_limits_i9xx_sdvo;
 577         } else {
 578                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 579                         limit = &intel_limits_i8xx_lvds;
 580                 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
 581                         limit = &intel_limits_i8xx_dvo;
 582                 else
 583                         limit = &intel_limits_i8xx_dac;
 584         }
 585         return limit;
 586 }
 587
 588 /*
 589  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 590  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 591  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 592  * The helpers' return value is the rate of the clock that is fed to the
 593  * display engine's pipe which can be the above fast dot clock rate or a
 594  * divided-down version of it.
 595  */
 596 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 597 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
 598 {
 599         clock->m = clock->m2 + 2;
 600         clock->p = clock->p1 * clock->p2;
 601         if (WARN_ON(clock->n == 0 || clock->p == 0))
 602                 return 0;
 603         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 604         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 605
 606         return clock->dot;
 607 }
 608
 609 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 610 {
 611         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 612 }
 613
 614 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
 615 {
 616         clock->m = i9xx_dpll_compute_m(clock);
 617         clock->p = clock->p1 * clock->p2;
 618         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 619                 return 0;
 620         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 621         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 622
 623         return clock->dot;
 624 }
 625
 626 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
 627 {
 628         clock->m = clock->m1 * clock->m2;
 629         clock->p = clock->p1 * clock->p2;
 630         if (WARN_ON(clock->n == 0 || clock->p == 0))
 631                 return 0;
 632         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 633         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 634
 635         return clock->dot / 5;
 636 }
 637
 638 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
 639 {
 640         clock->m = clock->m1 * clock->m2;
 641         clock->p = clock->p1 * clock->p2;
 642         if (WARN_ON(clock->n == 0 || clock->p == 0))
 643                 return 0;
 644         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 645                         clock->n << 22);
 646         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 647
 648         return clock->dot / 5;
 649 }
 650
 651 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 652 /**
 653  * Returns whether the given set of divisors are valid for a given refclk with
 654  * the given connectors.
 655  */
 656
 657 static bool intel_PLL_is_valid(struct drm_device *dev,
 658                                const intel_limit_t *limit,
 659                                const intel_clock_t *clock)
 660 {
 661         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 662                 INTELPllInvalid("n out of range\n");
 663         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 664                 INTELPllInvalid("p1 out of range\n");
 665         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 666                 INTELPllInvalid("m2 out of range\n");
 667         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 668                 INTELPllInvalid("m1 out of range\n");
 669
 670         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
 671                 if (clock->m1 <= clock->m2)
 672                         INTELPllInvalid("m1 <= m2\n");
 673
 674         if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
 675                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 676                         INTELPllInvalid("p out of range\n");
 677                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 678                         INTELPllInvalid("m out of range\n");
 679         }
 680
 681         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 682                 INTELPllInvalid("vco out of range\n");
 683         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 684          * connector, etc., rather than just a single range.
 685          */
 686         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 687                 INTELPllInvalid("dot out of range\n");
 688
 689         return true;
 690 }
 691
 692 static int
 693 i9xx_select_p2_div(const intel_limit_t *limit,
 694                    const struct intel_crtc_state *crtc_state,
 695                    int target)
 696 {
 697         struct drm_device *dev = crtc_state->base.crtc->dev;
 698
 699         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 700                 /*
 701                  * For LVDS just rely on its current settings for dual-channel.
 702                  * We haven't figured out how to reliably set up different
 703                  * single/dual channel state, if we even can.
 704                  */
 705                 if (intel_is_dual_link_lvds(dev))
 706                         return limit->p2.p2_fast;
 707                 else
 708                         return limit->p2.p2_slow;
 709         } else {
 710                 if (target < limit->p2.dot_limit)
 711                         return limit->p2.p2_slow;
 712                 else
 713                         return limit->p2.p2_fast;
 714         }
 715 }
 716
 717 static bool
 718 i9xx_find_best_dpll(const intel_limit_t *limit,
 719                     struct intel_crtc_state *crtc_state,
 720                     int target, int refclk, intel_clock_t *match_clock,
 721                     intel_clock_t *best_clock)
 722 {
 723         struct drm_device *dev = crtc_state->base.crtc->dev;
 724         intel_clock_t clock;
 725         int err = target;
 726
 727         memset(best_clock, 0, sizeof(*best_clock));
 728
 729         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 730
 731         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 732              clock.m1++) {
 733                 for (clock.m2 = limit->m2.min;
 734                      clock.m2 <= limit->m2.max; clock.m2++) {
 735                         if (clock.m2 >= clock.m1)
 736                                 break;
 737                         for (clock.n = limit->n.min;
 738                              clock.n <= limit->n.max; clock.n++) {
 739                                 for (clock.p1 = limit->p1.min;
 740                                         clock.p1 <= limit->p1.max; clock.p1++) {
 741                                         int this_err;
 742
 743                                         i9xx_calc_dpll_params(refclk, &clock);
 744                                         if (!intel_PLL_is_valid(dev, limit,
 745                                                                 &clock))
 746                                                 continue;
 747                                         if (match_clock &&
 748                                             clock.p != match_clock->p)
 749                                                 continue;
 750
 751                                         this_err = abs(clock.dot - target);
 752                                         if (this_err < err) {
 753                                                 *best_clock = clock;
 754                                                 err = this_err;
 755                                         }
 756                                 }
 757                         }
 758                 }
 759         }
 760
 761         return (err != target);
 762 }
 763
 764 static bool
 765 pnv_find_best_dpll(const intel_limit_t *limit,
 766                    struct intel_crtc_state *crtc_state,
 767                    int target, int refclk, intel_clock_t *match_clock,
 768                    intel_clock_t *best_clock)
 769 {
 770         struct drm_device *dev = crtc_state->base.crtc->dev;
 771         intel_clock_t clock;
 772         int err = target;
 773
 774         memset(best_clock, 0, sizeof(*best_clock));
 775
 776         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 777
 778         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 779              clock.m1++) {
 780                 for (clock.m2 = limit->m2.min;
 781                      clock.m2 <= limit->m2.max; clock.m2++) {
 782                         for (clock.n = limit->n.min;
 783                              clock.n <= limit->n.max; clock.n++) {
 784                                 for (clock.p1 = limit->p1.min;
 785                                         clock.p1 <= limit->p1.max; clock.p1++) {
 786                                         int this_err;
 787
 788                                         pnv_calc_dpll_params(refclk, &clock);
 789                                         if (!intel_PLL_is_valid(dev, limit,
 790                                                                 &clock))
 791                                                 continue;
 792                                         if (match_clock &&
 793                                             clock.p != match_clock->p)
 794                                                 continue;
 795
 796                                         this_err = abs(clock.dot - target);
 797                                         if (this_err < err) {
 798                                                 *best_clock = clock;
 799                                                 err = this_err;
 800                                         }
 801                                 }
 802                         }
 803                 }
 804         }
 805
 806         return (err != target);
 807 }
 808
 809 static bool
 810 g4x_find_best_dpll(const intel_limit_t *limit,
 811                    struct intel_crtc_state *crtc_state,
 812                    int target, int refclk, intel_clock_t *match_clock,
 813                    intel_clock_t *best_clock)
 814 {
 815         struct drm_device *dev = crtc_state->base.crtc->dev;
 816         intel_clock_t clock;
 817         int max_n;
 818         bool found = false;
 819         /* approximately equals target * 0.00585 */
 820         int err_most = (target >> 8) + (target >> 9);
 821
 822         memset(best_clock, 0, sizeof(*best_clock));
 823
 824         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 825
 826         max_n = limit->n.max;
 827         /* based on hardware requirement, prefer smaller n to precision */
 828         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 829                 /* based on hardware requirement, prefere larger m1,m2 */
 830                 for (clock.m1 = limit->m1.max;
 831                      clock.m1 >= limit->m1.min; clock.m1--) {
 832                         for (clock.m2 = limit->m2.max;
 833                              clock.m2 >= limit->m2.min; clock.m2--) {
 834                                 for (clock.p1 = limit->p1.max;
 835                                      clock.p1 >= limit->p1.min; clock.p1--) {
 836                                         int this_err;
 837
 838                                         i9xx_calc_dpll_params(refclk, &clock);
 839                                         if (!intel_PLL_is_valid(dev, limit,
 840                                                                 &clock))
 841                                                 continue;
 842
 843                                         this_err = abs(clock.dot - target);
 844                                         if (this_err < err_most) {
 845                                                 *best_clock = clock;
 846                                                 err_most = this_err;
 847                                                 max_n = clock.n;
 848                                                 found = true;
 849                                         }
 850                                 }
 851                         }
 852                 }
 853         }
 854         return found;
 855 }
 856
 857 /*
 858  * Check if the calculated PLL configuration is more optimal compared to the
 859  * best configuration and error found so far. Return the calculated error.
 860  */
 861 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 862                                const intel_clock_t *calculated_clock,
 863                                const intel_clock_t *best_clock,
 864                                unsigned int best_error_ppm,
 865                                unsigned int *error_ppm)
 866 {
 867         /*
 868          * For CHV ignore the error and consider only the P value.
 869          * Prefer a bigger P value based on HW requirements.
 870          */
 871         if (IS_CHERRYVIEW(dev)) {
 872                 *error_ppm = 0;
 873
 874                 return calculated_clock->p > best_clock->p;
 875         }
 876
 877         if (WARN_ON_ONCE(!target_freq))
 878                 return false;
 879
 880         *error_ppm = div_u64(1000000ULL *
 881                                 abs(target_freq - calculated_clock->dot),
 882                              target_freq);
 883         /*
 884          * Prefer a better P value over a better (smaller) error if the error
 885          * is small. Ensure this preference for future configurations too by
 886          * setting the error to 0.
 887          */
 888         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 889                 *error_ppm = 0;
 890
 891                 return true;
 892         }
 893
 894         return *error_ppm + 10 < best_error_ppm;
 895 }
 896
 897 static bool
 898 vlv_find_best_dpll(const intel_limit_t *limit,
 899                    struct intel_crtc_state *crtc_state,
 900                    int target, int refclk, intel_clock_t *match_clock,
 901                    intel_clock_t *best_clock)
 902 {
 903         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 904         struct drm_device *dev = crtc->base.dev;
 905         intel_clock_t clock;
 906         unsigned int bestppm = 1000000;
 907         /* min update 19.2 MHz */
 908         int max_n = min(limit->n.max, refclk / 19200);
 909         bool found = false;
 910
 911         target *= 5; /* fast clock */
 912
 913         memset(best_clock, 0, sizeof(*best_clock));
 914
 915         /* based on hardware requirement, prefer smaller n to precision */
 916         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 917                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 918                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 919                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 920                                 clock.p = clock.p1 * clock.p2;
 921                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 922                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 923                                         unsigned int ppm;
 924
 925                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 926                                                                      refclk * clock.m1);
 927
 928                                         vlv_calc_dpll_params(refclk, &clock);
 929
 930                                         if (!intel_PLL_is_valid(dev, limit,
 931                                                                 &clock))
 932                                                 continue;
 933
 934                                         if (!vlv_PLL_is_optimal(dev, target,
 935                                                                 &clock,
 936                                                                 best_clock,
 937                                                                 bestppm, &ppm))
 938                                                 continue;
 939
 940                                         *best_clock = clock;
 941                                         bestppm = ppm;
 942                                         found = true;
 943                                 }
 944                         }
 945                 }
 946         }
 947
 948         return found;
 949 }
 950
 951 static bool
 952 chv_find_best_dpll(const intel_limit_t *limit,
 953                    struct intel_crtc_state *crtc_state,
 954                    int target, int refclk, intel_clock_t *match_clock,
 955                    intel_clock_t *best_clock)
 956 {
 957         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 958         struct drm_device *dev = crtc->base.dev;
 959         unsigned int best_error_ppm;
 960         intel_clock_t clock;
 961         uint64_t m2;
 962         int found = false;
 963
 964         memset(best_clock, 0, sizeof(*best_clock));
 965         best_error_ppm = 1000000;
 966
 967         /*
 968          * Based on hardware doc, the n always set to 1, and m1 always
 969          * set to 2.  If requires to support 200Mhz refclk, we need to
 970          * revisit this because n may not 1 anymore.
 971          */
 972         clock.n = 1, clock.m1 = 2;
 973         target *= 5;    /* fast clock */
 974
 975         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 976                 for (clock.p2 = limit->p2.p2_fast;
 977                                 clock.p2 >= limit->p2.p2_slow;
 978                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 979                         unsigned int error_ppm;
 980
 981                         clock.p = clock.p1 * clock.p2;
 982
 983                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 984                                         clock.n) << 22, refclk * clock.m1);
 985
 986                         if (m2 > INT_MAX/clock.m1)
 987                                 continue;
 988
 989                         clock.m2 = m2;
 990
 991                         chv_calc_dpll_params(refclk, &clock);
 992
 993                         if (!intel_PLL_is_valid(dev, limit, &clock))
 994                                 continue;
 995
 996                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 997                                                 best_error_ppm, &error_ppm))
 998                                 continue;
 999
1000                         *best_clock = clock;
1001                         best_error_ppm = error_ppm;
1002                         found = true;
1003                 }
1004         }
1005
1006         return found;
1007 }
1008
1009 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1010                         intel_clock_t *best_clock)
1011 {
1012         int refclk = i9xx_get_refclk(crtc_state, 0);
1013
1014         return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1015                                   target_clock, refclk, NULL, best_clock);
1016 }
1017
1018 bool intel_crtc_active(struct drm_crtc *crtc)
1019 {
1020         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1021
1022         /* Be paranoid as we can arrive here with only partial
1023          * state retrieved from the hardware during setup.
1024          *
1025          * We can ditch the adjusted_mode.crtc_clock check as soon
1026          * as Haswell has gained clock readout/fastboot support.
1027          *
1028          * We can ditch the crtc->primary->fb check as soon as we can
1029          * properly reconstruct framebuffers.
1030          *
1031          * FIXME: The intel_crtc->active here should be switched to
1032          * crtc->state->active once we have proper CRTC states wired up
1033          * for atomic.
1034          */
1035         return intel_crtc->active && crtc->primary->state->fb &&
1036                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1037 }
1038
1039 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1040                                              enum pipe pipe)
1041 {
1042         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1043         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1044
1045         return intel_crtc->config->cpu_transcoder;
1046 }
1047
1048 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1049 {
1050         struct drm_i915_private *dev_priv = dev->dev_private;
1051         u32 reg = PIPEDSL(pipe);
1052         u32 line1, line2;
1053         u32 line_mask;
1054
1055         if (IS_GEN2(dev))
1056                 line_mask = DSL_LINEMASK_GEN2;
1057         else
1058                 line_mask = DSL_LINEMASK_GEN3;
1059
1060         line1 = I915_READ(reg) & line_mask;
1061         msleep(5);
1062         line2 = I915_READ(reg) & line_mask;
1063
1064         return line1 == line2;
1065 }
1066
1067 /*
1068  * intel_wait_for_pipe_off - wait for pipe to turn off
1069  * @crtc: crtc whose pipe to wait for
1070  *
1071  * After disabling a pipe, we can't wait for vblank in the usual way,
1072  * spinning on the vblank interrupt status bit, since we won't actually
1073  * see an interrupt when the pipe is disabled.
1074  *
1075  * On Gen4 and above:
1076  *   wait for the pipe register state bit to turn off
1077  *
1078  * Otherwise:
1079  *   wait for the display line value to settle (it usually
1080  *   ends up stopping at the start of the next frame).
1081  *
1082  */
1083 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1084 {
1085         struct drm_device *dev = crtc->base.dev;
1086         struct drm_i915_private *dev_priv = dev->dev_private;
1087         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1088         enum pipe pipe = crtc->pipe;
1089
1090         if (INTEL_INFO(dev)->gen >= 4) {
1091                 int reg = PIPECONF(cpu_transcoder);
1092
1093                 /* Wait for the Pipe State to go off */
1094                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1095                              100))
1096                         WARN(1, "pipe_off wait timed out\n");
1097         } else {
1098                 /* Wait for the display line to settle */
1099                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1100                         WARN(1, "pipe_off wait timed out\n");
1101         }
1102 }
1103
1104 static const char *state_string(bool enabled)
1105 {
1106         return enabled ? "on" : "off";
1107 }
1108
1109 /* Only for pre-ILK configs */
1110 void assert_pll(struct drm_i915_private *dev_priv,
1111                 enum pipe pipe, bool state)
1112 {
1113         int reg;
1114         u32 val;
1115         bool cur_state;
1116
1117         reg = DPLL(pipe);
1118         val = I915_READ(reg);
1119         cur_state = !!(val & DPLL_VCO_ENABLE);
1120         I915_STATE_WARN(cur_state != state,
1121              "PLL state assertion failure (expected %s, current %s)\n",
1122              state_string(state), state_string(cur_state));
1123 }
1124
1125 /* XXX: the dsi pll is shared between MIPI DSI ports */
1126 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1127 {
1128         u32 val;
1129         bool cur_state;
1130
1131         mutex_lock(&dev_priv->sb_lock);
1132         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1133         mutex_unlock(&dev_priv->sb_lock);
1134
1135         cur_state = val & DSI_PLL_VCO_EN;
1136         I915_STATE_WARN(cur_state != state,
1137              "DSI PLL state assertion failure (expected %s, current %s)\n",
1138              state_string(state), state_string(cur_state));
1139 }
1140 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1141 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1142
1143 struct intel_shared_dpll *
1144 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1145 {
1146         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1147
1148         if (crtc->config->shared_dpll < 0)
1149                 return NULL;
1150
1151         return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1152 }
1153
1154 /* For ILK+ */
1155 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1156                         struct intel_shared_dpll *pll,
1157                         bool state)
1158 {
1159         bool cur_state;
1160         struct intel_dpll_hw_state hw_state;
1161
1162         if (WARN (!pll,
1163                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1164                 return;
1165
1166         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1167         I915_STATE_WARN(cur_state != state,
1168              "%s assertion failure (expected %s, current %s)\n",
1169              pll->name, state_string(state), state_string(cur_state));
1170 }
1171
1172 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1173                           enum pipe pipe, bool state)
1174 {
1175         int reg;
1176         u32 val;
1177         bool cur_state;
1178         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1179                                                                       pipe);
1180
1181         if (HAS_DDI(dev_priv->dev)) {
1182                 /* DDI does not have a specific FDI_TX register */
1183                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1184                 val = I915_READ(reg);
1185                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1186         } else {
1187                 reg = FDI_TX_CTL(pipe);
1188                 val = I915_READ(reg);
1189                 cur_state = !!(val & FDI_TX_ENABLE);
1190         }
1191         I915_STATE_WARN(cur_state != state,
1192              "FDI TX state assertion failure (expected %s, current %s)\n",
1193              state_string(state), state_string(cur_state));
1194 }
1195 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1196 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1197
1198 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1199                           enum pipe pipe, bool state)
1200 {
1201         int reg;
1202         u32 val;
1203         bool cur_state;
1204
1205         reg = FDI_RX_CTL(pipe);
1206         val = I915_READ(reg);
1207         cur_state = !!(val & FDI_RX_ENABLE);
1208         I915_STATE_WARN(cur_state != state,
1209              "FDI RX state assertion failure (expected %s, current %s)\n",
1210              state_string(state), state_string(cur_state));
1211 }
1212 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1213 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1214
1215 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1216                                       enum pipe pipe)
1217 {
1218         int reg;
1219         u32 val;
1220
1221         /* ILK FDI PLL is always enabled */
1222         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1223                 return;
1224
1225         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1226         if (HAS_DDI(dev_priv->dev))
1227                 return;
1228
1229         reg = FDI_TX_CTL(pipe);
1230         val = I915_READ(reg);
1231         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1232 }
1233
1234 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1235                        enum pipe pipe, bool state)
1236 {
1237         int reg;
1238         u32 val;
1239         bool cur_state;
1240
1241         reg = FDI_RX_CTL(pipe);
1242         val = I915_READ(reg);
1243         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1244         I915_STATE_WARN(cur_state != state,
1245              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1246              state_string(state), state_string(cur_state));
1247 }
1248
1249 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1250                            enum pipe pipe)
1251 {
1252         struct drm_device *dev = dev_priv->dev;
1253         int pp_reg;
1254         u32 val;
1255         enum pipe panel_pipe = PIPE_A;
1256         bool locked = true;
1257
1258         if (WARN_ON(HAS_DDI(dev)))
1259                 return;
1260
1261         if (HAS_PCH_SPLIT(dev)) {
1262                 u32 port_sel;
1263
1264                 pp_reg = PCH_PP_CONTROL;
1265                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1266
1267                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1268                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1269                         panel_pipe = PIPE_B;
1270                 /* XXX: else fix for eDP */
1271         } else if (IS_VALLEYVIEW(dev)) {
1272                 /* presumably write lock depends on pipe, not port select */
1273                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1274                 panel_pipe = pipe;
1275         } else {
1276                 pp_reg = PP_CONTROL;
1277                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1278                         panel_pipe = PIPE_B;
1279         }
1280
1281         val = I915_READ(pp_reg);
1282         if (!(val & PANEL_POWER_ON) ||
1283             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1284                 locked = false;
1285
1286         I915_STATE_WARN(panel_pipe == pipe && locked,
1287              "panel assertion failure, pipe %c regs locked\n",
1288              pipe_name(pipe));
1289 }
1290
1291 static void assert_cursor(struct drm_i915_private *dev_priv,
1292                           enum pipe pipe, bool state)
1293 {
1294         struct drm_device *dev = dev_priv->dev;
1295         bool cur_state;
1296
1297         if (IS_845G(dev) || IS_I865G(dev))
1298                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1299         else
1300                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1301
1302         I915_STATE_WARN(cur_state != state,
1303              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1304              pipe_name(pipe), state_string(state), state_string(cur_state));
1305 }
1306 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1307 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1308
1309 void assert_pipe(struct drm_i915_private *dev_priv,
1310                  enum pipe pipe, bool state)
1311 {
1312         int reg;
1313         u32 val;
1314         bool cur_state;
1315         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1316                                                                       pipe);
1317
1318         /* if we need the pipe quirk it must be always on */
1319         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1320             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1321                 state = true;
1322
1323         if (!intel_display_power_is_enabled(dev_priv,
1324                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1325                 cur_state = false;
1326         } else {
1327                 reg = PIPECONF(cpu_transcoder);
1328                 val = I915_READ(reg);
1329                 cur_state = !!(val & PIPECONF_ENABLE);
1330         }
1331
1332         I915_STATE_WARN(cur_state != state,
1333              "pipe %c assertion failure (expected %s, current %s)\n",
1334              pipe_name(pipe), state_string(state), state_string(cur_state));
1335 }
1336
1337 static void assert_plane(struct drm_i915_private *dev_priv,
1338                          enum plane plane, bool state)
1339 {
1340         int reg;
1341         u32 val;
1342         bool cur_state;
1343
1344         reg = DSPCNTR(plane);
1345         val = I915_READ(reg);
1346         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1347         I915_STATE_WARN(cur_state != state,
1348              "plane %c assertion failure (expected %s, current %s)\n",
1349              plane_name(plane), state_string(state), state_string(cur_state));
1350 }
1351
1352 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1353 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1354
1355 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1356                                    enum pipe pipe)
1357 {
1358         struct drm_device *dev = dev_priv->dev;
1359         int reg, i;
1360         u32 val;
1361         int cur_pipe;
1362
1363         /* Primary planes are fixed to pipes on gen4+ */
1364         if (INTEL_INFO(dev)->gen >= 4) {
1365                 reg = DSPCNTR(pipe);
1366                 val = I915_READ(reg);
1367                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1368                      "plane %c assertion failure, should be disabled but not\n",
1369                      plane_name(pipe));
1370                 return;
1371         }
1372
1373         /* Need to check both planes against the pipe */
1374         for_each_pipe(dev_priv, i) {
1375                 reg = DSPCNTR(i);
1376                 val = I915_READ(reg);
1377                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1378                         DISPPLANE_SEL_PIPE_SHIFT;
1379                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1380                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1381                      plane_name(i), pipe_name(pipe));
1382         }
1383 }
1384
1385 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1386                                     enum pipe pipe)
1387 {
1388         struct drm_device *dev = dev_priv->dev;
1389         int reg, sprite;
1390         u32 val;
1391
1392         if (INTEL_INFO(dev)->gen >= 9) {
1393                 for_each_sprite(dev_priv, pipe, sprite) {
1394                         val = I915_READ(PLANE_CTL(pipe, sprite));
1395                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1396                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1397                              sprite, pipe_name(pipe));
1398                 }
1399         } else if (IS_VALLEYVIEW(dev)) {
1400                 for_each_sprite(dev_priv, pipe, sprite) {
1401                         reg = SPCNTR(pipe, sprite);
1402                         val = I915_READ(reg);
1403                         I915_STATE_WARN(val & SP_ENABLE,
1404                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1405                              sprite_name(pipe, sprite), pipe_name(pipe));
1406                 }
1407         } else if (INTEL_INFO(dev)->gen >= 7) {
1408                 reg = SPRCTL(pipe);
1409                 val = I915_READ(reg);
1410                 I915_STATE_WARN(val & SPRITE_ENABLE,
1411                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1412                      plane_name(pipe), pipe_name(pipe));
1413         } else if (INTEL_INFO(dev)->gen >= 5) {
1414                 reg = DVSCNTR(pipe);
1415                 val = I915_READ(reg);
1416                 I915_STATE_WARN(val & DVS_ENABLE,
1417                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1418                      plane_name(pipe), pipe_name(pipe));
1419         }
1420 }
1421
1422 static void assert_vblank_disabled(struct drm_crtc *crtc)
1423 {
1424         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1425                 drm_crtc_vblank_put(crtc);
1426 }
1427
1428 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1429 {
1430         u32 val;
1431         bool enabled;
1432
1433         I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1434
1435         val = I915_READ(PCH_DREF_CONTROL);
1436         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1437                             DREF_SUPERSPREAD_SOURCE_MASK));
1438         I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1439 }
1440
1441 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1442                                            enum pipe pipe)
1443 {
1444         int reg;
1445         u32 val;
1446         bool enabled;
1447
1448         reg = PCH_TRANSCONF(pipe);
1449         val = I915_READ(reg);
1450         enabled = !!(val & TRANS_ENABLE);
1451         I915_STATE_WARN(enabled,
1452              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1453              pipe_name(pipe));
1454 }
1455
1456 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1457                             enum pipe pipe, u32 port_sel, u32 val)
1458 {
1459         if ((val & DP_PORT_EN) == 0)
1460                 return false;
1461
1462         if (HAS_PCH_CPT(dev_priv->dev)) {
1463                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1464                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1465                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1466                         return false;
1467         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1468                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1469                         return false;
1470         } else {
1471                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1472                         return false;
1473         }
1474         return true;
1475 }
1476
1477 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1478                               enum pipe pipe, u32 val)
1479 {
1480         if ((val & SDVO_ENABLE) == 0)
1481                 return false;
1482
1483         if (HAS_PCH_CPT(dev_priv->dev)) {
1484                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1485                         return false;
1486         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1487                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1488                         return false;
1489         } else {
1490                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1491                         return false;
1492         }
1493         return true;
1494 }
1495
1496 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1497                               enum pipe pipe, u32 val)
1498 {
1499         if ((val & LVDS_PORT_EN) == 0)
1500                 return false;
1501
1502         if (HAS_PCH_CPT(dev_priv->dev)) {
1503                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1504                         return false;
1505         } else {
1506                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1507                         return false;
1508         }
1509         return true;
1510 }
1511
1512 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1513                               enum pipe pipe, u32 val)
1514 {
1515         if ((val & ADPA_DAC_ENABLE) == 0)
1516                 return false;
1517         if (HAS_PCH_CPT(dev_priv->dev)) {
1518                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1519                         return false;
1520         } else {
1521                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1522                         return false;
1523         }
1524         return true;
1525 }
1526
1527 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1528                                    enum pipe pipe, int reg, u32 port_sel)
1529 {
1530         u32 val = I915_READ(reg);
1531         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1532              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1533              reg, pipe_name(pipe));
1534
1535         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1536              && (val & DP_PIPEB_SELECT),
1537              "IBX PCH dp port still using transcoder B\n");
1538 }
1539
1540 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1541                                      enum pipe pipe, int reg)
1542 {
1543         u32 val = I915_READ(reg);
1544         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1545              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1546              reg, pipe_name(pipe));
1547
1548         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1549              && (val & SDVO_PIPE_B_SELECT),
1550              "IBX PCH hdmi port still using transcoder B\n");
1551 }
1552
1553 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1554                                       enum pipe pipe)
1555 {
1556         int reg;
1557         u32 val;
1558
1559         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1560         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1561         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1562
1563         reg = PCH_ADPA;
1564         val = I915_READ(reg);
1565         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1566              "PCH VGA enabled on transcoder %c, should be disabled\n",
1567              pipe_name(pipe));
1568
1569         reg = PCH_LVDS;
1570         val = I915_READ(reg);
1571         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1572              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1573              pipe_name(pipe));
1574
1575         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1576         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1577         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1578 }
1579
1580 static void vlv_enable_pll(struct intel_crtc *crtc,
1581                            const struct intel_crtc_state *pipe_config)
1582 {
1583         struct drm_device *dev = crtc->base.dev;
1584         struct drm_i915_private *dev_priv = dev->dev_private;
1585         int reg = DPLL(crtc->pipe);
1586         u32 dpll = pipe_config->dpll_hw_state.dpll;
1587
1588         assert_pipe_disabled(dev_priv, crtc->pipe);
1589
1590         /* No really, not for ILK+ */
1591         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1592
1593         /* PLL is protected by panel, make sure we can write it */
1594         if (IS_MOBILE(dev_priv->dev))
1595                 assert_panel_unlocked(dev_priv, crtc->pipe);
1596
1597         I915_WRITE(reg, dpll);
1598         POSTING_READ(reg);
1599         udelay(150);
1600
1601         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1602                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1603
1604         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1605         POSTING_READ(DPLL_MD(crtc->pipe));
1606
1607         /* We do this three times for luck */
1608         I915_WRITE(reg, dpll);
1609         POSTING_READ(reg);
1610         udelay(150); /* wait for warmup */
1611         I915_WRITE(reg, dpll);
1612         POSTING_READ(reg);
1613         udelay(150); /* wait for warmup */
1614         I915_WRITE(reg, dpll);
1615         POSTING_READ(reg);
1616         udelay(150); /* wait for warmup */
1617 }
1618
1619 static void chv_enable_pll(struct intel_crtc *crtc,
1620                            const struct intel_crtc_state *pipe_config)
1621 {
1622         struct drm_device *dev = crtc->base.dev;
1623         struct drm_i915_private *dev_priv = dev->dev_private;
1624         int pipe = crtc->pipe;
1625         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1626         u32 tmp;
1627
1628         assert_pipe_disabled(dev_priv, crtc->pipe);
1629
1630         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1631
1632         mutex_lock(&dev_priv->sb_lock);
1633
1634         /* Enable back the 10bit clock to display controller */
1635         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1636         tmp |= DPIO_DCLKP_EN;
1637         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1638
1639         mutex_unlock(&dev_priv->sb_lock);
1640
1641         /*
1642          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1643          */
1644         udelay(1);
1645
1646         /* Enable PLL */
1647         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1648
1649         /* Check PLL is locked */
1650         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1651                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1652
1653         /* not sure when this should be written */
1654         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1655         POSTING_READ(DPLL_MD(pipe));
1656 }
1657
1658 static int intel_num_dvo_pipes(struct drm_device *dev)
1659 {
1660         struct intel_crtc *crtc;
1661         int count = 0;
1662
1663         for_each_intel_crtc(dev, crtc)
1664                 count += crtc->base.state->active &&
1665                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1666
1667         return count;
1668 }
1669
1670 static void i9xx_enable_pll(struct intel_crtc *crtc)
1671 {
1672         struct drm_device *dev = crtc->base.dev;
1673         struct drm_i915_private *dev_priv = dev->dev_private;
1674         int reg = DPLL(crtc->pipe);
1675         u32 dpll = crtc->config->dpll_hw_state.dpll;
1676
1677         assert_pipe_disabled(dev_priv, crtc->pipe);
1678
1679         /* No really, not for ILK+ */
1680         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1681
1682         /* PLL is protected by panel, make sure we can write it */
1683         if (IS_MOBILE(dev) && !IS_I830(dev))
1684                 assert_panel_unlocked(dev_priv, crtc->pipe);
1685
1686         /* Enable DVO 2x clock on both PLLs if necessary */
1687         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1688                 /*
1689                  * It appears to be important that we don't enable this
1690                  * for the current pipe before otherwise configuring the
1691                  * PLL. No idea how this should be handled if multiple
1692                  * DVO outputs are enabled simultaneosly.
1693                  */
1694                 dpll |= DPLL_DVO_2X_MODE;
1695                 I915_WRITE(DPLL(!crtc->pipe),
1696                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1697         }
1698
1699         /* Wait for the clocks to stabilize. */
1700         POSTING_READ(reg);
1701         udelay(150);
1702
1703         if (INTEL_INFO(dev)->gen >= 4) {
1704                 I915_WRITE(DPLL_MD(crtc->pipe),
1705                            crtc->config->dpll_hw_state.dpll_md);
1706         } else {
1707                 /* The pixel multiplier can only be updated once the
1708                  * DPLL is enabled and the clocks are stable.
1709                  *
1710                  * So write it again.
1711                  */
1712                 I915_WRITE(reg, dpll);
1713         }
1714
1715         /* We do this three times for luck */
1716         I915_WRITE(reg, dpll);
1717         POSTING_READ(reg);
1718         udelay(150); /* wait for warmup */
1719         I915_WRITE(reg, dpll);
1720         POSTING_READ(reg);
1721         udelay(150); /* wait for warmup */
1722         I915_WRITE(reg, dpll);
1723         POSTING_READ(reg);
1724         udelay(150); /* wait for warmup */
1725 }
1726
1727 /**
1728  * i9xx_disable_pll - disable a PLL
1729  * @dev_priv: i915 private structure
1730  * @pipe: pipe PLL to disable
1731  *
1732  * Disable the PLL for @pipe, making sure the pipe is off first.
1733  *
1734  * Note!  This is for pre-ILK only.
1735  */
1736 static void i9xx_disable_pll(struct intel_crtc *crtc)
1737 {
1738         struct drm_device *dev = crtc->base.dev;
1739         struct drm_i915_private *dev_priv = dev->dev_private;
1740         enum pipe pipe = crtc->pipe;
1741
1742         /* Disable DVO 2x clock on both PLLs if necessary */
1743         if (IS_I830(dev) &&
1744             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1745             !intel_num_dvo_pipes(dev)) {
1746                 I915_WRITE(DPLL(PIPE_B),
1747                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1748                 I915_WRITE(DPLL(PIPE_A),
1749                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1750         }
1751
1752         /* Don't disable pipe or pipe PLLs if needed */
1753         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1754             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1755                 return;
1756
1757         /* Make sure the pipe isn't still relying on us */
1758         assert_pipe_disabled(dev_priv, pipe);
1759
1760         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1761         POSTING_READ(DPLL(pipe));
1762 }
1763
1764 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1765 {
1766         u32 val;
1767
1768         /* Make sure the pipe isn't still relying on us */
1769         assert_pipe_disabled(dev_priv, pipe);
1770
1771         /*
1772          * Leave integrated clock source and reference clock enabled for pipe B.
1773          * The latter is needed for VGA hotplug / manual detection.
1774          */
1775         val = DPLL_VGA_MODE_DIS;
1776         if (pipe == PIPE_B)
1777                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1778         I915_WRITE(DPLL(pipe), val);
1779         POSTING_READ(DPLL(pipe));
1780
1781 }
1782
1783 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1784 {
1785         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1786         u32 val;
1787
1788         /* Make sure the pipe isn't still relying on us */
1789         assert_pipe_disabled(dev_priv, pipe);
1790
1791         /* Set PLL en = 0 */
1792         val = DPLL_SSC_REF_CLK_CHV |
1793                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1794         if (pipe != PIPE_A)
1795                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1796         I915_WRITE(DPLL(pipe), val);
1797         POSTING_READ(DPLL(pipe));
1798
1799         mutex_lock(&dev_priv->sb_lock);
1800
1801         /* Disable 10bit clock to display controller */
1802         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1803         val &= ~DPIO_DCLKP_EN;
1804         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1805
1806         mutex_unlock(&dev_priv->sb_lock);
1807 }
1808
1809 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1810                          struct intel_digital_port *dport,
1811                          unsigned int expected_mask)
1812 {
1813         u32 port_mask;
1814         int dpll_reg;
1815
1816         switch (dport->port) {
1817         case PORT_B:
1818                 port_mask = DPLL_PORTB_READY_MASK;
1819                 dpll_reg = DPLL(0);
1820                 break;
1821         case PORT_C:
1822                 port_mask = DPLL_PORTC_READY_MASK;
1823                 dpll_reg = DPLL(0);
1824                 expected_mask <<= 4;
1825                 break;
1826         case PORT_D:
1827                 port_mask = DPLL_PORTD_READY_MASK;
1828                 dpll_reg = DPIO_PHY_STATUS;
1829                 break;
1830         default:
1831                 BUG();
1832         }
1833
1834         if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1835                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1836                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1837 }
1838
1839 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1840 {
1841         struct drm_device *dev = crtc->base.dev;
1842         struct drm_i915_private *dev_priv = dev->dev_private;
1843         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1844
1845         if (WARN_ON(pll == NULL))
1846                 return;
1847
1848         WARN_ON(!pll->config.crtc_mask);
1849         if (pll->active == 0) {
1850                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1851                 WARN_ON(pll->on);
1852                 assert_shared_dpll_disabled(dev_priv, pll);
1853
1854                 pll->mode_set(dev_priv, pll);
1855         }
1856 }
1857
1858 /**
1859  * intel_enable_shared_dpll - enable PCH PLL
1860  * @dev_priv: i915 private structure
1861  * @pipe: pipe PLL to enable
1862  *
1863  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1864  * drives the transcoder clock.
1865  */
1866 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1867 {
1868         struct drm_device *dev = crtc->base.dev;
1869         struct drm_i915_private *dev_priv = dev->dev_private;
1870         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1871
1872         if (WARN_ON(pll == NULL))
1873                 return;
1874
1875         if (WARN_ON(pll->config.crtc_mask == 0))
1876                 return;
1877
1878         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1879                       pll->name, pll->active, pll->on,
1880                       crtc->base.base.id);
1881
1882         if (pll->active++) {
1883                 WARN_ON(!pll->on);
1884                 assert_shared_dpll_enabled(dev_priv, pll);
1885                 return;
1886         }
1887         WARN_ON(pll->on);
1888
1889         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1890
1891         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1892         pll->enable(dev_priv, pll);
1893         pll->on = true;
1894 }
1895
1896 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1897 {
1898         struct drm_device *dev = crtc->base.dev;
1899         struct drm_i915_private *dev_priv = dev->dev_private;
1900         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1901
1902         /* PCH only available on ILK+ */
1903         if (INTEL_INFO(dev)->gen < 5)
1904                 return;
1905
1906         if (pll == NULL)
1907                 return;
1908
1909         if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1910                 return;
1911
1912         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1913                       pll->name, pll->active, pll->on,
1914                       crtc->base.base.id);
1915
1916         if (WARN_ON(pll->active == 0)) {
1917                 assert_shared_dpll_disabled(dev_priv, pll);
1918                 return;
1919         }
1920
1921         assert_shared_dpll_enabled(dev_priv, pll);
1922         WARN_ON(!pll->on);
1923         if (--pll->active)
1924                 return;
1925
1926         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1927         pll->disable(dev_priv, pll);
1928         pll->on = false;
1929
1930         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1931 }
1932
1933 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1934                                            enum pipe pipe)
1935 {
1936         struct drm_device *dev = dev_priv->dev;
1937         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1938         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1939         uint32_t reg, val, pipeconf_val;
1940
1941         /* PCH only available on ILK+ */
1942         BUG_ON(!HAS_PCH_SPLIT(dev));
1943
1944         /* Make sure PCH DPLL is enabled */
1945         assert_shared_dpll_enabled(dev_priv,
1946                                    intel_crtc_to_shared_dpll(intel_crtc));
1947
1948         /* FDI must be feeding us bits for PCH ports */
1949         assert_fdi_tx_enabled(dev_priv, pipe);
1950         assert_fdi_rx_enabled(dev_priv, pipe);
1951
1952         if (HAS_PCH_CPT(dev)) {
1953                 /* Workaround: Set the timing override bit before enabling the
1954                  * pch transcoder. */
1955                 reg = TRANS_CHICKEN2(pipe);
1956                 val = I915_READ(reg);
1957                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1958                 I915_WRITE(reg, val);
1959         }
1960
1961         reg = PCH_TRANSCONF(pipe);
1962         val = I915_READ(reg);
1963         pipeconf_val = I915_READ(PIPECONF(pipe));
1964
1965         if (HAS_PCH_IBX(dev_priv->dev)) {
1966                 /*
1967                  * Make the BPC in transcoder be consistent with
1968                  * that in pipeconf reg. For HDMI we must use 8bpc
1969                  * here for both 8bpc and 12bpc.
1970                  */
1971                 val &= ~PIPECONF_BPC_MASK;
1972                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1973                         val |= PIPECONF_8BPC;
1974                 else
1975                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1976         }
1977
1978         val &= ~TRANS_INTERLACE_MASK;
1979         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1980                 if (HAS_PCH_IBX(dev_priv->dev) &&
1981                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1982                         val |= TRANS_LEGACY_INTERLACED_ILK;
1983                 else
1984                         val |= TRANS_INTERLACED;
1985         else
1986                 val |= TRANS_PROGRESSIVE;
1987
1988         I915_WRITE(reg, val | TRANS_ENABLE);
1989         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1990                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1991 }
1992
1993 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1994                                       enum transcoder cpu_transcoder)
1995 {
1996         u32 val, pipeconf_val;
1997
1998         /* PCH only available on ILK+ */
1999         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2000
2001         /* FDI must be feeding us bits for PCH ports */
2002         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2003         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2004
2005         /* Workaround: set timing override bit. */
2006         val = I915_READ(_TRANSA_CHICKEN2);
2007         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2008         I915_WRITE(_TRANSA_CHICKEN2, val);
2009
2010         val = TRANS_ENABLE;
2011         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2012
2013         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2014             PIPECONF_INTERLACED_ILK)
2015                 val |= TRANS_INTERLACED;
2016         else
2017                 val |= TRANS_PROGRESSIVE;
2018
2019         I915_WRITE(LPT_TRANSCONF, val);
2020         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2021                 DRM_ERROR("Failed to enable PCH transcoder\n");
2022 }
2023
2024 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2025                                             enum pipe pipe)
2026 {
2027         struct drm_device *dev = dev_priv->dev;
2028         uint32_t reg, val;
2029
2030         /* FDI relies on the transcoder */
2031         assert_fdi_tx_disabled(dev_priv, pipe);
2032         assert_fdi_rx_disabled(dev_priv, pipe);
2033
2034         /* Ports must be off as well */
2035         assert_pch_ports_disabled(dev_priv, pipe);
2036
2037         reg = PCH_TRANSCONF(pipe);
2038         val = I915_READ(reg);
2039         val &= ~TRANS_ENABLE;
2040         I915_WRITE(reg, val);
2041         /* wait for PCH transcoder off, transcoder state */
2042         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2043                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2044
2045         if (!HAS_PCH_IBX(dev)) {
2046                 /* Workaround: Clear the timing override chicken bit again. */
2047                 reg = TRANS_CHICKEN2(pipe);
2048                 val = I915_READ(reg);
2049                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2050                 I915_WRITE(reg, val);
2051         }
2052 }
2053
2054 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2055 {
2056         u32 val;
2057
2058         val = I915_READ(LPT_TRANSCONF);
2059         val &= ~TRANS_ENABLE;
2060         I915_WRITE(LPT_TRANSCONF, val);
2061         /* wait for PCH transcoder off, transcoder state */
2062         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2063                 DRM_ERROR("Failed to disable PCH transcoder\n");
2064
2065         /* Workaround: clear timing override bit. */
2066         val = I915_READ(_TRANSA_CHICKEN2);
2067         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2068         I915_WRITE(_TRANSA_CHICKEN2, val);
2069 }
2070
2071 /**
2072  * intel_enable_pipe - enable a pipe, asserting requirements
2073  * @crtc: crtc responsible for the pipe
2074  *
2075  * Enable @crtc's pipe, making sure that various hardware specific requirements
2076  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2077  */
2078 static void intel_enable_pipe(struct intel_crtc *crtc)
2079 {
2080         struct drm_device *dev = crtc->base.dev;
2081         struct drm_i915_private *dev_priv = dev->dev_private;
2082         enum pipe pipe = crtc->pipe;
2083         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2084                                                                       pipe);
2085         enum pipe pch_transcoder;
2086         int reg;
2087         u32 val;
2088
2089         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2090
2091         assert_planes_disabled(dev_priv, pipe);
2092         assert_cursor_disabled(dev_priv, pipe);
2093         assert_sprites_disabled(dev_priv, pipe);
2094
2095         if (HAS_PCH_LPT(dev_priv->dev))
2096                 pch_transcoder = TRANSCODER_A;
2097         else
2098                 pch_transcoder = pipe;
2099
2100         /*
2101          * A pipe without a PLL won't actually be able to drive bits from
2102          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2103          * need the check.
2104          */
2105         if (HAS_GMCH_DISPLAY(dev_priv->dev))
2106                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2107                         assert_dsi_pll_enabled(dev_priv);
2108                 else
2109                         assert_pll_enabled(dev_priv, pipe);
2110         else {
2111                 if (crtc->config->has_pch_encoder) {
2112                         /* if driving the PCH, we need FDI enabled */
2113                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2114                         assert_fdi_tx_pll_enabled(dev_priv,
2115                                                   (enum pipe) cpu_transcoder);
2116                 }
2117                 /* FIXME: assert CPU port conditions for SNB+ */
2118         }
2119
2120         reg = PIPECONF(cpu_transcoder);
2121         val = I915_READ(reg);
2122         if (val & PIPECONF_ENABLE) {
2123                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2124                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2125                 return;
2126         }
2127
2128         I915_WRITE(reg, val | PIPECONF_ENABLE);
2129         POSTING_READ(reg);
2130 }
2131
2132 /**
2133  * intel_disable_pipe - disable a pipe, asserting requirements
2134  * @crtc: crtc whose pipes is to be disabled
2135  *
2136  * Disable the pipe of @crtc, making sure that various hardware
2137  * specific requirements are met, if applicable, e.g. plane
2138  * disabled, panel fitter off, etc.
2139  *
2140  * Will wait until the pipe has shut down before returning.
2141  */
2142 static void intel_disable_pipe(struct intel_crtc *crtc)
2143 {
2144         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2145         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2146         enum pipe pipe = crtc->pipe;
2147         int reg;
2148         u32 val;
2149
2150         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2151
2152         /*
2153          * Make sure planes won't keep trying to pump pixels to us,
2154          * or we might hang the display.
2155          */
2156         assert_planes_disabled(dev_priv, pipe);
2157         assert_cursor_disabled(dev_priv, pipe);
2158         assert_sprites_disabled(dev_priv, pipe);
2159
2160         reg = PIPECONF(cpu_transcoder);
2161         val = I915_READ(reg);
2162         if ((val & PIPECONF_ENABLE) == 0)
2163                 return;
2164
2165         /*
2166          * Double wide has implications for planes
2167          * so best keep it disabled when not needed.
2168          */
2169         if (crtc->config->double_wide)
2170                 val &= ~PIPECONF_DOUBLE_WIDE;
2171
2172         /* Don't disable pipe or pipe PLLs if needed */
2173         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2174             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2175                 val &= ~PIPECONF_ENABLE;
2176
2177         I915_WRITE(reg, val);
2178         if ((val & PIPECONF_ENABLE) == 0)
2179                 intel_wait_for_pipe_off(crtc);
2180 }
2181
2182 static bool need_vtd_wa(struct drm_device *dev)
2183 {
2184 #ifdef CONFIG_INTEL_IOMMU
2185         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2186                 return true;
2187 #endif
2188         return false;
2189 }
2190
2191 unsigned int
2192 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2193                   uint64_t fb_format_modifier, unsigned int plane)
2194 {
2195         unsigned int tile_height;
2196         uint32_t pixel_bytes;
2197
2198         switch (fb_format_modifier) {
2199         case DRM_FORMAT_MOD_NONE:
2200                 tile_height = 1;
2201                 break;
2202         case I915_FORMAT_MOD_X_TILED:
2203                 tile_height = IS_GEN2(dev) ? 16 : 8;
2204                 break;
2205         case I915_FORMAT_MOD_Y_TILED:
2206                 tile_height = 32;
2207                 break;
2208         case I915_FORMAT_MOD_Yf_TILED:
2209                 pixel_bytes = drm_format_plane_cpp(pixel_format, plane);
2210                 switch (pixel_bytes) {
2211                 default:
2212                 case 1:
2213                         tile_height = 64;
2214                         break;
2215                 case 2:
2216                 case 4:
2217                         tile_height = 32;
2218                         break;
2219                 case 8:
2220                         tile_height = 16;
2221                         break;
2222                 case 16:
2223                         WARN_ONCE(1,
2224                                   "128-bit pixels are not supported for display!");
2225                         tile_height = 16;
2226                         break;
2227                 }
2228                 break;
2229         default:
2230                 MISSING_CASE(fb_format_modifier);
2231                 tile_height = 1;
2232                 break;
2233         }
2234
2235         return tile_height;
2236 }
2237
2238 unsigned int
2239 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2240                       uint32_t pixel_format, uint64_t fb_format_modifier)
2241 {
2242         return ALIGN(height, intel_tile_height(dev, pixel_format,
2243                                                fb_format_modifier, 0));
2244 }
2245
2246 static int
2247 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2248                         const struct drm_plane_state *plane_state)
2249 {
2250         struct intel_rotation_info *info = &view->rotation_info;
2251         unsigned int tile_height, tile_pitch;
2252
2253         *view = i915_ggtt_view_normal;
2254
2255         if (!plane_state)
2256                 return 0;
2257
2258         if (!intel_rotation_90_or_270(plane_state->rotation))
2259                 return 0;
2260
2261         *view = i915_ggtt_view_rotated;
2262
2263         info->height = fb->height;
2264         info->pixel_format = fb->pixel_format;
2265         info->pitch = fb->pitches[0];
2266         info->uv_offset = fb->offsets[1];
2267         info->fb_modifier = fb->modifier[0];
2268
2269         tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2270                                         fb->modifier[0], 0);
2271         tile_pitch = PAGE_SIZE / tile_height;
2272         info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2273         info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2274         info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2275
2276         if (info->pixel_format == DRM_FORMAT_NV12) {
2277                 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2278                                                 fb->modifier[0], 1);
2279                 tile_pitch = PAGE_SIZE / tile_height;
2280                 info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2281                 info->height_pages_uv = DIV_ROUND_UP(fb->height / 2,
2282                                                      tile_height);
2283                 info->size_uv = info->width_pages_uv * info->height_pages_uv *
2284                                 PAGE_SIZE;
2285         }
2286
2287         return 0;
2288 }
2289
2290 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2291 {
2292         if (INTEL_INFO(dev_priv)->gen >= 9)
2293                 return 256 * 1024;
2294         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2295                  IS_VALLEYVIEW(dev_priv))
2296                 return 128 * 1024;
2297         else if (INTEL_INFO(dev_priv)->gen >= 4)
2298                 return 4 * 1024;
2299         else
2300                 return 0;
2301 }
2302
2303 int
2304 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2305                            struct drm_framebuffer *fb,
2306                            const struct drm_plane_state *plane_state,
2307                            struct intel_engine_cs *pipelined,
2308                            struct drm_i915_gem_request **pipelined_request)
2309 {
2310         struct drm_device *dev = fb->dev;
2311         struct drm_i915_private *dev_priv = dev->dev_private;
2312         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2313         struct i915_ggtt_view view;
2314         u32 alignment;
2315         int ret;
2316
2317         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2318
2319         switch (fb->modifier[0]) {
2320         case DRM_FORMAT_MOD_NONE:
2321                 alignment = intel_linear_alignment(dev_priv);
2322                 break;
2323         case I915_FORMAT_MOD_X_TILED:
2324                 if (INTEL_INFO(dev)->gen >= 9)
2325                         alignment = 256 * 1024;
2326                 else {
2327                         /* pin() will align the object as required by fence */
2328                         alignment = 0;
2329                 }
2330                 break;
2331         case I915_FORMAT_MOD_Y_TILED:
2332         case I915_FORMAT_MOD_Yf_TILED:
2333                 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2334                           "Y tiling bo slipped through, driver bug!\n"))
2335                         return -EINVAL;
2336                 alignment = 1 * 1024 * 1024;
2337                 break;
2338         default:
2339                 MISSING_CASE(fb->modifier[0]);
2340                 return -EINVAL;
2341         }
2342
2343         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2344         if (ret)
2345                 return ret;
2346
2347         /* Note that the w/a also requires 64 PTE of padding following the
2348          * bo. We currently fill all unused PTE with the shadow page and so
2349          * we should always have valid PTE following the scanout preventing
2350          * the VT-d warning.
2351          */
2352         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2353                 alignment = 256 * 1024;
2354
2355         /*
2356          * Global gtt pte registers are special registers which actually forward
2357          * writes to a chunk of system memory. Which means that there is no risk
2358          * that the register values disappear as soon as we call
2359          * intel_runtime_pm_put(), so it is correct to wrap only the
2360          * pin/unpin/fence and not more.
2361          */
2362         intel_runtime_pm_get(dev_priv);
2363
2364         dev_priv->mm.interruptible = false;
2365         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2366                                                    pipelined_request, &view);
2367         if (ret)
2368                 goto err_interruptible;
2369
2370         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2371          * fence, whereas 965+ only requires a fence if using
2372          * framebuffer compression.  For simplicity, we always install
2373          * a fence as the cost is not that onerous.
2374          */
2375         ret = i915_gem_object_get_fence(obj);
2376         if (ret == -EDEADLK) {
2377                 /*
2378                  * -EDEADLK means there are no free fences
2379                  * no pending flips.
2380                  *
2381                  * This is propagated to atomic, but it uses
2382                  * -EDEADLK to force a locking recovery, so
2383                  * change the returned error to -EBUSY.
2384                  */
2385                 ret = -EBUSY;
2386                 goto err_unpin;
2387         } else if (ret)
2388                 goto err_unpin;
2389
2390         i915_gem_object_pin_fence(obj);
2391
2392         dev_priv->mm.interruptible = true;
2393         intel_runtime_pm_put(dev_priv);
2394         return 0;
2395
2396 err_unpin:
2397         i915_gem_object_unpin_from_display_plane(obj, &view);
2398 err_interruptible:
2399         dev_priv->mm.interruptible = true;
2400         intel_runtime_pm_put(dev_priv);
2401         return ret;
2402 }
2403
2404 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2405                                const struct drm_plane_state *plane_state)
2406 {
2407         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2408         struct i915_ggtt_view view;
2409         int ret;
2410
2411         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2412
2413         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2414         WARN_ONCE(ret, "Couldn't get view from plane state!");
2415
2416         i915_gem_object_unpin_fence(obj);
2417         i915_gem_object_unpin_from_display_plane(obj, &view);
2418 }
2419
2420 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2421  * is assumed to be a power-of-two. */
2422 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2423                                              int *x, int *y,
2424                                              unsigned int tiling_mode,
2425                                              unsigned int cpp,
2426                                              unsigned int pitch)
2427 {
2428         if (tiling_mode != I915_TILING_NONE) {
2429                 unsigned int tile_rows, tiles;
2430
2431                 tile_rows = *y / 8;
2432                 *y %= 8;
2433
2434                 tiles = *x / (512/cpp);
2435                 *x %= 512/cpp;
2436
2437                 return tile_rows * pitch * 8 + tiles * 4096;
2438         } else {
2439                 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2440                 unsigned int offset;
2441
2442                 offset = *y * pitch + *x * cpp;
2443                 *y = (offset & alignment) / pitch;
2444                 *x = ((offset & alignment) - *y * pitch) / cpp;
2445                 return offset & ~alignment;
2446         }
2447 }
2448
2449 static int i9xx_format_to_fourcc(int format)
2450 {
2451         switch (format) {
2452         case DISPPLANE_8BPP:
2453                 return DRM_FORMAT_C8;
2454         case DISPPLANE_BGRX555:
2455                 return DRM_FORMAT_XRGB1555;
2456         case DISPPLANE_BGRX565:
2457                 return DRM_FORMAT_RGB565;
2458         default:
2459         case DISPPLANE_BGRX888:
2460                 return DRM_FORMAT_XRGB8888;
2461         case DISPPLANE_RGBX888:
2462                 return DRM_FORMAT_XBGR8888;
2463         case DISPPLANE_BGRX101010:
2464                 return DRM_FORMAT_XRGB2101010;
2465         case DISPPLANE_RGBX101010:
2466                 return DRM_FORMAT_XBGR2101010;
2467         }
2468 }
2469
2470 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2471 {
2472         switch (format) {
2473         case PLANE_CTL_FORMAT_RGB_565:
2474                 return DRM_FORMAT_RGB565;
2475         default:
2476         case PLANE_CTL_FORMAT_XRGB_8888:
2477                 if (rgb_order) {
2478                         if (alpha)
2479                                 return DRM_FORMAT_ABGR8888;
2480                         else
2481                                 return DRM_FORMAT_XBGR8888;
2482                 } else {
2483                         if (alpha)
2484                                 return DRM_FORMAT_ARGB8888;
2485                         else
2486                                 return DRM_FORMAT_XRGB8888;
2487                 }
2488         case PLANE_CTL_FORMAT_XRGB_2101010:
2489                 if (rgb_order)
2490                         return DRM_FORMAT_XBGR2101010;
2491                 else
2492                         return DRM_FORMAT_XRGB2101010;
2493         }
2494 }
2495
2496 static bool
2497 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2498                               struct intel_initial_plane_config *plane_config)
2499 {
2500         struct drm_device *dev = crtc->base.dev;
2501         struct drm_i915_gem_object *obj = NULL;
2502         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2503         struct drm_framebuffer *fb = &plane_config->fb->base;
2504         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2505         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2506                                     PAGE_SIZE);
2507
2508         size_aligned -= base_aligned;
2509
2510         if (plane_config->size == 0)
2511                 return false;
2512
2513         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2514                                                              base_aligned,
2515                                                              base_aligned,
2516                                                              size_aligned);
2517         if (!obj)
2518                 return false;
2519
2520         obj->tiling_mode = plane_config->tiling;
2521         if (obj->tiling_mode == I915_TILING_X)
2522                 obj->stride = fb->pitches[0];
2523
2524         mode_cmd.pixel_format = fb->pixel_format;
2525         mode_cmd.width = fb->width;
2526         mode_cmd.height = fb->height;
2527         mode_cmd.pitches[0] = fb->pitches[0];
2528         mode_cmd.modifier[0] = fb->modifier[0];
2529         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2530
2531         mutex_lock(&dev->struct_mutex);
2532         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2533                                    &mode_cmd, obj)) {
2534                 DRM_DEBUG_KMS("intel fb init failed\n");
2535                 goto out_unref_obj;
2536         }
2537         mutex_unlock(&dev->struct_mutex);
2538
2539         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2540         return true;
2541
2542 out_unref_obj:
2543         drm_gem_object_unreference(&obj->base);
2544         mutex_unlock(&dev->struct_mutex);
2545         return false;
2546 }
2547
2548 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2549 static void
2550 update_state_fb(struct drm_plane *plane)
2551 {
2552         if (plane->fb == plane->state->fb)
2553                 return;
2554
2555         if (plane->state->fb)
2556                 drm_framebuffer_unreference(plane->state->fb);
2557         plane->state->fb = plane->fb;
2558         if (plane->state->fb)
2559                 drm_framebuffer_reference(plane->state->fb);
2560 }
2561
2562 static void
2563 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2564                              struct intel_initial_plane_config *plane_config)
2565 {
2566         struct drm_device *dev = intel_crtc->base.dev;
2567         struct drm_i915_private *dev_priv = dev->dev_private;
2568         struct drm_crtc *c;
2569         struct intel_crtc *i;
2570         struct drm_i915_gem_object *obj;
2571         struct drm_plane *primary = intel_crtc->base.primary;
2572         struct drm_plane_state *plane_state = primary->state;
2573         struct drm_framebuffer *fb;
2574
2575         if (!plane_config->fb)
2576                 return;
2577
2578         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2579                 fb = &plane_config->fb->base;
2580                 goto valid_fb;
2581         }
2582
2583         kfree(plane_config->fb);
2584
2585         /*
2586          * Failed to alloc the obj, check to see if we should share
2587          * an fb with another CRTC instead
2588          */
2589         for_each_crtc(dev, c) {
2590                 i = to_intel_crtc(c);
2591
2592                 if (c == &intel_crtc->base)
2593                         continue;
2594
2595                 if (!i->active)
2596                         continue;
2597
2598                 fb = c->primary->fb;
2599                 if (!fb)
2600                         continue;
2601
2602                 obj = intel_fb_obj(fb);
2603                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2604                         drm_framebuffer_reference(fb);
2605                         goto valid_fb;
2606                 }
2607         }
2608
2609         return;
2610
2611 valid_fb:
2612         plane_state->src_x = plane_state->src_y = 0;
2613         plane_state->src_w = fb->width << 16;
2614         plane_state->src_h = fb->height << 16;
2615
2616         plane_state->crtc_x = plane_state->src_y = 0;
2617         plane_state->crtc_w = fb->width;
2618         plane_state->crtc_h = fb->height;
2619
2620         obj = intel_fb_obj(fb);
2621         if (obj->tiling_mode != I915_TILING_NONE)
2622                 dev_priv->preserve_bios_swizzle = true;
2623
2624         drm_framebuffer_reference(fb);
2625         primary->fb = primary->state->fb = fb;
2626         primary->crtc = primary->state->crtc = &intel_crtc->base;
2627         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2628         obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2629 }
2630
2631 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2632                                       struct drm_framebuffer *fb,
2633                                       int x, int y)
2634 {
2635         struct drm_device *dev = crtc->dev;
2636         struct drm_i915_private *dev_priv = dev->dev_private;
2637         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2638         struct drm_plane *primary = crtc->primary;
2639         bool visible = to_intel_plane_state(primary->state)->visible;
2640         struct drm_i915_gem_object *obj;
2641         int plane = intel_crtc->plane;
2642         unsigned long linear_offset;
2643         u32 dspcntr;
2644         u32 reg = DSPCNTR(plane);
2645         int pixel_size;
2646
2647         if (!visible || !fb) {
2648                 I915_WRITE(reg, 0);
2649                 if (INTEL_INFO(dev)->gen >= 4)
2650                         I915_WRITE(DSPSURF(plane), 0);
2651                 else
2652                         I915_WRITE(DSPADDR(plane), 0);
2653                 POSTING_READ(reg);
2654                 return;
2655         }
2656
2657         obj = intel_fb_obj(fb);
2658         if (WARN_ON(obj == NULL))
2659                 return;
2660
2661         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2662
2663         dspcntr = DISPPLANE_GAMMA_ENABLE;
2664
2665         dspcntr |= DISPLAY_PLANE_ENABLE;
2666
2667         if (INTEL_INFO(dev)->gen < 4) {
2668                 if (intel_crtc->pipe == PIPE_B)
2669                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2670
2671                 /* pipesrc and dspsize control the size that is scaled from,
2672                  * which should always be the user's requested size.
2673                  */
2674                 I915_WRITE(DSPSIZE(plane),
2675                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2676                            (intel_crtc->config->pipe_src_w - 1));
2677                 I915_WRITE(DSPPOS(plane), 0);
2678         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2679                 I915_WRITE(PRIMSIZE(plane),
2680                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2681                            (intel_crtc->config->pipe_src_w - 1));
2682                 I915_WRITE(PRIMPOS(plane), 0);
2683                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2684         }
2685
2686         switch (fb->pixel_format) {
2687         case DRM_FORMAT_C8:
2688                 dspcntr |= DISPPLANE_8BPP;
2689                 break;
2690         case DRM_FORMAT_XRGB1555:
2691                 dspcntr |= DISPPLANE_BGRX555;
2692                 break;
2693         case DRM_FORMAT_RGB565:
2694                 dspcntr |= DISPPLANE_BGRX565;
2695                 break;
2696         case DRM_FORMAT_XRGB8888:
2697                 dspcntr |= DISPPLANE_BGRX888;
2698                 break;
2699         case DRM_FORMAT_XBGR8888:
2700                 dspcntr |= DISPPLANE_RGBX888;
2701                 break;
2702         case DRM_FORMAT_XRGB2101010:
2703                 dspcntr |= DISPPLANE_BGRX101010;
2704                 break;
2705         case DRM_FORMAT_XBGR2101010:
2706                 dspcntr |= DISPPLANE_RGBX101010;
2707                 break;
2708         default:
2709                 BUG();
2710         }
2711
2712         if (INTEL_INFO(dev)->gen >= 4 &&
2713             obj->tiling_mode != I915_TILING_NONE)
2714                 dspcntr |= DISPPLANE_TILED;
2715
2716         if (IS_G4X(dev))
2717                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2718
2719         linear_offset = y * fb->pitches[0] + x * pixel_size;
2720
2721         if (INTEL_INFO(dev)->gen >= 4) {
2722                 intel_crtc->dspaddr_offset =
2723                         intel_gen4_compute_page_offset(dev_priv,
2724                                                        &x, &y, obj->tiling_mode,
2725                                                        pixel_size,
2726                                                        fb->pitches[0]);
2727                 linear_offset -= intel_crtc->dspaddr_offset;
2728         } else {
2729                 intel_crtc->dspaddr_offset = linear_offset;
2730         }
2731
2732         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2733                 dspcntr |= DISPPLANE_ROTATE_180;
2734
2735                 x += (intel_crtc->config->pipe_src_w - 1);
2736                 y += (intel_crtc->config->pipe_src_h - 1);
2737
2738                 /* Finding the last pixel of the last line of the display
2739                 data and adding to linear_offset*/
2740                 linear_offset +=
2741                         (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2742                         (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2743         }
2744
2745         intel_crtc->adjusted_x = x;
2746         intel_crtc->adjusted_y = y;
2747
2748         I915_WRITE(reg, dspcntr);
2749
2750         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2751         if (INTEL_INFO(dev)->gen >= 4) {
2752                 I915_WRITE(DSPSURF(plane),
2753                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2754                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2755                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2756         } else
2757                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2758         POSTING_READ(reg);
2759 }
2760
2761 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2762                                           struct drm_framebuffer *fb,
2763                                           int x, int y)
2764 {
2765         struct drm_device *dev = crtc->dev;
2766         struct drm_i915_private *dev_priv = dev->dev_private;
2767         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2768         struct drm_plane *primary = crtc->primary;
2769         bool visible = to_intel_plane_state(primary->state)->visible;
2770         struct drm_i915_gem_object *obj;
2771         int plane = intel_crtc->plane;
2772         unsigned long linear_offset;
2773         u32 dspcntr;
2774         u32 reg = DSPCNTR(plane);
2775         int pixel_size;
2776
2777         if (!visible || !fb) {
2778                 I915_WRITE(reg, 0);
2779                 I915_WRITE(DSPSURF(plane), 0);
2780                 POSTING_READ(reg);
2781                 return;
2782         }
2783
2784         obj = intel_fb_obj(fb);
2785         if (WARN_ON(obj == NULL))
2786                 return;
2787
2788         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2789
2790         dspcntr = DISPPLANE_GAMMA_ENABLE;
2791
2792         dspcntr |= DISPLAY_PLANE_ENABLE;
2793
2794         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2795                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2796
2797         switch (fb->pixel_format) {
2798         case DRM_FORMAT_C8:
2799                 dspcntr |= DISPPLANE_8BPP;
2800                 break;
2801         case DRM_FORMAT_RGB565:
2802                 dspcntr |= DISPPLANE_BGRX565;
2803                 break;
2804         case DRM_FORMAT_XRGB8888:
2805                 dspcntr |= DISPPLANE_BGRX888;
2806                 break;
2807         case DRM_FORMAT_XBGR8888:
2808                 dspcntr |= DISPPLANE_RGBX888;
2809                 break;
2810         case DRM_FORMAT_XRGB2101010:
2811                 dspcntr |= DISPPLANE_BGRX101010;
2812                 break;
2813         case DRM_FORMAT_XBGR2101010:
2814                 dspcntr |= DISPPLANE_RGBX101010;
2815                 break;
2816         default:
2817                 BUG();
2818         }
2819
2820         if (obj->tiling_mode != I915_TILING_NONE)
2821                 dspcntr |= DISPPLANE_TILED;
2822
2823         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2824                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2825
2826         linear_offset = y * fb->pitches[0] + x * pixel_size;
2827         intel_crtc->dspaddr_offset =
2828                 intel_gen4_compute_page_offset(dev_priv,
2829                                                &x, &y, obj->tiling_mode,
2830                                                pixel_size,
2831                                                fb->pitches[0]);
2832         linear_offset -= intel_crtc->dspaddr_offset;
2833         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2834                 dspcntr |= DISPPLANE_ROTATE_180;
2835
2836                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2837                         x += (intel_crtc->config->pipe_src_w - 1);
2838                         y += (intel_crtc->config->pipe_src_h - 1);
2839
2840                         /* Finding the last pixel of the last line of the display
2841                         data and adding to linear_offset*/
2842                         linear_offset +=
2843                                 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2844                                 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2845                 }
2846         }
2847
2848         intel_crtc->adjusted_x = x;
2849         intel_crtc->adjusted_y = y;
2850
2851         I915_WRITE(reg, dspcntr);
2852
2853         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2854         I915_WRITE(DSPSURF(plane),
2855                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2856         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2857                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2858         } else {
2859                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2860                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2861         }
2862         POSTING_READ(reg);
2863 }
2864
2865 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2866                               uint32_t pixel_format)
2867 {
2868         u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2869
2870         /*
2871          * The stride is either expressed as a multiple of 64 bytes
2872          * chunks for linear buffers or in number of tiles for tiled
2873          * buffers.
2874          */
2875         switch (fb_modifier) {
2876         case DRM_FORMAT_MOD_NONE:
2877                 return 64;
2878         case I915_FORMAT_MOD_X_TILED:
2879                 if (INTEL_INFO(dev)->gen == 2)
2880                         return 128;
2881                 return 512;
2882         case I915_FORMAT_MOD_Y_TILED:
2883                 /* No need to check for old gens and Y tiling since this is
2884                  * about the display engine and those will be blocked before
2885                  * we get here.
2886                  */
2887                 return 128;
2888         case I915_FORMAT_MOD_Yf_TILED:
2889                 if (bits_per_pixel == 8)
2890                         return 64;
2891                 else
2892                         return 128;
2893         default:
2894                 MISSING_CASE(fb_modifier);
2895                 return 64;
2896         }
2897 }
2898
2899 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2900                                      struct drm_i915_gem_object *obj,
2901                                      unsigned int plane)
2902 {
2903         const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2904         struct i915_vma *vma;
2905         unsigned char *offset;
2906
2907         if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2908                 view = &i915_ggtt_view_rotated;
2909
2910         vma = i915_gem_obj_to_ggtt_view(obj, view);
2911         if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2912                 view->type))
2913                 return -1;
2914
2915         offset = (unsigned char *)vma->node.start;
2916
2917         if (plane == 1) {
2918                 offset += vma->ggtt_view.rotation_info.uv_start_page *
2919                           PAGE_SIZE;
2920         }
2921
2922         return (unsigned long)offset;
2923 }
2924
2925 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2926 {
2927         struct drm_device *dev = intel_crtc->base.dev;
2928         struct drm_i915_private *dev_priv = dev->dev_private;
2929
2930         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2931         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2932         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2933 }
2934
2935 /*
2936  * This function detaches (aka. unbinds) unused scalers in hardware
2937  */
2938 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2939 {
2940         struct intel_crtc_scaler_state *scaler_state;
2941         int i;
2942
2943         scaler_state = &intel_crtc->config->scaler_state;
2944
2945         /* loop through and disable scalers that aren't in use */
2946         for (i = 0; i < intel_crtc->num_scalers; i++) {
2947                 if (!scaler_state->scalers[i].in_use)
2948                         skl_detach_scaler(intel_crtc, i);
2949         }
2950 }
2951
2952 u32 skl_plane_ctl_format(uint32_t pixel_format)
2953 {
2954         switch (pixel_format) {
2955         case DRM_FORMAT_C8:
2956                 return PLANE_CTL_FORMAT_INDEXED;
2957         case DRM_FORMAT_RGB565:
2958                 return PLANE_CTL_FORMAT_RGB_565;
2959         case DRM_FORMAT_XBGR8888:
2960                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2961         case DRM_FORMAT_XRGB8888:
2962                 return PLANE_CTL_FORMAT_XRGB_8888;
2963         /*
2964          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2965          * to be already pre-multiplied. We need to add a knob (or a different
2966          * DRM_FORMAT) for user-space to configure that.
2967          */
2968         case DRM_FORMAT_ABGR8888:
2969                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2970                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2971         case DRM_FORMAT_ARGB8888:
2972                 return PLANE_CTL_FORMAT_XRGB_8888 |
2973                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2974         case DRM_FORMAT_XRGB2101010:
2975                 return PLANE_CTL_FORMAT_XRGB_2101010;
2976         case DRM_FORMAT_XBGR2101010:
2977                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2978         case DRM_FORMAT_YUYV:
2979                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2980         case DRM_FORMAT_YVYU:
2981                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2982         case DRM_FORMAT_UYVY:
2983                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2984         case DRM_FORMAT_VYUY:
2985                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2986         default:
2987                 MISSING_CASE(pixel_format);
2988         }
2989
2990         return 0;
2991 }
2992
2993 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2994 {
2995         switch (fb_modifier) {
2996         case DRM_FORMAT_MOD_NONE:
2997                 break;
2998         case I915_FORMAT_MOD_X_TILED:
2999                 return PLANE_CTL_TILED_X;
3000         case I915_FORMAT_MOD_Y_TILED:
3001                 return PLANE_CTL_TILED_Y;
3002         case I915_FORMAT_MOD_Yf_TILED:
3003                 return PLANE_CTL_TILED_YF;
3004         default:
3005                 MISSING_CASE(fb_modifier);
3006         }
3007
3008         return 0;
3009 }
3010
3011 u32 skl_plane_ctl_rotation(unsigned int rotation)
3012 {
3013         switch (rotation) {
3014         case BIT(DRM_ROTATE_0):
3015                 break;
3016         /*
3017          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3018          * while i915 HW rotation is clockwise, thats why this swapping.
3019          */
3020         case BIT(DRM_ROTATE_90):
3021                 return PLANE_CTL_ROTATE_270;
3022         case BIT(DRM_ROTATE_180):
3023                 return PLANE_CTL_ROTATE_180;
3024         case BIT(DRM_ROTATE_270):
3025                 return PLANE_CTL_ROTATE_90;
3026         default:
3027                 MISSING_CASE(rotation);
3028         }
3029
3030         return 0;
3031 }
3032
3033 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3034                                          struct drm_framebuffer *fb,
3035                                          int x, int y)
3036 {
3037         struct drm_device *dev = crtc->dev;
3038         struct drm_i915_private *dev_priv = dev->dev_private;
3039         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3040         struct drm_plane *plane = crtc->primary;
3041         bool visible = to_intel_plane_state(plane->state)->visible;
3042         struct drm_i915_gem_object *obj;
3043         int pipe = intel_crtc->pipe;
3044         u32 plane_ctl, stride_div, stride;
3045         u32 tile_height, plane_offset, plane_size;
3046         unsigned int rotation;
3047         int x_offset, y_offset;
3048         unsigned long surf_addr;
3049         struct intel_crtc_state *crtc_state = intel_crtc->config;
3050         struct intel_plane_state *plane_state;
3051         int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3052         int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3053         int scaler_id = -1;
3054
3055         plane_state = to_intel_plane_state(plane->state);
3056
3057         if (!visible || !fb) {
3058                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3059                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3060                 POSTING_READ(PLANE_CTL(pipe, 0));
3061                 return;
3062         }
3063
3064         plane_ctl = PLANE_CTL_ENABLE |
3065                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3066                     PLANE_CTL_PIPE_CSC_ENABLE;
3067
3068         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3069         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3070         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3071
3072         rotation = plane->state->rotation;
3073         plane_ctl |= skl_plane_ctl_rotation(rotation);
3074
3075         obj = intel_fb_obj(fb);
3076         stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3077                                                fb->pixel_format);
3078         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3079
3080         /*
3081          * FIXME: intel_plane_state->src, dst aren't set when transitional
3082          * update_plane helpers are called from legacy paths.
3083          * Once full atomic crtc is available, below check can be avoided.
3084          */
3085         if (drm_rect_width(&plane_state->src)) {
3086                 scaler_id = plane_state->scaler_id;
3087                 src_x = plane_state->src.x1 >> 16;
3088                 src_y = plane_state->src.y1 >> 16;
3089                 src_w = drm_rect_width(&plane_state->src) >> 16;
3090                 src_h = drm_rect_height(&plane_state->src) >> 16;
3091                 dst_x = plane_state->dst.x1;
3092                 dst_y = plane_state->dst.y1;
3093                 dst_w = drm_rect_width(&plane_state->dst);
3094                 dst_h = drm_rect_height(&plane_state->dst);
3095
3096                 WARN_ON(x != src_x || y != src_y);
3097         } else {
3098                 src_w = intel_crtc->config->pipe_src_w;
3099                 src_h = intel_crtc->config->pipe_src_h;
3100         }
3101
3102         if (intel_rotation_90_or_270(rotation)) {
3103                 /* stride = Surface height in tiles */
3104                 tile_height = intel_tile_height(dev, fb->pixel_format,
3105                                                 fb->modifier[0], 0);
3106                 stride = DIV_ROUND_UP(fb->height, tile_height);
3107                 x_offset = stride * tile_height - y - src_h;
3108                 y_offset = x;
3109                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3110         } else {
3111                 stride = fb->pitches[0] / stride_div;
3112                 x_offset = x;
3113                 y_offset = y;
3114                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3115         }
3116         plane_offset = y_offset << 16 | x_offset;
3117
3118         intel_crtc->adjusted_x = x_offset;
3119         intel_crtc->adjusted_y = y_offset;
3120
3121         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3122         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3123         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3124         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3125
3126         if (scaler_id >= 0) {
3127                 uint32_t ps_ctrl = 0;
3128
3129                 WARN_ON(!dst_w || !dst_h);
3130                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3131                         crtc_state->scaler_state.scalers[scaler_id].mode;
3132                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3133                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3134                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3135                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3136                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3137         } else {
3138                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3139         }
3140
3141         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3142
3143         POSTING_READ(PLANE_SURF(pipe, 0));
3144 }
3145
3146 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3147 static int
3148 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3149                            int x, int y, enum mode_set_atomic state)
3150 {
3151         struct drm_device *dev = crtc->dev;
3152         struct drm_i915_private *dev_priv = dev->dev_private;
3153
3154         if (dev_priv->fbc.disable_fbc)
3155                 dev_priv->fbc.disable_fbc(dev_priv);
3156
3157         dev_priv->display.update_primary_plane(crtc, fb, x, y);
3158
3159         return 0;
3160 }
3161
3162 static void intel_complete_page_flips(struct drm_device *dev)
3163 {
3164         struct drm_crtc *crtc;
3165
3166         for_each_crtc(dev, crtc) {
3167                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3168                 enum plane plane = intel_crtc->plane;
3169
3170                 intel_prepare_page_flip(dev, plane);
3171                 intel_finish_page_flip_plane(dev, plane);
3172         }
3173 }
3174
3175 static void intel_update_primary_planes(struct drm_device *dev)
3176 {
3177         struct drm_crtc *crtc;
3178
3179         for_each_crtc(dev, crtc) {
3180                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3181                 struct intel_plane_state *plane_state;
3182
3183                 drm_modeset_lock_crtc(crtc, &plane->base);
3184
3185                 plane_state = to_intel_plane_state(plane->base.state);
3186
3187                 if (plane_state->base.fb)
3188                         plane->commit_plane(&plane->base, plane_state);
3189
3190                 drm_modeset_unlock_crtc(crtc);
3191         }
3192 }
3193
3194 void intel_prepare_reset(struct drm_device *dev)
3195 {
3196         /* no reset support for gen2 */
3197         if (IS_GEN2(dev))
3198                 return;
3199
3200         /* reset doesn't touch the display */
3201         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3202                 return;
3203
3204         drm_modeset_lock_all(dev);
3205         /*
3206          * Disabling the crtcs gracefully seems nicer. Also the
3207          * g33 docs say we should at least disable all the planes.
3208          */
3209         intel_display_suspend(dev);
3210 }
3211
3212 void intel_finish_reset(struct drm_device *dev)
3213 {
3214         struct drm_i915_private *dev_priv = to_i915(dev);
3215
3216         /*
3217          * Flips in the rings will be nuked by the reset,
3218          * so complete all pending flips so that user space
3219          * will get its events and not get stuck.
3220          */
3221         intel_complete_page_flips(dev);
3222
3223         /* no reset support for gen2 */
3224         if (IS_GEN2(dev))
3225                 return;
3226
3227         /* reset doesn't touch the display */
3228         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3229                 /*
3230                  * Flips in the rings have been nuked by the reset,
3231                  * so update the base address of all primary
3232                  * planes to the the last fb to make sure we're
3233                  * showing the correct fb after a reset.
3234                  *
3235                  * FIXME: Atomic will make this obsolete since we won't schedule
3236                  * CS-based flips (which might get lost in gpu resets) any more.
3237                  */
3238                 intel_update_primary_planes(dev);
3239                 return;
3240         }
3241
3242         /*
3243          * The display has been reset as well,
3244          * so need a full re-initialization.
3245          */
3246         intel_runtime_pm_disable_interrupts(dev_priv);
3247         intel_runtime_pm_enable_interrupts(dev_priv);
3248
3249         intel_modeset_init_hw(dev);
3250
3251         spin_lock_irq(&dev_priv->irq_lock);
3252         if (dev_priv->display.hpd_irq_setup)
3253                 dev_priv->display.hpd_irq_setup(dev);
3254         spin_unlock_irq(&dev_priv->irq_lock);
3255
3256         intel_display_resume(dev);
3257
3258         intel_hpd_init(dev_priv);
3259
3260         drm_modeset_unlock_all(dev);
3261 }
3262
3263 static void
3264 intel_finish_fb(struct drm_framebuffer *old_fb)
3265 {
3266         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3267         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3268         bool was_interruptible = dev_priv->mm.interruptible;
3269         int ret;
3270
3271         /* Big Hammer, we also need to ensure that any pending
3272          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3273          * current scanout is retired before unpinning the old
3274          * framebuffer. Note that we rely on userspace rendering
3275          * into the buffer attached to the pipe they are waiting
3276          * on. If not, userspace generates a GPU hang with IPEHR
3277          * point to the MI_WAIT_FOR_EVENT.
3278          *
3279          * This should only fail upon a hung GPU, in which case we
3280          * can safely continue.
3281          */
3282         dev_priv->mm.interruptible = false;
3283         ret = i915_gem_object_wait_rendering(obj, true);
3284         dev_priv->mm.interruptible = was_interruptible;
3285
3286         WARN_ON(ret);
3287 }
3288
3289 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3290 {
3291         struct drm_device *dev = crtc->dev;
3292         struct drm_i915_private *dev_priv = dev->dev_private;
3293         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3294         bool pending;
3295
3296         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3297             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3298                 return false;
3299
3300         spin_lock_irq(&dev->event_lock);
3301         pending = to_intel_crtc(crtc)->unpin_work != NULL;
3302         spin_unlock_irq(&dev->event_lock);
3303
3304         return pending;
3305 }
3306
3307 static void intel_update_pipe_config(struct intel_crtc *crtc,
3308                                      struct intel_crtc_state *old_crtc_state)
3309 {
3310         struct drm_device *dev = crtc->base.dev;
3311         struct drm_i915_private *dev_priv = dev->dev_private;
3312         struct intel_crtc_state *pipe_config =
3313                 to_intel_crtc_state(crtc->base.state);
3314
3315         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3316         crtc->base.mode = crtc->base.state->mode;
3317
3318         DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3319                       old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3320                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3321
3322         if (HAS_DDI(dev))
3323                 intel_set_pipe_csc(&crtc->base);
3324
3325         /*
3326          * Update pipe size and adjust fitter if needed: the reason for this is
3327          * that in compute_mode_changes we check the native mode (not the pfit
3328          * mode) to see if we can flip rather than do a full mode set. In the
3329          * fastboot case, we'll flip, but if we don't update the pipesrc and
3330          * pfit state, we'll end up with a big fb scanned out into the wrong
3331          * sized surface.
3332          */
3333
3334         I915_WRITE(PIPESRC(crtc->pipe),
3335                    ((pipe_config->pipe_src_w - 1) << 16) |
3336                    (pipe_config->pipe_src_h - 1));
3337
3338         /* on skylake this is done by detaching scalers */
3339         if (INTEL_INFO(dev)->gen >= 9) {
3340                 skl_detach_scalers(crtc);
3341
3342                 if (pipe_config->pch_pfit.enabled)
3343                         skylake_pfit_enable(crtc);
3344         } else if (HAS_PCH_SPLIT(dev)) {
3345                 if (pipe_config->pch_pfit.enabled)
3346                         ironlake_pfit_enable(crtc);
3347                 else if (old_crtc_state->pch_pfit.enabled)
3348                         ironlake_pfit_disable(crtc, true);
3349         }
3350 }
3351
3352 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3353 {
3354         struct drm_device *dev = crtc->dev;
3355         struct drm_i915_private *dev_priv = dev->dev_private;
3356         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3357         int pipe = intel_crtc->pipe;
3358         u32 reg, temp;
3359
3360         /* enable normal train */
3361         reg = FDI_TX_CTL(pipe);
3362         temp = I915_READ(reg);
3363         if (IS_IVYBRIDGE(dev)) {
3364                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3365                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3366         } else {
3367                 temp &= ~FDI_LINK_TRAIN_NONE;
3368                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3369         }
3370         I915_WRITE(reg, temp);
3371
3372         reg = FDI_RX_CTL(pipe);
3373         temp = I915_READ(reg);
3374         if (HAS_PCH_CPT(dev)) {
3375                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3376                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3377         } else {
3378                 temp &= ~FDI_LINK_TRAIN_NONE;
3379                 temp |= FDI_LINK_TRAIN_NONE;
3380         }
3381         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3382
3383         /* wait one idle pattern time */
3384         POSTING_READ(reg);
3385         udelay(1000);
3386
3387         /* IVB wants error correction enabled */
3388         if (IS_IVYBRIDGE(dev))
3389                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3390                            FDI_FE_ERRC_ENABLE);
3391 }
3392
3393 /* The FDI link training functions for ILK/Ibexpeak. */
3394 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3395 {
3396         struct drm_device *dev = crtc->dev;
3397         struct drm_i915_private *dev_priv = dev->dev_private;
3398         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3399         int pipe = intel_crtc->pipe;
3400         u32 reg, temp, tries;
3401
3402         /* FDI needs bits from pipe first */
3403         assert_pipe_enabled(dev_priv, pipe);
3404
3405         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3406            for train result */
3407         reg = FDI_RX_IMR(pipe);
3408         temp = I915_READ(reg);
3409         temp &= ~FDI_RX_SYMBOL_LOCK;
3410         temp &= ~FDI_RX_BIT_LOCK;
3411         I915_WRITE(reg, temp);
3412         I915_READ(reg);
3413         udelay(150);
3414
3415         /* enable CPU FDI TX and PCH FDI RX */
3416         reg = FDI_TX_CTL(pipe);
3417         temp = I915_READ(reg);
3418         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3419         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3420         temp &= ~FDI_LINK_TRAIN_NONE;
3421         temp |= FDI_LINK_TRAIN_PATTERN_1;
3422         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3423
3424         reg = FDI_RX_CTL(pipe);
3425         temp = I915_READ(reg);
3426         temp &= ~FDI_LINK_TRAIN_NONE;
3427         temp |= FDI_LINK_TRAIN_PATTERN_1;
3428         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3429
3430         POSTING_READ(reg);
3431         udelay(150);
3432
3433         /* Ironlake workaround, enable clock pointer after FDI enable*/
3434         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3435         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3436                    FDI_RX_PHASE_SYNC_POINTER_EN);
3437
3438         reg = FDI_RX_IIR(pipe);
3439         for (tries = 0; tries < 5; tries++) {
3440                 temp = I915_READ(reg);
3441                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3442
3443                 if ((temp & FDI_RX_BIT_LOCK)) {
3444                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3445                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3446                         break;
3447                 }
3448         }
3449         if (tries == 5)
3450                 DRM_ERROR("FDI train 1 fail!\n");
3451
3452         /* Train 2 */
3453         reg = FDI_TX_CTL(pipe);
3454         temp = I915_READ(reg);
3455         temp &= ~FDI_LINK_TRAIN_NONE;
3456         temp |= FDI_LINK_TRAIN_PATTERN_2;
3457         I915_WRITE(reg, temp);
3458
3459         reg = FDI_RX_CTL(pipe);
3460         temp = I915_READ(reg);
3461         temp &= ~FDI_LINK_TRAIN_NONE;
3462         temp |= FDI_LINK_TRAIN_PATTERN_2;
3463         I915_WRITE(reg, temp);
3464
3465         POSTING_READ(reg);
3466         udelay(150);
3467
3468         reg = FDI_RX_IIR(pipe);
3469         for (tries = 0; tries < 5; tries++) {
3470                 temp = I915_READ(reg);
3471                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3472
3473                 if (temp & FDI_RX_SYMBOL_LOCK) {
3474                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3475                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3476                         break;
3477                 }
3478         }
3479         if (tries == 5)
3480                 DRM_ERROR("FDI train 2 fail!\n");
3481
3482         DRM_DEBUG_KMS("FDI train done\n");
3483
3484 }
3485
3486 static const int snb_b_fdi_train_param[] = {
3487         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3488         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3489         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3490         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3491 };
3492
3493 /* The FDI link training functions for SNB/Cougarpoint. */
3494 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3495 {
3496         struct drm_device *dev = crtc->dev;
3497         struct drm_i915_private *dev_priv = dev->dev_private;
3498         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3499         int pipe = intel_crtc->pipe;
3500         u32 reg, temp, i, retry;
3501
3502         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3503            for train result */
3504         reg = FDI_RX_IMR(pipe);
3505         temp = I915_READ(reg);
3506         temp &= ~FDI_RX_SYMBOL_LOCK;
3507         temp &= ~FDI_RX_BIT_LOCK;
3508         I915_WRITE(reg, temp);
3509
3510         POSTING_READ(reg);
3511         udelay(150);
3512
3513         /* enable CPU FDI TX and PCH FDI RX */
3514         reg = FDI_TX_CTL(pipe);
3515         temp = I915_READ(reg);
3516         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3517         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3518         temp &= ~FDI_LINK_TRAIN_NONE;
3519         temp |= FDI_LINK_TRAIN_PATTERN_1;
3520         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3521         /* SNB-B */
3522         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3523         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3524
3525         I915_WRITE(FDI_RX_MISC(pipe),
3526                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3527
3528         reg = FDI_RX_CTL(pipe);
3529         temp = I915_READ(reg);
3530         if (HAS_PCH_CPT(dev)) {
3531                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3532                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3533         } else {
3534                 temp &= ~FDI_LINK_TRAIN_NONE;
3535                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3536         }
3537         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3538
3539         POSTING_READ(reg);
3540         udelay(150);
3541
3542         for (i = 0; i < 4; i++) {
3543                 reg = FDI_TX_CTL(pipe);
3544                 temp = I915_READ(reg);
3545                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3546                 temp |= snb_b_fdi_train_param[i];
3547                 I915_WRITE(reg, temp);
3548
3549                 POSTING_READ(reg);
3550                 udelay(500);
3551
3552                 for (retry = 0; retry < 5; retry++) {
3553                         reg = FDI_RX_IIR(pipe);
3554                         temp = I915_READ(reg);
3555                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3556                         if (temp & FDI_RX_BIT_LOCK) {
3557                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3558                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3559                                 break;
3560                         }
3561                         udelay(50);
3562                 }
3563                 if (retry < 5)
3564                         break;
3565         }
3566         if (i == 4)
3567                 DRM_ERROR("FDI train 1 fail!\n");
3568
3569         /* Train 2 */
3570         reg = FDI_TX_CTL(pipe);
3571         temp = I915_READ(reg);
3572         temp &= ~FDI_LINK_TRAIN_NONE;
3573         temp |= FDI_LINK_TRAIN_PATTERN_2;
3574         if (IS_GEN6(dev)) {
3575                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3576                 /* SNB-B */
3577                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3578         }
3579         I915_WRITE(reg, temp);
3580
3581         reg = FDI_RX_CTL(pipe);
3582         temp = I915_READ(reg);
3583         if (HAS_PCH_CPT(dev)) {
3584                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3585                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3586         } else {
3587                 temp &= ~FDI_LINK_TRAIN_NONE;
3588                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3589         }
3590         I915_WRITE(reg, temp);
3591
3592         POSTING_READ(reg);
3593         udelay(150);
3594
3595         for (i = 0; i < 4; i++) {
3596                 reg = FDI_TX_CTL(pipe);
3597                 temp = I915_READ(reg);
3598                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3599                 temp |= snb_b_fdi_train_param[i];
3600                 I915_WRITE(reg, temp);
3601
3602                 POSTING_READ(reg);
3603                 udelay(500);
3604
3605                 for (retry = 0; retry < 5; retry++) {
3606                         reg = FDI_RX_IIR(pipe);
3607                         temp = I915_READ(reg);
3608                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3609                         if (temp & FDI_RX_SYMBOL_LOCK) {
3610                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3611                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3612                                 break;
3613                         }
3614                         udelay(50);
3615                 }
3616                 if (retry < 5)
3617                         break;
3618         }
3619         if (i == 4)
3620                 DRM_ERROR("FDI train 2 fail!\n");
3621
3622         DRM_DEBUG_KMS("FDI train done.\n");
3623 }
3624
3625 /* Manual link training for Ivy Bridge A0 parts */
3626 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3627 {
3628         struct drm_device *dev = crtc->dev;
3629         struct drm_i915_private *dev_priv = dev->dev_private;
3630         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3631         int pipe = intel_crtc->pipe;
3632         u32 reg, temp, i, j;
3633
3634         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3635            for train result */
3636         reg = FDI_RX_IMR(pipe);
3637         temp = I915_READ(reg);
3638         temp &= ~FDI_RX_SYMBOL_LOCK;
3639         temp &= ~FDI_RX_BIT_LOCK;
3640         I915_WRITE(reg, temp);
3641
3642         POSTING_READ(reg);
3643         udelay(150);
3644
3645         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3646                       I915_READ(FDI_RX_IIR(pipe)));
3647
3648         /* Try each vswing and preemphasis setting twice before moving on */
3649         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3650                 /* disable first in case we need to retry */
3651                 reg = FDI_TX_CTL(pipe);
3652                 temp = I915_READ(reg);
3653                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3654                 temp &= ~FDI_TX_ENABLE;
3655                 I915_WRITE(reg, temp);
3656
3657                 reg = FDI_RX_CTL(pipe);
3658                 temp = I915_READ(reg);
3659                 temp &= ~FDI_LINK_TRAIN_AUTO;
3660                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3661                 temp &= ~FDI_RX_ENABLE;
3662                 I915_WRITE(reg, temp);
3663
3664                 /* enable CPU FDI TX and PCH FDI RX */
3665                 reg = FDI_TX_CTL(pipe);
3666                 temp = I915_READ(reg);
3667                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3668                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3669                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3670                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3671                 temp |= snb_b_fdi_train_param[j/2];
3672                 temp |= FDI_COMPOSITE_SYNC;
3673                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3674
3675                 I915_WRITE(FDI_RX_MISC(pipe),
3676                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3677
3678                 reg = FDI_RX_CTL(pipe);
3679                 temp = I915_READ(reg);
3680                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3681                 temp |= FDI_COMPOSITE_SYNC;
3682                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3683
3684                 POSTING_READ(reg);
3685                 udelay(1); /* should be 0.5us */
3686
3687                 for (i = 0; i < 4; i++) {
3688                         reg = FDI_RX_IIR(pipe);
3689                         temp = I915_READ(reg);
3690                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3691
3692                         if (temp & FDI_RX_BIT_LOCK ||
3693                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3694                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3695                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3696                                               i);
3697                                 break;
3698                         }
3699                         udelay(1); /* should be 0.5us */
3700                 }
3701                 if (i == 4) {
3702                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3703                         continue;
3704                 }
3705
3706                 /* Train 2 */
3707                 reg = FDI_TX_CTL(pipe);
3708                 temp = I915_READ(reg);
3709                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3710                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3711                 I915_WRITE(reg, temp);
3712
3713                 reg = FDI_RX_CTL(pipe);
3714                 temp = I915_READ(reg);
3715                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3716                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3717                 I915_WRITE(reg, temp);
3718
3719                 POSTING_READ(reg);
3720                 udelay(2); /* should be 1.5us */
3721
3722                 for (i = 0; i < 4; i++) {
3723                         reg = FDI_RX_IIR(pipe);
3724                         temp = I915_READ(reg);
3725                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3726
3727                         if (temp & FDI_RX_SYMBOL_LOCK ||
3728                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3729                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3730                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3731                                               i);
3732                                 goto train_done;
3733                         }
3734                         udelay(2); /* should be 1.5us */
3735                 }
3736                 if (i == 4)
3737                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3738         }
3739
3740 train_done:
3741         DRM_DEBUG_KMS("FDI train done.\n");
3742 }
3743
3744 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3745 {
3746         struct drm_device *dev = intel_crtc->base.dev;
3747         struct drm_i915_private *dev_priv = dev->dev_private;
3748         int pipe = intel_crtc->pipe;
3749         u32 reg, temp;
3750
3751
3752         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3753         reg = FDI_RX_CTL(pipe);
3754         temp = I915_READ(reg);
3755         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3756         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3757         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3758         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3759
3760         POSTING_READ(reg);
3761         udelay(200);
3762
3763         /* Switch from Rawclk to PCDclk */
3764         temp = I915_READ(reg);
3765         I915_WRITE(reg, temp | FDI_PCDCLK);
3766
3767         POSTING_READ(reg);
3768         udelay(200);
3769
3770         /* Enable CPU FDI TX PLL, always on for Ironlake */
3771         reg = FDI_TX_CTL(pipe);
3772         temp = I915_READ(reg);
3773         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3774                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3775
3776                 POSTING_READ(reg);
3777                 udelay(100);
3778         }
3779 }
3780
3781 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3782 {
3783         struct drm_device *dev = intel_crtc->base.dev;
3784         struct drm_i915_private *dev_priv = dev->dev_private;
3785         int pipe = intel_crtc->pipe;
3786         u32 reg, temp;
3787
3788         /* Switch from PCDclk to Rawclk */
3789         reg = FDI_RX_CTL(pipe);
3790         temp = I915_READ(reg);
3791         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3792
3793         /* Disable CPU FDI TX PLL */
3794         reg = FDI_TX_CTL(pipe);
3795         temp = I915_READ(reg);
3796         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3797
3798         POSTING_READ(reg);
3799         udelay(100);
3800
3801         reg = FDI_RX_CTL(pipe);
3802         temp = I915_READ(reg);
3803         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3804
3805         /* Wait for the clocks to turn off. */
3806         POSTING_READ(reg);
3807         udelay(100);
3808 }
3809
3810 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3811 {
3812         struct drm_device *dev = crtc->dev;
3813         struct drm_i915_private *dev_priv = dev->dev_private;
3814         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3815         int pipe = intel_crtc->pipe;
3816         u32 reg, temp;
3817
3818         /* disable CPU FDI tx and PCH FDI rx */
3819         reg = FDI_TX_CTL(pipe);
3820         temp = I915_READ(reg);
3821         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3822         POSTING_READ(reg);
3823
3824         reg = FDI_RX_CTL(pipe);
3825         temp = I915_READ(reg);
3826         temp &= ~(0x7 << 16);
3827         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3828         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3829
3830         POSTING_READ(reg);
3831         udelay(100);
3832
3833         /* Ironlake workaround, disable clock pointer after downing FDI */
3834         if (HAS_PCH_IBX(dev))
3835                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3836
3837         /* still set train pattern 1 */
3838         reg = FDI_TX_CTL(pipe);
3839         temp = I915_READ(reg);
3840         temp &= ~FDI_LINK_TRAIN_NONE;
3841         temp |= FDI_LINK_TRAIN_PATTERN_1;
3842         I915_WRITE(reg, temp);
3843
3844         reg = FDI_RX_CTL(pipe);
3845         temp = I915_READ(reg);
3846         if (HAS_PCH_CPT(dev)) {
3847                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3848                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3849         } else {
3850                 temp &= ~FDI_LINK_TRAIN_NONE;
3851                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3852         }
3853         /* BPC in FDI rx is consistent with that in PIPECONF */
3854         temp &= ~(0x07 << 16);
3855         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3856         I915_WRITE(reg, temp);
3857
3858         POSTING_READ(reg);
3859         udelay(100);
3860 }
3861
3862 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3863 {
3864         struct intel_crtc *crtc;
3865
3866         /* Note that we don't need to be called with mode_config.lock here
3867          * as our list of CRTC objects is static for the lifetime of the
3868          * device and so cannot disappear as we iterate. Similarly, we can
3869          * happily treat the predicates as racy, atomic checks as userspace
3870          * cannot claim and pin a new fb without at least acquring the
3871          * struct_mutex and so serialising with us.
3872          */
3873         for_each_intel_crtc(dev, crtc) {
3874                 if (atomic_read(&crtc->unpin_work_count) == 0)
3875                         continue;
3876
3877                 if (crtc->unpin_work)
3878                         intel_wait_for_vblank(dev, crtc->pipe);
3879
3880                 return true;
3881         }
3882
3883         return false;
3884 }
3885
3886 static void page_flip_completed(struct intel_crtc *intel_crtc)
3887 {
3888         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3889         struct intel_unpin_work *work = intel_crtc->unpin_work;
3890
3891         /* ensure that the unpin work is consistent wrt ->pending. */
3892         smp_rmb();
3893         intel_crtc->unpin_work = NULL;
3894
3895         if (work->event)
3896                 drm_send_vblank_event(intel_crtc->base.dev,
3897                                       intel_crtc->pipe,
3898                                       work->event);
3899
3900         drm_crtc_vblank_put(&intel_crtc->base);
3901
3902         wake_up_all(&dev_priv->pending_flip_queue);
3903         queue_work(dev_priv->wq, &work->work);
3904
3905         trace_i915_flip_complete(intel_crtc->plane,
3906                                  work->pending_flip_obj);
3907 }
3908
3909 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3910 {
3911         struct drm_device *dev = crtc->dev;
3912         struct drm_i915_private *dev_priv = dev->dev_private;
3913
3914         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3915         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3916                                        !intel_crtc_has_pending_flip(crtc),
3917                                        60*HZ) == 0)) {
3918                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3919
3920                 spin_lock_irq(&dev->event_lock);
3921                 if (intel_crtc->unpin_work) {
3922                         WARN_ONCE(1, "Removing stuck page flip\n");
3923                         page_flip_completed(intel_crtc);
3924                 }
3925                 spin_unlock_irq(&dev->event_lock);
3926         }
3927
3928         if (crtc->primary->fb) {
3929                 mutex_lock(&dev->struct_mutex);
3930                 intel_finish_fb(crtc->primary->fb);
3931                 mutex_unlock(&dev->struct_mutex);
3932         }
3933 }
3934
3935 /* Program iCLKIP clock to the desired frequency */
3936 static void lpt_program_iclkip(struct drm_crtc *crtc)
3937 {
3938         struct drm_device *dev = crtc->dev;
3939         struct drm_i915_private *dev_priv = dev->dev_private;
3940         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3941         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3942         u32 temp;
3943
3944         mutex_lock(&dev_priv->sb_lock);
3945
3946         /* It is necessary to ungate the pixclk gate prior to programming
3947          * the divisors, and gate it back when it is done.
3948          */
3949         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3950
3951         /* Disable SSCCTL */
3952         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3953                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3954                                 SBI_SSCCTL_DISABLE,
3955                         SBI_ICLK);
3956
3957         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3958         if (clock == 20000) {
3959                 auxdiv = 1;
3960                 divsel = 0x41;
3961                 phaseinc = 0x20;
3962         } else {
3963                 /* The iCLK virtual clock root frequency is in MHz,
3964                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3965                  * divisors, it is necessary to divide one by another, so we
3966                  * convert the virtual clock precision to KHz here for higher
3967                  * precision.
3968                  */
3969                 u32 iclk_virtual_root_freq = 172800 * 1000;
3970                 u32 iclk_pi_range = 64;
3971                 u32 desired_divisor, msb_divisor_value, pi_value;
3972
3973                 desired_divisor = (iclk_virtual_root_freq / clock);
3974                 msb_divisor_value = desired_divisor / iclk_pi_range;
3975                 pi_value = desired_divisor % iclk_pi_range;
3976
3977                 auxdiv = 0;
3978                 divsel = msb_divisor_value - 2;
3979                 phaseinc = pi_value;
3980         }
3981
3982         /* This should not happen with any sane values */
3983         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3984                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3985         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3986                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3987
3988         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3989                         clock,
3990                         auxdiv,
3991                         divsel,
3992                         phasedir,
3993                         phaseinc);
3994
3995         /* Program SSCDIVINTPHASE6 */
3996         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3997         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3998         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3999         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4000         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4001         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4002         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4003         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4004
4005         /* Program SSCAUXDIV */
4006         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4007         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4008         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4009         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4010
4011         /* Enable modulator and associated divider */
4012         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4013         temp &= ~SBI_SSCCTL_DISABLE;
4014         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4015
4016         /* Wait for initialization time */
4017         udelay(24);
4018
4019         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4020
4021         mutex_unlock(&dev_priv->sb_lock);
4022 }
4023
4024 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4025                                                 enum pipe pch_transcoder)
4026 {
4027         struct drm_device *dev = crtc->base.dev;
4028         struct drm_i915_private *dev_priv = dev->dev_private;
4029         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4030
4031         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4032                    I915_READ(HTOTAL(cpu_transcoder)));
4033         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4034                    I915_READ(HBLANK(cpu_transcoder)));
4035         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4036                    I915_READ(HSYNC(cpu_transcoder)));
4037
4038         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4039                    I915_READ(VTOTAL(cpu_transcoder)));
4040         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4041                    I915_READ(VBLANK(cpu_transcoder)));
4042         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4043                    I915_READ(VSYNC(cpu_transcoder)));
4044         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4045                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4046 }
4047
4048 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4049 {
4050         struct drm_i915_private *dev_priv = dev->dev_private;
4051         uint32_t temp;
4052
4053         temp = I915_READ(SOUTH_CHICKEN1);
4054         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4055                 return;
4056
4057         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4058         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4059
4060         temp &= ~FDI_BC_BIFURCATION_SELECT;
4061         if (enable)
4062                 temp |= FDI_BC_BIFURCATION_SELECT;
4063
4064         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4065         I915_WRITE(SOUTH_CHICKEN1, temp);
4066         POSTING_READ(SOUTH_CHICKEN1);
4067 }
4068
4069 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4070 {
4071         struct drm_device *dev = intel_crtc->base.dev;
4072
4073         switch (intel_crtc->pipe) {
4074         case PIPE_A:
4075                 break;
4076         case PIPE_B:
4077                 if (intel_crtc->config->fdi_lanes > 2)
4078                         cpt_set_fdi_bc_bifurcation(dev, false);
4079                 else
4080                         cpt_set_fdi_bc_bifurcation(dev, true);
4081
4082                 break;
4083         case PIPE_C:
4084                 cpt_set_fdi_bc_bifurcation(dev, true);
4085
4086                 break;
4087         default:
4088                 BUG();
4089         }
4090 }
4091
4092 /*
4093  * Enable PCH resources required for PCH ports:
4094  *   - PCH PLLs
4095  *   - FDI training & RX/TX
4096  *   - update transcoder timings
4097  *   - DP transcoding bits
4098  *   - transcoder
4099  */
4100 static void ironlake_pch_enable(struct drm_crtc *crtc)
4101 {
4102         struct drm_device *dev = crtc->dev;
4103         struct drm_i915_private *dev_priv = dev->dev_private;
4104         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4105         int pipe = intel_crtc->pipe;
4106         u32 reg, temp;
4107
4108         assert_pch_transcoder_disabled(dev_priv, pipe);
4109
4110         if (IS_IVYBRIDGE(dev))
4111                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4112
4113         /* Write the TU size bits before fdi link training, so that error
4114          * detection works. */
4115         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4116                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4117
4118         /* For PCH output, training FDI link */
4119         dev_priv->display.fdi_link_train(crtc);
4120
4121         /* We need to program the right clock selection before writing the pixel
4122          * mutliplier into the DPLL. */
4123         if (HAS_PCH_CPT(dev)) {
4124                 u32 sel;
4125
4126                 temp = I915_READ(PCH_DPLL_SEL);
4127                 temp |= TRANS_DPLL_ENABLE(pipe);
4128                 sel = TRANS_DPLLB_SEL(pipe);
4129                 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4130                         temp |= sel;
4131                 else
4132                         temp &= ~sel;
4133                 I915_WRITE(PCH_DPLL_SEL, temp);
4134         }
4135
4136         /* XXX: pch pll's can be enabled any time before we enable the PCH
4137          * transcoder, and we actually should do this to not upset any PCH
4138          * transcoder that already use the clock when we share it.
4139          *
4140          * Note that enable_shared_dpll tries to do the right thing, but
4141          * get_shared_dpll unconditionally resets the pll - we need that to have
4142          * the right LVDS enable sequence. */
4143         intel_enable_shared_dpll(intel_crtc);
4144
4145         /* set transcoder timing, panel must allow it */
4146         assert_panel_unlocked(dev_priv, pipe);
4147         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4148
4149         intel_fdi_normal_train(crtc);
4150
4151         /* For PCH DP, enable TRANS_DP_CTL */
4152         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4153                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4154                 reg = TRANS_DP_CTL(pipe);
4155                 temp = I915_READ(reg);
4156                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4157                           TRANS_DP_SYNC_MASK |
4158                           TRANS_DP_BPC_MASK);
4159                 temp |= TRANS_DP_OUTPUT_ENABLE;
4160                 temp |= bpc << 9; /* same format but at 11:9 */
4161
4162                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4163                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4164                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4165                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4166
4167                 switch (intel_trans_dp_port_sel(crtc)) {
4168                 case PCH_DP_B:
4169                         temp |= TRANS_DP_PORT_SEL_B;
4170                         break;
4171                 case PCH_DP_C:
4172                         temp |= TRANS_DP_PORT_SEL_C;
4173                         break;
4174                 case PCH_DP_D:
4175                         temp |= TRANS_DP_PORT_SEL_D;
4176                         break;
4177                 default:
4178                         BUG();
4179                 }
4180
4181                 I915_WRITE(reg, temp);
4182         }
4183
4184         ironlake_enable_pch_transcoder(dev_priv, pipe);
4185 }
4186
4187 static void lpt_pch_enable(struct drm_crtc *crtc)
4188 {
4189         struct drm_device *dev = crtc->dev;
4190         struct drm_i915_private *dev_priv = dev->dev_private;
4191         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4192         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4193
4194         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4195
4196         lpt_program_iclkip(crtc);
4197
4198         /* Set transcoder timing. */
4199         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4200
4201         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4202 }
4203
4204 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4205                                                 struct intel_crtc_state *crtc_state)
4206 {
4207         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4208         struct intel_shared_dpll *pll;
4209         struct intel_shared_dpll_config *shared_dpll;
4210         enum intel_dpll_id i;
4211
4212         shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4213
4214         if (HAS_PCH_IBX(dev_priv->dev)) {
4215                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4216                 i = (enum intel_dpll_id) crtc->pipe;
4217                 pll = &dev_priv->shared_dplls[i];
4218
4219                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4220                               crtc->base.base.id, pll->name);
4221
4222                 WARN_ON(shared_dpll[i].crtc_mask);
4223
4224                 goto found;
4225         }
4226
4227         if (IS_BROXTON(dev_priv->dev)) {
4228                 /* PLL is attached to port in bxt */
4229                 struct intel_encoder *encoder;
4230                 struct intel_digital_port *intel_dig_port;
4231
4232                 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4233                 if (WARN_ON(!encoder))
4234                         return NULL;
4235
4236                 intel_dig_port = enc_to_dig_port(&encoder->base);
4237                 /* 1:1 mapping between ports and PLLs */
4238                 i = (enum intel_dpll_id)intel_dig_port->port;
4239                 pll = &dev_priv->shared_dplls[i];
4240                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4241                         crtc->base.base.id, pll->name);
4242                 WARN_ON(shared_dpll[i].crtc_mask);
4243
4244                 goto found;
4245         }
4246
4247         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4248                 pll = &dev_priv->shared_dplls[i];
4249
4250                 /* Only want to check enabled timings first */
4251                 if (shared_dpll[i].crtc_mask == 0)
4252                         continue;
4253
4254                 if (memcmp(&crtc_state->dpll_hw_state,
4255                            &shared_dpll[i].hw_state,
4256                            sizeof(crtc_state->dpll_hw_state)) == 0) {
4257                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4258                                       crtc->base.base.id, pll->name,
4259                                       shared_dpll[i].crtc_mask,
4260                                       pll->active);
4261                         goto found;
4262                 }
4263         }
4264
4265         /* Ok no matching timings, maybe there's a free one? */
4266         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4267                 pll = &dev_priv->shared_dplls[i];
4268                 if (shared_dpll[i].crtc_mask == 0) {
4269                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4270                                       crtc->base.base.id, pll->name);
4271                         goto found;
4272                 }
4273         }
4274
4275         return NULL;
4276
4277 found:
4278         if (shared_dpll[i].crtc_mask == 0)
4279                 shared_dpll[i].hw_state =
4280                         crtc_state->dpll_hw_state;
4281
4282         crtc_state->shared_dpll = i;
4283         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4284                          pipe_name(crtc->pipe));
4285
4286         shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4287
4288         return pll;
4289 }
4290
4291 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4292 {
4293         struct drm_i915_private *dev_priv = to_i915(state->dev);
4294         struct intel_shared_dpll_config *shared_dpll;
4295         struct intel_shared_dpll *pll;
4296         enum intel_dpll_id i;
4297
4298         if (!to_intel_atomic_state(state)->dpll_set)
4299                 return;
4300
4301         shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4302         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4303                 pll = &dev_priv->shared_dplls[i];
4304                 pll->config = shared_dpll[i];
4305         }
4306 }
4307
4308 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4309 {
4310         struct drm_i915_private *dev_priv = dev->dev_private;
4311         int dslreg = PIPEDSL(pipe);
4312         u32 temp;
4313
4314         temp = I915_READ(dslreg);
4315         udelay(500);
4316         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4317                 if (wait_for(I915_READ(dslreg) != temp, 5))
4318                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4319         }
4320 }
4321
4322 static int
4323 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4324                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4325                   int src_w, int src_h, int dst_w, int dst_h)
4326 {
4327         struct intel_crtc_scaler_state *scaler_state =
4328                 &crtc_state->scaler_state;
4329         struct intel_crtc *intel_crtc =
4330                 to_intel_crtc(crtc_state->base.crtc);
4331         int need_scaling;
4332
4333         need_scaling = intel_rotation_90_or_270(rotation) ?
4334                 (src_h != dst_w || src_w != dst_h):
4335                 (src_w != dst_w || src_h != dst_h);
4336
4337         /*
4338          * if plane is being disabled or scaler is no more required or force detach
4339          *  - free scaler binded to this plane/crtc
4340          *  - in order to do this, update crtc->scaler_usage
4341          *
4342          * Here scaler state in crtc_state is set free so that
4343          * scaler can be assigned to other user. Actual register
4344          * update to free the scaler is done in plane/panel-fit programming.
4345          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4346          */
4347         if (force_detach || !need_scaling) {
4348                 if (*scaler_id >= 0) {
4349                         scaler_state->scaler_users &= ~(1 << scaler_user);
4350                         scaler_state->scalers[*scaler_id].in_use = 0;
4351
4352                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4353                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4354                                 intel_crtc->pipe, scaler_user, *scaler_id,
4355                                 scaler_state->scaler_users);
4356                         *scaler_id = -1;
4357                 }
4358                 return 0;
4359         }
4360
4361         /* range checks */
4362         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4363                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4364
4365                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4366                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4367                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4368                         "size is out of scaler range\n",
4369                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4370                 return -EINVAL;
4371         }
4372
4373         /* mark this plane as a scaler user in crtc_state */
4374         scaler_state->scaler_users |= (1 << scaler_user);
4375         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4376                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4377                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4378                 scaler_state->scaler_users);
4379
4380         return 0;
4381 }
4382
4383 /**
4384  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4385  *
4386  * @state: crtc's scaler state
4387  *
4388  * Return
4389  *     0 - scaler_usage updated successfully
4390  *    error - requested scaling cannot be supported or other error condition
4391  */
4392 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4393 {
4394         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4395         struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4396
4397         DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4398                       intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4399
4400         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4401                 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4402                 state->pipe_src_w, state->pipe_src_h,
4403                 adjusted_mode->hdisplay, adjusted_mode->vdisplay);
4404 }
4405
4406 /**
4407  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4408  *
4409  * @state: crtc's scaler state
4410  * @plane_state: atomic plane state to update
4411  *
4412  * Return
4413  *     0 - scaler_usage updated successfully
4414  *    error - requested scaling cannot be supported or other error condition
4415  */
4416 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4417                                    struct intel_plane_state *plane_state)
4418 {
4419
4420         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4421         struct intel_plane *intel_plane =
4422                 to_intel_plane(plane_state->base.plane);
4423         struct drm_framebuffer *fb = plane_state->base.fb;
4424         int ret;
4425
4426         bool force_detach = !fb || !plane_state->visible;
4427
4428         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4429                       intel_plane->base.base.id, intel_crtc->pipe,
4430                       drm_plane_index(&intel_plane->base));
4431
4432         ret = skl_update_scaler(crtc_state, force_detach,
4433                                 drm_plane_index(&intel_plane->base),
4434                                 &plane_state->scaler_id,
4435                                 plane_state->base.rotation,
4436                                 drm_rect_width(&plane_state->src) >> 16,
4437                                 drm_rect_height(&plane_state->src) >> 16,
4438                                 drm_rect_width(&plane_state->dst),
4439                                 drm_rect_height(&plane_state->dst));
4440
4441         if (ret || plane_state->scaler_id < 0)
4442                 return ret;
4443
4444         /* check colorkey */
4445         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4446                 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4447                               intel_plane->base.base.id);
4448                 return -EINVAL;
4449         }
4450
4451         /* Check src format */
4452         switch (fb->pixel_format) {
4453         case DRM_FORMAT_RGB565:
4454         case DRM_FORMAT_XBGR8888:
4455         case DRM_FORMAT_XRGB8888:
4456         case DRM_FORMAT_ABGR8888:
4457         case DRM_FORMAT_ARGB8888:
4458         case DRM_FORMAT_XRGB2101010:
4459         case DRM_FORMAT_XBGR2101010:
4460         case DRM_FORMAT_YUYV:
4461         case DRM_FORMAT_YVYU:
4462         case DRM_FORMAT_UYVY:
4463         case DRM_FORMAT_VYUY:
4464                 break;
4465         default:
4466                 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4467                         intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4468                 return -EINVAL;
4469         }
4470
4471         return 0;
4472 }
4473
4474 static void skylake_scaler_disable(struct intel_crtc *crtc)
4475 {
4476         int i;
4477
4478         for (i = 0; i < crtc->num_scalers; i++)
4479                 skl_detach_scaler(crtc, i);
4480 }
4481
4482 static void skylake_pfit_enable(struct intel_crtc *crtc)
4483 {
4484         struct drm_device *dev = crtc->base.dev;
4485         struct drm_i915_private *dev_priv = dev->dev_private;
4486         int pipe = crtc->pipe;
4487         struct intel_crtc_scaler_state *scaler_state =
4488                 &crtc->config->scaler_state;
4489
4490         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4491
4492         if (crtc->config->pch_pfit.enabled) {
4493                 int id;
4494
4495                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4496                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4497                         return;
4498                 }
4499
4500                 id = scaler_state->scaler_id;
4501                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4502                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4503                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4504                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4505
4506                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4507         }
4508 }
4509
4510 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4511 {
4512         struct drm_device *dev = crtc->base.dev;
4513         struct drm_i915_private *dev_priv = dev->dev_private;
4514         int pipe = crtc->pipe;
4515
4516         if (crtc->config->pch_pfit.enabled) {
4517                 /* Force use of hard-coded filter coefficients
4518                  * as some pre-programmed values are broken,
4519                  * e.g. x201.
4520                  */
4521                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4522                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4523                                                  PF_PIPE_SEL_IVB(pipe));
4524                 else
4525                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4526                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4527                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4528         }
4529 }
4530
4531 void hsw_enable_ips(struct intel_crtc *crtc)
4532 {
4533         struct drm_device *dev = crtc->base.dev;
4534         struct drm_i915_private *dev_priv = dev->dev_private;
4535
4536         if (!crtc->config->ips_enabled)
4537                 return;
4538
4539         /* We can only enable IPS after we enable a plane and wait for a vblank */
4540         intel_wait_for_vblank(dev, crtc->pipe);
4541
4542         assert_plane_enabled(dev_priv, crtc->plane);
4543         if (IS_BROADWELL(dev)) {
4544                 mutex_lock(&dev_priv->rps.hw_lock);
4545                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4546                 mutex_unlock(&dev_priv->rps.hw_lock);
4547                 /* Quoting Art Runyan: "its not safe to expect any particular
4548                  * value in IPS_CTL bit 31 after enabling IPS through the
4549                  * mailbox." Moreover, the mailbox may return a bogus state,
4550                  * so we need to just enable it and continue on.
4551                  */
4552         } else {
4553                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4554                 /* The bit only becomes 1 in the next vblank, so this wait here
4555                  * is essentially intel_wait_for_vblank. If we don't have this
4556                  * and don't wait for vblanks until the end of crtc_enable, then
4557                  * the HW state readout code will complain that the expected
4558                  * IPS_CTL value is not the one we read. */
4559                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4560                         DRM_ERROR("Timed out waiting for IPS enable\n");
4561         }
4562 }
4563
4564 void hsw_disable_ips(struct intel_crtc *crtc)
4565 {
4566         struct drm_device *dev = crtc->base.dev;
4567         struct drm_i915_private *dev_priv = dev->dev_private;
4568
4569         if (!crtc->config->ips_enabled)
4570                 return;
4571
4572         assert_plane_enabled(dev_priv, crtc->plane);
4573         if (IS_BROADWELL(dev)) {
4574                 mutex_lock(&dev_priv->rps.hw_lock);
4575                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4576                 mutex_unlock(&dev_priv->rps.hw_lock);
4577                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4578                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4579                         DRM_ERROR("Timed out waiting for IPS disable\n");
4580         } else {
4581                 I915_WRITE(IPS_CTL, 0);
4582                 POSTING_READ(IPS_CTL);
4583         }
4584
4585         /* We need to wait for a vblank before we can disable the plane. */
4586         intel_wait_for_vblank(dev, crtc->pipe);
4587 }
4588
4589 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4590 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4591 {
4592         struct drm_device *dev = crtc->dev;
4593         struct drm_i915_private *dev_priv = dev->dev_private;
4594         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4595         enum pipe pipe = intel_crtc->pipe;
4596         int palreg = PALETTE(pipe);
4597         int i;
4598         bool reenable_ips = false;
4599
4600         /* The clocks have to be on to load the palette. */
4601         if (!crtc->state->active)
4602                 return;
4603
4604         if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4605                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4606                         assert_dsi_pll_enabled(dev_priv);
4607                 else
4608                         assert_pll_enabled(dev_priv, pipe);
4609         }
4610
4611         /* use legacy palette for Ironlake */
4612         if (!HAS_GMCH_DISPLAY(dev))
4613                 palreg = LGC_PALETTE(pipe);
4614
4615         /* Workaround : Do not read or write the pipe palette/gamma data while
4616          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4617          */
4618         if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4619             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4620              GAMMA_MODE_MODE_SPLIT)) {
4621                 hsw_disable_ips(intel_crtc);
4622                 reenable_ips = true;
4623         }
4624
4625         for (i = 0; i < 256; i++) {
4626                 I915_WRITE(palreg + 4 * i,
4627                            (intel_crtc->lut_r[i] << 16) |
4628                            (intel_crtc->lut_g[i] << 8) |
4629                            intel_crtc->lut_b[i]);
4630         }
4631
4632         if (reenable_ips)
4633                 hsw_enable_ips(intel_crtc);
4634 }
4635
4636 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4637 {
4638         if (intel_crtc->overlay) {
4639                 struct drm_device *dev = intel_crtc->base.dev;
4640                 struct drm_i915_private *dev_priv = dev->dev_private;
4641
4642                 mutex_lock(&dev->struct_mutex);
4643                 dev_priv->mm.interruptible = false;
4644                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4645                 dev_priv->mm.interruptible = true;
4646                 mutex_unlock(&dev->struct_mutex);
4647         }
4648
4649         /* Let userspace switch the overlay on again. In most cases userspace
4650          * has to recompute where to put it anyway.
4651          */
4652 }
4653
4654 /**
4655  * intel_post_enable_primary - Perform operations after enabling primary plane
4656  * @crtc: the CRTC whose primary plane was just enabled
4657  *
4658  * Performs potentially sleeping operations that must be done after the primary
4659  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4660  * called due to an explicit primary plane update, or due to an implicit
4661  * re-enable that is caused when a sprite plane is updated to no longer
4662  * completely hide the primary plane.
4663  */
4664 static void
4665 intel_post_enable_primary(struct drm_crtc *crtc)
4666 {
4667         struct drm_device *dev = crtc->dev;
4668         struct drm_i915_private *dev_priv = dev->dev_private;
4669         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4670         int pipe = intel_crtc->pipe;
4671
4672         /*
4673          * BDW signals flip done immediately if the plane
4674          * is disabled, even if the plane enable is already
4675          * armed to occur at the next vblank :(
4676          */
4677         if (IS_BROADWELL(dev))
4678                 intel_wait_for_vblank(dev, pipe);
4679
4680         /*
4681          * FIXME IPS should be fine as long as one plane is
4682          * enabled, but in practice it seems to have problems
4683          * when going from primary only to sprite only and vice
4684          * versa.
4685          */
4686         hsw_enable_ips(intel_crtc);
4687
4688         /*
4689          * Gen2 reports pipe underruns whenever all planes are disabled.
4690          * So don't enable underrun reporting before at least some planes
4691          * are enabled.
4692          * FIXME: Need to fix the logic to work when we turn off all planes
4693          * but leave the pipe running.
4694          */
4695         if (IS_GEN2(dev))
4696                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4697
4698         /* Underruns don't raise interrupts, so check manually. */
4699         if (HAS_GMCH_DISPLAY(dev))
4700                 i9xx_check_fifo_underruns(dev_priv);
4701 }
4702
4703 /**
4704  * intel_pre_disable_primary - Perform operations before disabling primary plane
4705  * @crtc: the CRTC whose primary plane is to be disabled
4706  *
4707  * Performs potentially sleeping operations that must be done before the
4708  * primary plane is disabled, such as updating FBC and IPS.  Note that this may
4709  * be called due to an explicit primary plane update, or due to an implicit
4710  * disable that is caused when a sprite plane completely hides the primary
4711  * plane.
4712  */
4713 static void
4714 intel_pre_disable_primary(struct drm_crtc *crtc)
4715 {
4716         struct drm_device *dev = crtc->dev;
4717         struct drm_i915_private *dev_priv = dev->dev_private;
4718         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4719         int pipe = intel_crtc->pipe;
4720
4721         /*
4722          * Gen2 reports pipe underruns whenever all planes are disabled.
4723          * So diasble underrun reporting before all the planes get disabled.
4724          * FIXME: Need to fix the logic to work when we turn off all planes
4725          * but leave the pipe running.
4726          */
4727         if (IS_GEN2(dev))
4728                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4729
4730         /*
4731          * Vblank time updates from the shadow to live plane control register
4732          * are blocked if the memory self-refresh mode is active at that
4733          * moment. So to make sure the plane gets truly disabled, disable
4734          * first the self-refresh mode. The self-refresh enable bit in turn
4735          * will be checked/applied by the HW only at the next frame start
4736          * event which is after the vblank start event, so we need to have a
4737          * wait-for-vblank between disabling the plane and the pipe.
4738          */
4739         if (HAS_GMCH_DISPLAY(dev)) {
4740                 intel_set_memory_cxsr(dev_priv, false);
4741                 dev_priv->wm.vlv.cxsr = false;
4742                 intel_wait_for_vblank(dev, pipe);
4743         }
4744
4745         /*
4746          * FIXME IPS should be fine as long as one plane is
4747          * enabled, but in practice it seems to have problems
4748          * when going from primary only to sprite only and vice
4749          * versa.
4750          */
4751         hsw_disable_ips(intel_crtc);
4752 }
4753
4754 static void intel_post_plane_update(struct intel_crtc *crtc)
4755 {
4756         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4757         struct drm_device *dev = crtc->base.dev;
4758         struct drm_i915_private *dev_priv = dev->dev_private;
4759         struct drm_plane *plane;
4760
4761         if (atomic->wait_vblank)
4762                 intel_wait_for_vblank(dev, crtc->pipe);
4763
4764         intel_frontbuffer_flip(dev, atomic->fb_bits);
4765
4766         if (atomic->disable_cxsr)
4767                 crtc->wm.cxsr_allowed = true;
4768
4769         if (crtc->atomic.update_wm_post)
4770                 intel_update_watermarks(&crtc->base);
4771
4772         if (atomic->update_fbc)
4773                 intel_fbc_update(dev_priv);
4774
4775         if (atomic->post_enable_primary)
4776                 intel_post_enable_primary(&crtc->base);
4777
4778         drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4779                 intel_update_sprite_watermarks(plane, &crtc->base,
4780                                                0, 0, 0, false, false);
4781
4782         memset(atomic, 0, sizeof(*atomic));
4783 }
4784
4785 static void intel_pre_plane_update(struct intel_crtc *crtc)
4786 {
4787         struct drm_device *dev = crtc->base.dev;
4788         struct drm_i915_private *dev_priv = dev->dev_private;
4789         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4790         struct drm_plane *p;
4791
4792         /* Track fb's for any planes being disabled */
4793         drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4794                 struct intel_plane *plane = to_intel_plane(p);
4795
4796                 mutex_lock(&dev->struct_mutex);
4797                 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4798                                   plane->frontbuffer_bit);
4799                 mutex_unlock(&dev->struct_mutex);
4800         }
4801
4802         if (atomic->wait_for_flips)
4803                 intel_crtc_wait_for_pending_flips(&crtc->base);
4804
4805         if (atomic->disable_fbc)
4806                 intel_fbc_disable_crtc(crtc);
4807
4808         if (crtc->atomic.disable_ips)
4809                 hsw_disable_ips(crtc);
4810
4811         if (atomic->pre_disable_primary)
4812                 intel_pre_disable_primary(&crtc->base);
4813
4814         if (atomic->disable_cxsr) {
4815                 crtc->wm.cxsr_allowed = false;
4816                 intel_set_memory_cxsr(dev_priv, false);
4817         }
4818 }
4819
4820 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4821 {
4822         struct drm_device *dev = crtc->dev;
4823         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4824         struct drm_plane *p;
4825         int pipe = intel_crtc->pipe;
4826
4827         intel_crtc_dpms_overlay_disable(intel_crtc);
4828
4829         drm_for_each_plane_mask(p, dev, plane_mask)
4830                 to_intel_plane(p)->disable_plane(p, crtc);
4831
4832         /*
4833          * FIXME: Once we grow proper nuclear flip support out of this we need
4834          * to compute the mask of flip planes precisely. For the time being
4835          * consider this a flip to a NULL plane.
4836          */
4837         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4838 }
4839
4840 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4841 {
4842         struct drm_device *dev = crtc->dev;
4843         struct drm_i915_private *dev_priv = dev->dev_private;
4844         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4845         struct intel_encoder *encoder;
4846         int pipe = intel_crtc->pipe;
4847
4848         if (WARN_ON(intel_crtc->active))
4849                 return;
4850
4851         if (intel_crtc->config->has_pch_encoder)
4852                 intel_prepare_shared_dpll(intel_crtc);
4853
4854         if (intel_crtc->config->has_dp_encoder)
4855                 intel_dp_set_m_n(intel_crtc, M1_N1);
4856
4857         intel_set_pipe_timings(intel_crtc);
4858
4859         if (intel_crtc->config->has_pch_encoder) {
4860                 intel_cpu_transcoder_set_m_n(intel_crtc,
4861                                      &intel_crtc->config->fdi_m_n, NULL);
4862         }
4863
4864         ironlake_set_pipeconf(crtc);
4865
4866         intel_crtc->active = true;
4867
4868         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4869         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4870
4871         for_each_encoder_on_crtc(dev, crtc, encoder)
4872                 if (encoder->pre_enable)
4873                         encoder->pre_enable(encoder);
4874
4875         if (intel_crtc->config->has_pch_encoder) {
4876                 /* Note: FDI PLL enabling _must_ be done before we enable the
4877                  * cpu pipes, hence this is separate from all the other fdi/pch
4878                  * enabling. */
4879                 ironlake_fdi_pll_enable(intel_crtc);
4880         } else {
4881                 assert_fdi_tx_disabled(dev_priv, pipe);
4882                 assert_fdi_rx_disabled(dev_priv, pipe);
4883         }
4884
4885         ironlake_pfit_enable(intel_crtc);
4886
4887         /*
4888          * On ILK+ LUT must be loaded before the pipe is running but with
4889          * clocks enabled
4890          */
4891         intel_crtc_load_lut(crtc);
4892
4893         intel_update_watermarks(crtc);
4894         intel_enable_pipe(intel_crtc);
4895
4896         if (intel_crtc->config->has_pch_encoder)
4897                 ironlake_pch_enable(crtc);
4898
4899         assert_vblank_disabled(crtc);
4900         drm_crtc_vblank_on(crtc);
4901
4902         for_each_encoder_on_crtc(dev, crtc, encoder)
4903                 encoder->enable(encoder);
4904
4905         if (HAS_PCH_CPT(dev))
4906                 cpt_verify_modeset(dev, intel_crtc->pipe);
4907 }
4908
4909 /* IPS only exists on ULT machines and is tied to pipe A. */
4910 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4911 {
4912         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4913 }
4914
4915 static void haswell_crtc_enable(struct drm_crtc *crtc)
4916 {
4917         struct drm_device *dev = crtc->dev;
4918         struct drm_i915_private *dev_priv = dev->dev_private;
4919         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4920         struct intel_encoder *encoder;
4921         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4922         struct intel_crtc_state *pipe_config =
4923                 to_intel_crtc_state(crtc->state);
4924
4925         if (WARN_ON(intel_crtc->active))
4926                 return;
4927
4928         if (intel_crtc_to_shared_dpll(intel_crtc))
4929                 intel_enable_shared_dpll(intel_crtc);
4930
4931         if (intel_crtc->config->has_dp_encoder)
4932                 intel_dp_set_m_n(intel_crtc, M1_N1);
4933
4934         intel_set_pipe_timings(intel_crtc);
4935
4936         if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4937                 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4938                            intel_crtc->config->pixel_multiplier - 1);
4939         }
4940
4941         if (intel_crtc->config->has_pch_encoder) {
4942                 intel_cpu_transcoder_set_m_n(intel_crtc,
4943                                      &intel_crtc->config->fdi_m_n, NULL);
4944         }
4945
4946         haswell_set_pipeconf(crtc);
4947
4948         intel_set_pipe_csc(crtc);
4949
4950         intel_crtc->active = true;
4951
4952         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4953         for_each_encoder_on_crtc(dev, crtc, encoder)
4954                 if (encoder->pre_enable)
4955                         encoder->pre_enable(encoder);
4956
4957         if (intel_crtc->config->has_pch_encoder) {
4958                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4959                                                       true);
4960                 dev_priv->display.fdi_link_train(crtc);
4961         }
4962
4963         intel_ddi_enable_pipe_clock(intel_crtc);
4964
4965         if (INTEL_INFO(dev)->gen >= 9)
4966                 skylake_pfit_enable(intel_crtc);
4967         else
4968                 ironlake_pfit_enable(intel_crtc);
4969
4970         /*
4971          * On ILK+ LUT must be loaded before the pipe is running but with
4972          * clocks enabled
4973          */
4974         intel_crtc_load_lut(crtc);
4975
4976         intel_ddi_set_pipe_settings(crtc);
4977         intel_ddi_enable_transcoder_func(crtc);
4978
4979         intel_update_watermarks(crtc);
4980         intel_enable_pipe(intel_crtc);
4981
4982         if (intel_crtc->config->has_pch_encoder)
4983                 lpt_pch_enable(crtc);
4984
4985         if (intel_crtc->config->dp_encoder_is_mst)
4986                 intel_ddi_set_vc_payload_alloc(crtc, true);
4987
4988         assert_vblank_disabled(crtc);
4989         drm_crtc_vblank_on(crtc);
4990
4991         for_each_encoder_on_crtc(dev, crtc, encoder) {
4992                 encoder->enable(encoder);
4993                 intel_opregion_notify_encoder(encoder, true);
4994         }
4995
4996         /* If we change the relative order between pipe/planes enabling, we need
4997          * to change the workaround. */
4998         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4999         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5000                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5001                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5002         }
5003 }
5004
5005 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5006 {
5007         struct drm_device *dev = crtc->base.dev;
5008         struct drm_i915_private *dev_priv = dev->dev_private;
5009         int pipe = crtc->pipe;
5010
5011         /* To avoid upsetting the power well on haswell only disable the pfit if
5012          * it's in use. The hw state code will make sure we get this right. */
5013         if (force || crtc->config->pch_pfit.enabled) {
5014                 I915_WRITE(PF_CTL(pipe), 0);
5015                 I915_WRITE(PF_WIN_POS(pipe), 0);
5016                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5017         }
5018 }
5019
5020 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5021 {
5022         struct drm_device *dev = crtc->dev;
5023         struct drm_i915_private *dev_priv = dev->dev_private;
5024         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5025         struct intel_encoder *encoder;
5026         int pipe = intel_crtc->pipe;
5027         u32 reg, temp;
5028
5029         for_each_encoder_on_crtc(dev, crtc, encoder)
5030                 encoder->disable(encoder);
5031
5032         drm_crtc_vblank_off(crtc);
5033         assert_vblank_disabled(crtc);
5034
5035         if (intel_crtc->config->has_pch_encoder)
5036                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5037
5038         intel_disable_pipe(intel_crtc);
5039
5040         ironlake_pfit_disable(intel_crtc, false);
5041
5042         if (intel_crtc->config->has_pch_encoder)
5043                 ironlake_fdi_disable(crtc);
5044
5045         for_each_encoder_on_crtc(dev, crtc, encoder)
5046                 if (encoder->post_disable)
5047                         encoder->post_disable(encoder);
5048
5049         if (intel_crtc->config->has_pch_encoder) {
5050                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5051
5052                 if (HAS_PCH_CPT(dev)) {
5053                         /* disable TRANS_DP_CTL */
5054                         reg = TRANS_DP_CTL(pipe);
5055                         temp = I915_READ(reg);
5056                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5057                                   TRANS_DP_PORT_SEL_MASK);
5058                         temp |= TRANS_DP_PORT_SEL_NONE;
5059                         I915_WRITE(reg, temp);
5060
5061                         /* disable DPLL_SEL */
5062                         temp = I915_READ(PCH_DPLL_SEL);
5063                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5064                         I915_WRITE(PCH_DPLL_SEL, temp);
5065                 }
5066
5067                 ironlake_fdi_pll_disable(intel_crtc);
5068         }
5069
5070         intel_crtc->active = false;
5071         intel_update_watermarks(crtc);
5072 }
5073
5074 static void haswell_crtc_disable(struct drm_crtc *crtc)
5075 {
5076         struct drm_device *dev = crtc->dev;
5077         struct drm_i915_private *dev_priv = dev->dev_private;
5078         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5079         struct intel_encoder *encoder;
5080         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5081
5082         for_each_encoder_on_crtc(dev, crtc, encoder) {
5083                 intel_opregion_notify_encoder(encoder, false);
5084                 encoder->disable(encoder);
5085         }
5086
5087         drm_crtc_vblank_off(crtc);
5088         assert_vblank_disabled(crtc);
5089
5090         if (intel_crtc->config->has_pch_encoder)
5091                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5092                                                       false);
5093         intel_disable_pipe(intel_crtc);
5094
5095         if (intel_crtc->config->dp_encoder_is_mst)
5096                 intel_ddi_set_vc_payload_alloc(crtc, false);
5097
5098         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5099
5100         if (INTEL_INFO(dev)->gen >= 9)
5101                 skylake_scaler_disable(intel_crtc);
5102         else
5103                 ironlake_pfit_disable(intel_crtc, false);
5104
5105         intel_ddi_disable_pipe_clock(intel_crtc);
5106
5107         if (intel_crtc->config->has_pch_encoder) {
5108                 lpt_disable_pch_transcoder(dev_priv);
5109                 intel_ddi_fdi_disable(crtc);
5110         }
5111
5112         for_each_encoder_on_crtc(dev, crtc, encoder)
5113                 if (encoder->post_disable)
5114                         encoder->post_disable(encoder);
5115
5116         intel_crtc->active = false;
5117         intel_update_watermarks(crtc);
5118 }
5119
5120 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5121 {
5122         struct drm_device *dev = crtc->base.dev;
5123         struct drm_i915_private *dev_priv = dev->dev_private;
5124         struct intel_crtc_state *pipe_config = crtc->config;
5125
5126         if (!pipe_config->gmch_pfit.control)
5127                 return;
5128
5129         /*
5130          * The panel fitter should only be adjusted whilst the pipe is disabled,
5131          * according to register description and PRM.
5132          */
5133         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5134         assert_pipe_disabled(dev_priv, crtc->pipe);
5135
5136         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5137         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5138
5139         /* Border color in case we don't scale up to the full screen. Black by
5140          * default, change to something else for debugging. */
5141         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5142 }
5143
5144 static enum intel_display_power_domain port_to_power_domain(enum port port)
5145 {
5146         switch (port) {
5147         case PORT_A:
5148                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5149         case PORT_B:
5150                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5151         case PORT_C:
5152                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5153         case PORT_D:
5154                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5155         case PORT_E:
5156                 return POWER_DOMAIN_PORT_DDI_E_2_LANES;
5157         default:
5158                 WARN_ON_ONCE(1);
5159                 return POWER_DOMAIN_PORT_OTHER;
5160         }
5161 }
5162
5163 #define for_each_power_domain(domain, mask)                             \
5164         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
5165                 if ((1 << (domain)) & (mask))
5166
5167 enum intel_display_power_domain
5168 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5169 {
5170         struct drm_device *dev = intel_encoder->base.dev;
5171         struct intel_digital_port *intel_dig_port;
5172
5173         switch (intel_encoder->type) {
5174         case INTEL_OUTPUT_UNKNOWN:
5175                 /* Only DDI platforms should ever use this output type */
5176                 WARN_ON_ONCE(!HAS_DDI(dev));
5177         case INTEL_OUTPUT_DISPLAYPORT:
5178         case INTEL_OUTPUT_HDMI:
5179         case INTEL_OUTPUT_EDP:
5180                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5181                 return port_to_power_domain(intel_dig_port->port);
5182         case INTEL_OUTPUT_DP_MST:
5183                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5184                 return port_to_power_domain(intel_dig_port->port);
5185         case INTEL_OUTPUT_ANALOG:
5186                 return POWER_DOMAIN_PORT_CRT;
5187         case INTEL_OUTPUT_DSI:
5188                 return POWER_DOMAIN_PORT_DSI;
5189         default:
5190                 return POWER_DOMAIN_PORT_OTHER;
5191         }
5192 }
5193
5194 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5195 {
5196         struct drm_device *dev = crtc->dev;
5197         struct intel_encoder *intel_encoder;
5198         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5199         enum pipe pipe = intel_crtc->pipe;
5200         unsigned long mask;
5201         enum transcoder transcoder;
5202
5203         if (!crtc->state->active)
5204                 return 0;
5205
5206         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5207
5208         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5209         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5210         if (intel_crtc->config->pch_pfit.enabled ||
5211             intel_crtc->config->pch_pfit.force_thru)
5212                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5213
5214         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5215                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5216
5217         return mask;
5218 }
5219
5220 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5221 {
5222         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5223         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5224         enum intel_display_power_domain domain;
5225         unsigned long domains, new_domains, old_domains;
5226
5227         old_domains = intel_crtc->enabled_power_domains;
5228         intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5229
5230         domains = new_domains & ~old_domains;
5231
5232         for_each_power_domain(domain, domains)
5233                 intel_display_power_get(dev_priv, domain);
5234
5235         return old_domains & ~new_domains;
5236 }
5237
5238 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5239                                       unsigned long domains)
5240 {
5241         enum intel_display_power_domain domain;
5242
5243         for_each_power_domain(domain, domains)
5244                 intel_display_power_put(dev_priv, domain);
5245 }
5246
5247 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5248 {
5249         struct drm_device *dev = state->dev;
5250         struct drm_i915_private *dev_priv = dev->dev_private;
5251         unsigned long put_domains[I915_MAX_PIPES] = {};
5252         struct drm_crtc_state *crtc_state;
5253         struct drm_crtc *crtc;
5254         int i;
5255
5256         for_each_crtc_in_state(state, crtc, crtc_state, i) {
5257                 if (needs_modeset(crtc->state))
5258                         put_domains[to_intel_crtc(crtc)->pipe] =
5259                                 modeset_get_crtc_power_domains(crtc);
5260         }
5261
5262         if (dev_priv->display.modeset_commit_cdclk) {
5263                 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5264
5265                 if (cdclk != dev_priv->cdclk_freq &&
5266                     !WARN_ON(!state->allow_modeset))
5267                         dev_priv->display.modeset_commit_cdclk(state);
5268         }
5269
5270         for (i = 0; i < I915_MAX_PIPES; i++)
5271                 if (put_domains[i])
5272                         modeset_put_power_domains(dev_priv, put_domains[i]);
5273 }
5274
5275 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5276 {
5277         int max_cdclk_freq = dev_priv->max_cdclk_freq;
5278
5279         if (INTEL_INFO(dev_priv)->gen >= 9 ||
5280             IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5281                 return max_cdclk_freq;
5282         else if (IS_CHERRYVIEW(dev_priv))
5283                 return max_cdclk_freq*95/100;
5284         else if (INTEL_INFO(dev_priv)->gen < 4)
5285                 return 2*max_cdclk_freq*90/100;
5286         else
5287                 return max_cdclk_freq*90/100;
5288 }
5289
5290 static void intel_update_max_cdclk(struct drm_device *dev)
5291 {
5292         struct drm_i915_private *dev_priv = dev->dev_private;
5293
5294         if (IS_SKYLAKE(dev)) {
5295                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5296
5297                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5298                         dev_priv->max_cdclk_freq = 675000;
5299                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5300                         dev_priv->max_cdclk_freq = 540000;
5301                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5302                         dev_priv->max_cdclk_freq = 450000;
5303                 else
5304                         dev_priv->max_cdclk_freq = 337500;
5305         } else if (IS_BROADWELL(dev))  {
5306                 /*
5307                  * FIXME with extra cooling we can allow
5308                  * 540 MHz for ULX and 675 Mhz for ULT.
5309                  * How can we know if extra cooling is
5310                  * available? PCI ID, VTB, something else?
5311                  */
5312                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5313                         dev_priv->max_cdclk_freq = 450000;
5314                 else if (IS_BDW_ULX(dev))
5315                         dev_priv->max_cdclk_freq = 450000;
5316                 else if (IS_BDW_ULT(dev))
5317                         dev_priv->max_cdclk_freq = 540000;
5318                 else
5319                         dev_priv->max_cdclk_freq = 675000;
5320         } else if (IS_CHERRYVIEW(dev)) {
5321                 dev_priv->max_cdclk_freq = 320000;
5322         } else if (IS_VALLEYVIEW(dev)) {
5323                 dev_priv->max_cdclk_freq = 400000;
5324         } else {
5325                 /* otherwise assume cdclk is fixed */
5326                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5327         }
5328
5329         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5330
5331         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5332                          dev_priv->max_cdclk_freq);
5333
5334         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5335                          dev_priv->max_dotclk_freq);
5336 }
5337
5338 static void intel_update_cdclk(struct drm_device *dev)
5339 {
5340         struct drm_i915_private *dev_priv = dev->dev_private;
5341
5342         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5343         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5344                          dev_priv->cdclk_freq);
5345
5346         /*
5347          * Program the gmbus_freq based on the cdclk frequency.
5348          * BSpec erroneously claims we should aim for 4MHz, but
5349          * in fact 1MHz is the correct frequency.
5350          */
5351         if (IS_VALLEYVIEW(dev)) {
5352                 /*
5353                  * Program the gmbus_freq based on the cdclk frequency.
5354                  * BSpec erroneously claims we should aim for 4MHz, but
5355                  * in fact 1MHz is the correct frequency.
5356                  */
5357                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5358         }
5359
5360         if (dev_priv->max_cdclk_freq == 0)
5361                 intel_update_max_cdclk(dev);
5362 }
5363
5364 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5365 {
5366         struct drm_i915_private *dev_priv = dev->dev_private;
5367         uint32_t divider;
5368         uint32_t ratio;
5369         uint32_t current_freq;
5370         int ret;
5371
5372         /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5373         switch (frequency) {
5374         case 144000:
5375                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5376                 ratio = BXT_DE_PLL_RATIO(60);
5377                 break;
5378         case 288000:
5379                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5380                 ratio = BXT_DE_PLL_RATIO(60);
5381                 break;
5382         case 384000:
5383                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5384                 ratio = BXT_DE_PLL_RATIO(60);
5385                 break;
5386         case 576000:
5387                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5388                 ratio = BXT_DE_PLL_RATIO(60);
5389                 break;
5390         case 624000:
5391                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5392                 ratio = BXT_DE_PLL_RATIO(65);
5393                 break;
5394         case 19200:
5395                 /*
5396                  * Bypass frequency with DE PLL disabled. Init ratio, divider
5397                  * to suppress GCC warning.
5398                  */
5399                 ratio = 0;
5400                 divider = 0;
5401                 break;
5402         default:
5403                 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5404
5405                 return;
5406         }
5407
5408         mutex_lock(&dev_priv->rps.hw_lock);
5409         /* Inform power controller of upcoming frequency change */
5410         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5411                                       0x80000000);
5412         mutex_unlock(&dev_priv->rps.hw_lock);
5413
5414         if (ret) {
5415                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5416                           ret, frequency);
5417                 return;
5418         }
5419
5420         current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5421         /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5422         current_freq = current_freq * 500 + 1000;
5423
5424         /*
5425          * DE PLL has to be disabled when
5426          * - setting to 19.2MHz (bypass, PLL isn't used)
5427          * - before setting to 624MHz (PLL needs toggling)
5428          * - before setting to any frequency from 624MHz (PLL needs toggling)
5429          */
5430         if (frequency == 19200 || frequency == 624000 ||
5431             current_freq == 624000) {
5432                 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5433                 /* Timeout 200us */
5434                 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5435                              1))
5436                         DRM_ERROR("timout waiting for DE PLL unlock\n");
5437         }
5438
5439         if (frequency != 19200) {
5440                 uint32_t val;
5441
5442                 val = I915_READ(BXT_DE_PLL_CTL);
5443                 val &= ~BXT_DE_PLL_RATIO_MASK;
5444                 val |= ratio;
5445                 I915_WRITE(BXT_DE_PLL_CTL, val);
5446
5447                 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5448                 /* Timeout 200us */
5449                 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5450                         DRM_ERROR("timeout waiting for DE PLL lock\n");
5451
5452                 val = I915_READ(CDCLK_CTL);
5453                 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5454                 val |= divider;
5455                 /*
5456                  * Disable SSA Precharge when CD clock frequency < 500 MHz,
5457                  * enable otherwise.
5458                  */
5459                 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5460                 if (frequency >= 500000)
5461                         val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5462
5463                 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5464                 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5465                 val |= (frequency - 1000) / 500;
5466                 I915_WRITE(CDCLK_CTL, val);
5467         }
5468
5469         mutex_lock(&dev_priv->rps.hw_lock);
5470         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5471                                       DIV_ROUND_UP(frequency, 25000));
5472         mutex_unlock(&dev_priv->rps.hw_lock);
5473
5474         if (ret) {
5475                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5476                           ret, frequency);
5477                 return;
5478         }
5479
5480         intel_update_cdclk(dev);
5481 }
5482
5483 void broxton_init_cdclk(struct drm_device *dev)
5484 {
5485         struct drm_i915_private *dev_priv = dev->dev_private;
5486         uint32_t val;
5487
5488         /*
5489          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5490          * or else the reset will hang because there is no PCH to respond.
5491          * Move the handshake programming to initialization sequence.
5492          * Previously was left up to BIOS.
5493          */
5494         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5495         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5496         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5497
5498         /* Enable PG1 for cdclk */
5499         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5500
5501         /* check if cd clock is enabled */
5502         if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5503                 DRM_DEBUG_KMS("Display already initialized\n");
5504                 return;
5505         }
5506
5507         /*
5508          * FIXME:
5509          * - The initial CDCLK needs to be read from VBT.
5510          *   Need to make this change after VBT has changes for BXT.
5511          * - check if setting the max (or any) cdclk freq is really necessary
5512          *   here, it belongs to modeset time
5513          */
5514         broxton_set_cdclk(dev, 624000);
5515
5516         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5517         POSTING_READ(DBUF_CTL);
5518
5519         udelay(10);
5520
5521         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5522                 DRM_ERROR("DBuf power enable timeout!\n");
5523 }
5524
5525 void broxton_uninit_cdclk(struct drm_device *dev)
5526 {
5527         struct drm_i915_private *dev_priv = dev->dev_private;
5528
5529         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5530         POSTING_READ(DBUF_CTL);
5531
5532         udelay(10);
5533
5534         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5535                 DRM_ERROR("DBuf power disable timeout!\n");
5536
5537         /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5538         broxton_set_cdclk(dev, 19200);
5539
5540         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5541 }
5542
5543 static const struct skl_cdclk_entry {
5544         unsigned int freq;
5545         unsigned int vco;
5546 } skl_cdclk_frequencies[] = {
5547         { .freq = 308570, .vco = 8640 },
5548         { .freq = 337500, .vco = 8100 },
5549         { .freq = 432000, .vco = 8640 },
5550         { .freq = 450000, .vco = 8100 },
5551         { .freq = 540000, .vco = 8100 },
5552         { .freq = 617140, .vco = 8640 },
5553         { .freq = 675000, .vco = 8100 },
5554 };
5555
5556 static unsigned int skl_cdclk_decimal(unsigned int freq)
5557 {
5558         return (freq - 1000) / 500;
5559 }
5560
5561 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5562 {
5563         unsigned int i;
5564
5565         for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5566                 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5567
5568                 if (e->freq == freq)
5569                         return e->vco;
5570         }
5571
5572         return 8100;
5573 }
5574
5575 static void
5576 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5577 {
5578         unsigned int min_freq;
5579         u32 val;
5580
5581         /* select the minimum CDCLK before enabling DPLL 0 */
5582         val = I915_READ(CDCLK_CTL);
5583         val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5584         val |= CDCLK_FREQ_337_308;
5585
5586         if (required_vco == 8640)
5587                 min_freq = 308570;
5588         else
5589                 min_freq = 337500;
5590
5591         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5592
5593         I915_WRITE(CDCLK_CTL, val);
5594         POSTING_READ(CDCLK_CTL);
5595
5596         /*
5597          * We always enable DPLL0 with the lowest link rate possible, but still
5598          * taking into account the VCO required to operate the eDP panel at the
5599          * desired frequency. The usual DP link rates operate with a VCO of
5600          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5601          * The modeset code is responsible for the selection of the exact link
5602          * rate later on, with the constraint of choosing a frequency that
5603          * works with required_vco.
5604          */
5605         val = I915_READ(DPLL_CTRL1);
5606
5607         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5608                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5609         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5610         if (required_vco == 8640)
5611                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5612                                             SKL_DPLL0);
5613         else
5614                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5615                                             SKL_DPLL0);
5616
5617         I915_WRITE(DPLL_CTRL1, val);
5618         POSTING_READ(DPLL_CTRL1);
5619
5620         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5621
5622         if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5623                 DRM_ERROR("DPLL0 not locked\n");
5624 }
5625
5626 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5627 {
5628         int ret;
5629         u32 val;
5630
5631         /* inform PCU we want to change CDCLK */
5632         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5633         mutex_lock(&dev_priv->rps.hw_lock);
5634         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5635         mutex_unlock(&dev_priv->rps.hw_lock);
5636
5637         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5638 }
5639
5640 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5641 {
5642         unsigned int i;
5643
5644         for (i = 0; i < 15; i++) {
5645                 if (skl_cdclk_pcu_ready(dev_priv))
5646                         return true;
5647                 udelay(10);
5648         }
5649
5650         return false;
5651 }
5652
5653 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5654 {
5655         struct drm_device *dev = dev_priv->dev;
5656         u32 freq_select, pcu_ack;
5657
5658         DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5659
5660         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5661                 DRM_ERROR("failed to inform PCU about cdclk change\n");
5662                 return;
5663         }
5664
5665         /* set CDCLK_CTL */
5666         switch(freq) {
5667         case 450000:
5668         case 432000:
5669                 freq_select = CDCLK_FREQ_450_432;
5670                 pcu_ack = 1;
5671                 break;
5672         case 540000:
5673                 freq_select = CDCLK_FREQ_540;
5674                 pcu_ack = 2;
5675                 break;
5676         case 308570:
5677         case 337500:
5678         default:
5679                 freq_select = CDCLK_FREQ_337_308;
5680                 pcu_ack = 0;
5681                 break;
5682         case 617140:
5683         case 675000:
5684                 freq_select = CDCLK_FREQ_675_617;
5685                 pcu_ack = 3;
5686                 break;
5687         }
5688
5689         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5690         POSTING_READ(CDCLK_CTL);
5691
5692         /* inform PCU of the change */
5693         mutex_lock(&dev_priv->rps.hw_lock);
5694         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5695         mutex_unlock(&dev_priv->rps.hw_lock);
5696
5697         intel_update_cdclk(dev);
5698 }
5699
5700 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5701 {
5702         /* disable DBUF power */
5703         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5704         POSTING_READ(DBUF_CTL);
5705
5706         udelay(10);
5707
5708         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5709                 DRM_ERROR("DBuf power disable timeout\n");
5710
5711         /*
5712          * DMC assumes ownership of LCPLL and will get confused if we touch it.
5713          */
5714         if (dev_priv->csr.dmc_payload) {
5715                 /* disable DPLL0 */
5716                 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) &
5717                                         ~LCPLL_PLL_ENABLE);
5718                 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5719                         DRM_ERROR("Couldn't disable DPLL0\n");
5720         }
5721
5722         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5723 }
5724
5725 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5726 {
5727         u32 val;
5728         unsigned int required_vco;
5729
5730         /* enable PCH reset handshake */
5731         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5732         I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5733
5734         /* enable PG1 and Misc I/O */
5735         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5736
5737         /* DPLL0 not enabled (happens on early BIOS versions) */
5738         if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5739                 /* enable DPLL0 */
5740                 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5741                 skl_dpll0_enable(dev_priv, required_vco);
5742         }
5743
5744         /* set CDCLK to the frequency the BIOS chose */
5745         skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5746
5747         /* enable DBUF power */
5748         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5749         POSTING_READ(DBUF_CTL);
5750
5751         udelay(10);
5752
5753         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5754                 DRM_ERROR("DBuf power enable timeout\n");
5755 }
5756
5757 /* returns HPLL frequency in kHz */
5758 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5759 {
5760         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5761
5762         /* Obtain SKU information */
5763         mutex_lock(&dev_priv->sb_lock);
5764         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5765                 CCK_FUSE_HPLL_FREQ_MASK;
5766         mutex_unlock(&dev_priv->sb_lock);
5767
5768         return vco_freq[hpll_freq] * 1000;
5769 }
5770
5771 /* Adjust CDclk dividers to allow high res or save power if possible */
5772 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5773 {
5774         struct drm_i915_private *dev_priv = dev->dev_private;
5775         u32 val, cmd;
5776
5777         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5778                                         != dev_priv->cdclk_freq);
5779
5780         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5781                 cmd = 2;
5782         else if (cdclk == 266667)
5783                 cmd = 1;
5784         else
5785                 cmd = 0;
5786
5787         mutex_lock(&dev_priv->rps.hw_lock);
5788         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5789         val &= ~DSPFREQGUAR_MASK;
5790         val |= (cmd << DSPFREQGUAR_SHIFT);
5791         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5792         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5793                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5794                      50)) {
5795                 DRM_ERROR("timed out waiting for CDclk change\n");
5796         }
5797         mutex_unlock(&dev_priv->rps.hw_lock);
5798
5799         mutex_lock(&dev_priv->sb_lock);
5800
5801         if (cdclk == 400000) {
5802                 u32 divider;
5803
5804                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5805
5806                 /* adjust cdclk divider */
5807                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5808                 val &= ~DISPLAY_FREQUENCY_VALUES;
5809                 val |= divider;
5810                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5811
5812                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5813                               DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5814                              50))
5815                         DRM_ERROR("timed out waiting for CDclk change\n");
5816         }
5817
5818         /* adjust self-refresh exit latency value */
5819         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5820         val &= ~0x7f;
5821
5822         /*
5823          * For high bandwidth configs, we set a higher latency in the bunit
5824          * so that the core display fetch happens in time to avoid underruns.
5825          */
5826         if (cdclk == 400000)
5827                 val |= 4500 / 250; /* 4.5 usec */
5828         else
5829                 val |= 3000 / 250; /* 3.0 usec */
5830         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5831
5832         mutex_unlock(&dev_priv->sb_lock);
5833
5834         intel_update_cdclk(dev);
5835 }
5836
5837 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5838 {
5839         struct drm_i915_private *dev_priv = dev->dev_private;
5840         u32 val, cmd;
5841
5842         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5843                                                 != dev_priv->cdclk_freq);
5844
5845         switch (cdclk) {
5846         case 333333:
5847         case 320000:
5848         case 266667:
5849         case 200000:
5850                 break;
5851         default:
5852                 MISSING_CASE(cdclk);
5853                 return;
5854         }
5855
5856         /*
5857          * Specs are full of misinformation, but testing on actual
5858          * hardware has shown that we just need to write the desired
5859          * CCK divider into the Punit register.
5860          */
5861         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5862
5863         mutex_lock(&dev_priv->rps.hw_lock);
5864         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5865         val &= ~DSPFREQGUAR_MASK_CHV;
5866         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5867         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5868         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5869                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5870                      50)) {
5871                 DRM_ERROR("timed out waiting for CDclk change\n");
5872         }
5873         mutex_unlock(&dev_priv->rps.hw_lock);
5874
5875         intel_update_cdclk(dev);
5876 }
5877
5878 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5879                                  int max_pixclk)
5880 {
5881         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
5882         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5883
5884         /*
5885          * Really only a few cases to deal with, as only 4 CDclks are supported:
5886          *   200MHz
5887          *   267MHz
5888          *   320/333MHz (depends on HPLL freq)
5889          *   400MHz (VLV only)
5890          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5891          * of the lower bin and adjust if needed.
5892          *
5893          * We seem to get an unstable or solid color picture at 200MHz.
5894          * Not sure what's wrong. For now use 200MHz only when all pipes
5895          * are off.
5896          */
5897         if (!IS_CHERRYVIEW(dev_priv) &&
5898             max_pixclk > freq_320*limit/100)
5899                 return 400000;
5900         else if (max_pixclk > 266667*limit/100)
5901                 return freq_320;
5902         else if (max_pixclk > 0)
5903                 return 266667;
5904         else
5905                 return 200000;
5906 }
5907
5908 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5909                               int max_pixclk)
5910 {
5911         /*
5912          * FIXME:
5913          * - remove the guardband, it's not needed on BXT
5914          * - set 19.2MHz bypass frequency if there are no active pipes
5915          */
5916         if (max_pixclk > 576000*9/10)
5917                 return 624000;
5918         else if (max_pixclk > 384000*9/10)
5919                 return 576000;
5920         else if (max_pixclk > 288000*9/10)
5921                 return 384000;
5922         else if (max_pixclk > 144000*9/10)
5923                 return 288000;
5924         else
5925                 return 144000;
5926 }
5927
5928 /* Compute the max pixel clock for new configuration. Uses atomic state if
5929  * that's non-NULL, look at current state otherwise. */
5930 static int intel_mode_max_pixclk(struct drm_device *dev,
5931                                  struct drm_atomic_state *state)
5932 {
5933         struct intel_crtc *intel_crtc;
5934         struct intel_crtc_state *crtc_state;
5935         int max_pixclk = 0;
5936
5937         for_each_intel_crtc(dev, intel_crtc) {
5938                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5939                 if (IS_ERR(crtc_state))
5940                         return PTR_ERR(crtc_state);
5941
5942                 if (!crtc_state->base.enable)
5943                         continue;
5944
5945                 max_pixclk = max(max_pixclk,
5946                                  crtc_state->base.adjusted_mode.crtc_clock);
5947         }
5948
5949         return max_pixclk;
5950 }
5951
5952 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5953 {
5954         struct drm_device *dev = state->dev;
5955         struct drm_i915_private *dev_priv = dev->dev_private;
5956         int max_pixclk = intel_mode_max_pixclk(dev, state);
5957
5958         if (max_pixclk < 0)
5959                 return max_pixclk;
5960
5961         to_intel_atomic_state(state)->cdclk =
5962                 valleyview_calc_cdclk(dev_priv, max_pixclk);
5963
5964         return 0;
5965 }
5966
5967 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5968 {
5969         struct drm_device *dev = state->dev;
5970         struct drm_i915_private *dev_priv = dev->dev_private;
5971         int max_pixclk = intel_mode_max_pixclk(dev, state);
5972
5973         if (max_pixclk < 0)
5974                 return max_pixclk;
5975
5976         to_intel_atomic_state(state)->cdclk =
5977                 broxton_calc_cdclk(dev_priv, max_pixclk);
5978
5979         return 0;
5980 }
5981
5982 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5983 {
5984         unsigned int credits, default_credits;
5985
5986         if (IS_CHERRYVIEW(dev_priv))
5987                 default_credits = PFI_CREDIT(12);
5988         else
5989                 default_credits = PFI_CREDIT(8);
5990
5991         if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5992                 /* CHV suggested value is 31 or 63 */
5993                 if (IS_CHERRYVIEW(dev_priv))
5994                         credits = PFI_CREDIT_63;
5995                 else
5996                         credits = PFI_CREDIT(15);
5997         } else {
5998                 credits = default_credits;
5999         }
6000
6001         /*
6002          * WA - write default credits before re-programming
6003          * FIXME: should we also set the resend bit here?
6004          */
6005         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6006                    default_credits);
6007
6008         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6009                    credits | PFI_CREDIT_RESEND);
6010
6011         /*
6012          * FIXME is this guaranteed to clear
6013          * immediately or should we poll for it?
6014          */
6015         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6016 }
6017
6018 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6019 {
6020         struct drm_device *dev = old_state->dev;
6021         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
6022         struct drm_i915_private *dev_priv = dev->dev_private;
6023
6024         /*
6025          * FIXME: We can end up here with all power domains off, yet
6026          * with a CDCLK frequency other than the minimum. To account
6027          * for this take the PIPE-A power domain, which covers the HW
6028          * blocks needed for the following programming. This can be
6029          * removed once it's guaranteed that we get here either with
6030          * the minimum CDCLK set, or the required power domains
6031          * enabled.
6032          */
6033         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6034
6035         if (IS_CHERRYVIEW(dev))
6036                 cherryview_set_cdclk(dev, req_cdclk);
6037         else
6038                 valleyview_set_cdclk(dev, req_cdclk);
6039
6040         vlv_program_pfi_credits(dev_priv);
6041
6042         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6043 }
6044
6045 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6046 {
6047         struct drm_device *dev = crtc->dev;
6048         struct drm_i915_private *dev_priv = to_i915(dev);
6049         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6050         struct intel_encoder *encoder;
6051         int pipe = intel_crtc->pipe;
6052         bool is_dsi;
6053
6054         if (WARN_ON(intel_crtc->active))
6055                 return;
6056
6057         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6058
6059         if (intel_crtc->config->has_dp_encoder)
6060                 intel_dp_set_m_n(intel_crtc, M1_N1);
6061
6062         intel_set_pipe_timings(intel_crtc);
6063
6064         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6065                 struct drm_i915_private *dev_priv = dev->dev_private;
6066
6067                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6068                 I915_WRITE(CHV_CANVAS(pipe), 0);
6069         }
6070
6071         i9xx_set_pipeconf(intel_crtc);
6072
6073         intel_crtc->active = true;
6074
6075         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6076
6077         for_each_encoder_on_crtc(dev, crtc, encoder)
6078                 if (encoder->pre_pll_enable)
6079                         encoder->pre_pll_enable(encoder);
6080
6081         if (!is_dsi) {
6082                 if (IS_CHERRYVIEW(dev)) {
6083                         chv_prepare_pll(intel_crtc, intel_crtc->config);
6084                         chv_enable_pll(intel_crtc, intel_crtc->config);
6085                 } else {
6086                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
6087                         vlv_enable_pll(intel_crtc, intel_crtc->config);
6088                 }
6089         }
6090
6091         for_each_encoder_on_crtc(dev, crtc, encoder)
6092                 if (encoder->pre_enable)
6093                         encoder->pre_enable(encoder);
6094
6095         i9xx_pfit_enable(intel_crtc);
6096
6097         intel_crtc_load_lut(crtc);
6098
6099         intel_enable_pipe(intel_crtc);
6100
6101         assert_vblank_disabled(crtc);
6102         drm_crtc_vblank_on(crtc);
6103
6104         for_each_encoder_on_crtc(dev, crtc, encoder)
6105                 encoder->enable(encoder);
6106 }
6107
6108 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6109 {
6110         struct drm_device *dev = crtc->base.dev;
6111         struct drm_i915_private *dev_priv = dev->dev_private;
6112
6113         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6114         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6115 }
6116
6117 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6118 {
6119         struct drm_device *dev = crtc->dev;
6120         struct drm_i915_private *dev_priv = to_i915(dev);
6121         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6122         struct intel_encoder *encoder;
6123         int pipe = intel_crtc->pipe;
6124
6125         if (WARN_ON(intel_crtc->active))
6126                 return;
6127
6128         i9xx_set_pll_dividers(intel_crtc);
6129
6130         if (intel_crtc->config->has_dp_encoder)
6131                 intel_dp_set_m_n(intel_crtc, M1_N1);
6132
6133         intel_set_pipe_timings(intel_crtc);
6134
6135         i9xx_set_pipeconf(intel_crtc);
6136
6137         intel_crtc->active = true;
6138
6139         if (!IS_GEN2(dev))
6140                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6141
6142         for_each_encoder_on_crtc(dev, crtc, encoder)
6143                 if (encoder->pre_enable)
6144                         encoder->pre_enable(encoder);
6145
6146         i9xx_enable_pll(intel_crtc);
6147
6148         i9xx_pfit_enable(intel_crtc);
6149
6150         intel_crtc_load_lut(crtc);
6151
6152         intel_update_watermarks(crtc);
6153         intel_enable_pipe(intel_crtc);
6154
6155         assert_vblank_disabled(crtc);
6156         drm_crtc_vblank_on(crtc);
6157
6158         for_each_encoder_on_crtc(dev, crtc, encoder)
6159                 encoder->enable(encoder);
6160 }
6161
6162 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6163 {
6164         struct drm_device *dev = crtc->base.dev;
6165         struct drm_i915_private *dev_priv = dev->dev_private;
6166
6167         if (!crtc->config->gmch_pfit.control)
6168                 return;
6169
6170         assert_pipe_disabled(dev_priv, crtc->pipe);
6171
6172         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6173                          I915_READ(PFIT_CONTROL));
6174         I915_WRITE(PFIT_CONTROL, 0);
6175 }
6176
6177 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6178 {
6179         struct drm_device *dev = crtc->dev;
6180         struct drm_i915_private *dev_priv = dev->dev_private;
6181         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6182         struct intel_encoder *encoder;
6183         int pipe = intel_crtc->pipe;
6184
6185         /*
6186          * On gen2 planes are double buffered but the pipe isn't, so we must
6187          * wait for planes to fully turn off before disabling the pipe.
6188          * We also need to wait on all gmch platforms because of the
6189          * self-refresh mode constraint explained above.
6190          */
6191         intel_wait_for_vblank(dev, pipe);
6192
6193         for_each_encoder_on_crtc(dev, crtc, encoder)
6194                 encoder->disable(encoder);
6195
6196         drm_crtc_vblank_off(crtc);
6197         assert_vblank_disabled(crtc);
6198
6199         intel_disable_pipe(intel_crtc);
6200
6201         i9xx_pfit_disable(intel_crtc);
6202
6203         for_each_encoder_on_crtc(dev, crtc, encoder)
6204                 if (encoder->post_disable)
6205                         encoder->post_disable(encoder);
6206
6207         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6208                 if (IS_CHERRYVIEW(dev))
6209                         chv_disable_pll(dev_priv, pipe);
6210                 else if (IS_VALLEYVIEW(dev))
6211                         vlv_disable_pll(dev_priv, pipe);
6212                 else
6213                         i9xx_disable_pll(intel_crtc);
6214         }
6215
6216         for_each_encoder_on_crtc(dev, crtc, encoder)
6217                 if (encoder->post_pll_disable)
6218                         encoder->post_pll_disable(encoder);
6219
6220         if (!IS_GEN2(dev))
6221                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6222
6223         intel_crtc->active = false;
6224         intel_update_watermarks(crtc);
6225 }
6226
6227 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6228 {
6229         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6230         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6231         enum intel_display_power_domain domain;
6232         unsigned long domains;
6233
6234         if (!intel_crtc->active)
6235                 return;
6236
6237         if (to_intel_plane_state(crtc->primary->state)->visible) {
6238                 intel_crtc_wait_for_pending_flips(crtc);
6239                 intel_pre_disable_primary(crtc);
6240         }
6241
6242         intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
6243         dev_priv->display.crtc_disable(crtc);
6244         intel_disable_shared_dpll(intel_crtc);
6245
6246         domains = intel_crtc->enabled_power_domains;
6247         for_each_power_domain(domain, domains)
6248                 intel_display_power_put(dev_priv, domain);
6249         intel_crtc->enabled_power_domains = 0;
6250 }
6251
6252 /*
6253  * turn all crtc's off, but do not adjust state
6254  * This has to be paired with a call to intel_modeset_setup_hw_state.
6255  */
6256 int intel_display_suspend(struct drm_device *dev)
6257 {
6258         struct drm_mode_config *config = &dev->mode_config;
6259         struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6260         struct drm_atomic_state *state;
6261         struct drm_crtc *crtc;
6262         unsigned crtc_mask = 0;
6263         int ret = 0;
6264
6265         if (WARN_ON(!ctx))
6266                 return 0;
6267
6268         lockdep_assert_held(&ctx->ww_ctx);
6269         state = drm_atomic_state_alloc(dev);
6270         if (WARN_ON(!state))
6271                 return -ENOMEM;
6272
6273         state->acquire_ctx = ctx;
6274         state->allow_modeset = true;
6275
6276         for_each_crtc(dev, crtc) {
6277                 struct drm_crtc_state *crtc_state =
6278                         drm_atomic_get_crtc_state(state, crtc);
6279
6280                 ret = PTR_ERR_OR_ZERO(crtc_state);
6281                 if (ret)
6282                         goto free;
6283
6284                 if (!crtc_state->active)
6285                         continue;
6286
6287                 crtc_state->active = false;
6288                 crtc_mask |= 1 << drm_crtc_index(crtc);
6289         }
6290
6291         if (crtc_mask) {
6292                 ret = drm_atomic_commit(state);
6293
6294                 if (!ret) {
6295                         for_each_crtc(dev, crtc)
6296                                 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6297                                         crtc->state->active = true;
6298
6299                         return ret;
6300                 }
6301         }
6302
6303 free:
6304         if (ret)
6305                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6306         drm_atomic_state_free(state);
6307         return ret;
6308 }
6309
6310 void intel_encoder_destroy(struct drm_encoder *encoder)
6311 {
6312         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6313
6314         drm_encoder_cleanup(encoder);
6315         kfree(intel_encoder);
6316 }
6317
6318 /* Cross check the actual hw state with our own modeset state tracking (and it's
6319  * internal consistency). */
6320 static void intel_connector_check_state(struct intel_connector *connector)
6321 {
6322         struct drm_crtc *crtc = connector->base.state->crtc;
6323
6324         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6325                       connector->base.base.id,
6326                       connector->base.name);
6327
6328         if (connector->get_hw_state(connector)) {
6329                 struct intel_encoder *encoder = connector->encoder;
6330                 struct drm_connector_state *conn_state = connector->base.state;
6331
6332                 I915_STATE_WARN(!crtc,
6333                          "connector enabled without attached crtc\n");
6334
6335                 if (!crtc)
6336                         return;
6337
6338                 I915_STATE_WARN(!crtc->state->active,
6339                       "connector is active, but attached crtc isn't\n");
6340
6341                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6342                         return;
6343
6344                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6345                         "atomic encoder doesn't match attached encoder\n");
6346
6347                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6348                         "attached encoder crtc differs from connector crtc\n");
6349         } else {
6350                 I915_STATE_WARN(crtc && crtc->state->active,
6351                         "attached crtc is active, but connector isn't\n");
6352                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6353                         "best encoder set without crtc!\n");
6354         }
6355 }
6356
6357 int intel_connector_init(struct intel_connector *connector)
6358 {
6359         struct drm_connector_state *connector_state;
6360
6361         connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6362         if (!connector_state)
6363                 return -ENOMEM;
6364
6365         connector->base.state = connector_state;
6366         return 0;
6367 }
6368
6369 struct intel_connector *intel_connector_alloc(void)
6370 {
6371         struct intel_connector *connector;
6372
6373         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6374         if (!connector)
6375                 return NULL;
6376
6377         if (intel_connector_init(connector) < 0) {
6378                 kfree(connector);
6379                 return NULL;
6380         }
6381
6382         return connector;
6383 }
6384
6385 /* Simple connector->get_hw_state implementation for encoders that support only
6386  * one connector and no cloning and hence the encoder state determines the state
6387  * of the connector. */
6388 bool intel_connector_get_hw_state(struct intel_connector *connector)
6389 {
6390         enum pipe pipe = 0;
6391         struct intel_encoder *encoder = connector->encoder;
6392
6393         return encoder->get_hw_state(encoder, &pipe);
6394 }
6395
6396 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6397 {
6398         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6399                 return crtc_state->fdi_lanes;
6400
6401         return 0;
6402 }
6403
6404 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6405                                      struct intel_crtc_state *pipe_config)
6406 {
6407         struct drm_atomic_state *state = pipe_config->base.state;
6408         struct intel_crtc *other_crtc;
6409         struct intel_crtc_state *other_crtc_state;
6410
6411         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6412                       pipe_name(pipe), pipe_config->fdi_lanes);
6413         if (pipe_config->fdi_lanes > 4) {
6414                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6415                               pipe_name(pipe), pipe_config->fdi_lanes);
6416                 return -EINVAL;
6417         }
6418
6419         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6420                 if (pipe_config->fdi_lanes > 2) {
6421                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6422                                       pipe_config->fdi_lanes);
6423                         return -EINVAL;
6424                 } else {
6425                         return 0;
6426                 }
6427         }
6428
6429         if (INTEL_INFO(dev)->num_pipes == 2)
6430                 return 0;
6431
6432         /* Ivybridge 3 pipe is really complicated */
6433         switch (pipe) {
6434         case PIPE_A:
6435                 return 0;
6436         case PIPE_B:
6437                 if (pipe_config->fdi_lanes <= 2)
6438                         return 0;
6439
6440                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6441                 other_crtc_state =
6442                         intel_atomic_get_crtc_state(state, other_crtc);
6443                 if (IS_ERR(other_crtc_state))
6444                         return PTR_ERR(other_crtc_state);
6445
6446                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6447                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6448                                       pipe_name(pipe), pipe_config->fdi_lanes);
6449                         return -EINVAL;
6450                 }
6451                 return 0;
6452         case PIPE_C:
6453                 if (pipe_config->fdi_lanes > 2) {
6454                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6455                                       pipe_name(pipe), pipe_config->fdi_lanes);
6456                         return -EINVAL;
6457                 }
6458
6459                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6460                 other_crtc_state =
6461                         intel_atomic_get_crtc_state(state, other_crtc);
6462                 if (IS_ERR(other_crtc_state))
6463                         return PTR_ERR(other_crtc_state);
6464
6465                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6466                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6467                         return -EINVAL;
6468                 }
6469                 return 0;
6470         default:
6471                 BUG();
6472         }
6473 }
6474
6475 #define RETRY 1
6476 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6477                                        struct intel_crtc_state *pipe_config)
6478 {
6479         struct drm_device *dev = intel_crtc->base.dev;
6480         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6481         int lane, link_bw, fdi_dotclock, ret;
6482         bool needs_recompute = false;
6483
6484 retry:
6485         /* FDI is a binary signal running at ~2.7GHz, encoding
6486          * each output octet as 10 bits. The actual frequency
6487          * is stored as a divider into a 100MHz clock, and the
6488          * mode pixel clock is stored in units of 1KHz.
6489          * Hence the bw of each lane in terms of the mode signal
6490          * is:
6491          */
6492         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6493
6494         fdi_dotclock = adjusted_mode->crtc_clock;
6495
6496         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6497                                            pipe_config->pipe_bpp);
6498
6499         pipe_config->fdi_lanes = lane;
6500
6501         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6502                                link_bw, &pipe_config->fdi_m_n);
6503
6504         ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6505                                        intel_crtc->pipe, pipe_config);
6506         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6507                 pipe_config->pipe_bpp -= 2*3;
6508                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6509                               pipe_config->pipe_bpp);
6510                 needs_recompute = true;
6511                 pipe_config->bw_constrained = true;
6512
6513                 goto retry;
6514         }
6515
6516         if (needs_recompute)
6517                 return RETRY;
6518
6519         return ret;
6520 }
6521
6522 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6523                                      struct intel_crtc_state *pipe_config)
6524 {
6525         if (pipe_config->pipe_bpp > 24)
6526                 return false;
6527
6528         /* HSW can handle pixel rate up to cdclk? */
6529         if (IS_HASWELL(dev_priv->dev))
6530                 return true;
6531
6532         /*
6533          * We compare against max which means we must take
6534          * the increased cdclk requirement into account when
6535          * calculating the new cdclk.
6536          *
6537          * Should measure whether using a lower cdclk w/o IPS
6538          */
6539         return ilk_pipe_pixel_rate(pipe_config) <=
6540                 dev_priv->max_cdclk_freq * 95 / 100;
6541 }
6542
6543 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6544                                    struct intel_crtc_state *pipe_config)
6545 {
6546         struct drm_device *dev = crtc->base.dev;
6547         struct drm_i915_private *dev_priv = dev->dev_private;
6548
6549         pipe_config->ips_enabled = i915.enable_ips &&
6550                 hsw_crtc_supports_ips(crtc) &&
6551                 pipe_config_supports_ips(dev_priv, pipe_config);
6552 }
6553
6554 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6555                                      struct intel_crtc_state *pipe_config)
6556 {
6557         struct drm_device *dev = crtc->base.dev;
6558         struct drm_i915_private *dev_priv = dev->dev_private;
6559         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6560
6561         /* FIXME should check pixel clock limits on all platforms */
6562         if (INTEL_INFO(dev)->gen < 4) {
6563                 int clock_limit = dev_priv->max_cdclk_freq;
6564
6565                 /*
6566                  * Enable pixel doubling when the dot clock
6567                  * is > 90% of the (display) core speed.
6568                  *
6569                  * GDG double wide on either pipe,
6570                  * otherwise pipe A only.
6571                  */
6572                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6573                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6574                         clock_limit *= 2;
6575                         pipe_config->double_wide = true;
6576                 }
6577
6578                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6579                         return -EINVAL;
6580         }
6581
6582         /*
6583          * Pipe horizontal size must be even in:
6584          * - DVO ganged mode
6585          * - LVDS dual channel mode
6586          * - Double wide pipe
6587          */
6588         if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6589              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6590                 pipe_config->pipe_src_w &= ~1;
6591
6592         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6593          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6594          */
6595         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6596                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
6597                 return -EINVAL;
6598
6599         if (HAS_IPS(dev))
6600                 hsw_compute_ips_config(crtc, pipe_config);
6601
6602         if (pipe_config->has_pch_encoder)
6603                 return ironlake_fdi_compute_config(crtc, pipe_config);
6604
6605         return 0;
6606 }
6607
6608 static int skylake_get_display_clock_speed(struct drm_device *dev)
6609 {
6610         struct drm_i915_private *dev_priv = to_i915(dev);
6611         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6612         uint32_t cdctl = I915_READ(CDCLK_CTL);
6613         uint32_t linkrate;
6614
6615         if (!(lcpll1 & LCPLL_PLL_ENABLE))
6616                 return 24000; /* 24MHz is the cd freq with NSSC ref */
6617
6618         if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6619                 return 540000;
6620
6621         linkrate = (I915_READ(DPLL_CTRL1) &
6622                     DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6623
6624         if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6625             linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6626                 /* vco 8640 */
6627                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6628                 case CDCLK_FREQ_450_432:
6629                         return 432000;
6630                 case CDCLK_FREQ_337_308:
6631                         return 308570;
6632                 case CDCLK_FREQ_675_617:
6633                         return 617140;
6634                 default:
6635                         WARN(1, "Unknown cd freq selection\n");
6636                 }
6637         } else {
6638                 /* vco 8100 */
6639                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6640                 case CDCLK_FREQ_450_432:
6641                         return 450000;
6642                 case CDCLK_FREQ_337_308:
6643                         return 337500;
6644                 case CDCLK_FREQ_675_617:
6645                         return 675000;
6646                 default:
6647                         WARN(1, "Unknown cd freq selection\n");
6648                 }
6649         }
6650
6651         /* error case, do as if DPLL0 isn't enabled */
6652         return 24000;
6653 }
6654
6655 static int broxton_get_display_clock_speed(struct drm_device *dev)
6656 {
6657         struct drm_i915_private *dev_priv = to_i915(dev);
6658         uint32_t cdctl = I915_READ(CDCLK_CTL);
6659         uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6660         uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6661         int cdclk;
6662
6663         if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6664                 return 19200;
6665
6666         cdclk = 19200 * pll_ratio / 2;
6667
6668         switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6669         case BXT_CDCLK_CD2X_DIV_SEL_1:
6670                 return cdclk;  /* 576MHz or 624MHz */
6671         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6672                 return cdclk * 2 / 3; /* 384MHz */
6673         case BXT_CDCLK_CD2X_DIV_SEL_2:
6674                 return cdclk / 2; /* 288MHz */
6675         case BXT_CDCLK_CD2X_DIV_SEL_4:
6676                 return cdclk / 4; /* 144MHz */
6677         }
6678
6679         /* error case, do as if DE PLL isn't enabled */
6680         return 19200;
6681 }
6682
6683 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6684 {
6685         struct drm_i915_private *dev_priv = dev->dev_private;
6686         uint32_t lcpll = I915_READ(LCPLL_CTL);
6687         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6688
6689         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6690                 return 800000;
6691         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6692                 return 450000;
6693         else if (freq == LCPLL_CLK_FREQ_450)
6694                 return 450000;
6695         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6696                 return 540000;
6697         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6698                 return 337500;
6699         else
6700                 return 675000;
6701 }
6702
6703 static int haswell_get_display_clock_speed(struct drm_device *dev)
6704 {
6705         struct drm_i915_private *dev_priv = dev->dev_private;
6706         uint32_t lcpll = I915_READ(LCPLL_CTL);
6707         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6708
6709         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6710                 return 800000;
6711         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6712                 return 450000;
6713         else if (freq == LCPLL_CLK_FREQ_450)
6714                 return 450000;
6715         else if (IS_HSW_ULT(dev))
6716                 return 337500;
6717         else
6718                 return 540000;
6719 }
6720
6721 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6722 {
6723         struct drm_i915_private *dev_priv = dev->dev_private;
6724         u32 val;
6725         int divider;
6726
6727         if (dev_priv->hpll_freq == 0)
6728                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6729
6730         mutex_lock(&dev_priv->sb_lock);
6731         val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6732         mutex_unlock(&dev_priv->sb_lock);
6733
6734         divider = val & DISPLAY_FREQUENCY_VALUES;
6735
6736         WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6737              (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6738              "cdclk change in progress\n");
6739
6740         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
6741 }
6742
6743 static int ilk_get_display_clock_speed(struct drm_device *dev)
6744 {
6745         return 450000;
6746 }
6747
6748 static int i945_get_display_clock_speed(struct drm_device *dev)
6749 {
6750         return 400000;
6751 }
6752
6753 static int i915_get_display_clock_speed(struct drm_device *dev)
6754 {
6755         return 333333;
6756 }
6757
6758 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6759 {
6760         return 200000;
6761 }
6762
6763 static int pnv_get_display_clock_speed(struct drm_device *dev)
6764 {
6765         u16 gcfgc = 0;
6766
6767         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6768
6769         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6770         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6771                 return 266667;
6772         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6773                 return 333333;
6774         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6775                 return 444444;
6776         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6777                 return 200000;
6778         default:
6779                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6780         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6781                 return 133333;
6782         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6783                 return 166667;
6784         }
6785 }
6786
6787 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6788 {
6789         u16 gcfgc = 0;
6790
6791         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6792
6793         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6794                 return 133333;
6795         else {
6796                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6797                 case GC_DISPLAY_CLOCK_333_MHZ:
6798                         return 333333;
6799                 default:
6800                 case GC_DISPLAY_CLOCK_190_200_MHZ:
6801                         return 190000;
6802                 }
6803         }
6804 }
6805
6806 static int i865_get_display_clock_speed(struct drm_device *dev)
6807 {
6808         return 266667;
6809 }
6810
6811 static int i85x_get_display_clock_speed(struct drm_device *dev)
6812 {
6813         u16 hpllcc = 0;
6814
6815         /*
6816          * 852GM/852GMV only supports 133 MHz and the HPLLCC
6817          * encoding is different :(
6818          * FIXME is this the right way to detect 852GM/852GMV?
6819          */
6820         if (dev->pdev->revision == 0x1)
6821                 return 133333;
6822
6823         pci_bus_read_config_word(dev->pdev->bus,
6824                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6825
6826         /* Assume that the hardware is in the high speed state.  This
6827          * should be the default.
6828          */
6829         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6830         case GC_CLOCK_133_200:
6831         case GC_CLOCK_133_200_2:
6832         case GC_CLOCK_100_200:
6833                 return 200000;
6834         case GC_CLOCK_166_250:
6835                 return 250000;
6836         case GC_CLOCK_100_133:
6837                 return 133333;
6838         case GC_CLOCK_133_266:
6839         case GC_CLOCK_133_266_2:
6840         case GC_CLOCK_166_266:
6841                 return 266667;
6842         }
6843
6844         /* Shouldn't happen */
6845         return 0;
6846 }
6847
6848 static int i830_get_display_clock_speed(struct drm_device *dev)
6849 {
6850         return 133333;
6851 }
6852
6853 static unsigned int intel_hpll_vco(struct drm_device *dev)
6854 {
6855         struct drm_i915_private *dev_priv = dev->dev_private;
6856         static const unsigned int blb_vco[8] = {
6857                 [0] = 3200000,
6858                 [1] = 4000000,
6859                 [2] = 5333333,
6860                 [3] = 4800000,
6861                 [4] = 6400000,
6862         };
6863         static const unsigned int pnv_vco[8] = {
6864                 [0] = 3200000,
6865                 [1] = 4000000,
6866                 [2] = 5333333,
6867                 [3] = 4800000,
6868                 [4] = 2666667,
6869         };
6870         static const unsigned int cl_vco[8] = {
6871                 [0] = 3200000,
6872                 [1] = 4000000,
6873                 [2] = 5333333,
6874                 [3] = 6400000,
6875                 [4] = 3333333,
6876                 [5] = 3566667,
6877                 [6] = 4266667,
6878         };
6879         static const unsigned int elk_vco[8] = {
6880                 [0] = 3200000,
6881                 [1] = 4000000,
6882                 [2] = 5333333,
6883                 [3] = 4800000,
6884         };
6885         static const unsigned int ctg_vco[8] = {
6886                 [0] = 3200000,
6887                 [1] = 4000000,
6888                 [2] = 5333333,
6889                 [3] = 6400000,
6890                 [4] = 2666667,
6891                 [5] = 4266667,
6892         };
6893         const unsigned int *vco_table;
6894         unsigned int vco;
6895         uint8_t tmp = 0;
6896
6897         /* FIXME other chipsets? */
6898         if (IS_GM45(dev))
6899                 vco_table = ctg_vco;
6900         else if (IS_G4X(dev))
6901                 vco_table = elk_vco;
6902         else if (IS_CRESTLINE(dev))
6903                 vco_table = cl_vco;
6904         else if (IS_PINEVIEW(dev))
6905                 vco_table = pnv_vco;
6906         else if (IS_G33(dev))
6907                 vco_table = blb_vco;
6908         else
6909                 return 0;
6910
6911         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6912
6913         vco = vco_table[tmp & 0x7];
6914         if (vco == 0)
6915                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6916         else
6917                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6918
6919         return vco;
6920 }
6921
6922 static int gm45_get_display_clock_speed(struct drm_device *dev)
6923 {
6924         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6925         uint16_t tmp = 0;
6926
6927         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6928
6929         cdclk_sel = (tmp >> 12) & 0x1;
6930
6931         switch (vco) {
6932         case 2666667:
6933         case 4000000:
6934         case 5333333:
6935                 return cdclk_sel ? 333333 : 222222;
6936         case 3200000:
6937                 return cdclk_sel ? 320000 : 228571;
6938         default:
6939                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6940                 return 222222;
6941         }
6942 }
6943
6944 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6945 {
6946         static const uint8_t div_3200[] = { 16, 10,  8 };
6947         static const uint8_t div_4000[] = { 20, 12, 10 };
6948         static const uint8_t div_5333[] = { 24, 16, 14 };
6949         const uint8_t *div_table;
6950         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6951         uint16_t tmp = 0;
6952
6953         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6954
6955         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6956
6957         if (cdclk_sel >= ARRAY_SIZE(div_3200))
6958                 goto fail;
6959
6960         switch (vco) {
6961         case 3200000:
6962                 div_table = div_3200;
6963                 break;
6964         case 4000000:
6965                 div_table = div_4000;
6966                 break;
6967         case 5333333:
6968                 div_table = div_5333;
6969                 break;
6970         default:
6971                 goto fail;
6972         }
6973
6974         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6975
6976 fail:
6977         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6978         return 200000;
6979 }
6980
6981 static int g33_get_display_clock_speed(struct drm_device *dev)
6982 {
6983         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
6984         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
6985         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6986         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6987         const uint8_t *div_table;
6988         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6989         uint16_t tmp = 0;
6990
6991         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6992
6993         cdclk_sel = (tmp >> 4) & 0x7;
6994
6995         if (cdclk_sel >= ARRAY_SIZE(div_3200))
6996                 goto fail;
6997
6998         switch (vco) {
6999         case 3200000:
7000                 div_table = div_3200;
7001                 break;
7002         case 4000000:
7003                 div_table = div_4000;
7004                 break;
7005         case 4800000:
7006                 div_table = div_4800;
7007                 break;
7008         case 5333333:
7009                 div_table = div_5333;
7010                 break;
7011         default:
7012                 goto fail;
7013         }
7014
7015         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7016
7017 fail:
7018         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7019         return 190476;
7020 }
7021
7022 static void
7023 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7024 {
7025         while (*num > DATA_LINK_M_N_MASK ||
7026                *den > DATA_LINK_M_N_MASK) {
7027                 *num >>= 1;
7028                 *den >>= 1;
7029         }
7030 }
7031
7032 static void compute_m_n(unsigned int m, unsigned int n,
7033                         uint32_t *ret_m, uint32_t *ret_n)
7034 {
7035         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7036         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7037         intel_reduce_m_n_ratio(ret_m, ret_n);
7038 }
7039
7040 void
7041 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7042                        int pixel_clock, int link_clock,
7043                        struct intel_link_m_n *m_n)
7044 {
7045         m_n->tu = 64;
7046
7047         compute_m_n(bits_per_pixel * pixel_clock,
7048                     link_clock * nlanes * 8,
7049                     &m_n->gmch_m, &m_n->gmch_n);
7050
7051         compute_m_n(pixel_clock, link_clock,
7052                     &m_n->link_m, &m_n->link_n);
7053 }
7054
7055 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7056 {
7057         if (i915.panel_use_ssc >= 0)
7058                 return i915.panel_use_ssc != 0;
7059         return dev_priv->vbt.lvds_use_ssc
7060                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7061 }
7062
7063 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7064                            int num_connectors)
7065 {
7066         struct drm_device *dev = crtc_state->base.crtc->dev;
7067         struct drm_i915_private *dev_priv = dev->dev_private;
7068         int refclk;
7069
7070         WARN_ON(!crtc_state->base.state);
7071
7072         if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7073                 refclk = 100000;
7074         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7075             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7076                 refclk = dev_priv->vbt.lvds_ssc_freq;
7077                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7078         } else if (!IS_GEN2(dev)) {
7079                 refclk = 96000;
7080         } else {
7081                 refclk = 48000;
7082         }
7083
7084         return refclk;
7085 }
7086
7087 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7088 {
7089         return (1 << dpll->n) << 16 | dpll->m2;
7090 }
7091
7092 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7093 {
7094         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7095 }
7096
7097 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7098                                      struct intel_crtc_state *crtc_state,
7099                                      intel_clock_t *reduced_clock)
7100 {
7101         struct drm_device *dev = crtc->base.dev;
7102         u32 fp, fp2 = 0;
7103
7104         if (IS_PINEVIEW(dev)) {
7105                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7106                 if (reduced_clock)
7107                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7108         } else {
7109                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7110                 if (reduced_clock)
7111                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7112         }
7113
7114         crtc_state->dpll_hw_state.fp0 = fp;
7115
7116         crtc->lowfreq_avail = false;
7117         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7118             reduced_clock) {
7119                 crtc_state->dpll_hw_state.fp1 = fp2;
7120                 crtc->lowfreq_avail = true;
7121         } else {
7122                 crtc_state->dpll_hw_state.fp1 = fp;
7123         }
7124 }
7125
7126 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7127                 pipe)
7128 {
7129         u32 reg_val;
7130
7131         /*
7132          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7133          * and set it to a reasonable value instead.
7134          */
7135         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7136         reg_val &= 0xffffff00;
7137         reg_val |= 0x00000030;
7138         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7139
7140         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7141         reg_val &= 0x8cffffff;
7142         reg_val = 0x8c000000;
7143         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7144
7145         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7146         reg_val &= 0xffffff00;
7147         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7148
7149         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7150         reg_val &= 0x00ffffff;
7151         reg_val |= 0xb0000000;
7152         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7153 }
7154
7155 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7156                                          struct intel_link_m_n *m_n)
7157 {
7158         struct drm_device *dev = crtc->base.dev;
7159         struct drm_i915_private *dev_priv = dev->dev_private;
7160         int pipe = crtc->pipe;
7161
7162         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7163         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7164         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7165         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7166 }
7167
7168 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7169                                          struct intel_link_m_n *m_n,
7170                                          struct intel_link_m_n *m2_n2)
7171 {
7172         struct drm_device *dev = crtc->base.dev;
7173         struct drm_i915_private *dev_priv = dev->dev_private;
7174         int pipe = crtc->pipe;
7175         enum transcoder transcoder = crtc->config->cpu_transcoder;
7176
7177         if (INTEL_INFO(dev)->gen >= 5) {
7178                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7179                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7180                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7181                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7182                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7183                  * for gen < 8) and if DRRS is supported (to make sure the
7184                  * registers are not unnecessarily accessed).
7185                  */
7186                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7187                         crtc->config->has_drrs) {
7188                         I915_WRITE(PIPE_DATA_M2(transcoder),
7189                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7190                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7191                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7192                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7193                 }
7194         } else {
7195                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7196                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7197                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7198                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7199         }
7200 }
7201
7202 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7203 {
7204         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7205
7206         if (m_n == M1_N1) {
7207                 dp_m_n = &crtc->config->dp_m_n;
7208                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7209         } else if (m_n == M2_N2) {
7210
7211                 /*
7212                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7213                  * needs to be programmed into M1_N1.
7214                  */
7215                 dp_m_n = &crtc->config->dp_m2_n2;
7216         } else {
7217                 DRM_ERROR("Unsupported divider value\n");
7218                 return;
7219         }
7220
7221         if (crtc->config->has_pch_encoder)
7222                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7223         else
7224                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7225 }
7226
7227 static void vlv_compute_dpll(struct intel_crtc *crtc,
7228                              struct intel_crtc_state *pipe_config)
7229 {
7230         u32 dpll, dpll_md;
7231
7232         /*
7233          * Enable DPIO clock input. We should never disable the reference
7234          * clock for pipe B, since VGA hotplug / manual detection depends
7235          * on it.
7236          */
7237         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7238                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7239         /* We should never disable this, set it here for state tracking */
7240         if (crtc->pipe == PIPE_B)
7241                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7242         dpll |= DPLL_VCO_ENABLE;
7243         pipe_config->dpll_hw_state.dpll = dpll;
7244
7245         dpll_md = (pipe_config->pixel_multiplier - 1)
7246                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7247         pipe_config->dpll_hw_state.dpll_md = dpll_md;
7248 }
7249
7250 static void vlv_prepare_pll(struct intel_crtc *crtc,
7251                             const struct intel_crtc_state *pipe_config)
7252 {
7253         struct drm_device *dev = crtc->base.dev;
7254         struct drm_i915_private *dev_priv = dev->dev_private;
7255         int pipe = crtc->pipe;
7256         u32 mdiv;
7257         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7258         u32 coreclk, reg_val;
7259
7260         mutex_lock(&dev_priv->sb_lock);
7261
7262         bestn = pipe_config->dpll.n;
7263         bestm1 = pipe_config->dpll.m1;
7264         bestm2 = pipe_config->dpll.m2;
7265         bestp1 = pipe_config->dpll.p1;
7266         bestp2 = pipe_config->dpll.p2;
7267
7268         /* See eDP HDMI DPIO driver vbios notes doc */
7269
7270         /* PLL B needs special handling */
7271         if (pipe == PIPE_B)
7272                 vlv_pllb_recal_opamp(dev_priv, pipe);
7273
7274         /* Set up Tx target for periodic Rcomp update */
7275         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7276
7277         /* Disable target IRef on PLL */
7278         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7279         reg_val &= 0x00ffffff;
7280         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7281
7282         /* Disable fast lock */
7283         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7284
7285         /* Set idtafcrecal before PLL is enabled */
7286         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7287         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7288         mdiv |= ((bestn << DPIO_N_SHIFT));
7289         mdiv |= (1 << DPIO_K_SHIFT);
7290
7291         /*
7292          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7293          * but we don't support that).
7294          * Note: don't use the DAC post divider as it seems unstable.
7295          */
7296         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7297         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7298
7299         mdiv |= DPIO_ENABLE_CALIBRATION;
7300         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7301
7302         /* Set HBR and RBR LPF coefficients */
7303         if (pipe_config->port_clock == 162000 ||
7304             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7305             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7306                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7307                                  0x009f0003);
7308         else
7309                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7310                                  0x00d0000f);
7311
7312         if (pipe_config->has_dp_encoder) {
7313                 /* Use SSC source */
7314                 if (pipe == PIPE_A)
7315                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7316                                          0x0df40000);
7317                 else
7318                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7319                                          0x0df70000);
7320         } else { /* HDMI or VGA */
7321                 /* Use bend source */
7322                 if (pipe == PIPE_A)
7323                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7324                                          0x0df70000);
7325                 else
7326                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7327                                          0x0df40000);
7328         }
7329
7330         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7331         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7332         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7333             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7334                 coreclk |= 0x01000000;
7335         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7336
7337         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7338         mutex_unlock(&dev_priv->sb_lock);
7339 }
7340
7341 static void chv_compute_dpll(struct intel_crtc *crtc,
7342                              struct intel_crtc_state *pipe_config)
7343 {
7344         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7345                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7346                 DPLL_VCO_ENABLE;
7347         if (crtc->pipe != PIPE_A)
7348                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7349
7350         pipe_config->dpll_hw_state.dpll_md =
7351                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7352 }
7353
7354 static void chv_prepare_pll(struct intel_crtc *crtc,
7355                             const struct intel_crtc_state *pipe_config)
7356 {
7357         struct drm_device *dev = crtc->base.dev;
7358         struct drm_i915_private *dev_priv = dev->dev_private;
7359         int pipe = crtc->pipe;
7360         int dpll_reg = DPLL(crtc->pipe);
7361         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7362         u32 loopfilter, tribuf_calcntr;
7363         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7364         u32 dpio_val;
7365         int vco;
7366
7367         bestn = pipe_config->dpll.n;
7368         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7369         bestm1 = pipe_config->dpll.m1;
7370         bestm2 = pipe_config->dpll.m2 >> 22;
7371         bestp1 = pipe_config->dpll.p1;
7372         bestp2 = pipe_config->dpll.p2;
7373         vco = pipe_config->dpll.vco;
7374         dpio_val = 0;
7375         loopfilter = 0;
7376
7377         /*
7378          * Enable Refclk and SSC
7379          */
7380         I915_WRITE(dpll_reg,
7381                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7382
7383         mutex_lock(&dev_priv->sb_lock);
7384
7385         /* p1 and p2 divider */
7386         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7387                         5 << DPIO_CHV_S1_DIV_SHIFT |
7388                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7389                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7390                         1 << DPIO_CHV_K_DIV_SHIFT);
7391
7392         /* Feedback post-divider - m2 */
7393         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7394
7395         /* Feedback refclk divider - n and m1 */
7396         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7397                         DPIO_CHV_M1_DIV_BY_2 |
7398                         1 << DPIO_CHV_N_DIV_SHIFT);
7399
7400         /* M2 fraction division */
7401         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7402
7403         /* M2 fraction division enable */
7404         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7405         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7406         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7407         if (bestm2_frac)
7408                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7409         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7410
7411         /* Program digital lock detect threshold */
7412         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7413         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7414                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7415         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7416         if (!bestm2_frac)
7417                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7418         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7419
7420         /* Loop filter */
7421         if (vco == 5400000) {
7422                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7423                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7424                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7425                 tribuf_calcntr = 0x9;
7426         } else if (vco <= 6200000) {
7427                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7428                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7429                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7430                 tribuf_calcntr = 0x9;
7431         } else if (vco <= 6480000) {
7432                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7433                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7434                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7435                 tribuf_calcntr = 0x8;
7436         } else {
7437                 /* Not supported. Apply the same limits as in the max case */
7438                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7439                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7440                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7441                 tribuf_calcntr = 0;
7442         }
7443         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7444
7445         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7446         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7447         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7448         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7449
7450         /* AFC Recal */
7451         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7452                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7453                         DPIO_AFC_RECAL);
7454
7455         mutex_unlock(&dev_priv->sb_lock);
7456 }
7457
7458 /**
7459  * vlv_force_pll_on - forcibly enable just the PLL
7460  * @dev_priv: i915 private structure
7461  * @pipe: pipe PLL to enable
7462  * @dpll: PLL configuration
7463  *
7464  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7465  * in cases where we need the PLL enabled even when @pipe is not going to
7466  * be enabled.
7467  */
7468 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7469                       const struct dpll *dpll)
7470 {
7471         struct intel_crtc *crtc =
7472                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7473         struct intel_crtc_state pipe_config = {
7474                 .base.crtc = &crtc->base,
7475                 .pixel_multiplier = 1,
7476                 .dpll = *dpll,
7477         };
7478
7479         if (IS_CHERRYVIEW(dev)) {
7480                 chv_compute_dpll(crtc, &pipe_config);
7481                 chv_prepare_pll(crtc, &pipe_config);
7482                 chv_enable_pll(crtc, &pipe_config);
7483         } else {
7484                 vlv_compute_dpll(crtc, &pipe_config);
7485                 vlv_prepare_pll(crtc, &pipe_config);
7486                 vlv_enable_pll(crtc, &pipe_config);
7487         }
7488 }
7489
7490 /**
7491  * vlv_force_pll_off - forcibly disable just the PLL
7492  * @dev_priv: i915 private structure
7493  * @pipe: pipe PLL to disable
7494  *
7495  * Disable the PLL for @pipe. To be used in cases where we need
7496  * the PLL enabled even when @pipe is not going to be enabled.
7497  */
7498 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7499 {
7500         if (IS_CHERRYVIEW(dev))
7501                 chv_disable_pll(to_i915(dev), pipe);
7502         else
7503                 vlv_disable_pll(to_i915(dev), pipe);
7504 }
7505
7506 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7507                               struct intel_crtc_state *crtc_state,
7508                               intel_clock_t *reduced_clock,
7509                               int num_connectors)
7510 {
7511         struct drm_device *dev = crtc->base.dev;
7512         struct drm_i915_private *dev_priv = dev->dev_private;
7513         u32 dpll;
7514         bool is_sdvo;
7515         struct dpll *clock = &crtc_state->dpll;
7516
7517         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7518
7519         is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7520                 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7521
7522         dpll = DPLL_VGA_MODE_DIS;
7523
7524         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7525                 dpll |= DPLLB_MODE_LVDS;
7526         else
7527                 dpll |= DPLLB_MODE_DAC_SERIAL;
7528
7529         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7530                 dpll |= (crtc_state->pixel_multiplier - 1)
7531                         << SDVO_MULTIPLIER_SHIFT_HIRES;
7532         }
7533
7534         if (is_sdvo)
7535                 dpll |= DPLL_SDVO_HIGH_SPEED;
7536
7537         if (crtc_state->has_dp_encoder)
7538                 dpll |= DPLL_SDVO_HIGH_SPEED;
7539
7540         /* compute bitmask from p1 value */
7541         if (IS_PINEVIEW(dev))
7542                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7543         else {
7544                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7545                 if (IS_G4X(dev) && reduced_clock)
7546                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7547         }
7548         switch (clock->p2) {
7549         case 5:
7550                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7551                 break;
7552         case 7:
7553                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7554                 break;
7555         case 10:
7556                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7557                 break;
7558         case 14:
7559                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7560                 break;
7561         }
7562         if (INTEL_INFO(dev)->gen >= 4)
7563                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7564
7565         if (crtc_state->sdvo_tv_clock)
7566                 dpll |= PLL_REF_INPUT_TVCLKINBC;
7567         else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7568                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7569                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7570         else
7571                 dpll |= PLL_REF_INPUT_DREFCLK;
7572
7573         dpll |= DPLL_VCO_ENABLE;
7574         crtc_state->dpll_hw_state.dpll = dpll;
7575
7576         if (INTEL_INFO(dev)->gen >= 4) {
7577                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7578                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7579                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7580         }
7581 }
7582
7583 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7584                               struct intel_crtc_state *crtc_state,
7585                               intel_clock_t *reduced_clock,
7586                               int num_connectors)
7587 {
7588         struct drm_device *dev = crtc->base.dev;
7589         struct drm_i915_private *dev_priv = dev->dev_private;
7590         u32 dpll;
7591         struct dpll *clock = &crtc_state->dpll;
7592
7593         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7594
7595         dpll = DPLL_VGA_MODE_DIS;
7596
7597         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7598                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7599         } else {
7600                 if (clock->p1 == 2)
7601                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7602                 else
7603                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7604                 if (clock->p2 == 4)
7605                         dpll |= PLL_P2_DIVIDE_BY_4;
7606         }
7607
7608         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7609                 dpll |= DPLL_DVO_2X_MODE;
7610
7611         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7612                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7613                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7614         else
7615                 dpll |= PLL_REF_INPUT_DREFCLK;
7616
7617         dpll |= DPLL_VCO_ENABLE;
7618         crtc_state->dpll_hw_state.dpll = dpll;
7619 }
7620
7621 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7622 {
7623         struct drm_device *dev = intel_crtc->base.dev;
7624         struct drm_i915_private *dev_priv = dev->dev_private;
7625         enum pipe pipe = intel_crtc->pipe;
7626         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7627         struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7628         uint32_t crtc_vtotal, crtc_vblank_end;
7629         int vsyncshift = 0;
7630
7631         /* We need to be careful not to changed the adjusted mode, for otherwise
7632          * the hw state checker will get angry at the mismatch. */
7633         crtc_vtotal = adjusted_mode->crtc_vtotal;
7634         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7635
7636         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7637                 /* the chip adds 2 halflines automatically */
7638                 crtc_vtotal -= 1;
7639                 crtc_vblank_end -= 1;
7640
7641                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7642                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7643                 else
7644                         vsyncshift = adjusted_mode->crtc_hsync_start -
7645                                 adjusted_mode->crtc_htotal / 2;
7646                 if (vsyncshift < 0)
7647                         vsyncshift += adjusted_mode->crtc_htotal;
7648         }
7649
7650         if (INTEL_INFO(dev)->gen > 3)
7651                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7652
7653         I915_WRITE(HTOTAL(cpu_transcoder),
7654                    (adjusted_mode->crtc_hdisplay - 1) |
7655                    ((adjusted_mode->crtc_htotal - 1) << 16));
7656         I915_WRITE(HBLANK(cpu_transcoder),
7657                    (adjusted_mode->crtc_hblank_start - 1) |
7658                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7659         I915_WRITE(HSYNC(cpu_transcoder),
7660                    (adjusted_mode->crtc_hsync_start - 1) |
7661                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7662
7663         I915_WRITE(VTOTAL(cpu_transcoder),
7664                    (adjusted_mode->crtc_vdisplay - 1) |
7665                    ((crtc_vtotal - 1) << 16));
7666         I915_WRITE(VBLANK(cpu_transcoder),
7667                    (adjusted_mode->crtc_vblank_start - 1) |
7668                    ((crtc_vblank_end - 1) << 16));
7669         I915_WRITE(VSYNC(cpu_transcoder),
7670                    (adjusted_mode->crtc_vsync_start - 1) |
7671                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7672
7673         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7674          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7675          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7676          * bits. */
7677         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7678             (pipe == PIPE_B || pipe == PIPE_C))
7679                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7680
7681         /* pipesrc controls the size that is scaled from, which should
7682          * always be the user's requested size.
7683          */
7684         I915_WRITE(PIPESRC(pipe),
7685                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7686                    (intel_crtc->config->pipe_src_h - 1));
7687 }
7688
7689 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7690                                    struct intel_crtc_state *pipe_config)
7691 {
7692         struct drm_device *dev = crtc->base.dev;
7693         struct drm_i915_private *dev_priv = dev->dev_private;
7694         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7695         uint32_t tmp;
7696
7697         tmp = I915_READ(HTOTAL(cpu_transcoder));
7698         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7699         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7700         tmp = I915_READ(HBLANK(cpu_transcoder));
7701         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7702         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7703         tmp = I915_READ(HSYNC(cpu_transcoder));
7704         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7705         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7706
7707         tmp = I915_READ(VTOTAL(cpu_transcoder));
7708         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7709         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7710         tmp = I915_READ(VBLANK(cpu_transcoder));
7711         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7712         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7713         tmp = I915_READ(VSYNC(cpu_transcoder));
7714         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7715         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7716
7717         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7718                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7719                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7720                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7721         }
7722
7723         tmp = I915_READ(PIPESRC(crtc->pipe));
7724         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7725         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7726
7727         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7728         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7729 }
7730
7731 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7732                                  struct intel_crtc_state *pipe_config)
7733 {
7734         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7735         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7736         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7737         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7738
7739         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7740         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7741         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7742         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7743
7744         mode->flags = pipe_config->base.adjusted_mode.flags;
7745         mode->type = DRM_MODE_TYPE_DRIVER;
7746
7747         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7748         mode->flags |= pipe_config->base.adjusted_mode.flags;
7749
7750         mode->hsync = drm_mode_hsync(mode);
7751         mode->vrefresh = drm_mode_vrefresh(mode);
7752         drm_mode_set_name(mode);
7753 }
7754
7755 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7756 {
7757         struct drm_device *dev = intel_crtc->base.dev;
7758         struct drm_i915_private *dev_priv = dev->dev_private;
7759         uint32_t pipeconf;
7760
7761         pipeconf = 0;
7762
7763         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7764             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7765                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7766
7767         if (intel_crtc->config->double_wide)
7768                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7769
7770         /* only g4x and later have fancy bpc/dither controls */
7771         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7772                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7773                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7774                         pipeconf |= PIPECONF_DITHER_EN |
7775                                     PIPECONF_DITHER_TYPE_SP;
7776
7777                 switch (intel_crtc->config->pipe_bpp) {
7778                 case 18:
7779                         pipeconf |= PIPECONF_6BPC;
7780                         break;
7781                 case 24:
7782                         pipeconf |= PIPECONF_8BPC;
7783                         break;
7784                 case 30:
7785                         pipeconf |= PIPECONF_10BPC;
7786                         break;
7787                 default:
7788                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7789                         BUG();
7790                 }
7791         }
7792
7793         if (HAS_PIPE_CXSR(dev)) {
7794                 if (intel_crtc->lowfreq_avail) {
7795                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7796                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7797                 } else {
7798                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7799                 }
7800         }
7801
7802         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7803                 if (INTEL_INFO(dev)->gen < 4 ||
7804                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7805                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7806                 else
7807                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7808         } else
7809                 pipeconf |= PIPECONF_PROGRESSIVE;
7810
7811         if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7812                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7813
7814         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7815         POSTING_READ(PIPECONF(intel_crtc->pipe));
7816 }
7817
7818 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7819                                    struct intel_crtc_state *crtc_state)
7820 {
7821         struct drm_device *dev = crtc->base.dev;
7822         struct drm_i915_private *dev_priv = dev->dev_private;
7823         int refclk, num_connectors = 0;
7824         intel_clock_t clock;
7825         bool ok;
7826         bool is_dsi = false;
7827         struct intel_encoder *encoder;
7828         const intel_limit_t *limit;
7829         struct drm_atomic_state *state = crtc_state->base.state;
7830         struct drm_connector *connector;
7831         struct drm_connector_state *connector_state;
7832         int i;
7833
7834         memset(&crtc_state->dpll_hw_state, 0,
7835                sizeof(crtc_state->dpll_hw_state));
7836
7837         for_each_connector_in_state(state, connector, connector_state, i) {
7838                 if (connector_state->crtc != &crtc->base)
7839                         continue;
7840
7841                 encoder = to_intel_encoder(connector_state->best_encoder);
7842
7843                 switch (encoder->type) {
7844                 case INTEL_OUTPUT_DSI:
7845                         is_dsi = true;
7846                         break;
7847                 default:
7848                         break;
7849                 }
7850
7851                 num_connectors++;
7852         }
7853
7854         if (is_dsi)
7855                 return 0;
7856
7857         if (!crtc_state->clock_set) {
7858                 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7859
7860                 /*
7861                  * Returns a set of divisors for the desired target clock with
7862                  * the given refclk, or FALSE.  The returned values represent
7863                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7864                  * 2) / p1 / p2.
7865                  */
7866                 limit = intel_limit(crtc_state, refclk);
7867                 ok = dev_priv->display.find_dpll(limit, crtc_state,
7868                                                  crtc_state->port_clock,
7869                                                  refclk, NULL, &clock);
7870                 if (!ok) {
7871                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
7872                         return -EINVAL;
7873                 }
7874
7875                 /* Compat-code for transition, will disappear. */
7876                 crtc_state->dpll.n = clock.n;
7877                 crtc_state->dpll.m1 = clock.m1;
7878                 crtc_state->dpll.m2 = clock.m2;
7879                 crtc_state->dpll.p1 = clock.p1;
7880                 crtc_state->dpll.p2 = clock.p2;
7881         }
7882
7883         if (IS_GEN2(dev)) {
7884                 i8xx_compute_dpll(crtc, crtc_state, NULL,
7885                                   num_connectors);
7886         } else if (IS_CHERRYVIEW(dev)) {
7887                 chv_compute_dpll(crtc, crtc_state);
7888         } else if (IS_VALLEYVIEW(dev)) {
7889                 vlv_compute_dpll(crtc, crtc_state);
7890         } else {
7891                 i9xx_compute_dpll(crtc, crtc_state, NULL,
7892                                   num_connectors);
7893         }
7894
7895         return 0;
7896 }
7897
7898 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7899                                  struct intel_crtc_state *pipe_config)
7900 {
7901         struct drm_device *dev = crtc->base.dev;
7902         struct drm_i915_private *dev_priv = dev->dev_private;
7903         uint32_t tmp;
7904
7905         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7906                 return;
7907
7908         tmp = I915_READ(PFIT_CONTROL);
7909         if (!(tmp & PFIT_ENABLE))
7910                 return;
7911
7912         /* Check whether the pfit is attached to our pipe. */
7913         if (INTEL_INFO(dev)->gen < 4) {
7914                 if (crtc->pipe != PIPE_B)
7915                         return;
7916         } else {
7917                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7918                         return;
7919         }
7920
7921         pipe_config->gmch_pfit.control = tmp;
7922         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7923         if (INTEL_INFO(dev)->gen < 5)
7924                 pipe_config->gmch_pfit.lvds_border_bits =
7925                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7926 }
7927
7928 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7929                                struct intel_crtc_state *pipe_config)
7930 {
7931         struct drm_device *dev = crtc->base.dev;
7932         struct drm_i915_private *dev_priv = dev->dev_private;
7933         int pipe = pipe_config->cpu_transcoder;
7934         intel_clock_t clock;
7935         u32 mdiv;
7936         int refclk = 100000;
7937
7938         /* In case of MIPI DPLL will not even be used */
7939         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7940                 return;
7941
7942         mutex_lock(&dev_priv->sb_lock);
7943         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7944         mutex_unlock(&dev_priv->sb_lock);
7945
7946         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7947         clock.m2 = mdiv & DPIO_M2DIV_MASK;
7948         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7949         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7950         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7951
7952         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7953 }
7954
7955 static void
7956 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7957                               struct intel_initial_plane_config *plane_config)
7958 {
7959         struct drm_device *dev = crtc->base.dev;
7960         struct drm_i915_private *dev_priv = dev->dev_private;
7961         u32 val, base, offset;
7962         int pipe = crtc->pipe, plane = crtc->plane;
7963         int fourcc, pixel_format;
7964         unsigned int aligned_height;
7965         struct drm_framebuffer *fb;
7966         struct intel_framebuffer *intel_fb;
7967
7968         val = I915_READ(DSPCNTR(plane));
7969         if (!(val & DISPLAY_PLANE_ENABLE))
7970                 return;
7971
7972         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7973         if (!intel_fb) {
7974                 DRM_DEBUG_KMS("failed to alloc fb\n");
7975                 return;
7976         }
7977
7978         fb = &intel_fb->base;
7979
7980         if (INTEL_INFO(dev)->gen >= 4) {
7981                 if (val & DISPPLANE_TILED) {
7982                         plane_config->tiling = I915_TILING_X;
7983                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7984                 }
7985         }
7986
7987         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7988         fourcc = i9xx_format_to_fourcc(pixel_format);
7989         fb->pixel_format = fourcc;
7990         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7991
7992         if (INTEL_INFO(dev)->gen >= 4) {
7993                 if (plane_config->tiling)
7994                         offset = I915_READ(DSPTILEOFF(plane));
7995                 else
7996                         offset = I915_READ(DSPLINOFF(plane));
7997                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7998         } else {
7999                 base = I915_READ(DSPADDR(plane));
8000         }
8001         plane_config->base = base;
8002
8003         val = I915_READ(PIPESRC(pipe));
8004         fb->width = ((val >> 16) & 0xfff) + 1;
8005         fb->height = ((val >> 0) & 0xfff) + 1;
8006
8007         val = I915_READ(DSPSTRIDE(pipe));
8008         fb->pitches[0] = val & 0xffffffc0;
8009
8010         aligned_height = intel_fb_align_height(dev, fb->height,
8011                                                fb->pixel_format,
8012                                                fb->modifier[0]);
8013
8014         plane_config->size = fb->pitches[0] * aligned_height;
8015
8016         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8017                       pipe_name(pipe), plane, fb->width, fb->height,
8018                       fb->bits_per_pixel, base, fb->pitches[0],
8019                       plane_config->size);
8020
8021         plane_config->fb = intel_fb;
8022 }
8023
8024 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8025                                struct intel_crtc_state *pipe_config)
8026 {
8027         struct drm_device *dev = crtc->base.dev;
8028         struct drm_i915_private *dev_priv = dev->dev_private;
8029         int pipe = pipe_config->cpu_transcoder;
8030         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8031         intel_clock_t clock;
8032         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8033         int refclk = 100000;
8034
8035         mutex_lock(&dev_priv->sb_lock);
8036         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8037         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8038         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8039         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8040         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8041         mutex_unlock(&dev_priv->sb_lock);
8042
8043         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8044         clock.m2 = (pll_dw0 & 0xff) << 22;
8045         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8046                 clock.m2 |= pll_dw2 & 0x3fffff;
8047         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8048         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8049         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8050
8051         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8052 }
8053
8054 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8055                                  struct intel_crtc_state *pipe_config)
8056 {
8057         struct drm_device *dev = crtc->base.dev;
8058         struct drm_i915_private *dev_priv = dev->dev_private;
8059         uint32_t tmp;
8060
8061         if (!intel_display_power_is_enabled(dev_priv,
8062                                             POWER_DOMAIN_PIPE(crtc->pipe)))
8063                 return false;
8064
8065         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8066         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8067
8068         tmp = I915_READ(PIPECONF(crtc->pipe));
8069         if (!(tmp & PIPECONF_ENABLE))
8070                 return false;
8071
8072         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8073                 switch (tmp & PIPECONF_BPC_MASK) {
8074                 case PIPECONF_6BPC:
8075                         pipe_config->pipe_bpp = 18;
8076                         break;
8077                 case PIPECONF_8BPC:
8078                         pipe_config->pipe_bpp = 24;
8079                         break;
8080                 case PIPECONF_10BPC:
8081                         pipe_config->pipe_bpp = 30;
8082                         break;
8083                 default:
8084                         break;
8085                 }
8086         }
8087
8088         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8089                 pipe_config->limited_color_range = true;
8090
8091         if (INTEL_INFO(dev)->gen < 4)
8092                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8093
8094         intel_get_pipe_timings(crtc, pipe_config);
8095
8096         i9xx_get_pfit_config(crtc, pipe_config);
8097
8098         if (INTEL_INFO(dev)->gen >= 4) {
8099                 tmp = I915_READ(DPLL_MD(crtc->pipe));
8100                 pipe_config->pixel_multiplier =
8101                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8102                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8103                 pipe_config->dpll_hw_state.dpll_md = tmp;
8104         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8105                 tmp = I915_READ(DPLL(crtc->pipe));
8106                 pipe_config->pixel_multiplier =
8107                         ((tmp & SDVO_MULTIPLIER_MASK)
8108                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8109         } else {
8110                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8111                  * port and will be fixed up in the encoder->get_config
8112                  * function. */
8113                 pipe_config->pixel_multiplier = 1;
8114         }
8115         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8116         if (!IS_VALLEYVIEW(dev)) {
8117                 /*
8118                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8119                  * on 830. Filter it out here so that we don't
8120                  * report errors due to that.
8121                  */
8122                 if (IS_I830(dev))
8123                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8124
8125                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8126                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8127         } else {
8128                 /* Mask out read-only status bits. */
8129                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8130                                                      DPLL_PORTC_READY_MASK |
8131                                                      DPLL_PORTB_READY_MASK);
8132         }
8133
8134         if (IS_CHERRYVIEW(dev))
8135                 chv_crtc_clock_get(crtc, pipe_config);
8136         else if (IS_VALLEYVIEW(dev))
8137                 vlv_crtc_clock_get(crtc, pipe_config);
8138         else
8139                 i9xx_crtc_clock_get(crtc, pipe_config);
8140
8141         /*
8142          * Normally the dotclock is filled in by the encoder .get_config()
8143          * but in case the pipe is enabled w/o any ports we need a sane
8144          * default.
8145          */
8146         pipe_config->base.adjusted_mode.crtc_clock =
8147                 pipe_config->port_clock / pipe_config->pixel_multiplier;
8148
8149         return true;
8150 }
8151
8152 static void ironlake_init_pch_refclk(struct drm_device *dev)
8153 {
8154         struct drm_i915_private *dev_priv = dev->dev_private;
8155         struct intel_encoder *encoder;
8156         u32 val, final;
8157         bool has_lvds = false;
8158         bool has_cpu_edp = false;
8159         bool has_panel = false;
8160         bool has_ck505 = false;
8161         bool can_ssc = false;
8162
8163         /* We need to take the global config into account */
8164         for_each_intel_encoder(dev, encoder) {
8165                 switch (encoder->type) {
8166                 case INTEL_OUTPUT_LVDS:
8167                         has_panel = true;
8168                         has_lvds = true;
8169                         break;
8170                 case INTEL_OUTPUT_EDP:
8171                         has_panel = true;
8172                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8173                                 has_cpu_edp = true;
8174                         break;
8175                 default:
8176                         break;
8177                 }
8178         }
8179
8180         if (HAS_PCH_IBX(dev)) {
8181                 has_ck505 = dev_priv->vbt.display_clock_mode;
8182                 can_ssc = has_ck505;
8183         } else {
8184                 has_ck505 = false;
8185                 can_ssc = true;
8186         }
8187
8188         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8189                       has_panel, has_lvds, has_ck505);
8190
8191         /* Ironlake: try to setup display ref clock before DPLL
8192          * enabling. This is only under driver's control after
8193          * PCH B stepping, previous chipset stepping should be
8194          * ignoring this setting.
8195          */
8196         val = I915_READ(PCH_DREF_CONTROL);
8197
8198         /* As we must carefully and slowly disable/enable each source in turn,
8199          * compute the final state we want first and check if we need to
8200          * make any changes at all.
8201          */
8202         final = val;
8203         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8204         if (has_ck505)
8205                 final |= DREF_NONSPREAD_CK505_ENABLE;
8206         else
8207                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8208
8209         final &= ~DREF_SSC_SOURCE_MASK;
8210         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8211         final &= ~DREF_SSC1_ENABLE;
8212
8213         if (has_panel) {
8214                 final |= DREF_SSC_SOURCE_ENABLE;
8215
8216                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8217                         final |= DREF_SSC1_ENABLE;
8218
8219                 if (has_cpu_edp) {
8220                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
8221                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8222                         else
8223                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8224                 } else
8225                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8226         } else {
8227                 final |= DREF_SSC_SOURCE_DISABLE;
8228                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8229         }
8230
8231         if (final == val)
8232                 return;
8233
8234         /* Always enable nonspread source */
8235         val &= ~DREF_NONSPREAD_SOURCE_MASK;
8236
8237         if (has_ck505)
8238                 val |= DREF_NONSPREAD_CK505_ENABLE;
8239         else
8240                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8241
8242         if (has_panel) {
8243                 val &= ~DREF_SSC_SOURCE_MASK;
8244                 val |= DREF_SSC_SOURCE_ENABLE;
8245
8246                 /* SSC must be turned on before enabling the CPU output  */
8247                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8248                         DRM_DEBUG_KMS("Using SSC on panel\n");
8249                         val |= DREF_SSC1_ENABLE;
8250                 } else
8251                         val &= ~DREF_SSC1_ENABLE;
8252
8253                 /* Get SSC going before enabling the outputs */
8254                 I915_WRITE(PCH_DREF_CONTROL, val);
8255                 POSTING_READ(PCH_DREF_CONTROL);
8256                 udelay(200);
8257
8258                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8259
8260                 /* Enable CPU source on CPU attached eDP */
8261                 if (has_cpu_edp) {
8262                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8263                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
8264                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8265                         } else
8266                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8267                 } else
8268                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8269
8270                 I915_WRITE(PCH_DREF_CONTROL, val);
8271                 POSTING_READ(PCH_DREF_CONTROL);
8272                 udelay(200);
8273         } else {
8274                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8275
8276                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8277
8278                 /* Turn off CPU output */
8279                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8280
8281                 I915_WRITE(PCH_DREF_CONTROL, val);
8282                 POSTING_READ(PCH_DREF_CONTROL);
8283                 udelay(200);
8284
8285                 /* Turn off the SSC source */
8286                 val &= ~DREF_SSC_SOURCE_MASK;
8287                 val |= DREF_SSC_SOURCE_DISABLE;
8288
8289                 /* Turn off SSC1 */
8290                 val &= ~DREF_SSC1_ENABLE;
8291
8292                 I915_WRITE(PCH_DREF_CONTROL, val);
8293                 POSTING_READ(PCH_DREF_CONTROL);
8294                 udelay(200);
8295         }
8296
8297         BUG_ON(val != final);
8298 }
8299
8300 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8301 {
8302         uint32_t tmp;
8303
8304         tmp = I915_READ(SOUTH_CHICKEN2);
8305         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8306         I915_WRITE(SOUTH_CHICKEN2, tmp);
8307
8308         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8309                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8310                 DRM_ERROR("FDI mPHY reset assert timeout\n");
8311
8312         tmp = I915_READ(SOUTH_CHICKEN2);
8313         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8314         I915_WRITE(SOUTH_CHICKEN2, tmp);
8315
8316         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8317                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8318                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8319 }
8320
8321 /* WaMPhyProgramming:hsw */
8322 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8323 {
8324         uint32_t tmp;
8325
8326         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8327         tmp &= ~(0xFF << 24);
8328         tmp |= (0x12 << 24);
8329         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8330
8331         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8332         tmp |= (1 << 11);
8333         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8334
8335         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8336         tmp |= (1 << 11);
8337         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8338
8339         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8340         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8341         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8342
8343         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8344         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8345         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8346
8347         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8348         tmp &= ~(7 << 13);
8349         tmp |= (5 << 13);
8350         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8351
8352         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8353         tmp &= ~(7 << 13);
8354         tmp |= (5 << 13);
8355         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8356
8357         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8358         tmp &= ~0xFF;
8359         tmp |= 0x1C;
8360         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8361
8362         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8363         tmp &= ~0xFF;
8364         tmp |= 0x1C;
8365         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8366
8367         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8368         tmp &= ~(0xFF << 16);
8369         tmp |= (0x1C << 16);
8370         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8371
8372         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8373         tmp &= ~(0xFF << 16);
8374         tmp |= (0x1C << 16);
8375         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8376
8377         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8378         tmp |= (1 << 27);
8379         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8380
8381         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8382         tmp |= (1 << 27);
8383         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8384
8385         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8386         tmp &= ~(0xF << 28);
8387         tmp |= (4 << 28);
8388         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8389
8390         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8391         tmp &= ~(0xF << 28);
8392         tmp |= (4 << 28);
8393         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8394 }
8395
8396 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8397  * Programming" based on the parameters passed:
8398  * - Sequence to enable CLKOUT_DP
8399  * - Sequence to enable CLKOUT_DP without spread
8400  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8401  */
8402 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8403                                  bool with_fdi)
8404 {
8405         struct drm_i915_private *dev_priv = dev->dev_private;
8406         uint32_t reg, tmp;
8407
8408         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8409                 with_spread = true;
8410         if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8411                 with_fdi = false;
8412
8413         mutex_lock(&dev_priv->sb_lock);
8414
8415         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8416         tmp &= ~SBI_SSCCTL_DISABLE;
8417         tmp |= SBI_SSCCTL_PATHALT;
8418         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8419
8420         udelay(24);
8421
8422         if (with_spread) {
8423                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8424                 tmp &= ~SBI_SSCCTL_PATHALT;
8425                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8426
8427                 if (with_fdi) {
8428                         lpt_reset_fdi_mphy(dev_priv);
8429                         lpt_program_fdi_mphy(dev_priv);
8430                 }
8431         }
8432
8433         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8434         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8435         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8436         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8437
8438         mutex_unlock(&dev_priv->sb_lock);
8439 }
8440
8441 /* Sequence to disable CLKOUT_DP */
8442 static void lpt_disable_clkout_dp(struct drm_device *dev)
8443 {
8444         struct drm_i915_private *dev_priv = dev->dev_private;
8445         uint32_t reg, tmp;
8446
8447         mutex_lock(&dev_priv->sb_lock);
8448
8449         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8450         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8451         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8452         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8453
8454         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8455         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8456                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8457                         tmp |= SBI_SSCCTL_PATHALT;
8458                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8459                         udelay(32);
8460                 }
8461                 tmp |= SBI_SSCCTL_DISABLE;
8462                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8463         }
8464
8465         mutex_unlock(&dev_priv->sb_lock);
8466 }
8467
8468 static void lpt_init_pch_refclk(struct drm_device *dev)
8469 {
8470         struct intel_encoder *encoder;
8471         bool has_vga = false;
8472
8473         for_each_intel_encoder(dev, encoder) {
8474                 switch (encoder->type) {
8475                 case INTEL_OUTPUT_ANALOG:
8476                         has_vga = true;
8477                         break;
8478                 default:
8479                         break;
8480                 }
8481         }
8482
8483         if (has_vga)
8484                 lpt_enable_clkout_dp(dev, true, true);
8485         else
8486                 lpt_disable_clkout_dp(dev);
8487 }
8488
8489 /*
8490  * Initialize reference clocks when the driver loads
8491  */
8492 void intel_init_pch_refclk(struct drm_device *dev)
8493 {
8494         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8495                 ironlake_init_pch_refclk(dev);
8496         else if (HAS_PCH_LPT(dev))
8497                 lpt_init_pch_refclk(dev);
8498 }
8499
8500 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8501 {
8502         struct drm_device *dev = crtc_state->base.crtc->dev;
8503         struct drm_i915_private *dev_priv = dev->dev_private;
8504         struct drm_atomic_state *state = crtc_state->base.state;
8505         struct drm_connector *connector;
8506         struct drm_connector_state *connector_state;
8507         struct intel_encoder *encoder;
8508         int num_connectors = 0, i;
8509         bool is_lvds = false;
8510
8511         for_each_connector_in_state(state, connector, connector_state, i) {
8512                 if (connector_state->crtc != crtc_state->base.crtc)
8513                         continue;
8514
8515                 encoder = to_intel_encoder(connector_state->best_encoder);
8516
8517                 switch (encoder->type) {
8518                 case INTEL_OUTPUT_LVDS:
8519                         is_lvds = true;
8520                         break;
8521                 default:
8522                         break;
8523                 }
8524                 num_connectors++;
8525         }
8526
8527         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8528                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8529                               dev_priv->vbt.lvds_ssc_freq);
8530                 return dev_priv->vbt.lvds_ssc_freq;
8531         }
8532
8533         return 120000;
8534 }
8535
8536 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8537 {
8538         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8539         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8540         int pipe = intel_crtc->pipe;
8541         uint32_t val;
8542
8543         val = 0;
8544
8545         switch (intel_crtc->config->pipe_bpp) {
8546         case 18:
8547                 val |= PIPECONF_6BPC;
8548                 break;
8549         case 24:
8550                 val |= PIPECONF_8BPC;
8551                 break;
8552         case 30:
8553                 val |= PIPECONF_10BPC;
8554                 break;
8555         case 36:
8556                 val |= PIPECONF_12BPC;
8557                 break;
8558         default:
8559                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8560                 BUG();
8561         }
8562
8563         if (intel_crtc->config->dither)
8564                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8565
8566         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8567                 val |= PIPECONF_INTERLACED_ILK;
8568         else
8569                 val |= PIPECONF_PROGRESSIVE;
8570
8571         if (intel_crtc->config->limited_color_range)
8572                 val |= PIPECONF_COLOR_RANGE_SELECT;
8573
8574         I915_WRITE(PIPECONF(pipe), val);
8575         POSTING_READ(PIPECONF(pipe));
8576 }
8577
8578 /*
8579  * Set up the pipe CSC unit.
8580  *
8581  * Currently only full range RGB to limited range RGB conversion
8582  * is supported, but eventually this should handle various
8583  * RGB<->YCbCr scenarios as well.
8584  */
8585 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8586 {
8587         struct drm_device *dev = crtc->dev;
8588         struct drm_i915_private *dev_priv = dev->dev_private;
8589         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8590         int pipe = intel_crtc->pipe;
8591         uint16_t coeff = 0x7800; /* 1.0 */
8592
8593         /*
8594          * TODO: Check what kind of values actually come out of the pipe
8595          * with these coeff/postoff values and adjust to get the best
8596          * accuracy. Perhaps we even need to take the bpc value into
8597          * consideration.
8598          */
8599
8600         if (intel_crtc->config->limited_color_range)
8601                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8602
8603         /*
8604          * GY/GU and RY/RU should be the other way around according
8605          * to BSpec, but reality doesn't agree. Just set them up in
8606          * a way that results in the correct picture.
8607          */
8608         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8609         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8610
8611         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8612         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8613
8614         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8615         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8616
8617         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8618         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8619         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8620
8621         if (INTEL_INFO(dev)->gen > 6) {
8622                 uint16_t postoff = 0;
8623
8624                 if (intel_crtc->config->limited_color_range)
8625                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
8626
8627                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8628                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8629                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8630
8631                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8632         } else {
8633                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8634
8635                 if (intel_crtc->config->limited_color_range)
8636                         mode |= CSC_BLACK_SCREEN_OFFSET;
8637
8638                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8639         }
8640 }
8641
8642 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8643 {
8644         struct drm_device *dev = crtc->dev;
8645         struct drm_i915_private *dev_priv = dev->dev_private;
8646         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8647         enum pipe pipe = intel_crtc->pipe;
8648         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8649         uint32_t val;
8650
8651         val = 0;
8652
8653         if (IS_HASWELL(dev) && intel_crtc->config->dither)
8654                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8655
8656         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8657                 val |= PIPECONF_INTERLACED_ILK;
8658         else
8659                 val |= PIPECONF_PROGRESSIVE;
8660
8661         I915_WRITE(PIPECONF(cpu_transcoder), val);
8662         POSTING_READ(PIPECONF(cpu_transcoder));
8663
8664         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8665         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8666
8667         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8668                 val = 0;
8669
8670                 switch (intel_crtc->config->pipe_bpp) {
8671                 case 18:
8672                         val |= PIPEMISC_DITHER_6_BPC;
8673                         break;
8674                 case 24:
8675                         val |= PIPEMISC_DITHER_8_BPC;
8676                         break;
8677                 case 30:
8678                         val |= PIPEMISC_DITHER_10_BPC;
8679                         break;
8680                 case 36:
8681                         val |= PIPEMISC_DITHER_12_BPC;
8682                         break;
8683                 default:
8684                         /* Case prevented by pipe_config_set_bpp. */
8685                         BUG();
8686                 }
8687
8688                 if (intel_crtc->config->dither)
8689                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8690
8691                 I915_WRITE(PIPEMISC(pipe), val);
8692         }
8693 }
8694
8695 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8696                                     struct intel_crtc_state *crtc_state,
8697                                     intel_clock_t *clock,
8698                                     bool *has_reduced_clock,
8699                                     intel_clock_t *reduced_clock)
8700 {
8701         struct drm_device *dev = crtc->dev;
8702         struct drm_i915_private *dev_priv = dev->dev_private;
8703         int refclk;
8704         const intel_limit_t *limit;
8705         bool ret;
8706
8707         refclk = ironlake_get_refclk(crtc_state);
8708
8709         /*
8710          * Returns a set of divisors for the desired target clock with the given
8711          * refclk, or FALSE.  The returned values represent the clock equation:
8712          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8713          */
8714         limit = intel_limit(crtc_state, refclk);
8715         ret = dev_priv->display.find_dpll(limit, crtc_state,
8716                                           crtc_state->port_clock,
8717                                           refclk, NULL, clock);
8718         if (!ret)
8719                 return false;
8720
8721         return true;
8722 }
8723
8724 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8725 {
8726         /*
8727          * Account for spread spectrum to avoid
8728          * oversubscribing the link. Max center spread
8729          * is 2.5%; use 5% for safety's sake.
8730          */
8731         u32 bps = target_clock * bpp * 21 / 20;
8732         return DIV_ROUND_UP(bps, link_bw * 8);
8733 }
8734
8735 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8736 {
8737         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8738 }
8739
8740 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8741                                       struct intel_crtc_state *crtc_state,
8742                                       u32 *fp,
8743                                       intel_clock_t *reduced_clock, u32 *fp2)
8744 {
8745         struct drm_crtc *crtc = &intel_crtc->base;
8746         struct drm_device *dev = crtc->dev;
8747         struct drm_i915_private *dev_priv = dev->dev_private;
8748         struct drm_atomic_state *state = crtc_state->base.state;
8749         struct drm_connector *connector;
8750         struct drm_connector_state *connector_state;
8751         struct intel_encoder *encoder;
8752         uint32_t dpll;
8753         int factor, num_connectors = 0, i;
8754         bool is_lvds = false, is_sdvo = false;
8755
8756         for_each_connector_in_state(state, connector, connector_state, i) {
8757                 if (connector_state->crtc != crtc_state->base.crtc)
8758                         continue;
8759
8760                 encoder = to_intel_encoder(connector_state->best_encoder);
8761
8762                 switch (encoder->type) {
8763                 case INTEL_OUTPUT_LVDS:
8764                         is_lvds = true;
8765                         break;
8766                 case INTEL_OUTPUT_SDVO:
8767                 case INTEL_OUTPUT_HDMI:
8768                         is_sdvo = true;
8769                         break;
8770                 default:
8771                         break;
8772                 }
8773
8774                 num_connectors++;
8775         }
8776
8777         /* Enable autotuning of the PLL clock (if permissible) */
8778         factor = 21;
8779         if (is_lvds) {
8780                 if ((intel_panel_use_ssc(dev_priv) &&
8781                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8782                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8783                         factor = 25;
8784         } else if (crtc_state->sdvo_tv_clock)
8785                 factor = 20;
8786
8787         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8788                 *fp |= FP_CB_TUNE;
8789
8790         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8791                 *fp2 |= FP_CB_TUNE;
8792
8793         dpll = 0;
8794
8795         if (is_lvds)
8796                 dpll |= DPLLB_MODE_LVDS;
8797         else
8798                 dpll |= DPLLB_MODE_DAC_SERIAL;
8799
8800         dpll |= (crtc_state->pixel_multiplier - 1)
8801                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8802
8803         if (is_sdvo)
8804                 dpll |= DPLL_SDVO_HIGH_SPEED;
8805         if (crtc_state->has_dp_encoder)
8806                 dpll |= DPLL_SDVO_HIGH_SPEED;
8807
8808         /* compute bitmask from p1 value */
8809         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8810         /* also FPA1 */
8811         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8812
8813         switch (crtc_state->dpll.p2) {
8814         case 5:
8815                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8816                 break;
8817         case 7:
8818                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8819                 break;
8820         case 10:
8821                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8822                 break;
8823         case 14:
8824                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8825                 break;
8826         }
8827
8828         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8829                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8830         else
8831                 dpll |= PLL_REF_INPUT_DREFCLK;
8832
8833         return dpll | DPLL_VCO_ENABLE;
8834 }
8835
8836 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8837                                        struct intel_crtc_state *crtc_state)
8838 {
8839         struct drm_device *dev = crtc->base.dev;
8840         intel_clock_t clock, reduced_clock;
8841         u32 dpll = 0, fp = 0, fp2 = 0;
8842         bool ok, has_reduced_clock = false;
8843         bool is_lvds = false;
8844         struct intel_shared_dpll *pll;
8845
8846         memset(&crtc_state->dpll_hw_state, 0,
8847                sizeof(crtc_state->dpll_hw_state));
8848
8849         is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8850
8851         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8852              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8853
8854         ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8855                                      &has_reduced_clock, &reduced_clock);
8856         if (!ok && !crtc_state->clock_set) {
8857                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8858                 return -EINVAL;
8859         }
8860         /* Compat-code for transition, will disappear. */
8861         if (!crtc_state->clock_set) {
8862                 crtc_state->dpll.n = clock.n;
8863                 crtc_state->dpll.m1 = clock.m1;
8864                 crtc_state->dpll.m2 = clock.m2;
8865                 crtc_state->dpll.p1 = clock.p1;
8866                 crtc_state->dpll.p2 = clock.p2;
8867         }
8868
8869         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8870         if (crtc_state->has_pch_encoder) {
8871                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8872                 if (has_reduced_clock)
8873                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8874
8875                 dpll = ironlake_compute_dpll(crtc, crtc_state,
8876                                              &fp, &reduced_clock,
8877                                              has_reduced_clock ? &fp2 : NULL);
8878
8879                 crtc_state->dpll_hw_state.dpll = dpll;
8880                 crtc_state->dpll_hw_state.fp0 = fp;
8881                 if (has_reduced_clock)
8882                         crtc_state->dpll_hw_state.fp1 = fp2;
8883                 else
8884                         crtc_state->dpll_hw_state.fp1 = fp;
8885
8886                 pll = intel_get_shared_dpll(crtc, crtc_state);
8887                 if (pll == NULL) {
8888                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8889                                          pipe_name(crtc->pipe));
8890                         return -EINVAL;
8891                 }
8892         }
8893
8894         if (is_lvds && has_reduced_clock)
8895                 crtc->lowfreq_avail = true;
8896         else
8897                 crtc->lowfreq_avail = false;
8898
8899         return 0;
8900 }
8901
8902 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8903                                          struct intel_link_m_n *m_n)
8904 {
8905         struct drm_device *dev = crtc->base.dev;
8906         struct drm_i915_private *dev_priv = dev->dev_private;
8907         enum pipe pipe = crtc->pipe;
8908
8909         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8910         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8911         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8912                 & ~TU_SIZE_MASK;
8913         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8914         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8915                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8916 }
8917
8918 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8919                                          enum transcoder transcoder,
8920                                          struct intel_link_m_n *m_n,
8921                                          struct intel_link_m_n *m2_n2)
8922 {
8923         struct drm_device *dev = crtc->base.dev;
8924         struct drm_i915_private *dev_priv = dev->dev_private;
8925         enum pipe pipe = crtc->pipe;
8926
8927         if (INTEL_INFO(dev)->gen >= 5) {
8928                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8929                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8930                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8931                         & ~TU_SIZE_MASK;
8932                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8933                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8934                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8935                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8936                  * gen < 8) and if DRRS is supported (to make sure the
8937                  * registers are not unnecessarily read).
8938                  */
8939                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8940                         crtc->config->has_drrs) {
8941                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8942                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8943                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8944                                         & ~TU_SIZE_MASK;
8945                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8946                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8947                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8948                 }
8949         } else {
8950                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8951                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8952                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8953                         & ~TU_SIZE_MASK;
8954                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8955                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8956                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8957         }
8958 }
8959
8960 void intel_dp_get_m_n(struct intel_crtc *crtc,
8961                       struct intel_crtc_state *pipe_config)
8962 {
8963         if (pipe_config->has_pch_encoder)
8964                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8965         else
8966                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8967                                              &pipe_config->dp_m_n,
8968                                              &pipe_config->dp_m2_n2);
8969 }
8970
8971 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8972                                         struct intel_crtc_state *pipe_config)
8973 {
8974         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8975                                      &pipe_config->fdi_m_n, NULL);
8976 }
8977
8978 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8979                                     struct intel_crtc_state *pipe_config)
8980 {
8981         struct drm_device *dev = crtc->base.dev;
8982         struct drm_i915_private *dev_priv = dev->dev_private;
8983         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8984         uint32_t ps_ctrl = 0;
8985         int id = -1;
8986         int i;
8987
8988         /* find scaler attached to this pipe */
8989         for (i = 0; i < crtc->num_scalers; i++) {
8990                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8991                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8992                         id = i;
8993                         pipe_config->pch_pfit.enabled = true;
8994                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8995                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8996                         break;
8997                 }
8998         }
8999
9000         scaler_state->scaler_id = id;
9001         if (id >= 0) {
9002                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9003         } else {
9004                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9005         }
9006 }
9007
9008 static void
9009 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9010                                  struct intel_initial_plane_config *plane_config)
9011 {
9012         struct drm_device *dev = crtc->base.dev;
9013         struct drm_i915_private *dev_priv = dev->dev_private;
9014         u32 val, base, offset, stride_mult, tiling;
9015         int pipe = crtc->pipe;
9016         int fourcc, pixel_format;
9017         unsigned int aligned_height;
9018         struct drm_framebuffer *fb;
9019         struct intel_framebuffer *intel_fb;
9020
9021         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9022         if (!intel_fb) {
9023                 DRM_DEBUG_KMS("failed to alloc fb\n");
9024                 return;
9025         }
9026
9027         fb = &intel_fb->base;
9028
9029         val = I915_READ(PLANE_CTL(pipe, 0));
9030         if (!(val & PLANE_CTL_ENABLE))
9031                 goto error;
9032
9033         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9034         fourcc = skl_format_to_fourcc(pixel_format,
9035                                       val & PLANE_CTL_ORDER_RGBX,
9036                                       val & PLANE_CTL_ALPHA_MASK);
9037         fb->pixel_format = fourcc;
9038         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9039
9040         tiling = val & PLANE_CTL_TILED_MASK;
9041         switch (tiling) {
9042         case PLANE_CTL_TILED_LINEAR:
9043                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9044                 break;
9045         case PLANE_CTL_TILED_X:
9046                 plane_config->tiling = I915_TILING_X;
9047                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9048                 break;
9049         case PLANE_CTL_TILED_Y:
9050                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9051                 break;
9052         case PLANE_CTL_TILED_YF:
9053                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9054                 break;
9055         default:
9056                 MISSING_CASE(tiling);
9057                 goto error;
9058         }
9059
9060         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9061         plane_config->base = base;
9062
9063         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9064
9065         val = I915_READ(PLANE_SIZE(pipe, 0));
9066         fb->height = ((val >> 16) & 0xfff) + 1;
9067         fb->width = ((val >> 0) & 0x1fff) + 1;
9068
9069         val = I915_READ(PLANE_STRIDE(pipe, 0));
9070         stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9071                                                 fb->pixel_format);
9072         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9073
9074         aligned_height = intel_fb_align_height(dev, fb->height,
9075                                                fb->pixel_format,
9076                                                fb->modifier[0]);
9077
9078         plane_config->size = fb->pitches[0] * aligned_height;
9079
9080         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9081                       pipe_name(pipe), fb->width, fb->height,
9082                       fb->bits_per_pixel, base, fb->pitches[0],
9083                       plane_config->size);
9084
9085         plane_config->fb = intel_fb;
9086         return;
9087
9088 error:
9089         kfree(fb);
9090 }
9091
9092 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9093                                      struct intel_crtc_state *pipe_config)
9094 {
9095         struct drm_device *dev = crtc->base.dev;
9096         struct drm_i915_private *dev_priv = dev->dev_private;
9097         uint32_t tmp;
9098
9099         tmp = I915_READ(PF_CTL(crtc->pipe));
9100
9101         if (tmp & PF_ENABLE) {
9102                 pipe_config->pch_pfit.enabled = true;
9103                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9104                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9105
9106                 /* We currently do not free assignements of panel fitters on
9107                  * ivb/hsw (since we don't use the higher upscaling modes which
9108                  * differentiates them) so just WARN about this case for now. */
9109                 if (IS_GEN7(dev)) {
9110                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9111                                 PF_PIPE_SEL_IVB(crtc->pipe));
9112                 }
9113         }
9114 }
9115
9116 static void
9117 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9118                                   struct intel_initial_plane_config *plane_config)
9119 {
9120         struct drm_device *dev = crtc->base.dev;
9121         struct drm_i915_private *dev_priv = dev->dev_private;
9122         u32 val, base, offset;
9123         int pipe = crtc->pipe;
9124         int fourcc, pixel_format;
9125         unsigned int aligned_height;
9126         struct drm_framebuffer *fb;
9127         struct intel_framebuffer *intel_fb;
9128
9129         val = I915_READ(DSPCNTR(pipe));
9130         if (!(val & DISPLAY_PLANE_ENABLE))
9131                 return;
9132
9133         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9134         if (!intel_fb) {
9135                 DRM_DEBUG_KMS("failed to alloc fb\n");
9136                 return;
9137         }
9138
9139         fb = &intel_fb->base;
9140
9141         if (INTEL_INFO(dev)->gen >= 4) {
9142                 if (val & DISPPLANE_TILED) {
9143                         plane_config->tiling = I915_TILING_X;
9144                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9145                 }
9146         }
9147
9148         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9149         fourcc = i9xx_format_to_fourcc(pixel_format);
9150         fb->pixel_format = fourcc;
9151         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9152
9153         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9154         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9155                 offset = I915_READ(DSPOFFSET(pipe));
9156         } else {
9157                 if (plane_config->tiling)
9158                         offset = I915_READ(DSPTILEOFF(pipe));
9159                 else
9160                         offset = I915_READ(DSPLINOFF(pipe));
9161         }
9162         plane_config->base = base;
9163
9164         val = I915_READ(PIPESRC(pipe));
9165         fb->width = ((val >> 16) & 0xfff) + 1;
9166         fb->height = ((val >> 0) & 0xfff) + 1;
9167
9168         val = I915_READ(DSPSTRIDE(pipe));
9169         fb->pitches[0] = val & 0xffffffc0;
9170
9171         aligned_height = intel_fb_align_height(dev, fb->height,
9172                                                fb->pixel_format,
9173                                                fb->modifier[0]);
9174
9175         plane_config->size = fb->pitches[0] * aligned_height;
9176
9177         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9178                       pipe_name(pipe), fb->width, fb->height,
9179                       fb->bits_per_pixel, base, fb->pitches[0],
9180                       plane_config->size);
9181
9182         plane_config->fb = intel_fb;
9183 }
9184
9185 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9186                                      struct intel_crtc_state *pipe_config)
9187 {
9188         struct drm_device *dev = crtc->base.dev;
9189         struct drm_i915_private *dev_priv = dev->dev_private;
9190         uint32_t tmp;
9191
9192         if (!intel_display_power_is_enabled(dev_priv,
9193                                             POWER_DOMAIN_PIPE(crtc->pipe)))
9194                 return false;
9195
9196         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9197         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9198
9199         tmp = I915_READ(PIPECONF(crtc->pipe));
9200         if (!(tmp & PIPECONF_ENABLE))
9201                 return false;
9202
9203         switch (tmp & PIPECONF_BPC_MASK) {
9204         case PIPECONF_6BPC:
9205                 pipe_config->pipe_bpp = 18;
9206                 break;
9207         case PIPECONF_8BPC:
9208                 pipe_config->pipe_bpp = 24;
9209                 break;
9210         case PIPECONF_10BPC:
9211                 pipe_config->pipe_bpp = 30;
9212                 break;
9213         case PIPECONF_12BPC:
9214                 pipe_config->pipe_bpp = 36;
9215                 break;
9216         default:
9217                 break;
9218         }
9219
9220         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9221                 pipe_config->limited_color_range = true;
9222
9223         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9224                 struct intel_shared_dpll *pll;
9225
9226                 pipe_config->has_pch_encoder = true;
9227
9228                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9229                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9230                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9231
9232                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9233
9234                 if (HAS_PCH_IBX(dev_priv->dev)) {
9235                         pipe_config->shared_dpll =
9236                                 (enum intel_dpll_id) crtc->pipe;
9237                 } else {
9238                         tmp = I915_READ(PCH_DPLL_SEL);
9239                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9240                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9241                         else
9242                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9243                 }
9244
9245                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9246
9247                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9248                                            &pipe_config->dpll_hw_state));
9249
9250                 tmp = pipe_config->dpll_hw_state.dpll;
9251                 pipe_config->pixel_multiplier =
9252                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9253                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9254
9255                 ironlake_pch_clock_get(crtc, pipe_config);
9256         } else {
9257                 pipe_config->pixel_multiplier = 1;
9258         }
9259
9260         intel_get_pipe_timings(crtc, pipe_config);
9261
9262         ironlake_get_pfit_config(crtc, pipe_config);
9263
9264         return true;
9265 }
9266
9267 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9268 {
9269         struct drm_device *dev = dev_priv->dev;
9270         struct intel_crtc *crtc;
9271
9272         for_each_intel_crtc(dev, crtc)
9273                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9274                      pipe_name(crtc->pipe));
9275
9276         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9277         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9278         I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9279         I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9280         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9281         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9282              "CPU PWM1 enabled\n");
9283         if (IS_HASWELL(dev))
9284                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9285                      "CPU PWM2 enabled\n");
9286         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9287              "PCH PWM1 enabled\n");
9288         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9289              "Utility pin enabled\n");
9290         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9291
9292         /*
9293          * In theory we can still leave IRQs enabled, as long as only the HPD
9294          * interrupts remain enabled. We used to check for that, but since it's
9295          * gen-specific and since we only disable LCPLL after we fully disable
9296          * the interrupts, the check below should be enough.
9297          */
9298         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9299 }
9300
9301 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9302 {
9303         struct drm_device *dev = dev_priv->dev;
9304
9305         if (IS_HASWELL(dev))
9306                 return I915_READ(D_COMP_HSW);
9307         else
9308                 return I915_READ(D_COMP_BDW);
9309 }
9310
9311 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9312 {
9313         struct drm_device *dev = dev_priv->dev;
9314
9315         if (IS_HASWELL(dev)) {
9316                 mutex_lock(&dev_priv->rps.hw_lock);
9317                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9318                                             val))
9319                         DRM_ERROR("Failed to write to D_COMP\n");
9320                 mutex_unlock(&dev_priv->rps.hw_lock);
9321         } else {
9322                 I915_WRITE(D_COMP_BDW, val);
9323                 POSTING_READ(D_COMP_BDW);
9324         }
9325 }
9326
9327 /*
9328  * This function implements pieces of two sequences from BSpec:
9329  * - Sequence for display software to disable LCPLL
9330  * - Sequence for display software to allow package C8+
9331  * The steps implemented here are just the steps that actually touch the LCPLL
9332  * register. Callers should take care of disabling all the display engine
9333  * functions, doing the mode unset, fixing interrupts, etc.
9334  */
9335 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9336                               bool switch_to_fclk, bool allow_power_down)
9337 {
9338         uint32_t val;
9339
9340         assert_can_disable_lcpll(dev_priv);
9341
9342         val = I915_READ(LCPLL_CTL);
9343
9344         if (switch_to_fclk) {
9345                 val |= LCPLL_CD_SOURCE_FCLK;
9346                 I915_WRITE(LCPLL_CTL, val);
9347
9348                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9349                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
9350                         DRM_ERROR("Switching to FCLK failed\n");
9351
9352                 val = I915_READ(LCPLL_CTL);
9353         }
9354
9355         val |= LCPLL_PLL_DISABLE;
9356         I915_WRITE(LCPLL_CTL, val);
9357         POSTING_READ(LCPLL_CTL);
9358
9359         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9360                 DRM_ERROR("LCPLL still locked\n");
9361
9362         val = hsw_read_dcomp(dev_priv);
9363         val |= D_COMP_COMP_DISABLE;
9364         hsw_write_dcomp(dev_priv, val);
9365         ndelay(100);
9366
9367         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9368                      1))
9369                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9370
9371         if (allow_power_down) {
9372                 val = I915_READ(LCPLL_CTL);
9373                 val |= LCPLL_POWER_DOWN_ALLOW;
9374                 I915_WRITE(LCPLL_CTL, val);
9375                 POSTING_READ(LCPLL_CTL);
9376         }
9377 }
9378
9379 /*
9380  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9381  * source.
9382  */
9383 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9384 {
9385         uint32_t val;
9386
9387         val = I915_READ(LCPLL_CTL);
9388
9389         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9390                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9391                 return;
9392
9393         /*
9394          * Make sure we're not on PC8 state before disabling PC8, otherwise
9395          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9396          */
9397         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9398
9399         if (val & LCPLL_POWER_DOWN_ALLOW) {
9400                 val &= ~LCPLL_POWER_DOWN_ALLOW;
9401                 I915_WRITE(LCPLL_CTL, val);
9402                 POSTING_READ(LCPLL_CTL);
9403         }
9404
9405         val = hsw_read_dcomp(dev_priv);
9406         val |= D_COMP_COMP_FORCE;
9407         val &= ~D_COMP_COMP_DISABLE;
9408         hsw_write_dcomp(dev_priv, val);
9409
9410         val = I915_READ(LCPLL_CTL);
9411         val &= ~LCPLL_PLL_DISABLE;
9412         I915_WRITE(LCPLL_CTL, val);
9413
9414         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9415                 DRM_ERROR("LCPLL not locked yet\n");
9416
9417         if (val & LCPLL_CD_SOURCE_FCLK) {
9418                 val = I915_READ(LCPLL_CTL);
9419                 val &= ~LCPLL_CD_SOURCE_FCLK;
9420                 I915_WRITE(LCPLL_CTL, val);
9421
9422                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9423                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9424                         DRM_ERROR("Switching back to LCPLL failed\n");
9425         }
9426
9427         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9428         intel_update_cdclk(dev_priv->dev);
9429 }
9430
9431 /*
9432  * Package states C8 and deeper are really deep PC states that can only be
9433  * reached when all the devices on the system allow it, so even if the graphics
9434  * device allows PC8+, it doesn't mean the system will actually get to these
9435  * states. Our driver only allows PC8+ when going into runtime PM.
9436  *
9437  * The requirements for PC8+ are that all the outputs are disabled, the power
9438  * well is disabled and most interrupts are disabled, and these are also
9439  * requirements for runtime PM. When these conditions are met, we manually do
9440  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9441  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9442  * hang the machine.
9443  *
9444  * When we really reach PC8 or deeper states (not just when we allow it) we lose
9445  * the state of some registers, so when we come back from PC8+ we need to
9446  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9447  * need to take care of the registers kept by RC6. Notice that this happens even
9448  * if we don't put the device in PCI D3 state (which is what currently happens
9449  * because of the runtime PM support).
9450  *
9451  * For more, read "Display Sequences for Package C8" on the hardware
9452  * documentation.
9453  */
9454 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9455 {
9456         struct drm_device *dev = dev_priv->dev;
9457         uint32_t val;
9458
9459         DRM_DEBUG_KMS("Enabling package C8+\n");
9460
9461         if (HAS_PCH_LPT_LP(dev)) {
9462                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9463                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9464                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9465         }
9466
9467         lpt_disable_clkout_dp(dev);
9468         hsw_disable_lcpll(dev_priv, true, true);
9469 }
9470
9471 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9472 {
9473         struct drm_device *dev = dev_priv->dev;
9474         uint32_t val;
9475
9476         DRM_DEBUG_KMS("Disabling package C8+\n");
9477
9478         hsw_restore_lcpll(dev_priv);
9479         lpt_init_pch_refclk(dev);
9480
9481         if (HAS_PCH_LPT_LP(dev)) {
9482                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9483                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9484                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9485         }
9486
9487         intel_prepare_ddi(dev);
9488 }
9489
9490 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9491 {
9492         struct drm_device *dev = old_state->dev;
9493         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9494
9495         broxton_set_cdclk(dev, req_cdclk);
9496 }
9497
9498 /* compute the max rate for new configuration */
9499 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9500 {
9501         struct intel_crtc *intel_crtc;
9502         struct intel_crtc_state *crtc_state;
9503         int max_pixel_rate = 0;
9504
9505         for_each_intel_crtc(state->dev, intel_crtc) {
9506                 int pixel_rate;
9507
9508                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9509                 if (IS_ERR(crtc_state))
9510                         return PTR_ERR(crtc_state);
9511
9512                 if (!crtc_state->base.enable)
9513                         continue;
9514
9515                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9516
9517                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9518                 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9519                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9520
9521                 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9522         }
9523
9524         return max_pixel_rate;
9525 }
9526
9527 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9528 {
9529         struct drm_i915_private *dev_priv = dev->dev_private;
9530         uint32_t val, data;
9531         int ret;
9532
9533         if (WARN((I915_READ(LCPLL_CTL) &
9534                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9535                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9536                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9537                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9538                  "trying to change cdclk frequency with cdclk not enabled\n"))
9539                 return;
9540
9541         mutex_lock(&dev_priv->rps.hw_lock);
9542         ret = sandybridge_pcode_write(dev_priv,
9543                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9544         mutex_unlock(&dev_priv->rps.hw_lock);
9545         if (ret) {
9546                 DRM_ERROR("failed to inform pcode about cdclk change\n");
9547                 return;
9548         }
9549
9550         val = I915_READ(LCPLL_CTL);
9551         val |= LCPLL_CD_SOURCE_FCLK;
9552         I915_WRITE(LCPLL_CTL, val);
9553
9554         if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9555                                LCPLL_CD_SOURCE_FCLK_DONE, 1))
9556                 DRM_ERROR("Switching to FCLK failed\n");
9557
9558         val = I915_READ(LCPLL_CTL);
9559         val &= ~LCPLL_CLK_FREQ_MASK;
9560
9561         switch (cdclk) {
9562         case 450000:
9563                 val |= LCPLL_CLK_FREQ_450;
9564                 data = 0;
9565                 break;
9566         case 540000:
9567                 val |= LCPLL_CLK_FREQ_54O_BDW;
9568                 data = 1;
9569                 break;
9570         case 337500:
9571                 val |= LCPLL_CLK_FREQ_337_5_BDW;
9572                 data = 2;
9573                 break;
9574         case 675000:
9575                 val |= LCPLL_CLK_FREQ_675_BDW;
9576                 data = 3;
9577                 break;
9578         default:
9579                 WARN(1, "invalid cdclk frequency\n");
9580                 return;
9581         }
9582
9583         I915_WRITE(LCPLL_CTL, val);
9584
9585         val = I915_READ(LCPLL_CTL);
9586         val &= ~LCPLL_CD_SOURCE_FCLK;
9587         I915_WRITE(LCPLL_CTL, val);
9588
9589         if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9590                                 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9591                 DRM_ERROR("Switching back to LCPLL failed\n");
9592
9593         mutex_lock(&dev_priv->rps.hw_lock);
9594         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9595         mutex_unlock(&dev_priv->rps.hw_lock);
9596
9597         intel_update_cdclk(dev);
9598
9599         WARN(cdclk != dev_priv->cdclk_freq,
9600              "cdclk requested %d kHz but got %d kHz\n",
9601              cdclk, dev_priv->cdclk_freq);
9602 }
9603
9604 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9605 {
9606         struct drm_i915_private *dev_priv = to_i915(state->dev);
9607         int max_pixclk = ilk_max_pixel_rate(state);
9608         int cdclk;
9609
9610         /*
9611          * FIXME should also account for plane ratio
9612          * once 64bpp pixel formats are supported.
9613          */
9614         if (max_pixclk > 540000)
9615                 cdclk = 675000;
9616         else if (max_pixclk > 450000)
9617                 cdclk = 540000;
9618         else if (max_pixclk > 337500)
9619                 cdclk = 450000;
9620         else
9621                 cdclk = 337500;
9622
9623         /*
9624          * FIXME move the cdclk caclulation to
9625          * compute_config() so we can fail gracegully.
9626          */
9627         if (cdclk > dev_priv->max_cdclk_freq) {
9628                 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9629                           cdclk, dev_priv->max_cdclk_freq);
9630                 cdclk = dev_priv->max_cdclk_freq;
9631         }
9632
9633         to_intel_atomic_state(state)->cdclk = cdclk;
9634
9635         return 0;
9636 }
9637
9638 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9639 {
9640         struct drm_device *dev = old_state->dev;
9641         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9642
9643         broadwell_set_cdclk(dev, req_cdclk);
9644 }
9645
9646 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9647                                       struct intel_crtc_state *crtc_state)
9648 {
9649         if (!intel_ddi_pll_select(crtc, crtc_state))
9650                 return -EINVAL;
9651
9652         crtc->lowfreq_avail = false;
9653
9654         return 0;
9655 }
9656
9657 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9658                                 enum port port,
9659                                 struct intel_crtc_state *pipe_config)
9660 {
9661         switch (port) {
9662         case PORT_A:
9663                 pipe_config->ddi_pll_sel = SKL_DPLL0;
9664                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9665                 break;
9666         case PORT_B:
9667                 pipe_config->ddi_pll_sel = SKL_DPLL1;
9668                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9669                 break;
9670         case PORT_C:
9671                 pipe_config->ddi_pll_sel = SKL_DPLL2;
9672                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9673                 break;
9674         default:
9675                 DRM_ERROR("Incorrect port type\n");
9676         }
9677 }
9678
9679 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9680                                 enum port port,
9681                                 struct intel_crtc_state *pipe_config)
9682 {
9683         u32 temp, dpll_ctl1;
9684
9685         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9686         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9687
9688         switch (pipe_config->ddi_pll_sel) {
9689         case SKL_DPLL0:
9690                 /*
9691                  * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9692                  * of the shared DPLL framework and thus needs to be read out
9693                  * separately
9694                  */
9695                 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9696                 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9697                 break;
9698         case SKL_DPLL1:
9699                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9700                 break;
9701         case SKL_DPLL2:
9702                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9703                 break;
9704         case SKL_DPLL3:
9705                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9706                 break;
9707         }
9708 }
9709
9710 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9711                                 enum port port,
9712                                 struct intel_crtc_state *pipe_config)
9713 {
9714         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9715
9716         switch (pipe_config->ddi_pll_sel) {
9717         case PORT_CLK_SEL_WRPLL1:
9718                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9719                 break;
9720         case PORT_CLK_SEL_WRPLL2:
9721                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9722                 break;
9723         }
9724 }
9725
9726 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9727                                        struct intel_crtc_state *pipe_config)
9728 {
9729         struct drm_device *dev = crtc->base.dev;
9730         struct drm_i915_private *dev_priv = dev->dev_private;
9731         struct intel_shared_dpll *pll;
9732         enum port port;
9733         uint32_t tmp;
9734
9735         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9736
9737         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9738
9739         if (IS_SKYLAKE(dev))
9740                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9741         else if (IS_BROXTON(dev))
9742                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9743         else
9744                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9745
9746         if (pipe_config->shared_dpll >= 0) {
9747                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9748
9749                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9750                                            &pipe_config->dpll_hw_state));
9751         }
9752
9753         /*
9754          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9755          * DDI E. So just check whether this pipe is wired to DDI E and whether
9756          * the PCH transcoder is on.
9757          */
9758         if (INTEL_INFO(dev)->gen < 9 &&
9759             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9760                 pipe_config->has_pch_encoder = true;
9761
9762                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9763                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9764                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9765
9766                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9767         }
9768 }
9769
9770 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9771                                     struct intel_crtc_state *pipe_config)
9772 {
9773         struct drm_device *dev = crtc->base.dev;
9774         struct drm_i915_private *dev_priv = dev->dev_private;
9775         enum intel_display_power_domain pfit_domain;
9776         uint32_t tmp;
9777
9778         if (!intel_display_power_is_enabled(dev_priv,
9779                                          POWER_DOMAIN_PIPE(crtc->pipe)))
9780                 return false;
9781
9782         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9783         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9784
9785         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9786         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9787                 enum pipe trans_edp_pipe;
9788                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9789                 default:
9790                         WARN(1, "unknown pipe linked to edp transcoder\n");
9791                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9792                 case TRANS_DDI_EDP_INPUT_A_ON:
9793                         trans_edp_pipe = PIPE_A;
9794                         break;
9795                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9796                         trans_edp_pipe = PIPE_B;
9797                         break;
9798                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9799                         trans_edp_pipe = PIPE_C;
9800                         break;
9801                 }
9802
9803                 if (trans_edp_pipe == crtc->pipe)
9804                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9805         }
9806
9807         if (!intel_display_power_is_enabled(dev_priv,
9808                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9809                 return false;
9810
9811         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9812         if (!(tmp & PIPECONF_ENABLE))
9813                 return false;
9814
9815         haswell_get_ddi_port_state(crtc, pipe_config);
9816
9817         intel_get_pipe_timings(crtc, pipe_config);
9818
9819         if (INTEL_INFO(dev)->gen >= 9) {
9820                 skl_init_scalers(dev, crtc, pipe_config);
9821         }
9822
9823         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9824
9825         if (INTEL_INFO(dev)->gen >= 9) {
9826                 pipe_config->scaler_state.scaler_id = -1;
9827                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9828         }
9829
9830         if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9831                 if (INTEL_INFO(dev)->gen >= 9)
9832                         skylake_get_pfit_config(crtc, pipe_config);
9833                 else
9834                         ironlake_get_pfit_config(crtc, pipe_config);
9835         }
9836
9837         if (IS_HASWELL(dev))
9838                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9839                         (I915_READ(IPS_CTL) & IPS_ENABLE);
9840
9841         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9842                 pipe_config->pixel_multiplier =
9843                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9844         } else {
9845                 pipe_config->pixel_multiplier = 1;
9846         }
9847
9848         return true;
9849 }
9850
9851 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9852 {
9853         struct drm_device *dev = crtc->dev;
9854         struct drm_i915_private *dev_priv = dev->dev_private;
9855         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9856         uint32_t cntl = 0, size = 0;
9857
9858         if (base) {
9859                 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9860                 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9861                 unsigned int stride = roundup_pow_of_two(width) * 4;
9862
9863                 switch (stride) {
9864                 default:
9865                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9866                                   width, stride);
9867                         stride = 256;
9868                         /* fallthrough */
9869                 case 256:
9870                 case 512:
9871                 case 1024:
9872                 case 2048:
9873                         break;
9874                 }
9875
9876                 cntl |= CURSOR_ENABLE |
9877                         CURSOR_GAMMA_ENABLE |
9878                         CURSOR_FORMAT_ARGB |
9879                         CURSOR_STRIDE(stride);
9880
9881                 size = (height << 12) | width;
9882         }
9883
9884         if (intel_crtc->cursor_cntl != 0 &&
9885             (intel_crtc->cursor_base != base ||
9886              intel_crtc->cursor_size != size ||
9887              intel_crtc->cursor_cntl != cntl)) {
9888                 /* On these chipsets we can only modify the base/size/stride
9889                  * whilst the cursor is disabled.
9890                  */
9891                 I915_WRITE(_CURACNTR, 0);
9892                 POSTING_READ(_CURACNTR);
9893                 intel_crtc->cursor_cntl = 0;
9894         }
9895
9896         if (intel_crtc->cursor_base != base) {
9897                 I915_WRITE(_CURABASE, base);
9898                 intel_crtc->cursor_base = base;
9899         }
9900
9901         if (intel_crtc->cursor_size != size) {
9902                 I915_WRITE(CURSIZE, size);
9903                 intel_crtc->cursor_size = size;
9904         }
9905
9906         if (intel_crtc->cursor_cntl != cntl) {
9907                 I915_WRITE(_CURACNTR, cntl);
9908                 POSTING_READ(_CURACNTR);
9909                 intel_crtc->cursor_cntl = cntl;
9910         }
9911 }
9912
9913 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9914 {
9915         struct drm_device *dev = crtc->dev;
9916         struct drm_i915_private *dev_priv = dev->dev_private;
9917         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9918         int pipe = intel_crtc->pipe;
9919         uint32_t cntl;
9920
9921         cntl = 0;
9922         if (base) {
9923                 cntl = MCURSOR_GAMMA_ENABLE;
9924                 switch (intel_crtc->base.cursor->state->crtc_w) {
9925                         case 64:
9926                                 cntl |= CURSOR_MODE_64_ARGB_AX;
9927                                 break;
9928                         case 128:
9929                                 cntl |= CURSOR_MODE_128_ARGB_AX;
9930                                 break;
9931                         case 256:
9932                                 cntl |= CURSOR_MODE_256_ARGB_AX;
9933                                 break;
9934                         default:
9935                                 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9936                                 return;
9937                 }
9938                 cntl |= pipe << 28; /* Connect to correct pipe */
9939
9940                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9941                         cntl |= CURSOR_PIPE_CSC_ENABLE;
9942         }
9943
9944         if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
9945                 cntl |= CURSOR_ROTATE_180;
9946
9947         if (intel_crtc->cursor_cntl != cntl) {
9948                 I915_WRITE(CURCNTR(pipe), cntl);
9949                 POSTING_READ(CURCNTR(pipe));
9950                 intel_crtc->cursor_cntl = cntl;
9951         }
9952
9953         /* and commit changes on next vblank */
9954         I915_WRITE(CURBASE(pipe), base);
9955         POSTING_READ(CURBASE(pipe));
9956
9957         intel_crtc->cursor_base = base;
9958 }
9959
9960 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9961 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9962                                      bool on)
9963 {
9964         struct drm_device *dev = crtc->dev;
9965         struct drm_i915_private *dev_priv = dev->dev_private;
9966         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9967         int pipe = intel_crtc->pipe;
9968         struct drm_plane_state *cursor_state = crtc->cursor->state;
9969         int x = cursor_state->crtc_x;
9970         int y = cursor_state->crtc_y;
9971         u32 base = 0, pos = 0;
9972
9973         if (on)
9974                 base = intel_crtc->cursor_addr;
9975
9976         if (x >= intel_crtc->config->pipe_src_w)
9977                 base = 0;
9978
9979         if (y >= intel_crtc->config->pipe_src_h)
9980                 base = 0;
9981
9982         if (x < 0) {
9983                 if (x + cursor_state->crtc_w <= 0)
9984                         base = 0;
9985
9986                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9987                 x = -x;
9988         }
9989         pos |= x << CURSOR_X_SHIFT;
9990
9991         if (y < 0) {
9992                 if (y + cursor_state->crtc_h <= 0)
9993                         base = 0;
9994
9995                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9996                 y = -y;
9997         }
9998         pos |= y << CURSOR_Y_SHIFT;
9999
10000         if (base == 0 && intel_crtc->cursor_base == 0)
10001                 return;
10002
10003         I915_WRITE(CURPOS(pipe), pos);
10004
10005         /* ILK+ do this automagically */
10006         if (HAS_GMCH_DISPLAY(dev) &&
10007             crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
10008                 base += (cursor_state->crtc_h *
10009                          cursor_state->crtc_w - 1) * 4;
10010         }
10011
10012         if (IS_845G(dev) || IS_I865G(dev))
10013                 i845_update_cursor(crtc, base);
10014         else
10015                 i9xx_update_cursor(crtc, base);
10016 }
10017
10018 static bool cursor_size_ok(struct drm_device *dev,
10019                            uint32_t width, uint32_t height)
10020 {
10021         if (width == 0 || height == 0)
10022                 return false;
10023
10024         /*
10025          * 845g/865g are special in that they are only limited by
10026          * the width of their cursors, the height is arbitrary up to
10027          * the precision of the register. Everything else requires
10028          * square cursors, limited to a few power-of-two sizes.
10029          */
10030         if (IS_845G(dev) || IS_I865G(dev)) {
10031                 if ((width & 63) != 0)
10032                         return false;
10033
10034                 if (width > (IS_845G(dev) ? 64 : 512))
10035                         return false;
10036
10037                 if (height > 1023)
10038                         return false;
10039         } else {
10040                 switch (width | height) {
10041                 case 256:
10042                 case 128:
10043                         if (IS_GEN2(dev))
10044                                 return false;
10045                 case 64:
10046                         break;
10047                 default:
10048                         return false;
10049                 }
10050         }
10051
10052         return true;
10053 }
10054
10055 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10056                                  u16 *blue, uint32_t start, uint32_t size)
10057 {
10058         int end = (start + size > 256) ? 256 : start + size, i;
10059         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10060
10061         for (i = start; i < end; i++) {
10062                 intel_crtc->lut_r[i] = red[i] >> 8;
10063                 intel_crtc->lut_g[i] = green[i] >> 8;
10064                 intel_crtc->lut_b[i] = blue[i] >> 8;
10065         }
10066
10067         intel_crtc_load_lut(crtc);
10068 }
10069
10070 /* VESA 640x480x72Hz mode to set on the pipe */
10071 static struct drm_display_mode load_detect_mode = {
10072         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10073                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10074 };
10075
10076 struct drm_framebuffer *
10077 __intel_framebuffer_create(struct drm_device *dev,
10078                            struct drm_mode_fb_cmd2 *mode_cmd,
10079                            struct drm_i915_gem_object *obj)
10080 {
10081         struct intel_framebuffer *intel_fb;
10082         int ret;
10083
10084         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10085         if (!intel_fb) {
10086                 drm_gem_object_unreference(&obj->base);
10087                 return ERR_PTR(-ENOMEM);
10088         }
10089
10090         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10091         if (ret)
10092                 goto err;
10093
10094         return &intel_fb->base;
10095 err:
10096         drm_gem_object_unreference(&obj->base);
10097         kfree(intel_fb);
10098
10099         return ERR_PTR(ret);
10100 }
10101
10102 static struct drm_framebuffer *
10103 intel_framebuffer_create(struct drm_device *dev,
10104                          struct drm_mode_fb_cmd2 *mode_cmd,
10105                          struct drm_i915_gem_object *obj)
10106 {
10107         struct drm_framebuffer *fb;
10108         int ret;
10109
10110         ret = i915_mutex_lock_interruptible(dev);
10111         if (ret)
10112                 return ERR_PTR(ret);
10113         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10114         mutex_unlock(&dev->struct_mutex);
10115
10116         return fb;
10117 }
10118
10119 static u32
10120 intel_framebuffer_pitch_for_width(int width, int bpp)
10121 {
10122         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10123         return ALIGN(pitch, 64);
10124 }
10125
10126 static u32
10127 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10128 {
10129         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10130         return PAGE_ALIGN(pitch * mode->vdisplay);
10131 }
10132
10133 static struct drm_framebuffer *
10134 intel_framebuffer_create_for_mode(struct drm_device *dev,
10135                                   struct drm_display_mode *mode,
10136                                   int depth, int bpp)
10137 {
10138         struct drm_i915_gem_object *obj;
10139         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10140
10141         obj = i915_gem_alloc_object(dev,
10142                                     intel_framebuffer_size_for_mode(mode, bpp));
10143         if (obj == NULL)
10144                 return ERR_PTR(-ENOMEM);
10145
10146         mode_cmd.width = mode->hdisplay;
10147         mode_cmd.height = mode->vdisplay;
10148         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10149                                                                 bpp);
10150         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10151
10152         return intel_framebuffer_create(dev, &mode_cmd, obj);
10153 }
10154
10155 static struct drm_framebuffer *
10156 mode_fits_in_fbdev(struct drm_device *dev,
10157                    struct drm_display_mode *mode)
10158 {
10159 #ifdef CONFIG_DRM_FBDEV_EMULATION
10160         struct drm_i915_private *dev_priv = dev->dev_private;
10161         struct drm_i915_gem_object *obj;
10162         struct drm_framebuffer *fb;
10163
10164         if (!dev_priv->fbdev)
10165                 return NULL;
10166
10167         if (!dev_priv->fbdev->fb)
10168                 return NULL;
10169
10170         obj = dev_priv->fbdev->fb->obj;
10171         BUG_ON(!obj);
10172
10173         fb = &dev_priv->fbdev->fb->base;
10174         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10175                                                                fb->bits_per_pixel))
10176                 return NULL;
10177
10178         if (obj->base.size < mode->vdisplay * fb->pitches[0])
10179                 return NULL;
10180
10181         return fb;
10182 #else
10183         return NULL;
10184 #endif
10185 }
10186
10187 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10188                                            struct drm_crtc *crtc,
10189                                            struct drm_display_mode *mode,
10190                                            struct drm_framebuffer *fb,
10191                                            int x, int y)
10192 {
10193         struct drm_plane_state *plane_state;
10194         int hdisplay, vdisplay;
10195         int ret;
10196
10197         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10198         if (IS_ERR(plane_state))
10199                 return PTR_ERR(plane_state);
10200
10201         if (mode)
10202                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10203         else
10204                 hdisplay = vdisplay = 0;
10205
10206         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10207         if (ret)
10208                 return ret;
10209         drm_atomic_set_fb_for_plane(plane_state, fb);
10210         plane_state->crtc_x = 0;
10211         plane_state->crtc_y = 0;
10212         plane_state->crtc_w = hdisplay;
10213         plane_state->crtc_h = vdisplay;
10214         plane_state->src_x = x << 16;
10215         plane_state->src_y = y << 16;
10216         plane_state->src_w = hdisplay << 16;
10217         plane_state->src_h = vdisplay << 16;
10218
10219         return 0;
10220 }
10221
10222 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10223                                 struct drm_display_mode *mode,
10224                                 struct intel_load_detect_pipe *old,
10225                                 struct drm_modeset_acquire_ctx *ctx)
10226 {
10227         struct intel_crtc *intel_crtc;
10228         struct intel_encoder *intel_encoder =
10229                 intel_attached_encoder(connector);
10230         struct drm_crtc *possible_crtc;
10231         struct drm_encoder *encoder = &intel_encoder->base;
10232         struct drm_crtc *crtc = NULL;
10233         struct drm_device *dev = encoder->dev;
10234         struct drm_framebuffer *fb;
10235         struct drm_mode_config *config = &dev->mode_config;
10236         struct drm_atomic_state *state = NULL;
10237         struct drm_connector_state *connector_state;
10238         struct intel_crtc_state *crtc_state;
10239         int ret, i = -1;
10240
10241         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10242                       connector->base.id, connector->name,
10243                       encoder->base.id, encoder->name);
10244
10245 retry:
10246         ret = drm_modeset_lock(&config->connection_mutex, ctx);
10247         if (ret)
10248                 goto fail;
10249
10250         /*
10251          * Algorithm gets a little messy:
10252          *
10253          *   - if the connector already has an assigned crtc, use it (but make
10254          *     sure it's on first)
10255          *
10256          *   - try to find the first unused crtc that can drive this connector,
10257          *     and use that if we find one
10258          */
10259
10260         /* See if we already have a CRTC for this connector */
10261         if (encoder->crtc) {
10262                 crtc = encoder->crtc;
10263
10264                 ret = drm_modeset_lock(&crtc->mutex, ctx);
10265                 if (ret)
10266                         goto fail;
10267                 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10268                 if (ret)
10269                         goto fail;
10270
10271                 old->dpms_mode = connector->dpms;
10272                 old->load_detect_temp = false;
10273
10274                 /* Make sure the crtc and connector are running */
10275                 if (connector->dpms != DRM_MODE_DPMS_ON)
10276                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10277
10278                 return true;
10279         }
10280
10281         /* Find an unused one (if possible) */
10282         for_each_crtc(dev, possible_crtc) {
10283                 i++;
10284                 if (!(encoder->possible_crtcs & (1 << i)))
10285                         continue;
10286                 if (possible_crtc->state->enable)
10287                         continue;
10288
10289                 crtc = possible_crtc;
10290                 break;
10291         }
10292
10293         /*
10294          * If we didn't find an unused CRTC, don't use any.
10295          */
10296         if (!crtc) {
10297                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10298                 goto fail;
10299         }
10300
10301         ret = drm_modeset_lock(&crtc->mutex, ctx);
10302         if (ret)
10303                 goto fail;
10304         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10305         if (ret)
10306                 goto fail;
10307
10308         intel_crtc = to_intel_crtc(crtc);
10309         old->dpms_mode = connector->dpms;
10310         old->load_detect_temp = true;
10311         old->release_fb = NULL;
10312
10313         state = drm_atomic_state_alloc(dev);
10314         if (!state)
10315                 return false;
10316
10317         state->acquire_ctx = ctx;
10318
10319         connector_state = drm_atomic_get_connector_state(state, connector);
10320         if (IS_ERR(connector_state)) {
10321                 ret = PTR_ERR(connector_state);
10322                 goto fail;
10323         }
10324
10325         connector_state->crtc = crtc;
10326         connector_state->best_encoder = &intel_encoder->base;
10327
10328         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10329         if (IS_ERR(crtc_state)) {
10330                 ret = PTR_ERR(crtc_state);
10331                 goto fail;
10332         }
10333
10334         crtc_state->base.active = crtc_state->base.enable = true;
10335
10336         if (!mode)
10337                 mode = &load_detect_mode;
10338
10339         /* We need a framebuffer large enough to accommodate all accesses
10340          * that the plane may generate whilst we perform load detection.
10341          * We can not rely on the fbcon either being present (we get called
10342          * during its initialisation to detect all boot displays, or it may
10343          * not even exist) or that it is large enough to satisfy the
10344          * requested mode.
10345          */
10346         fb = mode_fits_in_fbdev(dev, mode);
10347         if (fb == NULL) {
10348                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10349                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10350                 old->release_fb = fb;
10351         } else
10352                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10353         if (IS_ERR(fb)) {
10354                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10355                 goto fail;
10356         }
10357
10358         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10359         if (ret)
10360                 goto fail;
10361
10362         drm_mode_copy(&crtc_state->base.mode, mode);
10363
10364         if (drm_atomic_commit(state)) {
10365                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10366                 if (old->release_fb)
10367                         old->release_fb->funcs->destroy(old->release_fb);
10368                 goto fail;
10369         }
10370         crtc->primary->crtc = crtc;
10371
10372         /* let the connector get through one full cycle before testing */
10373         intel_wait_for_vblank(dev, intel_crtc->pipe);
10374         return true;
10375
10376 fail:
10377         drm_atomic_state_free(state);
10378         state = NULL;
10379
10380         if (ret == -EDEADLK) {
10381                 drm_modeset_backoff(ctx);
10382                 goto retry;
10383         }
10384
10385         return false;
10386 }
10387
10388 void intel_release_load_detect_pipe(struct drm_connector *connector,
10389                                     struct intel_load_detect_pipe *old,
10390                                     struct drm_modeset_acquire_ctx *ctx)
10391 {
10392         struct drm_device *dev = connector->dev;
10393         struct intel_encoder *intel_encoder =
10394                 intel_attached_encoder(connector);
10395         struct drm_encoder *encoder = &intel_encoder->base;
10396         struct drm_crtc *crtc = encoder->crtc;
10397         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10398         struct drm_atomic_state *state;
10399         struct drm_connector_state *connector_state;
10400         struct intel_crtc_state *crtc_state;
10401         int ret;
10402
10403         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10404                       connector->base.id, connector->name,
10405                       encoder->base.id, encoder->name);
10406
10407         if (old->load_detect_temp) {
10408                 state = drm_atomic_state_alloc(dev);
10409                 if (!state)
10410                         goto fail;
10411
10412                 state->acquire_ctx = ctx;
10413
10414                 connector_state = drm_atomic_get_connector_state(state, connector);
10415                 if (IS_ERR(connector_state))
10416                         goto fail;
10417
10418                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10419                 if (IS_ERR(crtc_state))
10420                         goto fail;
10421
10422                 connector_state->best_encoder = NULL;
10423                 connector_state->crtc = NULL;
10424
10425                 crtc_state->base.enable = crtc_state->base.active = false;
10426
10427                 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10428                                                       0, 0);
10429                 if (ret)
10430                         goto fail;
10431
10432                 ret = drm_atomic_commit(state);
10433                 if (ret)
10434                         goto fail;
10435
10436                 if (old->release_fb) {
10437                         drm_framebuffer_unregister_private(old->release_fb);
10438                         drm_framebuffer_unreference(old->release_fb);
10439                 }
10440
10441                 return;
10442         }
10443
10444         /* Switch crtc and encoder back off if necessary */
10445         if (old->dpms_mode != DRM_MODE_DPMS_ON)
10446                 connector->funcs->dpms(connector, old->dpms_mode);
10447
10448         return;
10449 fail:
10450         DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10451         drm_atomic_state_free(state);
10452 }
10453
10454 static int i9xx_pll_refclk(struct drm_device *dev,
10455                            const struct intel_crtc_state *pipe_config)
10456 {
10457         struct drm_i915_private *dev_priv = dev->dev_private;
10458         u32 dpll = pipe_config->dpll_hw_state.dpll;
10459
10460         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10461                 return dev_priv->vbt.lvds_ssc_freq;
10462         else if (HAS_PCH_SPLIT(dev))
10463                 return 120000;
10464         else if (!IS_GEN2(dev))
10465                 return 96000;
10466         else
10467                 return 48000;
10468 }
10469
10470 /* Returns the clock of the currently programmed mode of the given pipe. */
10471 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10472                                 struct intel_crtc_state *pipe_config)
10473 {
10474         struct drm_device *dev = crtc->base.dev;
10475         struct drm_i915_private *dev_priv = dev->dev_private;
10476         int pipe = pipe_config->cpu_transcoder;
10477         u32 dpll = pipe_config->dpll_hw_state.dpll;
10478         u32 fp;
10479         intel_clock_t clock;
10480         int port_clock;
10481         int refclk = i9xx_pll_refclk(dev, pipe_config);
10482
10483         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10484                 fp = pipe_config->dpll_hw_state.fp0;
10485         else
10486                 fp = pipe_config->dpll_hw_state.fp1;
10487
10488         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10489         if (IS_PINEVIEW(dev)) {
10490                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10491                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10492         } else {
10493                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10494                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10495         }
10496
10497         if (!IS_GEN2(dev)) {
10498                 if (IS_PINEVIEW(dev))
10499                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10500                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10501                 else
10502                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10503                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10504
10505                 switch (dpll & DPLL_MODE_MASK) {
10506                 case DPLLB_MODE_DAC_SERIAL:
10507                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10508                                 5 : 10;
10509                         break;
10510                 case DPLLB_MODE_LVDS:
10511                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10512                                 7 : 14;
10513                         break;
10514                 default:
10515                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10516                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10517                         return;
10518                 }
10519
10520                 if (IS_PINEVIEW(dev))
10521                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10522                 else
10523                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10524         } else {
10525                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10526                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10527
10528                 if (is_lvds) {
10529                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10530                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10531
10532                         if (lvds & LVDS_CLKB_POWER_UP)
10533                                 clock.p2 = 7;
10534                         else
10535                                 clock.p2 = 14;
10536                 } else {
10537                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10538                                 clock.p1 = 2;
10539                         else {
10540                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10541                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10542                         }
10543                         if (dpll & PLL_P2_DIVIDE_BY_4)
10544                                 clock.p2 = 4;
10545                         else
10546                                 clock.p2 = 2;
10547                 }
10548
10549                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10550         }
10551
10552         /*
10553          * This value includes pixel_multiplier. We will use
10554          * port_clock to compute adjusted_mode.crtc_clock in the
10555          * encoder's get_config() function.
10556          */
10557         pipe_config->port_clock = port_clock;
10558 }
10559
10560 int intel_dotclock_calculate(int link_freq,
10561                              const struct intel_link_m_n *m_n)
10562 {
10563         /*
10564          * The calculation for the data clock is:
10565          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10566          * But we want to avoid losing precison if possible, so:
10567          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10568          *
10569          * and the link clock is simpler:
10570          * link_clock = (m * link_clock) / n
10571          */
10572
10573         if (!m_n->link_n)
10574                 return 0;
10575
10576         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10577 }
10578
10579 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10580                                    struct intel_crtc_state *pipe_config)
10581 {
10582         struct drm_device *dev = crtc->base.dev;
10583
10584         /* read out port_clock from the DPLL */
10585         i9xx_crtc_clock_get(crtc, pipe_config);
10586
10587         /*
10588          * This value does not include pixel_multiplier.
10589          * We will check that port_clock and adjusted_mode.crtc_clock
10590          * agree once we know their relationship in the encoder's
10591          * get_config() function.
10592          */
10593         pipe_config->base.adjusted_mode.crtc_clock =
10594                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10595                                          &pipe_config->fdi_m_n);
10596 }
10597
10598 /** Returns the currently programmed mode of the given pipe. */
10599 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10600                                              struct drm_crtc *crtc)
10601 {
10602         struct drm_i915_private *dev_priv = dev->dev_private;
10603         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10604         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10605         struct drm_display_mode *mode;
10606         struct intel_crtc_state pipe_config;
10607         int htot = I915_READ(HTOTAL(cpu_transcoder));
10608         int hsync = I915_READ(HSYNC(cpu_transcoder));
10609         int vtot = I915_READ(VTOTAL(cpu_transcoder));
10610         int vsync = I915_READ(VSYNC(cpu_transcoder));
10611         enum pipe pipe = intel_crtc->pipe;
10612
10613         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10614         if (!mode)
10615                 return NULL;
10616
10617         /*
10618          * Construct a pipe_config sufficient for getting the clock info
10619          * back out of crtc_clock_get.
10620          *
10621          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10622          * to use a real value here instead.
10623          */
10624         pipe_config.cpu_transcoder = (enum transcoder) pipe;
10625         pipe_config.pixel_multiplier = 1;
10626         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10627         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10628         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10629         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10630
10631         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10632         mode->hdisplay = (htot & 0xffff) + 1;
10633         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10634         mode->hsync_start = (hsync & 0xffff) + 1;
10635         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10636         mode->vdisplay = (vtot & 0xffff) + 1;
10637         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10638         mode->vsync_start = (vsync & 0xffff) + 1;
10639         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10640
10641         drm_mode_set_name(mode);
10642
10643         return mode;
10644 }
10645
10646 void intel_mark_busy(struct drm_device *dev)
10647 {
10648         struct drm_i915_private *dev_priv = dev->dev_private;
10649
10650         if (dev_priv->mm.busy)
10651                 return;
10652
10653         intel_runtime_pm_get(dev_priv);
10654         i915_update_gfx_val(dev_priv);
10655         if (INTEL_INFO(dev)->gen >= 6)
10656                 gen6_rps_busy(dev_priv);
10657         dev_priv->mm.busy = true;
10658 }
10659
10660 void intel_mark_idle(struct drm_device *dev)
10661 {
10662         struct drm_i915_private *dev_priv = dev->dev_private;
10663
10664         if (!dev_priv->mm.busy)
10665                 return;
10666
10667         dev_priv->mm.busy = false;
10668
10669         if (INTEL_INFO(dev)->gen >= 6)
10670                 gen6_rps_idle(dev->dev_private);
10671
10672         intel_runtime_pm_put(dev_priv);
10673 }
10674
10675 static void intel_crtc_destroy(struct drm_crtc *crtc)
10676 {
10677         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10678         struct drm_device *dev = crtc->dev;
10679         struct intel_unpin_work *work;
10680
10681         spin_lock_irq(&dev->event_lock);
10682         work = intel_crtc->unpin_work;
10683         intel_crtc->unpin_work = NULL;
10684         spin_unlock_irq(&dev->event_lock);
10685
10686         if (work) {
10687                 cancel_work_sync(&work->work);
10688                 kfree(work);
10689         }
10690
10691         drm_crtc_cleanup(crtc);
10692
10693         kfree(intel_crtc);
10694 }
10695
10696 static void intel_unpin_work_fn(struct work_struct *__work)
10697 {
10698         struct intel_unpin_work *work =
10699                 container_of(__work, struct intel_unpin_work, work);
10700         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10701         struct drm_device *dev = crtc->base.dev;
10702         struct drm_plane *primary = crtc->base.primary;
10703
10704         mutex_lock(&dev->struct_mutex);
10705         intel_unpin_fb_obj(work->old_fb, primary->state);
10706         drm_gem_object_unreference(&work->pending_flip_obj->base);
10707
10708         if (work->flip_queued_req)
10709                 i915_gem_request_assign(&work->flip_queued_req, NULL);
10710         mutex_unlock(&dev->struct_mutex);
10711
10712         intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10713         drm_framebuffer_unreference(work->old_fb);
10714
10715         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10716         atomic_dec(&crtc->unpin_work_count);
10717
10718         kfree(work);
10719 }
10720
10721 static void do_intel_finish_page_flip(struct drm_device *dev,
10722                                       struct drm_crtc *crtc)
10723 {
10724         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10725         struct intel_unpin_work *work;
10726         unsigned long flags;
10727
10728         /* Ignore early vblank irqs */
10729         if (intel_crtc == NULL)
10730                 return;
10731
10732         /*
10733          * This is called both by irq handlers and the reset code (to complete
10734          * lost pageflips) so needs the full irqsave spinlocks.
10735          */
10736         spin_lock_irqsave(&dev->event_lock, flags);
10737         work = intel_crtc->unpin_work;
10738
10739         /* Ensure we don't miss a work->pending update ... */
10740         smp_rmb();
10741
10742         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10743                 spin_unlock_irqrestore(&dev->event_lock, flags);
10744                 return;
10745         }
10746
10747         page_flip_completed(intel_crtc);
10748
10749         spin_unlock_irqrestore(&dev->event_lock, flags);
10750 }
10751
10752 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10753 {
10754         struct drm_i915_private *dev_priv = dev->dev_private;
10755         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10756
10757         do_intel_finish_page_flip(dev, crtc);
10758 }
10759
10760 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10761 {
10762         struct drm_i915_private *dev_priv = dev->dev_private;
10763         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10764
10765         do_intel_finish_page_flip(dev, crtc);
10766 }
10767
10768 /* Is 'a' after or equal to 'b'? */
10769 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10770 {
10771         return !((a - b) & 0x80000000);
10772 }
10773
10774 static bool page_flip_finished(struct intel_crtc *crtc)
10775 {
10776         struct drm_device *dev = crtc->base.dev;
10777         struct drm_i915_private *dev_priv = dev->dev_private;
10778
10779         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10780             crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10781                 return true;
10782
10783         /*
10784          * The relevant registers doen't exist on pre-ctg.
10785          * As the flip done interrupt doesn't trigger for mmio
10786          * flips on gmch platforms, a flip count check isn't
10787          * really needed there. But since ctg has the registers,
10788          * include it in the check anyway.
10789          */
10790         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10791                 return true;
10792
10793         /*
10794          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10795          * used the same base address. In that case the mmio flip might
10796          * have completed, but the CS hasn't even executed the flip yet.
10797          *
10798          * A flip count check isn't enough as the CS might have updated
10799          * the base address just after start of vblank, but before we
10800          * managed to process the interrupt. This means we'd complete the
10801          * CS flip too soon.
10802          *
10803          * Combining both checks should get us a good enough result. It may
10804          * still happen that the CS flip has been executed, but has not
10805          * yet actually completed. But in case the base address is the same
10806          * anyway, we don't really care.
10807          */
10808         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10809                 crtc->unpin_work->gtt_offset &&
10810                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10811                                     crtc->unpin_work->flip_count);
10812 }
10813
10814 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10815 {
10816         struct drm_i915_private *dev_priv = dev->dev_private;
10817         struct intel_crtc *intel_crtc =
10818                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10819         unsigned long flags;
10820
10821
10822         /*
10823          * This is called both by irq handlers and the reset code (to complete
10824          * lost pageflips) so needs the full irqsave spinlocks.
10825          *
10826          * NB: An MMIO update of the plane base pointer will also
10827          * generate a page-flip completion irq, i.e. every modeset
10828          * is also accompanied by a spurious intel_prepare_page_flip().
10829          */
10830         spin_lock_irqsave(&dev->event_lock, flags);
10831         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10832                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10833         spin_unlock_irqrestore(&dev->event_lock, flags);
10834 }
10835
10836 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10837 {
10838         /* Ensure that the work item is consistent when activating it ... */
10839         smp_wmb();
10840         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10841         /* and that it is marked active as soon as the irq could fire. */
10842         smp_wmb();
10843 }
10844
10845 static int intel_gen2_queue_flip(struct drm_device *dev,
10846                                  struct drm_crtc *crtc,
10847                                  struct drm_framebuffer *fb,
10848                                  struct drm_i915_gem_object *obj,
10849                                  struct drm_i915_gem_request *req,
10850                                  uint32_t flags)
10851 {
10852         struct intel_engine_cs *ring = req->ring;
10853         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10854         u32 flip_mask;
10855         int ret;
10856
10857         ret = intel_ring_begin(req, 6);
10858         if (ret)
10859                 return ret;
10860
10861         /* Can't queue multiple flips, so wait for the previous
10862          * one to finish before executing the next.
10863          */
10864         if (intel_crtc->plane)
10865                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10866         else
10867                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10868         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10869         intel_ring_emit(ring, MI_NOOP);
10870         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10871                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10872         intel_ring_emit(ring, fb->pitches[0]);
10873         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10874         intel_ring_emit(ring, 0); /* aux display base address, unused */
10875
10876         intel_mark_page_flip_active(intel_crtc);
10877         return 0;
10878 }
10879
10880 static int intel_gen3_queue_flip(struct drm_device *dev,
10881                                  struct drm_crtc *crtc,
10882                                  struct drm_framebuffer *fb,
10883                                  struct drm_i915_gem_object *obj,
10884                                  struct drm_i915_gem_request *req,
10885                                  uint32_t flags)
10886 {
10887         struct intel_engine_cs *ring = req->ring;
10888         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10889         u32 flip_mask;
10890         int ret;
10891
10892         ret = intel_ring_begin(req, 6);
10893         if (ret)
10894                 return ret;
10895
10896         if (intel_crtc->plane)
10897                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10898         else
10899                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10900         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10901         intel_ring_emit(ring, MI_NOOP);
10902         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10903                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10904         intel_ring_emit(ring, fb->pitches[0]);
10905         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10906         intel_ring_emit(ring, MI_NOOP);
10907
10908         intel_mark_page_flip_active(intel_crtc);
10909         return 0;
10910 }
10911
10912 static int intel_gen4_queue_flip(struct drm_device *dev,
10913                                  struct drm_crtc *crtc,
10914                                  struct drm_framebuffer *fb,
10915                                  struct drm_i915_gem_object *obj,
10916                                  struct drm_i915_gem_request *req,
10917                                  uint32_t flags)
10918 {
10919         struct intel_engine_cs *ring = req->ring;
10920         struct drm_i915_private *dev_priv = dev->dev_private;
10921         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10922         uint32_t pf, pipesrc;
10923         int ret;
10924
10925         ret = intel_ring_begin(req, 4);
10926         if (ret)
10927                 return ret;
10928
10929         /* i965+ uses the linear or tiled offsets from the
10930          * Display Registers (which do not change across a page-flip)
10931          * so we need only reprogram the base address.
10932          */
10933         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10934                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10935         intel_ring_emit(ring, fb->pitches[0]);
10936         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
10937                         obj->tiling_mode);
10938
10939         /* XXX Enabling the panel-fitter across page-flip is so far
10940          * untested on non-native modes, so ignore it for now.
10941          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10942          */
10943         pf = 0;
10944         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10945         intel_ring_emit(ring, pf | pipesrc);
10946
10947         intel_mark_page_flip_active(intel_crtc);
10948         return 0;
10949 }
10950
10951 static int intel_gen6_queue_flip(struct drm_device *dev,
10952                                  struct drm_crtc *crtc,
10953                                  struct drm_framebuffer *fb,
10954                                  struct drm_i915_gem_object *obj,
10955                                  struct drm_i915_gem_request *req,
10956                                  uint32_t flags)
10957 {
10958         struct intel_engine_cs *ring = req->ring;
10959         struct drm_i915_private *dev_priv = dev->dev_private;
10960         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10961         uint32_t pf, pipesrc;
10962         int ret;
10963
10964         ret = intel_ring_begin(req, 4);
10965         if (ret)
10966                 return ret;
10967
10968         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10969                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10970         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
10971         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10972
10973         /* Contrary to the suggestions in the documentation,
10974          * "Enable Panel Fitter" does not seem to be required when page
10975          * flipping with a non-native mode, and worse causes a normal
10976          * modeset to fail.
10977          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10978          */
10979         pf = 0;
10980         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10981         intel_ring_emit(ring, pf | pipesrc);
10982
10983         intel_mark_page_flip_active(intel_crtc);
10984         return 0;
10985 }
10986
10987 static int intel_gen7_queue_flip(struct drm_device *dev,
10988                                  struct drm_crtc *crtc,
10989                                  struct drm_framebuffer *fb,
10990                                  struct drm_i915_gem_object *obj,
10991                                  struct drm_i915_gem_request *req,
10992                                  uint32_t flags)
10993 {
10994         struct intel_engine_cs *ring = req->ring;
10995         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10996         uint32_t plane_bit = 0;
10997         int len, ret;
10998
10999         switch (intel_crtc->plane) {
11000         case PLANE_A:
11001                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11002                 break;
11003         case PLANE_B:
11004                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11005                 break;
11006         case PLANE_C:
11007                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11008                 break;
11009         default:
11010                 WARN_ONCE(1, "unknown plane in flip command\n");
11011                 return -ENODEV;
11012         }
11013
11014         len = 4;
11015         if (ring->id == RCS) {
11016                 len += 6;
11017                 /*
11018                  * On Gen 8, SRM is now taking an extra dword to accommodate
11019                  * 48bits addresses, and we need a NOOP for the batch size to
11020                  * stay even.
11021                  */
11022                 if (IS_GEN8(dev))
11023                         len += 2;
11024         }
11025
11026         /*
11027          * BSpec MI_DISPLAY_FLIP for IVB:
11028          * "The full packet must be contained within the same cache line."
11029          *
11030          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11031          * cacheline, if we ever start emitting more commands before
11032          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11033          * then do the cacheline alignment, and finally emit the
11034          * MI_DISPLAY_FLIP.
11035          */
11036         ret = intel_ring_cacheline_align(req);
11037         if (ret)
11038                 return ret;
11039
11040         ret = intel_ring_begin(req, len);
11041         if (ret)
11042                 return ret;
11043
11044         /* Unmask the flip-done completion message. Note that the bspec says that
11045          * we should do this for both the BCS and RCS, and that we must not unmask
11046          * more than one flip event at any time (or ensure that one flip message
11047          * can be sent by waiting for flip-done prior to queueing new flips).
11048          * Experimentation says that BCS works despite DERRMR masking all
11049          * flip-done completion events and that unmasking all planes at once
11050          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11051          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11052          */
11053         if (ring->id == RCS) {
11054                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11055                 intel_ring_emit(ring, DERRMR);
11056                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11057                                         DERRMR_PIPEB_PRI_FLIP_DONE |
11058                                         DERRMR_PIPEC_PRI_FLIP_DONE));
11059                 if (IS_GEN8(dev))
11060                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11061                                               MI_SRM_LRM_GLOBAL_GTT);
11062                 else
11063                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11064                                               MI_SRM_LRM_GLOBAL_GTT);
11065                 intel_ring_emit(ring, DERRMR);
11066                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11067                 if (IS_GEN8(dev)) {
11068                         intel_ring_emit(ring, 0);
11069                         intel_ring_emit(ring, MI_NOOP);
11070                 }
11071         }
11072
11073         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11074         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11075         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11076         intel_ring_emit(ring, (MI_NOOP));
11077
11078         intel_mark_page_flip_active(intel_crtc);
11079         return 0;
11080 }
11081
11082 static bool use_mmio_flip(struct intel_engine_cs *ring,
11083                           struct drm_i915_gem_object *obj)
11084 {
11085         /*
11086          * This is not being used for older platforms, because
11087          * non-availability of flip done interrupt forces us to use
11088          * CS flips. Older platforms derive flip done using some clever
11089          * tricks involving the flip_pending status bits and vblank irqs.
11090          * So using MMIO flips there would disrupt this mechanism.
11091          */
11092
11093         if (ring == NULL)
11094                 return true;
11095
11096         if (INTEL_INFO(ring->dev)->gen < 5)
11097                 return false;
11098
11099         if (i915.use_mmio_flip < 0)
11100                 return false;
11101         else if (i915.use_mmio_flip > 0)
11102                 return true;
11103         else if (i915.enable_execlists)
11104                 return true;
11105         else
11106                 return ring != i915_gem_request_get_ring(obj->last_write_req);
11107 }
11108
11109 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11110 {
11111         struct drm_device *dev = intel_crtc->base.dev;
11112         struct drm_i915_private *dev_priv = dev->dev_private;
11113         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11114         const enum pipe pipe = intel_crtc->pipe;
11115         u32 ctl, stride;
11116
11117         ctl = I915_READ(PLANE_CTL(pipe, 0));
11118         ctl &= ~PLANE_CTL_TILED_MASK;
11119         switch (fb->modifier[0]) {
11120         case DRM_FORMAT_MOD_NONE:
11121                 break;
11122         case I915_FORMAT_MOD_X_TILED:
11123                 ctl |= PLANE_CTL_TILED_X;
11124                 break;
11125         case I915_FORMAT_MOD_Y_TILED:
11126                 ctl |= PLANE_CTL_TILED_Y;
11127                 break;
11128         case I915_FORMAT_MOD_Yf_TILED:
11129                 ctl |= PLANE_CTL_TILED_YF;
11130                 break;
11131         default:
11132                 MISSING_CASE(fb->modifier[0]);
11133         }
11134
11135         /*
11136          * The stride is either expressed as a multiple of 64 bytes chunks for
11137          * linear buffers or in number of tiles for tiled buffers.
11138          */
11139         stride = fb->pitches[0] /
11140                  intel_fb_stride_alignment(dev, fb->modifier[0],
11141                                            fb->pixel_format);
11142
11143         /*
11144          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11145          * PLANE_SURF updates, the update is then guaranteed to be atomic.
11146          */
11147         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11148         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11149
11150         I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11151         POSTING_READ(PLANE_SURF(pipe, 0));
11152 }
11153
11154 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
11155 {
11156         struct drm_device *dev = intel_crtc->base.dev;
11157         struct drm_i915_private *dev_priv = dev->dev_private;
11158         struct intel_framebuffer *intel_fb =
11159                 to_intel_framebuffer(intel_crtc->base.primary->fb);
11160         struct drm_i915_gem_object *obj = intel_fb->obj;
11161         u32 dspcntr;
11162         u32 reg;
11163
11164         reg = DSPCNTR(intel_crtc->plane);
11165         dspcntr = I915_READ(reg);
11166
11167         if (obj->tiling_mode != I915_TILING_NONE)
11168                 dspcntr |= DISPPLANE_TILED;
11169         else
11170                 dspcntr &= ~DISPPLANE_TILED;
11171
11172         I915_WRITE(reg, dspcntr);
11173
11174         I915_WRITE(DSPSURF(intel_crtc->plane),
11175                    intel_crtc->unpin_work->gtt_offset);
11176         POSTING_READ(DSPSURF(intel_crtc->plane));
11177
11178 }
11179
11180 /*
11181  * XXX: This is the temporary way to update the plane registers until we get
11182  * around to using the usual plane update functions for MMIO flips
11183  */
11184 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11185 {
11186         struct drm_device *dev = intel_crtc->base.dev;
11187
11188         intel_mark_page_flip_active(intel_crtc);
11189
11190         intel_pipe_update_start(intel_crtc);
11191
11192         if (INTEL_INFO(dev)->gen >= 9)
11193                 skl_do_mmio_flip(intel_crtc);
11194         else
11195                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11196                 ilk_do_mmio_flip(intel_crtc);
11197
11198         intel_pipe_update_end(intel_crtc);
11199 }
11200
11201 static void intel_mmio_flip_work_func(struct work_struct *work)
11202 {
11203         struct intel_mmio_flip *mmio_flip =
11204                 container_of(work, struct intel_mmio_flip, work);
11205
11206         if (mmio_flip->req)
11207                 WARN_ON(__i915_wait_request(mmio_flip->req,
11208                                             mmio_flip->crtc->reset_counter,
11209                                             false, NULL,
11210                                             &mmio_flip->i915->rps.mmioflips));
11211
11212         intel_do_mmio_flip(mmio_flip->crtc);
11213
11214         i915_gem_request_unreference__unlocked(mmio_flip->req);
11215         kfree(mmio_flip);
11216 }
11217
11218 static int intel_queue_mmio_flip(struct drm_device *dev,
11219                                  struct drm_crtc *crtc,
11220                                  struct drm_framebuffer *fb,
11221                                  struct drm_i915_gem_object *obj,
11222                                  struct intel_engine_cs *ring,
11223                                  uint32_t flags)
11224 {
11225         struct intel_mmio_flip *mmio_flip;
11226
11227         mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11228         if (mmio_flip == NULL)
11229                 return -ENOMEM;
11230
11231         mmio_flip->i915 = to_i915(dev);
11232         mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11233         mmio_flip->crtc = to_intel_crtc(crtc);
11234
11235         INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11236         schedule_work(&mmio_flip->work);
11237
11238         return 0;
11239 }
11240
11241 static int intel_default_queue_flip(struct drm_device *dev,
11242                                     struct drm_crtc *crtc,
11243                                     struct drm_framebuffer *fb,
11244                                     struct drm_i915_gem_object *obj,
11245                                     struct drm_i915_gem_request *req,
11246                                     uint32_t flags)
11247 {
11248         return -ENODEV;
11249 }
11250
11251 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11252                                          struct drm_crtc *crtc)
11253 {
11254         struct drm_i915_private *dev_priv = dev->dev_private;
11255         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11256         struct intel_unpin_work *work = intel_crtc->unpin_work;
11257         u32 addr;
11258
11259         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11260                 return true;
11261
11262         if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11263                 return false;
11264
11265         if (!work->enable_stall_check)
11266                 return false;
11267
11268         if (work->flip_ready_vblank == 0) {
11269                 if (work->flip_queued_req &&
11270                     !i915_gem_request_completed(work->flip_queued_req, true))
11271                         return false;
11272
11273                 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11274         }
11275
11276         if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11277                 return false;
11278
11279         /* Potential stall - if we see that the flip has happened,
11280          * assume a missed interrupt. */
11281         if (INTEL_INFO(dev)->gen >= 4)
11282                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11283         else
11284                 addr = I915_READ(DSPADDR(intel_crtc->plane));
11285
11286         /* There is a potential issue here with a false positive after a flip
11287          * to the same address. We could address this by checking for a
11288          * non-incrementing frame counter.
11289          */
11290         return addr == work->gtt_offset;
11291 }
11292
11293 void intel_check_page_flip(struct drm_device *dev, int pipe)
11294 {
11295         struct drm_i915_private *dev_priv = dev->dev_private;
11296         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11297         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11298         struct intel_unpin_work *work;
11299
11300         WARN_ON(!in_interrupt());
11301
11302         if (crtc == NULL)
11303                 return;
11304
11305         spin_lock(&dev->event_lock);
11306         work = intel_crtc->unpin_work;
11307         if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11308                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11309                          work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11310                 page_flip_completed(intel_crtc);
11311                 work = NULL;
11312         }
11313         if (work != NULL &&
11314             drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11315                 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11316         spin_unlock(&dev->event_lock);
11317 }
11318
11319 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11320                                 struct drm_framebuffer *fb,
11321                                 struct drm_pending_vblank_event *event,
11322                                 uint32_t page_flip_flags)
11323 {
11324         struct drm_device *dev = crtc->dev;
11325         struct drm_i915_private *dev_priv = dev->dev_private;
11326         struct drm_framebuffer *old_fb = crtc->primary->fb;
11327         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11328         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11329         struct drm_plane *primary = crtc->primary;
11330         enum pipe pipe = intel_crtc->pipe;
11331         struct intel_unpin_work *work;
11332         struct intel_engine_cs *ring;
11333         bool mmio_flip;
11334         struct drm_i915_gem_request *request = NULL;
11335         int ret;
11336
11337         /*
11338          * drm_mode_page_flip_ioctl() should already catch this, but double
11339          * check to be safe.  In the future we may enable pageflipping from
11340          * a disabled primary plane.
11341          */
11342         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11343                 return -EBUSY;
11344
11345         /* Can't change pixel format via MI display flips. */
11346         if (fb->pixel_format != crtc->primary->fb->pixel_format)
11347                 return -EINVAL;
11348
11349         /*
11350          * TILEOFF/LINOFF registers can't be changed via MI display flips.
11351          * Note that pitch changes could also affect these register.
11352          */
11353         if (INTEL_INFO(dev)->gen > 3 &&
11354             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11355              fb->pitches[0] != crtc->primary->fb->pitches[0]))
11356                 return -EINVAL;
11357
11358         if (i915_terminally_wedged(&dev_priv->gpu_error))
11359                 goto out_hang;
11360
11361         work = kzalloc(sizeof(*work), GFP_KERNEL);
11362         if (work == NULL)
11363                 return -ENOMEM;
11364
11365         work->event = event;
11366         work->crtc = crtc;
11367         work->old_fb = old_fb;
11368         INIT_WORK(&work->work, intel_unpin_work_fn);
11369
11370         ret = drm_crtc_vblank_get(crtc);
11371         if (ret)
11372                 goto free_work;
11373
11374         /* We borrow the event spin lock for protecting unpin_work */
11375         spin_lock_irq(&dev->event_lock);
11376         if (intel_crtc->unpin_work) {
11377                 /* Before declaring the flip queue wedged, check if
11378                  * the hardware completed the operation behind our backs.
11379                  */
11380                 if (__intel_pageflip_stall_check(dev, crtc)) {
11381                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11382                         page_flip_completed(intel_crtc);
11383                 } else {
11384                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11385                         spin_unlock_irq(&dev->event_lock);
11386
11387                         drm_crtc_vblank_put(crtc);
11388                         kfree(work);
11389                         return -EBUSY;
11390                 }
11391         }
11392         intel_crtc->unpin_work = work;
11393         spin_unlock_irq(&dev->event_lock);
11394
11395         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11396                 flush_workqueue(dev_priv->wq);
11397
11398         /* Reference the objects for the scheduled work. */
11399         drm_framebuffer_reference(work->old_fb);
11400         drm_gem_object_reference(&obj->base);
11401
11402         crtc->primary->fb = fb;
11403         update_state_fb(crtc->primary);
11404
11405         work->pending_flip_obj = obj;
11406
11407         ret = i915_mutex_lock_interruptible(dev);
11408         if (ret)
11409                 goto cleanup;
11410
11411         atomic_inc(&intel_crtc->unpin_work_count);
11412         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11413
11414         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11415                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
11416
11417         if (IS_VALLEYVIEW(dev)) {
11418                 ring = &dev_priv->ring[BCS];
11419                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11420                         /* vlv: DISPLAY_FLIP fails to change tiling */
11421                         ring = NULL;
11422         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11423                 ring = &dev_priv->ring[BCS];
11424         } else if (INTEL_INFO(dev)->gen >= 7) {
11425                 ring = i915_gem_request_get_ring(obj->last_write_req);
11426                 if (ring == NULL || ring->id != RCS)
11427                         ring = &dev_priv->ring[BCS];
11428         } else {
11429                 ring = &dev_priv->ring[RCS];
11430         }
11431
11432         mmio_flip = use_mmio_flip(ring, obj);
11433
11434         /* When using CS flips, we want to emit semaphores between rings.
11435          * However, when using mmio flips we will create a task to do the
11436          * synchronisation, so all we want here is to pin the framebuffer
11437          * into the display plane and skip any waits.
11438          */
11439         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11440                                          crtc->primary->state,
11441                                          mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
11442         if (ret)
11443                 goto cleanup_pending;
11444
11445         work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11446                                                   obj, 0);
11447         work->gtt_offset += intel_crtc->dspaddr_offset;
11448
11449         if (mmio_flip) {
11450                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11451                                             page_flip_flags);
11452                 if (ret)
11453                         goto cleanup_unpin;
11454
11455                 i915_gem_request_assign(&work->flip_queued_req,
11456                                         obj->last_write_req);
11457         } else {
11458                 if (!request) {
11459                         ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11460                         if (ret)
11461                                 goto cleanup_unpin;
11462                 }
11463
11464                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11465                                                    page_flip_flags);
11466                 if (ret)
11467                         goto cleanup_unpin;
11468
11469                 i915_gem_request_assign(&work->flip_queued_req, request);
11470         }
11471
11472         if (request)
11473                 i915_add_request_no_flush(request);
11474
11475         work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11476         work->enable_stall_check = true;
11477
11478         i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11479                           to_intel_plane(primary)->frontbuffer_bit);
11480         mutex_unlock(&dev->struct_mutex);
11481
11482         intel_fbc_disable_crtc(intel_crtc);
11483         intel_frontbuffer_flip_prepare(dev,
11484                                        to_intel_plane(primary)->frontbuffer_bit);
11485
11486         trace_i915_flip_request(intel_crtc->plane, obj);
11487
11488         return 0;
11489
11490 cleanup_unpin:
11491         intel_unpin_fb_obj(fb, crtc->primary->state);
11492 cleanup_pending:
11493         if (request)
11494                 i915_gem_request_cancel(request);
11495         atomic_dec(&intel_crtc->unpin_work_count);
11496         mutex_unlock(&dev->struct_mutex);
11497 cleanup:
11498         crtc->primary->fb = old_fb;
11499         update_state_fb(crtc->primary);
11500
11501         drm_gem_object_unreference_unlocked(&obj->base);
11502         drm_framebuffer_unreference(work->old_fb);
11503
11504         spin_lock_irq(&dev->event_lock);
11505         intel_crtc->unpin_work = NULL;
11506         spin_unlock_irq(&dev->event_lock);
11507
11508         drm_crtc_vblank_put(crtc);
11509 free_work:
11510         kfree(work);
11511
11512         if (ret == -EIO) {
11513                 struct drm_atomic_state *state;
11514                 struct drm_plane_state *plane_state;
11515
11516 out_hang:
11517                 state = drm_atomic_state_alloc(dev);
11518                 if (!state)
11519                         return -ENOMEM;
11520                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11521
11522 retry:
11523                 plane_state = drm_atomic_get_plane_state(state, primary);
11524                 ret = PTR_ERR_OR_ZERO(plane_state);
11525                 if (!ret) {
11526                         drm_atomic_set_fb_for_plane(plane_state, fb);
11527
11528                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11529                         if (!ret)
11530                                 ret = drm_atomic_commit(state);
11531                 }
11532
11533                 if (ret == -EDEADLK) {
11534                         drm_modeset_backoff(state->acquire_ctx);
11535                         drm_atomic_state_clear(state);
11536                         goto retry;
11537                 }
11538
11539                 if (ret)
11540                         drm_atomic_state_free(state);
11541
11542                 if (ret == 0 && event) {
11543                         spin_lock_irq(&dev->event_lock);
11544                         drm_send_vblank_event(dev, pipe, event);
11545                         spin_unlock_irq(&dev->event_lock);
11546                 }
11547         }
11548         return ret;
11549 }
11550
11551
11552 /**
11553  * intel_wm_need_update - Check whether watermarks need updating
11554  * @plane: drm plane
11555  * @state: new plane state
11556  *
11557  * Check current plane state versus the new one to determine whether
11558  * watermarks need to be recalculated.
11559  *
11560  * Returns true or false.
11561  */
11562 static bool intel_wm_need_update(struct drm_plane *plane,
11563                                  struct drm_plane_state *state)
11564 {
11565         /* Update watermarks on tiling changes. */
11566         if (!plane->state->fb || !state->fb ||
11567             plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11568             plane->state->rotation != state->rotation)
11569                 return true;
11570
11571         if (plane->state->crtc_w != state->crtc_w)
11572                 return true;
11573
11574         return false;
11575 }
11576
11577 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11578                                     struct drm_plane_state *plane_state)
11579 {
11580         struct drm_crtc *crtc = crtc_state->crtc;
11581         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11582         struct drm_plane *plane = plane_state->plane;
11583         struct drm_device *dev = crtc->dev;
11584         struct drm_i915_private *dev_priv = dev->dev_private;
11585         struct intel_plane_state *old_plane_state =
11586                 to_intel_plane_state(plane->state);
11587         int idx = intel_crtc->base.base.id, ret;
11588         int i = drm_plane_index(plane);
11589         bool mode_changed = needs_modeset(crtc_state);
11590         bool was_crtc_enabled = crtc->state->active;
11591         bool is_crtc_enabled = crtc_state->active;
11592
11593         bool turn_off, turn_on, visible, was_visible;
11594         struct drm_framebuffer *fb = plane_state->fb;
11595
11596         if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11597             plane->type != DRM_PLANE_TYPE_CURSOR) {
11598                 ret = skl_update_scaler_plane(
11599                         to_intel_crtc_state(crtc_state),
11600                         to_intel_plane_state(plane_state));
11601                 if (ret)
11602                         return ret;
11603         }
11604
11605         /*
11606          * Disabling a plane is always okay; we just need to update
11607          * fb tracking in a special way since cleanup_fb() won't
11608          * get called by the plane helpers.
11609          */
11610         if (old_plane_state->base.fb && !fb)
11611                 intel_crtc->atomic.disabled_planes |= 1 << i;
11612
11613         was_visible = old_plane_state->visible;
11614         visible = to_intel_plane_state(plane_state)->visible;
11615
11616         if (!was_crtc_enabled && WARN_ON(was_visible))
11617                 was_visible = false;
11618
11619         if (!is_crtc_enabled && WARN_ON(visible))
11620                 visible = false;
11621
11622         if (!was_visible && !visible)
11623                 return 0;
11624
11625         turn_off = was_visible && (!visible || mode_changed);
11626         turn_on = visible && (!was_visible || mode_changed);
11627
11628         DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11629                          plane->base.id, fb ? fb->base.id : -1);
11630
11631         DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11632                          plane->base.id, was_visible, visible,
11633                          turn_off, turn_on, mode_changed);
11634
11635         if (turn_on) {
11636                 intel_crtc->atomic.update_wm_pre = true;
11637                 /* must disable cxsr around plane enable/disable */
11638                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11639                         intel_crtc->atomic.disable_cxsr = true;
11640                         /* to potentially re-enable cxsr */
11641                         intel_crtc->atomic.wait_vblank = true;
11642                         intel_crtc->atomic.update_wm_post = true;
11643                 }
11644         } else if (turn_off) {
11645                 intel_crtc->atomic.update_wm_post = true;
11646                 /* must disable cxsr around plane enable/disable */
11647                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11648                         if (is_crtc_enabled)
11649                                 intel_crtc->atomic.wait_vblank = true;
11650                         intel_crtc->atomic.disable_cxsr = true;
11651                 }
11652         } else if (intel_wm_need_update(plane, plane_state)) {
11653                 intel_crtc->atomic.update_wm_pre = true;
11654         }
11655
11656         if (visible || was_visible)
11657                 intel_crtc->atomic.fb_bits |=
11658                         to_intel_plane(plane)->frontbuffer_bit;
11659
11660         switch (plane->type) {
11661         case DRM_PLANE_TYPE_PRIMARY:
11662                 intel_crtc->atomic.wait_for_flips = true;
11663                 intel_crtc->atomic.pre_disable_primary = turn_off;
11664                 intel_crtc->atomic.post_enable_primary = turn_on;
11665
11666                 if (turn_off) {
11667                         /*
11668                          * FIXME: Actually if we will still have any other
11669                          * plane enabled on the pipe we could let IPS enabled
11670                          * still, but for now lets consider that when we make
11671                          * primary invisible by setting DSPCNTR to 0 on
11672                          * update_primary_plane function IPS needs to be
11673                          * disable.
11674                          */
11675                         intel_crtc->atomic.disable_ips = true;
11676
11677                         intel_crtc->atomic.disable_fbc = true;
11678                 }
11679
11680                 /*
11681                  * FBC does not work on some platforms for rotated
11682                  * planes, so disable it when rotation is not 0 and
11683                  * update it when rotation is set back to 0.
11684                  *
11685                  * FIXME: This is redundant with the fbc update done in
11686                  * the primary plane enable function except that that
11687                  * one is done too late. We eventually need to unify
11688                  * this.
11689                  */
11690
11691                 if (visible &&
11692                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11693                     dev_priv->fbc.crtc == intel_crtc &&
11694                     plane_state->rotation != BIT(DRM_ROTATE_0))
11695                         intel_crtc->atomic.disable_fbc = true;
11696
11697                 /*
11698                  * BDW signals flip done immediately if the plane
11699                  * is disabled, even if the plane enable is already
11700                  * armed to occur at the next vblank :(
11701                  */
11702                 if (turn_on && IS_BROADWELL(dev))
11703                         intel_crtc->atomic.wait_vblank = true;
11704
11705                 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11706                 break;
11707         case DRM_PLANE_TYPE_CURSOR:
11708                 break;
11709         case DRM_PLANE_TYPE_OVERLAY:
11710                 if (turn_off && !mode_changed) {
11711                         intel_crtc->atomic.wait_vblank = true;
11712                         intel_crtc->atomic.update_sprite_watermarks |=
11713                                 1 << i;
11714                 }
11715         }
11716         return 0;
11717 }
11718
11719 static bool encoders_cloneable(const struct intel_encoder *a,
11720                                const struct intel_encoder *b)
11721 {
11722         /* masks could be asymmetric, so check both ways */
11723         return a == b || (a->cloneable & (1 << b->type) &&
11724                           b->cloneable & (1 << a->type));
11725 }
11726
11727 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11728                                          struct intel_crtc *crtc,
11729                                          struct intel_encoder *encoder)
11730 {
11731         struct intel_encoder *source_encoder;
11732         struct drm_connector *connector;
11733         struct drm_connector_state *connector_state;
11734         int i;
11735
11736         for_each_connector_in_state(state, connector, connector_state, i) {
11737                 if (connector_state->crtc != &crtc->base)
11738                         continue;
11739
11740                 source_encoder =
11741                         to_intel_encoder(connector_state->best_encoder);
11742                 if (!encoders_cloneable(encoder, source_encoder))
11743                         return false;
11744         }
11745
11746         return true;
11747 }
11748
11749 static bool check_encoder_cloning(struct drm_atomic_state *state,
11750                                   struct intel_crtc *crtc)
11751 {
11752         struct intel_encoder *encoder;
11753         struct drm_connector *connector;
11754         struct drm_connector_state *connector_state;
11755         int i;
11756
11757         for_each_connector_in_state(state, connector, connector_state, i) {
11758                 if (connector_state->crtc != &crtc->base)
11759                         continue;
11760
11761                 encoder = to_intel_encoder(connector_state->best_encoder);
11762                 if (!check_single_encoder_cloning(state, crtc, encoder))
11763                         return false;
11764         }
11765
11766         return true;
11767 }
11768
11769 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11770                                    struct drm_crtc_state *crtc_state)
11771 {
11772         struct drm_device *dev = crtc->dev;
11773         struct drm_i915_private *dev_priv = dev->dev_private;
11774         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11775         struct intel_crtc_state *pipe_config =
11776                 to_intel_crtc_state(crtc_state);
11777         struct drm_atomic_state *state = crtc_state->state;
11778         int ret;
11779         bool mode_changed = needs_modeset(crtc_state);
11780
11781         if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11782                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11783                 return -EINVAL;
11784         }
11785
11786         if (mode_changed && !crtc_state->active)
11787                 intel_crtc->atomic.update_wm_post = true;
11788
11789         if (mode_changed && crtc_state->enable &&
11790             dev_priv->display.crtc_compute_clock &&
11791             !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11792                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11793                                                            pipe_config);
11794                 if (ret)
11795                         return ret;
11796         }
11797
11798         ret = 0;
11799         if (INTEL_INFO(dev)->gen >= 9) {
11800                 if (mode_changed)
11801                         ret = skl_update_scaler_crtc(pipe_config);
11802
11803                 if (!ret)
11804                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
11805                                                          pipe_config);
11806         }
11807
11808         return ret;
11809 }
11810
11811 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11812         .mode_set_base_atomic = intel_pipe_set_base_atomic,
11813         .load_lut = intel_crtc_load_lut,
11814         .atomic_begin = intel_begin_crtc_commit,
11815         .atomic_flush = intel_finish_crtc_commit,
11816         .atomic_check = intel_crtc_atomic_check,
11817 };
11818
11819 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11820 {
11821         struct intel_connector *connector;
11822
11823         for_each_intel_connector(dev, connector) {
11824                 if (connector->base.encoder) {
11825                         connector->base.state->best_encoder =
11826                                 connector->base.encoder;
11827                         connector->base.state->crtc =
11828                                 connector->base.encoder->crtc;
11829                 } else {
11830                         connector->base.state->best_encoder = NULL;
11831                         connector->base.state->crtc = NULL;
11832                 }
11833         }
11834 }
11835
11836 static void
11837 connected_sink_compute_bpp(struct intel_connector *connector,
11838                            struct intel_crtc_state *pipe_config)
11839 {
11840         int bpp = pipe_config->pipe_bpp;
11841
11842         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11843                 connector->base.base.id,
11844                 connector->base.name);
11845
11846         /* Don't use an invalid EDID bpc value */
11847         if (connector->base.display_info.bpc &&
11848             connector->base.display_info.bpc * 3 < bpp) {
11849                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11850                               bpp, connector->base.display_info.bpc*3);
11851                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11852         }
11853
11854         /* Clamp bpp to 8 on screens without EDID 1.4 */
11855         if (connector->base.display_info.bpc == 0 && bpp > 24) {
11856                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11857                               bpp);
11858                 pipe_config->pipe_bpp = 24;
11859         }
11860 }
11861
11862 static int
11863 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11864                           struct intel_crtc_state *pipe_config)
11865 {
11866         struct drm_device *dev = crtc->base.dev;
11867         struct drm_atomic_state *state;
11868         struct drm_connector *connector;
11869         struct drm_connector_state *connector_state;
11870         int bpp, i;
11871
11872         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11873                 bpp = 10*3;
11874         else if (INTEL_INFO(dev)->gen >= 5)
11875                 bpp = 12*3;
11876         else
11877                 bpp = 8*3;
11878
11879
11880         pipe_config->pipe_bpp = bpp;
11881
11882         state = pipe_config->base.state;
11883
11884         /* Clamp display bpp to EDID value */
11885         for_each_connector_in_state(state, connector, connector_state, i) {
11886                 if (connector_state->crtc != &crtc->base)
11887                         continue;
11888
11889                 connected_sink_compute_bpp(to_intel_connector(connector),
11890                                            pipe_config);
11891         }
11892
11893         return bpp;
11894 }
11895
11896 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11897 {
11898         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11899                         "type: 0x%x flags: 0x%x\n",
11900                 mode->crtc_clock,
11901                 mode->crtc_hdisplay, mode->crtc_hsync_start,
11902                 mode->crtc_hsync_end, mode->crtc_htotal,
11903                 mode->crtc_vdisplay, mode->crtc_vsync_start,
11904                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11905 }
11906
11907 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11908                                    struct intel_crtc_state *pipe_config,
11909                                    const char *context)
11910 {
11911         struct drm_device *dev = crtc->base.dev;
11912         struct drm_plane *plane;
11913         struct intel_plane *intel_plane;
11914         struct intel_plane_state *state;
11915         struct drm_framebuffer *fb;
11916
11917         DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11918                       context, pipe_config, pipe_name(crtc->pipe));
11919
11920         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11921         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11922                       pipe_config->pipe_bpp, pipe_config->dither);
11923         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11924                       pipe_config->has_pch_encoder,
11925                       pipe_config->fdi_lanes,
11926                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11927                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11928                       pipe_config->fdi_m_n.tu);
11929         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11930                       pipe_config->has_dp_encoder,
11931                       pipe_config->lane_count,
11932                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11933                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11934                       pipe_config->dp_m_n.tu);
11935
11936         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11937                       pipe_config->has_dp_encoder,
11938                       pipe_config->lane_count,
11939                       pipe_config->dp_m2_n2.gmch_m,
11940                       pipe_config->dp_m2_n2.gmch_n,
11941                       pipe_config->dp_m2_n2.link_m,
11942                       pipe_config->dp_m2_n2.link_n,
11943                       pipe_config->dp_m2_n2.tu);
11944
11945         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11946                       pipe_config->has_audio,
11947                       pipe_config->has_infoframe);
11948
11949         DRM_DEBUG_KMS("requested mode:\n");
11950         drm_mode_debug_printmodeline(&pipe_config->base.mode);
11951         DRM_DEBUG_KMS("adjusted mode:\n");
11952         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11953         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11954         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
11955         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11956                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
11957         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11958                       crtc->num_scalers,
11959                       pipe_config->scaler_state.scaler_users,
11960                       pipe_config->scaler_state.scaler_id);
11961         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11962                       pipe_config->gmch_pfit.control,
11963                       pipe_config->gmch_pfit.pgm_ratios,
11964                       pipe_config->gmch_pfit.lvds_border_bits);
11965         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11966                       pipe_config->pch_pfit.pos,
11967                       pipe_config->pch_pfit.size,
11968                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
11969         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
11970         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
11971
11972         if (IS_BROXTON(dev)) {
11973                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
11974                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11975                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
11976                               pipe_config->ddi_pll_sel,
11977                               pipe_config->dpll_hw_state.ebb0,
11978                               pipe_config->dpll_hw_state.ebb4,
11979                               pipe_config->dpll_hw_state.pll0,
11980                               pipe_config->dpll_hw_state.pll1,
11981                               pipe_config->dpll_hw_state.pll2,
11982                               pipe_config->dpll_hw_state.pll3,
11983                               pipe_config->dpll_hw_state.pll6,
11984                               pipe_config->dpll_hw_state.pll8,
11985                               pipe_config->dpll_hw_state.pll9,
11986                               pipe_config->dpll_hw_state.pll10,
11987                               pipe_config->dpll_hw_state.pcsdw12);
11988         } else if (IS_SKYLAKE(dev)) {
11989                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11990                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11991                               pipe_config->ddi_pll_sel,
11992                               pipe_config->dpll_hw_state.ctrl1,
11993                               pipe_config->dpll_hw_state.cfgcr1,
11994                               pipe_config->dpll_hw_state.cfgcr2);
11995         } else if (HAS_DDI(dev)) {
11996                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11997                               pipe_config->ddi_pll_sel,
11998                               pipe_config->dpll_hw_state.wrpll);
11999         } else {
12000                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12001                               "fp0: 0x%x, fp1: 0x%x\n",
12002                               pipe_config->dpll_hw_state.dpll,
12003                               pipe_config->dpll_hw_state.dpll_md,
12004                               pipe_config->dpll_hw_state.fp0,
12005                               pipe_config->dpll_hw_state.fp1);
12006         }
12007
12008         DRM_DEBUG_KMS("planes on this crtc\n");
12009         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12010                 intel_plane = to_intel_plane(plane);
12011                 if (intel_plane->pipe != crtc->pipe)
12012                         continue;
12013
12014                 state = to_intel_plane_state(plane->state);
12015                 fb = state->base.fb;
12016                 if (!fb) {
12017                         DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12018                                 "disabled, scaler_id = %d\n",
12019                                 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12020                                 plane->base.id, intel_plane->pipe,
12021                                 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12022                                 drm_plane_index(plane), state->scaler_id);
12023                         continue;
12024                 }
12025
12026                 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12027                         plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12028                         plane->base.id, intel_plane->pipe,
12029                         crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12030                         drm_plane_index(plane));
12031                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12032                         fb->base.id, fb->width, fb->height, fb->pixel_format);
12033                 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12034                         state->scaler_id,
12035                         state->src.x1 >> 16, state->src.y1 >> 16,
12036                         drm_rect_width(&state->src) >> 16,
12037                         drm_rect_height(&state->src) >> 16,
12038                         state->dst.x1, state->dst.y1,
12039                         drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12040         }
12041 }
12042
12043 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12044 {
12045         struct drm_device *dev = state->dev;
12046         struct intel_encoder *encoder;
12047         struct drm_connector *connector;
12048         struct drm_connector_state *connector_state;
12049         unsigned int used_ports = 0;
12050         int i;
12051
12052         /*
12053          * Walk the connector list instead of the encoder
12054          * list to detect the problem on ddi platforms
12055          * where there's just one encoder per digital port.
12056          */
12057         for_each_connector_in_state(state, connector, connector_state, i) {
12058                 if (!connector_state->best_encoder)
12059                         continue;
12060
12061                 encoder = to_intel_encoder(connector_state->best_encoder);
12062
12063                 WARN_ON(!connector_state->crtc);
12064
12065                 switch (encoder->type) {
12066                         unsigned int port_mask;
12067                 case INTEL_OUTPUT_UNKNOWN:
12068                         if (WARN_ON(!HAS_DDI(dev)))
12069                                 break;
12070                 case INTEL_OUTPUT_DISPLAYPORT:
12071                 case INTEL_OUTPUT_HDMI:
12072                 case INTEL_OUTPUT_EDP:
12073                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12074
12075                         /* the same port mustn't appear more than once */
12076                         if (used_ports & port_mask)
12077                                 return false;
12078
12079                         used_ports |= port_mask;
12080                 default:
12081                         break;
12082                 }
12083         }
12084
12085         return true;
12086 }
12087
12088 static void
12089 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12090 {
12091         struct drm_crtc_state tmp_state;
12092         struct intel_crtc_scaler_state scaler_state;
12093         struct intel_dpll_hw_state dpll_hw_state;
12094         enum intel_dpll_id shared_dpll;
12095         uint32_t ddi_pll_sel;
12096         bool force_thru;
12097
12098         /* FIXME: before the switch to atomic started, a new pipe_config was
12099          * kzalloc'd. Code that depends on any field being zero should be
12100          * fixed, so that the crtc_state can be safely duplicated. For now,
12101          * only fields that are know to not cause problems are preserved. */
12102
12103         tmp_state = crtc_state->base;
12104         scaler_state = crtc_state->scaler_state;
12105         shared_dpll = crtc_state->shared_dpll;
12106         dpll_hw_state = crtc_state->dpll_hw_state;
12107         ddi_pll_sel = crtc_state->ddi_pll_sel;
12108         force_thru = crtc_state->pch_pfit.force_thru;
12109
12110         memset(crtc_state, 0, sizeof *crtc_state);
12111
12112         crtc_state->base = tmp_state;
12113         crtc_state->scaler_state = scaler_state;
12114         crtc_state->shared_dpll = shared_dpll;
12115         crtc_state->dpll_hw_state = dpll_hw_state;
12116         crtc_state->ddi_pll_sel = ddi_pll_sel;
12117         crtc_state->pch_pfit.force_thru = force_thru;
12118 }
12119
12120 static int
12121 intel_modeset_pipe_config(struct drm_crtc *crtc,
12122                           struct intel_crtc_state *pipe_config)
12123 {
12124         struct drm_atomic_state *state = pipe_config->base.state;
12125         struct intel_encoder *encoder;
12126         struct drm_connector *connector;
12127         struct drm_connector_state *connector_state;
12128         int base_bpp, ret = -EINVAL;
12129         int i;
12130         bool retry = true;
12131
12132         clear_intel_crtc_state(pipe_config);
12133
12134         pipe_config->cpu_transcoder =
12135                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12136
12137         /*
12138          * Sanitize sync polarity flags based on requested ones. If neither
12139          * positive or negative polarity is requested, treat this as meaning
12140          * negative polarity.
12141          */
12142         if (!(pipe_config->base.adjusted_mode.flags &
12143               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12144                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12145
12146         if (!(pipe_config->base.adjusted_mode.flags &
12147               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12148                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12149
12150         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12151                                              pipe_config);
12152         if (base_bpp < 0)
12153                 goto fail;
12154
12155         /*
12156          * Determine the real pipe dimensions. Note that stereo modes can
12157          * increase the actual pipe size due to the frame doubling and
12158          * insertion of additional space for blanks between the frame. This
12159          * is stored in the crtc timings. We use the requested mode to do this
12160          * computation to clearly distinguish it from the adjusted mode, which
12161          * can be changed by the connectors in the below retry loop.
12162          */
12163         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12164                                &pipe_config->pipe_src_w,
12165                                &pipe_config->pipe_src_h);
12166
12167 encoder_retry:
12168         /* Ensure the port clock defaults are reset when retrying. */
12169         pipe_config->port_clock = 0;
12170         pipe_config->pixel_multiplier = 1;
12171
12172         /* Fill in default crtc timings, allow encoders to overwrite them. */
12173         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12174                               CRTC_STEREO_DOUBLE);
12175
12176         /* Pass our mode to the connectors and the CRTC to give them a chance to
12177          * adjust it according to limitations or connector properties, and also
12178          * a chance to reject the mode entirely.
12179          */
12180         for_each_connector_in_state(state, connector, connector_state, i) {
12181                 if (connector_state->crtc != crtc)
12182                         continue;
12183
12184                 encoder = to_intel_encoder(connector_state->best_encoder);
12185
12186                 if (!(encoder->compute_config(encoder, pipe_config))) {
12187                         DRM_DEBUG_KMS("Encoder config failure\n");
12188                         goto fail;
12189                 }
12190         }
12191
12192         /* Set default port clock if not overwritten by the encoder. Needs to be
12193          * done afterwards in case the encoder adjusts the mode. */
12194         if (!pipe_config->port_clock)
12195                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12196                         * pipe_config->pixel_multiplier;
12197
12198         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12199         if (ret < 0) {
12200                 DRM_DEBUG_KMS("CRTC fixup failed\n");
12201                 goto fail;
12202         }
12203
12204         if (ret == RETRY) {
12205                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12206                         ret = -EINVAL;
12207                         goto fail;
12208                 }
12209
12210                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12211                 retry = false;
12212                 goto encoder_retry;
12213         }
12214
12215         /* Dithering seems to not pass-through bits correctly when it should, so
12216          * only enable it on 6bpc panels. */
12217         pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12218         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12219                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12220
12221 fail:
12222         return ret;
12223 }
12224
12225 static void
12226 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12227 {
12228         struct drm_crtc *crtc;
12229         struct drm_crtc_state *crtc_state;
12230         int i;
12231
12232         /* Double check state. */
12233         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12234                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12235
12236                 /* Update hwmode for vblank functions */
12237                 if (crtc->state->active)
12238                         crtc->hwmode = crtc->state->adjusted_mode;
12239                 else
12240                         crtc->hwmode.crtc_clock = 0;
12241         }
12242 }
12243
12244 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12245 {
12246         int diff;
12247
12248         if (clock1 == clock2)
12249                 return true;
12250
12251         if (!clock1 || !clock2)
12252                 return false;
12253
12254         diff = abs(clock1 - clock2);
12255
12256         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12257                 return true;
12258
12259         return false;
12260 }
12261
12262 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12263         list_for_each_entry((intel_crtc), \
12264                             &(dev)->mode_config.crtc_list, \
12265                             base.head) \
12266                 if (mask & (1 <<(intel_crtc)->pipe))
12267
12268 static bool
12269 intel_compare_m_n(unsigned int m, unsigned int n,
12270                   unsigned int m2, unsigned int n2,
12271                   bool exact)
12272 {
12273         if (m == m2 && n == n2)
12274                 return true;
12275
12276         if (exact || !m || !n || !m2 || !n2)
12277                 return false;
12278
12279         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12280
12281         if (m > m2) {
12282                 while (m > m2) {
12283                         m2 <<= 1;
12284                         n2 <<= 1;
12285                 }
12286         } else if (m < m2) {
12287                 while (m < m2) {
12288                         m <<= 1;
12289                         n <<= 1;
12290                 }
12291         }
12292
12293         return m == m2 && n == n2;
12294 }
12295
12296 static bool
12297 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12298                        struct intel_link_m_n *m2_n2,
12299                        bool adjust)
12300 {
12301         if (m_n->tu == m2_n2->tu &&
12302             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12303                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12304             intel_compare_m_n(m_n->link_m, m_n->link_n,
12305                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
12306                 if (adjust)
12307                         *m2_n2 = *m_n;
12308
12309                 return true;
12310         }
12311
12312         return false;
12313 }
12314
12315 static bool
12316 intel_pipe_config_compare(struct drm_device *dev,
12317                           struct intel_crtc_state *current_config,
12318                           struct intel_crtc_state *pipe_config,
12319                           bool adjust)
12320 {
12321         bool ret = true;
12322
12323 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12324         do { \
12325                 if (!adjust) \
12326                         DRM_ERROR(fmt, ##__VA_ARGS__); \
12327                 else \
12328                         DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12329         } while (0)
12330
12331 #define PIPE_CONF_CHECK_X(name) \
12332         if (current_config->name != pipe_config->name) { \
12333                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12334                           "(expected 0x%08x, found 0x%08x)\n", \
12335                           current_config->name, \
12336                           pipe_config->name); \
12337                 ret = false; \
12338         }
12339
12340 #define PIPE_CONF_CHECK_I(name) \
12341         if (current_config->name != pipe_config->name) { \
12342                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12343                           "(expected %i, found %i)\n", \
12344                           current_config->name, \
12345                           pipe_config->name); \
12346                 ret = false; \
12347         }
12348
12349 #define PIPE_CONF_CHECK_M_N(name) \
12350         if (!intel_compare_link_m_n(&current_config->name, \
12351                                     &pipe_config->name,\
12352                                     adjust)) { \
12353                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12354                           "(expected tu %i gmch %i/%i link %i/%i, " \
12355                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12356                           current_config->name.tu, \
12357                           current_config->name.gmch_m, \
12358                           current_config->name.gmch_n, \
12359                           current_config->name.link_m, \
12360                           current_config->name.link_n, \
12361                           pipe_config->name.tu, \
12362                           pipe_config->name.gmch_m, \
12363                           pipe_config->name.gmch_n, \
12364                           pipe_config->name.link_m, \
12365                           pipe_config->name.link_n); \
12366                 ret = false; \
12367         }
12368
12369 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12370         if (!intel_compare_link_m_n(&current_config->name, \
12371                                     &pipe_config->name, adjust) && \
12372             !intel_compare_link_m_n(&current_config->alt_name, \
12373                                     &pipe_config->name, adjust)) { \
12374                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12375                           "(expected tu %i gmch %i/%i link %i/%i, " \
12376                           "or tu %i gmch %i/%i link %i/%i, " \
12377                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12378                           current_config->name.tu, \
12379                           current_config->name.gmch_m, \
12380                           current_config->name.gmch_n, \
12381                           current_config->name.link_m, \
12382                           current_config->name.link_n, \
12383                           current_config->alt_name.tu, \
12384                           current_config->alt_name.gmch_m, \
12385                           current_config->alt_name.gmch_n, \
12386                           current_config->alt_name.link_m, \
12387                           current_config->alt_name.link_n, \
12388                           pipe_config->name.tu, \
12389                           pipe_config->name.gmch_m, \
12390                           pipe_config->name.gmch_n, \
12391                           pipe_config->name.link_m, \
12392                           pipe_config->name.link_n); \
12393                 ret = false; \
12394         }
12395
12396 /* This is required for BDW+ where there is only one set of registers for
12397  * switching between high and low RR.
12398  * This macro can be used whenever a comparison has to be made between one
12399  * hw state and multiple sw state variables.
12400  */
12401 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12402         if ((current_config->name != pipe_config->name) && \
12403                 (current_config->alt_name != pipe_config->name)) { \
12404                         INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12405                                   "(expected %i or %i, found %i)\n", \
12406                                   current_config->name, \
12407                                   current_config->alt_name, \
12408                                   pipe_config->name); \
12409                         ret = false; \
12410         }
12411
12412 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
12413         if ((current_config->name ^ pipe_config->name) & (mask)) { \
12414                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12415                           "(expected %i, found %i)\n", \
12416                           current_config->name & (mask), \
12417                           pipe_config->name & (mask)); \
12418                 ret = false; \
12419         }
12420
12421 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12422         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12423                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12424                           "(expected %i, found %i)\n", \
12425                           current_config->name, \
12426                           pipe_config->name); \
12427                 ret = false; \
12428         }
12429
12430 #define PIPE_CONF_QUIRK(quirk)  \
12431         ((current_config->quirks | pipe_config->quirks) & (quirk))
12432
12433         PIPE_CONF_CHECK_I(cpu_transcoder);
12434
12435         PIPE_CONF_CHECK_I(has_pch_encoder);
12436         PIPE_CONF_CHECK_I(fdi_lanes);
12437         PIPE_CONF_CHECK_M_N(fdi_m_n);
12438
12439         PIPE_CONF_CHECK_I(has_dp_encoder);
12440         PIPE_CONF_CHECK_I(lane_count);
12441
12442         if (INTEL_INFO(dev)->gen < 8) {
12443                 PIPE_CONF_CHECK_M_N(dp_m_n);
12444
12445                 PIPE_CONF_CHECK_I(has_drrs);
12446                 if (current_config->has_drrs)
12447                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
12448         } else
12449                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12450
12451         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12452         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12453         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12454         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12455         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12456         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12457
12458         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12459         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12460         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12461         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12462         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12463         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12464
12465         PIPE_CONF_CHECK_I(pixel_multiplier);
12466         PIPE_CONF_CHECK_I(has_hdmi_sink);
12467         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12468             IS_VALLEYVIEW(dev))
12469                 PIPE_CONF_CHECK_I(limited_color_range);
12470         PIPE_CONF_CHECK_I(has_infoframe);
12471
12472         PIPE_CONF_CHECK_I(has_audio);
12473
12474         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12475                               DRM_MODE_FLAG_INTERLACE);
12476
12477         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12478                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12479                                       DRM_MODE_FLAG_PHSYNC);
12480                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12481                                       DRM_MODE_FLAG_NHSYNC);
12482                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12483                                       DRM_MODE_FLAG_PVSYNC);
12484                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12485                                       DRM_MODE_FLAG_NVSYNC);
12486         }
12487
12488         PIPE_CONF_CHECK_X(gmch_pfit.control);
12489         /* pfit ratios are autocomputed by the hw on gen4+ */
12490         if (INTEL_INFO(dev)->gen < 4)
12491                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12492         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12493
12494         if (!adjust) {
12495                 PIPE_CONF_CHECK_I(pipe_src_w);
12496                 PIPE_CONF_CHECK_I(pipe_src_h);
12497
12498                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12499                 if (current_config->pch_pfit.enabled) {
12500                         PIPE_CONF_CHECK_X(pch_pfit.pos);
12501                         PIPE_CONF_CHECK_X(pch_pfit.size);
12502                 }
12503
12504                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12505         }
12506
12507         /* BDW+ don't expose a synchronous way to read the state */
12508         if (IS_HASWELL(dev))
12509                 PIPE_CONF_CHECK_I(ips_enabled);
12510
12511         PIPE_CONF_CHECK_I(double_wide);
12512
12513         PIPE_CONF_CHECK_X(ddi_pll_sel);
12514
12515         PIPE_CONF_CHECK_I(shared_dpll);
12516         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12517         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12518         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12519         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12520         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12521         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12522         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12523         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12524
12525         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12526                 PIPE_CONF_CHECK_I(pipe_bpp);
12527
12528         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12529         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12530
12531 #undef PIPE_CONF_CHECK_X
12532 #undef PIPE_CONF_CHECK_I
12533 #undef PIPE_CONF_CHECK_I_ALT
12534 #undef PIPE_CONF_CHECK_FLAGS
12535 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12536 #undef PIPE_CONF_QUIRK
12537 #undef INTEL_ERR_OR_DBG_KMS
12538
12539         return ret;
12540 }
12541
12542 static void check_wm_state(struct drm_device *dev)
12543 {
12544         struct drm_i915_private *dev_priv = dev->dev_private;
12545         struct skl_ddb_allocation hw_ddb, *sw_ddb;
12546         struct intel_crtc *intel_crtc;
12547         int plane;
12548
12549         if (INTEL_INFO(dev)->gen < 9)
12550                 return;
12551
12552         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12553         sw_ddb = &dev_priv->wm.skl_hw.ddb;
12554
12555         for_each_intel_crtc(dev, intel_crtc) {
12556                 struct skl_ddb_entry *hw_entry, *sw_entry;
12557                 const enum pipe pipe = intel_crtc->pipe;
12558
12559                 if (!intel_crtc->active)
12560                         continue;
12561
12562                 /* planes */
12563                 for_each_plane(dev_priv, pipe, plane) {
12564                         hw_entry = &hw_ddb.plane[pipe][plane];
12565                         sw_entry = &sw_ddb->plane[pipe][plane];
12566
12567                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
12568                                 continue;
12569
12570                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12571                                   "(expected (%u,%u), found (%u,%u))\n",
12572                                   pipe_name(pipe), plane + 1,
12573                                   sw_entry->start, sw_entry->end,
12574                                   hw_entry->start, hw_entry->end);
12575                 }
12576
12577                 /* cursor */
12578                 hw_entry = &hw_ddb.cursor[pipe];
12579                 sw_entry = &sw_ddb->cursor[pipe];
12580
12581                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12582                         continue;
12583
12584                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12585                           "(expected (%u,%u), found (%u,%u))\n",
12586                           pipe_name(pipe),
12587                           sw_entry->start, sw_entry->end,
12588                           hw_entry->start, hw_entry->end);
12589         }
12590 }
12591
12592 static void
12593 check_connector_state(struct drm_device *dev,
12594                       struct drm_atomic_state *old_state)
12595 {
12596         struct drm_connector_state *old_conn_state;
12597         struct drm_connector *connector;
12598         int i;
12599
12600         for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12601                 struct drm_encoder *encoder = connector->encoder;
12602                 struct drm_connector_state *state = connector->state;
12603
12604                 /* This also checks the encoder/connector hw state with the
12605                  * ->get_hw_state callbacks. */
12606                 intel_connector_check_state(to_intel_connector(connector));
12607
12608                 I915_STATE_WARN(state->best_encoder != encoder,
12609                      "connector's atomic encoder doesn't match legacy encoder\n");
12610         }
12611 }
12612
12613 static void
12614 check_encoder_state(struct drm_device *dev)
12615 {
12616         struct intel_encoder *encoder;
12617         struct intel_connector *connector;
12618
12619         for_each_intel_encoder(dev, encoder) {
12620                 bool enabled = false;
12621                 enum pipe pipe;
12622
12623                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12624                               encoder->base.base.id,
12625                               encoder->base.name);
12626
12627                 for_each_intel_connector(dev, connector) {
12628                         if (connector->base.state->best_encoder != &encoder->base)
12629                                 continue;
12630                         enabled = true;
12631
12632                         I915_STATE_WARN(connector->base.state->crtc !=
12633                                         encoder->base.crtc,
12634                              "connector's crtc doesn't match encoder crtc\n");
12635                 }
12636
12637                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12638                      "encoder's enabled state mismatch "
12639                      "(expected %i, found %i)\n",
12640                      !!encoder->base.crtc, enabled);
12641
12642                 if (!encoder->base.crtc) {
12643                         bool active;
12644
12645                         active = encoder->get_hw_state(encoder, &pipe);
12646                         I915_STATE_WARN(active,
12647                              "encoder detached but still enabled on pipe %c.\n",
12648                              pipe_name(pipe));
12649                 }
12650         }
12651 }
12652
12653 static void
12654 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12655 {
12656         struct drm_i915_private *dev_priv = dev->dev_private;
12657         struct intel_encoder *encoder;
12658         struct drm_crtc_state *old_crtc_state;
12659         struct drm_crtc *crtc;
12660         int i;
12661
12662         for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12663                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12664                 struct intel_crtc_state *pipe_config, *sw_config;
12665                 bool active;
12666
12667                 if (!needs_modeset(crtc->state) &&
12668                     !to_intel_crtc_state(crtc->state)->update_pipe)
12669                         continue;
12670
12671                 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12672                 pipe_config = to_intel_crtc_state(old_crtc_state);
12673                 memset(pipe_config, 0, sizeof(*pipe_config));
12674                 pipe_config->base.crtc = crtc;
12675                 pipe_config->base.state = old_state;
12676
12677                 DRM_DEBUG_KMS("[CRTC:%d]\n",
12678                               crtc->base.id);
12679
12680                 active = dev_priv->display.get_pipe_config(intel_crtc,
12681                                                            pipe_config);
12682
12683                 /* hw state is inconsistent with the pipe quirk */
12684                 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12685                     (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12686                         active = crtc->state->active;
12687
12688                 I915_STATE_WARN(crtc->state->active != active,
12689                      "crtc active state doesn't match with hw state "
12690                      "(expected %i, found %i)\n", crtc->state->active, active);
12691
12692                 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
12693                      "transitional active state does not match atomic hw state "
12694                      "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12695
12696                 for_each_encoder_on_crtc(dev, crtc, encoder) {
12697                         enum pipe pipe;
12698
12699                         active = encoder->get_hw_state(encoder, &pipe);
12700                         I915_STATE_WARN(active != crtc->state->active,
12701                                 "[ENCODER:%i] active %i with crtc active %i\n",
12702                                 encoder->base.base.id, active, crtc->state->active);
12703
12704                         I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12705                                         "Encoder connected to wrong pipe %c\n",
12706                                         pipe_name(pipe));
12707
12708                         if (active)
12709                                 encoder->get_config(encoder, pipe_config);
12710                 }
12711
12712                 if (!crtc->state->active)
12713                         continue;
12714
12715                 sw_config = to_intel_crtc_state(crtc->state);
12716                 if (!intel_pipe_config_compare(dev, sw_config,
12717                                                pipe_config, false)) {
12718                         I915_STATE_WARN(1, "pipe state doesn't match!\n");
12719                         intel_dump_pipe_config(intel_crtc, pipe_config,
12720                                                "[hw state]");
12721                         intel_dump_pipe_config(intel_crtc, sw_config,
12722                                                "[sw state]");
12723                 }
12724         }
12725 }
12726
12727 static void
12728 check_shared_dpll_state(struct drm_device *dev)
12729 {
12730         struct drm_i915_private *dev_priv = dev->dev_private;
12731         struct intel_crtc *crtc;
12732         struct intel_dpll_hw_state dpll_hw_state;
12733         int i;
12734
12735         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12736                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12737                 int enabled_crtcs = 0, active_crtcs = 0;
12738                 bool active;
12739
12740                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12741
12742                 DRM_DEBUG_KMS("%s\n", pll->name);
12743
12744                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12745
12746                 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12747                      "more active pll users than references: %i vs %i\n",
12748                      pll->active, hweight32(pll->config.crtc_mask));
12749                 I915_STATE_WARN(pll->active && !pll->on,
12750                      "pll in active use but not on in sw tracking\n");
12751                 I915_STATE_WARN(pll->on && !pll->active,
12752                      "pll in on but not on in use in sw tracking\n");
12753                 I915_STATE_WARN(pll->on != active,
12754                      "pll on state mismatch (expected %i, found %i)\n",
12755                      pll->on, active);
12756
12757                 for_each_intel_crtc(dev, crtc) {
12758                         if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12759                                 enabled_crtcs++;
12760                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12761                                 active_crtcs++;
12762                 }
12763                 I915_STATE_WARN(pll->active != active_crtcs,
12764                      "pll active crtcs mismatch (expected %i, found %i)\n",
12765                      pll->active, active_crtcs);
12766                 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12767                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
12768                      hweight32(pll->config.crtc_mask), enabled_crtcs);
12769
12770                 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12771                                        sizeof(dpll_hw_state)),
12772                      "pll hw state mismatch\n");
12773         }
12774 }
12775
12776 static void
12777 intel_modeset_check_state(struct drm_device *dev,
12778                           struct drm_atomic_state *old_state)
12779 {
12780         check_wm_state(dev);
12781         check_connector_state(dev, old_state);
12782         check_encoder_state(dev);
12783         check_crtc_state(dev, old_state);
12784         check_shared_dpll_state(dev);
12785 }
12786
12787 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12788                                      int dotclock)
12789 {
12790         /*
12791          * FDI already provided one idea for the dotclock.
12792          * Yell if the encoder disagrees.
12793          */
12794         WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12795              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12796              pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12797 }
12798
12799 static void update_scanline_offset(struct intel_crtc *crtc)
12800 {
12801         struct drm_device *dev = crtc->base.dev;
12802
12803         /*
12804          * The scanline counter increments at the leading edge of hsync.
12805          *
12806          * On most platforms it starts counting from vtotal-1 on the
12807          * first active line. That means the scanline counter value is
12808          * always one less than what we would expect. Ie. just after
12809          * start of vblank, which also occurs at start of hsync (on the
12810          * last active line), the scanline counter will read vblank_start-1.
12811          *
12812          * On gen2 the scanline counter starts counting from 1 instead
12813          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12814          * to keep the value positive), instead of adding one.
12815          *
12816          * On HSW+ the behaviour of the scanline counter depends on the output
12817          * type. For DP ports it behaves like most other platforms, but on HDMI
12818          * there's an extra 1 line difference. So we need to add two instead of
12819          * one to the value.
12820          */
12821         if (IS_GEN2(dev)) {
12822                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
12823                 int vtotal;
12824
12825                 vtotal = adjusted_mode->crtc_vtotal;
12826                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12827                         vtotal /= 2;
12828
12829                 crtc->scanline_offset = vtotal - 1;
12830         } else if (HAS_DDI(dev) &&
12831                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12832                 crtc->scanline_offset = 2;
12833         } else
12834                 crtc->scanline_offset = 1;
12835 }
12836
12837 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12838 {
12839         struct drm_device *dev = state->dev;
12840         struct drm_i915_private *dev_priv = to_i915(dev);
12841         struct intel_shared_dpll_config *shared_dpll = NULL;
12842         struct intel_crtc *intel_crtc;
12843         struct intel_crtc_state *intel_crtc_state;
12844         struct drm_crtc *crtc;
12845         struct drm_crtc_state *crtc_state;
12846         int i;
12847
12848         if (!dev_priv->display.crtc_compute_clock)
12849                 return;
12850
12851         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12852                 int dpll;
12853
12854                 intel_crtc = to_intel_crtc(crtc);
12855                 intel_crtc_state = to_intel_crtc_state(crtc_state);
12856                 dpll = intel_crtc_state->shared_dpll;
12857
12858                 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
12859                         continue;
12860
12861                 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12862
12863                 if (!shared_dpll)
12864                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
12865
12866                 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12867         }
12868 }
12869
12870 /*
12871  * This implements the workaround described in the "notes" section of the mode
12872  * set sequence documentation. When going from no pipes or single pipe to
12873  * multiple pipes, and planes are enabled after the pipe, we need to wait at
12874  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12875  */
12876 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12877 {
12878         struct drm_crtc_state *crtc_state;
12879         struct intel_crtc *intel_crtc;
12880         struct drm_crtc *crtc;
12881         struct intel_crtc_state *first_crtc_state = NULL;
12882         struct intel_crtc_state *other_crtc_state = NULL;
12883         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12884         int i;
12885
12886         /* look at all crtc's that are going to be enabled in during modeset */
12887         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12888                 intel_crtc = to_intel_crtc(crtc);
12889
12890                 if (!crtc_state->active || !needs_modeset(crtc_state))
12891                         continue;
12892
12893                 if (first_crtc_state) {
12894                         other_crtc_state = to_intel_crtc_state(crtc_state);
12895                         break;
12896                 } else {
12897                         first_crtc_state = to_intel_crtc_state(crtc_state);
12898                         first_pipe = intel_crtc->pipe;
12899                 }
12900         }
12901
12902         /* No workaround needed? */
12903         if (!first_crtc_state)
12904                 return 0;
12905
12906         /* w/a possibly needed, check how many crtc's are already enabled. */
12907         for_each_intel_crtc(state->dev, intel_crtc) {
12908                 struct intel_crtc_state *pipe_config;
12909
12910                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12911                 if (IS_ERR(pipe_config))
12912                         return PTR_ERR(pipe_config);
12913
12914                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12915
12916                 if (!pipe_config->base.active ||
12917                     needs_modeset(&pipe_config->base))
12918                         continue;
12919
12920                 /* 2 or more enabled crtcs means no need for w/a */
12921                 if (enabled_pipe != INVALID_PIPE)
12922                         return 0;
12923
12924                 enabled_pipe = intel_crtc->pipe;
12925         }
12926
12927         if (enabled_pipe != INVALID_PIPE)
12928                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12929         else if (other_crtc_state)
12930                 other_crtc_state->hsw_workaround_pipe = first_pipe;
12931
12932         return 0;
12933 }
12934
12935 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12936 {
12937         struct drm_crtc *crtc;
12938         struct drm_crtc_state *crtc_state;
12939         int ret = 0;
12940
12941         /* add all active pipes to the state */
12942         for_each_crtc(state->dev, crtc) {
12943                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12944                 if (IS_ERR(crtc_state))
12945                         return PTR_ERR(crtc_state);
12946
12947                 if (!crtc_state->active || needs_modeset(crtc_state))
12948                         continue;
12949
12950                 crtc_state->mode_changed = true;
12951
12952                 ret = drm_atomic_add_affected_connectors(state, crtc);
12953                 if (ret)
12954                         break;
12955
12956                 ret = drm_atomic_add_affected_planes(state, crtc);
12957                 if (ret)
12958                         break;
12959         }
12960
12961         return ret;
12962 }
12963
12964 static int intel_modeset_checks(struct drm_atomic_state *state)
12965 {
12966         struct drm_device *dev = state->dev;
12967         struct drm_i915_private *dev_priv = dev->dev_private;
12968         int ret;
12969
12970         if (!check_digital_port_conflicts(state)) {
12971                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12972                 return -EINVAL;
12973         }
12974
12975         /*
12976          * See if the config requires any additional preparation, e.g.
12977          * to adjust global state with pipes off.  We need to do this
12978          * here so we can get the modeset_pipe updated config for the new
12979          * mode set on this crtc.  For other crtcs we need to use the
12980          * adjusted_mode bits in the crtc directly.
12981          */
12982         if (dev_priv->display.modeset_calc_cdclk) {
12983                 unsigned int cdclk;
12984
12985                 ret = dev_priv->display.modeset_calc_cdclk(state);
12986
12987                 cdclk = to_intel_atomic_state(state)->cdclk;
12988                 if (!ret && cdclk != dev_priv->cdclk_freq)
12989                         ret = intel_modeset_all_pipes(state);
12990
12991                 if (ret < 0)
12992                         return ret;
12993         } else
12994                 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
12995
12996         intel_modeset_clear_plls(state);
12997
12998         if (IS_HASWELL(dev))
12999                 return haswell_mode_set_planes_workaround(state);
13000
13001         return 0;
13002 }
13003
13004 /**
13005  * intel_atomic_check - validate state object
13006  * @dev: drm device
13007  * @state: state to validate
13008  */
13009 static int intel_atomic_check(struct drm_device *dev,
13010                               struct drm_atomic_state *state)
13011 {
13012         struct drm_crtc *crtc;
13013         struct drm_crtc_state *crtc_state;
13014         int ret, i;
13015         bool any_ms = false;
13016
13017         ret = drm_atomic_helper_check_modeset(dev, state);
13018         if (ret)
13019                 return ret;
13020
13021         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13022                 struct intel_crtc_state *pipe_config =
13023                         to_intel_crtc_state(crtc_state);
13024
13025                 /* Catch I915_MODE_FLAG_INHERITED */
13026                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13027                         crtc_state->mode_changed = true;
13028
13029                 if (!crtc_state->enable) {
13030                         if (needs_modeset(crtc_state))
13031                                 any_ms = true;
13032                         continue;
13033                 }
13034
13035                 if (!needs_modeset(crtc_state))
13036                         continue;
13037
13038                 /* FIXME: For only active_changed we shouldn't need to do any
13039                  * state recomputation at all. */
13040
13041                 ret = drm_atomic_add_affected_connectors(state, crtc);
13042                 if (ret)
13043                         return ret;
13044
13045                 ret = intel_modeset_pipe_config(crtc, pipe_config);
13046                 if (ret)
13047                         return ret;
13048
13049                 if (intel_pipe_config_compare(state->dev,
13050                                         to_intel_crtc_state(crtc->state),
13051                                         pipe_config, true)) {
13052                         crtc_state->mode_changed = false;
13053                         to_intel_crtc_state(crtc_state)->update_pipe = true;
13054                 }
13055
13056                 if (needs_modeset(crtc_state)) {
13057                         any_ms = true;
13058
13059                         ret = drm_atomic_add_affected_planes(state, crtc);
13060                         if (ret)
13061                                 return ret;
13062                 }
13063
13064                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13065                                        needs_modeset(crtc_state) ?
13066                                        "[modeset]" : "[fastset]");
13067         }
13068
13069         if (any_ms) {
13070                 ret = intel_modeset_checks(state);
13071
13072                 if (ret)
13073                         return ret;
13074         } else
13075                 to_intel_atomic_state(state)->cdclk =
13076                         to_i915(state->dev)->cdclk_freq;
13077
13078         return drm_atomic_helper_check_planes(state->dev, state);
13079 }
13080
13081 /**
13082  * intel_atomic_commit - commit validated state object
13083  * @dev: DRM device
13084  * @state: the top-level driver state object
13085  * @async: asynchronous commit
13086  *
13087  * This function commits a top-level state object that has been validated
13088  * with drm_atomic_helper_check().
13089  *
13090  * FIXME:  Atomic modeset support for i915 is not yet complete.  At the moment
13091  * we can only handle plane-related operations and do not yet support
13092  * asynchronous commit.
13093  *
13094  * RETURNS
13095  * Zero for success or -errno.
13096  */
13097 static int intel_atomic_commit(struct drm_device *dev,
13098                                struct drm_atomic_state *state,
13099                                bool async)
13100 {
13101         struct drm_i915_private *dev_priv = dev->dev_private;
13102         struct drm_crtc *crtc;
13103         struct drm_crtc_state *crtc_state;
13104         int ret = 0;
13105         int i;
13106         bool any_ms = false;
13107
13108         if (async) {
13109                 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13110                 return -EINVAL;
13111         }
13112
13113         ret = drm_atomic_helper_prepare_planes(dev, state);
13114         if (ret)
13115                 return ret;
13116
13117         drm_atomic_helper_swap_state(dev, state);
13118
13119         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13120                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13121
13122                 if (!needs_modeset(crtc->state))
13123                         continue;
13124
13125                 any_ms = true;
13126                 intel_pre_plane_update(intel_crtc);
13127
13128                 if (crtc_state->active) {
13129                         intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13130                         dev_priv->display.crtc_disable(crtc);
13131                         intel_crtc->active = false;
13132                         intel_disable_shared_dpll(intel_crtc);
13133                 }
13134         }
13135
13136         /* Only after disabling all output pipelines that will be changed can we
13137          * update the the output configuration. */
13138         intel_modeset_update_crtc_state(state);
13139
13140         if (any_ms) {
13141                 intel_shared_dpll_commit(state);
13142
13143                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13144                 modeset_update_crtc_power_domains(state);
13145         }
13146
13147         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13148         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13149                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13150                 bool modeset = needs_modeset(crtc->state);
13151                 bool update_pipe = !modeset &&
13152                         to_intel_crtc_state(crtc->state)->update_pipe;
13153                 unsigned long put_domains = 0;
13154
13155                 if (modeset && crtc->state->active) {
13156                         update_scanline_offset(to_intel_crtc(crtc));
13157                         dev_priv->display.crtc_enable(crtc);
13158                 }
13159
13160                 if (update_pipe) {
13161                         put_domains = modeset_get_crtc_power_domains(crtc);
13162
13163                         /* make sure intel_modeset_check_state runs */
13164                         any_ms = true;
13165                 }
13166
13167                 if (!modeset)
13168                         intel_pre_plane_update(intel_crtc);
13169
13170                 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13171
13172                 if (put_domains)
13173                         modeset_put_power_domains(dev_priv, put_domains);
13174
13175                 intel_post_plane_update(intel_crtc);
13176         }
13177
13178         /* FIXME: add subpixel order */
13179
13180         drm_atomic_helper_wait_for_vblanks(dev, state);
13181         drm_atomic_helper_cleanup_planes(dev, state);
13182
13183         if (any_ms)
13184                 intel_modeset_check_state(dev, state);
13185
13186         drm_atomic_state_free(state);
13187
13188         return 0;
13189 }
13190
13191 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13192 {
13193         struct drm_device *dev = crtc->dev;
13194         struct drm_atomic_state *state;
13195         struct drm_crtc_state *crtc_state;
13196         int ret;
13197
13198         state = drm_atomic_state_alloc(dev);
13199         if (!state) {
13200                 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13201                               crtc->base.id);
13202                 return;
13203         }
13204
13205         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13206
13207 retry:
13208         crtc_state = drm_atomic_get_crtc_state(state, crtc);
13209         ret = PTR_ERR_OR_ZERO(crtc_state);
13210         if (!ret) {
13211                 if (!crtc_state->active)
13212                         goto out;
13213
13214                 crtc_state->mode_changed = true;
13215                 ret = drm_atomic_commit(state);
13216         }
13217
13218         if (ret == -EDEADLK) {
13219                 drm_atomic_state_clear(state);
13220                 drm_modeset_backoff(state->acquire_ctx);
13221                 goto retry;
13222         }
13223
13224         if (ret)
13225 out:
13226                 drm_atomic_state_free(state);
13227 }
13228
13229 #undef for_each_intel_crtc_masked
13230
13231 static const struct drm_crtc_funcs intel_crtc_funcs = {
13232         .gamma_set = intel_crtc_gamma_set,
13233         .set_config = drm_atomic_helper_set_config,
13234         .destroy = intel_crtc_destroy,
13235         .page_flip = intel_crtc_page_flip,
13236         .atomic_duplicate_state = intel_crtc_duplicate_state,
13237         .atomic_destroy_state = intel_crtc_destroy_state,
13238 };
13239
13240 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13241                                       struct intel_shared_dpll *pll,
13242                                       struct intel_dpll_hw_state *hw_state)
13243 {
13244         uint32_t val;
13245
13246         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13247                 return false;
13248
13249         val = I915_READ(PCH_DPLL(pll->id));
13250         hw_state->dpll = val;
13251         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13252         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13253
13254         return val & DPLL_VCO_ENABLE;
13255 }
13256
13257 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13258                                   struct intel_shared_dpll *pll)
13259 {
13260         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13261         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13262 }
13263
13264 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13265                                 struct intel_shared_dpll *pll)
13266 {
13267         /* PCH refclock must be enabled first */
13268         ibx_assert_pch_refclk_enabled(dev_priv);
13269
13270         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13271
13272         /* Wait for the clocks to stabilize. */
13273         POSTING_READ(PCH_DPLL(pll->id));
13274         udelay(150);
13275
13276         /* The pixel multiplier can only be updated once the
13277          * DPLL is enabled and the clocks are stable.
13278          *
13279          * So write it again.
13280          */
13281         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13282         POSTING_READ(PCH_DPLL(pll->id));
13283         udelay(200);
13284 }
13285
13286 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13287                                  struct intel_shared_dpll *pll)
13288 {
13289         struct drm_device *dev = dev_priv->dev;
13290         struct intel_crtc *crtc;
13291
13292         /* Make sure no transcoder isn't still depending on us. */
13293         for_each_intel_crtc(dev, crtc) {
13294                 if (intel_crtc_to_shared_dpll(crtc) == pll)
13295                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13296         }
13297
13298         I915_WRITE(PCH_DPLL(pll->id), 0);
13299         POSTING_READ(PCH_DPLL(pll->id));
13300         udelay(200);
13301 }
13302
13303 static char *ibx_pch_dpll_names[] = {
13304         "PCH DPLL A",
13305         "PCH DPLL B",
13306 };
13307
13308 static void ibx_pch_dpll_init(struct drm_device *dev)
13309 {
13310         struct drm_i915_private *dev_priv = dev->dev_private;
13311         int i;
13312
13313         dev_priv->num_shared_dpll = 2;
13314
13315         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13316                 dev_priv->shared_dplls[i].id = i;
13317                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13318                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13319                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13320                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13321                 dev_priv->shared_dplls[i].get_hw_state =
13322                         ibx_pch_dpll_get_hw_state;
13323         }
13324 }
13325
13326 static void intel_shared_dpll_init(struct drm_device *dev)
13327 {
13328         struct drm_i915_private *dev_priv = dev->dev_private;
13329
13330         intel_update_cdclk(dev);
13331
13332         if (HAS_DDI(dev))
13333                 intel_ddi_pll_init(dev);
13334         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13335                 ibx_pch_dpll_init(dev);
13336         else
13337                 dev_priv->num_shared_dpll = 0;
13338
13339         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13340 }
13341
13342 /**
13343  * intel_prepare_plane_fb - Prepare fb for usage on plane
13344  * @plane: drm plane to prepare for
13345  * @fb: framebuffer to prepare for presentation
13346  *
13347  * Prepares a framebuffer for usage on a display plane.  Generally this
13348  * involves pinning the underlying object and updating the frontbuffer tracking
13349  * bits.  Some older platforms need special physical address handling for
13350  * cursor planes.
13351  *
13352  * Returns 0 on success, negative error code on failure.
13353  */
13354 int
13355 intel_prepare_plane_fb(struct drm_plane *plane,
13356                        const struct drm_plane_state *new_state)
13357 {
13358         struct drm_device *dev = plane->dev;
13359         struct drm_framebuffer *fb = new_state->fb;
13360         struct intel_plane *intel_plane = to_intel_plane(plane);
13361         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13362         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13363         int ret = 0;
13364
13365         if (!obj)
13366                 return 0;
13367
13368         mutex_lock(&dev->struct_mutex);
13369
13370         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13371             INTEL_INFO(dev)->cursor_needs_physical) {
13372                 int align = IS_I830(dev) ? 16 * 1024 : 256;
13373                 ret = i915_gem_object_attach_phys(obj, align);
13374                 if (ret)
13375                         DRM_DEBUG_KMS("failed to attach phys object\n");
13376         } else {
13377                 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
13378         }
13379
13380         if (ret == 0)
13381                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13382
13383         mutex_unlock(&dev->struct_mutex);
13384
13385         return ret;
13386 }
13387
13388 /**
13389  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13390  * @plane: drm plane to clean up for
13391  * @fb: old framebuffer that was on plane
13392  *
13393  * Cleans up a framebuffer that has just been removed from a plane.
13394  */
13395 void
13396 intel_cleanup_plane_fb(struct drm_plane *plane,
13397                        const struct drm_plane_state *old_state)
13398 {
13399         struct drm_device *dev = plane->dev;
13400         struct drm_i915_gem_object *obj = intel_fb_obj(old_state->fb);
13401
13402         if (!obj)
13403                 return;
13404
13405         if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13406             !INTEL_INFO(dev)->cursor_needs_physical) {
13407                 mutex_lock(&dev->struct_mutex);
13408                 intel_unpin_fb_obj(old_state->fb, old_state);
13409                 mutex_unlock(&dev->struct_mutex);
13410         }
13411 }
13412
13413 int
13414 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13415 {
13416         int max_scale;
13417         struct drm_device *dev;
13418         struct drm_i915_private *dev_priv;
13419         int crtc_clock, cdclk;
13420
13421         if (!intel_crtc || !crtc_state)
13422                 return DRM_PLANE_HELPER_NO_SCALING;
13423
13424         dev = intel_crtc->base.dev;
13425         dev_priv = dev->dev_private;
13426         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13427         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13428
13429         if (!crtc_clock || !cdclk)
13430                 return DRM_PLANE_HELPER_NO_SCALING;
13431
13432         /*
13433          * skl max scale is lower of:
13434          *    close to 3 but not 3, -1 is for that purpose
13435          *            or
13436          *    cdclk/crtc_clock
13437          */
13438         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13439
13440         return max_scale;
13441 }
13442
13443 static int
13444 intel_check_primary_plane(struct drm_plane *plane,
13445                           struct intel_crtc_state *crtc_state,
13446                           struct intel_plane_state *state)
13447 {
13448         struct drm_crtc *crtc = state->base.crtc;
13449         struct drm_framebuffer *fb = state->base.fb;
13450         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13451         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13452         bool can_position = false;
13453
13454         /* use scaler when colorkey is not required */
13455         if (INTEL_INFO(plane->dev)->gen >= 9 &&
13456             state->ckey.flags == I915_SET_COLORKEY_NONE) {
13457                 min_scale = 1;
13458                 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13459                 can_position = true;
13460         }
13461
13462         return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13463                                              &state->dst, &state->clip,
13464                                              min_scale, max_scale,
13465                                              can_position, true,
13466                                              &state->visible);
13467 }
13468
13469 static void
13470 intel_commit_primary_plane(struct drm_plane *plane,
13471                            struct intel_plane_state *state)
13472 {
13473         struct drm_crtc *crtc = state->base.crtc;
13474         struct drm_framebuffer *fb = state->base.fb;
13475         struct drm_device *dev = plane->dev;
13476         struct drm_i915_private *dev_priv = dev->dev_private;
13477         struct intel_crtc *intel_crtc;
13478         struct drm_rect *src = &state->src;
13479
13480         crtc = crtc ? crtc : plane->crtc;
13481         intel_crtc = to_intel_crtc(crtc);
13482
13483         plane->fb = fb;
13484         crtc->x = src->x1 >> 16;
13485         crtc->y = src->y1 >> 16;
13486
13487         if (!crtc->state->active)
13488                 return;
13489
13490         dev_priv->display.update_primary_plane(crtc, fb,
13491                                                state->src.x1 >> 16,
13492                                                state->src.y1 >> 16);
13493 }
13494
13495 static void
13496 intel_disable_primary_plane(struct drm_plane *plane,
13497                             struct drm_crtc *crtc)
13498 {
13499         struct drm_device *dev = plane->dev;
13500         struct drm_i915_private *dev_priv = dev->dev_private;
13501
13502         dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13503 }
13504
13505 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13506                                     struct drm_crtc_state *old_crtc_state)
13507 {
13508         struct drm_device *dev = crtc->dev;
13509         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13510         struct intel_crtc_state *old_intel_state =
13511                 to_intel_crtc_state(old_crtc_state);
13512         bool modeset = needs_modeset(crtc->state);
13513
13514         if (intel_crtc->atomic.update_wm_pre)
13515                 intel_update_watermarks(crtc);
13516
13517         /* Perform vblank evasion around commit operation */
13518         if (crtc->state->active)
13519                 intel_pipe_update_start(intel_crtc);
13520
13521         if (modeset)
13522                 return;
13523
13524         if (to_intel_crtc_state(crtc->state)->update_pipe)
13525                 intel_update_pipe_config(intel_crtc, old_intel_state);
13526         else if (INTEL_INFO(dev)->gen >= 9)
13527                 skl_detach_scalers(intel_crtc);
13528 }
13529
13530 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13531                                      struct drm_crtc_state *old_crtc_state)
13532 {
13533         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13534
13535         if (crtc->state->active)
13536                 intel_pipe_update_end(intel_crtc);
13537 }
13538
13539 /**
13540  * intel_plane_destroy - destroy a plane
13541  * @plane: plane to destroy
13542  *
13543  * Common destruction function for all types of planes (primary, cursor,
13544  * sprite).
13545  */
13546 void intel_plane_destroy(struct drm_plane *plane)
13547 {
13548         struct intel_plane *intel_plane = to_intel_plane(plane);
13549         drm_plane_cleanup(plane);
13550         kfree(intel_plane);
13551 }
13552
13553 const struct drm_plane_funcs intel_plane_funcs = {
13554         .update_plane = drm_atomic_helper_update_plane,
13555         .disable_plane = drm_atomic_helper_disable_plane,
13556         .destroy = intel_plane_destroy,
13557         .set_property = drm_atomic_helper_plane_set_property,
13558         .atomic_get_property = intel_plane_atomic_get_property,
13559         .atomic_set_property = intel_plane_atomic_set_property,
13560         .atomic_duplicate_state = intel_plane_duplicate_state,
13561         .atomic_destroy_state = intel_plane_destroy_state,
13562
13563 };
13564
13565 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13566                                                     int pipe)
13567 {
13568         struct intel_plane *primary;
13569         struct intel_plane_state *state;
13570         const uint32_t *intel_primary_formats;
13571         unsigned int num_formats;
13572
13573         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13574         if (primary == NULL)
13575                 return NULL;
13576
13577         state = intel_create_plane_state(&primary->base);
13578         if (!state) {
13579                 kfree(primary);
13580                 return NULL;
13581         }
13582         primary->base.state = &state->base;
13583
13584         primary->can_scale = false;
13585         primary->max_downscale = 1;
13586         if (INTEL_INFO(dev)->gen >= 9) {
13587                 primary->can_scale = true;
13588                 state->scaler_id = -1;
13589         }
13590         primary->pipe = pipe;
13591         primary->plane = pipe;
13592         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13593         primary->check_plane = intel_check_primary_plane;
13594         primary->commit_plane = intel_commit_primary_plane;
13595         primary->disable_plane = intel_disable_primary_plane;
13596         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13597                 primary->plane = !pipe;
13598
13599         if (INTEL_INFO(dev)->gen >= 9) {
13600                 intel_primary_formats = skl_primary_formats;
13601                 num_formats = ARRAY_SIZE(skl_primary_formats);
13602         } else if (INTEL_INFO(dev)->gen >= 4) {
13603                 intel_primary_formats = i965_primary_formats;
13604                 num_formats = ARRAY_SIZE(i965_primary_formats);
13605         } else {
13606                 intel_primary_formats = i8xx_primary_formats;
13607                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13608         }
13609
13610         drm_universal_plane_init(dev, &primary->base, 0,
13611                                  &intel_plane_funcs,
13612                                  intel_primary_formats, num_formats,
13613                                  DRM_PLANE_TYPE_PRIMARY);
13614
13615         if (INTEL_INFO(dev)->gen >= 4)
13616                 intel_create_rotation_property(dev, primary);
13617
13618         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13619
13620         return &primary->base;
13621 }
13622
13623 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13624 {
13625         if (!dev->mode_config.rotation_property) {
13626                 unsigned long flags = BIT(DRM_ROTATE_0) |
13627                         BIT(DRM_ROTATE_180);
13628
13629                 if (INTEL_INFO(dev)->gen >= 9)
13630                         flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13631
13632                 dev->mode_config.rotation_property =
13633                         drm_mode_create_rotation_property(dev, flags);
13634         }
13635         if (dev->mode_config.rotation_property)
13636                 drm_object_attach_property(&plane->base.base,
13637                                 dev->mode_config.rotation_property,
13638                                 plane->base.state->rotation);
13639 }
13640
13641 static int
13642 intel_check_cursor_plane(struct drm_plane *plane,
13643                          struct intel_crtc_state *crtc_state,
13644                          struct intel_plane_state *state)
13645 {
13646         struct drm_crtc *crtc = crtc_state->base.crtc;
13647         struct drm_framebuffer *fb = state->base.fb;
13648         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13649         unsigned stride;
13650         int ret;
13651
13652         ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13653                                             &state->dst, &state->clip,
13654                                             DRM_PLANE_HELPER_NO_SCALING,
13655                                             DRM_PLANE_HELPER_NO_SCALING,
13656                                             true, true, &state->visible);
13657         if (ret)
13658                 return ret;
13659
13660         /* if we want to turn off the cursor ignore width and height */
13661         if (!obj)
13662                 return 0;
13663
13664         /* Check for which cursor types we support */
13665         if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
13666                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13667                           state->base.crtc_w, state->base.crtc_h);
13668                 return -EINVAL;
13669         }
13670
13671         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13672         if (obj->base.size < stride * state->base.crtc_h) {
13673                 DRM_DEBUG_KMS("buffer is too small\n");
13674                 return -ENOMEM;
13675         }
13676
13677         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13678                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13679                 return -EINVAL;
13680         }
13681
13682         return 0;
13683 }
13684
13685 static void
13686 intel_disable_cursor_plane(struct drm_plane *plane,
13687                            struct drm_crtc *crtc)
13688 {
13689         intel_crtc_update_cursor(crtc, false);
13690 }
13691
13692 static void
13693 intel_commit_cursor_plane(struct drm_plane *plane,
13694                           struct intel_plane_state *state)
13695 {
13696         struct drm_crtc *crtc = state->base.crtc;
13697         struct drm_device *dev = plane->dev;
13698         struct intel_crtc *intel_crtc;
13699         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13700         uint32_t addr;
13701
13702         crtc = crtc ? crtc : plane->crtc;
13703         intel_crtc = to_intel_crtc(crtc);
13704
13705         if (intel_crtc->cursor_bo == obj)
13706                 goto update;
13707
13708         if (!obj)
13709                 addr = 0;
13710         else if (!INTEL_INFO(dev)->cursor_needs_physical)
13711                 addr = i915_gem_obj_ggtt_offset(obj);
13712         else
13713                 addr = obj->phys_handle->busaddr;
13714
13715         intel_crtc->cursor_addr = addr;
13716         intel_crtc->cursor_bo = obj;
13717
13718 update:
13719         if (crtc->state->active)
13720                 intel_crtc_update_cursor(crtc, state->visible);
13721 }
13722
13723 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13724                                                    int pipe)
13725 {
13726         struct intel_plane *cursor;
13727         struct intel_plane_state *state;
13728
13729         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13730         if (cursor == NULL)
13731                 return NULL;
13732
13733         state = intel_create_plane_state(&cursor->base);
13734         if (!state) {
13735                 kfree(cursor);
13736                 return NULL;
13737         }
13738         cursor->base.state = &state->base;
13739
13740         cursor->can_scale = false;
13741         cursor->max_downscale = 1;
13742         cursor->pipe = pipe;
13743         cursor->plane = pipe;
13744         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13745         cursor->check_plane = intel_check_cursor_plane;
13746         cursor->commit_plane = intel_commit_cursor_plane;
13747         cursor->disable_plane = intel_disable_cursor_plane;
13748
13749         drm_universal_plane_init(dev, &cursor->base, 0,
13750                                  &intel_plane_funcs,
13751                                  intel_cursor_formats,
13752                                  ARRAY_SIZE(intel_cursor_formats),
13753                                  DRM_PLANE_TYPE_CURSOR);
13754
13755         if (INTEL_INFO(dev)->gen >= 4) {
13756                 if (!dev->mode_config.rotation_property)
13757                         dev->mode_config.rotation_property =
13758                                 drm_mode_create_rotation_property(dev,
13759                                                         BIT(DRM_ROTATE_0) |
13760                                                         BIT(DRM_ROTATE_180));
13761                 if (dev->mode_config.rotation_property)
13762                         drm_object_attach_property(&cursor->base.base,
13763                                 dev->mode_config.rotation_property,
13764                                 state->base.rotation);
13765         }
13766
13767         if (INTEL_INFO(dev)->gen >=9)
13768                 state->scaler_id = -1;
13769
13770         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13771
13772         return &cursor->base;
13773 }
13774
13775 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13776         struct intel_crtc_state *crtc_state)
13777 {
13778         int i;
13779         struct intel_scaler *intel_scaler;
13780         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13781
13782         for (i = 0; i < intel_crtc->num_scalers; i++) {
13783                 intel_scaler = &scaler_state->scalers[i];
13784                 intel_scaler->in_use = 0;
13785                 intel_scaler->mode = PS_SCALER_MODE_DYN;
13786         }
13787
13788         scaler_state->scaler_id = -1;
13789 }
13790
13791 static void intel_crtc_init(struct drm_device *dev, int pipe)
13792 {
13793         struct drm_i915_private *dev_priv = dev->dev_private;
13794         struct intel_crtc *intel_crtc;
13795         struct intel_crtc_state *crtc_state = NULL;
13796         struct drm_plane *primary = NULL;
13797         struct drm_plane *cursor = NULL;
13798         int i, ret;
13799
13800         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13801         if (intel_crtc == NULL)
13802                 return;
13803
13804         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13805         if (!crtc_state)
13806                 goto fail;
13807         intel_crtc->config = crtc_state;
13808         intel_crtc->base.state = &crtc_state->base;
13809         crtc_state->base.crtc = &intel_crtc->base;
13810
13811         /* initialize shared scalers */
13812         if (INTEL_INFO(dev)->gen >= 9) {
13813                 if (pipe == PIPE_C)
13814                         intel_crtc->num_scalers = 1;
13815                 else
13816                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
13817
13818                 skl_init_scalers(dev, intel_crtc, crtc_state);
13819         }
13820
13821         primary = intel_primary_plane_create(dev, pipe);
13822         if (!primary)
13823                 goto fail;
13824
13825         cursor = intel_cursor_plane_create(dev, pipe);
13826         if (!cursor)
13827                 goto fail;
13828
13829         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
13830                                         cursor, &intel_crtc_funcs);
13831         if (ret)
13832                 goto fail;
13833
13834         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
13835         for (i = 0; i < 256; i++) {
13836                 intel_crtc->lut_r[i] = i;
13837                 intel_crtc->lut_g[i] = i;
13838                 intel_crtc->lut_b[i] = i;
13839         }
13840
13841         /*
13842          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13843          * is hooked to pipe B. Hence we want plane A feeding pipe B.
13844          */
13845         intel_crtc->pipe = pipe;
13846         intel_crtc->plane = pipe;
13847         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
13848                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13849                 intel_crtc->plane = !pipe;
13850         }
13851
13852         intel_crtc->cursor_base = ~0;
13853         intel_crtc->cursor_cntl = ~0;
13854         intel_crtc->cursor_size = ~0;
13855
13856         intel_crtc->wm.cxsr_allowed = true;
13857
13858         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13859                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13860         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13861         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13862
13863         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13864
13865         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13866         return;
13867
13868 fail:
13869         if (primary)
13870                 drm_plane_cleanup(primary);
13871         if (cursor)
13872                 drm_plane_cleanup(cursor);
13873         kfree(crtc_state);
13874         kfree(intel_crtc);
13875 }
13876
13877 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13878 {
13879         struct drm_encoder *encoder = connector->base.encoder;
13880         struct drm_device *dev = connector->base.dev;
13881
13882         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13883
13884         if (!encoder || WARN_ON(!encoder->crtc))
13885                 return INVALID_PIPE;
13886
13887         return to_intel_crtc(encoder->crtc)->pipe;
13888 }
13889
13890 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13891                                 struct drm_file *file)
13892 {
13893         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13894         struct drm_crtc *drmmode_crtc;
13895         struct intel_crtc *crtc;
13896
13897         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13898
13899         if (!drmmode_crtc) {
13900                 DRM_ERROR("no such CRTC id\n");
13901                 return -ENOENT;
13902         }
13903
13904         crtc = to_intel_crtc(drmmode_crtc);
13905         pipe_from_crtc_id->pipe = crtc->pipe;
13906
13907         return 0;
13908 }
13909
13910 static int intel_encoder_clones(struct intel_encoder *encoder)
13911 {
13912         struct drm_device *dev = encoder->base.dev;
13913         struct intel_encoder *source_encoder;
13914         int index_mask = 0;
13915         int entry = 0;
13916
13917         for_each_intel_encoder(dev, source_encoder) {
13918                 if (encoders_cloneable(encoder, source_encoder))
13919                         index_mask |= (1 << entry);
13920
13921                 entry++;
13922         }
13923
13924         return index_mask;
13925 }
13926
13927 static bool has_edp_a(struct drm_device *dev)
13928 {
13929         struct drm_i915_private *dev_priv = dev->dev_private;
13930
13931         if (!IS_MOBILE(dev))
13932                 return false;
13933
13934         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13935                 return false;
13936
13937         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13938                 return false;
13939
13940         return true;
13941 }
13942
13943 static bool intel_crt_present(struct drm_device *dev)
13944 {
13945         struct drm_i915_private *dev_priv = dev->dev_private;
13946
13947         if (INTEL_INFO(dev)->gen >= 9)
13948                 return false;
13949
13950         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
13951                 return false;
13952
13953         if (IS_CHERRYVIEW(dev))
13954                 return false;
13955
13956         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13957                 return false;
13958
13959         return true;
13960 }
13961
13962 static void intel_setup_outputs(struct drm_device *dev)
13963 {
13964         struct drm_i915_private *dev_priv = dev->dev_private;
13965         struct intel_encoder *encoder;
13966         bool dpd_is_edp = false;
13967
13968         intel_lvds_init(dev);
13969
13970         if (intel_crt_present(dev))
13971                 intel_crt_init(dev);
13972
13973         if (IS_BROXTON(dev)) {
13974                 /*
13975                  * FIXME: Broxton doesn't support port detection via the
13976                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13977                  * detect the ports.
13978                  */
13979                 intel_ddi_init(dev, PORT_A);
13980                 intel_ddi_init(dev, PORT_B);
13981                 intel_ddi_init(dev, PORT_C);
13982         } else if (HAS_DDI(dev)) {
13983                 int found;
13984
13985                 /*
13986                  * Haswell uses DDI functions to detect digital outputs.
13987                  * On SKL pre-D0 the strap isn't connected, so we assume
13988                  * it's there.
13989                  */
13990                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
13991                 /* WaIgnoreDDIAStrap: skl */
13992                 if (found || IS_SKYLAKE(dev))
13993                         intel_ddi_init(dev, PORT_A);
13994
13995                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13996                  * register */
13997                 found = I915_READ(SFUSE_STRAP);
13998
13999                 if (found & SFUSE_STRAP_DDIB_DETECTED)
14000                         intel_ddi_init(dev, PORT_B);
14001                 if (found & SFUSE_STRAP_DDIC_DETECTED)
14002                         intel_ddi_init(dev, PORT_C);
14003                 if (found & SFUSE_STRAP_DDID_DETECTED)
14004                         intel_ddi_init(dev, PORT_D);
14005                 /*
14006                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14007                  */
14008                 if (IS_SKYLAKE(dev) &&
14009                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14010                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14011                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14012                         intel_ddi_init(dev, PORT_E);
14013
14014         } else if (HAS_PCH_SPLIT(dev)) {
14015                 int found;
14016                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14017
14018                 if (has_edp_a(dev))
14019                         intel_dp_init(dev, DP_A, PORT_A);
14020
14021                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14022                         /* PCH SDVOB multiplex with HDMIB */
14023                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
14024                         if (!found)
14025                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14026                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14027                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
14028                 }
14029
14030                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14031                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14032
14033                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14034                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14035
14036                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14037                         intel_dp_init(dev, PCH_DP_C, PORT_C);
14038
14039                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14040                         intel_dp_init(dev, PCH_DP_D, PORT_D);
14041         } else if (IS_VALLEYVIEW(dev)) {
14042                 /*
14043                  * The DP_DETECTED bit is the latched state of the DDC
14044                  * SDA pin at boot. However since eDP doesn't require DDC
14045                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14046                  * eDP ports may have been muxed to an alternate function.
14047                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14048                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14049                  * detect eDP ports.
14050                  */
14051                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14052                     !intel_dp_is_edp(dev, PORT_B))
14053                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14054                                         PORT_B);
14055                 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14056                     intel_dp_is_edp(dev, PORT_B))
14057                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
14058
14059                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14060                     !intel_dp_is_edp(dev, PORT_C))
14061                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14062                                         PORT_C);
14063                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14064                     intel_dp_is_edp(dev, PORT_C))
14065                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
14066
14067                 if (IS_CHERRYVIEW(dev)) {
14068                         if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
14069                                 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14070                                                 PORT_D);
14071                         /* eDP not supported on port D, so don't check VBT */
14072                         if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14073                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
14074                 }
14075
14076                 intel_dsi_init(dev);
14077         } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14078                 bool found = false;
14079
14080                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14081                         DRM_DEBUG_KMS("probing SDVOB\n");
14082                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14083                         if (!found && IS_G4X(dev)) {
14084                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14085                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14086                         }
14087
14088                         if (!found && IS_G4X(dev))
14089                                 intel_dp_init(dev, DP_B, PORT_B);
14090                 }
14091
14092                 /* Before G4X SDVOC doesn't have its own detect register */
14093
14094                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14095                         DRM_DEBUG_KMS("probing SDVOC\n");
14096                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14097                 }
14098
14099                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14100
14101                         if (IS_G4X(dev)) {
14102                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14103                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14104                         }
14105                         if (IS_G4X(dev))
14106                                 intel_dp_init(dev, DP_C, PORT_C);
14107                 }
14108
14109                 if (IS_G4X(dev) &&
14110                     (I915_READ(DP_D) & DP_DETECTED))
14111                         intel_dp_init(dev, DP_D, PORT_D);
14112         } else if (IS_GEN2(dev))
14113                 intel_dvo_init(dev);
14114
14115         if (SUPPORTS_TV(dev))
14116                 intel_tv_init(dev);
14117
14118         intel_psr_init(dev);
14119
14120         for_each_intel_encoder(dev, encoder) {
14121                 encoder->base.possible_crtcs = encoder->crtc_mask;
14122                 encoder->base.possible_clones =
14123                         intel_encoder_clones(encoder);
14124         }
14125
14126         intel_init_pch_refclk(dev);
14127
14128         drm_helper_move_panel_connectors_to_head(dev);
14129 }
14130
14131 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14132 {
14133         struct drm_device *dev = fb->dev;
14134         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14135
14136         drm_framebuffer_cleanup(fb);
14137         mutex_lock(&dev->struct_mutex);
14138         WARN_ON(!intel_fb->obj->framebuffer_references--);
14139         drm_gem_object_unreference(&intel_fb->obj->base);
14140         mutex_unlock(&dev->struct_mutex);
14141         kfree(intel_fb);
14142 }
14143
14144 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14145                                                 struct drm_file *file,
14146                                                 unsigned int *handle)
14147 {
14148         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14149         struct drm_i915_gem_object *obj = intel_fb->obj;
14150
14151         return drm_gem_handle_create(file, &obj->base, handle);
14152 }
14153
14154 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14155                                         struct drm_file *file,
14156                                         unsigned flags, unsigned color,
14157                                         struct drm_clip_rect *clips,
14158                                         unsigned num_clips)
14159 {
14160         struct drm_device *dev = fb->dev;
14161         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14162         struct drm_i915_gem_object *obj = intel_fb->obj;
14163
14164         mutex_lock(&dev->struct_mutex);
14165         intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14166         mutex_unlock(&dev->struct_mutex);
14167
14168         return 0;
14169 }
14170
14171 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14172         .destroy = intel_user_framebuffer_destroy,
14173         .create_handle = intel_user_framebuffer_create_handle,
14174         .dirty = intel_user_framebuffer_dirty,
14175 };
14176
14177 static
14178 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14179                          uint32_t pixel_format)
14180 {
14181         u32 gen = INTEL_INFO(dev)->gen;
14182
14183         if (gen >= 9) {
14184                 /* "The stride in bytes must not exceed the of the size of 8K
14185                  *  pixels and 32K bytes."
14186                  */
14187                  return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14188         } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14189                 return 32*1024;
14190         } else if (gen >= 4) {
14191                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14192                         return 16*1024;
14193                 else
14194                         return 32*1024;
14195         } else if (gen >= 3) {
14196                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14197                         return 8*1024;
14198                 else
14199                         return 16*1024;
14200         } else {
14201                 /* XXX DSPC is limited to 4k tiled */
14202                 return 8*1024;
14203         }
14204 }
14205
14206 static int intel_framebuffer_init(struct drm_device *dev,
14207                                   struct intel_framebuffer *intel_fb,
14208                                   struct drm_mode_fb_cmd2 *mode_cmd,
14209                                   struct drm_i915_gem_object *obj)
14210 {
14211         unsigned int aligned_height;
14212         int ret;
14213         u32 pitch_limit, stride_alignment;
14214
14215         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14216
14217         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14218                 /* Enforce that fb modifier and tiling mode match, but only for
14219                  * X-tiled. This is needed for FBC. */
14220                 if (!!(obj->tiling_mode == I915_TILING_X) !=
14221                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14222                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14223                         return -EINVAL;
14224                 }
14225         } else {
14226                 if (obj->tiling_mode == I915_TILING_X)
14227                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14228                 else if (obj->tiling_mode == I915_TILING_Y) {
14229                         DRM_DEBUG("No Y tiling for legacy addfb\n");
14230                         return -EINVAL;
14231                 }
14232         }
14233
14234         /* Passed in modifier sanity checking. */
14235         switch (mode_cmd->modifier[0]) {
14236         case I915_FORMAT_MOD_Y_TILED:
14237         case I915_FORMAT_MOD_Yf_TILED:
14238                 if (INTEL_INFO(dev)->gen < 9) {
14239                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14240                                   mode_cmd->modifier[0]);
14241                         return -EINVAL;
14242                 }
14243         case DRM_FORMAT_MOD_NONE:
14244         case I915_FORMAT_MOD_X_TILED:
14245                 break;
14246         default:
14247                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14248                           mode_cmd->modifier[0]);
14249                 return -EINVAL;
14250         }
14251
14252         stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14253                                                      mode_cmd->pixel_format);
14254         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14255                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14256                           mode_cmd->pitches[0], stride_alignment);
14257                 return -EINVAL;
14258         }
14259
14260         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14261                                            mode_cmd->pixel_format);
14262         if (mode_cmd->pitches[0] > pitch_limit) {
14263                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14264                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14265                           "tiled" : "linear",
14266                           mode_cmd->pitches[0], pitch_limit);
14267                 return -EINVAL;
14268         }
14269
14270         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14271             mode_cmd->pitches[0] != obj->stride) {
14272                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14273                           mode_cmd->pitches[0], obj->stride);
14274                 return -EINVAL;
14275         }
14276
14277         /* Reject formats not supported by any plane early. */
14278         switch (mode_cmd->pixel_format) {
14279         case DRM_FORMAT_C8:
14280         case DRM_FORMAT_RGB565:
14281         case DRM_FORMAT_XRGB8888:
14282         case DRM_FORMAT_ARGB8888:
14283                 break;
14284         case DRM_FORMAT_XRGB1555:
14285                 if (INTEL_INFO(dev)->gen > 3) {
14286                         DRM_DEBUG("unsupported pixel format: %s\n",
14287                                   drm_get_format_name(mode_cmd->pixel_format));
14288                         return -EINVAL;
14289                 }
14290                 break;
14291         case DRM_FORMAT_ABGR8888:
14292                 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14293                         DRM_DEBUG("unsupported pixel format: %s\n",
14294                                   drm_get_format_name(mode_cmd->pixel_format));
14295                         return -EINVAL;
14296                 }
14297                 break;
14298         case DRM_FORMAT_XBGR8888:
14299         case DRM_FORMAT_XRGB2101010:
14300         case DRM_FORMAT_XBGR2101010:
14301                 if (INTEL_INFO(dev)->gen < 4) {
14302                         DRM_DEBUG("unsupported pixel format: %s\n",
14303                                   drm_get_format_name(mode_cmd->pixel_format));
14304                         return -EINVAL;
14305                 }
14306                 break;
14307         case DRM_FORMAT_ABGR2101010:
14308                 if (!IS_VALLEYVIEW(dev)) {
14309                         DRM_DEBUG("unsupported pixel format: %s\n",
14310                                   drm_get_format_name(mode_cmd->pixel_format));
14311                         return -EINVAL;
14312                 }
14313                 break;
14314         case DRM_FORMAT_YUYV:
14315         case DRM_FORMAT_UYVY:
14316         case DRM_FORMAT_YVYU:
14317         case DRM_FORMAT_VYUY:
14318                 if (INTEL_INFO(dev)->gen < 5) {
14319                         DRM_DEBUG("unsupported pixel format: %s\n",
14320                                   drm_get_format_name(mode_cmd->pixel_format));
14321                         return -EINVAL;
14322                 }
14323                 break;
14324         default:
14325                 DRM_DEBUG("unsupported pixel format: %s\n",
14326                           drm_get_format_name(mode_cmd->pixel_format));
14327                 return -EINVAL;
14328         }
14329
14330         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14331         if (mode_cmd->offsets[0] != 0)
14332                 return -EINVAL;
14333
14334         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14335                                                mode_cmd->pixel_format,
14336                                                mode_cmd->modifier[0]);
14337         /* FIXME drm helper for size checks (especially planar formats)? */
14338         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14339                 return -EINVAL;
14340
14341         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14342         intel_fb->obj = obj;
14343         intel_fb->obj->framebuffer_references++;
14344
14345         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14346         if (ret) {
14347                 DRM_ERROR("framebuffer init failed %d\n", ret);
14348                 return ret;
14349         }
14350
14351         return 0;
14352 }
14353
14354 static struct drm_framebuffer *
14355 intel_user_framebuffer_create(struct drm_device *dev,
14356                               struct drm_file *filp,
14357                               struct drm_mode_fb_cmd2 *mode_cmd)
14358 {
14359         struct drm_i915_gem_object *obj;
14360
14361         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14362                                                 mode_cmd->handles[0]));
14363         if (&obj->base == NULL)
14364                 return ERR_PTR(-ENOENT);
14365
14366         return intel_framebuffer_create(dev, mode_cmd, obj);
14367 }
14368
14369 #ifndef CONFIG_DRM_FBDEV_EMULATION
14370 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14371 {
14372 }
14373 #endif
14374
14375 static const struct drm_mode_config_funcs intel_mode_funcs = {
14376         .fb_create = intel_user_framebuffer_create,
14377         .output_poll_changed = intel_fbdev_output_poll_changed,
14378         .atomic_check = intel_atomic_check,
14379         .atomic_commit = intel_atomic_commit,
14380         .atomic_state_alloc = intel_atomic_state_alloc,
14381         .atomic_state_clear = intel_atomic_state_clear,
14382 };
14383
14384 /* Set up chip specific display functions */
14385 static void intel_init_display(struct drm_device *dev)
14386 {
14387         struct drm_i915_private *dev_priv = dev->dev_private;
14388
14389         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14390                 dev_priv->display.find_dpll = g4x_find_best_dpll;
14391         else if (IS_CHERRYVIEW(dev))
14392                 dev_priv->display.find_dpll = chv_find_best_dpll;
14393         else if (IS_VALLEYVIEW(dev))
14394                 dev_priv->display.find_dpll = vlv_find_best_dpll;
14395         else if (IS_PINEVIEW(dev))
14396                 dev_priv->display.find_dpll = pnv_find_best_dpll;
14397         else
14398                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14399
14400         if (INTEL_INFO(dev)->gen >= 9) {
14401                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14402                 dev_priv->display.get_initial_plane_config =
14403                         skylake_get_initial_plane_config;
14404                 dev_priv->display.crtc_compute_clock =
14405                         haswell_crtc_compute_clock;
14406                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14407                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14408                 dev_priv->display.update_primary_plane =
14409                         skylake_update_primary_plane;
14410         } else if (HAS_DDI(dev)) {
14411                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14412                 dev_priv->display.get_initial_plane_config =
14413                         ironlake_get_initial_plane_config;
14414                 dev_priv->display.crtc_compute_clock =
14415                         haswell_crtc_compute_clock;
14416                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14417                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14418                 dev_priv->display.update_primary_plane =
14419                         ironlake_update_primary_plane;
14420         } else if (HAS_PCH_SPLIT(dev)) {
14421                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14422                 dev_priv->display.get_initial_plane_config =
14423                         ironlake_get_initial_plane_config;
14424                 dev_priv->display.crtc_compute_clock =
14425                         ironlake_crtc_compute_clock;
14426                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14427                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14428                 dev_priv->display.update_primary_plane =
14429                         ironlake_update_primary_plane;
14430         } else if (IS_VALLEYVIEW(dev)) {
14431                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14432                 dev_priv->display.get_initial_plane_config =
14433                         i9xx_get_initial_plane_config;
14434                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14435                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14436                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14437                 dev_priv->display.update_primary_plane =
14438                         i9xx_update_primary_plane;
14439         } else {
14440                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14441                 dev_priv->display.get_initial_plane_config =
14442                         i9xx_get_initial_plane_config;
14443                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14444                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14445                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14446                 dev_priv->display.update_primary_plane =
14447                         i9xx_update_primary_plane;
14448         }
14449
14450         /* Returns the core display clock speed */
14451         if (IS_SKYLAKE(dev))
14452                 dev_priv->display.get_display_clock_speed =
14453                         skylake_get_display_clock_speed;
14454         else if (IS_BROXTON(dev))
14455                 dev_priv->display.get_display_clock_speed =
14456                         broxton_get_display_clock_speed;
14457         else if (IS_BROADWELL(dev))
14458                 dev_priv->display.get_display_clock_speed =
14459                         broadwell_get_display_clock_speed;
14460         else if (IS_HASWELL(dev))
14461                 dev_priv->display.get_display_clock_speed =
14462                         haswell_get_display_clock_speed;
14463         else if (IS_VALLEYVIEW(dev))
14464                 dev_priv->display.get_display_clock_speed =
14465                         valleyview_get_display_clock_speed;
14466         else if (IS_GEN5(dev))
14467                 dev_priv->display.get_display_clock_speed =
14468                         ilk_get_display_clock_speed;
14469         else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14470                  IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14471                 dev_priv->display.get_display_clock_speed =
14472                         i945_get_display_clock_speed;
14473         else if (IS_GM45(dev))
14474                 dev_priv->display.get_display_clock_speed =
14475                         gm45_get_display_clock_speed;
14476         else if (IS_CRESTLINE(dev))
14477                 dev_priv->display.get_display_clock_speed =
14478                         i965gm_get_display_clock_speed;
14479         else if (IS_PINEVIEW(dev))
14480                 dev_priv->display.get_display_clock_speed =
14481                         pnv_get_display_clock_speed;
14482         else if (IS_G33(dev) || IS_G4X(dev))
14483                 dev_priv->display.get_display_clock_speed =
14484                         g33_get_display_clock_speed;
14485         else if (IS_I915G(dev))
14486                 dev_priv->display.get_display_clock_speed =
14487                         i915_get_display_clock_speed;
14488         else if (IS_I945GM(dev) || IS_845G(dev))
14489                 dev_priv->display.get_display_clock_speed =
14490                         i9xx_misc_get_display_clock_speed;
14491         else if (IS_PINEVIEW(dev))
14492                 dev_priv->display.get_display_clock_speed =
14493                         pnv_get_display_clock_speed;
14494         else if (IS_I915GM(dev))
14495                 dev_priv->display.get_display_clock_speed =
14496                         i915gm_get_display_clock_speed;
14497         else if (IS_I865G(dev))
14498                 dev_priv->display.get_display_clock_speed =
14499                         i865_get_display_clock_speed;
14500         else if (IS_I85X(dev))
14501                 dev_priv->display.get_display_clock_speed =
14502                         i85x_get_display_clock_speed;
14503         else { /* 830 */
14504                 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14505                 dev_priv->display.get_display_clock_speed =
14506                         i830_get_display_clock_speed;
14507         }
14508
14509         if (IS_GEN5(dev)) {
14510                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14511         } else if (IS_GEN6(dev)) {
14512                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14513         } else if (IS_IVYBRIDGE(dev)) {
14514                 /* FIXME: detect B0+ stepping and use auto training */
14515                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14516         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14517                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14518                 if (IS_BROADWELL(dev)) {
14519                         dev_priv->display.modeset_commit_cdclk =
14520                                 broadwell_modeset_commit_cdclk;
14521                         dev_priv->display.modeset_calc_cdclk =
14522                                 broadwell_modeset_calc_cdclk;
14523                 }
14524         } else if (IS_VALLEYVIEW(dev)) {
14525                 dev_priv->display.modeset_commit_cdclk =
14526                         valleyview_modeset_commit_cdclk;
14527                 dev_priv->display.modeset_calc_cdclk =
14528                         valleyview_modeset_calc_cdclk;
14529         } else if (IS_BROXTON(dev)) {
14530                 dev_priv->display.modeset_commit_cdclk =
14531                         broxton_modeset_commit_cdclk;
14532                 dev_priv->display.modeset_calc_cdclk =
14533                         broxton_modeset_calc_cdclk;
14534         }
14535
14536         switch (INTEL_INFO(dev)->gen) {
14537         case 2:
14538                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14539                 break;
14540
14541         case 3:
14542                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14543                 break;
14544
14545         case 4:
14546         case 5:
14547                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14548                 break;
14549
14550         case 6:
14551                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14552                 break;
14553         case 7:
14554         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14555                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14556                 break;
14557         case 9:
14558                 /* Drop through - unsupported since execlist only. */
14559         default:
14560                 /* Default just returns -ENODEV to indicate unsupported */
14561                 dev_priv->display.queue_flip = intel_default_queue_flip;
14562         }
14563
14564         intel_panel_init_backlight_funcs(dev);
14565
14566         mutex_init(&dev_priv->pps_mutex);
14567 }
14568
14569 /*
14570  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14571  * resume, or other times.  This quirk makes sure that's the case for
14572  * affected systems.
14573  */
14574 static void quirk_pipea_force(struct drm_device *dev)
14575 {
14576         struct drm_i915_private *dev_priv = dev->dev_private;
14577
14578         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14579         DRM_INFO("applying pipe a force quirk\n");
14580 }
14581
14582 static void quirk_pipeb_force(struct drm_device *dev)
14583 {
14584         struct drm_i915_private *dev_priv = dev->dev_private;
14585
14586         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14587         DRM_INFO("applying pipe b force quirk\n");
14588 }
14589
14590 /*
14591  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14592  */
14593 static void quirk_ssc_force_disable(struct drm_device *dev)
14594 {
14595         struct drm_i915_private *dev_priv = dev->dev_private;
14596         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14597         DRM_INFO("applying lvds SSC disable quirk\n");
14598 }
14599
14600 /*
14601  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14602  * brightness value
14603  */
14604 static void quirk_invert_brightness(struct drm_device *dev)
14605 {
14606         struct drm_i915_private *dev_priv = dev->dev_private;
14607         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14608         DRM_INFO("applying inverted panel brightness quirk\n");
14609 }
14610
14611 /* Some VBT's incorrectly indicate no backlight is present */
14612 static void quirk_backlight_present(struct drm_device *dev)
14613 {
14614         struct drm_i915_private *dev_priv = dev->dev_private;
14615         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14616         DRM_INFO("applying backlight present quirk\n");
14617 }
14618
14619 struct intel_quirk {
14620         int device;
14621         int subsystem_vendor;
14622         int subsystem_device;
14623         void (*hook)(struct drm_device *dev);
14624 };
14625
14626 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14627 struct intel_dmi_quirk {
14628         void (*hook)(struct drm_device *dev);
14629         const struct dmi_system_id (*dmi_id_list)[];
14630 };
14631
14632 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14633 {
14634         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14635         return 1;
14636 }
14637
14638 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14639         {
14640                 .dmi_id_list = &(const struct dmi_system_id[]) {
14641                         {
14642                                 .callback = intel_dmi_reverse_brightness,
14643                                 .ident = "NCR Corporation",
14644                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14645                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
14646                                 },
14647                         },
14648                         { }  /* terminating entry */
14649                 },
14650                 .hook = quirk_invert_brightness,
14651         },
14652 };
14653
14654 static struct intel_quirk intel_quirks[] = {
14655         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14656         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14657
14658         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14659         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14660
14661         /* 830 needs to leave pipe A & dpll A up */
14662         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14663
14664         /* 830 needs to leave pipe B & dpll B up */
14665         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14666
14667         /* Lenovo U160 cannot use SSC on LVDS */
14668         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14669
14670         /* Sony Vaio Y cannot use SSC on LVDS */
14671         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14672
14673         /* Acer Aspire 5734Z must invert backlight brightness */
14674         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14675
14676         /* Acer/eMachines G725 */
14677         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14678
14679         /* Acer/eMachines e725 */
14680         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14681
14682         /* Acer/Packard Bell NCL20 */
14683         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14684
14685         /* Acer Aspire 4736Z */
14686         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14687
14688         /* Acer Aspire 5336 */
14689         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14690
14691         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14692         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14693
14694         /* Acer C720 Chromebook (Core i3 4005U) */
14695         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14696
14697         /* Apple Macbook 2,1 (Core 2 T7400) */
14698         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14699
14700         /* Toshiba CB35 Chromebook (Celeron 2955U) */
14701         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14702
14703         /* HP Chromebook 14 (Celeron 2955U) */
14704         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14705
14706         /* Dell Chromebook 11 */
14707         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14708 };
14709
14710 static void intel_init_quirks(struct drm_device *dev)
14711 {
14712         struct pci_dev *d = dev->pdev;
14713         int i;
14714
14715         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14716                 struct intel_quirk *q = &intel_quirks[i];
14717
14718                 if (d->device == q->device &&
14719                     (d->subsystem_vendor == q->subsystem_vendor ||
14720                      q->subsystem_vendor == PCI_ANY_ID) &&
14721                     (d->subsystem_device == q->subsystem_device ||
14722                      q->subsystem_device == PCI_ANY_ID))
14723                         q->hook(dev);
14724         }
14725         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14726                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14727                         intel_dmi_quirks[i].hook(dev);
14728         }
14729 }
14730
14731 /* Disable the VGA plane that we never use */
14732 static void i915_disable_vga(struct drm_device *dev)
14733 {
14734         struct drm_i915_private *dev_priv = dev->dev_private;
14735         u8 sr1;
14736         u32 vga_reg = i915_vgacntrl_reg(dev);
14737
14738         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14739         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14740         outb(SR01, VGA_SR_INDEX);
14741         sr1 = inb(VGA_SR_DATA);
14742         outb(sr1 | 1<<5, VGA_SR_DATA);
14743         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14744         udelay(300);
14745
14746         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14747         POSTING_READ(vga_reg);
14748 }
14749
14750 void intel_modeset_init_hw(struct drm_device *dev)
14751 {
14752         intel_update_cdclk(dev);
14753         intel_prepare_ddi(dev);
14754         intel_init_clock_gating(dev);
14755         intel_enable_gt_powersave(dev);
14756 }
14757
14758 void intel_modeset_init(struct drm_device *dev)
14759 {
14760         struct drm_i915_private *dev_priv = dev->dev_private;
14761         int sprite, ret;
14762         enum pipe pipe;
14763         struct intel_crtc *crtc;
14764
14765         drm_mode_config_init(dev);
14766
14767         dev->mode_config.min_width = 0;
14768         dev->mode_config.min_height = 0;
14769
14770         dev->mode_config.preferred_depth = 24;
14771         dev->mode_config.prefer_shadow = 1;
14772
14773         dev->mode_config.allow_fb_modifiers = true;
14774
14775         dev->mode_config.funcs = &intel_mode_funcs;
14776
14777         intel_init_quirks(dev);
14778
14779         intel_init_pm(dev);
14780
14781         if (INTEL_INFO(dev)->num_pipes == 0)
14782                 return;
14783
14784         /*
14785          * There may be no VBT; and if the BIOS enabled SSC we can
14786          * just keep using it to avoid unnecessary flicker.  Whereas if the
14787          * BIOS isn't using it, don't assume it will work even if the VBT
14788          * indicates as much.
14789          */
14790         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
14791                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14792                                             DREF_SSC1_ENABLE);
14793
14794                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14795                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14796                                      bios_lvds_use_ssc ? "en" : "dis",
14797                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14798                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14799                 }
14800         }
14801
14802         intel_init_display(dev);
14803         intel_init_audio(dev);
14804
14805         if (IS_GEN2(dev)) {
14806                 dev->mode_config.max_width = 2048;
14807                 dev->mode_config.max_height = 2048;
14808         } else if (IS_GEN3(dev)) {
14809                 dev->mode_config.max_width = 4096;
14810                 dev->mode_config.max_height = 4096;
14811         } else {
14812                 dev->mode_config.max_width = 8192;
14813                 dev->mode_config.max_height = 8192;
14814         }
14815
14816         if (IS_845G(dev) || IS_I865G(dev)) {
14817                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14818                 dev->mode_config.cursor_height = 1023;
14819         } else if (IS_GEN2(dev)) {
14820                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14821                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14822         } else {
14823                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14824                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14825         }
14826
14827         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
14828
14829         DRM_DEBUG_KMS("%d display pipe%s available.\n",
14830                       INTEL_INFO(dev)->num_pipes,
14831                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14832
14833         for_each_pipe(dev_priv, pipe) {
14834                 intel_crtc_init(dev, pipe);
14835                 for_each_sprite(dev_priv, pipe, sprite) {
14836                         ret = intel_plane_init(dev, pipe, sprite);
14837                         if (ret)
14838                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14839                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
14840                 }
14841         }
14842
14843         intel_shared_dpll_init(dev);
14844
14845         /* Just disable it once at startup */
14846         i915_disable_vga(dev);
14847         intel_setup_outputs(dev);
14848
14849         /* Just in case the BIOS is doing something questionable. */
14850         intel_fbc_disable(dev_priv);
14851
14852         drm_modeset_lock_all(dev);
14853         intel_modeset_setup_hw_state(dev);
14854         drm_modeset_unlock_all(dev);
14855
14856         for_each_intel_crtc(dev, crtc) {
14857                 struct intel_initial_plane_config plane_config = {};
14858
14859                 if (!crtc->active)
14860                         continue;
14861
14862                 /*
14863                  * Note that reserving the BIOS fb up front prevents us
14864                  * from stuffing other stolen allocations like the ring
14865                  * on top.  This prevents some ugliness at boot time, and
14866                  * can even allow for smooth boot transitions if the BIOS
14867                  * fb is large enough for the active pipe configuration.
14868                  */
14869                 dev_priv->display.get_initial_plane_config(crtc,
14870                                                            &plane_config);
14871
14872                 /*
14873                  * If the fb is shared between multiple heads, we'll
14874                  * just get the first one.
14875                  */
14876                 intel_find_initial_plane_obj(crtc, &plane_config);
14877         }
14878 }
14879
14880 static void intel_enable_pipe_a(struct drm_device *dev)
14881 {
14882         struct intel_connector *connector;
14883         struct drm_connector *crt = NULL;
14884         struct intel_load_detect_pipe load_detect_temp;
14885         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
14886
14887         /* We can't just switch on the pipe A, we need to set things up with a
14888          * proper mode and output configuration. As a gross hack, enable pipe A
14889          * by enabling the load detect pipe once. */
14890         for_each_intel_connector(dev, connector) {
14891                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14892                         crt = &connector->base;
14893                         break;
14894                 }
14895         }
14896
14897         if (!crt)
14898                 return;
14899
14900         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
14901                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
14902 }
14903
14904 static bool
14905 intel_check_plane_mapping(struct intel_crtc *crtc)
14906 {
14907         struct drm_device *dev = crtc->base.dev;
14908         struct drm_i915_private *dev_priv = dev->dev_private;
14909         u32 reg, val;
14910
14911         if (INTEL_INFO(dev)->num_pipes == 1)
14912                 return true;
14913
14914         reg = DSPCNTR(!crtc->plane);
14915         val = I915_READ(reg);
14916
14917         if ((val & DISPLAY_PLANE_ENABLE) &&
14918             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14919                 return false;
14920
14921         return true;
14922 }
14923
14924 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
14925 {
14926         struct drm_device *dev = crtc->base.dev;
14927         struct intel_encoder *encoder;
14928
14929         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
14930                 return true;
14931
14932         return false;
14933 }
14934
14935 static void intel_sanitize_crtc(struct intel_crtc *crtc)
14936 {
14937         struct drm_device *dev = crtc->base.dev;
14938         struct drm_i915_private *dev_priv = dev->dev_private;
14939         u32 reg;
14940
14941         /* Clear any frame start delays used for debugging left by the BIOS */
14942         reg = PIPECONF(crtc->config->cpu_transcoder);
14943         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14944
14945         /* restore vblank interrupts to correct state */
14946         drm_crtc_vblank_reset(&crtc->base);
14947         if (crtc->active) {
14948                 struct intel_plane *plane;
14949
14950                 drm_crtc_vblank_on(&crtc->base);
14951
14952                 /* Disable everything but the primary plane */
14953                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
14954                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
14955                                 continue;
14956
14957                         plane->disable_plane(&plane->base, &crtc->base);
14958                 }
14959         }
14960
14961         /* We need to sanitize the plane -> pipe mapping first because this will
14962          * disable the crtc (and hence change the state) if it is wrong. Note
14963          * that gen4+ has a fixed plane -> pipe mapping.  */
14964         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
14965                 bool plane;
14966
14967                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14968                               crtc->base.base.id);
14969
14970                 /* Pipe has the wrong plane attached and the plane is active.
14971                  * Temporarily change the plane mapping and disable everything
14972                  * ...  */
14973                 plane = crtc->plane;
14974                 to_intel_plane_state(crtc->base.primary->state)->visible = true;
14975                 crtc->plane = !plane;
14976                 intel_crtc_disable_noatomic(&crtc->base);
14977                 crtc->plane = plane;
14978         }
14979
14980         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14981             crtc->pipe == PIPE_A && !crtc->active) {
14982                 /* BIOS forgot to enable pipe A, this mostly happens after
14983                  * resume. Force-enable the pipe to fix this, the update_dpms
14984                  * call below we restore the pipe to the right state, but leave
14985                  * the required bits on. */
14986                 intel_enable_pipe_a(dev);
14987         }
14988
14989         /* Adjust the state of the output pipe according to whether we
14990          * have active connectors/encoders. */
14991         if (!intel_crtc_has_encoders(crtc))
14992                 intel_crtc_disable_noatomic(&crtc->base);
14993
14994         if (crtc->active != crtc->base.state->active) {
14995                 struct intel_encoder *encoder;
14996
14997                 /* This can happen either due to bugs in the get_hw_state
14998                  * functions or because of calls to intel_crtc_disable_noatomic,
14999                  * or because the pipe is force-enabled due to the
15000                  * pipe A quirk. */
15001                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15002                               crtc->base.base.id,
15003                               crtc->base.state->enable ? "enabled" : "disabled",
15004                               crtc->active ? "enabled" : "disabled");
15005
15006                 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
15007                 crtc->base.state->active = crtc->active;
15008                 crtc->base.enabled = crtc->active;
15009
15010                 /* Because we only establish the connector -> encoder ->
15011                  * crtc links if something is active, this means the
15012                  * crtc is now deactivated. Break the links. connector
15013                  * -> encoder links are only establish when things are
15014                  *  actually up, hence no need to break them. */
15015                 WARN_ON(crtc->active);
15016
15017                 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15018                         encoder->base.crtc = NULL;
15019         }
15020
15021         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15022                 /*
15023                  * We start out with underrun reporting disabled to avoid races.
15024                  * For correct bookkeeping mark this on active crtcs.
15025                  *
15026                  * Also on gmch platforms we dont have any hardware bits to
15027                  * disable the underrun reporting. Which means we need to start
15028                  * out with underrun reporting disabled also on inactive pipes,
15029                  * since otherwise we'll complain about the garbage we read when
15030                  * e.g. coming up after runtime pm.
15031                  *
15032                  * No protection against concurrent access is required - at
15033                  * worst a fifo underrun happens which also sets this to false.
15034                  */
15035                 crtc->cpu_fifo_underrun_disabled = true;
15036                 crtc->pch_fifo_underrun_disabled = true;
15037         }
15038 }
15039
15040 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15041 {
15042         struct intel_connector *connector;
15043         struct drm_device *dev = encoder->base.dev;
15044         bool active = false;
15045
15046         /* We need to check both for a crtc link (meaning that the
15047          * encoder is active and trying to read from a pipe) and the
15048          * pipe itself being active. */
15049         bool has_active_crtc = encoder->base.crtc &&
15050                 to_intel_crtc(encoder->base.crtc)->active;
15051
15052         for_each_intel_connector(dev, connector) {
15053                 if (connector->base.encoder != &encoder->base)
15054                         continue;
15055
15056                 active = true;
15057                 break;
15058         }
15059
15060         if (active && !has_active_crtc) {
15061                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15062                               encoder->base.base.id,
15063                               encoder->base.name);
15064
15065                 /* Connector is active, but has no active pipe. This is
15066                  * fallout from our resume register restoring. Disable
15067                  * the encoder manually again. */
15068                 if (encoder->base.crtc) {
15069                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15070                                       encoder->base.base.id,
15071                                       encoder->base.name);
15072                         encoder->disable(encoder);
15073                         if (encoder->post_disable)
15074                                 encoder->post_disable(encoder);
15075                 }
15076                 encoder->base.crtc = NULL;
15077
15078                 /* Inconsistent output/port/pipe state happens presumably due to
15079                  * a bug in one of the get_hw_state functions. Or someplace else
15080                  * in our code, like the register restore mess on resume. Clamp
15081                  * things to off as a safer default. */
15082                 for_each_intel_connector(dev, connector) {
15083                         if (connector->encoder != encoder)
15084                                 continue;
15085                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15086                         connector->base.encoder = NULL;
15087                 }
15088         }
15089         /* Enabled encoders without active connectors will be fixed in
15090          * the crtc fixup. */
15091 }
15092
15093 void i915_redisable_vga_power_on(struct drm_device *dev)
15094 {
15095         struct drm_i915_private *dev_priv = dev->dev_private;
15096         u32 vga_reg = i915_vgacntrl_reg(dev);
15097
15098         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15099                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15100                 i915_disable_vga(dev);
15101         }
15102 }
15103
15104 void i915_redisable_vga(struct drm_device *dev)
15105 {
15106         struct drm_i915_private *dev_priv = dev->dev_private;
15107
15108         /* This function can be called both from intel_modeset_setup_hw_state or
15109          * at a very early point in our resume sequence, where the power well
15110          * structures are not yet restored. Since this function is at a very
15111          * paranoid "someone might have enabled VGA while we were not looking"
15112          * level, just check if the power well is enabled instead of trying to
15113          * follow the "don't touch the power well if we don't need it" policy
15114          * the rest of the driver uses. */
15115         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15116                 return;
15117
15118         i915_redisable_vga_power_on(dev);
15119 }
15120
15121 static bool primary_get_hw_state(struct intel_plane *plane)
15122 {
15123         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15124
15125         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15126 }
15127
15128 /* FIXME read out full plane state for all planes */
15129 static void readout_plane_state(struct intel_crtc *crtc)
15130 {
15131         struct drm_plane *primary = crtc->base.primary;
15132         struct intel_plane_state *plane_state =
15133                 to_intel_plane_state(primary->state);
15134
15135         plane_state->visible =
15136                 primary_get_hw_state(to_intel_plane(primary));
15137
15138         if (plane_state->visible)
15139                 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15140 }
15141
15142 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15143 {
15144         struct drm_i915_private *dev_priv = dev->dev_private;
15145         enum pipe pipe;
15146         struct intel_crtc *crtc;
15147         struct intel_encoder *encoder;
15148         struct intel_connector *connector;
15149         int i;
15150
15151         for_each_intel_crtc(dev, crtc) {
15152                 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
15153                 memset(crtc->config, 0, sizeof(*crtc->config));
15154                 crtc->config->base.crtc = &crtc->base;
15155
15156                 crtc->active = dev_priv->display.get_pipe_config(crtc,
15157                                                                  crtc->config);
15158
15159                 crtc->base.state->active = crtc->active;
15160                 crtc->base.enabled = crtc->active;
15161
15162                 readout_plane_state(crtc);
15163
15164                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15165                               crtc->base.base.id,
15166                               crtc->active ? "enabled" : "disabled");
15167         }
15168
15169         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15170                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15171
15172                 pll->on = pll->get_hw_state(dev_priv, pll,
15173                                             &pll->config.hw_state);
15174                 pll->active = 0;
15175                 pll->config.crtc_mask = 0;
15176                 for_each_intel_crtc(dev, crtc) {
15177                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15178                                 pll->active++;
15179                                 pll->config.crtc_mask |= 1 << crtc->pipe;
15180                         }
15181                 }
15182
15183                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15184                               pll->name, pll->config.crtc_mask, pll->on);
15185
15186                 if (pll->config.crtc_mask)
15187                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15188         }
15189
15190         for_each_intel_encoder(dev, encoder) {
15191                 pipe = 0;
15192
15193                 if (encoder->get_hw_state(encoder, &pipe)) {
15194                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15195                         encoder->base.crtc = &crtc->base;
15196                         encoder->get_config(encoder, crtc->config);
15197                 } else {
15198                         encoder->base.crtc = NULL;
15199                 }
15200
15201                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15202                               encoder->base.base.id,
15203                               encoder->base.name,
15204                               encoder->base.crtc ? "enabled" : "disabled",
15205                               pipe_name(pipe));
15206         }
15207
15208         for_each_intel_connector(dev, connector) {
15209                 if (connector->get_hw_state(connector)) {
15210                         connector->base.dpms = DRM_MODE_DPMS_ON;
15211                         connector->base.encoder = &connector->encoder->base;
15212                 } else {
15213                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15214                         connector->base.encoder = NULL;
15215                 }
15216                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15217                               connector->base.base.id,
15218                               connector->base.name,
15219                               connector->base.encoder ? "enabled" : "disabled");
15220         }
15221
15222         for_each_intel_crtc(dev, crtc) {
15223                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15224
15225                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15226                 if (crtc->base.state->active) {
15227                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15228                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15229                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15230
15231                         /*
15232                          * The initial mode needs to be set in order to keep
15233                          * the atomic core happy. It wants a valid mode if the
15234                          * crtc's enabled, so we do the above call.
15235                          *
15236                          * At this point some state updated by the connectors
15237                          * in their ->detect() callback has not run yet, so
15238                          * no recalculation can be done yet.
15239                          *
15240                          * Even if we could do a recalculation and modeset
15241                          * right now it would cause a double modeset if
15242                          * fbdev or userspace chooses a different initial mode.
15243                          *
15244                          * If that happens, someone indicated they wanted a
15245                          * mode change, which means it's safe to do a full
15246                          * recalculation.
15247                          */
15248                         crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15249
15250                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15251                         update_scanline_offset(crtc);
15252                 }
15253         }
15254 }
15255
15256 /* Scan out the current hw modeset state,
15257  * and sanitizes it to the current state
15258  */
15259 static void
15260 intel_modeset_setup_hw_state(struct drm_device *dev)
15261 {
15262         struct drm_i915_private *dev_priv = dev->dev_private;
15263         enum pipe pipe;
15264         struct intel_crtc *crtc;
15265         struct intel_encoder *encoder;
15266         int i;
15267
15268         intel_modeset_readout_hw_state(dev);
15269
15270         /* HW state is read out, now we need to sanitize this mess. */
15271         for_each_intel_encoder(dev, encoder) {
15272                 intel_sanitize_encoder(encoder);
15273         }
15274
15275         for_each_pipe(dev_priv, pipe) {
15276                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15277                 intel_sanitize_crtc(crtc);
15278                 intel_dump_pipe_config(crtc, crtc->config,
15279                                        "[setup_hw_state]");
15280         }
15281
15282         intel_modeset_update_connector_atomic_state(dev);
15283
15284         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15285                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15286
15287                 if (!pll->on || pll->active)
15288                         continue;
15289
15290                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15291
15292                 pll->disable(dev_priv, pll);
15293                 pll->on = false;
15294         }
15295
15296         if (IS_VALLEYVIEW(dev))
15297                 vlv_wm_get_hw_state(dev);
15298         else if (IS_GEN9(dev))
15299                 skl_wm_get_hw_state(dev);
15300         else if (HAS_PCH_SPLIT(dev))
15301                 ilk_wm_get_hw_state(dev);
15302
15303         for_each_intel_crtc(dev, crtc) {
15304                 unsigned long put_domains;
15305
15306                 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15307                 if (WARN_ON(put_domains))
15308                         modeset_put_power_domains(dev_priv, put_domains);
15309         }
15310         intel_display_set_init_power(dev_priv, false);
15311 }
15312
15313 void intel_display_resume(struct drm_device *dev)
15314 {
15315         struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15316         struct intel_connector *conn;
15317         struct intel_plane *plane;
15318         struct drm_crtc *crtc;
15319         int ret;
15320
15321         if (!state)
15322                 return;
15323
15324         state->acquire_ctx = dev->mode_config.acquire_ctx;
15325
15326         /* preserve complete old state, including dpll */
15327         intel_atomic_get_shared_dpll_state(state);
15328
15329         for_each_crtc(dev, crtc) {
15330                 struct drm_crtc_state *crtc_state =
15331                         drm_atomic_get_crtc_state(state, crtc);
15332
15333                 ret = PTR_ERR_OR_ZERO(crtc_state);
15334                 if (ret)
15335                         goto err;
15336
15337                 /* force a restore */
15338                 crtc_state->mode_changed = true;
15339         }
15340
15341         for_each_intel_plane(dev, plane) {
15342                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15343                 if (ret)
15344                         goto err;
15345         }
15346
15347         for_each_intel_connector(dev, conn) {
15348                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15349                 if (ret)
15350                         goto err;
15351         }
15352
15353         intel_modeset_setup_hw_state(dev);
15354
15355         i915_redisable_vga(dev);
15356         ret = drm_atomic_commit(state);
15357         if (!ret)
15358                 return;
15359
15360 err:
15361         DRM_ERROR("Restoring old state failed with %i\n", ret);
15362         drm_atomic_state_free(state);
15363 }
15364
15365 void intel_modeset_gem_init(struct drm_device *dev)
15366 {
15367         struct drm_crtc *c;
15368         struct drm_i915_gem_object *obj;
15369         int ret;
15370
15371         mutex_lock(&dev->struct_mutex);
15372         intel_init_gt_powersave(dev);
15373         mutex_unlock(&dev->struct_mutex);
15374
15375         intel_modeset_init_hw(dev);
15376
15377         intel_setup_overlay(dev);
15378
15379         /*
15380          * Make sure any fbs we allocated at startup are properly
15381          * pinned & fenced.  When we do the allocation it's too early
15382          * for this.
15383          */
15384         for_each_crtc(dev, c) {
15385                 obj = intel_fb_obj(c->primary->fb);
15386                 if (obj == NULL)
15387                         continue;
15388
15389                 mutex_lock(&dev->struct_mutex);
15390                 ret = intel_pin_and_fence_fb_obj(c->primary,
15391                                                  c->primary->fb,
15392                                                  c->primary->state,
15393                                                  NULL, NULL);
15394                 mutex_unlock(&dev->struct_mutex);
15395                 if (ret) {
15396                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
15397                                   to_intel_crtc(c)->pipe);
15398                         drm_framebuffer_unreference(c->primary->fb);
15399                         c->primary->fb = NULL;
15400                         c->primary->crtc = c->primary->state->crtc = NULL;
15401                         update_state_fb(c->primary);
15402                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15403                 }
15404         }
15405
15406         intel_backlight_register(dev);
15407 }
15408
15409 void intel_connector_unregister(struct intel_connector *intel_connector)
15410 {
15411         struct drm_connector *connector = &intel_connector->base;
15412
15413         intel_panel_destroy_backlight(connector);
15414         drm_connector_unregister(connector);
15415 }
15416
15417 void intel_modeset_cleanup(struct drm_device *dev)
15418 {
15419         struct drm_i915_private *dev_priv = dev->dev_private;
15420         struct drm_connector *connector;
15421
15422         intel_disable_gt_powersave(dev);
15423
15424         intel_backlight_unregister(dev);
15425
15426         /*
15427          * Interrupts and polling as the first thing to avoid creating havoc.
15428          * Too much stuff here (turning of connectors, ...) would
15429          * experience fancy races otherwise.
15430          */
15431         intel_irq_uninstall(dev_priv);
15432
15433         /*
15434          * Due to the hpd irq storm handling the hotplug work can re-arm the
15435          * poll handlers. Hence disable polling after hpd handling is shut down.
15436          */
15437         drm_kms_helper_poll_fini(dev);
15438
15439         intel_unregister_dsm_handler();
15440
15441         intel_fbc_disable(dev_priv);
15442
15443         /* flush any delayed tasks or pending work */
15444         flush_scheduled_work();
15445
15446         /* destroy the backlight and sysfs files before encoders/connectors */
15447         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15448                 struct intel_connector *intel_connector;
15449
15450                 intel_connector = to_intel_connector(connector);
15451                 intel_connector->unregister(intel_connector);
15452         }
15453
15454         drm_mode_config_cleanup(dev);
15455
15456         intel_cleanup_overlay(dev);
15457
15458         mutex_lock(&dev->struct_mutex);
15459         intel_cleanup_gt_powersave(dev);
15460         mutex_unlock(&dev->struct_mutex);
15461 }
15462
15463 /*
15464  * Return which encoder is currently attached for connector.
15465  */
15466 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15467 {
15468         return &intel_attached_encoder(connector)->base;
15469 }
15470
15471 void intel_connector_attach_encoder(struct intel_connector *connector,
15472                                     struct intel_encoder *encoder)
15473 {
15474         connector->encoder = encoder;
15475         drm_mode_connector_attach_encoder(&connector->base,
15476                                           &encoder->base);
15477 }
15478
15479 /*
15480  * set vga decode state - true == enable VGA decode
15481  */
15482 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15483 {
15484         struct drm_i915_private *dev_priv = dev->dev_private;
15485         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15486         u16 gmch_ctrl;
15487
15488         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15489                 DRM_ERROR("failed to read control word\n");
15490                 return -EIO;
15491         }
15492
15493         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15494                 return 0;
15495
15496         if (state)
15497                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15498         else
15499                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15500
15501         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15502                 DRM_ERROR("failed to write control word\n");
15503                 return -EIO;
15504         }
15505
15506         return 0;
15507 }
15508
15509 struct intel_display_error_state {
15510
15511         u32 power_well_driver;
15512
15513         int num_transcoders;
15514
15515         struct intel_cursor_error_state {
15516                 u32 control;
15517                 u32 position;
15518                 u32 base;
15519                 u32 size;
15520         } cursor[I915_MAX_PIPES];
15521
15522         struct intel_pipe_error_state {
15523                 bool power_domain_on;
15524                 u32 source;
15525                 u32 stat;
15526         } pipe[I915_MAX_PIPES];
15527
15528         struct intel_plane_error_state {
15529                 u32 control;
15530                 u32 stride;
15531                 u32 size;
15532                 u32 pos;
15533                 u32 addr;
15534                 u32 surface;
15535                 u32 tile_offset;
15536         } plane[I915_MAX_PIPES];
15537
15538         struct intel_transcoder_error_state {
15539                 bool power_domain_on;
15540                 enum transcoder cpu_transcoder;
15541
15542                 u32 conf;
15543
15544                 u32 htotal;
15545                 u32 hblank;
15546                 u32 hsync;
15547                 u32 vtotal;
15548                 u32 vblank;
15549                 u32 vsync;
15550         } transcoder[4];
15551 };
15552
15553 struct intel_display_error_state *
15554 intel_display_capture_error_state(struct drm_device *dev)
15555 {
15556         struct drm_i915_private *dev_priv = dev->dev_private;
15557         struct intel_display_error_state *error;
15558         int transcoders[] = {
15559                 TRANSCODER_A,
15560                 TRANSCODER_B,
15561                 TRANSCODER_C,
15562                 TRANSCODER_EDP,
15563         };
15564         int i;
15565
15566         if (INTEL_INFO(dev)->num_pipes == 0)
15567                 return NULL;
15568
15569         error = kzalloc(sizeof(*error), GFP_ATOMIC);
15570         if (error == NULL)
15571                 return NULL;
15572
15573         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15574                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15575
15576         for_each_pipe(dev_priv, i) {
15577                 error->pipe[i].power_domain_on =
15578                         __intel_display_power_is_enabled(dev_priv,
15579                                                          POWER_DOMAIN_PIPE(i));
15580                 if (!error->pipe[i].power_domain_on)
15581                         continue;
15582
15583                 error->cursor[i].control = I915_READ(CURCNTR(i));
15584                 error->cursor[i].position = I915_READ(CURPOS(i));
15585                 error->cursor[i].base = I915_READ(CURBASE(i));
15586
15587                 error->plane[i].control = I915_READ(DSPCNTR(i));
15588                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15589                 if (INTEL_INFO(dev)->gen <= 3) {
15590                         error->plane[i].size = I915_READ(DSPSIZE(i));
15591                         error->plane[i].pos = I915_READ(DSPPOS(i));
15592                 }
15593                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15594                         error->plane[i].addr = I915_READ(DSPADDR(i));
15595                 if (INTEL_INFO(dev)->gen >= 4) {
15596                         error->plane[i].surface = I915_READ(DSPSURF(i));
15597                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15598                 }
15599
15600                 error->pipe[i].source = I915_READ(PIPESRC(i));
15601
15602                 if (HAS_GMCH_DISPLAY(dev))
15603                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
15604         }
15605
15606         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15607         if (HAS_DDI(dev_priv->dev))
15608                 error->num_transcoders++; /* Account for eDP. */
15609
15610         for (i = 0; i < error->num_transcoders; i++) {
15611                 enum transcoder cpu_transcoder = transcoders[i];
15612
15613                 error->transcoder[i].power_domain_on =
15614                         __intel_display_power_is_enabled(dev_priv,
15615                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15616                 if (!error->transcoder[i].power_domain_on)
15617                         continue;
15618
15619                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15620
15621                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15622                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15623                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15624                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15625                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15626                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15627                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15628         }
15629
15630         return error;
15631 }
15632
15633 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15634
15635 void
15636 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15637                                 struct drm_device *dev,
15638                                 struct intel_display_error_state *error)
15639 {
15640         struct drm_i915_private *dev_priv = dev->dev_private;
15641         int i;
15642
15643         if (!error)
15644                 return;
15645
15646         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15647         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15648                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15649                            error->power_well_driver);
15650         for_each_pipe(dev_priv, i) {
15651                 err_printf(m, "Pipe [%d]:\n", i);
15652                 err_printf(m, "  Power: %s\n",
15653                            error->pipe[i].power_domain_on ? "on" : "off");
15654                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
15655                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
15656
15657                 err_printf(m, "Plane [%d]:\n", i);
15658                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
15659                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
15660                 if (INTEL_INFO(dev)->gen <= 3) {
15661                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
15662                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
15663                 }
15664                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15665                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
15666                 if (INTEL_INFO(dev)->gen >= 4) {
15667                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
15668                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
15669                 }
15670
15671                 err_printf(m, "Cursor [%d]:\n", i);
15672                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
15673                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
15674                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
15675         }
15676
15677         for (i = 0; i < error->num_transcoders; i++) {
15678                 err_printf(m, "CPU transcoder: %c\n",
15679                            transcoder_name(error->transcoder[i].cpu_transcoder));
15680                 err_printf(m, "  Power: %s\n",
15681                            error->transcoder[i].power_domain_on ? "on" : "off");
15682                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
15683                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
15684                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
15685                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
15686                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
15687                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
15688                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
15689         }
15690 }
15691
15692 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15693 {
15694         struct intel_crtc *crtc;
15695
15696         for_each_intel_crtc(dev, crtc) {
15697                 struct intel_unpin_work *work;
15698
15699                 spin_lock_irq(&dev->event_lock);
15700
15701                 work = crtc->unpin_work;
15702
15703                 if (work && work->event &&
15704                     work->event->base.file_priv == file) {
15705                         kfree(work->event);
15706                         work->event = NULL;
15707                 }
15708
15709                 spin_unlock_irq(&dev->event_lock);
15710         }
15711 }