drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 static void intel_increase_pllclock(struct drm_crtc *crtc);
  45 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  46
  47 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  48                                 struct intel_crtc_config *pipe_config);
  49 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  50                                    struct intel_crtc_config *pipe_config);
  51
  52 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  53                           int x, int y, struct drm_framebuffer *old_fb);
  54 static int intel_framebuffer_init(struct drm_device *dev,
  55                                   struct intel_framebuffer *ifb,
  56                                   struct drm_mode_fb_cmd2 *mode_cmd,
  57                                   struct drm_i915_gem_object *obj);
  58
  59 typedef struct {
  60         int     min, max;
  61 } intel_range_t;
  62
  63 typedef struct {
  64         int     dot_limit;
  65         int     p2_slow, p2_fast;
  66 } intel_p2_t;
  67
  68 typedef struct intel_limit intel_limit_t;
  69 struct intel_limit {
  70         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  71         intel_p2_t          p2;
  72 };
  73
  74 int
  75 intel_pch_rawclk(struct drm_device *dev)
  76 {
  77         struct drm_i915_private *dev_priv = dev->dev_private;
  78
  79         WARN_ON(!HAS_PCH_SPLIT(dev));
  80
  81         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  82 }
  83
  84 static inline u32 /* units of 100MHz */
  85 intel_fdi_link_freq(struct drm_device *dev)
  86 {
  87         if (IS_GEN5(dev)) {
  88                 struct drm_i915_private *dev_priv = dev->dev_private;
  89                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  90         } else
  91                 return 27;
  92 }
  93
  94 static const intel_limit_t intel_limits_i8xx_dac = {
  95         .dot = { .min = 25000, .max = 350000 },
  96         .vco = { .min = 908000, .max = 1512000 },
  97         .n = { .min = 2, .max = 16 },
  98         .m = { .min = 96, .max = 140 },
  99         .m1 = { .min = 18, .max = 26 },
 100         .m2 = { .min = 6, .max = 16 },
 101         .p = { .min = 4, .max = 128 },
 102         .p1 = { .min = 2, .max = 33 },
 103         .p2 = { .dot_limit = 165000,
 104                 .p2_slow = 4, .p2_fast = 2 },
 105 };
 106
 107 static const intel_limit_t intel_limits_i8xx_dvo = {
 108         .dot = { .min = 25000, .max = 350000 },
 109         .vco = { .min = 908000, .max = 1512000 },
 110         .n = { .min = 2, .max = 16 },
 111         .m = { .min = 96, .max = 140 },
 112         .m1 = { .min = 18, .max = 26 },
 113         .m2 = { .min = 6, .max = 16 },
 114         .p = { .min = 4, .max = 128 },
 115         .p1 = { .min = 2, .max = 33 },
 116         .p2 = { .dot_limit = 165000,
 117                 .p2_slow = 4, .p2_fast = 4 },
 118 };
 119
 120 static const intel_limit_t intel_limits_i8xx_lvds = {
 121         .dot = { .min = 25000, .max = 350000 },
 122         .vco = { .min = 908000, .max = 1512000 },
 123         .n = { .min = 2, .max = 16 },
 124         .m = { .min = 96, .max = 140 },
 125         .m1 = { .min = 18, .max = 26 },
 126         .m2 = { .min = 6, .max = 16 },
 127         .p = { .min = 4, .max = 128 },
 128         .p1 = { .min = 1, .max = 6 },
 129         .p2 = { .dot_limit = 165000,
 130                 .p2_slow = 14, .p2_fast = 7 },
 131 };
 132
 133 static const intel_limit_t intel_limits_i9xx_sdvo = {
 134         .dot = { .min = 20000, .max = 400000 },
 135         .vco = { .min = 1400000, .max = 2800000 },
 136         .n = { .min = 1, .max = 6 },
 137         .m = { .min = 70, .max = 120 },
 138         .m1 = { .min = 8, .max = 18 },
 139         .m2 = { .min = 3, .max = 7 },
 140         .p = { .min = 5, .max = 80 },
 141         .p1 = { .min = 1, .max = 8 },
 142         .p2 = { .dot_limit = 200000,
 143                 .p2_slow = 10, .p2_fast = 5 },
 144 };
 145
 146 static const intel_limit_t intel_limits_i9xx_lvds = {
 147         .dot = { .min = 20000, .max = 400000 },
 148         .vco = { .min = 1400000, .max = 2800000 },
 149         .n = { .min = 1, .max = 6 },
 150         .m = { .min = 70, .max = 120 },
 151         .m1 = { .min = 8, .max = 18 },
 152         .m2 = { .min = 3, .max = 7 },
 153         .p = { .min = 7, .max = 98 },
 154         .p1 = { .min = 1, .max = 8 },
 155         .p2 = { .dot_limit = 112000,
 156                 .p2_slow = 14, .p2_fast = 7 },
 157 };
 158
 159
 160 static const intel_limit_t intel_limits_g4x_sdvo = {
 161         .dot = { .min = 25000, .max = 270000 },
 162         .vco = { .min = 1750000, .max = 3500000},
 163         .n = { .min = 1, .max = 4 },
 164         .m = { .min = 104, .max = 138 },
 165         .m1 = { .min = 17, .max = 23 },
 166         .m2 = { .min = 5, .max = 11 },
 167         .p = { .min = 10, .max = 30 },
 168         .p1 = { .min = 1, .max = 3},
 169         .p2 = { .dot_limit = 270000,
 170                 .p2_slow = 10,
 171                 .p2_fast = 10
 172         },
 173 };
 174
 175 static const intel_limit_t intel_limits_g4x_hdmi = {
 176         .dot = { .min = 22000, .max = 400000 },
 177         .vco = { .min = 1750000, .max = 3500000},
 178         .n = { .min = 1, .max = 4 },
 179         .m = { .min = 104, .max = 138 },
 180         .m1 = { .min = 16, .max = 23 },
 181         .m2 = { .min = 5, .max = 11 },
 182         .p = { .min = 5, .max = 80 },
 183         .p1 = { .min = 1, .max = 8},
 184         .p2 = { .dot_limit = 165000,
 185                 .p2_slow = 10, .p2_fast = 5 },
 186 };
 187
 188 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 189         .dot = { .min = 20000, .max = 115000 },
 190         .vco = { .min = 1750000, .max = 3500000 },
 191         .n = { .min = 1, .max = 3 },
 192         .m = { .min = 104, .max = 138 },
 193         .m1 = { .min = 17, .max = 23 },
 194         .m2 = { .min = 5, .max = 11 },
 195         .p = { .min = 28, .max = 112 },
 196         .p1 = { .min = 2, .max = 8 },
 197         .p2 = { .dot_limit = 0,
 198                 .p2_slow = 14, .p2_fast = 14
 199         },
 200 };
 201
 202 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 203         .dot = { .min = 80000, .max = 224000 },
 204         .vco = { .min = 1750000, .max = 3500000 },
 205         .n = { .min = 1, .max = 3 },
 206         .m = { .min = 104, .max = 138 },
 207         .m1 = { .min = 17, .max = 23 },
 208         .m2 = { .min = 5, .max = 11 },
 209         .p = { .min = 14, .max = 42 },
 210         .p1 = { .min = 2, .max = 6 },
 211         .p2 = { .dot_limit = 0,
 212                 .p2_slow = 7, .p2_fast = 7
 213         },
 214 };
 215
 216 static const intel_limit_t intel_limits_pineview_sdvo = {
 217         .dot = { .min = 20000, .max = 400000},
 218         .vco = { .min = 1700000, .max = 3500000 },
 219         /* Pineview's Ncounter is a ring counter */
 220         .n = { .min = 3, .max = 6 },
 221         .m = { .min = 2, .max = 256 },
 222         /* Pineview only has one combined m divider, which we treat as m2. */
 223         .m1 = { .min = 0, .max = 0 },
 224         .m2 = { .min = 0, .max = 254 },
 225         .p = { .min = 5, .max = 80 },
 226         .p1 = { .min = 1, .max = 8 },
 227         .p2 = { .dot_limit = 200000,
 228                 .p2_slow = 10, .p2_fast = 5 },
 229 };
 230
 231 static const intel_limit_t intel_limits_pineview_lvds = {
 232         .dot = { .min = 20000, .max = 400000 },
 233         .vco = { .min = 1700000, .max = 3500000 },
 234         .n = { .min = 3, .max = 6 },
 235         .m = { .min = 2, .max = 256 },
 236         .m1 = { .min = 0, .max = 0 },
 237         .m2 = { .min = 0, .max = 254 },
 238         .p = { .min = 7, .max = 112 },
 239         .p1 = { .min = 1, .max = 8 },
 240         .p2 = { .dot_limit = 112000,
 241                 .p2_slow = 14, .p2_fast = 14 },
 242 };
 243
 244 /* Ironlake / Sandybridge
 245  *
 246  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 247  * the range value for them is (actual_value - 2).
 248  */
 249 static const intel_limit_t intel_limits_ironlake_dac = {
 250         .dot = { .min = 25000, .max = 350000 },
 251         .vco = { .min = 1760000, .max = 3510000 },
 252         .n = { .min = 1, .max = 5 },
 253         .m = { .min = 79, .max = 127 },
 254         .m1 = { .min = 12, .max = 22 },
 255         .m2 = { .min = 5, .max = 9 },
 256         .p = { .min = 5, .max = 80 },
 257         .p1 = { .min = 1, .max = 8 },
 258         .p2 = { .dot_limit = 225000,
 259                 .p2_slow = 10, .p2_fast = 5 },
 260 };
 261
 262 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 263         .dot = { .min = 25000, .max = 350000 },
 264         .vco = { .min = 1760000, .max = 3510000 },
 265         .n = { .min = 1, .max = 3 },
 266         .m = { .min = 79, .max = 118 },
 267         .m1 = { .min = 12, .max = 22 },
 268         .m2 = { .min = 5, .max = 9 },
 269         .p = { .min = 28, .max = 112 },
 270         .p1 = { .min = 2, .max = 8 },
 271         .p2 = { .dot_limit = 225000,
 272                 .p2_slow = 14, .p2_fast = 14 },
 273 };
 274
 275 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 276         .dot = { .min = 25000, .max = 350000 },
 277         .vco = { .min = 1760000, .max = 3510000 },
 278         .n = { .min = 1, .max = 3 },
 279         .m = { .min = 79, .max = 127 },
 280         .m1 = { .min = 12, .max = 22 },
 281         .m2 = { .min = 5, .max = 9 },
 282         .p = { .min = 14, .max = 56 },
 283         .p1 = { .min = 2, .max = 8 },
 284         .p2 = { .dot_limit = 225000,
 285                 .p2_slow = 7, .p2_fast = 7 },
 286 };
 287
 288 /* LVDS 100mhz refclk limits. */
 289 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 290         .dot = { .min = 25000, .max = 350000 },
 291         .vco = { .min = 1760000, .max = 3510000 },
 292         .n = { .min = 1, .max = 2 },
 293         .m = { .min = 79, .max = 126 },
 294         .m1 = { .min = 12, .max = 22 },
 295         .m2 = { .min = 5, .max = 9 },
 296         .p = { .min = 28, .max = 112 },
 297         .p1 = { .min = 2, .max = 8 },
 298         .p2 = { .dot_limit = 225000,
 299                 .p2_slow = 14, .p2_fast = 14 },
 300 };
 301
 302 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 303         .dot = { .min = 25000, .max = 350000 },
 304         .vco = { .min = 1760000, .max = 3510000 },
 305         .n = { .min = 1, .max = 3 },
 306         .m = { .min = 79, .max = 126 },
 307         .m1 = { .min = 12, .max = 22 },
 308         .m2 = { .min = 5, .max = 9 },
 309         .p = { .min = 14, .max = 42 },
 310         .p1 = { .min = 2, .max = 6 },
 311         .p2 = { .dot_limit = 225000,
 312                 .p2_slow = 7, .p2_fast = 7 },
 313 };
 314
 315 static const intel_limit_t intel_limits_vlv = {
 316          /*
 317           * These are the data rate limits (measured in fast clocks)
 318           * since those are the strictest limits we have. The fast
 319           * clock and actual rate limits are more relaxed, so checking
 320           * them would make no difference.
 321           */
 322         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 323         .vco = { .min = 4000000, .max = 6000000 },
 324         .n = { .min = 1, .max = 7 },
 325         .m1 = { .min = 2, .max = 3 },
 326         .m2 = { .min = 11, .max = 156 },
 327         .p1 = { .min = 2, .max = 3 },
 328         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 329 };
 330
 331 static void vlv_clock(int refclk, intel_clock_t *clock)
 332 {
 333         clock->m = clock->m1 * clock->m2;
 334         clock->p = clock->p1 * clock->p2;
 335         if (WARN_ON(clock->n == 0 || clock->p == 0))
 336                 return;
 337         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 338         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 339 }
 340
 341 /**
 342  * Returns whether any output on the specified pipe is of the specified type
 343  */
 344 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 345 {
 346         struct drm_device *dev = crtc->dev;
 347         struct intel_encoder *encoder;
 348
 349         for_each_encoder_on_crtc(dev, crtc, encoder)
 350                 if (encoder->type == type)
 351                         return true;
 352
 353         return false;
 354 }
 355
 356 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 357                                                 int refclk)
 358 {
 359         struct drm_device *dev = crtc->dev;
 360         const intel_limit_t *limit;
 361
 362         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 363                 if (intel_is_dual_link_lvds(dev)) {
 364                         if (refclk == 100000)
 365                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 366                         else
 367                                 limit = &intel_limits_ironlake_dual_lvds;
 368                 } else {
 369                         if (refclk == 100000)
 370                                 limit = &intel_limits_ironlake_single_lvds_100m;
 371                         else
 372                                 limit = &intel_limits_ironlake_single_lvds;
 373                 }
 374         } else
 375                 limit = &intel_limits_ironlake_dac;
 376
 377         return limit;
 378 }
 379
 380 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 381 {
 382         struct drm_device *dev = crtc->dev;
 383         const intel_limit_t *limit;
 384
 385         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 386                 if (intel_is_dual_link_lvds(dev))
 387                         limit = &intel_limits_g4x_dual_channel_lvds;
 388                 else
 389                         limit = &intel_limits_g4x_single_channel_lvds;
 390         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 391                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 392                 limit = &intel_limits_g4x_hdmi;
 393         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 394                 limit = &intel_limits_g4x_sdvo;
 395         } else /* The option is for other outputs */
 396                 limit = &intel_limits_i9xx_sdvo;
 397
 398         return limit;
 399 }
 400
 401 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 402 {
 403         struct drm_device *dev = crtc->dev;
 404         const intel_limit_t *limit;
 405
 406         if (HAS_PCH_SPLIT(dev))
 407                 limit = intel_ironlake_limit(crtc, refclk);
 408         else if (IS_G4X(dev)) {
 409                 limit = intel_g4x_limit(crtc);
 410         } else if (IS_PINEVIEW(dev)) {
 411                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 412                         limit = &intel_limits_pineview_lvds;
 413                 else
 414                         limit = &intel_limits_pineview_sdvo;
 415         } else if (IS_VALLEYVIEW(dev)) {
 416                 limit = &intel_limits_vlv;
 417         } else if (!IS_GEN2(dev)) {
 418                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 419                         limit = &intel_limits_i9xx_lvds;
 420                 else
 421                         limit = &intel_limits_i9xx_sdvo;
 422         } else {
 423                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 424                         limit = &intel_limits_i8xx_lvds;
 425                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 426                         limit = &intel_limits_i8xx_dvo;
 427                 else
 428                         limit = &intel_limits_i8xx_dac;
 429         }
 430         return limit;
 431 }
 432
 433 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 434 static void pineview_clock(int refclk, intel_clock_t *clock)
 435 {
 436         clock->m = clock->m2 + 2;
 437         clock->p = clock->p1 * clock->p2;
 438         if (WARN_ON(clock->n == 0 || clock->p == 0))
 439                 return;
 440         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 441         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 442 }
 443
 444 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 445 {
 446         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 447 }
 448
 449 static void i9xx_clock(int refclk, intel_clock_t *clock)
 450 {
 451         clock->m = i9xx_dpll_compute_m(clock);
 452         clock->p = clock->p1 * clock->p2;
 453         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 454                 return;
 455         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 456         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 457 }
 458
 459 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 460 /**
 461  * Returns whether the given set of divisors are valid for a given refclk with
 462  * the given connectors.
 463  */
 464
 465 static bool intel_PLL_is_valid(struct drm_device *dev,
 466                                const intel_limit_t *limit,
 467                                const intel_clock_t *clock)
 468 {
 469         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 470                 INTELPllInvalid("n out of range\n");
 471         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 472                 INTELPllInvalid("p1 out of range\n");
 473         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 474                 INTELPllInvalid("m2 out of range\n");
 475         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 476                 INTELPllInvalid("m1 out of range\n");
 477
 478         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 479                 if (clock->m1 <= clock->m2)
 480                         INTELPllInvalid("m1 <= m2\n");
 481
 482         if (!IS_VALLEYVIEW(dev)) {
 483                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 484                         INTELPllInvalid("p out of range\n");
 485                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 486                         INTELPllInvalid("m out of range\n");
 487         }
 488
 489         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 490                 INTELPllInvalid("vco out of range\n");
 491         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 492          * connector, etc., rather than just a single range.
 493          */
 494         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 495                 INTELPllInvalid("dot out of range\n");
 496
 497         return true;
 498 }
 499
 500 static bool
 501 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 502                     int target, int refclk, intel_clock_t *match_clock,
 503                     intel_clock_t *best_clock)
 504 {
 505         struct drm_device *dev = crtc->dev;
 506         intel_clock_t clock;
 507         int err = target;
 508
 509         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 510                 /*
 511                  * For LVDS just rely on its current settings for dual-channel.
 512                  * We haven't figured out how to reliably set up different
 513                  * single/dual channel state, if we even can.
 514                  */
 515                 if (intel_is_dual_link_lvds(dev))
 516                         clock.p2 = limit->p2.p2_fast;
 517                 else
 518                         clock.p2 = limit->p2.p2_slow;
 519         } else {
 520                 if (target < limit->p2.dot_limit)
 521                         clock.p2 = limit->p2.p2_slow;
 522                 else
 523                         clock.p2 = limit->p2.p2_fast;
 524         }
 525
 526         memset(best_clock, 0, sizeof(*best_clock));
 527
 528         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 529              clock.m1++) {
 530                 for (clock.m2 = limit->m2.min;
 531                      clock.m2 <= limit->m2.max; clock.m2++) {
 532                         if (clock.m2 >= clock.m1)
 533                                 break;
 534                         for (clock.n = limit->n.min;
 535                              clock.n <= limit->n.max; clock.n++) {
 536                                 for (clock.p1 = limit->p1.min;
 537                                         clock.p1 <= limit->p1.max; clock.p1++) {
 538                                         int this_err;
 539
 540                                         i9xx_clock(refclk, &clock);
 541                                         if (!intel_PLL_is_valid(dev, limit,
 542                                                                 &clock))
 543                                                 continue;
 544                                         if (match_clock &&
 545                                             clock.p != match_clock->p)
 546                                                 continue;
 547
 548                                         this_err = abs(clock.dot - target);
 549                                         if (this_err < err) {
 550                                                 *best_clock = clock;
 551                                                 err = this_err;
 552                                         }
 553                                 }
 554                         }
 555                 }
 556         }
 557
 558         return (err != target);
 559 }
 560
 561 static bool
 562 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 563                    int target, int refclk, intel_clock_t *match_clock,
 564                    intel_clock_t *best_clock)
 565 {
 566         struct drm_device *dev = crtc->dev;
 567         intel_clock_t clock;
 568         int err = target;
 569
 570         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 571                 /*
 572                  * For LVDS just rely on its current settings for dual-channel.
 573                  * We haven't figured out how to reliably set up different
 574                  * single/dual channel state, if we even can.
 575                  */
 576                 if (intel_is_dual_link_lvds(dev))
 577                         clock.p2 = limit->p2.p2_fast;
 578                 else
 579                         clock.p2 = limit->p2.p2_slow;
 580         } else {
 581                 if (target < limit->p2.dot_limit)
 582                         clock.p2 = limit->p2.p2_slow;
 583                 else
 584                         clock.p2 = limit->p2.p2_fast;
 585         }
 586
 587         memset(best_clock, 0, sizeof(*best_clock));
 588
 589         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 590              clock.m1++) {
 591                 for (clock.m2 = limit->m2.min;
 592                      clock.m2 <= limit->m2.max; clock.m2++) {
 593                         for (clock.n = limit->n.min;
 594                              clock.n <= limit->n.max; clock.n++) {
 595                                 for (clock.p1 = limit->p1.min;
 596                                         clock.p1 <= limit->p1.max; clock.p1++) {
 597                                         int this_err;
 598
 599                                         pineview_clock(refclk, &clock);
 600                                         if (!intel_PLL_is_valid(dev, limit,
 601                                                                 &clock))
 602                                                 continue;
 603                                         if (match_clock &&
 604                                             clock.p != match_clock->p)
 605                                                 continue;
 606
 607                                         this_err = abs(clock.dot - target);
 608                                         if (this_err < err) {
 609                                                 *best_clock = clock;
 610                                                 err = this_err;
 611                                         }
 612                                 }
 613                         }
 614                 }
 615         }
 616
 617         return (err != target);
 618 }
 619
 620 static bool
 621 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 622                    int target, int refclk, intel_clock_t *match_clock,
 623                    intel_clock_t *best_clock)
 624 {
 625         struct drm_device *dev = crtc->dev;
 626         intel_clock_t clock;
 627         int max_n;
 628         bool found;
 629         /* approximately equals target * 0.00585 */
 630         int err_most = (target >> 8) + (target >> 9);
 631         found = false;
 632
 633         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 634                 if (intel_is_dual_link_lvds(dev))
 635                         clock.p2 = limit->p2.p2_fast;
 636                 else
 637                         clock.p2 = limit->p2.p2_slow;
 638         } else {
 639                 if (target < limit->p2.dot_limit)
 640                         clock.p2 = limit->p2.p2_slow;
 641                 else
 642                         clock.p2 = limit->p2.p2_fast;
 643         }
 644
 645         memset(best_clock, 0, sizeof(*best_clock));
 646         max_n = limit->n.max;
 647         /* based on hardware requirement, prefer smaller n to precision */
 648         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 649                 /* based on hardware requirement, prefere larger m1,m2 */
 650                 for (clock.m1 = limit->m1.max;
 651                      clock.m1 >= limit->m1.min; clock.m1--) {
 652                         for (clock.m2 = limit->m2.max;
 653                              clock.m2 >= limit->m2.min; clock.m2--) {
 654                                 for (clock.p1 = limit->p1.max;
 655                                      clock.p1 >= limit->p1.min; clock.p1--) {
 656                                         int this_err;
 657
 658                                         i9xx_clock(refclk, &clock);
 659                                         if (!intel_PLL_is_valid(dev, limit,
 660                                                                 &clock))
 661                                                 continue;
 662
 663                                         this_err = abs(clock.dot - target);
 664                                         if (this_err < err_most) {
 665                                                 *best_clock = clock;
 666                                                 err_most = this_err;
 667                                                 max_n = clock.n;
 668                                                 found = true;
 669                                         }
 670                                 }
 671                         }
 672                 }
 673         }
 674         return found;
 675 }
 676
 677 static bool
 678 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 679                    int target, int refclk, intel_clock_t *match_clock,
 680                    intel_clock_t *best_clock)
 681 {
 682         struct drm_device *dev = crtc->dev;
 683         intel_clock_t clock;
 684         unsigned int bestppm = 1000000;
 685         /* min update 19.2 MHz */
 686         int max_n = min(limit->n.max, refclk / 19200);
 687         bool found = false;
 688
 689         target *= 5; /* fast clock */
 690
 691         memset(best_clock, 0, sizeof(*best_clock));
 692
 693         /* based on hardware requirement, prefer smaller n to precision */
 694         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 695                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 696                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 697                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 698                                 clock.p = clock.p1 * clock.p2;
 699                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 700                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 701                                         unsigned int ppm, diff;
 702
 703                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 704                                                                      refclk * clock.m1);
 705
 706                                         vlv_clock(refclk, &clock);
 707
 708                                         if (!intel_PLL_is_valid(dev, limit,
 709                                                                 &clock))
 710                                                 continue;
 711
 712                                         diff = abs(clock.dot - target);
 713                                         ppm = div_u64(1000000ULL * diff, target);
 714
 715                                         if (ppm < 100 && clock.p > best_clock->p) {
 716                                                 bestppm = 0;
 717                                                 *best_clock = clock;
 718                                                 found = true;
 719                                         }
 720
 721                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 722                                                 bestppm = ppm;
 723                                                 *best_clock = clock;
 724                                                 found = true;
 725                                         }
 726                                 }
 727                         }
 728                 }
 729         }
 730
 731         return found;
 732 }
 733
 734 bool intel_crtc_active(struct drm_crtc *crtc)
 735 {
 736         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 737
 738         /* Be paranoid as we can arrive here with only partial
 739          * state retrieved from the hardware during setup.
 740          *
 741          * We can ditch the adjusted_mode.crtc_clock check as soon
 742          * as Haswell has gained clock readout/fastboot support.
 743          *
 744          * We can ditch the crtc->primary->fb check as soon as we can
 745          * properly reconstruct framebuffers.
 746          */
 747         return intel_crtc->active && crtc->primary->fb &&
 748                 intel_crtc->config.adjusted_mode.crtc_clock;
 749 }
 750
 751 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 752                                              enum pipe pipe)
 753 {
 754         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 755         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 756
 757         return intel_crtc->config.cpu_transcoder;
 758 }
 759
 760 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
 761 {
 762         struct drm_i915_private *dev_priv = dev->dev_private;
 763         u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
 764
 765         frame = I915_READ(frame_reg);
 766
 767         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 768                 WARN(1, "vblank wait timed out\n");
 769 }
 770
 771 /**
 772  * intel_wait_for_vblank - wait for vblank on a given pipe
 773  * @dev: drm device
 774  * @pipe: pipe to wait for
 775  *
 776  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 777  * mode setting code.
 778  */
 779 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 780 {
 781         struct drm_i915_private *dev_priv = dev->dev_private;
 782         int pipestat_reg = PIPESTAT(pipe);
 783
 784         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 785                 g4x_wait_for_vblank(dev, pipe);
 786                 return;
 787         }
 788
 789         /* Clear existing vblank status. Note this will clear any other
 790          * sticky status fields as well.
 791          *
 792          * This races with i915_driver_irq_handler() with the result
 793          * that either function could miss a vblank event.  Here it is not
 794          * fatal, as we will either wait upon the next vblank interrupt or
 795          * timeout.  Generally speaking intel_wait_for_vblank() is only
 796          * called during modeset at which time the GPU should be idle and
 797          * should *not* be performing page flips and thus not waiting on
 798          * vblanks...
 799          * Currently, the result of us stealing a vblank from the irq
 800          * handler is that a single frame will be skipped during swapbuffers.
 801          */
 802         I915_WRITE(pipestat_reg,
 803                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 804
 805         /* Wait for vblank interrupt bit to set */
 806         if (wait_for(I915_READ(pipestat_reg) &
 807                      PIPE_VBLANK_INTERRUPT_STATUS,
 808                      50))
 809                 DRM_DEBUG_KMS("vblank wait timed out\n");
 810 }
 811
 812 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 813 {
 814         struct drm_i915_private *dev_priv = dev->dev_private;
 815         u32 reg = PIPEDSL(pipe);
 816         u32 line1, line2;
 817         u32 line_mask;
 818
 819         if (IS_GEN2(dev))
 820                 line_mask = DSL_LINEMASK_GEN2;
 821         else
 822                 line_mask = DSL_LINEMASK_GEN3;
 823
 824         line1 = I915_READ(reg) & line_mask;
 825         mdelay(5);
 826         line2 = I915_READ(reg) & line_mask;
 827
 828         return line1 == line2;
 829 }
 830
 831 /*
 832  * intel_wait_for_pipe_off - wait for pipe to turn off
 833  * @dev: drm device
 834  * @pipe: pipe to wait for
 835  *
 836  * After disabling a pipe, we can't wait for vblank in the usual way,
 837  * spinning on the vblank interrupt status bit, since we won't actually
 838  * see an interrupt when the pipe is disabled.
 839  *
 840  * On Gen4 and above:
 841  *   wait for the pipe register state bit to turn off
 842  *
 843  * Otherwise:
 844  *   wait for the display line value to settle (it usually
 845  *   ends up stopping at the start of the next frame).
 846  *
 847  */
 848 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 849 {
 850         struct drm_i915_private *dev_priv = dev->dev_private;
 851         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 852                                                                       pipe);
 853
 854         if (INTEL_INFO(dev)->gen >= 4) {
 855                 int reg = PIPECONF(cpu_transcoder);
 856
 857                 /* Wait for the Pipe State to go off */
 858                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 859                              100))
 860                         WARN(1, "pipe_off wait timed out\n");
 861         } else {
 862                 /* Wait for the display line to settle */
 863                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 864                         WARN(1, "pipe_off wait timed out\n");
 865         }
 866 }
 867
 868 /*
 869  * ibx_digital_port_connected - is the specified port connected?
 870  * @dev_priv: i915 private structure
 871  * @port: the port to test
 872  *
 873  * Returns true if @port is connected, false otherwise.
 874  */
 875 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 876                                 struct intel_digital_port *port)
 877 {
 878         u32 bit;
 879
 880         if (HAS_PCH_IBX(dev_priv->dev)) {
 881                 switch(port->port) {
 882                 case PORT_B:
 883                         bit = SDE_PORTB_HOTPLUG;
 884                         break;
 885                 case PORT_C:
 886                         bit = SDE_PORTC_HOTPLUG;
 887                         break;
 888                 case PORT_D:
 889                         bit = SDE_PORTD_HOTPLUG;
 890                         break;
 891                 default:
 892                         return true;
 893                 }
 894         } else {
 895                 switch(port->port) {
 896                 case PORT_B:
 897                         bit = SDE_PORTB_HOTPLUG_CPT;
 898                         break;
 899                 case PORT_C:
 900                         bit = SDE_PORTC_HOTPLUG_CPT;
 901                         break;
 902                 case PORT_D:
 903                         bit = SDE_PORTD_HOTPLUG_CPT;
 904                         break;
 905                 default:
 906                         return true;
 907                 }
 908         }
 909
 910         return I915_READ(SDEISR) & bit;
 911 }
 912
 913 static const char *state_string(bool enabled)
 914 {
 915         return enabled ? "on" : "off";
 916 }
 917
 918 /* Only for pre-ILK configs */
 919 void assert_pll(struct drm_i915_private *dev_priv,
 920                 enum pipe pipe, bool state)
 921 {
 922         int reg;
 923         u32 val;
 924         bool cur_state;
 925
 926         reg = DPLL(pipe);
 927         val = I915_READ(reg);
 928         cur_state = !!(val & DPLL_VCO_ENABLE);
 929         WARN(cur_state != state,
 930              "PLL state assertion failure (expected %s, current %s)\n",
 931              state_string(state), state_string(cur_state));
 932 }
 933
 934 /* XXX: the dsi pll is shared between MIPI DSI ports */
 935 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
 936 {
 937         u32 val;
 938         bool cur_state;
 939
 940         mutex_lock(&dev_priv->dpio_lock);
 941         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
 942         mutex_unlock(&dev_priv->dpio_lock);
 943
 944         cur_state = val & DSI_PLL_VCO_EN;
 945         WARN(cur_state != state,
 946              "DSI PLL state assertion failure (expected %s, current %s)\n",
 947              state_string(state), state_string(cur_state));
 948 }
 949 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
 950 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
 951
 952 struct intel_shared_dpll *
 953 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 954 {
 955         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 956
 957         if (crtc->config.shared_dpll < 0)
 958                 return NULL;
 959
 960         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
 961 }
 962
 963 /* For ILK+ */
 964 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 965                         struct intel_shared_dpll *pll,
 966                         bool state)
 967 {
 968         bool cur_state;
 969         struct intel_dpll_hw_state hw_state;
 970
 971         if (HAS_PCH_LPT(dev_priv->dev)) {
 972                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 973                 return;
 974         }
 975
 976         if (WARN (!pll,
 977                   "asserting DPLL %s with no DPLL\n", state_string(state)))
 978                 return;
 979
 980         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
 981         WARN(cur_state != state,
 982              "%s assertion failure (expected %s, current %s)\n",
 983              pll->name, state_string(state), state_string(cur_state));
 984 }
 985
 986 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 987                           enum pipe pipe, bool state)
 988 {
 989         int reg;
 990         u32 val;
 991         bool cur_state;
 992         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 993                                                                       pipe);
 994
 995         if (HAS_DDI(dev_priv->dev)) {
 996                 /* DDI does not have a specific FDI_TX register */
 997                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 998                 val = I915_READ(reg);
 999                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1000         } else {
1001                 reg = FDI_TX_CTL(pipe);
1002                 val = I915_READ(reg);
1003                 cur_state = !!(val & FDI_TX_ENABLE);
1004         }
1005         WARN(cur_state != state,
1006              "FDI TX state assertion failure (expected %s, current %s)\n",
1007              state_string(state), state_string(cur_state));
1008 }
1009 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1010 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1011
1012 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1013                           enum pipe pipe, bool state)
1014 {
1015         int reg;
1016         u32 val;
1017         bool cur_state;
1018
1019         reg = FDI_RX_CTL(pipe);
1020         val = I915_READ(reg);
1021         cur_state = !!(val & FDI_RX_ENABLE);
1022         WARN(cur_state != state,
1023              "FDI RX state assertion failure (expected %s, current %s)\n",
1024              state_string(state), state_string(cur_state));
1025 }
1026 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1027 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1028
1029 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1030                                       enum pipe pipe)
1031 {
1032         int reg;
1033         u32 val;
1034
1035         /* ILK FDI PLL is always enabled */
1036         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1037                 return;
1038
1039         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1040         if (HAS_DDI(dev_priv->dev))
1041                 return;
1042
1043         reg = FDI_TX_CTL(pipe);
1044         val = I915_READ(reg);
1045         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1046 }
1047
1048 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1049                        enum pipe pipe, bool state)
1050 {
1051         int reg;
1052         u32 val;
1053         bool cur_state;
1054
1055         reg = FDI_RX_CTL(pipe);
1056         val = I915_READ(reg);
1057         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1058         WARN(cur_state != state,
1059              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1060              state_string(state), state_string(cur_state));
1061 }
1062
1063 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1064                                   enum pipe pipe)
1065 {
1066         int pp_reg, lvds_reg;
1067         u32 val;
1068         enum pipe panel_pipe = PIPE_A;
1069         bool locked = true;
1070
1071         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1072                 pp_reg = PCH_PP_CONTROL;
1073                 lvds_reg = PCH_LVDS;
1074         } else {
1075                 pp_reg = PP_CONTROL;
1076                 lvds_reg = LVDS;
1077         }
1078
1079         val = I915_READ(pp_reg);
1080         if (!(val & PANEL_POWER_ON) ||
1081             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1082                 locked = false;
1083
1084         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1085                 panel_pipe = PIPE_B;
1086
1087         WARN(panel_pipe == pipe && locked,
1088              "panel assertion failure, pipe %c regs locked\n",
1089              pipe_name(pipe));
1090 }
1091
1092 static void assert_cursor(struct drm_i915_private *dev_priv,
1093                           enum pipe pipe, bool state)
1094 {
1095         struct drm_device *dev = dev_priv->dev;
1096         bool cur_state;
1097
1098         if (IS_845G(dev) || IS_I865G(dev))
1099                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1100         else if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev))
1101                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1102         else
1103                 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1104
1105         WARN(cur_state != state,
1106              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1107              pipe_name(pipe), state_string(state), state_string(cur_state));
1108 }
1109 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1110 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1111
1112 void assert_pipe(struct drm_i915_private *dev_priv,
1113                  enum pipe pipe, bool state)
1114 {
1115         int reg;
1116         u32 val;
1117         bool cur_state;
1118         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1119                                                                       pipe);
1120
1121         /* if we need the pipe A quirk it must be always on */
1122         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1123                 state = true;
1124
1125         if (!intel_display_power_enabled(dev_priv,
1126                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1127                 cur_state = false;
1128         } else {
1129                 reg = PIPECONF(cpu_transcoder);
1130                 val = I915_READ(reg);
1131                 cur_state = !!(val & PIPECONF_ENABLE);
1132         }
1133
1134         WARN(cur_state != state,
1135              "pipe %c assertion failure (expected %s, current %s)\n",
1136              pipe_name(pipe), state_string(state), state_string(cur_state));
1137 }
1138
1139 static void assert_plane(struct drm_i915_private *dev_priv,
1140                          enum plane plane, bool state)
1141 {
1142         int reg;
1143         u32 val;
1144         bool cur_state;
1145
1146         reg = DSPCNTR(plane);
1147         val = I915_READ(reg);
1148         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1149         WARN(cur_state != state,
1150              "plane %c assertion failure (expected %s, current %s)\n",
1151              plane_name(plane), state_string(state), state_string(cur_state));
1152 }
1153
1154 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1155 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1156
1157 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1158                                    enum pipe pipe)
1159 {
1160         struct drm_device *dev = dev_priv->dev;
1161         int reg, i;
1162         u32 val;
1163         int cur_pipe;
1164
1165         /* Primary planes are fixed to pipes on gen4+ */
1166         if (INTEL_INFO(dev)->gen >= 4) {
1167                 reg = DSPCNTR(pipe);
1168                 val = I915_READ(reg);
1169                 WARN(val & DISPLAY_PLANE_ENABLE,
1170                      "plane %c assertion failure, should be disabled but not\n",
1171                      plane_name(pipe));
1172                 return;
1173         }
1174
1175         /* Need to check both planes against the pipe */
1176         for_each_pipe(i) {
1177                 reg = DSPCNTR(i);
1178                 val = I915_READ(reg);
1179                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1180                         DISPPLANE_SEL_PIPE_SHIFT;
1181                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1182                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1183                      plane_name(i), pipe_name(pipe));
1184         }
1185 }
1186
1187 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1188                                     enum pipe pipe)
1189 {
1190         struct drm_device *dev = dev_priv->dev;
1191         int reg, sprite;
1192         u32 val;
1193
1194         if (IS_VALLEYVIEW(dev)) {
1195                 for_each_sprite(pipe, sprite) {
1196                         reg = SPCNTR(pipe, sprite);
1197                         val = I915_READ(reg);
1198                         WARN(val & SP_ENABLE,
1199                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1200                              sprite_name(pipe, sprite), pipe_name(pipe));
1201                 }
1202         } else if (INTEL_INFO(dev)->gen >= 7) {
1203                 reg = SPRCTL(pipe);
1204                 val = I915_READ(reg);
1205                 WARN(val & SPRITE_ENABLE,
1206                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1207                      plane_name(pipe), pipe_name(pipe));
1208         } else if (INTEL_INFO(dev)->gen >= 5) {
1209                 reg = DVSCNTR(pipe);
1210                 val = I915_READ(reg);
1211                 WARN(val & DVS_ENABLE,
1212                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1213                      plane_name(pipe), pipe_name(pipe));
1214         }
1215 }
1216
1217 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1218 {
1219         u32 val;
1220         bool enabled;
1221
1222         WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1223
1224         val = I915_READ(PCH_DREF_CONTROL);
1225         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1226                             DREF_SUPERSPREAD_SOURCE_MASK));
1227         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1228 }
1229
1230 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1231                                            enum pipe pipe)
1232 {
1233         int reg;
1234         u32 val;
1235         bool enabled;
1236
1237         reg = PCH_TRANSCONF(pipe);
1238         val = I915_READ(reg);
1239         enabled = !!(val & TRANS_ENABLE);
1240         WARN(enabled,
1241              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1242              pipe_name(pipe));
1243 }
1244
1245 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1246                             enum pipe pipe, u32 port_sel, u32 val)
1247 {
1248         if ((val & DP_PORT_EN) == 0)
1249                 return false;
1250
1251         if (HAS_PCH_CPT(dev_priv->dev)) {
1252                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1253                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1254                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1255                         return false;
1256         } else {
1257                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1258                         return false;
1259         }
1260         return true;
1261 }
1262
1263 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1264                               enum pipe pipe, u32 val)
1265 {
1266         if ((val & SDVO_ENABLE) == 0)
1267                 return false;
1268
1269         if (HAS_PCH_CPT(dev_priv->dev)) {
1270                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1271                         return false;
1272         } else {
1273                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1274                         return false;
1275         }
1276         return true;
1277 }
1278
1279 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1280                               enum pipe pipe, u32 val)
1281 {
1282         if ((val & LVDS_PORT_EN) == 0)
1283                 return false;
1284
1285         if (HAS_PCH_CPT(dev_priv->dev)) {
1286                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1287                         return false;
1288         } else {
1289                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1290                         return false;
1291         }
1292         return true;
1293 }
1294
1295 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1296                               enum pipe pipe, u32 val)
1297 {
1298         if ((val & ADPA_DAC_ENABLE) == 0)
1299                 return false;
1300         if (HAS_PCH_CPT(dev_priv->dev)) {
1301                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1302                         return false;
1303         } else {
1304                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1305                         return false;
1306         }
1307         return true;
1308 }
1309
1310 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1311                                    enum pipe pipe, int reg, u32 port_sel)
1312 {
1313         u32 val = I915_READ(reg);
1314         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1315              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1316              reg, pipe_name(pipe));
1317
1318         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1319              && (val & DP_PIPEB_SELECT),
1320              "IBX PCH dp port still using transcoder B\n");
1321 }
1322
1323 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1324                                      enum pipe pipe, int reg)
1325 {
1326         u32 val = I915_READ(reg);
1327         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1328              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1329              reg, pipe_name(pipe));
1330
1331         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1332              && (val & SDVO_PIPE_B_SELECT),
1333              "IBX PCH hdmi port still using transcoder B\n");
1334 }
1335
1336 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1337                                       enum pipe pipe)
1338 {
1339         int reg;
1340         u32 val;
1341
1342         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1343         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1344         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1345
1346         reg = PCH_ADPA;
1347         val = I915_READ(reg);
1348         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1349              "PCH VGA enabled on transcoder %c, should be disabled\n",
1350              pipe_name(pipe));
1351
1352         reg = PCH_LVDS;
1353         val = I915_READ(reg);
1354         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1355              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1356              pipe_name(pipe));
1357
1358         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1359         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1360         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1361 }
1362
1363 static void intel_init_dpio(struct drm_device *dev)
1364 {
1365         struct drm_i915_private *dev_priv = dev->dev_private;
1366
1367         if (!IS_VALLEYVIEW(dev))
1368                 return;
1369
1370         DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1371 }
1372
1373 static void intel_reset_dpio(struct drm_device *dev)
1374 {
1375         struct drm_i915_private *dev_priv = dev->dev_private;
1376
1377         if (!IS_VALLEYVIEW(dev))
1378                 return;
1379
1380         /*
1381          * Enable the CRI clock source so we can get at the display and the
1382          * reference clock for VGA hotplug / manual detection.
1383          */
1384         I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
1385                    DPLL_REFA_CLK_ENABLE_VLV |
1386                    DPLL_INTEGRATED_CRI_CLK_VLV);
1387
1388         /*
1389          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1390          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1391          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1392          *   b. The other bits such as sfr settings / modesel may all be set
1393          *      to 0.
1394          *
1395          * This should only be done on init and resume from S3 with both
1396          * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1397          */
1398         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1399 }
1400
1401 static void vlv_enable_pll(struct intel_crtc *crtc)
1402 {
1403         struct drm_device *dev = crtc->base.dev;
1404         struct drm_i915_private *dev_priv = dev->dev_private;
1405         int reg = DPLL(crtc->pipe);
1406         u32 dpll = crtc->config.dpll_hw_state.dpll;
1407
1408         assert_pipe_disabled(dev_priv, crtc->pipe);
1409
1410         /* No really, not for ILK+ */
1411         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1412
1413         /* PLL is protected by panel, make sure we can write it */
1414         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1415                 assert_panel_unlocked(dev_priv, crtc->pipe);
1416
1417         I915_WRITE(reg, dpll);
1418         POSTING_READ(reg);
1419         udelay(150);
1420
1421         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1422                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1423
1424         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1425         POSTING_READ(DPLL_MD(crtc->pipe));
1426
1427         /* We do this three times for luck */
1428         I915_WRITE(reg, dpll);
1429         POSTING_READ(reg);
1430         udelay(150); /* wait for warmup */
1431         I915_WRITE(reg, dpll);
1432         POSTING_READ(reg);
1433         udelay(150); /* wait for warmup */
1434         I915_WRITE(reg, dpll);
1435         POSTING_READ(reg);
1436         udelay(150); /* wait for warmup */
1437 }
1438
1439 static void i9xx_enable_pll(struct intel_crtc *crtc)
1440 {
1441         struct drm_device *dev = crtc->base.dev;
1442         struct drm_i915_private *dev_priv = dev->dev_private;
1443         int reg = DPLL(crtc->pipe);
1444         u32 dpll = crtc->config.dpll_hw_state.dpll;
1445
1446         assert_pipe_disabled(dev_priv, crtc->pipe);
1447
1448         /* No really, not for ILK+ */
1449         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1450
1451         /* PLL is protected by panel, make sure we can write it */
1452         if (IS_MOBILE(dev) && !IS_I830(dev))
1453                 assert_panel_unlocked(dev_priv, crtc->pipe);
1454
1455         I915_WRITE(reg, dpll);
1456
1457         /* Wait for the clocks to stabilize. */
1458         POSTING_READ(reg);
1459         udelay(150);
1460
1461         if (INTEL_INFO(dev)->gen >= 4) {
1462                 I915_WRITE(DPLL_MD(crtc->pipe),
1463                            crtc->config.dpll_hw_state.dpll_md);
1464         } else {
1465                 /* The pixel multiplier can only be updated once the
1466                  * DPLL is enabled and the clocks are stable.
1467                  *
1468                  * So write it again.
1469                  */
1470                 I915_WRITE(reg, dpll);
1471         }
1472
1473         /* We do this three times for luck */
1474         I915_WRITE(reg, dpll);
1475         POSTING_READ(reg);
1476         udelay(150); /* wait for warmup */
1477         I915_WRITE(reg, dpll);
1478         POSTING_READ(reg);
1479         udelay(150); /* wait for warmup */
1480         I915_WRITE(reg, dpll);
1481         POSTING_READ(reg);
1482         udelay(150); /* wait for warmup */
1483 }
1484
1485 /**
1486  * i9xx_disable_pll - disable a PLL
1487  * @dev_priv: i915 private structure
1488  * @pipe: pipe PLL to disable
1489  *
1490  * Disable the PLL for @pipe, making sure the pipe is off first.
1491  *
1492  * Note!  This is for pre-ILK only.
1493  */
1494 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1495 {
1496         /* Don't disable pipe A or pipe A PLLs if needed */
1497         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1498                 return;
1499
1500         /* Make sure the pipe isn't still relying on us */
1501         assert_pipe_disabled(dev_priv, pipe);
1502
1503         I915_WRITE(DPLL(pipe), 0);
1504         POSTING_READ(DPLL(pipe));
1505 }
1506
1507 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1508 {
1509         u32 val = 0;
1510
1511         /* Make sure the pipe isn't still relying on us */
1512         assert_pipe_disabled(dev_priv, pipe);
1513
1514         /*
1515          * Leave integrated clock source and reference clock enabled for pipe B.
1516          * The latter is needed for VGA hotplug / manual detection.
1517          */
1518         if (pipe == PIPE_B)
1519                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1520         I915_WRITE(DPLL(pipe), val);
1521         POSTING_READ(DPLL(pipe));
1522 }
1523
1524 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1525                 struct intel_digital_port *dport)
1526 {
1527         u32 port_mask;
1528
1529         switch (dport->port) {
1530         case PORT_B:
1531                 port_mask = DPLL_PORTB_READY_MASK;
1532                 break;
1533         case PORT_C:
1534                 port_mask = DPLL_PORTC_READY_MASK;
1535                 break;
1536         default:
1537                 BUG();
1538         }
1539
1540         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1541                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1542                      port_name(dport->port), I915_READ(DPLL(0)));
1543 }
1544
1545 /**
1546  * ironlake_enable_shared_dpll - enable PCH PLL
1547  * @dev_priv: i915 private structure
1548  * @pipe: pipe PLL to enable
1549  *
1550  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1551  * drives the transcoder clock.
1552  */
1553 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1554 {
1555         struct drm_device *dev = crtc->base.dev;
1556         struct drm_i915_private *dev_priv = dev->dev_private;
1557         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1558
1559         /* PCH PLLs only available on ILK, SNB and IVB */
1560         BUG_ON(INTEL_INFO(dev)->gen < 5);
1561         if (WARN_ON(pll == NULL))
1562                 return;
1563
1564         if (WARN_ON(pll->refcount == 0))
1565                 return;
1566
1567         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1568                       pll->name, pll->active, pll->on,
1569                       crtc->base.base.id);
1570
1571         if (pll->active++) {
1572                 WARN_ON(!pll->on);
1573                 assert_shared_dpll_enabled(dev_priv, pll);
1574                 return;
1575         }
1576         WARN_ON(pll->on);
1577
1578         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1579         pll->enable(dev_priv, pll);
1580         pll->on = true;
1581 }
1582
1583 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1584 {
1585         struct drm_device *dev = crtc->base.dev;
1586         struct drm_i915_private *dev_priv = dev->dev_private;
1587         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1588
1589         /* PCH only available on ILK+ */
1590         BUG_ON(INTEL_INFO(dev)->gen < 5);
1591         if (WARN_ON(pll == NULL))
1592                return;
1593
1594         if (WARN_ON(pll->refcount == 0))
1595                 return;
1596
1597         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1598                       pll->name, pll->active, pll->on,
1599                       crtc->base.base.id);
1600
1601         if (WARN_ON(pll->active == 0)) {
1602                 assert_shared_dpll_disabled(dev_priv, pll);
1603                 return;
1604         }
1605
1606         assert_shared_dpll_enabled(dev_priv, pll);
1607         WARN_ON(!pll->on);
1608         if (--pll->active)
1609                 return;
1610
1611         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1612         pll->disable(dev_priv, pll);
1613         pll->on = false;
1614 }
1615
1616 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1617                                            enum pipe pipe)
1618 {
1619         struct drm_device *dev = dev_priv->dev;
1620         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1621         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1622         uint32_t reg, val, pipeconf_val;
1623
1624         /* PCH only available on ILK+ */
1625         BUG_ON(INTEL_INFO(dev)->gen < 5);
1626
1627         /* Make sure PCH DPLL is enabled */
1628         assert_shared_dpll_enabled(dev_priv,
1629                                    intel_crtc_to_shared_dpll(intel_crtc));
1630
1631         /* FDI must be feeding us bits for PCH ports */
1632         assert_fdi_tx_enabled(dev_priv, pipe);
1633         assert_fdi_rx_enabled(dev_priv, pipe);
1634
1635         if (HAS_PCH_CPT(dev)) {
1636                 /* Workaround: Set the timing override bit before enabling the
1637                  * pch transcoder. */
1638                 reg = TRANS_CHICKEN2(pipe);
1639                 val = I915_READ(reg);
1640                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1641                 I915_WRITE(reg, val);
1642         }
1643
1644         reg = PCH_TRANSCONF(pipe);
1645         val = I915_READ(reg);
1646         pipeconf_val = I915_READ(PIPECONF(pipe));
1647
1648         if (HAS_PCH_IBX(dev_priv->dev)) {
1649                 /*
1650                  * make the BPC in transcoder be consistent with
1651                  * that in pipeconf reg.
1652                  */
1653                 val &= ~PIPECONF_BPC_MASK;
1654                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1655         }
1656
1657         val &= ~TRANS_INTERLACE_MASK;
1658         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1659                 if (HAS_PCH_IBX(dev_priv->dev) &&
1660                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1661                         val |= TRANS_LEGACY_INTERLACED_ILK;
1662                 else
1663                         val |= TRANS_INTERLACED;
1664         else
1665                 val |= TRANS_PROGRESSIVE;
1666
1667         I915_WRITE(reg, val | TRANS_ENABLE);
1668         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1669                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1670 }
1671
1672 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1673                                       enum transcoder cpu_transcoder)
1674 {
1675         u32 val, pipeconf_val;
1676
1677         /* PCH only available on ILK+ */
1678         BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1679
1680         /* FDI must be feeding us bits for PCH ports */
1681         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1682         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1683
1684         /* Workaround: set timing override bit. */
1685         val = I915_READ(_TRANSA_CHICKEN2);
1686         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1687         I915_WRITE(_TRANSA_CHICKEN2, val);
1688
1689         val = TRANS_ENABLE;
1690         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1691
1692         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1693             PIPECONF_INTERLACED_ILK)
1694                 val |= TRANS_INTERLACED;
1695         else
1696                 val |= TRANS_PROGRESSIVE;
1697
1698         I915_WRITE(LPT_TRANSCONF, val);
1699         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1700                 DRM_ERROR("Failed to enable PCH transcoder\n");
1701 }
1702
1703 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1704                                             enum pipe pipe)
1705 {
1706         struct drm_device *dev = dev_priv->dev;
1707         uint32_t reg, val;
1708
1709         /* FDI relies on the transcoder */
1710         assert_fdi_tx_disabled(dev_priv, pipe);
1711         assert_fdi_rx_disabled(dev_priv, pipe);
1712
1713         /* Ports must be off as well */
1714         assert_pch_ports_disabled(dev_priv, pipe);
1715
1716         reg = PCH_TRANSCONF(pipe);
1717         val = I915_READ(reg);
1718         val &= ~TRANS_ENABLE;
1719         I915_WRITE(reg, val);
1720         /* wait for PCH transcoder off, transcoder state */
1721         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1722                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1723
1724         if (!HAS_PCH_IBX(dev)) {
1725                 /* Workaround: Clear the timing override chicken bit again. */
1726                 reg = TRANS_CHICKEN2(pipe);
1727                 val = I915_READ(reg);
1728                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1729                 I915_WRITE(reg, val);
1730         }
1731 }
1732
1733 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1734 {
1735         u32 val;
1736
1737         val = I915_READ(LPT_TRANSCONF);
1738         val &= ~TRANS_ENABLE;
1739         I915_WRITE(LPT_TRANSCONF, val);
1740         /* wait for PCH transcoder off, transcoder state */
1741         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1742                 DRM_ERROR("Failed to disable PCH transcoder\n");
1743
1744         /* Workaround: clear timing override bit. */
1745         val = I915_READ(_TRANSA_CHICKEN2);
1746         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1747         I915_WRITE(_TRANSA_CHICKEN2, val);
1748 }
1749
1750 /**
1751  * intel_enable_pipe - enable a pipe, asserting requirements
1752  * @crtc: crtc responsible for the pipe
1753  *
1754  * Enable @crtc's pipe, making sure that various hardware specific requirements
1755  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1756  */
1757 static void intel_enable_pipe(struct intel_crtc *crtc)
1758 {
1759         struct drm_device *dev = crtc->base.dev;
1760         struct drm_i915_private *dev_priv = dev->dev_private;
1761         enum pipe pipe = crtc->pipe;
1762         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1763                                                                       pipe);
1764         enum pipe pch_transcoder;
1765         int reg;
1766         u32 val;
1767
1768         assert_planes_disabled(dev_priv, pipe);
1769         assert_cursor_disabled(dev_priv, pipe);
1770         assert_sprites_disabled(dev_priv, pipe);
1771
1772         if (HAS_PCH_LPT(dev_priv->dev))
1773                 pch_transcoder = TRANSCODER_A;
1774         else
1775                 pch_transcoder = pipe;
1776
1777         /*
1778          * A pipe without a PLL won't actually be able to drive bits from
1779          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1780          * need the check.
1781          */
1782         if (!HAS_PCH_SPLIT(dev_priv->dev))
1783                 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
1784                         assert_dsi_pll_enabled(dev_priv);
1785                 else
1786                         assert_pll_enabled(dev_priv, pipe);
1787         else {
1788                 if (crtc->config.has_pch_encoder) {
1789                         /* if driving the PCH, we need FDI enabled */
1790                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1791                         assert_fdi_tx_pll_enabled(dev_priv,
1792                                                   (enum pipe) cpu_transcoder);
1793                 }
1794                 /* FIXME: assert CPU port conditions for SNB+ */
1795         }
1796
1797         reg = PIPECONF(cpu_transcoder);
1798         val = I915_READ(reg);
1799         if (val & PIPECONF_ENABLE) {
1800                 WARN_ON(!(pipe == PIPE_A &&
1801                           dev_priv->quirks & QUIRK_PIPEA_FORCE));
1802                 return;
1803         }
1804
1805         I915_WRITE(reg, val | PIPECONF_ENABLE);
1806         POSTING_READ(reg);
1807 }
1808
1809 /**
1810  * intel_disable_pipe - disable a pipe, asserting requirements
1811  * @dev_priv: i915 private structure
1812  * @pipe: pipe to disable
1813  *
1814  * Disable @pipe, making sure that various hardware specific requirements
1815  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1816  *
1817  * @pipe should be %PIPE_A or %PIPE_B.
1818  *
1819  * Will wait until the pipe has shut down before returning.
1820  */
1821 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1822                                enum pipe pipe)
1823 {
1824         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1825                                                                       pipe);
1826         int reg;
1827         u32 val;
1828
1829         /*
1830          * Make sure planes won't keep trying to pump pixels to us,
1831          * or we might hang the display.
1832          */
1833         assert_planes_disabled(dev_priv, pipe);
1834         assert_cursor_disabled(dev_priv, pipe);
1835         assert_sprites_disabled(dev_priv, pipe);
1836
1837         /* Don't disable pipe A or pipe A PLLs if needed */
1838         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1839                 return;
1840
1841         reg = PIPECONF(cpu_transcoder);
1842         val = I915_READ(reg);
1843         if ((val & PIPECONF_ENABLE) == 0)
1844                 return;
1845
1846         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1847         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1848 }
1849
1850 /*
1851  * Plane regs are double buffered, going from enabled->disabled needs a
1852  * trigger in order to latch.  The display address reg provides this.
1853  */
1854 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1855                                enum plane plane)
1856 {
1857         struct drm_device *dev = dev_priv->dev;
1858         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1859
1860         I915_WRITE(reg, I915_READ(reg));
1861         POSTING_READ(reg);
1862 }
1863
1864 /**
1865  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
1866  * @dev_priv: i915 private structure
1867  * @plane: plane to enable
1868  * @pipe: pipe being fed
1869  *
1870  * Enable @plane on @pipe, making sure that @pipe is running first.
1871  */
1872 static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
1873                                           enum plane plane, enum pipe pipe)
1874 {
1875         struct intel_crtc *intel_crtc =
1876                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1877         int reg;
1878         u32 val;
1879
1880         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1881         assert_pipe_enabled(dev_priv, pipe);
1882
1883         WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n");
1884
1885         intel_crtc->primary_enabled = true;
1886
1887         reg = DSPCNTR(plane);
1888         val = I915_READ(reg);
1889         if (val & DISPLAY_PLANE_ENABLE)
1890                 return;
1891
1892         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1893         intel_flush_primary_plane(dev_priv, plane);
1894         intel_wait_for_vblank(dev_priv->dev, pipe);
1895 }
1896
1897 /**
1898  * intel_disable_primary_hw_plane - disable the primary hardware plane
1899  * @dev_priv: i915 private structure
1900  * @plane: plane to disable
1901  * @pipe: pipe consuming the data
1902  *
1903  * Disable @plane; should be an independent operation.
1904  */
1905 static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
1906                                            enum plane plane, enum pipe pipe)
1907 {
1908         struct intel_crtc *intel_crtc =
1909                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1910         int reg;
1911         u32 val;
1912
1913         WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n");
1914
1915         intel_crtc->primary_enabled = false;
1916
1917         reg = DSPCNTR(plane);
1918         val = I915_READ(reg);
1919         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1920                 return;
1921
1922         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1923         intel_flush_primary_plane(dev_priv, plane);
1924         intel_wait_for_vblank(dev_priv->dev, pipe);
1925 }
1926
1927 static bool need_vtd_wa(struct drm_device *dev)
1928 {
1929 #ifdef CONFIG_INTEL_IOMMU
1930         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1931                 return true;
1932 #endif
1933         return false;
1934 }
1935
1936 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
1937 {
1938         int tile_height;
1939
1940         tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
1941         return ALIGN(height, tile_height);
1942 }
1943
1944 int
1945 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1946                            struct drm_i915_gem_object *obj,
1947                            struct intel_ring_buffer *pipelined)
1948 {
1949         struct drm_i915_private *dev_priv = dev->dev_private;
1950         u32 alignment;
1951         int ret;
1952
1953         switch (obj->tiling_mode) {
1954         case I915_TILING_NONE:
1955                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1956                         alignment = 128 * 1024;
1957                 else if (INTEL_INFO(dev)->gen >= 4)
1958                         alignment = 4 * 1024;
1959                 else
1960                         alignment = 64 * 1024;
1961                 break;
1962         case I915_TILING_X:
1963                 /* pin() will align the object as required by fence */
1964                 alignment = 0;
1965                 break;
1966         case I915_TILING_Y:
1967                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
1968                 return -EINVAL;
1969         default:
1970                 BUG();
1971         }
1972
1973         /* Note that the w/a also requires 64 PTE of padding following the
1974          * bo. We currently fill all unused PTE with the shadow page and so
1975          * we should always have valid PTE following the scanout preventing
1976          * the VT-d warning.
1977          */
1978         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1979                 alignment = 256 * 1024;
1980
1981         dev_priv->mm.interruptible = false;
1982         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1983         if (ret)
1984                 goto err_interruptible;
1985
1986         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1987          * fence, whereas 965+ only requires a fence if using
1988          * framebuffer compression.  For simplicity, we always install
1989          * a fence as the cost is not that onerous.
1990          */
1991         ret = i915_gem_object_get_fence(obj);
1992         if (ret)
1993                 goto err_unpin;
1994
1995         i915_gem_object_pin_fence(obj);
1996
1997         dev_priv->mm.interruptible = true;
1998         return 0;
1999
2000 err_unpin:
2001         i915_gem_object_unpin_from_display_plane(obj);
2002 err_interruptible:
2003         dev_priv->mm.interruptible = true;
2004         return ret;
2005 }
2006
2007 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2008 {
2009         i915_gem_object_unpin_fence(obj);
2010         i915_gem_object_unpin_from_display_plane(obj);
2011 }
2012
2013 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2014  * is assumed to be a power-of-two. */
2015 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2016                                              unsigned int tiling_mode,
2017                                              unsigned int cpp,
2018                                              unsigned int pitch)
2019 {
2020         if (tiling_mode != I915_TILING_NONE) {
2021                 unsigned int tile_rows, tiles;
2022
2023                 tile_rows = *y / 8;
2024                 *y %= 8;
2025
2026                 tiles = *x / (512/cpp);
2027                 *x %= 512/cpp;
2028
2029                 return tile_rows * pitch * 8 + tiles * 4096;
2030         } else {
2031                 unsigned int offset;
2032
2033                 offset = *y * pitch + *x * cpp;
2034                 *y = 0;
2035                 *x = (offset & 4095) / cpp;
2036                 return offset & -4096;
2037         }
2038 }
2039
2040 int intel_format_to_fourcc(int format)
2041 {
2042         switch (format) {
2043         case DISPPLANE_8BPP:
2044                 return DRM_FORMAT_C8;
2045         case DISPPLANE_BGRX555:
2046                 return DRM_FORMAT_XRGB1555;
2047         case DISPPLANE_BGRX565:
2048                 return DRM_FORMAT_RGB565;
2049         default:
2050         case DISPPLANE_BGRX888:
2051                 return DRM_FORMAT_XRGB8888;
2052         case DISPPLANE_RGBX888:
2053                 return DRM_FORMAT_XBGR8888;
2054         case DISPPLANE_BGRX101010:
2055                 return DRM_FORMAT_XRGB2101010;
2056         case DISPPLANE_RGBX101010:
2057                 return DRM_FORMAT_XBGR2101010;
2058         }
2059 }
2060
2061 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2062                                   struct intel_plane_config *plane_config)
2063 {
2064         struct drm_device *dev = crtc->base.dev;
2065         struct drm_i915_gem_object *obj = NULL;
2066         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2067         u32 base = plane_config->base;
2068
2069         if (plane_config->size == 0)
2070                 return false;
2071
2072         obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2073                                                              plane_config->size);
2074         if (!obj)
2075                 return false;
2076
2077         if (plane_config->tiled) {
2078                 obj->tiling_mode = I915_TILING_X;
2079                 obj->stride = crtc->base.primary->fb->pitches[0];
2080         }
2081
2082         mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2083         mode_cmd.width = crtc->base.primary->fb->width;
2084         mode_cmd.height = crtc->base.primary->fb->height;
2085         mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2086
2087         mutex_lock(&dev->struct_mutex);
2088
2089         if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2090                                    &mode_cmd, obj)) {
2091                 DRM_DEBUG_KMS("intel fb init failed\n");
2092                 goto out_unref_obj;
2093         }
2094
2095         mutex_unlock(&dev->struct_mutex);
2096
2097         DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2098         return true;
2099
2100 out_unref_obj:
2101         drm_gem_object_unreference(&obj->base);
2102         mutex_unlock(&dev->struct_mutex);
2103         return false;
2104 }
2105
2106 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2107                                  struct intel_plane_config *plane_config)
2108 {
2109         struct drm_device *dev = intel_crtc->base.dev;
2110         struct drm_crtc *c;
2111         struct intel_crtc *i;
2112         struct intel_framebuffer *fb;
2113
2114         if (!intel_crtc->base.primary->fb)
2115                 return;
2116
2117         if (intel_alloc_plane_obj(intel_crtc, plane_config))
2118                 return;
2119
2120         kfree(intel_crtc->base.primary->fb);
2121         intel_crtc->base.primary->fb = NULL;
2122
2123         /*
2124          * Failed to alloc the obj, check to see if we should share
2125          * an fb with another CRTC instead
2126          */
2127         list_for_each_entry(c, &dev->mode_config.crtc_list, head) {
2128                 i = to_intel_crtc(c);
2129
2130                 if (c == &intel_crtc->base)
2131                         continue;
2132
2133                 if (!i->active || !c->primary->fb)
2134                         continue;
2135
2136                 fb = to_intel_framebuffer(c->primary->fb);
2137                 if (i915_gem_obj_ggtt_offset(fb->obj) == plane_config->base) {
2138                         drm_framebuffer_reference(c->primary->fb);
2139                         intel_crtc->base.primary->fb = c->primary->fb;
2140                         break;
2141                 }
2142         }
2143 }
2144
2145 static int i9xx_update_primary_plane(struct drm_crtc *crtc,
2146                                      struct drm_framebuffer *fb,
2147                                      int x, int y)
2148 {
2149         struct drm_device *dev = crtc->dev;
2150         struct drm_i915_private *dev_priv = dev->dev_private;
2151         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2152         struct intel_framebuffer *intel_fb;
2153         struct drm_i915_gem_object *obj;
2154         int plane = intel_crtc->plane;
2155         unsigned long linear_offset;
2156         u32 dspcntr;
2157         u32 reg;
2158
2159         intel_fb = to_intel_framebuffer(fb);
2160         obj = intel_fb->obj;
2161
2162         reg = DSPCNTR(plane);
2163         dspcntr = I915_READ(reg);
2164         /* Mask out pixel format bits in case we change it */
2165         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2166         switch (fb->pixel_format) {
2167         case DRM_FORMAT_C8:
2168                 dspcntr |= DISPPLANE_8BPP;
2169                 break;
2170         case DRM_FORMAT_XRGB1555:
2171         case DRM_FORMAT_ARGB1555:
2172                 dspcntr |= DISPPLANE_BGRX555;
2173                 break;
2174         case DRM_FORMAT_RGB565:
2175                 dspcntr |= DISPPLANE_BGRX565;
2176                 break;
2177         case DRM_FORMAT_XRGB8888:
2178         case DRM_FORMAT_ARGB8888:
2179                 dspcntr |= DISPPLANE_BGRX888;
2180                 break;
2181         case DRM_FORMAT_XBGR8888:
2182         case DRM_FORMAT_ABGR8888:
2183                 dspcntr |= DISPPLANE_RGBX888;
2184                 break;
2185         case DRM_FORMAT_XRGB2101010:
2186         case DRM_FORMAT_ARGB2101010:
2187                 dspcntr |= DISPPLANE_BGRX101010;
2188                 break;
2189         case DRM_FORMAT_XBGR2101010:
2190         case DRM_FORMAT_ABGR2101010:
2191                 dspcntr |= DISPPLANE_RGBX101010;
2192                 break;
2193         default:
2194                 BUG();
2195         }
2196
2197         if (INTEL_INFO(dev)->gen >= 4) {
2198                 if (obj->tiling_mode != I915_TILING_NONE)
2199                         dspcntr |= DISPPLANE_TILED;
2200                 else
2201                         dspcntr &= ~DISPPLANE_TILED;
2202         }
2203
2204         if (IS_G4X(dev))
2205                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2206
2207         I915_WRITE(reg, dspcntr);
2208
2209         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2210
2211         if (INTEL_INFO(dev)->gen >= 4) {
2212                 intel_crtc->dspaddr_offset =
2213                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2214                                                        fb->bits_per_pixel / 8,
2215                                                        fb->pitches[0]);
2216                 linear_offset -= intel_crtc->dspaddr_offset;
2217         } else {
2218                 intel_crtc->dspaddr_offset = linear_offset;
2219         }
2220
2221         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2222                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2223                       fb->pitches[0]);
2224         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2225         if (INTEL_INFO(dev)->gen >= 4) {
2226                 I915_WRITE(DSPSURF(plane),
2227                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2228                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2229                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2230         } else
2231                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2232         POSTING_READ(reg);
2233
2234         return 0;
2235 }
2236
2237 static int ironlake_update_primary_plane(struct drm_crtc *crtc,
2238                                          struct drm_framebuffer *fb,
2239                                          int x, int y)
2240 {
2241         struct drm_device *dev = crtc->dev;
2242         struct drm_i915_private *dev_priv = dev->dev_private;
2243         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2244         struct intel_framebuffer *intel_fb;
2245         struct drm_i915_gem_object *obj;
2246         int plane = intel_crtc->plane;
2247         unsigned long linear_offset;
2248         u32 dspcntr;
2249         u32 reg;
2250
2251         intel_fb = to_intel_framebuffer(fb);
2252         obj = intel_fb->obj;
2253
2254         reg = DSPCNTR(plane);
2255         dspcntr = I915_READ(reg);
2256         /* Mask out pixel format bits in case we change it */
2257         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2258         switch (fb->pixel_format) {
2259         case DRM_FORMAT_C8:
2260                 dspcntr |= DISPPLANE_8BPP;
2261                 break;
2262         case DRM_FORMAT_RGB565:
2263                 dspcntr |= DISPPLANE_BGRX565;
2264                 break;
2265         case DRM_FORMAT_XRGB8888:
2266         case DRM_FORMAT_ARGB8888:
2267                 dspcntr |= DISPPLANE_BGRX888;
2268                 break;
2269         case DRM_FORMAT_XBGR8888:
2270         case DRM_FORMAT_ABGR8888:
2271                 dspcntr |= DISPPLANE_RGBX888;
2272                 break;
2273         case DRM_FORMAT_XRGB2101010:
2274         case DRM_FORMAT_ARGB2101010:
2275                 dspcntr |= DISPPLANE_BGRX101010;
2276                 break;
2277         case DRM_FORMAT_XBGR2101010:
2278         case DRM_FORMAT_ABGR2101010:
2279                 dspcntr |= DISPPLANE_RGBX101010;
2280                 break;
2281         default:
2282                 BUG();
2283         }
2284
2285         if (obj->tiling_mode != I915_TILING_NONE)
2286                 dspcntr |= DISPPLANE_TILED;
2287         else
2288                 dspcntr &= ~DISPPLANE_TILED;
2289
2290         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2291                 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2292         else
2293                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2294
2295         I915_WRITE(reg, dspcntr);
2296
2297         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2298         intel_crtc->dspaddr_offset =
2299                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2300                                                fb->bits_per_pixel / 8,
2301                                                fb->pitches[0]);
2302         linear_offset -= intel_crtc->dspaddr_offset;
2303
2304         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2305                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2306                       fb->pitches[0]);
2307         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2308         I915_WRITE(DSPSURF(plane),
2309                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2310         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2311                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2312         } else {
2313                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2314                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2315         }
2316         POSTING_READ(reg);
2317
2318         return 0;
2319 }
2320
2321 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2322 static int
2323 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2324                            int x, int y, enum mode_set_atomic state)
2325 {
2326         struct drm_device *dev = crtc->dev;
2327         struct drm_i915_private *dev_priv = dev->dev_private;
2328
2329         if (dev_priv->display.disable_fbc)
2330                 dev_priv->display.disable_fbc(dev);
2331         intel_increase_pllclock(crtc);
2332
2333         return dev_priv->display.update_primary_plane(crtc, fb, x, y);
2334 }
2335
2336 void intel_display_handle_reset(struct drm_device *dev)
2337 {
2338         struct drm_i915_private *dev_priv = dev->dev_private;
2339         struct drm_crtc *crtc;
2340
2341         /*
2342          * Flips in the rings have been nuked by the reset,
2343          * so complete all pending flips so that user space
2344          * will get its events and not get stuck.
2345          *
2346          * Also update the base address of all primary
2347          * planes to the the last fb to make sure we're
2348          * showing the correct fb after a reset.
2349          *
2350          * Need to make two loops over the crtcs so that we
2351          * don't try to grab a crtc mutex before the
2352          * pending_flip_queue really got woken up.
2353          */
2354
2355         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2356                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2357                 enum plane plane = intel_crtc->plane;
2358
2359                 intel_prepare_page_flip(dev, plane);
2360                 intel_finish_page_flip_plane(dev, plane);
2361         }
2362
2363         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2364                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2365
2366                 mutex_lock(&crtc->mutex);
2367                 /*
2368                  * FIXME: Once we have proper support for primary planes (and
2369                  * disabling them without disabling the entire crtc) allow again
2370                  * a NULL crtc->primary->fb.
2371                  */
2372                 if (intel_crtc->active && crtc->primary->fb)
2373                         dev_priv->display.update_primary_plane(crtc,
2374                                                                crtc->primary->fb,
2375                                                                crtc->x,
2376                                                                crtc->y);
2377                 mutex_unlock(&crtc->mutex);
2378         }
2379 }
2380
2381 static int
2382 intel_finish_fb(struct drm_framebuffer *old_fb)
2383 {
2384         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2385         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2386         bool was_interruptible = dev_priv->mm.interruptible;
2387         int ret;
2388
2389         /* Big Hammer, we also need to ensure that any pending
2390          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2391          * current scanout is retired before unpinning the old
2392          * framebuffer.
2393          *
2394          * This should only fail upon a hung GPU, in which case we
2395          * can safely continue.
2396          */
2397         dev_priv->mm.interruptible = false;
2398         ret = i915_gem_object_finish_gpu(obj);
2399         dev_priv->mm.interruptible = was_interruptible;
2400
2401         return ret;
2402 }
2403
2404 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2405 {
2406         struct drm_device *dev = crtc->dev;
2407         struct drm_i915_private *dev_priv = dev->dev_private;
2408         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2409         unsigned long flags;
2410         bool pending;
2411
2412         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2413             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2414                 return false;
2415
2416         spin_lock_irqsave(&dev->event_lock, flags);
2417         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2418         spin_unlock_irqrestore(&dev->event_lock, flags);
2419
2420         return pending;
2421 }
2422
2423 static int
2424 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2425                     struct drm_framebuffer *fb)
2426 {
2427         struct drm_device *dev = crtc->dev;
2428         struct drm_i915_private *dev_priv = dev->dev_private;
2429         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2430         struct drm_framebuffer *old_fb;
2431         int ret;
2432
2433         if (intel_crtc_has_pending_flip(crtc)) {
2434                 DRM_ERROR("pipe is still busy with an old pageflip\n");
2435                 return -EBUSY;
2436         }
2437
2438         /* no fb bound */
2439         if (!fb) {
2440                 DRM_ERROR("No FB bound\n");
2441                 return 0;
2442         }
2443
2444         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2445                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2446                           plane_name(intel_crtc->plane),
2447                           INTEL_INFO(dev)->num_pipes);
2448                 return -EINVAL;
2449         }
2450
2451         mutex_lock(&dev->struct_mutex);
2452         ret = intel_pin_and_fence_fb_obj(dev,
2453                                          to_intel_framebuffer(fb)->obj,
2454                                          NULL);
2455         mutex_unlock(&dev->struct_mutex);
2456         if (ret != 0) {
2457                 DRM_ERROR("pin & fence failed\n");
2458                 return ret;
2459         }
2460
2461         /*
2462          * Update pipe size and adjust fitter if needed: the reason for this is
2463          * that in compute_mode_changes we check the native mode (not the pfit
2464          * mode) to see if we can flip rather than do a full mode set. In the
2465          * fastboot case, we'll flip, but if we don't update the pipesrc and
2466          * pfit state, we'll end up with a big fb scanned out into the wrong
2467          * sized surface.
2468          *
2469          * To fix this properly, we need to hoist the checks up into
2470          * compute_mode_changes (or above), check the actual pfit state and
2471          * whether the platform allows pfit disable with pipe active, and only
2472          * then update the pipesrc and pfit state, even on the flip path.
2473          */
2474         if (i915.fastboot) {
2475                 const struct drm_display_mode *adjusted_mode =
2476                         &intel_crtc->config.adjusted_mode;
2477
2478                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2479                            ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2480                            (adjusted_mode->crtc_vdisplay - 1));
2481                 if (!intel_crtc->config.pch_pfit.enabled &&
2482                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2483                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2484                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2485                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2486                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2487                 }
2488                 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2489                 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2490         }
2491
2492         ret = dev_priv->display.update_primary_plane(crtc, fb, x, y);
2493         if (ret) {
2494                 mutex_lock(&dev->struct_mutex);
2495                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2496                 mutex_unlock(&dev->struct_mutex);
2497                 DRM_ERROR("failed to update base address\n");
2498                 return ret;
2499         }
2500
2501         old_fb = crtc->primary->fb;
2502         crtc->primary->fb = fb;
2503         crtc->x = x;
2504         crtc->y = y;
2505
2506         if (old_fb) {
2507                 if (intel_crtc->active && old_fb != fb)
2508                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2509                 mutex_lock(&dev->struct_mutex);
2510                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2511                 mutex_unlock(&dev->struct_mutex);
2512         }
2513
2514         mutex_lock(&dev->struct_mutex);
2515         intel_update_fbc(dev);
2516         intel_edp_psr_update(dev);
2517         mutex_unlock(&dev->struct_mutex);
2518
2519         return 0;
2520 }
2521
2522 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2523 {
2524         struct drm_device *dev = crtc->dev;
2525         struct drm_i915_private *dev_priv = dev->dev_private;
2526         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2527         int pipe = intel_crtc->pipe;
2528         u32 reg, temp;
2529
2530         /* enable normal train */
2531         reg = FDI_TX_CTL(pipe);
2532         temp = I915_READ(reg);
2533         if (IS_IVYBRIDGE(dev)) {
2534                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2535                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2536         } else {
2537                 temp &= ~FDI_LINK_TRAIN_NONE;
2538                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2539         }
2540         I915_WRITE(reg, temp);
2541
2542         reg = FDI_RX_CTL(pipe);
2543         temp = I915_READ(reg);
2544         if (HAS_PCH_CPT(dev)) {
2545                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2546                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2547         } else {
2548                 temp &= ~FDI_LINK_TRAIN_NONE;
2549                 temp |= FDI_LINK_TRAIN_NONE;
2550         }
2551         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2552
2553         /* wait one idle pattern time */
2554         POSTING_READ(reg);
2555         udelay(1000);
2556
2557         /* IVB wants error correction enabled */
2558         if (IS_IVYBRIDGE(dev))
2559                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2560                            FDI_FE_ERRC_ENABLE);
2561 }
2562
2563 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2564 {
2565         return crtc->base.enabled && crtc->active &&
2566                 crtc->config.has_pch_encoder;
2567 }
2568
2569 static void ivb_modeset_global_resources(struct drm_device *dev)
2570 {
2571         struct drm_i915_private *dev_priv = dev->dev_private;
2572         struct intel_crtc *pipe_B_crtc =
2573                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2574         struct intel_crtc *pipe_C_crtc =
2575                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2576         uint32_t temp;
2577
2578         /*
2579          * When everything is off disable fdi C so that we could enable fdi B
2580          * with all lanes. Note that we don't care about enabled pipes without
2581          * an enabled pch encoder.
2582          */
2583         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2584             !pipe_has_enabled_pch(pipe_C_crtc)) {
2585                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2586                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2587
2588                 temp = I915_READ(SOUTH_CHICKEN1);
2589                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2590                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2591                 I915_WRITE(SOUTH_CHICKEN1, temp);
2592         }
2593 }
2594
2595 /* The FDI link training functions for ILK/Ibexpeak. */
2596 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2597 {
2598         struct drm_device *dev = crtc->dev;
2599         struct drm_i915_private *dev_priv = dev->dev_private;
2600         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2601         int pipe = intel_crtc->pipe;
2602         int plane = intel_crtc->plane;
2603         u32 reg, temp, tries;
2604
2605         /* FDI needs bits from pipe & plane first */
2606         assert_pipe_enabled(dev_priv, pipe);
2607         assert_plane_enabled(dev_priv, plane);
2608
2609         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2610            for train result */
2611         reg = FDI_RX_IMR(pipe);
2612         temp = I915_READ(reg);
2613         temp &= ~FDI_RX_SYMBOL_LOCK;
2614         temp &= ~FDI_RX_BIT_LOCK;
2615         I915_WRITE(reg, temp);
2616         I915_READ(reg);
2617         udelay(150);
2618
2619         /* enable CPU FDI TX and PCH FDI RX */
2620         reg = FDI_TX_CTL(pipe);
2621         temp = I915_READ(reg);
2622         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2623         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2624         temp &= ~FDI_LINK_TRAIN_NONE;
2625         temp |= FDI_LINK_TRAIN_PATTERN_1;
2626         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2627
2628         reg = FDI_RX_CTL(pipe);
2629         temp = I915_READ(reg);
2630         temp &= ~FDI_LINK_TRAIN_NONE;
2631         temp |= FDI_LINK_TRAIN_PATTERN_1;
2632         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2633
2634         POSTING_READ(reg);
2635         udelay(150);
2636
2637         /* Ironlake workaround, enable clock pointer after FDI enable*/
2638         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2639         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2640                    FDI_RX_PHASE_SYNC_POINTER_EN);
2641
2642         reg = FDI_RX_IIR(pipe);
2643         for (tries = 0; tries < 5; tries++) {
2644                 temp = I915_READ(reg);
2645                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2646
2647                 if ((temp & FDI_RX_BIT_LOCK)) {
2648                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2649                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2650                         break;
2651                 }
2652         }
2653         if (tries == 5)
2654                 DRM_ERROR("FDI train 1 fail!\n");
2655
2656         /* Train 2 */
2657         reg = FDI_TX_CTL(pipe);
2658         temp = I915_READ(reg);
2659         temp &= ~FDI_LINK_TRAIN_NONE;
2660         temp |= FDI_LINK_TRAIN_PATTERN_2;
2661         I915_WRITE(reg, temp);
2662
2663         reg = FDI_RX_CTL(pipe);
2664         temp = I915_READ(reg);
2665         temp &= ~FDI_LINK_TRAIN_NONE;
2666         temp |= FDI_LINK_TRAIN_PATTERN_2;
2667         I915_WRITE(reg, temp);
2668
2669         POSTING_READ(reg);
2670         udelay(150);
2671
2672         reg = FDI_RX_IIR(pipe);
2673         for (tries = 0; tries < 5; tries++) {
2674                 temp = I915_READ(reg);
2675                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2676
2677                 if (temp & FDI_RX_SYMBOL_LOCK) {
2678                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2679                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2680                         break;
2681                 }
2682         }
2683         if (tries == 5)
2684                 DRM_ERROR("FDI train 2 fail!\n");
2685
2686         DRM_DEBUG_KMS("FDI train done\n");
2687
2688 }
2689
2690 static const int snb_b_fdi_train_param[] = {
2691         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2692         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2693         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2694         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2695 };
2696
2697 /* The FDI link training functions for SNB/Cougarpoint. */
2698 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2699 {
2700         struct drm_device *dev = crtc->dev;
2701         struct drm_i915_private *dev_priv = dev->dev_private;
2702         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2703         int pipe = intel_crtc->pipe;
2704         u32 reg, temp, i, retry;
2705
2706         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2707            for train result */
2708         reg = FDI_RX_IMR(pipe);
2709         temp = I915_READ(reg);
2710         temp &= ~FDI_RX_SYMBOL_LOCK;
2711         temp &= ~FDI_RX_BIT_LOCK;
2712         I915_WRITE(reg, temp);
2713
2714         POSTING_READ(reg);
2715         udelay(150);
2716
2717         /* enable CPU FDI TX and PCH FDI RX */
2718         reg = FDI_TX_CTL(pipe);
2719         temp = I915_READ(reg);
2720         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2721         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2722         temp &= ~FDI_LINK_TRAIN_NONE;
2723         temp |= FDI_LINK_TRAIN_PATTERN_1;
2724         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2725         /* SNB-B */
2726         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2727         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2728
2729         I915_WRITE(FDI_RX_MISC(pipe),
2730                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2731
2732         reg = FDI_RX_CTL(pipe);
2733         temp = I915_READ(reg);
2734         if (HAS_PCH_CPT(dev)) {
2735                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2736                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2737         } else {
2738                 temp &= ~FDI_LINK_TRAIN_NONE;
2739                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2740         }
2741         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2742
2743         POSTING_READ(reg);
2744         udelay(150);
2745
2746         for (i = 0; i < 4; i++) {
2747                 reg = FDI_TX_CTL(pipe);
2748                 temp = I915_READ(reg);
2749                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2750                 temp |= snb_b_fdi_train_param[i];
2751                 I915_WRITE(reg, temp);
2752
2753                 POSTING_READ(reg);
2754                 udelay(500);
2755
2756                 for (retry = 0; retry < 5; retry++) {
2757                         reg = FDI_RX_IIR(pipe);
2758                         temp = I915_READ(reg);
2759                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2760                         if (temp & FDI_RX_BIT_LOCK) {
2761                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2762                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2763                                 break;
2764                         }
2765                         udelay(50);
2766                 }
2767                 if (retry < 5)
2768                         break;
2769         }
2770         if (i == 4)
2771                 DRM_ERROR("FDI train 1 fail!\n");
2772
2773         /* Train 2 */
2774         reg = FDI_TX_CTL(pipe);
2775         temp = I915_READ(reg);
2776         temp &= ~FDI_LINK_TRAIN_NONE;
2777         temp |= FDI_LINK_TRAIN_PATTERN_2;
2778         if (IS_GEN6(dev)) {
2779                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2780                 /* SNB-B */
2781                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2782         }
2783         I915_WRITE(reg, temp);
2784
2785         reg = FDI_RX_CTL(pipe);
2786         temp = I915_READ(reg);
2787         if (HAS_PCH_CPT(dev)) {
2788                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2789                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2790         } else {
2791                 temp &= ~FDI_LINK_TRAIN_NONE;
2792                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2793         }
2794         I915_WRITE(reg, temp);
2795
2796         POSTING_READ(reg);
2797         udelay(150);
2798
2799         for (i = 0; i < 4; i++) {
2800                 reg = FDI_TX_CTL(pipe);
2801                 temp = I915_READ(reg);
2802                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2803                 temp |= snb_b_fdi_train_param[i];
2804                 I915_WRITE(reg, temp);
2805
2806                 POSTING_READ(reg);
2807                 udelay(500);
2808
2809                 for (retry = 0; retry < 5; retry++) {
2810                         reg = FDI_RX_IIR(pipe);
2811                         temp = I915_READ(reg);
2812                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2813                         if (temp & FDI_RX_SYMBOL_LOCK) {
2814                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2815                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2816                                 break;
2817                         }
2818                         udelay(50);
2819                 }
2820                 if (retry < 5)
2821                         break;
2822         }
2823         if (i == 4)
2824                 DRM_ERROR("FDI train 2 fail!\n");
2825
2826         DRM_DEBUG_KMS("FDI train done.\n");
2827 }
2828
2829 /* Manual link training for Ivy Bridge A0 parts */
2830 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2831 {
2832         struct drm_device *dev = crtc->dev;
2833         struct drm_i915_private *dev_priv = dev->dev_private;
2834         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2835         int pipe = intel_crtc->pipe;
2836         u32 reg, temp, i, j;
2837
2838         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2839            for train result */
2840         reg = FDI_RX_IMR(pipe);
2841         temp = I915_READ(reg);
2842         temp &= ~FDI_RX_SYMBOL_LOCK;
2843         temp &= ~FDI_RX_BIT_LOCK;
2844         I915_WRITE(reg, temp);
2845
2846         POSTING_READ(reg);
2847         udelay(150);
2848
2849         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2850                       I915_READ(FDI_RX_IIR(pipe)));
2851
2852         /* Try each vswing and preemphasis setting twice before moving on */
2853         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2854                 /* disable first in case we need to retry */
2855                 reg = FDI_TX_CTL(pipe);
2856                 temp = I915_READ(reg);
2857                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2858                 temp &= ~FDI_TX_ENABLE;
2859                 I915_WRITE(reg, temp);
2860
2861                 reg = FDI_RX_CTL(pipe);
2862                 temp = I915_READ(reg);
2863                 temp &= ~FDI_LINK_TRAIN_AUTO;
2864                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2865                 temp &= ~FDI_RX_ENABLE;
2866                 I915_WRITE(reg, temp);
2867
2868                 /* enable CPU FDI TX and PCH FDI RX */
2869                 reg = FDI_TX_CTL(pipe);
2870                 temp = I915_READ(reg);
2871                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2872                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2873                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2874                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2875                 temp |= snb_b_fdi_train_param[j/2];
2876                 temp |= FDI_COMPOSITE_SYNC;
2877                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2878
2879                 I915_WRITE(FDI_RX_MISC(pipe),
2880                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2881
2882                 reg = FDI_RX_CTL(pipe);
2883                 temp = I915_READ(reg);
2884                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2885                 temp |= FDI_COMPOSITE_SYNC;
2886                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2887
2888                 POSTING_READ(reg);
2889                 udelay(1); /* should be 0.5us */
2890
2891                 for (i = 0; i < 4; i++) {
2892                         reg = FDI_RX_IIR(pipe);
2893                         temp = I915_READ(reg);
2894                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2895
2896                         if (temp & FDI_RX_BIT_LOCK ||
2897                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2898                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2899                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2900                                               i);
2901                                 break;
2902                         }
2903                         udelay(1); /* should be 0.5us */
2904                 }
2905                 if (i == 4) {
2906                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2907                         continue;
2908                 }
2909
2910                 /* Train 2 */
2911                 reg = FDI_TX_CTL(pipe);
2912                 temp = I915_READ(reg);
2913                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2914                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2915                 I915_WRITE(reg, temp);
2916
2917                 reg = FDI_RX_CTL(pipe);
2918                 temp = I915_READ(reg);
2919                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2920                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2921                 I915_WRITE(reg, temp);
2922
2923                 POSTING_READ(reg);
2924                 udelay(2); /* should be 1.5us */
2925
2926                 for (i = 0; i < 4; i++) {
2927                         reg = FDI_RX_IIR(pipe);
2928                         temp = I915_READ(reg);
2929                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2930
2931                         if (temp & FDI_RX_SYMBOL_LOCK ||
2932                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2933                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2934                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2935                                               i);
2936                                 goto train_done;
2937                         }
2938                         udelay(2); /* should be 1.5us */
2939                 }
2940                 if (i == 4)
2941                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2942         }
2943
2944 train_done:
2945         DRM_DEBUG_KMS("FDI train done.\n");
2946 }
2947
2948 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2949 {
2950         struct drm_device *dev = intel_crtc->base.dev;
2951         struct drm_i915_private *dev_priv = dev->dev_private;
2952         int pipe = intel_crtc->pipe;
2953         u32 reg, temp;
2954
2955
2956         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2957         reg = FDI_RX_CTL(pipe);
2958         temp = I915_READ(reg);
2959         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2960         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2961         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2962         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2963
2964         POSTING_READ(reg);
2965         udelay(200);
2966
2967         /* Switch from Rawclk to PCDclk */
2968         temp = I915_READ(reg);
2969         I915_WRITE(reg, temp | FDI_PCDCLK);
2970
2971         POSTING_READ(reg);
2972         udelay(200);
2973
2974         /* Enable CPU FDI TX PLL, always on for Ironlake */
2975         reg = FDI_TX_CTL(pipe);
2976         temp = I915_READ(reg);
2977         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2978                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2979
2980                 POSTING_READ(reg);
2981                 udelay(100);
2982         }
2983 }
2984
2985 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2986 {
2987         struct drm_device *dev = intel_crtc->base.dev;
2988         struct drm_i915_private *dev_priv = dev->dev_private;
2989         int pipe = intel_crtc->pipe;
2990         u32 reg, temp;
2991
2992         /* Switch from PCDclk to Rawclk */
2993         reg = FDI_RX_CTL(pipe);
2994         temp = I915_READ(reg);
2995         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2996
2997         /* Disable CPU FDI TX PLL */
2998         reg = FDI_TX_CTL(pipe);
2999         temp = I915_READ(reg);
3000         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3001
3002         POSTING_READ(reg);
3003         udelay(100);
3004
3005         reg = FDI_RX_CTL(pipe);
3006         temp = I915_READ(reg);
3007         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3008
3009         /* Wait for the clocks to turn off. */
3010         POSTING_READ(reg);
3011         udelay(100);
3012 }
3013
3014 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3015 {
3016         struct drm_device *dev = crtc->dev;
3017         struct drm_i915_private *dev_priv = dev->dev_private;
3018         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3019         int pipe = intel_crtc->pipe;
3020         u32 reg, temp;
3021
3022         /* disable CPU FDI tx and PCH FDI rx */
3023         reg = FDI_TX_CTL(pipe);
3024         temp = I915_READ(reg);
3025         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3026         POSTING_READ(reg);
3027
3028         reg = FDI_RX_CTL(pipe);
3029         temp = I915_READ(reg);
3030         temp &= ~(0x7 << 16);
3031         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3032         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3033
3034         POSTING_READ(reg);
3035         udelay(100);
3036
3037         /* Ironlake workaround, disable clock pointer after downing FDI */
3038         if (HAS_PCH_IBX(dev)) {
3039                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3040         }
3041
3042         /* still set train pattern 1 */
3043         reg = FDI_TX_CTL(pipe);
3044         temp = I915_READ(reg);
3045         temp &= ~FDI_LINK_TRAIN_NONE;
3046         temp |= FDI_LINK_TRAIN_PATTERN_1;
3047         I915_WRITE(reg, temp);
3048
3049         reg = FDI_RX_CTL(pipe);
3050         temp = I915_READ(reg);
3051         if (HAS_PCH_CPT(dev)) {
3052                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3053                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3054         } else {
3055                 temp &= ~FDI_LINK_TRAIN_NONE;
3056                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3057         }
3058         /* BPC in FDI rx is consistent with that in PIPECONF */
3059         temp &= ~(0x07 << 16);
3060         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3061         I915_WRITE(reg, temp);
3062
3063         POSTING_READ(reg);
3064         udelay(100);
3065 }
3066
3067 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3068 {
3069         struct intel_crtc *crtc;
3070
3071         /* Note that we don't need to be called with mode_config.lock here
3072          * as our list of CRTC objects is static for the lifetime of the
3073          * device and so cannot disappear as we iterate. Similarly, we can
3074          * happily treat the predicates as racy, atomic checks as userspace
3075          * cannot claim and pin a new fb without at least acquring the
3076          * struct_mutex and so serialising with us.
3077          */
3078         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3079                 if (atomic_read(&crtc->unpin_work_count) == 0)
3080                         continue;
3081
3082                 if (crtc->unpin_work)
3083                         intel_wait_for_vblank(dev, crtc->pipe);
3084
3085                 return true;
3086         }
3087
3088         return false;
3089 }
3090
3091 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3092 {
3093         struct drm_device *dev = crtc->dev;
3094         struct drm_i915_private *dev_priv = dev->dev_private;
3095
3096         if (crtc->primary->fb == NULL)
3097                 return;
3098
3099         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3100
3101         wait_event(dev_priv->pending_flip_queue,
3102                    !intel_crtc_has_pending_flip(crtc));
3103
3104         mutex_lock(&dev->struct_mutex);
3105         intel_finish_fb(crtc->primary->fb);
3106         mutex_unlock(&dev->struct_mutex);
3107 }
3108
3109 /* Program iCLKIP clock to the desired frequency */
3110 static void lpt_program_iclkip(struct drm_crtc *crtc)
3111 {
3112         struct drm_device *dev = crtc->dev;
3113         struct drm_i915_private *dev_priv = dev->dev_private;
3114         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3115         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3116         u32 temp;
3117
3118         mutex_lock(&dev_priv->dpio_lock);
3119
3120         /* It is necessary to ungate the pixclk gate prior to programming
3121          * the divisors, and gate it back when it is done.
3122          */
3123         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3124
3125         /* Disable SSCCTL */
3126         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3127                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3128                                 SBI_SSCCTL_DISABLE,
3129                         SBI_ICLK);
3130
3131         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3132         if (clock == 20000) {
3133                 auxdiv = 1;
3134                 divsel = 0x41;
3135                 phaseinc = 0x20;
3136         } else {
3137                 /* The iCLK virtual clock root frequency is in MHz,
3138                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3139                  * divisors, it is necessary to divide one by another, so we
3140                  * convert the virtual clock precision to KHz here for higher
3141                  * precision.
3142                  */
3143                 u32 iclk_virtual_root_freq = 172800 * 1000;
3144                 u32 iclk_pi_range = 64;
3145                 u32 desired_divisor, msb_divisor_value, pi_value;
3146
3147                 desired_divisor = (iclk_virtual_root_freq / clock);
3148                 msb_divisor_value = desired_divisor / iclk_pi_range;
3149                 pi_value = desired_divisor % iclk_pi_range;
3150
3151                 auxdiv = 0;
3152                 divsel = msb_divisor_value - 2;
3153                 phaseinc = pi_value;
3154         }
3155
3156         /* This should not happen with any sane values */
3157         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3158                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3159         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3160                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3161
3162         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3163                         clock,
3164                         auxdiv,
3165                         divsel,
3166                         phasedir,
3167                         phaseinc);
3168
3169         /* Program SSCDIVINTPHASE6 */
3170         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3171         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3172         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3173         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3174         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3175         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3176         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3177         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3178
3179         /* Program SSCAUXDIV */
3180         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3181         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3182         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3183         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3184
3185         /* Enable modulator and associated divider */
3186         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3187         temp &= ~SBI_SSCCTL_DISABLE;
3188         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3189
3190         /* Wait for initialization time */
3191         udelay(24);
3192
3193         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3194
3195         mutex_unlock(&dev_priv->dpio_lock);
3196 }
3197
3198 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3199                                                 enum pipe pch_transcoder)
3200 {
3201         struct drm_device *dev = crtc->base.dev;
3202         struct drm_i915_private *dev_priv = dev->dev_private;
3203         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3204
3205         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3206                    I915_READ(HTOTAL(cpu_transcoder)));
3207         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3208                    I915_READ(HBLANK(cpu_transcoder)));
3209         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3210                    I915_READ(HSYNC(cpu_transcoder)));
3211
3212         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3213                    I915_READ(VTOTAL(cpu_transcoder)));
3214         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3215                    I915_READ(VBLANK(cpu_transcoder)));
3216         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3217                    I915_READ(VSYNC(cpu_transcoder)));
3218         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3219                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3220 }
3221
3222 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3223 {
3224         struct drm_i915_private *dev_priv = dev->dev_private;
3225         uint32_t temp;
3226
3227         temp = I915_READ(SOUTH_CHICKEN1);
3228         if (temp & FDI_BC_BIFURCATION_SELECT)
3229                 return;
3230
3231         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3232         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3233
3234         temp |= FDI_BC_BIFURCATION_SELECT;
3235         DRM_DEBUG_KMS("enabling fdi C rx\n");
3236         I915_WRITE(SOUTH_CHICKEN1, temp);
3237         POSTING_READ(SOUTH_CHICKEN1);
3238 }
3239
3240 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3241 {
3242         struct drm_device *dev = intel_crtc->base.dev;
3243         struct drm_i915_private *dev_priv = dev->dev_private;
3244
3245         switch (intel_crtc->pipe) {
3246         case PIPE_A:
3247                 break;
3248         case PIPE_B:
3249                 if (intel_crtc->config.fdi_lanes > 2)
3250                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3251                 else
3252                         cpt_enable_fdi_bc_bifurcation(dev);
3253
3254                 break;
3255         case PIPE_C:
3256                 cpt_enable_fdi_bc_bifurcation(dev);
3257
3258                 break;
3259         default:
3260                 BUG();
3261         }
3262 }
3263
3264 /*
3265  * Enable PCH resources required for PCH ports:
3266  *   - PCH PLLs
3267  *   - FDI training & RX/TX
3268  *   - update transcoder timings
3269  *   - DP transcoding bits
3270  *   - transcoder
3271  */
3272 static void ironlake_pch_enable(struct drm_crtc *crtc)
3273 {
3274         struct drm_device *dev = crtc->dev;
3275         struct drm_i915_private *dev_priv = dev->dev_private;
3276         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3277         int pipe = intel_crtc->pipe;
3278         u32 reg, temp;
3279
3280         assert_pch_transcoder_disabled(dev_priv, pipe);
3281
3282         if (IS_IVYBRIDGE(dev))
3283                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3284
3285         /* Write the TU size bits before fdi link training, so that error
3286          * detection works. */
3287         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3288                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3289
3290         /* For PCH output, training FDI link */
3291         dev_priv->display.fdi_link_train(crtc);
3292
3293         /* We need to program the right clock selection before writing the pixel
3294          * mutliplier into the DPLL. */
3295         if (HAS_PCH_CPT(dev)) {
3296                 u32 sel;
3297
3298                 temp = I915_READ(PCH_DPLL_SEL);
3299                 temp |= TRANS_DPLL_ENABLE(pipe);
3300                 sel = TRANS_DPLLB_SEL(pipe);
3301                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3302                         temp |= sel;
3303                 else
3304                         temp &= ~sel;
3305                 I915_WRITE(PCH_DPLL_SEL, temp);
3306         }
3307
3308         /* XXX: pch pll's can be enabled any time before we enable the PCH
3309          * transcoder, and we actually should do this to not upset any PCH
3310          * transcoder that already use the clock when we share it.
3311          *
3312          * Note that enable_shared_dpll tries to do the right thing, but
3313          * get_shared_dpll unconditionally resets the pll - we need that to have
3314          * the right LVDS enable sequence. */
3315         ironlake_enable_shared_dpll(intel_crtc);
3316
3317         /* set transcoder timing, panel must allow it */
3318         assert_panel_unlocked(dev_priv, pipe);
3319         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3320
3321         intel_fdi_normal_train(crtc);
3322
3323         /* For PCH DP, enable TRANS_DP_CTL */
3324         if (HAS_PCH_CPT(dev) &&
3325             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3326              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3327                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3328                 reg = TRANS_DP_CTL(pipe);
3329                 temp = I915_READ(reg);
3330                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3331                           TRANS_DP_SYNC_MASK |
3332                           TRANS_DP_BPC_MASK);
3333                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3334                          TRANS_DP_ENH_FRAMING);
3335                 temp |= bpc << 9; /* same format but at 11:9 */
3336
3337                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3338                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3339                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3340                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3341
3342                 switch (intel_trans_dp_port_sel(crtc)) {
3343                 case PCH_DP_B:
3344                         temp |= TRANS_DP_PORT_SEL_B;
3345                         break;
3346                 case PCH_DP_C:
3347                         temp |= TRANS_DP_PORT_SEL_C;
3348                         break;
3349                 case PCH_DP_D:
3350                         temp |= TRANS_DP_PORT_SEL_D;
3351                         break;
3352                 default:
3353                         BUG();
3354                 }
3355
3356                 I915_WRITE(reg, temp);
3357         }
3358
3359         ironlake_enable_pch_transcoder(dev_priv, pipe);
3360 }
3361
3362 static void lpt_pch_enable(struct drm_crtc *crtc)
3363 {
3364         struct drm_device *dev = crtc->dev;
3365         struct drm_i915_private *dev_priv = dev->dev_private;
3366         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3367         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3368
3369         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3370
3371         lpt_program_iclkip(crtc);
3372
3373         /* Set transcoder timing. */
3374         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3375
3376         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3377 }
3378
3379 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3380 {
3381         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3382
3383         if (pll == NULL)
3384                 return;
3385
3386         if (pll->refcount == 0) {
3387                 WARN(1, "bad %s refcount\n", pll->name);
3388                 return;
3389         }
3390
3391         if (--pll->refcount == 0) {
3392                 WARN_ON(pll->on);
3393                 WARN_ON(pll->active);
3394         }
3395
3396         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3397 }
3398
3399 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3400 {
3401         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3402         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3403         enum intel_dpll_id i;
3404
3405         if (pll) {
3406                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3407                               crtc->base.base.id, pll->name);
3408                 intel_put_shared_dpll(crtc);
3409         }
3410
3411         if (HAS_PCH_IBX(dev_priv->dev)) {
3412                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3413                 i = (enum intel_dpll_id) crtc->pipe;
3414                 pll = &dev_priv->shared_dplls[i];
3415
3416                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3417                               crtc->base.base.id, pll->name);
3418
3419                 goto found;
3420         }
3421
3422         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3423                 pll = &dev_priv->shared_dplls[i];
3424
3425                 /* Only want to check enabled timings first */
3426                 if (pll->refcount == 0)
3427                         continue;
3428
3429                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3430                            sizeof(pll->hw_state)) == 0) {
3431                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3432                                       crtc->base.base.id,
3433                                       pll->name, pll->refcount, pll->active);
3434
3435                         goto found;
3436                 }
3437         }
3438
3439         /* Ok no matching timings, maybe there's a free one? */
3440         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3441                 pll = &dev_priv->shared_dplls[i];
3442                 if (pll->refcount == 0) {
3443                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3444                                       crtc->base.base.id, pll->name);
3445                         goto found;
3446                 }
3447         }
3448
3449         return NULL;
3450
3451 found:
3452         crtc->config.shared_dpll = i;
3453         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3454                          pipe_name(crtc->pipe));
3455
3456         if (pll->active == 0) {
3457                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3458                        sizeof(pll->hw_state));
3459
3460                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3461                 WARN_ON(pll->on);
3462                 assert_shared_dpll_disabled(dev_priv, pll);
3463
3464                 pll->mode_set(dev_priv, pll);
3465         }
3466         pll->refcount++;
3467
3468         return pll;
3469 }
3470
3471 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3472 {
3473         struct drm_i915_private *dev_priv = dev->dev_private;
3474         int dslreg = PIPEDSL(pipe);
3475         u32 temp;
3476
3477         temp = I915_READ(dslreg);
3478         udelay(500);
3479         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3480                 if (wait_for(I915_READ(dslreg) != temp, 5))
3481                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3482         }
3483 }
3484
3485 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3486 {
3487         struct drm_device *dev = crtc->base.dev;
3488         struct drm_i915_private *dev_priv = dev->dev_private;
3489         int pipe = crtc->pipe;
3490
3491         if (crtc->config.pch_pfit.enabled) {
3492                 /* Force use of hard-coded filter coefficients
3493                  * as some pre-programmed values are broken,
3494                  * e.g. x201.
3495                  */
3496                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3497                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3498                                                  PF_PIPE_SEL_IVB(pipe));
3499                 else
3500                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3501                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3502                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3503         }
3504 }
3505
3506 static void intel_enable_planes(struct drm_crtc *crtc)
3507 {
3508         struct drm_device *dev = crtc->dev;
3509         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3510         struct drm_plane *plane;
3511         struct intel_plane *intel_plane;
3512
3513         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3514                 intel_plane = to_intel_plane(plane);
3515                 if (intel_plane->pipe == pipe)
3516                         intel_plane_restore(&intel_plane->base);
3517         }
3518 }
3519
3520 static void intel_disable_planes(struct drm_crtc *crtc)
3521 {
3522         struct drm_device *dev = crtc->dev;
3523         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3524         struct drm_plane *plane;
3525         struct intel_plane *intel_plane;
3526
3527         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3528                 intel_plane = to_intel_plane(plane);
3529                 if (intel_plane->pipe == pipe)
3530                         intel_plane_disable(&intel_plane->base);
3531         }
3532 }
3533
3534 void hsw_enable_ips(struct intel_crtc *crtc)
3535 {
3536         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3537
3538         if (!crtc->config.ips_enabled)
3539                 return;
3540
3541         /* We can only enable IPS after we enable a plane and wait for a vblank.
3542          * We guarantee that the plane is enabled by calling intel_enable_ips
3543          * only after intel_enable_plane. And intel_enable_plane already waits
3544          * for a vblank, so all we need to do here is to enable the IPS bit. */
3545         assert_plane_enabled(dev_priv, crtc->plane);
3546         if (IS_BROADWELL(crtc->base.dev)) {
3547                 mutex_lock(&dev_priv->rps.hw_lock);
3548                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3549                 mutex_unlock(&dev_priv->rps.hw_lock);
3550                 /* Quoting Art Runyan: "its not safe to expect any particular
3551                  * value in IPS_CTL bit 31 after enabling IPS through the
3552                  * mailbox." Moreover, the mailbox may return a bogus state,
3553                  * so we need to just enable it and continue on.
3554                  */
3555         } else {
3556                 I915_WRITE(IPS_CTL, IPS_ENABLE);
3557                 /* The bit only becomes 1 in the next vblank, so this wait here
3558                  * is essentially intel_wait_for_vblank. If we don't have this
3559                  * and don't wait for vblanks until the end of crtc_enable, then
3560                  * the HW state readout code will complain that the expected
3561                  * IPS_CTL value is not the one we read. */
3562                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3563                         DRM_ERROR("Timed out waiting for IPS enable\n");
3564         }
3565 }
3566
3567 void hsw_disable_ips(struct intel_crtc *crtc)
3568 {
3569         struct drm_device *dev = crtc->base.dev;
3570         struct drm_i915_private *dev_priv = dev->dev_private;
3571
3572         if (!crtc->config.ips_enabled)
3573                 return;
3574
3575         assert_plane_enabled(dev_priv, crtc->plane);
3576         if (IS_BROADWELL(dev)) {
3577                 mutex_lock(&dev_priv->rps.hw_lock);
3578                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3579                 mutex_unlock(&dev_priv->rps.hw_lock);
3580                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3581                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3582                         DRM_ERROR("Timed out waiting for IPS disable\n");
3583         } else {
3584                 I915_WRITE(IPS_CTL, 0);
3585                 POSTING_READ(IPS_CTL);
3586         }
3587
3588         /* We need to wait for a vblank before we can disable the plane. */
3589         intel_wait_for_vblank(dev, crtc->pipe);
3590 }
3591
3592 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3593 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3594 {
3595         struct drm_device *dev = crtc->dev;
3596         struct drm_i915_private *dev_priv = dev->dev_private;
3597         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3598         enum pipe pipe = intel_crtc->pipe;
3599         int palreg = PALETTE(pipe);
3600         int i;
3601         bool reenable_ips = false;
3602
3603         /* The clocks have to be on to load the palette. */
3604         if (!crtc->enabled || !intel_crtc->active)
3605                 return;
3606
3607         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3608                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3609                         assert_dsi_pll_enabled(dev_priv);
3610                 else
3611                         assert_pll_enabled(dev_priv, pipe);
3612         }
3613
3614         /* use legacy palette for Ironlake */
3615         if (HAS_PCH_SPLIT(dev))
3616                 palreg = LGC_PALETTE(pipe);
3617
3618         /* Workaround : Do not read or write the pipe palette/gamma data while
3619          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3620          */
3621         if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3622             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3623              GAMMA_MODE_MODE_SPLIT)) {
3624                 hsw_disable_ips(intel_crtc);
3625                 reenable_ips = true;
3626         }
3627
3628         for (i = 0; i < 256; i++) {
3629                 I915_WRITE(palreg + 4 * i,
3630                            (intel_crtc->lut_r[i] << 16) |
3631                            (intel_crtc->lut_g[i] << 8) |
3632                            intel_crtc->lut_b[i]);
3633         }
3634
3635         if (reenable_ips)
3636                 hsw_enable_ips(intel_crtc);
3637 }
3638
3639 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3640 {
3641         struct drm_device *dev = crtc->dev;
3642         struct drm_i915_private *dev_priv = dev->dev_private;
3643         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3644         struct intel_encoder *encoder;
3645         int pipe = intel_crtc->pipe;
3646         int plane = intel_crtc->plane;
3647
3648         WARN_ON(!crtc->enabled);
3649
3650         if (intel_crtc->active)
3651                 return;
3652
3653         intel_crtc->active = true;
3654
3655         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3656         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3657
3658         for_each_encoder_on_crtc(dev, crtc, encoder)
3659                 if (encoder->pre_enable)
3660                         encoder->pre_enable(encoder);
3661
3662         if (intel_crtc->config.has_pch_encoder) {
3663                 /* Note: FDI PLL enabling _must_ be done before we enable the
3664                  * cpu pipes, hence this is separate from all the other fdi/pch
3665                  * enabling. */
3666                 ironlake_fdi_pll_enable(intel_crtc);
3667         } else {
3668                 assert_fdi_tx_disabled(dev_priv, pipe);
3669                 assert_fdi_rx_disabled(dev_priv, pipe);
3670         }
3671
3672         ironlake_pfit_enable(intel_crtc);
3673
3674         /*
3675          * On ILK+ LUT must be loaded before the pipe is running but with
3676          * clocks enabled
3677          */
3678         intel_crtc_load_lut(crtc);
3679
3680         intel_update_watermarks(crtc);
3681         intel_enable_pipe(intel_crtc);
3682         intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3683         intel_enable_planes(crtc);
3684         intel_crtc_update_cursor(crtc, true);
3685
3686         if (intel_crtc->config.has_pch_encoder)
3687                 ironlake_pch_enable(crtc);
3688
3689         mutex_lock(&dev->struct_mutex);
3690         intel_update_fbc(dev);
3691         mutex_unlock(&dev->struct_mutex);
3692
3693         for_each_encoder_on_crtc(dev, crtc, encoder)
3694                 encoder->enable(encoder);
3695
3696         if (HAS_PCH_CPT(dev))
3697                 cpt_verify_modeset(dev, intel_crtc->pipe);
3698
3699         /*
3700          * There seems to be a race in PCH platform hw (at least on some
3701          * outputs) where an enabled pipe still completes any pageflip right
3702          * away (as if the pipe is off) instead of waiting for vblank. As soon
3703          * as the first vblank happend, everything works as expected. Hence just
3704          * wait for one vblank before returning to avoid strange things
3705          * happening.
3706          */
3707         intel_wait_for_vblank(dev, intel_crtc->pipe);
3708 }
3709
3710 /* IPS only exists on ULT machines and is tied to pipe A. */
3711 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3712 {
3713         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3714 }
3715
3716 static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
3717 {
3718         struct drm_device *dev = crtc->dev;
3719         struct drm_i915_private *dev_priv = dev->dev_private;
3720         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3721         int pipe = intel_crtc->pipe;
3722         int plane = intel_crtc->plane;
3723
3724         intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3725         intel_enable_planes(crtc);
3726         intel_crtc_update_cursor(crtc, true);
3727
3728         hsw_enable_ips(intel_crtc);
3729
3730         mutex_lock(&dev->struct_mutex);
3731         intel_update_fbc(dev);
3732         mutex_unlock(&dev->struct_mutex);
3733 }
3734
3735 static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
3736 {
3737         struct drm_device *dev = crtc->dev;
3738         struct drm_i915_private *dev_priv = dev->dev_private;
3739         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3740         int pipe = intel_crtc->pipe;
3741         int plane = intel_crtc->plane;
3742
3743         intel_crtc_wait_for_pending_flips(crtc);
3744         drm_vblank_off(dev, pipe);
3745
3746         /* FBC must be disabled before disabling the plane on HSW. */
3747         if (dev_priv->fbc.plane == plane)
3748                 intel_disable_fbc(dev);
3749
3750         hsw_disable_ips(intel_crtc);
3751
3752         intel_crtc_update_cursor(crtc, false);
3753         intel_disable_planes(crtc);
3754         intel_disable_primary_hw_plane(dev_priv, plane, pipe);
3755 }
3756
3757 /*
3758  * This implements the workaround described in the "notes" section of the mode
3759  * set sequence documentation. When going from no pipes or single pipe to
3760  * multiple pipes, and planes are enabled after the pipe, we need to wait at
3761  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3762  */
3763 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3764 {
3765         struct drm_device *dev = crtc->base.dev;
3766         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3767
3768         /* We want to get the other_active_crtc only if there's only 1 other
3769          * active crtc. */
3770         list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3771                 if (!crtc_it->active || crtc_it == crtc)
3772                         continue;
3773
3774                 if (other_active_crtc)
3775                         return;
3776
3777                 other_active_crtc = crtc_it;
3778         }
3779         if (!other_active_crtc)
3780                 return;
3781
3782         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3783         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3784 }
3785
3786 static void haswell_crtc_enable(struct drm_crtc *crtc)
3787 {
3788         struct drm_device *dev = crtc->dev;
3789         struct drm_i915_private *dev_priv = dev->dev_private;
3790         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3791         struct intel_encoder *encoder;
3792         int pipe = intel_crtc->pipe;
3793
3794         WARN_ON(!crtc->enabled);
3795
3796         if (intel_crtc->active)
3797                 return;
3798
3799         intel_crtc->active = true;
3800
3801         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3802         if (intel_crtc->config.has_pch_encoder)
3803                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3804
3805         if (intel_crtc->config.has_pch_encoder)
3806                 dev_priv->display.fdi_link_train(crtc);
3807
3808         for_each_encoder_on_crtc(dev, crtc, encoder)
3809                 if (encoder->pre_enable)
3810                         encoder->pre_enable(encoder);
3811
3812         intel_ddi_enable_pipe_clock(intel_crtc);
3813
3814         ironlake_pfit_enable(intel_crtc);
3815
3816         /*
3817          * On ILK+ LUT must be loaded before the pipe is running but with
3818          * clocks enabled
3819          */
3820         intel_crtc_load_lut(crtc);
3821
3822         intel_ddi_set_pipe_settings(crtc);
3823         intel_ddi_enable_transcoder_func(crtc);
3824
3825         intel_update_watermarks(crtc);
3826         intel_enable_pipe(intel_crtc);
3827
3828         if (intel_crtc->config.has_pch_encoder)
3829                 lpt_pch_enable(crtc);
3830
3831         for_each_encoder_on_crtc(dev, crtc, encoder) {
3832                 encoder->enable(encoder);
3833                 intel_opregion_notify_encoder(encoder, true);
3834         }
3835
3836         /* If we change the relative order between pipe/planes enabling, we need
3837          * to change the workaround. */
3838         haswell_mode_set_planes_workaround(intel_crtc);
3839         haswell_crtc_enable_planes(crtc);
3840 }
3841
3842 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3843 {
3844         struct drm_device *dev = crtc->base.dev;
3845         struct drm_i915_private *dev_priv = dev->dev_private;
3846         int pipe = crtc->pipe;
3847
3848         /* To avoid upsetting the power well on haswell only disable the pfit if
3849          * it's in use. The hw state code will make sure we get this right. */
3850         if (crtc->config.pch_pfit.enabled) {
3851                 I915_WRITE(PF_CTL(pipe), 0);
3852                 I915_WRITE(PF_WIN_POS(pipe), 0);
3853                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3854         }
3855 }
3856
3857 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3858 {
3859         struct drm_device *dev = crtc->dev;
3860         struct drm_i915_private *dev_priv = dev->dev_private;
3861         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3862         struct intel_encoder *encoder;
3863         int pipe = intel_crtc->pipe;
3864         int plane = intel_crtc->plane;
3865         u32 reg, temp;
3866
3867
3868         if (!intel_crtc->active)
3869                 return;
3870
3871         for_each_encoder_on_crtc(dev, crtc, encoder)
3872                 encoder->disable(encoder);
3873
3874         intel_crtc_wait_for_pending_flips(crtc);
3875         drm_vblank_off(dev, pipe);
3876
3877         if (dev_priv->fbc.plane == plane)
3878                 intel_disable_fbc(dev);
3879
3880         intel_crtc_update_cursor(crtc, false);
3881         intel_disable_planes(crtc);
3882         intel_disable_primary_hw_plane(dev_priv, plane, pipe);
3883
3884         if (intel_crtc->config.has_pch_encoder)
3885                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3886
3887         intel_disable_pipe(dev_priv, pipe);
3888
3889         ironlake_pfit_disable(intel_crtc);
3890
3891         for_each_encoder_on_crtc(dev, crtc, encoder)
3892                 if (encoder->post_disable)
3893                         encoder->post_disable(encoder);
3894
3895         if (intel_crtc->config.has_pch_encoder) {
3896                 ironlake_fdi_disable(crtc);
3897
3898                 ironlake_disable_pch_transcoder(dev_priv, pipe);
3899                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3900
3901                 if (HAS_PCH_CPT(dev)) {
3902                         /* disable TRANS_DP_CTL */
3903                         reg = TRANS_DP_CTL(pipe);
3904                         temp = I915_READ(reg);
3905                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3906                                   TRANS_DP_PORT_SEL_MASK);
3907                         temp |= TRANS_DP_PORT_SEL_NONE;
3908                         I915_WRITE(reg, temp);
3909
3910                         /* disable DPLL_SEL */
3911                         temp = I915_READ(PCH_DPLL_SEL);
3912                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3913                         I915_WRITE(PCH_DPLL_SEL, temp);
3914                 }
3915
3916                 /* disable PCH DPLL */
3917                 intel_disable_shared_dpll(intel_crtc);
3918
3919                 ironlake_fdi_pll_disable(intel_crtc);
3920         }
3921
3922         intel_crtc->active = false;
3923         intel_update_watermarks(crtc);
3924
3925         mutex_lock(&dev->struct_mutex);
3926         intel_update_fbc(dev);
3927         mutex_unlock(&dev->struct_mutex);
3928 }
3929
3930 static void haswell_crtc_disable(struct drm_crtc *crtc)
3931 {
3932         struct drm_device *dev = crtc->dev;
3933         struct drm_i915_private *dev_priv = dev->dev_private;
3934         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3935         struct intel_encoder *encoder;
3936         int pipe = intel_crtc->pipe;
3937         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3938
3939         if (!intel_crtc->active)
3940                 return;
3941
3942         haswell_crtc_disable_planes(crtc);
3943
3944         for_each_encoder_on_crtc(dev, crtc, encoder) {
3945                 intel_opregion_notify_encoder(encoder, false);
3946                 encoder->disable(encoder);
3947         }
3948
3949         if (intel_crtc->config.has_pch_encoder)
3950                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3951         intel_disable_pipe(dev_priv, pipe);
3952
3953         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3954
3955         ironlake_pfit_disable(intel_crtc);
3956
3957         intel_ddi_disable_pipe_clock(intel_crtc);
3958
3959         for_each_encoder_on_crtc(dev, crtc, encoder)
3960                 if (encoder->post_disable)
3961                         encoder->post_disable(encoder);
3962
3963         if (intel_crtc->config.has_pch_encoder) {
3964                 lpt_disable_pch_transcoder(dev_priv);
3965                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3966                 intel_ddi_fdi_disable(crtc);
3967         }
3968
3969         intel_crtc->active = false;
3970         intel_update_watermarks(crtc);
3971
3972         mutex_lock(&dev->struct_mutex);
3973         intel_update_fbc(dev);
3974         mutex_unlock(&dev->struct_mutex);
3975 }
3976
3977 static void ironlake_crtc_off(struct drm_crtc *crtc)
3978 {
3979         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3980         intel_put_shared_dpll(intel_crtc);
3981 }
3982
3983 static void haswell_crtc_off(struct drm_crtc *crtc)
3984 {
3985         intel_ddi_put_crtc_pll(crtc);
3986 }
3987
3988 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3989 {
3990         if (!enable && intel_crtc->overlay) {
3991                 struct drm_device *dev = intel_crtc->base.dev;
3992                 struct drm_i915_private *dev_priv = dev->dev_private;
3993
3994                 mutex_lock(&dev->struct_mutex);
3995                 dev_priv->mm.interruptible = false;
3996                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3997                 dev_priv->mm.interruptible = true;
3998                 mutex_unlock(&dev->struct_mutex);
3999         }
4000
4001         /* Let userspace switch the overlay on again. In most cases userspace
4002          * has to recompute where to put it anyway.
4003          */
4004 }
4005
4006 /**
4007  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
4008  * cursor plane briefly if not already running after enabling the display
4009  * plane.
4010  * This workaround avoids occasional blank screens when self refresh is
4011  * enabled.
4012  */
4013 static void
4014 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
4015 {
4016         u32 cntl = I915_READ(CURCNTR(pipe));
4017
4018         if ((cntl & CURSOR_MODE) == 0) {
4019                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
4020
4021                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
4022                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
4023                 intel_wait_for_vblank(dev_priv->dev, pipe);
4024                 I915_WRITE(CURCNTR(pipe), cntl);
4025                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
4026                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
4027         }
4028 }
4029
4030 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4031 {
4032         struct drm_device *dev = crtc->base.dev;
4033         struct drm_i915_private *dev_priv = dev->dev_private;
4034         struct intel_crtc_config *pipe_config = &crtc->config;
4035
4036         if (!crtc->config.gmch_pfit.control)
4037                 return;
4038
4039         /*
4040          * The panel fitter should only be adjusted whilst the pipe is disabled,
4041          * according to register description and PRM.
4042          */
4043         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4044         assert_pipe_disabled(dev_priv, crtc->pipe);
4045
4046         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4047         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4048
4049         /* Border color in case we don't scale up to the full screen. Black by
4050          * default, change to something else for debugging. */
4051         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4052 }
4053
4054 #define for_each_power_domain(domain, mask)                             \
4055         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4056                 if ((1 << (domain)) & (mask))
4057
4058 enum intel_display_power_domain
4059 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4060 {
4061         struct drm_device *dev = intel_encoder->base.dev;
4062         struct intel_digital_port *intel_dig_port;
4063
4064         switch (intel_encoder->type) {
4065         case INTEL_OUTPUT_UNKNOWN:
4066                 /* Only DDI platforms should ever use this output type */
4067                 WARN_ON_ONCE(!HAS_DDI(dev));
4068         case INTEL_OUTPUT_DISPLAYPORT:
4069         case INTEL_OUTPUT_HDMI:
4070         case INTEL_OUTPUT_EDP:
4071                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4072                 switch (intel_dig_port->port) {
4073                 case PORT_A:
4074                         return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4075                 case PORT_B:
4076                         return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4077                 case PORT_C:
4078                         return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4079                 case PORT_D:
4080                         return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4081                 default:
4082                         WARN_ON_ONCE(1);
4083                         return POWER_DOMAIN_PORT_OTHER;
4084                 }
4085         case INTEL_OUTPUT_ANALOG:
4086                 return POWER_DOMAIN_PORT_CRT;
4087         case INTEL_OUTPUT_DSI:
4088                 return POWER_DOMAIN_PORT_DSI;
4089         default:
4090                 return POWER_DOMAIN_PORT_OTHER;
4091         }
4092 }
4093
4094 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4095 {
4096         struct drm_device *dev = crtc->dev;
4097         struct intel_encoder *intel_encoder;
4098         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4099         enum pipe pipe = intel_crtc->pipe;
4100         bool pfit_enabled = intel_crtc->config.pch_pfit.enabled;
4101         unsigned long mask;
4102         enum transcoder transcoder;
4103
4104         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4105
4106         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4107         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4108         if (pfit_enabled)
4109                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4110
4111         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4112                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4113
4114         return mask;
4115 }
4116
4117 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4118                                   bool enable)
4119 {
4120         if (dev_priv->power_domains.init_power_on == enable)
4121                 return;
4122
4123         if (enable)
4124                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4125         else
4126                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4127
4128         dev_priv->power_domains.init_power_on = enable;
4129 }
4130
4131 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4132 {
4133         struct drm_i915_private *dev_priv = dev->dev_private;
4134         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4135         struct intel_crtc *crtc;
4136
4137         /*
4138          * First get all needed power domains, then put all unneeded, to avoid
4139          * any unnecessary toggling of the power wells.
4140          */
4141         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
4142                 enum intel_display_power_domain domain;
4143
4144                 if (!crtc->base.enabled)
4145                         continue;
4146
4147                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4148
4149                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4150                         intel_display_power_get(dev_priv, domain);
4151         }
4152
4153         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
4154                 enum intel_display_power_domain domain;
4155
4156                 for_each_power_domain(domain, crtc->enabled_power_domains)
4157                         intel_display_power_put(dev_priv, domain);
4158
4159                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4160         }
4161
4162         intel_display_set_init_power(dev_priv, false);
4163 }
4164
4165 int valleyview_get_vco(struct drm_i915_private *dev_priv)
4166 {
4167         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4168
4169         /* Obtain SKU information */
4170         mutex_lock(&dev_priv->dpio_lock);
4171         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4172                 CCK_FUSE_HPLL_FREQ_MASK;
4173         mutex_unlock(&dev_priv->dpio_lock);
4174
4175         return vco_freq[hpll_freq];
4176 }
4177
4178 /* Adjust CDclk dividers to allow high res or save power if possible */
4179 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4180 {
4181         struct drm_i915_private *dev_priv = dev->dev_private;
4182         u32 val, cmd;
4183
4184         WARN_ON(valleyview_cur_cdclk(dev_priv) != dev_priv->vlv_cdclk_freq);
4185         dev_priv->vlv_cdclk_freq = cdclk;
4186
4187         if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
4188                 cmd = 2;
4189         else if (cdclk == 266)
4190                 cmd = 1;
4191         else
4192                 cmd = 0;
4193
4194         mutex_lock(&dev_priv->rps.hw_lock);
4195         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4196         val &= ~DSPFREQGUAR_MASK;
4197         val |= (cmd << DSPFREQGUAR_SHIFT);
4198         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4199         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4200                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4201                      50)) {
4202                 DRM_ERROR("timed out waiting for CDclk change\n");
4203         }
4204         mutex_unlock(&dev_priv->rps.hw_lock);
4205
4206         if (cdclk == 400) {
4207                 u32 divider, vco;
4208
4209                 vco = valleyview_get_vco(dev_priv);
4210                 divider = ((vco << 1) / cdclk) - 1;
4211
4212                 mutex_lock(&dev_priv->dpio_lock);
4213                 /* adjust cdclk divider */
4214                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4215                 val &= ~0xf;
4216                 val |= divider;
4217                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4218                 mutex_unlock(&dev_priv->dpio_lock);
4219         }
4220
4221         mutex_lock(&dev_priv->dpio_lock);
4222         /* adjust self-refresh exit latency value */
4223         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4224         val &= ~0x7f;
4225
4226         /*
4227          * For high bandwidth configs, we set a higher latency in the bunit
4228          * so that the core display fetch happens in time to avoid underruns.
4229          */
4230         if (cdclk == 400)
4231                 val |= 4500 / 250; /* 4.5 usec */
4232         else
4233                 val |= 3000 / 250; /* 3.0 usec */
4234         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4235         mutex_unlock(&dev_priv->dpio_lock);
4236
4237         /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4238         intel_i2c_reset(dev);
4239 }
4240
4241 int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4242 {
4243         int cur_cdclk, vco;
4244         int divider;
4245
4246         vco = valleyview_get_vco(dev_priv);
4247
4248         mutex_lock(&dev_priv->dpio_lock);
4249         divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4250         mutex_unlock(&dev_priv->dpio_lock);
4251
4252         divider &= 0xf;
4253
4254         cur_cdclk = (vco << 1) / (divider + 1);
4255
4256         return cur_cdclk;
4257 }
4258
4259 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4260                                  int max_pixclk)
4261 {
4262         /*
4263          * Really only a few cases to deal with, as only 4 CDclks are supported:
4264          *   200MHz
4265          *   267MHz
4266          *   320MHz
4267          *   400MHz
4268          * So we check to see whether we're above 90% of the lower bin and
4269          * adjust if needed.
4270          */
4271         if (max_pixclk > 288000) {
4272                 return 400;
4273         } else if (max_pixclk > 240000) {
4274                 return 320;
4275         } else
4276                 return 266;
4277         /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4278 }
4279
4280 /* compute the max pixel clock for new configuration */
4281 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4282 {
4283         struct drm_device *dev = dev_priv->dev;
4284         struct intel_crtc *intel_crtc;
4285         int max_pixclk = 0;
4286
4287         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4288                             base.head) {
4289                 if (intel_crtc->new_enabled)
4290                         max_pixclk = max(max_pixclk,
4291                                          intel_crtc->new_config->adjusted_mode.crtc_clock);
4292         }
4293
4294         return max_pixclk;
4295 }
4296
4297 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4298                                             unsigned *prepare_pipes)
4299 {
4300         struct drm_i915_private *dev_priv = dev->dev_private;
4301         struct intel_crtc *intel_crtc;
4302         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4303
4304         if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4305             dev_priv->vlv_cdclk_freq)
4306                 return;
4307
4308         /* disable/enable all currently active pipes while we change cdclk */
4309         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4310                             base.head)
4311                 if (intel_crtc->base.enabled)
4312                         *prepare_pipes |= (1 << intel_crtc->pipe);
4313 }
4314
4315 static void valleyview_modeset_global_resources(struct drm_device *dev)
4316 {
4317         struct drm_i915_private *dev_priv = dev->dev_private;
4318         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4319         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4320
4321         if (req_cdclk != dev_priv->vlv_cdclk_freq)
4322                 valleyview_set_cdclk(dev, req_cdclk);
4323         modeset_update_crtc_power_domains(dev);
4324 }
4325
4326 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4327 {
4328         struct drm_device *dev = crtc->dev;
4329         struct drm_i915_private *dev_priv = dev->dev_private;
4330         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4331         struct intel_encoder *encoder;
4332         int pipe = intel_crtc->pipe;
4333         int plane = intel_crtc->plane;
4334         bool is_dsi;
4335
4336         WARN_ON(!crtc->enabled);
4337
4338         if (intel_crtc->active)
4339                 return;
4340
4341         intel_crtc->active = true;
4342
4343         for_each_encoder_on_crtc(dev, crtc, encoder)
4344                 if (encoder->pre_pll_enable)
4345                         encoder->pre_pll_enable(encoder);
4346
4347         is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4348
4349         if (!is_dsi)
4350                 vlv_enable_pll(intel_crtc);
4351
4352         for_each_encoder_on_crtc(dev, crtc, encoder)
4353                 if (encoder->pre_enable)
4354                         encoder->pre_enable(encoder);
4355
4356         i9xx_pfit_enable(intel_crtc);
4357
4358         intel_crtc_load_lut(crtc);
4359
4360         intel_update_watermarks(crtc);
4361         intel_enable_pipe(intel_crtc);
4362         intel_wait_for_vblank(dev_priv->dev, pipe);
4363         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4364
4365         intel_enable_primary_hw_plane(dev_priv, plane, pipe);
4366         intel_enable_planes(crtc);
4367         intel_crtc_update_cursor(crtc, true);
4368
4369         intel_update_fbc(dev);
4370
4371         for_each_encoder_on_crtc(dev, crtc, encoder)
4372                 encoder->enable(encoder);
4373 }
4374
4375 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4376 {
4377         struct drm_device *dev = crtc->dev;
4378         struct drm_i915_private *dev_priv = dev->dev_private;
4379         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4380         struct intel_encoder *encoder;
4381         int pipe = intel_crtc->pipe;
4382         int plane = intel_crtc->plane;
4383
4384         WARN_ON(!crtc->enabled);
4385
4386         if (intel_crtc->active)
4387                 return;
4388
4389         intel_crtc->active = true;
4390
4391         for_each_encoder_on_crtc(dev, crtc, encoder)
4392                 if (encoder->pre_enable)
4393                         encoder->pre_enable(encoder);
4394
4395         i9xx_enable_pll(intel_crtc);
4396
4397         i9xx_pfit_enable(intel_crtc);
4398
4399         intel_crtc_load_lut(crtc);
4400
4401         intel_update_watermarks(crtc);
4402         intel_enable_pipe(intel_crtc);
4403         intel_wait_for_vblank(dev_priv->dev, pipe);
4404         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4405
4406         intel_enable_primary_hw_plane(dev_priv, plane, pipe);
4407         intel_enable_planes(crtc);
4408         /* The fixup needs to happen before cursor is enabled */
4409         if (IS_G4X(dev))
4410                 g4x_fixup_plane(dev_priv, pipe);
4411         intel_crtc_update_cursor(crtc, true);
4412
4413         /* Give the overlay scaler a chance to enable if it's on this pipe */
4414         intel_crtc_dpms_overlay(intel_crtc, true);
4415
4416         intel_update_fbc(dev);
4417
4418         for_each_encoder_on_crtc(dev, crtc, encoder)
4419                 encoder->enable(encoder);
4420 }
4421
4422 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4423 {
4424         struct drm_device *dev = crtc->base.dev;
4425         struct drm_i915_private *dev_priv = dev->dev_private;
4426
4427         if (!crtc->config.gmch_pfit.control)
4428                 return;
4429
4430         assert_pipe_disabled(dev_priv, crtc->pipe);
4431
4432         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4433                          I915_READ(PFIT_CONTROL));
4434         I915_WRITE(PFIT_CONTROL, 0);
4435 }
4436
4437 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4438 {
4439         struct drm_device *dev = crtc->dev;
4440         struct drm_i915_private *dev_priv = dev->dev_private;
4441         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4442         struct intel_encoder *encoder;
4443         int pipe = intel_crtc->pipe;
4444         int plane = intel_crtc->plane;
4445
4446         if (!intel_crtc->active)
4447                 return;
4448
4449         for_each_encoder_on_crtc(dev, crtc, encoder)
4450                 encoder->disable(encoder);
4451
4452         /* Give the overlay scaler a chance to disable if it's on this pipe */
4453         intel_crtc_wait_for_pending_flips(crtc);
4454         drm_vblank_off(dev, pipe);
4455
4456         if (dev_priv->fbc.plane == plane)
4457                 intel_disable_fbc(dev);
4458
4459         intel_crtc_dpms_overlay(intel_crtc, false);
4460         intel_crtc_update_cursor(crtc, false);
4461         intel_disable_planes(crtc);
4462         intel_disable_primary_hw_plane(dev_priv, plane, pipe);
4463
4464         intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4465         intel_disable_pipe(dev_priv, pipe);
4466
4467         i9xx_pfit_disable(intel_crtc);
4468
4469         for_each_encoder_on_crtc(dev, crtc, encoder)
4470                 if (encoder->post_disable)
4471                         encoder->post_disable(encoder);
4472
4473         if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
4474                 vlv_disable_pll(dev_priv, pipe);
4475         else if (!IS_VALLEYVIEW(dev))
4476                 i9xx_disable_pll(dev_priv, pipe);
4477
4478         intel_crtc->active = false;
4479         intel_update_watermarks(crtc);
4480
4481         intel_update_fbc(dev);
4482 }
4483
4484 static void i9xx_crtc_off(struct drm_crtc *crtc)
4485 {
4486 }
4487
4488 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4489                                     bool enabled)
4490 {
4491         struct drm_device *dev = crtc->dev;
4492         struct drm_i915_master_private *master_priv;
4493         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4494         int pipe = intel_crtc->pipe;
4495
4496         if (!dev->primary->master)
4497                 return;
4498
4499         master_priv = dev->primary->master->driver_priv;
4500         if (!master_priv->sarea_priv)
4501                 return;
4502
4503         switch (pipe) {
4504         case 0:
4505                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4506                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4507                 break;
4508         case 1:
4509                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4510                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4511                 break;
4512         default:
4513                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4514                 break;
4515         }
4516 }
4517
4518 /**
4519  * Sets the power management mode of the pipe and plane.
4520  */
4521 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4522 {
4523         struct drm_device *dev = crtc->dev;
4524         struct drm_i915_private *dev_priv = dev->dev_private;
4525         struct intel_encoder *intel_encoder;
4526         bool enable = false;
4527
4528         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4529                 enable |= intel_encoder->connectors_active;
4530
4531         if (enable)
4532                 dev_priv->display.crtc_enable(crtc);
4533         else
4534                 dev_priv->display.crtc_disable(crtc);
4535
4536         intel_crtc_update_sarea(crtc, enable);
4537 }
4538
4539 static void intel_crtc_disable(struct drm_crtc *crtc)
4540 {
4541         struct drm_device *dev = crtc->dev;
4542         struct drm_connector *connector;
4543         struct drm_i915_private *dev_priv = dev->dev_private;
4544         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4545
4546         /* crtc should still be enabled when we disable it. */
4547         WARN_ON(!crtc->enabled);
4548
4549         dev_priv->display.crtc_disable(crtc);
4550         intel_crtc->eld_vld = false;
4551         intel_crtc_update_sarea(crtc, false);
4552         dev_priv->display.off(crtc);
4553
4554         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4555         assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4556         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4557
4558         if (crtc->primary->fb) {
4559                 mutex_lock(&dev->struct_mutex);
4560                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->primary->fb)->obj);
4561                 mutex_unlock(&dev->struct_mutex);
4562                 crtc->primary->fb = NULL;
4563         }
4564
4565         /* Update computed state. */
4566         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4567                 if (!connector->encoder || !connector->encoder->crtc)
4568                         continue;
4569
4570                 if (connector->encoder->crtc != crtc)
4571                         continue;
4572
4573                 connector->dpms = DRM_MODE_DPMS_OFF;
4574                 to_intel_encoder(connector->encoder)->connectors_active = false;
4575         }
4576 }
4577
4578 void intel_encoder_destroy(struct drm_encoder *encoder)
4579 {
4580         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4581
4582         drm_encoder_cleanup(encoder);
4583         kfree(intel_encoder);
4584 }
4585
4586 /* Simple dpms helper for encoders with just one connector, no cloning and only
4587  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4588  * state of the entire output pipe. */
4589 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4590 {
4591         if (mode == DRM_MODE_DPMS_ON) {
4592                 encoder->connectors_active = true;
4593
4594                 intel_crtc_update_dpms(encoder->base.crtc);
4595         } else {
4596                 encoder->connectors_active = false;
4597
4598                 intel_crtc_update_dpms(encoder->base.crtc);
4599         }
4600 }
4601
4602 /* Cross check the actual hw state with our own modeset state tracking (and it's
4603  * internal consistency). */
4604 static void intel_connector_check_state(struct intel_connector *connector)
4605 {
4606         if (connector->get_hw_state(connector)) {
4607                 struct intel_encoder *encoder = connector->encoder;
4608                 struct drm_crtc *crtc;
4609                 bool encoder_enabled;
4610                 enum pipe pipe;
4611
4612                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4613                               connector->base.base.id,
4614                               drm_get_connector_name(&connector->base));
4615
4616                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4617                      "wrong connector dpms state\n");
4618                 WARN(connector->base.encoder != &encoder->base,
4619                      "active connector not linked to encoder\n");
4620                 WARN(!encoder->connectors_active,
4621                      "encoder->connectors_active not set\n");
4622
4623                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4624                 WARN(!encoder_enabled, "encoder not enabled\n");
4625                 if (WARN_ON(!encoder->base.crtc))
4626                         return;
4627
4628                 crtc = encoder->base.crtc;
4629
4630                 WARN(!crtc->enabled, "crtc not enabled\n");
4631                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4632                 WARN(pipe != to_intel_crtc(crtc)->pipe,
4633                      "encoder active on the wrong pipe\n");
4634         }
4635 }
4636
4637 /* Even simpler default implementation, if there's really no special case to
4638  * consider. */
4639 void intel_connector_dpms(struct drm_connector *connector, int mode)
4640 {
4641         /* All the simple cases only support two dpms states. */
4642         if (mode != DRM_MODE_DPMS_ON)
4643                 mode = DRM_MODE_DPMS_OFF;
4644
4645         if (mode == connector->dpms)
4646                 return;
4647
4648         connector->dpms = mode;
4649
4650         /* Only need to change hw state when actually enabled */
4651         if (connector->encoder)
4652                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
4653
4654         intel_modeset_check_state(connector->dev);
4655 }
4656
4657 /* Simple connector->get_hw_state implementation for encoders that support only
4658  * one connector and no cloning and hence the encoder state determines the state
4659  * of the connector. */
4660 bool intel_connector_get_hw_state(struct intel_connector *connector)
4661 {
4662         enum pipe pipe = 0;
4663         struct intel_encoder *encoder = connector->encoder;
4664
4665         return encoder->get_hw_state(encoder, &pipe);
4666 }
4667
4668 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4669                                      struct intel_crtc_config *pipe_config)
4670 {
4671         struct drm_i915_private *dev_priv = dev->dev_private;
4672         struct intel_crtc *pipe_B_crtc =
4673                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4674
4675         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4676                       pipe_name(pipe), pipe_config->fdi_lanes);
4677         if (pipe_config->fdi_lanes > 4) {
4678                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4679                               pipe_name(pipe), pipe_config->fdi_lanes);
4680                 return false;
4681         }
4682
4683         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4684                 if (pipe_config->fdi_lanes > 2) {
4685                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4686                                       pipe_config->fdi_lanes);
4687                         return false;
4688                 } else {
4689                         return true;
4690                 }
4691         }
4692
4693         if (INTEL_INFO(dev)->num_pipes == 2)
4694                 return true;
4695
4696         /* Ivybridge 3 pipe is really complicated */
4697         switch (pipe) {
4698         case PIPE_A:
4699                 return true;
4700         case PIPE_B:
4701                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4702                     pipe_config->fdi_lanes > 2) {
4703                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4704                                       pipe_name(pipe), pipe_config->fdi_lanes);
4705                         return false;
4706                 }
4707                 return true;
4708         case PIPE_C:
4709                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4710                     pipe_B_crtc->config.fdi_lanes <= 2) {
4711                         if (pipe_config->fdi_lanes > 2) {
4712                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4713                                               pipe_name(pipe), pipe_config->fdi_lanes);
4714                                 return false;
4715                         }
4716                 } else {
4717                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4718                         return false;
4719                 }
4720                 return true;
4721         default:
4722                 BUG();
4723         }
4724 }
4725
4726 #define RETRY 1
4727 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4728                                        struct intel_crtc_config *pipe_config)
4729 {
4730         struct drm_device *dev = intel_crtc->base.dev;
4731         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4732         int lane, link_bw, fdi_dotclock;
4733         bool setup_ok, needs_recompute = false;
4734
4735 retry:
4736         /* FDI is a binary signal running at ~2.7GHz, encoding
4737          * each output octet as 10 bits. The actual frequency
4738          * is stored as a divider into a 100MHz clock, and the
4739          * mode pixel clock is stored in units of 1KHz.
4740          * Hence the bw of each lane in terms of the mode signal
4741          * is:
4742          */
4743         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4744
4745         fdi_dotclock = adjusted_mode->crtc_clock;
4746
4747         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4748                                            pipe_config->pipe_bpp);
4749
4750         pipe_config->fdi_lanes = lane;
4751
4752         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4753                                link_bw, &pipe_config->fdi_m_n);
4754
4755         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4756                                             intel_crtc->pipe, pipe_config);
4757         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4758                 pipe_config->pipe_bpp -= 2*3;
4759                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4760                               pipe_config->pipe_bpp);
4761                 needs_recompute = true;
4762                 pipe_config->bw_constrained = true;
4763
4764                 goto retry;
4765         }
4766
4767         if (needs_recompute)
4768                 return RETRY;
4769
4770         return setup_ok ? 0 : -EINVAL;
4771 }
4772
4773 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4774                                    struct intel_crtc_config *pipe_config)
4775 {
4776         pipe_config->ips_enabled = i915.enable_ips &&
4777                                    hsw_crtc_supports_ips(crtc) &&
4778                                    pipe_config->pipe_bpp <= 24;
4779 }
4780
4781 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4782                                      struct intel_crtc_config *pipe_config)
4783 {
4784         struct drm_device *dev = crtc->base.dev;
4785         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4786
4787         /* FIXME should check pixel clock limits on all platforms */
4788         if (INTEL_INFO(dev)->gen < 4) {
4789                 struct drm_i915_private *dev_priv = dev->dev_private;
4790                 int clock_limit =
4791                         dev_priv->display.get_display_clock_speed(dev);
4792
4793                 /*
4794                  * Enable pixel doubling when the dot clock
4795                  * is > 90% of the (display) core speed.
4796                  *
4797                  * GDG double wide on either pipe,
4798                  * otherwise pipe A only.
4799                  */
4800                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4801                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
4802                         clock_limit *= 2;
4803                         pipe_config->double_wide = true;
4804                 }
4805
4806                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
4807                         return -EINVAL;
4808         }
4809
4810         /*
4811          * Pipe horizontal size must be even in:
4812          * - DVO ganged mode
4813          * - LVDS dual channel mode
4814          * - Double wide pipe
4815          */
4816         if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4817              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4818                 pipe_config->pipe_src_w &= ~1;
4819
4820         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4821          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4822          */
4823         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4824                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4825                 return -EINVAL;
4826
4827         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4828                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4829         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4830                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4831                  * for lvds. */
4832                 pipe_config->pipe_bpp = 8*3;
4833         }
4834
4835         if (HAS_IPS(dev))
4836                 hsw_compute_ips_config(crtc, pipe_config);
4837
4838         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4839          * clock survives for now. */
4840         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4841                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4842
4843         if (pipe_config->has_pch_encoder)
4844                 return ironlake_fdi_compute_config(crtc, pipe_config);
4845
4846         return 0;
4847 }
4848
4849 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4850 {
4851         return 400000; /* FIXME */
4852 }
4853
4854 static int i945_get_display_clock_speed(struct drm_device *dev)
4855 {
4856         return 400000;
4857 }
4858
4859 static int i915_get_display_clock_speed(struct drm_device *dev)
4860 {
4861         return 333000;
4862 }
4863
4864 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4865 {
4866         return 200000;
4867 }
4868
4869 static int pnv_get_display_clock_speed(struct drm_device *dev)
4870 {
4871         u16 gcfgc = 0;
4872
4873         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4874
4875         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4876         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4877                 return 267000;
4878         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4879                 return 333000;
4880         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4881                 return 444000;
4882         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4883                 return 200000;
4884         default:
4885                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4886         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4887                 return 133000;
4888         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4889                 return 167000;
4890         }
4891 }
4892
4893 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4894 {
4895         u16 gcfgc = 0;
4896
4897         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4898
4899         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4900                 return 133000;
4901         else {
4902                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4903                 case GC_DISPLAY_CLOCK_333_MHZ:
4904                         return 333000;
4905                 default:
4906                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4907                         return 190000;
4908                 }
4909         }
4910 }
4911
4912 static int i865_get_display_clock_speed(struct drm_device *dev)
4913 {
4914         return 266000;
4915 }
4916
4917 static int i855_get_display_clock_speed(struct drm_device *dev)
4918 {
4919         u16 hpllcc = 0;
4920         /* Assume that the hardware is in the high speed state.  This
4921          * should be the default.
4922          */
4923         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4924         case GC_CLOCK_133_200:
4925         case GC_CLOCK_100_200:
4926                 return 200000;
4927         case GC_CLOCK_166_250:
4928                 return 250000;
4929         case GC_CLOCK_100_133:
4930                 return 133000;
4931         }
4932
4933         /* Shouldn't happen */
4934         return 0;
4935 }
4936
4937 static int i830_get_display_clock_speed(struct drm_device *dev)
4938 {
4939         return 133000;
4940 }
4941
4942 static void
4943 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4944 {
4945         while (*num > DATA_LINK_M_N_MASK ||
4946                *den > DATA_LINK_M_N_MASK) {
4947                 *num >>= 1;
4948                 *den >>= 1;
4949         }
4950 }
4951
4952 static void compute_m_n(unsigned int m, unsigned int n,
4953                         uint32_t *ret_m, uint32_t *ret_n)
4954 {
4955         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4956         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4957         intel_reduce_m_n_ratio(ret_m, ret_n);
4958 }
4959
4960 void
4961 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4962                        int pixel_clock, int link_clock,
4963                        struct intel_link_m_n *m_n)
4964 {
4965         m_n->tu = 64;
4966
4967         compute_m_n(bits_per_pixel * pixel_clock,
4968                     link_clock * nlanes * 8,
4969                     &m_n->gmch_m, &m_n->gmch_n);
4970
4971         compute_m_n(pixel_clock, link_clock,
4972                     &m_n->link_m, &m_n->link_n);
4973 }
4974
4975 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4976 {
4977         if (i915.panel_use_ssc >= 0)
4978                 return i915.panel_use_ssc != 0;
4979         return dev_priv->vbt.lvds_use_ssc
4980                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4981 }
4982
4983 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4984 {
4985         struct drm_device *dev = crtc->dev;
4986         struct drm_i915_private *dev_priv = dev->dev_private;
4987         int refclk;
4988
4989         if (IS_VALLEYVIEW(dev)) {
4990                 refclk = 100000;
4991         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4992             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4993                 refclk = dev_priv->vbt.lvds_ssc_freq;
4994                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
4995         } else if (!IS_GEN2(dev)) {
4996                 refclk = 96000;
4997         } else {
4998                 refclk = 48000;
4999         }
5000
5001         return refclk;
5002 }
5003
5004 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5005 {
5006         return (1 << dpll->n) << 16 | dpll->m2;
5007 }
5008
5009 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5010 {
5011         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5012 }
5013
5014 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5015                                      intel_clock_t *reduced_clock)
5016 {
5017         struct drm_device *dev = crtc->base.dev;
5018         struct drm_i915_private *dev_priv = dev->dev_private;
5019         int pipe = crtc->pipe;
5020         u32 fp, fp2 = 0;
5021
5022         if (IS_PINEVIEW(dev)) {
5023                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5024                 if (reduced_clock)
5025                         fp2 = pnv_dpll_compute_fp(reduced_clock);
5026         } else {
5027                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5028                 if (reduced_clock)
5029                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
5030         }
5031
5032         I915_WRITE(FP0(pipe), fp);
5033         crtc->config.dpll_hw_state.fp0 = fp;
5034
5035         crtc->lowfreq_avail = false;
5036         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5037             reduced_clock && i915.powersave) {
5038                 I915_WRITE(FP1(pipe), fp2);
5039                 crtc->config.dpll_hw_state.fp1 = fp2;
5040                 crtc->lowfreq_avail = true;
5041         } else {
5042                 I915_WRITE(FP1(pipe), fp);
5043                 crtc->config.dpll_hw_state.fp1 = fp;
5044         }
5045 }
5046
5047 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5048                 pipe)
5049 {
5050         u32 reg_val;
5051
5052         /*
5053          * PLLB opamp always calibrates to max value of 0x3f, force enable it
5054          * and set it to a reasonable value instead.
5055          */
5056         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5057         reg_val &= 0xffffff00;
5058         reg_val |= 0x00000030;
5059         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5060
5061         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5062         reg_val &= 0x8cffffff;
5063         reg_val = 0x8c000000;
5064         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5065
5066         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5067         reg_val &= 0xffffff00;
5068         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5069
5070         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5071         reg_val &= 0x00ffffff;
5072         reg_val |= 0xb0000000;
5073         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5074 }
5075
5076 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5077                                          struct intel_link_m_n *m_n)
5078 {
5079         struct drm_device *dev = crtc->base.dev;
5080         struct drm_i915_private *dev_priv = dev->dev_private;
5081         int pipe = crtc->pipe;
5082
5083         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5084         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5085         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5086         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5087 }
5088
5089 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5090                                          struct intel_link_m_n *m_n)
5091 {
5092         struct drm_device *dev = crtc->base.dev;
5093         struct drm_i915_private *dev_priv = dev->dev_private;
5094         int pipe = crtc->pipe;
5095         enum transcoder transcoder = crtc->config.cpu_transcoder;
5096
5097         if (INTEL_INFO(dev)->gen >= 5) {
5098                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5099                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5100                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5101                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5102         } else {
5103                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5104                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5105                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5106                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5107         }
5108 }
5109
5110 static void intel_dp_set_m_n(struct intel_crtc *crtc)
5111 {
5112         if (crtc->config.has_pch_encoder)
5113                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5114         else
5115                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5116 }
5117
5118 static void vlv_update_pll(struct intel_crtc *crtc)
5119 {
5120         struct drm_device *dev = crtc->base.dev;
5121         struct drm_i915_private *dev_priv = dev->dev_private;
5122         int pipe = crtc->pipe;
5123         u32 dpll, mdiv;
5124         u32 bestn, bestm1, bestm2, bestp1, bestp2;
5125         u32 coreclk, reg_val, dpll_md;
5126
5127         mutex_lock(&dev_priv->dpio_lock);
5128
5129         bestn = crtc->config.dpll.n;
5130         bestm1 = crtc->config.dpll.m1;
5131         bestm2 = crtc->config.dpll.m2;
5132         bestp1 = crtc->config.dpll.p1;
5133         bestp2 = crtc->config.dpll.p2;
5134
5135         /* See eDP HDMI DPIO driver vbios notes doc */
5136
5137         /* PLL B needs special handling */
5138         if (pipe)
5139                 vlv_pllb_recal_opamp(dev_priv, pipe);
5140
5141         /* Set up Tx target for periodic Rcomp update */
5142         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5143
5144         /* Disable target IRef on PLL */
5145         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5146         reg_val &= 0x00ffffff;
5147         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5148
5149         /* Disable fast lock */
5150         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5151
5152         /* Set idtafcrecal before PLL is enabled */
5153         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5154         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5155         mdiv |= ((bestn << DPIO_N_SHIFT));
5156         mdiv |= (1 << DPIO_K_SHIFT);
5157
5158         /*
5159          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5160          * but we don't support that).
5161          * Note: don't use the DAC post divider as it seems unstable.
5162          */
5163         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5164         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5165
5166         mdiv |= DPIO_ENABLE_CALIBRATION;
5167         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5168
5169         /* Set HBR and RBR LPF coefficients */
5170         if (crtc->config.port_clock == 162000 ||
5171             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5172             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5173                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5174                                  0x009f0003);
5175         else
5176                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5177                                  0x00d0000f);
5178
5179         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5180             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5181                 /* Use SSC source */
5182                 if (!pipe)
5183                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5184                                          0x0df40000);
5185                 else
5186                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5187                                          0x0df70000);
5188         } else { /* HDMI or VGA */
5189                 /* Use bend source */
5190                 if (!pipe)
5191                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5192                                          0x0df70000);
5193                 else
5194                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5195                                          0x0df40000);
5196         }
5197
5198         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5199         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5200         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5201             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5202                 coreclk |= 0x01000000;
5203         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5204
5205         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5206
5207         /*
5208          * Enable DPIO clock input. We should never disable the reference
5209          * clock for pipe B, since VGA hotplug / manual detection depends
5210          * on it.
5211          */
5212         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5213                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5214         /* We should never disable this, set it here for state tracking */
5215         if (pipe == PIPE_B)
5216                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5217         dpll |= DPLL_VCO_ENABLE;
5218         crtc->config.dpll_hw_state.dpll = dpll;
5219
5220         dpll_md = (crtc->config.pixel_multiplier - 1)
5221                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5222         crtc->config.dpll_hw_state.dpll_md = dpll_md;
5223
5224         mutex_unlock(&dev_priv->dpio_lock);
5225 }
5226
5227 static void i9xx_update_pll(struct intel_crtc *crtc,
5228                             intel_clock_t *reduced_clock,
5229                             int num_connectors)
5230 {
5231         struct drm_device *dev = crtc->base.dev;
5232         struct drm_i915_private *dev_priv = dev->dev_private;
5233         u32 dpll;
5234         bool is_sdvo;
5235         struct dpll *clock = &crtc->config.dpll;
5236
5237         i9xx_update_pll_dividers(crtc, reduced_clock);
5238
5239         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5240                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5241
5242         dpll = DPLL_VGA_MODE_DIS;
5243
5244         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5245                 dpll |= DPLLB_MODE_LVDS;
5246         else
5247                 dpll |= DPLLB_MODE_DAC_SERIAL;
5248
5249         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5250                 dpll |= (crtc->config.pixel_multiplier - 1)
5251                         << SDVO_MULTIPLIER_SHIFT_HIRES;
5252         }
5253
5254         if (is_sdvo)
5255                 dpll |= DPLL_SDVO_HIGH_SPEED;
5256
5257         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5258                 dpll |= DPLL_SDVO_HIGH_SPEED;
5259
5260         /* compute bitmask from p1 value */
5261         if (IS_PINEVIEW(dev))
5262                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5263         else {
5264                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5265                 if (IS_G4X(dev) && reduced_clock)
5266                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5267         }
5268         switch (clock->p2) {
5269         case 5:
5270                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5271                 break;
5272         case 7:
5273                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5274                 break;
5275         case 10:
5276                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5277                 break;
5278         case 14:
5279                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5280                 break;
5281         }
5282         if (INTEL_INFO(dev)->gen >= 4)
5283                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5284
5285         if (crtc->config.sdvo_tv_clock)
5286                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5287         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5288                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5289                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5290         else
5291                 dpll |= PLL_REF_INPUT_DREFCLK;
5292
5293         dpll |= DPLL_VCO_ENABLE;
5294         crtc->config.dpll_hw_state.dpll = dpll;
5295
5296         if (INTEL_INFO(dev)->gen >= 4) {
5297                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5298                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5299                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5300         }
5301 }
5302
5303 static void i8xx_update_pll(struct intel_crtc *crtc,
5304                             intel_clock_t *reduced_clock,
5305                             int num_connectors)
5306 {
5307         struct drm_device *dev = crtc->base.dev;
5308         struct drm_i915_private *dev_priv = dev->dev_private;
5309         u32 dpll;
5310         struct dpll *clock = &crtc->config.dpll;
5311
5312         i9xx_update_pll_dividers(crtc, reduced_clock);
5313
5314         dpll = DPLL_VGA_MODE_DIS;
5315
5316         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5317                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5318         } else {
5319                 if (clock->p1 == 2)
5320                         dpll |= PLL_P1_DIVIDE_BY_TWO;
5321                 else
5322                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5323                 if (clock->p2 == 4)
5324                         dpll |= PLL_P2_DIVIDE_BY_4;
5325         }
5326
5327         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5328                 dpll |= DPLL_DVO_2X_MODE;
5329
5330         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5331                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5332                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5333         else
5334                 dpll |= PLL_REF_INPUT_DREFCLK;
5335
5336         dpll |= DPLL_VCO_ENABLE;
5337         crtc->config.dpll_hw_state.dpll = dpll;
5338 }
5339
5340 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5341 {
5342         struct drm_device *dev = intel_crtc->base.dev;
5343         struct drm_i915_private *dev_priv = dev->dev_private;
5344         enum pipe pipe = intel_crtc->pipe;
5345         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5346         struct drm_display_mode *adjusted_mode =
5347                 &intel_crtc->config.adjusted_mode;
5348         uint32_t crtc_vtotal, crtc_vblank_end;
5349         int vsyncshift = 0;
5350
5351         /* We need to be careful not to changed the adjusted mode, for otherwise
5352          * the hw state checker will get angry at the mismatch. */
5353         crtc_vtotal = adjusted_mode->crtc_vtotal;
5354         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5355
5356         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5357                 /* the chip adds 2 halflines automatically */
5358                 crtc_vtotal -= 1;
5359                 crtc_vblank_end -= 1;
5360
5361                 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5362                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5363                 else
5364                         vsyncshift = adjusted_mode->crtc_hsync_start -
5365                                 adjusted_mode->crtc_htotal / 2;
5366                 if (vsyncshift < 0)
5367                         vsyncshift += adjusted_mode->crtc_htotal;
5368         }
5369
5370         if (INTEL_INFO(dev)->gen > 3)
5371                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5372
5373         I915_WRITE(HTOTAL(cpu_transcoder),
5374                    (adjusted_mode->crtc_hdisplay - 1) |
5375                    ((adjusted_mode->crtc_htotal - 1) << 16));
5376         I915_WRITE(HBLANK(cpu_transcoder),
5377                    (adjusted_mode->crtc_hblank_start - 1) |
5378                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5379         I915_WRITE(HSYNC(cpu_transcoder),
5380                    (adjusted_mode->crtc_hsync_start - 1) |
5381                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5382
5383         I915_WRITE(VTOTAL(cpu_transcoder),
5384                    (adjusted_mode->crtc_vdisplay - 1) |
5385                    ((crtc_vtotal - 1) << 16));
5386         I915_WRITE(VBLANK(cpu_transcoder),
5387                    (adjusted_mode->crtc_vblank_start - 1) |
5388                    ((crtc_vblank_end - 1) << 16));
5389         I915_WRITE(VSYNC(cpu_transcoder),
5390                    (adjusted_mode->crtc_vsync_start - 1) |
5391                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5392
5393         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5394          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5395          * documented on the DDI_FUNC_CTL register description, EDP Input Select
5396          * bits. */
5397         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5398             (pipe == PIPE_B || pipe == PIPE_C))
5399                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5400
5401         /* pipesrc controls the size that is scaled from, which should
5402          * always be the user's requested size.
5403          */
5404         I915_WRITE(PIPESRC(pipe),
5405                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
5406                    (intel_crtc->config.pipe_src_h - 1));
5407 }
5408
5409 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5410                                    struct intel_crtc_config *pipe_config)
5411 {
5412         struct drm_device *dev = crtc->base.dev;
5413         struct drm_i915_private *dev_priv = dev->dev_private;
5414         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5415         uint32_t tmp;
5416
5417         tmp = I915_READ(HTOTAL(cpu_transcoder));
5418         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5419         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5420         tmp = I915_READ(HBLANK(cpu_transcoder));
5421         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5422         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5423         tmp = I915_READ(HSYNC(cpu_transcoder));
5424         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5425         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5426
5427         tmp = I915_READ(VTOTAL(cpu_transcoder));
5428         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5429         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5430         tmp = I915_READ(VBLANK(cpu_transcoder));
5431         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5432         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5433         tmp = I915_READ(VSYNC(cpu_transcoder));
5434         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5435         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5436
5437         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5438                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5439                 pipe_config->adjusted_mode.crtc_vtotal += 1;
5440                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5441         }
5442
5443         tmp = I915_READ(PIPESRC(crtc->pipe));
5444         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5445         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5446
5447         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5448         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5449 }
5450
5451 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5452                                  struct intel_crtc_config *pipe_config)
5453 {
5454         mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5455         mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5456         mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5457         mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5458
5459         mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5460         mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5461         mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5462         mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5463
5464         mode->flags = pipe_config->adjusted_mode.flags;
5465
5466         mode->clock = pipe_config->adjusted_mode.crtc_clock;
5467         mode->flags |= pipe_config->adjusted_mode.flags;
5468 }
5469
5470 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5471 {
5472         struct drm_device *dev = intel_crtc->base.dev;
5473         struct drm_i915_private *dev_priv = dev->dev_private;
5474         uint32_t pipeconf;
5475
5476         pipeconf = 0;
5477
5478         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5479             I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5480                 pipeconf |= PIPECONF_ENABLE;
5481
5482         if (intel_crtc->config.double_wide)
5483                 pipeconf |= PIPECONF_DOUBLE_WIDE;
5484
5485         /* only g4x and later have fancy bpc/dither controls */
5486         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5487                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5488                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5489                         pipeconf |= PIPECONF_DITHER_EN |
5490                                     PIPECONF_DITHER_TYPE_SP;
5491
5492                 switch (intel_crtc->config.pipe_bpp) {
5493                 case 18:
5494                         pipeconf |= PIPECONF_6BPC;
5495                         break;
5496                 case 24:
5497                         pipeconf |= PIPECONF_8BPC;
5498                         break;
5499                 case 30:
5500                         pipeconf |= PIPECONF_10BPC;
5501                         break;
5502                 default:
5503                         /* Case prevented by intel_choose_pipe_bpp_dither. */
5504                         BUG();
5505                 }
5506         }
5507
5508         if (HAS_PIPE_CXSR(dev)) {
5509                 if (intel_crtc->lowfreq_avail) {
5510                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5511                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5512                 } else {
5513                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5514                 }
5515         }
5516
5517         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
5518                 if (INTEL_INFO(dev)->gen < 4 ||
5519                     intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5520                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5521                 else
5522                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
5523         } else
5524                 pipeconf |= PIPECONF_PROGRESSIVE;
5525
5526         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5527                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5528
5529         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5530         POSTING_READ(PIPECONF(intel_crtc->pipe));
5531 }
5532
5533 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5534                               int x, int y,
5535                               struct drm_framebuffer *fb)
5536 {
5537         struct drm_device *dev = crtc->dev;
5538         struct drm_i915_private *dev_priv = dev->dev_private;
5539         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5540         int pipe = intel_crtc->pipe;
5541         int plane = intel_crtc->plane;
5542         int refclk, num_connectors = 0;
5543         intel_clock_t clock, reduced_clock;
5544         u32 dspcntr;
5545         bool ok, has_reduced_clock = false;
5546         bool is_lvds = false, is_dsi = false;
5547         struct intel_encoder *encoder;
5548         const intel_limit_t *limit;
5549         int ret;
5550
5551         for_each_encoder_on_crtc(dev, crtc, encoder) {
5552                 switch (encoder->type) {
5553                 case INTEL_OUTPUT_LVDS:
5554                         is_lvds = true;
5555                         break;
5556                 case INTEL_OUTPUT_DSI:
5557                         is_dsi = true;
5558                         break;
5559                 }
5560
5561                 num_connectors++;
5562         }
5563
5564         if (is_dsi)
5565                 goto skip_dpll;
5566
5567         if (!intel_crtc->config.clock_set) {
5568                 refclk = i9xx_get_refclk(crtc, num_connectors);
5569
5570                 /*
5571                  * Returns a set of divisors for the desired target clock with
5572                  * the given refclk, or FALSE.  The returned values represent
5573                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5574                  * 2) / p1 / p2.
5575                  */
5576                 limit = intel_limit(crtc, refclk);
5577                 ok = dev_priv->display.find_dpll(limit, crtc,
5578                                                  intel_crtc->config.port_clock,
5579                                                  refclk, NULL, &clock);
5580                 if (!ok) {
5581                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5582                         return -EINVAL;
5583                 }
5584
5585                 if (is_lvds && dev_priv->lvds_downclock_avail) {
5586                         /*
5587                          * Ensure we match the reduced clock's P to the target
5588                          * clock.  If the clocks don't match, we can't switch
5589                          * the display clock by using the FP0/FP1. In such case
5590                          * we will disable the LVDS downclock feature.
5591                          */
5592                         has_reduced_clock =
5593                                 dev_priv->display.find_dpll(limit, crtc,
5594                                                             dev_priv->lvds_downclock,
5595                                                             refclk, &clock,
5596                                                             &reduced_clock);
5597                 }
5598                 /* Compat-code for transition, will disappear. */
5599                 intel_crtc->config.dpll.n = clock.n;
5600                 intel_crtc->config.dpll.m1 = clock.m1;
5601                 intel_crtc->config.dpll.m2 = clock.m2;
5602                 intel_crtc->config.dpll.p1 = clock.p1;
5603                 intel_crtc->config.dpll.p2 = clock.p2;
5604         }
5605
5606         if (IS_GEN2(dev)) {
5607                 i8xx_update_pll(intel_crtc,
5608                                 has_reduced_clock ? &reduced_clock : NULL,
5609                                 num_connectors);
5610         } else if (IS_VALLEYVIEW(dev)) {
5611                 vlv_update_pll(intel_crtc);
5612         } else {
5613                 i9xx_update_pll(intel_crtc,
5614                                 has_reduced_clock ? &reduced_clock : NULL,
5615                                 num_connectors);
5616         }
5617
5618 skip_dpll:
5619         /* Set up the display plane register */
5620         dspcntr = DISPPLANE_GAMMA_ENABLE;
5621
5622         if (!IS_VALLEYVIEW(dev)) {
5623                 if (pipe == 0)
5624                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5625                 else
5626                         dspcntr |= DISPPLANE_SEL_PIPE_B;
5627         }
5628
5629         if (intel_crtc->config.has_dp_encoder)
5630                 intel_dp_set_m_n(intel_crtc);
5631
5632         intel_set_pipe_timings(intel_crtc);
5633
5634         /* pipesrc and dspsize control the size that is scaled from,
5635          * which should always be the user's requested size.
5636          */
5637         I915_WRITE(DSPSIZE(plane),
5638                    ((intel_crtc->config.pipe_src_h - 1) << 16) |
5639                    (intel_crtc->config.pipe_src_w - 1));
5640         I915_WRITE(DSPPOS(plane), 0);
5641
5642         i9xx_set_pipeconf(intel_crtc);
5643
5644         I915_WRITE(DSPCNTR(plane), dspcntr);
5645         POSTING_READ(DSPCNTR(plane));
5646
5647         ret = intel_pipe_set_base(crtc, x, y, fb);
5648
5649         return ret;
5650 }
5651
5652 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5653                                  struct intel_crtc_config *pipe_config)
5654 {
5655         struct drm_device *dev = crtc->base.dev;
5656         struct drm_i915_private *dev_priv = dev->dev_private;
5657         uint32_t tmp;
5658
5659         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
5660                 return;
5661
5662         tmp = I915_READ(PFIT_CONTROL);
5663         if (!(tmp & PFIT_ENABLE))
5664                 return;
5665
5666         /* Check whether the pfit is attached to our pipe. */
5667         if (INTEL_INFO(dev)->gen < 4) {
5668                 if (crtc->pipe != PIPE_B)
5669                         return;
5670         } else {
5671                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5672                         return;
5673         }
5674
5675         pipe_config->gmch_pfit.control = tmp;
5676         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5677         if (INTEL_INFO(dev)->gen < 5)
5678                 pipe_config->gmch_pfit.lvds_border_bits =
5679                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5680 }
5681
5682 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5683                                struct intel_crtc_config *pipe_config)
5684 {
5685         struct drm_device *dev = crtc->base.dev;
5686         struct drm_i915_private *dev_priv = dev->dev_private;
5687         int pipe = pipe_config->cpu_transcoder;
5688         intel_clock_t clock;
5689         u32 mdiv;
5690         int refclk = 100000;
5691
5692         mutex_lock(&dev_priv->dpio_lock);
5693         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
5694         mutex_unlock(&dev_priv->dpio_lock);
5695
5696         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5697         clock.m2 = mdiv & DPIO_M2DIV_MASK;
5698         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5699         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5700         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5701
5702         vlv_clock(refclk, &clock);
5703
5704         /* clock.dot is the fast clock */
5705         pipe_config->port_clock = clock.dot / 5;
5706 }
5707
5708 static void i9xx_get_plane_config(struct intel_crtc *crtc,
5709                                   struct intel_plane_config *plane_config)
5710 {
5711         struct drm_device *dev = crtc->base.dev;
5712         struct drm_i915_private *dev_priv = dev->dev_private;
5713         u32 val, base, offset;
5714         int pipe = crtc->pipe, plane = crtc->plane;
5715         int fourcc, pixel_format;
5716         int aligned_height;
5717
5718         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
5719         if (!crtc->base.primary->fb) {
5720                 DRM_DEBUG_KMS("failed to alloc fb\n");
5721                 return;
5722         }
5723
5724         val = I915_READ(DSPCNTR(plane));
5725
5726         if (INTEL_INFO(dev)->gen >= 4)
5727                 if (val & DISPPLANE_TILED)
5728                         plane_config->tiled = true;
5729
5730         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
5731         fourcc = intel_format_to_fourcc(pixel_format);
5732         crtc->base.primary->fb->pixel_format = fourcc;
5733         crtc->base.primary->fb->bits_per_pixel =
5734                 drm_format_plane_cpp(fourcc, 0) * 8;
5735
5736         if (INTEL_INFO(dev)->gen >= 4) {
5737                 if (plane_config->tiled)
5738                         offset = I915_READ(DSPTILEOFF(plane));
5739                 else
5740                         offset = I915_READ(DSPLINOFF(plane));
5741                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
5742         } else {
5743                 base = I915_READ(DSPADDR(plane));
5744         }
5745         plane_config->base = base;
5746
5747         val = I915_READ(PIPESRC(pipe));
5748         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
5749         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
5750
5751         val = I915_READ(DSPSTRIDE(pipe));
5752         crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
5753
5754         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
5755                                             plane_config->tiled);
5756
5757         plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
5758                                    aligned_height, PAGE_SIZE);
5759
5760         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
5761                       pipe, plane, crtc->base.primary->fb->width,
5762                       crtc->base.primary->fb->height,
5763                       crtc->base.primary->fb->bits_per_pixel, base,
5764                       crtc->base.primary->fb->pitches[0],
5765                       plane_config->size);
5766
5767 }
5768
5769 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5770                                  struct intel_crtc_config *pipe_config)
5771 {
5772         struct drm_device *dev = crtc->base.dev;
5773         struct drm_i915_private *dev_priv = dev->dev_private;
5774         uint32_t tmp;
5775
5776         if (!intel_display_power_enabled(dev_priv,
5777                                          POWER_DOMAIN_PIPE(crtc->pipe)))
5778                 return false;
5779
5780         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5781         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5782
5783         tmp = I915_READ(PIPECONF(crtc->pipe));
5784         if (!(tmp & PIPECONF_ENABLE))
5785                 return false;
5786
5787         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5788                 switch (tmp & PIPECONF_BPC_MASK) {
5789                 case PIPECONF_6BPC:
5790                         pipe_config->pipe_bpp = 18;
5791                         break;
5792                 case PIPECONF_8BPC:
5793                         pipe_config->pipe_bpp = 24;
5794                         break;
5795                 case PIPECONF_10BPC:
5796                         pipe_config->pipe_bpp = 30;
5797                         break;
5798                 default:
5799                         break;
5800                 }
5801         }
5802
5803         if (INTEL_INFO(dev)->gen < 4)
5804                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5805
5806         intel_get_pipe_timings(crtc, pipe_config);
5807
5808         i9xx_get_pfit_config(crtc, pipe_config);
5809
5810         if (INTEL_INFO(dev)->gen >= 4) {
5811                 tmp = I915_READ(DPLL_MD(crtc->pipe));
5812                 pipe_config->pixel_multiplier =
5813                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5814                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5815                 pipe_config->dpll_hw_state.dpll_md = tmp;
5816         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5817                 tmp = I915_READ(DPLL(crtc->pipe));
5818                 pipe_config->pixel_multiplier =
5819                         ((tmp & SDVO_MULTIPLIER_MASK)
5820                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5821         } else {
5822                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5823                  * port and will be fixed up in the encoder->get_config
5824                  * function. */
5825                 pipe_config->pixel_multiplier = 1;
5826         }
5827         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5828         if (!IS_VALLEYVIEW(dev)) {
5829                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5830                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5831         } else {
5832                 /* Mask out read-only status bits. */
5833                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5834                                                      DPLL_PORTC_READY_MASK |
5835                                                      DPLL_PORTB_READY_MASK);
5836         }
5837
5838         if (IS_VALLEYVIEW(dev))
5839                 vlv_crtc_clock_get(crtc, pipe_config);
5840         else
5841                 i9xx_crtc_clock_get(crtc, pipe_config);
5842
5843         return true;
5844 }
5845
5846 static void ironlake_init_pch_refclk(struct drm_device *dev)
5847 {
5848         struct drm_i915_private *dev_priv = dev->dev_private;
5849         struct drm_mode_config *mode_config = &dev->mode_config;
5850         struct intel_encoder *encoder;
5851         u32 val, final;
5852         bool has_lvds = false;
5853         bool has_cpu_edp = false;
5854         bool has_panel = false;
5855         bool has_ck505 = false;
5856         bool can_ssc = false;
5857
5858         /* We need to take the global config into account */
5859         list_for_each_entry(encoder, &mode_config->encoder_list,
5860                             base.head) {
5861                 switch (encoder->type) {
5862                 case INTEL_OUTPUT_LVDS:
5863                         has_panel = true;
5864                         has_lvds = true;
5865                         break;
5866                 case INTEL_OUTPUT_EDP:
5867                         has_panel = true;
5868                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5869                                 has_cpu_edp = true;
5870                         break;
5871                 }
5872         }
5873
5874         if (HAS_PCH_IBX(dev)) {
5875                 has_ck505 = dev_priv->vbt.display_clock_mode;
5876                 can_ssc = has_ck505;
5877         } else {
5878                 has_ck505 = false;
5879                 can_ssc = true;
5880         }
5881
5882         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5883                       has_panel, has_lvds, has_ck505);
5884
5885         /* Ironlake: try to setup display ref clock before DPLL
5886          * enabling. This is only under driver's control after
5887          * PCH B stepping, previous chipset stepping should be
5888          * ignoring this setting.
5889          */
5890         val = I915_READ(PCH_DREF_CONTROL);
5891
5892         /* As we must carefully and slowly disable/enable each source in turn,
5893          * compute the final state we want first and check if we need to
5894          * make any changes at all.
5895          */
5896         final = val;
5897         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5898         if (has_ck505)
5899                 final |= DREF_NONSPREAD_CK505_ENABLE;
5900         else
5901                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5902
5903         final &= ~DREF_SSC_SOURCE_MASK;
5904         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5905         final &= ~DREF_SSC1_ENABLE;
5906
5907         if (has_panel) {
5908                 final |= DREF_SSC_SOURCE_ENABLE;
5909
5910                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5911                         final |= DREF_SSC1_ENABLE;
5912
5913                 if (has_cpu_edp) {
5914                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5915                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5916                         else
5917                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5918                 } else
5919                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5920         } else {
5921                 final |= DREF_SSC_SOURCE_DISABLE;
5922                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5923         }
5924
5925         if (final == val)
5926                 return;
5927
5928         /* Always enable nonspread source */
5929         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5930
5931         if (has_ck505)
5932                 val |= DREF_NONSPREAD_CK505_ENABLE;
5933         else
5934                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5935
5936         if (has_panel) {
5937                 val &= ~DREF_SSC_SOURCE_MASK;
5938                 val |= DREF_SSC_SOURCE_ENABLE;
5939
5940                 /* SSC must be turned on before enabling the CPU output  */
5941                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5942                         DRM_DEBUG_KMS("Using SSC on panel\n");
5943                         val |= DREF_SSC1_ENABLE;
5944                 } else
5945                         val &= ~DREF_SSC1_ENABLE;
5946
5947                 /* Get SSC going before enabling the outputs */
5948                 I915_WRITE(PCH_DREF_CONTROL, val);
5949                 POSTING_READ(PCH_DREF_CONTROL);
5950                 udelay(200);
5951
5952                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5953
5954                 /* Enable CPU source on CPU attached eDP */
5955                 if (has_cpu_edp) {
5956                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5957                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5958                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5959                         }
5960                         else
5961                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5962                 } else
5963                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5964
5965                 I915_WRITE(PCH_DREF_CONTROL, val);
5966                 POSTING_READ(PCH_DREF_CONTROL);
5967                 udelay(200);
5968         } else {
5969                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5970
5971                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5972
5973                 /* Turn off CPU output */
5974                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5975
5976                 I915_WRITE(PCH_DREF_CONTROL, val);
5977                 POSTING_READ(PCH_DREF_CONTROL);
5978                 udelay(200);
5979
5980                 /* Turn off the SSC source */
5981                 val &= ~DREF_SSC_SOURCE_MASK;
5982                 val |= DREF_SSC_SOURCE_DISABLE;
5983
5984                 /* Turn off SSC1 */
5985                 val &= ~DREF_SSC1_ENABLE;
5986
5987                 I915_WRITE(PCH_DREF_CONTROL, val);
5988                 POSTING_READ(PCH_DREF_CONTROL);
5989                 udelay(200);
5990         }
5991
5992         BUG_ON(val != final);
5993 }
5994
5995 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5996 {
5997         uint32_t tmp;
5998
5999         tmp = I915_READ(SOUTH_CHICKEN2);
6000         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6001         I915_WRITE(SOUTH_CHICKEN2, tmp);
6002
6003         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6004                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6005                 DRM_ERROR("FDI mPHY reset assert timeout\n");
6006
6007         tmp = I915_READ(SOUTH_CHICKEN2);
6008         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6009         I915_WRITE(SOUTH_CHICKEN2, tmp);
6010
6011         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6012                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6013                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6014 }
6015
6016 /* WaMPhyProgramming:hsw */
6017 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6018 {
6019         uint32_t tmp;
6020
6021         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6022         tmp &= ~(0xFF << 24);
6023         tmp |= (0x12 << 24);
6024         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6025
6026         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6027         tmp |= (1 << 11);
6028         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6029
6030         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6031         tmp |= (1 << 11);
6032         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6033
6034         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6035         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6036         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6037
6038         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6039         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6040         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6041
6042         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6043         tmp &= ~(7 << 13);
6044         tmp |= (5 << 13);
6045         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6046
6047         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6048         tmp &= ~(7 << 13);
6049         tmp |= (5 << 13);
6050         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6051
6052         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6053         tmp &= ~0xFF;
6054         tmp |= 0x1C;
6055         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6056
6057         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6058         tmp &= ~0xFF;
6059         tmp |= 0x1C;
6060         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6061
6062         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6063         tmp &= ~(0xFF << 16);
6064         tmp |= (0x1C << 16);
6065         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6066
6067         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6068         tmp &= ~(0xFF << 16);
6069         tmp |= (0x1C << 16);
6070         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6071
6072         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6073         tmp |= (1 << 27);
6074         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6075
6076         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6077         tmp |= (1 << 27);
6078         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6079
6080         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6081         tmp &= ~(0xF << 28);
6082         tmp |= (4 << 28);
6083         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6084
6085         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6086         tmp &= ~(0xF << 28);
6087         tmp |= (4 << 28);
6088         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6089 }
6090
6091 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6092  * Programming" based on the parameters passed:
6093  * - Sequence to enable CLKOUT_DP
6094  * - Sequence to enable CLKOUT_DP without spread
6095  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6096  */
6097 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6098                                  bool with_fdi)
6099 {
6100         struct drm_i915_private *dev_priv = dev->dev_private;
6101         uint32_t reg, tmp;
6102
6103         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6104                 with_spread = true;
6105         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6106                  with_fdi, "LP PCH doesn't have FDI\n"))
6107                 with_fdi = false;
6108
6109         mutex_lock(&dev_priv->dpio_lock);
6110
6111         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6112         tmp &= ~SBI_SSCCTL_DISABLE;
6113         tmp |= SBI_SSCCTL_PATHALT;
6114         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6115
6116         udelay(24);
6117
6118         if (with_spread) {
6119                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6120                 tmp &= ~SBI_SSCCTL_PATHALT;
6121                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6122
6123                 if (with_fdi) {
6124                         lpt_reset_fdi_mphy(dev_priv);
6125                         lpt_program_fdi_mphy(dev_priv);
6126                 }
6127         }
6128
6129         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6130                SBI_GEN0 : SBI_DBUFF0;
6131         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6132         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6133         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6134
6135         mutex_unlock(&dev_priv->dpio_lock);
6136 }
6137
6138 /* Sequence to disable CLKOUT_DP */
6139 static void lpt_disable_clkout_dp(struct drm_device *dev)
6140 {
6141         struct drm_i915_private *dev_priv = dev->dev_private;
6142         uint32_t reg, tmp;
6143
6144         mutex_lock(&dev_priv->dpio_lock);
6145
6146         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6147                SBI_GEN0 : SBI_DBUFF0;
6148         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6149         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6150         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6151
6152         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6153         if (!(tmp & SBI_SSCCTL_DISABLE)) {
6154                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6155                         tmp |= SBI_SSCCTL_PATHALT;
6156                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6157                         udelay(32);
6158                 }
6159                 tmp |= SBI_SSCCTL_DISABLE;
6160                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6161         }
6162
6163         mutex_unlock(&dev_priv->dpio_lock);
6164 }
6165
6166 static void lpt_init_pch_refclk(struct drm_device *dev)
6167 {
6168         struct drm_mode_config *mode_config = &dev->mode_config;
6169         struct intel_encoder *encoder;
6170         bool has_vga = false;
6171
6172         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
6173                 switch (encoder->type) {
6174                 case INTEL_OUTPUT_ANALOG:
6175                         has_vga = true;
6176                         break;
6177                 }
6178         }
6179
6180         if (has_vga)
6181                 lpt_enable_clkout_dp(dev, true, true);
6182         else
6183                 lpt_disable_clkout_dp(dev);
6184 }
6185
6186 /*
6187  * Initialize reference clocks when the driver loads
6188  */
6189 void intel_init_pch_refclk(struct drm_device *dev)
6190 {
6191         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6192                 ironlake_init_pch_refclk(dev);
6193         else if (HAS_PCH_LPT(dev))
6194                 lpt_init_pch_refclk(dev);
6195 }
6196
6197 static int ironlake_get_refclk(struct drm_crtc *crtc)
6198 {
6199         struct drm_device *dev = crtc->dev;
6200         struct drm_i915_private *dev_priv = dev->dev_private;
6201         struct intel_encoder *encoder;
6202         int num_connectors = 0;
6203         bool is_lvds = false;
6204
6205         for_each_encoder_on_crtc(dev, crtc, encoder) {
6206                 switch (encoder->type) {
6207                 case INTEL_OUTPUT_LVDS:
6208                         is_lvds = true;
6209                         break;
6210                 }
6211                 num_connectors++;
6212         }
6213
6214         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6215                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6216                               dev_priv->vbt.lvds_ssc_freq);
6217                 return dev_priv->vbt.lvds_ssc_freq;
6218         }
6219
6220         return 120000;
6221 }
6222
6223 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6224 {
6225         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6226         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6227         int pipe = intel_crtc->pipe;
6228         uint32_t val;
6229
6230         val = 0;
6231
6232         switch (intel_crtc->config.pipe_bpp) {
6233         case 18:
6234                 val |= PIPECONF_6BPC;
6235                 break;
6236         case 24:
6237                 val |= PIPECONF_8BPC;
6238                 break;
6239         case 30:
6240                 val |= PIPECONF_10BPC;
6241                 break;
6242         case 36:
6243                 val |= PIPECONF_12BPC;
6244                 break;
6245         default:
6246                 /* Case prevented by intel_choose_pipe_bpp_dither. */
6247                 BUG();
6248         }
6249
6250         if (intel_crtc->config.dither)
6251                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6252
6253         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6254                 val |= PIPECONF_INTERLACED_ILK;
6255         else
6256                 val |= PIPECONF_PROGRESSIVE;
6257
6258         if (intel_crtc->config.limited_color_range)
6259                 val |= PIPECONF_COLOR_RANGE_SELECT;
6260
6261         I915_WRITE(PIPECONF(pipe), val);
6262         POSTING_READ(PIPECONF(pipe));
6263 }
6264
6265 /*
6266  * Set up the pipe CSC unit.
6267  *
6268  * Currently only full range RGB to limited range RGB conversion
6269  * is supported, but eventually this should handle various
6270  * RGB<->YCbCr scenarios as well.
6271  */
6272 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6273 {
6274         struct drm_device *dev = crtc->dev;
6275         struct drm_i915_private *dev_priv = dev->dev_private;
6276         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6277         int pipe = intel_crtc->pipe;
6278         uint16_t coeff = 0x7800; /* 1.0 */
6279
6280         /*
6281          * TODO: Check what kind of values actually come out of the pipe
6282          * with these coeff/postoff values and adjust to get the best
6283          * accuracy. Perhaps we even need to take the bpc value into
6284          * consideration.
6285          */
6286
6287         if (intel_crtc->config.limited_color_range)
6288                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6289
6290         /*
6291          * GY/GU and RY/RU should be the other way around according
6292          * to BSpec, but reality doesn't agree. Just set them up in
6293          * a way that results in the correct picture.
6294          */
6295         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6296         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6297
6298         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6299         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6300
6301         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6302         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6303
6304         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6305         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6306         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6307
6308         if (INTEL_INFO(dev)->gen > 6) {
6309                 uint16_t postoff = 0;
6310
6311                 if (intel_crtc->config.limited_color_range)
6312                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
6313
6314                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6315                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6316                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6317
6318                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6319         } else {
6320                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6321
6322                 if (intel_crtc->config.limited_color_range)
6323                         mode |= CSC_BLACK_SCREEN_OFFSET;
6324
6325                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6326         }
6327 }
6328
6329 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6330 {
6331         struct drm_device *dev = crtc->dev;
6332         struct drm_i915_private *dev_priv = dev->dev_private;
6333         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6334         enum pipe pipe = intel_crtc->pipe;
6335         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6336         uint32_t val;
6337
6338         val = 0;
6339
6340         if (IS_HASWELL(dev) && intel_crtc->config.dither)
6341                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6342
6343         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6344                 val |= PIPECONF_INTERLACED_ILK;
6345         else
6346                 val |= PIPECONF_PROGRESSIVE;
6347
6348         I915_WRITE(PIPECONF(cpu_transcoder), val);
6349         POSTING_READ(PIPECONF(cpu_transcoder));
6350
6351         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6352         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6353
6354         if (IS_BROADWELL(dev)) {
6355                 val = 0;
6356
6357                 switch (intel_crtc->config.pipe_bpp) {
6358                 case 18:
6359                         val |= PIPEMISC_DITHER_6_BPC;
6360                         break;
6361                 case 24:
6362                         val |= PIPEMISC_DITHER_8_BPC;
6363                         break;
6364                 case 30:
6365                         val |= PIPEMISC_DITHER_10_BPC;
6366                         break;
6367                 case 36:
6368                         val |= PIPEMISC_DITHER_12_BPC;
6369                         break;
6370                 default:
6371                         /* Case prevented by pipe_config_set_bpp. */
6372                         BUG();
6373                 }
6374
6375                 if (intel_crtc->config.dither)
6376                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6377
6378                 I915_WRITE(PIPEMISC(pipe), val);
6379         }
6380 }
6381
6382 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6383                                     intel_clock_t *clock,
6384                                     bool *has_reduced_clock,
6385                                     intel_clock_t *reduced_clock)
6386 {
6387         struct drm_device *dev = crtc->dev;
6388         struct drm_i915_private *dev_priv = dev->dev_private;
6389         struct intel_encoder *intel_encoder;
6390         int refclk;
6391         const intel_limit_t *limit;
6392         bool ret, is_lvds = false;
6393
6394         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6395                 switch (intel_encoder->type) {
6396                 case INTEL_OUTPUT_LVDS:
6397                         is_lvds = true;
6398                         break;
6399                 }
6400         }
6401
6402         refclk = ironlake_get_refclk(crtc);
6403
6404         /*
6405          * Returns a set of divisors for the desired target clock with the given
6406          * refclk, or FALSE.  The returned values represent the clock equation:
6407          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6408          */
6409         limit = intel_limit(crtc, refclk);
6410         ret = dev_priv->display.find_dpll(limit, crtc,
6411                                           to_intel_crtc(crtc)->config.port_clock,
6412                                           refclk, NULL, clock);
6413         if (!ret)
6414                 return false;
6415
6416         if (is_lvds && dev_priv->lvds_downclock_avail) {
6417                 /*
6418                  * Ensure we match the reduced clock's P to the target clock.
6419                  * If the clocks don't match, we can't switch the display clock
6420                  * by using the FP0/FP1. In such case we will disable the LVDS
6421                  * downclock feature.
6422                 */
6423                 *has_reduced_clock =
6424                         dev_priv->display.find_dpll(limit, crtc,
6425                                                     dev_priv->lvds_downclock,
6426                                                     refclk, clock,
6427                                                     reduced_clock);
6428         }
6429
6430         return true;
6431 }
6432
6433 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6434 {
6435         /*
6436          * Account for spread spectrum to avoid
6437          * oversubscribing the link. Max center spread
6438          * is 2.5%; use 5% for safety's sake.
6439          */
6440         u32 bps = target_clock * bpp * 21 / 20;
6441         return DIV_ROUND_UP(bps, link_bw * 8);
6442 }
6443
6444 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6445 {
6446         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6447 }
6448
6449 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6450                                       u32 *fp,
6451                                       intel_clock_t *reduced_clock, u32 *fp2)
6452 {
6453         struct drm_crtc *crtc = &intel_crtc->base;
6454         struct drm_device *dev = crtc->dev;
6455         struct drm_i915_private *dev_priv = dev->dev_private;
6456         struct intel_encoder *intel_encoder;
6457         uint32_t dpll;
6458         int factor, num_connectors = 0;
6459         bool is_lvds = false, is_sdvo = false;
6460
6461         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6462                 switch (intel_encoder->type) {
6463                 case INTEL_OUTPUT_LVDS:
6464                         is_lvds = true;
6465                         break;
6466                 case INTEL_OUTPUT_SDVO:
6467                 case INTEL_OUTPUT_HDMI:
6468                         is_sdvo = true;
6469                         break;
6470                 }
6471
6472                 num_connectors++;
6473         }
6474
6475         /* Enable autotuning of the PLL clock (if permissible) */
6476         factor = 21;
6477         if (is_lvds) {
6478                 if ((intel_panel_use_ssc(dev_priv) &&
6479                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
6480                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6481                         factor = 25;
6482         } else if (intel_crtc->config.sdvo_tv_clock)
6483                 factor = 20;
6484
6485         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6486                 *fp |= FP_CB_TUNE;
6487
6488         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6489                 *fp2 |= FP_CB_TUNE;
6490
6491         dpll = 0;
6492
6493         if (is_lvds)
6494                 dpll |= DPLLB_MODE_LVDS;
6495         else
6496                 dpll |= DPLLB_MODE_DAC_SERIAL;
6497
6498         dpll |= (intel_crtc->config.pixel_multiplier - 1)
6499                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6500
6501         if (is_sdvo)
6502                 dpll |= DPLL_SDVO_HIGH_SPEED;
6503         if (intel_crtc->config.has_dp_encoder)
6504                 dpll |= DPLL_SDVO_HIGH_SPEED;
6505
6506         /* compute bitmask from p1 value */
6507         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6508         /* also FPA1 */
6509         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6510
6511         switch (intel_crtc->config.dpll.p2) {
6512         case 5:
6513                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6514                 break;
6515         case 7:
6516                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6517                 break;
6518         case 10:
6519                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6520                 break;
6521         case 14:
6522                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6523                 break;
6524         }
6525
6526         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6527                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6528         else
6529                 dpll |= PLL_REF_INPUT_DREFCLK;
6530
6531         return dpll | DPLL_VCO_ENABLE;
6532 }
6533
6534 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
6535                                   int x, int y,
6536                                   struct drm_framebuffer *fb)
6537 {
6538         struct drm_device *dev = crtc->dev;
6539         struct drm_i915_private *dev_priv = dev->dev_private;
6540         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6541         int pipe = intel_crtc->pipe;
6542         int plane = intel_crtc->plane;
6543         int num_connectors = 0;
6544         intel_clock_t clock, reduced_clock;
6545         u32 dpll = 0, fp = 0, fp2 = 0;
6546         bool ok, has_reduced_clock = false;
6547         bool is_lvds = false;
6548         struct intel_encoder *encoder;
6549         struct intel_shared_dpll *pll;
6550         int ret;
6551
6552         for_each_encoder_on_crtc(dev, crtc, encoder) {
6553                 switch (encoder->type) {
6554                 case INTEL_OUTPUT_LVDS:
6555                         is_lvds = true;
6556                         break;
6557                 }
6558
6559                 num_connectors++;
6560         }
6561
6562         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6563              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6564
6565         ok = ironlake_compute_clocks(crtc, &clock,
6566                                      &has_reduced_clock, &reduced_clock);
6567         if (!ok && !intel_crtc->config.clock_set) {
6568                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6569                 return -EINVAL;
6570         }
6571         /* Compat-code for transition, will disappear. */
6572         if (!intel_crtc->config.clock_set) {
6573                 intel_crtc->config.dpll.n = clock.n;
6574                 intel_crtc->config.dpll.m1 = clock.m1;
6575                 intel_crtc->config.dpll.m2 = clock.m2;
6576                 intel_crtc->config.dpll.p1 = clock.p1;
6577                 intel_crtc->config.dpll.p2 = clock.p2;
6578         }
6579
6580         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6581         if (intel_crtc->config.has_pch_encoder) {
6582                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6583                 if (has_reduced_clock)
6584                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6585
6586                 dpll = ironlake_compute_dpll(intel_crtc,
6587                                              &fp, &reduced_clock,
6588                                              has_reduced_clock ? &fp2 : NULL);
6589
6590                 intel_crtc->config.dpll_hw_state.dpll = dpll;
6591                 intel_crtc->config.dpll_hw_state.fp0 = fp;
6592                 if (has_reduced_clock)
6593                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
6594                 else
6595                         intel_crtc->config.dpll_hw_state.fp1 = fp;
6596
6597                 pll = intel_get_shared_dpll(intel_crtc);
6598                 if (pll == NULL) {
6599                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6600                                          pipe_name(pipe));
6601                         return -EINVAL;
6602                 }
6603         } else
6604                 intel_put_shared_dpll(intel_crtc);
6605
6606         if (intel_crtc->config.has_dp_encoder)
6607                 intel_dp_set_m_n(intel_crtc);
6608
6609         if (is_lvds && has_reduced_clock && i915.powersave)
6610                 intel_crtc->lowfreq_avail = true;
6611         else
6612                 intel_crtc->lowfreq_avail = false;
6613
6614         intel_set_pipe_timings(intel_crtc);
6615
6616         if (intel_crtc->config.has_pch_encoder) {
6617                 intel_cpu_transcoder_set_m_n(intel_crtc,
6618                                              &intel_crtc->config.fdi_m_n);
6619         }
6620
6621         ironlake_set_pipeconf(crtc);
6622
6623         /* Set up the display plane register */
6624         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
6625         POSTING_READ(DSPCNTR(plane));
6626
6627         ret = intel_pipe_set_base(crtc, x, y, fb);
6628
6629         return ret;
6630 }
6631
6632 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6633                                          struct intel_link_m_n *m_n)
6634 {
6635         struct drm_device *dev = crtc->base.dev;
6636         struct drm_i915_private *dev_priv = dev->dev_private;
6637         enum pipe pipe = crtc->pipe;
6638
6639         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6640         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6641         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6642                 & ~TU_SIZE_MASK;
6643         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6644         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6645                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6646 }
6647
6648 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6649                                          enum transcoder transcoder,
6650                                          struct intel_link_m_n *m_n)
6651 {
6652         struct drm_device *dev = crtc->base.dev;
6653         struct drm_i915_private *dev_priv = dev->dev_private;
6654         enum pipe pipe = crtc->pipe;
6655
6656         if (INTEL_INFO(dev)->gen >= 5) {
6657                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6658                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6659                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6660                         & ~TU_SIZE_MASK;
6661                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6662                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6663                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6664         } else {
6665                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6666                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6667                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6668                         & ~TU_SIZE_MASK;
6669                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6670                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6671                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6672         }
6673 }
6674
6675 void intel_dp_get_m_n(struct intel_crtc *crtc,
6676                       struct intel_crtc_config *pipe_config)
6677 {
6678         if (crtc->config.has_pch_encoder)
6679                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6680         else
6681                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6682                                              &pipe_config->dp_m_n);
6683 }
6684
6685 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6686                                         struct intel_crtc_config *pipe_config)
6687 {
6688         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6689                                      &pipe_config->fdi_m_n);
6690 }
6691
6692 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6693                                      struct intel_crtc_config *pipe_config)
6694 {
6695         struct drm_device *dev = crtc->base.dev;
6696         struct drm_i915_private *dev_priv = dev->dev_private;
6697         uint32_t tmp;
6698
6699         tmp = I915_READ(PF_CTL(crtc->pipe));
6700
6701         if (tmp & PF_ENABLE) {
6702                 pipe_config->pch_pfit.enabled = true;
6703                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6704                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
6705
6706                 /* We currently do not free assignements of panel fitters on
6707                  * ivb/hsw (since we don't use the higher upscaling modes which
6708                  * differentiates them) so just WARN about this case for now. */
6709                 if (IS_GEN7(dev)) {
6710                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6711                                 PF_PIPE_SEL_IVB(crtc->pipe));
6712                 }
6713         }
6714 }
6715
6716 static void ironlake_get_plane_config(struct intel_crtc *crtc,
6717                                       struct intel_plane_config *plane_config)
6718 {
6719         struct drm_device *dev = crtc->base.dev;
6720         struct drm_i915_private *dev_priv = dev->dev_private;
6721         u32 val, base, offset;
6722         int pipe = crtc->pipe, plane = crtc->plane;
6723         int fourcc, pixel_format;
6724         int aligned_height;
6725
6726         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6727         if (!crtc->base.primary->fb) {
6728                 DRM_DEBUG_KMS("failed to alloc fb\n");
6729                 return;
6730         }
6731
6732         val = I915_READ(DSPCNTR(plane));
6733
6734         if (INTEL_INFO(dev)->gen >= 4)
6735                 if (val & DISPPLANE_TILED)
6736                         plane_config->tiled = true;
6737
6738         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6739         fourcc = intel_format_to_fourcc(pixel_format);
6740         crtc->base.primary->fb->pixel_format = fourcc;
6741         crtc->base.primary->fb->bits_per_pixel =
6742                 drm_format_plane_cpp(fourcc, 0) * 8;
6743
6744         base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6745         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6746                 offset = I915_READ(DSPOFFSET(plane));
6747         } else {
6748                 if (plane_config->tiled)
6749                         offset = I915_READ(DSPTILEOFF(plane));
6750                 else
6751                         offset = I915_READ(DSPLINOFF(plane));
6752         }
6753         plane_config->base = base;
6754
6755         val = I915_READ(PIPESRC(pipe));
6756         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6757         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6758
6759         val = I915_READ(DSPSTRIDE(pipe));
6760         crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
6761
6762         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6763                                             plane_config->tiled);
6764
6765         plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
6766                                    aligned_height, PAGE_SIZE);
6767
6768         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6769                       pipe, plane, crtc->base.primary->fb->width,
6770                       crtc->base.primary->fb->height,
6771                       crtc->base.primary->fb->bits_per_pixel, base,
6772                       crtc->base.primary->fb->pitches[0],
6773                       plane_config->size);
6774 }
6775
6776 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6777                                      struct intel_crtc_config *pipe_config)
6778 {
6779         struct drm_device *dev = crtc->base.dev;
6780         struct drm_i915_private *dev_priv = dev->dev_private;
6781         uint32_t tmp;
6782
6783         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6784         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6785
6786         tmp = I915_READ(PIPECONF(crtc->pipe));
6787         if (!(tmp & PIPECONF_ENABLE))
6788                 return false;
6789
6790         switch (tmp & PIPECONF_BPC_MASK) {
6791         case PIPECONF_6BPC:
6792                 pipe_config->pipe_bpp = 18;
6793                 break;
6794         case PIPECONF_8BPC:
6795                 pipe_config->pipe_bpp = 24;
6796                 break;
6797         case PIPECONF_10BPC:
6798                 pipe_config->pipe_bpp = 30;
6799                 break;
6800         case PIPECONF_12BPC:
6801                 pipe_config->pipe_bpp = 36;
6802                 break;
6803         default:
6804                 break;
6805         }
6806
6807         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
6808                 struct intel_shared_dpll *pll;
6809
6810                 pipe_config->has_pch_encoder = true;
6811
6812                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6813                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6814                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6815
6816                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6817
6818                 if (HAS_PCH_IBX(dev_priv->dev)) {
6819                         pipe_config->shared_dpll =
6820                                 (enum intel_dpll_id) crtc->pipe;
6821                 } else {
6822                         tmp = I915_READ(PCH_DPLL_SEL);
6823                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6824                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6825                         else
6826                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6827                 }
6828
6829                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6830
6831                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6832                                            &pipe_config->dpll_hw_state));
6833
6834                 tmp = pipe_config->dpll_hw_state.dpll;
6835                 pipe_config->pixel_multiplier =
6836                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6837                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6838
6839                 ironlake_pch_clock_get(crtc, pipe_config);
6840         } else {
6841                 pipe_config->pixel_multiplier = 1;
6842         }
6843
6844         intel_get_pipe_timings(crtc, pipe_config);
6845
6846         ironlake_get_pfit_config(crtc, pipe_config);
6847
6848         return true;
6849 }
6850
6851 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6852 {
6853         struct drm_device *dev = dev_priv->dev;
6854         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6855         struct intel_crtc *crtc;
6856
6857         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6858                 WARN(crtc->active, "CRTC for pipe %c enabled\n",
6859                      pipe_name(crtc->pipe));
6860
6861         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6862         WARN(plls->spll_refcount, "SPLL enabled\n");
6863         WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6864         WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6865         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6866         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6867              "CPU PWM1 enabled\n");
6868         WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6869              "CPU PWM2 enabled\n");
6870         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6871              "PCH PWM1 enabled\n");
6872         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6873              "Utility pin enabled\n");
6874         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6875
6876         /*
6877          * In theory we can still leave IRQs enabled, as long as only the HPD
6878          * interrupts remain enabled. We used to check for that, but since it's
6879          * gen-specific and since we only disable LCPLL after we fully disable
6880          * the interrupts, the check below should be enough.
6881          */
6882         WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n");
6883 }
6884
6885 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
6886 {
6887         struct drm_device *dev = dev_priv->dev;
6888
6889         if (IS_HASWELL(dev)) {
6890                 mutex_lock(&dev_priv->rps.hw_lock);
6891                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
6892                                             val))
6893                         DRM_ERROR("Failed to disable D_COMP\n");
6894                 mutex_unlock(&dev_priv->rps.hw_lock);
6895         } else {
6896                 I915_WRITE(D_COMP, val);
6897         }
6898         POSTING_READ(D_COMP);
6899 }
6900
6901 /*
6902  * This function implements pieces of two sequences from BSpec:
6903  * - Sequence for display software to disable LCPLL
6904  * - Sequence for display software to allow package C8+
6905  * The steps implemented here are just the steps that actually touch the LCPLL
6906  * register. Callers should take care of disabling all the display engine
6907  * functions, doing the mode unset, fixing interrupts, etc.
6908  */
6909 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6910                               bool switch_to_fclk, bool allow_power_down)
6911 {
6912         uint32_t val;
6913
6914         assert_can_disable_lcpll(dev_priv);
6915
6916         val = I915_READ(LCPLL_CTL);
6917
6918         if (switch_to_fclk) {
6919                 val |= LCPLL_CD_SOURCE_FCLK;
6920                 I915_WRITE(LCPLL_CTL, val);
6921
6922                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6923                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
6924                         DRM_ERROR("Switching to FCLK failed\n");
6925
6926                 val = I915_READ(LCPLL_CTL);
6927         }
6928
6929         val |= LCPLL_PLL_DISABLE;
6930         I915_WRITE(LCPLL_CTL, val);
6931         POSTING_READ(LCPLL_CTL);
6932
6933         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6934                 DRM_ERROR("LCPLL still locked\n");
6935
6936         val = I915_READ(D_COMP);
6937         val |= D_COMP_COMP_DISABLE;
6938         hsw_write_dcomp(dev_priv, val);
6939         ndelay(100);
6940
6941         if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6942                 DRM_ERROR("D_COMP RCOMP still in progress\n");
6943
6944         if (allow_power_down) {
6945                 val = I915_READ(LCPLL_CTL);
6946                 val |= LCPLL_POWER_DOWN_ALLOW;
6947                 I915_WRITE(LCPLL_CTL, val);
6948                 POSTING_READ(LCPLL_CTL);
6949         }
6950 }
6951
6952 /*
6953  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6954  * source.
6955  */
6956 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6957 {
6958         uint32_t val;
6959         unsigned long irqflags;
6960
6961         val = I915_READ(LCPLL_CTL);
6962
6963         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6964                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6965                 return;
6966
6967         /*
6968          * Make sure we're not on PC8 state before disabling PC8, otherwise
6969          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
6970          *
6971          * The other problem is that hsw_restore_lcpll() is called as part of
6972          * the runtime PM resume sequence, so we can't just call
6973          * gen6_gt_force_wake_get() because that function calls
6974          * intel_runtime_pm_get(), and we can't change the runtime PM refcount
6975          * while we are on the resume sequence. So to solve this problem we have
6976          * to call special forcewake code that doesn't touch runtime PM and
6977          * doesn't enable the forcewake delayed work.
6978          */
6979         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
6980         if (dev_priv->uncore.forcewake_count++ == 0)
6981                 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
6982         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
6983
6984         if (val & LCPLL_POWER_DOWN_ALLOW) {
6985                 val &= ~LCPLL_POWER_DOWN_ALLOW;
6986                 I915_WRITE(LCPLL_CTL, val);
6987                 POSTING_READ(LCPLL_CTL);
6988         }
6989
6990         val = I915_READ(D_COMP);
6991         val |= D_COMP_COMP_FORCE;
6992         val &= ~D_COMP_COMP_DISABLE;
6993         hsw_write_dcomp(dev_priv, val);
6994
6995         val = I915_READ(LCPLL_CTL);
6996         val &= ~LCPLL_PLL_DISABLE;
6997         I915_WRITE(LCPLL_CTL, val);
6998
6999         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7000                 DRM_ERROR("LCPLL not locked yet\n");
7001
7002         if (val & LCPLL_CD_SOURCE_FCLK) {
7003                 val = I915_READ(LCPLL_CTL);
7004                 val &= ~LCPLL_CD_SOURCE_FCLK;
7005                 I915_WRITE(LCPLL_CTL, val);
7006
7007                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7008                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7009                         DRM_ERROR("Switching back to LCPLL failed\n");
7010         }
7011
7012         /* See the big comment above. */
7013         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7014         if (--dev_priv->uncore.forcewake_count == 0)
7015                 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7016         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7017 }
7018
7019 /*
7020  * Package states C8 and deeper are really deep PC states that can only be
7021  * reached when all the devices on the system allow it, so even if the graphics
7022  * device allows PC8+, it doesn't mean the system will actually get to these
7023  * states. Our driver only allows PC8+ when going into runtime PM.
7024  *
7025  * The requirements for PC8+ are that all the outputs are disabled, the power
7026  * well is disabled and most interrupts are disabled, and these are also
7027  * requirements for runtime PM. When these conditions are met, we manually do
7028  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7029  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7030  * hang the machine.
7031  *
7032  * When we really reach PC8 or deeper states (not just when we allow it) we lose
7033  * the state of some registers, so when we come back from PC8+ we need to
7034  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7035  * need to take care of the registers kept by RC6. Notice that this happens even
7036  * if we don't put the device in PCI D3 state (which is what currently happens
7037  * because of the runtime PM support).
7038  *
7039  * For more, read "Display Sequences for Package C8" on the hardware
7040  * documentation.
7041  */
7042 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7043 {
7044         struct drm_device *dev = dev_priv->dev;
7045         uint32_t val;
7046
7047         DRM_DEBUG_KMS("Enabling package C8+\n");
7048
7049         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7050                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7051                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7052                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7053         }
7054
7055         lpt_disable_clkout_dp(dev);
7056         intel_runtime_pm_disable_interrupts(dev);
7057         hsw_disable_lcpll(dev_priv, true, true);
7058 }
7059
7060 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7061 {
7062         struct drm_device *dev = dev_priv->dev;
7063         uint32_t val;
7064
7065         DRM_DEBUG_KMS("Disabling package C8+\n");
7066
7067         hsw_restore_lcpll(dev_priv);
7068         intel_runtime_pm_restore_interrupts(dev);
7069         lpt_init_pch_refclk(dev);
7070
7071         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7072                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7073                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7074                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7075         }
7076
7077         intel_prepare_ddi(dev);
7078         i915_gem_init_swizzling(dev);
7079         mutex_lock(&dev_priv->rps.hw_lock);
7080         gen6_update_ring_freq(dev);
7081         mutex_unlock(&dev_priv->rps.hw_lock);
7082 }
7083
7084 static void snb_modeset_global_resources(struct drm_device *dev)
7085 {
7086         modeset_update_crtc_power_domains(dev);
7087 }
7088
7089 static void haswell_modeset_global_resources(struct drm_device *dev)
7090 {
7091         modeset_update_crtc_power_domains(dev);
7092 }
7093
7094 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7095                                  int x, int y,
7096                                  struct drm_framebuffer *fb)
7097 {
7098         struct drm_device *dev = crtc->dev;
7099         struct drm_i915_private *dev_priv = dev->dev_private;
7100         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7101         int plane = intel_crtc->plane;
7102         int ret;
7103
7104         if (!intel_ddi_pll_select(intel_crtc))
7105                 return -EINVAL;
7106         intel_ddi_pll_enable(intel_crtc);
7107
7108         if (intel_crtc->config.has_dp_encoder)
7109                 intel_dp_set_m_n(intel_crtc);
7110
7111         intel_crtc->lowfreq_avail = false;
7112
7113         intel_set_pipe_timings(intel_crtc);
7114
7115         if (intel_crtc->config.has_pch_encoder) {
7116                 intel_cpu_transcoder_set_m_n(intel_crtc,
7117                                              &intel_crtc->config.fdi_m_n);
7118         }
7119
7120         haswell_set_pipeconf(crtc);
7121
7122         intel_set_pipe_csc(crtc);
7123
7124         /* Set up the display plane register */
7125         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
7126         POSTING_READ(DSPCNTR(plane));
7127
7128         ret = intel_pipe_set_base(crtc, x, y, fb);
7129
7130         return ret;
7131 }
7132
7133 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7134                                     struct intel_crtc_config *pipe_config)
7135 {
7136         struct drm_device *dev = crtc->base.dev;
7137         struct drm_i915_private *dev_priv = dev->dev_private;
7138         enum intel_display_power_domain pfit_domain;
7139         uint32_t tmp;
7140
7141         if (!intel_display_power_enabled(dev_priv,
7142                                          POWER_DOMAIN_PIPE(crtc->pipe)))
7143                 return false;
7144
7145         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7146         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7147
7148         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7149         if (tmp & TRANS_DDI_FUNC_ENABLE) {
7150                 enum pipe trans_edp_pipe;
7151                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7152                 default:
7153                         WARN(1, "unknown pipe linked to edp transcoder\n");
7154                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7155                 case TRANS_DDI_EDP_INPUT_A_ON:
7156                         trans_edp_pipe = PIPE_A;
7157                         break;
7158                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7159                         trans_edp_pipe = PIPE_B;
7160                         break;
7161                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7162                         trans_edp_pipe = PIPE_C;
7163                         break;
7164                 }
7165
7166                 if (trans_edp_pipe == crtc->pipe)
7167                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
7168         }
7169
7170         if (!intel_display_power_enabled(dev_priv,
7171                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7172                 return false;
7173
7174         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7175         if (!(tmp & PIPECONF_ENABLE))
7176                 return false;
7177
7178         /*
7179          * Haswell has only FDI/PCH transcoder A. It is which is connected to
7180          * DDI E. So just check whether this pipe is wired to DDI E and whether
7181          * the PCH transcoder is on.
7182          */
7183         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7184         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
7185             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7186                 pipe_config->has_pch_encoder = true;
7187
7188                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7189                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7190                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7191
7192                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7193         }
7194
7195         intel_get_pipe_timings(crtc, pipe_config);
7196
7197         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7198         if (intel_display_power_enabled(dev_priv, pfit_domain))
7199                 ironlake_get_pfit_config(crtc, pipe_config);
7200
7201         if (IS_HASWELL(dev))
7202                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7203                         (I915_READ(IPS_CTL) & IPS_ENABLE);
7204
7205         pipe_config->pixel_multiplier = 1;
7206
7207         return true;
7208 }
7209
7210 static int intel_crtc_mode_set(struct drm_crtc *crtc,
7211                                int x, int y,
7212                                struct drm_framebuffer *fb)
7213 {
7214         struct drm_device *dev = crtc->dev;
7215         struct drm_i915_private *dev_priv = dev->dev_private;
7216         struct intel_encoder *encoder;
7217         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7218         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
7219         int pipe = intel_crtc->pipe;
7220         int ret;
7221
7222         drm_vblank_pre_modeset(dev, pipe);
7223
7224         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
7225
7226         drm_vblank_post_modeset(dev, pipe);
7227
7228         if (ret != 0)
7229                 return ret;
7230
7231         for_each_encoder_on_crtc(dev, crtc, encoder) {
7232                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7233                         encoder->base.base.id,
7234                         drm_get_encoder_name(&encoder->base),
7235                         mode->base.id, mode->name);
7236                 encoder->mode_set(encoder);
7237         }
7238
7239         return 0;
7240 }
7241
7242 static struct {
7243         int clock;
7244         u32 config;
7245 } hdmi_audio_clock[] = {
7246         { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7247         { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7248         { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7249         { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7250         { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7251         { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7252         { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7253         { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7254         { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7255         { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7256 };
7257
7258 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7259 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7260 {
7261         int i;
7262
7263         for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7264                 if (mode->clock == hdmi_audio_clock[i].clock)
7265                         break;
7266         }
7267
7268         if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7269                 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7270                 i = 1;
7271         }
7272
7273         DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7274                       hdmi_audio_clock[i].clock,
7275                       hdmi_audio_clock[i].config);
7276
7277         return hdmi_audio_clock[i].config;
7278 }
7279
7280 static bool intel_eld_uptodate(struct drm_connector *connector,
7281                                int reg_eldv, uint32_t bits_eldv,
7282                                int reg_elda, uint32_t bits_elda,
7283                                int reg_edid)
7284 {
7285         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7286         uint8_t *eld = connector->eld;
7287         uint32_t i;
7288
7289         i = I915_READ(reg_eldv);
7290         i &= bits_eldv;
7291
7292         if (!eld[0])
7293                 return !i;
7294
7295         if (!i)
7296                 return false;
7297
7298         i = I915_READ(reg_elda);
7299         i &= ~bits_elda;
7300         I915_WRITE(reg_elda, i);
7301
7302         for (i = 0; i < eld[2]; i++)
7303                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7304                         return false;
7305
7306         return true;
7307 }
7308
7309 static void g4x_write_eld(struct drm_connector *connector,
7310                           struct drm_crtc *crtc,
7311                           struct drm_display_mode *mode)
7312 {
7313         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7314         uint8_t *eld = connector->eld;
7315         uint32_t eldv;
7316         uint32_t len;
7317         uint32_t i;
7318
7319         i = I915_READ(G4X_AUD_VID_DID);
7320
7321         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7322                 eldv = G4X_ELDV_DEVCL_DEVBLC;
7323         else
7324                 eldv = G4X_ELDV_DEVCTG;
7325
7326         if (intel_eld_uptodate(connector,
7327                                G4X_AUD_CNTL_ST, eldv,
7328                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7329                                G4X_HDMIW_HDMIEDID))
7330                 return;
7331
7332         i = I915_READ(G4X_AUD_CNTL_ST);
7333         i &= ~(eldv | G4X_ELD_ADDR);
7334         len = (i >> 9) & 0x1f;          /* ELD buffer size */
7335         I915_WRITE(G4X_AUD_CNTL_ST, i);
7336
7337         if (!eld[0])
7338                 return;
7339
7340         len = min_t(uint8_t, eld[2], len);
7341         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7342         for (i = 0; i < len; i++)
7343                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7344
7345         i = I915_READ(G4X_AUD_CNTL_ST);
7346         i |= eldv;
7347         I915_WRITE(G4X_AUD_CNTL_ST, i);
7348 }
7349
7350 static void haswell_write_eld(struct drm_connector *connector,
7351                               struct drm_crtc *crtc,
7352                               struct drm_display_mode *mode)
7353 {
7354         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7355         uint8_t *eld = connector->eld;
7356         struct drm_device *dev = crtc->dev;
7357         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7358         uint32_t eldv;
7359         uint32_t i;
7360         int len;
7361         int pipe = to_intel_crtc(crtc)->pipe;
7362         int tmp;
7363
7364         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7365         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7366         int aud_config = HSW_AUD_CFG(pipe);
7367         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7368
7369         /* Audio output enable */
7370         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7371         tmp = I915_READ(aud_cntrl_st2);
7372         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7373         I915_WRITE(aud_cntrl_st2, tmp);
7374
7375         /* Wait for 1 vertical blank */
7376         intel_wait_for_vblank(dev, pipe);
7377
7378         /* Set ELD valid state */
7379         tmp = I915_READ(aud_cntrl_st2);
7380         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7381         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7382         I915_WRITE(aud_cntrl_st2, tmp);
7383         tmp = I915_READ(aud_cntrl_st2);
7384         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7385
7386         /* Enable HDMI mode */
7387         tmp = I915_READ(aud_config);
7388         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7389         /* clear N_programing_enable and N_value_index */
7390         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7391         I915_WRITE(aud_config, tmp);
7392
7393         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7394
7395         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7396         intel_crtc->eld_vld = true;
7397
7398         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7399                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7400                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7401                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7402         } else {
7403                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7404         }
7405
7406         if (intel_eld_uptodate(connector,
7407                                aud_cntrl_st2, eldv,
7408                                aud_cntl_st, IBX_ELD_ADDRESS,
7409                                hdmiw_hdmiedid))
7410                 return;
7411
7412         i = I915_READ(aud_cntrl_st2);
7413         i &= ~eldv;
7414         I915_WRITE(aud_cntrl_st2, i);
7415
7416         if (!eld[0])
7417                 return;
7418
7419         i = I915_READ(aud_cntl_st);
7420         i &= ~IBX_ELD_ADDRESS;
7421         I915_WRITE(aud_cntl_st, i);
7422         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
7423         DRM_DEBUG_DRIVER("port num:%d\n", i);
7424
7425         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7426         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7427         for (i = 0; i < len; i++)
7428                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7429
7430         i = I915_READ(aud_cntrl_st2);
7431         i |= eldv;
7432         I915_WRITE(aud_cntrl_st2, i);
7433
7434 }
7435
7436 static void ironlake_write_eld(struct drm_connector *connector,
7437                                struct drm_crtc *crtc,
7438                                struct drm_display_mode *mode)
7439 {
7440         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7441         uint8_t *eld = connector->eld;
7442         uint32_t eldv;
7443         uint32_t i;
7444         int len;
7445         int hdmiw_hdmiedid;
7446         int aud_config;
7447         int aud_cntl_st;
7448         int aud_cntrl_st2;
7449         int pipe = to_intel_crtc(crtc)->pipe;
7450
7451         if (HAS_PCH_IBX(connector->dev)) {
7452                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7453                 aud_config = IBX_AUD_CFG(pipe);
7454                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7455                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7456         } else if (IS_VALLEYVIEW(connector->dev)) {
7457                 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7458                 aud_config = VLV_AUD_CFG(pipe);
7459                 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7460                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7461         } else {
7462                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7463                 aud_config = CPT_AUD_CFG(pipe);
7464                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7465                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7466         }
7467
7468         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7469
7470         if (IS_VALLEYVIEW(connector->dev))  {
7471                 struct intel_encoder *intel_encoder;
7472                 struct intel_digital_port *intel_dig_port;
7473
7474                 intel_encoder = intel_attached_encoder(connector);
7475                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7476                 i = intel_dig_port->port;
7477         } else {
7478                 i = I915_READ(aud_cntl_st);
7479                 i = (i >> 29) & DIP_PORT_SEL_MASK;
7480                 /* DIP_Port_Select, 0x1 = PortB */
7481         }
7482
7483         if (!i) {
7484                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7485                 /* operate blindly on all ports */
7486                 eldv = IBX_ELD_VALIDB;
7487                 eldv |= IBX_ELD_VALIDB << 4;
7488                 eldv |= IBX_ELD_VALIDB << 8;
7489         } else {
7490                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7491                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7492         }
7493
7494         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7495                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7496                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7497                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7498         } else {
7499                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7500         }
7501
7502         if (intel_eld_uptodate(connector,
7503                                aud_cntrl_st2, eldv,
7504                                aud_cntl_st, IBX_ELD_ADDRESS,
7505                                hdmiw_hdmiedid))
7506                 return;
7507
7508         i = I915_READ(aud_cntrl_st2);
7509         i &= ~eldv;
7510         I915_WRITE(aud_cntrl_st2, i);
7511
7512         if (!eld[0])
7513                 return;
7514
7515         i = I915_READ(aud_cntl_st);
7516         i &= ~IBX_ELD_ADDRESS;
7517         I915_WRITE(aud_cntl_st, i);
7518
7519         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7520         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7521         for (i = 0; i < len; i++)
7522                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7523
7524         i = I915_READ(aud_cntrl_st2);
7525         i |= eldv;
7526         I915_WRITE(aud_cntrl_st2, i);
7527 }
7528
7529 void intel_write_eld(struct drm_encoder *encoder,
7530                      struct drm_display_mode *mode)
7531 {
7532         struct drm_crtc *crtc = encoder->crtc;
7533         struct drm_connector *connector;
7534         struct drm_device *dev = encoder->dev;
7535         struct drm_i915_private *dev_priv = dev->dev_private;
7536
7537         connector = drm_select_eld(encoder, mode);
7538         if (!connector)
7539                 return;
7540
7541         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7542                          connector->base.id,
7543                          drm_get_connector_name(connector),
7544                          connector->encoder->base.id,
7545                          drm_get_encoder_name(connector->encoder));
7546
7547         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7548
7549         if (dev_priv->display.write_eld)
7550                 dev_priv->display.write_eld(connector, crtc, mode);
7551 }
7552
7553 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7554 {
7555         struct drm_device *dev = crtc->dev;
7556         struct drm_i915_private *dev_priv = dev->dev_private;
7557         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7558         bool visible = base != 0;
7559         u32 cntl;
7560
7561         if (intel_crtc->cursor_visible == visible)
7562                 return;
7563
7564         cntl = I915_READ(_CURACNTR);
7565         if (visible) {
7566                 /* On these chipsets we can only modify the base whilst
7567                  * the cursor is disabled.
7568                  */
7569                 I915_WRITE(_CURABASE, base);
7570
7571                 cntl &= ~(CURSOR_FORMAT_MASK);
7572                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7573                 cntl |= CURSOR_ENABLE |
7574                         CURSOR_GAMMA_ENABLE |
7575                         CURSOR_FORMAT_ARGB;
7576         } else
7577                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
7578         I915_WRITE(_CURACNTR, cntl);
7579
7580         intel_crtc->cursor_visible = visible;
7581 }
7582
7583 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7584 {
7585         struct drm_device *dev = crtc->dev;
7586         struct drm_i915_private *dev_priv = dev->dev_private;
7587         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7588         int pipe = intel_crtc->pipe;
7589         bool visible = base != 0;
7590
7591         if (intel_crtc->cursor_visible != visible) {
7592                 int16_t width = intel_crtc->cursor_width;
7593                 uint32_t cntl = I915_READ(CURCNTR(pipe));
7594                 if (base) {
7595                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7596                         cntl |= MCURSOR_GAMMA_ENABLE;
7597
7598                         switch (width) {
7599                         case 64:
7600                                 cntl |= CURSOR_MODE_64_ARGB_AX;
7601                                 break;
7602                         case 128:
7603                                 cntl |= CURSOR_MODE_128_ARGB_AX;
7604                                 break;
7605                         case 256:
7606                                 cntl |= CURSOR_MODE_256_ARGB_AX;
7607                                 break;
7608                         default:
7609                                 WARN_ON(1);
7610                                 return;
7611                         }
7612                         cntl |= pipe << 28; /* Connect to correct pipe */
7613                 } else {
7614                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7615                         cntl |= CURSOR_MODE_DISABLE;
7616                 }
7617                 I915_WRITE(CURCNTR(pipe), cntl);
7618
7619                 intel_crtc->cursor_visible = visible;
7620         }
7621         /* and commit changes on next vblank */
7622         POSTING_READ(CURCNTR(pipe));
7623         I915_WRITE(CURBASE(pipe), base);
7624         POSTING_READ(CURBASE(pipe));
7625 }
7626
7627 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7628 {
7629         struct drm_device *dev = crtc->dev;
7630         struct drm_i915_private *dev_priv = dev->dev_private;
7631         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7632         int pipe = intel_crtc->pipe;
7633         bool visible = base != 0;
7634
7635         if (intel_crtc->cursor_visible != visible) {
7636                 int16_t width = intel_crtc->cursor_width;
7637                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7638                 if (base) {
7639                         cntl &= ~CURSOR_MODE;
7640                         cntl |= MCURSOR_GAMMA_ENABLE;
7641                         switch (width) {
7642                         case 64:
7643                                 cntl |= CURSOR_MODE_64_ARGB_AX;
7644                                 break;
7645                         case 128:
7646                                 cntl |= CURSOR_MODE_128_ARGB_AX;
7647                                 break;
7648                         case 256:
7649                                 cntl |= CURSOR_MODE_256_ARGB_AX;
7650                                 break;
7651                         default:
7652                                 WARN_ON(1);
7653                                 return;
7654                         }
7655                 } else {
7656                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7657                         cntl |= CURSOR_MODE_DISABLE;
7658                 }
7659                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7660                         cntl |= CURSOR_PIPE_CSC_ENABLE;
7661                         cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7662                 }
7663                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7664
7665                 intel_crtc->cursor_visible = visible;
7666         }
7667         /* and commit changes on next vblank */
7668         POSTING_READ(CURCNTR_IVB(pipe));
7669         I915_WRITE(CURBASE_IVB(pipe), base);
7670         POSTING_READ(CURBASE_IVB(pipe));
7671 }
7672
7673 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7674 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7675                                      bool on)
7676 {
7677         struct drm_device *dev = crtc->dev;
7678         struct drm_i915_private *dev_priv = dev->dev_private;
7679         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7680         int pipe = intel_crtc->pipe;
7681         int x = intel_crtc->cursor_x;
7682         int y = intel_crtc->cursor_y;
7683         u32 base = 0, pos = 0;
7684         bool visible;
7685
7686         if (on)
7687                 base = intel_crtc->cursor_addr;
7688
7689         if (x >= intel_crtc->config.pipe_src_w)
7690                 base = 0;
7691
7692         if (y >= intel_crtc->config.pipe_src_h)
7693                 base = 0;
7694
7695         if (x < 0) {
7696                 if (x + intel_crtc->cursor_width <= 0)
7697                         base = 0;
7698
7699                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7700                 x = -x;
7701         }
7702         pos |= x << CURSOR_X_SHIFT;
7703
7704         if (y < 0) {
7705                 if (y + intel_crtc->cursor_height <= 0)
7706                         base = 0;
7707
7708                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7709                 y = -y;
7710         }
7711         pos |= y << CURSOR_Y_SHIFT;
7712
7713         visible = base != 0;
7714         if (!visible && !intel_crtc->cursor_visible)
7715                 return;
7716
7717         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7718                 I915_WRITE(CURPOS_IVB(pipe), pos);
7719                 ivb_update_cursor(crtc, base);
7720         } else {
7721                 I915_WRITE(CURPOS(pipe), pos);
7722                 if (IS_845G(dev) || IS_I865G(dev))
7723                         i845_update_cursor(crtc, base);
7724                 else
7725                         i9xx_update_cursor(crtc, base);
7726         }
7727 }
7728
7729 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
7730                                  struct drm_file *file,
7731                                  uint32_t handle,
7732                                  uint32_t width, uint32_t height)
7733 {
7734         struct drm_device *dev = crtc->dev;
7735         struct drm_i915_private *dev_priv = dev->dev_private;
7736         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7737         struct drm_i915_gem_object *obj;
7738         unsigned old_width;
7739         uint32_t addr;
7740         int ret;
7741
7742         /* if we want to turn off the cursor ignore width and height */
7743         if (!handle) {
7744                 DRM_DEBUG_KMS("cursor off\n");
7745                 addr = 0;
7746                 obj = NULL;
7747                 mutex_lock(&dev->struct_mutex);
7748                 goto finish;
7749         }
7750
7751         /* Check for which cursor types we support */
7752         if (!((width == 64 && height == 64) ||
7753                         (width == 128 && height == 128 && !IS_GEN2(dev)) ||
7754                         (width == 256 && height == 256 && !IS_GEN2(dev)))) {
7755                 DRM_DEBUG("Cursor dimension not supported\n");
7756                 return -EINVAL;
7757         }
7758
7759         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
7760         if (&obj->base == NULL)
7761                 return -ENOENT;
7762
7763         if (obj->base.size < width * height * 4) {
7764                 DRM_DEBUG_KMS("buffer is to small\n");
7765                 ret = -ENOMEM;
7766                 goto fail;
7767         }
7768
7769         /* we only need to pin inside GTT if cursor is non-phy */
7770         mutex_lock(&dev->struct_mutex);
7771         if (!INTEL_INFO(dev)->cursor_needs_physical) {
7772                 unsigned alignment;
7773
7774                 if (obj->tiling_mode) {
7775                         DRM_DEBUG_KMS("cursor cannot be tiled\n");
7776                         ret = -EINVAL;
7777                         goto fail_locked;
7778                 }
7779
7780                 /* Note that the w/a also requires 2 PTE of padding following
7781                  * the bo. We currently fill all unused PTE with the shadow
7782                  * page and so we should always have valid PTE following the
7783                  * cursor preventing the VT-d warning.
7784                  */
7785                 alignment = 0;
7786                 if (need_vtd_wa(dev))
7787                         alignment = 64*1024;
7788
7789                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
7790                 if (ret) {
7791                         DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
7792                         goto fail_locked;
7793                 }
7794
7795                 ret = i915_gem_object_put_fence(obj);
7796                 if (ret) {
7797                         DRM_DEBUG_KMS("failed to release fence for cursor");
7798                         goto fail_unpin;
7799                 }
7800
7801                 addr = i915_gem_obj_ggtt_offset(obj);
7802         } else {
7803                 int align = IS_I830(dev) ? 16 * 1024 : 256;
7804                 ret = i915_gem_attach_phys_object(dev, obj,
7805                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7806                                                   align);
7807                 if (ret) {
7808                         DRM_DEBUG_KMS("failed to attach phys object\n");
7809                         goto fail_locked;
7810                 }
7811                 addr = obj->phys_obj->handle->busaddr;
7812         }
7813
7814         if (IS_GEN2(dev))
7815                 I915_WRITE(CURSIZE, (height << 12) | width);
7816
7817  finish:
7818         if (intel_crtc->cursor_bo) {
7819                 if (INTEL_INFO(dev)->cursor_needs_physical) {
7820                         if (intel_crtc->cursor_bo != obj)
7821                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7822                 } else
7823                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
7824                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
7825         }
7826
7827         mutex_unlock(&dev->struct_mutex);
7828
7829         old_width = intel_crtc->cursor_width;
7830
7831         intel_crtc->cursor_addr = addr;
7832         intel_crtc->cursor_bo = obj;
7833         intel_crtc->cursor_width = width;
7834         intel_crtc->cursor_height = height;
7835
7836         if (intel_crtc->active) {
7837                 if (old_width != width)
7838                         intel_update_watermarks(crtc);
7839                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7840         }
7841
7842         return 0;
7843 fail_unpin:
7844         i915_gem_object_unpin_from_display_plane(obj);
7845 fail_locked:
7846         mutex_unlock(&dev->struct_mutex);
7847 fail:
7848         drm_gem_object_unreference_unlocked(&obj->base);
7849         return ret;
7850 }
7851
7852 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7853 {
7854         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7855
7856         intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
7857         intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
7858
7859         if (intel_crtc->active)
7860                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7861
7862         return 0;
7863 }
7864
7865 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7866                                  u16 *blue, uint32_t start, uint32_t size)
7867 {
7868         int end = (start + size > 256) ? 256 : start + size, i;
7869         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7870
7871         for (i = start; i < end; i++) {
7872                 intel_crtc->lut_r[i] = red[i] >> 8;
7873                 intel_crtc->lut_g[i] = green[i] >> 8;
7874                 intel_crtc->lut_b[i] = blue[i] >> 8;
7875         }
7876
7877         intel_crtc_load_lut(crtc);
7878 }
7879
7880 /* VESA 640x480x72Hz mode to set on the pipe */
7881 static struct drm_display_mode load_detect_mode = {
7882         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7883                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7884 };
7885
7886 struct drm_framebuffer *
7887 __intel_framebuffer_create(struct drm_device *dev,
7888                            struct drm_mode_fb_cmd2 *mode_cmd,
7889                            struct drm_i915_gem_object *obj)
7890 {
7891         struct intel_framebuffer *intel_fb;
7892         int ret;
7893
7894         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7895         if (!intel_fb) {
7896                 drm_gem_object_unreference_unlocked(&obj->base);
7897                 return ERR_PTR(-ENOMEM);
7898         }
7899
7900         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7901         if (ret)
7902                 goto err;
7903
7904         return &intel_fb->base;
7905 err:
7906         drm_gem_object_unreference_unlocked(&obj->base);
7907         kfree(intel_fb);
7908
7909         return ERR_PTR(ret);
7910 }
7911
7912 static struct drm_framebuffer *
7913 intel_framebuffer_create(struct drm_device *dev,
7914                          struct drm_mode_fb_cmd2 *mode_cmd,
7915                          struct drm_i915_gem_object *obj)
7916 {
7917         struct drm_framebuffer *fb;
7918         int ret;
7919
7920         ret = i915_mutex_lock_interruptible(dev);
7921         if (ret)
7922                 return ERR_PTR(ret);
7923         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
7924         mutex_unlock(&dev->struct_mutex);
7925
7926         return fb;
7927 }
7928
7929 static u32
7930 intel_framebuffer_pitch_for_width(int width, int bpp)
7931 {
7932         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7933         return ALIGN(pitch, 64);
7934 }
7935
7936 static u32
7937 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7938 {
7939         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7940         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7941 }
7942
7943 static struct drm_framebuffer *
7944 intel_framebuffer_create_for_mode(struct drm_device *dev,
7945                                   struct drm_display_mode *mode,
7946                                   int depth, int bpp)
7947 {
7948         struct drm_i915_gem_object *obj;
7949         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
7950
7951         obj = i915_gem_alloc_object(dev,
7952                                     intel_framebuffer_size_for_mode(mode, bpp));
7953         if (obj == NULL)
7954                 return ERR_PTR(-ENOMEM);
7955
7956         mode_cmd.width = mode->hdisplay;
7957         mode_cmd.height = mode->vdisplay;
7958         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7959                                                                 bpp);
7960         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7961
7962         return intel_framebuffer_create(dev, &mode_cmd, obj);
7963 }
7964
7965 static struct drm_framebuffer *
7966 mode_fits_in_fbdev(struct drm_device *dev,
7967                    struct drm_display_mode *mode)
7968 {
7969 #ifdef CONFIG_DRM_I915_FBDEV
7970         struct drm_i915_private *dev_priv = dev->dev_private;
7971         struct drm_i915_gem_object *obj;
7972         struct drm_framebuffer *fb;
7973
7974         if (!dev_priv->fbdev)
7975                 return NULL;
7976
7977         if (!dev_priv->fbdev->fb)
7978                 return NULL;
7979
7980         obj = dev_priv->fbdev->fb->obj;
7981         BUG_ON(!obj);
7982
7983         fb = &dev_priv->fbdev->fb->base;
7984         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7985                                                                fb->bits_per_pixel))
7986                 return NULL;
7987
7988         if (obj->base.size < mode->vdisplay * fb->pitches[0])
7989                 return NULL;
7990
7991         return fb;
7992 #else
7993         return NULL;
7994 #endif
7995 }
7996
7997 bool intel_get_load_detect_pipe(struct drm_connector *connector,
7998                                 struct drm_display_mode *mode,
7999                                 struct intel_load_detect_pipe *old)
8000 {
8001         struct intel_crtc *intel_crtc;
8002         struct intel_encoder *intel_encoder =
8003                 intel_attached_encoder(connector);
8004         struct drm_crtc *possible_crtc;
8005         struct drm_encoder *encoder = &intel_encoder->base;
8006         struct drm_crtc *crtc = NULL;
8007         struct drm_device *dev = encoder->dev;
8008         struct drm_framebuffer *fb;
8009         int i = -1;
8010
8011         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8012                       connector->base.id, drm_get_connector_name(connector),
8013                       encoder->base.id, drm_get_encoder_name(encoder));
8014
8015         /*
8016          * Algorithm gets a little messy:
8017          *
8018          *   - if the connector already has an assigned crtc, use it (but make
8019          *     sure it's on first)
8020          *
8021          *   - try to find the first unused crtc that can drive this connector,
8022          *     and use that if we find one
8023          */
8024
8025         /* See if we already have a CRTC for this connector */
8026         if (encoder->crtc) {
8027                 crtc = encoder->crtc;
8028
8029                 mutex_lock(&crtc->mutex);
8030
8031                 old->dpms_mode = connector->dpms;
8032                 old->load_detect_temp = false;
8033
8034                 /* Make sure the crtc and connector are running */
8035                 if (connector->dpms != DRM_MODE_DPMS_ON)
8036                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8037
8038                 return true;
8039         }
8040
8041         /* Find an unused one (if possible) */
8042         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
8043                 i++;
8044                 if (!(encoder->possible_crtcs & (1 << i)))
8045                         continue;
8046                 if (!possible_crtc->enabled) {
8047                         crtc = possible_crtc;
8048                         break;
8049                 }
8050         }
8051
8052         /*
8053          * If we didn't find an unused CRTC, don't use any.
8054          */
8055         if (!crtc) {
8056                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8057                 return false;
8058         }
8059
8060         mutex_lock(&crtc->mutex);
8061         intel_encoder->new_crtc = to_intel_crtc(crtc);
8062         to_intel_connector(connector)->new_encoder = intel_encoder;
8063
8064         intel_crtc = to_intel_crtc(crtc);
8065         intel_crtc->new_enabled = true;
8066         intel_crtc->new_config = &intel_crtc->config;
8067         old->dpms_mode = connector->dpms;
8068         old->load_detect_temp = true;
8069         old->release_fb = NULL;
8070
8071         if (!mode)
8072                 mode = &load_detect_mode;
8073
8074         /* We need a framebuffer large enough to accommodate all accesses
8075          * that the plane may generate whilst we perform load detection.
8076          * We can not rely on the fbcon either being present (we get called
8077          * during its initialisation to detect all boot displays, or it may
8078          * not even exist) or that it is large enough to satisfy the
8079          * requested mode.
8080          */
8081         fb = mode_fits_in_fbdev(dev, mode);
8082         if (fb == NULL) {
8083                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8084                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8085                 old->release_fb = fb;
8086         } else
8087                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8088         if (IS_ERR(fb)) {
8089                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8090                 goto fail;
8091         }
8092
8093         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8094                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8095                 if (old->release_fb)
8096                         old->release_fb->funcs->destroy(old->release_fb);
8097                 goto fail;
8098         }
8099
8100         /* let the connector get through one full cycle before testing */
8101         intel_wait_for_vblank(dev, intel_crtc->pipe);
8102         return true;
8103
8104  fail:
8105         intel_crtc->new_enabled = crtc->enabled;
8106         if (intel_crtc->new_enabled)
8107                 intel_crtc->new_config = &intel_crtc->config;
8108         else
8109                 intel_crtc->new_config = NULL;
8110         mutex_unlock(&crtc->mutex);
8111         return false;
8112 }
8113
8114 void intel_release_load_detect_pipe(struct drm_connector *connector,
8115                                     struct intel_load_detect_pipe *old)
8116 {
8117         struct intel_encoder *intel_encoder =
8118                 intel_attached_encoder(connector);
8119         struct drm_encoder *encoder = &intel_encoder->base;
8120         struct drm_crtc *crtc = encoder->crtc;
8121         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8122
8123         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8124                       connector->base.id, drm_get_connector_name(connector),
8125                       encoder->base.id, drm_get_encoder_name(encoder));
8126
8127         if (old->load_detect_temp) {
8128                 to_intel_connector(connector)->new_encoder = NULL;
8129                 intel_encoder->new_crtc = NULL;
8130                 intel_crtc->new_enabled = false;
8131                 intel_crtc->new_config = NULL;
8132                 intel_set_mode(crtc, NULL, 0, 0, NULL);
8133
8134                 if (old->release_fb) {
8135                         drm_framebuffer_unregister_private(old->release_fb);
8136                         drm_framebuffer_unreference(old->release_fb);
8137                 }
8138
8139                 mutex_unlock(&crtc->mutex);
8140                 return;
8141         }
8142
8143         /* Switch crtc and encoder back off if necessary */
8144         if (old->dpms_mode != DRM_MODE_DPMS_ON)
8145                 connector->funcs->dpms(connector, old->dpms_mode);
8146
8147         mutex_unlock(&crtc->mutex);
8148 }
8149
8150 static int i9xx_pll_refclk(struct drm_device *dev,
8151                            const struct intel_crtc_config *pipe_config)
8152 {
8153         struct drm_i915_private *dev_priv = dev->dev_private;
8154         u32 dpll = pipe_config->dpll_hw_state.dpll;
8155
8156         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8157                 return dev_priv->vbt.lvds_ssc_freq;
8158         else if (HAS_PCH_SPLIT(dev))
8159                 return 120000;
8160         else if (!IS_GEN2(dev))
8161                 return 96000;
8162         else
8163                 return 48000;
8164 }
8165
8166 /* Returns the clock of the currently programmed mode of the given pipe. */
8167 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8168                                 struct intel_crtc_config *pipe_config)
8169 {
8170         struct drm_device *dev = crtc->base.dev;
8171         struct drm_i915_private *dev_priv = dev->dev_private;
8172         int pipe = pipe_config->cpu_transcoder;
8173         u32 dpll = pipe_config->dpll_hw_state.dpll;
8174         u32 fp;
8175         intel_clock_t clock;
8176         int refclk = i9xx_pll_refclk(dev, pipe_config);
8177
8178         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8179                 fp = pipe_config->dpll_hw_state.fp0;
8180         else
8181                 fp = pipe_config->dpll_hw_state.fp1;
8182
8183         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8184         if (IS_PINEVIEW(dev)) {
8185                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8186                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8187         } else {
8188                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8189                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8190         }
8191
8192         if (!IS_GEN2(dev)) {
8193                 if (IS_PINEVIEW(dev))
8194                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8195                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8196                 else
8197                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8198                                DPLL_FPA01_P1_POST_DIV_SHIFT);
8199
8200                 switch (dpll & DPLL_MODE_MASK) {
8201                 case DPLLB_MODE_DAC_SERIAL:
8202                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8203                                 5 : 10;
8204                         break;
8205                 case DPLLB_MODE_LVDS:
8206                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8207                                 7 : 14;
8208                         break;
8209                 default:
8210                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8211                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
8212                         return;
8213                 }
8214
8215                 if (IS_PINEVIEW(dev))
8216                         pineview_clock(refclk, &clock);
8217                 else
8218                         i9xx_clock(refclk, &clock);
8219         } else {
8220                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8221                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8222
8223                 if (is_lvds) {
8224                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8225                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
8226
8227                         if (lvds & LVDS_CLKB_POWER_UP)
8228                                 clock.p2 = 7;
8229                         else
8230                                 clock.p2 = 14;
8231                 } else {
8232                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
8233                                 clock.p1 = 2;
8234                         else {
8235                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8236                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8237                         }
8238                         if (dpll & PLL_P2_DIVIDE_BY_4)
8239                                 clock.p2 = 4;
8240                         else
8241                                 clock.p2 = 2;
8242                 }
8243
8244                 i9xx_clock(refclk, &clock);
8245         }
8246
8247         /*
8248          * This value includes pixel_multiplier. We will use
8249          * port_clock to compute adjusted_mode.crtc_clock in the
8250          * encoder's get_config() function.
8251          */
8252         pipe_config->port_clock = clock.dot;
8253 }
8254
8255 int intel_dotclock_calculate(int link_freq,
8256                              const struct intel_link_m_n *m_n)
8257 {
8258         /*
8259          * The calculation for the data clock is:
8260          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8261          * But we want to avoid losing precison if possible, so:
8262          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8263          *
8264          * and the link clock is simpler:
8265          * link_clock = (m * link_clock) / n
8266          */
8267
8268         if (!m_n->link_n)
8269                 return 0;
8270
8271         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8272 }
8273
8274 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8275                                    struct intel_crtc_config *pipe_config)
8276 {
8277         struct drm_device *dev = crtc->base.dev;
8278
8279         /* read out port_clock from the DPLL */
8280         i9xx_crtc_clock_get(crtc, pipe_config);
8281
8282         /*
8283          * This value does not include pixel_multiplier.
8284          * We will check that port_clock and adjusted_mode.crtc_clock
8285          * agree once we know their relationship in the encoder's
8286          * get_config() function.
8287          */
8288         pipe_config->adjusted_mode.crtc_clock =
8289                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8290                                          &pipe_config->fdi_m_n);
8291 }
8292
8293 /** Returns the currently programmed mode of the given pipe. */
8294 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8295                                              struct drm_crtc *crtc)
8296 {
8297         struct drm_i915_private *dev_priv = dev->dev_private;
8298         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8299         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8300         struct drm_display_mode *mode;
8301         struct intel_crtc_config pipe_config;
8302         int htot = I915_READ(HTOTAL(cpu_transcoder));
8303         int hsync = I915_READ(HSYNC(cpu_transcoder));
8304         int vtot = I915_READ(VTOTAL(cpu_transcoder));
8305         int vsync = I915_READ(VSYNC(cpu_transcoder));
8306         enum pipe pipe = intel_crtc->pipe;
8307
8308         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8309         if (!mode)
8310                 return NULL;
8311
8312         /*
8313          * Construct a pipe_config sufficient for getting the clock info
8314          * back out of crtc_clock_get.
8315          *
8316          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8317          * to use a real value here instead.
8318          */
8319         pipe_config.cpu_transcoder = (enum transcoder) pipe;
8320         pipe_config.pixel_multiplier = 1;
8321         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8322         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8323         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8324         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8325
8326         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8327         mode->hdisplay = (htot & 0xffff) + 1;
8328         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8329         mode->hsync_start = (hsync & 0xffff) + 1;
8330         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8331         mode->vdisplay = (vtot & 0xffff) + 1;
8332         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8333         mode->vsync_start = (vsync & 0xffff) + 1;
8334         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8335
8336         drm_mode_set_name(mode);
8337
8338         return mode;
8339 }
8340
8341 static void intel_increase_pllclock(struct drm_crtc *crtc)
8342 {
8343         struct drm_device *dev = crtc->dev;
8344         struct drm_i915_private *dev_priv = dev->dev_private;
8345         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8346         int pipe = intel_crtc->pipe;
8347         int dpll_reg = DPLL(pipe);
8348         int dpll;
8349
8350         if (HAS_PCH_SPLIT(dev))
8351                 return;
8352
8353         if (!dev_priv->lvds_downclock_avail)
8354                 return;
8355
8356         dpll = I915_READ(dpll_reg);
8357         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8358                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8359
8360                 assert_panel_unlocked(dev_priv, pipe);
8361
8362                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8363                 I915_WRITE(dpll_reg, dpll);
8364                 intel_wait_for_vblank(dev, pipe);
8365
8366                 dpll = I915_READ(dpll_reg);
8367                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8368                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8369         }
8370 }
8371
8372 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8373 {
8374         struct drm_device *dev = crtc->dev;
8375         struct drm_i915_private *dev_priv = dev->dev_private;
8376         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8377
8378         if (HAS_PCH_SPLIT(dev))
8379                 return;
8380
8381         if (!dev_priv->lvds_downclock_avail)
8382                 return;
8383
8384         /*
8385          * Since this is called by a timer, we should never get here in
8386          * the manual case.
8387          */
8388         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8389                 int pipe = intel_crtc->pipe;
8390                 int dpll_reg = DPLL(pipe);
8391                 int dpll;
8392
8393                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8394
8395                 assert_panel_unlocked(dev_priv, pipe);
8396
8397                 dpll = I915_READ(dpll_reg);
8398                 dpll |= DISPLAY_RATE_SELECT_FPA1;
8399                 I915_WRITE(dpll_reg, dpll);
8400                 intel_wait_for_vblank(dev, pipe);
8401                 dpll = I915_READ(dpll_reg);
8402                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8403                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8404         }
8405
8406 }
8407
8408 void intel_mark_busy(struct drm_device *dev)
8409 {
8410         struct drm_i915_private *dev_priv = dev->dev_private;
8411
8412         if (dev_priv->mm.busy)
8413                 return;
8414
8415         intel_runtime_pm_get(dev_priv);
8416         i915_update_gfx_val(dev_priv);
8417         dev_priv->mm.busy = true;
8418 }
8419
8420 void intel_mark_idle(struct drm_device *dev)
8421 {
8422         struct drm_i915_private *dev_priv = dev->dev_private;
8423         struct drm_crtc *crtc;
8424
8425         if (!dev_priv->mm.busy)
8426                 return;
8427
8428         dev_priv->mm.busy = false;
8429
8430         if (!i915.powersave)
8431                 goto out;
8432
8433         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8434                 if (!crtc->primary->fb)
8435                         continue;
8436
8437                 intel_decrease_pllclock(crtc);
8438         }
8439
8440         if (INTEL_INFO(dev)->gen >= 6)
8441                 gen6_rps_idle(dev->dev_private);
8442
8443 out:
8444         intel_runtime_pm_put(dev_priv);
8445 }
8446
8447 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
8448                         struct intel_ring_buffer *ring)
8449 {
8450         struct drm_device *dev = obj->base.dev;
8451         struct drm_crtc *crtc;
8452
8453         if (!i915.powersave)
8454                 return;
8455
8456         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8457                 if (!crtc->primary->fb)
8458                         continue;
8459
8460                 if (to_intel_framebuffer(crtc->primary->fb)->obj != obj)
8461                         continue;
8462
8463                 intel_increase_pllclock(crtc);
8464                 if (ring && intel_fbc_enabled(dev))
8465                         ring->fbc_dirty = true;
8466         }
8467 }
8468
8469 static void intel_crtc_destroy(struct drm_crtc *crtc)
8470 {
8471         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8472         struct drm_device *dev = crtc->dev;
8473         struct intel_unpin_work *work;
8474         unsigned long flags;
8475
8476         spin_lock_irqsave(&dev->event_lock, flags);
8477         work = intel_crtc->unpin_work;
8478         intel_crtc->unpin_work = NULL;
8479         spin_unlock_irqrestore(&dev->event_lock, flags);
8480
8481         if (work) {
8482                 cancel_work_sync(&work->work);
8483                 kfree(work);
8484         }
8485
8486         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
8487
8488         drm_crtc_cleanup(crtc);
8489
8490         kfree(intel_crtc);
8491 }
8492
8493 static void intel_unpin_work_fn(struct work_struct *__work)
8494 {
8495         struct intel_unpin_work *work =
8496                 container_of(__work, struct intel_unpin_work, work);
8497         struct drm_device *dev = work->crtc->dev;
8498
8499         mutex_lock(&dev->struct_mutex);
8500         intel_unpin_fb_obj(work->old_fb_obj);
8501         drm_gem_object_unreference(&work->pending_flip_obj->base);
8502         drm_gem_object_unreference(&work->old_fb_obj->base);
8503
8504         intel_update_fbc(dev);
8505         mutex_unlock(&dev->struct_mutex);
8506
8507         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8508         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8509
8510         kfree(work);
8511 }
8512
8513 static void do_intel_finish_page_flip(struct drm_device *dev,
8514                                       struct drm_crtc *crtc)
8515 {
8516         struct drm_i915_private *dev_priv = dev->dev_private;
8517         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8518         struct intel_unpin_work *work;
8519         unsigned long flags;
8520
8521         /* Ignore early vblank irqs */
8522         if (intel_crtc == NULL)
8523                 return;
8524
8525         spin_lock_irqsave(&dev->event_lock, flags);
8526         work = intel_crtc->unpin_work;
8527
8528         /* Ensure we don't miss a work->pending update ... */
8529         smp_rmb();
8530
8531         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8532                 spin_unlock_irqrestore(&dev->event_lock, flags);
8533                 return;
8534         }
8535
8536         /* and that the unpin work is consistent wrt ->pending. */
8537         smp_rmb();
8538
8539         intel_crtc->unpin_work = NULL;
8540
8541         if (work->event)
8542                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
8543
8544         drm_vblank_put(dev, intel_crtc->pipe);
8545
8546         spin_unlock_irqrestore(&dev->event_lock, flags);
8547
8548         wake_up_all(&dev_priv->pending_flip_queue);
8549
8550         queue_work(dev_priv->wq, &work->work);
8551
8552         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
8553 }
8554
8555 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8556 {
8557         struct drm_i915_private *dev_priv = dev->dev_private;
8558         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8559
8560         do_intel_finish_page_flip(dev, crtc);
8561 }
8562
8563 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8564 {
8565         struct drm_i915_private *dev_priv = dev->dev_private;
8566         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8567
8568         do_intel_finish_page_flip(dev, crtc);
8569 }
8570
8571 void intel_prepare_page_flip(struct drm_device *dev, int plane)
8572 {
8573         struct drm_i915_private *dev_priv = dev->dev_private;
8574         struct intel_crtc *intel_crtc =
8575                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8576         unsigned long flags;
8577
8578         /* NB: An MMIO update of the plane base pointer will also
8579          * generate a page-flip completion irq, i.e. every modeset
8580          * is also accompanied by a spurious intel_prepare_page_flip().
8581          */
8582         spin_lock_irqsave(&dev->event_lock, flags);
8583         if (intel_crtc->unpin_work)
8584                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
8585         spin_unlock_irqrestore(&dev->event_lock, flags);
8586 }
8587
8588 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8589 {
8590         /* Ensure that the work item is consistent when activating it ... */
8591         smp_wmb();
8592         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8593         /* and that it is marked active as soon as the irq could fire. */
8594         smp_wmb();
8595 }
8596
8597 static int intel_gen2_queue_flip(struct drm_device *dev,
8598                                  struct drm_crtc *crtc,
8599                                  struct drm_framebuffer *fb,
8600                                  struct drm_i915_gem_object *obj,
8601                                  uint32_t flags)
8602 {
8603         struct drm_i915_private *dev_priv = dev->dev_private;
8604         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8605         u32 flip_mask;
8606         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8607         int ret;
8608
8609         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8610         if (ret)
8611                 goto err;
8612
8613         ret = intel_ring_begin(ring, 6);
8614         if (ret)
8615                 goto err_unpin;
8616
8617         /* Can't queue multiple flips, so wait for the previous
8618          * one to finish before executing the next.
8619          */
8620         if (intel_crtc->plane)
8621                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8622         else
8623                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8624         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8625         intel_ring_emit(ring, MI_NOOP);
8626         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8627                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8628         intel_ring_emit(ring, fb->pitches[0]);
8629         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8630         intel_ring_emit(ring, 0); /* aux display base address, unused */
8631
8632         intel_mark_page_flip_active(intel_crtc);
8633         __intel_ring_advance(ring);
8634         return 0;
8635
8636 err_unpin:
8637         intel_unpin_fb_obj(obj);
8638 err:
8639         return ret;
8640 }
8641
8642 static int intel_gen3_queue_flip(struct drm_device *dev,
8643                                  struct drm_crtc *crtc,
8644                                  struct drm_framebuffer *fb,
8645                                  struct drm_i915_gem_object *obj,
8646                                  uint32_t flags)
8647 {
8648         struct drm_i915_private *dev_priv = dev->dev_private;
8649         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8650         u32 flip_mask;
8651         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8652         int ret;
8653
8654         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8655         if (ret)
8656                 goto err;
8657
8658         ret = intel_ring_begin(ring, 6);
8659         if (ret)
8660                 goto err_unpin;
8661
8662         if (intel_crtc->plane)
8663                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8664         else
8665                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8666         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8667         intel_ring_emit(ring, MI_NOOP);
8668         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8669                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8670         intel_ring_emit(ring, fb->pitches[0]);
8671         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8672         intel_ring_emit(ring, MI_NOOP);
8673
8674         intel_mark_page_flip_active(intel_crtc);
8675         __intel_ring_advance(ring);
8676         return 0;
8677
8678 err_unpin:
8679         intel_unpin_fb_obj(obj);
8680 err:
8681         return ret;
8682 }
8683
8684 static int intel_gen4_queue_flip(struct drm_device *dev,
8685                                  struct drm_crtc *crtc,
8686                                  struct drm_framebuffer *fb,
8687                                  struct drm_i915_gem_object *obj,
8688                                  uint32_t flags)
8689 {
8690         struct drm_i915_private *dev_priv = dev->dev_private;
8691         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8692         uint32_t pf, pipesrc;
8693         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8694         int ret;
8695
8696         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8697         if (ret)
8698                 goto err;
8699
8700         ret = intel_ring_begin(ring, 4);
8701         if (ret)
8702                 goto err_unpin;
8703
8704         /* i965+ uses the linear or tiled offsets from the
8705          * Display Registers (which do not change across a page-flip)
8706          * so we need only reprogram the base address.
8707          */
8708         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8709                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8710         intel_ring_emit(ring, fb->pitches[0]);
8711         intel_ring_emit(ring,
8712                         (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
8713                         obj->tiling_mode);
8714
8715         /* XXX Enabling the panel-fitter across page-flip is so far
8716          * untested on non-native modes, so ignore it for now.
8717          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8718          */
8719         pf = 0;
8720         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8721         intel_ring_emit(ring, pf | pipesrc);
8722
8723         intel_mark_page_flip_active(intel_crtc);
8724         __intel_ring_advance(ring);
8725         return 0;
8726
8727 err_unpin:
8728         intel_unpin_fb_obj(obj);
8729 err:
8730         return ret;
8731 }
8732
8733 static int intel_gen6_queue_flip(struct drm_device *dev,
8734                                  struct drm_crtc *crtc,
8735                                  struct drm_framebuffer *fb,
8736                                  struct drm_i915_gem_object *obj,
8737                                  uint32_t flags)
8738 {
8739         struct drm_i915_private *dev_priv = dev->dev_private;
8740         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8741         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8742         uint32_t pf, pipesrc;
8743         int ret;
8744
8745         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8746         if (ret)
8747                 goto err;
8748
8749         ret = intel_ring_begin(ring, 4);
8750         if (ret)
8751                 goto err_unpin;
8752
8753         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8754                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8755         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
8756         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8757
8758         /* Contrary to the suggestions in the documentation,
8759          * "Enable Panel Fitter" does not seem to be required when page
8760          * flipping with a non-native mode, and worse causes a normal
8761          * modeset to fail.
8762          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8763          */
8764         pf = 0;
8765         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8766         intel_ring_emit(ring, pf | pipesrc);
8767
8768         intel_mark_page_flip_active(intel_crtc);
8769         __intel_ring_advance(ring);
8770         return 0;
8771
8772 err_unpin:
8773         intel_unpin_fb_obj(obj);
8774 err:
8775         return ret;
8776 }
8777
8778 static int intel_gen7_queue_flip(struct drm_device *dev,
8779                                  struct drm_crtc *crtc,
8780                                  struct drm_framebuffer *fb,
8781                                  struct drm_i915_gem_object *obj,
8782                                  uint32_t flags)
8783 {
8784         struct drm_i915_private *dev_priv = dev->dev_private;
8785         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8786         struct intel_ring_buffer *ring;
8787         uint32_t plane_bit = 0;
8788         int len, ret;
8789
8790         ring = obj->ring;
8791         if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
8792                 ring = &dev_priv->ring[BCS];
8793
8794         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8795         if (ret)
8796                 goto err;
8797
8798         switch(intel_crtc->plane) {
8799         case PLANE_A:
8800                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8801                 break;
8802         case PLANE_B:
8803                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8804                 break;
8805         case PLANE_C:
8806                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8807                 break;
8808         default:
8809                 WARN_ONCE(1, "unknown plane in flip command\n");
8810                 ret = -ENODEV;
8811                 goto err_unpin;
8812         }
8813
8814         len = 4;
8815         if (ring->id == RCS) {
8816                 len += 6;
8817                 /*
8818                  * On Gen 8, SRM is now taking an extra dword to accommodate
8819                  * 48bits addresses, and we need a NOOP for the batch size to
8820                  * stay even.
8821                  */
8822                 if (IS_GEN8(dev))
8823                         len += 2;
8824         }
8825
8826         /*
8827          * BSpec MI_DISPLAY_FLIP for IVB:
8828          * "The full packet must be contained within the same cache line."
8829          *
8830          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
8831          * cacheline, if we ever start emitting more commands before
8832          * the MI_DISPLAY_FLIP we may need to first emit everything else,
8833          * then do the cacheline alignment, and finally emit the
8834          * MI_DISPLAY_FLIP.
8835          */
8836         ret = intel_ring_cacheline_align(ring);
8837         if (ret)
8838                 goto err_unpin;
8839
8840         ret = intel_ring_begin(ring, len);
8841         if (ret)
8842                 goto err_unpin;
8843
8844         /* Unmask the flip-done completion message. Note that the bspec says that
8845          * we should do this for both the BCS and RCS, and that we must not unmask
8846          * more than one flip event at any time (or ensure that one flip message
8847          * can be sent by waiting for flip-done prior to queueing new flips).
8848          * Experimentation says that BCS works despite DERRMR masking all
8849          * flip-done completion events and that unmasking all planes at once
8850          * for the RCS also doesn't appear to drop events. Setting the DERRMR
8851          * to zero does lead to lockups within MI_DISPLAY_FLIP.
8852          */
8853         if (ring->id == RCS) {
8854                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8855                 intel_ring_emit(ring, DERRMR);
8856                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8857                                         DERRMR_PIPEB_PRI_FLIP_DONE |
8858                                         DERRMR_PIPEC_PRI_FLIP_DONE));
8859                 if (IS_GEN8(dev))
8860                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
8861                                               MI_SRM_LRM_GLOBAL_GTT);
8862                 else
8863                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
8864                                               MI_SRM_LRM_GLOBAL_GTT);
8865                 intel_ring_emit(ring, DERRMR);
8866                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8867                 if (IS_GEN8(dev)) {
8868                         intel_ring_emit(ring, 0);
8869                         intel_ring_emit(ring, MI_NOOP);
8870                 }
8871         }
8872
8873         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
8874         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
8875         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8876         intel_ring_emit(ring, (MI_NOOP));
8877
8878         intel_mark_page_flip_active(intel_crtc);
8879         __intel_ring_advance(ring);
8880         return 0;
8881
8882 err_unpin:
8883         intel_unpin_fb_obj(obj);
8884 err:
8885         return ret;
8886 }
8887
8888 static int intel_default_queue_flip(struct drm_device *dev,
8889                                     struct drm_crtc *crtc,
8890                                     struct drm_framebuffer *fb,
8891                                     struct drm_i915_gem_object *obj,
8892                                     uint32_t flags)
8893 {
8894         return -ENODEV;
8895 }
8896
8897 static int intel_crtc_page_flip(struct drm_crtc *crtc,
8898                                 struct drm_framebuffer *fb,
8899                                 struct drm_pending_vblank_event *event,
8900                                 uint32_t page_flip_flags)
8901 {
8902         struct drm_device *dev = crtc->dev;
8903         struct drm_i915_private *dev_priv = dev->dev_private;
8904         struct drm_framebuffer *old_fb = crtc->primary->fb;
8905         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
8906         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8907         struct intel_unpin_work *work;
8908         unsigned long flags;
8909         int ret;
8910
8911         /* Can't change pixel format via MI display flips. */
8912         if (fb->pixel_format != crtc->primary->fb->pixel_format)
8913                 return -EINVAL;
8914
8915         /*
8916          * TILEOFF/LINOFF registers can't be changed via MI display flips.
8917          * Note that pitch changes could also affect these register.
8918          */
8919         if (INTEL_INFO(dev)->gen > 3 &&
8920             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
8921              fb->pitches[0] != crtc->primary->fb->pitches[0]))
8922                 return -EINVAL;
8923
8924         if (i915_terminally_wedged(&dev_priv->gpu_error))
8925                 goto out_hang;
8926
8927         work = kzalloc(sizeof(*work), GFP_KERNEL);
8928         if (work == NULL)
8929                 return -ENOMEM;
8930
8931         work->event = event;
8932         work->crtc = crtc;
8933         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
8934         INIT_WORK(&work->work, intel_unpin_work_fn);
8935
8936         ret = drm_vblank_get(dev, intel_crtc->pipe);
8937         if (ret)
8938                 goto free_work;
8939
8940         /* We borrow the event spin lock for protecting unpin_work */
8941         spin_lock_irqsave(&dev->event_lock, flags);
8942         if (intel_crtc->unpin_work) {
8943                 spin_unlock_irqrestore(&dev->event_lock, flags);
8944                 kfree(work);
8945                 drm_vblank_put(dev, intel_crtc->pipe);
8946
8947                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8948                 return -EBUSY;
8949         }
8950         intel_crtc->unpin_work = work;
8951         spin_unlock_irqrestore(&dev->event_lock, flags);
8952
8953         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8954                 flush_workqueue(dev_priv->wq);
8955
8956         ret = i915_mutex_lock_interruptible(dev);
8957         if (ret)
8958                 goto cleanup;
8959
8960         /* Reference the objects for the scheduled work. */
8961         drm_gem_object_reference(&work->old_fb_obj->base);
8962         drm_gem_object_reference(&obj->base);
8963
8964         crtc->primary->fb = fb;
8965
8966         work->pending_flip_obj = obj;
8967
8968         work->enable_stall_check = true;
8969
8970         atomic_inc(&intel_crtc->unpin_work_count);
8971         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
8972
8973         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8974         if (ret)
8975                 goto cleanup_pending;
8976
8977         intel_disable_fbc(dev);
8978         intel_mark_fb_busy(obj, NULL);
8979         mutex_unlock(&dev->struct_mutex);
8980
8981         trace_i915_flip_request(intel_crtc->plane, obj);
8982
8983         return 0;
8984
8985 cleanup_pending:
8986         atomic_dec(&intel_crtc->unpin_work_count);
8987         crtc->primary->fb = old_fb;
8988         drm_gem_object_unreference(&work->old_fb_obj->base);
8989         drm_gem_object_unreference(&obj->base);
8990         mutex_unlock(&dev->struct_mutex);
8991
8992 cleanup:
8993         spin_lock_irqsave(&dev->event_lock, flags);
8994         intel_crtc->unpin_work = NULL;
8995         spin_unlock_irqrestore(&dev->event_lock, flags);
8996
8997         drm_vblank_put(dev, intel_crtc->pipe);
8998 free_work:
8999         kfree(work);
9000
9001         if (ret == -EIO) {
9002 out_hang:
9003                 intel_crtc_wait_for_pending_flips(crtc);
9004                 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9005                 if (ret == 0 && event)
9006                         drm_send_vblank_event(dev, intel_crtc->pipe, event);
9007         }
9008         return ret;
9009 }
9010
9011 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9012         .mode_set_base_atomic = intel_pipe_set_base_atomic,
9013         .load_lut = intel_crtc_load_lut,
9014 };
9015
9016 /**
9017  * intel_modeset_update_staged_output_state
9018  *
9019  * Updates the staged output configuration state, e.g. after we've read out the
9020  * current hw state.
9021  */
9022 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9023 {
9024         struct intel_crtc *crtc;
9025         struct intel_encoder *encoder;
9026         struct intel_connector *connector;
9027
9028         list_for_each_entry(connector, &dev->mode_config.connector_list,
9029                             base.head) {
9030                 connector->new_encoder =
9031                         to_intel_encoder(connector->base.encoder);
9032         }
9033
9034         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9035                             base.head) {
9036                 encoder->new_crtc =
9037                         to_intel_crtc(encoder->base.crtc);
9038         }
9039
9040         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9041                             base.head) {
9042                 crtc->new_enabled = crtc->base.enabled;
9043
9044                 if (crtc->new_enabled)
9045                         crtc->new_config = &crtc->config;
9046                 else
9047                         crtc->new_config = NULL;
9048         }
9049 }
9050
9051 /**
9052  * intel_modeset_commit_output_state
9053  *
9054  * This function copies the stage display pipe configuration to the real one.
9055  */
9056 static void intel_modeset_commit_output_state(struct drm_device *dev)
9057 {
9058         struct intel_crtc *crtc;
9059         struct intel_encoder *encoder;
9060         struct intel_connector *connector;
9061
9062         list_for_each_entry(connector, &dev->mode_config.connector_list,
9063                             base.head) {
9064                 connector->base.encoder = &connector->new_encoder->base;
9065         }
9066
9067         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9068                             base.head) {
9069                 encoder->base.crtc = &encoder->new_crtc->base;
9070         }
9071
9072         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9073                             base.head) {
9074                 crtc->base.enabled = crtc->new_enabled;
9075         }
9076 }
9077
9078 static void
9079 connected_sink_compute_bpp(struct intel_connector * connector,
9080                            struct intel_crtc_config *pipe_config)
9081 {
9082         int bpp = pipe_config->pipe_bpp;
9083
9084         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9085                 connector->base.base.id,
9086                 drm_get_connector_name(&connector->base));
9087
9088         /* Don't use an invalid EDID bpc value */
9089         if (connector->base.display_info.bpc &&
9090             connector->base.display_info.bpc * 3 < bpp) {
9091                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9092                               bpp, connector->base.display_info.bpc*3);
9093                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9094         }
9095
9096         /* Clamp bpp to 8 on screens without EDID 1.4 */
9097         if (connector->base.display_info.bpc == 0 && bpp > 24) {
9098                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9099                               bpp);
9100                 pipe_config->pipe_bpp = 24;
9101         }
9102 }
9103
9104 static int
9105 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9106                           struct drm_framebuffer *fb,
9107                           struct intel_crtc_config *pipe_config)
9108 {
9109         struct drm_device *dev = crtc->base.dev;
9110         struct intel_connector *connector;
9111         int bpp;
9112
9113         switch (fb->pixel_format) {
9114         case DRM_FORMAT_C8:
9115                 bpp = 8*3; /* since we go through a colormap */
9116                 break;
9117         case DRM_FORMAT_XRGB1555:
9118         case DRM_FORMAT_ARGB1555:
9119                 /* checked in intel_framebuffer_init already */
9120                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9121                         return -EINVAL;
9122         case DRM_FORMAT_RGB565:
9123                 bpp = 6*3; /* min is 18bpp */
9124                 break;
9125         case DRM_FORMAT_XBGR8888:
9126         case DRM_FORMAT_ABGR8888:
9127                 /* checked in intel_framebuffer_init already */
9128                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9129                         return -EINVAL;
9130         case DRM_FORMAT_XRGB8888:
9131         case DRM_FORMAT_ARGB8888:
9132                 bpp = 8*3;
9133                 break;
9134         case DRM_FORMAT_XRGB2101010:
9135         case DRM_FORMAT_ARGB2101010:
9136         case DRM_FORMAT_XBGR2101010:
9137         case DRM_FORMAT_ABGR2101010:
9138                 /* checked in intel_framebuffer_init already */
9139                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9140                         return -EINVAL;
9141                 bpp = 10*3;
9142                 break;
9143         /* TODO: gen4+ supports 16 bpc floating point, too. */
9144         default:
9145                 DRM_DEBUG_KMS("unsupported depth\n");
9146                 return -EINVAL;
9147         }
9148
9149         pipe_config->pipe_bpp = bpp;
9150
9151         /* Clamp display bpp to EDID value */
9152         list_for_each_entry(connector, &dev->mode_config.connector_list,
9153                             base.head) {
9154                 if (!connector->new_encoder ||
9155                     connector->new_encoder->new_crtc != crtc)
9156                         continue;
9157
9158                 connected_sink_compute_bpp(connector, pipe_config);
9159         }
9160
9161         return bpp;
9162 }
9163
9164 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9165 {
9166         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9167                         "type: 0x%x flags: 0x%x\n",
9168                 mode->crtc_clock,
9169                 mode->crtc_hdisplay, mode->crtc_hsync_start,
9170                 mode->crtc_hsync_end, mode->crtc_htotal,
9171                 mode->crtc_vdisplay, mode->crtc_vsync_start,
9172                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9173 }
9174
9175 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9176                                    struct intel_crtc_config *pipe_config,
9177                                    const char *context)
9178 {
9179         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9180                       context, pipe_name(crtc->pipe));
9181
9182         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9183         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9184                       pipe_config->pipe_bpp, pipe_config->dither);
9185         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9186                       pipe_config->has_pch_encoder,
9187                       pipe_config->fdi_lanes,
9188                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9189                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9190                       pipe_config->fdi_m_n.tu);
9191         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9192                       pipe_config->has_dp_encoder,
9193                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9194                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9195                       pipe_config->dp_m_n.tu);
9196         DRM_DEBUG_KMS("requested mode:\n");
9197         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9198         DRM_DEBUG_KMS("adjusted mode:\n");
9199         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9200         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9201         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9202         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9203                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9204         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9205                       pipe_config->gmch_pfit.control,
9206                       pipe_config->gmch_pfit.pgm_ratios,
9207                       pipe_config->gmch_pfit.lvds_border_bits);
9208         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9209                       pipe_config->pch_pfit.pos,
9210                       pipe_config->pch_pfit.size,
9211                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9212         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9213         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
9214 }
9215
9216 static bool encoders_cloneable(const struct intel_encoder *a,
9217                                const struct intel_encoder *b)
9218 {
9219         /* masks could be asymmetric, so check both ways */
9220         return a == b || (a->cloneable & (1 << b->type) &&
9221                           b->cloneable & (1 << a->type));
9222 }
9223
9224 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9225                                          struct intel_encoder *encoder)
9226 {
9227         struct drm_device *dev = crtc->base.dev;
9228         struct intel_encoder *source_encoder;
9229
9230         list_for_each_entry(source_encoder,
9231                             &dev->mode_config.encoder_list, base.head) {
9232                 if (source_encoder->new_crtc != crtc)
9233                         continue;
9234
9235                 if (!encoders_cloneable(encoder, source_encoder))
9236                         return false;
9237         }
9238
9239         return true;
9240 }
9241
9242 static bool check_encoder_cloning(struct intel_crtc *crtc)
9243 {
9244         struct drm_device *dev = crtc->base.dev;
9245         struct intel_encoder *encoder;
9246
9247         list_for_each_entry(encoder,
9248                             &dev->mode_config.encoder_list, base.head) {
9249                 if (encoder->new_crtc != crtc)
9250                         continue;
9251
9252                 if (!check_single_encoder_cloning(crtc, encoder))
9253                         return false;
9254         }
9255
9256         return true;
9257 }
9258
9259 static struct intel_crtc_config *
9260 intel_modeset_pipe_config(struct drm_crtc *crtc,
9261                           struct drm_framebuffer *fb,
9262                           struct drm_display_mode *mode)
9263 {
9264         struct drm_device *dev = crtc->dev;
9265         struct intel_encoder *encoder;
9266         struct intel_crtc_config *pipe_config;
9267         int plane_bpp, ret = -EINVAL;
9268         bool retry = true;
9269
9270         if (!check_encoder_cloning(to_intel_crtc(crtc))) {
9271                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
9272                 return ERR_PTR(-EINVAL);
9273         }
9274
9275         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9276         if (!pipe_config)
9277                 return ERR_PTR(-ENOMEM);
9278
9279         drm_mode_copy(&pipe_config->adjusted_mode, mode);
9280         drm_mode_copy(&pipe_config->requested_mode, mode);
9281
9282         pipe_config->cpu_transcoder =
9283                 (enum transcoder) to_intel_crtc(crtc)->pipe;
9284         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9285
9286         /*
9287          * Sanitize sync polarity flags based on requested ones. If neither
9288          * positive or negative polarity is requested, treat this as meaning
9289          * negative polarity.
9290          */
9291         if (!(pipe_config->adjusted_mode.flags &
9292               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
9293                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
9294
9295         if (!(pipe_config->adjusted_mode.flags &
9296               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
9297                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
9298
9299         /* Compute a starting value for pipe_config->pipe_bpp taking the source
9300          * plane pixel format and any sink constraints into account. Returns the
9301          * source plane bpp so that dithering can be selected on mismatches
9302          * after encoders and crtc also have had their say. */
9303         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
9304                                               fb, pipe_config);
9305         if (plane_bpp < 0)
9306                 goto fail;
9307
9308         /*
9309          * Determine the real pipe dimensions. Note that stereo modes can
9310          * increase the actual pipe size due to the frame doubling and
9311          * insertion of additional space for blanks between the frame. This
9312          * is stored in the crtc timings. We use the requested mode to do this
9313          * computation to clearly distinguish it from the adjusted mode, which
9314          * can be changed by the connectors in the below retry loop.
9315          */
9316         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
9317         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
9318         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
9319
9320 encoder_retry:
9321         /* Ensure the port clock defaults are reset when retrying. */
9322         pipe_config->port_clock = 0;
9323         pipe_config->pixel_multiplier = 1;
9324
9325         /* Fill in default crtc timings, allow encoders to overwrite them. */
9326         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
9327
9328         /* Pass our mode to the connectors and the CRTC to give them a chance to
9329          * adjust it according to limitations or connector properties, and also
9330          * a chance to reject the mode entirely.
9331          */
9332         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9333                             base.head) {
9334
9335                 if (&encoder->new_crtc->base != crtc)
9336                         continue;
9337
9338                 if (!(encoder->compute_config(encoder, pipe_config))) {
9339                         DRM_DEBUG_KMS("Encoder config failure\n");
9340                         goto fail;
9341                 }
9342         }
9343
9344         /* Set default port clock if not overwritten by the encoder. Needs to be
9345          * done afterwards in case the encoder adjusts the mode. */
9346         if (!pipe_config->port_clock)
9347                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
9348                         * pipe_config->pixel_multiplier;
9349
9350         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
9351         if (ret < 0) {
9352                 DRM_DEBUG_KMS("CRTC fixup failed\n");
9353                 goto fail;
9354         }
9355
9356         if (ret == RETRY) {
9357                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
9358                         ret = -EINVAL;
9359                         goto fail;
9360                 }
9361
9362                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9363                 retry = false;
9364                 goto encoder_retry;
9365         }
9366
9367         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
9368         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9369                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
9370
9371         return pipe_config;
9372 fail:
9373         kfree(pipe_config);
9374         return ERR_PTR(ret);
9375 }
9376
9377 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
9378  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9379 static void
9380 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
9381                              unsigned *prepare_pipes, unsigned *disable_pipes)
9382 {
9383         struct intel_crtc *intel_crtc;
9384         struct drm_device *dev = crtc->dev;
9385         struct intel_encoder *encoder;
9386         struct intel_connector *connector;
9387         struct drm_crtc *tmp_crtc;
9388
9389         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
9390
9391         /* Check which crtcs have changed outputs connected to them, these need
9392          * to be part of the prepare_pipes mask. We don't (yet) support global
9393          * modeset across multiple crtcs, so modeset_pipes will only have one
9394          * bit set at most. */
9395         list_for_each_entry(connector, &dev->mode_config.connector_list,
9396                             base.head) {
9397                 if (connector->base.encoder == &connector->new_encoder->base)
9398                         continue;
9399
9400                 if (connector->base.encoder) {
9401                         tmp_crtc = connector->base.encoder->crtc;
9402
9403                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9404                 }
9405
9406                 if (connector->new_encoder)
9407                         *prepare_pipes |=
9408                                 1 << connector->new_encoder->new_crtc->pipe;
9409         }
9410
9411         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9412                             base.head) {
9413                 if (encoder->base.crtc == &encoder->new_crtc->base)
9414                         continue;
9415
9416                 if (encoder->base.crtc) {
9417                         tmp_crtc = encoder->base.crtc;
9418
9419                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9420                 }
9421
9422                 if (encoder->new_crtc)
9423                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
9424         }
9425
9426         /* Check for pipes that will be enabled/disabled ... */
9427         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9428                             base.head) {
9429                 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
9430                         continue;
9431
9432                 if (!intel_crtc->new_enabled)
9433                         *disable_pipes |= 1 << intel_crtc->pipe;
9434                 else
9435                         *prepare_pipes |= 1 << intel_crtc->pipe;
9436         }
9437
9438
9439         /* set_mode is also used to update properties on life display pipes. */
9440         intel_crtc = to_intel_crtc(crtc);
9441         if (intel_crtc->new_enabled)
9442                 *prepare_pipes |= 1 << intel_crtc->pipe;
9443
9444         /*
9445          * For simplicity do a full modeset on any pipe where the output routing
9446          * changed. We could be more clever, but that would require us to be
9447          * more careful with calling the relevant encoder->mode_set functions.
9448          */
9449         if (*prepare_pipes)
9450                 *modeset_pipes = *prepare_pipes;
9451
9452         /* ... and mask these out. */
9453         *modeset_pipes &= ~(*disable_pipes);
9454         *prepare_pipes &= ~(*disable_pipes);
9455
9456         /*
9457          * HACK: We don't (yet) fully support global modesets. intel_set_config
9458          * obies this rule, but the modeset restore mode of
9459          * intel_modeset_setup_hw_state does not.
9460          */
9461         *modeset_pipes &= 1 << intel_crtc->pipe;
9462         *prepare_pipes &= 1 << intel_crtc->pipe;
9463
9464         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9465                       *modeset_pipes, *prepare_pipes, *disable_pipes);
9466 }
9467
9468 static bool intel_crtc_in_use(struct drm_crtc *crtc)
9469 {
9470         struct drm_encoder *encoder;
9471         struct drm_device *dev = crtc->dev;
9472
9473         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
9474                 if (encoder->crtc == crtc)
9475                         return true;
9476
9477         return false;
9478 }
9479
9480 static void
9481 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
9482 {
9483         struct intel_encoder *intel_encoder;
9484         struct intel_crtc *intel_crtc;
9485         struct drm_connector *connector;
9486
9487         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
9488                             base.head) {
9489                 if (!intel_encoder->base.crtc)
9490                         continue;
9491
9492                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
9493
9494                 if (prepare_pipes & (1 << intel_crtc->pipe))
9495                         intel_encoder->connectors_active = false;
9496         }
9497
9498         intel_modeset_commit_output_state(dev);
9499
9500         /* Double check state. */
9501         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9502                             base.head) {
9503                 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
9504                 WARN_ON(intel_crtc->new_config &&
9505                         intel_crtc->new_config != &intel_crtc->config);
9506                 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
9507         }
9508
9509         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9510                 if (!connector->encoder || !connector->encoder->crtc)
9511                         continue;
9512
9513                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
9514
9515                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
9516                         struct drm_property *dpms_property =
9517                                 dev->mode_config.dpms_property;
9518
9519                         connector->dpms = DRM_MODE_DPMS_ON;
9520                         drm_object_property_set_value(&connector->base,
9521                                                          dpms_property,
9522                                                          DRM_MODE_DPMS_ON);
9523
9524                         intel_encoder = to_intel_encoder(connector->encoder);
9525                         intel_encoder->connectors_active = true;
9526                 }
9527         }
9528
9529 }
9530
9531 static bool intel_fuzzy_clock_check(int clock1, int clock2)
9532 {
9533         int diff;
9534
9535         if (clock1 == clock2)
9536                 return true;
9537
9538         if (!clock1 || !clock2)
9539                 return false;
9540
9541         diff = abs(clock1 - clock2);
9542
9543         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
9544                 return true;
9545
9546         return false;
9547 }
9548
9549 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9550         list_for_each_entry((intel_crtc), \
9551                             &(dev)->mode_config.crtc_list, \
9552                             base.head) \
9553                 if (mask & (1 <<(intel_crtc)->pipe))
9554
9555 static bool
9556 intel_pipe_config_compare(struct drm_device *dev,
9557                           struct intel_crtc_config *current_config,
9558                           struct intel_crtc_config *pipe_config)
9559 {
9560 #define PIPE_CONF_CHECK_X(name) \
9561         if (current_config->name != pipe_config->name) { \
9562                 DRM_ERROR("mismatch in " #name " " \
9563                           "(expected 0x%08x, found 0x%08x)\n", \
9564                           current_config->name, \
9565                           pipe_config->name); \
9566                 return false; \
9567         }
9568
9569 #define PIPE_CONF_CHECK_I(name) \
9570         if (current_config->name != pipe_config->name) { \
9571                 DRM_ERROR("mismatch in " #name " " \
9572                           "(expected %i, found %i)\n", \
9573                           current_config->name, \
9574                           pipe_config->name); \
9575                 return false; \
9576         }
9577
9578 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
9579         if ((current_config->name ^ pipe_config->name) & (mask)) { \
9580                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
9581                           "(expected %i, found %i)\n", \
9582                           current_config->name & (mask), \
9583                           pipe_config->name & (mask)); \
9584                 return false; \
9585         }
9586
9587 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9588         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9589                 DRM_ERROR("mismatch in " #name " " \
9590                           "(expected %i, found %i)\n", \
9591                           current_config->name, \
9592                           pipe_config->name); \
9593                 return false; \
9594         }
9595
9596 #define PIPE_CONF_QUIRK(quirk)  \
9597         ((current_config->quirks | pipe_config->quirks) & (quirk))
9598
9599         PIPE_CONF_CHECK_I(cpu_transcoder);
9600
9601         PIPE_CONF_CHECK_I(has_pch_encoder);
9602         PIPE_CONF_CHECK_I(fdi_lanes);
9603         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9604         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9605         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9606         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9607         PIPE_CONF_CHECK_I(fdi_m_n.tu);
9608
9609         PIPE_CONF_CHECK_I(has_dp_encoder);
9610         PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9611         PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9612         PIPE_CONF_CHECK_I(dp_m_n.link_m);
9613         PIPE_CONF_CHECK_I(dp_m_n.link_n);
9614         PIPE_CONF_CHECK_I(dp_m_n.tu);
9615
9616         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9617         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9618         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9619         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9620         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9621         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9622
9623         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9624         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9625         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9626         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9627         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9628         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9629
9630         PIPE_CONF_CHECK_I(pixel_multiplier);
9631
9632         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9633                               DRM_MODE_FLAG_INTERLACE);
9634
9635         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9636                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9637                                       DRM_MODE_FLAG_PHSYNC);
9638                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9639                                       DRM_MODE_FLAG_NHSYNC);
9640                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9641                                       DRM_MODE_FLAG_PVSYNC);
9642                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9643                                       DRM_MODE_FLAG_NVSYNC);
9644         }
9645
9646         PIPE_CONF_CHECK_I(pipe_src_w);
9647         PIPE_CONF_CHECK_I(pipe_src_h);
9648
9649         PIPE_CONF_CHECK_I(gmch_pfit.control);
9650         /* pfit ratios are autocomputed by the hw on gen4+ */
9651         if (INTEL_INFO(dev)->gen < 4)
9652                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9653         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9654         PIPE_CONF_CHECK_I(pch_pfit.enabled);
9655         if (current_config->pch_pfit.enabled) {
9656                 PIPE_CONF_CHECK_I(pch_pfit.pos);
9657                 PIPE_CONF_CHECK_I(pch_pfit.size);
9658         }
9659
9660         /* BDW+ don't expose a synchronous way to read the state */
9661         if (IS_HASWELL(dev))
9662                 PIPE_CONF_CHECK_I(ips_enabled);
9663
9664         PIPE_CONF_CHECK_I(double_wide);
9665
9666         PIPE_CONF_CHECK_I(shared_dpll);
9667         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
9668         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
9669         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
9670         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
9671
9672         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
9673                 PIPE_CONF_CHECK_I(pipe_bpp);
9674
9675         PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
9676         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
9677
9678 #undef PIPE_CONF_CHECK_X
9679 #undef PIPE_CONF_CHECK_I
9680 #undef PIPE_CONF_CHECK_FLAGS
9681 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
9682 #undef PIPE_CONF_QUIRK
9683
9684         return true;
9685 }
9686
9687 static void
9688 check_connector_state(struct drm_device *dev)
9689 {
9690         struct intel_connector *connector;
9691
9692         list_for_each_entry(connector, &dev->mode_config.connector_list,
9693                             base.head) {
9694                 /* This also checks the encoder/connector hw state with the
9695                  * ->get_hw_state callbacks. */
9696                 intel_connector_check_state(connector);
9697
9698                 WARN(&connector->new_encoder->base != connector->base.encoder,
9699                      "connector's staged encoder doesn't match current encoder\n");
9700         }
9701 }
9702
9703 static void
9704 check_encoder_state(struct drm_device *dev)
9705 {
9706         struct intel_encoder *encoder;
9707         struct intel_connector *connector;
9708
9709         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9710                             base.head) {
9711                 bool enabled = false;
9712                 bool active = false;
9713                 enum pipe pipe, tracked_pipe;
9714
9715                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
9716                               encoder->base.base.id,
9717                               drm_get_encoder_name(&encoder->base));
9718
9719                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
9720                      "encoder's stage crtc doesn't match current crtc\n");
9721                 WARN(encoder->connectors_active && !encoder->base.crtc,
9722                      "encoder's active_connectors set, but no crtc\n");
9723
9724                 list_for_each_entry(connector, &dev->mode_config.connector_list,
9725                                     base.head) {
9726                         if (connector->base.encoder != &encoder->base)
9727                                 continue;
9728                         enabled = true;
9729                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
9730                                 active = true;
9731                 }
9732                 WARN(!!encoder->base.crtc != enabled,
9733                      "encoder's enabled state mismatch "
9734                      "(expected %i, found %i)\n",
9735                      !!encoder->base.crtc, enabled);
9736                 WARN(active && !encoder->base.crtc,
9737                      "active encoder with no crtc\n");
9738
9739                 WARN(encoder->connectors_active != active,
9740                      "encoder's computed active state doesn't match tracked active state "
9741                      "(expected %i, found %i)\n", active, encoder->connectors_active);
9742
9743                 active = encoder->get_hw_state(encoder, &pipe);
9744                 WARN(active != encoder->connectors_active,
9745                      "encoder's hw state doesn't match sw tracking "
9746                      "(expected %i, found %i)\n",
9747                      encoder->connectors_active, active);
9748
9749                 if (!encoder->base.crtc)
9750                         continue;
9751
9752                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9753                 WARN(active && pipe != tracked_pipe,
9754                      "active encoder's pipe doesn't match"
9755                      "(expected %i, found %i)\n",
9756                      tracked_pipe, pipe);
9757
9758         }
9759 }
9760
9761 static void
9762 check_crtc_state(struct drm_device *dev)
9763 {
9764         struct drm_i915_private *dev_priv = dev->dev_private;
9765         struct intel_crtc *crtc;
9766         struct intel_encoder *encoder;
9767         struct intel_crtc_config pipe_config;
9768
9769         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9770                             base.head) {
9771                 bool enabled = false;
9772                 bool active = false;
9773
9774                 memset(&pipe_config, 0, sizeof(pipe_config));
9775
9776                 DRM_DEBUG_KMS("[CRTC:%d]\n",
9777                               crtc->base.base.id);
9778
9779                 WARN(crtc->active && !crtc->base.enabled,
9780                      "active crtc, but not enabled in sw tracking\n");
9781
9782                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9783                                     base.head) {
9784                         if (encoder->base.crtc != &crtc->base)
9785                                 continue;
9786                         enabled = true;
9787                         if (encoder->connectors_active)
9788                                 active = true;
9789                 }
9790
9791                 WARN(active != crtc->active,
9792                      "crtc's computed active state doesn't match tracked active state "
9793                      "(expected %i, found %i)\n", active, crtc->active);
9794                 WARN(enabled != crtc->base.enabled,
9795                      "crtc's computed enabled state doesn't match tracked enabled state "
9796                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9797
9798                 active = dev_priv->display.get_pipe_config(crtc,
9799                                                            &pipe_config);
9800
9801                 /* hw state is inconsistent with the pipe A quirk */
9802                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9803                         active = crtc->active;
9804
9805                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9806                                     base.head) {
9807                         enum pipe pipe;
9808                         if (encoder->base.crtc != &crtc->base)
9809                                 continue;
9810                         if (encoder->get_hw_state(encoder, &pipe))
9811                                 encoder->get_config(encoder, &pipe_config);
9812                 }
9813
9814                 WARN(crtc->active != active,
9815                      "crtc active state doesn't match with hw state "
9816                      "(expected %i, found %i)\n", crtc->active, active);
9817
9818                 if (active &&
9819                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9820                         WARN(1, "pipe state doesn't match!\n");
9821                         intel_dump_pipe_config(crtc, &pipe_config,
9822                                                "[hw state]");
9823                         intel_dump_pipe_config(crtc, &crtc->config,
9824                                                "[sw state]");
9825                 }
9826         }
9827 }
9828
9829 static void
9830 check_shared_dpll_state(struct drm_device *dev)
9831 {
9832         struct drm_i915_private *dev_priv = dev->dev_private;
9833         struct intel_crtc *crtc;
9834         struct intel_dpll_hw_state dpll_hw_state;
9835         int i;
9836
9837         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9838                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9839                 int enabled_crtcs = 0, active_crtcs = 0;
9840                 bool active;
9841
9842                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9843
9844                 DRM_DEBUG_KMS("%s\n", pll->name);
9845
9846                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9847
9848                 WARN(pll->active > pll->refcount,
9849                      "more active pll users than references: %i vs %i\n",
9850                      pll->active, pll->refcount);
9851                 WARN(pll->active && !pll->on,
9852                      "pll in active use but not on in sw tracking\n");
9853                 WARN(pll->on && !pll->active,
9854                      "pll in on but not on in use in sw tracking\n");
9855                 WARN(pll->on != active,
9856                      "pll on state mismatch (expected %i, found %i)\n",
9857                      pll->on, active);
9858
9859                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9860                                     base.head) {
9861                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9862                                 enabled_crtcs++;
9863                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9864                                 active_crtcs++;
9865                 }
9866                 WARN(pll->active != active_crtcs,
9867                      "pll active crtcs mismatch (expected %i, found %i)\n",
9868                      pll->active, active_crtcs);
9869                 WARN(pll->refcount != enabled_crtcs,
9870                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
9871                      pll->refcount, enabled_crtcs);
9872
9873                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9874                                        sizeof(dpll_hw_state)),
9875                      "pll hw state mismatch\n");
9876         }
9877 }
9878
9879 void
9880 intel_modeset_check_state(struct drm_device *dev)
9881 {
9882         check_connector_state(dev);
9883         check_encoder_state(dev);
9884         check_crtc_state(dev);
9885         check_shared_dpll_state(dev);
9886 }
9887
9888 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9889                                      int dotclock)
9890 {
9891         /*
9892          * FDI already provided one idea for the dotclock.
9893          * Yell if the encoder disagrees.
9894          */
9895         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
9896              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9897              pipe_config->adjusted_mode.crtc_clock, dotclock);
9898 }
9899
9900 static int __intel_set_mode(struct drm_crtc *crtc,
9901                             struct drm_display_mode *mode,
9902                             int x, int y, struct drm_framebuffer *fb)
9903 {
9904         struct drm_device *dev = crtc->dev;
9905         struct drm_i915_private *dev_priv = dev->dev_private;
9906         struct drm_display_mode *saved_mode;
9907         struct intel_crtc_config *pipe_config = NULL;
9908         struct intel_crtc *intel_crtc;
9909         unsigned disable_pipes, prepare_pipes, modeset_pipes;
9910         int ret = 0;
9911
9912         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
9913         if (!saved_mode)
9914                 return -ENOMEM;
9915
9916         intel_modeset_affected_pipes(crtc, &modeset_pipes,
9917                                      &prepare_pipes, &disable_pipes);
9918
9919         *saved_mode = crtc->mode;
9920
9921         /* Hack: Because we don't (yet) support global modeset on multiple
9922          * crtcs, we don't keep track of the new mode for more than one crtc.
9923          * Hence simply check whether any bit is set in modeset_pipes in all the
9924          * pieces of code that are not yet converted to deal with mutliple crtcs
9925          * changing their mode at the same time. */
9926         if (modeset_pipes) {
9927                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
9928                 if (IS_ERR(pipe_config)) {
9929                         ret = PTR_ERR(pipe_config);
9930                         pipe_config = NULL;
9931
9932                         goto out;
9933                 }
9934                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9935                                        "[modeset]");
9936                 to_intel_crtc(crtc)->new_config = pipe_config;
9937         }
9938
9939         /*
9940          * See if the config requires any additional preparation, e.g.
9941          * to adjust global state with pipes off.  We need to do this
9942          * here so we can get the modeset_pipe updated config for the new
9943          * mode set on this crtc.  For other crtcs we need to use the
9944          * adjusted_mode bits in the crtc directly.
9945          */
9946         if (IS_VALLEYVIEW(dev)) {
9947                 valleyview_modeset_global_pipes(dev, &prepare_pipes);
9948
9949                 /* may have added more to prepare_pipes than we should */
9950                 prepare_pipes &= ~disable_pipes;
9951         }
9952
9953         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9954                 intel_crtc_disable(&intel_crtc->base);
9955
9956         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9957                 if (intel_crtc->base.enabled)
9958                         dev_priv->display.crtc_disable(&intel_crtc->base);
9959         }
9960
9961         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9962          * to set it here already despite that we pass it down the callchain.
9963          */
9964         if (modeset_pipes) {
9965                 crtc->mode = *mode;
9966                 /* mode_set/enable/disable functions rely on a correct pipe
9967                  * config. */
9968                 to_intel_crtc(crtc)->config = *pipe_config;
9969                 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
9970
9971                 /*
9972                  * Calculate and store various constants which
9973                  * are later needed by vblank and swap-completion
9974                  * timestamping. They are derived from true hwmode.
9975                  */
9976                 drm_calc_timestamping_constants(crtc,
9977                                                 &pipe_config->adjusted_mode);
9978         }
9979
9980         /* Only after disabling all output pipelines that will be changed can we
9981          * update the the output configuration. */
9982         intel_modeset_update_state(dev, prepare_pipes);
9983
9984         if (dev_priv->display.modeset_global_resources)
9985                 dev_priv->display.modeset_global_resources(dev);
9986
9987         /* Set up the DPLL and any encoders state that needs to adjust or depend
9988          * on the DPLL.
9989          */
9990         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
9991                 ret = intel_crtc_mode_set(&intel_crtc->base,
9992                                           x, y, fb);
9993                 if (ret)
9994                         goto done;
9995         }
9996
9997         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9998         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9999                 dev_priv->display.crtc_enable(&intel_crtc->base);
10000
10001         /* FIXME: add subpixel order */
10002 done:
10003         if (ret && crtc->enabled)
10004                 crtc->mode = *saved_mode;
10005
10006 out:
10007         kfree(pipe_config);
10008         kfree(saved_mode);
10009         return ret;
10010 }
10011
10012 static int intel_set_mode(struct drm_crtc *crtc,
10013                           struct drm_display_mode *mode,
10014                           int x, int y, struct drm_framebuffer *fb)
10015 {
10016         int ret;
10017
10018         ret = __intel_set_mode(crtc, mode, x, y, fb);
10019
10020         if (ret == 0)
10021                 intel_modeset_check_state(crtc->dev);
10022
10023         return ret;
10024 }
10025
10026 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10027 {
10028         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10029 }
10030
10031 #undef for_each_intel_crtc_masked
10032
10033 static void intel_set_config_free(struct intel_set_config *config)
10034 {
10035         if (!config)
10036                 return;
10037
10038         kfree(config->save_connector_encoders);
10039         kfree(config->save_encoder_crtcs);
10040         kfree(config->save_crtc_enabled);
10041         kfree(config);
10042 }
10043
10044 static int intel_set_config_save_state(struct drm_device *dev,
10045                                        struct intel_set_config *config)
10046 {
10047         struct drm_crtc *crtc;
10048         struct drm_encoder *encoder;
10049         struct drm_connector *connector;
10050         int count;
10051
10052         config->save_crtc_enabled =
10053                 kcalloc(dev->mode_config.num_crtc,
10054                         sizeof(bool), GFP_KERNEL);
10055         if (!config->save_crtc_enabled)
10056                 return -ENOMEM;
10057
10058         config->save_encoder_crtcs =
10059                 kcalloc(dev->mode_config.num_encoder,
10060                         sizeof(struct drm_crtc *), GFP_KERNEL);
10061         if (!config->save_encoder_crtcs)
10062                 return -ENOMEM;
10063
10064         config->save_connector_encoders =
10065                 kcalloc(dev->mode_config.num_connector,
10066                         sizeof(struct drm_encoder *), GFP_KERNEL);
10067         if (!config->save_connector_encoders)
10068                 return -ENOMEM;
10069
10070         /* Copy data. Note that driver private data is not affected.
10071          * Should anything bad happen only the expected state is
10072          * restored, not the drivers personal bookkeeping.
10073          */
10074         count = 0;
10075         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10076                 config->save_crtc_enabled[count++] = crtc->enabled;
10077         }
10078
10079         count = 0;
10080         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10081                 config->save_encoder_crtcs[count++] = encoder->crtc;
10082         }
10083
10084         count = 0;
10085         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10086                 config->save_connector_encoders[count++] = connector->encoder;
10087         }
10088
10089         return 0;
10090 }
10091
10092 static void intel_set_config_restore_state(struct drm_device *dev,
10093                                            struct intel_set_config *config)
10094 {
10095         struct intel_crtc *crtc;
10096         struct intel_encoder *encoder;
10097         struct intel_connector *connector;
10098         int count;
10099
10100         count = 0;
10101         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
10102                 crtc->new_enabled = config->save_crtc_enabled[count++];
10103
10104                 if (crtc->new_enabled)
10105                         crtc->new_config = &crtc->config;
10106                 else
10107                         crtc->new_config = NULL;
10108         }
10109
10110         count = 0;
10111         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10112                 encoder->new_crtc =
10113                         to_intel_crtc(config->save_encoder_crtcs[count++]);
10114         }
10115
10116         count = 0;
10117         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10118                 connector->new_encoder =
10119                         to_intel_encoder(config->save_connector_encoders[count++]);
10120         }
10121 }
10122
10123 static bool
10124 is_crtc_connector_off(struct drm_mode_set *set)
10125 {
10126         int i;
10127
10128         if (set->num_connectors == 0)
10129                 return false;
10130
10131         if (WARN_ON(set->connectors == NULL))
10132                 return false;
10133
10134         for (i = 0; i < set->num_connectors; i++)
10135                 if (set->connectors[i]->encoder &&
10136                     set->connectors[i]->encoder->crtc == set->crtc &&
10137                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
10138                         return true;
10139
10140         return false;
10141 }
10142
10143 static void
10144 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
10145                                       struct intel_set_config *config)
10146 {
10147
10148         /* We should be able to check here if the fb has the same properties
10149          * and then just flip_or_move it */
10150         if (is_crtc_connector_off(set)) {
10151                 config->mode_changed = true;
10152         } else if (set->crtc->primary->fb != set->fb) {
10153                 /* If we have no fb then treat it as a full mode set */
10154                 if (set->crtc->primary->fb == NULL) {
10155                         struct intel_crtc *intel_crtc =
10156                                 to_intel_crtc(set->crtc);
10157
10158                         if (intel_crtc->active && i915.fastboot) {
10159                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
10160                                 config->fb_changed = true;
10161                         } else {
10162                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
10163                                 config->mode_changed = true;
10164                         }
10165                 } else if (set->fb == NULL) {
10166                         config->mode_changed = true;
10167                 } else if (set->fb->pixel_format !=
10168                            set->crtc->primary->fb->pixel_format) {
10169                         config->mode_changed = true;
10170                 } else {
10171                         config->fb_changed = true;
10172                 }
10173         }
10174
10175         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
10176                 config->fb_changed = true;
10177
10178         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
10179                 DRM_DEBUG_KMS("modes are different, full mode set\n");
10180                 drm_mode_debug_printmodeline(&set->crtc->mode);
10181                 drm_mode_debug_printmodeline(set->mode);
10182                 config->mode_changed = true;
10183         }
10184
10185         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
10186                         set->crtc->base.id, config->mode_changed, config->fb_changed);
10187 }
10188
10189 static int
10190 intel_modeset_stage_output_state(struct drm_device *dev,
10191                                  struct drm_mode_set *set,
10192                                  struct intel_set_config *config)
10193 {
10194         struct intel_connector *connector;
10195         struct intel_encoder *encoder;
10196         struct intel_crtc *crtc;
10197         int ro;
10198
10199         /* The upper layers ensure that we either disable a crtc or have a list
10200          * of connectors. For paranoia, double-check this. */
10201         WARN_ON(!set->fb && (set->num_connectors != 0));
10202         WARN_ON(set->fb && (set->num_connectors == 0));
10203
10204         list_for_each_entry(connector, &dev->mode_config.connector_list,
10205                             base.head) {
10206                 /* Otherwise traverse passed in connector list and get encoders
10207                  * for them. */
10208                 for (ro = 0; ro < set->num_connectors; ro++) {
10209                         if (set->connectors[ro] == &connector->base) {
10210                                 connector->new_encoder = connector->encoder;
10211                                 break;
10212                         }
10213                 }
10214
10215                 /* If we disable the crtc, disable all its connectors. Also, if
10216                  * the connector is on the changing crtc but not on the new
10217                  * connector list, disable it. */
10218                 if ((!set->fb || ro == set->num_connectors) &&
10219                     connector->base.encoder &&
10220                     connector->base.encoder->crtc == set->crtc) {
10221                         connector->new_encoder = NULL;
10222
10223                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
10224                                 connector->base.base.id,
10225                                 drm_get_connector_name(&connector->base));
10226                 }
10227
10228
10229                 if (&connector->new_encoder->base != connector->base.encoder) {
10230                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
10231                         config->mode_changed = true;
10232                 }
10233         }
10234         /* connector->new_encoder is now updated for all connectors. */
10235
10236         /* Update crtc of enabled connectors. */
10237         list_for_each_entry(connector, &dev->mode_config.connector_list,
10238                             base.head) {
10239                 struct drm_crtc *new_crtc;
10240
10241                 if (!connector->new_encoder)
10242                         continue;
10243
10244                 new_crtc = connector->new_encoder->base.crtc;
10245
10246                 for (ro = 0; ro < set->num_connectors; ro++) {
10247                         if (set->connectors[ro] == &connector->base)
10248                                 new_crtc = set->crtc;
10249                 }
10250
10251                 /* Make sure the new CRTC will work with the encoder */
10252                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
10253                                          new_crtc)) {
10254                         return -EINVAL;
10255                 }
10256                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
10257
10258                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
10259                         connector->base.base.id,
10260                         drm_get_connector_name(&connector->base),
10261                         new_crtc->base.id);
10262         }
10263
10264         /* Check for any encoders that needs to be disabled. */
10265         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10266                             base.head) {
10267                 int num_connectors = 0;
10268                 list_for_each_entry(connector,
10269                                     &dev->mode_config.connector_list,
10270                                     base.head) {
10271                         if (connector->new_encoder == encoder) {
10272                                 WARN_ON(!connector->new_encoder->new_crtc);
10273                                 num_connectors++;
10274                         }
10275                 }
10276
10277                 if (num_connectors == 0)
10278                         encoder->new_crtc = NULL;
10279                 else if (num_connectors > 1)
10280                         return -EINVAL;
10281
10282                 /* Only now check for crtc changes so we don't miss encoders
10283                  * that will be disabled. */
10284                 if (&encoder->new_crtc->base != encoder->base.crtc) {
10285                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
10286                         config->mode_changed = true;
10287                 }
10288         }
10289         /* Now we've also updated encoder->new_crtc for all encoders. */
10290
10291         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10292                             base.head) {
10293                 crtc->new_enabled = false;
10294
10295                 list_for_each_entry(encoder,
10296                                     &dev->mode_config.encoder_list,
10297                                     base.head) {
10298                         if (encoder->new_crtc == crtc) {
10299                                 crtc->new_enabled = true;
10300                                 break;
10301                         }
10302                 }
10303
10304                 if (crtc->new_enabled != crtc->base.enabled) {
10305                         DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
10306                                       crtc->new_enabled ? "en" : "dis");
10307                         config->mode_changed = true;
10308                 }
10309
10310                 if (crtc->new_enabled)
10311                         crtc->new_config = &crtc->config;
10312                 else
10313                         crtc->new_config = NULL;
10314         }
10315
10316         return 0;
10317 }
10318
10319 static void disable_crtc_nofb(struct intel_crtc *crtc)
10320 {
10321         struct drm_device *dev = crtc->base.dev;
10322         struct intel_encoder *encoder;
10323         struct intel_connector *connector;
10324
10325         DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
10326                       pipe_name(crtc->pipe));
10327
10328         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10329                 if (connector->new_encoder &&
10330                     connector->new_encoder->new_crtc == crtc)
10331                         connector->new_encoder = NULL;
10332         }
10333
10334         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10335                 if (encoder->new_crtc == crtc)
10336                         encoder->new_crtc = NULL;
10337         }
10338
10339         crtc->new_enabled = false;
10340         crtc->new_config = NULL;
10341 }
10342
10343 static int intel_crtc_set_config(struct drm_mode_set *set)
10344 {
10345         struct drm_device *dev;
10346         struct drm_mode_set save_set;
10347         struct intel_set_config *config;
10348         int ret;
10349
10350         BUG_ON(!set);
10351         BUG_ON(!set->crtc);
10352         BUG_ON(!set->crtc->helper_private);
10353
10354         /* Enforce sane interface api - has been abused by the fb helper. */
10355         BUG_ON(!set->mode && set->fb);
10356         BUG_ON(set->fb && set->num_connectors == 0);
10357
10358         if (set->fb) {
10359                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
10360                                 set->crtc->base.id, set->fb->base.id,
10361                                 (int)set->num_connectors, set->x, set->y);
10362         } else {
10363                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
10364         }
10365
10366         dev = set->crtc->dev;
10367
10368         ret = -ENOMEM;
10369         config = kzalloc(sizeof(*config), GFP_KERNEL);
10370         if (!config)
10371                 goto out_config;
10372
10373         ret = intel_set_config_save_state(dev, config);
10374         if (ret)
10375                 goto out_config;
10376
10377         save_set.crtc = set->crtc;
10378         save_set.mode = &set->crtc->mode;
10379         save_set.x = set->crtc->x;
10380         save_set.y = set->crtc->y;
10381         save_set.fb = set->crtc->primary->fb;
10382
10383         /* Compute whether we need a full modeset, only an fb base update or no
10384          * change at all. In the future we might also check whether only the
10385          * mode changed, e.g. for LVDS where we only change the panel fitter in
10386          * such cases. */
10387         intel_set_config_compute_mode_changes(set, config);
10388
10389         ret = intel_modeset_stage_output_state(dev, set, config);
10390         if (ret)
10391                 goto fail;
10392
10393         if (config->mode_changed) {
10394                 ret = intel_set_mode(set->crtc, set->mode,
10395                                      set->x, set->y, set->fb);
10396         } else if (config->fb_changed) {
10397                 intel_crtc_wait_for_pending_flips(set->crtc);
10398
10399                 ret = intel_pipe_set_base(set->crtc,
10400                                           set->x, set->y, set->fb);
10401                 /*
10402                  * In the fastboot case this may be our only check of the
10403                  * state after boot.  It would be better to only do it on
10404                  * the first update, but we don't have a nice way of doing that
10405                  * (and really, set_config isn't used much for high freq page
10406                  * flipping, so increasing its cost here shouldn't be a big
10407                  * deal).
10408                  */
10409                 if (i915.fastboot && ret == 0)
10410                         intel_modeset_check_state(set->crtc->dev);
10411         }
10412
10413         if (ret) {
10414                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
10415                               set->crtc->base.id, ret);
10416 fail:
10417                 intel_set_config_restore_state(dev, config);
10418
10419                 /*
10420                  * HACK: if the pipe was on, but we didn't have a framebuffer,
10421                  * force the pipe off to avoid oopsing in the modeset code
10422                  * due to fb==NULL. This should only happen during boot since
10423                  * we don't yet reconstruct the FB from the hardware state.
10424                  */
10425                 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
10426                         disable_crtc_nofb(to_intel_crtc(save_set.crtc));
10427
10428                 /* Try to restore the config */
10429                 if (config->mode_changed &&
10430                     intel_set_mode(save_set.crtc, save_set.mode,
10431                                    save_set.x, save_set.y, save_set.fb))
10432                         DRM_ERROR("failed to restore config after modeset failure\n");
10433         }
10434
10435 out_config:
10436         intel_set_config_free(config);
10437         return ret;
10438 }
10439
10440 static const struct drm_crtc_funcs intel_crtc_funcs = {
10441         .cursor_set = intel_crtc_cursor_set,
10442         .cursor_move = intel_crtc_cursor_move,
10443         .gamma_set = intel_crtc_gamma_set,
10444         .set_config = intel_crtc_set_config,
10445         .destroy = intel_crtc_destroy,
10446         .page_flip = intel_crtc_page_flip,
10447 };
10448
10449 static void intel_cpu_pll_init(struct drm_device *dev)
10450 {
10451         if (HAS_DDI(dev))
10452                 intel_ddi_pll_init(dev);
10453 }
10454
10455 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
10456                                       struct intel_shared_dpll *pll,
10457                                       struct intel_dpll_hw_state *hw_state)
10458 {
10459         uint32_t val;
10460
10461         val = I915_READ(PCH_DPLL(pll->id));
10462         hw_state->dpll = val;
10463         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
10464         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
10465
10466         return val & DPLL_VCO_ENABLE;
10467 }
10468
10469 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
10470                                   struct intel_shared_dpll *pll)
10471 {
10472         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
10473         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
10474 }
10475
10476 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
10477                                 struct intel_shared_dpll *pll)
10478 {
10479         /* PCH refclock must be enabled first */
10480         ibx_assert_pch_refclk_enabled(dev_priv);
10481
10482         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10483
10484         /* Wait for the clocks to stabilize. */
10485         POSTING_READ(PCH_DPLL(pll->id));
10486         udelay(150);
10487
10488         /* The pixel multiplier can only be updated once the
10489          * DPLL is enabled and the clocks are stable.
10490          *
10491          * So write it again.
10492          */
10493         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10494         POSTING_READ(PCH_DPLL(pll->id));
10495         udelay(200);
10496 }
10497
10498 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
10499                                  struct intel_shared_dpll *pll)
10500 {
10501         struct drm_device *dev = dev_priv->dev;
10502         struct intel_crtc *crtc;
10503
10504         /* Make sure no transcoder isn't still depending on us. */
10505         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
10506                 if (intel_crtc_to_shared_dpll(crtc) == pll)
10507                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
10508         }
10509
10510         I915_WRITE(PCH_DPLL(pll->id), 0);
10511         POSTING_READ(PCH_DPLL(pll->id));
10512         udelay(200);
10513 }
10514
10515 static char *ibx_pch_dpll_names[] = {
10516         "PCH DPLL A",
10517         "PCH DPLL B",
10518 };
10519
10520 static void ibx_pch_dpll_init(struct drm_device *dev)
10521 {
10522         struct drm_i915_private *dev_priv = dev->dev_private;
10523         int i;
10524
10525         dev_priv->num_shared_dpll = 2;
10526
10527         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10528                 dev_priv->shared_dplls[i].id = i;
10529                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
10530                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
10531                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
10532                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
10533                 dev_priv->shared_dplls[i].get_hw_state =
10534                         ibx_pch_dpll_get_hw_state;
10535         }
10536 }
10537
10538 static void intel_shared_dpll_init(struct drm_device *dev)
10539 {
10540         struct drm_i915_private *dev_priv = dev->dev_private;
10541
10542         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
10543                 ibx_pch_dpll_init(dev);
10544         else
10545                 dev_priv->num_shared_dpll = 0;
10546
10547         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
10548 }
10549
10550 static void intel_crtc_init(struct drm_device *dev, int pipe)
10551 {
10552         struct drm_i915_private *dev_priv = dev->dev_private;
10553         struct intel_crtc *intel_crtc;
10554         int i;
10555
10556         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
10557         if (intel_crtc == NULL)
10558                 return;
10559
10560         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
10561
10562         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
10563         for (i = 0; i < 256; i++) {
10564                 intel_crtc->lut_r[i] = i;
10565                 intel_crtc->lut_g[i] = i;
10566                 intel_crtc->lut_b[i] = i;
10567         }
10568
10569         /*
10570          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
10571          * is hooked to plane B. Hence we want plane A feeding pipe B.
10572          */
10573         intel_crtc->pipe = pipe;
10574         intel_crtc->plane = pipe;
10575         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
10576                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
10577                 intel_crtc->plane = !pipe;
10578         }
10579
10580         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
10581                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
10582         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
10583         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
10584
10585         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
10586 }
10587
10588 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
10589 {
10590         struct drm_encoder *encoder = connector->base.encoder;
10591
10592         WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex));
10593
10594         if (!encoder)
10595                 return INVALID_PIPE;
10596
10597         return to_intel_crtc(encoder->crtc)->pipe;
10598 }
10599
10600 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
10601                                 struct drm_file *file)
10602 {
10603         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
10604         struct drm_mode_object *drmmode_obj;
10605         struct intel_crtc *crtc;
10606
10607         if (!drm_core_check_feature(dev, DRIVER_MODESET))
10608                 return -ENODEV;
10609
10610         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
10611                         DRM_MODE_OBJECT_CRTC);
10612
10613         if (!drmmode_obj) {
10614                 DRM_ERROR("no such CRTC id\n");
10615                 return -ENOENT;
10616         }
10617
10618         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
10619         pipe_from_crtc_id->pipe = crtc->pipe;
10620
10621         return 0;
10622 }
10623
10624 static int intel_encoder_clones(struct intel_encoder *encoder)
10625 {
10626         struct drm_device *dev = encoder->base.dev;
10627         struct intel_encoder *source_encoder;
10628         int index_mask = 0;
10629         int entry = 0;
10630
10631         list_for_each_entry(source_encoder,
10632                             &dev->mode_config.encoder_list, base.head) {
10633                 if (encoders_cloneable(encoder, source_encoder))
10634                         index_mask |= (1 << entry);
10635
10636                 entry++;
10637         }
10638
10639         return index_mask;
10640 }
10641
10642 static bool has_edp_a(struct drm_device *dev)
10643 {
10644         struct drm_i915_private *dev_priv = dev->dev_private;
10645
10646         if (!IS_MOBILE(dev))
10647                 return false;
10648
10649         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
10650                 return false;
10651
10652         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
10653                 return false;
10654
10655         return true;
10656 }
10657
10658 const char *intel_output_name(int output)
10659 {
10660         static const char *names[] = {
10661                 [INTEL_OUTPUT_UNUSED] = "Unused",
10662                 [INTEL_OUTPUT_ANALOG] = "Analog",
10663                 [INTEL_OUTPUT_DVO] = "DVO",
10664                 [INTEL_OUTPUT_SDVO] = "SDVO",
10665                 [INTEL_OUTPUT_LVDS] = "LVDS",
10666                 [INTEL_OUTPUT_TVOUT] = "TV",
10667                 [INTEL_OUTPUT_HDMI] = "HDMI",
10668                 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
10669                 [INTEL_OUTPUT_EDP] = "eDP",
10670                 [INTEL_OUTPUT_DSI] = "DSI",
10671                 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
10672         };
10673
10674         if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
10675                 return "Invalid";
10676
10677         return names[output];
10678 }
10679
10680 static void intel_setup_outputs(struct drm_device *dev)
10681 {
10682         struct drm_i915_private *dev_priv = dev->dev_private;
10683         struct intel_encoder *encoder;
10684         bool dpd_is_edp = false;
10685
10686         intel_lvds_init(dev);
10687
10688         if (!IS_ULT(dev))
10689                 intel_crt_init(dev);
10690
10691         if (HAS_DDI(dev)) {
10692                 int found;
10693
10694                 /* Haswell uses DDI functions to detect digital outputs */
10695                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
10696                 /* DDI A only supports eDP */
10697                 if (found)
10698                         intel_ddi_init(dev, PORT_A);
10699
10700                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
10701                  * register */
10702                 found = I915_READ(SFUSE_STRAP);
10703
10704                 if (found & SFUSE_STRAP_DDIB_DETECTED)
10705                         intel_ddi_init(dev, PORT_B);
10706                 if (found & SFUSE_STRAP_DDIC_DETECTED)
10707                         intel_ddi_init(dev, PORT_C);
10708                 if (found & SFUSE_STRAP_DDID_DETECTED)
10709                         intel_ddi_init(dev, PORT_D);
10710         } else if (HAS_PCH_SPLIT(dev)) {
10711                 int found;
10712                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
10713
10714                 if (has_edp_a(dev))
10715                         intel_dp_init(dev, DP_A, PORT_A);
10716
10717                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
10718                         /* PCH SDVOB multiplex with HDMIB */
10719                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
10720                         if (!found)
10721                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
10722                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
10723                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
10724                 }
10725
10726                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
10727                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
10728
10729                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
10730                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
10731
10732                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
10733                         intel_dp_init(dev, PCH_DP_C, PORT_C);
10734
10735                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
10736                         intel_dp_init(dev, PCH_DP_D, PORT_D);
10737         } else if (IS_VALLEYVIEW(dev)) {
10738                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
10739                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
10740                                         PORT_B);
10741                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
10742                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
10743                 }
10744
10745                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
10746                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
10747                                         PORT_C);
10748                         if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
10749                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
10750                 }
10751
10752                 intel_dsi_init(dev);
10753         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
10754                 bool found = false;
10755
10756                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10757                         DRM_DEBUG_KMS("probing SDVOB\n");
10758                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
10759                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
10760                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
10761                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
10762                         }
10763
10764                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
10765                                 intel_dp_init(dev, DP_B, PORT_B);
10766                 }
10767
10768                 /* Before G4X SDVOC doesn't have its own detect register */
10769
10770                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10771                         DRM_DEBUG_KMS("probing SDVOC\n");
10772                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
10773                 }
10774
10775                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
10776
10777                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
10778                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
10779                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
10780                         }
10781                         if (SUPPORTS_INTEGRATED_DP(dev))
10782                                 intel_dp_init(dev, DP_C, PORT_C);
10783                 }
10784
10785                 if (SUPPORTS_INTEGRATED_DP(dev) &&
10786                     (I915_READ(DP_D) & DP_DETECTED))
10787                         intel_dp_init(dev, DP_D, PORT_D);
10788         } else if (IS_GEN2(dev))
10789                 intel_dvo_init(dev);
10790
10791         if (SUPPORTS_TV(dev))
10792                 intel_tv_init(dev);
10793
10794         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10795                 encoder->base.possible_crtcs = encoder->crtc_mask;
10796                 encoder->base.possible_clones =
10797                         intel_encoder_clones(encoder);
10798         }
10799
10800         intel_init_pch_refclk(dev);
10801
10802         drm_helper_move_panel_connectors_to_head(dev);
10803 }
10804
10805 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
10806 {
10807         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10808
10809         drm_framebuffer_cleanup(fb);
10810         WARN_ON(!intel_fb->obj->framebuffer_references--);
10811         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
10812         kfree(intel_fb);
10813 }
10814
10815 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
10816                                                 struct drm_file *file,
10817                                                 unsigned int *handle)
10818 {
10819         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10820         struct drm_i915_gem_object *obj = intel_fb->obj;
10821
10822         return drm_gem_handle_create(file, &obj->base, handle);
10823 }
10824
10825 static const struct drm_framebuffer_funcs intel_fb_funcs = {
10826         .destroy = intel_user_framebuffer_destroy,
10827         .create_handle = intel_user_framebuffer_create_handle,
10828 };
10829
10830 static int intel_framebuffer_init(struct drm_device *dev,
10831                                   struct intel_framebuffer *intel_fb,
10832                                   struct drm_mode_fb_cmd2 *mode_cmd,
10833                                   struct drm_i915_gem_object *obj)
10834 {
10835         int aligned_height;
10836         int pitch_limit;
10837         int ret;
10838
10839         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
10840
10841         if (obj->tiling_mode == I915_TILING_Y) {
10842                 DRM_DEBUG("hardware does not support tiling Y\n");
10843                 return -EINVAL;
10844         }
10845
10846         if (mode_cmd->pitches[0] & 63) {
10847                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
10848                           mode_cmd->pitches[0]);
10849                 return -EINVAL;
10850         }
10851
10852         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
10853                 pitch_limit = 32*1024;
10854         } else if (INTEL_INFO(dev)->gen >= 4) {
10855                 if (obj->tiling_mode)
10856                         pitch_limit = 16*1024;
10857                 else
10858                         pitch_limit = 32*1024;
10859         } else if (INTEL_INFO(dev)->gen >= 3) {
10860                 if (obj->tiling_mode)
10861                         pitch_limit = 8*1024;
10862                 else
10863                         pitch_limit = 16*1024;
10864         } else
10865                 /* XXX DSPC is limited to 4k tiled */
10866                 pitch_limit = 8*1024;
10867
10868         if (mode_cmd->pitches[0] > pitch_limit) {
10869                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10870                           obj->tiling_mode ? "tiled" : "linear",
10871                           mode_cmd->pitches[0], pitch_limit);
10872                 return -EINVAL;
10873         }
10874
10875         if (obj->tiling_mode != I915_TILING_NONE &&
10876             mode_cmd->pitches[0] != obj->stride) {
10877                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10878                           mode_cmd->pitches[0], obj->stride);
10879                 return -EINVAL;
10880         }
10881
10882         /* Reject formats not supported by any plane early. */
10883         switch (mode_cmd->pixel_format) {
10884         case DRM_FORMAT_C8:
10885         case DRM_FORMAT_RGB565:
10886         case DRM_FORMAT_XRGB8888:
10887         case DRM_FORMAT_ARGB8888:
10888                 break;
10889         case DRM_FORMAT_XRGB1555:
10890         case DRM_FORMAT_ARGB1555:
10891                 if (INTEL_INFO(dev)->gen > 3) {
10892                         DRM_DEBUG("unsupported pixel format: %s\n",
10893                                   drm_get_format_name(mode_cmd->pixel_format));
10894                         return -EINVAL;
10895                 }
10896                 break;
10897         case DRM_FORMAT_XBGR8888:
10898         case DRM_FORMAT_ABGR8888:
10899         case DRM_FORMAT_XRGB2101010:
10900         case DRM_FORMAT_ARGB2101010:
10901         case DRM_FORMAT_XBGR2101010:
10902         case DRM_FORMAT_ABGR2101010:
10903                 if (INTEL_INFO(dev)->gen < 4) {
10904                         DRM_DEBUG("unsupported pixel format: %s\n",
10905                                   drm_get_format_name(mode_cmd->pixel_format));
10906                         return -EINVAL;
10907                 }
10908                 break;
10909         case DRM_FORMAT_YUYV:
10910         case DRM_FORMAT_UYVY:
10911         case DRM_FORMAT_YVYU:
10912         case DRM_FORMAT_VYUY:
10913                 if (INTEL_INFO(dev)->gen < 5) {
10914                         DRM_DEBUG("unsupported pixel format: %s\n",
10915                                   drm_get_format_name(mode_cmd->pixel_format));
10916                         return -EINVAL;
10917                 }
10918                 break;
10919         default:
10920                 DRM_DEBUG("unsupported pixel format: %s\n",
10921                           drm_get_format_name(mode_cmd->pixel_format));
10922                 return -EINVAL;
10923         }
10924
10925         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10926         if (mode_cmd->offsets[0] != 0)
10927                 return -EINVAL;
10928
10929         aligned_height = intel_align_height(dev, mode_cmd->height,
10930                                             obj->tiling_mode);
10931         /* FIXME drm helper for size checks (especially planar formats)? */
10932         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
10933                 return -EINVAL;
10934
10935         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
10936         intel_fb->obj = obj;
10937         intel_fb->obj->framebuffer_references++;
10938
10939         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
10940         if (ret) {
10941                 DRM_ERROR("framebuffer init failed %d\n", ret);
10942                 return ret;
10943         }
10944
10945         return 0;
10946 }
10947
10948 static struct drm_framebuffer *
10949 intel_user_framebuffer_create(struct drm_device *dev,
10950                               struct drm_file *filp,
10951                               struct drm_mode_fb_cmd2 *mode_cmd)
10952 {
10953         struct drm_i915_gem_object *obj;
10954
10955         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10956                                                 mode_cmd->handles[0]));
10957         if (&obj->base == NULL)
10958                 return ERR_PTR(-ENOENT);
10959
10960         return intel_framebuffer_create(dev, mode_cmd, obj);
10961 }
10962
10963 #ifndef CONFIG_DRM_I915_FBDEV
10964 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
10965 {
10966 }
10967 #endif
10968
10969 static const struct drm_mode_config_funcs intel_mode_funcs = {
10970         .fb_create = intel_user_framebuffer_create,
10971         .output_poll_changed = intel_fbdev_output_poll_changed,
10972 };
10973
10974 /* Set up chip specific display functions */
10975 static void intel_init_display(struct drm_device *dev)
10976 {
10977         struct drm_i915_private *dev_priv = dev->dev_private;
10978
10979         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10980                 dev_priv->display.find_dpll = g4x_find_best_dpll;
10981         else if (IS_VALLEYVIEW(dev))
10982                 dev_priv->display.find_dpll = vlv_find_best_dpll;
10983         else if (IS_PINEVIEW(dev))
10984                 dev_priv->display.find_dpll = pnv_find_best_dpll;
10985         else
10986                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10987
10988         if (HAS_DDI(dev)) {
10989                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
10990                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
10991                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
10992                 dev_priv->display.crtc_enable = haswell_crtc_enable;
10993                 dev_priv->display.crtc_disable = haswell_crtc_disable;
10994                 dev_priv->display.off = haswell_crtc_off;
10995                 dev_priv->display.update_primary_plane =
10996                         ironlake_update_primary_plane;
10997         } else if (HAS_PCH_SPLIT(dev)) {
10998                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
10999                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
11000                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
11001                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
11002                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
11003                 dev_priv->display.off = ironlake_crtc_off;
11004                 dev_priv->display.update_primary_plane =
11005                         ironlake_update_primary_plane;
11006         } else if (IS_VALLEYVIEW(dev)) {
11007                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11008                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11009                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11010                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
11011                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11012                 dev_priv->display.off = i9xx_crtc_off;
11013                 dev_priv->display.update_primary_plane =
11014                         i9xx_update_primary_plane;
11015         } else {
11016                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11017                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11018                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11019                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
11020                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11021                 dev_priv->display.off = i9xx_crtc_off;
11022                 dev_priv->display.update_primary_plane =
11023                         i9xx_update_primary_plane;
11024         }
11025
11026         /* Returns the core display clock speed */
11027         if (IS_VALLEYVIEW(dev))
11028                 dev_priv->display.get_display_clock_speed =
11029                         valleyview_get_display_clock_speed;
11030         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
11031                 dev_priv->display.get_display_clock_speed =
11032                         i945_get_display_clock_speed;
11033         else if (IS_I915G(dev))
11034                 dev_priv->display.get_display_clock_speed =
11035                         i915_get_display_clock_speed;
11036         else if (IS_I945GM(dev) || IS_845G(dev))
11037                 dev_priv->display.get_display_clock_speed =
11038                         i9xx_misc_get_display_clock_speed;
11039         else if (IS_PINEVIEW(dev))
11040                 dev_priv->display.get_display_clock_speed =
11041                         pnv_get_display_clock_speed;
11042         else if (IS_I915GM(dev))
11043                 dev_priv->display.get_display_clock_speed =
11044                         i915gm_get_display_clock_speed;
11045         else if (IS_I865G(dev))
11046                 dev_priv->display.get_display_clock_speed =
11047                         i865_get_display_clock_speed;
11048         else if (IS_I85X(dev))
11049                 dev_priv->display.get_display_clock_speed =
11050                         i855_get_display_clock_speed;
11051         else /* 852, 830 */
11052                 dev_priv->display.get_display_clock_speed =
11053                         i830_get_display_clock_speed;
11054
11055         if (HAS_PCH_SPLIT(dev)) {
11056                 if (IS_GEN5(dev)) {
11057                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
11058                         dev_priv->display.write_eld = ironlake_write_eld;
11059                 } else if (IS_GEN6(dev)) {
11060                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
11061                         dev_priv->display.write_eld = ironlake_write_eld;
11062                         dev_priv->display.modeset_global_resources =
11063                                 snb_modeset_global_resources;
11064                 } else if (IS_IVYBRIDGE(dev)) {
11065                         /* FIXME: detect B0+ stepping and use auto training */
11066                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
11067                         dev_priv->display.write_eld = ironlake_write_eld;
11068                         dev_priv->display.modeset_global_resources =
11069                                 ivb_modeset_global_resources;
11070                 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
11071                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
11072                         dev_priv->display.write_eld = haswell_write_eld;
11073                         dev_priv->display.modeset_global_resources =
11074                                 haswell_modeset_global_resources;
11075                 }
11076         } else if (IS_G4X(dev)) {
11077                 dev_priv->display.write_eld = g4x_write_eld;
11078         } else if (IS_VALLEYVIEW(dev)) {
11079                 dev_priv->display.modeset_global_resources =
11080                         valleyview_modeset_global_resources;
11081                 dev_priv->display.write_eld = ironlake_write_eld;
11082         }
11083
11084         /* Default just returns -ENODEV to indicate unsupported */
11085         dev_priv->display.queue_flip = intel_default_queue_flip;
11086
11087         switch (INTEL_INFO(dev)->gen) {
11088         case 2:
11089                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
11090                 break;
11091
11092         case 3:
11093                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
11094                 break;
11095
11096         case 4:
11097         case 5:
11098                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
11099                 break;
11100
11101         case 6:
11102                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
11103                 break;
11104         case 7:
11105         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
11106                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
11107                 break;
11108         }
11109
11110         intel_panel_init_backlight_funcs(dev);
11111 }
11112
11113 /*
11114  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
11115  * resume, or other times.  This quirk makes sure that's the case for
11116  * affected systems.
11117  */
11118 static void quirk_pipea_force(struct drm_device *dev)
11119 {
11120         struct drm_i915_private *dev_priv = dev->dev_private;
11121
11122         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
11123         DRM_INFO("applying pipe a force quirk\n");
11124 }
11125
11126 /*
11127  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
11128  */
11129 static void quirk_ssc_force_disable(struct drm_device *dev)
11130 {
11131         struct drm_i915_private *dev_priv = dev->dev_private;
11132         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
11133         DRM_INFO("applying lvds SSC disable quirk\n");
11134 }
11135
11136 /*
11137  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
11138  * brightness value
11139  */
11140 static void quirk_invert_brightness(struct drm_device *dev)
11141 {
11142         struct drm_i915_private *dev_priv = dev->dev_private;
11143         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
11144         DRM_INFO("applying inverted panel brightness quirk\n");
11145 }
11146
11147 struct intel_quirk {
11148         int device;
11149         int subsystem_vendor;
11150         int subsystem_device;
11151         void (*hook)(struct drm_device *dev);
11152 };
11153
11154 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
11155 struct intel_dmi_quirk {
11156         void (*hook)(struct drm_device *dev);
11157         const struct dmi_system_id (*dmi_id_list)[];
11158 };
11159
11160 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
11161 {
11162         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
11163         return 1;
11164 }
11165
11166 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
11167         {
11168                 .dmi_id_list = &(const struct dmi_system_id[]) {
11169                         {
11170                                 .callback = intel_dmi_reverse_brightness,
11171                                 .ident = "NCR Corporation",
11172                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
11173                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
11174                                 },
11175                         },
11176                         { }  /* terminating entry */
11177                 },
11178                 .hook = quirk_invert_brightness,
11179         },
11180 };
11181
11182 static struct intel_quirk intel_quirks[] = {
11183         /* HP Mini needs pipe A force quirk (LP: #322104) */
11184         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
11185
11186         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
11187         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
11188
11189         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
11190         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
11191
11192         /* 830 needs to leave pipe A & dpll A up */
11193         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
11194
11195         /* Lenovo U160 cannot use SSC on LVDS */
11196         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
11197
11198         /* Sony Vaio Y cannot use SSC on LVDS */
11199         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
11200
11201         /* Acer Aspire 5734Z must invert backlight brightness */
11202         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
11203
11204         /* Acer/eMachines G725 */
11205         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
11206
11207         /* Acer/eMachines e725 */
11208         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
11209
11210         /* Acer/Packard Bell NCL20 */
11211         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
11212
11213         /* Acer Aspire 4736Z */
11214         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
11215
11216         /* Acer Aspire 5336 */
11217         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
11218 };
11219
11220 static void intel_init_quirks(struct drm_device *dev)
11221 {
11222         struct pci_dev *d = dev->pdev;
11223         int i;
11224
11225         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
11226                 struct intel_quirk *q = &intel_quirks[i];
11227
11228                 if (d->device == q->device &&
11229                     (d->subsystem_vendor == q->subsystem_vendor ||
11230                      q->subsystem_vendor == PCI_ANY_ID) &&
11231                     (d->subsystem_device == q->subsystem_device ||
11232                      q->subsystem_device == PCI_ANY_ID))
11233                         q->hook(dev);
11234         }
11235         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
11236                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
11237                         intel_dmi_quirks[i].hook(dev);
11238         }
11239 }
11240
11241 /* Disable the VGA plane that we never use */
11242 static void i915_disable_vga(struct drm_device *dev)
11243 {
11244         struct drm_i915_private *dev_priv = dev->dev_private;
11245         u8 sr1;
11246         u32 vga_reg = i915_vgacntrl_reg(dev);
11247
11248         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
11249         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
11250         outb(SR01, VGA_SR_INDEX);
11251         sr1 = inb(VGA_SR_DATA);
11252         outb(sr1 | 1<<5, VGA_SR_DATA);
11253         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
11254         udelay(300);
11255
11256         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
11257         POSTING_READ(vga_reg);
11258 }
11259
11260 void intel_modeset_init_hw(struct drm_device *dev)
11261 {
11262         intel_prepare_ddi(dev);
11263
11264         intel_init_clock_gating(dev);
11265
11266         intel_reset_dpio(dev);
11267
11268         mutex_lock(&dev->struct_mutex);
11269         intel_enable_gt_powersave(dev);
11270         mutex_unlock(&dev->struct_mutex);
11271 }
11272
11273 void intel_modeset_suspend_hw(struct drm_device *dev)
11274 {
11275         intel_suspend_hw(dev);
11276 }
11277
11278 void intel_modeset_init(struct drm_device *dev)
11279 {
11280         struct drm_i915_private *dev_priv = dev->dev_private;
11281         int sprite, ret;
11282         enum pipe pipe;
11283         struct intel_crtc *crtc;
11284
11285         drm_mode_config_init(dev);
11286
11287         dev->mode_config.min_width = 0;
11288         dev->mode_config.min_height = 0;
11289
11290         dev->mode_config.preferred_depth = 24;
11291         dev->mode_config.prefer_shadow = 1;
11292
11293         dev->mode_config.funcs = &intel_mode_funcs;
11294
11295         intel_init_quirks(dev);
11296
11297         intel_init_pm(dev);
11298
11299         if (INTEL_INFO(dev)->num_pipes == 0)
11300                 return;
11301
11302         intel_init_display(dev);
11303
11304         if (IS_GEN2(dev)) {
11305                 dev->mode_config.max_width = 2048;
11306                 dev->mode_config.max_height = 2048;
11307         } else if (IS_GEN3(dev)) {
11308                 dev->mode_config.max_width = 4096;
11309                 dev->mode_config.max_height = 4096;
11310         } else {
11311                 dev->mode_config.max_width = 8192;
11312                 dev->mode_config.max_height = 8192;
11313         }
11314
11315         if (IS_GEN2(dev)) {
11316                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
11317                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
11318         } else {
11319                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
11320                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
11321         }
11322
11323         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
11324
11325         DRM_DEBUG_KMS("%d display pipe%s available.\n",
11326                       INTEL_INFO(dev)->num_pipes,
11327                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
11328
11329         for_each_pipe(pipe) {
11330                 intel_crtc_init(dev, pipe);
11331                 for_each_sprite(pipe, sprite) {
11332                         ret = intel_plane_init(dev, pipe, sprite);
11333                         if (ret)
11334                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
11335                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
11336                 }
11337         }
11338
11339         intel_init_dpio(dev);
11340         intel_reset_dpio(dev);
11341
11342         intel_cpu_pll_init(dev);
11343         intel_shared_dpll_init(dev);
11344
11345         /* Just disable it once at startup */
11346         i915_disable_vga(dev);
11347         intel_setup_outputs(dev);
11348
11349         /* Just in case the BIOS is doing something questionable. */
11350         intel_disable_fbc(dev);
11351
11352         mutex_lock(&dev->mode_config.mutex);
11353         intel_modeset_setup_hw_state(dev, false);
11354         mutex_unlock(&dev->mode_config.mutex);
11355
11356         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11357                             base.head) {
11358                 if (!crtc->active)
11359                         continue;
11360
11361                 /*
11362                  * Note that reserving the BIOS fb up front prevents us
11363                  * from stuffing other stolen allocations like the ring
11364                  * on top.  This prevents some ugliness at boot time, and
11365                  * can even allow for smooth boot transitions if the BIOS
11366                  * fb is large enough for the active pipe configuration.
11367                  */
11368                 if (dev_priv->display.get_plane_config) {
11369                         dev_priv->display.get_plane_config(crtc,
11370                                                            &crtc->plane_config);
11371                         /*
11372                          * If the fb is shared between multiple heads, we'll
11373                          * just get the first one.
11374                          */
11375                         intel_find_plane_obj(crtc, &crtc->plane_config);
11376                 }
11377         }
11378 }
11379
11380 static void
11381 intel_connector_break_all_links(struct intel_connector *connector)
11382 {
11383         connector->base.dpms = DRM_MODE_DPMS_OFF;
11384         connector->base.encoder = NULL;
11385         connector->encoder->connectors_active = false;
11386         connector->encoder->base.crtc = NULL;
11387 }
11388
11389 static void intel_enable_pipe_a(struct drm_device *dev)
11390 {
11391         struct intel_connector *connector;
11392         struct drm_connector *crt = NULL;
11393         struct intel_load_detect_pipe load_detect_temp;
11394
11395         /* We can't just switch on the pipe A, we need to set things up with a
11396          * proper mode and output configuration. As a gross hack, enable pipe A
11397          * by enabling the load detect pipe once. */
11398         list_for_each_entry(connector,
11399                             &dev->mode_config.connector_list,
11400                             base.head) {
11401                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
11402                         crt = &connector->base;
11403                         break;
11404                 }
11405         }
11406
11407         if (!crt)
11408                 return;
11409
11410         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
11411                 intel_release_load_detect_pipe(crt, &load_detect_temp);
11412
11413
11414 }
11415
11416 static bool
11417 intel_check_plane_mapping(struct intel_crtc *crtc)
11418 {
11419         struct drm_device *dev = crtc->base.dev;
11420         struct drm_i915_private *dev_priv = dev->dev_private;
11421         u32 reg, val;
11422
11423         if (INTEL_INFO(dev)->num_pipes == 1)
11424                 return true;
11425
11426         reg = DSPCNTR(!crtc->plane);
11427         val = I915_READ(reg);
11428
11429         if ((val & DISPLAY_PLANE_ENABLE) &&
11430             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
11431                 return false;
11432
11433         return true;
11434 }
11435
11436 static void intel_sanitize_crtc(struct intel_crtc *crtc)
11437 {
11438         struct drm_device *dev = crtc->base.dev;
11439         struct drm_i915_private *dev_priv = dev->dev_private;
11440         u32 reg;
11441
11442         /* Clear any frame start delays used for debugging left by the BIOS */
11443         reg = PIPECONF(crtc->config.cpu_transcoder);
11444         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
11445
11446         /* We need to sanitize the plane -> pipe mapping first because this will
11447          * disable the crtc (and hence change the state) if it is wrong. Note
11448          * that gen4+ has a fixed plane -> pipe mapping.  */
11449         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
11450                 struct intel_connector *connector;
11451                 bool plane;
11452
11453                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
11454                               crtc->base.base.id);
11455
11456                 /* Pipe has the wrong plane attached and the plane is active.
11457                  * Temporarily change the plane mapping and disable everything
11458                  * ...  */
11459                 plane = crtc->plane;
11460                 crtc->plane = !plane;
11461                 dev_priv->display.crtc_disable(&crtc->base);
11462                 crtc->plane = plane;
11463
11464                 /* ... and break all links. */
11465                 list_for_each_entry(connector, &dev->mode_config.connector_list,
11466                                     base.head) {
11467                         if (connector->encoder->base.crtc != &crtc->base)
11468                                 continue;
11469
11470                         intel_connector_break_all_links(connector);
11471                 }
11472
11473                 WARN_ON(crtc->active);
11474                 crtc->base.enabled = false;
11475         }
11476
11477         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
11478             crtc->pipe == PIPE_A && !crtc->active) {
11479                 /* BIOS forgot to enable pipe A, this mostly happens after
11480                  * resume. Force-enable the pipe to fix this, the update_dpms
11481                  * call below we restore the pipe to the right state, but leave
11482                  * the required bits on. */
11483                 intel_enable_pipe_a(dev);
11484         }
11485
11486         /* Adjust the state of the output pipe according to whether we
11487          * have active connectors/encoders. */
11488         intel_crtc_update_dpms(&crtc->base);
11489
11490         if (crtc->active != crtc->base.enabled) {
11491                 struct intel_encoder *encoder;
11492
11493                 /* This can happen either due to bugs in the get_hw_state
11494                  * functions or because the pipe is force-enabled due to the
11495                  * pipe A quirk. */
11496                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
11497                               crtc->base.base.id,
11498                               crtc->base.enabled ? "enabled" : "disabled",
11499                               crtc->active ? "enabled" : "disabled");
11500
11501                 crtc->base.enabled = crtc->active;
11502
11503                 /* Because we only establish the connector -> encoder ->
11504                  * crtc links if something is active, this means the
11505                  * crtc is now deactivated. Break the links. connector
11506                  * -> encoder links are only establish when things are
11507                  *  actually up, hence no need to break them. */
11508                 WARN_ON(crtc->active);
11509
11510                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
11511                         WARN_ON(encoder->connectors_active);
11512                         encoder->base.crtc = NULL;
11513                 }
11514         }
11515         if (crtc->active) {
11516                 /*
11517                  * We start out with underrun reporting disabled to avoid races.
11518                  * For correct bookkeeping mark this on active crtcs.
11519                  *
11520                  * No protection against concurrent access is required - at
11521                  * worst a fifo underrun happens which also sets this to false.
11522                  */
11523                 crtc->cpu_fifo_underrun_disabled = true;
11524                 crtc->pch_fifo_underrun_disabled = true;
11525         }
11526 }
11527
11528 static void intel_sanitize_encoder(struct intel_encoder *encoder)
11529 {
11530         struct intel_connector *connector;
11531         struct drm_device *dev = encoder->base.dev;
11532
11533         /* We need to check both for a crtc link (meaning that the
11534          * encoder is active and trying to read from a pipe) and the
11535          * pipe itself being active. */
11536         bool has_active_crtc = encoder->base.crtc &&
11537                 to_intel_crtc(encoder->base.crtc)->active;
11538
11539         if (encoder->connectors_active && !has_active_crtc) {
11540                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
11541                               encoder->base.base.id,
11542                               drm_get_encoder_name(&encoder->base));
11543
11544                 /* Connector is active, but has no active pipe. This is
11545                  * fallout from our resume register restoring. Disable
11546                  * the encoder manually again. */
11547                 if (encoder->base.crtc) {
11548                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
11549                                       encoder->base.base.id,
11550                                       drm_get_encoder_name(&encoder->base));
11551                         encoder->disable(encoder);
11552                 }
11553
11554                 /* Inconsistent output/port/pipe state happens presumably due to
11555                  * a bug in one of the get_hw_state functions. Or someplace else
11556                  * in our code, like the register restore mess on resume. Clamp
11557                  * things to off as a safer default. */
11558                 list_for_each_entry(connector,
11559                                     &dev->mode_config.connector_list,
11560                                     base.head) {
11561                         if (connector->encoder != encoder)
11562                                 continue;
11563
11564                         intel_connector_break_all_links(connector);
11565                 }
11566         }
11567         /* Enabled encoders without active connectors will be fixed in
11568          * the crtc fixup. */
11569 }
11570
11571 void i915_redisable_vga_power_on(struct drm_device *dev)
11572 {
11573         struct drm_i915_private *dev_priv = dev->dev_private;
11574         u32 vga_reg = i915_vgacntrl_reg(dev);
11575
11576         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
11577                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
11578                 i915_disable_vga(dev);
11579         }
11580 }
11581
11582 void i915_redisable_vga(struct drm_device *dev)
11583 {
11584         struct drm_i915_private *dev_priv = dev->dev_private;
11585
11586         /* This function can be called both from intel_modeset_setup_hw_state or
11587          * at a very early point in our resume sequence, where the power well
11588          * structures are not yet restored. Since this function is at a very
11589          * paranoid "someone might have enabled VGA while we were not looking"
11590          * level, just check if the power well is enabled instead of trying to
11591          * follow the "don't touch the power well if we don't need it" policy
11592          * the rest of the driver uses. */
11593         if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
11594                 return;
11595
11596         i915_redisable_vga_power_on(dev);
11597 }
11598
11599 static void intel_modeset_readout_hw_state(struct drm_device *dev)
11600 {
11601         struct drm_i915_private *dev_priv = dev->dev_private;
11602         enum pipe pipe;
11603         struct intel_crtc *crtc;
11604         struct intel_encoder *encoder;
11605         struct intel_connector *connector;
11606         int i;
11607
11608         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11609                             base.head) {
11610                 memset(&crtc->config, 0, sizeof(crtc->config));
11611
11612                 crtc->active = dev_priv->display.get_pipe_config(crtc,
11613                                                                  &crtc->config);
11614
11615                 crtc->base.enabled = crtc->active;
11616                 crtc->primary_enabled = crtc->active;
11617
11618                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
11619                               crtc->base.base.id,
11620                               crtc->active ? "enabled" : "disabled");
11621         }
11622
11623         /* FIXME: Smash this into the new shared dpll infrastructure. */
11624         if (HAS_DDI(dev))
11625                 intel_ddi_setup_hw_pll_state(dev);
11626
11627         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11628                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11629
11630                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
11631                 pll->active = 0;
11632                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11633                                     base.head) {
11634                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11635                                 pll->active++;
11636                 }
11637                 pll->refcount = pll->active;
11638
11639                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
11640                               pll->name, pll->refcount, pll->on);
11641         }
11642
11643         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11644                             base.head) {
11645                 pipe = 0;
11646
11647                 if (encoder->get_hw_state(encoder, &pipe)) {
11648                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11649                         encoder->base.crtc = &crtc->base;
11650                         encoder->get_config(encoder, &crtc->config);
11651                 } else {
11652                         encoder->base.crtc = NULL;
11653                 }
11654
11655                 encoder->connectors_active = false;
11656                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
11657                               encoder->base.base.id,
11658                               drm_get_encoder_name(&encoder->base),
11659                               encoder->base.crtc ? "enabled" : "disabled",
11660                               pipe_name(pipe));
11661         }
11662
11663         list_for_each_entry(connector, &dev->mode_config.connector_list,
11664                             base.head) {
11665                 if (connector->get_hw_state(connector)) {
11666                         connector->base.dpms = DRM_MODE_DPMS_ON;
11667                         connector->encoder->connectors_active = true;
11668                         connector->base.encoder = &connector->encoder->base;
11669                 } else {
11670                         connector->base.dpms = DRM_MODE_DPMS_OFF;
11671                         connector->base.encoder = NULL;
11672                 }
11673                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
11674                               connector->base.base.id,
11675                               drm_get_connector_name(&connector->base),
11676                               connector->base.encoder ? "enabled" : "disabled");
11677         }
11678 }
11679
11680 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
11681  * and i915 state tracking structures. */
11682 void intel_modeset_setup_hw_state(struct drm_device *dev,
11683                                   bool force_restore)
11684 {
11685         struct drm_i915_private *dev_priv = dev->dev_private;
11686         enum pipe pipe;
11687         struct intel_crtc *crtc;
11688         struct intel_encoder *encoder;
11689         int i;
11690
11691         intel_modeset_readout_hw_state(dev);
11692
11693         /*
11694          * Now that we have the config, copy it to each CRTC struct
11695          * Note that this could go away if we move to using crtc_config
11696          * checking everywhere.
11697          */
11698         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11699                             base.head) {
11700                 if (crtc->active && i915.fastboot) {
11701                         intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
11702                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
11703                                       crtc->base.base.id);
11704                         drm_mode_debug_printmodeline(&crtc->base.mode);
11705                 }
11706         }
11707
11708         /* HW state is read out, now we need to sanitize this mess. */
11709         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11710                             base.head) {
11711                 intel_sanitize_encoder(encoder);
11712         }
11713
11714         for_each_pipe(pipe) {
11715                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11716                 intel_sanitize_crtc(crtc);
11717                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
11718         }
11719
11720         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11721                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11722
11723                 if (!pll->on || pll->active)
11724                         continue;
11725
11726                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
11727
11728                 pll->disable(dev_priv, pll);
11729                 pll->on = false;
11730         }
11731
11732         if (HAS_PCH_SPLIT(dev))
11733                 ilk_wm_get_hw_state(dev);
11734
11735         if (force_restore) {
11736                 i915_redisable_vga(dev);
11737
11738                 /*
11739                  * We need to use raw interfaces for restoring state to avoid
11740                  * checking (bogus) intermediate states.
11741                  */
11742                 for_each_pipe(pipe) {
11743                         struct drm_crtc *crtc =
11744                                 dev_priv->pipe_to_crtc_mapping[pipe];
11745
11746                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
11747                                          crtc->primary->fb);
11748                 }
11749         } else {
11750                 intel_modeset_update_staged_output_state(dev);
11751         }
11752
11753         intel_modeset_check_state(dev);
11754 }
11755
11756 void intel_modeset_gem_init(struct drm_device *dev)
11757 {
11758         struct drm_crtc *c;
11759         struct intel_framebuffer *fb;
11760
11761         mutex_lock(&dev->struct_mutex);
11762         intel_init_gt_powersave(dev);
11763         mutex_unlock(&dev->struct_mutex);
11764
11765         intel_modeset_init_hw(dev);
11766
11767         intel_setup_overlay(dev);
11768
11769         /*
11770          * Make sure any fbs we allocated at startup are properly
11771          * pinned & fenced.  When we do the allocation it's too early
11772          * for this.
11773          */
11774         mutex_lock(&dev->struct_mutex);
11775         list_for_each_entry(c, &dev->mode_config.crtc_list, head) {
11776                 if (!c->primary->fb)
11777                         continue;
11778
11779                 fb = to_intel_framebuffer(c->primary->fb);
11780                 if (intel_pin_and_fence_fb_obj(dev, fb->obj, NULL)) {
11781                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
11782                                   to_intel_crtc(c)->pipe);
11783                         drm_framebuffer_unreference(c->primary->fb);
11784                         c->primary->fb = NULL;
11785                 }
11786         }
11787         mutex_unlock(&dev->struct_mutex);
11788 }
11789
11790 void intel_connector_unregister(struct intel_connector *intel_connector)
11791 {
11792         struct drm_connector *connector = &intel_connector->base;
11793
11794         intel_panel_destroy_backlight(connector);
11795         drm_sysfs_connector_remove(connector);
11796 }
11797
11798 void intel_modeset_cleanup(struct drm_device *dev)
11799 {
11800         struct drm_i915_private *dev_priv = dev->dev_private;
11801         struct drm_crtc *crtc;
11802         struct drm_connector *connector;
11803
11804         /*
11805          * Interrupts and polling as the first thing to avoid creating havoc.
11806          * Too much stuff here (turning of rps, connectors, ...) would
11807          * experience fancy races otherwise.
11808          */
11809         drm_irq_uninstall(dev);
11810         cancel_work_sync(&dev_priv->hotplug_work);
11811         /*
11812          * Due to the hpd irq storm handling the hotplug work can re-arm the
11813          * poll handlers. Hence disable polling after hpd handling is shut down.
11814          */
11815         drm_kms_helper_poll_fini(dev);
11816
11817         mutex_lock(&dev->struct_mutex);
11818
11819         intel_unregister_dsm_handler();
11820
11821         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
11822                 /* Skip inactive CRTCs */
11823                 if (!crtc->primary->fb)
11824                         continue;
11825
11826                 intel_increase_pllclock(crtc);
11827         }
11828
11829         intel_disable_fbc(dev);
11830
11831         intel_disable_gt_powersave(dev);
11832
11833         ironlake_teardown_rc6(dev);
11834
11835         mutex_unlock(&dev->struct_mutex);
11836
11837         /* flush any delayed tasks or pending work */
11838         flush_scheduled_work();
11839
11840         /* destroy the backlight and sysfs files before encoders/connectors */
11841         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11842                 struct intel_connector *intel_connector;
11843
11844                 intel_connector = to_intel_connector(connector);
11845                 intel_connector->unregister(intel_connector);
11846         }
11847
11848         drm_mode_config_cleanup(dev);
11849
11850         intel_cleanup_overlay(dev);
11851
11852         mutex_lock(&dev->struct_mutex);
11853         intel_cleanup_gt_powersave(dev);
11854         mutex_unlock(&dev->struct_mutex);
11855 }
11856
11857 /*
11858  * Return which encoder is currently attached for connector.
11859  */
11860 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
11861 {
11862         return &intel_attached_encoder(connector)->base;
11863 }
11864
11865 void intel_connector_attach_encoder(struct intel_connector *connector,
11866                                     struct intel_encoder *encoder)
11867 {
11868         connector->encoder = encoder;
11869         drm_mode_connector_attach_encoder(&connector->base,
11870                                           &encoder->base);
11871 }
11872
11873 /*
11874  * set vga decode state - true == enable VGA decode
11875  */
11876 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
11877 {
11878         struct drm_i915_private *dev_priv = dev->dev_private;
11879         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
11880         u16 gmch_ctrl;
11881
11882         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
11883                 DRM_ERROR("failed to read control word\n");
11884                 return -EIO;
11885         }
11886
11887         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
11888                 return 0;
11889
11890         if (state)
11891                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
11892         else
11893                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
11894
11895         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
11896                 DRM_ERROR("failed to write control word\n");
11897                 return -EIO;
11898         }
11899
11900         return 0;
11901 }
11902
11903 struct intel_display_error_state {
11904
11905         u32 power_well_driver;
11906
11907         int num_transcoders;
11908
11909         struct intel_cursor_error_state {
11910                 u32 control;
11911                 u32 position;
11912                 u32 base;
11913                 u32 size;
11914         } cursor[I915_MAX_PIPES];
11915
11916         struct intel_pipe_error_state {
11917                 bool power_domain_on;
11918                 u32 source;
11919         } pipe[I915_MAX_PIPES];
11920
11921         struct intel_plane_error_state {
11922                 u32 control;
11923                 u32 stride;
11924                 u32 size;
11925                 u32 pos;
11926                 u32 addr;
11927                 u32 surface;
11928                 u32 tile_offset;
11929         } plane[I915_MAX_PIPES];
11930
11931         struct intel_transcoder_error_state {
11932                 bool power_domain_on;
11933                 enum transcoder cpu_transcoder;
11934
11935                 u32 conf;
11936
11937                 u32 htotal;
11938                 u32 hblank;
11939                 u32 hsync;
11940                 u32 vtotal;
11941                 u32 vblank;
11942                 u32 vsync;
11943         } transcoder[4];
11944 };
11945
11946 struct intel_display_error_state *
11947 intel_display_capture_error_state(struct drm_device *dev)
11948 {
11949         struct drm_i915_private *dev_priv = dev->dev_private;
11950         struct intel_display_error_state *error;
11951         int transcoders[] = {
11952                 TRANSCODER_A,
11953                 TRANSCODER_B,
11954                 TRANSCODER_C,
11955                 TRANSCODER_EDP,
11956         };
11957         int i;
11958
11959         if (INTEL_INFO(dev)->num_pipes == 0)
11960                 return NULL;
11961
11962         error = kzalloc(sizeof(*error), GFP_ATOMIC);
11963         if (error == NULL)
11964                 return NULL;
11965
11966         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
11967                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
11968
11969         for_each_pipe(i) {
11970                 error->pipe[i].power_domain_on =
11971                         intel_display_power_enabled_sw(dev_priv,
11972                                                        POWER_DOMAIN_PIPE(i));
11973                 if (!error->pipe[i].power_domain_on)
11974                         continue;
11975
11976                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
11977                         error->cursor[i].control = I915_READ(CURCNTR(i));
11978                         error->cursor[i].position = I915_READ(CURPOS(i));
11979                         error->cursor[i].base = I915_READ(CURBASE(i));
11980                 } else {
11981                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
11982                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
11983                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
11984                 }
11985
11986                 error->plane[i].control = I915_READ(DSPCNTR(i));
11987                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
11988                 if (INTEL_INFO(dev)->gen <= 3) {
11989                         error->plane[i].size = I915_READ(DSPSIZE(i));
11990                         error->plane[i].pos = I915_READ(DSPPOS(i));
11991                 }
11992                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11993                         error->plane[i].addr = I915_READ(DSPADDR(i));
11994                 if (INTEL_INFO(dev)->gen >= 4) {
11995                         error->plane[i].surface = I915_READ(DSPSURF(i));
11996                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
11997                 }
11998
11999                 error->pipe[i].source = I915_READ(PIPESRC(i));
12000         }
12001
12002         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
12003         if (HAS_DDI(dev_priv->dev))
12004                 error->num_transcoders++; /* Account for eDP. */
12005
12006         for (i = 0; i < error->num_transcoders; i++) {
12007                 enum transcoder cpu_transcoder = transcoders[i];
12008
12009                 error->transcoder[i].power_domain_on =
12010                         intel_display_power_enabled_sw(dev_priv,
12011                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
12012                 if (!error->transcoder[i].power_domain_on)
12013                         continue;
12014
12015                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
12016
12017                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
12018                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
12019                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
12020                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
12021                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
12022                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
12023                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
12024         }
12025
12026         return error;
12027 }
12028
12029 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
12030
12031 void
12032 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
12033                                 struct drm_device *dev,
12034                                 struct intel_display_error_state *error)
12035 {
12036         int i;
12037
12038         if (!error)
12039                 return;
12040
12041         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
12042         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
12043                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
12044                            error->power_well_driver);
12045         for_each_pipe(i) {
12046                 err_printf(m, "Pipe [%d]:\n", i);
12047                 err_printf(m, "  Power: %s\n",
12048                            error->pipe[i].power_domain_on ? "on" : "off");
12049                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
12050
12051                 err_printf(m, "Plane [%d]:\n", i);
12052                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
12053                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
12054                 if (INTEL_INFO(dev)->gen <= 3) {
12055                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
12056                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
12057                 }
12058                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
12059                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
12060                 if (INTEL_INFO(dev)->gen >= 4) {
12061                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
12062                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
12063                 }
12064
12065                 err_printf(m, "Cursor [%d]:\n", i);
12066                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
12067                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
12068                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
12069         }
12070
12071         for (i = 0; i < error->num_transcoders; i++) {
12072                 err_printf(m, "CPU transcoder: %c\n",
12073                            transcoder_name(error->transcoder[i].cpu_transcoder));
12074                 err_printf(m, "  Power: %s\n",
12075                            error->transcoder[i].power_domain_on ? "on" : "off");
12076                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
12077                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
12078                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
12079                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
12080                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
12081                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
12082                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
12083         }
12084 }