drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <drm/drm_plane_helper.h>
  43 #include <drm/drm_rect.h>
  44 #include <linux/dma_remapping.h>
  45
  46 /* Primary plane formats supported by all gen */
  47 #define COMMON_PRIMARY_FORMATS \
  48         DRM_FORMAT_C8, \
  49         DRM_FORMAT_RGB565, \
  50         DRM_FORMAT_XRGB8888, \
  51         DRM_FORMAT_ARGB8888
  52
  53 /* Primary plane formats for gen <= 3 */
  54 static const uint32_t intel_primary_formats_gen2[] = {
  55         COMMON_PRIMARY_FORMATS,
  56         DRM_FORMAT_XRGB1555,
  57         DRM_FORMAT_ARGB1555,
  58 };
  59
  60 /* Primary plane formats for gen >= 4 */
  61 static const uint32_t intel_primary_formats_gen4[] = {
  62         COMMON_PRIMARY_FORMATS, \
  63         DRM_FORMAT_XBGR8888,
  64         DRM_FORMAT_ABGR8888,
  65         DRM_FORMAT_XRGB2101010,
  66         DRM_FORMAT_ARGB2101010,
  67         DRM_FORMAT_XBGR2101010,
  68         DRM_FORMAT_ABGR2101010,
  69 };
  70
  71 /* Cursor formats */
  72 static const uint32_t intel_cursor_formats[] = {
  73         DRM_FORMAT_ARGB8888,
  74 };
  75
  76 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  77
  78 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  79                                 struct intel_crtc_config *pipe_config);
  80 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  81                                    struct intel_crtc_config *pipe_config);
  82
  83 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  84                           int x, int y, struct drm_framebuffer *old_fb);
  85 static int intel_framebuffer_init(struct drm_device *dev,
  86                                   struct intel_framebuffer *ifb,
  87                                   struct drm_mode_fb_cmd2 *mode_cmd,
  88                                   struct drm_i915_gem_object *obj);
  89 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  90 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  91 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  92                                          struct intel_link_m_n *m_n,
  93                                          struct intel_link_m_n *m2_n2);
  94 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
  95 static void haswell_set_pipeconf(struct drm_crtc *crtc);
  96 static void intel_set_pipe_csc(struct drm_crtc *crtc);
  97 static void vlv_prepare_pll(struct intel_crtc *crtc,
  98                             const struct intel_crtc_config *pipe_config);
  99 static void chv_prepare_pll(struct intel_crtc *crtc,
 100                             const struct intel_crtc_config *pipe_config);
 101
 102 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
 103 {
 104         if (!connector->mst_port)
 105                 return connector->encoder;
 106         else
 107                 return &connector->mst_port->mst_encoders[pipe]->base;
 108 }
 109
 110 typedef struct {
 111         int     min, max;
 112 } intel_range_t;
 113
 114 typedef struct {
 115         int     dot_limit;
 116         int     p2_slow, p2_fast;
 117 } intel_p2_t;
 118
 119 typedef struct intel_limit intel_limit_t;
 120 struct intel_limit {
 121         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 122         intel_p2_t          p2;
 123 };
 124
 125 int
 126 intel_pch_rawclk(struct drm_device *dev)
 127 {
 128         struct drm_i915_private *dev_priv = dev->dev_private;
 129
 130         WARN_ON(!HAS_PCH_SPLIT(dev));
 131
 132         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 133 }
 134
 135 static inline u32 /* units of 100MHz */
 136 intel_fdi_link_freq(struct drm_device *dev)
 137 {
 138         if (IS_GEN5(dev)) {
 139                 struct drm_i915_private *dev_priv = dev->dev_private;
 140                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 141         } else
 142                 return 27;
 143 }
 144
 145 static const intel_limit_t intel_limits_i8xx_dac = {
 146         .dot = { .min = 25000, .max = 350000 },
 147         .vco = { .min = 908000, .max = 1512000 },
 148         .n = { .min = 2, .max = 16 },
 149         .m = { .min = 96, .max = 140 },
 150         .m1 = { .min = 18, .max = 26 },
 151         .m2 = { .min = 6, .max = 16 },
 152         .p = { .min = 4, .max = 128 },
 153         .p1 = { .min = 2, .max = 33 },
 154         .p2 = { .dot_limit = 165000,
 155                 .p2_slow = 4, .p2_fast = 2 },
 156 };
 157
 158 static const intel_limit_t intel_limits_i8xx_dvo = {
 159         .dot = { .min = 25000, .max = 350000 },
 160         .vco = { .min = 908000, .max = 1512000 },
 161         .n = { .min = 2, .max = 16 },
 162         .m = { .min = 96, .max = 140 },
 163         .m1 = { .min = 18, .max = 26 },
 164         .m2 = { .min = 6, .max = 16 },
 165         .p = { .min = 4, .max = 128 },
 166         .p1 = { .min = 2, .max = 33 },
 167         .p2 = { .dot_limit = 165000,
 168                 .p2_slow = 4, .p2_fast = 4 },
 169 };
 170
 171 static const intel_limit_t intel_limits_i8xx_lvds = {
 172         .dot = { .min = 25000, .max = 350000 },
 173         .vco = { .min = 908000, .max = 1512000 },
 174         .n = { .min = 2, .max = 16 },
 175         .m = { .min = 96, .max = 140 },
 176         .m1 = { .min = 18, .max = 26 },
 177         .m2 = { .min = 6, .max = 16 },
 178         .p = { .min = 4, .max = 128 },
 179         .p1 = { .min = 1, .max = 6 },
 180         .p2 = { .dot_limit = 165000,
 181                 .p2_slow = 14, .p2_fast = 7 },
 182 };
 183
 184 static const intel_limit_t intel_limits_i9xx_sdvo = {
 185         .dot = { .min = 20000, .max = 400000 },
 186         .vco = { .min = 1400000, .max = 2800000 },
 187         .n = { .min = 1, .max = 6 },
 188         .m = { .min = 70, .max = 120 },
 189         .m1 = { .min = 8, .max = 18 },
 190         .m2 = { .min = 3, .max = 7 },
 191         .p = { .min = 5, .max = 80 },
 192         .p1 = { .min = 1, .max = 8 },
 193         .p2 = { .dot_limit = 200000,
 194                 .p2_slow = 10, .p2_fast = 5 },
 195 };
 196
 197 static const intel_limit_t intel_limits_i9xx_lvds = {
 198         .dot = { .min = 20000, .max = 400000 },
 199         .vco = { .min = 1400000, .max = 2800000 },
 200         .n = { .min = 1, .max = 6 },
 201         .m = { .min = 70, .max = 120 },
 202         .m1 = { .min = 8, .max = 18 },
 203         .m2 = { .min = 3, .max = 7 },
 204         .p = { .min = 7, .max = 98 },
 205         .p1 = { .min = 1, .max = 8 },
 206         .p2 = { .dot_limit = 112000,
 207                 .p2_slow = 14, .p2_fast = 7 },
 208 };
 209
 210
 211 static const intel_limit_t intel_limits_g4x_sdvo = {
 212         .dot = { .min = 25000, .max = 270000 },
 213         .vco = { .min = 1750000, .max = 3500000},
 214         .n = { .min = 1, .max = 4 },
 215         .m = { .min = 104, .max = 138 },
 216         .m1 = { .min = 17, .max = 23 },
 217         .m2 = { .min = 5, .max = 11 },
 218         .p = { .min = 10, .max = 30 },
 219         .p1 = { .min = 1, .max = 3},
 220         .p2 = { .dot_limit = 270000,
 221                 .p2_slow = 10,
 222                 .p2_fast = 10
 223         },
 224 };
 225
 226 static const intel_limit_t intel_limits_g4x_hdmi = {
 227         .dot = { .min = 22000, .max = 400000 },
 228         .vco = { .min = 1750000, .max = 3500000},
 229         .n = { .min = 1, .max = 4 },
 230         .m = { .min = 104, .max = 138 },
 231         .m1 = { .min = 16, .max = 23 },
 232         .m2 = { .min = 5, .max = 11 },
 233         .p = { .min = 5, .max = 80 },
 234         .p1 = { .min = 1, .max = 8},
 235         .p2 = { .dot_limit = 165000,
 236                 .p2_slow = 10, .p2_fast = 5 },
 237 };
 238
 239 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 240         .dot = { .min = 20000, .max = 115000 },
 241         .vco = { .min = 1750000, .max = 3500000 },
 242         .n = { .min = 1, .max = 3 },
 243         .m = { .min = 104, .max = 138 },
 244         .m1 = { .min = 17, .max = 23 },
 245         .m2 = { .min = 5, .max = 11 },
 246         .p = { .min = 28, .max = 112 },
 247         .p1 = { .min = 2, .max = 8 },
 248         .p2 = { .dot_limit = 0,
 249                 .p2_slow = 14, .p2_fast = 14
 250         },
 251 };
 252
 253 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 254         .dot = { .min = 80000, .max = 224000 },
 255         .vco = { .min = 1750000, .max = 3500000 },
 256         .n = { .min = 1, .max = 3 },
 257         .m = { .min = 104, .max = 138 },
 258         .m1 = { .min = 17, .max = 23 },
 259         .m2 = { .min = 5, .max = 11 },
 260         .p = { .min = 14, .max = 42 },
 261         .p1 = { .min = 2, .max = 6 },
 262         .p2 = { .dot_limit = 0,
 263                 .p2_slow = 7, .p2_fast = 7
 264         },
 265 };
 266
 267 static const intel_limit_t intel_limits_pineview_sdvo = {
 268         .dot = { .min = 20000, .max = 400000},
 269         .vco = { .min = 1700000, .max = 3500000 },
 270         /* Pineview's Ncounter is a ring counter */
 271         .n = { .min = 3, .max = 6 },
 272         .m = { .min = 2, .max = 256 },
 273         /* Pineview only has one combined m divider, which we treat as m2. */
 274         .m1 = { .min = 0, .max = 0 },
 275         .m2 = { .min = 0, .max = 254 },
 276         .p = { .min = 5, .max = 80 },
 277         .p1 = { .min = 1, .max = 8 },
 278         .p2 = { .dot_limit = 200000,
 279                 .p2_slow = 10, .p2_fast = 5 },
 280 };
 281
 282 static const intel_limit_t intel_limits_pineview_lvds = {
 283         .dot = { .min = 20000, .max = 400000 },
 284         .vco = { .min = 1700000, .max = 3500000 },
 285         .n = { .min = 3, .max = 6 },
 286         .m = { .min = 2, .max = 256 },
 287         .m1 = { .min = 0, .max = 0 },
 288         .m2 = { .min = 0, .max = 254 },
 289         .p = { .min = 7, .max = 112 },
 290         .p1 = { .min = 1, .max = 8 },
 291         .p2 = { .dot_limit = 112000,
 292                 .p2_slow = 14, .p2_fast = 14 },
 293 };
 294
 295 /* Ironlake / Sandybridge
 296  *
 297  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 298  * the range value for them is (actual_value - 2).
 299  */
 300 static const intel_limit_t intel_limits_ironlake_dac = {
 301         .dot = { .min = 25000, .max = 350000 },
 302         .vco = { .min = 1760000, .max = 3510000 },
 303         .n = { .min = 1, .max = 5 },
 304         .m = { .min = 79, .max = 127 },
 305         .m1 = { .min = 12, .max = 22 },
 306         .m2 = { .min = 5, .max = 9 },
 307         .p = { .min = 5, .max = 80 },
 308         .p1 = { .min = 1, .max = 8 },
 309         .p2 = { .dot_limit = 225000,
 310                 .p2_slow = 10, .p2_fast = 5 },
 311 };
 312
 313 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 314         .dot = { .min = 25000, .max = 350000 },
 315         .vco = { .min = 1760000, .max = 3510000 },
 316         .n = { .min = 1, .max = 3 },
 317         .m = { .min = 79, .max = 118 },
 318         .m1 = { .min = 12, .max = 22 },
 319         .m2 = { .min = 5, .max = 9 },
 320         .p = { .min = 28, .max = 112 },
 321         .p1 = { .min = 2, .max = 8 },
 322         .p2 = { .dot_limit = 225000,
 323                 .p2_slow = 14, .p2_fast = 14 },
 324 };
 325
 326 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 327         .dot = { .min = 25000, .max = 350000 },
 328         .vco = { .min = 1760000, .max = 3510000 },
 329         .n = { .min = 1, .max = 3 },
 330         .m = { .min = 79, .max = 127 },
 331         .m1 = { .min = 12, .max = 22 },
 332         .m2 = { .min = 5, .max = 9 },
 333         .p = { .min = 14, .max = 56 },
 334         .p1 = { .min = 2, .max = 8 },
 335         .p2 = { .dot_limit = 225000,
 336                 .p2_slow = 7, .p2_fast = 7 },
 337 };
 338
 339 /* LVDS 100mhz refclk limits. */
 340 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 341         .dot = { .min = 25000, .max = 350000 },
 342         .vco = { .min = 1760000, .max = 3510000 },
 343         .n = { .min = 1, .max = 2 },
 344         .m = { .min = 79, .max = 126 },
 345         .m1 = { .min = 12, .max = 22 },
 346         .m2 = { .min = 5, .max = 9 },
 347         .p = { .min = 28, .max = 112 },
 348         .p1 = { .min = 2, .max = 8 },
 349         .p2 = { .dot_limit = 225000,
 350                 .p2_slow = 14, .p2_fast = 14 },
 351 };
 352
 353 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 354         .dot = { .min = 25000, .max = 350000 },
 355         .vco = { .min = 1760000, .max = 3510000 },
 356         .n = { .min = 1, .max = 3 },
 357         .m = { .min = 79, .max = 126 },
 358         .m1 = { .min = 12, .max = 22 },
 359         .m2 = { .min = 5, .max = 9 },
 360         .p = { .min = 14, .max = 42 },
 361         .p1 = { .min = 2, .max = 6 },
 362         .p2 = { .dot_limit = 225000,
 363                 .p2_slow = 7, .p2_fast = 7 },
 364 };
 365
 366 static const intel_limit_t intel_limits_vlv = {
 367          /*
 368           * These are the data rate limits (measured in fast clocks)
 369           * since those are the strictest limits we have. The fast
 370           * clock and actual rate limits are more relaxed, so checking
 371           * them would make no difference.
 372           */
 373         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 374         .vco = { .min = 4000000, .max = 6000000 },
 375         .n = { .min = 1, .max = 7 },
 376         .m1 = { .min = 2, .max = 3 },
 377         .m2 = { .min = 11, .max = 156 },
 378         .p1 = { .min = 2, .max = 3 },
 379         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 380 };
 381
 382 static const intel_limit_t intel_limits_chv = {
 383         /*
 384          * These are the data rate limits (measured in fast clocks)
 385          * since those are the strictest limits we have.  The fast
 386          * clock and actual rate limits are more relaxed, so checking
 387          * them would make no difference.
 388          */
 389         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 390         .vco = { .min = 4860000, .max = 6700000 },
 391         .n = { .min = 1, .max = 1 },
 392         .m1 = { .min = 2, .max = 2 },
 393         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 394         .p1 = { .min = 2, .max = 4 },
 395         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 396 };
 397
 398 static void vlv_clock(int refclk, intel_clock_t *clock)
 399 {
 400         clock->m = clock->m1 * clock->m2;
 401         clock->p = clock->p1 * clock->p2;
 402         if (WARN_ON(clock->n == 0 || clock->p == 0))
 403                 return;
 404         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 405         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 406 }
 407
 408 /**
 409  * Returns whether any output on the specified pipe is of the specified type
 410  */
 411 bool intel_pipe_has_type(struct intel_crtc *crtc, int type)
 412 {
 413         struct drm_device *dev = crtc->base.dev;
 414         struct intel_encoder *encoder;
 415
 416         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 417                 if (encoder->type == type)
 418                         return true;
 419
 420         return false;
 421 }
 422
 423 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
 424                                                 int refclk)
 425 {
 426         struct drm_device *dev = crtc->base.dev;
 427         const intel_limit_t *limit;
 428
 429         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 430                 if (intel_is_dual_link_lvds(dev)) {
 431                         if (refclk == 100000)
 432                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 433                         else
 434                                 limit = &intel_limits_ironlake_dual_lvds;
 435                 } else {
 436                         if (refclk == 100000)
 437                                 limit = &intel_limits_ironlake_single_lvds_100m;
 438                         else
 439                                 limit = &intel_limits_ironlake_single_lvds;
 440                 }
 441         } else
 442                 limit = &intel_limits_ironlake_dac;
 443
 444         return limit;
 445 }
 446
 447 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
 448 {
 449         struct drm_device *dev = crtc->base.dev;
 450         const intel_limit_t *limit;
 451
 452         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 453                 if (intel_is_dual_link_lvds(dev))
 454                         limit = &intel_limits_g4x_dual_channel_lvds;
 455                 else
 456                         limit = &intel_limits_g4x_single_channel_lvds;
 457         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 458                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 459                 limit = &intel_limits_g4x_hdmi;
 460         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 461                 limit = &intel_limits_g4x_sdvo;
 462         } else /* The option is for other outputs */
 463                 limit = &intel_limits_i9xx_sdvo;
 464
 465         return limit;
 466 }
 467
 468 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
 469 {
 470         struct drm_device *dev = crtc->base.dev;
 471         const intel_limit_t *limit;
 472
 473         if (HAS_PCH_SPLIT(dev))
 474                 limit = intel_ironlake_limit(crtc, refclk);
 475         else if (IS_G4X(dev)) {
 476                 limit = intel_g4x_limit(crtc);
 477         } else if (IS_PINEVIEW(dev)) {
 478                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 479                         limit = &intel_limits_pineview_lvds;
 480                 else
 481                         limit = &intel_limits_pineview_sdvo;
 482         } else if (IS_CHERRYVIEW(dev)) {
 483                 limit = &intel_limits_chv;
 484         } else if (IS_VALLEYVIEW(dev)) {
 485                 limit = &intel_limits_vlv;
 486         } else if (!IS_GEN2(dev)) {
 487                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 488                         limit = &intel_limits_i9xx_lvds;
 489                 else
 490                         limit = &intel_limits_i9xx_sdvo;
 491         } else {
 492                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 493                         limit = &intel_limits_i8xx_lvds;
 494                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 495                         limit = &intel_limits_i8xx_dvo;
 496                 else
 497                         limit = &intel_limits_i8xx_dac;
 498         }
 499         return limit;
 500 }
 501
 502 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 503 static void pineview_clock(int refclk, intel_clock_t *clock)
 504 {
 505         clock->m = clock->m2 + 2;
 506         clock->p = clock->p1 * clock->p2;
 507         if (WARN_ON(clock->n == 0 || clock->p == 0))
 508                 return;
 509         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 510         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 511 }
 512
 513 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 514 {
 515         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 516 }
 517
 518 static void i9xx_clock(int refclk, intel_clock_t *clock)
 519 {
 520         clock->m = i9xx_dpll_compute_m(clock);
 521         clock->p = clock->p1 * clock->p2;
 522         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 523                 return;
 524         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 525         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 526 }
 527
 528 static void chv_clock(int refclk, intel_clock_t *clock)
 529 {
 530         clock->m = clock->m1 * clock->m2;
 531         clock->p = clock->p1 * clock->p2;
 532         if (WARN_ON(clock->n == 0 || clock->p == 0))
 533                 return;
 534         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 535                         clock->n << 22);
 536         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 537 }
 538
 539 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 540 /**
 541  * Returns whether the given set of divisors are valid for a given refclk with
 542  * the given connectors.
 543  */
 544
 545 static bool intel_PLL_is_valid(struct drm_device *dev,
 546                                const intel_limit_t *limit,
 547                                const intel_clock_t *clock)
 548 {
 549         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 550                 INTELPllInvalid("n out of range\n");
 551         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 552                 INTELPllInvalid("p1 out of range\n");
 553         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 554                 INTELPllInvalid("m2 out of range\n");
 555         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 556                 INTELPllInvalid("m1 out of range\n");
 557
 558         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 559                 if (clock->m1 <= clock->m2)
 560                         INTELPllInvalid("m1 <= m2\n");
 561
 562         if (!IS_VALLEYVIEW(dev)) {
 563                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 564                         INTELPllInvalid("p out of range\n");
 565                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 566                         INTELPllInvalid("m out of range\n");
 567         }
 568
 569         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 570                 INTELPllInvalid("vco out of range\n");
 571         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 572          * connector, etc., rather than just a single range.
 573          */
 574         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 575                 INTELPllInvalid("dot out of range\n");
 576
 577         return true;
 578 }
 579
 580 static bool
 581 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 582                     int target, int refclk, intel_clock_t *match_clock,
 583                     intel_clock_t *best_clock)
 584 {
 585         struct drm_device *dev = crtc->base.dev;
 586         intel_clock_t clock;
 587         int err = target;
 588
 589         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 590                 /*
 591                  * For LVDS just rely on its current settings for dual-channel.
 592                  * We haven't figured out how to reliably set up different
 593                  * single/dual channel state, if we even can.
 594                  */
 595                 if (intel_is_dual_link_lvds(dev))
 596                         clock.p2 = limit->p2.p2_fast;
 597                 else
 598                         clock.p2 = limit->p2.p2_slow;
 599         } else {
 600                 if (target < limit->p2.dot_limit)
 601                         clock.p2 = limit->p2.p2_slow;
 602                 else
 603                         clock.p2 = limit->p2.p2_fast;
 604         }
 605
 606         memset(best_clock, 0, sizeof(*best_clock));
 607
 608         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 609              clock.m1++) {
 610                 for (clock.m2 = limit->m2.min;
 611                      clock.m2 <= limit->m2.max; clock.m2++) {
 612                         if (clock.m2 >= clock.m1)
 613                                 break;
 614                         for (clock.n = limit->n.min;
 615                              clock.n <= limit->n.max; clock.n++) {
 616                                 for (clock.p1 = limit->p1.min;
 617                                         clock.p1 <= limit->p1.max; clock.p1++) {
 618                                         int this_err;
 619
 620                                         i9xx_clock(refclk, &clock);
 621                                         if (!intel_PLL_is_valid(dev, limit,
 622                                                                 &clock))
 623                                                 continue;
 624                                         if (match_clock &&
 625                                             clock.p != match_clock->p)
 626                                                 continue;
 627
 628                                         this_err = abs(clock.dot - target);
 629                                         if (this_err < err) {
 630                                                 *best_clock = clock;
 631                                                 err = this_err;
 632                                         }
 633                                 }
 634                         }
 635                 }
 636         }
 637
 638         return (err != target);
 639 }
 640
 641 static bool
 642 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 643                    int target, int refclk, intel_clock_t *match_clock,
 644                    intel_clock_t *best_clock)
 645 {
 646         struct drm_device *dev = crtc->base.dev;
 647         intel_clock_t clock;
 648         int err = target;
 649
 650         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 651                 /*
 652                  * For LVDS just rely on its current settings for dual-channel.
 653                  * We haven't figured out how to reliably set up different
 654                  * single/dual channel state, if we even can.
 655                  */
 656                 if (intel_is_dual_link_lvds(dev))
 657                         clock.p2 = limit->p2.p2_fast;
 658                 else
 659                         clock.p2 = limit->p2.p2_slow;
 660         } else {
 661                 if (target < limit->p2.dot_limit)
 662                         clock.p2 = limit->p2.p2_slow;
 663                 else
 664                         clock.p2 = limit->p2.p2_fast;
 665         }
 666
 667         memset(best_clock, 0, sizeof(*best_clock));
 668
 669         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 670              clock.m1++) {
 671                 for (clock.m2 = limit->m2.min;
 672                      clock.m2 <= limit->m2.max; clock.m2++) {
 673                         for (clock.n = limit->n.min;
 674                              clock.n <= limit->n.max; clock.n++) {
 675                                 for (clock.p1 = limit->p1.min;
 676                                         clock.p1 <= limit->p1.max; clock.p1++) {
 677                                         int this_err;
 678
 679                                         pineview_clock(refclk, &clock);
 680                                         if (!intel_PLL_is_valid(dev, limit,
 681                                                                 &clock))
 682                                                 continue;
 683                                         if (match_clock &&
 684                                             clock.p != match_clock->p)
 685                                                 continue;
 686
 687                                         this_err = abs(clock.dot - target);
 688                                         if (this_err < err) {
 689                                                 *best_clock = clock;
 690                                                 err = this_err;
 691                                         }
 692                                 }
 693                         }
 694                 }
 695         }
 696
 697         return (err != target);
 698 }
 699
 700 static bool
 701 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 702                    int target, int refclk, intel_clock_t *match_clock,
 703                    intel_clock_t *best_clock)
 704 {
 705         struct drm_device *dev = crtc->base.dev;
 706         intel_clock_t clock;
 707         int max_n;
 708         bool found;
 709         /* approximately equals target * 0.00585 */
 710         int err_most = (target >> 8) + (target >> 9);
 711         found = false;
 712
 713         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 714                 if (intel_is_dual_link_lvds(dev))
 715                         clock.p2 = limit->p2.p2_fast;
 716                 else
 717                         clock.p2 = limit->p2.p2_slow;
 718         } else {
 719                 if (target < limit->p2.dot_limit)
 720                         clock.p2 = limit->p2.p2_slow;
 721                 else
 722                         clock.p2 = limit->p2.p2_fast;
 723         }
 724
 725         memset(best_clock, 0, sizeof(*best_clock));
 726         max_n = limit->n.max;
 727         /* based on hardware requirement, prefer smaller n to precision */
 728         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 729                 /* based on hardware requirement, prefere larger m1,m2 */
 730                 for (clock.m1 = limit->m1.max;
 731                      clock.m1 >= limit->m1.min; clock.m1--) {
 732                         for (clock.m2 = limit->m2.max;
 733                              clock.m2 >= limit->m2.min; clock.m2--) {
 734                                 for (clock.p1 = limit->p1.max;
 735                                      clock.p1 >= limit->p1.min; clock.p1--) {
 736                                         int this_err;
 737
 738                                         i9xx_clock(refclk, &clock);
 739                                         if (!intel_PLL_is_valid(dev, limit,
 740                                                                 &clock))
 741                                                 continue;
 742
 743                                         this_err = abs(clock.dot - target);
 744                                         if (this_err < err_most) {
 745                                                 *best_clock = clock;
 746                                                 err_most = this_err;
 747                                                 max_n = clock.n;
 748                                                 found = true;
 749                                         }
 750                                 }
 751                         }
 752                 }
 753         }
 754         return found;
 755 }
 756
 757 static bool
 758 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 759                    int target, int refclk, intel_clock_t *match_clock,
 760                    intel_clock_t *best_clock)
 761 {
 762         struct drm_device *dev = crtc->base.dev;
 763         intel_clock_t clock;
 764         unsigned int bestppm = 1000000;
 765         /* min update 19.2 MHz */
 766         int max_n = min(limit->n.max, refclk / 19200);
 767         bool found = false;
 768
 769         target *= 5; /* fast clock */
 770
 771         memset(best_clock, 0, sizeof(*best_clock));
 772
 773         /* based on hardware requirement, prefer smaller n to precision */
 774         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 775                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 776                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 777                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 778                                 clock.p = clock.p1 * clock.p2;
 779                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 780                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 781                                         unsigned int ppm, diff;
 782
 783                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 784                                                                      refclk * clock.m1);
 785
 786                                         vlv_clock(refclk, &clock);
 787
 788                                         if (!intel_PLL_is_valid(dev, limit,
 789                                                                 &clock))
 790                                                 continue;
 791
 792                                         diff = abs(clock.dot - target);
 793                                         ppm = div_u64(1000000ULL * diff, target);
 794
 795                                         if (ppm < 100 && clock.p > best_clock->p) {
 796                                                 bestppm = 0;
 797                                                 *best_clock = clock;
 798                                                 found = true;
 799                                         }
 800
 801                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 802                                                 bestppm = ppm;
 803                                                 *best_clock = clock;
 804                                                 found = true;
 805                                         }
 806                                 }
 807                         }
 808                 }
 809         }
 810
 811         return found;
 812 }
 813
 814 static bool
 815 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 816                    int target, int refclk, intel_clock_t *match_clock,
 817                    intel_clock_t *best_clock)
 818 {
 819         struct drm_device *dev = crtc->base.dev;
 820         intel_clock_t clock;
 821         uint64_t m2;
 822         int found = false;
 823
 824         memset(best_clock, 0, sizeof(*best_clock));
 825
 826         /*
 827          * Based on hardware doc, the n always set to 1, and m1 always
 828          * set to 2.  If requires to support 200Mhz refclk, we need to
 829          * revisit this because n may not 1 anymore.
 830          */
 831         clock.n = 1, clock.m1 = 2;
 832         target *= 5;    /* fast clock */
 833
 834         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 835                 for (clock.p2 = limit->p2.p2_fast;
 836                                 clock.p2 >= limit->p2.p2_slow;
 837                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 838
 839                         clock.p = clock.p1 * clock.p2;
 840
 841                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 842                                         clock.n) << 22, refclk * clock.m1);
 843
 844                         if (m2 > INT_MAX/clock.m1)
 845                                 continue;
 846
 847                         clock.m2 = m2;
 848
 849                         chv_clock(refclk, &clock);
 850
 851                         if (!intel_PLL_is_valid(dev, limit, &clock))
 852                                 continue;
 853
 854                         /* based on hardware requirement, prefer bigger p
 855                          */
 856                         if (clock.p > best_clock->p) {
 857                                 *best_clock = clock;
 858                                 found = true;
 859                         }
 860                 }
 861         }
 862
 863         return found;
 864 }
 865
 866 bool intel_crtc_active(struct drm_crtc *crtc)
 867 {
 868         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 869
 870         /* Be paranoid as we can arrive here with only partial
 871          * state retrieved from the hardware during setup.
 872          *
 873          * We can ditch the adjusted_mode.crtc_clock check as soon
 874          * as Haswell has gained clock readout/fastboot support.
 875          *
 876          * We can ditch the crtc->primary->fb check as soon as we can
 877          * properly reconstruct framebuffers.
 878          */
 879         return intel_crtc->active && crtc->primary->fb &&
 880                 intel_crtc->config.adjusted_mode.crtc_clock;
 881 }
 882
 883 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 884                                              enum pipe pipe)
 885 {
 886         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 887         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 888
 889         return intel_crtc->config.cpu_transcoder;
 890 }
 891
 892 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 893 {
 894         struct drm_i915_private *dev_priv = dev->dev_private;
 895         u32 reg = PIPEDSL(pipe);
 896         u32 line1, line2;
 897         u32 line_mask;
 898
 899         if (IS_GEN2(dev))
 900                 line_mask = DSL_LINEMASK_GEN2;
 901         else
 902                 line_mask = DSL_LINEMASK_GEN3;
 903
 904         line1 = I915_READ(reg) & line_mask;
 905         mdelay(5);
 906         line2 = I915_READ(reg) & line_mask;
 907
 908         return line1 == line2;
 909 }
 910
 911 /*
 912  * intel_wait_for_pipe_off - wait for pipe to turn off
 913  * @crtc: crtc whose pipe to wait for
 914  *
 915  * After disabling a pipe, we can't wait for vblank in the usual way,
 916  * spinning on the vblank interrupt status bit, since we won't actually
 917  * see an interrupt when the pipe is disabled.
 918  *
 919  * On Gen4 and above:
 920  *   wait for the pipe register state bit to turn off
 921  *
 922  * Otherwise:
 923  *   wait for the display line value to settle (it usually
 924  *   ends up stopping at the start of the next frame).
 925  *
 926  */
 927 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
 928 {
 929         struct drm_device *dev = crtc->base.dev;
 930         struct drm_i915_private *dev_priv = dev->dev_private;
 931         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
 932         enum pipe pipe = crtc->pipe;
 933
 934         if (INTEL_INFO(dev)->gen >= 4) {
 935                 int reg = PIPECONF(cpu_transcoder);
 936
 937                 /* Wait for the Pipe State to go off */
 938                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 939                              100))
 940                         WARN(1, "pipe_off wait timed out\n");
 941         } else {
 942                 /* Wait for the display line to settle */
 943                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 944                         WARN(1, "pipe_off wait timed out\n");
 945         }
 946 }
 947
 948 /*
 949  * ibx_digital_port_connected - is the specified port connected?
 950  * @dev_priv: i915 private structure
 951  * @port: the port to test
 952  *
 953  * Returns true if @port is connected, false otherwise.
 954  */
 955 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 956                                 struct intel_digital_port *port)
 957 {
 958         u32 bit;
 959
 960         if (HAS_PCH_IBX(dev_priv->dev)) {
 961                 switch (port->port) {
 962                 case PORT_B:
 963                         bit = SDE_PORTB_HOTPLUG;
 964                         break;
 965                 case PORT_C:
 966                         bit = SDE_PORTC_HOTPLUG;
 967                         break;
 968                 case PORT_D:
 969                         bit = SDE_PORTD_HOTPLUG;
 970                         break;
 971                 default:
 972                         return true;
 973                 }
 974         } else {
 975                 switch (port->port) {
 976                 case PORT_B:
 977                         bit = SDE_PORTB_HOTPLUG_CPT;
 978                         break;
 979                 case PORT_C:
 980                         bit = SDE_PORTC_HOTPLUG_CPT;
 981                         break;
 982                 case PORT_D:
 983                         bit = SDE_PORTD_HOTPLUG_CPT;
 984                         break;
 985                 default:
 986                         return true;
 987                 }
 988         }
 989
 990         return I915_READ(SDEISR) & bit;
 991 }
 992
 993 static const char *state_string(bool enabled)
 994 {
 995         return enabled ? "on" : "off";
 996 }
 997
 998 /* Only for pre-ILK configs */
 999 void assert_pll(struct drm_i915_private *dev_priv,
1000                 enum pipe pipe, bool state)
1001 {
1002         int reg;
1003         u32 val;
1004         bool cur_state;
1005
1006         reg = DPLL(pipe);
1007         val = I915_READ(reg);
1008         cur_state = !!(val & DPLL_VCO_ENABLE);
1009         WARN(cur_state != state,
1010              "PLL state assertion failure (expected %s, current %s)\n",
1011              state_string(state), state_string(cur_state));
1012 }
1013
1014 /* XXX: the dsi pll is shared between MIPI DSI ports */
1015 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1016 {
1017         u32 val;
1018         bool cur_state;
1019
1020         mutex_lock(&dev_priv->dpio_lock);
1021         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1022         mutex_unlock(&dev_priv->dpio_lock);
1023
1024         cur_state = val & DSI_PLL_VCO_EN;
1025         WARN(cur_state != state,
1026              "DSI PLL state assertion failure (expected %s, current %s)\n",
1027              state_string(state), state_string(cur_state));
1028 }
1029 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1030 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1031
1032 struct intel_shared_dpll *
1033 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1034 {
1035         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1036
1037         if (crtc->config.shared_dpll < 0)
1038                 return NULL;
1039
1040         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1041 }
1042
1043 /* For ILK+ */
1044 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1045                         struct intel_shared_dpll *pll,
1046                         bool state)
1047 {
1048         bool cur_state;
1049         struct intel_dpll_hw_state hw_state;
1050
1051         if (WARN (!pll,
1052                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1053                 return;
1054
1055         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1056         WARN(cur_state != state,
1057              "%s assertion failure (expected %s, current %s)\n",
1058              pll->name, state_string(state), state_string(cur_state));
1059 }
1060
1061 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1062                           enum pipe pipe, bool state)
1063 {
1064         int reg;
1065         u32 val;
1066         bool cur_state;
1067         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1068                                                                       pipe);
1069
1070         if (HAS_DDI(dev_priv->dev)) {
1071                 /* DDI does not have a specific FDI_TX register */
1072                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1073                 val = I915_READ(reg);
1074                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1075         } else {
1076                 reg = FDI_TX_CTL(pipe);
1077                 val = I915_READ(reg);
1078                 cur_state = !!(val & FDI_TX_ENABLE);
1079         }
1080         WARN(cur_state != state,
1081              "FDI TX state assertion failure (expected %s, current %s)\n",
1082              state_string(state), state_string(cur_state));
1083 }
1084 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1085 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1086
1087 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1088                           enum pipe pipe, bool state)
1089 {
1090         int reg;
1091         u32 val;
1092         bool cur_state;
1093
1094         reg = FDI_RX_CTL(pipe);
1095         val = I915_READ(reg);
1096         cur_state = !!(val & FDI_RX_ENABLE);
1097         WARN(cur_state != state,
1098              "FDI RX state assertion failure (expected %s, current %s)\n",
1099              state_string(state), state_string(cur_state));
1100 }
1101 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1102 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1103
1104 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1105                                       enum pipe pipe)
1106 {
1107         int reg;
1108         u32 val;
1109
1110         /* ILK FDI PLL is always enabled */
1111         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1112                 return;
1113
1114         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1115         if (HAS_DDI(dev_priv->dev))
1116                 return;
1117
1118         reg = FDI_TX_CTL(pipe);
1119         val = I915_READ(reg);
1120         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1121 }
1122
1123 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1124                        enum pipe pipe, bool state)
1125 {
1126         int reg;
1127         u32 val;
1128         bool cur_state;
1129
1130         reg = FDI_RX_CTL(pipe);
1131         val = I915_READ(reg);
1132         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1133         WARN(cur_state != state,
1134              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1135              state_string(state), state_string(cur_state));
1136 }
1137
1138 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1139                            enum pipe pipe)
1140 {
1141         struct drm_device *dev = dev_priv->dev;
1142         int pp_reg;
1143         u32 val;
1144         enum pipe panel_pipe = PIPE_A;
1145         bool locked = true;
1146
1147         if (WARN_ON(HAS_DDI(dev)))
1148                 return;
1149
1150         if (HAS_PCH_SPLIT(dev)) {
1151                 u32 port_sel;
1152
1153                 pp_reg = PCH_PP_CONTROL;
1154                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1155
1156                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1157                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1158                         panel_pipe = PIPE_B;
1159                 /* XXX: else fix for eDP */
1160         } else if (IS_VALLEYVIEW(dev)) {
1161                 /* presumably write lock depends on pipe, not port select */
1162                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1163                 panel_pipe = pipe;
1164         } else {
1165                 pp_reg = PP_CONTROL;
1166                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1167                         panel_pipe = PIPE_B;
1168         }
1169
1170         val = I915_READ(pp_reg);
1171         if (!(val & PANEL_POWER_ON) ||
1172             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1173                 locked = false;
1174
1175         WARN(panel_pipe == pipe && locked,
1176              "panel assertion failure, pipe %c regs locked\n",
1177              pipe_name(pipe));
1178 }
1179
1180 static void assert_cursor(struct drm_i915_private *dev_priv,
1181                           enum pipe pipe, bool state)
1182 {
1183         struct drm_device *dev = dev_priv->dev;
1184         bool cur_state;
1185
1186         if (IS_845G(dev) || IS_I865G(dev))
1187                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1188         else
1189                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1190
1191         WARN(cur_state != state,
1192              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1193              pipe_name(pipe), state_string(state), state_string(cur_state));
1194 }
1195 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1196 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1197
1198 void assert_pipe(struct drm_i915_private *dev_priv,
1199                  enum pipe pipe, bool state)
1200 {
1201         int reg;
1202         u32 val;
1203         bool cur_state;
1204         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1205                                                                       pipe);
1206
1207         /* if we need the pipe quirk it must be always on */
1208         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1209             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1210                 state = true;
1211
1212         if (!intel_display_power_is_enabled(dev_priv,
1213                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1214                 cur_state = false;
1215         } else {
1216                 reg = PIPECONF(cpu_transcoder);
1217                 val = I915_READ(reg);
1218                 cur_state = !!(val & PIPECONF_ENABLE);
1219         }
1220
1221         WARN(cur_state != state,
1222              "pipe %c assertion failure (expected %s, current %s)\n",
1223              pipe_name(pipe), state_string(state), state_string(cur_state));
1224 }
1225
1226 static void assert_plane(struct drm_i915_private *dev_priv,
1227                          enum plane plane, bool state)
1228 {
1229         int reg;
1230         u32 val;
1231         bool cur_state;
1232
1233         reg = DSPCNTR(plane);
1234         val = I915_READ(reg);
1235         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1236         WARN(cur_state != state,
1237              "plane %c assertion failure (expected %s, current %s)\n",
1238              plane_name(plane), state_string(state), state_string(cur_state));
1239 }
1240
1241 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1242 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1243
1244 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1245                                    enum pipe pipe)
1246 {
1247         struct drm_device *dev = dev_priv->dev;
1248         int reg, i;
1249         u32 val;
1250         int cur_pipe;
1251
1252         /* Primary planes are fixed to pipes on gen4+ */
1253         if (INTEL_INFO(dev)->gen >= 4) {
1254                 reg = DSPCNTR(pipe);
1255                 val = I915_READ(reg);
1256                 WARN(val & DISPLAY_PLANE_ENABLE,
1257                      "plane %c assertion failure, should be disabled but not\n",
1258                      plane_name(pipe));
1259                 return;
1260         }
1261
1262         /* Need to check both planes against the pipe */
1263         for_each_pipe(dev_priv, i) {
1264                 reg = DSPCNTR(i);
1265                 val = I915_READ(reg);
1266                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1267                         DISPPLANE_SEL_PIPE_SHIFT;
1268                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1269                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1270                      plane_name(i), pipe_name(pipe));
1271         }
1272 }
1273
1274 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1275                                     enum pipe pipe)
1276 {
1277         struct drm_device *dev = dev_priv->dev;
1278         int reg, sprite;
1279         u32 val;
1280
1281         if (INTEL_INFO(dev)->gen >= 9) {
1282                 for_each_sprite(pipe, sprite) {
1283                         val = I915_READ(PLANE_CTL(pipe, sprite));
1284                         WARN(val & PLANE_CTL_ENABLE,
1285                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1286                              sprite, pipe_name(pipe));
1287                 }
1288         } else if (IS_VALLEYVIEW(dev)) {
1289                 for_each_sprite(pipe, sprite) {
1290                         reg = SPCNTR(pipe, sprite);
1291                         val = I915_READ(reg);
1292                         WARN(val & SP_ENABLE,
1293                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1294                              sprite_name(pipe, sprite), pipe_name(pipe));
1295                 }
1296         } else if (INTEL_INFO(dev)->gen >= 7) {
1297                 reg = SPRCTL(pipe);
1298                 val = I915_READ(reg);
1299                 WARN(val & SPRITE_ENABLE,
1300                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1301                      plane_name(pipe), pipe_name(pipe));
1302         } else if (INTEL_INFO(dev)->gen >= 5) {
1303                 reg = DVSCNTR(pipe);
1304                 val = I915_READ(reg);
1305                 WARN(val & DVS_ENABLE,
1306                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1307                      plane_name(pipe), pipe_name(pipe));
1308         }
1309 }
1310
1311 static void assert_vblank_disabled(struct drm_crtc *crtc)
1312 {
1313         if (WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1314                 drm_crtc_vblank_put(crtc);
1315 }
1316
1317 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1318 {
1319         u32 val;
1320         bool enabled;
1321
1322         WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1323
1324         val = I915_READ(PCH_DREF_CONTROL);
1325         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1326                             DREF_SUPERSPREAD_SOURCE_MASK));
1327         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1328 }
1329
1330 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1331                                            enum pipe pipe)
1332 {
1333         int reg;
1334         u32 val;
1335         bool enabled;
1336
1337         reg = PCH_TRANSCONF(pipe);
1338         val = I915_READ(reg);
1339         enabled = !!(val & TRANS_ENABLE);
1340         WARN(enabled,
1341              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1342              pipe_name(pipe));
1343 }
1344
1345 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1346                             enum pipe pipe, u32 port_sel, u32 val)
1347 {
1348         if ((val & DP_PORT_EN) == 0)
1349                 return false;
1350
1351         if (HAS_PCH_CPT(dev_priv->dev)) {
1352                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1353                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1354                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1355                         return false;
1356         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1357                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1358                         return false;
1359         } else {
1360                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1361                         return false;
1362         }
1363         return true;
1364 }
1365
1366 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1367                               enum pipe pipe, u32 val)
1368 {
1369         if ((val & SDVO_ENABLE) == 0)
1370                 return false;
1371
1372         if (HAS_PCH_CPT(dev_priv->dev)) {
1373                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1374                         return false;
1375         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1376                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1377                         return false;
1378         } else {
1379                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1380                         return false;
1381         }
1382         return true;
1383 }
1384
1385 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1386                               enum pipe pipe, u32 val)
1387 {
1388         if ((val & LVDS_PORT_EN) == 0)
1389                 return false;
1390
1391         if (HAS_PCH_CPT(dev_priv->dev)) {
1392                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1393                         return false;
1394         } else {
1395                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1396                         return false;
1397         }
1398         return true;
1399 }
1400
1401 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1402                               enum pipe pipe, u32 val)
1403 {
1404         if ((val & ADPA_DAC_ENABLE) == 0)
1405                 return false;
1406         if (HAS_PCH_CPT(dev_priv->dev)) {
1407                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1408                         return false;
1409         } else {
1410                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1411                         return false;
1412         }
1413         return true;
1414 }
1415
1416 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1417                                    enum pipe pipe, int reg, u32 port_sel)
1418 {
1419         u32 val = I915_READ(reg);
1420         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1421              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1422              reg, pipe_name(pipe));
1423
1424         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1425              && (val & DP_PIPEB_SELECT),
1426              "IBX PCH dp port still using transcoder B\n");
1427 }
1428
1429 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1430                                      enum pipe pipe, int reg)
1431 {
1432         u32 val = I915_READ(reg);
1433         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1434              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1435              reg, pipe_name(pipe));
1436
1437         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1438              && (val & SDVO_PIPE_B_SELECT),
1439              "IBX PCH hdmi port still using transcoder B\n");
1440 }
1441
1442 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1443                                       enum pipe pipe)
1444 {
1445         int reg;
1446         u32 val;
1447
1448         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1449         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1450         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1451
1452         reg = PCH_ADPA;
1453         val = I915_READ(reg);
1454         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1455              "PCH VGA enabled on transcoder %c, should be disabled\n",
1456              pipe_name(pipe));
1457
1458         reg = PCH_LVDS;
1459         val = I915_READ(reg);
1460         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1461              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1462              pipe_name(pipe));
1463
1464         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1465         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1466         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1467 }
1468
1469 static void intel_init_dpio(struct drm_device *dev)
1470 {
1471         struct drm_i915_private *dev_priv = dev->dev_private;
1472
1473         if (!IS_VALLEYVIEW(dev))
1474                 return;
1475
1476         /*
1477          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1478          * CHV x1 PHY (DP/HDMI D)
1479          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1480          */
1481         if (IS_CHERRYVIEW(dev)) {
1482                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1483                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1484         } else {
1485                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1486         }
1487 }
1488
1489 static void vlv_enable_pll(struct intel_crtc *crtc,
1490                            const struct intel_crtc_config *pipe_config)
1491 {
1492         struct drm_device *dev = crtc->base.dev;
1493         struct drm_i915_private *dev_priv = dev->dev_private;
1494         int reg = DPLL(crtc->pipe);
1495         u32 dpll = pipe_config->dpll_hw_state.dpll;
1496
1497         assert_pipe_disabled(dev_priv, crtc->pipe);
1498
1499         /* No really, not for ILK+ */
1500         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1501
1502         /* PLL is protected by panel, make sure we can write it */
1503         if (IS_MOBILE(dev_priv->dev))
1504                 assert_panel_unlocked(dev_priv, crtc->pipe);
1505
1506         I915_WRITE(reg, dpll);
1507         POSTING_READ(reg);
1508         udelay(150);
1509
1510         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1511                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1512
1513         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1514         POSTING_READ(DPLL_MD(crtc->pipe));
1515
1516         /* We do this three times for luck */
1517         I915_WRITE(reg, dpll);
1518         POSTING_READ(reg);
1519         udelay(150); /* wait for warmup */
1520         I915_WRITE(reg, dpll);
1521         POSTING_READ(reg);
1522         udelay(150); /* wait for warmup */
1523         I915_WRITE(reg, dpll);
1524         POSTING_READ(reg);
1525         udelay(150); /* wait for warmup */
1526 }
1527
1528 static void chv_enable_pll(struct intel_crtc *crtc,
1529                            const struct intel_crtc_config *pipe_config)
1530 {
1531         struct drm_device *dev = crtc->base.dev;
1532         struct drm_i915_private *dev_priv = dev->dev_private;
1533         int pipe = crtc->pipe;
1534         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1535         u32 tmp;
1536
1537         assert_pipe_disabled(dev_priv, crtc->pipe);
1538
1539         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1540
1541         mutex_lock(&dev_priv->dpio_lock);
1542
1543         /* Enable back the 10bit clock to display controller */
1544         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1545         tmp |= DPIO_DCLKP_EN;
1546         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1547
1548         /*
1549          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1550          */
1551         udelay(1);
1552
1553         /* Enable PLL */
1554         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1555
1556         /* Check PLL is locked */
1557         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1558                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1559
1560         /* not sure when this should be written */
1561         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1562         POSTING_READ(DPLL_MD(pipe));
1563
1564         mutex_unlock(&dev_priv->dpio_lock);
1565 }
1566
1567 static int intel_num_dvo_pipes(struct drm_device *dev)
1568 {
1569         struct intel_crtc *crtc;
1570         int count = 0;
1571
1572         for_each_intel_crtc(dev, crtc)
1573                 count += crtc->active &&
1574                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1575
1576         return count;
1577 }
1578
1579 static void i9xx_enable_pll(struct intel_crtc *crtc)
1580 {
1581         struct drm_device *dev = crtc->base.dev;
1582         struct drm_i915_private *dev_priv = dev->dev_private;
1583         int reg = DPLL(crtc->pipe);
1584         u32 dpll = crtc->config.dpll_hw_state.dpll;
1585
1586         assert_pipe_disabled(dev_priv, crtc->pipe);
1587
1588         /* No really, not for ILK+ */
1589         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1590
1591         /* PLL is protected by panel, make sure we can write it */
1592         if (IS_MOBILE(dev) && !IS_I830(dev))
1593                 assert_panel_unlocked(dev_priv, crtc->pipe);
1594
1595         /* Enable DVO 2x clock on both PLLs if necessary */
1596         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1597                 /*
1598                  * It appears to be important that we don't enable this
1599                  * for the current pipe before otherwise configuring the
1600                  * PLL. No idea how this should be handled if multiple
1601                  * DVO outputs are enabled simultaneosly.
1602                  */
1603                 dpll |= DPLL_DVO_2X_MODE;
1604                 I915_WRITE(DPLL(!crtc->pipe),
1605                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1606         }
1607
1608         /* Wait for the clocks to stabilize. */
1609         POSTING_READ(reg);
1610         udelay(150);
1611
1612         if (INTEL_INFO(dev)->gen >= 4) {
1613                 I915_WRITE(DPLL_MD(crtc->pipe),
1614                            crtc->config.dpll_hw_state.dpll_md);
1615         } else {
1616                 /* The pixel multiplier can only be updated once the
1617                  * DPLL is enabled and the clocks are stable.
1618                  *
1619                  * So write it again.
1620                  */
1621                 I915_WRITE(reg, dpll);
1622         }
1623
1624         /* We do this three times for luck */
1625         I915_WRITE(reg, dpll);
1626         POSTING_READ(reg);
1627         udelay(150); /* wait for warmup */
1628         I915_WRITE(reg, dpll);
1629         POSTING_READ(reg);
1630         udelay(150); /* wait for warmup */
1631         I915_WRITE(reg, dpll);
1632         POSTING_READ(reg);
1633         udelay(150); /* wait for warmup */
1634 }
1635
1636 /**
1637  * i9xx_disable_pll - disable a PLL
1638  * @dev_priv: i915 private structure
1639  * @pipe: pipe PLL to disable
1640  *
1641  * Disable the PLL for @pipe, making sure the pipe is off first.
1642  *
1643  * Note!  This is for pre-ILK only.
1644  */
1645 static void i9xx_disable_pll(struct intel_crtc *crtc)
1646 {
1647         struct drm_device *dev = crtc->base.dev;
1648         struct drm_i915_private *dev_priv = dev->dev_private;
1649         enum pipe pipe = crtc->pipe;
1650
1651         /* Disable DVO 2x clock on both PLLs if necessary */
1652         if (IS_I830(dev) &&
1653             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1654             intel_num_dvo_pipes(dev) == 1) {
1655                 I915_WRITE(DPLL(PIPE_B),
1656                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1657                 I915_WRITE(DPLL(PIPE_A),
1658                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1659         }
1660
1661         /* Don't disable pipe or pipe PLLs if needed */
1662         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1663             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1664                 return;
1665
1666         /* Make sure the pipe isn't still relying on us */
1667         assert_pipe_disabled(dev_priv, pipe);
1668
1669         I915_WRITE(DPLL(pipe), 0);
1670         POSTING_READ(DPLL(pipe));
1671 }
1672
1673 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1674 {
1675         u32 val = 0;
1676
1677         /* Make sure the pipe isn't still relying on us */
1678         assert_pipe_disabled(dev_priv, pipe);
1679
1680         /*
1681          * Leave integrated clock source and reference clock enabled for pipe B.
1682          * The latter is needed for VGA hotplug / manual detection.
1683          */
1684         if (pipe == PIPE_B)
1685                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1686         I915_WRITE(DPLL(pipe), val);
1687         POSTING_READ(DPLL(pipe));
1688
1689 }
1690
1691 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1692 {
1693         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1694         u32 val;
1695
1696         /* Make sure the pipe isn't still relying on us */
1697         assert_pipe_disabled(dev_priv, pipe);
1698
1699         /* Set PLL en = 0 */
1700         val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1701         if (pipe != PIPE_A)
1702                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1703         I915_WRITE(DPLL(pipe), val);
1704         POSTING_READ(DPLL(pipe));
1705
1706         mutex_lock(&dev_priv->dpio_lock);
1707
1708         /* Disable 10bit clock to display controller */
1709         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1710         val &= ~DPIO_DCLKP_EN;
1711         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1712
1713         /* disable left/right clock distribution */
1714         if (pipe != PIPE_B) {
1715                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1716                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1717                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1718         } else {
1719                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1720                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1721                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1722         }
1723
1724         mutex_unlock(&dev_priv->dpio_lock);
1725 }
1726
1727 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1728                 struct intel_digital_port *dport)
1729 {
1730         u32 port_mask;
1731         int dpll_reg;
1732
1733         switch (dport->port) {
1734         case PORT_B:
1735                 port_mask = DPLL_PORTB_READY_MASK;
1736                 dpll_reg = DPLL(0);
1737                 break;
1738         case PORT_C:
1739                 port_mask = DPLL_PORTC_READY_MASK;
1740                 dpll_reg = DPLL(0);
1741                 break;
1742         case PORT_D:
1743                 port_mask = DPLL_PORTD_READY_MASK;
1744                 dpll_reg = DPIO_PHY_STATUS;
1745                 break;
1746         default:
1747                 BUG();
1748         }
1749
1750         if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1751                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1752                      port_name(dport->port), I915_READ(dpll_reg));
1753 }
1754
1755 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1756 {
1757         struct drm_device *dev = crtc->base.dev;
1758         struct drm_i915_private *dev_priv = dev->dev_private;
1759         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1760
1761         if (WARN_ON(pll == NULL))
1762                 return;
1763
1764         WARN_ON(!pll->refcount);
1765         if (pll->active == 0) {
1766                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1767                 WARN_ON(pll->on);
1768                 assert_shared_dpll_disabled(dev_priv, pll);
1769
1770                 pll->mode_set(dev_priv, pll);
1771         }
1772 }
1773
1774 /**
1775  * intel_enable_shared_dpll - enable PCH PLL
1776  * @dev_priv: i915 private structure
1777  * @pipe: pipe PLL to enable
1778  *
1779  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1780  * drives the transcoder clock.
1781  */
1782 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1783 {
1784         struct drm_device *dev = crtc->base.dev;
1785         struct drm_i915_private *dev_priv = dev->dev_private;
1786         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1787
1788         if (WARN_ON(pll == NULL))
1789                 return;
1790
1791         if (WARN_ON(pll->refcount == 0))
1792                 return;
1793
1794         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1795                       pll->name, pll->active, pll->on,
1796                       crtc->base.base.id);
1797
1798         if (pll->active++) {
1799                 WARN_ON(!pll->on);
1800                 assert_shared_dpll_enabled(dev_priv, pll);
1801                 return;
1802         }
1803         WARN_ON(pll->on);
1804
1805         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1806
1807         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1808         pll->enable(dev_priv, pll);
1809         pll->on = true;
1810 }
1811
1812 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1813 {
1814         struct drm_device *dev = crtc->base.dev;
1815         struct drm_i915_private *dev_priv = dev->dev_private;
1816         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1817
1818         /* PCH only available on ILK+ */
1819         BUG_ON(INTEL_INFO(dev)->gen < 5);
1820         if (WARN_ON(pll == NULL))
1821                return;
1822
1823         if (WARN_ON(pll->refcount == 0))
1824                 return;
1825
1826         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1827                       pll->name, pll->active, pll->on,
1828                       crtc->base.base.id);
1829
1830         if (WARN_ON(pll->active == 0)) {
1831                 assert_shared_dpll_disabled(dev_priv, pll);
1832                 return;
1833         }
1834
1835         assert_shared_dpll_enabled(dev_priv, pll);
1836         WARN_ON(!pll->on);
1837         if (--pll->active)
1838                 return;
1839
1840         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1841         pll->disable(dev_priv, pll);
1842         pll->on = false;
1843
1844         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1845 }
1846
1847 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1848                                            enum pipe pipe)
1849 {
1850         struct drm_device *dev = dev_priv->dev;
1851         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1852         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1853         uint32_t reg, val, pipeconf_val;
1854
1855         /* PCH only available on ILK+ */
1856         BUG_ON(!HAS_PCH_SPLIT(dev));
1857
1858         /* Make sure PCH DPLL is enabled */
1859         assert_shared_dpll_enabled(dev_priv,
1860                                    intel_crtc_to_shared_dpll(intel_crtc));
1861
1862         /* FDI must be feeding us bits for PCH ports */
1863         assert_fdi_tx_enabled(dev_priv, pipe);
1864         assert_fdi_rx_enabled(dev_priv, pipe);
1865
1866         if (HAS_PCH_CPT(dev)) {
1867                 /* Workaround: Set the timing override bit before enabling the
1868                  * pch transcoder. */
1869                 reg = TRANS_CHICKEN2(pipe);
1870                 val = I915_READ(reg);
1871                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1872                 I915_WRITE(reg, val);
1873         }
1874
1875         reg = PCH_TRANSCONF(pipe);
1876         val = I915_READ(reg);
1877         pipeconf_val = I915_READ(PIPECONF(pipe));
1878
1879         if (HAS_PCH_IBX(dev_priv->dev)) {
1880                 /*
1881                  * make the BPC in transcoder be consistent with
1882                  * that in pipeconf reg.
1883                  */
1884                 val &= ~PIPECONF_BPC_MASK;
1885                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1886         }
1887
1888         val &= ~TRANS_INTERLACE_MASK;
1889         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1890                 if (HAS_PCH_IBX(dev_priv->dev) &&
1891                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1892                         val |= TRANS_LEGACY_INTERLACED_ILK;
1893                 else
1894                         val |= TRANS_INTERLACED;
1895         else
1896                 val |= TRANS_PROGRESSIVE;
1897
1898         I915_WRITE(reg, val | TRANS_ENABLE);
1899         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1900                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1901 }
1902
1903 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1904                                       enum transcoder cpu_transcoder)
1905 {
1906         u32 val, pipeconf_val;
1907
1908         /* PCH only available on ILK+ */
1909         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1910
1911         /* FDI must be feeding us bits for PCH ports */
1912         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1913         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1914
1915         /* Workaround: set timing override bit. */
1916         val = I915_READ(_TRANSA_CHICKEN2);
1917         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1918         I915_WRITE(_TRANSA_CHICKEN2, val);
1919
1920         val = TRANS_ENABLE;
1921         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1922
1923         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1924             PIPECONF_INTERLACED_ILK)
1925                 val |= TRANS_INTERLACED;
1926         else
1927                 val |= TRANS_PROGRESSIVE;
1928
1929         I915_WRITE(LPT_TRANSCONF, val);
1930         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1931                 DRM_ERROR("Failed to enable PCH transcoder\n");
1932 }
1933
1934 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1935                                             enum pipe pipe)
1936 {
1937         struct drm_device *dev = dev_priv->dev;
1938         uint32_t reg, val;
1939
1940         /* FDI relies on the transcoder */
1941         assert_fdi_tx_disabled(dev_priv, pipe);
1942         assert_fdi_rx_disabled(dev_priv, pipe);
1943
1944         /* Ports must be off as well */
1945         assert_pch_ports_disabled(dev_priv, pipe);
1946
1947         reg = PCH_TRANSCONF(pipe);
1948         val = I915_READ(reg);
1949         val &= ~TRANS_ENABLE;
1950         I915_WRITE(reg, val);
1951         /* wait for PCH transcoder off, transcoder state */
1952         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1953                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1954
1955         if (!HAS_PCH_IBX(dev)) {
1956                 /* Workaround: Clear the timing override chicken bit again. */
1957                 reg = TRANS_CHICKEN2(pipe);
1958                 val = I915_READ(reg);
1959                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1960                 I915_WRITE(reg, val);
1961         }
1962 }
1963
1964 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1965 {
1966         u32 val;
1967
1968         val = I915_READ(LPT_TRANSCONF);
1969         val &= ~TRANS_ENABLE;
1970         I915_WRITE(LPT_TRANSCONF, val);
1971         /* wait for PCH transcoder off, transcoder state */
1972         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1973                 DRM_ERROR("Failed to disable PCH transcoder\n");
1974
1975         /* Workaround: clear timing override bit. */
1976         val = I915_READ(_TRANSA_CHICKEN2);
1977         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1978         I915_WRITE(_TRANSA_CHICKEN2, val);
1979 }
1980
1981 /**
1982  * intel_enable_pipe - enable a pipe, asserting requirements
1983  * @crtc: crtc responsible for the pipe
1984  *
1985  * Enable @crtc's pipe, making sure that various hardware specific requirements
1986  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1987  */
1988 static void intel_enable_pipe(struct intel_crtc *crtc)
1989 {
1990         struct drm_device *dev = crtc->base.dev;
1991         struct drm_i915_private *dev_priv = dev->dev_private;
1992         enum pipe pipe = crtc->pipe;
1993         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1994                                                                       pipe);
1995         enum pipe pch_transcoder;
1996         int reg;
1997         u32 val;
1998
1999         assert_planes_disabled(dev_priv, pipe);
2000         assert_cursor_disabled(dev_priv, pipe);
2001         assert_sprites_disabled(dev_priv, pipe);
2002
2003         if (HAS_PCH_LPT(dev_priv->dev))
2004                 pch_transcoder = TRANSCODER_A;
2005         else
2006                 pch_transcoder = pipe;
2007
2008         /*
2009          * A pipe without a PLL won't actually be able to drive bits from
2010          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2011          * need the check.
2012          */
2013         if (!HAS_PCH_SPLIT(dev_priv->dev))
2014                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2015                         assert_dsi_pll_enabled(dev_priv);
2016                 else
2017                         assert_pll_enabled(dev_priv, pipe);
2018         else {
2019                 if (crtc->config.has_pch_encoder) {
2020                         /* if driving the PCH, we need FDI enabled */
2021                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2022                         assert_fdi_tx_pll_enabled(dev_priv,
2023                                                   (enum pipe) cpu_transcoder);
2024                 }
2025                 /* FIXME: assert CPU port conditions for SNB+ */
2026         }
2027
2028         reg = PIPECONF(cpu_transcoder);
2029         val = I915_READ(reg);
2030         if (val & PIPECONF_ENABLE) {
2031                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2032                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2033                 return;
2034         }
2035
2036         I915_WRITE(reg, val | PIPECONF_ENABLE);
2037         POSTING_READ(reg);
2038 }
2039
2040 /**
2041  * intel_disable_pipe - disable a pipe, asserting requirements
2042  * @crtc: crtc whose pipes is to be disabled
2043  *
2044  * Disable the pipe of @crtc, making sure that various hardware
2045  * specific requirements are met, if applicable, e.g. plane
2046  * disabled, panel fitter off, etc.
2047  *
2048  * Will wait until the pipe has shut down before returning.
2049  */
2050 static void intel_disable_pipe(struct intel_crtc *crtc)
2051 {
2052         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2053         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2054         enum pipe pipe = crtc->pipe;
2055         int reg;
2056         u32 val;
2057
2058         /*
2059          * Make sure planes won't keep trying to pump pixels to us,
2060          * or we might hang the display.
2061          */
2062         assert_planes_disabled(dev_priv, pipe);
2063         assert_cursor_disabled(dev_priv, pipe);
2064         assert_sprites_disabled(dev_priv, pipe);
2065
2066         reg = PIPECONF(cpu_transcoder);
2067         val = I915_READ(reg);
2068         if ((val & PIPECONF_ENABLE) == 0)
2069                 return;
2070
2071         /*
2072          * Double wide has implications for planes
2073          * so best keep it disabled when not needed.
2074          */
2075         if (crtc->config.double_wide)
2076                 val &= ~PIPECONF_DOUBLE_WIDE;
2077
2078         /* Don't disable pipe or pipe PLLs if needed */
2079         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2080             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2081                 val &= ~PIPECONF_ENABLE;
2082
2083         I915_WRITE(reg, val);
2084         if ((val & PIPECONF_ENABLE) == 0)
2085                 intel_wait_for_pipe_off(crtc);
2086 }
2087
2088 /*
2089  * Plane regs are double buffered, going from enabled->disabled needs a
2090  * trigger in order to latch.  The display address reg provides this.
2091  */
2092 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2093                                enum plane plane)
2094 {
2095         struct drm_device *dev = dev_priv->dev;
2096         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2097
2098         I915_WRITE(reg, I915_READ(reg));
2099         POSTING_READ(reg);
2100 }
2101
2102 /**
2103  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2104  * @plane:  plane to be enabled
2105  * @crtc: crtc for the plane
2106  *
2107  * Enable @plane on @crtc, making sure that the pipe is running first.
2108  */
2109 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2110                                           struct drm_crtc *crtc)
2111 {
2112         struct drm_device *dev = plane->dev;
2113         struct drm_i915_private *dev_priv = dev->dev_private;
2114         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2115
2116         /* If the pipe isn't enabled, we can't pump pixels and may hang */
2117         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2118
2119         if (intel_crtc->primary_enabled)
2120                 return;
2121
2122         intel_crtc->primary_enabled = true;
2123
2124         dev_priv->display.update_primary_plane(crtc, plane->fb,
2125                                                crtc->x, crtc->y);
2126
2127         /*
2128          * BDW signals flip done immediately if the plane
2129          * is disabled, even if the plane enable is already
2130          * armed to occur at the next vblank :(
2131          */
2132         if (IS_BROADWELL(dev))
2133                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2134 }
2135
2136 /**
2137  * intel_disable_primary_hw_plane - disable the primary hardware plane
2138  * @plane: plane to be disabled
2139  * @crtc: crtc for the plane
2140  *
2141  * Disable @plane on @crtc, making sure that the pipe is running first.
2142  */
2143 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2144                                            struct drm_crtc *crtc)
2145 {
2146         struct drm_device *dev = plane->dev;
2147         struct drm_i915_private *dev_priv = dev->dev_private;
2148         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2149
2150         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2151
2152         if (!intel_crtc->primary_enabled)
2153                 return;
2154
2155         intel_crtc->primary_enabled = false;
2156
2157         dev_priv->display.update_primary_plane(crtc, plane->fb,
2158                                                crtc->x, crtc->y);
2159 }
2160
2161 static bool need_vtd_wa(struct drm_device *dev)
2162 {
2163 #ifdef CONFIG_INTEL_IOMMU
2164         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2165                 return true;
2166 #endif
2167         return false;
2168 }
2169
2170 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2171 {
2172         int tile_height;
2173
2174         tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2175         return ALIGN(height, tile_height);
2176 }
2177
2178 int
2179 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2180                            struct drm_i915_gem_object *obj,
2181                            struct intel_engine_cs *pipelined)
2182 {
2183         struct drm_i915_private *dev_priv = dev->dev_private;
2184         u32 alignment;
2185         int ret;
2186
2187         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2188
2189         switch (obj->tiling_mode) {
2190         case I915_TILING_NONE:
2191                 if (INTEL_INFO(dev)->gen >= 9)
2192                         alignment = 256 * 1024;
2193                 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2194                         alignment = 128 * 1024;
2195                 else if (INTEL_INFO(dev)->gen >= 4)
2196                         alignment = 4 * 1024;
2197                 else
2198                         alignment = 64 * 1024;
2199                 break;
2200         case I915_TILING_X:
2201                 if (INTEL_INFO(dev)->gen >= 9)
2202                         alignment = 256 * 1024;
2203                 else {
2204                         /* pin() will align the object as required by fence */
2205                         alignment = 0;
2206                 }
2207                 break;
2208         case I915_TILING_Y:
2209                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2210                 return -EINVAL;
2211         default:
2212                 BUG();
2213         }
2214
2215         /* Note that the w/a also requires 64 PTE of padding following the
2216          * bo. We currently fill all unused PTE with the shadow page and so
2217          * we should always have valid PTE following the scanout preventing
2218          * the VT-d warning.
2219          */
2220         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2221                 alignment = 256 * 1024;
2222
2223         /*
2224          * Global gtt pte registers are special registers which actually forward
2225          * writes to a chunk of system memory. Which means that there is no risk
2226          * that the register values disappear as soon as we call
2227          * intel_runtime_pm_put(), so it is correct to wrap only the
2228          * pin/unpin/fence and not more.
2229          */
2230         intel_runtime_pm_get(dev_priv);
2231
2232         dev_priv->mm.interruptible = false;
2233         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2234         if (ret)
2235                 goto err_interruptible;
2236
2237         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2238          * fence, whereas 965+ only requires a fence if using
2239          * framebuffer compression.  For simplicity, we always install
2240          * a fence as the cost is not that onerous.
2241          */
2242         ret = i915_gem_object_get_fence(obj);
2243         if (ret)
2244                 goto err_unpin;
2245
2246         i915_gem_object_pin_fence(obj);
2247
2248         dev_priv->mm.interruptible = true;
2249         intel_runtime_pm_put(dev_priv);
2250         return 0;
2251
2252 err_unpin:
2253         i915_gem_object_unpin_from_display_plane(obj);
2254 err_interruptible:
2255         dev_priv->mm.interruptible = true;
2256         intel_runtime_pm_put(dev_priv);
2257         return ret;
2258 }
2259
2260 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2261 {
2262         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2263
2264         i915_gem_object_unpin_fence(obj);
2265         i915_gem_object_unpin_from_display_plane(obj);
2266 }
2267
2268 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2269  * is assumed to be a power-of-two. */
2270 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2271                                              unsigned int tiling_mode,
2272                                              unsigned int cpp,
2273                                              unsigned int pitch)
2274 {
2275         if (tiling_mode != I915_TILING_NONE) {
2276                 unsigned int tile_rows, tiles;
2277
2278                 tile_rows = *y / 8;
2279                 *y %= 8;
2280
2281                 tiles = *x / (512/cpp);
2282                 *x %= 512/cpp;
2283
2284                 return tile_rows * pitch * 8 + tiles * 4096;
2285         } else {
2286                 unsigned int offset;
2287
2288                 offset = *y * pitch + *x * cpp;
2289                 *y = 0;
2290                 *x = (offset & 4095) / cpp;
2291                 return offset & -4096;
2292         }
2293 }
2294
2295 int intel_format_to_fourcc(int format)
2296 {
2297         switch (format) {
2298         case DISPPLANE_8BPP:
2299                 return DRM_FORMAT_C8;
2300         case DISPPLANE_BGRX555:
2301                 return DRM_FORMAT_XRGB1555;
2302         case DISPPLANE_BGRX565:
2303                 return DRM_FORMAT_RGB565;
2304         default:
2305         case DISPPLANE_BGRX888:
2306                 return DRM_FORMAT_XRGB8888;
2307         case DISPPLANE_RGBX888:
2308                 return DRM_FORMAT_XBGR8888;
2309         case DISPPLANE_BGRX101010:
2310                 return DRM_FORMAT_XRGB2101010;
2311         case DISPPLANE_RGBX101010:
2312                 return DRM_FORMAT_XBGR2101010;
2313         }
2314 }
2315
2316 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2317                                   struct intel_plane_config *plane_config)
2318 {
2319         struct drm_device *dev = crtc->base.dev;
2320         struct drm_i915_gem_object *obj = NULL;
2321         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2322         u32 base = plane_config->base;
2323
2324         if (plane_config->size == 0)
2325                 return false;
2326
2327         obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2328                                                              plane_config->size);
2329         if (!obj)
2330                 return false;
2331
2332         if (plane_config->tiled) {
2333                 obj->tiling_mode = I915_TILING_X;
2334                 obj->stride = crtc->base.primary->fb->pitches[0];
2335         }
2336
2337         mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2338         mode_cmd.width = crtc->base.primary->fb->width;
2339         mode_cmd.height = crtc->base.primary->fb->height;
2340         mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2341
2342         mutex_lock(&dev->struct_mutex);
2343
2344         if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2345                                    &mode_cmd, obj)) {
2346                 DRM_DEBUG_KMS("intel fb init failed\n");
2347                 goto out_unref_obj;
2348         }
2349
2350         obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2351         mutex_unlock(&dev->struct_mutex);
2352
2353         DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2354         return true;
2355
2356 out_unref_obj:
2357         drm_gem_object_unreference(&obj->base);
2358         mutex_unlock(&dev->struct_mutex);
2359         return false;
2360 }
2361
2362 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2363                                  struct intel_plane_config *plane_config)
2364 {
2365         struct drm_device *dev = intel_crtc->base.dev;
2366         struct drm_i915_private *dev_priv = dev->dev_private;
2367         struct drm_crtc *c;
2368         struct intel_crtc *i;
2369         struct drm_i915_gem_object *obj;
2370
2371         if (!intel_crtc->base.primary->fb)
2372                 return;
2373
2374         if (intel_alloc_plane_obj(intel_crtc, plane_config))
2375                 return;
2376
2377         kfree(intel_crtc->base.primary->fb);
2378         intel_crtc->base.primary->fb = NULL;
2379
2380         /*
2381          * Failed to alloc the obj, check to see if we should share
2382          * an fb with another CRTC instead
2383          */
2384         for_each_crtc(dev, c) {
2385                 i = to_intel_crtc(c);
2386
2387                 if (c == &intel_crtc->base)
2388                         continue;
2389
2390                 if (!i->active)
2391                         continue;
2392
2393                 obj = intel_fb_obj(c->primary->fb);
2394                 if (obj == NULL)
2395                         continue;
2396
2397                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2398                         if (obj->tiling_mode != I915_TILING_NONE)
2399                                 dev_priv->preserve_bios_swizzle = true;
2400
2401                         drm_framebuffer_reference(c->primary->fb);
2402                         intel_crtc->base.primary->fb = c->primary->fb;
2403                         obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2404                         break;
2405                 }
2406         }
2407 }
2408
2409 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2410                                       struct drm_framebuffer *fb,
2411                                       int x, int y)
2412 {
2413         struct drm_device *dev = crtc->dev;
2414         struct drm_i915_private *dev_priv = dev->dev_private;
2415         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2416         struct drm_i915_gem_object *obj;
2417         int plane = intel_crtc->plane;
2418         unsigned long linear_offset;
2419         u32 dspcntr;
2420         u32 reg = DSPCNTR(plane);
2421         int pixel_size;
2422
2423         if (!intel_crtc->primary_enabled) {
2424                 I915_WRITE(reg, 0);
2425                 if (INTEL_INFO(dev)->gen >= 4)
2426                         I915_WRITE(DSPSURF(plane), 0);
2427                 else
2428                         I915_WRITE(DSPADDR(plane), 0);
2429                 POSTING_READ(reg);
2430                 return;
2431         }
2432
2433         obj = intel_fb_obj(fb);
2434         if (WARN_ON(obj == NULL))
2435                 return;
2436
2437         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2438
2439         dspcntr = DISPPLANE_GAMMA_ENABLE;
2440
2441         dspcntr |= DISPLAY_PLANE_ENABLE;
2442
2443         if (INTEL_INFO(dev)->gen < 4) {
2444                 if (intel_crtc->pipe == PIPE_B)
2445                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2446
2447                 /* pipesrc and dspsize control the size that is scaled from,
2448                  * which should always be the user's requested size.
2449                  */
2450                 I915_WRITE(DSPSIZE(plane),
2451                            ((intel_crtc->config.pipe_src_h - 1) << 16) |
2452                            (intel_crtc->config.pipe_src_w - 1));
2453                 I915_WRITE(DSPPOS(plane), 0);
2454         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2455                 I915_WRITE(PRIMSIZE(plane),
2456                            ((intel_crtc->config.pipe_src_h - 1) << 16) |
2457                            (intel_crtc->config.pipe_src_w - 1));
2458                 I915_WRITE(PRIMPOS(plane), 0);
2459                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2460         }
2461
2462         switch (fb->pixel_format) {
2463         case DRM_FORMAT_C8:
2464                 dspcntr |= DISPPLANE_8BPP;
2465                 break;
2466         case DRM_FORMAT_XRGB1555:
2467         case DRM_FORMAT_ARGB1555:
2468                 dspcntr |= DISPPLANE_BGRX555;
2469                 break;
2470         case DRM_FORMAT_RGB565:
2471                 dspcntr |= DISPPLANE_BGRX565;
2472                 break;
2473         case DRM_FORMAT_XRGB8888:
2474         case DRM_FORMAT_ARGB8888:
2475                 dspcntr |= DISPPLANE_BGRX888;
2476                 break;
2477         case DRM_FORMAT_XBGR8888:
2478         case DRM_FORMAT_ABGR8888:
2479                 dspcntr |= DISPPLANE_RGBX888;
2480                 break;
2481         case DRM_FORMAT_XRGB2101010:
2482         case DRM_FORMAT_ARGB2101010:
2483                 dspcntr |= DISPPLANE_BGRX101010;
2484                 break;
2485         case DRM_FORMAT_XBGR2101010:
2486         case DRM_FORMAT_ABGR2101010:
2487                 dspcntr |= DISPPLANE_RGBX101010;
2488                 break;
2489         default:
2490                 BUG();
2491         }
2492
2493         if (INTEL_INFO(dev)->gen >= 4 &&
2494             obj->tiling_mode != I915_TILING_NONE)
2495                 dspcntr |= DISPPLANE_TILED;
2496
2497         if (IS_G4X(dev))
2498                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2499
2500         linear_offset = y * fb->pitches[0] + x * pixel_size;
2501
2502         if (INTEL_INFO(dev)->gen >= 4) {
2503                 intel_crtc->dspaddr_offset =
2504                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2505                                                        pixel_size,
2506                                                        fb->pitches[0]);
2507                 linear_offset -= intel_crtc->dspaddr_offset;
2508         } else {
2509                 intel_crtc->dspaddr_offset = linear_offset;
2510         }
2511
2512         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2513                 dspcntr |= DISPPLANE_ROTATE_180;
2514
2515                 x += (intel_crtc->config.pipe_src_w - 1);
2516                 y += (intel_crtc->config.pipe_src_h - 1);
2517
2518                 /* Finding the last pixel of the last line of the display
2519                 data and adding to linear_offset*/
2520                 linear_offset +=
2521                         (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2522                         (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2523         }
2524
2525         I915_WRITE(reg, dspcntr);
2526
2527         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2528                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2529                       fb->pitches[0]);
2530         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2531         if (INTEL_INFO(dev)->gen >= 4) {
2532                 I915_WRITE(DSPSURF(plane),
2533                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2534                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2535                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2536         } else
2537                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2538         POSTING_READ(reg);
2539 }
2540
2541 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2542                                           struct drm_framebuffer *fb,
2543                                           int x, int y)
2544 {
2545         struct drm_device *dev = crtc->dev;
2546         struct drm_i915_private *dev_priv = dev->dev_private;
2547         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2548         struct drm_i915_gem_object *obj;
2549         int plane = intel_crtc->plane;
2550         unsigned long linear_offset;
2551         u32 dspcntr;
2552         u32 reg = DSPCNTR(plane);
2553         int pixel_size;
2554
2555         if (!intel_crtc->primary_enabled) {
2556                 I915_WRITE(reg, 0);
2557                 I915_WRITE(DSPSURF(plane), 0);
2558                 POSTING_READ(reg);
2559                 return;
2560         }
2561
2562         obj = intel_fb_obj(fb);
2563         if (WARN_ON(obj == NULL))
2564                 return;
2565
2566         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2567
2568         dspcntr = DISPPLANE_GAMMA_ENABLE;
2569
2570         dspcntr |= DISPLAY_PLANE_ENABLE;
2571
2572         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2573                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2574
2575         switch (fb->pixel_format) {
2576         case DRM_FORMAT_C8:
2577                 dspcntr |= DISPPLANE_8BPP;
2578                 break;
2579         case DRM_FORMAT_RGB565:
2580                 dspcntr |= DISPPLANE_BGRX565;
2581                 break;
2582         case DRM_FORMAT_XRGB8888:
2583         case DRM_FORMAT_ARGB8888:
2584                 dspcntr |= DISPPLANE_BGRX888;
2585                 break;
2586         case DRM_FORMAT_XBGR8888:
2587         case DRM_FORMAT_ABGR8888:
2588                 dspcntr |= DISPPLANE_RGBX888;
2589                 break;
2590         case DRM_FORMAT_XRGB2101010:
2591         case DRM_FORMAT_ARGB2101010:
2592                 dspcntr |= DISPPLANE_BGRX101010;
2593                 break;
2594         case DRM_FORMAT_XBGR2101010:
2595         case DRM_FORMAT_ABGR2101010:
2596                 dspcntr |= DISPPLANE_RGBX101010;
2597                 break;
2598         default:
2599                 BUG();
2600         }
2601
2602         if (obj->tiling_mode != I915_TILING_NONE)
2603                 dspcntr |= DISPPLANE_TILED;
2604
2605         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2606                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2607
2608         linear_offset = y * fb->pitches[0] + x * pixel_size;
2609         intel_crtc->dspaddr_offset =
2610                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2611                                                pixel_size,
2612                                                fb->pitches[0]);
2613         linear_offset -= intel_crtc->dspaddr_offset;
2614         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2615                 dspcntr |= DISPPLANE_ROTATE_180;
2616
2617                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2618                         x += (intel_crtc->config.pipe_src_w - 1);
2619                         y += (intel_crtc->config.pipe_src_h - 1);
2620
2621                         /* Finding the last pixel of the last line of the display
2622                         data and adding to linear_offset*/
2623                         linear_offset +=
2624                                 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2625                                 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2626                 }
2627         }
2628
2629         I915_WRITE(reg, dspcntr);
2630
2631         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2632                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2633                       fb->pitches[0]);
2634         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2635         I915_WRITE(DSPSURF(plane),
2636                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2637         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2638                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2639         } else {
2640                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2641                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2642         }
2643         POSTING_READ(reg);
2644 }
2645
2646 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2647                                          struct drm_framebuffer *fb,
2648                                          int x, int y)
2649 {
2650         struct drm_device *dev = crtc->dev;
2651         struct drm_i915_private *dev_priv = dev->dev_private;
2652         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2653         struct intel_framebuffer *intel_fb;
2654         struct drm_i915_gem_object *obj;
2655         int pipe = intel_crtc->pipe;
2656         u32 plane_ctl, stride;
2657
2658         if (!intel_crtc->primary_enabled) {
2659                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2660                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2661                 POSTING_READ(PLANE_CTL(pipe, 0));
2662                 return;
2663         }
2664
2665         plane_ctl = PLANE_CTL_ENABLE |
2666                     PLANE_CTL_PIPE_GAMMA_ENABLE |
2667                     PLANE_CTL_PIPE_CSC_ENABLE;
2668
2669         switch (fb->pixel_format) {
2670         case DRM_FORMAT_RGB565:
2671                 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2672                 break;
2673         case DRM_FORMAT_XRGB8888:
2674                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2675                 break;
2676         case DRM_FORMAT_XBGR8888:
2677                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2678                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2679                 break;
2680         case DRM_FORMAT_XRGB2101010:
2681                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2682                 break;
2683         case DRM_FORMAT_XBGR2101010:
2684                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2685                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2686                 break;
2687         default:
2688                 BUG();
2689         }
2690
2691         intel_fb = to_intel_framebuffer(fb);
2692         obj = intel_fb->obj;
2693
2694         /*
2695          * The stride is either expressed as a multiple of 64 bytes chunks for
2696          * linear buffers or in number of tiles for tiled buffers.
2697          */
2698         switch (obj->tiling_mode) {
2699         case I915_TILING_NONE:
2700                 stride = fb->pitches[0] >> 6;
2701                 break;
2702         case I915_TILING_X:
2703                 plane_ctl |= PLANE_CTL_TILED_X;
2704                 stride = fb->pitches[0] >> 9;
2705                 break;
2706         default:
2707                 BUG();
2708         }
2709
2710         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2711         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180))
2712                 plane_ctl |= PLANE_CTL_ROTATE_180;
2713
2714         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2715
2716         DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2717                       i915_gem_obj_ggtt_offset(obj),
2718                       x, y, fb->width, fb->height,
2719                       fb->pitches[0]);
2720
2721         I915_WRITE(PLANE_POS(pipe, 0), 0);
2722         I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2723         I915_WRITE(PLANE_SIZE(pipe, 0),
2724                    (intel_crtc->config.pipe_src_h - 1) << 16 |
2725                    (intel_crtc->config.pipe_src_w - 1));
2726         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
2727         I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2728
2729         POSTING_READ(PLANE_SURF(pipe, 0));
2730 }
2731
2732 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2733 static int
2734 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2735                            int x, int y, enum mode_set_atomic state)
2736 {
2737         struct drm_device *dev = crtc->dev;
2738         struct drm_i915_private *dev_priv = dev->dev_private;
2739
2740         if (dev_priv->display.disable_fbc)
2741                 dev_priv->display.disable_fbc(dev);
2742
2743         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2744
2745         return 0;
2746 }
2747
2748 void intel_display_handle_reset(struct drm_device *dev)
2749 {
2750         struct drm_i915_private *dev_priv = dev->dev_private;
2751         struct drm_crtc *crtc;
2752
2753         /*
2754          * Flips in the rings have been nuked by the reset,
2755          * so complete all pending flips so that user space
2756          * will get its events and not get stuck.
2757          *
2758          * Also update the base address of all primary
2759          * planes to the the last fb to make sure we're
2760          * showing the correct fb after a reset.
2761          *
2762          * Need to make two loops over the crtcs so that we
2763          * don't try to grab a crtc mutex before the
2764          * pending_flip_queue really got woken up.
2765          */
2766
2767         for_each_crtc(dev, crtc) {
2768                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2769                 enum plane plane = intel_crtc->plane;
2770
2771                 intel_prepare_page_flip(dev, plane);
2772                 intel_finish_page_flip_plane(dev, plane);
2773         }
2774
2775         for_each_crtc(dev, crtc) {
2776                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2777
2778                 drm_modeset_lock(&crtc->mutex, NULL);
2779                 /*
2780                  * FIXME: Once we have proper support for primary planes (and
2781                  * disabling them without disabling the entire crtc) allow again
2782                  * a NULL crtc->primary->fb.
2783                  */
2784                 if (intel_crtc->active && crtc->primary->fb)
2785                         dev_priv->display.update_primary_plane(crtc,
2786                                                                crtc->primary->fb,
2787                                                                crtc->x,
2788                                                                crtc->y);
2789                 drm_modeset_unlock(&crtc->mutex);
2790         }
2791 }
2792
2793 static int
2794 intel_finish_fb(struct drm_framebuffer *old_fb)
2795 {
2796         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2797         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2798         bool was_interruptible = dev_priv->mm.interruptible;
2799         int ret;
2800
2801         /* Big Hammer, we also need to ensure that any pending
2802          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2803          * current scanout is retired before unpinning the old
2804          * framebuffer.
2805          *
2806          * This should only fail upon a hung GPU, in which case we
2807          * can safely continue.
2808          */
2809         dev_priv->mm.interruptible = false;
2810         ret = i915_gem_object_finish_gpu(obj);
2811         dev_priv->mm.interruptible = was_interruptible;
2812
2813         return ret;
2814 }
2815
2816 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2817 {
2818         struct drm_device *dev = crtc->dev;
2819         struct drm_i915_private *dev_priv = dev->dev_private;
2820         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2821         bool pending;
2822
2823         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2824             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2825                 return false;
2826
2827         spin_lock_irq(&dev->event_lock);
2828         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2829         spin_unlock_irq(&dev->event_lock);
2830
2831         return pending;
2832 }
2833
2834 static void intel_update_pipe_size(struct intel_crtc *crtc)
2835 {
2836         struct drm_device *dev = crtc->base.dev;
2837         struct drm_i915_private *dev_priv = dev->dev_private;
2838         const struct drm_display_mode *adjusted_mode;
2839
2840         if (!i915.fastboot)
2841                 return;
2842
2843         /*
2844          * Update pipe size and adjust fitter if needed: the reason for this is
2845          * that in compute_mode_changes we check the native mode (not the pfit
2846          * mode) to see if we can flip rather than do a full mode set. In the
2847          * fastboot case, we'll flip, but if we don't update the pipesrc and
2848          * pfit state, we'll end up with a big fb scanned out into the wrong
2849          * sized surface.
2850          *
2851          * To fix this properly, we need to hoist the checks up into
2852          * compute_mode_changes (or above), check the actual pfit state and
2853          * whether the platform allows pfit disable with pipe active, and only
2854          * then update the pipesrc and pfit state, even on the flip path.
2855          */
2856
2857         adjusted_mode = &crtc->config.adjusted_mode;
2858
2859         I915_WRITE(PIPESRC(crtc->pipe),
2860                    ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2861                    (adjusted_mode->crtc_vdisplay - 1));
2862         if (!crtc->config.pch_pfit.enabled &&
2863             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2864              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2865                 I915_WRITE(PF_CTL(crtc->pipe), 0);
2866                 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
2867                 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
2868         }
2869         crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2870         crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2871 }
2872
2873 static int
2874 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2875                     struct drm_framebuffer *fb)
2876 {
2877         struct drm_device *dev = crtc->dev;
2878         struct drm_i915_private *dev_priv = dev->dev_private;
2879         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2880         enum pipe pipe = intel_crtc->pipe;
2881         struct drm_framebuffer *old_fb = crtc->primary->fb;
2882         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2883         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
2884         int ret;
2885
2886         if (intel_crtc_has_pending_flip(crtc)) {
2887                 DRM_ERROR("pipe is still busy with an old pageflip\n");
2888                 return -EBUSY;
2889         }
2890
2891         /* no fb bound */
2892         if (!fb) {
2893                 DRM_ERROR("No FB bound\n");
2894                 return 0;
2895         }
2896
2897         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2898                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2899                           plane_name(intel_crtc->plane),
2900                           INTEL_INFO(dev)->num_pipes);
2901                 return -EINVAL;
2902         }
2903
2904         mutex_lock(&dev->struct_mutex);
2905         ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
2906         if (ret == 0)
2907                 i915_gem_track_fb(old_obj, obj,
2908                                   INTEL_FRONTBUFFER_PRIMARY(pipe));
2909         mutex_unlock(&dev->struct_mutex);
2910         if (ret != 0) {
2911                 DRM_ERROR("pin & fence failed\n");
2912                 return ret;
2913         }
2914
2915         intel_update_pipe_size(intel_crtc);
2916
2917         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2918
2919         if (intel_crtc->active)
2920                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2921
2922         crtc->primary->fb = fb;
2923         crtc->x = x;
2924         crtc->y = y;
2925
2926         if (old_fb) {
2927                 if (intel_crtc->active && old_fb != fb)
2928                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2929                 mutex_lock(&dev->struct_mutex);
2930                 intel_unpin_fb_obj(old_obj);
2931                 mutex_unlock(&dev->struct_mutex);
2932         }
2933
2934         mutex_lock(&dev->struct_mutex);
2935         intel_update_fbc(dev);
2936         mutex_unlock(&dev->struct_mutex);
2937
2938         return 0;
2939 }
2940
2941 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2942 {
2943         struct drm_device *dev = crtc->dev;
2944         struct drm_i915_private *dev_priv = dev->dev_private;
2945         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2946         int pipe = intel_crtc->pipe;
2947         u32 reg, temp;
2948
2949         /* enable normal train */
2950         reg = FDI_TX_CTL(pipe);
2951         temp = I915_READ(reg);
2952         if (IS_IVYBRIDGE(dev)) {
2953                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2954                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2955         } else {
2956                 temp &= ~FDI_LINK_TRAIN_NONE;
2957                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2958         }
2959         I915_WRITE(reg, temp);
2960
2961         reg = FDI_RX_CTL(pipe);
2962         temp = I915_READ(reg);
2963         if (HAS_PCH_CPT(dev)) {
2964                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2965                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2966         } else {
2967                 temp &= ~FDI_LINK_TRAIN_NONE;
2968                 temp |= FDI_LINK_TRAIN_NONE;
2969         }
2970         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2971
2972         /* wait one idle pattern time */
2973         POSTING_READ(reg);
2974         udelay(1000);
2975
2976         /* IVB wants error correction enabled */
2977         if (IS_IVYBRIDGE(dev))
2978                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2979                            FDI_FE_ERRC_ENABLE);
2980 }
2981
2982 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2983 {
2984         return crtc->base.enabled && crtc->active &&
2985                 crtc->config.has_pch_encoder;
2986 }
2987
2988 static void ivb_modeset_global_resources(struct drm_device *dev)
2989 {
2990         struct drm_i915_private *dev_priv = dev->dev_private;
2991         struct intel_crtc *pipe_B_crtc =
2992                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2993         struct intel_crtc *pipe_C_crtc =
2994                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2995         uint32_t temp;
2996
2997         /*
2998          * When everything is off disable fdi C so that we could enable fdi B
2999          * with all lanes. Note that we don't care about enabled pipes without
3000          * an enabled pch encoder.
3001          */
3002         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
3003             !pipe_has_enabled_pch(pipe_C_crtc)) {
3004                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3005                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3006
3007                 temp = I915_READ(SOUTH_CHICKEN1);
3008                 temp &= ~FDI_BC_BIFURCATION_SELECT;
3009                 DRM_DEBUG_KMS("disabling fdi C rx\n");
3010                 I915_WRITE(SOUTH_CHICKEN1, temp);
3011         }
3012 }
3013
3014 /* The FDI link training functions for ILK/Ibexpeak. */
3015 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3016 {
3017         struct drm_device *dev = crtc->dev;
3018         struct drm_i915_private *dev_priv = dev->dev_private;
3019         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3020         int pipe = intel_crtc->pipe;
3021         u32 reg, temp, tries;
3022
3023         /* FDI needs bits from pipe first */
3024         assert_pipe_enabled(dev_priv, pipe);
3025
3026         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3027            for train result */
3028         reg = FDI_RX_IMR(pipe);
3029         temp = I915_READ(reg);
3030         temp &= ~FDI_RX_SYMBOL_LOCK;
3031         temp &= ~FDI_RX_BIT_LOCK;
3032         I915_WRITE(reg, temp);
3033         I915_READ(reg);
3034         udelay(150);
3035
3036         /* enable CPU FDI TX and PCH FDI RX */
3037         reg = FDI_TX_CTL(pipe);
3038         temp = I915_READ(reg);
3039         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3040         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3041         temp &= ~FDI_LINK_TRAIN_NONE;
3042         temp |= FDI_LINK_TRAIN_PATTERN_1;
3043         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3044
3045         reg = FDI_RX_CTL(pipe);
3046         temp = I915_READ(reg);
3047         temp &= ~FDI_LINK_TRAIN_NONE;
3048         temp |= FDI_LINK_TRAIN_PATTERN_1;
3049         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3050
3051         POSTING_READ(reg);
3052         udelay(150);
3053
3054         /* Ironlake workaround, enable clock pointer after FDI enable*/
3055         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3056         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3057                    FDI_RX_PHASE_SYNC_POINTER_EN);
3058
3059         reg = FDI_RX_IIR(pipe);
3060         for (tries = 0; tries < 5; tries++) {
3061                 temp = I915_READ(reg);
3062                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3063
3064                 if ((temp & FDI_RX_BIT_LOCK)) {
3065                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3066                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3067                         break;
3068                 }
3069         }
3070         if (tries == 5)
3071                 DRM_ERROR("FDI train 1 fail!\n");
3072
3073         /* Train 2 */
3074         reg = FDI_TX_CTL(pipe);
3075         temp = I915_READ(reg);
3076         temp &= ~FDI_LINK_TRAIN_NONE;
3077         temp |= FDI_LINK_TRAIN_PATTERN_2;
3078         I915_WRITE(reg, temp);
3079
3080         reg = FDI_RX_CTL(pipe);
3081         temp = I915_READ(reg);
3082         temp &= ~FDI_LINK_TRAIN_NONE;
3083         temp |= FDI_LINK_TRAIN_PATTERN_2;
3084         I915_WRITE(reg, temp);
3085
3086         POSTING_READ(reg);
3087         udelay(150);
3088
3089         reg = FDI_RX_IIR(pipe);
3090         for (tries = 0; tries < 5; tries++) {
3091                 temp = I915_READ(reg);
3092                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3093
3094                 if (temp & FDI_RX_SYMBOL_LOCK) {
3095                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3096                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3097                         break;
3098                 }
3099         }
3100         if (tries == 5)
3101                 DRM_ERROR("FDI train 2 fail!\n");
3102
3103         DRM_DEBUG_KMS("FDI train done\n");
3104
3105 }
3106
3107 static const int snb_b_fdi_train_param[] = {
3108         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3109         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3110         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3111         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3112 };
3113
3114 /* The FDI link training functions for SNB/Cougarpoint. */
3115 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3116 {
3117         struct drm_device *dev = crtc->dev;
3118         struct drm_i915_private *dev_priv = dev->dev_private;
3119         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3120         int pipe = intel_crtc->pipe;
3121         u32 reg, temp, i, retry;
3122
3123         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3124            for train result */
3125         reg = FDI_RX_IMR(pipe);
3126         temp = I915_READ(reg);
3127         temp &= ~FDI_RX_SYMBOL_LOCK;
3128         temp &= ~FDI_RX_BIT_LOCK;
3129         I915_WRITE(reg, temp);
3130
3131         POSTING_READ(reg);
3132         udelay(150);
3133
3134         /* enable CPU FDI TX and PCH FDI RX */
3135         reg = FDI_TX_CTL(pipe);
3136         temp = I915_READ(reg);
3137         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3138         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3139         temp &= ~FDI_LINK_TRAIN_NONE;
3140         temp |= FDI_LINK_TRAIN_PATTERN_1;
3141         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3142         /* SNB-B */
3143         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3144         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3145
3146         I915_WRITE(FDI_RX_MISC(pipe),
3147                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3148
3149         reg = FDI_RX_CTL(pipe);
3150         temp = I915_READ(reg);
3151         if (HAS_PCH_CPT(dev)) {
3152                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3153                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3154         } else {
3155                 temp &= ~FDI_LINK_TRAIN_NONE;
3156                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3157         }
3158         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3159
3160         POSTING_READ(reg);
3161         udelay(150);
3162
3163         for (i = 0; i < 4; i++) {
3164                 reg = FDI_TX_CTL(pipe);
3165                 temp = I915_READ(reg);
3166                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3167                 temp |= snb_b_fdi_train_param[i];
3168                 I915_WRITE(reg, temp);
3169
3170                 POSTING_READ(reg);
3171                 udelay(500);
3172
3173                 for (retry = 0; retry < 5; retry++) {
3174                         reg = FDI_RX_IIR(pipe);
3175                         temp = I915_READ(reg);
3176                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3177                         if (temp & FDI_RX_BIT_LOCK) {
3178                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3179                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3180                                 break;
3181                         }
3182                         udelay(50);
3183                 }
3184                 if (retry < 5)
3185                         break;
3186         }
3187         if (i == 4)
3188                 DRM_ERROR("FDI train 1 fail!\n");
3189
3190         /* Train 2 */
3191         reg = FDI_TX_CTL(pipe);
3192         temp = I915_READ(reg);
3193         temp &= ~FDI_LINK_TRAIN_NONE;
3194         temp |= FDI_LINK_TRAIN_PATTERN_2;
3195         if (IS_GEN6(dev)) {
3196                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3197                 /* SNB-B */
3198                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3199         }
3200         I915_WRITE(reg, temp);
3201
3202         reg = FDI_RX_CTL(pipe);
3203         temp = I915_READ(reg);
3204         if (HAS_PCH_CPT(dev)) {
3205                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3206                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3207         } else {
3208                 temp &= ~FDI_LINK_TRAIN_NONE;
3209                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3210         }
3211         I915_WRITE(reg, temp);
3212
3213         POSTING_READ(reg);
3214         udelay(150);
3215
3216         for (i = 0; i < 4; i++) {
3217                 reg = FDI_TX_CTL(pipe);
3218                 temp = I915_READ(reg);
3219                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3220                 temp |= snb_b_fdi_train_param[i];
3221                 I915_WRITE(reg, temp);
3222
3223                 POSTING_READ(reg);
3224                 udelay(500);
3225
3226                 for (retry = 0; retry < 5; retry++) {
3227                         reg = FDI_RX_IIR(pipe);
3228                         temp = I915_READ(reg);
3229                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3230                         if (temp & FDI_RX_SYMBOL_LOCK) {
3231                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3232                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3233                                 break;
3234                         }
3235                         udelay(50);
3236                 }
3237                 if (retry < 5)
3238                         break;
3239         }
3240         if (i == 4)
3241                 DRM_ERROR("FDI train 2 fail!\n");
3242
3243         DRM_DEBUG_KMS("FDI train done.\n");
3244 }
3245
3246 /* Manual link training for Ivy Bridge A0 parts */
3247 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3248 {
3249         struct drm_device *dev = crtc->dev;
3250         struct drm_i915_private *dev_priv = dev->dev_private;
3251         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3252         int pipe = intel_crtc->pipe;
3253         u32 reg, temp, i, j;
3254
3255         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3256            for train result */
3257         reg = FDI_RX_IMR(pipe);
3258         temp = I915_READ(reg);
3259         temp &= ~FDI_RX_SYMBOL_LOCK;
3260         temp &= ~FDI_RX_BIT_LOCK;
3261         I915_WRITE(reg, temp);
3262
3263         POSTING_READ(reg);
3264         udelay(150);
3265
3266         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3267                       I915_READ(FDI_RX_IIR(pipe)));
3268
3269         /* Try each vswing and preemphasis setting twice before moving on */
3270         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3271                 /* disable first in case we need to retry */
3272                 reg = FDI_TX_CTL(pipe);
3273                 temp = I915_READ(reg);
3274                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3275                 temp &= ~FDI_TX_ENABLE;
3276                 I915_WRITE(reg, temp);
3277
3278                 reg = FDI_RX_CTL(pipe);
3279                 temp = I915_READ(reg);
3280                 temp &= ~FDI_LINK_TRAIN_AUTO;
3281                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3282                 temp &= ~FDI_RX_ENABLE;
3283                 I915_WRITE(reg, temp);
3284
3285                 /* enable CPU FDI TX and PCH FDI RX */
3286                 reg = FDI_TX_CTL(pipe);
3287                 temp = I915_READ(reg);
3288                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3289                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3290                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3291                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3292                 temp |= snb_b_fdi_train_param[j/2];
3293                 temp |= FDI_COMPOSITE_SYNC;
3294                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3295
3296                 I915_WRITE(FDI_RX_MISC(pipe),
3297                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3298
3299                 reg = FDI_RX_CTL(pipe);
3300                 temp = I915_READ(reg);
3301                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3302                 temp |= FDI_COMPOSITE_SYNC;
3303                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3304
3305                 POSTING_READ(reg);
3306                 udelay(1); /* should be 0.5us */
3307
3308                 for (i = 0; i < 4; i++) {
3309                         reg = FDI_RX_IIR(pipe);
3310                         temp = I915_READ(reg);
3311                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3312
3313                         if (temp & FDI_RX_BIT_LOCK ||
3314                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3315                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3316                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3317                                               i);
3318                                 break;
3319                         }
3320                         udelay(1); /* should be 0.5us */
3321                 }
3322                 if (i == 4) {
3323                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3324                         continue;
3325                 }
3326
3327                 /* Train 2 */
3328                 reg = FDI_TX_CTL(pipe);
3329                 temp = I915_READ(reg);
3330                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3331                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3332                 I915_WRITE(reg, temp);
3333
3334                 reg = FDI_RX_CTL(pipe);
3335                 temp = I915_READ(reg);
3336                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3337                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3338                 I915_WRITE(reg, temp);
3339
3340                 POSTING_READ(reg);
3341                 udelay(2); /* should be 1.5us */
3342
3343                 for (i = 0; i < 4; i++) {
3344                         reg = FDI_RX_IIR(pipe);
3345                         temp = I915_READ(reg);
3346                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3347
3348                         if (temp & FDI_RX_SYMBOL_LOCK ||
3349                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3350                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3351                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3352                                               i);
3353                                 goto train_done;
3354                         }
3355                         udelay(2); /* should be 1.5us */
3356                 }
3357                 if (i == 4)
3358                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3359         }
3360
3361 train_done:
3362         DRM_DEBUG_KMS("FDI train done.\n");
3363 }
3364
3365 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3366 {
3367         struct drm_device *dev = intel_crtc->base.dev;
3368         struct drm_i915_private *dev_priv = dev->dev_private;
3369         int pipe = intel_crtc->pipe;
3370         u32 reg, temp;
3371
3372
3373         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3374         reg = FDI_RX_CTL(pipe);
3375         temp = I915_READ(reg);
3376         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3377         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3378         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3379         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3380
3381         POSTING_READ(reg);
3382         udelay(200);
3383
3384         /* Switch from Rawclk to PCDclk */
3385         temp = I915_READ(reg);
3386         I915_WRITE(reg, temp | FDI_PCDCLK);
3387
3388         POSTING_READ(reg);
3389         udelay(200);
3390
3391         /* Enable CPU FDI TX PLL, always on for Ironlake */
3392         reg = FDI_TX_CTL(pipe);
3393         temp = I915_READ(reg);
3394         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3395                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3396
3397                 POSTING_READ(reg);
3398                 udelay(100);
3399         }
3400 }
3401
3402 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3403 {
3404         struct drm_device *dev = intel_crtc->base.dev;
3405         struct drm_i915_private *dev_priv = dev->dev_private;
3406         int pipe = intel_crtc->pipe;
3407         u32 reg, temp;
3408
3409         /* Switch from PCDclk to Rawclk */
3410         reg = FDI_RX_CTL(pipe);
3411         temp = I915_READ(reg);
3412         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3413
3414         /* Disable CPU FDI TX PLL */
3415         reg = FDI_TX_CTL(pipe);
3416         temp = I915_READ(reg);
3417         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3418
3419         POSTING_READ(reg);
3420         udelay(100);
3421
3422         reg = FDI_RX_CTL(pipe);
3423         temp = I915_READ(reg);
3424         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3425
3426         /* Wait for the clocks to turn off. */
3427         POSTING_READ(reg);
3428         udelay(100);
3429 }
3430
3431 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3432 {
3433         struct drm_device *dev = crtc->dev;
3434         struct drm_i915_private *dev_priv = dev->dev_private;
3435         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3436         int pipe = intel_crtc->pipe;
3437         u32 reg, temp;
3438
3439         /* disable CPU FDI tx and PCH FDI rx */
3440         reg = FDI_TX_CTL(pipe);
3441         temp = I915_READ(reg);
3442         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3443         POSTING_READ(reg);
3444
3445         reg = FDI_RX_CTL(pipe);
3446         temp = I915_READ(reg);
3447         temp &= ~(0x7 << 16);
3448         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3449         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3450
3451         POSTING_READ(reg);
3452         udelay(100);
3453
3454         /* Ironlake workaround, disable clock pointer after downing FDI */
3455         if (HAS_PCH_IBX(dev))
3456                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3457
3458         /* still set train pattern 1 */
3459         reg = FDI_TX_CTL(pipe);
3460         temp = I915_READ(reg);
3461         temp &= ~FDI_LINK_TRAIN_NONE;
3462         temp |= FDI_LINK_TRAIN_PATTERN_1;
3463         I915_WRITE(reg, temp);
3464
3465         reg = FDI_RX_CTL(pipe);
3466         temp = I915_READ(reg);
3467         if (HAS_PCH_CPT(dev)) {
3468                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3469                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3470         } else {
3471                 temp &= ~FDI_LINK_TRAIN_NONE;
3472                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3473         }
3474         /* BPC in FDI rx is consistent with that in PIPECONF */
3475         temp &= ~(0x07 << 16);
3476         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3477         I915_WRITE(reg, temp);
3478
3479         POSTING_READ(reg);
3480         udelay(100);
3481 }
3482
3483 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3484 {
3485         struct intel_crtc *crtc;
3486
3487         /* Note that we don't need to be called with mode_config.lock here
3488          * as our list of CRTC objects is static for the lifetime of the
3489          * device and so cannot disappear as we iterate. Similarly, we can
3490          * happily treat the predicates as racy, atomic checks as userspace
3491          * cannot claim and pin a new fb without at least acquring the
3492          * struct_mutex and so serialising with us.
3493          */
3494         for_each_intel_crtc(dev, crtc) {
3495                 if (atomic_read(&crtc->unpin_work_count) == 0)
3496                         continue;
3497
3498                 if (crtc->unpin_work)
3499                         intel_wait_for_vblank(dev, crtc->pipe);
3500
3501                 return true;
3502         }
3503
3504         return false;
3505 }
3506
3507 static void page_flip_completed(struct intel_crtc *intel_crtc)
3508 {
3509         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3510         struct intel_unpin_work *work = intel_crtc->unpin_work;
3511
3512         /* ensure that the unpin work is consistent wrt ->pending. */
3513         smp_rmb();
3514         intel_crtc->unpin_work = NULL;
3515
3516         if (work->event)
3517                 drm_send_vblank_event(intel_crtc->base.dev,
3518                                       intel_crtc->pipe,
3519                                       work->event);
3520
3521         drm_crtc_vblank_put(&intel_crtc->base);
3522
3523         wake_up_all(&dev_priv->pending_flip_queue);
3524         queue_work(dev_priv->wq, &work->work);
3525
3526         trace_i915_flip_complete(intel_crtc->plane,
3527                                  work->pending_flip_obj);
3528 }
3529
3530 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3531 {
3532         struct drm_device *dev = crtc->dev;
3533         struct drm_i915_private *dev_priv = dev->dev_private;
3534
3535         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3536         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3537                                        !intel_crtc_has_pending_flip(crtc),
3538                                        60*HZ) == 0)) {
3539                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3540
3541                 spin_lock_irq(&dev->event_lock);
3542                 if (intel_crtc->unpin_work) {
3543                         WARN_ONCE(1, "Removing stuck page flip\n");
3544                         page_flip_completed(intel_crtc);
3545                 }
3546                 spin_unlock_irq(&dev->event_lock);
3547         }
3548
3549         if (crtc->primary->fb) {
3550                 mutex_lock(&dev->struct_mutex);
3551                 intel_finish_fb(crtc->primary->fb);
3552                 mutex_unlock(&dev->struct_mutex);
3553         }
3554 }
3555
3556 /* Program iCLKIP clock to the desired frequency */
3557 static void lpt_program_iclkip(struct drm_crtc *crtc)
3558 {
3559         struct drm_device *dev = crtc->dev;
3560         struct drm_i915_private *dev_priv = dev->dev_private;
3561         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3562         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3563         u32 temp;
3564
3565         mutex_lock(&dev_priv->dpio_lock);
3566
3567         /* It is necessary to ungate the pixclk gate prior to programming
3568          * the divisors, and gate it back when it is done.
3569          */
3570         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3571
3572         /* Disable SSCCTL */
3573         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3574                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3575                                 SBI_SSCCTL_DISABLE,
3576                         SBI_ICLK);
3577
3578         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3579         if (clock == 20000) {
3580                 auxdiv = 1;
3581                 divsel = 0x41;
3582                 phaseinc = 0x20;
3583         } else {
3584                 /* The iCLK virtual clock root frequency is in MHz,
3585                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3586                  * divisors, it is necessary to divide one by another, so we
3587                  * convert the virtual clock precision to KHz here for higher
3588                  * precision.
3589                  */
3590                 u32 iclk_virtual_root_freq = 172800 * 1000;
3591                 u32 iclk_pi_range = 64;
3592                 u32 desired_divisor, msb_divisor_value, pi_value;
3593
3594                 desired_divisor = (iclk_virtual_root_freq / clock);
3595                 msb_divisor_value = desired_divisor / iclk_pi_range;
3596                 pi_value = desired_divisor % iclk_pi_range;
3597
3598                 auxdiv = 0;
3599                 divsel = msb_divisor_value - 2;
3600                 phaseinc = pi_value;
3601         }
3602
3603         /* This should not happen with any sane values */
3604         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3605                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3606         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3607                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3608
3609         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3610                         clock,
3611                         auxdiv,
3612                         divsel,
3613                         phasedir,
3614                         phaseinc);
3615
3616         /* Program SSCDIVINTPHASE6 */
3617         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3618         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3619         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3620         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3621         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3622         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3623         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3624         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3625
3626         /* Program SSCAUXDIV */
3627         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3628         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3629         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3630         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3631
3632         /* Enable modulator and associated divider */
3633         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3634         temp &= ~SBI_SSCCTL_DISABLE;
3635         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3636
3637         /* Wait for initialization time */
3638         udelay(24);
3639
3640         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3641
3642         mutex_unlock(&dev_priv->dpio_lock);
3643 }
3644
3645 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3646                                                 enum pipe pch_transcoder)
3647 {
3648         struct drm_device *dev = crtc->base.dev;
3649         struct drm_i915_private *dev_priv = dev->dev_private;
3650         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3651
3652         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3653                    I915_READ(HTOTAL(cpu_transcoder)));
3654         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3655                    I915_READ(HBLANK(cpu_transcoder)));
3656         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3657                    I915_READ(HSYNC(cpu_transcoder)));
3658
3659         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3660                    I915_READ(VTOTAL(cpu_transcoder)));
3661         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3662                    I915_READ(VBLANK(cpu_transcoder)));
3663         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3664                    I915_READ(VSYNC(cpu_transcoder)));
3665         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3666                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3667 }
3668
3669 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3670 {
3671         struct drm_i915_private *dev_priv = dev->dev_private;
3672         uint32_t temp;
3673
3674         temp = I915_READ(SOUTH_CHICKEN1);
3675         if (temp & FDI_BC_BIFURCATION_SELECT)
3676                 return;
3677
3678         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3679         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3680
3681         temp |= FDI_BC_BIFURCATION_SELECT;
3682         DRM_DEBUG_KMS("enabling fdi C rx\n");
3683         I915_WRITE(SOUTH_CHICKEN1, temp);
3684         POSTING_READ(SOUTH_CHICKEN1);
3685 }
3686
3687 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3688 {
3689         struct drm_device *dev = intel_crtc->base.dev;
3690         struct drm_i915_private *dev_priv = dev->dev_private;
3691
3692         switch (intel_crtc->pipe) {
3693         case PIPE_A:
3694                 break;
3695         case PIPE_B:
3696                 if (intel_crtc->config.fdi_lanes > 2)
3697                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3698                 else
3699                         cpt_enable_fdi_bc_bifurcation(dev);
3700
3701                 break;
3702         case PIPE_C:
3703                 cpt_enable_fdi_bc_bifurcation(dev);
3704
3705                 break;
3706         default:
3707                 BUG();
3708         }
3709 }
3710
3711 /*
3712  * Enable PCH resources required for PCH ports:
3713  *   - PCH PLLs
3714  *   - FDI training & RX/TX
3715  *   - update transcoder timings
3716  *   - DP transcoding bits
3717  *   - transcoder
3718  */
3719 static void ironlake_pch_enable(struct drm_crtc *crtc)
3720 {
3721         struct drm_device *dev = crtc->dev;
3722         struct drm_i915_private *dev_priv = dev->dev_private;
3723         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3724         int pipe = intel_crtc->pipe;
3725         u32 reg, temp;
3726
3727         assert_pch_transcoder_disabled(dev_priv, pipe);
3728
3729         if (IS_IVYBRIDGE(dev))
3730                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3731
3732         /* Write the TU size bits before fdi link training, so that error
3733          * detection works. */
3734         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3735                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3736
3737         /* For PCH output, training FDI link */
3738         dev_priv->display.fdi_link_train(crtc);
3739
3740         /* We need to program the right clock selection before writing the pixel
3741          * mutliplier into the DPLL. */
3742         if (HAS_PCH_CPT(dev)) {
3743                 u32 sel;
3744
3745                 temp = I915_READ(PCH_DPLL_SEL);
3746                 temp |= TRANS_DPLL_ENABLE(pipe);
3747                 sel = TRANS_DPLLB_SEL(pipe);
3748                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3749                         temp |= sel;
3750                 else
3751                         temp &= ~sel;
3752                 I915_WRITE(PCH_DPLL_SEL, temp);
3753         }
3754
3755         /* XXX: pch pll's can be enabled any time before we enable the PCH
3756          * transcoder, and we actually should do this to not upset any PCH
3757          * transcoder that already use the clock when we share it.
3758          *
3759          * Note that enable_shared_dpll tries to do the right thing, but
3760          * get_shared_dpll unconditionally resets the pll - we need that to have
3761          * the right LVDS enable sequence. */
3762         intel_enable_shared_dpll(intel_crtc);
3763
3764         /* set transcoder timing, panel must allow it */
3765         assert_panel_unlocked(dev_priv, pipe);
3766         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3767
3768         intel_fdi_normal_train(crtc);
3769
3770         /* For PCH DP, enable TRANS_DP_CTL */
3771         if (HAS_PCH_CPT(dev) &&
3772             (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3773              intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_EDP))) {
3774                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3775                 reg = TRANS_DP_CTL(pipe);
3776                 temp = I915_READ(reg);
3777                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3778                           TRANS_DP_SYNC_MASK |
3779                           TRANS_DP_BPC_MASK);
3780                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3781                          TRANS_DP_ENH_FRAMING);
3782                 temp |= bpc << 9; /* same format but at 11:9 */
3783
3784                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3785                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3786                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3787                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3788
3789                 switch (intel_trans_dp_port_sel(crtc)) {
3790                 case PCH_DP_B:
3791                         temp |= TRANS_DP_PORT_SEL_B;
3792                         break;
3793                 case PCH_DP_C:
3794                         temp |= TRANS_DP_PORT_SEL_C;
3795                         break;
3796                 case PCH_DP_D:
3797                         temp |= TRANS_DP_PORT_SEL_D;
3798                         break;
3799                 default:
3800                         BUG();
3801                 }
3802
3803                 I915_WRITE(reg, temp);
3804         }
3805
3806         ironlake_enable_pch_transcoder(dev_priv, pipe);
3807 }
3808
3809 static void lpt_pch_enable(struct drm_crtc *crtc)
3810 {
3811         struct drm_device *dev = crtc->dev;
3812         struct drm_i915_private *dev_priv = dev->dev_private;
3813         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3814         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3815
3816         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3817
3818         lpt_program_iclkip(crtc);
3819
3820         /* Set transcoder timing. */
3821         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3822
3823         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3824 }
3825
3826 void intel_put_shared_dpll(struct intel_crtc *crtc)
3827 {
3828         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3829
3830         if (pll == NULL)
3831                 return;
3832
3833         if (pll->refcount == 0) {
3834                 WARN(1, "bad %s refcount\n", pll->name);
3835                 return;
3836         }
3837
3838         if (--pll->refcount == 0) {
3839                 WARN_ON(pll->on);
3840                 WARN_ON(pll->active);
3841         }
3842
3843         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3844 }
3845
3846 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3847 {
3848         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3849         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3850         enum intel_dpll_id i;
3851
3852         if (pll) {
3853                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3854                               crtc->base.base.id, pll->name);
3855                 intel_put_shared_dpll(crtc);
3856         }
3857
3858         if (HAS_PCH_IBX(dev_priv->dev)) {
3859                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3860                 i = (enum intel_dpll_id) crtc->pipe;
3861                 pll = &dev_priv->shared_dplls[i];
3862
3863                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3864                               crtc->base.base.id, pll->name);
3865
3866                 WARN_ON(pll->refcount);
3867
3868                 goto found;
3869         }
3870
3871         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3872                 pll = &dev_priv->shared_dplls[i];
3873
3874                 /* Only want to check enabled timings first */
3875                 if (pll->refcount == 0)
3876                         continue;
3877
3878                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3879                            sizeof(pll->hw_state)) == 0) {
3880                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3881                                       crtc->base.base.id,
3882                                       pll->name, pll->refcount, pll->active);
3883
3884                         goto found;
3885                 }
3886         }
3887
3888         /* Ok no matching timings, maybe there's a free one? */
3889         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3890                 pll = &dev_priv->shared_dplls[i];
3891                 if (pll->refcount == 0) {
3892                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3893                                       crtc->base.base.id, pll->name);
3894                         goto found;
3895                 }
3896         }
3897
3898         return NULL;
3899
3900 found:
3901         if (pll->refcount == 0)
3902                 pll->hw_state = crtc->config.dpll_hw_state;
3903
3904         crtc->config.shared_dpll = i;
3905         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3906                          pipe_name(crtc->pipe));
3907
3908         pll->refcount++;
3909
3910         return pll;
3911 }
3912
3913 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3914 {
3915         struct drm_i915_private *dev_priv = dev->dev_private;
3916         int dslreg = PIPEDSL(pipe);
3917         u32 temp;
3918
3919         temp = I915_READ(dslreg);
3920         udelay(500);
3921         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3922                 if (wait_for(I915_READ(dslreg) != temp, 5))
3923                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3924         }
3925 }
3926
3927 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3928 {
3929         struct drm_device *dev = crtc->base.dev;
3930         struct drm_i915_private *dev_priv = dev->dev_private;
3931         int pipe = crtc->pipe;
3932
3933         if (crtc->config.pch_pfit.enabled) {
3934                 /* Force use of hard-coded filter coefficients
3935                  * as some pre-programmed values are broken,
3936                  * e.g. x201.
3937                  */
3938                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3939                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3940                                                  PF_PIPE_SEL_IVB(pipe));
3941                 else
3942                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3943                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3944                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3945         }
3946 }
3947
3948 static void intel_enable_planes(struct drm_crtc *crtc)
3949 {
3950         struct drm_device *dev = crtc->dev;
3951         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3952         struct drm_plane *plane;
3953         struct intel_plane *intel_plane;
3954
3955         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3956                 intel_plane = to_intel_plane(plane);
3957                 if (intel_plane->pipe == pipe)
3958                         intel_plane_restore(&intel_plane->base);
3959         }
3960 }
3961
3962 static void intel_disable_planes(struct drm_crtc *crtc)
3963 {
3964         struct drm_device *dev = crtc->dev;
3965         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3966         struct drm_plane *plane;
3967         struct intel_plane *intel_plane;
3968
3969         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3970                 intel_plane = to_intel_plane(plane);
3971                 if (intel_plane->pipe == pipe)
3972                         intel_plane_disable(&intel_plane->base);
3973         }
3974 }
3975
3976 void hsw_enable_ips(struct intel_crtc *crtc)
3977 {
3978         struct drm_device *dev = crtc->base.dev;
3979         struct drm_i915_private *dev_priv = dev->dev_private;
3980
3981         if (!crtc->config.ips_enabled)
3982                 return;
3983
3984         /* We can only enable IPS after we enable a plane and wait for a vblank */
3985         intel_wait_for_vblank(dev, crtc->pipe);
3986
3987         assert_plane_enabled(dev_priv, crtc->plane);
3988         if (IS_BROADWELL(dev)) {
3989                 mutex_lock(&dev_priv->rps.hw_lock);
3990                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3991                 mutex_unlock(&dev_priv->rps.hw_lock);
3992                 /* Quoting Art Runyan: "its not safe to expect any particular
3993                  * value in IPS_CTL bit 31 after enabling IPS through the
3994                  * mailbox." Moreover, the mailbox may return a bogus state,
3995                  * so we need to just enable it and continue on.
3996                  */
3997         } else {
3998                 I915_WRITE(IPS_CTL, IPS_ENABLE);
3999                 /* The bit only becomes 1 in the next vblank, so this wait here
4000                  * is essentially intel_wait_for_vblank. If we don't have this
4001                  * and don't wait for vblanks until the end of crtc_enable, then
4002                  * the HW state readout code will complain that the expected
4003                  * IPS_CTL value is not the one we read. */
4004                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4005                         DRM_ERROR("Timed out waiting for IPS enable\n");
4006         }
4007 }
4008
4009 void hsw_disable_ips(struct intel_crtc *crtc)
4010 {
4011         struct drm_device *dev = crtc->base.dev;
4012         struct drm_i915_private *dev_priv = dev->dev_private;
4013
4014         if (!crtc->config.ips_enabled)
4015                 return;
4016
4017         assert_plane_enabled(dev_priv, crtc->plane);
4018         if (IS_BROADWELL(dev)) {
4019                 mutex_lock(&dev_priv->rps.hw_lock);
4020                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4021                 mutex_unlock(&dev_priv->rps.hw_lock);
4022                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4023                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4024                         DRM_ERROR("Timed out waiting for IPS disable\n");
4025         } else {
4026                 I915_WRITE(IPS_CTL, 0);
4027                 POSTING_READ(IPS_CTL);
4028         }
4029
4030         /* We need to wait for a vblank before we can disable the plane. */
4031         intel_wait_for_vblank(dev, crtc->pipe);
4032 }
4033
4034 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4035 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4036 {
4037         struct drm_device *dev = crtc->dev;
4038         struct drm_i915_private *dev_priv = dev->dev_private;
4039         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4040         enum pipe pipe = intel_crtc->pipe;
4041         int palreg = PALETTE(pipe);
4042         int i;
4043         bool reenable_ips = false;
4044
4045         /* The clocks have to be on to load the palette. */
4046         if (!crtc->enabled || !intel_crtc->active)
4047                 return;
4048
4049         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4050                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4051                         assert_dsi_pll_enabled(dev_priv);
4052                 else
4053                         assert_pll_enabled(dev_priv, pipe);
4054         }
4055
4056         /* use legacy palette for Ironlake */
4057         if (!HAS_GMCH_DISPLAY(dev))
4058                 palreg = LGC_PALETTE(pipe);
4059
4060         /* Workaround : Do not read or write the pipe palette/gamma data while
4061          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4062          */
4063         if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
4064             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4065              GAMMA_MODE_MODE_SPLIT)) {
4066                 hsw_disable_ips(intel_crtc);
4067                 reenable_ips = true;
4068         }
4069
4070         for (i = 0; i < 256; i++) {
4071                 I915_WRITE(palreg + 4 * i,
4072                            (intel_crtc->lut_r[i] << 16) |
4073                            (intel_crtc->lut_g[i] << 8) |
4074                            intel_crtc->lut_b[i]);
4075         }
4076
4077         if (reenable_ips)
4078                 hsw_enable_ips(intel_crtc);
4079 }
4080
4081 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4082 {
4083         if (!enable && intel_crtc->overlay) {
4084                 struct drm_device *dev = intel_crtc->base.dev;
4085                 struct drm_i915_private *dev_priv = dev->dev_private;
4086
4087                 mutex_lock(&dev->struct_mutex);
4088                 dev_priv->mm.interruptible = false;
4089                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4090                 dev_priv->mm.interruptible = true;
4091                 mutex_unlock(&dev->struct_mutex);
4092         }
4093
4094         /* Let userspace switch the overlay on again. In most cases userspace
4095          * has to recompute where to put it anyway.
4096          */
4097 }
4098
4099 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4100 {
4101         struct drm_device *dev = crtc->dev;
4102         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4103         int pipe = intel_crtc->pipe;
4104
4105         intel_enable_primary_hw_plane(crtc->primary, crtc);
4106         intel_enable_planes(crtc);
4107         intel_crtc_update_cursor(crtc, true);
4108         intel_crtc_dpms_overlay(intel_crtc, true);
4109
4110         hsw_enable_ips(intel_crtc);
4111
4112         mutex_lock(&dev->struct_mutex);
4113         intel_update_fbc(dev);
4114         mutex_unlock(&dev->struct_mutex);
4115
4116         /*
4117          * FIXME: Once we grow proper nuclear flip support out of this we need
4118          * to compute the mask of flip planes precisely. For the time being
4119          * consider this a flip from a NULL plane.
4120          */
4121         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4122 }
4123
4124 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4125 {
4126         struct drm_device *dev = crtc->dev;
4127         struct drm_i915_private *dev_priv = dev->dev_private;
4128         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4129         int pipe = intel_crtc->pipe;
4130         int plane = intel_crtc->plane;
4131
4132         intel_crtc_wait_for_pending_flips(crtc);
4133
4134         if (dev_priv->fbc.plane == plane)
4135                 intel_disable_fbc(dev);
4136
4137         hsw_disable_ips(intel_crtc);
4138
4139         intel_crtc_dpms_overlay(intel_crtc, false);
4140         intel_crtc_update_cursor(crtc, false);
4141         intel_disable_planes(crtc);
4142         intel_disable_primary_hw_plane(crtc->primary, crtc);
4143
4144         /*
4145          * FIXME: Once we grow proper nuclear flip support out of this we need
4146          * to compute the mask of flip planes precisely. For the time being
4147          * consider this a flip to a NULL plane.
4148          */
4149         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4150 }
4151
4152 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4153 {
4154         struct drm_device *dev = crtc->dev;
4155         struct drm_i915_private *dev_priv = dev->dev_private;
4156         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4157         struct intel_encoder *encoder;
4158         int pipe = intel_crtc->pipe;
4159
4160         WARN_ON(!crtc->enabled);
4161
4162         if (intel_crtc->active)
4163                 return;
4164
4165         if (intel_crtc->config.has_pch_encoder)
4166                 intel_prepare_shared_dpll(intel_crtc);
4167
4168         if (intel_crtc->config.has_dp_encoder)
4169                 intel_dp_set_m_n(intel_crtc);
4170
4171         intel_set_pipe_timings(intel_crtc);
4172
4173         if (intel_crtc->config.has_pch_encoder) {
4174                 intel_cpu_transcoder_set_m_n(intel_crtc,
4175                                      &intel_crtc->config.fdi_m_n, NULL);
4176         }
4177
4178         ironlake_set_pipeconf(crtc);
4179
4180         intel_crtc->active = true;
4181
4182         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4183         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4184
4185         for_each_encoder_on_crtc(dev, crtc, encoder)
4186                 if (encoder->pre_enable)
4187                         encoder->pre_enable(encoder);
4188
4189         if (intel_crtc->config.has_pch_encoder) {
4190                 /* Note: FDI PLL enabling _must_ be done before we enable the
4191                  * cpu pipes, hence this is separate from all the other fdi/pch
4192                  * enabling. */
4193                 ironlake_fdi_pll_enable(intel_crtc);
4194         } else {
4195                 assert_fdi_tx_disabled(dev_priv, pipe);
4196                 assert_fdi_rx_disabled(dev_priv, pipe);
4197         }
4198
4199         ironlake_pfit_enable(intel_crtc);
4200
4201         /*
4202          * On ILK+ LUT must be loaded before the pipe is running but with
4203          * clocks enabled
4204          */
4205         intel_crtc_load_lut(crtc);
4206
4207         intel_update_watermarks(crtc);
4208         intel_enable_pipe(intel_crtc);
4209
4210         if (intel_crtc->config.has_pch_encoder)
4211                 ironlake_pch_enable(crtc);
4212
4213         for_each_encoder_on_crtc(dev, crtc, encoder)
4214                 encoder->enable(encoder);
4215
4216         if (HAS_PCH_CPT(dev))
4217                 cpt_verify_modeset(dev, intel_crtc->pipe);
4218
4219         assert_vblank_disabled(crtc);
4220         drm_crtc_vblank_on(crtc);
4221
4222         intel_crtc_enable_planes(crtc);
4223 }
4224
4225 /* IPS only exists on ULT machines and is tied to pipe A. */
4226 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4227 {
4228         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4229 }
4230
4231 /*
4232  * This implements the workaround described in the "notes" section of the mode
4233  * set sequence documentation. When going from no pipes or single pipe to
4234  * multiple pipes, and planes are enabled after the pipe, we need to wait at
4235  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4236  */
4237 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4238 {
4239         struct drm_device *dev = crtc->base.dev;
4240         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4241
4242         /* We want to get the other_active_crtc only if there's only 1 other
4243          * active crtc. */
4244         for_each_intel_crtc(dev, crtc_it) {
4245                 if (!crtc_it->active || crtc_it == crtc)
4246                         continue;
4247
4248                 if (other_active_crtc)
4249                         return;
4250
4251                 other_active_crtc = crtc_it;
4252         }
4253         if (!other_active_crtc)
4254                 return;
4255
4256         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4257         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4258 }
4259
4260 static void haswell_crtc_enable(struct drm_crtc *crtc)
4261 {
4262         struct drm_device *dev = crtc->dev;
4263         struct drm_i915_private *dev_priv = dev->dev_private;
4264         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4265         struct intel_encoder *encoder;
4266         int pipe = intel_crtc->pipe;
4267
4268         WARN_ON(!crtc->enabled);
4269
4270         if (intel_crtc->active)
4271                 return;
4272
4273         if (intel_crtc_to_shared_dpll(intel_crtc))
4274                 intel_enable_shared_dpll(intel_crtc);
4275
4276         if (intel_crtc->config.has_dp_encoder)
4277                 intel_dp_set_m_n(intel_crtc);
4278
4279         intel_set_pipe_timings(intel_crtc);
4280
4281         if (intel_crtc->config.cpu_transcoder != TRANSCODER_EDP) {
4282                 I915_WRITE(PIPE_MULT(intel_crtc->config.cpu_transcoder),
4283                            intel_crtc->config.pixel_multiplier - 1);
4284         }
4285
4286         if (intel_crtc->config.has_pch_encoder) {
4287                 intel_cpu_transcoder_set_m_n(intel_crtc,
4288                                      &intel_crtc->config.fdi_m_n, NULL);
4289         }
4290
4291         haswell_set_pipeconf(crtc);
4292
4293         intel_set_pipe_csc(crtc);
4294
4295         intel_crtc->active = true;
4296
4297         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4298         for_each_encoder_on_crtc(dev, crtc, encoder)
4299                 if (encoder->pre_enable)
4300                         encoder->pre_enable(encoder);
4301
4302         if (intel_crtc->config.has_pch_encoder) {
4303                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4304                                                       true);
4305                 dev_priv->display.fdi_link_train(crtc);
4306         }
4307
4308         intel_ddi_enable_pipe_clock(intel_crtc);
4309
4310         ironlake_pfit_enable(intel_crtc);
4311
4312         /*
4313          * On ILK+ LUT must be loaded before the pipe is running but with
4314          * clocks enabled
4315          */
4316         intel_crtc_load_lut(crtc);
4317
4318         intel_ddi_set_pipe_settings(crtc);
4319         intel_ddi_enable_transcoder_func(crtc);
4320
4321         intel_update_watermarks(crtc);
4322         intel_enable_pipe(intel_crtc);
4323
4324         if (intel_crtc->config.has_pch_encoder)
4325                 lpt_pch_enable(crtc);
4326
4327         if (intel_crtc->config.dp_encoder_is_mst)
4328                 intel_ddi_set_vc_payload_alloc(crtc, true);
4329
4330         for_each_encoder_on_crtc(dev, crtc, encoder) {
4331                 encoder->enable(encoder);
4332                 intel_opregion_notify_encoder(encoder, true);
4333         }
4334
4335         assert_vblank_disabled(crtc);
4336         drm_crtc_vblank_on(crtc);
4337
4338         /* If we change the relative order between pipe/planes enabling, we need
4339          * to change the workaround. */
4340         haswell_mode_set_planes_workaround(intel_crtc);
4341         intel_crtc_enable_planes(crtc);
4342 }
4343
4344 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4345 {
4346         struct drm_device *dev = crtc->base.dev;
4347         struct drm_i915_private *dev_priv = dev->dev_private;
4348         int pipe = crtc->pipe;
4349
4350         /* To avoid upsetting the power well on haswell only disable the pfit if
4351          * it's in use. The hw state code will make sure we get this right. */
4352         if (crtc->config.pch_pfit.enabled) {
4353                 I915_WRITE(PF_CTL(pipe), 0);
4354                 I915_WRITE(PF_WIN_POS(pipe), 0);
4355                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4356         }
4357 }
4358
4359 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4360 {
4361         struct drm_device *dev = crtc->dev;
4362         struct drm_i915_private *dev_priv = dev->dev_private;
4363         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4364         struct intel_encoder *encoder;
4365         int pipe = intel_crtc->pipe;
4366         u32 reg, temp;
4367
4368         if (!intel_crtc->active)
4369                 return;
4370
4371         intel_crtc_disable_planes(crtc);
4372
4373         drm_crtc_vblank_off(crtc);
4374         assert_vblank_disabled(crtc);
4375
4376         for_each_encoder_on_crtc(dev, crtc, encoder)
4377                 encoder->disable(encoder);
4378
4379         if (intel_crtc->config.has_pch_encoder)
4380                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4381
4382         intel_disable_pipe(intel_crtc);
4383
4384         ironlake_pfit_disable(intel_crtc);
4385
4386         for_each_encoder_on_crtc(dev, crtc, encoder)
4387                 if (encoder->post_disable)
4388                         encoder->post_disable(encoder);
4389
4390         if (intel_crtc->config.has_pch_encoder) {
4391                 ironlake_fdi_disable(crtc);
4392
4393                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4394                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4395
4396                 if (HAS_PCH_CPT(dev)) {
4397                         /* disable TRANS_DP_CTL */
4398                         reg = TRANS_DP_CTL(pipe);
4399                         temp = I915_READ(reg);
4400                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4401                                   TRANS_DP_PORT_SEL_MASK);
4402                         temp |= TRANS_DP_PORT_SEL_NONE;
4403                         I915_WRITE(reg, temp);
4404
4405                         /* disable DPLL_SEL */
4406                         temp = I915_READ(PCH_DPLL_SEL);
4407                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4408                         I915_WRITE(PCH_DPLL_SEL, temp);
4409                 }
4410
4411                 /* disable PCH DPLL */
4412                 intel_disable_shared_dpll(intel_crtc);
4413
4414                 ironlake_fdi_pll_disable(intel_crtc);
4415         }
4416
4417         intel_crtc->active = false;
4418         intel_update_watermarks(crtc);
4419
4420         mutex_lock(&dev->struct_mutex);
4421         intel_update_fbc(dev);
4422         mutex_unlock(&dev->struct_mutex);
4423 }
4424
4425 static void haswell_crtc_disable(struct drm_crtc *crtc)
4426 {
4427         struct drm_device *dev = crtc->dev;
4428         struct drm_i915_private *dev_priv = dev->dev_private;
4429         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4430         struct intel_encoder *encoder;
4431         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4432
4433         if (!intel_crtc->active)
4434                 return;
4435
4436         intel_crtc_disable_planes(crtc);
4437
4438         drm_crtc_vblank_off(crtc);
4439         assert_vblank_disabled(crtc);
4440
4441         for_each_encoder_on_crtc(dev, crtc, encoder) {
4442                 intel_opregion_notify_encoder(encoder, false);
4443                 encoder->disable(encoder);
4444         }
4445
4446         if (intel_crtc->config.has_pch_encoder)
4447                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4448                                                       false);
4449         intel_disable_pipe(intel_crtc);
4450
4451         if (intel_crtc->config.dp_encoder_is_mst)
4452                 intel_ddi_set_vc_payload_alloc(crtc, false);
4453
4454         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4455
4456         ironlake_pfit_disable(intel_crtc);
4457
4458         intel_ddi_disable_pipe_clock(intel_crtc);
4459
4460         if (intel_crtc->config.has_pch_encoder) {
4461                 lpt_disable_pch_transcoder(dev_priv);
4462                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4463                                                       true);
4464                 intel_ddi_fdi_disable(crtc);
4465         }
4466
4467         for_each_encoder_on_crtc(dev, crtc, encoder)
4468                 if (encoder->post_disable)
4469                         encoder->post_disable(encoder);
4470
4471         intel_crtc->active = false;
4472         intel_update_watermarks(crtc);
4473
4474         mutex_lock(&dev->struct_mutex);
4475         intel_update_fbc(dev);
4476         mutex_unlock(&dev->struct_mutex);
4477
4478         if (intel_crtc_to_shared_dpll(intel_crtc))
4479                 intel_disable_shared_dpll(intel_crtc);
4480 }
4481
4482 static void ironlake_crtc_off(struct drm_crtc *crtc)
4483 {
4484         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4485         intel_put_shared_dpll(intel_crtc);
4486 }
4487
4488
4489 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4490 {
4491         struct drm_device *dev = crtc->base.dev;
4492         struct drm_i915_private *dev_priv = dev->dev_private;
4493         struct intel_crtc_config *pipe_config = &crtc->config;
4494
4495         if (!crtc->config.gmch_pfit.control)
4496                 return;
4497
4498         /*
4499          * The panel fitter should only be adjusted whilst the pipe is disabled,
4500          * according to register description and PRM.
4501          */
4502         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4503         assert_pipe_disabled(dev_priv, crtc->pipe);
4504
4505         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4506         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4507
4508         /* Border color in case we don't scale up to the full screen. Black by
4509          * default, change to something else for debugging. */
4510         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4511 }
4512
4513 static enum intel_display_power_domain port_to_power_domain(enum port port)
4514 {
4515         switch (port) {
4516         case PORT_A:
4517                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4518         case PORT_B:
4519                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4520         case PORT_C:
4521                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4522         case PORT_D:
4523                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4524         default:
4525                 WARN_ON_ONCE(1);
4526                 return POWER_DOMAIN_PORT_OTHER;
4527         }
4528 }
4529
4530 #define for_each_power_domain(domain, mask)                             \
4531         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4532                 if ((1 << (domain)) & (mask))
4533
4534 enum intel_display_power_domain
4535 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4536 {
4537         struct drm_device *dev = intel_encoder->base.dev;
4538         struct intel_digital_port *intel_dig_port;
4539
4540         switch (intel_encoder->type) {
4541         case INTEL_OUTPUT_UNKNOWN:
4542                 /* Only DDI platforms should ever use this output type */
4543                 WARN_ON_ONCE(!HAS_DDI(dev));
4544         case INTEL_OUTPUT_DISPLAYPORT:
4545         case INTEL_OUTPUT_HDMI:
4546         case INTEL_OUTPUT_EDP:
4547                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4548                 return port_to_power_domain(intel_dig_port->port);
4549         case INTEL_OUTPUT_DP_MST:
4550                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4551                 return port_to_power_domain(intel_dig_port->port);
4552         case INTEL_OUTPUT_ANALOG:
4553                 return POWER_DOMAIN_PORT_CRT;
4554         case INTEL_OUTPUT_DSI:
4555                 return POWER_DOMAIN_PORT_DSI;
4556         default:
4557                 return POWER_DOMAIN_PORT_OTHER;
4558         }
4559 }
4560
4561 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4562 {
4563         struct drm_device *dev = crtc->dev;
4564         struct intel_encoder *intel_encoder;
4565         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4566         enum pipe pipe = intel_crtc->pipe;
4567         unsigned long mask;
4568         enum transcoder transcoder;
4569
4570         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4571
4572         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4573         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4574         if (intel_crtc->config.pch_pfit.enabled ||
4575             intel_crtc->config.pch_pfit.force_thru)
4576                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4577
4578         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4579                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4580
4581         return mask;
4582 }
4583
4584 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4585 {
4586         struct drm_i915_private *dev_priv = dev->dev_private;
4587         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4588         struct intel_crtc *crtc;
4589
4590         /*
4591          * First get all needed power domains, then put all unneeded, to avoid
4592          * any unnecessary toggling of the power wells.
4593          */
4594         for_each_intel_crtc(dev, crtc) {
4595                 enum intel_display_power_domain domain;
4596
4597                 if (!crtc->base.enabled)
4598                         continue;
4599
4600                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4601
4602                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4603                         intel_display_power_get(dev_priv, domain);
4604         }
4605
4606         for_each_intel_crtc(dev, crtc) {
4607                 enum intel_display_power_domain domain;
4608
4609                 for_each_power_domain(domain, crtc->enabled_power_domains)
4610                         intel_display_power_put(dev_priv, domain);
4611
4612                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4613         }
4614
4615         intel_display_set_init_power(dev_priv, false);
4616 }
4617
4618 /* returns HPLL frequency in kHz */
4619 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4620 {
4621         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4622
4623         /* Obtain SKU information */
4624         mutex_lock(&dev_priv->dpio_lock);
4625         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4626                 CCK_FUSE_HPLL_FREQ_MASK;
4627         mutex_unlock(&dev_priv->dpio_lock);
4628
4629         return vco_freq[hpll_freq] * 1000;
4630 }
4631
4632 static void vlv_update_cdclk(struct drm_device *dev)
4633 {
4634         struct drm_i915_private *dev_priv = dev->dev_private;
4635
4636         dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4637         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4638                          dev_priv->vlv_cdclk_freq);
4639
4640         /*
4641          * Program the gmbus_freq based on the cdclk frequency.
4642          * BSpec erroneously claims we should aim for 4MHz, but
4643          * in fact 1MHz is the correct frequency.
4644          */
4645         I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
4646 }
4647
4648 /* Adjust CDclk dividers to allow high res or save power if possible */
4649 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4650 {
4651         struct drm_i915_private *dev_priv = dev->dev_private;
4652         u32 val, cmd;
4653
4654         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4655
4656         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4657                 cmd = 2;
4658         else if (cdclk == 266667)
4659                 cmd = 1;
4660         else
4661                 cmd = 0;
4662
4663         mutex_lock(&dev_priv->rps.hw_lock);
4664         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4665         val &= ~DSPFREQGUAR_MASK;
4666         val |= (cmd << DSPFREQGUAR_SHIFT);
4667         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4668         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4669                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4670                      50)) {
4671                 DRM_ERROR("timed out waiting for CDclk change\n");
4672         }
4673         mutex_unlock(&dev_priv->rps.hw_lock);
4674
4675         if (cdclk == 400000) {
4676                 u32 divider, vco;
4677
4678                 vco = valleyview_get_vco(dev_priv);
4679                 divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1;
4680
4681                 mutex_lock(&dev_priv->dpio_lock);
4682                 /* adjust cdclk divider */
4683                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4684                 val &= ~DISPLAY_FREQUENCY_VALUES;
4685                 val |= divider;
4686                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4687
4688                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4689                               DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4690                              50))
4691                         DRM_ERROR("timed out waiting for CDclk change\n");
4692                 mutex_unlock(&dev_priv->dpio_lock);
4693         }
4694
4695         mutex_lock(&dev_priv->dpio_lock);
4696         /* adjust self-refresh exit latency value */
4697         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4698         val &= ~0x7f;
4699
4700         /*
4701          * For high bandwidth configs, we set a higher latency in the bunit
4702          * so that the core display fetch happens in time to avoid underruns.
4703          */
4704         if (cdclk == 400000)
4705                 val |= 4500 / 250; /* 4.5 usec */
4706         else
4707                 val |= 3000 / 250; /* 3.0 usec */
4708         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4709         mutex_unlock(&dev_priv->dpio_lock);
4710
4711         vlv_update_cdclk(dev);
4712 }
4713
4714 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4715 {
4716         struct drm_i915_private *dev_priv = dev->dev_private;
4717         u32 val, cmd;
4718
4719         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4720
4721         switch (cdclk) {
4722         case 400000:
4723                 cmd = 3;
4724                 break;
4725         case 333333:
4726         case 320000:
4727                 cmd = 2;
4728                 break;
4729         case 266667:
4730                 cmd = 1;
4731                 break;
4732         case 200000:
4733                 cmd = 0;
4734                 break;
4735         default:
4736                 WARN_ON(1);
4737                 return;
4738         }
4739
4740         mutex_lock(&dev_priv->rps.hw_lock);
4741         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4742         val &= ~DSPFREQGUAR_MASK_CHV;
4743         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4744         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4745         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4746                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4747                      50)) {
4748                 DRM_ERROR("timed out waiting for CDclk change\n");
4749         }
4750         mutex_unlock(&dev_priv->rps.hw_lock);
4751
4752         vlv_update_cdclk(dev);
4753 }
4754
4755 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4756                                  int max_pixclk)
4757 {
4758         int vco = valleyview_get_vco(dev_priv);
4759         int freq_320 = (vco <<  1) % 320000 != 0 ? 333333 : 320000;
4760
4761         /* FIXME: Punit isn't quite ready yet */
4762         if (IS_CHERRYVIEW(dev_priv->dev))
4763                 return 400000;
4764
4765         /*
4766          * Really only a few cases to deal with, as only 4 CDclks are supported:
4767          *   200MHz
4768          *   267MHz
4769          *   320/333MHz (depends on HPLL freq)
4770          *   400MHz
4771          * So we check to see whether we're above 90% of the lower bin and
4772          * adjust if needed.
4773          *
4774          * We seem to get an unstable or solid color picture at 200MHz.
4775          * Not sure what's wrong. For now use 200MHz only when all pipes
4776          * are off.
4777          */
4778         if (max_pixclk > freq_320*9/10)
4779                 return 400000;
4780         else if (max_pixclk > 266667*9/10)
4781                 return freq_320;
4782         else if (max_pixclk > 0)
4783                 return 266667;
4784         else
4785                 return 200000;
4786 }
4787
4788 /* compute the max pixel clock for new configuration */
4789 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4790 {
4791         struct drm_device *dev = dev_priv->dev;
4792         struct intel_crtc *intel_crtc;
4793         int max_pixclk = 0;
4794
4795         for_each_intel_crtc(dev, intel_crtc) {
4796                 if (intel_crtc->new_enabled)
4797                         max_pixclk = max(max_pixclk,
4798                                          intel_crtc->new_config->adjusted_mode.crtc_clock);
4799         }
4800
4801         return max_pixclk;
4802 }
4803
4804 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4805                                             unsigned *prepare_pipes)
4806 {
4807         struct drm_i915_private *dev_priv = dev->dev_private;
4808         struct intel_crtc *intel_crtc;
4809         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4810
4811         if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4812             dev_priv->vlv_cdclk_freq)
4813                 return;
4814
4815         /* disable/enable all currently active pipes while we change cdclk */
4816         for_each_intel_crtc(dev, intel_crtc)
4817                 if (intel_crtc->base.enabled)
4818                         *prepare_pipes |= (1 << intel_crtc->pipe);
4819 }
4820
4821 static void valleyview_modeset_global_resources(struct drm_device *dev)
4822 {
4823         struct drm_i915_private *dev_priv = dev->dev_private;
4824         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4825         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4826
4827         if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4828                 if (IS_CHERRYVIEW(dev))
4829                         cherryview_set_cdclk(dev, req_cdclk);
4830                 else
4831                         valleyview_set_cdclk(dev, req_cdclk);
4832         }
4833
4834         modeset_update_crtc_power_domains(dev);
4835 }
4836
4837 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4838 {
4839         struct drm_device *dev = crtc->dev;
4840         struct drm_i915_private *dev_priv = to_i915(dev);
4841         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4842         struct intel_encoder *encoder;
4843         int pipe = intel_crtc->pipe;
4844         bool is_dsi;
4845
4846         WARN_ON(!crtc->enabled);
4847
4848         if (intel_crtc->active)
4849                 return;
4850
4851         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
4852
4853         if (!is_dsi) {
4854                 if (IS_CHERRYVIEW(dev))
4855                         chv_prepare_pll(intel_crtc, &intel_crtc->config);
4856                 else
4857                         vlv_prepare_pll(intel_crtc, &intel_crtc->config);
4858         }
4859
4860         if (intel_crtc->config.has_dp_encoder)
4861                 intel_dp_set_m_n(intel_crtc);
4862
4863         intel_set_pipe_timings(intel_crtc);
4864
4865         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
4866                 struct drm_i915_private *dev_priv = dev->dev_private;
4867
4868                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
4869                 I915_WRITE(CHV_CANVAS(pipe), 0);
4870         }
4871
4872         i9xx_set_pipeconf(intel_crtc);
4873
4874         intel_crtc->active = true;
4875
4876         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4877
4878         for_each_encoder_on_crtc(dev, crtc, encoder)
4879                 if (encoder->pre_pll_enable)
4880                         encoder->pre_pll_enable(encoder);
4881
4882         if (!is_dsi) {
4883                 if (IS_CHERRYVIEW(dev))
4884                         chv_enable_pll(intel_crtc, &intel_crtc->config);
4885                 else
4886                         vlv_enable_pll(intel_crtc, &intel_crtc->config);
4887         }
4888
4889         for_each_encoder_on_crtc(dev, crtc, encoder)
4890                 if (encoder->pre_enable)
4891                         encoder->pre_enable(encoder);
4892
4893         i9xx_pfit_enable(intel_crtc);
4894
4895         intel_crtc_load_lut(crtc);
4896
4897         intel_update_watermarks(crtc);
4898         intel_enable_pipe(intel_crtc);
4899
4900         for_each_encoder_on_crtc(dev, crtc, encoder)
4901                 encoder->enable(encoder);
4902
4903         assert_vblank_disabled(crtc);
4904         drm_crtc_vblank_on(crtc);
4905
4906         intel_crtc_enable_planes(crtc);
4907
4908         /* Underruns don't raise interrupts, so check manually. */
4909         i9xx_check_fifo_underruns(dev_priv);
4910 }
4911
4912 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4913 {
4914         struct drm_device *dev = crtc->base.dev;
4915         struct drm_i915_private *dev_priv = dev->dev_private;
4916
4917         I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4918         I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4919 }
4920
4921 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4922 {
4923         struct drm_device *dev = crtc->dev;
4924         struct drm_i915_private *dev_priv = to_i915(dev);
4925         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4926         struct intel_encoder *encoder;
4927         int pipe = intel_crtc->pipe;
4928
4929         WARN_ON(!crtc->enabled);
4930
4931         if (intel_crtc->active)
4932                 return;
4933
4934         i9xx_set_pll_dividers(intel_crtc);
4935
4936         if (intel_crtc->config.has_dp_encoder)
4937                 intel_dp_set_m_n(intel_crtc);
4938
4939         intel_set_pipe_timings(intel_crtc);
4940
4941         i9xx_set_pipeconf(intel_crtc);
4942
4943         intel_crtc->active = true;
4944
4945         if (!IS_GEN2(dev))
4946                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4947
4948         for_each_encoder_on_crtc(dev, crtc, encoder)
4949                 if (encoder->pre_enable)
4950                         encoder->pre_enable(encoder);
4951
4952         i9xx_enable_pll(intel_crtc);
4953
4954         i9xx_pfit_enable(intel_crtc);
4955
4956         intel_crtc_load_lut(crtc);
4957
4958         intel_update_watermarks(crtc);
4959         intel_enable_pipe(intel_crtc);
4960
4961         for_each_encoder_on_crtc(dev, crtc, encoder)
4962                 encoder->enable(encoder);
4963
4964         assert_vblank_disabled(crtc);
4965         drm_crtc_vblank_on(crtc);
4966
4967         intel_crtc_enable_planes(crtc);
4968
4969         /*
4970          * Gen2 reports pipe underruns whenever all planes are disabled.
4971          * So don't enable underrun reporting before at least some planes
4972          * are enabled.
4973          * FIXME: Need to fix the logic to work when we turn off all planes
4974          * but leave the pipe running.
4975          */
4976         if (IS_GEN2(dev))
4977                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4978
4979         /* Underruns don't raise interrupts, so check manually. */
4980         i9xx_check_fifo_underruns(dev_priv);
4981 }
4982
4983 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4984 {
4985         struct drm_device *dev = crtc->base.dev;
4986         struct drm_i915_private *dev_priv = dev->dev_private;
4987
4988         if (!crtc->config.gmch_pfit.control)
4989                 return;
4990
4991         assert_pipe_disabled(dev_priv, crtc->pipe);
4992
4993         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4994                          I915_READ(PFIT_CONTROL));
4995         I915_WRITE(PFIT_CONTROL, 0);
4996 }
4997
4998 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4999 {
5000         struct drm_device *dev = crtc->dev;
5001         struct drm_i915_private *dev_priv = dev->dev_private;
5002         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5003         struct intel_encoder *encoder;
5004         int pipe = intel_crtc->pipe;
5005
5006         if (!intel_crtc->active)
5007                 return;
5008
5009         /*
5010          * Gen2 reports pipe underruns whenever all planes are disabled.
5011          * So diasble underrun reporting before all the planes get disabled.
5012          * FIXME: Need to fix the logic to work when we turn off all planes
5013          * but leave the pipe running.
5014          */
5015         if (IS_GEN2(dev))
5016                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5017
5018         /*
5019          * Vblank time updates from the shadow to live plane control register
5020          * are blocked if the memory self-refresh mode is active at that
5021          * moment. So to make sure the plane gets truly disabled, disable
5022          * first the self-refresh mode. The self-refresh enable bit in turn
5023          * will be checked/applied by the HW only at the next frame start
5024          * event which is after the vblank start event, so we need to have a
5025          * wait-for-vblank between disabling the plane and the pipe.
5026          */
5027         intel_set_memory_cxsr(dev_priv, false);
5028         intel_crtc_disable_planes(crtc);
5029
5030         /*
5031          * On gen2 planes are double buffered but the pipe isn't, so we must
5032          * wait for planes to fully turn off before disabling the pipe.
5033          * We also need to wait on all gmch platforms because of the
5034          * self-refresh mode constraint explained above.
5035          */
5036         intel_wait_for_vblank(dev, pipe);
5037
5038         drm_crtc_vblank_off(crtc);
5039         assert_vblank_disabled(crtc);
5040
5041         for_each_encoder_on_crtc(dev, crtc, encoder)
5042                 encoder->disable(encoder);
5043
5044         intel_disable_pipe(intel_crtc);
5045
5046         i9xx_pfit_disable(intel_crtc);
5047
5048         for_each_encoder_on_crtc(dev, crtc, encoder)
5049                 if (encoder->post_disable)
5050                         encoder->post_disable(encoder);
5051
5052         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5053                 if (IS_CHERRYVIEW(dev))
5054                         chv_disable_pll(dev_priv, pipe);
5055                 else if (IS_VALLEYVIEW(dev))
5056                         vlv_disable_pll(dev_priv, pipe);
5057                 else
5058                         i9xx_disable_pll(intel_crtc);
5059         }
5060
5061         if (!IS_GEN2(dev))
5062                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5063
5064         intel_crtc->active = false;
5065         intel_update_watermarks(crtc);
5066
5067         mutex_lock(&dev->struct_mutex);
5068         intel_update_fbc(dev);
5069         mutex_unlock(&dev->struct_mutex);
5070 }
5071
5072 static void i9xx_crtc_off(struct drm_crtc *crtc)
5073 {
5074 }
5075
5076 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
5077                                     bool enabled)
5078 {
5079         struct drm_device *dev = crtc->dev;
5080         struct drm_i915_master_private *master_priv;
5081         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5082         int pipe = intel_crtc->pipe;
5083
5084         if (!dev->primary->master)
5085                 return;
5086
5087         master_priv = dev->primary->master->driver_priv;
5088         if (!master_priv->sarea_priv)
5089                 return;
5090
5091         switch (pipe) {
5092         case 0:
5093                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
5094                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
5095                 break;
5096         case 1:
5097                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
5098                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
5099                 break;
5100         default:
5101                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
5102                 break;
5103         }
5104 }
5105
5106 /* Master function to enable/disable CRTC and corresponding power wells */
5107 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5108 {
5109         struct drm_device *dev = crtc->dev;
5110         struct drm_i915_private *dev_priv = dev->dev_private;
5111         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5112         enum intel_display_power_domain domain;
5113         unsigned long domains;
5114
5115         if (enable) {
5116                 if (!intel_crtc->active) {
5117                         domains = get_crtc_power_domains(crtc);
5118                         for_each_power_domain(domain, domains)
5119                                 intel_display_power_get(dev_priv, domain);
5120                         intel_crtc->enabled_power_domains = domains;
5121
5122                         dev_priv->display.crtc_enable(crtc);
5123                 }
5124         } else {
5125                 if (intel_crtc->active) {
5126                         dev_priv->display.crtc_disable(crtc);
5127
5128                         domains = intel_crtc->enabled_power_domains;
5129                         for_each_power_domain(domain, domains)
5130                                 intel_display_power_put(dev_priv, domain);
5131                         intel_crtc->enabled_power_domains = 0;
5132                 }
5133         }
5134 }
5135
5136 /**
5137  * Sets the power management mode of the pipe and plane.
5138  */
5139 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5140 {
5141         struct drm_device *dev = crtc->dev;
5142         struct intel_encoder *intel_encoder;
5143         bool enable = false;
5144
5145         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5146                 enable |= intel_encoder->connectors_active;
5147
5148         intel_crtc_control(crtc, enable);
5149
5150         intel_crtc_update_sarea(crtc, enable);
5151 }
5152
5153 static void intel_crtc_disable(struct drm_crtc *crtc)
5154 {
5155         struct drm_device *dev = crtc->dev;
5156         struct drm_connector *connector;
5157         struct drm_i915_private *dev_priv = dev->dev_private;
5158         struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
5159         enum pipe pipe = to_intel_crtc(crtc)->pipe;
5160
5161         /* crtc should still be enabled when we disable it. */
5162         WARN_ON(!crtc->enabled);
5163
5164         dev_priv->display.crtc_disable(crtc);
5165         intel_crtc_update_sarea(crtc, false);
5166         dev_priv->display.off(crtc);
5167
5168         if (crtc->primary->fb) {
5169                 mutex_lock(&dev->struct_mutex);
5170                 intel_unpin_fb_obj(old_obj);
5171                 i915_gem_track_fb(old_obj, NULL,
5172                                   INTEL_FRONTBUFFER_PRIMARY(pipe));
5173                 mutex_unlock(&dev->struct_mutex);
5174                 crtc->primary->fb = NULL;
5175         }
5176
5177         /* Update computed state. */
5178         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5179                 if (!connector->encoder || !connector->encoder->crtc)
5180                         continue;
5181
5182                 if (connector->encoder->crtc != crtc)
5183                         continue;
5184
5185                 connector->dpms = DRM_MODE_DPMS_OFF;
5186                 to_intel_encoder(connector->encoder)->connectors_active = false;
5187         }
5188 }
5189
5190 void intel_encoder_destroy(struct drm_encoder *encoder)
5191 {
5192         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5193
5194         drm_encoder_cleanup(encoder);
5195         kfree(intel_encoder);
5196 }
5197
5198 /* Simple dpms helper for encoders with just one connector, no cloning and only
5199  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5200  * state of the entire output pipe. */
5201 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5202 {
5203         if (mode == DRM_MODE_DPMS_ON) {
5204                 encoder->connectors_active = true;
5205
5206                 intel_crtc_update_dpms(encoder->base.crtc);
5207         } else {
5208                 encoder->connectors_active = false;
5209
5210                 intel_crtc_update_dpms(encoder->base.crtc);
5211         }
5212 }
5213
5214 /* Cross check the actual hw state with our own modeset state tracking (and it's
5215  * internal consistency). */
5216 static void intel_connector_check_state(struct intel_connector *connector)
5217 {
5218         if (connector->get_hw_state(connector)) {
5219                 struct intel_encoder *encoder = connector->encoder;
5220                 struct drm_crtc *crtc;
5221                 bool encoder_enabled;
5222                 enum pipe pipe;
5223
5224                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5225                               connector->base.base.id,
5226                               connector->base.name);
5227
5228                 /* there is no real hw state for MST connectors */
5229                 if (connector->mst_port)
5230                         return;
5231
5232                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5233                      "wrong connector dpms state\n");
5234                 WARN(connector->base.encoder != &encoder->base,
5235                      "active connector not linked to encoder\n");
5236
5237                 if (encoder) {
5238                         WARN(!encoder->connectors_active,
5239                              "encoder->connectors_active not set\n");
5240
5241                         encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5242                         WARN(!encoder_enabled, "encoder not enabled\n");
5243                         if (WARN_ON(!encoder->base.crtc))
5244                                 return;
5245
5246                         crtc = encoder->base.crtc;
5247
5248                         WARN(!crtc->enabled, "crtc not enabled\n");
5249                         WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5250                         WARN(pipe != to_intel_crtc(crtc)->pipe,
5251                              "encoder active on the wrong pipe\n");
5252                 }
5253         }
5254 }
5255
5256 /* Even simpler default implementation, if there's really no special case to
5257  * consider. */
5258 void intel_connector_dpms(struct drm_connector *connector, int mode)
5259 {
5260         /* All the simple cases only support two dpms states. */
5261         if (mode != DRM_MODE_DPMS_ON)
5262                 mode = DRM_MODE_DPMS_OFF;
5263
5264         if (mode == connector->dpms)
5265                 return;
5266
5267         connector->dpms = mode;
5268
5269         /* Only need to change hw state when actually enabled */
5270         if (connector->encoder)
5271                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5272
5273         intel_modeset_check_state(connector->dev);
5274 }
5275
5276 /* Simple connector->get_hw_state implementation for encoders that support only
5277  * one connector and no cloning and hence the encoder state determines the state
5278  * of the connector. */
5279 bool intel_connector_get_hw_state(struct intel_connector *connector)
5280 {
5281         enum pipe pipe = 0;
5282         struct intel_encoder *encoder = connector->encoder;
5283
5284         return encoder->get_hw_state(encoder, &pipe);
5285 }
5286
5287 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5288                                      struct intel_crtc_config *pipe_config)
5289 {
5290         struct drm_i915_private *dev_priv = dev->dev_private;
5291         struct intel_crtc *pipe_B_crtc =
5292                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5293
5294         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5295                       pipe_name(pipe), pipe_config->fdi_lanes);
5296         if (pipe_config->fdi_lanes > 4) {
5297                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5298                               pipe_name(pipe), pipe_config->fdi_lanes);
5299                 return false;
5300         }
5301
5302         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5303                 if (pipe_config->fdi_lanes > 2) {
5304                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5305                                       pipe_config->fdi_lanes);
5306                         return false;
5307                 } else {
5308                         return true;
5309                 }
5310         }
5311
5312         if (INTEL_INFO(dev)->num_pipes == 2)
5313                 return true;
5314
5315         /* Ivybridge 3 pipe is really complicated */
5316         switch (pipe) {
5317         case PIPE_A:
5318                 return true;
5319         case PIPE_B:
5320                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5321                     pipe_config->fdi_lanes > 2) {
5322                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5323                                       pipe_name(pipe), pipe_config->fdi_lanes);
5324                         return false;
5325                 }
5326                 return true;
5327         case PIPE_C:
5328                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5329                     pipe_B_crtc->config.fdi_lanes <= 2) {
5330                         if (pipe_config->fdi_lanes > 2) {
5331                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5332                                               pipe_name(pipe), pipe_config->fdi_lanes);
5333                                 return false;
5334                         }
5335                 } else {
5336                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5337                         return false;
5338                 }
5339                 return true;
5340         default:
5341                 BUG();
5342         }
5343 }
5344
5345 #define RETRY 1
5346 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5347                                        struct intel_crtc_config *pipe_config)
5348 {
5349         struct drm_device *dev = intel_crtc->base.dev;
5350         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5351         int lane, link_bw, fdi_dotclock;
5352         bool setup_ok, needs_recompute = false;
5353
5354 retry:
5355         /* FDI is a binary signal running at ~2.7GHz, encoding
5356          * each output octet as 10 bits. The actual frequency
5357          * is stored as a divider into a 100MHz clock, and the
5358          * mode pixel clock is stored in units of 1KHz.
5359          * Hence the bw of each lane in terms of the mode signal
5360          * is:
5361          */
5362         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5363
5364         fdi_dotclock = adjusted_mode->crtc_clock;
5365
5366         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5367                                            pipe_config->pipe_bpp);
5368
5369         pipe_config->fdi_lanes = lane;
5370
5371         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5372                                link_bw, &pipe_config->fdi_m_n);
5373
5374         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5375                                             intel_crtc->pipe, pipe_config);
5376         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5377                 pipe_config->pipe_bpp -= 2*3;
5378                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5379                               pipe_config->pipe_bpp);
5380                 needs_recompute = true;
5381                 pipe_config->bw_constrained = true;
5382
5383                 goto retry;
5384         }
5385
5386         if (needs_recompute)
5387                 return RETRY;
5388
5389         return setup_ok ? 0 : -EINVAL;
5390 }
5391
5392 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5393                                    struct intel_crtc_config *pipe_config)
5394 {
5395         pipe_config->ips_enabled = i915.enable_ips &&
5396                                    hsw_crtc_supports_ips(crtc) &&
5397                                    pipe_config->pipe_bpp <= 24;
5398 }
5399
5400 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5401                                      struct intel_crtc_config *pipe_config)
5402 {
5403         struct drm_device *dev = crtc->base.dev;
5404         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5405
5406         /* FIXME should check pixel clock limits on all platforms */
5407         if (INTEL_INFO(dev)->gen < 4) {
5408                 struct drm_i915_private *dev_priv = dev->dev_private;
5409                 int clock_limit =
5410                         dev_priv->display.get_display_clock_speed(dev);
5411
5412                 /*
5413                  * Enable pixel doubling when the dot clock
5414                  * is > 90% of the (display) core speed.
5415                  *
5416                  * GDG double wide on either pipe,
5417                  * otherwise pipe A only.
5418                  */
5419                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5420                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5421                         clock_limit *= 2;
5422                         pipe_config->double_wide = true;
5423                 }
5424
5425                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5426                         return -EINVAL;
5427         }
5428
5429         /*
5430          * Pipe horizontal size must be even in:
5431          * - DVO ganged mode
5432          * - LVDS dual channel mode
5433          * - Double wide pipe
5434          */
5435         if ((intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5436              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5437                 pipe_config->pipe_src_w &= ~1;
5438
5439         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5440          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5441          */
5442         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5443                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5444                 return -EINVAL;
5445
5446         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5447                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5448         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5449                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5450                  * for lvds. */
5451                 pipe_config->pipe_bpp = 8*3;
5452         }
5453
5454         if (HAS_IPS(dev))
5455                 hsw_compute_ips_config(crtc, pipe_config);
5456
5457         /*
5458          * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the
5459          * old clock survives for now.
5460          */
5461         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev) || HAS_DDI(dev))
5462                 pipe_config->shared_dpll = crtc->config.shared_dpll;
5463
5464         if (pipe_config->has_pch_encoder)
5465                 return ironlake_fdi_compute_config(crtc, pipe_config);
5466
5467         return 0;
5468 }
5469
5470 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5471 {
5472         struct drm_i915_private *dev_priv = dev->dev_private;
5473         int vco = valleyview_get_vco(dev_priv);
5474         u32 val;
5475         int divider;
5476
5477         /* FIXME: Punit isn't quite ready yet */
5478         if (IS_CHERRYVIEW(dev))
5479                 return 400000;
5480
5481         mutex_lock(&dev_priv->dpio_lock);
5482         val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5483         mutex_unlock(&dev_priv->dpio_lock);
5484
5485         divider = val & DISPLAY_FREQUENCY_VALUES;
5486
5487         WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5488              (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5489              "cdclk change in progress\n");
5490
5491         return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
5492 }
5493
5494 static int i945_get_display_clock_speed(struct drm_device *dev)
5495 {
5496         return 400000;
5497 }
5498
5499 static int i915_get_display_clock_speed(struct drm_device *dev)
5500 {
5501         return 333000;
5502 }
5503
5504 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5505 {
5506         return 200000;
5507 }
5508
5509 static int pnv_get_display_clock_speed(struct drm_device *dev)
5510 {
5511         u16 gcfgc = 0;
5512
5513         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5514
5515         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5516         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5517                 return 267000;
5518         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5519                 return 333000;
5520         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5521                 return 444000;
5522         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5523                 return 200000;
5524         default:
5525                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5526         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5527                 return 133000;
5528         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5529                 return 167000;
5530         }
5531 }
5532
5533 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5534 {
5535         u16 gcfgc = 0;
5536
5537         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5538
5539         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5540                 return 133000;
5541         else {
5542                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5543                 case GC_DISPLAY_CLOCK_333_MHZ:
5544                         return 333000;
5545                 default:
5546                 case GC_DISPLAY_CLOCK_190_200_MHZ:
5547                         return 190000;
5548                 }
5549         }
5550 }
5551
5552 static int i865_get_display_clock_speed(struct drm_device *dev)
5553 {
5554         return 266000;
5555 }
5556
5557 static int i855_get_display_clock_speed(struct drm_device *dev)
5558 {
5559         u16 hpllcc = 0;
5560         /* Assume that the hardware is in the high speed state.  This
5561          * should be the default.
5562          */
5563         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5564         case GC_CLOCK_133_200:
5565         case GC_CLOCK_100_200:
5566                 return 200000;
5567         case GC_CLOCK_166_250:
5568                 return 250000;
5569         case GC_CLOCK_100_133:
5570                 return 133000;
5571         }
5572
5573         /* Shouldn't happen */
5574         return 0;
5575 }
5576
5577 static int i830_get_display_clock_speed(struct drm_device *dev)
5578 {
5579         return 133000;
5580 }
5581
5582 static void
5583 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5584 {
5585         while (*num > DATA_LINK_M_N_MASK ||
5586                *den > DATA_LINK_M_N_MASK) {
5587                 *num >>= 1;
5588                 *den >>= 1;
5589         }
5590 }
5591
5592 static void compute_m_n(unsigned int m, unsigned int n,
5593                         uint32_t *ret_m, uint32_t *ret_n)
5594 {
5595         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5596         *ret_m = div_u64((uint64_t) m * *ret_n, n);
5597         intel_reduce_m_n_ratio(ret_m, ret_n);
5598 }
5599
5600 void
5601 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5602                        int pixel_clock, int link_clock,
5603                        struct intel_link_m_n *m_n)
5604 {
5605         m_n->tu = 64;
5606
5607         compute_m_n(bits_per_pixel * pixel_clock,
5608                     link_clock * nlanes * 8,
5609                     &m_n->gmch_m, &m_n->gmch_n);
5610
5611         compute_m_n(pixel_clock, link_clock,
5612                     &m_n->link_m, &m_n->link_n);
5613 }
5614
5615 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5616 {
5617         if (i915.panel_use_ssc >= 0)
5618                 return i915.panel_use_ssc != 0;
5619         return dev_priv->vbt.lvds_use_ssc
5620                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5621 }
5622
5623 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5624 {
5625         struct drm_device *dev = crtc->base.dev;
5626         struct drm_i915_private *dev_priv = dev->dev_private;
5627         int refclk;
5628
5629         if (IS_VALLEYVIEW(dev)) {
5630                 refclk = 100000;
5631         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5632             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5633                 refclk = dev_priv->vbt.lvds_ssc_freq;
5634                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5635         } else if (!IS_GEN2(dev)) {
5636                 refclk = 96000;
5637         } else {
5638                 refclk = 48000;
5639         }
5640
5641         return refclk;
5642 }
5643
5644 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5645 {
5646         return (1 << dpll->n) << 16 | dpll->m2;
5647 }
5648
5649 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5650 {
5651         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5652 }
5653
5654 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5655                                      intel_clock_t *reduced_clock)
5656 {
5657         struct drm_device *dev = crtc->base.dev;
5658         u32 fp, fp2 = 0;
5659
5660         if (IS_PINEVIEW(dev)) {
5661                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5662                 if (reduced_clock)
5663                         fp2 = pnv_dpll_compute_fp(reduced_clock);
5664         } else {
5665                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5666                 if (reduced_clock)
5667                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
5668         }
5669
5670         crtc->config.dpll_hw_state.fp0 = fp;
5671
5672         crtc->lowfreq_avail = false;
5673         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5674             reduced_clock && i915.powersave) {
5675                 crtc->config.dpll_hw_state.fp1 = fp2;
5676                 crtc->lowfreq_avail = true;
5677         } else {
5678                 crtc->config.dpll_hw_state.fp1 = fp;
5679         }
5680 }
5681
5682 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5683                 pipe)
5684 {
5685         u32 reg_val;
5686
5687         /*
5688          * PLLB opamp always calibrates to max value of 0x3f, force enable it
5689          * and set it to a reasonable value instead.
5690          */
5691         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5692         reg_val &= 0xffffff00;
5693         reg_val |= 0x00000030;
5694         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5695
5696         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5697         reg_val &= 0x8cffffff;
5698         reg_val = 0x8c000000;
5699         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5700
5701         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5702         reg_val &= 0xffffff00;
5703         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5704
5705         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5706         reg_val &= 0x00ffffff;
5707         reg_val |= 0xb0000000;
5708         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5709 }
5710
5711 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5712                                          struct intel_link_m_n *m_n)
5713 {
5714         struct drm_device *dev = crtc->base.dev;
5715         struct drm_i915_private *dev_priv = dev->dev_private;
5716         int pipe = crtc->pipe;
5717
5718         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5719         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5720         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5721         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5722 }
5723
5724 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5725                                          struct intel_link_m_n *m_n,
5726                                          struct intel_link_m_n *m2_n2)
5727 {
5728         struct drm_device *dev = crtc->base.dev;
5729         struct drm_i915_private *dev_priv = dev->dev_private;
5730         int pipe = crtc->pipe;
5731         enum transcoder transcoder = crtc->config.cpu_transcoder;
5732
5733         if (INTEL_INFO(dev)->gen >= 5) {
5734                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5735                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5736                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5737                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5738                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5739                  * for gen < 8) and if DRRS is supported (to make sure the
5740                  * registers are not unnecessarily accessed).
5741                  */
5742                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5743                         crtc->config.has_drrs) {
5744                         I915_WRITE(PIPE_DATA_M2(transcoder),
5745                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5746                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5747                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5748                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5749                 }
5750         } else {
5751                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5752                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5753                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5754                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5755         }
5756 }
5757
5758 void intel_dp_set_m_n(struct intel_crtc *crtc)
5759 {
5760         if (crtc->config.has_pch_encoder)
5761                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5762         else
5763                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
5764                                                    &crtc->config.dp_m2_n2);
5765 }
5766
5767 static void vlv_update_pll(struct intel_crtc *crtc,
5768                            struct intel_crtc_config *pipe_config)
5769 {
5770         u32 dpll, dpll_md;
5771
5772         /*
5773          * Enable DPIO clock input. We should never disable the reference
5774          * clock for pipe B, since VGA hotplug / manual detection depends
5775          * on it.
5776          */
5777         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5778                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5779         /* We should never disable this, set it here for state tracking */
5780         if (crtc->pipe == PIPE_B)
5781                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5782         dpll |= DPLL_VCO_ENABLE;
5783         pipe_config->dpll_hw_state.dpll = dpll;
5784
5785         dpll_md = (pipe_config->pixel_multiplier - 1)
5786                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5787         pipe_config->dpll_hw_state.dpll_md = dpll_md;
5788 }
5789
5790 static void vlv_prepare_pll(struct intel_crtc *crtc,
5791                             const struct intel_crtc_config *pipe_config)
5792 {
5793         struct drm_device *dev = crtc->base.dev;
5794         struct drm_i915_private *dev_priv = dev->dev_private;
5795         int pipe = crtc->pipe;
5796         u32 mdiv;
5797         u32 bestn, bestm1, bestm2, bestp1, bestp2;
5798         u32 coreclk, reg_val;
5799
5800         mutex_lock(&dev_priv->dpio_lock);
5801
5802         bestn = pipe_config->dpll.n;
5803         bestm1 = pipe_config->dpll.m1;
5804         bestm2 = pipe_config->dpll.m2;
5805         bestp1 = pipe_config->dpll.p1;
5806         bestp2 = pipe_config->dpll.p2;
5807
5808         /* See eDP HDMI DPIO driver vbios notes doc */
5809
5810         /* PLL B needs special handling */
5811         if (pipe == PIPE_B)
5812                 vlv_pllb_recal_opamp(dev_priv, pipe);
5813
5814         /* Set up Tx target for periodic Rcomp update */
5815         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5816
5817         /* Disable target IRef on PLL */
5818         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5819         reg_val &= 0x00ffffff;
5820         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5821
5822         /* Disable fast lock */
5823         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5824
5825         /* Set idtafcrecal before PLL is enabled */
5826         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5827         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5828         mdiv |= ((bestn << DPIO_N_SHIFT));
5829         mdiv |= (1 << DPIO_K_SHIFT);
5830
5831         /*
5832          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5833          * but we don't support that).
5834          * Note: don't use the DAC post divider as it seems unstable.
5835          */
5836         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5837         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5838
5839         mdiv |= DPIO_ENABLE_CALIBRATION;
5840         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5841
5842         /* Set HBR and RBR LPF coefficients */
5843         if (pipe_config->port_clock == 162000 ||
5844             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
5845             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
5846                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5847                                  0x009f0003);
5848         else
5849                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5850                                  0x00d0000f);
5851
5852         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP) ||
5853             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5854                 /* Use SSC source */
5855                 if (pipe == PIPE_A)
5856                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5857                                          0x0df40000);
5858                 else
5859                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5860                                          0x0df70000);
5861         } else { /* HDMI or VGA */
5862                 /* Use bend source */
5863                 if (pipe == PIPE_A)
5864                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5865                                          0x0df70000);
5866                 else
5867                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5868                                          0x0df40000);
5869         }
5870
5871         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5872         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5873         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
5874             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5875                 coreclk |= 0x01000000;
5876         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5877
5878         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5879         mutex_unlock(&dev_priv->dpio_lock);
5880 }
5881
5882 static void chv_update_pll(struct intel_crtc *crtc,
5883                            struct intel_crtc_config *pipe_config)
5884 {
5885         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5886                 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5887                 DPLL_VCO_ENABLE;
5888         if (crtc->pipe != PIPE_A)
5889                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5890
5891         pipe_config->dpll_hw_state.dpll_md =
5892                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5893 }
5894
5895 static void chv_prepare_pll(struct intel_crtc *crtc,
5896                             const struct intel_crtc_config *pipe_config)
5897 {
5898         struct drm_device *dev = crtc->base.dev;
5899         struct drm_i915_private *dev_priv = dev->dev_private;
5900         int pipe = crtc->pipe;
5901         int dpll_reg = DPLL(crtc->pipe);
5902         enum dpio_channel port = vlv_pipe_to_channel(pipe);
5903         u32 loopfilter, intcoeff;
5904         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5905         int refclk;
5906
5907         bestn = pipe_config->dpll.n;
5908         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
5909         bestm1 = pipe_config->dpll.m1;
5910         bestm2 = pipe_config->dpll.m2 >> 22;
5911         bestp1 = pipe_config->dpll.p1;
5912         bestp2 = pipe_config->dpll.p2;
5913
5914         /*
5915          * Enable Refclk and SSC
5916          */
5917         I915_WRITE(dpll_reg,
5918                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5919
5920         mutex_lock(&dev_priv->dpio_lock);
5921
5922         /* p1 and p2 divider */
5923         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5924                         5 << DPIO_CHV_S1_DIV_SHIFT |
5925                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5926                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5927                         1 << DPIO_CHV_K_DIV_SHIFT);
5928
5929         /* Feedback post-divider - m2 */
5930         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5931
5932         /* Feedback refclk divider - n and m1 */
5933         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5934                         DPIO_CHV_M1_DIV_BY_2 |
5935                         1 << DPIO_CHV_N_DIV_SHIFT);
5936
5937         /* M2 fraction division */
5938         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5939
5940         /* M2 fraction division enable */
5941         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5942                        DPIO_CHV_FRAC_DIV_EN |
5943                        (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5944
5945         /* Loop filter */
5946         refclk = i9xx_get_refclk(crtc, 0);
5947         loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5948                 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5949         if (refclk == 100000)
5950                 intcoeff = 11;
5951         else if (refclk == 38400)
5952                 intcoeff = 10;
5953         else
5954                 intcoeff = 9;
5955         loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5956         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5957
5958         /* AFC Recal */
5959         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5960                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5961                         DPIO_AFC_RECAL);
5962
5963         mutex_unlock(&dev_priv->dpio_lock);
5964 }
5965
5966 /**
5967  * vlv_force_pll_on - forcibly enable just the PLL
5968  * @dev_priv: i915 private structure
5969  * @pipe: pipe PLL to enable
5970  * @dpll: PLL configuration
5971  *
5972  * Enable the PLL for @pipe using the supplied @dpll config. To be used
5973  * in cases where we need the PLL enabled even when @pipe is not going to
5974  * be enabled.
5975  */
5976 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
5977                       const struct dpll *dpll)
5978 {
5979         struct intel_crtc *crtc =
5980                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5981         struct intel_crtc_config pipe_config = {
5982                 .pixel_multiplier = 1,
5983                 .dpll = *dpll,
5984         };
5985
5986         if (IS_CHERRYVIEW(dev)) {
5987                 chv_update_pll(crtc, &pipe_config);
5988                 chv_prepare_pll(crtc, &pipe_config);
5989                 chv_enable_pll(crtc, &pipe_config);
5990         } else {
5991                 vlv_update_pll(crtc, &pipe_config);
5992                 vlv_prepare_pll(crtc, &pipe_config);
5993                 vlv_enable_pll(crtc, &pipe_config);
5994         }
5995 }
5996
5997 /**
5998  * vlv_force_pll_off - forcibly disable just the PLL
5999  * @dev_priv: i915 private structure
6000  * @pipe: pipe PLL to disable
6001  *
6002  * Disable the PLL for @pipe. To be used in cases where we need
6003  * the PLL enabled even when @pipe is not going to be enabled.
6004  */
6005 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6006 {
6007         if (IS_CHERRYVIEW(dev))
6008                 chv_disable_pll(to_i915(dev), pipe);
6009         else
6010                 vlv_disable_pll(to_i915(dev), pipe);
6011 }
6012
6013 static void i9xx_update_pll(struct intel_crtc *crtc,
6014                             intel_clock_t *reduced_clock,
6015                             int num_connectors)
6016 {
6017         struct drm_device *dev = crtc->base.dev;
6018         struct drm_i915_private *dev_priv = dev->dev_private;
6019         u32 dpll;
6020         bool is_sdvo;
6021         struct dpll *clock = &crtc->config.dpll;
6022
6023         i9xx_update_pll_dividers(crtc, reduced_clock);
6024
6025         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
6026                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
6027
6028         dpll = DPLL_VGA_MODE_DIS;
6029
6030         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
6031                 dpll |= DPLLB_MODE_LVDS;
6032         else
6033                 dpll |= DPLLB_MODE_DAC_SERIAL;
6034
6035         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6036                 dpll |= (crtc->config.pixel_multiplier - 1)
6037                         << SDVO_MULTIPLIER_SHIFT_HIRES;
6038         }
6039
6040         if (is_sdvo)
6041                 dpll |= DPLL_SDVO_HIGH_SPEED;
6042
6043         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
6044                 dpll |= DPLL_SDVO_HIGH_SPEED;
6045
6046         /* compute bitmask from p1 value */
6047         if (IS_PINEVIEW(dev))
6048                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6049         else {
6050                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6051                 if (IS_G4X(dev) && reduced_clock)
6052                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6053         }
6054         switch (clock->p2) {
6055         case 5:
6056                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6057                 break;
6058         case 7:
6059                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6060                 break;
6061         case 10:
6062                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6063                 break;
6064         case 14:
6065                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6066                 break;
6067         }
6068         if (INTEL_INFO(dev)->gen >= 4)
6069                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6070
6071         if (crtc->config.sdvo_tv_clock)
6072                 dpll |= PLL_REF_INPUT_TVCLKINBC;
6073         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
6074                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6075                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6076         else
6077                 dpll |= PLL_REF_INPUT_DREFCLK;
6078
6079         dpll |= DPLL_VCO_ENABLE;
6080         crtc->config.dpll_hw_state.dpll = dpll;
6081
6082         if (INTEL_INFO(dev)->gen >= 4) {
6083                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
6084                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6085                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
6086         }
6087 }
6088
6089 static void i8xx_update_pll(struct intel_crtc *crtc,
6090                             intel_clock_t *reduced_clock,
6091                             int num_connectors)
6092 {
6093         struct drm_device *dev = crtc->base.dev;
6094         struct drm_i915_private *dev_priv = dev->dev_private;
6095         u32 dpll;
6096         struct dpll *clock = &crtc->config.dpll;
6097
6098         i9xx_update_pll_dividers(crtc, reduced_clock);
6099
6100         dpll = DPLL_VGA_MODE_DIS;
6101
6102         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
6103                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6104         } else {
6105                 if (clock->p1 == 2)
6106                         dpll |= PLL_P1_DIVIDE_BY_TWO;
6107                 else
6108                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6109                 if (clock->p2 == 4)
6110                         dpll |= PLL_P2_DIVIDE_BY_4;
6111         }
6112
6113         if (!IS_I830(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
6114                 dpll |= DPLL_DVO_2X_MODE;
6115
6116         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
6117                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6118                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6119         else
6120                 dpll |= PLL_REF_INPUT_DREFCLK;
6121
6122         dpll |= DPLL_VCO_ENABLE;
6123         crtc->config.dpll_hw_state.dpll = dpll;
6124 }
6125
6126 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6127 {
6128         struct drm_device *dev = intel_crtc->base.dev;
6129         struct drm_i915_private *dev_priv = dev->dev_private;
6130         enum pipe pipe = intel_crtc->pipe;
6131         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6132         struct drm_display_mode *adjusted_mode =
6133                 &intel_crtc->config.adjusted_mode;
6134         uint32_t crtc_vtotal, crtc_vblank_end;
6135         int vsyncshift = 0;
6136
6137         /* We need to be careful not to changed the adjusted mode, for otherwise
6138          * the hw state checker will get angry at the mismatch. */
6139         crtc_vtotal = adjusted_mode->crtc_vtotal;
6140         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6141
6142         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6143                 /* the chip adds 2 halflines automatically */
6144                 crtc_vtotal -= 1;
6145                 crtc_vblank_end -= 1;
6146
6147                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6148                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6149                 else
6150                         vsyncshift = adjusted_mode->crtc_hsync_start -
6151                                 adjusted_mode->crtc_htotal / 2;
6152                 if (vsyncshift < 0)
6153                         vsyncshift += adjusted_mode->crtc_htotal;
6154         }
6155
6156         if (INTEL_INFO(dev)->gen > 3)
6157                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6158
6159         I915_WRITE(HTOTAL(cpu_transcoder),
6160                    (adjusted_mode->crtc_hdisplay - 1) |
6161                    ((adjusted_mode->crtc_htotal - 1) << 16));
6162         I915_WRITE(HBLANK(cpu_transcoder),
6163                    (adjusted_mode->crtc_hblank_start - 1) |
6164                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
6165         I915_WRITE(HSYNC(cpu_transcoder),
6166                    (adjusted_mode->crtc_hsync_start - 1) |
6167                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
6168
6169         I915_WRITE(VTOTAL(cpu_transcoder),
6170                    (adjusted_mode->crtc_vdisplay - 1) |
6171                    ((crtc_vtotal - 1) << 16));
6172         I915_WRITE(VBLANK(cpu_transcoder),
6173                    (adjusted_mode->crtc_vblank_start - 1) |
6174                    ((crtc_vblank_end - 1) << 16));
6175         I915_WRITE(VSYNC(cpu_transcoder),
6176                    (adjusted_mode->crtc_vsync_start - 1) |
6177                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
6178
6179         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6180          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6181          * documented on the DDI_FUNC_CTL register description, EDP Input Select
6182          * bits. */
6183         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6184             (pipe == PIPE_B || pipe == PIPE_C))
6185                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6186
6187         /* pipesrc controls the size that is scaled from, which should
6188          * always be the user's requested size.
6189          */
6190         I915_WRITE(PIPESRC(pipe),
6191                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
6192                    (intel_crtc->config.pipe_src_h - 1));
6193 }
6194
6195 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6196                                    struct intel_crtc_config *pipe_config)
6197 {
6198         struct drm_device *dev = crtc->base.dev;
6199         struct drm_i915_private *dev_priv = dev->dev_private;
6200         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6201         uint32_t tmp;
6202
6203         tmp = I915_READ(HTOTAL(cpu_transcoder));
6204         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6205         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6206         tmp = I915_READ(HBLANK(cpu_transcoder));
6207         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6208         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6209         tmp = I915_READ(HSYNC(cpu_transcoder));
6210         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6211         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6212
6213         tmp = I915_READ(VTOTAL(cpu_transcoder));
6214         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6215         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6216         tmp = I915_READ(VBLANK(cpu_transcoder));
6217         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6218         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6219         tmp = I915_READ(VSYNC(cpu_transcoder));
6220         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6221         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6222
6223         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6224                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6225                 pipe_config->adjusted_mode.crtc_vtotal += 1;
6226                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
6227         }
6228
6229         tmp = I915_READ(PIPESRC(crtc->pipe));
6230         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6231         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6232
6233         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
6234         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
6235 }
6236
6237 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6238                                  struct intel_crtc_config *pipe_config)
6239 {
6240         mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
6241         mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
6242         mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
6243         mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
6244
6245         mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
6246         mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
6247         mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
6248         mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
6249
6250         mode->flags = pipe_config->adjusted_mode.flags;
6251
6252         mode->clock = pipe_config->adjusted_mode.crtc_clock;
6253         mode->flags |= pipe_config->adjusted_mode.flags;
6254 }
6255
6256 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6257 {
6258         struct drm_device *dev = intel_crtc->base.dev;
6259         struct drm_i915_private *dev_priv = dev->dev_private;
6260         uint32_t pipeconf;
6261
6262         pipeconf = 0;
6263
6264         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6265             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6266                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6267
6268         if (intel_crtc->config.double_wide)
6269                 pipeconf |= PIPECONF_DOUBLE_WIDE;
6270
6271         /* only g4x and later have fancy bpc/dither controls */
6272         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6273                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6274                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
6275                         pipeconf |= PIPECONF_DITHER_EN |
6276                                     PIPECONF_DITHER_TYPE_SP;
6277
6278                 switch (intel_crtc->config.pipe_bpp) {
6279                 case 18:
6280                         pipeconf |= PIPECONF_6BPC;
6281                         break;
6282                 case 24:
6283                         pipeconf |= PIPECONF_8BPC;
6284                         break;
6285                 case 30:
6286                         pipeconf |= PIPECONF_10BPC;
6287                         break;
6288                 default:
6289                         /* Case prevented by intel_choose_pipe_bpp_dither. */
6290                         BUG();
6291                 }
6292         }
6293
6294         if (HAS_PIPE_CXSR(dev)) {
6295                 if (intel_crtc->lowfreq_avail) {
6296                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6297                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6298                 } else {
6299                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6300                 }
6301         }
6302
6303         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6304                 if (INTEL_INFO(dev)->gen < 4 ||
6305                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6306                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6307                 else
6308                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6309         } else
6310                 pipeconf |= PIPECONF_PROGRESSIVE;
6311
6312         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6313                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6314
6315         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6316         POSTING_READ(PIPECONF(intel_crtc->pipe));
6317 }
6318
6319 static int i9xx_crtc_mode_set(struct intel_crtc *crtc,
6320                               int x, int y,
6321                               struct drm_framebuffer *fb)
6322 {
6323         struct drm_device *dev = crtc->base.dev;
6324         struct drm_i915_private *dev_priv = dev->dev_private;
6325         int refclk, num_connectors = 0;
6326         intel_clock_t clock, reduced_clock;
6327         bool ok, has_reduced_clock = false;
6328         bool is_lvds = false, is_dsi = false;
6329         struct intel_encoder *encoder;
6330         const intel_limit_t *limit;
6331
6332         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
6333                 switch (encoder->type) {
6334                 case INTEL_OUTPUT_LVDS:
6335                         is_lvds = true;
6336                         break;
6337                 case INTEL_OUTPUT_DSI:
6338                         is_dsi = true;
6339                         break;
6340                 default:
6341                         break;
6342                 }
6343
6344                 num_connectors++;
6345         }
6346
6347         if (is_dsi)
6348                 return 0;
6349
6350         if (!crtc->config.clock_set) {
6351                 refclk = i9xx_get_refclk(crtc, num_connectors);
6352
6353                 /*
6354                  * Returns a set of divisors for the desired target clock with
6355                  * the given refclk, or FALSE.  The returned values represent
6356                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6357                  * 2) / p1 / p2.
6358                  */
6359                 limit = intel_limit(crtc, refclk);
6360                 ok = dev_priv->display.find_dpll(limit, crtc,
6361                                                  crtc->config.port_clock,
6362                                                  refclk, NULL, &clock);
6363                 if (!ok) {
6364                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
6365                         return -EINVAL;
6366                 }
6367
6368                 if (is_lvds && dev_priv->lvds_downclock_avail) {
6369                         /*
6370                          * Ensure we match the reduced clock's P to the target
6371                          * clock.  If the clocks don't match, we can't switch
6372                          * the display clock by using the FP0/FP1. In such case
6373                          * we will disable the LVDS downclock feature.
6374                          */
6375                         has_reduced_clock =
6376                                 dev_priv->display.find_dpll(limit, crtc,
6377                                                             dev_priv->lvds_downclock,
6378                                                             refclk, &clock,
6379                                                             &reduced_clock);
6380                 }
6381                 /* Compat-code for transition, will disappear. */
6382                 crtc->config.dpll.n = clock.n;
6383                 crtc->config.dpll.m1 = clock.m1;
6384                 crtc->config.dpll.m2 = clock.m2;
6385                 crtc->config.dpll.p1 = clock.p1;
6386                 crtc->config.dpll.p2 = clock.p2;
6387         }
6388
6389         if (IS_GEN2(dev)) {
6390                 i8xx_update_pll(crtc,
6391                                 has_reduced_clock ? &reduced_clock : NULL,
6392                                 num_connectors);
6393         } else if (IS_CHERRYVIEW(dev)) {
6394                 chv_update_pll(crtc, &crtc->config);
6395         } else if (IS_VALLEYVIEW(dev)) {
6396                 vlv_update_pll(crtc, &crtc->config);
6397         } else {
6398                 i9xx_update_pll(crtc,
6399                                 has_reduced_clock ? &reduced_clock : NULL,
6400                                 num_connectors);
6401         }
6402
6403         return 0;
6404 }
6405
6406 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6407                                  struct intel_crtc_config *pipe_config)
6408 {
6409         struct drm_device *dev = crtc->base.dev;
6410         struct drm_i915_private *dev_priv = dev->dev_private;
6411         uint32_t tmp;
6412
6413         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6414                 return;
6415
6416         tmp = I915_READ(PFIT_CONTROL);
6417         if (!(tmp & PFIT_ENABLE))
6418                 return;
6419
6420         /* Check whether the pfit is attached to our pipe. */
6421         if (INTEL_INFO(dev)->gen < 4) {
6422                 if (crtc->pipe != PIPE_B)
6423                         return;
6424         } else {
6425                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6426                         return;
6427         }
6428
6429         pipe_config->gmch_pfit.control = tmp;
6430         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6431         if (INTEL_INFO(dev)->gen < 5)
6432                 pipe_config->gmch_pfit.lvds_border_bits =
6433                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6434 }
6435
6436 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6437                                struct intel_crtc_config *pipe_config)
6438 {
6439         struct drm_device *dev = crtc->base.dev;
6440         struct drm_i915_private *dev_priv = dev->dev_private;
6441         int pipe = pipe_config->cpu_transcoder;
6442         intel_clock_t clock;
6443         u32 mdiv;
6444         int refclk = 100000;
6445
6446         /* In case of MIPI DPLL will not even be used */
6447         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6448                 return;
6449
6450         mutex_lock(&dev_priv->dpio_lock);
6451         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6452         mutex_unlock(&dev_priv->dpio_lock);
6453
6454         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6455         clock.m2 = mdiv & DPIO_M2DIV_MASK;
6456         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6457         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6458         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6459
6460         vlv_clock(refclk, &clock);
6461
6462         /* clock.dot is the fast clock */
6463         pipe_config->port_clock = clock.dot / 5;
6464 }
6465
6466 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6467                                   struct intel_plane_config *plane_config)
6468 {
6469         struct drm_device *dev = crtc->base.dev;
6470         struct drm_i915_private *dev_priv = dev->dev_private;
6471         u32 val, base, offset;
6472         int pipe = crtc->pipe, plane = crtc->plane;
6473         int fourcc, pixel_format;
6474         int aligned_height;
6475
6476         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6477         if (!crtc->base.primary->fb) {
6478                 DRM_DEBUG_KMS("failed to alloc fb\n");
6479                 return;
6480         }
6481
6482         val = I915_READ(DSPCNTR(plane));
6483
6484         if (INTEL_INFO(dev)->gen >= 4)
6485                 if (val & DISPPLANE_TILED)
6486                         plane_config->tiled = true;
6487
6488         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6489         fourcc = intel_format_to_fourcc(pixel_format);
6490         crtc->base.primary->fb->pixel_format = fourcc;
6491         crtc->base.primary->fb->bits_per_pixel =
6492                 drm_format_plane_cpp(fourcc, 0) * 8;
6493
6494         if (INTEL_INFO(dev)->gen >= 4) {
6495                 if (plane_config->tiled)
6496                         offset = I915_READ(DSPTILEOFF(plane));
6497                 else
6498                         offset = I915_READ(DSPLINOFF(plane));
6499                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6500         } else {
6501                 base = I915_READ(DSPADDR(plane));
6502         }
6503         plane_config->base = base;
6504
6505         val = I915_READ(PIPESRC(pipe));
6506         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6507         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6508
6509         val = I915_READ(DSPSTRIDE(pipe));
6510         crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
6511
6512         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6513                                             plane_config->tiled);
6514
6515         plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6516                                         aligned_height);
6517
6518         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6519                       pipe, plane, crtc->base.primary->fb->width,
6520                       crtc->base.primary->fb->height,
6521                       crtc->base.primary->fb->bits_per_pixel, base,
6522                       crtc->base.primary->fb->pitches[0],
6523                       plane_config->size);
6524
6525 }
6526
6527 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6528                                struct intel_crtc_config *pipe_config)
6529 {
6530         struct drm_device *dev = crtc->base.dev;
6531         struct drm_i915_private *dev_priv = dev->dev_private;
6532         int pipe = pipe_config->cpu_transcoder;
6533         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6534         intel_clock_t clock;
6535         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6536         int refclk = 100000;
6537
6538         mutex_lock(&dev_priv->dpio_lock);
6539         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6540         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6541         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6542         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6543         mutex_unlock(&dev_priv->dpio_lock);
6544
6545         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6546         clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6547         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6548         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6549         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6550
6551         chv_clock(refclk, &clock);
6552
6553         /* clock.dot is the fast clock */
6554         pipe_config->port_clock = clock.dot / 5;
6555 }
6556
6557 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6558                                  struct intel_crtc_config *pipe_config)
6559 {
6560         struct drm_device *dev = crtc->base.dev;
6561         struct drm_i915_private *dev_priv = dev->dev_private;
6562         uint32_t tmp;
6563
6564         if (!intel_display_power_is_enabled(dev_priv,
6565                                             POWER_DOMAIN_PIPE(crtc->pipe)))
6566                 return false;
6567
6568         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6569         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6570
6571         tmp = I915_READ(PIPECONF(crtc->pipe));
6572         if (!(tmp & PIPECONF_ENABLE))
6573                 return false;
6574
6575         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6576                 switch (tmp & PIPECONF_BPC_MASK) {
6577                 case PIPECONF_6BPC:
6578                         pipe_config->pipe_bpp = 18;
6579                         break;
6580                 case PIPECONF_8BPC:
6581                         pipe_config->pipe_bpp = 24;
6582                         break;
6583                 case PIPECONF_10BPC:
6584                         pipe_config->pipe_bpp = 30;
6585                         break;
6586                 default:
6587                         break;
6588                 }
6589         }
6590
6591         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6592                 pipe_config->limited_color_range = true;
6593
6594         if (INTEL_INFO(dev)->gen < 4)
6595                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6596
6597         intel_get_pipe_timings(crtc, pipe_config);
6598
6599         i9xx_get_pfit_config(crtc, pipe_config);
6600
6601         if (INTEL_INFO(dev)->gen >= 4) {
6602                 tmp = I915_READ(DPLL_MD(crtc->pipe));
6603                 pipe_config->pixel_multiplier =
6604                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6605                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6606                 pipe_config->dpll_hw_state.dpll_md = tmp;
6607         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6608                 tmp = I915_READ(DPLL(crtc->pipe));
6609                 pipe_config->pixel_multiplier =
6610                         ((tmp & SDVO_MULTIPLIER_MASK)
6611                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6612         } else {
6613                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6614                  * port and will be fixed up in the encoder->get_config
6615                  * function. */
6616                 pipe_config->pixel_multiplier = 1;
6617         }
6618         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6619         if (!IS_VALLEYVIEW(dev)) {
6620                 /*
6621                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6622                  * on 830. Filter it out here so that we don't
6623                  * report errors due to that.
6624                  */
6625                 if (IS_I830(dev))
6626                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6627
6628                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6629                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6630         } else {
6631                 /* Mask out read-only status bits. */
6632                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6633                                                      DPLL_PORTC_READY_MASK |
6634                                                      DPLL_PORTB_READY_MASK);
6635         }
6636
6637         if (IS_CHERRYVIEW(dev))
6638                 chv_crtc_clock_get(crtc, pipe_config);
6639         else if (IS_VALLEYVIEW(dev))
6640                 vlv_crtc_clock_get(crtc, pipe_config);
6641         else
6642                 i9xx_crtc_clock_get(crtc, pipe_config);
6643
6644         return true;
6645 }
6646
6647 static void ironlake_init_pch_refclk(struct drm_device *dev)
6648 {
6649         struct drm_i915_private *dev_priv = dev->dev_private;
6650         struct intel_encoder *encoder;
6651         u32 val, final;
6652         bool has_lvds = false;
6653         bool has_cpu_edp = false;
6654         bool has_panel = false;
6655         bool has_ck505 = false;
6656         bool can_ssc = false;
6657
6658         /* We need to take the global config into account */
6659         for_each_intel_encoder(dev, encoder) {
6660                 switch (encoder->type) {
6661                 case INTEL_OUTPUT_LVDS:
6662                         has_panel = true;
6663                         has_lvds = true;
6664                         break;
6665                 case INTEL_OUTPUT_EDP:
6666                         has_panel = true;
6667                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6668                                 has_cpu_edp = true;
6669                         break;
6670                 default:
6671                         break;
6672                 }
6673         }
6674
6675         if (HAS_PCH_IBX(dev)) {
6676                 has_ck505 = dev_priv->vbt.display_clock_mode;
6677                 can_ssc = has_ck505;
6678         } else {
6679                 has_ck505 = false;
6680                 can_ssc = true;
6681         }
6682
6683         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6684                       has_panel, has_lvds, has_ck505);
6685
6686         /* Ironlake: try to setup display ref clock before DPLL
6687          * enabling. This is only under driver's control after
6688          * PCH B stepping, previous chipset stepping should be
6689          * ignoring this setting.
6690          */
6691         val = I915_READ(PCH_DREF_CONTROL);
6692
6693         /* As we must carefully and slowly disable/enable each source in turn,
6694          * compute the final state we want first and check if we need to
6695          * make any changes at all.
6696          */
6697         final = val;
6698         final &= ~DREF_NONSPREAD_SOURCE_MASK;
6699         if (has_ck505)
6700                 final |= DREF_NONSPREAD_CK505_ENABLE;
6701         else
6702                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6703
6704         final &= ~DREF_SSC_SOURCE_MASK;
6705         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6706         final &= ~DREF_SSC1_ENABLE;
6707
6708         if (has_panel) {
6709                 final |= DREF_SSC_SOURCE_ENABLE;
6710
6711                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6712                         final |= DREF_SSC1_ENABLE;
6713
6714                 if (has_cpu_edp) {
6715                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
6716                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6717                         else
6718                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6719                 } else
6720                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6721         } else {
6722                 final |= DREF_SSC_SOURCE_DISABLE;
6723                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6724         }
6725
6726         if (final == val)
6727                 return;
6728
6729         /* Always enable nonspread source */
6730         val &= ~DREF_NONSPREAD_SOURCE_MASK;
6731
6732         if (has_ck505)
6733                 val |= DREF_NONSPREAD_CK505_ENABLE;
6734         else
6735                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6736
6737         if (has_panel) {
6738                 val &= ~DREF_SSC_SOURCE_MASK;
6739                 val |= DREF_SSC_SOURCE_ENABLE;
6740
6741                 /* SSC must be turned on before enabling the CPU output  */
6742                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6743                         DRM_DEBUG_KMS("Using SSC on panel\n");
6744                         val |= DREF_SSC1_ENABLE;
6745                 } else
6746                         val &= ~DREF_SSC1_ENABLE;
6747
6748                 /* Get SSC going before enabling the outputs */
6749                 I915_WRITE(PCH_DREF_CONTROL, val);
6750                 POSTING_READ(PCH_DREF_CONTROL);
6751                 udelay(200);
6752
6753                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6754
6755                 /* Enable CPU source on CPU attached eDP */
6756                 if (has_cpu_edp) {
6757                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6758                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
6759                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6760                         } else
6761                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6762                 } else
6763                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6764
6765                 I915_WRITE(PCH_DREF_CONTROL, val);
6766                 POSTING_READ(PCH_DREF_CONTROL);
6767                 udelay(200);
6768         } else {
6769                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6770
6771                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6772
6773                 /* Turn off CPU output */
6774                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6775
6776                 I915_WRITE(PCH_DREF_CONTROL, val);
6777                 POSTING_READ(PCH_DREF_CONTROL);
6778                 udelay(200);
6779
6780                 /* Turn off the SSC source */
6781                 val &= ~DREF_SSC_SOURCE_MASK;
6782                 val |= DREF_SSC_SOURCE_DISABLE;
6783
6784                 /* Turn off SSC1 */
6785                 val &= ~DREF_SSC1_ENABLE;
6786
6787                 I915_WRITE(PCH_DREF_CONTROL, val);
6788                 POSTING_READ(PCH_DREF_CONTROL);
6789                 udelay(200);
6790         }
6791
6792         BUG_ON(val != final);
6793 }
6794
6795 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6796 {
6797         uint32_t tmp;
6798
6799         tmp = I915_READ(SOUTH_CHICKEN2);
6800         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6801         I915_WRITE(SOUTH_CHICKEN2, tmp);
6802
6803         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6804                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6805                 DRM_ERROR("FDI mPHY reset assert timeout\n");
6806
6807         tmp = I915_READ(SOUTH_CHICKEN2);
6808         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6809         I915_WRITE(SOUTH_CHICKEN2, tmp);
6810
6811         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6812                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6813                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6814 }
6815
6816 /* WaMPhyProgramming:hsw */
6817 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6818 {
6819         uint32_t tmp;
6820
6821         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6822         tmp &= ~(0xFF << 24);
6823         tmp |= (0x12 << 24);
6824         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6825
6826         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6827         tmp |= (1 << 11);
6828         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6829
6830         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6831         tmp |= (1 << 11);
6832         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6833
6834         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6835         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6836         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6837
6838         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6839         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6840         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6841
6842         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6843         tmp &= ~(7 << 13);
6844         tmp |= (5 << 13);
6845         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6846
6847         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6848         tmp &= ~(7 << 13);
6849         tmp |= (5 << 13);
6850         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6851
6852         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6853         tmp &= ~0xFF;
6854         tmp |= 0x1C;
6855         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6856
6857         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6858         tmp &= ~0xFF;
6859         tmp |= 0x1C;
6860         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6861
6862         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6863         tmp &= ~(0xFF << 16);
6864         tmp |= (0x1C << 16);
6865         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6866
6867         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6868         tmp &= ~(0xFF << 16);
6869         tmp |= (0x1C << 16);
6870         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6871
6872         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6873         tmp |= (1 << 27);
6874         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6875
6876         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6877         tmp |= (1 << 27);
6878         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6879
6880         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6881         tmp &= ~(0xF << 28);
6882         tmp |= (4 << 28);
6883         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6884
6885         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6886         tmp &= ~(0xF << 28);
6887         tmp |= (4 << 28);
6888         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6889 }
6890
6891 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6892  * Programming" based on the parameters passed:
6893  * - Sequence to enable CLKOUT_DP
6894  * - Sequence to enable CLKOUT_DP without spread
6895  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6896  */
6897 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6898                                  bool with_fdi)
6899 {
6900         struct drm_i915_private *dev_priv = dev->dev_private;
6901         uint32_t reg, tmp;
6902
6903         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6904                 with_spread = true;
6905         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6906                  with_fdi, "LP PCH doesn't have FDI\n"))
6907                 with_fdi = false;
6908
6909         mutex_lock(&dev_priv->dpio_lock);
6910
6911         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6912         tmp &= ~SBI_SSCCTL_DISABLE;
6913         tmp |= SBI_SSCCTL_PATHALT;
6914         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6915
6916         udelay(24);
6917
6918         if (with_spread) {
6919                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6920                 tmp &= ~SBI_SSCCTL_PATHALT;
6921                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6922
6923                 if (with_fdi) {
6924                         lpt_reset_fdi_mphy(dev_priv);
6925                         lpt_program_fdi_mphy(dev_priv);
6926                 }
6927         }
6928
6929         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6930                SBI_GEN0 : SBI_DBUFF0;
6931         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6932         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6933         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6934
6935         mutex_unlock(&dev_priv->dpio_lock);
6936 }
6937
6938 /* Sequence to disable CLKOUT_DP */
6939 static void lpt_disable_clkout_dp(struct drm_device *dev)
6940 {
6941         struct drm_i915_private *dev_priv = dev->dev_private;
6942         uint32_t reg, tmp;
6943
6944         mutex_lock(&dev_priv->dpio_lock);
6945
6946         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6947                SBI_GEN0 : SBI_DBUFF0;
6948         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6949         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6950         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6951
6952         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6953         if (!(tmp & SBI_SSCCTL_DISABLE)) {
6954                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6955                         tmp |= SBI_SSCCTL_PATHALT;
6956                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6957                         udelay(32);
6958                 }
6959                 tmp |= SBI_SSCCTL_DISABLE;
6960                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6961         }
6962
6963         mutex_unlock(&dev_priv->dpio_lock);
6964 }
6965
6966 static void lpt_init_pch_refclk(struct drm_device *dev)
6967 {
6968         struct intel_encoder *encoder;
6969         bool has_vga = false;
6970
6971         for_each_intel_encoder(dev, encoder) {
6972                 switch (encoder->type) {
6973                 case INTEL_OUTPUT_ANALOG:
6974                         has_vga = true;
6975                         break;
6976                 default:
6977                         break;
6978                 }
6979         }
6980
6981         if (has_vga)
6982                 lpt_enable_clkout_dp(dev, true, true);
6983         else
6984                 lpt_disable_clkout_dp(dev);
6985 }
6986
6987 /*
6988  * Initialize reference clocks when the driver loads
6989  */
6990 void intel_init_pch_refclk(struct drm_device *dev)
6991 {
6992         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6993                 ironlake_init_pch_refclk(dev);
6994         else if (HAS_PCH_LPT(dev))
6995                 lpt_init_pch_refclk(dev);
6996 }
6997
6998 static int ironlake_get_refclk(struct drm_crtc *crtc)
6999 {
7000         struct drm_device *dev = crtc->dev;
7001         struct drm_i915_private *dev_priv = dev->dev_private;
7002         struct intel_encoder *encoder;
7003         int num_connectors = 0;
7004         bool is_lvds = false;
7005
7006         for_each_encoder_on_crtc(dev, crtc, encoder) {
7007                 switch (encoder->type) {
7008                 case INTEL_OUTPUT_LVDS:
7009                         is_lvds = true;
7010                         break;
7011                 default:
7012                         break;
7013                 }
7014                 num_connectors++;
7015         }
7016
7017         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7018                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7019                               dev_priv->vbt.lvds_ssc_freq);
7020                 return dev_priv->vbt.lvds_ssc_freq;
7021         }
7022
7023         return 120000;
7024 }
7025
7026 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7027 {
7028         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7029         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7030         int pipe = intel_crtc->pipe;
7031         uint32_t val;
7032
7033         val = 0;
7034
7035         switch (intel_crtc->config.pipe_bpp) {
7036         case 18:
7037                 val |= PIPECONF_6BPC;
7038                 break;
7039         case 24:
7040                 val |= PIPECONF_8BPC;
7041                 break;
7042         case 30:
7043                 val |= PIPECONF_10BPC;
7044                 break;
7045         case 36:
7046                 val |= PIPECONF_12BPC;
7047                 break;
7048         default:
7049                 /* Case prevented by intel_choose_pipe_bpp_dither. */
7050                 BUG();
7051         }
7052
7053         if (intel_crtc->config.dither)
7054                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7055
7056         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7057                 val |= PIPECONF_INTERLACED_ILK;
7058         else
7059                 val |= PIPECONF_PROGRESSIVE;
7060
7061         if (intel_crtc->config.limited_color_range)
7062                 val |= PIPECONF_COLOR_RANGE_SELECT;
7063
7064         I915_WRITE(PIPECONF(pipe), val);
7065         POSTING_READ(PIPECONF(pipe));
7066 }
7067
7068 /*
7069  * Set up the pipe CSC unit.
7070  *
7071  * Currently only full range RGB to limited range RGB conversion
7072  * is supported, but eventually this should handle various
7073  * RGB<->YCbCr scenarios as well.
7074  */
7075 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7076 {
7077         struct drm_device *dev = crtc->dev;
7078         struct drm_i915_private *dev_priv = dev->dev_private;
7079         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7080         int pipe = intel_crtc->pipe;
7081         uint16_t coeff = 0x7800; /* 1.0 */
7082
7083         /*
7084          * TODO: Check what kind of values actually come out of the pipe
7085          * with these coeff/postoff values and adjust to get the best
7086          * accuracy. Perhaps we even need to take the bpc value into
7087          * consideration.
7088          */
7089
7090         if (intel_crtc->config.limited_color_range)
7091                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7092
7093         /*
7094          * GY/GU and RY/RU should be the other way around according
7095          * to BSpec, but reality doesn't agree. Just set them up in
7096          * a way that results in the correct picture.
7097          */
7098         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7099         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7100
7101         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7102         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7103
7104         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7105         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7106
7107         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7108         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7109         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7110
7111         if (INTEL_INFO(dev)->gen > 6) {
7112                 uint16_t postoff = 0;
7113
7114                 if (intel_crtc->config.limited_color_range)
7115                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
7116
7117                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7118                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7119                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7120
7121                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7122         } else {
7123                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7124
7125                 if (intel_crtc->config.limited_color_range)
7126                         mode |= CSC_BLACK_SCREEN_OFFSET;
7127
7128                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7129         }
7130 }
7131
7132 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7133 {
7134         struct drm_device *dev = crtc->dev;
7135         struct drm_i915_private *dev_priv = dev->dev_private;
7136         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7137         enum pipe pipe = intel_crtc->pipe;
7138         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7139         uint32_t val;
7140
7141         val = 0;
7142
7143         if (IS_HASWELL(dev) && intel_crtc->config.dither)
7144                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7145
7146         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7147                 val |= PIPECONF_INTERLACED_ILK;
7148         else
7149                 val |= PIPECONF_PROGRESSIVE;
7150
7151         I915_WRITE(PIPECONF(cpu_transcoder), val);
7152         POSTING_READ(PIPECONF(cpu_transcoder));
7153
7154         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7155         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7156
7157         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7158                 val = 0;
7159
7160                 switch (intel_crtc->config.pipe_bpp) {
7161                 case 18:
7162                         val |= PIPEMISC_DITHER_6_BPC;
7163                         break;
7164                 case 24:
7165                         val |= PIPEMISC_DITHER_8_BPC;
7166                         break;
7167                 case 30:
7168                         val |= PIPEMISC_DITHER_10_BPC;
7169                         break;
7170                 case 36:
7171                         val |= PIPEMISC_DITHER_12_BPC;
7172                         break;
7173                 default:
7174                         /* Case prevented by pipe_config_set_bpp. */
7175                         BUG();
7176                 }
7177
7178                 if (intel_crtc->config.dither)
7179                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7180
7181                 I915_WRITE(PIPEMISC(pipe), val);
7182         }
7183 }
7184
7185 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7186                                     intel_clock_t *clock,
7187                                     bool *has_reduced_clock,
7188                                     intel_clock_t *reduced_clock)
7189 {
7190         struct drm_device *dev = crtc->dev;
7191         struct drm_i915_private *dev_priv = dev->dev_private;
7192         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7193         int refclk;
7194         const intel_limit_t *limit;
7195         bool ret, is_lvds = false;
7196
7197         is_lvds = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_LVDS);
7198
7199         refclk = ironlake_get_refclk(crtc);
7200
7201         /*
7202          * Returns a set of divisors for the desired target clock with the given
7203          * refclk, or FALSE.  The returned values represent the clock equation:
7204          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7205          */
7206         limit = intel_limit(intel_crtc, refclk);
7207         ret = dev_priv->display.find_dpll(limit, intel_crtc,
7208                                           intel_crtc->config.port_clock,
7209                                           refclk, NULL, clock);
7210         if (!ret)
7211                 return false;
7212
7213         if (is_lvds && dev_priv->lvds_downclock_avail) {
7214                 /*
7215                  * Ensure we match the reduced clock's P to the target clock.
7216                  * If the clocks don't match, we can't switch the display clock
7217                  * by using the FP0/FP1. In such case we will disable the LVDS
7218                  * downclock feature.
7219                 */
7220                 *has_reduced_clock =
7221                         dev_priv->display.find_dpll(limit, intel_crtc,
7222                                                     dev_priv->lvds_downclock,
7223                                                     refclk, clock,
7224                                                     reduced_clock);
7225         }
7226
7227         return true;
7228 }
7229
7230 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7231 {
7232         /*
7233          * Account for spread spectrum to avoid
7234          * oversubscribing the link. Max center spread
7235          * is 2.5%; use 5% for safety's sake.
7236          */
7237         u32 bps = target_clock * bpp * 21 / 20;
7238         return DIV_ROUND_UP(bps, link_bw * 8);
7239 }
7240
7241 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7242 {
7243         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7244 }
7245
7246 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7247                                       u32 *fp,
7248                                       intel_clock_t *reduced_clock, u32 *fp2)
7249 {
7250         struct drm_crtc *crtc = &intel_crtc->base;
7251         struct drm_device *dev = crtc->dev;
7252         struct drm_i915_private *dev_priv = dev->dev_private;
7253         struct intel_encoder *intel_encoder;
7254         uint32_t dpll;
7255         int factor, num_connectors = 0;
7256         bool is_lvds = false, is_sdvo = false;
7257
7258         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
7259                 switch (intel_encoder->type) {
7260                 case INTEL_OUTPUT_LVDS:
7261                         is_lvds = true;
7262                         break;
7263                 case INTEL_OUTPUT_SDVO:
7264                 case INTEL_OUTPUT_HDMI:
7265                         is_sdvo = true;
7266                         break;
7267                 default:
7268                         break;
7269                 }
7270
7271                 num_connectors++;
7272         }
7273
7274         /* Enable autotuning of the PLL clock (if permissible) */
7275         factor = 21;
7276         if (is_lvds) {
7277                 if ((intel_panel_use_ssc(dev_priv) &&
7278                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
7279                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7280                         factor = 25;
7281         } else if (intel_crtc->config.sdvo_tv_clock)
7282                 factor = 20;
7283
7284         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7285                 *fp |= FP_CB_TUNE;
7286
7287         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7288                 *fp2 |= FP_CB_TUNE;
7289
7290         dpll = 0;
7291
7292         if (is_lvds)
7293                 dpll |= DPLLB_MODE_LVDS;
7294         else
7295                 dpll |= DPLLB_MODE_DAC_SERIAL;
7296
7297         dpll |= (intel_crtc->config.pixel_multiplier - 1)
7298                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7299
7300         if (is_sdvo)
7301                 dpll |= DPLL_SDVO_HIGH_SPEED;
7302         if (intel_crtc->config.has_dp_encoder)
7303                 dpll |= DPLL_SDVO_HIGH_SPEED;
7304
7305         /* compute bitmask from p1 value */
7306         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7307         /* also FPA1 */
7308         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7309
7310         switch (intel_crtc->config.dpll.p2) {
7311         case 5:
7312                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7313                 break;
7314         case 7:
7315                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7316                 break;
7317         case 10:
7318                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7319                 break;
7320         case 14:
7321                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7322                 break;
7323         }
7324
7325         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7326                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7327         else
7328                 dpll |= PLL_REF_INPUT_DREFCLK;
7329
7330         return dpll | DPLL_VCO_ENABLE;
7331 }
7332
7333 static int ironlake_crtc_mode_set(struct intel_crtc *crtc,
7334                                   int x, int y,
7335                                   struct drm_framebuffer *fb)
7336 {
7337         struct drm_device *dev = crtc->base.dev;
7338         intel_clock_t clock, reduced_clock;
7339         u32 dpll = 0, fp = 0, fp2 = 0;
7340         bool ok, has_reduced_clock = false;
7341         bool is_lvds = false;
7342         struct intel_shared_dpll *pll;
7343
7344         is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7345
7346         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7347              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7348
7349         ok = ironlake_compute_clocks(&crtc->base, &clock,
7350                                      &has_reduced_clock, &reduced_clock);
7351         if (!ok && !crtc->config.clock_set) {
7352                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7353                 return -EINVAL;
7354         }
7355         /* Compat-code for transition, will disappear. */
7356         if (!crtc->config.clock_set) {
7357                 crtc->config.dpll.n = clock.n;
7358                 crtc->config.dpll.m1 = clock.m1;
7359                 crtc->config.dpll.m2 = clock.m2;
7360                 crtc->config.dpll.p1 = clock.p1;
7361                 crtc->config.dpll.p2 = clock.p2;
7362         }
7363
7364         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7365         if (crtc->config.has_pch_encoder) {
7366                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
7367                 if (has_reduced_clock)
7368                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7369
7370                 dpll = ironlake_compute_dpll(crtc,
7371                                              &fp, &reduced_clock,
7372                                              has_reduced_clock ? &fp2 : NULL);
7373
7374                 crtc->config.dpll_hw_state.dpll = dpll;
7375                 crtc->config.dpll_hw_state.fp0 = fp;
7376                 if (has_reduced_clock)
7377                         crtc->config.dpll_hw_state.fp1 = fp2;
7378                 else
7379                         crtc->config.dpll_hw_state.fp1 = fp;
7380
7381                 pll = intel_get_shared_dpll(crtc);
7382                 if (pll == NULL) {
7383                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7384                                          pipe_name(crtc->pipe));
7385                         return -EINVAL;
7386                 }
7387         } else
7388                 intel_put_shared_dpll(crtc);
7389
7390         if (is_lvds && has_reduced_clock && i915.powersave)
7391                 crtc->lowfreq_avail = true;
7392         else
7393                 crtc->lowfreq_avail = false;
7394
7395         return 0;
7396 }
7397
7398 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7399                                          struct intel_link_m_n *m_n)
7400 {
7401         struct drm_device *dev = crtc->base.dev;
7402         struct drm_i915_private *dev_priv = dev->dev_private;
7403         enum pipe pipe = crtc->pipe;
7404
7405         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7406         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7407         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7408                 & ~TU_SIZE_MASK;
7409         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7410         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7411                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7412 }
7413
7414 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7415                                          enum transcoder transcoder,
7416                                          struct intel_link_m_n *m_n,
7417                                          struct intel_link_m_n *m2_n2)
7418 {
7419         struct drm_device *dev = crtc->base.dev;
7420         struct drm_i915_private *dev_priv = dev->dev_private;
7421         enum pipe pipe = crtc->pipe;
7422
7423         if (INTEL_INFO(dev)->gen >= 5) {
7424                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7425                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7426                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7427                         & ~TU_SIZE_MASK;
7428                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7429                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7430                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7431                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7432                  * gen < 8) and if DRRS is supported (to make sure the
7433                  * registers are not unnecessarily read).
7434                  */
7435                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7436                         crtc->config.has_drrs) {
7437                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7438                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7439                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7440                                         & ~TU_SIZE_MASK;
7441                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7442                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7443                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7444                 }
7445         } else {
7446                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7447                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7448                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7449                         & ~TU_SIZE_MASK;
7450                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7451                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7452                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7453         }
7454 }
7455
7456 void intel_dp_get_m_n(struct intel_crtc *crtc,
7457                       struct intel_crtc_config *pipe_config)
7458 {
7459         if (crtc->config.has_pch_encoder)
7460                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7461         else
7462                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7463                                              &pipe_config->dp_m_n,
7464                                              &pipe_config->dp_m2_n2);
7465 }
7466
7467 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7468                                         struct intel_crtc_config *pipe_config)
7469 {
7470         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7471                                      &pipe_config->fdi_m_n, NULL);
7472 }
7473
7474 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7475                                      struct intel_crtc_config *pipe_config)
7476 {
7477         struct drm_device *dev = crtc->base.dev;
7478         struct drm_i915_private *dev_priv = dev->dev_private;
7479         uint32_t tmp;
7480
7481         tmp = I915_READ(PF_CTL(crtc->pipe));
7482
7483         if (tmp & PF_ENABLE) {
7484                 pipe_config->pch_pfit.enabled = true;
7485                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7486                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7487
7488                 /* We currently do not free assignements of panel fitters on
7489                  * ivb/hsw (since we don't use the higher upscaling modes which
7490                  * differentiates them) so just WARN about this case for now. */
7491                 if (IS_GEN7(dev)) {
7492                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7493                                 PF_PIPE_SEL_IVB(crtc->pipe));
7494                 }
7495         }
7496 }
7497
7498 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7499                                       struct intel_plane_config *plane_config)
7500 {
7501         struct drm_device *dev = crtc->base.dev;
7502         struct drm_i915_private *dev_priv = dev->dev_private;
7503         u32 val, base, offset;
7504         int pipe = crtc->pipe, plane = crtc->plane;
7505         int fourcc, pixel_format;
7506         int aligned_height;
7507
7508         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7509         if (!crtc->base.primary->fb) {
7510                 DRM_DEBUG_KMS("failed to alloc fb\n");
7511                 return;
7512         }
7513
7514         val = I915_READ(DSPCNTR(plane));
7515
7516         if (INTEL_INFO(dev)->gen >= 4)
7517                 if (val & DISPPLANE_TILED)
7518                         plane_config->tiled = true;
7519
7520         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7521         fourcc = intel_format_to_fourcc(pixel_format);
7522         crtc->base.primary->fb->pixel_format = fourcc;
7523         crtc->base.primary->fb->bits_per_pixel =
7524                 drm_format_plane_cpp(fourcc, 0) * 8;
7525
7526         base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7527         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7528                 offset = I915_READ(DSPOFFSET(plane));
7529         } else {
7530                 if (plane_config->tiled)
7531                         offset = I915_READ(DSPTILEOFF(plane));
7532                 else
7533                         offset = I915_READ(DSPLINOFF(plane));
7534         }
7535         plane_config->base = base;
7536
7537         val = I915_READ(PIPESRC(pipe));
7538         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7539         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7540
7541         val = I915_READ(DSPSTRIDE(pipe));
7542         crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
7543
7544         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7545                                             plane_config->tiled);
7546
7547         plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7548                                         aligned_height);
7549
7550         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7551                       pipe, plane, crtc->base.primary->fb->width,
7552                       crtc->base.primary->fb->height,
7553                       crtc->base.primary->fb->bits_per_pixel, base,
7554                       crtc->base.primary->fb->pitches[0],
7555                       plane_config->size);
7556 }
7557
7558 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7559                                      struct intel_crtc_config *pipe_config)
7560 {
7561         struct drm_device *dev = crtc->base.dev;
7562         struct drm_i915_private *dev_priv = dev->dev_private;
7563         uint32_t tmp;
7564
7565         if (!intel_display_power_is_enabled(dev_priv,
7566                                             POWER_DOMAIN_PIPE(crtc->pipe)))
7567                 return false;
7568
7569         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7570         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7571
7572         tmp = I915_READ(PIPECONF(crtc->pipe));
7573         if (!(tmp & PIPECONF_ENABLE))
7574                 return false;
7575
7576         switch (tmp & PIPECONF_BPC_MASK) {
7577         case PIPECONF_6BPC:
7578                 pipe_config->pipe_bpp = 18;
7579                 break;
7580         case PIPECONF_8BPC:
7581                 pipe_config->pipe_bpp = 24;
7582                 break;
7583         case PIPECONF_10BPC:
7584                 pipe_config->pipe_bpp = 30;
7585                 break;
7586         case PIPECONF_12BPC:
7587                 pipe_config->pipe_bpp = 36;
7588                 break;
7589         default:
7590                 break;
7591         }
7592
7593         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7594                 pipe_config->limited_color_range = true;
7595
7596         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7597                 struct intel_shared_dpll *pll;
7598
7599                 pipe_config->has_pch_encoder = true;
7600
7601                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7602                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7603                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7604
7605                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7606
7607                 if (HAS_PCH_IBX(dev_priv->dev)) {
7608                         pipe_config->shared_dpll =
7609                                 (enum intel_dpll_id) crtc->pipe;
7610                 } else {
7611                         tmp = I915_READ(PCH_DPLL_SEL);
7612                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7613                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7614                         else
7615                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7616                 }
7617
7618                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7619
7620                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7621                                            &pipe_config->dpll_hw_state));
7622
7623                 tmp = pipe_config->dpll_hw_state.dpll;
7624                 pipe_config->pixel_multiplier =
7625                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7626                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7627
7628                 ironlake_pch_clock_get(crtc, pipe_config);
7629         } else {
7630                 pipe_config->pixel_multiplier = 1;
7631         }
7632
7633         intel_get_pipe_timings(crtc, pipe_config);
7634
7635         ironlake_get_pfit_config(crtc, pipe_config);
7636
7637         return true;
7638 }
7639
7640 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7641 {
7642         struct drm_device *dev = dev_priv->dev;
7643         struct intel_crtc *crtc;
7644
7645         for_each_intel_crtc(dev, crtc)
7646                 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7647                      pipe_name(crtc->pipe));
7648
7649         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7650         WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7651         WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7652         WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7653         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7654         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7655              "CPU PWM1 enabled\n");
7656         if (IS_HASWELL(dev))
7657                 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7658                      "CPU PWM2 enabled\n");
7659         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7660              "PCH PWM1 enabled\n");
7661         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7662              "Utility pin enabled\n");
7663         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7664
7665         /*
7666          * In theory we can still leave IRQs enabled, as long as only the HPD
7667          * interrupts remain enabled. We used to check for that, but since it's
7668          * gen-specific and since we only disable LCPLL after we fully disable
7669          * the interrupts, the check below should be enough.
7670          */
7671         WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7672 }
7673
7674 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7675 {
7676         struct drm_device *dev = dev_priv->dev;
7677
7678         if (IS_HASWELL(dev))
7679                 return I915_READ(D_COMP_HSW);
7680         else
7681                 return I915_READ(D_COMP_BDW);
7682 }
7683
7684 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7685 {
7686         struct drm_device *dev = dev_priv->dev;
7687
7688         if (IS_HASWELL(dev)) {
7689                 mutex_lock(&dev_priv->rps.hw_lock);
7690                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7691                                             val))
7692                         DRM_ERROR("Failed to write to D_COMP\n");
7693                 mutex_unlock(&dev_priv->rps.hw_lock);
7694         } else {
7695                 I915_WRITE(D_COMP_BDW, val);
7696                 POSTING_READ(D_COMP_BDW);
7697         }
7698 }
7699
7700 /*
7701  * This function implements pieces of two sequences from BSpec:
7702  * - Sequence for display software to disable LCPLL
7703  * - Sequence for display software to allow package C8+
7704  * The steps implemented here are just the steps that actually touch the LCPLL
7705  * register. Callers should take care of disabling all the display engine
7706  * functions, doing the mode unset, fixing interrupts, etc.
7707  */
7708 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7709                               bool switch_to_fclk, bool allow_power_down)
7710 {
7711         uint32_t val;
7712
7713         assert_can_disable_lcpll(dev_priv);
7714
7715         val = I915_READ(LCPLL_CTL);
7716
7717         if (switch_to_fclk) {
7718                 val |= LCPLL_CD_SOURCE_FCLK;
7719                 I915_WRITE(LCPLL_CTL, val);
7720
7721                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7722                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
7723                         DRM_ERROR("Switching to FCLK failed\n");
7724
7725                 val = I915_READ(LCPLL_CTL);
7726         }
7727
7728         val |= LCPLL_PLL_DISABLE;
7729         I915_WRITE(LCPLL_CTL, val);
7730         POSTING_READ(LCPLL_CTL);
7731
7732         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7733                 DRM_ERROR("LCPLL still locked\n");
7734
7735         val = hsw_read_dcomp(dev_priv);
7736         val |= D_COMP_COMP_DISABLE;
7737         hsw_write_dcomp(dev_priv, val);
7738         ndelay(100);
7739
7740         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7741                      1))
7742                 DRM_ERROR("D_COMP RCOMP still in progress\n");
7743
7744         if (allow_power_down) {
7745                 val = I915_READ(LCPLL_CTL);
7746                 val |= LCPLL_POWER_DOWN_ALLOW;
7747                 I915_WRITE(LCPLL_CTL, val);
7748                 POSTING_READ(LCPLL_CTL);
7749         }
7750 }
7751
7752 /*
7753  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7754  * source.
7755  */
7756 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7757 {
7758         uint32_t val;
7759
7760         val = I915_READ(LCPLL_CTL);
7761
7762         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7763                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7764                 return;
7765
7766         /*
7767          * Make sure we're not on PC8 state before disabling PC8, otherwise
7768          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7769          *
7770          * The other problem is that hsw_restore_lcpll() is called as part of
7771          * the runtime PM resume sequence, so we can't just call
7772          * gen6_gt_force_wake_get() because that function calls
7773          * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7774          * while we are on the resume sequence. So to solve this problem we have
7775          * to call special forcewake code that doesn't touch runtime PM and
7776          * doesn't enable the forcewake delayed work.
7777          */
7778         spin_lock_irq(&dev_priv->uncore.lock);
7779         if (dev_priv->uncore.forcewake_count++ == 0)
7780                 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7781         spin_unlock_irq(&dev_priv->uncore.lock);
7782
7783         if (val & LCPLL_POWER_DOWN_ALLOW) {
7784                 val &= ~LCPLL_POWER_DOWN_ALLOW;
7785                 I915_WRITE(LCPLL_CTL, val);
7786                 POSTING_READ(LCPLL_CTL);
7787         }
7788
7789         val = hsw_read_dcomp(dev_priv);
7790         val |= D_COMP_COMP_FORCE;
7791         val &= ~D_COMP_COMP_DISABLE;
7792         hsw_write_dcomp(dev_priv, val);
7793
7794         val = I915_READ(LCPLL_CTL);
7795         val &= ~LCPLL_PLL_DISABLE;
7796         I915_WRITE(LCPLL_CTL, val);
7797
7798         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7799                 DRM_ERROR("LCPLL not locked yet\n");
7800
7801         if (val & LCPLL_CD_SOURCE_FCLK) {
7802                 val = I915_READ(LCPLL_CTL);
7803                 val &= ~LCPLL_CD_SOURCE_FCLK;
7804                 I915_WRITE(LCPLL_CTL, val);
7805
7806                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7807                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7808                         DRM_ERROR("Switching back to LCPLL failed\n");
7809         }
7810
7811         /* See the big comment above. */
7812         spin_lock_irq(&dev_priv->uncore.lock);
7813         if (--dev_priv->uncore.forcewake_count == 0)
7814                 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7815         spin_unlock_irq(&dev_priv->uncore.lock);
7816 }
7817
7818 /*
7819  * Package states C8 and deeper are really deep PC states that can only be
7820  * reached when all the devices on the system allow it, so even if the graphics
7821  * device allows PC8+, it doesn't mean the system will actually get to these
7822  * states. Our driver only allows PC8+ when going into runtime PM.
7823  *
7824  * The requirements for PC8+ are that all the outputs are disabled, the power
7825  * well is disabled and most interrupts are disabled, and these are also
7826  * requirements for runtime PM. When these conditions are met, we manually do
7827  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7828  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7829  * hang the machine.
7830  *
7831  * When we really reach PC8 or deeper states (not just when we allow it) we lose
7832  * the state of some registers, so when we come back from PC8+ we need to
7833  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7834  * need to take care of the registers kept by RC6. Notice that this happens even
7835  * if we don't put the device in PCI D3 state (which is what currently happens
7836  * because of the runtime PM support).
7837  *
7838  * For more, read "Display Sequences for Package C8" on the hardware
7839  * documentation.
7840  */
7841 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7842 {
7843         struct drm_device *dev = dev_priv->dev;
7844         uint32_t val;
7845
7846         DRM_DEBUG_KMS("Enabling package C8+\n");
7847
7848         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7849                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7850                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7851                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7852         }
7853
7854         lpt_disable_clkout_dp(dev);
7855         hsw_disable_lcpll(dev_priv, true, true);
7856 }
7857
7858 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7859 {
7860         struct drm_device *dev = dev_priv->dev;
7861         uint32_t val;
7862
7863         DRM_DEBUG_KMS("Disabling package C8+\n");
7864
7865         hsw_restore_lcpll(dev_priv);
7866         lpt_init_pch_refclk(dev);
7867
7868         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7869                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7870                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7871                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7872         }
7873
7874         intel_prepare_ddi(dev);
7875 }
7876
7877 static void snb_modeset_global_resources(struct drm_device *dev)
7878 {
7879         modeset_update_crtc_power_domains(dev);
7880 }
7881
7882 static void haswell_modeset_global_resources(struct drm_device *dev)
7883 {
7884         modeset_update_crtc_power_domains(dev);
7885 }
7886
7887 static int haswell_crtc_mode_set(struct intel_crtc *crtc,
7888                                  int x, int y,
7889                                  struct drm_framebuffer *fb)
7890 {
7891         if (!intel_ddi_pll_select(crtc))
7892                 return -EINVAL;
7893
7894         crtc->lowfreq_avail = false;
7895
7896         return 0;
7897 }
7898
7899 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
7900                                 enum port port,
7901                                 struct intel_crtc_config *pipe_config)
7902 {
7903         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
7904
7905         switch (pipe_config->ddi_pll_sel) {
7906         case PORT_CLK_SEL_WRPLL1:
7907                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7908                 break;
7909         case PORT_CLK_SEL_WRPLL2:
7910                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7911                 break;
7912         }
7913 }
7914
7915 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
7916                                        struct intel_crtc_config *pipe_config)
7917 {
7918         struct drm_device *dev = crtc->base.dev;
7919         struct drm_i915_private *dev_priv = dev->dev_private;
7920         struct intel_shared_dpll *pll;
7921         enum port port;
7922         uint32_t tmp;
7923
7924         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7925
7926         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
7927
7928         haswell_get_ddi_pll(dev_priv, port, pipe_config);
7929
7930         if (pipe_config->shared_dpll >= 0) {
7931                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7932
7933                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7934                                            &pipe_config->dpll_hw_state));
7935         }
7936
7937         /*
7938          * Haswell has only FDI/PCH transcoder A. It is which is connected to
7939          * DDI E. So just check whether this pipe is wired to DDI E and whether
7940          * the PCH transcoder is on.
7941          */
7942         if (INTEL_INFO(dev)->gen < 9 &&
7943             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7944                 pipe_config->has_pch_encoder = true;
7945
7946                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7947                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7948                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7949
7950                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7951         }
7952 }
7953
7954 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7955                                     struct intel_crtc_config *pipe_config)
7956 {
7957         struct drm_device *dev = crtc->base.dev;
7958         struct drm_i915_private *dev_priv = dev->dev_private;
7959         enum intel_display_power_domain pfit_domain;
7960         uint32_t tmp;
7961
7962         if (!intel_display_power_is_enabled(dev_priv,
7963                                          POWER_DOMAIN_PIPE(crtc->pipe)))
7964                 return false;
7965
7966         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7967         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7968
7969         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7970         if (tmp & TRANS_DDI_FUNC_ENABLE) {
7971                 enum pipe trans_edp_pipe;
7972                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7973                 default:
7974                         WARN(1, "unknown pipe linked to edp transcoder\n");
7975                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7976                 case TRANS_DDI_EDP_INPUT_A_ON:
7977                         trans_edp_pipe = PIPE_A;
7978                         break;
7979                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7980                         trans_edp_pipe = PIPE_B;
7981                         break;
7982                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7983                         trans_edp_pipe = PIPE_C;
7984                         break;
7985                 }
7986
7987                 if (trans_edp_pipe == crtc->pipe)
7988                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
7989         }
7990
7991         if (!intel_display_power_is_enabled(dev_priv,
7992                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7993                 return false;
7994
7995         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7996         if (!(tmp & PIPECONF_ENABLE))
7997                 return false;
7998
7999         haswell_get_ddi_port_state(crtc, pipe_config);
8000
8001         intel_get_pipe_timings(crtc, pipe_config);
8002
8003         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8004         if (intel_display_power_is_enabled(dev_priv, pfit_domain))
8005                 ironlake_get_pfit_config(crtc, pipe_config);
8006
8007         if (IS_HASWELL(dev))
8008                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8009                         (I915_READ(IPS_CTL) & IPS_ENABLE);
8010
8011         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8012                 pipe_config->pixel_multiplier =
8013                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8014         } else {
8015                 pipe_config->pixel_multiplier = 1;
8016         }
8017
8018         return true;
8019 }
8020
8021 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8022 {
8023         struct drm_device *dev = crtc->dev;
8024         struct drm_i915_private *dev_priv = dev->dev_private;
8025         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8026         uint32_t cntl = 0, size = 0;
8027
8028         if (base) {
8029                 unsigned int width = intel_crtc->cursor_width;
8030                 unsigned int height = intel_crtc->cursor_height;
8031                 unsigned int stride = roundup_pow_of_two(width) * 4;
8032
8033                 switch (stride) {
8034                 default:
8035                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8036                                   width, stride);
8037                         stride = 256;
8038                         /* fallthrough */
8039                 case 256:
8040                 case 512:
8041                 case 1024:
8042                 case 2048:
8043                         break;
8044                 }
8045
8046                 cntl |= CURSOR_ENABLE |
8047                         CURSOR_GAMMA_ENABLE |
8048                         CURSOR_FORMAT_ARGB |
8049                         CURSOR_STRIDE(stride);
8050
8051                 size = (height << 12) | width;
8052         }
8053
8054         if (intel_crtc->cursor_cntl != 0 &&
8055             (intel_crtc->cursor_base != base ||
8056              intel_crtc->cursor_size != size ||
8057              intel_crtc->cursor_cntl != cntl)) {
8058                 /* On these chipsets we can only modify the base/size/stride
8059                  * whilst the cursor is disabled.
8060                  */
8061                 I915_WRITE(_CURACNTR, 0);
8062                 POSTING_READ(_CURACNTR);
8063                 intel_crtc->cursor_cntl = 0;
8064         }
8065
8066         if (intel_crtc->cursor_base != base) {
8067                 I915_WRITE(_CURABASE, base);
8068                 intel_crtc->cursor_base = base;
8069         }
8070
8071         if (intel_crtc->cursor_size != size) {
8072                 I915_WRITE(CURSIZE, size);
8073                 intel_crtc->cursor_size = size;
8074         }
8075
8076         if (intel_crtc->cursor_cntl != cntl) {
8077                 I915_WRITE(_CURACNTR, cntl);
8078                 POSTING_READ(_CURACNTR);
8079                 intel_crtc->cursor_cntl = cntl;
8080         }
8081 }
8082
8083 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8084 {
8085         struct drm_device *dev = crtc->dev;
8086         struct drm_i915_private *dev_priv = dev->dev_private;
8087         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8088         int pipe = intel_crtc->pipe;
8089         uint32_t cntl;
8090
8091         cntl = 0;
8092         if (base) {
8093                 cntl = MCURSOR_GAMMA_ENABLE;
8094                 switch (intel_crtc->cursor_width) {
8095                         case 64:
8096                                 cntl |= CURSOR_MODE_64_ARGB_AX;
8097                                 break;
8098                         case 128:
8099                                 cntl |= CURSOR_MODE_128_ARGB_AX;
8100                                 break;
8101                         case 256:
8102                                 cntl |= CURSOR_MODE_256_ARGB_AX;
8103                                 break;
8104                         default:
8105                                 WARN_ON(1);
8106                                 return;
8107                 }
8108                 cntl |= pipe << 28; /* Connect to correct pipe */
8109
8110                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8111                         cntl |= CURSOR_PIPE_CSC_ENABLE;
8112         }
8113
8114         if (to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180))
8115                 cntl |= CURSOR_ROTATE_180;
8116
8117         if (intel_crtc->cursor_cntl != cntl) {
8118                 I915_WRITE(CURCNTR(pipe), cntl);
8119                 POSTING_READ(CURCNTR(pipe));
8120                 intel_crtc->cursor_cntl = cntl;
8121         }
8122
8123         /* and commit changes on next vblank */
8124         I915_WRITE(CURBASE(pipe), base);
8125         POSTING_READ(CURBASE(pipe));
8126
8127         intel_crtc->cursor_base = base;
8128 }
8129
8130 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8131 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8132                                      bool on)
8133 {
8134         struct drm_device *dev = crtc->dev;
8135         struct drm_i915_private *dev_priv = dev->dev_private;
8136         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8137         int pipe = intel_crtc->pipe;
8138         int x = crtc->cursor_x;
8139         int y = crtc->cursor_y;
8140         u32 base = 0, pos = 0;
8141
8142         if (on)
8143                 base = intel_crtc->cursor_addr;
8144
8145         if (x >= intel_crtc->config.pipe_src_w)
8146                 base = 0;
8147
8148         if (y >= intel_crtc->config.pipe_src_h)
8149                 base = 0;
8150
8151         if (x < 0) {
8152                 if (x + intel_crtc->cursor_width <= 0)
8153                         base = 0;
8154
8155                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8156                 x = -x;
8157         }
8158         pos |= x << CURSOR_X_SHIFT;
8159
8160         if (y < 0) {
8161                 if (y + intel_crtc->cursor_height <= 0)
8162                         base = 0;
8163
8164                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8165                 y = -y;
8166         }
8167         pos |= y << CURSOR_Y_SHIFT;
8168
8169         if (base == 0 && intel_crtc->cursor_base == 0)
8170                 return;
8171
8172         I915_WRITE(CURPOS(pipe), pos);
8173
8174         /* ILK+ do this automagically */
8175         if (HAS_GMCH_DISPLAY(dev) &&
8176                 to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180)) {
8177                 base += (intel_crtc->cursor_height *
8178                         intel_crtc->cursor_width - 1) * 4;
8179         }
8180
8181         if (IS_845G(dev) || IS_I865G(dev))
8182                 i845_update_cursor(crtc, base);
8183         else
8184                 i9xx_update_cursor(crtc, base);
8185 }
8186
8187 static bool cursor_size_ok(struct drm_device *dev,
8188                            uint32_t width, uint32_t height)
8189 {
8190         if (width == 0 || height == 0)
8191                 return false;
8192
8193         /*
8194          * 845g/865g are special in that they are only limited by
8195          * the width of their cursors, the height is arbitrary up to
8196          * the precision of the register. Everything else requires
8197          * square cursors, limited to a few power-of-two sizes.
8198          */
8199         if (IS_845G(dev) || IS_I865G(dev)) {
8200                 if ((width & 63) != 0)
8201                         return false;
8202
8203                 if (width > (IS_845G(dev) ? 64 : 512))
8204                         return false;
8205
8206                 if (height > 1023)
8207                         return false;
8208         } else {
8209                 switch (width | height) {
8210                 case 256:
8211                 case 128:
8212                         if (IS_GEN2(dev))
8213                                 return false;
8214                 case 64:
8215                         break;
8216                 default:
8217                         return false;
8218                 }
8219         }
8220
8221         return true;
8222 }
8223
8224 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8225                                      struct drm_i915_gem_object *obj,
8226                                      uint32_t width, uint32_t height)
8227 {
8228         struct drm_device *dev = crtc->dev;
8229         struct drm_i915_private *dev_priv = dev->dev_private;
8230         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8231         enum pipe pipe = intel_crtc->pipe;
8232         unsigned old_width;
8233         uint32_t addr;
8234         int ret;
8235
8236         /* if we want to turn off the cursor ignore width and height */
8237         if (!obj) {
8238                 DRM_DEBUG_KMS("cursor off\n");
8239                 addr = 0;
8240                 mutex_lock(&dev->struct_mutex);
8241                 goto finish;
8242         }
8243
8244         /* we only need to pin inside GTT if cursor is non-phy */
8245         mutex_lock(&dev->struct_mutex);
8246         if (!INTEL_INFO(dev)->cursor_needs_physical) {
8247                 unsigned alignment;
8248
8249                 /*
8250                  * Global gtt pte registers are special registers which actually
8251                  * forward writes to a chunk of system memory. Which means that
8252                  * there is no risk that the register values disappear as soon
8253                  * as we call intel_runtime_pm_put(), so it is correct to wrap
8254                  * only the pin/unpin/fence and not more.
8255                  */
8256                 intel_runtime_pm_get(dev_priv);
8257
8258                 /* Note that the w/a also requires 2 PTE of padding following
8259                  * the bo. We currently fill all unused PTE with the shadow
8260                  * page and so we should always have valid PTE following the
8261                  * cursor preventing the VT-d warning.
8262                  */
8263                 alignment = 0;
8264                 if (need_vtd_wa(dev))
8265                         alignment = 64*1024;
8266
8267                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8268                 if (ret) {
8269                         DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8270                         intel_runtime_pm_put(dev_priv);
8271                         goto fail_locked;
8272                 }
8273
8274                 ret = i915_gem_object_put_fence(obj);
8275                 if (ret) {
8276                         DRM_DEBUG_KMS("failed to release fence for cursor");
8277                         intel_runtime_pm_put(dev_priv);
8278                         goto fail_unpin;
8279                 }
8280
8281                 addr = i915_gem_obj_ggtt_offset(obj);
8282
8283                 intel_runtime_pm_put(dev_priv);
8284         } else {
8285                 int align = IS_I830(dev) ? 16 * 1024 : 256;
8286                 ret = i915_gem_object_attach_phys(obj, align);
8287                 if (ret) {
8288                         DRM_DEBUG_KMS("failed to attach phys object\n");
8289                         goto fail_locked;
8290                 }
8291                 addr = obj->phys_handle->busaddr;
8292         }
8293
8294  finish:
8295         if (intel_crtc->cursor_bo) {
8296                 if (!INTEL_INFO(dev)->cursor_needs_physical)
8297                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8298         }
8299
8300         i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8301                           INTEL_FRONTBUFFER_CURSOR(pipe));
8302         mutex_unlock(&dev->struct_mutex);
8303
8304         old_width = intel_crtc->cursor_width;
8305
8306         intel_crtc->cursor_addr = addr;
8307         intel_crtc->cursor_bo = obj;
8308         intel_crtc->cursor_width = width;
8309         intel_crtc->cursor_height = height;
8310
8311         if (intel_crtc->active) {
8312                 if (old_width != width)
8313                         intel_update_watermarks(crtc);
8314                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8315
8316                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8317         }
8318
8319         return 0;
8320 fail_unpin:
8321         i915_gem_object_unpin_from_display_plane(obj);
8322 fail_locked:
8323         mutex_unlock(&dev->struct_mutex);
8324         return ret;
8325 }
8326
8327 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8328                                  u16 *blue, uint32_t start, uint32_t size)
8329 {
8330         int end = (start + size > 256) ? 256 : start + size, i;
8331         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8332
8333         for (i = start; i < end; i++) {
8334                 intel_crtc->lut_r[i] = red[i] >> 8;
8335                 intel_crtc->lut_g[i] = green[i] >> 8;
8336                 intel_crtc->lut_b[i] = blue[i] >> 8;
8337         }
8338
8339         intel_crtc_load_lut(crtc);
8340 }
8341
8342 /* VESA 640x480x72Hz mode to set on the pipe */
8343 static struct drm_display_mode load_detect_mode = {
8344         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8345                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8346 };
8347
8348 struct drm_framebuffer *
8349 __intel_framebuffer_create(struct drm_device *dev,
8350                            struct drm_mode_fb_cmd2 *mode_cmd,
8351                            struct drm_i915_gem_object *obj)
8352 {
8353         struct intel_framebuffer *intel_fb;
8354         int ret;
8355
8356         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8357         if (!intel_fb) {
8358                 drm_gem_object_unreference_unlocked(&obj->base);
8359                 return ERR_PTR(-ENOMEM);
8360         }
8361
8362         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8363         if (ret)
8364                 goto err;
8365
8366         return &intel_fb->base;
8367 err:
8368         drm_gem_object_unreference_unlocked(&obj->base);
8369         kfree(intel_fb);
8370
8371         return ERR_PTR(ret);
8372 }
8373
8374 static struct drm_framebuffer *
8375 intel_framebuffer_create(struct drm_device *dev,
8376                          struct drm_mode_fb_cmd2 *mode_cmd,
8377                          struct drm_i915_gem_object *obj)
8378 {
8379         struct drm_framebuffer *fb;
8380         int ret;
8381
8382         ret = i915_mutex_lock_interruptible(dev);
8383         if (ret)
8384                 return ERR_PTR(ret);
8385         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8386         mutex_unlock(&dev->struct_mutex);
8387
8388         return fb;
8389 }
8390
8391 static u32
8392 intel_framebuffer_pitch_for_width(int width, int bpp)
8393 {
8394         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8395         return ALIGN(pitch, 64);
8396 }
8397
8398 static u32
8399 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8400 {
8401         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8402         return PAGE_ALIGN(pitch * mode->vdisplay);
8403 }
8404
8405 static struct drm_framebuffer *
8406 intel_framebuffer_create_for_mode(struct drm_device *dev,
8407                                   struct drm_display_mode *mode,
8408                                   int depth, int bpp)
8409 {
8410         struct drm_i915_gem_object *obj;
8411         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8412
8413         obj = i915_gem_alloc_object(dev,
8414                                     intel_framebuffer_size_for_mode(mode, bpp));
8415         if (obj == NULL)
8416                 return ERR_PTR(-ENOMEM);
8417
8418         mode_cmd.width = mode->hdisplay;
8419         mode_cmd.height = mode->vdisplay;
8420         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8421                                                                 bpp);
8422         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8423
8424         return intel_framebuffer_create(dev, &mode_cmd, obj);
8425 }
8426
8427 static struct drm_framebuffer *
8428 mode_fits_in_fbdev(struct drm_device *dev,
8429                    struct drm_display_mode *mode)
8430 {
8431 #ifdef CONFIG_DRM_I915_FBDEV
8432         struct drm_i915_private *dev_priv = dev->dev_private;
8433         struct drm_i915_gem_object *obj;
8434         struct drm_framebuffer *fb;
8435
8436         if (!dev_priv->fbdev)
8437                 return NULL;
8438
8439         if (!dev_priv->fbdev->fb)
8440                 return NULL;
8441
8442         obj = dev_priv->fbdev->fb->obj;
8443         BUG_ON(!obj);
8444
8445         fb = &dev_priv->fbdev->fb->base;
8446         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8447                                                                fb->bits_per_pixel))
8448                 return NULL;
8449
8450         if (obj->base.size < mode->vdisplay * fb->pitches[0])
8451                 return NULL;
8452
8453         return fb;
8454 #else
8455         return NULL;
8456 #endif
8457 }
8458
8459 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8460                                 struct drm_display_mode *mode,
8461                                 struct intel_load_detect_pipe *old,
8462                                 struct drm_modeset_acquire_ctx *ctx)
8463 {
8464         struct intel_crtc *intel_crtc;
8465         struct intel_encoder *intel_encoder =
8466                 intel_attached_encoder(connector);
8467         struct drm_crtc *possible_crtc;
8468         struct drm_encoder *encoder = &intel_encoder->base;
8469         struct drm_crtc *crtc = NULL;
8470         struct drm_device *dev = encoder->dev;
8471         struct drm_framebuffer *fb;
8472         struct drm_mode_config *config = &dev->mode_config;
8473         int ret, i = -1;
8474
8475         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8476                       connector->base.id, connector->name,
8477                       encoder->base.id, encoder->name);
8478
8479 retry:
8480         ret = drm_modeset_lock(&config->connection_mutex, ctx);
8481         if (ret)
8482                 goto fail_unlock;
8483
8484         /*
8485          * Algorithm gets a little messy:
8486          *
8487          *   - if the connector already has an assigned crtc, use it (but make
8488          *     sure it's on first)
8489          *
8490          *   - try to find the first unused crtc that can drive this connector,
8491          *     and use that if we find one
8492          */
8493
8494         /* See if we already have a CRTC for this connector */
8495         if (encoder->crtc) {
8496                 crtc = encoder->crtc;
8497
8498                 ret = drm_modeset_lock(&crtc->mutex, ctx);
8499                 if (ret)
8500                         goto fail_unlock;
8501
8502                 old->dpms_mode = connector->dpms;
8503                 old->load_detect_temp = false;
8504
8505                 /* Make sure the crtc and connector are running */
8506                 if (connector->dpms != DRM_MODE_DPMS_ON)
8507                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8508
8509                 return true;
8510         }
8511
8512         /* Find an unused one (if possible) */
8513         for_each_crtc(dev, possible_crtc) {
8514                 i++;
8515                 if (!(encoder->possible_crtcs & (1 << i)))
8516                         continue;
8517                 if (possible_crtc->enabled)
8518                         continue;
8519                 /* This can occur when applying the pipe A quirk on resume. */
8520                 if (to_intel_crtc(possible_crtc)->new_enabled)
8521                         continue;
8522
8523                 crtc = possible_crtc;
8524                 break;
8525         }
8526
8527         /*
8528          * If we didn't find an unused CRTC, don't use any.
8529          */
8530         if (!crtc) {
8531                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8532                 goto fail_unlock;
8533         }
8534
8535         ret = drm_modeset_lock(&crtc->mutex, ctx);
8536         if (ret)
8537                 goto fail_unlock;
8538         intel_encoder->new_crtc = to_intel_crtc(crtc);
8539         to_intel_connector(connector)->new_encoder = intel_encoder;
8540
8541         intel_crtc = to_intel_crtc(crtc);
8542         intel_crtc->new_enabled = true;
8543         intel_crtc->new_config = &intel_crtc->config;
8544         old->dpms_mode = connector->dpms;
8545         old->load_detect_temp = true;
8546         old->release_fb = NULL;
8547
8548         if (!mode)
8549                 mode = &load_detect_mode;
8550
8551         /* We need a framebuffer large enough to accommodate all accesses
8552          * that the plane may generate whilst we perform load detection.
8553          * We can not rely on the fbcon either being present (we get called
8554          * during its initialisation to detect all boot displays, or it may
8555          * not even exist) or that it is large enough to satisfy the
8556          * requested mode.
8557          */
8558         fb = mode_fits_in_fbdev(dev, mode);
8559         if (fb == NULL) {
8560                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8561                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8562                 old->release_fb = fb;
8563         } else
8564                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8565         if (IS_ERR(fb)) {
8566                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8567                 goto fail;
8568         }
8569
8570         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8571                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8572                 if (old->release_fb)
8573                         old->release_fb->funcs->destroy(old->release_fb);
8574                 goto fail;
8575         }
8576
8577         /* let the connector get through one full cycle before testing */
8578         intel_wait_for_vblank(dev, intel_crtc->pipe);
8579         return true;
8580
8581  fail:
8582         intel_crtc->new_enabled = crtc->enabled;
8583         if (intel_crtc->new_enabled)
8584                 intel_crtc->new_config = &intel_crtc->config;
8585         else
8586                 intel_crtc->new_config = NULL;
8587 fail_unlock:
8588         if (ret == -EDEADLK) {
8589                 drm_modeset_backoff(ctx);
8590                 goto retry;
8591         }
8592
8593         return false;
8594 }
8595
8596 void intel_release_load_detect_pipe(struct drm_connector *connector,
8597                                     struct intel_load_detect_pipe *old)
8598 {
8599         struct intel_encoder *intel_encoder =
8600                 intel_attached_encoder(connector);
8601         struct drm_encoder *encoder = &intel_encoder->base;
8602         struct drm_crtc *crtc = encoder->crtc;
8603         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8604
8605         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8606                       connector->base.id, connector->name,
8607                       encoder->base.id, encoder->name);
8608
8609         if (old->load_detect_temp) {
8610                 to_intel_connector(connector)->new_encoder = NULL;
8611                 intel_encoder->new_crtc = NULL;
8612                 intel_crtc->new_enabled = false;
8613                 intel_crtc->new_config = NULL;
8614                 intel_set_mode(crtc, NULL, 0, 0, NULL);
8615
8616                 if (old->release_fb) {
8617                         drm_framebuffer_unregister_private(old->release_fb);
8618                         drm_framebuffer_unreference(old->release_fb);
8619                 }
8620
8621                 return;
8622         }
8623
8624         /* Switch crtc and encoder back off if necessary */
8625         if (old->dpms_mode != DRM_MODE_DPMS_ON)
8626                 connector->funcs->dpms(connector, old->dpms_mode);
8627 }
8628
8629 static int i9xx_pll_refclk(struct drm_device *dev,
8630                            const struct intel_crtc_config *pipe_config)
8631 {
8632         struct drm_i915_private *dev_priv = dev->dev_private;
8633         u32 dpll = pipe_config->dpll_hw_state.dpll;
8634
8635         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8636                 return dev_priv->vbt.lvds_ssc_freq;
8637         else if (HAS_PCH_SPLIT(dev))
8638                 return 120000;
8639         else if (!IS_GEN2(dev))
8640                 return 96000;
8641         else
8642                 return 48000;
8643 }
8644
8645 /* Returns the clock of the currently programmed mode of the given pipe. */
8646 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8647                                 struct intel_crtc_config *pipe_config)
8648 {
8649         struct drm_device *dev = crtc->base.dev;
8650         struct drm_i915_private *dev_priv = dev->dev_private;
8651         int pipe = pipe_config->cpu_transcoder;
8652         u32 dpll = pipe_config->dpll_hw_state.dpll;
8653         u32 fp;
8654         intel_clock_t clock;
8655         int refclk = i9xx_pll_refclk(dev, pipe_config);
8656
8657         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8658                 fp = pipe_config->dpll_hw_state.fp0;
8659         else
8660                 fp = pipe_config->dpll_hw_state.fp1;
8661
8662         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8663         if (IS_PINEVIEW(dev)) {
8664                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8665                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8666         } else {
8667                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8668                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8669         }
8670
8671         if (!IS_GEN2(dev)) {
8672                 if (IS_PINEVIEW(dev))
8673                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8674                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8675                 else
8676                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8677                                DPLL_FPA01_P1_POST_DIV_SHIFT);
8678
8679                 switch (dpll & DPLL_MODE_MASK) {
8680                 case DPLLB_MODE_DAC_SERIAL:
8681                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8682                                 5 : 10;
8683                         break;
8684                 case DPLLB_MODE_LVDS:
8685                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8686                                 7 : 14;
8687                         break;
8688                 default:
8689                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8690                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
8691                         return;
8692                 }
8693
8694                 if (IS_PINEVIEW(dev))
8695                         pineview_clock(refclk, &clock);
8696                 else
8697                         i9xx_clock(refclk, &clock);
8698         } else {
8699                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8700                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8701
8702                 if (is_lvds) {
8703                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8704                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
8705
8706                         if (lvds & LVDS_CLKB_POWER_UP)
8707                                 clock.p2 = 7;
8708                         else
8709                                 clock.p2 = 14;
8710                 } else {
8711                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
8712                                 clock.p1 = 2;
8713                         else {
8714                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8715                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8716                         }
8717                         if (dpll & PLL_P2_DIVIDE_BY_4)
8718                                 clock.p2 = 4;
8719                         else
8720                                 clock.p2 = 2;
8721                 }
8722
8723                 i9xx_clock(refclk, &clock);
8724         }
8725
8726         /*
8727          * This value includes pixel_multiplier. We will use
8728          * port_clock to compute adjusted_mode.crtc_clock in the
8729          * encoder's get_config() function.
8730          */
8731         pipe_config->port_clock = clock.dot;
8732 }
8733
8734 int intel_dotclock_calculate(int link_freq,
8735                              const struct intel_link_m_n *m_n)
8736 {
8737         /*
8738          * The calculation for the data clock is:
8739          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8740          * But we want to avoid losing precison if possible, so:
8741          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8742          *
8743          * and the link clock is simpler:
8744          * link_clock = (m * link_clock) / n
8745          */
8746
8747         if (!m_n->link_n)
8748                 return 0;
8749
8750         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8751 }
8752
8753 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8754                                    struct intel_crtc_config *pipe_config)
8755 {
8756         struct drm_device *dev = crtc->base.dev;
8757
8758         /* read out port_clock from the DPLL */
8759         i9xx_crtc_clock_get(crtc, pipe_config);
8760
8761         /*
8762          * This value does not include pixel_multiplier.
8763          * We will check that port_clock and adjusted_mode.crtc_clock
8764          * agree once we know their relationship in the encoder's
8765          * get_config() function.
8766          */
8767         pipe_config->adjusted_mode.crtc_clock =
8768                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8769                                          &pipe_config->fdi_m_n);
8770 }
8771
8772 /** Returns the currently programmed mode of the given pipe. */
8773 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8774                                              struct drm_crtc *crtc)
8775 {
8776         struct drm_i915_private *dev_priv = dev->dev_private;
8777         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8778         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8779         struct drm_display_mode *mode;
8780         struct intel_crtc_config pipe_config;
8781         int htot = I915_READ(HTOTAL(cpu_transcoder));
8782         int hsync = I915_READ(HSYNC(cpu_transcoder));
8783         int vtot = I915_READ(VTOTAL(cpu_transcoder));
8784         int vsync = I915_READ(VSYNC(cpu_transcoder));
8785         enum pipe pipe = intel_crtc->pipe;
8786
8787         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8788         if (!mode)
8789                 return NULL;
8790
8791         /*
8792          * Construct a pipe_config sufficient for getting the clock info
8793          * back out of crtc_clock_get.
8794          *
8795          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8796          * to use a real value here instead.
8797          */
8798         pipe_config.cpu_transcoder = (enum transcoder) pipe;
8799         pipe_config.pixel_multiplier = 1;
8800         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8801         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8802         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8803         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8804
8805         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8806         mode->hdisplay = (htot & 0xffff) + 1;
8807         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8808         mode->hsync_start = (hsync & 0xffff) + 1;
8809         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8810         mode->vdisplay = (vtot & 0xffff) + 1;
8811         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8812         mode->vsync_start = (vsync & 0xffff) + 1;
8813         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8814
8815         drm_mode_set_name(mode);
8816
8817         return mode;
8818 }
8819
8820 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8821 {
8822         struct drm_device *dev = crtc->dev;
8823         struct drm_i915_private *dev_priv = dev->dev_private;
8824         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8825
8826         if (!HAS_GMCH_DISPLAY(dev))
8827                 return;
8828
8829         if (!dev_priv->lvds_downclock_avail)
8830                 return;
8831
8832         /*
8833          * Since this is called by a timer, we should never get here in
8834          * the manual case.
8835          */
8836         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8837                 int pipe = intel_crtc->pipe;
8838                 int dpll_reg = DPLL(pipe);
8839                 int dpll;
8840
8841                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8842
8843                 assert_panel_unlocked(dev_priv, pipe);
8844
8845                 dpll = I915_READ(dpll_reg);
8846                 dpll |= DISPLAY_RATE_SELECT_FPA1;
8847                 I915_WRITE(dpll_reg, dpll);
8848                 intel_wait_for_vblank(dev, pipe);
8849                 dpll = I915_READ(dpll_reg);
8850                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8851                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8852         }
8853
8854 }
8855
8856 void intel_mark_busy(struct drm_device *dev)
8857 {
8858         struct drm_i915_private *dev_priv = dev->dev_private;
8859
8860         if (dev_priv->mm.busy)
8861                 return;
8862
8863         intel_runtime_pm_get(dev_priv);
8864         i915_update_gfx_val(dev_priv);
8865         dev_priv->mm.busy = true;
8866 }
8867
8868 void intel_mark_idle(struct drm_device *dev)
8869 {
8870         struct drm_i915_private *dev_priv = dev->dev_private;
8871         struct drm_crtc *crtc;
8872
8873         if (!dev_priv->mm.busy)
8874                 return;
8875
8876         dev_priv->mm.busy = false;
8877
8878         if (!i915.powersave)
8879                 goto out;
8880
8881         for_each_crtc(dev, crtc) {
8882                 if (!crtc->primary->fb)
8883                         continue;
8884
8885                 intel_decrease_pllclock(crtc);
8886         }
8887
8888         if (INTEL_INFO(dev)->gen >= 6)
8889                 gen6_rps_idle(dev->dev_private);
8890
8891 out:
8892         intel_runtime_pm_put(dev_priv);
8893 }
8894
8895 static void intel_crtc_destroy(struct drm_crtc *crtc)
8896 {
8897         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8898         struct drm_device *dev = crtc->dev;
8899         struct intel_unpin_work *work;
8900
8901         spin_lock_irq(&dev->event_lock);
8902         work = intel_crtc->unpin_work;
8903         intel_crtc->unpin_work = NULL;
8904         spin_unlock_irq(&dev->event_lock);
8905
8906         if (work) {
8907                 cancel_work_sync(&work->work);
8908                 kfree(work);
8909         }
8910
8911         drm_crtc_cleanup(crtc);
8912
8913         kfree(intel_crtc);
8914 }
8915
8916 static void intel_unpin_work_fn(struct work_struct *__work)
8917 {
8918         struct intel_unpin_work *work =
8919                 container_of(__work, struct intel_unpin_work, work);
8920         struct drm_device *dev = work->crtc->dev;
8921         enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
8922
8923         mutex_lock(&dev->struct_mutex);
8924         intel_unpin_fb_obj(work->old_fb_obj);
8925         drm_gem_object_unreference(&work->pending_flip_obj->base);
8926         drm_gem_object_unreference(&work->old_fb_obj->base);
8927
8928         intel_update_fbc(dev);
8929         mutex_unlock(&dev->struct_mutex);
8930
8931         intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
8932
8933         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8934         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8935
8936         kfree(work);
8937 }
8938
8939 static void do_intel_finish_page_flip(struct drm_device *dev,
8940                                       struct drm_crtc *crtc)
8941 {
8942         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8943         struct intel_unpin_work *work;
8944         unsigned long flags;
8945
8946         /* Ignore early vblank irqs */
8947         if (intel_crtc == NULL)
8948                 return;
8949
8950         /*
8951          * This is called both by irq handlers and the reset code (to complete
8952          * lost pageflips) so needs the full irqsave spinlocks.
8953          */
8954         spin_lock_irqsave(&dev->event_lock, flags);
8955         work = intel_crtc->unpin_work;
8956
8957         /* Ensure we don't miss a work->pending update ... */
8958         smp_rmb();
8959
8960         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8961                 spin_unlock_irqrestore(&dev->event_lock, flags);
8962                 return;
8963         }
8964
8965         page_flip_completed(intel_crtc);
8966
8967         spin_unlock_irqrestore(&dev->event_lock, flags);
8968 }
8969
8970 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8971 {
8972         struct drm_i915_private *dev_priv = dev->dev_private;
8973         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8974
8975         do_intel_finish_page_flip(dev, crtc);
8976 }
8977
8978 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8979 {
8980         struct drm_i915_private *dev_priv = dev->dev_private;
8981         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8982
8983         do_intel_finish_page_flip(dev, crtc);
8984 }
8985
8986 /* Is 'a' after or equal to 'b'? */
8987 static bool g4x_flip_count_after_eq(u32 a, u32 b)
8988 {
8989         return !((a - b) & 0x80000000);
8990 }
8991
8992 static bool page_flip_finished(struct intel_crtc *crtc)
8993 {
8994         struct drm_device *dev = crtc->base.dev;
8995         struct drm_i915_private *dev_priv = dev->dev_private;
8996
8997         /*
8998          * The relevant registers doen't exist on pre-ctg.
8999          * As the flip done interrupt doesn't trigger for mmio
9000          * flips on gmch platforms, a flip count check isn't
9001          * really needed there. But since ctg has the registers,
9002          * include it in the check anyway.
9003          */
9004         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9005                 return true;
9006
9007         /*
9008          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9009          * used the same base address. In that case the mmio flip might
9010          * have completed, but the CS hasn't even executed the flip yet.
9011          *
9012          * A flip count check isn't enough as the CS might have updated
9013          * the base address just after start of vblank, but before we
9014          * managed to process the interrupt. This means we'd complete the
9015          * CS flip too soon.
9016          *
9017          * Combining both checks should get us a good enough result. It may
9018          * still happen that the CS flip has been executed, but has not
9019          * yet actually completed. But in case the base address is the same
9020          * anyway, we don't really care.
9021          */
9022         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9023                 crtc->unpin_work->gtt_offset &&
9024                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9025                                     crtc->unpin_work->flip_count);
9026 }
9027
9028 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9029 {
9030         struct drm_i915_private *dev_priv = dev->dev_private;
9031         struct intel_crtc *intel_crtc =
9032                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9033         unsigned long flags;
9034
9035
9036         /*
9037          * This is called both by irq handlers and the reset code (to complete
9038          * lost pageflips) so needs the full irqsave spinlocks.
9039          *
9040          * NB: An MMIO update of the plane base pointer will also
9041          * generate a page-flip completion irq, i.e. every modeset
9042          * is also accompanied by a spurious intel_prepare_page_flip().
9043          */
9044         spin_lock_irqsave(&dev->event_lock, flags);
9045         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9046                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9047         spin_unlock_irqrestore(&dev->event_lock, flags);
9048 }
9049
9050 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9051 {
9052         /* Ensure that the work item is consistent when activating it ... */
9053         smp_wmb();
9054         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9055         /* and that it is marked active as soon as the irq could fire. */
9056         smp_wmb();
9057 }
9058
9059 static int intel_gen2_queue_flip(struct drm_device *dev,
9060                                  struct drm_crtc *crtc,
9061                                  struct drm_framebuffer *fb,
9062                                  struct drm_i915_gem_object *obj,
9063                                  struct intel_engine_cs *ring,
9064                                  uint32_t flags)
9065 {
9066         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9067         u32 flip_mask;
9068         int ret;
9069
9070         ret = intel_ring_begin(ring, 6);
9071         if (ret)
9072                 return ret;
9073
9074         /* Can't queue multiple flips, so wait for the previous
9075          * one to finish before executing the next.
9076          */
9077         if (intel_crtc->plane)
9078                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9079         else
9080                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9081         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9082         intel_ring_emit(ring, MI_NOOP);
9083         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9084                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9085         intel_ring_emit(ring, fb->pitches[0]);
9086         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9087         intel_ring_emit(ring, 0); /* aux display base address, unused */
9088
9089         intel_mark_page_flip_active(intel_crtc);
9090         __intel_ring_advance(ring);
9091         return 0;
9092 }
9093
9094 static int intel_gen3_queue_flip(struct drm_device *dev,
9095                                  struct drm_crtc *crtc,
9096                                  struct drm_framebuffer *fb,
9097                                  struct drm_i915_gem_object *obj,
9098                                  struct intel_engine_cs *ring,
9099                                  uint32_t flags)
9100 {
9101         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9102         u32 flip_mask;
9103         int ret;
9104
9105         ret = intel_ring_begin(ring, 6);
9106         if (ret)
9107                 return ret;
9108
9109         if (intel_crtc->plane)
9110                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9111         else
9112                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9113         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9114         intel_ring_emit(ring, MI_NOOP);
9115         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9116                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9117         intel_ring_emit(ring, fb->pitches[0]);
9118         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9119         intel_ring_emit(ring, MI_NOOP);
9120
9121         intel_mark_page_flip_active(intel_crtc);
9122         __intel_ring_advance(ring);
9123         return 0;
9124 }
9125
9126 static int intel_gen4_queue_flip(struct drm_device *dev,
9127                                  struct drm_crtc *crtc,
9128                                  struct drm_framebuffer *fb,
9129                                  struct drm_i915_gem_object *obj,
9130                                  struct intel_engine_cs *ring,
9131                                  uint32_t flags)
9132 {
9133         struct drm_i915_private *dev_priv = dev->dev_private;
9134         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9135         uint32_t pf, pipesrc;
9136         int ret;
9137
9138         ret = intel_ring_begin(ring, 4);
9139         if (ret)
9140                 return ret;
9141
9142         /* i965+ uses the linear or tiled offsets from the
9143          * Display Registers (which do not change across a page-flip)
9144          * so we need only reprogram the base address.
9145          */
9146         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9147                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9148         intel_ring_emit(ring, fb->pitches[0]);
9149         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9150                         obj->tiling_mode);
9151
9152         /* XXX Enabling the panel-fitter across page-flip is so far
9153          * untested on non-native modes, so ignore it for now.
9154          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9155          */
9156         pf = 0;
9157         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9158         intel_ring_emit(ring, pf | pipesrc);
9159
9160         intel_mark_page_flip_active(intel_crtc);
9161         __intel_ring_advance(ring);
9162         return 0;
9163 }
9164
9165 static int intel_gen6_queue_flip(struct drm_device *dev,
9166                                  struct drm_crtc *crtc,
9167                                  struct drm_framebuffer *fb,
9168                                  struct drm_i915_gem_object *obj,
9169                                  struct intel_engine_cs *ring,
9170                                  uint32_t flags)
9171 {
9172         struct drm_i915_private *dev_priv = dev->dev_private;
9173         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9174         uint32_t pf, pipesrc;
9175         int ret;
9176
9177         ret = intel_ring_begin(ring, 4);
9178         if (ret)
9179                 return ret;
9180
9181         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9182                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9183         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9184         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9185
9186         /* Contrary to the suggestions in the documentation,
9187          * "Enable Panel Fitter" does not seem to be required when page
9188          * flipping with a non-native mode, and worse causes a normal
9189          * modeset to fail.
9190          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9191          */
9192         pf = 0;
9193         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9194         intel_ring_emit(ring, pf | pipesrc);
9195
9196         intel_mark_page_flip_active(intel_crtc);
9197         __intel_ring_advance(ring);
9198         return 0;
9199 }
9200
9201 static int intel_gen7_queue_flip(struct drm_device *dev,
9202                                  struct drm_crtc *crtc,
9203                                  struct drm_framebuffer *fb,
9204                                  struct drm_i915_gem_object *obj,
9205                                  struct intel_engine_cs *ring,
9206                                  uint32_t flags)
9207 {
9208         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9209         uint32_t plane_bit = 0;
9210         int len, ret;
9211
9212         switch (intel_crtc->plane) {
9213         case PLANE_A:
9214                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9215                 break;
9216         case PLANE_B:
9217                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9218                 break;
9219         case PLANE_C:
9220                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9221                 break;
9222         default:
9223                 WARN_ONCE(1, "unknown plane in flip command\n");
9224                 return -ENODEV;
9225         }
9226
9227         len = 4;
9228         if (ring->id == RCS) {
9229                 len += 6;
9230                 /*
9231                  * On Gen 8, SRM is now taking an extra dword to accommodate
9232                  * 48bits addresses, and we need a NOOP for the batch size to
9233                  * stay even.
9234                  */
9235                 if (IS_GEN8(dev))
9236                         len += 2;
9237         }
9238
9239         /*
9240          * BSpec MI_DISPLAY_FLIP for IVB:
9241          * "The full packet must be contained within the same cache line."
9242          *
9243          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9244          * cacheline, if we ever start emitting more commands before
9245          * the MI_DISPLAY_FLIP we may need to first emit everything else,
9246          * then do the cacheline alignment, and finally emit the
9247          * MI_DISPLAY_FLIP.
9248          */
9249         ret = intel_ring_cacheline_align(ring);
9250         if (ret)
9251                 return ret;
9252
9253         ret = intel_ring_begin(ring, len);
9254         if (ret)
9255                 return ret;
9256
9257         /* Unmask the flip-done completion message. Note that the bspec says that
9258          * we should do this for both the BCS and RCS, and that we must not unmask
9259          * more than one flip event at any time (or ensure that one flip message
9260          * can be sent by waiting for flip-done prior to queueing new flips).
9261          * Experimentation says that BCS works despite DERRMR masking all
9262          * flip-done completion events and that unmasking all planes at once
9263          * for the RCS also doesn't appear to drop events. Setting the DERRMR
9264          * to zero does lead to lockups within MI_DISPLAY_FLIP.
9265          */
9266         if (ring->id == RCS) {
9267                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9268                 intel_ring_emit(ring, DERRMR);
9269                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9270                                         DERRMR_PIPEB_PRI_FLIP_DONE |
9271                                         DERRMR_PIPEC_PRI_FLIP_DONE));
9272                 if (IS_GEN8(dev))
9273                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9274                                               MI_SRM_LRM_GLOBAL_GTT);
9275                 else
9276                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9277                                               MI_SRM_LRM_GLOBAL_GTT);
9278                 intel_ring_emit(ring, DERRMR);
9279                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9280                 if (IS_GEN8(dev)) {
9281                         intel_ring_emit(ring, 0);
9282                         intel_ring_emit(ring, MI_NOOP);
9283                 }
9284         }
9285
9286         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9287         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9288         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9289         intel_ring_emit(ring, (MI_NOOP));
9290
9291         intel_mark_page_flip_active(intel_crtc);
9292         __intel_ring_advance(ring);
9293         return 0;
9294 }
9295
9296 static bool use_mmio_flip(struct intel_engine_cs *ring,
9297                           struct drm_i915_gem_object *obj)
9298 {
9299         /*
9300          * This is not being used for older platforms, because
9301          * non-availability of flip done interrupt forces us to use
9302          * CS flips. Older platforms derive flip done using some clever
9303          * tricks involving the flip_pending status bits and vblank irqs.
9304          * So using MMIO flips there would disrupt this mechanism.
9305          */
9306
9307         if (ring == NULL)
9308                 return true;
9309
9310         if (INTEL_INFO(ring->dev)->gen < 5)
9311                 return false;
9312
9313         if (i915.use_mmio_flip < 0)
9314                 return false;
9315         else if (i915.use_mmio_flip > 0)
9316                 return true;
9317         else if (i915.enable_execlists)
9318                 return true;
9319         else
9320                 return ring != obj->ring;
9321 }
9322
9323 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9324 {
9325         struct drm_device *dev = intel_crtc->base.dev;
9326         struct drm_i915_private *dev_priv = dev->dev_private;
9327         struct intel_framebuffer *intel_fb =
9328                 to_intel_framebuffer(intel_crtc->base.primary->fb);
9329         struct drm_i915_gem_object *obj = intel_fb->obj;
9330         u32 dspcntr;
9331         u32 reg;
9332
9333         intel_mark_page_flip_active(intel_crtc);
9334
9335         reg = DSPCNTR(intel_crtc->plane);
9336         dspcntr = I915_READ(reg);
9337
9338         if (obj->tiling_mode != I915_TILING_NONE)
9339                 dspcntr |= DISPPLANE_TILED;
9340         else
9341                 dspcntr &= ~DISPPLANE_TILED;
9342
9343         I915_WRITE(reg, dspcntr);
9344
9345         I915_WRITE(DSPSURF(intel_crtc->plane),
9346                    intel_crtc->unpin_work->gtt_offset);
9347         POSTING_READ(DSPSURF(intel_crtc->plane));
9348 }
9349
9350 static int intel_postpone_flip(struct drm_i915_gem_object *obj)
9351 {
9352         struct intel_engine_cs *ring;
9353         int ret;
9354
9355         lockdep_assert_held(&obj->base.dev->struct_mutex);
9356
9357         if (!obj->last_write_seqno)
9358                 return 0;
9359
9360         ring = obj->ring;
9361
9362         if (i915_seqno_passed(ring->get_seqno(ring, true),
9363                               obj->last_write_seqno))
9364                 return 0;
9365
9366         ret = i915_gem_check_olr(ring, obj->last_write_seqno);
9367         if (ret)
9368                 return ret;
9369
9370         if (WARN_ON(!ring->irq_get(ring)))
9371                 return 0;
9372
9373         return 1;
9374 }
9375
9376 void intel_notify_mmio_flip(struct intel_engine_cs *ring)
9377 {
9378         struct drm_i915_private *dev_priv = to_i915(ring->dev);
9379         struct intel_crtc *intel_crtc;
9380         unsigned long irq_flags;
9381         u32 seqno;
9382
9383         seqno = ring->get_seqno(ring, false);
9384
9385         spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9386         for_each_intel_crtc(ring->dev, intel_crtc) {
9387                 struct intel_mmio_flip *mmio_flip;
9388
9389                 mmio_flip = &intel_crtc->mmio_flip;
9390                 if (mmio_flip->seqno == 0)
9391                         continue;
9392
9393                 if (ring->id != mmio_flip->ring_id)
9394                         continue;
9395
9396                 if (i915_seqno_passed(seqno, mmio_flip->seqno)) {
9397                         intel_do_mmio_flip(intel_crtc);
9398                         mmio_flip->seqno = 0;
9399                         ring->irq_put(ring);
9400                 }
9401         }
9402         spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9403 }
9404
9405 static int intel_queue_mmio_flip(struct drm_device *dev,
9406                                  struct drm_crtc *crtc,
9407                                  struct drm_framebuffer *fb,
9408                                  struct drm_i915_gem_object *obj,
9409                                  struct intel_engine_cs *ring,
9410                                  uint32_t flags)
9411 {
9412         struct drm_i915_private *dev_priv = dev->dev_private;
9413         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9414         int ret;
9415
9416         if (WARN_ON(intel_crtc->mmio_flip.seqno))
9417                 return -EBUSY;
9418
9419         ret = intel_postpone_flip(obj);
9420         if (ret < 0)
9421                 return ret;
9422         if (ret == 0) {
9423                 intel_do_mmio_flip(intel_crtc);
9424                 return 0;
9425         }
9426
9427         spin_lock_irq(&dev_priv->mmio_flip_lock);
9428         intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9429         intel_crtc->mmio_flip.ring_id = obj->ring->id;
9430         spin_unlock_irq(&dev_priv->mmio_flip_lock);
9431
9432         /*
9433          * Double check to catch cases where irq fired before
9434          * mmio flip data was ready
9435          */
9436         intel_notify_mmio_flip(obj->ring);
9437         return 0;
9438 }
9439
9440 static int intel_default_queue_flip(struct drm_device *dev,
9441                                     struct drm_crtc *crtc,
9442                                     struct drm_framebuffer *fb,
9443                                     struct drm_i915_gem_object *obj,
9444                                     struct intel_engine_cs *ring,
9445                                     uint32_t flags)
9446 {
9447         return -ENODEV;
9448 }
9449
9450 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9451                                          struct drm_crtc *crtc)
9452 {
9453         struct drm_i915_private *dev_priv = dev->dev_private;
9454         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9455         struct intel_unpin_work *work = intel_crtc->unpin_work;
9456         u32 addr;
9457
9458         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9459                 return true;
9460
9461         if (!work->enable_stall_check)
9462                 return false;
9463
9464         if (work->flip_ready_vblank == 0) {
9465                 if (work->flip_queued_ring &&
9466                     !i915_seqno_passed(work->flip_queued_ring->get_seqno(work->flip_queued_ring, true),
9467                                        work->flip_queued_seqno))
9468                         return false;
9469
9470                 work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9471         }
9472
9473         if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3)
9474                 return false;
9475
9476         /* Potential stall - if we see that the flip has happened,
9477          * assume a missed interrupt. */
9478         if (INTEL_INFO(dev)->gen >= 4)
9479                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9480         else
9481                 addr = I915_READ(DSPADDR(intel_crtc->plane));
9482
9483         /* There is a potential issue here with a false positive after a flip
9484          * to the same address. We could address this by checking for a
9485          * non-incrementing frame counter.
9486          */
9487         return addr == work->gtt_offset;
9488 }
9489
9490 void intel_check_page_flip(struct drm_device *dev, int pipe)
9491 {
9492         struct drm_i915_private *dev_priv = dev->dev_private;
9493         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9494         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9495
9496         WARN_ON(!in_irq());
9497
9498         if (crtc == NULL)
9499                 return;
9500
9501         spin_lock(&dev->event_lock);
9502         if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9503                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9504                          intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe));
9505                 page_flip_completed(intel_crtc);
9506         }
9507         spin_unlock(&dev->event_lock);
9508 }
9509
9510 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9511                                 struct drm_framebuffer *fb,
9512                                 struct drm_pending_vblank_event *event,
9513                                 uint32_t page_flip_flags)
9514 {
9515         struct drm_device *dev = crtc->dev;
9516         struct drm_i915_private *dev_priv = dev->dev_private;
9517         struct drm_framebuffer *old_fb = crtc->primary->fb;
9518         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9519         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9520         enum pipe pipe = intel_crtc->pipe;
9521         struct intel_unpin_work *work;
9522         struct intel_engine_cs *ring;
9523         int ret;
9524
9525         /*
9526          * drm_mode_page_flip_ioctl() should already catch this, but double
9527          * check to be safe.  In the future we may enable pageflipping from
9528          * a disabled primary plane.
9529          */
9530         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9531                 return -EBUSY;
9532
9533         /* Can't change pixel format via MI display flips. */
9534         if (fb->pixel_format != crtc->primary->fb->pixel_format)
9535                 return -EINVAL;
9536
9537         /*
9538          * TILEOFF/LINOFF registers can't be changed via MI display flips.
9539          * Note that pitch changes could also affect these register.
9540          */
9541         if (INTEL_INFO(dev)->gen > 3 &&
9542             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9543              fb->pitches[0] != crtc->primary->fb->pitches[0]))
9544                 return -EINVAL;
9545
9546         if (i915_terminally_wedged(&dev_priv->gpu_error))
9547                 goto out_hang;
9548
9549         work = kzalloc(sizeof(*work), GFP_KERNEL);
9550         if (work == NULL)
9551                 return -ENOMEM;
9552
9553         work->event = event;
9554         work->crtc = crtc;
9555         work->old_fb_obj = intel_fb_obj(old_fb);
9556         INIT_WORK(&work->work, intel_unpin_work_fn);
9557
9558         ret = drm_crtc_vblank_get(crtc);
9559         if (ret)
9560                 goto free_work;
9561
9562         /* We borrow the event spin lock for protecting unpin_work */
9563         spin_lock_irq(&dev->event_lock);
9564         if (intel_crtc->unpin_work) {
9565                 /* Before declaring the flip queue wedged, check if
9566                  * the hardware completed the operation behind our backs.
9567                  */
9568                 if (__intel_pageflip_stall_check(dev, crtc)) {
9569                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9570                         page_flip_completed(intel_crtc);
9571                 } else {
9572                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9573                         spin_unlock_irq(&dev->event_lock);
9574
9575                         drm_crtc_vblank_put(crtc);
9576                         kfree(work);
9577                         return -EBUSY;
9578                 }
9579         }
9580         intel_crtc->unpin_work = work;
9581         spin_unlock_irq(&dev->event_lock);
9582
9583         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9584                 flush_workqueue(dev_priv->wq);
9585
9586         ret = i915_mutex_lock_interruptible(dev);
9587         if (ret)
9588                 goto cleanup;
9589
9590         /* Reference the objects for the scheduled work. */
9591         drm_gem_object_reference(&work->old_fb_obj->base);
9592         drm_gem_object_reference(&obj->base);
9593
9594         crtc->primary->fb = fb;
9595
9596         work->pending_flip_obj = obj;
9597
9598         atomic_inc(&intel_crtc->unpin_work_count);
9599         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9600
9601         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9602                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9603
9604         if (IS_VALLEYVIEW(dev)) {
9605                 ring = &dev_priv->ring[BCS];
9606                 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9607                         /* vlv: DISPLAY_FLIP fails to change tiling */
9608                         ring = NULL;
9609         } else if (IS_IVYBRIDGE(dev)) {
9610                 ring = &dev_priv->ring[BCS];
9611         } else if (INTEL_INFO(dev)->gen >= 7) {
9612                 ring = obj->ring;
9613                 if (ring == NULL || ring->id != RCS)
9614                         ring = &dev_priv->ring[BCS];
9615         } else {
9616                 ring = &dev_priv->ring[RCS];
9617         }
9618
9619         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9620         if (ret)
9621                 goto cleanup_pending;
9622
9623         work->gtt_offset =
9624                 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9625
9626         if (use_mmio_flip(ring, obj)) {
9627                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9628                                             page_flip_flags);
9629                 if (ret)
9630                         goto cleanup_unpin;
9631
9632                 work->flip_queued_seqno = obj->last_write_seqno;
9633                 work->flip_queued_ring = obj->ring;
9634         } else {
9635                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9636                                                    page_flip_flags);
9637                 if (ret)
9638                         goto cleanup_unpin;
9639
9640                 work->flip_queued_seqno = intel_ring_get_seqno(ring);
9641                 work->flip_queued_ring = ring;
9642         }
9643
9644         work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9645         work->enable_stall_check = true;
9646
9647         i915_gem_track_fb(work->old_fb_obj, obj,
9648                           INTEL_FRONTBUFFER_PRIMARY(pipe));
9649
9650         intel_disable_fbc(dev);
9651         intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9652         mutex_unlock(&dev->struct_mutex);
9653
9654         trace_i915_flip_request(intel_crtc->plane, obj);
9655
9656         return 0;
9657
9658 cleanup_unpin:
9659         intel_unpin_fb_obj(obj);
9660 cleanup_pending:
9661         atomic_dec(&intel_crtc->unpin_work_count);
9662         crtc->primary->fb = old_fb;
9663         drm_gem_object_unreference(&work->old_fb_obj->base);
9664         drm_gem_object_unreference(&obj->base);
9665         mutex_unlock(&dev->struct_mutex);
9666
9667 cleanup:
9668         spin_lock_irq(&dev->event_lock);
9669         intel_crtc->unpin_work = NULL;
9670         spin_unlock_irq(&dev->event_lock);
9671
9672         drm_crtc_vblank_put(crtc);
9673 free_work:
9674         kfree(work);
9675
9676         if (ret == -EIO) {
9677 out_hang:
9678                 intel_crtc_wait_for_pending_flips(crtc);
9679                 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9680                 if (ret == 0 && event) {
9681                         spin_lock_irq(&dev->event_lock);
9682                         drm_send_vblank_event(dev, pipe, event);
9683                         spin_unlock_irq(&dev->event_lock);
9684                 }
9685         }
9686         return ret;
9687 }
9688
9689 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9690         .mode_set_base_atomic = intel_pipe_set_base_atomic,
9691         .load_lut = intel_crtc_load_lut,
9692 };
9693
9694 /**
9695  * intel_modeset_update_staged_output_state
9696  *
9697  * Updates the staged output configuration state, e.g. after we've read out the
9698  * current hw state.
9699  */
9700 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9701 {
9702         struct intel_crtc *crtc;
9703         struct intel_encoder *encoder;
9704         struct intel_connector *connector;
9705
9706         list_for_each_entry(connector, &dev->mode_config.connector_list,
9707                             base.head) {
9708                 connector->new_encoder =
9709                         to_intel_encoder(connector->base.encoder);
9710         }
9711
9712         for_each_intel_encoder(dev, encoder) {
9713                 encoder->new_crtc =
9714                         to_intel_crtc(encoder->base.crtc);
9715         }
9716
9717         for_each_intel_crtc(dev, crtc) {
9718                 crtc->new_enabled = crtc->base.enabled;
9719
9720                 if (crtc->new_enabled)
9721                         crtc->new_config = &crtc->config;
9722                 else
9723                         crtc->new_config = NULL;
9724         }
9725 }
9726
9727 /**
9728  * intel_modeset_commit_output_state
9729  *
9730  * This function copies the stage display pipe configuration to the real one.
9731  */
9732 static void intel_modeset_commit_output_state(struct drm_device *dev)
9733 {
9734         struct intel_crtc *crtc;
9735         struct intel_encoder *encoder;
9736         struct intel_connector *connector;
9737
9738         list_for_each_entry(connector, &dev->mode_config.connector_list,
9739                             base.head) {
9740                 connector->base.encoder = &connector->new_encoder->base;
9741         }
9742
9743         for_each_intel_encoder(dev, encoder) {
9744                 encoder->base.crtc = &encoder->new_crtc->base;
9745         }
9746
9747         for_each_intel_crtc(dev, crtc) {
9748                 crtc->base.enabled = crtc->new_enabled;
9749         }
9750 }
9751
9752 static void
9753 connected_sink_compute_bpp(struct intel_connector *connector,
9754                            struct intel_crtc_config *pipe_config)
9755 {
9756         int bpp = pipe_config->pipe_bpp;
9757
9758         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9759                 connector->base.base.id,
9760                 connector->base.name);
9761
9762         /* Don't use an invalid EDID bpc value */
9763         if (connector->base.display_info.bpc &&
9764             connector->base.display_info.bpc * 3 < bpp) {
9765                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9766                               bpp, connector->base.display_info.bpc*3);
9767                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9768         }
9769
9770         /* Clamp bpp to 8 on screens without EDID 1.4 */
9771         if (connector->base.display_info.bpc == 0 && bpp > 24) {
9772                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9773                               bpp);
9774                 pipe_config->pipe_bpp = 24;
9775         }
9776 }
9777
9778 static int
9779 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9780                           struct drm_framebuffer *fb,
9781                           struct intel_crtc_config *pipe_config)
9782 {
9783         struct drm_device *dev = crtc->base.dev;
9784         struct intel_connector *connector;
9785         int bpp;
9786
9787         switch (fb->pixel_format) {
9788         case DRM_FORMAT_C8:
9789                 bpp = 8*3; /* since we go through a colormap */
9790                 break;
9791         case DRM_FORMAT_XRGB1555:
9792         case DRM_FORMAT_ARGB1555:
9793                 /* checked in intel_framebuffer_init already */
9794                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9795                         return -EINVAL;
9796         case DRM_FORMAT_RGB565:
9797                 bpp = 6*3; /* min is 18bpp */
9798                 break;
9799         case DRM_FORMAT_XBGR8888:
9800         case DRM_FORMAT_ABGR8888:
9801                 /* checked in intel_framebuffer_init already */
9802                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9803                         return -EINVAL;
9804         case DRM_FORMAT_XRGB8888:
9805         case DRM_FORMAT_ARGB8888:
9806                 bpp = 8*3;
9807                 break;
9808         case DRM_FORMAT_XRGB2101010:
9809         case DRM_FORMAT_ARGB2101010:
9810         case DRM_FORMAT_XBGR2101010:
9811         case DRM_FORMAT_ABGR2101010:
9812                 /* checked in intel_framebuffer_init already */
9813                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9814                         return -EINVAL;
9815                 bpp = 10*3;
9816                 break;
9817         /* TODO: gen4+ supports 16 bpc floating point, too. */
9818         default:
9819                 DRM_DEBUG_KMS("unsupported depth\n");
9820                 return -EINVAL;
9821         }
9822
9823         pipe_config->pipe_bpp = bpp;
9824
9825         /* Clamp display bpp to EDID value */
9826         list_for_each_entry(connector, &dev->mode_config.connector_list,
9827                             base.head) {
9828                 if (!connector->new_encoder ||
9829                     connector->new_encoder->new_crtc != crtc)
9830                         continue;
9831
9832                 connected_sink_compute_bpp(connector, pipe_config);
9833         }
9834
9835         return bpp;
9836 }
9837
9838 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9839 {
9840         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9841                         "type: 0x%x flags: 0x%x\n",
9842                 mode->crtc_clock,
9843                 mode->crtc_hdisplay, mode->crtc_hsync_start,
9844                 mode->crtc_hsync_end, mode->crtc_htotal,
9845                 mode->crtc_vdisplay, mode->crtc_vsync_start,
9846                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9847 }
9848
9849 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9850                                    struct intel_crtc_config *pipe_config,
9851                                    const char *context)
9852 {
9853         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9854                       context, pipe_name(crtc->pipe));
9855
9856         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9857         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9858                       pipe_config->pipe_bpp, pipe_config->dither);
9859         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9860                       pipe_config->has_pch_encoder,
9861                       pipe_config->fdi_lanes,
9862                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9863                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9864                       pipe_config->fdi_m_n.tu);
9865         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9866                       pipe_config->has_dp_encoder,
9867                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9868                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9869                       pipe_config->dp_m_n.tu);
9870
9871         DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
9872                       pipe_config->has_dp_encoder,
9873                       pipe_config->dp_m2_n2.gmch_m,
9874                       pipe_config->dp_m2_n2.gmch_n,
9875                       pipe_config->dp_m2_n2.link_m,
9876                       pipe_config->dp_m2_n2.link_n,
9877                       pipe_config->dp_m2_n2.tu);
9878
9879         DRM_DEBUG_KMS("requested mode:\n");
9880         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9881         DRM_DEBUG_KMS("adjusted mode:\n");
9882         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9883         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9884         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9885         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9886                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9887         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9888                       pipe_config->gmch_pfit.control,
9889                       pipe_config->gmch_pfit.pgm_ratios,
9890                       pipe_config->gmch_pfit.lvds_border_bits);
9891         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9892                       pipe_config->pch_pfit.pos,
9893                       pipe_config->pch_pfit.size,
9894                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9895         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9896         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
9897 }
9898
9899 static bool encoders_cloneable(const struct intel_encoder *a,
9900                                const struct intel_encoder *b)
9901 {
9902         /* masks could be asymmetric, so check both ways */
9903         return a == b || (a->cloneable & (1 << b->type) &&
9904                           b->cloneable & (1 << a->type));
9905 }
9906
9907 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9908                                          struct intel_encoder *encoder)
9909 {
9910         struct drm_device *dev = crtc->base.dev;
9911         struct intel_encoder *source_encoder;
9912
9913         for_each_intel_encoder(dev, source_encoder) {
9914                 if (source_encoder->new_crtc != crtc)
9915                         continue;
9916
9917                 if (!encoders_cloneable(encoder, source_encoder))
9918                         return false;
9919         }
9920
9921         return true;
9922 }
9923
9924 static bool check_encoder_cloning(struct intel_crtc *crtc)
9925 {
9926         struct drm_device *dev = crtc->base.dev;
9927         struct intel_encoder *encoder;
9928
9929         for_each_intel_encoder(dev, encoder) {
9930                 if (encoder->new_crtc != crtc)
9931                         continue;
9932
9933                 if (!check_single_encoder_cloning(crtc, encoder))
9934                         return false;
9935         }
9936
9937         return true;
9938 }
9939
9940 static struct intel_crtc_config *
9941 intel_modeset_pipe_config(struct drm_crtc *crtc,
9942                           struct drm_framebuffer *fb,
9943                           struct drm_display_mode *mode)
9944 {
9945         struct drm_device *dev = crtc->dev;
9946         struct intel_encoder *encoder;
9947         struct intel_crtc_config *pipe_config;
9948         int plane_bpp, ret = -EINVAL;
9949         bool retry = true;
9950
9951         if (!check_encoder_cloning(to_intel_crtc(crtc))) {
9952                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
9953                 return ERR_PTR(-EINVAL);
9954         }
9955
9956         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9957         if (!pipe_config)
9958                 return ERR_PTR(-ENOMEM);
9959
9960         drm_mode_copy(&pipe_config->adjusted_mode, mode);
9961         drm_mode_copy(&pipe_config->requested_mode, mode);
9962
9963         pipe_config->cpu_transcoder =
9964                 (enum transcoder) to_intel_crtc(crtc)->pipe;
9965         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9966
9967         /*
9968          * Sanitize sync polarity flags based on requested ones. If neither
9969          * positive or negative polarity is requested, treat this as meaning
9970          * negative polarity.
9971          */
9972         if (!(pipe_config->adjusted_mode.flags &
9973               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
9974                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
9975
9976         if (!(pipe_config->adjusted_mode.flags &
9977               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
9978                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
9979
9980         /* Compute a starting value for pipe_config->pipe_bpp taking the source
9981          * plane pixel format and any sink constraints into account. Returns the
9982          * source plane bpp so that dithering can be selected on mismatches
9983          * after encoders and crtc also have had their say. */
9984         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
9985                                               fb, pipe_config);
9986         if (plane_bpp < 0)
9987                 goto fail;
9988
9989         /*
9990          * Determine the real pipe dimensions. Note that stereo modes can
9991          * increase the actual pipe size due to the frame doubling and
9992          * insertion of additional space for blanks between the frame. This
9993          * is stored in the crtc timings. We use the requested mode to do this
9994          * computation to clearly distinguish it from the adjusted mode, which
9995          * can be changed by the connectors in the below retry loop.
9996          */
9997         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
9998         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
9999         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10000
10001 encoder_retry:
10002         /* Ensure the port clock defaults are reset when retrying. */
10003         pipe_config->port_clock = 0;
10004         pipe_config->pixel_multiplier = 1;
10005
10006         /* Fill in default crtc timings, allow encoders to overwrite them. */
10007         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
10008
10009         /* Pass our mode to the connectors and the CRTC to give them a chance to
10010          * adjust it according to limitations or connector properties, and also
10011          * a chance to reject the mode entirely.
10012          */
10013         for_each_intel_encoder(dev, encoder) {
10014
10015                 if (&encoder->new_crtc->base != crtc)
10016                         continue;
10017
10018                 if (!(encoder->compute_config(encoder, pipe_config))) {
10019                         DRM_DEBUG_KMS("Encoder config failure\n");
10020                         goto fail;
10021                 }
10022         }
10023
10024         /* Set default port clock if not overwritten by the encoder. Needs to be
10025          * done afterwards in case the encoder adjusts the mode. */
10026         if (!pipe_config->port_clock)
10027                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10028                         * pipe_config->pixel_multiplier;
10029
10030         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10031         if (ret < 0) {
10032                 DRM_DEBUG_KMS("CRTC fixup failed\n");
10033                 goto fail;
10034         }
10035
10036         if (ret == RETRY) {
10037                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10038                         ret = -EINVAL;
10039                         goto fail;
10040                 }
10041
10042                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10043                 retry = false;
10044                 goto encoder_retry;
10045         }
10046
10047         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10048         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10049                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10050
10051         return pipe_config;
10052 fail:
10053         kfree(pipe_config);
10054         return ERR_PTR(ret);
10055 }
10056
10057 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10058  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10059 static void
10060 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10061                              unsigned *prepare_pipes, unsigned *disable_pipes)
10062 {
10063         struct intel_crtc *intel_crtc;
10064         struct drm_device *dev = crtc->dev;
10065         struct intel_encoder *encoder;
10066         struct intel_connector *connector;
10067         struct drm_crtc *tmp_crtc;
10068
10069         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10070
10071         /* Check which crtcs have changed outputs connected to them, these need
10072          * to be part of the prepare_pipes mask. We don't (yet) support global
10073          * modeset across multiple crtcs, so modeset_pipes will only have one
10074          * bit set at most. */
10075         list_for_each_entry(connector, &dev->mode_config.connector_list,
10076                             base.head) {
10077                 if (connector->base.encoder == &connector->new_encoder->base)
10078                         continue;
10079
10080                 if (connector->base.encoder) {
10081                         tmp_crtc = connector->base.encoder->crtc;
10082
10083                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10084                 }
10085
10086                 if (connector->new_encoder)
10087                         *prepare_pipes |=
10088                                 1 << connector->new_encoder->new_crtc->pipe;
10089         }
10090
10091         for_each_intel_encoder(dev, encoder) {
10092                 if (encoder->base.crtc == &encoder->new_crtc->base)
10093                         continue;
10094
10095                 if (encoder->base.crtc) {
10096                         tmp_crtc = encoder->base.crtc;
10097
10098                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10099                 }
10100
10101                 if (encoder->new_crtc)
10102                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10103         }
10104
10105         /* Check for pipes that will be enabled/disabled ... */
10106         for_each_intel_crtc(dev, intel_crtc) {
10107                 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10108                         continue;
10109
10110                 if (!intel_crtc->new_enabled)
10111                         *disable_pipes |= 1 << intel_crtc->pipe;
10112                 else
10113                         *prepare_pipes |= 1 << intel_crtc->pipe;
10114         }
10115
10116
10117         /* set_mode is also used to update properties on life display pipes. */
10118         intel_crtc = to_intel_crtc(crtc);
10119         if (intel_crtc->new_enabled)
10120                 *prepare_pipes |= 1 << intel_crtc->pipe;
10121
10122         /*
10123          * For simplicity do a full modeset on any pipe where the output routing
10124          * changed. We could be more clever, but that would require us to be
10125          * more careful with calling the relevant encoder->mode_set functions.
10126          */
10127         if (*prepare_pipes)
10128                 *modeset_pipes = *prepare_pipes;
10129
10130         /* ... and mask these out. */
10131         *modeset_pipes &= ~(*disable_pipes);
10132         *prepare_pipes &= ~(*disable_pipes);
10133
10134         /*
10135          * HACK: We don't (yet) fully support global modesets. intel_set_config
10136          * obies this rule, but the modeset restore mode of
10137          * intel_modeset_setup_hw_state does not.
10138          */
10139         *modeset_pipes &= 1 << intel_crtc->pipe;
10140         *prepare_pipes &= 1 << intel_crtc->pipe;
10141
10142         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10143                       *modeset_pipes, *prepare_pipes, *disable_pipes);
10144 }
10145
10146 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10147 {
10148         struct drm_encoder *encoder;
10149         struct drm_device *dev = crtc->dev;
10150
10151         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10152                 if (encoder->crtc == crtc)
10153                         return true;
10154
10155         return false;
10156 }
10157
10158 static void
10159 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10160 {
10161         struct intel_encoder *intel_encoder;
10162         struct intel_crtc *intel_crtc;
10163         struct drm_connector *connector;
10164
10165         for_each_intel_encoder(dev, intel_encoder) {
10166                 if (!intel_encoder->base.crtc)
10167                         continue;
10168
10169                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10170
10171                 if (prepare_pipes & (1 << intel_crtc->pipe))
10172                         intel_encoder->connectors_active = false;
10173         }
10174
10175         intel_modeset_commit_output_state(dev);
10176
10177         /* Double check state. */
10178         for_each_intel_crtc(dev, intel_crtc) {
10179                 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10180                 WARN_ON(intel_crtc->new_config &&
10181                         intel_crtc->new_config != &intel_crtc->config);
10182                 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10183         }
10184
10185         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10186                 if (!connector->encoder || !connector->encoder->crtc)
10187                         continue;
10188
10189                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10190
10191                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10192                         struct drm_property *dpms_property =
10193                                 dev->mode_config.dpms_property;
10194
10195                         connector->dpms = DRM_MODE_DPMS_ON;
10196                         drm_object_property_set_value(&connector->base,
10197                                                          dpms_property,
10198                                                          DRM_MODE_DPMS_ON);
10199
10200                         intel_encoder = to_intel_encoder(connector->encoder);
10201                         intel_encoder->connectors_active = true;
10202                 }
10203         }
10204
10205 }
10206
10207 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10208 {
10209         int diff;
10210
10211         if (clock1 == clock2)
10212                 return true;
10213
10214         if (!clock1 || !clock2)
10215                 return false;
10216
10217         diff = abs(clock1 - clock2);
10218
10219         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10220                 return true;
10221
10222         return false;
10223 }
10224
10225 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10226         list_for_each_entry((intel_crtc), \
10227                             &(dev)->mode_config.crtc_list, \
10228                             base.head) \
10229                 if (mask & (1 <<(intel_crtc)->pipe))
10230
10231 static bool
10232 intel_pipe_config_compare(struct drm_device *dev,
10233                           struct intel_crtc_config *current_config,
10234                           struct intel_crtc_config *pipe_config)
10235 {
10236 #define PIPE_CONF_CHECK_X(name) \
10237         if (current_config->name != pipe_config->name) { \
10238                 DRM_ERROR("mismatch in " #name " " \
10239                           "(expected 0x%08x, found 0x%08x)\n", \
10240                           current_config->name, \
10241                           pipe_config->name); \
10242                 return false; \
10243         }
10244
10245 #define PIPE_CONF_CHECK_I(name) \
10246         if (current_config->name != pipe_config->name) { \
10247                 DRM_ERROR("mismatch in " #name " " \
10248                           "(expected %i, found %i)\n", \
10249                           current_config->name, \
10250                           pipe_config->name); \
10251                 return false; \
10252         }
10253
10254 /* This is required for BDW+ where there is only one set of registers for
10255  * switching between high and low RR.
10256  * This macro can be used whenever a comparison has to be made between one
10257  * hw state and multiple sw state variables.
10258  */
10259 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10260         if ((current_config->name != pipe_config->name) && \
10261                 (current_config->alt_name != pipe_config->name)) { \
10262                         DRM_ERROR("mismatch in " #name " " \
10263                                   "(expected %i or %i, found %i)\n", \
10264                                   current_config->name, \
10265                                   current_config->alt_name, \
10266                                   pipe_config->name); \
10267                         return false; \
10268         }
10269
10270 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
10271         if ((current_config->name ^ pipe_config->name) & (mask)) { \
10272                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
10273                           "(expected %i, found %i)\n", \
10274                           current_config->name & (mask), \
10275                           pipe_config->name & (mask)); \
10276                 return false; \
10277         }
10278
10279 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10280         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10281                 DRM_ERROR("mismatch in " #name " " \
10282                           "(expected %i, found %i)\n", \
10283                           current_config->name, \
10284                           pipe_config->name); \
10285                 return false; \
10286         }
10287
10288 #define PIPE_CONF_QUIRK(quirk)  \
10289         ((current_config->quirks | pipe_config->quirks) & (quirk))
10290
10291         PIPE_CONF_CHECK_I(cpu_transcoder);
10292
10293         PIPE_CONF_CHECK_I(has_pch_encoder);
10294         PIPE_CONF_CHECK_I(fdi_lanes);
10295         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10296         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10297         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10298         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10299         PIPE_CONF_CHECK_I(fdi_m_n.tu);
10300
10301         PIPE_CONF_CHECK_I(has_dp_encoder);
10302
10303         if (INTEL_INFO(dev)->gen < 8) {
10304                 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10305                 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10306                 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10307                 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10308                 PIPE_CONF_CHECK_I(dp_m_n.tu);
10309
10310                 if (current_config->has_drrs) {
10311                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10312                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10313                         PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10314                         PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10315                         PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10316                 }
10317         } else {
10318                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10319                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10320                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10321                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10322                 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10323         }
10324
10325         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10326         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10327         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10328         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10329         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10330         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10331
10332         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10333         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10334         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10335         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10336         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10337         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10338
10339         PIPE_CONF_CHECK_I(pixel_multiplier);
10340         PIPE_CONF_CHECK_I(has_hdmi_sink);
10341         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10342             IS_VALLEYVIEW(dev))
10343                 PIPE_CONF_CHECK_I(limited_color_range);
10344
10345         PIPE_CONF_CHECK_I(has_audio);
10346
10347         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10348                               DRM_MODE_FLAG_INTERLACE);
10349
10350         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10351                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10352                                       DRM_MODE_FLAG_PHSYNC);
10353                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10354                                       DRM_MODE_FLAG_NHSYNC);
10355                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10356                                       DRM_MODE_FLAG_PVSYNC);
10357                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10358                                       DRM_MODE_FLAG_NVSYNC);
10359         }
10360
10361         PIPE_CONF_CHECK_I(pipe_src_w);
10362         PIPE_CONF_CHECK_I(pipe_src_h);
10363
10364         /*
10365          * FIXME: BIOS likes to set up a cloned config with lvds+external
10366          * screen. Since we don't yet re-compute the pipe config when moving
10367          * just the lvds port away to another pipe the sw tracking won't match.
10368          *
10369          * Proper atomic modesets with recomputed global state will fix this.
10370          * Until then just don't check gmch state for inherited modes.
10371          */
10372         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10373                 PIPE_CONF_CHECK_I(gmch_pfit.control);
10374                 /* pfit ratios are autocomputed by the hw on gen4+ */
10375                 if (INTEL_INFO(dev)->gen < 4)
10376                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10377                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10378         }
10379
10380         PIPE_CONF_CHECK_I(pch_pfit.enabled);
10381         if (current_config->pch_pfit.enabled) {
10382                 PIPE_CONF_CHECK_I(pch_pfit.pos);
10383                 PIPE_CONF_CHECK_I(pch_pfit.size);
10384         }
10385
10386         /* BDW+ don't expose a synchronous way to read the state */
10387         if (IS_HASWELL(dev))
10388                 PIPE_CONF_CHECK_I(ips_enabled);
10389
10390         PIPE_CONF_CHECK_I(double_wide);
10391
10392         PIPE_CONF_CHECK_X(ddi_pll_sel);
10393
10394         PIPE_CONF_CHECK_I(shared_dpll);
10395         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10396         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10397         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10398         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10399         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10400
10401         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10402                 PIPE_CONF_CHECK_I(pipe_bpp);
10403
10404         PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10405         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10406
10407 #undef PIPE_CONF_CHECK_X
10408 #undef PIPE_CONF_CHECK_I
10409 #undef PIPE_CONF_CHECK_I_ALT
10410 #undef PIPE_CONF_CHECK_FLAGS
10411 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10412 #undef PIPE_CONF_QUIRK
10413
10414         return true;
10415 }
10416
10417 static void
10418 check_connector_state(struct drm_device *dev)
10419 {
10420         struct intel_connector *connector;
10421
10422         list_for_each_entry(connector, &dev->mode_config.connector_list,
10423                             base.head) {
10424                 /* This also checks the encoder/connector hw state with the
10425                  * ->get_hw_state callbacks. */
10426                 intel_connector_check_state(connector);
10427
10428                 WARN(&connector->new_encoder->base != connector->base.encoder,
10429                      "connector's staged encoder doesn't match current encoder\n");
10430         }
10431 }
10432
10433 static void
10434 check_encoder_state(struct drm_device *dev)
10435 {
10436         struct intel_encoder *encoder;
10437         struct intel_connector *connector;
10438
10439         for_each_intel_encoder(dev, encoder) {
10440                 bool enabled = false;
10441                 bool active = false;
10442                 enum pipe pipe, tracked_pipe;
10443
10444                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10445                               encoder->base.base.id,
10446                               encoder->base.name);
10447
10448                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10449                      "encoder's stage crtc doesn't match current crtc\n");
10450                 WARN(encoder->connectors_active && !encoder->base.crtc,
10451                      "encoder's active_connectors set, but no crtc\n");
10452
10453                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10454                                     base.head) {
10455                         if (connector->base.encoder != &encoder->base)
10456                                 continue;
10457                         enabled = true;
10458                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10459                                 active = true;
10460                 }
10461                 /*
10462                  * for MST connectors if we unplug the connector is gone
10463                  * away but the encoder is still connected to a crtc
10464                  * until a modeset happens in response to the hotplug.
10465                  */
10466                 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10467                         continue;
10468
10469                 WARN(!!encoder->base.crtc != enabled,
10470                      "encoder's enabled state mismatch "
10471                      "(expected %i, found %i)\n",
10472                      !!encoder->base.crtc, enabled);
10473                 WARN(active && !encoder->base.crtc,
10474                      "active encoder with no crtc\n");
10475
10476                 WARN(encoder->connectors_active != active,
10477                      "encoder's computed active state doesn't match tracked active state "
10478                      "(expected %i, found %i)\n", active, encoder->connectors_active);
10479
10480                 active = encoder->get_hw_state(encoder, &pipe);
10481                 WARN(active != encoder->connectors_active,
10482                      "encoder's hw state doesn't match sw tracking "
10483                      "(expected %i, found %i)\n",
10484                      encoder->connectors_active, active);
10485
10486                 if (!encoder->base.crtc)
10487                         continue;
10488
10489                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10490                 WARN(active && pipe != tracked_pipe,
10491                      "active encoder's pipe doesn't match"
10492                      "(expected %i, found %i)\n",
10493                      tracked_pipe, pipe);
10494
10495         }
10496 }
10497
10498 static void
10499 check_crtc_state(struct drm_device *dev)
10500 {
10501         struct drm_i915_private *dev_priv = dev->dev_private;
10502         struct intel_crtc *crtc;
10503         struct intel_encoder *encoder;
10504         struct intel_crtc_config pipe_config;
10505
10506         for_each_intel_crtc(dev, crtc) {
10507                 bool enabled = false;
10508                 bool active = false;
10509
10510                 memset(&pipe_config, 0, sizeof(pipe_config));
10511
10512                 DRM_DEBUG_KMS("[CRTC:%d]\n",
10513                               crtc->base.base.id);
10514
10515                 WARN(crtc->active && !crtc->base.enabled,
10516                      "active crtc, but not enabled in sw tracking\n");
10517
10518                 for_each_intel_encoder(dev, encoder) {
10519                         if (encoder->base.crtc != &crtc->base)
10520                                 continue;
10521                         enabled = true;
10522                         if (encoder->connectors_active)
10523                                 active = true;
10524                 }
10525
10526                 WARN(active != crtc->active,
10527                      "crtc's computed active state doesn't match tracked active state "
10528                      "(expected %i, found %i)\n", active, crtc->active);
10529                 WARN(enabled != crtc->base.enabled,
10530                      "crtc's computed enabled state doesn't match tracked enabled state "
10531                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10532
10533                 active = dev_priv->display.get_pipe_config(crtc,
10534                                                            &pipe_config);
10535
10536                 /* hw state is inconsistent with the pipe quirk */
10537                 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10538                     (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10539                         active = crtc->active;
10540
10541                 for_each_intel_encoder(dev, encoder) {
10542                         enum pipe pipe;
10543                         if (encoder->base.crtc != &crtc->base)
10544                                 continue;
10545                         if (encoder->get_hw_state(encoder, &pipe))
10546                                 encoder->get_config(encoder, &pipe_config);
10547                 }
10548
10549                 WARN(crtc->active != active,
10550                      "crtc active state doesn't match with hw state "
10551                      "(expected %i, found %i)\n", crtc->active, active);
10552
10553                 if (active &&
10554                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10555                         WARN(1, "pipe state doesn't match!\n");
10556                         intel_dump_pipe_config(crtc, &pipe_config,
10557                                                "[hw state]");
10558                         intel_dump_pipe_config(crtc, &crtc->config,
10559                                                "[sw state]");
10560                 }
10561         }
10562 }
10563
10564 static void
10565 check_shared_dpll_state(struct drm_device *dev)
10566 {
10567         struct drm_i915_private *dev_priv = dev->dev_private;
10568         struct intel_crtc *crtc;
10569         struct intel_dpll_hw_state dpll_hw_state;
10570         int i;
10571
10572         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10573                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10574                 int enabled_crtcs = 0, active_crtcs = 0;
10575                 bool active;
10576
10577                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10578
10579                 DRM_DEBUG_KMS("%s\n", pll->name);
10580
10581                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10582
10583                 WARN(pll->active > pll->refcount,
10584                      "more active pll users than references: %i vs %i\n",
10585                      pll->active, pll->refcount);
10586                 WARN(pll->active && !pll->on,
10587                      "pll in active use but not on in sw tracking\n");
10588                 WARN(pll->on && !pll->active,
10589                      "pll in on but not on in use in sw tracking\n");
10590                 WARN(pll->on != active,
10591                      "pll on state mismatch (expected %i, found %i)\n",
10592                      pll->on, active);
10593
10594                 for_each_intel_crtc(dev, crtc) {
10595                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10596                                 enabled_crtcs++;
10597                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10598                                 active_crtcs++;
10599                 }
10600                 WARN(pll->active != active_crtcs,
10601                      "pll active crtcs mismatch (expected %i, found %i)\n",
10602                      pll->active, active_crtcs);
10603                 WARN(pll->refcount != enabled_crtcs,
10604                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
10605                      pll->refcount, enabled_crtcs);
10606
10607                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10608                                        sizeof(dpll_hw_state)),
10609                      "pll hw state mismatch\n");
10610         }
10611 }
10612
10613 void
10614 intel_modeset_check_state(struct drm_device *dev)
10615 {
10616         check_connector_state(dev);
10617         check_encoder_state(dev);
10618         check_crtc_state(dev);
10619         check_shared_dpll_state(dev);
10620 }
10621
10622 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10623                                      int dotclock)
10624 {
10625         /*
10626          * FDI already provided one idea for the dotclock.
10627          * Yell if the encoder disagrees.
10628          */
10629         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10630              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10631              pipe_config->adjusted_mode.crtc_clock, dotclock);
10632 }
10633
10634 static void update_scanline_offset(struct intel_crtc *crtc)
10635 {
10636         struct drm_device *dev = crtc->base.dev;
10637
10638         /*
10639          * The scanline counter increments at the leading edge of hsync.
10640          *
10641          * On most platforms it starts counting from vtotal-1 on the
10642          * first active line. That means the scanline counter value is
10643          * always one less than what we would expect. Ie. just after
10644          * start of vblank, which also occurs at start of hsync (on the
10645          * last active line), the scanline counter will read vblank_start-1.
10646          *
10647          * On gen2 the scanline counter starts counting from 1 instead
10648          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10649          * to keep the value positive), instead of adding one.
10650          *
10651          * On HSW+ the behaviour of the scanline counter depends on the output
10652          * type. For DP ports it behaves like most other platforms, but on HDMI
10653          * there's an extra 1 line difference. So we need to add two instead of
10654          * one to the value.
10655          */
10656         if (IS_GEN2(dev)) {
10657                 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10658                 int vtotal;
10659
10660                 vtotal = mode->crtc_vtotal;
10661                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10662                         vtotal /= 2;
10663
10664                 crtc->scanline_offset = vtotal - 1;
10665         } else if (HAS_DDI(dev) &&
10666                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
10667                 crtc->scanline_offset = 2;
10668         } else
10669                 crtc->scanline_offset = 1;
10670 }
10671
10672 static int __intel_set_mode(struct drm_crtc *crtc,
10673                             struct drm_display_mode *mode,
10674                             int x, int y, struct drm_framebuffer *fb)
10675 {
10676         struct drm_device *dev = crtc->dev;
10677         struct drm_i915_private *dev_priv = dev->dev_private;
10678         struct drm_display_mode *saved_mode;
10679         struct intel_crtc_config *pipe_config = NULL;
10680         struct intel_crtc *intel_crtc;
10681         unsigned disable_pipes, prepare_pipes, modeset_pipes;
10682         int ret = 0;
10683
10684         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10685         if (!saved_mode)
10686                 return -ENOMEM;
10687
10688         intel_modeset_affected_pipes(crtc, &modeset_pipes,
10689                                      &prepare_pipes, &disable_pipes);
10690
10691         *saved_mode = crtc->mode;
10692
10693         /* Hack: Because we don't (yet) support global modeset on multiple
10694          * crtcs, we don't keep track of the new mode for more than one crtc.
10695          * Hence simply check whether any bit is set in modeset_pipes in all the
10696          * pieces of code that are not yet converted to deal with mutliple crtcs
10697          * changing their mode at the same time. */
10698         if (modeset_pipes) {
10699                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10700                 if (IS_ERR(pipe_config)) {
10701                         ret = PTR_ERR(pipe_config);
10702                         pipe_config = NULL;
10703
10704                         goto out;
10705                 }
10706                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10707                                        "[modeset]");
10708                 to_intel_crtc(crtc)->new_config = pipe_config;
10709         }
10710
10711         /*
10712          * See if the config requires any additional preparation, e.g.
10713          * to adjust global state with pipes off.  We need to do this
10714          * here so we can get the modeset_pipe updated config for the new
10715          * mode set on this crtc.  For other crtcs we need to use the
10716          * adjusted_mode bits in the crtc directly.
10717          */
10718         if (IS_VALLEYVIEW(dev)) {
10719                 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10720
10721                 /* may have added more to prepare_pipes than we should */
10722                 prepare_pipes &= ~disable_pipes;
10723         }
10724
10725         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10726                 intel_crtc_disable(&intel_crtc->base);
10727
10728         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10729                 if (intel_crtc->base.enabled)
10730                         dev_priv->display.crtc_disable(&intel_crtc->base);
10731         }
10732
10733         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10734          * to set it here already despite that we pass it down the callchain.
10735          */
10736         if (modeset_pipes) {
10737                 crtc->mode = *mode;
10738                 /* mode_set/enable/disable functions rely on a correct pipe
10739                  * config. */
10740                 to_intel_crtc(crtc)->config = *pipe_config;
10741                 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10742
10743                 /*
10744                  * Calculate and store various constants which
10745                  * are later needed by vblank and swap-completion
10746                  * timestamping. They are derived from true hwmode.
10747                  */
10748                 drm_calc_timestamping_constants(crtc,
10749                                                 &pipe_config->adjusted_mode);
10750         }
10751
10752         /* Only after disabling all output pipelines that will be changed can we
10753          * update the the output configuration. */
10754         intel_modeset_update_state(dev, prepare_pipes);
10755
10756         if (dev_priv->display.modeset_global_resources)
10757                 dev_priv->display.modeset_global_resources(dev);
10758
10759         /* Set up the DPLL and any encoders state that needs to adjust or depend
10760          * on the DPLL.
10761          */
10762         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10763                 struct drm_framebuffer *old_fb = crtc->primary->fb;
10764                 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
10765                 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10766
10767                 mutex_lock(&dev->struct_mutex);
10768                 ret = intel_pin_and_fence_fb_obj(dev,
10769                                                  obj,
10770                                                  NULL);
10771                 if (ret != 0) {
10772                         DRM_ERROR("pin & fence failed\n");
10773                         mutex_unlock(&dev->struct_mutex);
10774                         goto done;
10775                 }
10776                 if (old_fb)
10777                         intel_unpin_fb_obj(old_obj);
10778                 i915_gem_track_fb(old_obj, obj,
10779                                   INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
10780                 mutex_unlock(&dev->struct_mutex);
10781
10782                 crtc->primary->fb = fb;
10783                 crtc->x = x;
10784                 crtc->y = y;
10785
10786                 ret = dev_priv->display.crtc_mode_set(intel_crtc, x, y, fb);
10787                 if (ret)
10788                         goto done;
10789         }
10790
10791         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10792         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10793                 update_scanline_offset(intel_crtc);
10794
10795                 dev_priv->display.crtc_enable(&intel_crtc->base);
10796         }
10797
10798         /* FIXME: add subpixel order */
10799 done:
10800         if (ret && crtc->enabled)
10801                 crtc->mode = *saved_mode;
10802
10803 out:
10804         kfree(pipe_config);
10805         kfree(saved_mode);
10806         return ret;
10807 }
10808
10809 static int intel_set_mode(struct drm_crtc *crtc,
10810                           struct drm_display_mode *mode,
10811                           int x, int y, struct drm_framebuffer *fb)
10812 {
10813         int ret;
10814
10815         ret = __intel_set_mode(crtc, mode, x, y, fb);
10816
10817         if (ret == 0)
10818                 intel_modeset_check_state(crtc->dev);
10819
10820         return ret;
10821 }
10822
10823 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10824 {
10825         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10826 }
10827
10828 #undef for_each_intel_crtc_masked
10829
10830 static void intel_set_config_free(struct intel_set_config *config)
10831 {
10832         if (!config)
10833                 return;
10834
10835         kfree(config->save_connector_encoders);
10836         kfree(config->save_encoder_crtcs);
10837         kfree(config->save_crtc_enabled);
10838         kfree(config);
10839 }
10840
10841 static int intel_set_config_save_state(struct drm_device *dev,
10842                                        struct intel_set_config *config)
10843 {
10844         struct drm_crtc *crtc;
10845         struct drm_encoder *encoder;
10846         struct drm_connector *connector;
10847         int count;
10848
10849         config->save_crtc_enabled =
10850                 kcalloc(dev->mode_config.num_crtc,
10851                         sizeof(bool), GFP_KERNEL);
10852         if (!config->save_crtc_enabled)
10853                 return -ENOMEM;
10854
10855         config->save_encoder_crtcs =
10856                 kcalloc(dev->mode_config.num_encoder,
10857                         sizeof(struct drm_crtc *), GFP_KERNEL);
10858         if (!config->save_encoder_crtcs)
10859                 return -ENOMEM;
10860
10861         config->save_connector_encoders =
10862                 kcalloc(dev->mode_config.num_connector,
10863                         sizeof(struct drm_encoder *), GFP_KERNEL);
10864         if (!config->save_connector_encoders)
10865                 return -ENOMEM;
10866
10867         /* Copy data. Note that driver private data is not affected.
10868          * Should anything bad happen only the expected state is
10869          * restored, not the drivers personal bookkeeping.
10870          */
10871         count = 0;
10872         for_each_crtc(dev, crtc) {
10873                 config->save_crtc_enabled[count++] = crtc->enabled;
10874         }
10875
10876         count = 0;
10877         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10878                 config->save_encoder_crtcs[count++] = encoder->crtc;
10879         }
10880
10881         count = 0;
10882         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10883                 config->save_connector_encoders[count++] = connector->encoder;
10884         }
10885
10886         return 0;
10887 }
10888
10889 static void intel_set_config_restore_state(struct drm_device *dev,
10890                                            struct intel_set_config *config)
10891 {
10892         struct intel_crtc *crtc;
10893         struct intel_encoder *encoder;
10894         struct intel_connector *connector;
10895         int count;
10896
10897         count = 0;
10898         for_each_intel_crtc(dev, crtc) {
10899                 crtc->new_enabled = config->save_crtc_enabled[count++];
10900
10901                 if (crtc->new_enabled)
10902                         crtc->new_config = &crtc->config;
10903                 else
10904                         crtc->new_config = NULL;
10905         }
10906
10907         count = 0;
10908         for_each_intel_encoder(dev, encoder) {
10909                 encoder->new_crtc =
10910                         to_intel_crtc(config->save_encoder_crtcs[count++]);
10911         }
10912
10913         count = 0;
10914         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10915                 connector->new_encoder =
10916                         to_intel_encoder(config->save_connector_encoders[count++]);
10917         }
10918 }
10919
10920 static bool
10921 is_crtc_connector_off(struct drm_mode_set *set)
10922 {
10923         int i;
10924
10925         if (set->num_connectors == 0)
10926                 return false;
10927
10928         if (WARN_ON(set->connectors == NULL))
10929                 return false;
10930
10931         for (i = 0; i < set->num_connectors; i++)
10932                 if (set->connectors[i]->encoder &&
10933                     set->connectors[i]->encoder->crtc == set->crtc &&
10934                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
10935                         return true;
10936
10937         return false;
10938 }
10939
10940 static void
10941 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
10942                                       struct intel_set_config *config)
10943 {
10944
10945         /* We should be able to check here if the fb has the same properties
10946          * and then just flip_or_move it */
10947         if (is_crtc_connector_off(set)) {
10948                 config->mode_changed = true;
10949         } else if (set->crtc->primary->fb != set->fb) {
10950                 /*
10951                  * If we have no fb, we can only flip as long as the crtc is
10952                  * active, otherwise we need a full mode set.  The crtc may
10953                  * be active if we've only disabled the primary plane, or
10954                  * in fastboot situations.
10955                  */
10956                 if (set->crtc->primary->fb == NULL) {
10957                         struct intel_crtc *intel_crtc =
10958                                 to_intel_crtc(set->crtc);
10959
10960                         if (intel_crtc->active) {
10961                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
10962                                 config->fb_changed = true;
10963                         } else {
10964                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
10965                                 config->mode_changed = true;
10966                         }
10967                 } else if (set->fb == NULL) {
10968                         config->mode_changed = true;
10969                 } else if (set->fb->pixel_format !=
10970                            set->crtc->primary->fb->pixel_format) {
10971                         config->mode_changed = true;
10972                 } else {
10973                         config->fb_changed = true;
10974                 }
10975         }
10976
10977         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
10978                 config->fb_changed = true;
10979
10980         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
10981                 DRM_DEBUG_KMS("modes are different, full mode set\n");
10982                 drm_mode_debug_printmodeline(&set->crtc->mode);
10983                 drm_mode_debug_printmodeline(set->mode);
10984                 config->mode_changed = true;
10985         }
10986
10987         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
10988                         set->crtc->base.id, config->mode_changed, config->fb_changed);
10989 }
10990
10991 static int
10992 intel_modeset_stage_output_state(struct drm_device *dev,
10993                                  struct drm_mode_set *set,
10994                                  struct intel_set_config *config)
10995 {
10996         struct intel_connector *connector;
10997         struct intel_encoder *encoder;
10998         struct intel_crtc *crtc;
10999         int ro;
11000
11001         /* The upper layers ensure that we either disable a crtc or have a list
11002          * of connectors. For paranoia, double-check this. */
11003         WARN_ON(!set->fb && (set->num_connectors != 0));
11004         WARN_ON(set->fb && (set->num_connectors == 0));
11005
11006         list_for_each_entry(connector, &dev->mode_config.connector_list,
11007                             base.head) {
11008                 /* Otherwise traverse passed in connector list and get encoders
11009                  * for them. */
11010                 for (ro = 0; ro < set->num_connectors; ro++) {
11011                         if (set->connectors[ro] == &connector->base) {
11012                                 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11013                                 break;
11014                         }
11015                 }
11016
11017                 /* If we disable the crtc, disable all its connectors. Also, if
11018                  * the connector is on the changing crtc but not on the new
11019                  * connector list, disable it. */
11020                 if ((!set->fb || ro == set->num_connectors) &&
11021                     connector->base.encoder &&
11022                     connector->base.encoder->crtc == set->crtc) {
11023                         connector->new_encoder = NULL;
11024
11025                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11026                                 connector->base.base.id,
11027                                 connector->base.name);
11028                 }
11029
11030
11031                 if (&connector->new_encoder->base != connector->base.encoder) {
11032                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11033                         config->mode_changed = true;
11034                 }
11035         }
11036         /* connector->new_encoder is now updated for all connectors. */
11037
11038         /* Update crtc of enabled connectors. */
11039         list_for_each_entry(connector, &dev->mode_config.connector_list,
11040                             base.head) {
11041                 struct drm_crtc *new_crtc;
11042
11043                 if (!connector->new_encoder)
11044                         continue;
11045
11046                 new_crtc = connector->new_encoder->base.crtc;
11047
11048                 for (ro = 0; ro < set->num_connectors; ro++) {
11049                         if (set->connectors[ro] == &connector->base)
11050                                 new_crtc = set->crtc;
11051                 }
11052
11053                 /* Make sure the new CRTC will work with the encoder */
11054                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11055                                          new_crtc)) {
11056                         return -EINVAL;
11057                 }
11058                 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11059
11060                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11061                         connector->base.base.id,
11062                         connector->base.name,
11063                         new_crtc->base.id);
11064         }
11065
11066         /* Check for any encoders that needs to be disabled. */
11067         for_each_intel_encoder(dev, encoder) {
11068                 int num_connectors = 0;
11069                 list_for_each_entry(connector,
11070                                     &dev->mode_config.connector_list,
11071                                     base.head) {
11072                         if (connector->new_encoder == encoder) {
11073                                 WARN_ON(!connector->new_encoder->new_crtc);
11074                                 num_connectors++;
11075                         }
11076                 }
11077
11078                 if (num_connectors == 0)
11079                         encoder->new_crtc = NULL;
11080                 else if (num_connectors > 1)
11081                         return -EINVAL;
11082
11083                 /* Only now check for crtc changes so we don't miss encoders
11084                  * that will be disabled. */
11085                 if (&encoder->new_crtc->base != encoder->base.crtc) {
11086                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11087                         config->mode_changed = true;
11088                 }
11089         }
11090         /* Now we've also updated encoder->new_crtc for all encoders. */
11091         list_for_each_entry(connector, &dev->mode_config.connector_list,
11092                             base.head) {
11093                 if (connector->new_encoder)
11094                         if (connector->new_encoder != connector->encoder)
11095                                 connector->encoder = connector->new_encoder;
11096         }
11097         for_each_intel_crtc(dev, crtc) {
11098                 crtc->new_enabled = false;
11099
11100                 for_each_intel_encoder(dev, encoder) {
11101                         if (encoder->new_crtc == crtc) {
11102                                 crtc->new_enabled = true;
11103                                 break;
11104                         }
11105                 }
11106
11107                 if (crtc->new_enabled != crtc->base.enabled) {
11108                         DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11109                                       crtc->new_enabled ? "en" : "dis");
11110                         config->mode_changed = true;
11111                 }
11112
11113                 if (crtc->new_enabled)
11114                         crtc->new_config = &crtc->config;
11115                 else
11116                         crtc->new_config = NULL;
11117         }
11118
11119         return 0;
11120 }
11121
11122 static void disable_crtc_nofb(struct intel_crtc *crtc)
11123 {
11124         struct drm_device *dev = crtc->base.dev;
11125         struct intel_encoder *encoder;
11126         struct intel_connector *connector;
11127
11128         DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11129                       pipe_name(crtc->pipe));
11130
11131         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11132                 if (connector->new_encoder &&
11133                     connector->new_encoder->new_crtc == crtc)
11134                         connector->new_encoder = NULL;
11135         }
11136
11137         for_each_intel_encoder(dev, encoder) {
11138                 if (encoder->new_crtc == crtc)
11139                         encoder->new_crtc = NULL;
11140         }
11141
11142         crtc->new_enabled = false;
11143         crtc->new_config = NULL;
11144 }
11145
11146 static int intel_crtc_set_config(struct drm_mode_set *set)
11147 {
11148         struct drm_device *dev;
11149         struct drm_mode_set save_set;
11150         struct intel_set_config *config;
11151         int ret;
11152
11153         BUG_ON(!set);
11154         BUG_ON(!set->crtc);
11155         BUG_ON(!set->crtc->helper_private);
11156
11157         /* Enforce sane interface api - has been abused by the fb helper. */
11158         BUG_ON(!set->mode && set->fb);
11159         BUG_ON(set->fb && set->num_connectors == 0);
11160
11161         if (set->fb) {
11162                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11163                                 set->crtc->base.id, set->fb->base.id,
11164                                 (int)set->num_connectors, set->x, set->y);
11165         } else {
11166                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11167         }
11168
11169         dev = set->crtc->dev;
11170
11171         ret = -ENOMEM;
11172         config = kzalloc(sizeof(*config), GFP_KERNEL);
11173         if (!config)
11174                 goto out_config;
11175
11176         ret = intel_set_config_save_state(dev, config);
11177         if (ret)
11178                 goto out_config;
11179
11180         save_set.crtc = set->crtc;
11181         save_set.mode = &set->crtc->mode;
11182         save_set.x = set->crtc->x;
11183         save_set.y = set->crtc->y;
11184         save_set.fb = set->crtc->primary->fb;
11185
11186         /* Compute whether we need a full modeset, only an fb base update or no
11187          * change at all. In the future we might also check whether only the
11188          * mode changed, e.g. for LVDS where we only change the panel fitter in
11189          * such cases. */
11190         intel_set_config_compute_mode_changes(set, config);
11191
11192         ret = intel_modeset_stage_output_state(dev, set, config);
11193         if (ret)
11194                 goto fail;
11195
11196         if (config->mode_changed) {
11197                 ret = intel_set_mode(set->crtc, set->mode,
11198                                      set->x, set->y, set->fb);
11199         } else if (config->fb_changed) {
11200                 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11201
11202                 intel_crtc_wait_for_pending_flips(set->crtc);
11203
11204                 ret = intel_pipe_set_base(set->crtc,
11205                                           set->x, set->y, set->fb);
11206
11207                 /*
11208                  * We need to make sure the primary plane is re-enabled if it
11209                  * has previously been turned off.
11210                  */
11211                 if (!intel_crtc->primary_enabled && ret == 0) {
11212                         WARN_ON(!intel_crtc->active);
11213                         intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11214                 }
11215
11216                 /*
11217                  * In the fastboot case this may be our only check of the
11218                  * state after boot.  It would be better to only do it on
11219                  * the first update, but we don't have a nice way of doing that
11220                  * (and really, set_config isn't used much for high freq page
11221                  * flipping, so increasing its cost here shouldn't be a big
11222                  * deal).
11223                  */
11224                 if (i915.fastboot && ret == 0)
11225                         intel_modeset_check_state(set->crtc->dev);
11226         }
11227
11228         if (ret) {
11229                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11230                               set->crtc->base.id, ret);
11231 fail:
11232                 intel_set_config_restore_state(dev, config);
11233
11234                 /*
11235                  * HACK: if the pipe was on, but we didn't have a framebuffer,
11236                  * force the pipe off to avoid oopsing in the modeset code
11237                  * due to fb==NULL. This should only happen during boot since
11238                  * we don't yet reconstruct the FB from the hardware state.
11239                  */
11240                 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11241                         disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11242
11243                 /* Try to restore the config */
11244                 if (config->mode_changed &&
11245                     intel_set_mode(save_set.crtc, save_set.mode,
11246                                    save_set.x, save_set.y, save_set.fb))
11247                         DRM_ERROR("failed to restore config after modeset failure\n");
11248         }
11249
11250 out_config:
11251         intel_set_config_free(config);
11252         return ret;
11253 }
11254
11255 static const struct drm_crtc_funcs intel_crtc_funcs = {
11256         .gamma_set = intel_crtc_gamma_set,
11257         .set_config = intel_crtc_set_config,
11258         .destroy = intel_crtc_destroy,
11259         .page_flip = intel_crtc_page_flip,
11260 };
11261
11262 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11263                                       struct intel_shared_dpll *pll,
11264                                       struct intel_dpll_hw_state *hw_state)
11265 {
11266         uint32_t val;
11267
11268         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11269                 return false;
11270
11271         val = I915_READ(PCH_DPLL(pll->id));
11272         hw_state->dpll = val;
11273         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11274         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11275
11276         return val & DPLL_VCO_ENABLE;
11277 }
11278
11279 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11280                                   struct intel_shared_dpll *pll)
11281 {
11282         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
11283         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
11284 }
11285
11286 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11287                                 struct intel_shared_dpll *pll)
11288 {
11289         /* PCH refclock must be enabled first */
11290         ibx_assert_pch_refclk_enabled(dev_priv);
11291
11292         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11293
11294         /* Wait for the clocks to stabilize. */
11295         POSTING_READ(PCH_DPLL(pll->id));
11296         udelay(150);
11297
11298         /* The pixel multiplier can only be updated once the
11299          * DPLL is enabled and the clocks are stable.
11300          *
11301          * So write it again.
11302          */
11303         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11304         POSTING_READ(PCH_DPLL(pll->id));
11305         udelay(200);
11306 }
11307
11308 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11309                                  struct intel_shared_dpll *pll)
11310 {
11311         struct drm_device *dev = dev_priv->dev;
11312         struct intel_crtc *crtc;
11313
11314         /* Make sure no transcoder isn't still depending on us. */
11315         for_each_intel_crtc(dev, crtc) {
11316                 if (intel_crtc_to_shared_dpll(crtc) == pll)
11317                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11318         }
11319
11320         I915_WRITE(PCH_DPLL(pll->id), 0);
11321         POSTING_READ(PCH_DPLL(pll->id));
11322         udelay(200);
11323 }
11324
11325 static char *ibx_pch_dpll_names[] = {
11326         "PCH DPLL A",
11327         "PCH DPLL B",
11328 };
11329
11330 static void ibx_pch_dpll_init(struct drm_device *dev)
11331 {
11332         struct drm_i915_private *dev_priv = dev->dev_private;
11333         int i;
11334
11335         dev_priv->num_shared_dpll = 2;
11336
11337         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11338                 dev_priv->shared_dplls[i].id = i;
11339                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11340                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11341                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11342                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11343                 dev_priv->shared_dplls[i].get_hw_state =
11344                         ibx_pch_dpll_get_hw_state;
11345         }
11346 }
11347
11348 static void intel_shared_dpll_init(struct drm_device *dev)
11349 {
11350         struct drm_i915_private *dev_priv = dev->dev_private;
11351
11352         if (HAS_DDI(dev))
11353                 intel_ddi_pll_init(dev);
11354         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11355                 ibx_pch_dpll_init(dev);
11356         else
11357                 dev_priv->num_shared_dpll = 0;
11358
11359         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11360 }
11361
11362 static int
11363 intel_primary_plane_disable(struct drm_plane *plane)
11364 {
11365         struct drm_device *dev = plane->dev;
11366         struct intel_crtc *intel_crtc;
11367
11368         if (!plane->fb)
11369                 return 0;
11370
11371         BUG_ON(!plane->crtc);
11372
11373         intel_crtc = to_intel_crtc(plane->crtc);
11374
11375         /*
11376          * Even though we checked plane->fb above, it's still possible that
11377          * the primary plane has been implicitly disabled because the crtc
11378          * coordinates given weren't visible, or because we detected
11379          * that it was 100% covered by a sprite plane.  Or, the CRTC may be
11380          * off and we've set a fb, but haven't actually turned on the CRTC yet.
11381          * In either case, we need to unpin the FB and let the fb pointer get
11382          * updated, but otherwise we don't need to touch the hardware.
11383          */
11384         if (!intel_crtc->primary_enabled)
11385                 goto disable_unpin;
11386
11387         intel_crtc_wait_for_pending_flips(plane->crtc);
11388         intel_disable_primary_hw_plane(plane, plane->crtc);
11389
11390 disable_unpin:
11391         mutex_lock(&dev->struct_mutex);
11392         i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
11393                           INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11394         intel_unpin_fb_obj(intel_fb_obj(plane->fb));
11395         mutex_unlock(&dev->struct_mutex);
11396         plane->fb = NULL;
11397
11398         return 0;
11399 }
11400
11401 static int
11402 intel_check_primary_plane(struct drm_plane *plane,
11403                           struct intel_plane_state *state)
11404 {
11405         struct drm_crtc *crtc = state->crtc;
11406         struct drm_framebuffer *fb = state->fb;
11407         struct drm_rect *dest = &state->dst;
11408         struct drm_rect *src = &state->src;
11409         const struct drm_rect *clip = &state->clip;
11410
11411         return drm_plane_helper_check_update(plane, crtc, fb,
11412                                              src, dest, clip,
11413                                              DRM_PLANE_HELPER_NO_SCALING,
11414                                              DRM_PLANE_HELPER_NO_SCALING,
11415                                              false, true, &state->visible);
11416 }
11417
11418 static int
11419 intel_prepare_primary_plane(struct drm_plane *plane,
11420                             struct intel_plane_state *state)
11421 {
11422         struct drm_crtc *crtc = state->crtc;
11423         struct drm_framebuffer *fb = state->fb;
11424         struct drm_device *dev = crtc->dev;
11425         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11426         enum pipe pipe = intel_crtc->pipe;
11427         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11428         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11429         int ret;
11430
11431         intel_crtc_wait_for_pending_flips(crtc);
11432
11433         if (intel_crtc_has_pending_flip(crtc)) {
11434                 DRM_ERROR("pipe is still busy with an old pageflip\n");
11435                 return -EBUSY;
11436         }
11437
11438         if (old_obj != obj) {
11439                 mutex_lock(&dev->struct_mutex);
11440                 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11441                 if (ret == 0)
11442                         i915_gem_track_fb(old_obj, obj,
11443                                           INTEL_FRONTBUFFER_PRIMARY(pipe));
11444                 mutex_unlock(&dev->struct_mutex);
11445                 if (ret != 0) {
11446                         DRM_DEBUG_KMS("pin & fence failed\n");
11447                         return ret;
11448                 }
11449         }
11450
11451         return 0;
11452 }
11453
11454 static void
11455 intel_commit_primary_plane(struct drm_plane *plane,
11456                            struct intel_plane_state *state)
11457 {
11458         struct drm_crtc *crtc = state->crtc;
11459         struct drm_framebuffer *fb = state->fb;
11460         struct drm_device *dev = crtc->dev;
11461         struct drm_i915_private *dev_priv = dev->dev_private;
11462         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11463         enum pipe pipe = intel_crtc->pipe;
11464         struct drm_framebuffer *old_fb = plane->fb;
11465         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11466         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11467         struct intel_plane *intel_plane = to_intel_plane(plane);
11468         struct drm_rect *src = &state->src;
11469
11470         crtc->primary->fb = fb;
11471         crtc->x = src->x1;
11472         crtc->y = src->y1;
11473
11474         intel_plane->crtc_x = state->orig_dst.x1;
11475         intel_plane->crtc_y = state->orig_dst.y1;
11476         intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
11477         intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
11478         intel_plane->src_x = state->orig_src.x1;
11479         intel_plane->src_y = state->orig_src.y1;
11480         intel_plane->src_w = drm_rect_width(&state->orig_src);
11481         intel_plane->src_h = drm_rect_height(&state->orig_src);
11482         intel_plane->obj = obj;
11483
11484         if (intel_crtc->active) {
11485                 /*
11486                  * FBC does not work on some platforms for rotated
11487                  * planes, so disable it when rotation is not 0 and
11488                  * update it when rotation is set back to 0.
11489                  *
11490                  * FIXME: This is redundant with the fbc update done in
11491                  * the primary plane enable function except that that
11492                  * one is done too late. We eventually need to unify
11493                  * this.
11494                  */
11495                 if (intel_crtc->primary_enabled &&
11496                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11497                     dev_priv->fbc.plane == intel_crtc->plane &&
11498                     intel_plane->rotation != BIT(DRM_ROTATE_0)) {
11499                         intel_disable_fbc(dev);
11500                 }
11501
11502                 if (state->visible) {
11503                         bool was_enabled = intel_crtc->primary_enabled;
11504
11505                         /* FIXME: kill this fastboot hack */
11506                         intel_update_pipe_size(intel_crtc);
11507
11508                         intel_crtc->primary_enabled = true;
11509
11510                         dev_priv->display.update_primary_plane(crtc, plane->fb,
11511                                         crtc->x, crtc->y);
11512
11513                         /*
11514                          * BDW signals flip done immediately if the plane
11515                          * is disabled, even if the plane enable is already
11516                          * armed to occur at the next vblank :(
11517                          */
11518                         if (IS_BROADWELL(dev) && !was_enabled)
11519                                 intel_wait_for_vblank(dev, intel_crtc->pipe);
11520                 } else {
11521                         /*
11522                          * If clipping results in a non-visible primary plane,
11523                          * we'll disable the primary plane.  Note that this is
11524                          * a bit different than what happens if userspace
11525                          * explicitly disables the plane by passing fb=0
11526                          * because plane->fb still gets set and pinned.
11527                          */
11528                         intel_disable_primary_hw_plane(plane, crtc);
11529                 }
11530
11531                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11532
11533                 mutex_lock(&dev->struct_mutex);
11534                 intel_update_fbc(dev);
11535                 mutex_unlock(&dev->struct_mutex);
11536         }
11537
11538         if (old_fb && old_fb != fb) {
11539                 if (intel_crtc->active)
11540                         intel_wait_for_vblank(dev, intel_crtc->pipe);
11541
11542                 mutex_lock(&dev->struct_mutex);
11543                 intel_unpin_fb_obj(old_obj);
11544                 mutex_unlock(&dev->struct_mutex);
11545         }
11546 }
11547
11548 static int
11549 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11550                              struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11551                              unsigned int crtc_w, unsigned int crtc_h,
11552                              uint32_t src_x, uint32_t src_y,
11553                              uint32_t src_w, uint32_t src_h)
11554 {
11555         struct intel_plane_state state;
11556         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11557         int ret;
11558
11559         state.crtc = crtc;
11560         state.fb = fb;
11561
11562         /* sample coordinates in 16.16 fixed point */
11563         state.src.x1 = src_x;
11564         state.src.x2 = src_x + src_w;
11565         state.src.y1 = src_y;
11566         state.src.y2 = src_y + src_h;
11567
11568         /* integer pixels */
11569         state.dst.x1 = crtc_x;
11570         state.dst.x2 = crtc_x + crtc_w;
11571         state.dst.y1 = crtc_y;
11572         state.dst.y2 = crtc_y + crtc_h;
11573
11574         state.clip.x1 = 0;
11575         state.clip.y1 = 0;
11576         state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
11577         state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
11578
11579         state.orig_src = state.src;
11580         state.orig_dst = state.dst;
11581
11582         ret = intel_check_primary_plane(plane, &state);
11583         if (ret)
11584                 return ret;
11585
11586         ret = intel_prepare_primary_plane(plane, &state);
11587         if (ret)
11588                 return ret;
11589
11590         intel_commit_primary_plane(plane, &state);
11591
11592         return 0;
11593 }
11594
11595 /* Common destruction function for both primary and cursor planes */
11596 static void intel_plane_destroy(struct drm_plane *plane)
11597 {
11598         struct intel_plane *intel_plane = to_intel_plane(plane);
11599         drm_plane_cleanup(plane);
11600         kfree(intel_plane);
11601 }
11602
11603 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11604         .update_plane = intel_primary_plane_setplane,
11605         .disable_plane = intel_primary_plane_disable,
11606         .destroy = intel_plane_destroy,
11607         .set_property = intel_plane_set_property
11608 };
11609
11610 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11611                                                     int pipe)
11612 {
11613         struct intel_plane *primary;
11614         const uint32_t *intel_primary_formats;
11615         int num_formats;
11616
11617         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11618         if (primary == NULL)
11619                 return NULL;
11620
11621         primary->can_scale = false;
11622         primary->max_downscale = 1;
11623         primary->pipe = pipe;
11624         primary->plane = pipe;
11625         primary->rotation = BIT(DRM_ROTATE_0);
11626         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11627                 primary->plane = !pipe;
11628
11629         if (INTEL_INFO(dev)->gen <= 3) {
11630                 intel_primary_formats = intel_primary_formats_gen2;
11631                 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11632         } else {
11633                 intel_primary_formats = intel_primary_formats_gen4;
11634                 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11635         }
11636
11637         drm_universal_plane_init(dev, &primary->base, 0,
11638                                  &intel_primary_plane_funcs,
11639                                  intel_primary_formats, num_formats,
11640                                  DRM_PLANE_TYPE_PRIMARY);
11641
11642         if (INTEL_INFO(dev)->gen >= 4) {
11643                 if (!dev->mode_config.rotation_property)
11644                         dev->mode_config.rotation_property =
11645                                 drm_mode_create_rotation_property(dev,
11646                                                         BIT(DRM_ROTATE_0) |
11647                                                         BIT(DRM_ROTATE_180));
11648                 if (dev->mode_config.rotation_property)
11649                         drm_object_attach_property(&primary->base.base,
11650                                 dev->mode_config.rotation_property,
11651                                 primary->rotation);
11652         }
11653
11654         return &primary->base;
11655 }
11656
11657 static int
11658 intel_cursor_plane_disable(struct drm_plane *plane)
11659 {
11660         if (!plane->fb)
11661                 return 0;
11662
11663         BUG_ON(!plane->crtc);
11664
11665         return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
11666 }
11667
11668 static int
11669 intel_check_cursor_plane(struct drm_plane *plane,
11670                          struct intel_plane_state *state)
11671 {
11672         struct drm_crtc *crtc = state->crtc;
11673         struct drm_device *dev = crtc->dev;
11674         struct drm_framebuffer *fb = state->fb;
11675         struct drm_rect *dest = &state->dst;
11676         struct drm_rect *src = &state->src;
11677         const struct drm_rect *clip = &state->clip;
11678         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11679         int crtc_w, crtc_h;
11680         unsigned stride;
11681         int ret;
11682
11683         ret = drm_plane_helper_check_update(plane, crtc, fb,
11684                                             src, dest, clip,
11685                                             DRM_PLANE_HELPER_NO_SCALING,
11686                                             DRM_PLANE_HELPER_NO_SCALING,
11687                                             true, true, &state->visible);
11688         if (ret)
11689                 return ret;
11690
11691
11692         /* if we want to turn off the cursor ignore width and height */
11693         if (!obj)
11694                 return 0;
11695
11696         /* Check for which cursor types we support */
11697         crtc_w = drm_rect_width(&state->orig_dst);
11698         crtc_h = drm_rect_height(&state->orig_dst);
11699         if (!cursor_size_ok(dev, crtc_w, crtc_h)) {
11700                 DRM_DEBUG("Cursor dimension not supported\n");
11701                 return -EINVAL;
11702         }
11703
11704         stride = roundup_pow_of_two(crtc_w) * 4;
11705         if (obj->base.size < stride * crtc_h) {
11706                 DRM_DEBUG_KMS("buffer is too small\n");
11707                 return -ENOMEM;
11708         }
11709
11710         if (fb == crtc->cursor->fb)
11711                 return 0;
11712
11713         /* we only need to pin inside GTT if cursor is non-phy */
11714         mutex_lock(&dev->struct_mutex);
11715         if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) {
11716                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
11717                 ret = -EINVAL;
11718         }
11719         mutex_unlock(&dev->struct_mutex);
11720
11721         return ret;
11722 }
11723
11724 static int
11725 intel_commit_cursor_plane(struct drm_plane *plane,
11726                           struct intel_plane_state *state)
11727 {
11728         struct drm_crtc *crtc = state->crtc;
11729         struct drm_framebuffer *fb = state->fb;
11730         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11731         struct intel_plane *intel_plane = to_intel_plane(plane);
11732         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11733         struct drm_i915_gem_object *obj = intel_fb->obj;
11734         int crtc_w, crtc_h;
11735
11736         crtc->cursor_x = state->orig_dst.x1;
11737         crtc->cursor_y = state->orig_dst.y1;
11738
11739         intel_plane->crtc_x = state->orig_dst.x1;
11740         intel_plane->crtc_y = state->orig_dst.y1;
11741         intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
11742         intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
11743         intel_plane->src_x = state->orig_src.x1;
11744         intel_plane->src_y = state->orig_src.y1;
11745         intel_plane->src_w = drm_rect_width(&state->orig_src);
11746         intel_plane->src_h = drm_rect_height(&state->orig_src);
11747         intel_plane->obj = obj;
11748
11749         if (fb != crtc->cursor->fb) {
11750                 crtc_w = drm_rect_width(&state->orig_dst);
11751                 crtc_h = drm_rect_height(&state->orig_dst);
11752                 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
11753         } else {
11754                 intel_crtc_update_cursor(crtc, state->visible);
11755
11756                 intel_frontbuffer_flip(crtc->dev,
11757                                        INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe));
11758
11759                 return 0;
11760         }
11761 }
11762
11763 static int
11764 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
11765                           struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11766                           unsigned int crtc_w, unsigned int crtc_h,
11767                           uint32_t src_x, uint32_t src_y,
11768                           uint32_t src_w, uint32_t src_h)
11769 {
11770         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11771         struct intel_plane_state state;
11772         int ret;
11773
11774         state.crtc = crtc;
11775         state.fb = fb;
11776
11777         /* sample coordinates in 16.16 fixed point */
11778         state.src.x1 = src_x;
11779         state.src.x2 = src_x + src_w;
11780         state.src.y1 = src_y;
11781         state.src.y2 = src_y + src_h;
11782
11783         /* integer pixels */
11784         state.dst.x1 = crtc_x;
11785         state.dst.x2 = crtc_x + crtc_w;
11786         state.dst.y1 = crtc_y;
11787         state.dst.y2 = crtc_y + crtc_h;
11788
11789         state.clip.x1 = 0;
11790         state.clip.y1 = 0;
11791         state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
11792         state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
11793
11794         state.orig_src = state.src;
11795         state.orig_dst = state.dst;
11796
11797         ret = intel_check_cursor_plane(plane, &state);
11798         if (ret)
11799                 return ret;
11800
11801         return intel_commit_cursor_plane(plane, &state);
11802 }
11803
11804 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
11805         .update_plane = intel_cursor_plane_update,
11806         .disable_plane = intel_cursor_plane_disable,
11807         .destroy = intel_plane_destroy,
11808         .set_property = intel_plane_set_property,
11809 };
11810
11811 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
11812                                                    int pipe)
11813 {
11814         struct intel_plane *cursor;
11815
11816         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
11817         if (cursor == NULL)
11818                 return NULL;
11819
11820         cursor->can_scale = false;
11821         cursor->max_downscale = 1;
11822         cursor->pipe = pipe;
11823         cursor->plane = pipe;
11824         cursor->rotation = BIT(DRM_ROTATE_0);
11825
11826         drm_universal_plane_init(dev, &cursor->base, 0,
11827                                  &intel_cursor_plane_funcs,
11828                                  intel_cursor_formats,
11829                                  ARRAY_SIZE(intel_cursor_formats),
11830                                  DRM_PLANE_TYPE_CURSOR);
11831
11832         if (INTEL_INFO(dev)->gen >= 4) {
11833                 if (!dev->mode_config.rotation_property)
11834                         dev->mode_config.rotation_property =
11835                                 drm_mode_create_rotation_property(dev,
11836                                                         BIT(DRM_ROTATE_0) |
11837                                                         BIT(DRM_ROTATE_180));
11838                 if (dev->mode_config.rotation_property)
11839                         drm_object_attach_property(&cursor->base.base,
11840                                 dev->mode_config.rotation_property,
11841                                 cursor->rotation);
11842         }
11843
11844         return &cursor->base;
11845 }
11846
11847 static void intel_crtc_init(struct drm_device *dev, int pipe)
11848 {
11849         struct drm_i915_private *dev_priv = dev->dev_private;
11850         struct intel_crtc *intel_crtc;
11851         struct drm_plane *primary = NULL;
11852         struct drm_plane *cursor = NULL;
11853         int i, ret;
11854
11855         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
11856         if (intel_crtc == NULL)
11857                 return;
11858
11859         primary = intel_primary_plane_create(dev, pipe);
11860         if (!primary)
11861                 goto fail;
11862
11863         cursor = intel_cursor_plane_create(dev, pipe);
11864         if (!cursor)
11865                 goto fail;
11866
11867         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
11868                                         cursor, &intel_crtc_funcs);
11869         if (ret)
11870                 goto fail;
11871
11872         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
11873         for (i = 0; i < 256; i++) {
11874                 intel_crtc->lut_r[i] = i;
11875                 intel_crtc->lut_g[i] = i;
11876                 intel_crtc->lut_b[i] = i;
11877         }
11878
11879         /*
11880          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
11881          * is hooked to pipe B. Hence we want plane A feeding pipe B.
11882          */
11883         intel_crtc->pipe = pipe;
11884         intel_crtc->plane = pipe;
11885         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
11886                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
11887                 intel_crtc->plane = !pipe;
11888         }
11889
11890         intel_crtc->cursor_base = ~0;
11891         intel_crtc->cursor_cntl = ~0;
11892         intel_crtc->cursor_size = ~0;
11893
11894         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
11895                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
11896         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
11897         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
11898
11899         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
11900
11901         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
11902         return;
11903
11904 fail:
11905         if (primary)
11906                 drm_plane_cleanup(primary);
11907         if (cursor)
11908                 drm_plane_cleanup(cursor);
11909         kfree(intel_crtc);
11910 }
11911
11912 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
11913 {
11914         struct drm_encoder *encoder = connector->base.encoder;
11915         struct drm_device *dev = connector->base.dev;
11916
11917         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
11918
11919         if (!encoder)
11920                 return INVALID_PIPE;
11921
11922         return to_intel_crtc(encoder->crtc)->pipe;
11923 }
11924
11925 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
11926                                 struct drm_file *file)
11927 {
11928         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
11929         struct drm_crtc *drmmode_crtc;
11930         struct intel_crtc *crtc;
11931
11932         if (!drm_core_check_feature(dev, DRIVER_MODESET))
11933                 return -ENODEV;
11934
11935         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
11936
11937         if (!drmmode_crtc) {
11938                 DRM_ERROR("no such CRTC id\n");
11939                 return -ENOENT;
11940         }
11941
11942         crtc = to_intel_crtc(drmmode_crtc);
11943         pipe_from_crtc_id->pipe = crtc->pipe;
11944
11945         return 0;
11946 }
11947
11948 static int intel_encoder_clones(struct intel_encoder *encoder)
11949 {
11950         struct drm_device *dev = encoder->base.dev;
11951         struct intel_encoder *source_encoder;
11952         int index_mask = 0;
11953         int entry = 0;
11954
11955         for_each_intel_encoder(dev, source_encoder) {
11956                 if (encoders_cloneable(encoder, source_encoder))
11957                         index_mask |= (1 << entry);
11958
11959                 entry++;
11960         }
11961
11962         return index_mask;
11963 }
11964
11965 static bool has_edp_a(struct drm_device *dev)
11966 {
11967         struct drm_i915_private *dev_priv = dev->dev_private;
11968
11969         if (!IS_MOBILE(dev))
11970                 return false;
11971
11972         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
11973                 return false;
11974
11975         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
11976                 return false;
11977
11978         return true;
11979 }
11980
11981 const char *intel_output_name(int output)
11982 {
11983         static const char *names[] = {
11984                 [INTEL_OUTPUT_UNUSED] = "Unused",
11985                 [INTEL_OUTPUT_ANALOG] = "Analog",
11986                 [INTEL_OUTPUT_DVO] = "DVO",
11987                 [INTEL_OUTPUT_SDVO] = "SDVO",
11988                 [INTEL_OUTPUT_LVDS] = "LVDS",
11989                 [INTEL_OUTPUT_TVOUT] = "TV",
11990                 [INTEL_OUTPUT_HDMI] = "HDMI",
11991                 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
11992                 [INTEL_OUTPUT_EDP] = "eDP",
11993                 [INTEL_OUTPUT_DSI] = "DSI",
11994                 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
11995         };
11996
11997         if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
11998                 return "Invalid";
11999
12000         return names[output];
12001 }
12002
12003 static bool intel_crt_present(struct drm_device *dev)
12004 {
12005         struct drm_i915_private *dev_priv = dev->dev_private;
12006
12007         if (INTEL_INFO(dev)->gen >= 9)
12008                 return false;
12009
12010         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12011                 return false;
12012
12013         if (IS_CHERRYVIEW(dev))
12014                 return false;
12015
12016         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12017                 return false;
12018
12019         return true;
12020 }
12021
12022 static void intel_setup_outputs(struct drm_device *dev)
12023 {
12024         struct drm_i915_private *dev_priv = dev->dev_private;
12025         struct intel_encoder *encoder;
12026         bool dpd_is_edp = false;
12027
12028         intel_lvds_init(dev);
12029
12030         if (intel_crt_present(dev))
12031                 intel_crt_init(dev);
12032
12033         if (HAS_DDI(dev)) {
12034                 int found;
12035
12036                 /* Haswell uses DDI functions to detect digital outputs */
12037                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12038                 /* DDI A only supports eDP */
12039                 if (found)
12040                         intel_ddi_init(dev, PORT_A);
12041
12042                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12043                  * register */
12044                 found = I915_READ(SFUSE_STRAP);
12045
12046                 if (found & SFUSE_STRAP_DDIB_DETECTED)
12047                         intel_ddi_init(dev, PORT_B);
12048                 if (found & SFUSE_STRAP_DDIC_DETECTED)
12049                         intel_ddi_init(dev, PORT_C);
12050                 if (found & SFUSE_STRAP_DDID_DETECTED)
12051                         intel_ddi_init(dev, PORT_D);
12052         } else if (HAS_PCH_SPLIT(dev)) {
12053                 int found;
12054                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12055
12056                 if (has_edp_a(dev))
12057                         intel_dp_init(dev, DP_A, PORT_A);
12058
12059                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12060                         /* PCH SDVOB multiplex with HDMIB */
12061                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
12062                         if (!found)
12063                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12064                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12065                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
12066                 }
12067
12068                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12069                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12070
12071                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12072                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12073
12074                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12075                         intel_dp_init(dev, PCH_DP_C, PORT_C);
12076
12077                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12078                         intel_dp_init(dev, PCH_DP_D, PORT_D);
12079         } else if (IS_VALLEYVIEW(dev)) {
12080                 /*
12081                  * The DP_DETECTED bit is the latched state of the DDC
12082                  * SDA pin at boot. However since eDP doesn't require DDC
12083                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
12084                  * eDP ports may have been muxed to an alternate function.
12085                  * Thus we can't rely on the DP_DETECTED bit alone to detect
12086                  * eDP ports. Consult the VBT as well as DP_DETECTED to
12087                  * detect eDP ports.
12088                  */
12089                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED)
12090                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12091                                         PORT_B);
12092                 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12093                     intel_dp_is_edp(dev, PORT_B))
12094                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12095
12096                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED)
12097                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12098                                         PORT_C);
12099                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12100                     intel_dp_is_edp(dev, PORT_C))
12101                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12102
12103                 if (IS_CHERRYVIEW(dev)) {
12104                         if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12105                                 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12106                                                 PORT_D);
12107                         /* eDP not supported on port D, so don't check VBT */
12108                         if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12109                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12110                 }
12111
12112                 intel_dsi_init(dev);
12113         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12114                 bool found = false;
12115
12116                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12117                         DRM_DEBUG_KMS("probing SDVOB\n");
12118                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12119                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12120                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12121                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12122                         }
12123
12124                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
12125                                 intel_dp_init(dev, DP_B, PORT_B);
12126                 }
12127
12128                 /* Before G4X SDVOC doesn't have its own detect register */
12129
12130                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12131                         DRM_DEBUG_KMS("probing SDVOC\n");
12132                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12133                 }
12134
12135                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12136
12137                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12138                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12139                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12140                         }
12141                         if (SUPPORTS_INTEGRATED_DP(dev))
12142                                 intel_dp_init(dev, DP_C, PORT_C);
12143                 }
12144
12145                 if (SUPPORTS_INTEGRATED_DP(dev) &&
12146                     (I915_READ(DP_D) & DP_DETECTED))
12147                         intel_dp_init(dev, DP_D, PORT_D);
12148         } else if (IS_GEN2(dev))
12149                 intel_dvo_init(dev);
12150
12151         if (SUPPORTS_TV(dev))
12152                 intel_tv_init(dev);
12153
12154         intel_edp_psr_init(dev);
12155
12156         for_each_intel_encoder(dev, encoder) {
12157                 encoder->base.possible_crtcs = encoder->crtc_mask;
12158                 encoder->base.possible_clones =
12159                         intel_encoder_clones(encoder);
12160         }
12161
12162         intel_init_pch_refclk(dev);
12163
12164         drm_helper_move_panel_connectors_to_head(dev);
12165 }
12166
12167 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12168 {
12169         struct drm_device *dev = fb->dev;
12170         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12171
12172         drm_framebuffer_cleanup(fb);
12173         mutex_lock(&dev->struct_mutex);
12174         WARN_ON(!intel_fb->obj->framebuffer_references--);
12175         drm_gem_object_unreference(&intel_fb->obj->base);
12176         mutex_unlock(&dev->struct_mutex);
12177         kfree(intel_fb);
12178 }
12179
12180 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12181                                                 struct drm_file *file,
12182                                                 unsigned int *handle)
12183 {
12184         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12185         struct drm_i915_gem_object *obj = intel_fb->obj;
12186
12187         return drm_gem_handle_create(file, &obj->base, handle);
12188 }
12189
12190 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12191         .destroy = intel_user_framebuffer_destroy,
12192         .create_handle = intel_user_framebuffer_create_handle,
12193 };
12194
12195 static int intel_framebuffer_init(struct drm_device *dev,
12196                                   struct intel_framebuffer *intel_fb,
12197                                   struct drm_mode_fb_cmd2 *mode_cmd,
12198                                   struct drm_i915_gem_object *obj)
12199 {
12200         int aligned_height;
12201         int pitch_limit;
12202         int ret;
12203
12204         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12205
12206         if (obj->tiling_mode == I915_TILING_Y) {
12207                 DRM_DEBUG("hardware does not support tiling Y\n");
12208                 return -EINVAL;
12209         }
12210
12211         if (mode_cmd->pitches[0] & 63) {
12212                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12213                           mode_cmd->pitches[0]);
12214                 return -EINVAL;
12215         }
12216
12217         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12218                 pitch_limit = 32*1024;
12219         } else if (INTEL_INFO(dev)->gen >= 4) {
12220                 if (obj->tiling_mode)
12221                         pitch_limit = 16*1024;
12222                 else
12223                         pitch_limit = 32*1024;
12224         } else if (INTEL_INFO(dev)->gen >= 3) {
12225                 if (obj->tiling_mode)
12226                         pitch_limit = 8*1024;
12227                 else
12228                         pitch_limit = 16*1024;
12229         } else
12230                 /* XXX DSPC is limited to 4k tiled */
12231                 pitch_limit = 8*1024;
12232
12233         if (mode_cmd->pitches[0] > pitch_limit) {
12234                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12235                           obj->tiling_mode ? "tiled" : "linear",
12236                           mode_cmd->pitches[0], pitch_limit);
12237                 return -EINVAL;
12238         }
12239
12240         if (obj->tiling_mode != I915_TILING_NONE &&
12241             mode_cmd->pitches[0] != obj->stride) {
12242                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12243                           mode_cmd->pitches[0], obj->stride);
12244                 return -EINVAL;
12245         }
12246
12247         /* Reject formats not supported by any plane early. */
12248         switch (mode_cmd->pixel_format) {
12249         case DRM_FORMAT_C8:
12250         case DRM_FORMAT_RGB565:
12251         case DRM_FORMAT_XRGB8888:
12252         case DRM_FORMAT_ARGB8888:
12253                 break;
12254         case DRM_FORMAT_XRGB1555:
12255         case DRM_FORMAT_ARGB1555:
12256                 if (INTEL_INFO(dev)->gen > 3) {
12257                         DRM_DEBUG("unsupported pixel format: %s\n",
12258                                   drm_get_format_name(mode_cmd->pixel_format));
12259                         return -EINVAL;
12260                 }
12261                 break;
12262         case DRM_FORMAT_XBGR8888:
12263         case DRM_FORMAT_ABGR8888:
12264         case DRM_FORMAT_XRGB2101010:
12265         case DRM_FORMAT_ARGB2101010:
12266         case DRM_FORMAT_XBGR2101010:
12267         case DRM_FORMAT_ABGR2101010:
12268                 if (INTEL_INFO(dev)->gen < 4) {
12269                         DRM_DEBUG("unsupported pixel format: %s\n",
12270                                   drm_get_format_name(mode_cmd->pixel_format));
12271                         return -EINVAL;
12272                 }
12273                 break;
12274         case DRM_FORMAT_YUYV:
12275         case DRM_FORMAT_UYVY:
12276         case DRM_FORMAT_YVYU:
12277         case DRM_FORMAT_VYUY:
12278                 if (INTEL_INFO(dev)->gen < 5) {
12279                         DRM_DEBUG("unsupported pixel format: %s\n",
12280                                   drm_get_format_name(mode_cmd->pixel_format));
12281                         return -EINVAL;
12282                 }
12283                 break;
12284         default:
12285                 DRM_DEBUG("unsupported pixel format: %s\n",
12286                           drm_get_format_name(mode_cmd->pixel_format));
12287                 return -EINVAL;
12288         }
12289
12290         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12291         if (mode_cmd->offsets[0] != 0)
12292                 return -EINVAL;
12293
12294         aligned_height = intel_align_height(dev, mode_cmd->height,
12295                                             obj->tiling_mode);
12296         /* FIXME drm helper for size checks (especially planar formats)? */
12297         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12298                 return -EINVAL;
12299
12300         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12301         intel_fb->obj = obj;
12302         intel_fb->obj->framebuffer_references++;
12303
12304         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12305         if (ret) {
12306                 DRM_ERROR("framebuffer init failed %d\n", ret);
12307                 return ret;
12308         }
12309
12310         return 0;
12311 }
12312
12313 static struct drm_framebuffer *
12314 intel_user_framebuffer_create(struct drm_device *dev,
12315                               struct drm_file *filp,
12316                               struct drm_mode_fb_cmd2 *mode_cmd)
12317 {
12318         struct drm_i915_gem_object *obj;
12319
12320         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12321                                                 mode_cmd->handles[0]));
12322         if (&obj->base == NULL)
12323                 return ERR_PTR(-ENOENT);
12324
12325         return intel_framebuffer_create(dev, mode_cmd, obj);
12326 }
12327
12328 #ifndef CONFIG_DRM_I915_FBDEV
12329 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12330 {
12331 }
12332 #endif
12333
12334 static const struct drm_mode_config_funcs intel_mode_funcs = {
12335         .fb_create = intel_user_framebuffer_create,
12336         .output_poll_changed = intel_fbdev_output_poll_changed,
12337 };
12338
12339 /* Set up chip specific display functions */
12340 static void intel_init_display(struct drm_device *dev)
12341 {
12342         struct drm_i915_private *dev_priv = dev->dev_private;
12343
12344         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12345                 dev_priv->display.find_dpll = g4x_find_best_dpll;
12346         else if (IS_CHERRYVIEW(dev))
12347                 dev_priv->display.find_dpll = chv_find_best_dpll;
12348         else if (IS_VALLEYVIEW(dev))
12349                 dev_priv->display.find_dpll = vlv_find_best_dpll;
12350         else if (IS_PINEVIEW(dev))
12351                 dev_priv->display.find_dpll = pnv_find_best_dpll;
12352         else
12353                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12354
12355         if (HAS_DDI(dev)) {
12356                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12357                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12358                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
12359                 dev_priv->display.crtc_enable = haswell_crtc_enable;
12360                 dev_priv->display.crtc_disable = haswell_crtc_disable;
12361                 dev_priv->display.off = ironlake_crtc_off;
12362                 if (INTEL_INFO(dev)->gen >= 9)
12363                         dev_priv->display.update_primary_plane =
12364                                 skylake_update_primary_plane;
12365                 else
12366                         dev_priv->display.update_primary_plane =
12367                                 ironlake_update_primary_plane;
12368         } else if (HAS_PCH_SPLIT(dev)) {
12369                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12370                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12371                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
12372                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12373                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12374                 dev_priv->display.off = ironlake_crtc_off;
12375                 dev_priv->display.update_primary_plane =
12376                         ironlake_update_primary_plane;
12377         } else if (IS_VALLEYVIEW(dev)) {
12378                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12379                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12380                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12381                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12382                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12383                 dev_priv->display.off = i9xx_crtc_off;
12384                 dev_priv->display.update_primary_plane =
12385                         i9xx_update_primary_plane;
12386         } else {
12387                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12388                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12389                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12390                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12391                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12392                 dev_priv->display.off = i9xx_crtc_off;
12393                 dev_priv->display.update_primary_plane =
12394                         i9xx_update_primary_plane;
12395         }
12396
12397         /* Returns the core display clock speed */
12398         if (IS_VALLEYVIEW(dev))
12399                 dev_priv->display.get_display_clock_speed =
12400                         valleyview_get_display_clock_speed;
12401         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12402                 dev_priv->display.get_display_clock_speed =
12403                         i945_get_display_clock_speed;
12404         else if (IS_I915G(dev))
12405                 dev_priv->display.get_display_clock_speed =
12406                         i915_get_display_clock_speed;
12407         else if (IS_I945GM(dev) || IS_845G(dev))
12408                 dev_priv->display.get_display_clock_speed =
12409                         i9xx_misc_get_display_clock_speed;
12410         else if (IS_PINEVIEW(dev))
12411                 dev_priv->display.get_display_clock_speed =
12412                         pnv_get_display_clock_speed;
12413         else if (IS_I915GM(dev))
12414                 dev_priv->display.get_display_clock_speed =
12415                         i915gm_get_display_clock_speed;
12416         else if (IS_I865G(dev))
12417                 dev_priv->display.get_display_clock_speed =
12418                         i865_get_display_clock_speed;
12419         else if (IS_I85X(dev))
12420                 dev_priv->display.get_display_clock_speed =
12421                         i855_get_display_clock_speed;
12422         else /* 852, 830 */
12423                 dev_priv->display.get_display_clock_speed =
12424                         i830_get_display_clock_speed;
12425
12426         if (IS_GEN5(dev)) {
12427                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12428         } else if (IS_GEN6(dev)) {
12429                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12430                 dev_priv->display.modeset_global_resources =
12431                         snb_modeset_global_resources;
12432         } else if (IS_IVYBRIDGE(dev)) {
12433                 /* FIXME: detect B0+ stepping and use auto training */
12434                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12435                 dev_priv->display.modeset_global_resources =
12436                         ivb_modeset_global_resources;
12437         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12438                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12439                 dev_priv->display.modeset_global_resources =
12440                         haswell_modeset_global_resources;
12441         } else if (IS_VALLEYVIEW(dev)) {
12442                 dev_priv->display.modeset_global_resources =
12443                         valleyview_modeset_global_resources;
12444         } else if (INTEL_INFO(dev)->gen >= 9) {
12445                 dev_priv->display.modeset_global_resources =
12446                         haswell_modeset_global_resources;
12447         }
12448
12449         /* Default just returns -ENODEV to indicate unsupported */
12450         dev_priv->display.queue_flip = intel_default_queue_flip;
12451
12452         switch (INTEL_INFO(dev)->gen) {
12453         case 2:
12454                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12455                 break;
12456
12457         case 3:
12458                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12459                 break;
12460
12461         case 4:
12462         case 5:
12463                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12464                 break;
12465
12466         case 6:
12467                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12468                 break;
12469         case 7:
12470         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12471                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12472                 break;
12473         }
12474
12475         intel_panel_init_backlight_funcs(dev);
12476
12477         mutex_init(&dev_priv->pps_mutex);
12478 }
12479
12480 /*
12481  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12482  * resume, or other times.  This quirk makes sure that's the case for
12483  * affected systems.
12484  */
12485 static void quirk_pipea_force(struct drm_device *dev)
12486 {
12487         struct drm_i915_private *dev_priv = dev->dev_private;
12488
12489         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12490         DRM_INFO("applying pipe a force quirk\n");
12491 }
12492
12493 static void quirk_pipeb_force(struct drm_device *dev)
12494 {
12495         struct drm_i915_private *dev_priv = dev->dev_private;
12496
12497         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
12498         DRM_INFO("applying pipe b force quirk\n");
12499 }
12500
12501 /*
12502  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12503  */
12504 static void quirk_ssc_force_disable(struct drm_device *dev)
12505 {
12506         struct drm_i915_private *dev_priv = dev->dev_private;
12507         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12508         DRM_INFO("applying lvds SSC disable quirk\n");
12509 }
12510
12511 /*
12512  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12513  * brightness value
12514  */
12515 static void quirk_invert_brightness(struct drm_device *dev)
12516 {
12517         struct drm_i915_private *dev_priv = dev->dev_private;
12518         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12519         DRM_INFO("applying inverted panel brightness quirk\n");
12520 }
12521
12522 /* Some VBT's incorrectly indicate no backlight is present */
12523 static void quirk_backlight_present(struct drm_device *dev)
12524 {
12525         struct drm_i915_private *dev_priv = dev->dev_private;
12526         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12527         DRM_INFO("applying backlight present quirk\n");
12528 }
12529
12530 struct intel_quirk {
12531         int device;
12532         int subsystem_vendor;
12533         int subsystem_device;
12534         void (*hook)(struct drm_device *dev);
12535 };
12536
12537 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12538 struct intel_dmi_quirk {
12539         void (*hook)(struct drm_device *dev);
12540         const struct dmi_system_id (*dmi_id_list)[];
12541 };
12542
12543 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12544 {
12545         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12546         return 1;
12547 }
12548
12549 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12550         {
12551                 .dmi_id_list = &(const struct dmi_system_id[]) {
12552                         {
12553                                 .callback = intel_dmi_reverse_brightness,
12554                                 .ident = "NCR Corporation",
12555                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12556                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
12557                                 },
12558                         },
12559                         { }  /* terminating entry */
12560                 },
12561                 .hook = quirk_invert_brightness,
12562         },
12563 };
12564
12565 static struct intel_quirk intel_quirks[] = {
12566         /* HP Mini needs pipe A force quirk (LP: #322104) */
12567         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12568
12569         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12570         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12571
12572         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12573         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12574
12575         /* 830 needs to leave pipe A & dpll A up */
12576         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
12577
12578         /* 830 needs to leave pipe B & dpll B up */
12579         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
12580
12581         /* Lenovo U160 cannot use SSC on LVDS */
12582         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12583
12584         /* Sony Vaio Y cannot use SSC on LVDS */
12585         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12586
12587         /* Acer Aspire 5734Z must invert backlight brightness */
12588         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12589
12590         /* Acer/eMachines G725 */
12591         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12592
12593         /* Acer/eMachines e725 */
12594         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12595
12596         /* Acer/Packard Bell NCL20 */
12597         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12598
12599         /* Acer Aspire 4736Z */
12600         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12601
12602         /* Acer Aspire 5336 */
12603         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12604
12605         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12606         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
12607
12608         /* Acer C720 Chromebook (Core i3 4005U) */
12609         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
12610
12611         /* Toshiba CB35 Chromebook (Celeron 2955U) */
12612         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
12613
12614         /* HP Chromebook 14 (Celeron 2955U) */
12615         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
12616 };
12617
12618 static void intel_init_quirks(struct drm_device *dev)
12619 {
12620         struct pci_dev *d = dev->pdev;
12621         int i;
12622
12623         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12624                 struct intel_quirk *q = &intel_quirks[i];
12625
12626                 if (d->device == q->device &&
12627                     (d->subsystem_vendor == q->subsystem_vendor ||
12628                      q->subsystem_vendor == PCI_ANY_ID) &&
12629                     (d->subsystem_device == q->subsystem_device ||
12630                      q->subsystem_device == PCI_ANY_ID))
12631                         q->hook(dev);
12632         }
12633         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12634                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12635                         intel_dmi_quirks[i].hook(dev);
12636         }
12637 }
12638
12639 /* Disable the VGA plane that we never use */
12640 static void i915_disable_vga(struct drm_device *dev)
12641 {
12642         struct drm_i915_private *dev_priv = dev->dev_private;
12643         u8 sr1;
12644         u32 vga_reg = i915_vgacntrl_reg(dev);
12645
12646         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12647         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12648         outb(SR01, VGA_SR_INDEX);
12649         sr1 = inb(VGA_SR_DATA);
12650         outb(sr1 | 1<<5, VGA_SR_DATA);
12651         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12652         udelay(300);
12653
12654         /*
12655          * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming
12656          * from S3 without preserving (some of?) the other bits.
12657          */
12658         I915_WRITE(vga_reg, dev_priv->bios_vgacntr | VGA_DISP_DISABLE);
12659         POSTING_READ(vga_reg);
12660 }
12661
12662 void intel_modeset_init_hw(struct drm_device *dev)
12663 {
12664         intel_prepare_ddi(dev);
12665
12666         if (IS_VALLEYVIEW(dev))
12667                 vlv_update_cdclk(dev);
12668
12669         intel_init_clock_gating(dev);
12670
12671         intel_enable_gt_powersave(dev);
12672 }
12673
12674 void intel_modeset_init(struct drm_device *dev)
12675 {
12676         struct drm_i915_private *dev_priv = dev->dev_private;
12677         int sprite, ret;
12678         enum pipe pipe;
12679         struct intel_crtc *crtc;
12680
12681         drm_mode_config_init(dev);
12682
12683         dev->mode_config.min_width = 0;
12684         dev->mode_config.min_height = 0;
12685
12686         dev->mode_config.preferred_depth = 24;
12687         dev->mode_config.prefer_shadow = 1;
12688
12689         dev->mode_config.funcs = &intel_mode_funcs;
12690
12691         intel_init_quirks(dev);
12692
12693         intel_init_pm(dev);
12694
12695         if (INTEL_INFO(dev)->num_pipes == 0)
12696                 return;
12697
12698         intel_init_display(dev);
12699         intel_init_audio(dev);
12700
12701         if (IS_GEN2(dev)) {
12702                 dev->mode_config.max_width = 2048;
12703                 dev->mode_config.max_height = 2048;
12704         } else if (IS_GEN3(dev)) {
12705                 dev->mode_config.max_width = 4096;
12706                 dev->mode_config.max_height = 4096;
12707         } else {
12708                 dev->mode_config.max_width = 8192;
12709                 dev->mode_config.max_height = 8192;
12710         }
12711
12712         if (IS_845G(dev) || IS_I865G(dev)) {
12713                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
12714                 dev->mode_config.cursor_height = 1023;
12715         } else if (IS_GEN2(dev)) {
12716                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12717                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12718         } else {
12719                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
12720                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
12721         }
12722
12723         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
12724
12725         DRM_DEBUG_KMS("%d display pipe%s available.\n",
12726                       INTEL_INFO(dev)->num_pipes,
12727                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
12728
12729         for_each_pipe(dev_priv, pipe) {
12730                 intel_crtc_init(dev, pipe);
12731                 for_each_sprite(pipe, sprite) {
12732                         ret = intel_plane_init(dev, pipe, sprite);
12733                         if (ret)
12734                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12735                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
12736                 }
12737         }
12738
12739         intel_init_dpio(dev);
12740
12741         intel_shared_dpll_init(dev);
12742
12743         /* save the BIOS value before clobbering it */
12744         dev_priv->bios_vgacntr = I915_READ(i915_vgacntrl_reg(dev));
12745         /* Just disable it once at startup */
12746         i915_disable_vga(dev);
12747         intel_setup_outputs(dev);
12748
12749         /* Just in case the BIOS is doing something questionable. */
12750         intel_disable_fbc(dev);
12751
12752         drm_modeset_lock_all(dev);
12753         intel_modeset_setup_hw_state(dev, false);
12754         drm_modeset_unlock_all(dev);
12755
12756         for_each_intel_crtc(dev, crtc) {
12757                 if (!crtc->active)
12758                         continue;
12759
12760                 /*
12761                  * Note that reserving the BIOS fb up front prevents us
12762                  * from stuffing other stolen allocations like the ring
12763                  * on top.  This prevents some ugliness at boot time, and
12764                  * can even allow for smooth boot transitions if the BIOS
12765                  * fb is large enough for the active pipe configuration.
12766                  */
12767                 if (dev_priv->display.get_plane_config) {
12768                         dev_priv->display.get_plane_config(crtc,
12769                                                            &crtc->plane_config);
12770                         /*
12771                          * If the fb is shared between multiple heads, we'll
12772                          * just get the first one.
12773                          */
12774                         intel_find_plane_obj(crtc, &crtc->plane_config);
12775                 }
12776         }
12777 }
12778
12779 static void intel_enable_pipe_a(struct drm_device *dev)
12780 {
12781         struct intel_connector *connector;
12782         struct drm_connector *crt = NULL;
12783         struct intel_load_detect_pipe load_detect_temp;
12784         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
12785
12786         /* We can't just switch on the pipe A, we need to set things up with a
12787          * proper mode and output configuration. As a gross hack, enable pipe A
12788          * by enabling the load detect pipe once. */
12789         list_for_each_entry(connector,
12790                             &dev->mode_config.connector_list,
12791                             base.head) {
12792                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
12793                         crt = &connector->base;
12794                         break;
12795                 }
12796         }
12797
12798         if (!crt)
12799                 return;
12800
12801         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
12802                 intel_release_load_detect_pipe(crt, &load_detect_temp);
12803 }
12804
12805 static bool
12806 intel_check_plane_mapping(struct intel_crtc *crtc)
12807 {
12808         struct drm_device *dev = crtc->base.dev;
12809         struct drm_i915_private *dev_priv = dev->dev_private;
12810         u32 reg, val;
12811
12812         if (INTEL_INFO(dev)->num_pipes == 1)
12813                 return true;
12814
12815         reg = DSPCNTR(!crtc->plane);
12816         val = I915_READ(reg);
12817
12818         if ((val & DISPLAY_PLANE_ENABLE) &&
12819             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
12820                 return false;
12821
12822         return true;
12823 }
12824
12825 static void intel_sanitize_crtc(struct intel_crtc *crtc)
12826 {
12827         struct drm_device *dev = crtc->base.dev;
12828         struct drm_i915_private *dev_priv = dev->dev_private;
12829         u32 reg;
12830
12831         /* Clear any frame start delays used for debugging left by the BIOS */
12832         reg = PIPECONF(crtc->config.cpu_transcoder);
12833         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
12834
12835         /* restore vblank interrupts to correct state */
12836         if (crtc->active) {
12837                 update_scanline_offset(crtc);
12838                 drm_vblank_on(dev, crtc->pipe);
12839         } else
12840                 drm_vblank_off(dev, crtc->pipe);
12841
12842         /* We need to sanitize the plane -> pipe mapping first because this will
12843          * disable the crtc (and hence change the state) if it is wrong. Note
12844          * that gen4+ has a fixed plane -> pipe mapping.  */
12845         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
12846                 struct intel_connector *connector;
12847                 bool plane;
12848
12849                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
12850                               crtc->base.base.id);
12851
12852                 /* Pipe has the wrong plane attached and the plane is active.
12853                  * Temporarily change the plane mapping and disable everything
12854                  * ...  */
12855                 plane = crtc->plane;
12856                 crtc->plane = !plane;
12857                 crtc->primary_enabled = true;
12858                 dev_priv->display.crtc_disable(&crtc->base);
12859                 crtc->plane = plane;
12860
12861                 /* ... and break all links. */
12862                 list_for_each_entry(connector, &dev->mode_config.connector_list,
12863                                     base.head) {
12864                         if (connector->encoder->base.crtc != &crtc->base)
12865                                 continue;
12866
12867                         connector->base.dpms = DRM_MODE_DPMS_OFF;
12868                         connector->base.encoder = NULL;
12869                 }
12870                 /* multiple connectors may have the same encoder:
12871                  *  handle them and break crtc link separately */
12872                 list_for_each_entry(connector, &dev->mode_config.connector_list,
12873                                     base.head)
12874                         if (connector->encoder->base.crtc == &crtc->base) {
12875                                 connector->encoder->base.crtc = NULL;
12876                                 connector->encoder->connectors_active = false;
12877                         }
12878
12879                 WARN_ON(crtc->active);
12880                 crtc->base.enabled = false;
12881         }
12882
12883         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
12884             crtc->pipe == PIPE_A && !crtc->active) {
12885                 /* BIOS forgot to enable pipe A, this mostly happens after
12886                  * resume. Force-enable the pipe to fix this, the update_dpms
12887                  * call below we restore the pipe to the right state, but leave
12888                  * the required bits on. */
12889                 intel_enable_pipe_a(dev);
12890         }
12891
12892         /* Adjust the state of the output pipe according to whether we
12893          * have active connectors/encoders. */
12894         intel_crtc_update_dpms(&crtc->base);
12895
12896         if (crtc->active != crtc->base.enabled) {
12897                 struct intel_encoder *encoder;
12898
12899                 /* This can happen either due to bugs in the get_hw_state
12900                  * functions or because the pipe is force-enabled due to the
12901                  * pipe A quirk. */
12902                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
12903                               crtc->base.base.id,
12904                               crtc->base.enabled ? "enabled" : "disabled",
12905                               crtc->active ? "enabled" : "disabled");
12906
12907                 crtc->base.enabled = crtc->active;
12908
12909                 /* Because we only establish the connector -> encoder ->
12910                  * crtc links if something is active, this means the
12911                  * crtc is now deactivated. Break the links. connector
12912                  * -> encoder links are only establish when things are
12913                  *  actually up, hence no need to break them. */
12914                 WARN_ON(crtc->active);
12915
12916                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
12917                         WARN_ON(encoder->connectors_active);
12918                         encoder->base.crtc = NULL;
12919                 }
12920         }
12921
12922         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
12923                 /*
12924                  * We start out with underrun reporting disabled to avoid races.
12925                  * For correct bookkeeping mark this on active crtcs.
12926                  *
12927                  * Also on gmch platforms we dont have any hardware bits to
12928                  * disable the underrun reporting. Which means we need to start
12929                  * out with underrun reporting disabled also on inactive pipes,
12930                  * since otherwise we'll complain about the garbage we read when
12931                  * e.g. coming up after runtime pm.
12932                  *
12933                  * No protection against concurrent access is required - at
12934                  * worst a fifo underrun happens which also sets this to false.
12935                  */
12936                 crtc->cpu_fifo_underrun_disabled = true;
12937                 crtc->pch_fifo_underrun_disabled = true;
12938         }
12939 }
12940
12941 static void intel_sanitize_encoder(struct intel_encoder *encoder)
12942 {
12943         struct intel_connector *connector;
12944         struct drm_device *dev = encoder->base.dev;
12945
12946         /* We need to check both for a crtc link (meaning that the
12947          * encoder is active and trying to read from a pipe) and the
12948          * pipe itself being active. */
12949         bool has_active_crtc = encoder->base.crtc &&
12950                 to_intel_crtc(encoder->base.crtc)->active;
12951
12952         if (encoder->connectors_active && !has_active_crtc) {
12953                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
12954                               encoder->base.base.id,
12955                               encoder->base.name);
12956
12957                 /* Connector is active, but has no active pipe. This is
12958                  * fallout from our resume register restoring. Disable
12959                  * the encoder manually again. */
12960                 if (encoder->base.crtc) {
12961                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
12962                                       encoder->base.base.id,
12963                                       encoder->base.name);
12964                         encoder->disable(encoder);
12965                         if (encoder->post_disable)
12966                                 encoder->post_disable(encoder);
12967                 }
12968                 encoder->base.crtc = NULL;
12969                 encoder->connectors_active = false;
12970
12971                 /* Inconsistent output/port/pipe state happens presumably due to
12972                  * a bug in one of the get_hw_state functions. Or someplace else
12973                  * in our code, like the register restore mess on resume. Clamp
12974                  * things to off as a safer default. */
12975                 list_for_each_entry(connector,
12976                                     &dev->mode_config.connector_list,
12977                                     base.head) {
12978                         if (connector->encoder != encoder)
12979                                 continue;
12980                         connector->base.dpms = DRM_MODE_DPMS_OFF;
12981                         connector->base.encoder = NULL;
12982                 }
12983         }
12984         /* Enabled encoders without active connectors will be fixed in
12985          * the crtc fixup. */
12986 }
12987
12988 void i915_redisable_vga_power_on(struct drm_device *dev)
12989 {
12990         struct drm_i915_private *dev_priv = dev->dev_private;
12991         u32 vga_reg = i915_vgacntrl_reg(dev);
12992
12993         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
12994                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
12995                 i915_disable_vga(dev);
12996         }
12997 }
12998
12999 void i915_redisable_vga(struct drm_device *dev)
13000 {
13001         struct drm_i915_private *dev_priv = dev->dev_private;
13002
13003         /* This function can be called both from intel_modeset_setup_hw_state or
13004          * at a very early point in our resume sequence, where the power well
13005          * structures are not yet restored. Since this function is at a very
13006          * paranoid "someone might have enabled VGA while we were not looking"
13007          * level, just check if the power well is enabled instead of trying to
13008          * follow the "don't touch the power well if we don't need it" policy
13009          * the rest of the driver uses. */
13010         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13011                 return;
13012
13013         i915_redisable_vga_power_on(dev);
13014 }
13015
13016 static bool primary_get_hw_state(struct intel_crtc *crtc)
13017 {
13018         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13019
13020         if (!crtc->active)
13021                 return false;
13022
13023         return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13024 }
13025
13026 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13027 {
13028         struct drm_i915_private *dev_priv = dev->dev_private;
13029         enum pipe pipe;
13030         struct intel_crtc *crtc;
13031         struct intel_encoder *encoder;
13032         struct intel_connector *connector;
13033         int i;
13034
13035         for_each_intel_crtc(dev, crtc) {
13036                 memset(&crtc->config, 0, sizeof(crtc->config));
13037
13038                 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13039
13040                 crtc->active = dev_priv->display.get_pipe_config(crtc,
13041                                                                  &crtc->config);
13042
13043                 crtc->base.enabled = crtc->active;
13044                 crtc->primary_enabled = primary_get_hw_state(crtc);
13045
13046                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13047                               crtc->base.base.id,
13048                               crtc->active ? "enabled" : "disabled");
13049         }
13050
13051         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13052                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13053
13054                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
13055                 pll->active = 0;
13056                 for_each_intel_crtc(dev, crtc) {
13057                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
13058                                 pll->active++;
13059                 }
13060                 pll->refcount = pll->active;
13061
13062                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
13063                               pll->name, pll->refcount, pll->on);
13064
13065                 if (pll->refcount)
13066                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13067         }
13068
13069         for_each_intel_encoder(dev, encoder) {
13070                 pipe = 0;
13071
13072                 if (encoder->get_hw_state(encoder, &pipe)) {
13073                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13074                         encoder->base.crtc = &crtc->base;
13075                         encoder->get_config(encoder, &crtc->config);
13076                 } else {
13077                         encoder->base.crtc = NULL;
13078                 }
13079
13080                 encoder->connectors_active = false;
13081                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13082                               encoder->base.base.id,
13083                               encoder->base.name,
13084                               encoder->base.crtc ? "enabled" : "disabled",
13085                               pipe_name(pipe));
13086         }
13087
13088         list_for_each_entry(connector, &dev->mode_config.connector_list,
13089                             base.head) {
13090                 if (connector->get_hw_state(connector)) {
13091                         connector->base.dpms = DRM_MODE_DPMS_ON;
13092                         connector->encoder->connectors_active = true;
13093                         connector->base.encoder = &connector->encoder->base;
13094                 } else {
13095                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13096                         connector->base.encoder = NULL;
13097                 }
13098                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13099                               connector->base.base.id,
13100                               connector->base.name,
13101                               connector->base.encoder ? "enabled" : "disabled");
13102         }
13103 }
13104
13105 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13106  * and i915 state tracking structures. */
13107 void intel_modeset_setup_hw_state(struct drm_device *dev,
13108                                   bool force_restore)
13109 {
13110         struct drm_i915_private *dev_priv = dev->dev_private;
13111         enum pipe pipe;
13112         struct intel_crtc *crtc;
13113         struct intel_encoder *encoder;
13114         int i;
13115
13116         intel_modeset_readout_hw_state(dev);
13117
13118         /*
13119          * Now that we have the config, copy it to each CRTC struct
13120          * Note that this could go away if we move to using crtc_config
13121          * checking everywhere.
13122          */
13123         for_each_intel_crtc(dev, crtc) {
13124                 if (crtc->active && i915.fastboot) {
13125                         intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
13126                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13127                                       crtc->base.base.id);
13128                         drm_mode_debug_printmodeline(&crtc->base.mode);
13129                 }
13130         }
13131
13132         /* HW state is read out, now we need to sanitize this mess. */
13133         for_each_intel_encoder(dev, encoder) {
13134                 intel_sanitize_encoder(encoder);
13135         }
13136
13137         for_each_pipe(dev_priv, pipe) {
13138                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13139                 intel_sanitize_crtc(crtc);
13140                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
13141         }
13142
13143         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13144                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13145
13146                 if (!pll->on || pll->active)
13147                         continue;
13148
13149                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13150
13151                 pll->disable(dev_priv, pll);
13152                 pll->on = false;
13153         }
13154
13155         if (HAS_PCH_SPLIT(dev))
13156                 ilk_wm_get_hw_state(dev);
13157
13158         if (force_restore) {
13159                 i915_redisable_vga(dev);
13160
13161                 /*
13162                  * We need to use raw interfaces for restoring state to avoid
13163                  * checking (bogus) intermediate states.
13164                  */
13165                 for_each_pipe(dev_priv, pipe) {
13166                         struct drm_crtc *crtc =
13167                                 dev_priv->pipe_to_crtc_mapping[pipe];
13168
13169                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13170                                          crtc->primary->fb);
13171                 }
13172         } else {
13173                 intel_modeset_update_staged_output_state(dev);
13174         }
13175
13176         intel_modeset_check_state(dev);
13177 }
13178
13179 void intel_modeset_gem_init(struct drm_device *dev)
13180 {
13181         struct drm_crtc *c;
13182         struct drm_i915_gem_object *obj;
13183
13184         mutex_lock(&dev->struct_mutex);
13185         intel_init_gt_powersave(dev);
13186         mutex_unlock(&dev->struct_mutex);
13187
13188         intel_modeset_init_hw(dev);
13189
13190         intel_setup_overlay(dev);
13191
13192         /*
13193          * Make sure any fbs we allocated at startup are properly
13194          * pinned & fenced.  When we do the allocation it's too early
13195          * for this.
13196          */
13197         mutex_lock(&dev->struct_mutex);
13198         for_each_crtc(dev, c) {
13199                 obj = intel_fb_obj(c->primary->fb);
13200                 if (obj == NULL)
13201                         continue;
13202
13203                 if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) {
13204                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
13205                                   to_intel_crtc(c)->pipe);
13206                         drm_framebuffer_unreference(c->primary->fb);
13207                         c->primary->fb = NULL;
13208                 }
13209         }
13210         mutex_unlock(&dev->struct_mutex);
13211 }
13212
13213 void intel_connector_unregister(struct intel_connector *intel_connector)
13214 {
13215         struct drm_connector *connector = &intel_connector->base;
13216
13217         intel_panel_destroy_backlight(connector);
13218         drm_connector_unregister(connector);
13219 }
13220
13221 void intel_modeset_cleanup(struct drm_device *dev)
13222 {
13223         struct drm_i915_private *dev_priv = dev->dev_private;
13224         struct drm_connector *connector;
13225
13226         /*
13227          * Interrupts and polling as the first thing to avoid creating havoc.
13228          * Too much stuff here (turning of rps, connectors, ...) would
13229          * experience fancy races otherwise.
13230          */
13231         intel_irq_uninstall(dev_priv);
13232
13233         /*
13234          * Due to the hpd irq storm handling the hotplug work can re-arm the
13235          * poll handlers. Hence disable polling after hpd handling is shut down.
13236          */
13237         drm_kms_helper_poll_fini(dev);
13238
13239         mutex_lock(&dev->struct_mutex);
13240
13241         intel_unregister_dsm_handler();
13242
13243         intel_disable_fbc(dev);
13244
13245         intel_disable_gt_powersave(dev);
13246
13247         ironlake_teardown_rc6(dev);
13248
13249         mutex_unlock(&dev->struct_mutex);
13250
13251         /* flush any delayed tasks or pending work */
13252         flush_scheduled_work();
13253
13254         /* destroy the backlight and sysfs files before encoders/connectors */
13255         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13256                 struct intel_connector *intel_connector;
13257
13258                 intel_connector = to_intel_connector(connector);
13259                 intel_connector->unregister(intel_connector);
13260         }
13261
13262         drm_mode_config_cleanup(dev);
13263
13264         intel_cleanup_overlay(dev);
13265
13266         mutex_lock(&dev->struct_mutex);
13267         intel_cleanup_gt_powersave(dev);
13268         mutex_unlock(&dev->struct_mutex);
13269 }
13270
13271 /*
13272  * Return which encoder is currently attached for connector.
13273  */
13274 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13275 {
13276         return &intel_attached_encoder(connector)->base;
13277 }
13278
13279 void intel_connector_attach_encoder(struct intel_connector *connector,
13280                                     struct intel_encoder *encoder)
13281 {
13282         connector->encoder = encoder;
13283         drm_mode_connector_attach_encoder(&connector->base,
13284                                           &encoder->base);
13285 }
13286
13287 /*
13288  * set vga decode state - true == enable VGA decode
13289  */
13290 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13291 {
13292         struct drm_i915_private *dev_priv = dev->dev_private;
13293         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13294         u16 gmch_ctrl;
13295
13296         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13297                 DRM_ERROR("failed to read control word\n");
13298                 return -EIO;
13299         }
13300
13301         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13302                 return 0;
13303
13304         if (state)
13305                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13306         else
13307                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13308
13309         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13310                 DRM_ERROR("failed to write control word\n");
13311                 return -EIO;
13312         }
13313
13314         return 0;
13315 }
13316
13317 struct intel_display_error_state {
13318
13319         u32 power_well_driver;
13320
13321         int num_transcoders;
13322
13323         struct intel_cursor_error_state {
13324                 u32 control;
13325                 u32 position;
13326                 u32 base;
13327                 u32 size;
13328         } cursor[I915_MAX_PIPES];
13329
13330         struct intel_pipe_error_state {
13331                 bool power_domain_on;
13332                 u32 source;
13333                 u32 stat;
13334         } pipe[I915_MAX_PIPES];
13335
13336         struct intel_plane_error_state {
13337                 u32 control;
13338                 u32 stride;
13339                 u32 size;
13340                 u32 pos;
13341                 u32 addr;
13342                 u32 surface;
13343                 u32 tile_offset;
13344         } plane[I915_MAX_PIPES];
13345
13346         struct intel_transcoder_error_state {
13347                 bool power_domain_on;
13348                 enum transcoder cpu_transcoder;
13349
13350                 u32 conf;
13351
13352                 u32 htotal;
13353                 u32 hblank;
13354                 u32 hsync;
13355                 u32 vtotal;
13356                 u32 vblank;
13357                 u32 vsync;
13358         } transcoder[4];
13359 };
13360
13361 struct intel_display_error_state *
13362 intel_display_capture_error_state(struct drm_device *dev)
13363 {
13364         struct drm_i915_private *dev_priv = dev->dev_private;
13365         struct intel_display_error_state *error;
13366         int transcoders[] = {
13367                 TRANSCODER_A,
13368                 TRANSCODER_B,
13369                 TRANSCODER_C,
13370                 TRANSCODER_EDP,
13371         };
13372         int i;
13373
13374         if (INTEL_INFO(dev)->num_pipes == 0)
13375                 return NULL;
13376
13377         error = kzalloc(sizeof(*error), GFP_ATOMIC);
13378         if (error == NULL)
13379                 return NULL;
13380
13381         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13382                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13383
13384         for_each_pipe(dev_priv, i) {
13385                 error->pipe[i].power_domain_on =
13386                         __intel_display_power_is_enabled(dev_priv,
13387                                                          POWER_DOMAIN_PIPE(i));
13388                 if (!error->pipe[i].power_domain_on)
13389                         continue;
13390
13391                 error->cursor[i].control = I915_READ(CURCNTR(i));
13392                 error->cursor[i].position = I915_READ(CURPOS(i));
13393                 error->cursor[i].base = I915_READ(CURBASE(i));
13394
13395                 error->plane[i].control = I915_READ(DSPCNTR(i));
13396                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13397                 if (INTEL_INFO(dev)->gen <= 3) {
13398                         error->plane[i].size = I915_READ(DSPSIZE(i));
13399                         error->plane[i].pos = I915_READ(DSPPOS(i));
13400                 }
13401                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13402                         error->plane[i].addr = I915_READ(DSPADDR(i));
13403                 if (INTEL_INFO(dev)->gen >= 4) {
13404                         error->plane[i].surface = I915_READ(DSPSURF(i));
13405                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13406                 }
13407
13408                 error->pipe[i].source = I915_READ(PIPESRC(i));
13409
13410                 if (HAS_GMCH_DISPLAY(dev))
13411                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
13412         }
13413
13414         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13415         if (HAS_DDI(dev_priv->dev))
13416                 error->num_transcoders++; /* Account for eDP. */
13417
13418         for (i = 0; i < error->num_transcoders; i++) {
13419                 enum transcoder cpu_transcoder = transcoders[i];
13420
13421                 error->transcoder[i].power_domain_on =
13422                         __intel_display_power_is_enabled(dev_priv,
13423                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13424                 if (!error->transcoder[i].power_domain_on)
13425                         continue;
13426
13427                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13428
13429                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13430                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13431                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13432                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13433                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13434                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13435                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13436         }
13437
13438         return error;
13439 }
13440
13441 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13442
13443 void
13444 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13445                                 struct drm_device *dev,
13446                                 struct intel_display_error_state *error)
13447 {
13448         struct drm_i915_private *dev_priv = dev->dev_private;
13449         int i;
13450
13451         if (!error)
13452                 return;
13453
13454         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13455         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13456                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13457                            error->power_well_driver);
13458         for_each_pipe(dev_priv, i) {
13459                 err_printf(m, "Pipe [%d]:\n", i);
13460                 err_printf(m, "  Power: %s\n",
13461                            error->pipe[i].power_domain_on ? "on" : "off");
13462                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
13463                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
13464
13465                 err_printf(m, "Plane [%d]:\n", i);
13466                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
13467                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
13468                 if (INTEL_INFO(dev)->gen <= 3) {
13469                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
13470                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
13471                 }
13472                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13473                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
13474                 if (INTEL_INFO(dev)->gen >= 4) {
13475                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
13476                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
13477                 }
13478
13479                 err_printf(m, "Cursor [%d]:\n", i);
13480                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
13481                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
13482                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
13483         }
13484
13485         for (i = 0; i < error->num_transcoders; i++) {
13486                 err_printf(m, "CPU transcoder: %c\n",
13487                            transcoder_name(error->transcoder[i].cpu_transcoder));
13488                 err_printf(m, "  Power: %s\n",
13489                            error->transcoder[i].power_domain_on ? "on" : "off");
13490                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
13491                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
13492                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
13493                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
13494                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
13495                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
13496                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
13497         }
13498 }
13499
13500 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
13501 {
13502         struct intel_crtc *crtc;
13503
13504         for_each_intel_crtc(dev, crtc) {
13505                 struct intel_unpin_work *work;
13506
13507                 spin_lock_irq(&dev->event_lock);
13508
13509                 work = crtc->unpin_work;
13510
13511                 if (work && work->event &&
13512                     work->event->base.file_priv == file) {
13513                         kfree(work->event);
13514                         work->event = NULL;
13515                 }
13516
13517                 spin_unlock_irq(&dev->event_lock);
13518         }
13519 }