drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 #define DIV_ROUND_CLOSEST_ULL(ll, d)    \
  45         ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
  46
  47 static void intel_increase_pllclock(struct drm_crtc *crtc);
  48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  49
  50 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  51                                 struct intel_crtc_config *pipe_config);
  52 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  53                                    struct intel_crtc_config *pipe_config);
  54
  55 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  56                           int x, int y, struct drm_framebuffer *old_fb);
  57 static int intel_framebuffer_init(struct drm_device *dev,
  58                                   struct intel_framebuffer *ifb,
  59                                   struct drm_mode_fb_cmd2 *mode_cmd,
  60                                   struct drm_i915_gem_object *obj);
  61
  62 typedef struct {
  63         int     min, max;
  64 } intel_range_t;
  65
  66 typedef struct {
  67         int     dot_limit;
  68         int     p2_slow, p2_fast;
  69 } intel_p2_t;
  70
  71 typedef struct intel_limit intel_limit_t;
  72 struct intel_limit {
  73         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  74         intel_p2_t          p2;
  75 };
  76
  77 int
  78 intel_pch_rawclk(struct drm_device *dev)
  79 {
  80         struct drm_i915_private *dev_priv = dev->dev_private;
  81
  82         WARN_ON(!HAS_PCH_SPLIT(dev));
  83
  84         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  85 }
  86
  87 static inline u32 /* units of 100MHz */
  88 intel_fdi_link_freq(struct drm_device *dev)
  89 {
  90         if (IS_GEN5(dev)) {
  91                 struct drm_i915_private *dev_priv = dev->dev_private;
  92                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  93         } else
  94                 return 27;
  95 }
  96
  97 static const intel_limit_t intel_limits_i8xx_dac = {
  98         .dot = { .min = 25000, .max = 350000 },
  99         .vco = { .min = 908000, .max = 1512000 },
 100         .n = { .min = 2, .max = 16 },
 101         .m = { .min = 96, .max = 140 },
 102         .m1 = { .min = 18, .max = 26 },
 103         .m2 = { .min = 6, .max = 16 },
 104         .p = { .min = 4, .max = 128 },
 105         .p1 = { .min = 2, .max = 33 },
 106         .p2 = { .dot_limit = 165000,
 107                 .p2_slow = 4, .p2_fast = 2 },
 108 };
 109
 110 static const intel_limit_t intel_limits_i8xx_dvo = {
 111         .dot = { .min = 25000, .max = 350000 },
 112         .vco = { .min = 908000, .max = 1512000 },
 113         .n = { .min = 2, .max = 16 },
 114         .m = { .min = 96, .max = 140 },
 115         .m1 = { .min = 18, .max = 26 },
 116         .m2 = { .min = 6, .max = 16 },
 117         .p = { .min = 4, .max = 128 },
 118         .p1 = { .min = 2, .max = 33 },
 119         .p2 = { .dot_limit = 165000,
 120                 .p2_slow = 4, .p2_fast = 4 },
 121 };
 122
 123 static const intel_limit_t intel_limits_i8xx_lvds = {
 124         .dot = { .min = 25000, .max = 350000 },
 125         .vco = { .min = 908000, .max = 1512000 },
 126         .n = { .min = 2, .max = 16 },
 127         .m = { .min = 96, .max = 140 },
 128         .m1 = { .min = 18, .max = 26 },
 129         .m2 = { .min = 6, .max = 16 },
 130         .p = { .min = 4, .max = 128 },
 131         .p1 = { .min = 1, .max = 6 },
 132         .p2 = { .dot_limit = 165000,
 133                 .p2_slow = 14, .p2_fast = 7 },
 134 };
 135
 136 static const intel_limit_t intel_limits_i9xx_sdvo = {
 137         .dot = { .min = 20000, .max = 400000 },
 138         .vco = { .min = 1400000, .max = 2800000 },
 139         .n = { .min = 1, .max = 6 },
 140         .m = { .min = 70, .max = 120 },
 141         .m1 = { .min = 8, .max = 18 },
 142         .m2 = { .min = 3, .max = 7 },
 143         .p = { .min = 5, .max = 80 },
 144         .p1 = { .min = 1, .max = 8 },
 145         .p2 = { .dot_limit = 200000,
 146                 .p2_slow = 10, .p2_fast = 5 },
 147 };
 148
 149 static const intel_limit_t intel_limits_i9xx_lvds = {
 150         .dot = { .min = 20000, .max = 400000 },
 151         .vco = { .min = 1400000, .max = 2800000 },
 152         .n = { .min = 1, .max = 6 },
 153         .m = { .min = 70, .max = 120 },
 154         .m1 = { .min = 8, .max = 18 },
 155         .m2 = { .min = 3, .max = 7 },
 156         .p = { .min = 7, .max = 98 },
 157         .p1 = { .min = 1, .max = 8 },
 158         .p2 = { .dot_limit = 112000,
 159                 .p2_slow = 14, .p2_fast = 7 },
 160 };
 161
 162
 163 static const intel_limit_t intel_limits_g4x_sdvo = {
 164         .dot = { .min = 25000, .max = 270000 },
 165         .vco = { .min = 1750000, .max = 3500000},
 166         .n = { .min = 1, .max = 4 },
 167         .m = { .min = 104, .max = 138 },
 168         .m1 = { .min = 17, .max = 23 },
 169         .m2 = { .min = 5, .max = 11 },
 170         .p = { .min = 10, .max = 30 },
 171         .p1 = { .min = 1, .max = 3},
 172         .p2 = { .dot_limit = 270000,
 173                 .p2_slow = 10,
 174                 .p2_fast = 10
 175         },
 176 };
 177
 178 static const intel_limit_t intel_limits_g4x_hdmi = {
 179         .dot = { .min = 22000, .max = 400000 },
 180         .vco = { .min = 1750000, .max = 3500000},
 181         .n = { .min = 1, .max = 4 },
 182         .m = { .min = 104, .max = 138 },
 183         .m1 = { .min = 16, .max = 23 },
 184         .m2 = { .min = 5, .max = 11 },
 185         .p = { .min = 5, .max = 80 },
 186         .p1 = { .min = 1, .max = 8},
 187         .p2 = { .dot_limit = 165000,
 188                 .p2_slow = 10, .p2_fast = 5 },
 189 };
 190
 191 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 192         .dot = { .min = 20000, .max = 115000 },
 193         .vco = { .min = 1750000, .max = 3500000 },
 194         .n = { .min = 1, .max = 3 },
 195         .m = { .min = 104, .max = 138 },
 196         .m1 = { .min = 17, .max = 23 },
 197         .m2 = { .min = 5, .max = 11 },
 198         .p = { .min = 28, .max = 112 },
 199         .p1 = { .min = 2, .max = 8 },
 200         .p2 = { .dot_limit = 0,
 201                 .p2_slow = 14, .p2_fast = 14
 202         },
 203 };
 204
 205 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 206         .dot = { .min = 80000, .max = 224000 },
 207         .vco = { .min = 1750000, .max = 3500000 },
 208         .n = { .min = 1, .max = 3 },
 209         .m = { .min = 104, .max = 138 },
 210         .m1 = { .min = 17, .max = 23 },
 211         .m2 = { .min = 5, .max = 11 },
 212         .p = { .min = 14, .max = 42 },
 213         .p1 = { .min = 2, .max = 6 },
 214         .p2 = { .dot_limit = 0,
 215                 .p2_slow = 7, .p2_fast = 7
 216         },
 217 };
 218
 219 static const intel_limit_t intel_limits_pineview_sdvo = {
 220         .dot = { .min = 20000, .max = 400000},
 221         .vco = { .min = 1700000, .max = 3500000 },
 222         /* Pineview's Ncounter is a ring counter */
 223         .n = { .min = 3, .max = 6 },
 224         .m = { .min = 2, .max = 256 },
 225         /* Pineview only has one combined m divider, which we treat as m2. */
 226         .m1 = { .min = 0, .max = 0 },
 227         .m2 = { .min = 0, .max = 254 },
 228         .p = { .min = 5, .max = 80 },
 229         .p1 = { .min = 1, .max = 8 },
 230         .p2 = { .dot_limit = 200000,
 231                 .p2_slow = 10, .p2_fast = 5 },
 232 };
 233
 234 static const intel_limit_t intel_limits_pineview_lvds = {
 235         .dot = { .min = 20000, .max = 400000 },
 236         .vco = { .min = 1700000, .max = 3500000 },
 237         .n = { .min = 3, .max = 6 },
 238         .m = { .min = 2, .max = 256 },
 239         .m1 = { .min = 0, .max = 0 },
 240         .m2 = { .min = 0, .max = 254 },
 241         .p = { .min = 7, .max = 112 },
 242         .p1 = { .min = 1, .max = 8 },
 243         .p2 = { .dot_limit = 112000,
 244                 .p2_slow = 14, .p2_fast = 14 },
 245 };
 246
 247 /* Ironlake / Sandybridge
 248  *
 249  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 250  * the range value for them is (actual_value - 2).
 251  */
 252 static const intel_limit_t intel_limits_ironlake_dac = {
 253         .dot = { .min = 25000, .max = 350000 },
 254         .vco = { .min = 1760000, .max = 3510000 },
 255         .n = { .min = 1, .max = 5 },
 256         .m = { .min = 79, .max = 127 },
 257         .m1 = { .min = 12, .max = 22 },
 258         .m2 = { .min = 5, .max = 9 },
 259         .p = { .min = 5, .max = 80 },
 260         .p1 = { .min = 1, .max = 8 },
 261         .p2 = { .dot_limit = 225000,
 262                 .p2_slow = 10, .p2_fast = 5 },
 263 };
 264
 265 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 266         .dot = { .min = 25000, .max = 350000 },
 267         .vco = { .min = 1760000, .max = 3510000 },
 268         .n = { .min = 1, .max = 3 },
 269         .m = { .min = 79, .max = 118 },
 270         .m1 = { .min = 12, .max = 22 },
 271         .m2 = { .min = 5, .max = 9 },
 272         .p = { .min = 28, .max = 112 },
 273         .p1 = { .min = 2, .max = 8 },
 274         .p2 = { .dot_limit = 225000,
 275                 .p2_slow = 14, .p2_fast = 14 },
 276 };
 277
 278 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 279         .dot = { .min = 25000, .max = 350000 },
 280         .vco = { .min = 1760000, .max = 3510000 },
 281         .n = { .min = 1, .max = 3 },
 282         .m = { .min = 79, .max = 127 },
 283         .m1 = { .min = 12, .max = 22 },
 284         .m2 = { .min = 5, .max = 9 },
 285         .p = { .min = 14, .max = 56 },
 286         .p1 = { .min = 2, .max = 8 },
 287         .p2 = { .dot_limit = 225000,
 288                 .p2_slow = 7, .p2_fast = 7 },
 289 };
 290
 291 /* LVDS 100mhz refclk limits. */
 292 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 293         .dot = { .min = 25000, .max = 350000 },
 294         .vco = { .min = 1760000, .max = 3510000 },
 295         .n = { .min = 1, .max = 2 },
 296         .m = { .min = 79, .max = 126 },
 297         .m1 = { .min = 12, .max = 22 },
 298         .m2 = { .min = 5, .max = 9 },
 299         .p = { .min = 28, .max = 112 },
 300         .p1 = { .min = 2, .max = 8 },
 301         .p2 = { .dot_limit = 225000,
 302                 .p2_slow = 14, .p2_fast = 14 },
 303 };
 304
 305 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 306         .dot = { .min = 25000, .max = 350000 },
 307         .vco = { .min = 1760000, .max = 3510000 },
 308         .n = { .min = 1, .max = 3 },
 309         .m = { .min = 79, .max = 126 },
 310         .m1 = { .min = 12, .max = 22 },
 311         .m2 = { .min = 5, .max = 9 },
 312         .p = { .min = 14, .max = 42 },
 313         .p1 = { .min = 2, .max = 6 },
 314         .p2 = { .dot_limit = 225000,
 315                 .p2_slow = 7, .p2_fast = 7 },
 316 };
 317
 318 static const intel_limit_t intel_limits_vlv = {
 319          /*
 320           * These are the data rate limits (measured in fast clocks)
 321           * since those are the strictest limits we have. The fast
 322           * clock and actual rate limits are more relaxed, so checking
 323           * them would make no difference.
 324           */
 325         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 326         .vco = { .min = 4000000, .max = 6000000 },
 327         .n = { .min = 1, .max = 7 },
 328         .m1 = { .min = 2, .max = 3 },
 329         .m2 = { .min = 11, .max = 156 },
 330         .p1 = { .min = 2, .max = 3 },
 331         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 332 };
 333
 334 static const intel_limit_t intel_limits_chv = {
 335         /*
 336          * These are the data rate limits (measured in fast clocks)
 337          * since those are the strictest limits we have.  The fast
 338          * clock and actual rate limits are more relaxed, so checking
 339          * them would make no difference.
 340          */
 341         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 342         .vco = { .min = 4860000, .max = 6700000 },
 343         .n = { .min = 1, .max = 1 },
 344         .m1 = { .min = 2, .max = 2 },
 345         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 346         .p1 = { .min = 2, .max = 4 },
 347         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 348 };
 349
 350 static void vlv_clock(int refclk, intel_clock_t *clock)
 351 {
 352         clock->m = clock->m1 * clock->m2;
 353         clock->p = clock->p1 * clock->p2;
 354         if (WARN_ON(clock->n == 0 || clock->p == 0))
 355                 return;
 356         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 357         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 358 }
 359
 360 /**
 361  * Returns whether any output on the specified pipe is of the specified type
 362  */
 363 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 364 {
 365         struct drm_device *dev = crtc->dev;
 366         struct intel_encoder *encoder;
 367
 368         for_each_encoder_on_crtc(dev, crtc, encoder)
 369                 if (encoder->type == type)
 370                         return true;
 371
 372         return false;
 373 }
 374
 375 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 376                                                 int refclk)
 377 {
 378         struct drm_device *dev = crtc->dev;
 379         const intel_limit_t *limit;
 380
 381         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 382                 if (intel_is_dual_link_lvds(dev)) {
 383                         if (refclk == 100000)
 384                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 385                         else
 386                                 limit = &intel_limits_ironlake_dual_lvds;
 387                 } else {
 388                         if (refclk == 100000)
 389                                 limit = &intel_limits_ironlake_single_lvds_100m;
 390                         else
 391                                 limit = &intel_limits_ironlake_single_lvds;
 392                 }
 393         } else
 394                 limit = &intel_limits_ironlake_dac;
 395
 396         return limit;
 397 }
 398
 399 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 400 {
 401         struct drm_device *dev = crtc->dev;
 402         const intel_limit_t *limit;
 403
 404         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 405                 if (intel_is_dual_link_lvds(dev))
 406                         limit = &intel_limits_g4x_dual_channel_lvds;
 407                 else
 408                         limit = &intel_limits_g4x_single_channel_lvds;
 409         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 410                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 411                 limit = &intel_limits_g4x_hdmi;
 412         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 413                 limit = &intel_limits_g4x_sdvo;
 414         } else /* The option is for other outputs */
 415                 limit = &intel_limits_i9xx_sdvo;
 416
 417         return limit;
 418 }
 419
 420 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 421 {
 422         struct drm_device *dev = crtc->dev;
 423         const intel_limit_t *limit;
 424
 425         if (HAS_PCH_SPLIT(dev))
 426                 limit = intel_ironlake_limit(crtc, refclk);
 427         else if (IS_G4X(dev)) {
 428                 limit = intel_g4x_limit(crtc);
 429         } else if (IS_PINEVIEW(dev)) {
 430                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 431                         limit = &intel_limits_pineview_lvds;
 432                 else
 433                         limit = &intel_limits_pineview_sdvo;
 434         } else if (IS_CHERRYVIEW(dev)) {
 435                 limit = &intel_limits_chv;
 436         } else if (IS_VALLEYVIEW(dev)) {
 437                 limit = &intel_limits_vlv;
 438         } else if (!IS_GEN2(dev)) {
 439                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 440                         limit = &intel_limits_i9xx_lvds;
 441                 else
 442                         limit = &intel_limits_i9xx_sdvo;
 443         } else {
 444                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 445                         limit = &intel_limits_i8xx_lvds;
 446                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 447                         limit = &intel_limits_i8xx_dvo;
 448                 else
 449                         limit = &intel_limits_i8xx_dac;
 450         }
 451         return limit;
 452 }
 453
 454 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 455 static void pineview_clock(int refclk, intel_clock_t *clock)
 456 {
 457         clock->m = clock->m2 + 2;
 458         clock->p = clock->p1 * clock->p2;
 459         if (WARN_ON(clock->n == 0 || clock->p == 0))
 460                 return;
 461         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 462         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 463 }
 464
 465 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 466 {
 467         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 468 }
 469
 470 static void i9xx_clock(int refclk, intel_clock_t *clock)
 471 {
 472         clock->m = i9xx_dpll_compute_m(clock);
 473         clock->p = clock->p1 * clock->p2;
 474         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 475                 return;
 476         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 477         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 478 }
 479
 480 static void chv_clock(int refclk, intel_clock_t *clock)
 481 {
 482         clock->m = clock->m1 * clock->m2;
 483         clock->p = clock->p1 * clock->p2;
 484         if (WARN_ON(clock->n == 0 || clock->p == 0))
 485                 return;
 486         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 487                         clock->n << 22);
 488         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 489 }
 490
 491 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 492 /**
 493  * Returns whether the given set of divisors are valid for a given refclk with
 494  * the given connectors.
 495  */
 496
 497 static bool intel_PLL_is_valid(struct drm_device *dev,
 498                                const intel_limit_t *limit,
 499                                const intel_clock_t *clock)
 500 {
 501         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 502                 INTELPllInvalid("n out of range\n");
 503         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 504                 INTELPllInvalid("p1 out of range\n");
 505         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 506                 INTELPllInvalid("m2 out of range\n");
 507         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 508                 INTELPllInvalid("m1 out of range\n");
 509
 510         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 511                 if (clock->m1 <= clock->m2)
 512                         INTELPllInvalid("m1 <= m2\n");
 513
 514         if (!IS_VALLEYVIEW(dev)) {
 515                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 516                         INTELPllInvalid("p out of range\n");
 517                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 518                         INTELPllInvalid("m out of range\n");
 519         }
 520
 521         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 522                 INTELPllInvalid("vco out of range\n");
 523         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 524          * connector, etc., rather than just a single range.
 525          */
 526         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 527                 INTELPllInvalid("dot out of range\n");
 528
 529         return true;
 530 }
 531
 532 static bool
 533 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 534                     int target, int refclk, intel_clock_t *match_clock,
 535                     intel_clock_t *best_clock)
 536 {
 537         struct drm_device *dev = crtc->dev;
 538         intel_clock_t clock;
 539         int err = target;
 540
 541         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 542                 /*
 543                  * For LVDS just rely on its current settings for dual-channel.
 544                  * We haven't figured out how to reliably set up different
 545                  * single/dual channel state, if we even can.
 546                  */
 547                 if (intel_is_dual_link_lvds(dev))
 548                         clock.p2 = limit->p2.p2_fast;
 549                 else
 550                         clock.p2 = limit->p2.p2_slow;
 551         } else {
 552                 if (target < limit->p2.dot_limit)
 553                         clock.p2 = limit->p2.p2_slow;
 554                 else
 555                         clock.p2 = limit->p2.p2_fast;
 556         }
 557
 558         memset(best_clock, 0, sizeof(*best_clock));
 559
 560         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 561              clock.m1++) {
 562                 for (clock.m2 = limit->m2.min;
 563                      clock.m2 <= limit->m2.max; clock.m2++) {
 564                         if (clock.m2 >= clock.m1)
 565                                 break;
 566                         for (clock.n = limit->n.min;
 567                              clock.n <= limit->n.max; clock.n++) {
 568                                 for (clock.p1 = limit->p1.min;
 569                                         clock.p1 <= limit->p1.max; clock.p1++) {
 570                                         int this_err;
 571
 572                                         i9xx_clock(refclk, &clock);
 573                                         if (!intel_PLL_is_valid(dev, limit,
 574                                                                 &clock))
 575                                                 continue;
 576                                         if (match_clock &&
 577                                             clock.p != match_clock->p)
 578                                                 continue;
 579
 580                                         this_err = abs(clock.dot - target);
 581                                         if (this_err < err) {
 582                                                 *best_clock = clock;
 583                                                 err = this_err;
 584                                         }
 585                                 }
 586                         }
 587                 }
 588         }
 589
 590         return (err != target);
 591 }
 592
 593 static bool
 594 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 595                    int target, int refclk, intel_clock_t *match_clock,
 596                    intel_clock_t *best_clock)
 597 {
 598         struct drm_device *dev = crtc->dev;
 599         intel_clock_t clock;
 600         int err = target;
 601
 602         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 603                 /*
 604                  * For LVDS just rely on its current settings for dual-channel.
 605                  * We haven't figured out how to reliably set up different
 606                  * single/dual channel state, if we even can.
 607                  */
 608                 if (intel_is_dual_link_lvds(dev))
 609                         clock.p2 = limit->p2.p2_fast;
 610                 else
 611                         clock.p2 = limit->p2.p2_slow;
 612         } else {
 613                 if (target < limit->p2.dot_limit)
 614                         clock.p2 = limit->p2.p2_slow;
 615                 else
 616                         clock.p2 = limit->p2.p2_fast;
 617         }
 618
 619         memset(best_clock, 0, sizeof(*best_clock));
 620
 621         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 622              clock.m1++) {
 623                 for (clock.m2 = limit->m2.min;
 624                      clock.m2 <= limit->m2.max; clock.m2++) {
 625                         for (clock.n = limit->n.min;
 626                              clock.n <= limit->n.max; clock.n++) {
 627                                 for (clock.p1 = limit->p1.min;
 628                                         clock.p1 <= limit->p1.max; clock.p1++) {
 629                                         int this_err;
 630
 631                                         pineview_clock(refclk, &clock);
 632                                         if (!intel_PLL_is_valid(dev, limit,
 633                                                                 &clock))
 634                                                 continue;
 635                                         if (match_clock &&
 636                                             clock.p != match_clock->p)
 637                                                 continue;
 638
 639                                         this_err = abs(clock.dot - target);
 640                                         if (this_err < err) {
 641                                                 *best_clock = clock;
 642                                                 err = this_err;
 643                                         }
 644                                 }
 645                         }
 646                 }
 647         }
 648
 649         return (err != target);
 650 }
 651
 652 static bool
 653 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 654                    int target, int refclk, intel_clock_t *match_clock,
 655                    intel_clock_t *best_clock)
 656 {
 657         struct drm_device *dev = crtc->dev;
 658         intel_clock_t clock;
 659         int max_n;
 660         bool found;
 661         /* approximately equals target * 0.00585 */
 662         int err_most = (target >> 8) + (target >> 9);
 663         found = false;
 664
 665         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 666                 if (intel_is_dual_link_lvds(dev))
 667                         clock.p2 = limit->p2.p2_fast;
 668                 else
 669                         clock.p2 = limit->p2.p2_slow;
 670         } else {
 671                 if (target < limit->p2.dot_limit)
 672                         clock.p2 = limit->p2.p2_slow;
 673                 else
 674                         clock.p2 = limit->p2.p2_fast;
 675         }
 676
 677         memset(best_clock, 0, sizeof(*best_clock));
 678         max_n = limit->n.max;
 679         /* based on hardware requirement, prefer smaller n to precision */
 680         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 681                 /* based on hardware requirement, prefere larger m1,m2 */
 682                 for (clock.m1 = limit->m1.max;
 683                      clock.m1 >= limit->m1.min; clock.m1--) {
 684                         for (clock.m2 = limit->m2.max;
 685                              clock.m2 >= limit->m2.min; clock.m2--) {
 686                                 for (clock.p1 = limit->p1.max;
 687                                      clock.p1 >= limit->p1.min; clock.p1--) {
 688                                         int this_err;
 689
 690                                         i9xx_clock(refclk, &clock);
 691                                         if (!intel_PLL_is_valid(dev, limit,
 692                                                                 &clock))
 693                                                 continue;
 694
 695                                         this_err = abs(clock.dot - target);
 696                                         if (this_err < err_most) {
 697                                                 *best_clock = clock;
 698                                                 err_most = this_err;
 699                                                 max_n = clock.n;
 700                                                 found = true;
 701                                         }
 702                                 }
 703                         }
 704                 }
 705         }
 706         return found;
 707 }
 708
 709 static bool
 710 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 711                    int target, int refclk, intel_clock_t *match_clock,
 712                    intel_clock_t *best_clock)
 713 {
 714         struct drm_device *dev = crtc->dev;
 715         intel_clock_t clock;
 716         unsigned int bestppm = 1000000;
 717         /* min update 19.2 MHz */
 718         int max_n = min(limit->n.max, refclk / 19200);
 719         bool found = false;
 720
 721         target *= 5; /* fast clock */
 722
 723         memset(best_clock, 0, sizeof(*best_clock));
 724
 725         /* based on hardware requirement, prefer smaller n to precision */
 726         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 727                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 728                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 729                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 730                                 clock.p = clock.p1 * clock.p2;
 731                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 732                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 733                                         unsigned int ppm, diff;
 734
 735                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 736                                                                      refclk * clock.m1);
 737
 738                                         vlv_clock(refclk, &clock);
 739
 740                                         if (!intel_PLL_is_valid(dev, limit,
 741                                                                 &clock))
 742                                                 continue;
 743
 744                                         diff = abs(clock.dot - target);
 745                                         ppm = div_u64(1000000ULL * diff, target);
 746
 747                                         if (ppm < 100 && clock.p > best_clock->p) {
 748                                                 bestppm = 0;
 749                                                 *best_clock = clock;
 750                                                 found = true;
 751                                         }
 752
 753                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 754                                                 bestppm = ppm;
 755                                                 *best_clock = clock;
 756                                                 found = true;
 757                                         }
 758                                 }
 759                         }
 760                 }
 761         }
 762
 763         return found;
 764 }
 765
 766 static bool
 767 chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 768                    int target, int refclk, intel_clock_t *match_clock,
 769                    intel_clock_t *best_clock)
 770 {
 771         struct drm_device *dev = crtc->dev;
 772         intel_clock_t clock;
 773         uint64_t m2;
 774         int found = false;
 775
 776         memset(best_clock, 0, sizeof(*best_clock));
 777
 778         /*
 779          * Based on hardware doc, the n always set to 1, and m1 always
 780          * set to 2.  If requires to support 200Mhz refclk, we need to
 781          * revisit this because n may not 1 anymore.
 782          */
 783         clock.n = 1, clock.m1 = 2;
 784         target *= 5;    /* fast clock */
 785
 786         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 787                 for (clock.p2 = limit->p2.p2_fast;
 788                                 clock.p2 >= limit->p2.p2_slow;
 789                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 790
 791                         clock.p = clock.p1 * clock.p2;
 792
 793                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 794                                         clock.n) << 22, refclk * clock.m1);
 795
 796                         if (m2 > INT_MAX/clock.m1)
 797                                 continue;
 798
 799                         clock.m2 = m2;
 800
 801                         chv_clock(refclk, &clock);
 802
 803                         if (!intel_PLL_is_valid(dev, limit, &clock))
 804                                 continue;
 805
 806                         /* based on hardware requirement, prefer bigger p
 807                          */
 808                         if (clock.p > best_clock->p) {
 809                                 *best_clock = clock;
 810                                 found = true;
 811                         }
 812                 }
 813         }
 814
 815         return found;
 816 }
 817
 818 bool intel_crtc_active(struct drm_crtc *crtc)
 819 {
 820         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 821
 822         /* Be paranoid as we can arrive here with only partial
 823          * state retrieved from the hardware during setup.
 824          *
 825          * We can ditch the adjusted_mode.crtc_clock check as soon
 826          * as Haswell has gained clock readout/fastboot support.
 827          *
 828          * We can ditch the crtc->primary->fb check as soon as we can
 829          * properly reconstruct framebuffers.
 830          */
 831         return intel_crtc->active && crtc->primary->fb &&
 832                 intel_crtc->config.adjusted_mode.crtc_clock;
 833 }
 834
 835 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 836                                              enum pipe pipe)
 837 {
 838         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 839         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 840
 841         return intel_crtc->config.cpu_transcoder;
 842 }
 843
 844 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
 845 {
 846         struct drm_i915_private *dev_priv = dev->dev_private;
 847         u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
 848
 849         frame = I915_READ(frame_reg);
 850
 851         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 852                 WARN(1, "vblank wait timed out\n");
 853 }
 854
 855 /**
 856  * intel_wait_for_vblank - wait for vblank on a given pipe
 857  * @dev: drm device
 858  * @pipe: pipe to wait for
 859  *
 860  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 861  * mode setting code.
 862  */
 863 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 864 {
 865         struct drm_i915_private *dev_priv = dev->dev_private;
 866         int pipestat_reg = PIPESTAT(pipe);
 867
 868         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 869                 g4x_wait_for_vblank(dev, pipe);
 870                 return;
 871         }
 872
 873         /* Clear existing vblank status. Note this will clear any other
 874          * sticky status fields as well.
 875          *
 876          * This races with i915_driver_irq_handler() with the result
 877          * that either function could miss a vblank event.  Here it is not
 878          * fatal, as we will either wait upon the next vblank interrupt or
 879          * timeout.  Generally speaking intel_wait_for_vblank() is only
 880          * called during modeset at which time the GPU should be idle and
 881          * should *not* be performing page flips and thus not waiting on
 882          * vblanks...
 883          * Currently, the result of us stealing a vblank from the irq
 884          * handler is that a single frame will be skipped during swapbuffers.
 885          */
 886         I915_WRITE(pipestat_reg,
 887                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 888
 889         /* Wait for vblank interrupt bit to set */
 890         if (wait_for(I915_READ(pipestat_reg) &
 891                      PIPE_VBLANK_INTERRUPT_STATUS,
 892                      50))
 893                 DRM_DEBUG_KMS("vblank wait timed out\n");
 894 }
 895
 896 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 897 {
 898         struct drm_i915_private *dev_priv = dev->dev_private;
 899         u32 reg = PIPEDSL(pipe);
 900         u32 line1, line2;
 901         u32 line_mask;
 902
 903         if (IS_GEN2(dev))
 904                 line_mask = DSL_LINEMASK_GEN2;
 905         else
 906                 line_mask = DSL_LINEMASK_GEN3;
 907
 908         line1 = I915_READ(reg) & line_mask;
 909         mdelay(5);
 910         line2 = I915_READ(reg) & line_mask;
 911
 912         return line1 == line2;
 913 }
 914
 915 /*
 916  * intel_wait_for_pipe_off - wait for pipe to turn off
 917  * @dev: drm device
 918  * @pipe: pipe to wait for
 919  *
 920  * After disabling a pipe, we can't wait for vblank in the usual way,
 921  * spinning on the vblank interrupt status bit, since we won't actually
 922  * see an interrupt when the pipe is disabled.
 923  *
 924  * On Gen4 and above:
 925  *   wait for the pipe register state bit to turn off
 926  *
 927  * Otherwise:
 928  *   wait for the display line value to settle (it usually
 929  *   ends up stopping at the start of the next frame).
 930  *
 931  */
 932 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 933 {
 934         struct drm_i915_private *dev_priv = dev->dev_private;
 935         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 936                                                                       pipe);
 937
 938         if (INTEL_INFO(dev)->gen >= 4) {
 939                 int reg = PIPECONF(cpu_transcoder);
 940
 941                 /* Wait for the Pipe State to go off */
 942                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 943                              100))
 944                         WARN(1, "pipe_off wait timed out\n");
 945         } else {
 946                 /* Wait for the display line to settle */
 947                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 948                         WARN(1, "pipe_off wait timed out\n");
 949         }
 950 }
 951
 952 /*
 953  * ibx_digital_port_connected - is the specified port connected?
 954  * @dev_priv: i915 private structure
 955  * @port: the port to test
 956  *
 957  * Returns true if @port is connected, false otherwise.
 958  */
 959 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 960                                 struct intel_digital_port *port)
 961 {
 962         u32 bit;
 963
 964         if (HAS_PCH_IBX(dev_priv->dev)) {
 965                 switch(port->port) {
 966                 case PORT_B:
 967                         bit = SDE_PORTB_HOTPLUG;
 968                         break;
 969                 case PORT_C:
 970                         bit = SDE_PORTC_HOTPLUG;
 971                         break;
 972                 case PORT_D:
 973                         bit = SDE_PORTD_HOTPLUG;
 974                         break;
 975                 default:
 976                         return true;
 977                 }
 978         } else {
 979                 switch(port->port) {
 980                 case PORT_B:
 981                         bit = SDE_PORTB_HOTPLUG_CPT;
 982                         break;
 983                 case PORT_C:
 984                         bit = SDE_PORTC_HOTPLUG_CPT;
 985                         break;
 986                 case PORT_D:
 987                         bit = SDE_PORTD_HOTPLUG_CPT;
 988                         break;
 989                 default:
 990                         return true;
 991                 }
 992         }
 993
 994         return I915_READ(SDEISR) & bit;
 995 }
 996
 997 static const char *state_string(bool enabled)
 998 {
 999         return enabled ? "on" : "off";
1000 }
1001
1002 /* Only for pre-ILK configs */
1003 void assert_pll(struct drm_i915_private *dev_priv,
1004                 enum pipe pipe, bool state)
1005 {
1006         int reg;
1007         u32 val;
1008         bool cur_state;
1009
1010         reg = DPLL(pipe);
1011         val = I915_READ(reg);
1012         cur_state = !!(val & DPLL_VCO_ENABLE);
1013         WARN(cur_state != state,
1014              "PLL state assertion failure (expected %s, current %s)\n",
1015              state_string(state), state_string(cur_state));
1016 }
1017
1018 /* XXX: the dsi pll is shared between MIPI DSI ports */
1019 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1020 {
1021         u32 val;
1022         bool cur_state;
1023
1024         mutex_lock(&dev_priv->dpio_lock);
1025         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1026         mutex_unlock(&dev_priv->dpio_lock);
1027
1028         cur_state = val & DSI_PLL_VCO_EN;
1029         WARN(cur_state != state,
1030              "DSI PLL state assertion failure (expected %s, current %s)\n",
1031              state_string(state), state_string(cur_state));
1032 }
1033 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1034 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1035
1036 struct intel_shared_dpll *
1037 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1038 {
1039         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1040
1041         if (crtc->config.shared_dpll < 0)
1042                 return NULL;
1043
1044         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1045 }
1046
1047 /* For ILK+ */
1048 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1049                         struct intel_shared_dpll *pll,
1050                         bool state)
1051 {
1052         bool cur_state;
1053         struct intel_dpll_hw_state hw_state;
1054
1055         if (HAS_PCH_LPT(dev_priv->dev)) {
1056                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1057                 return;
1058         }
1059
1060         if (WARN (!pll,
1061                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1062                 return;
1063
1064         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1065         WARN(cur_state != state,
1066              "%s assertion failure (expected %s, current %s)\n",
1067              pll->name, state_string(state), state_string(cur_state));
1068 }
1069
1070 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1071                           enum pipe pipe, bool state)
1072 {
1073         int reg;
1074         u32 val;
1075         bool cur_state;
1076         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1077                                                                       pipe);
1078
1079         if (HAS_DDI(dev_priv->dev)) {
1080                 /* DDI does not have a specific FDI_TX register */
1081                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1082                 val = I915_READ(reg);
1083                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1084         } else {
1085                 reg = FDI_TX_CTL(pipe);
1086                 val = I915_READ(reg);
1087                 cur_state = !!(val & FDI_TX_ENABLE);
1088         }
1089         WARN(cur_state != state,
1090              "FDI TX state assertion failure (expected %s, current %s)\n",
1091              state_string(state), state_string(cur_state));
1092 }
1093 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1094 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1095
1096 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1097                           enum pipe pipe, bool state)
1098 {
1099         int reg;
1100         u32 val;
1101         bool cur_state;
1102
1103         reg = FDI_RX_CTL(pipe);
1104         val = I915_READ(reg);
1105         cur_state = !!(val & FDI_RX_ENABLE);
1106         WARN(cur_state != state,
1107              "FDI RX state assertion failure (expected %s, current %s)\n",
1108              state_string(state), state_string(cur_state));
1109 }
1110 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1111 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1112
1113 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1114                                       enum pipe pipe)
1115 {
1116         int reg;
1117         u32 val;
1118
1119         /* ILK FDI PLL is always enabled */
1120         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1121                 return;
1122
1123         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1124         if (HAS_DDI(dev_priv->dev))
1125                 return;
1126
1127         reg = FDI_TX_CTL(pipe);
1128         val = I915_READ(reg);
1129         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1130 }
1131
1132 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1133                        enum pipe pipe, bool state)
1134 {
1135         int reg;
1136         u32 val;
1137         bool cur_state;
1138
1139         reg = FDI_RX_CTL(pipe);
1140         val = I915_READ(reg);
1141         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1142         WARN(cur_state != state,
1143              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1144              state_string(state), state_string(cur_state));
1145 }
1146
1147 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1148                                   enum pipe pipe)
1149 {
1150         int pp_reg, lvds_reg;
1151         u32 val;
1152         enum pipe panel_pipe = PIPE_A;
1153         bool locked = true;
1154
1155         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1156                 pp_reg = PCH_PP_CONTROL;
1157                 lvds_reg = PCH_LVDS;
1158         } else {
1159                 pp_reg = PP_CONTROL;
1160                 lvds_reg = LVDS;
1161         }
1162
1163         val = I915_READ(pp_reg);
1164         if (!(val & PANEL_POWER_ON) ||
1165             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1166                 locked = false;
1167
1168         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1169                 panel_pipe = PIPE_B;
1170
1171         WARN(panel_pipe == pipe && locked,
1172              "panel assertion failure, pipe %c regs locked\n",
1173              pipe_name(pipe));
1174 }
1175
1176 static void assert_cursor(struct drm_i915_private *dev_priv,
1177                           enum pipe pipe, bool state)
1178 {
1179         struct drm_device *dev = dev_priv->dev;
1180         bool cur_state;
1181
1182         if (IS_845G(dev) || IS_I865G(dev))
1183                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1184         else if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev))
1185                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1186         else
1187                 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1188
1189         WARN(cur_state != state,
1190              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1191              pipe_name(pipe), state_string(state), state_string(cur_state));
1192 }
1193 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1194 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1195
1196 void assert_pipe(struct drm_i915_private *dev_priv,
1197                  enum pipe pipe, bool state)
1198 {
1199         int reg;
1200         u32 val;
1201         bool cur_state;
1202         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1203                                                                       pipe);
1204
1205         /* if we need the pipe A quirk it must be always on */
1206         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1207                 state = true;
1208
1209         if (!intel_display_power_enabled(dev_priv,
1210                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1211                 cur_state = false;
1212         } else {
1213                 reg = PIPECONF(cpu_transcoder);
1214                 val = I915_READ(reg);
1215                 cur_state = !!(val & PIPECONF_ENABLE);
1216         }
1217
1218         WARN(cur_state != state,
1219              "pipe %c assertion failure (expected %s, current %s)\n",
1220              pipe_name(pipe), state_string(state), state_string(cur_state));
1221 }
1222
1223 static void assert_plane(struct drm_i915_private *dev_priv,
1224                          enum plane plane, bool state)
1225 {
1226         int reg;
1227         u32 val;
1228         bool cur_state;
1229
1230         reg = DSPCNTR(plane);
1231         val = I915_READ(reg);
1232         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1233         WARN(cur_state != state,
1234              "plane %c assertion failure (expected %s, current %s)\n",
1235              plane_name(plane), state_string(state), state_string(cur_state));
1236 }
1237
1238 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1239 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1240
1241 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1242                                    enum pipe pipe)
1243 {
1244         struct drm_device *dev = dev_priv->dev;
1245         int reg, i;
1246         u32 val;
1247         int cur_pipe;
1248
1249         /* Primary planes are fixed to pipes on gen4+ */
1250         if (INTEL_INFO(dev)->gen >= 4) {
1251                 reg = DSPCNTR(pipe);
1252                 val = I915_READ(reg);
1253                 WARN(val & DISPLAY_PLANE_ENABLE,
1254                      "plane %c assertion failure, should be disabled but not\n",
1255                      plane_name(pipe));
1256                 return;
1257         }
1258
1259         /* Need to check both planes against the pipe */
1260         for_each_pipe(i) {
1261                 reg = DSPCNTR(i);
1262                 val = I915_READ(reg);
1263                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1264                         DISPPLANE_SEL_PIPE_SHIFT;
1265                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1266                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1267                      plane_name(i), pipe_name(pipe));
1268         }
1269 }
1270
1271 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1272                                     enum pipe pipe)
1273 {
1274         struct drm_device *dev = dev_priv->dev;
1275         int reg, sprite;
1276         u32 val;
1277
1278         if (IS_VALLEYVIEW(dev)) {
1279                 for_each_sprite(pipe, sprite) {
1280                         reg = SPCNTR(pipe, sprite);
1281                         val = I915_READ(reg);
1282                         WARN(val & SP_ENABLE,
1283                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1284                              sprite_name(pipe, sprite), pipe_name(pipe));
1285                 }
1286         } else if (INTEL_INFO(dev)->gen >= 7) {
1287                 reg = SPRCTL(pipe);
1288                 val = I915_READ(reg);
1289                 WARN(val & SPRITE_ENABLE,
1290                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1291                      plane_name(pipe), pipe_name(pipe));
1292         } else if (INTEL_INFO(dev)->gen >= 5) {
1293                 reg = DVSCNTR(pipe);
1294                 val = I915_READ(reg);
1295                 WARN(val & DVS_ENABLE,
1296                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1297                      plane_name(pipe), pipe_name(pipe));
1298         }
1299 }
1300
1301 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1302 {
1303         u32 val;
1304         bool enabled;
1305
1306         WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1307
1308         val = I915_READ(PCH_DREF_CONTROL);
1309         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1310                             DREF_SUPERSPREAD_SOURCE_MASK));
1311         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1312 }
1313
1314 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1315                                            enum pipe pipe)
1316 {
1317         int reg;
1318         u32 val;
1319         bool enabled;
1320
1321         reg = PCH_TRANSCONF(pipe);
1322         val = I915_READ(reg);
1323         enabled = !!(val & TRANS_ENABLE);
1324         WARN(enabled,
1325              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1326              pipe_name(pipe));
1327 }
1328
1329 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1330                             enum pipe pipe, u32 port_sel, u32 val)
1331 {
1332         if ((val & DP_PORT_EN) == 0)
1333                 return false;
1334
1335         if (HAS_PCH_CPT(dev_priv->dev)) {
1336                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1337                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1338                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1339                         return false;
1340         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1341                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1342                         return false;
1343         } else {
1344                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1345                         return false;
1346         }
1347         return true;
1348 }
1349
1350 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1351                               enum pipe pipe, u32 val)
1352 {
1353         if ((val & SDVO_ENABLE) == 0)
1354                 return false;
1355
1356         if (HAS_PCH_CPT(dev_priv->dev)) {
1357                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1358                         return false;
1359         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1360                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1361                         return false;
1362         } else {
1363                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1364                         return false;
1365         }
1366         return true;
1367 }
1368
1369 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1370                               enum pipe pipe, u32 val)
1371 {
1372         if ((val & LVDS_PORT_EN) == 0)
1373                 return false;
1374
1375         if (HAS_PCH_CPT(dev_priv->dev)) {
1376                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1377                         return false;
1378         } else {
1379                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1380                         return false;
1381         }
1382         return true;
1383 }
1384
1385 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1386                               enum pipe pipe, u32 val)
1387 {
1388         if ((val & ADPA_DAC_ENABLE) == 0)
1389                 return false;
1390         if (HAS_PCH_CPT(dev_priv->dev)) {
1391                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1392                         return false;
1393         } else {
1394                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1395                         return false;
1396         }
1397         return true;
1398 }
1399
1400 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1401                                    enum pipe pipe, int reg, u32 port_sel)
1402 {
1403         u32 val = I915_READ(reg);
1404         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1405              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1406              reg, pipe_name(pipe));
1407
1408         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1409              && (val & DP_PIPEB_SELECT),
1410              "IBX PCH dp port still using transcoder B\n");
1411 }
1412
1413 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1414                                      enum pipe pipe, int reg)
1415 {
1416         u32 val = I915_READ(reg);
1417         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1418              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1419              reg, pipe_name(pipe));
1420
1421         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1422              && (val & SDVO_PIPE_B_SELECT),
1423              "IBX PCH hdmi port still using transcoder B\n");
1424 }
1425
1426 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1427                                       enum pipe pipe)
1428 {
1429         int reg;
1430         u32 val;
1431
1432         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1433         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1434         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1435
1436         reg = PCH_ADPA;
1437         val = I915_READ(reg);
1438         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1439              "PCH VGA enabled on transcoder %c, should be disabled\n",
1440              pipe_name(pipe));
1441
1442         reg = PCH_LVDS;
1443         val = I915_READ(reg);
1444         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1445              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1446              pipe_name(pipe));
1447
1448         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1449         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1450         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1451 }
1452
1453 static void intel_init_dpio(struct drm_device *dev)
1454 {
1455         struct drm_i915_private *dev_priv = dev->dev_private;
1456
1457         if (!IS_VALLEYVIEW(dev))
1458                 return;
1459
1460         /*
1461          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1462          * CHV x1 PHY (DP/HDMI D)
1463          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1464          */
1465         if (IS_CHERRYVIEW(dev)) {
1466                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1467                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1468         } else {
1469                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1470         }
1471 }
1472
1473 static void intel_reset_dpio(struct drm_device *dev)
1474 {
1475         struct drm_i915_private *dev_priv = dev->dev_private;
1476
1477         if (!IS_VALLEYVIEW(dev))
1478                 return;
1479
1480         /*
1481          * Enable the CRI clock source so we can get at the display and the
1482          * reference clock for VGA hotplug / manual detection.
1483          */
1484         I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
1485                    DPLL_REFA_CLK_ENABLE_VLV |
1486                    DPLL_INTEGRATED_CRI_CLK_VLV);
1487
1488         if (IS_CHERRYVIEW(dev)) {
1489                 enum dpio_phy phy;
1490                 u32 val;
1491
1492                 for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) {
1493                         /* Poll for phypwrgood signal */
1494                         if (wait_for(I915_READ(DISPLAY_PHY_STATUS) &
1495                                                 PHY_POWERGOOD(phy), 1))
1496                                 DRM_ERROR("Display PHY %d is not power up\n", phy);
1497
1498                         /*
1499                          * Deassert common lane reset for PHY.
1500                          *
1501                          * This should only be done on init and resume from S3
1502                          * with both PLLs disabled, or we risk losing DPIO and
1503                          * PLL synchronization.
1504                          */
1505                         val = I915_READ(DISPLAY_PHY_CONTROL);
1506                         I915_WRITE(DISPLAY_PHY_CONTROL,
1507                                 PHY_COM_LANE_RESET_DEASSERT(phy, val));
1508                 }
1509
1510         } else {
1511                 /*
1512                  * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1513                  *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1514                  *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1515                  *   b. The other bits such as sfr settings / modesel may all
1516                  *      be set to 0.
1517                  *
1518                  * This should only be done on init and resume from S3 with
1519                  * both PLLs disabled, or we risk losing DPIO and PLL
1520                  * synchronization.
1521                  */
1522                 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1523         }
1524 }
1525
1526 static void vlv_enable_pll(struct intel_crtc *crtc)
1527 {
1528         struct drm_device *dev = crtc->base.dev;
1529         struct drm_i915_private *dev_priv = dev->dev_private;
1530         int reg = DPLL(crtc->pipe);
1531         u32 dpll = crtc->config.dpll_hw_state.dpll;
1532
1533         assert_pipe_disabled(dev_priv, crtc->pipe);
1534
1535         /* No really, not for ILK+ */
1536         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1537
1538         /* PLL is protected by panel, make sure we can write it */
1539         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1540                 assert_panel_unlocked(dev_priv, crtc->pipe);
1541
1542         I915_WRITE(reg, dpll);
1543         POSTING_READ(reg);
1544         udelay(150);
1545
1546         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1547                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1548
1549         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1550         POSTING_READ(DPLL_MD(crtc->pipe));
1551
1552         /* We do this three times for luck */
1553         I915_WRITE(reg, dpll);
1554         POSTING_READ(reg);
1555         udelay(150); /* wait for warmup */
1556         I915_WRITE(reg, dpll);
1557         POSTING_READ(reg);
1558         udelay(150); /* wait for warmup */
1559         I915_WRITE(reg, dpll);
1560         POSTING_READ(reg);
1561         udelay(150); /* wait for warmup */
1562 }
1563
1564 static void chv_enable_pll(struct intel_crtc *crtc)
1565 {
1566         struct drm_device *dev = crtc->base.dev;
1567         struct drm_i915_private *dev_priv = dev->dev_private;
1568         int pipe = crtc->pipe;
1569         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1570         int dpll = DPLL(crtc->pipe);
1571         u32 tmp;
1572
1573         assert_pipe_disabled(dev_priv, crtc->pipe);
1574
1575         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1576
1577         mutex_lock(&dev_priv->dpio_lock);
1578
1579         /* Enable back the 10bit clock to display controller */
1580         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1581         tmp |= DPIO_DCLKP_EN;
1582         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1583
1584         /*
1585          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1586          */
1587         udelay(1);
1588
1589         /* Enable PLL */
1590         tmp = I915_READ(dpll);
1591         tmp |= DPLL_VCO_ENABLE;
1592         I915_WRITE(dpll, tmp);
1593
1594         /* Check PLL is locked */
1595         if (wait_for(((I915_READ(dpll) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1596                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1597
1598         /* Deassert soft data lane reset*/
1599         tmp = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(port));
1600         tmp |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1601         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), tmp);
1602
1603
1604         mutex_unlock(&dev_priv->dpio_lock);
1605 }
1606
1607 static void i9xx_enable_pll(struct intel_crtc *crtc)
1608 {
1609         struct drm_device *dev = crtc->base.dev;
1610         struct drm_i915_private *dev_priv = dev->dev_private;
1611         int reg = DPLL(crtc->pipe);
1612         u32 dpll = crtc->config.dpll_hw_state.dpll;
1613
1614         assert_pipe_disabled(dev_priv, crtc->pipe);
1615
1616         /* No really, not for ILK+ */
1617         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1618
1619         /* PLL is protected by panel, make sure we can write it */
1620         if (IS_MOBILE(dev) && !IS_I830(dev))
1621                 assert_panel_unlocked(dev_priv, crtc->pipe);
1622
1623         I915_WRITE(reg, dpll);
1624
1625         /* Wait for the clocks to stabilize. */
1626         POSTING_READ(reg);
1627         udelay(150);
1628
1629         if (INTEL_INFO(dev)->gen >= 4) {
1630                 I915_WRITE(DPLL_MD(crtc->pipe),
1631                            crtc->config.dpll_hw_state.dpll_md);
1632         } else {
1633                 /* The pixel multiplier can only be updated once the
1634                  * DPLL is enabled and the clocks are stable.
1635                  *
1636                  * So write it again.
1637                  */
1638                 I915_WRITE(reg, dpll);
1639         }
1640
1641         /* We do this three times for luck */
1642         I915_WRITE(reg, dpll);
1643         POSTING_READ(reg);
1644         udelay(150); /* wait for warmup */
1645         I915_WRITE(reg, dpll);
1646         POSTING_READ(reg);
1647         udelay(150); /* wait for warmup */
1648         I915_WRITE(reg, dpll);
1649         POSTING_READ(reg);
1650         udelay(150); /* wait for warmup */
1651 }
1652
1653 /**
1654  * i9xx_disable_pll - disable a PLL
1655  * @dev_priv: i915 private structure
1656  * @pipe: pipe PLL to disable
1657  *
1658  * Disable the PLL for @pipe, making sure the pipe is off first.
1659  *
1660  * Note!  This is for pre-ILK only.
1661  */
1662 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1663 {
1664         /* Don't disable pipe A or pipe A PLLs if needed */
1665         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1666                 return;
1667
1668         /* Make sure the pipe isn't still relying on us */
1669         assert_pipe_disabled(dev_priv, pipe);
1670
1671         I915_WRITE(DPLL(pipe), 0);
1672         POSTING_READ(DPLL(pipe));
1673 }
1674
1675 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1676 {
1677         u32 val = 0;
1678
1679         /* Make sure the pipe isn't still relying on us */
1680         assert_pipe_disabled(dev_priv, pipe);
1681
1682         /*
1683          * Leave integrated clock source and reference clock enabled for pipe B.
1684          * The latter is needed for VGA hotplug / manual detection.
1685          */
1686         if (pipe == PIPE_B)
1687                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1688         I915_WRITE(DPLL(pipe), val);
1689         POSTING_READ(DPLL(pipe));
1690
1691 }
1692
1693 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1694 {
1695         int dpll = DPLL(pipe);
1696         u32 val;
1697
1698         /* Set PLL en = 0 */
1699         val = I915_READ(dpll);
1700         val &= ~DPLL_VCO_ENABLE;
1701         I915_WRITE(dpll, val);
1702
1703 }
1704
1705 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1706                 struct intel_digital_port *dport)
1707 {
1708         u32 port_mask;
1709         int dpll_reg;
1710
1711         switch (dport->port) {
1712         case PORT_B:
1713                 port_mask = DPLL_PORTB_READY_MASK;
1714                 dpll_reg = DPLL(0);
1715                 break;
1716         case PORT_C:
1717                 port_mask = DPLL_PORTC_READY_MASK;
1718                 dpll_reg = DPLL(0);
1719                 break;
1720         case PORT_D:
1721                 port_mask = DPLL_PORTD_READY_MASK;
1722                 dpll_reg = DPIO_PHY_STATUS;
1723                 break;
1724         default:
1725                 BUG();
1726         }
1727
1728         if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1729                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1730                      port_name(dport->port), I915_READ(dpll_reg));
1731 }
1732
1733 /**
1734  * ironlake_enable_shared_dpll - enable PCH PLL
1735  * @dev_priv: i915 private structure
1736  * @pipe: pipe PLL to enable
1737  *
1738  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1739  * drives the transcoder clock.
1740  */
1741 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1742 {
1743         struct drm_device *dev = crtc->base.dev;
1744         struct drm_i915_private *dev_priv = dev->dev_private;
1745         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1746
1747         /* PCH PLLs only available on ILK, SNB and IVB */
1748         BUG_ON(INTEL_INFO(dev)->gen < 5);
1749         if (WARN_ON(pll == NULL))
1750                 return;
1751
1752         if (WARN_ON(pll->refcount == 0))
1753                 return;
1754
1755         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1756                       pll->name, pll->active, pll->on,
1757                       crtc->base.base.id);
1758
1759         if (pll->active++) {
1760                 WARN_ON(!pll->on);
1761                 assert_shared_dpll_enabled(dev_priv, pll);
1762                 return;
1763         }
1764         WARN_ON(pll->on);
1765
1766         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1767         pll->enable(dev_priv, pll);
1768         pll->on = true;
1769 }
1770
1771 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1772 {
1773         struct drm_device *dev = crtc->base.dev;
1774         struct drm_i915_private *dev_priv = dev->dev_private;
1775         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1776
1777         /* PCH only available on ILK+ */
1778         BUG_ON(INTEL_INFO(dev)->gen < 5);
1779         if (WARN_ON(pll == NULL))
1780                return;
1781
1782         if (WARN_ON(pll->refcount == 0))
1783                 return;
1784
1785         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1786                       pll->name, pll->active, pll->on,
1787                       crtc->base.base.id);
1788
1789         if (WARN_ON(pll->active == 0)) {
1790                 assert_shared_dpll_disabled(dev_priv, pll);
1791                 return;
1792         }
1793
1794         assert_shared_dpll_enabled(dev_priv, pll);
1795         WARN_ON(!pll->on);
1796         if (--pll->active)
1797                 return;
1798
1799         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1800         pll->disable(dev_priv, pll);
1801         pll->on = false;
1802 }
1803
1804 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1805                                            enum pipe pipe)
1806 {
1807         struct drm_device *dev = dev_priv->dev;
1808         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1809         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1810         uint32_t reg, val, pipeconf_val;
1811
1812         /* PCH only available on ILK+ */
1813         BUG_ON(INTEL_INFO(dev)->gen < 5);
1814
1815         /* Make sure PCH DPLL is enabled */
1816         assert_shared_dpll_enabled(dev_priv,
1817                                    intel_crtc_to_shared_dpll(intel_crtc));
1818
1819         /* FDI must be feeding us bits for PCH ports */
1820         assert_fdi_tx_enabled(dev_priv, pipe);
1821         assert_fdi_rx_enabled(dev_priv, pipe);
1822
1823         if (HAS_PCH_CPT(dev)) {
1824                 /* Workaround: Set the timing override bit before enabling the
1825                  * pch transcoder. */
1826                 reg = TRANS_CHICKEN2(pipe);
1827                 val = I915_READ(reg);
1828                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1829                 I915_WRITE(reg, val);
1830         }
1831
1832         reg = PCH_TRANSCONF(pipe);
1833         val = I915_READ(reg);
1834         pipeconf_val = I915_READ(PIPECONF(pipe));
1835
1836         if (HAS_PCH_IBX(dev_priv->dev)) {
1837                 /*
1838                  * make the BPC in transcoder be consistent with
1839                  * that in pipeconf reg.
1840                  */
1841                 val &= ~PIPECONF_BPC_MASK;
1842                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1843         }
1844
1845         val &= ~TRANS_INTERLACE_MASK;
1846         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1847                 if (HAS_PCH_IBX(dev_priv->dev) &&
1848                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1849                         val |= TRANS_LEGACY_INTERLACED_ILK;
1850                 else
1851                         val |= TRANS_INTERLACED;
1852         else
1853                 val |= TRANS_PROGRESSIVE;
1854
1855         I915_WRITE(reg, val | TRANS_ENABLE);
1856         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1857                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1858 }
1859
1860 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1861                                       enum transcoder cpu_transcoder)
1862 {
1863         u32 val, pipeconf_val;
1864
1865         /* PCH only available on ILK+ */
1866         BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1867
1868         /* FDI must be feeding us bits for PCH ports */
1869         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1870         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1871
1872         /* Workaround: set timing override bit. */
1873         val = I915_READ(_TRANSA_CHICKEN2);
1874         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1875         I915_WRITE(_TRANSA_CHICKEN2, val);
1876
1877         val = TRANS_ENABLE;
1878         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1879
1880         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1881             PIPECONF_INTERLACED_ILK)
1882                 val |= TRANS_INTERLACED;
1883         else
1884                 val |= TRANS_PROGRESSIVE;
1885
1886         I915_WRITE(LPT_TRANSCONF, val);
1887         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1888                 DRM_ERROR("Failed to enable PCH transcoder\n");
1889 }
1890
1891 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1892                                             enum pipe pipe)
1893 {
1894         struct drm_device *dev = dev_priv->dev;
1895         uint32_t reg, val;
1896
1897         /* FDI relies on the transcoder */
1898         assert_fdi_tx_disabled(dev_priv, pipe);
1899         assert_fdi_rx_disabled(dev_priv, pipe);
1900
1901         /* Ports must be off as well */
1902         assert_pch_ports_disabled(dev_priv, pipe);
1903
1904         reg = PCH_TRANSCONF(pipe);
1905         val = I915_READ(reg);
1906         val &= ~TRANS_ENABLE;
1907         I915_WRITE(reg, val);
1908         /* wait for PCH transcoder off, transcoder state */
1909         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1910                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1911
1912         if (!HAS_PCH_IBX(dev)) {
1913                 /* Workaround: Clear the timing override chicken bit again. */
1914                 reg = TRANS_CHICKEN2(pipe);
1915                 val = I915_READ(reg);
1916                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1917                 I915_WRITE(reg, val);
1918         }
1919 }
1920
1921 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1922 {
1923         u32 val;
1924
1925         val = I915_READ(LPT_TRANSCONF);
1926         val &= ~TRANS_ENABLE;
1927         I915_WRITE(LPT_TRANSCONF, val);
1928         /* wait for PCH transcoder off, transcoder state */
1929         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1930                 DRM_ERROR("Failed to disable PCH transcoder\n");
1931
1932         /* Workaround: clear timing override bit. */
1933         val = I915_READ(_TRANSA_CHICKEN2);
1934         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1935         I915_WRITE(_TRANSA_CHICKEN2, val);
1936 }
1937
1938 /**
1939  * intel_enable_pipe - enable a pipe, asserting requirements
1940  * @crtc: crtc responsible for the pipe
1941  *
1942  * Enable @crtc's pipe, making sure that various hardware specific requirements
1943  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1944  */
1945 static void intel_enable_pipe(struct intel_crtc *crtc)
1946 {
1947         struct drm_device *dev = crtc->base.dev;
1948         struct drm_i915_private *dev_priv = dev->dev_private;
1949         enum pipe pipe = crtc->pipe;
1950         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1951                                                                       pipe);
1952         enum pipe pch_transcoder;
1953         int reg;
1954         u32 val;
1955
1956         assert_planes_disabled(dev_priv, pipe);
1957         assert_cursor_disabled(dev_priv, pipe);
1958         assert_sprites_disabled(dev_priv, pipe);
1959
1960         if (HAS_PCH_LPT(dev_priv->dev))
1961                 pch_transcoder = TRANSCODER_A;
1962         else
1963                 pch_transcoder = pipe;
1964
1965         /*
1966          * A pipe without a PLL won't actually be able to drive bits from
1967          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1968          * need the check.
1969          */
1970         if (!HAS_PCH_SPLIT(dev_priv->dev))
1971                 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
1972                         assert_dsi_pll_enabled(dev_priv);
1973                 else
1974                         assert_pll_enabled(dev_priv, pipe);
1975         else {
1976                 if (crtc->config.has_pch_encoder) {
1977                         /* if driving the PCH, we need FDI enabled */
1978                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1979                         assert_fdi_tx_pll_enabled(dev_priv,
1980                                                   (enum pipe) cpu_transcoder);
1981                 }
1982                 /* FIXME: assert CPU port conditions for SNB+ */
1983         }
1984
1985         reg = PIPECONF(cpu_transcoder);
1986         val = I915_READ(reg);
1987         if (val & PIPECONF_ENABLE) {
1988                 WARN_ON(!(pipe == PIPE_A &&
1989                           dev_priv->quirks & QUIRK_PIPEA_FORCE));
1990                 return;
1991         }
1992
1993         I915_WRITE(reg, val | PIPECONF_ENABLE);
1994         POSTING_READ(reg);
1995 }
1996
1997 /**
1998  * intel_disable_pipe - disable a pipe, asserting requirements
1999  * @dev_priv: i915 private structure
2000  * @pipe: pipe to disable
2001  *
2002  * Disable @pipe, making sure that various hardware specific requirements
2003  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
2004  *
2005  * @pipe should be %PIPE_A or %PIPE_B.
2006  *
2007  * Will wait until the pipe has shut down before returning.
2008  */
2009 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
2010                                enum pipe pipe)
2011 {
2012         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2013                                                                       pipe);
2014         int reg;
2015         u32 val;
2016
2017         /*
2018          * Make sure planes won't keep trying to pump pixels to us,
2019          * or we might hang the display.
2020          */
2021         assert_planes_disabled(dev_priv, pipe);
2022         assert_cursor_disabled(dev_priv, pipe);
2023         assert_sprites_disabled(dev_priv, pipe);
2024
2025         /* Don't disable pipe A or pipe A PLLs if needed */
2026         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2027                 return;
2028
2029         reg = PIPECONF(cpu_transcoder);
2030         val = I915_READ(reg);
2031         if ((val & PIPECONF_ENABLE) == 0)
2032                 return;
2033
2034         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
2035         intel_wait_for_pipe_off(dev_priv->dev, pipe);
2036 }
2037
2038 /*
2039  * Plane regs are double buffered, going from enabled->disabled needs a
2040  * trigger in order to latch.  The display address reg provides this.
2041  */
2042 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2043                                enum plane plane)
2044 {
2045         struct drm_device *dev = dev_priv->dev;
2046         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2047
2048         I915_WRITE(reg, I915_READ(reg));
2049         POSTING_READ(reg);
2050 }
2051
2052 /**
2053  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2054  * @dev_priv: i915 private structure
2055  * @plane: plane to enable
2056  * @pipe: pipe being fed
2057  *
2058  * Enable @plane on @pipe, making sure that @pipe is running first.
2059  */
2060 static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
2061                                           enum plane plane, enum pipe pipe)
2062 {
2063         struct intel_crtc *intel_crtc =
2064                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2065         int reg;
2066         u32 val;
2067
2068         /* If the pipe isn't enabled, we can't pump pixels and may hang */
2069         assert_pipe_enabled(dev_priv, pipe);
2070
2071         if (intel_crtc->primary_enabled)
2072                 return;
2073
2074         intel_crtc->primary_enabled = true;
2075
2076         reg = DSPCNTR(plane);
2077         val = I915_READ(reg);
2078         WARN_ON(val & DISPLAY_PLANE_ENABLE);
2079
2080         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
2081         intel_flush_primary_plane(dev_priv, plane);
2082         intel_wait_for_vblank(dev_priv->dev, pipe);
2083 }
2084
2085 /**
2086  * intel_disable_primary_hw_plane - disable the primary hardware plane
2087  * @dev_priv: i915 private structure
2088  * @plane: plane to disable
2089  * @pipe: pipe consuming the data
2090  *
2091  * Disable @plane; should be an independent operation.
2092  */
2093 static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
2094                                            enum plane plane, enum pipe pipe)
2095 {
2096         struct intel_crtc *intel_crtc =
2097                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2098         int reg;
2099         u32 val;
2100
2101         if (!intel_crtc->primary_enabled)
2102                 return;
2103
2104         intel_crtc->primary_enabled = false;
2105
2106         reg = DSPCNTR(plane);
2107         val = I915_READ(reg);
2108         WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0);
2109
2110         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
2111         intel_flush_primary_plane(dev_priv, plane);
2112         intel_wait_for_vblank(dev_priv->dev, pipe);
2113 }
2114
2115 static bool need_vtd_wa(struct drm_device *dev)
2116 {
2117 #ifdef CONFIG_INTEL_IOMMU
2118         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2119                 return true;
2120 #endif
2121         return false;
2122 }
2123
2124 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2125 {
2126         int tile_height;
2127
2128         tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2129         return ALIGN(height, tile_height);
2130 }
2131
2132 int
2133 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2134                            struct drm_i915_gem_object *obj,
2135                            struct intel_ring_buffer *pipelined)
2136 {
2137         struct drm_i915_private *dev_priv = dev->dev_private;
2138         u32 alignment;
2139         int ret;
2140
2141         switch (obj->tiling_mode) {
2142         case I915_TILING_NONE:
2143                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2144                         alignment = 128 * 1024;
2145                 else if (INTEL_INFO(dev)->gen >= 4)
2146                         alignment = 4 * 1024;
2147                 else
2148                         alignment = 64 * 1024;
2149                 break;
2150         case I915_TILING_X:
2151                 /* pin() will align the object as required by fence */
2152                 alignment = 0;
2153                 break;
2154         case I915_TILING_Y:
2155                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2156                 return -EINVAL;
2157         default:
2158                 BUG();
2159         }
2160
2161         /* Note that the w/a also requires 64 PTE of padding following the
2162          * bo. We currently fill all unused PTE with the shadow page and so
2163          * we should always have valid PTE following the scanout preventing
2164          * the VT-d warning.
2165          */
2166         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2167                 alignment = 256 * 1024;
2168
2169         dev_priv->mm.interruptible = false;
2170         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2171         if (ret)
2172                 goto err_interruptible;
2173
2174         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2175          * fence, whereas 965+ only requires a fence if using
2176          * framebuffer compression.  For simplicity, we always install
2177          * a fence as the cost is not that onerous.
2178          */
2179         ret = i915_gem_object_get_fence(obj);
2180         if (ret)
2181                 goto err_unpin;
2182
2183         i915_gem_object_pin_fence(obj);
2184
2185         dev_priv->mm.interruptible = true;
2186         return 0;
2187
2188 err_unpin:
2189         i915_gem_object_unpin_from_display_plane(obj);
2190 err_interruptible:
2191         dev_priv->mm.interruptible = true;
2192         return ret;
2193 }
2194
2195 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2196 {
2197         i915_gem_object_unpin_fence(obj);
2198         i915_gem_object_unpin_from_display_plane(obj);
2199 }
2200
2201 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2202  * is assumed to be a power-of-two. */
2203 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2204                                              unsigned int tiling_mode,
2205                                              unsigned int cpp,
2206                                              unsigned int pitch)
2207 {
2208         if (tiling_mode != I915_TILING_NONE) {
2209                 unsigned int tile_rows, tiles;
2210
2211                 tile_rows = *y / 8;
2212                 *y %= 8;
2213
2214                 tiles = *x / (512/cpp);
2215                 *x %= 512/cpp;
2216
2217                 return tile_rows * pitch * 8 + tiles * 4096;
2218         } else {
2219                 unsigned int offset;
2220
2221                 offset = *y * pitch + *x * cpp;
2222                 *y = 0;
2223                 *x = (offset & 4095) / cpp;
2224                 return offset & -4096;
2225         }
2226 }
2227
2228 int intel_format_to_fourcc(int format)
2229 {
2230         switch (format) {
2231         case DISPPLANE_8BPP:
2232                 return DRM_FORMAT_C8;
2233         case DISPPLANE_BGRX555:
2234                 return DRM_FORMAT_XRGB1555;
2235         case DISPPLANE_BGRX565:
2236                 return DRM_FORMAT_RGB565;
2237         default:
2238         case DISPPLANE_BGRX888:
2239                 return DRM_FORMAT_XRGB8888;
2240         case DISPPLANE_RGBX888:
2241                 return DRM_FORMAT_XBGR8888;
2242         case DISPPLANE_BGRX101010:
2243                 return DRM_FORMAT_XRGB2101010;
2244         case DISPPLANE_RGBX101010:
2245                 return DRM_FORMAT_XBGR2101010;
2246         }
2247 }
2248
2249 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2250                                   struct intel_plane_config *plane_config)
2251 {
2252         struct drm_device *dev = crtc->base.dev;
2253         struct drm_i915_gem_object *obj = NULL;
2254         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2255         u32 base = plane_config->base;
2256
2257         if (plane_config->size == 0)
2258                 return false;
2259
2260         obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2261                                                              plane_config->size);
2262         if (!obj)
2263                 return false;
2264
2265         if (plane_config->tiled) {
2266                 obj->tiling_mode = I915_TILING_X;
2267                 obj->stride = crtc->base.primary->fb->pitches[0];
2268         }
2269
2270         mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2271         mode_cmd.width = crtc->base.primary->fb->width;
2272         mode_cmd.height = crtc->base.primary->fb->height;
2273         mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2274
2275         mutex_lock(&dev->struct_mutex);
2276
2277         if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2278                                    &mode_cmd, obj)) {
2279                 DRM_DEBUG_KMS("intel fb init failed\n");
2280                 goto out_unref_obj;
2281         }
2282
2283         mutex_unlock(&dev->struct_mutex);
2284
2285         DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2286         return true;
2287
2288 out_unref_obj:
2289         drm_gem_object_unreference(&obj->base);
2290         mutex_unlock(&dev->struct_mutex);
2291         return false;
2292 }
2293
2294 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2295                                  struct intel_plane_config *plane_config)
2296 {
2297         struct drm_device *dev = intel_crtc->base.dev;
2298         struct drm_crtc *c;
2299         struct intel_crtc *i;
2300         struct intel_framebuffer *fb;
2301
2302         if (!intel_crtc->base.primary->fb)
2303                 return;
2304
2305         if (intel_alloc_plane_obj(intel_crtc, plane_config))
2306                 return;
2307
2308         kfree(intel_crtc->base.primary->fb);
2309         intel_crtc->base.primary->fb = NULL;
2310
2311         /*
2312          * Failed to alloc the obj, check to see if we should share
2313          * an fb with another CRTC instead
2314          */
2315         for_each_crtc(dev, c) {
2316                 i = to_intel_crtc(c);
2317
2318                 if (c == &intel_crtc->base)
2319                         continue;
2320
2321                 if (!i->active || !c->primary->fb)
2322                         continue;
2323
2324                 fb = to_intel_framebuffer(c->primary->fb);
2325                 if (i915_gem_obj_ggtt_offset(fb->obj) == plane_config->base) {
2326                         drm_framebuffer_reference(c->primary->fb);
2327                         intel_crtc->base.primary->fb = c->primary->fb;
2328                         break;
2329                 }
2330         }
2331 }
2332
2333 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2334                                       struct drm_framebuffer *fb,
2335                                       int x, int y)
2336 {
2337         struct drm_device *dev = crtc->dev;
2338         struct drm_i915_private *dev_priv = dev->dev_private;
2339         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2340         struct intel_framebuffer *intel_fb;
2341         struct drm_i915_gem_object *obj;
2342         int plane = intel_crtc->plane;
2343         unsigned long linear_offset;
2344         u32 dspcntr;
2345         u32 reg;
2346
2347         intel_fb = to_intel_framebuffer(fb);
2348         obj = intel_fb->obj;
2349
2350         reg = DSPCNTR(plane);
2351         dspcntr = I915_READ(reg);
2352         /* Mask out pixel format bits in case we change it */
2353         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2354         switch (fb->pixel_format) {
2355         case DRM_FORMAT_C8:
2356                 dspcntr |= DISPPLANE_8BPP;
2357                 break;
2358         case DRM_FORMAT_XRGB1555:
2359         case DRM_FORMAT_ARGB1555:
2360                 dspcntr |= DISPPLANE_BGRX555;
2361                 break;
2362         case DRM_FORMAT_RGB565:
2363                 dspcntr |= DISPPLANE_BGRX565;
2364                 break;
2365         case DRM_FORMAT_XRGB8888:
2366         case DRM_FORMAT_ARGB8888:
2367                 dspcntr |= DISPPLANE_BGRX888;
2368                 break;
2369         case DRM_FORMAT_XBGR8888:
2370         case DRM_FORMAT_ABGR8888:
2371                 dspcntr |= DISPPLANE_RGBX888;
2372                 break;
2373         case DRM_FORMAT_XRGB2101010:
2374         case DRM_FORMAT_ARGB2101010:
2375                 dspcntr |= DISPPLANE_BGRX101010;
2376                 break;
2377         case DRM_FORMAT_XBGR2101010:
2378         case DRM_FORMAT_ABGR2101010:
2379                 dspcntr |= DISPPLANE_RGBX101010;
2380                 break;
2381         default:
2382                 BUG();
2383         }
2384
2385         if (INTEL_INFO(dev)->gen >= 4) {
2386                 if (obj->tiling_mode != I915_TILING_NONE)
2387                         dspcntr |= DISPPLANE_TILED;
2388                 else
2389                         dspcntr &= ~DISPPLANE_TILED;
2390         }
2391
2392         if (IS_G4X(dev))
2393                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2394
2395         I915_WRITE(reg, dspcntr);
2396
2397         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2398
2399         if (INTEL_INFO(dev)->gen >= 4) {
2400                 intel_crtc->dspaddr_offset =
2401                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2402                                                        fb->bits_per_pixel / 8,
2403                                                        fb->pitches[0]);
2404                 linear_offset -= intel_crtc->dspaddr_offset;
2405         } else {
2406                 intel_crtc->dspaddr_offset = linear_offset;
2407         }
2408
2409         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2410                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2411                       fb->pitches[0]);
2412         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2413         if (INTEL_INFO(dev)->gen >= 4) {
2414                 I915_WRITE(DSPSURF(plane),
2415                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2416                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2417                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2418         } else
2419                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2420         POSTING_READ(reg);
2421 }
2422
2423 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2424                                           struct drm_framebuffer *fb,
2425                                           int x, int y)
2426 {
2427         struct drm_device *dev = crtc->dev;
2428         struct drm_i915_private *dev_priv = dev->dev_private;
2429         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2430         struct intel_framebuffer *intel_fb;
2431         struct drm_i915_gem_object *obj;
2432         int plane = intel_crtc->plane;
2433         unsigned long linear_offset;
2434         u32 dspcntr;
2435         u32 reg;
2436
2437         intel_fb = to_intel_framebuffer(fb);
2438         obj = intel_fb->obj;
2439
2440         reg = DSPCNTR(plane);
2441         dspcntr = I915_READ(reg);
2442         /* Mask out pixel format bits in case we change it */
2443         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2444         switch (fb->pixel_format) {
2445         case DRM_FORMAT_C8:
2446                 dspcntr |= DISPPLANE_8BPP;
2447                 break;
2448         case DRM_FORMAT_RGB565:
2449                 dspcntr |= DISPPLANE_BGRX565;
2450                 break;
2451         case DRM_FORMAT_XRGB8888:
2452         case DRM_FORMAT_ARGB8888:
2453                 dspcntr |= DISPPLANE_BGRX888;
2454                 break;
2455         case DRM_FORMAT_XBGR8888:
2456         case DRM_FORMAT_ABGR8888:
2457                 dspcntr |= DISPPLANE_RGBX888;
2458                 break;
2459         case DRM_FORMAT_XRGB2101010:
2460         case DRM_FORMAT_ARGB2101010:
2461                 dspcntr |= DISPPLANE_BGRX101010;
2462                 break;
2463         case DRM_FORMAT_XBGR2101010:
2464         case DRM_FORMAT_ABGR2101010:
2465                 dspcntr |= DISPPLANE_RGBX101010;
2466                 break;
2467         default:
2468                 BUG();
2469         }
2470
2471         if (obj->tiling_mode != I915_TILING_NONE)
2472                 dspcntr |= DISPPLANE_TILED;
2473         else
2474                 dspcntr &= ~DISPPLANE_TILED;
2475
2476         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2477                 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2478         else
2479                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2480
2481         I915_WRITE(reg, dspcntr);
2482
2483         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2484         intel_crtc->dspaddr_offset =
2485                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2486                                                fb->bits_per_pixel / 8,
2487                                                fb->pitches[0]);
2488         linear_offset -= intel_crtc->dspaddr_offset;
2489
2490         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2491                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2492                       fb->pitches[0]);
2493         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2494         I915_WRITE(DSPSURF(plane),
2495                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2496         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2497                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2498         } else {
2499                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2500                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2501         }
2502         POSTING_READ(reg);
2503 }
2504
2505 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2506 static int
2507 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2508                            int x, int y, enum mode_set_atomic state)
2509 {
2510         struct drm_device *dev = crtc->dev;
2511         struct drm_i915_private *dev_priv = dev->dev_private;
2512
2513         if (dev_priv->display.disable_fbc)
2514                 dev_priv->display.disable_fbc(dev);
2515         intel_increase_pllclock(crtc);
2516
2517         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2518
2519         return 0;
2520 }
2521
2522 void intel_display_handle_reset(struct drm_device *dev)
2523 {
2524         struct drm_i915_private *dev_priv = dev->dev_private;
2525         struct drm_crtc *crtc;
2526
2527         /*
2528          * Flips in the rings have been nuked by the reset,
2529          * so complete all pending flips so that user space
2530          * will get its events and not get stuck.
2531          *
2532          * Also update the base address of all primary
2533          * planes to the the last fb to make sure we're
2534          * showing the correct fb after a reset.
2535          *
2536          * Need to make two loops over the crtcs so that we
2537          * don't try to grab a crtc mutex before the
2538          * pending_flip_queue really got woken up.
2539          */
2540
2541         for_each_crtc(dev, crtc) {
2542                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2543                 enum plane plane = intel_crtc->plane;
2544
2545                 intel_prepare_page_flip(dev, plane);
2546                 intel_finish_page_flip_plane(dev, plane);
2547         }
2548
2549         for_each_crtc(dev, crtc) {
2550                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2551
2552                 mutex_lock(&crtc->mutex);
2553                 /*
2554                  * FIXME: Once we have proper support for primary planes (and
2555                  * disabling them without disabling the entire crtc) allow again
2556                  * a NULL crtc->primary->fb.
2557                  */
2558                 if (intel_crtc->active && crtc->primary->fb)
2559                         dev_priv->display.update_primary_plane(crtc,
2560                                                                crtc->primary->fb,
2561                                                                crtc->x,
2562                                                                crtc->y);
2563                 mutex_unlock(&crtc->mutex);
2564         }
2565 }
2566
2567 static int
2568 intel_finish_fb(struct drm_framebuffer *old_fb)
2569 {
2570         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2571         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2572         bool was_interruptible = dev_priv->mm.interruptible;
2573         int ret;
2574
2575         /* Big Hammer, we also need to ensure that any pending
2576          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2577          * current scanout is retired before unpinning the old
2578          * framebuffer.
2579          *
2580          * This should only fail upon a hung GPU, in which case we
2581          * can safely continue.
2582          */
2583         dev_priv->mm.interruptible = false;
2584         ret = i915_gem_object_finish_gpu(obj);
2585         dev_priv->mm.interruptible = was_interruptible;
2586
2587         return ret;
2588 }
2589
2590 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2591 {
2592         struct drm_device *dev = crtc->dev;
2593         struct drm_i915_private *dev_priv = dev->dev_private;
2594         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2595         unsigned long flags;
2596         bool pending;
2597
2598         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2599             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2600                 return false;
2601
2602         spin_lock_irqsave(&dev->event_lock, flags);
2603         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2604         spin_unlock_irqrestore(&dev->event_lock, flags);
2605
2606         return pending;
2607 }
2608
2609 static int
2610 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2611                     struct drm_framebuffer *fb)
2612 {
2613         struct drm_device *dev = crtc->dev;
2614         struct drm_i915_private *dev_priv = dev->dev_private;
2615         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2616         struct drm_framebuffer *old_fb;
2617         int ret;
2618
2619         if (intel_crtc_has_pending_flip(crtc)) {
2620                 DRM_ERROR("pipe is still busy with an old pageflip\n");
2621                 return -EBUSY;
2622         }
2623
2624         /* no fb bound */
2625         if (!fb) {
2626                 DRM_ERROR("No FB bound\n");
2627                 return 0;
2628         }
2629
2630         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2631                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2632                           plane_name(intel_crtc->plane),
2633                           INTEL_INFO(dev)->num_pipes);
2634                 return -EINVAL;
2635         }
2636
2637         mutex_lock(&dev->struct_mutex);
2638         ret = intel_pin_and_fence_fb_obj(dev,
2639                                          to_intel_framebuffer(fb)->obj,
2640                                          NULL);
2641         mutex_unlock(&dev->struct_mutex);
2642         if (ret != 0) {
2643                 DRM_ERROR("pin & fence failed\n");
2644                 return ret;
2645         }
2646
2647         /*
2648          * Update pipe size and adjust fitter if needed: the reason for this is
2649          * that in compute_mode_changes we check the native mode (not the pfit
2650          * mode) to see if we can flip rather than do a full mode set. In the
2651          * fastboot case, we'll flip, but if we don't update the pipesrc and
2652          * pfit state, we'll end up with a big fb scanned out into the wrong
2653          * sized surface.
2654          *
2655          * To fix this properly, we need to hoist the checks up into
2656          * compute_mode_changes (or above), check the actual pfit state and
2657          * whether the platform allows pfit disable with pipe active, and only
2658          * then update the pipesrc and pfit state, even on the flip path.
2659          */
2660         if (i915.fastboot) {
2661                 const struct drm_display_mode *adjusted_mode =
2662                         &intel_crtc->config.adjusted_mode;
2663
2664                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2665                            ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2666                            (adjusted_mode->crtc_vdisplay - 1));
2667                 if (!intel_crtc->config.pch_pfit.enabled &&
2668                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2669                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2670                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2671                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2672                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2673                 }
2674                 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2675                 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2676         }
2677
2678         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2679
2680         old_fb = crtc->primary->fb;
2681         crtc->primary->fb = fb;
2682         crtc->x = x;
2683         crtc->y = y;
2684
2685         if (old_fb) {
2686                 if (intel_crtc->active && old_fb != fb)
2687                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2688                 mutex_lock(&dev->struct_mutex);
2689                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2690                 mutex_unlock(&dev->struct_mutex);
2691         }
2692
2693         mutex_lock(&dev->struct_mutex);
2694         intel_update_fbc(dev);
2695         intel_edp_psr_update(dev);
2696         mutex_unlock(&dev->struct_mutex);
2697
2698         return 0;
2699 }
2700
2701 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2702 {
2703         struct drm_device *dev = crtc->dev;
2704         struct drm_i915_private *dev_priv = dev->dev_private;
2705         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2706         int pipe = intel_crtc->pipe;
2707         u32 reg, temp;
2708
2709         /* enable normal train */
2710         reg = FDI_TX_CTL(pipe);
2711         temp = I915_READ(reg);
2712         if (IS_IVYBRIDGE(dev)) {
2713                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2714                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2715         } else {
2716                 temp &= ~FDI_LINK_TRAIN_NONE;
2717                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2718         }
2719         I915_WRITE(reg, temp);
2720
2721         reg = FDI_RX_CTL(pipe);
2722         temp = I915_READ(reg);
2723         if (HAS_PCH_CPT(dev)) {
2724                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2725                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2726         } else {
2727                 temp &= ~FDI_LINK_TRAIN_NONE;
2728                 temp |= FDI_LINK_TRAIN_NONE;
2729         }
2730         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2731
2732         /* wait one idle pattern time */
2733         POSTING_READ(reg);
2734         udelay(1000);
2735
2736         /* IVB wants error correction enabled */
2737         if (IS_IVYBRIDGE(dev))
2738                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2739                            FDI_FE_ERRC_ENABLE);
2740 }
2741
2742 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2743 {
2744         return crtc->base.enabled && crtc->active &&
2745                 crtc->config.has_pch_encoder;
2746 }
2747
2748 static void ivb_modeset_global_resources(struct drm_device *dev)
2749 {
2750         struct drm_i915_private *dev_priv = dev->dev_private;
2751         struct intel_crtc *pipe_B_crtc =
2752                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2753         struct intel_crtc *pipe_C_crtc =
2754                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2755         uint32_t temp;
2756
2757         /*
2758          * When everything is off disable fdi C so that we could enable fdi B
2759          * with all lanes. Note that we don't care about enabled pipes without
2760          * an enabled pch encoder.
2761          */
2762         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2763             !pipe_has_enabled_pch(pipe_C_crtc)) {
2764                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2765                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2766
2767                 temp = I915_READ(SOUTH_CHICKEN1);
2768                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2769                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2770                 I915_WRITE(SOUTH_CHICKEN1, temp);
2771         }
2772 }
2773
2774 /* The FDI link training functions for ILK/Ibexpeak. */
2775 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2776 {
2777         struct drm_device *dev = crtc->dev;
2778         struct drm_i915_private *dev_priv = dev->dev_private;
2779         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2780         int pipe = intel_crtc->pipe;
2781         u32 reg, temp, tries;
2782
2783         /* FDI needs bits from pipe first */
2784         assert_pipe_enabled(dev_priv, pipe);
2785
2786         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2787            for train result */
2788         reg = FDI_RX_IMR(pipe);
2789         temp = I915_READ(reg);
2790         temp &= ~FDI_RX_SYMBOL_LOCK;
2791         temp &= ~FDI_RX_BIT_LOCK;
2792         I915_WRITE(reg, temp);
2793         I915_READ(reg);
2794         udelay(150);
2795
2796         /* enable CPU FDI TX and PCH FDI RX */
2797         reg = FDI_TX_CTL(pipe);
2798         temp = I915_READ(reg);
2799         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2800         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2801         temp &= ~FDI_LINK_TRAIN_NONE;
2802         temp |= FDI_LINK_TRAIN_PATTERN_1;
2803         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2804
2805         reg = FDI_RX_CTL(pipe);
2806         temp = I915_READ(reg);
2807         temp &= ~FDI_LINK_TRAIN_NONE;
2808         temp |= FDI_LINK_TRAIN_PATTERN_1;
2809         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2810
2811         POSTING_READ(reg);
2812         udelay(150);
2813
2814         /* Ironlake workaround, enable clock pointer after FDI enable*/
2815         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2816         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2817                    FDI_RX_PHASE_SYNC_POINTER_EN);
2818
2819         reg = FDI_RX_IIR(pipe);
2820         for (tries = 0; tries < 5; tries++) {
2821                 temp = I915_READ(reg);
2822                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2823
2824                 if ((temp & FDI_RX_BIT_LOCK)) {
2825                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2826                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2827                         break;
2828                 }
2829         }
2830         if (tries == 5)
2831                 DRM_ERROR("FDI train 1 fail!\n");
2832
2833         /* Train 2 */
2834         reg = FDI_TX_CTL(pipe);
2835         temp = I915_READ(reg);
2836         temp &= ~FDI_LINK_TRAIN_NONE;
2837         temp |= FDI_LINK_TRAIN_PATTERN_2;
2838         I915_WRITE(reg, temp);
2839
2840         reg = FDI_RX_CTL(pipe);
2841         temp = I915_READ(reg);
2842         temp &= ~FDI_LINK_TRAIN_NONE;
2843         temp |= FDI_LINK_TRAIN_PATTERN_2;
2844         I915_WRITE(reg, temp);
2845
2846         POSTING_READ(reg);
2847         udelay(150);
2848
2849         reg = FDI_RX_IIR(pipe);
2850         for (tries = 0; tries < 5; tries++) {
2851                 temp = I915_READ(reg);
2852                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2853
2854                 if (temp & FDI_RX_SYMBOL_LOCK) {
2855                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2856                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2857                         break;
2858                 }
2859         }
2860         if (tries == 5)
2861                 DRM_ERROR("FDI train 2 fail!\n");
2862
2863         DRM_DEBUG_KMS("FDI train done\n");
2864
2865 }
2866
2867 static const int snb_b_fdi_train_param[] = {
2868         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2869         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2870         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2871         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2872 };
2873
2874 /* The FDI link training functions for SNB/Cougarpoint. */
2875 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2876 {
2877         struct drm_device *dev = crtc->dev;
2878         struct drm_i915_private *dev_priv = dev->dev_private;
2879         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2880         int pipe = intel_crtc->pipe;
2881         u32 reg, temp, i, retry;
2882
2883         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2884            for train result */
2885         reg = FDI_RX_IMR(pipe);
2886         temp = I915_READ(reg);
2887         temp &= ~FDI_RX_SYMBOL_LOCK;
2888         temp &= ~FDI_RX_BIT_LOCK;
2889         I915_WRITE(reg, temp);
2890
2891         POSTING_READ(reg);
2892         udelay(150);
2893
2894         /* enable CPU FDI TX and PCH FDI RX */
2895         reg = FDI_TX_CTL(pipe);
2896         temp = I915_READ(reg);
2897         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2898         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2899         temp &= ~FDI_LINK_TRAIN_NONE;
2900         temp |= FDI_LINK_TRAIN_PATTERN_1;
2901         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2902         /* SNB-B */
2903         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2904         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2905
2906         I915_WRITE(FDI_RX_MISC(pipe),
2907                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2908
2909         reg = FDI_RX_CTL(pipe);
2910         temp = I915_READ(reg);
2911         if (HAS_PCH_CPT(dev)) {
2912                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2913                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2914         } else {
2915                 temp &= ~FDI_LINK_TRAIN_NONE;
2916                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2917         }
2918         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2919
2920         POSTING_READ(reg);
2921         udelay(150);
2922
2923         for (i = 0; i < 4; i++) {
2924                 reg = FDI_TX_CTL(pipe);
2925                 temp = I915_READ(reg);
2926                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2927                 temp |= snb_b_fdi_train_param[i];
2928                 I915_WRITE(reg, temp);
2929
2930                 POSTING_READ(reg);
2931                 udelay(500);
2932
2933                 for (retry = 0; retry < 5; retry++) {
2934                         reg = FDI_RX_IIR(pipe);
2935                         temp = I915_READ(reg);
2936                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2937                         if (temp & FDI_RX_BIT_LOCK) {
2938                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2939                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2940                                 break;
2941                         }
2942                         udelay(50);
2943                 }
2944                 if (retry < 5)
2945                         break;
2946         }
2947         if (i == 4)
2948                 DRM_ERROR("FDI train 1 fail!\n");
2949
2950         /* Train 2 */
2951         reg = FDI_TX_CTL(pipe);
2952         temp = I915_READ(reg);
2953         temp &= ~FDI_LINK_TRAIN_NONE;
2954         temp |= FDI_LINK_TRAIN_PATTERN_2;
2955         if (IS_GEN6(dev)) {
2956                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2957                 /* SNB-B */
2958                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2959         }
2960         I915_WRITE(reg, temp);
2961
2962         reg = FDI_RX_CTL(pipe);
2963         temp = I915_READ(reg);
2964         if (HAS_PCH_CPT(dev)) {
2965                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2966                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2967         } else {
2968                 temp &= ~FDI_LINK_TRAIN_NONE;
2969                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2970         }
2971         I915_WRITE(reg, temp);
2972
2973         POSTING_READ(reg);
2974         udelay(150);
2975
2976         for (i = 0; i < 4; i++) {
2977                 reg = FDI_TX_CTL(pipe);
2978                 temp = I915_READ(reg);
2979                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2980                 temp |= snb_b_fdi_train_param[i];
2981                 I915_WRITE(reg, temp);
2982
2983                 POSTING_READ(reg);
2984                 udelay(500);
2985
2986                 for (retry = 0; retry < 5; retry++) {
2987                         reg = FDI_RX_IIR(pipe);
2988                         temp = I915_READ(reg);
2989                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2990                         if (temp & FDI_RX_SYMBOL_LOCK) {
2991                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2992                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2993                                 break;
2994                         }
2995                         udelay(50);
2996                 }
2997                 if (retry < 5)
2998                         break;
2999         }
3000         if (i == 4)
3001                 DRM_ERROR("FDI train 2 fail!\n");
3002
3003         DRM_DEBUG_KMS("FDI train done.\n");
3004 }
3005
3006 /* Manual link training for Ivy Bridge A0 parts */
3007 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3008 {
3009         struct drm_device *dev = crtc->dev;
3010         struct drm_i915_private *dev_priv = dev->dev_private;
3011         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3012         int pipe = intel_crtc->pipe;
3013         u32 reg, temp, i, j;
3014
3015         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3016            for train result */
3017         reg = FDI_RX_IMR(pipe);
3018         temp = I915_READ(reg);
3019         temp &= ~FDI_RX_SYMBOL_LOCK;
3020         temp &= ~FDI_RX_BIT_LOCK;
3021         I915_WRITE(reg, temp);
3022
3023         POSTING_READ(reg);
3024         udelay(150);
3025
3026         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3027                       I915_READ(FDI_RX_IIR(pipe)));
3028
3029         /* Try each vswing and preemphasis setting twice before moving on */
3030         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3031                 /* disable first in case we need to retry */
3032                 reg = FDI_TX_CTL(pipe);
3033                 temp = I915_READ(reg);
3034                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3035                 temp &= ~FDI_TX_ENABLE;
3036                 I915_WRITE(reg, temp);
3037
3038                 reg = FDI_RX_CTL(pipe);
3039                 temp = I915_READ(reg);
3040                 temp &= ~FDI_LINK_TRAIN_AUTO;
3041                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3042                 temp &= ~FDI_RX_ENABLE;
3043                 I915_WRITE(reg, temp);
3044
3045                 /* enable CPU FDI TX and PCH FDI RX */
3046                 reg = FDI_TX_CTL(pipe);
3047                 temp = I915_READ(reg);
3048                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3049                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3050                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3051                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3052                 temp |= snb_b_fdi_train_param[j/2];
3053                 temp |= FDI_COMPOSITE_SYNC;
3054                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3055
3056                 I915_WRITE(FDI_RX_MISC(pipe),
3057                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3058
3059                 reg = FDI_RX_CTL(pipe);
3060                 temp = I915_READ(reg);
3061                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3062                 temp |= FDI_COMPOSITE_SYNC;
3063                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3064
3065                 POSTING_READ(reg);
3066                 udelay(1); /* should be 0.5us */
3067
3068                 for (i = 0; i < 4; i++) {
3069                         reg = FDI_RX_IIR(pipe);
3070                         temp = I915_READ(reg);
3071                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3072
3073                         if (temp & FDI_RX_BIT_LOCK ||
3074                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3075                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3076                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3077                                               i);
3078                                 break;
3079                         }
3080                         udelay(1); /* should be 0.5us */
3081                 }
3082                 if (i == 4) {
3083                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3084                         continue;
3085                 }
3086
3087                 /* Train 2 */
3088                 reg = FDI_TX_CTL(pipe);
3089                 temp = I915_READ(reg);
3090                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3091                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3092                 I915_WRITE(reg, temp);
3093
3094                 reg = FDI_RX_CTL(pipe);
3095                 temp = I915_READ(reg);
3096                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3097                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3098                 I915_WRITE(reg, temp);
3099
3100                 POSTING_READ(reg);
3101                 udelay(2); /* should be 1.5us */
3102
3103                 for (i = 0; i < 4; i++) {
3104                         reg = FDI_RX_IIR(pipe);
3105                         temp = I915_READ(reg);
3106                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3107
3108                         if (temp & FDI_RX_SYMBOL_LOCK ||
3109                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3110                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3111                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3112                                               i);
3113                                 goto train_done;
3114                         }
3115                         udelay(2); /* should be 1.5us */
3116                 }
3117                 if (i == 4)
3118                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3119         }
3120
3121 train_done:
3122         DRM_DEBUG_KMS("FDI train done.\n");
3123 }
3124
3125 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3126 {
3127         struct drm_device *dev = intel_crtc->base.dev;
3128         struct drm_i915_private *dev_priv = dev->dev_private;
3129         int pipe = intel_crtc->pipe;
3130         u32 reg, temp;
3131
3132
3133         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3134         reg = FDI_RX_CTL(pipe);
3135         temp = I915_READ(reg);
3136         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3137         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3138         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3139         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3140
3141         POSTING_READ(reg);
3142         udelay(200);
3143
3144         /* Switch from Rawclk to PCDclk */
3145         temp = I915_READ(reg);
3146         I915_WRITE(reg, temp | FDI_PCDCLK);
3147
3148         POSTING_READ(reg);
3149         udelay(200);
3150
3151         /* Enable CPU FDI TX PLL, always on for Ironlake */
3152         reg = FDI_TX_CTL(pipe);
3153         temp = I915_READ(reg);
3154         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3155                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3156
3157                 POSTING_READ(reg);
3158                 udelay(100);
3159         }
3160 }
3161
3162 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3163 {
3164         struct drm_device *dev = intel_crtc->base.dev;
3165         struct drm_i915_private *dev_priv = dev->dev_private;
3166         int pipe = intel_crtc->pipe;
3167         u32 reg, temp;
3168
3169         /* Switch from PCDclk to Rawclk */
3170         reg = FDI_RX_CTL(pipe);
3171         temp = I915_READ(reg);
3172         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3173
3174         /* Disable CPU FDI TX PLL */
3175         reg = FDI_TX_CTL(pipe);
3176         temp = I915_READ(reg);
3177         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3178
3179         POSTING_READ(reg);
3180         udelay(100);
3181
3182         reg = FDI_RX_CTL(pipe);
3183         temp = I915_READ(reg);
3184         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3185
3186         /* Wait for the clocks to turn off. */
3187         POSTING_READ(reg);
3188         udelay(100);
3189 }
3190
3191 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3192 {
3193         struct drm_device *dev = crtc->dev;
3194         struct drm_i915_private *dev_priv = dev->dev_private;
3195         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3196         int pipe = intel_crtc->pipe;
3197         u32 reg, temp;
3198
3199         /* disable CPU FDI tx and PCH FDI rx */
3200         reg = FDI_TX_CTL(pipe);
3201         temp = I915_READ(reg);
3202         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3203         POSTING_READ(reg);
3204
3205         reg = FDI_RX_CTL(pipe);
3206         temp = I915_READ(reg);
3207         temp &= ~(0x7 << 16);
3208         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3209         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3210
3211         POSTING_READ(reg);
3212         udelay(100);
3213
3214         /* Ironlake workaround, disable clock pointer after downing FDI */
3215         if (HAS_PCH_IBX(dev)) {
3216                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3217         }
3218
3219         /* still set train pattern 1 */
3220         reg = FDI_TX_CTL(pipe);
3221         temp = I915_READ(reg);
3222         temp &= ~FDI_LINK_TRAIN_NONE;
3223         temp |= FDI_LINK_TRAIN_PATTERN_1;
3224         I915_WRITE(reg, temp);
3225
3226         reg = FDI_RX_CTL(pipe);
3227         temp = I915_READ(reg);
3228         if (HAS_PCH_CPT(dev)) {
3229                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3230                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3231         } else {
3232                 temp &= ~FDI_LINK_TRAIN_NONE;
3233                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3234         }
3235         /* BPC in FDI rx is consistent with that in PIPECONF */
3236         temp &= ~(0x07 << 16);
3237         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3238         I915_WRITE(reg, temp);
3239
3240         POSTING_READ(reg);
3241         udelay(100);
3242 }
3243
3244 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3245 {
3246         struct intel_crtc *crtc;
3247
3248         /* Note that we don't need to be called with mode_config.lock here
3249          * as our list of CRTC objects is static for the lifetime of the
3250          * device and so cannot disappear as we iterate. Similarly, we can
3251          * happily treat the predicates as racy, atomic checks as userspace
3252          * cannot claim and pin a new fb without at least acquring the
3253          * struct_mutex and so serialising with us.
3254          */
3255         for_each_intel_crtc(dev, crtc) {
3256                 if (atomic_read(&crtc->unpin_work_count) == 0)
3257                         continue;
3258
3259                 if (crtc->unpin_work)
3260                         intel_wait_for_vblank(dev, crtc->pipe);
3261
3262                 return true;
3263         }
3264
3265         return false;
3266 }
3267
3268 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3269 {
3270         struct drm_device *dev = crtc->dev;
3271         struct drm_i915_private *dev_priv = dev->dev_private;
3272
3273         if (crtc->primary->fb == NULL)
3274                 return;
3275
3276         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3277
3278         wait_event(dev_priv->pending_flip_queue,
3279                    !intel_crtc_has_pending_flip(crtc));
3280
3281         mutex_lock(&dev->struct_mutex);
3282         intel_finish_fb(crtc->primary->fb);
3283         mutex_unlock(&dev->struct_mutex);
3284 }
3285
3286 /* Program iCLKIP clock to the desired frequency */
3287 static void lpt_program_iclkip(struct drm_crtc *crtc)
3288 {
3289         struct drm_device *dev = crtc->dev;
3290         struct drm_i915_private *dev_priv = dev->dev_private;
3291         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3292         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3293         u32 temp;
3294
3295         mutex_lock(&dev_priv->dpio_lock);
3296
3297         /* It is necessary to ungate the pixclk gate prior to programming
3298          * the divisors, and gate it back when it is done.
3299          */
3300         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3301
3302         /* Disable SSCCTL */
3303         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3304                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3305                                 SBI_SSCCTL_DISABLE,
3306                         SBI_ICLK);
3307
3308         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3309         if (clock == 20000) {
3310                 auxdiv = 1;
3311                 divsel = 0x41;
3312                 phaseinc = 0x20;
3313         } else {
3314                 /* The iCLK virtual clock root frequency is in MHz,
3315                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3316                  * divisors, it is necessary to divide one by another, so we
3317                  * convert the virtual clock precision to KHz here for higher
3318                  * precision.
3319                  */
3320                 u32 iclk_virtual_root_freq = 172800 * 1000;
3321                 u32 iclk_pi_range = 64;
3322                 u32 desired_divisor, msb_divisor_value, pi_value;
3323
3324                 desired_divisor = (iclk_virtual_root_freq / clock);
3325                 msb_divisor_value = desired_divisor / iclk_pi_range;
3326                 pi_value = desired_divisor % iclk_pi_range;
3327
3328                 auxdiv = 0;
3329                 divsel = msb_divisor_value - 2;
3330                 phaseinc = pi_value;
3331         }
3332
3333         /* This should not happen with any sane values */
3334         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3335                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3336         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3337                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3338
3339         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3340                         clock,
3341                         auxdiv,
3342                         divsel,
3343                         phasedir,
3344                         phaseinc);
3345
3346         /* Program SSCDIVINTPHASE6 */
3347         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3348         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3349         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3350         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3351         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3352         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3353         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3354         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3355
3356         /* Program SSCAUXDIV */
3357         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3358         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3359         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3360         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3361
3362         /* Enable modulator and associated divider */
3363         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3364         temp &= ~SBI_SSCCTL_DISABLE;
3365         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3366
3367         /* Wait for initialization time */
3368         udelay(24);
3369
3370         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3371
3372         mutex_unlock(&dev_priv->dpio_lock);
3373 }
3374
3375 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3376                                                 enum pipe pch_transcoder)
3377 {
3378         struct drm_device *dev = crtc->base.dev;
3379         struct drm_i915_private *dev_priv = dev->dev_private;
3380         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3381
3382         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3383                    I915_READ(HTOTAL(cpu_transcoder)));
3384         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3385                    I915_READ(HBLANK(cpu_transcoder)));
3386         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3387                    I915_READ(HSYNC(cpu_transcoder)));
3388
3389         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3390                    I915_READ(VTOTAL(cpu_transcoder)));
3391         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3392                    I915_READ(VBLANK(cpu_transcoder)));
3393         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3394                    I915_READ(VSYNC(cpu_transcoder)));
3395         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3396                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3397 }
3398
3399 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3400 {
3401         struct drm_i915_private *dev_priv = dev->dev_private;
3402         uint32_t temp;
3403
3404         temp = I915_READ(SOUTH_CHICKEN1);
3405         if (temp & FDI_BC_BIFURCATION_SELECT)
3406                 return;
3407
3408         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3409         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3410
3411         temp |= FDI_BC_BIFURCATION_SELECT;
3412         DRM_DEBUG_KMS("enabling fdi C rx\n");
3413         I915_WRITE(SOUTH_CHICKEN1, temp);
3414         POSTING_READ(SOUTH_CHICKEN1);
3415 }
3416
3417 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3418 {
3419         struct drm_device *dev = intel_crtc->base.dev;
3420         struct drm_i915_private *dev_priv = dev->dev_private;
3421
3422         switch (intel_crtc->pipe) {
3423         case PIPE_A:
3424                 break;
3425         case PIPE_B:
3426                 if (intel_crtc->config.fdi_lanes > 2)
3427                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3428                 else
3429                         cpt_enable_fdi_bc_bifurcation(dev);
3430
3431                 break;
3432         case PIPE_C:
3433                 cpt_enable_fdi_bc_bifurcation(dev);
3434
3435                 break;
3436         default:
3437                 BUG();
3438         }
3439 }
3440
3441 /*
3442  * Enable PCH resources required for PCH ports:
3443  *   - PCH PLLs
3444  *   - FDI training & RX/TX
3445  *   - update transcoder timings
3446  *   - DP transcoding bits
3447  *   - transcoder
3448  */
3449 static void ironlake_pch_enable(struct drm_crtc *crtc)
3450 {
3451         struct drm_device *dev = crtc->dev;
3452         struct drm_i915_private *dev_priv = dev->dev_private;
3453         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3454         int pipe = intel_crtc->pipe;
3455         u32 reg, temp;
3456
3457         assert_pch_transcoder_disabled(dev_priv, pipe);
3458
3459         if (IS_IVYBRIDGE(dev))
3460                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3461
3462         /* Write the TU size bits before fdi link training, so that error
3463          * detection works. */
3464         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3465                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3466
3467         /* For PCH output, training FDI link */
3468         dev_priv->display.fdi_link_train(crtc);
3469
3470         /* We need to program the right clock selection before writing the pixel
3471          * mutliplier into the DPLL. */
3472         if (HAS_PCH_CPT(dev)) {
3473                 u32 sel;
3474
3475                 temp = I915_READ(PCH_DPLL_SEL);
3476                 temp |= TRANS_DPLL_ENABLE(pipe);
3477                 sel = TRANS_DPLLB_SEL(pipe);
3478                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3479                         temp |= sel;
3480                 else
3481                         temp &= ~sel;
3482                 I915_WRITE(PCH_DPLL_SEL, temp);
3483         }
3484
3485         /* XXX: pch pll's can be enabled any time before we enable the PCH
3486          * transcoder, and we actually should do this to not upset any PCH
3487          * transcoder that already use the clock when we share it.
3488          *
3489          * Note that enable_shared_dpll tries to do the right thing, but
3490          * get_shared_dpll unconditionally resets the pll - we need that to have
3491          * the right LVDS enable sequence. */
3492         ironlake_enable_shared_dpll(intel_crtc);
3493
3494         /* set transcoder timing, panel must allow it */
3495         assert_panel_unlocked(dev_priv, pipe);
3496         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3497
3498         intel_fdi_normal_train(crtc);
3499
3500         /* For PCH DP, enable TRANS_DP_CTL */
3501         if (HAS_PCH_CPT(dev) &&
3502             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3503              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3504                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3505                 reg = TRANS_DP_CTL(pipe);
3506                 temp = I915_READ(reg);
3507                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3508                           TRANS_DP_SYNC_MASK |
3509                           TRANS_DP_BPC_MASK);
3510                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3511                          TRANS_DP_ENH_FRAMING);
3512                 temp |= bpc << 9; /* same format but at 11:9 */
3513
3514                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3515                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3516                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3517                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3518
3519                 switch (intel_trans_dp_port_sel(crtc)) {
3520                 case PCH_DP_B:
3521                         temp |= TRANS_DP_PORT_SEL_B;
3522                         break;
3523                 case PCH_DP_C:
3524                         temp |= TRANS_DP_PORT_SEL_C;
3525                         break;
3526                 case PCH_DP_D:
3527                         temp |= TRANS_DP_PORT_SEL_D;
3528                         break;
3529                 default:
3530                         BUG();
3531                 }
3532
3533                 I915_WRITE(reg, temp);
3534         }
3535
3536         ironlake_enable_pch_transcoder(dev_priv, pipe);
3537 }
3538
3539 static void lpt_pch_enable(struct drm_crtc *crtc)
3540 {
3541         struct drm_device *dev = crtc->dev;
3542         struct drm_i915_private *dev_priv = dev->dev_private;
3543         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3544         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3545
3546         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3547
3548         lpt_program_iclkip(crtc);
3549
3550         /* Set transcoder timing. */
3551         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3552
3553         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3554 }
3555
3556 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3557 {
3558         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3559
3560         if (pll == NULL)
3561                 return;
3562
3563         if (pll->refcount == 0) {
3564                 WARN(1, "bad %s refcount\n", pll->name);
3565                 return;
3566         }
3567
3568         if (--pll->refcount == 0) {
3569                 WARN_ON(pll->on);
3570                 WARN_ON(pll->active);
3571         }
3572
3573         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3574 }
3575
3576 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3577 {
3578         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3579         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3580         enum intel_dpll_id i;
3581
3582         if (pll) {
3583                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3584                               crtc->base.base.id, pll->name);
3585                 intel_put_shared_dpll(crtc);
3586         }
3587
3588         if (HAS_PCH_IBX(dev_priv->dev)) {
3589                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3590                 i = (enum intel_dpll_id) crtc->pipe;
3591                 pll = &dev_priv->shared_dplls[i];
3592
3593                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3594                               crtc->base.base.id, pll->name);
3595
3596                 goto found;
3597         }
3598
3599         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3600                 pll = &dev_priv->shared_dplls[i];
3601
3602                 /* Only want to check enabled timings first */
3603                 if (pll->refcount == 0)
3604                         continue;
3605
3606                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3607                            sizeof(pll->hw_state)) == 0) {
3608                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3609                                       crtc->base.base.id,
3610                                       pll->name, pll->refcount, pll->active);
3611
3612                         goto found;
3613                 }
3614         }
3615
3616         /* Ok no matching timings, maybe there's a free one? */
3617         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3618                 pll = &dev_priv->shared_dplls[i];
3619                 if (pll->refcount == 0) {
3620                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3621                                       crtc->base.base.id, pll->name);
3622                         goto found;
3623                 }
3624         }
3625
3626         return NULL;
3627
3628 found:
3629         crtc->config.shared_dpll = i;
3630         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3631                          pipe_name(crtc->pipe));
3632
3633         if (pll->active == 0) {
3634                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3635                        sizeof(pll->hw_state));
3636
3637                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3638                 WARN_ON(pll->on);
3639                 assert_shared_dpll_disabled(dev_priv, pll);
3640
3641                 pll->mode_set(dev_priv, pll);
3642         }
3643         pll->refcount++;
3644
3645         return pll;
3646 }
3647
3648 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3649 {
3650         struct drm_i915_private *dev_priv = dev->dev_private;
3651         int dslreg = PIPEDSL(pipe);
3652         u32 temp;
3653
3654         temp = I915_READ(dslreg);
3655         udelay(500);
3656         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3657                 if (wait_for(I915_READ(dslreg) != temp, 5))
3658                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3659         }
3660 }
3661
3662 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3663 {
3664         struct drm_device *dev = crtc->base.dev;
3665         struct drm_i915_private *dev_priv = dev->dev_private;
3666         int pipe = crtc->pipe;
3667
3668         if (crtc->config.pch_pfit.enabled) {
3669                 /* Force use of hard-coded filter coefficients
3670                  * as some pre-programmed values are broken,
3671                  * e.g. x201.
3672                  */
3673                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3674                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3675                                                  PF_PIPE_SEL_IVB(pipe));
3676                 else
3677                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3678                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3679                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3680         }
3681 }
3682
3683 static void intel_enable_planes(struct drm_crtc *crtc)
3684 {
3685         struct drm_device *dev = crtc->dev;
3686         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3687         struct drm_plane *plane;
3688         struct intel_plane *intel_plane;
3689
3690         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3691                 intel_plane = to_intel_plane(plane);
3692                 if (intel_plane->pipe == pipe)
3693                         intel_plane_restore(&intel_plane->base);
3694         }
3695 }
3696
3697 static void intel_disable_planes(struct drm_crtc *crtc)
3698 {
3699         struct drm_device *dev = crtc->dev;
3700         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3701         struct drm_plane *plane;
3702         struct intel_plane *intel_plane;
3703
3704         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3705                 intel_plane = to_intel_plane(plane);
3706                 if (intel_plane->pipe == pipe)
3707                         intel_plane_disable(&intel_plane->base);
3708         }
3709 }
3710
3711 void hsw_enable_ips(struct intel_crtc *crtc)
3712 {
3713         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3714
3715         if (!crtc->config.ips_enabled)
3716                 return;
3717
3718         /* We can only enable IPS after we enable a plane and wait for a vblank.
3719          * We guarantee that the plane is enabled by calling intel_enable_ips
3720          * only after intel_enable_plane. And intel_enable_plane already waits
3721          * for a vblank, so all we need to do here is to enable the IPS bit. */
3722         assert_plane_enabled(dev_priv, crtc->plane);
3723         if (IS_BROADWELL(crtc->base.dev)) {
3724                 mutex_lock(&dev_priv->rps.hw_lock);
3725                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3726                 mutex_unlock(&dev_priv->rps.hw_lock);
3727                 /* Quoting Art Runyan: "its not safe to expect any particular
3728                  * value in IPS_CTL bit 31 after enabling IPS through the
3729                  * mailbox." Moreover, the mailbox may return a bogus state,
3730                  * so we need to just enable it and continue on.
3731                  */
3732         } else {
3733                 I915_WRITE(IPS_CTL, IPS_ENABLE);
3734                 /* The bit only becomes 1 in the next vblank, so this wait here
3735                  * is essentially intel_wait_for_vblank. If we don't have this
3736                  * and don't wait for vblanks until the end of crtc_enable, then
3737                  * the HW state readout code will complain that the expected
3738                  * IPS_CTL value is not the one we read. */
3739                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3740                         DRM_ERROR("Timed out waiting for IPS enable\n");
3741         }
3742 }
3743
3744 void hsw_disable_ips(struct intel_crtc *crtc)
3745 {
3746         struct drm_device *dev = crtc->base.dev;
3747         struct drm_i915_private *dev_priv = dev->dev_private;
3748
3749         if (!crtc->config.ips_enabled)
3750                 return;
3751
3752         assert_plane_enabled(dev_priv, crtc->plane);
3753         if (IS_BROADWELL(dev)) {
3754                 mutex_lock(&dev_priv->rps.hw_lock);
3755                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3756                 mutex_unlock(&dev_priv->rps.hw_lock);
3757                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3758                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3759                         DRM_ERROR("Timed out waiting for IPS disable\n");
3760         } else {
3761                 I915_WRITE(IPS_CTL, 0);
3762                 POSTING_READ(IPS_CTL);
3763         }
3764
3765         /* We need to wait for a vblank before we can disable the plane. */
3766         intel_wait_for_vblank(dev, crtc->pipe);
3767 }
3768
3769 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3770 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3771 {
3772         struct drm_device *dev = crtc->dev;
3773         struct drm_i915_private *dev_priv = dev->dev_private;
3774         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3775         enum pipe pipe = intel_crtc->pipe;
3776         int palreg = PALETTE(pipe);
3777         int i;
3778         bool reenable_ips = false;
3779
3780         /* The clocks have to be on to load the palette. */
3781         if (!crtc->enabled || !intel_crtc->active)
3782                 return;
3783
3784         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3785                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3786                         assert_dsi_pll_enabled(dev_priv);
3787                 else
3788                         assert_pll_enabled(dev_priv, pipe);
3789         }
3790
3791         /* use legacy palette for Ironlake */
3792         if (HAS_PCH_SPLIT(dev))
3793                 palreg = LGC_PALETTE(pipe);
3794
3795         /* Workaround : Do not read or write the pipe palette/gamma data while
3796          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3797          */
3798         if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3799             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3800              GAMMA_MODE_MODE_SPLIT)) {
3801                 hsw_disable_ips(intel_crtc);
3802                 reenable_ips = true;
3803         }
3804
3805         for (i = 0; i < 256; i++) {
3806                 I915_WRITE(palreg + 4 * i,
3807                            (intel_crtc->lut_r[i] << 16) |
3808                            (intel_crtc->lut_g[i] << 8) |
3809                            intel_crtc->lut_b[i]);
3810         }
3811
3812         if (reenable_ips)
3813                 hsw_enable_ips(intel_crtc);
3814 }
3815
3816 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3817 {
3818         if (!enable && intel_crtc->overlay) {
3819                 struct drm_device *dev = intel_crtc->base.dev;
3820                 struct drm_i915_private *dev_priv = dev->dev_private;
3821
3822                 mutex_lock(&dev->struct_mutex);
3823                 dev_priv->mm.interruptible = false;
3824                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3825                 dev_priv->mm.interruptible = true;
3826                 mutex_unlock(&dev->struct_mutex);
3827         }
3828
3829         /* Let userspace switch the overlay on again. In most cases userspace
3830          * has to recompute where to put it anyway.
3831          */
3832 }
3833
3834 /**
3835  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3836  * cursor plane briefly if not already running after enabling the display
3837  * plane.
3838  * This workaround avoids occasional blank screens when self refresh is
3839  * enabled.
3840  */
3841 static void
3842 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3843 {
3844         u32 cntl = I915_READ(CURCNTR(pipe));
3845
3846         if ((cntl & CURSOR_MODE) == 0) {
3847                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3848
3849                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3850                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3851                 intel_wait_for_vblank(dev_priv->dev, pipe);
3852                 I915_WRITE(CURCNTR(pipe), cntl);
3853                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3854                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3855         }
3856 }
3857
3858 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
3859 {
3860         struct drm_device *dev = crtc->dev;
3861         struct drm_i915_private *dev_priv = dev->dev_private;
3862         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3863         int pipe = intel_crtc->pipe;
3864         int plane = intel_crtc->plane;
3865
3866         intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3867         intel_enable_planes(crtc);
3868         /* The fixup needs to happen before cursor is enabled */
3869         if (IS_G4X(dev))
3870                 g4x_fixup_plane(dev_priv, pipe);
3871         intel_crtc_update_cursor(crtc, true);
3872         intel_crtc_dpms_overlay(intel_crtc, true);
3873
3874         hsw_enable_ips(intel_crtc);
3875
3876         mutex_lock(&dev->struct_mutex);
3877         intel_update_fbc(dev);
3878         intel_edp_psr_update(dev);
3879         mutex_unlock(&dev->struct_mutex);
3880 }
3881
3882 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
3883 {
3884         struct drm_device *dev = crtc->dev;
3885         struct drm_i915_private *dev_priv = dev->dev_private;
3886         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3887         int pipe = intel_crtc->pipe;
3888         int plane = intel_crtc->plane;
3889
3890         intel_crtc_wait_for_pending_flips(crtc);
3891         drm_vblank_off(dev, pipe);
3892
3893         if (dev_priv->fbc.plane == plane)
3894                 intel_disable_fbc(dev);
3895
3896         hsw_disable_ips(intel_crtc);
3897
3898         intel_crtc_dpms_overlay(intel_crtc, false);
3899         intel_crtc_update_cursor(crtc, false);
3900         intel_disable_planes(crtc);
3901         intel_disable_primary_hw_plane(dev_priv, plane, pipe);
3902 }
3903
3904 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3905 {
3906         struct drm_device *dev = crtc->dev;
3907         struct drm_i915_private *dev_priv = dev->dev_private;
3908         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3909         struct intel_encoder *encoder;
3910         int pipe = intel_crtc->pipe;
3911
3912         WARN_ON(!crtc->enabled);
3913
3914         if (intel_crtc->active)
3915                 return;
3916
3917         intel_crtc->active = true;
3918
3919         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3920         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3921
3922         for_each_encoder_on_crtc(dev, crtc, encoder)
3923                 if (encoder->pre_enable)
3924                         encoder->pre_enable(encoder);
3925
3926         if (intel_crtc->config.has_pch_encoder) {
3927                 /* Note: FDI PLL enabling _must_ be done before we enable the
3928                  * cpu pipes, hence this is separate from all the other fdi/pch
3929                  * enabling. */
3930                 ironlake_fdi_pll_enable(intel_crtc);
3931         } else {
3932                 assert_fdi_tx_disabled(dev_priv, pipe);
3933                 assert_fdi_rx_disabled(dev_priv, pipe);
3934         }
3935
3936         ironlake_pfit_enable(intel_crtc);
3937
3938         /*
3939          * On ILK+ LUT must be loaded before the pipe is running but with
3940          * clocks enabled
3941          */
3942         intel_crtc_load_lut(crtc);
3943
3944         intel_update_watermarks(crtc);
3945         intel_enable_pipe(intel_crtc);
3946
3947         if (intel_crtc->config.has_pch_encoder)
3948                 ironlake_pch_enable(crtc);
3949
3950         for_each_encoder_on_crtc(dev, crtc, encoder)
3951                 encoder->enable(encoder);
3952
3953         if (HAS_PCH_CPT(dev))
3954                 cpt_verify_modeset(dev, intel_crtc->pipe);
3955
3956         intel_crtc_enable_planes(crtc);
3957
3958         /*
3959          * There seems to be a race in PCH platform hw (at least on some
3960          * outputs) where an enabled pipe still completes any pageflip right
3961          * away (as if the pipe is off) instead of waiting for vblank. As soon
3962          * as the first vblank happend, everything works as expected. Hence just
3963          * wait for one vblank before returning to avoid strange things
3964          * happening.
3965          */
3966         intel_wait_for_vblank(dev, intel_crtc->pipe);
3967 }
3968
3969 /* IPS only exists on ULT machines and is tied to pipe A. */
3970 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3971 {
3972         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3973 }
3974
3975 /*
3976  * This implements the workaround described in the "notes" section of the mode
3977  * set sequence documentation. When going from no pipes or single pipe to
3978  * multiple pipes, and planes are enabled after the pipe, we need to wait at
3979  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3980  */
3981 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3982 {
3983         struct drm_device *dev = crtc->base.dev;
3984         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3985
3986         /* We want to get the other_active_crtc only if there's only 1 other
3987          * active crtc. */
3988         for_each_intel_crtc(dev, crtc_it) {
3989                 if (!crtc_it->active || crtc_it == crtc)
3990                         continue;
3991
3992                 if (other_active_crtc)
3993                         return;
3994
3995                 other_active_crtc = crtc_it;
3996         }
3997         if (!other_active_crtc)
3998                 return;
3999
4000         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4001         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4002 }
4003
4004 static void haswell_crtc_enable(struct drm_crtc *crtc)
4005 {
4006         struct drm_device *dev = crtc->dev;
4007         struct drm_i915_private *dev_priv = dev->dev_private;
4008         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4009         struct intel_encoder *encoder;
4010         int pipe = intel_crtc->pipe;
4011
4012         WARN_ON(!crtc->enabled);
4013
4014         if (intel_crtc->active)
4015                 return;
4016
4017         intel_crtc->active = true;
4018
4019         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4020         if (intel_crtc->config.has_pch_encoder)
4021                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4022
4023         if (intel_crtc->config.has_pch_encoder)
4024                 dev_priv->display.fdi_link_train(crtc);
4025
4026         for_each_encoder_on_crtc(dev, crtc, encoder)
4027                 if (encoder->pre_enable)
4028                         encoder->pre_enable(encoder);
4029
4030         intel_ddi_enable_pipe_clock(intel_crtc);
4031
4032         ironlake_pfit_enable(intel_crtc);
4033
4034         /*
4035          * On ILK+ LUT must be loaded before the pipe is running but with
4036          * clocks enabled
4037          */
4038         intel_crtc_load_lut(crtc);
4039
4040         intel_ddi_set_pipe_settings(crtc);
4041         intel_ddi_enable_transcoder_func(crtc);
4042
4043         intel_update_watermarks(crtc);
4044         intel_enable_pipe(intel_crtc);
4045
4046         if (intel_crtc->config.has_pch_encoder)
4047                 lpt_pch_enable(crtc);
4048
4049         for_each_encoder_on_crtc(dev, crtc, encoder) {
4050                 encoder->enable(encoder);
4051                 intel_opregion_notify_encoder(encoder, true);
4052         }
4053
4054         /* If we change the relative order between pipe/planes enabling, we need
4055          * to change the workaround. */
4056         haswell_mode_set_planes_workaround(intel_crtc);
4057         intel_crtc_enable_planes(crtc);
4058 }
4059
4060 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4061 {
4062         struct drm_device *dev = crtc->base.dev;
4063         struct drm_i915_private *dev_priv = dev->dev_private;
4064         int pipe = crtc->pipe;
4065
4066         /* To avoid upsetting the power well on haswell only disable the pfit if
4067          * it's in use. The hw state code will make sure we get this right. */
4068         if (crtc->config.pch_pfit.enabled) {
4069                 I915_WRITE(PF_CTL(pipe), 0);
4070                 I915_WRITE(PF_WIN_POS(pipe), 0);
4071                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4072         }
4073 }
4074
4075 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4076 {
4077         struct drm_device *dev = crtc->dev;
4078         struct drm_i915_private *dev_priv = dev->dev_private;
4079         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4080         struct intel_encoder *encoder;
4081         int pipe = intel_crtc->pipe;
4082         u32 reg, temp;
4083
4084         if (!intel_crtc->active)
4085                 return;
4086
4087         intel_crtc_disable_planes(crtc);
4088
4089         for_each_encoder_on_crtc(dev, crtc, encoder)
4090                 encoder->disable(encoder);
4091
4092         if (intel_crtc->config.has_pch_encoder)
4093                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4094
4095         intel_disable_pipe(dev_priv, pipe);
4096
4097         ironlake_pfit_disable(intel_crtc);
4098
4099         for_each_encoder_on_crtc(dev, crtc, encoder)
4100                 if (encoder->post_disable)
4101                         encoder->post_disable(encoder);
4102
4103         if (intel_crtc->config.has_pch_encoder) {
4104                 ironlake_fdi_disable(crtc);
4105
4106                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4107                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4108
4109                 if (HAS_PCH_CPT(dev)) {
4110                         /* disable TRANS_DP_CTL */
4111                         reg = TRANS_DP_CTL(pipe);
4112                         temp = I915_READ(reg);
4113                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4114                                   TRANS_DP_PORT_SEL_MASK);
4115                         temp |= TRANS_DP_PORT_SEL_NONE;
4116                         I915_WRITE(reg, temp);
4117
4118                         /* disable DPLL_SEL */
4119                         temp = I915_READ(PCH_DPLL_SEL);
4120                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4121                         I915_WRITE(PCH_DPLL_SEL, temp);
4122                 }
4123
4124                 /* disable PCH DPLL */
4125                 intel_disable_shared_dpll(intel_crtc);
4126
4127                 ironlake_fdi_pll_disable(intel_crtc);
4128         }
4129
4130         intel_crtc->active = false;
4131         intel_update_watermarks(crtc);
4132
4133         mutex_lock(&dev->struct_mutex);
4134         intel_update_fbc(dev);
4135         intel_edp_psr_update(dev);
4136         mutex_unlock(&dev->struct_mutex);
4137 }
4138
4139 static void haswell_crtc_disable(struct drm_crtc *crtc)
4140 {
4141         struct drm_device *dev = crtc->dev;
4142         struct drm_i915_private *dev_priv = dev->dev_private;
4143         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4144         struct intel_encoder *encoder;
4145         int pipe = intel_crtc->pipe;
4146         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4147
4148         if (!intel_crtc->active)
4149                 return;
4150
4151         intel_crtc_disable_planes(crtc);
4152
4153         for_each_encoder_on_crtc(dev, crtc, encoder) {
4154                 intel_opregion_notify_encoder(encoder, false);
4155                 encoder->disable(encoder);
4156         }
4157
4158         if (intel_crtc->config.has_pch_encoder)
4159                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4160         intel_disable_pipe(dev_priv, pipe);
4161
4162         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4163
4164         ironlake_pfit_disable(intel_crtc);
4165
4166         intel_ddi_disable_pipe_clock(intel_crtc);
4167
4168         for_each_encoder_on_crtc(dev, crtc, encoder)
4169                 if (encoder->post_disable)
4170                         encoder->post_disable(encoder);
4171
4172         if (intel_crtc->config.has_pch_encoder) {
4173                 lpt_disable_pch_transcoder(dev_priv);
4174                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4175                 intel_ddi_fdi_disable(crtc);
4176         }
4177
4178         intel_crtc->active = false;
4179         intel_update_watermarks(crtc);
4180
4181         mutex_lock(&dev->struct_mutex);
4182         intel_update_fbc(dev);
4183         intel_edp_psr_update(dev);
4184         mutex_unlock(&dev->struct_mutex);
4185 }
4186
4187 static void ironlake_crtc_off(struct drm_crtc *crtc)
4188 {
4189         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4190         intel_put_shared_dpll(intel_crtc);
4191 }
4192
4193 static void haswell_crtc_off(struct drm_crtc *crtc)
4194 {
4195         intel_ddi_put_crtc_pll(crtc);
4196 }
4197
4198 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4199 {
4200         struct drm_device *dev = crtc->base.dev;
4201         struct drm_i915_private *dev_priv = dev->dev_private;
4202         struct intel_crtc_config *pipe_config = &crtc->config;
4203
4204         if (!crtc->config.gmch_pfit.control)
4205                 return;
4206
4207         /*
4208          * The panel fitter should only be adjusted whilst the pipe is disabled,
4209          * according to register description and PRM.
4210          */
4211         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4212         assert_pipe_disabled(dev_priv, crtc->pipe);
4213
4214         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4215         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4216
4217         /* Border color in case we don't scale up to the full screen. Black by
4218          * default, change to something else for debugging. */
4219         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4220 }
4221
4222 #define for_each_power_domain(domain, mask)                             \
4223         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4224                 if ((1 << (domain)) & (mask))
4225
4226 enum intel_display_power_domain
4227 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4228 {
4229         struct drm_device *dev = intel_encoder->base.dev;
4230         struct intel_digital_port *intel_dig_port;
4231
4232         switch (intel_encoder->type) {
4233         case INTEL_OUTPUT_UNKNOWN:
4234                 /* Only DDI platforms should ever use this output type */
4235                 WARN_ON_ONCE(!HAS_DDI(dev));
4236         case INTEL_OUTPUT_DISPLAYPORT:
4237         case INTEL_OUTPUT_HDMI:
4238         case INTEL_OUTPUT_EDP:
4239                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4240                 switch (intel_dig_port->port) {
4241                 case PORT_A:
4242                         return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4243                 case PORT_B:
4244                         return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4245                 case PORT_C:
4246                         return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4247                 case PORT_D:
4248                         return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4249                 default:
4250                         WARN_ON_ONCE(1);
4251                         return POWER_DOMAIN_PORT_OTHER;
4252                 }
4253         case INTEL_OUTPUT_ANALOG:
4254                 return POWER_DOMAIN_PORT_CRT;
4255         case INTEL_OUTPUT_DSI:
4256                 return POWER_DOMAIN_PORT_DSI;
4257         default:
4258                 return POWER_DOMAIN_PORT_OTHER;
4259         }
4260 }
4261
4262 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4263 {
4264         struct drm_device *dev = crtc->dev;
4265         struct intel_encoder *intel_encoder;
4266         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4267         enum pipe pipe = intel_crtc->pipe;
4268         bool pfit_enabled = intel_crtc->config.pch_pfit.enabled;
4269         unsigned long mask;
4270         enum transcoder transcoder;
4271
4272         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4273
4274         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4275         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4276         if (pfit_enabled)
4277                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4278
4279         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4280                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4281
4282         return mask;
4283 }
4284
4285 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4286                                   bool enable)
4287 {
4288         if (dev_priv->power_domains.init_power_on == enable)
4289                 return;
4290
4291         if (enable)
4292                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4293         else
4294                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4295
4296         dev_priv->power_domains.init_power_on = enable;
4297 }
4298
4299 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4300 {
4301         struct drm_i915_private *dev_priv = dev->dev_private;
4302         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4303         struct intel_crtc *crtc;
4304
4305         /*
4306          * First get all needed power domains, then put all unneeded, to avoid
4307          * any unnecessary toggling of the power wells.
4308          */
4309         for_each_intel_crtc(dev, crtc) {
4310                 enum intel_display_power_domain domain;
4311
4312                 if (!crtc->base.enabled)
4313                         continue;
4314
4315                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4316
4317                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4318                         intel_display_power_get(dev_priv, domain);
4319         }
4320
4321         for_each_intel_crtc(dev, crtc) {
4322                 enum intel_display_power_domain domain;
4323
4324                 for_each_power_domain(domain, crtc->enabled_power_domains)
4325                         intel_display_power_put(dev_priv, domain);
4326
4327                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4328         }
4329
4330         intel_display_set_init_power(dev_priv, false);
4331 }
4332
4333 int valleyview_get_vco(struct drm_i915_private *dev_priv)
4334 {
4335         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4336
4337         /* Obtain SKU information */
4338         mutex_lock(&dev_priv->dpio_lock);
4339         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4340                 CCK_FUSE_HPLL_FREQ_MASK;
4341         mutex_unlock(&dev_priv->dpio_lock);
4342
4343         return vco_freq[hpll_freq];
4344 }
4345
4346 /* Adjust CDclk dividers to allow high res or save power if possible */
4347 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4348 {
4349         struct drm_i915_private *dev_priv = dev->dev_private;
4350         u32 val, cmd;
4351
4352         WARN_ON(valleyview_cur_cdclk(dev_priv) != dev_priv->vlv_cdclk_freq);
4353         dev_priv->vlv_cdclk_freq = cdclk;
4354
4355         if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
4356                 cmd = 2;
4357         else if (cdclk == 266)
4358                 cmd = 1;
4359         else
4360                 cmd = 0;
4361
4362         mutex_lock(&dev_priv->rps.hw_lock);
4363         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4364         val &= ~DSPFREQGUAR_MASK;
4365         val |= (cmd << DSPFREQGUAR_SHIFT);
4366         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4367         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4368                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4369                      50)) {
4370                 DRM_ERROR("timed out waiting for CDclk change\n");
4371         }
4372         mutex_unlock(&dev_priv->rps.hw_lock);
4373
4374         if (cdclk == 400) {
4375                 u32 divider, vco;
4376
4377                 vco = valleyview_get_vco(dev_priv);
4378                 divider = ((vco << 1) / cdclk) - 1;
4379
4380                 mutex_lock(&dev_priv->dpio_lock);
4381                 /* adjust cdclk divider */
4382                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4383                 val &= ~0xf;
4384                 val |= divider;
4385                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4386                 mutex_unlock(&dev_priv->dpio_lock);
4387         }
4388
4389         mutex_lock(&dev_priv->dpio_lock);
4390         /* adjust self-refresh exit latency value */
4391         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4392         val &= ~0x7f;
4393
4394         /*
4395          * For high bandwidth configs, we set a higher latency in the bunit
4396          * so that the core display fetch happens in time to avoid underruns.
4397          */
4398         if (cdclk == 400)
4399                 val |= 4500 / 250; /* 4.5 usec */
4400         else
4401                 val |= 3000 / 250; /* 3.0 usec */
4402         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4403         mutex_unlock(&dev_priv->dpio_lock);
4404
4405         /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4406         intel_i2c_reset(dev);
4407 }
4408
4409 int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4410 {
4411         int cur_cdclk, vco;
4412         int divider;
4413
4414         vco = valleyview_get_vco(dev_priv);
4415
4416         mutex_lock(&dev_priv->dpio_lock);
4417         divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4418         mutex_unlock(&dev_priv->dpio_lock);
4419
4420         divider &= 0xf;
4421
4422         cur_cdclk = (vco << 1) / (divider + 1);
4423
4424         return cur_cdclk;
4425 }
4426
4427 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4428                                  int max_pixclk)
4429 {
4430         /*
4431          * Really only a few cases to deal with, as only 4 CDclks are supported:
4432          *   200MHz
4433          *   267MHz
4434          *   320MHz
4435          *   400MHz
4436          * So we check to see whether we're above 90% of the lower bin and
4437          * adjust if needed.
4438          */
4439         if (max_pixclk > 288000) {
4440                 return 400;
4441         } else if (max_pixclk > 240000) {
4442                 return 320;
4443         } else
4444                 return 266;
4445         /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4446 }
4447
4448 /* compute the max pixel clock for new configuration */
4449 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4450 {
4451         struct drm_device *dev = dev_priv->dev;
4452         struct intel_crtc *intel_crtc;
4453         int max_pixclk = 0;
4454
4455         for_each_intel_crtc(dev, intel_crtc) {
4456                 if (intel_crtc->new_enabled)
4457                         max_pixclk = max(max_pixclk,
4458                                          intel_crtc->new_config->adjusted_mode.crtc_clock);
4459         }
4460
4461         return max_pixclk;
4462 }
4463
4464 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4465                                             unsigned *prepare_pipes)
4466 {
4467         struct drm_i915_private *dev_priv = dev->dev_private;
4468         struct intel_crtc *intel_crtc;
4469         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4470
4471         if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4472             dev_priv->vlv_cdclk_freq)
4473                 return;
4474
4475         /* disable/enable all currently active pipes while we change cdclk */
4476         for_each_intel_crtc(dev, intel_crtc)
4477                 if (intel_crtc->base.enabled)
4478                         *prepare_pipes |= (1 << intel_crtc->pipe);
4479 }
4480
4481 static void valleyview_modeset_global_resources(struct drm_device *dev)
4482 {
4483         struct drm_i915_private *dev_priv = dev->dev_private;
4484         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4485         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4486
4487         if (req_cdclk != dev_priv->vlv_cdclk_freq)
4488                 valleyview_set_cdclk(dev, req_cdclk);
4489         modeset_update_crtc_power_domains(dev);
4490 }
4491
4492 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4493 {
4494         struct drm_device *dev = crtc->dev;
4495         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4496         struct intel_encoder *encoder;
4497         int pipe = intel_crtc->pipe;
4498         bool is_dsi;
4499
4500         WARN_ON(!crtc->enabled);
4501
4502         if (intel_crtc->active)
4503                 return;
4504
4505         intel_crtc->active = true;
4506
4507         for_each_encoder_on_crtc(dev, crtc, encoder)
4508                 if (encoder->pre_pll_enable)
4509                         encoder->pre_pll_enable(encoder);
4510
4511         is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4512
4513         if (!is_dsi) {
4514                 if (IS_CHERRYVIEW(dev))
4515                         chv_enable_pll(intel_crtc);
4516                 else
4517                         vlv_enable_pll(intel_crtc);
4518         }
4519
4520         for_each_encoder_on_crtc(dev, crtc, encoder)
4521                 if (encoder->pre_enable)
4522                         encoder->pre_enable(encoder);
4523
4524         i9xx_pfit_enable(intel_crtc);
4525
4526         intel_crtc_load_lut(crtc);
4527
4528         intel_update_watermarks(crtc);
4529         intel_enable_pipe(intel_crtc);
4530         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4531
4532         for_each_encoder_on_crtc(dev, crtc, encoder)
4533                 encoder->enable(encoder);
4534
4535         intel_crtc_enable_planes(crtc);
4536 }
4537
4538 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4539 {
4540         struct drm_device *dev = crtc->dev;
4541         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4542         struct intel_encoder *encoder;
4543         int pipe = intel_crtc->pipe;
4544
4545         WARN_ON(!crtc->enabled);
4546
4547         if (intel_crtc->active)
4548                 return;
4549
4550         intel_crtc->active = true;
4551
4552         for_each_encoder_on_crtc(dev, crtc, encoder)
4553                 if (encoder->pre_enable)
4554                         encoder->pre_enable(encoder);
4555
4556         i9xx_enable_pll(intel_crtc);
4557
4558         i9xx_pfit_enable(intel_crtc);
4559
4560         intel_crtc_load_lut(crtc);
4561
4562         intel_update_watermarks(crtc);
4563         intel_enable_pipe(intel_crtc);
4564         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4565
4566         for_each_encoder_on_crtc(dev, crtc, encoder)
4567                 encoder->enable(encoder);
4568
4569         intel_crtc_enable_planes(crtc);
4570 }
4571
4572 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4573 {
4574         struct drm_device *dev = crtc->base.dev;
4575         struct drm_i915_private *dev_priv = dev->dev_private;
4576
4577         if (!crtc->config.gmch_pfit.control)
4578                 return;
4579
4580         assert_pipe_disabled(dev_priv, crtc->pipe);
4581
4582         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4583                          I915_READ(PFIT_CONTROL));
4584         I915_WRITE(PFIT_CONTROL, 0);
4585 }
4586
4587 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4588 {
4589         struct drm_device *dev = crtc->dev;
4590         struct drm_i915_private *dev_priv = dev->dev_private;
4591         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4592         struct intel_encoder *encoder;
4593         int pipe = intel_crtc->pipe;
4594
4595         if (!intel_crtc->active)
4596                 return;
4597
4598         intel_crtc_disable_planes(crtc);
4599
4600         for_each_encoder_on_crtc(dev, crtc, encoder)
4601                 encoder->disable(encoder);
4602
4603         intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4604         intel_disable_pipe(dev_priv, pipe);
4605
4606         i9xx_pfit_disable(intel_crtc);
4607
4608         for_each_encoder_on_crtc(dev, crtc, encoder)
4609                 if (encoder->post_disable)
4610                         encoder->post_disable(encoder);
4611
4612         if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4613                 if (IS_CHERRYVIEW(dev))
4614                         chv_disable_pll(dev_priv, pipe);
4615                 else if (IS_VALLEYVIEW(dev))
4616                         vlv_disable_pll(dev_priv, pipe);
4617                 else
4618                         i9xx_disable_pll(dev_priv, pipe);
4619         }
4620
4621         intel_crtc->active = false;
4622         intel_update_watermarks(crtc);
4623
4624         mutex_lock(&dev->struct_mutex);
4625         intel_update_fbc(dev);
4626         intel_edp_psr_update(dev);
4627         mutex_unlock(&dev->struct_mutex);
4628 }
4629
4630 static void i9xx_crtc_off(struct drm_crtc *crtc)
4631 {
4632 }
4633
4634 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4635                                     bool enabled)
4636 {
4637         struct drm_device *dev = crtc->dev;
4638         struct drm_i915_master_private *master_priv;
4639         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4640         int pipe = intel_crtc->pipe;
4641
4642         if (!dev->primary->master)
4643                 return;
4644
4645         master_priv = dev->primary->master->driver_priv;
4646         if (!master_priv->sarea_priv)
4647                 return;
4648
4649         switch (pipe) {
4650         case 0:
4651                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4652                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4653                 break;
4654         case 1:
4655                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4656                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4657                 break;
4658         default:
4659                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4660                 break;
4661         }
4662 }
4663
4664 /**
4665  * Sets the power management mode of the pipe and plane.
4666  */
4667 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4668 {
4669         struct drm_device *dev = crtc->dev;
4670         struct drm_i915_private *dev_priv = dev->dev_private;
4671         struct intel_encoder *intel_encoder;
4672         bool enable = false;
4673
4674         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4675                 enable |= intel_encoder->connectors_active;
4676
4677         if (enable)
4678                 dev_priv->display.crtc_enable(crtc);
4679         else
4680                 dev_priv->display.crtc_disable(crtc);
4681
4682         intel_crtc_update_sarea(crtc, enable);
4683 }
4684
4685 static void intel_crtc_disable(struct drm_crtc *crtc)
4686 {
4687         struct drm_device *dev = crtc->dev;
4688         struct drm_connector *connector;
4689         struct drm_i915_private *dev_priv = dev->dev_private;
4690
4691         /* crtc should still be enabled when we disable it. */
4692         WARN_ON(!crtc->enabled);
4693
4694         dev_priv->display.crtc_disable(crtc);
4695         intel_crtc_update_sarea(crtc, false);
4696         dev_priv->display.off(crtc);
4697
4698         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4699         assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4700         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4701
4702         if (crtc->primary->fb) {
4703                 mutex_lock(&dev->struct_mutex);
4704                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->primary->fb)->obj);
4705                 mutex_unlock(&dev->struct_mutex);
4706                 crtc->primary->fb = NULL;
4707         }
4708
4709         /* Update computed state. */
4710         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4711                 if (!connector->encoder || !connector->encoder->crtc)
4712                         continue;
4713
4714                 if (connector->encoder->crtc != crtc)
4715                         continue;
4716
4717                 connector->dpms = DRM_MODE_DPMS_OFF;
4718                 to_intel_encoder(connector->encoder)->connectors_active = false;
4719         }
4720 }
4721
4722 void intel_encoder_destroy(struct drm_encoder *encoder)
4723 {
4724         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4725
4726         drm_encoder_cleanup(encoder);
4727         kfree(intel_encoder);
4728 }
4729
4730 /* Simple dpms helper for encoders with just one connector, no cloning and only
4731  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4732  * state of the entire output pipe. */
4733 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4734 {
4735         if (mode == DRM_MODE_DPMS_ON) {
4736                 encoder->connectors_active = true;
4737
4738                 intel_crtc_update_dpms(encoder->base.crtc);
4739         } else {
4740                 encoder->connectors_active = false;
4741
4742                 intel_crtc_update_dpms(encoder->base.crtc);
4743         }
4744 }
4745
4746 /* Cross check the actual hw state with our own modeset state tracking (and it's
4747  * internal consistency). */
4748 static void intel_connector_check_state(struct intel_connector *connector)
4749 {
4750         if (connector->get_hw_state(connector)) {
4751                 struct intel_encoder *encoder = connector->encoder;
4752                 struct drm_crtc *crtc;
4753                 bool encoder_enabled;
4754                 enum pipe pipe;
4755
4756                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4757                               connector->base.base.id,
4758                               drm_get_connector_name(&connector->base));
4759
4760                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4761                      "wrong connector dpms state\n");
4762                 WARN(connector->base.encoder != &encoder->base,
4763                      "active connector not linked to encoder\n");
4764                 WARN(!encoder->connectors_active,
4765                      "encoder->connectors_active not set\n");
4766
4767                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4768                 WARN(!encoder_enabled, "encoder not enabled\n");
4769                 if (WARN_ON(!encoder->base.crtc))
4770                         return;
4771
4772                 crtc = encoder->base.crtc;
4773
4774                 WARN(!crtc->enabled, "crtc not enabled\n");
4775                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4776                 WARN(pipe != to_intel_crtc(crtc)->pipe,
4777                      "encoder active on the wrong pipe\n");
4778         }
4779 }
4780
4781 /* Even simpler default implementation, if there's really no special case to
4782  * consider. */
4783 void intel_connector_dpms(struct drm_connector *connector, int mode)
4784 {
4785         /* All the simple cases only support two dpms states. */
4786         if (mode != DRM_MODE_DPMS_ON)
4787                 mode = DRM_MODE_DPMS_OFF;
4788
4789         if (mode == connector->dpms)
4790                 return;
4791
4792         connector->dpms = mode;
4793
4794         /* Only need to change hw state when actually enabled */
4795         if (connector->encoder)
4796                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
4797
4798         intel_modeset_check_state(connector->dev);
4799 }
4800
4801 /* Simple connector->get_hw_state implementation for encoders that support only
4802  * one connector and no cloning and hence the encoder state determines the state
4803  * of the connector. */
4804 bool intel_connector_get_hw_state(struct intel_connector *connector)
4805 {
4806         enum pipe pipe = 0;
4807         struct intel_encoder *encoder = connector->encoder;
4808
4809         return encoder->get_hw_state(encoder, &pipe);
4810 }
4811
4812 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4813                                      struct intel_crtc_config *pipe_config)
4814 {
4815         struct drm_i915_private *dev_priv = dev->dev_private;
4816         struct intel_crtc *pipe_B_crtc =
4817                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4818
4819         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4820                       pipe_name(pipe), pipe_config->fdi_lanes);
4821         if (pipe_config->fdi_lanes > 4) {
4822                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4823                               pipe_name(pipe), pipe_config->fdi_lanes);
4824                 return false;
4825         }
4826
4827         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4828                 if (pipe_config->fdi_lanes > 2) {
4829                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4830                                       pipe_config->fdi_lanes);
4831                         return false;
4832                 } else {
4833                         return true;
4834                 }
4835         }
4836
4837         if (INTEL_INFO(dev)->num_pipes == 2)
4838                 return true;
4839
4840         /* Ivybridge 3 pipe is really complicated */
4841         switch (pipe) {
4842         case PIPE_A:
4843                 return true;
4844         case PIPE_B:
4845                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4846                     pipe_config->fdi_lanes > 2) {
4847                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4848                                       pipe_name(pipe), pipe_config->fdi_lanes);
4849                         return false;
4850                 }
4851                 return true;
4852         case PIPE_C:
4853                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4854                     pipe_B_crtc->config.fdi_lanes <= 2) {
4855                         if (pipe_config->fdi_lanes > 2) {
4856                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4857                                               pipe_name(pipe), pipe_config->fdi_lanes);
4858                                 return false;
4859                         }
4860                 } else {
4861                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4862                         return false;
4863                 }
4864                 return true;
4865         default:
4866                 BUG();
4867         }
4868 }
4869
4870 #define RETRY 1
4871 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4872                                        struct intel_crtc_config *pipe_config)
4873 {
4874         struct drm_device *dev = intel_crtc->base.dev;
4875         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4876         int lane, link_bw, fdi_dotclock;
4877         bool setup_ok, needs_recompute = false;
4878
4879 retry:
4880         /* FDI is a binary signal running at ~2.7GHz, encoding
4881          * each output octet as 10 bits. The actual frequency
4882          * is stored as a divider into a 100MHz clock, and the
4883          * mode pixel clock is stored in units of 1KHz.
4884          * Hence the bw of each lane in terms of the mode signal
4885          * is:
4886          */
4887         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4888
4889         fdi_dotclock = adjusted_mode->crtc_clock;
4890
4891         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4892                                            pipe_config->pipe_bpp);
4893
4894         pipe_config->fdi_lanes = lane;
4895
4896         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4897                                link_bw, &pipe_config->fdi_m_n);
4898
4899         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4900                                             intel_crtc->pipe, pipe_config);
4901         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4902                 pipe_config->pipe_bpp -= 2*3;
4903                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4904                               pipe_config->pipe_bpp);
4905                 needs_recompute = true;
4906                 pipe_config->bw_constrained = true;
4907
4908                 goto retry;
4909         }
4910
4911         if (needs_recompute)
4912                 return RETRY;
4913
4914         return setup_ok ? 0 : -EINVAL;
4915 }
4916
4917 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4918                                    struct intel_crtc_config *pipe_config)
4919 {
4920         pipe_config->ips_enabled = i915.enable_ips &&
4921                                    hsw_crtc_supports_ips(crtc) &&
4922                                    pipe_config->pipe_bpp <= 24;
4923 }
4924
4925 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4926                                      struct intel_crtc_config *pipe_config)
4927 {
4928         struct drm_device *dev = crtc->base.dev;
4929         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4930
4931         /* FIXME should check pixel clock limits on all platforms */
4932         if (INTEL_INFO(dev)->gen < 4) {
4933                 struct drm_i915_private *dev_priv = dev->dev_private;
4934                 int clock_limit =
4935                         dev_priv->display.get_display_clock_speed(dev);
4936
4937                 /*
4938                  * Enable pixel doubling when the dot clock
4939                  * is > 90% of the (display) core speed.
4940                  *
4941                  * GDG double wide on either pipe,
4942                  * otherwise pipe A only.
4943                  */
4944                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4945                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
4946                         clock_limit *= 2;
4947                         pipe_config->double_wide = true;
4948                 }
4949
4950                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
4951                         return -EINVAL;
4952         }
4953
4954         /*
4955          * Pipe horizontal size must be even in:
4956          * - DVO ganged mode
4957          * - LVDS dual channel mode
4958          * - Double wide pipe
4959          */
4960         if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4961              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4962                 pipe_config->pipe_src_w &= ~1;
4963
4964         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4965          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4966          */
4967         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4968                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4969                 return -EINVAL;
4970
4971         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4972                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4973         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4974                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4975                  * for lvds. */
4976                 pipe_config->pipe_bpp = 8*3;
4977         }
4978
4979         if (HAS_IPS(dev))
4980                 hsw_compute_ips_config(crtc, pipe_config);
4981
4982         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4983          * clock survives for now. */
4984         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4985                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4986
4987         if (pipe_config->has_pch_encoder)
4988                 return ironlake_fdi_compute_config(crtc, pipe_config);
4989
4990         return 0;
4991 }
4992
4993 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4994 {
4995         return 400000; /* FIXME */
4996 }
4997
4998 static int i945_get_display_clock_speed(struct drm_device *dev)
4999 {
5000         return 400000;
5001 }
5002
5003 static int i915_get_display_clock_speed(struct drm_device *dev)
5004 {
5005         return 333000;
5006 }
5007
5008 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5009 {
5010         return 200000;
5011 }
5012
5013 static int pnv_get_display_clock_speed(struct drm_device *dev)
5014 {
5015         u16 gcfgc = 0;
5016
5017         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5018
5019         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5020         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5021                 return 267000;
5022         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5023                 return 333000;
5024         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5025                 return 444000;
5026         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5027                 return 200000;
5028         default:
5029                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5030         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5031                 return 133000;
5032         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5033                 return 167000;
5034         }
5035 }
5036
5037 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5038 {
5039         u16 gcfgc = 0;
5040
5041         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5042
5043         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5044                 return 133000;
5045         else {
5046                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5047                 case GC_DISPLAY_CLOCK_333_MHZ:
5048                         return 333000;
5049                 default:
5050                 case GC_DISPLAY_CLOCK_190_200_MHZ:
5051                         return 190000;
5052                 }
5053         }
5054 }
5055
5056 static int i865_get_display_clock_speed(struct drm_device *dev)
5057 {
5058         return 266000;
5059 }
5060
5061 static int i855_get_display_clock_speed(struct drm_device *dev)
5062 {
5063         u16 hpllcc = 0;
5064         /* Assume that the hardware is in the high speed state.  This
5065          * should be the default.
5066          */
5067         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5068         case GC_CLOCK_133_200:
5069         case GC_CLOCK_100_200:
5070                 return 200000;
5071         case GC_CLOCK_166_250:
5072                 return 250000;
5073         case GC_CLOCK_100_133:
5074                 return 133000;
5075         }
5076
5077         /* Shouldn't happen */
5078         return 0;
5079 }
5080
5081 static int i830_get_display_clock_speed(struct drm_device *dev)
5082 {
5083         return 133000;
5084 }
5085
5086 static void
5087 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5088 {
5089         while (*num > DATA_LINK_M_N_MASK ||
5090                *den > DATA_LINK_M_N_MASK) {
5091                 *num >>= 1;
5092                 *den >>= 1;
5093         }
5094 }
5095
5096 static void compute_m_n(unsigned int m, unsigned int n,
5097                         uint32_t *ret_m, uint32_t *ret_n)
5098 {
5099         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5100         *ret_m = div_u64((uint64_t) m * *ret_n, n);
5101         intel_reduce_m_n_ratio(ret_m, ret_n);
5102 }
5103
5104 void
5105 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5106                        int pixel_clock, int link_clock,
5107                        struct intel_link_m_n *m_n)
5108 {
5109         m_n->tu = 64;
5110
5111         compute_m_n(bits_per_pixel * pixel_clock,
5112                     link_clock * nlanes * 8,
5113                     &m_n->gmch_m, &m_n->gmch_n);
5114
5115         compute_m_n(pixel_clock, link_clock,
5116                     &m_n->link_m, &m_n->link_n);
5117 }
5118
5119 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5120 {
5121         if (i915.panel_use_ssc >= 0)
5122                 return i915.panel_use_ssc != 0;
5123         return dev_priv->vbt.lvds_use_ssc
5124                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5125 }
5126
5127 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5128 {
5129         struct drm_device *dev = crtc->dev;
5130         struct drm_i915_private *dev_priv = dev->dev_private;
5131         int refclk;
5132
5133         if (IS_VALLEYVIEW(dev)) {
5134                 refclk = 100000;
5135         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5136             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5137                 refclk = dev_priv->vbt.lvds_ssc_freq;
5138                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5139         } else if (!IS_GEN2(dev)) {
5140                 refclk = 96000;
5141         } else {
5142                 refclk = 48000;
5143         }
5144
5145         return refclk;
5146 }
5147
5148 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5149 {
5150         return (1 << dpll->n) << 16 | dpll->m2;
5151 }
5152
5153 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5154 {
5155         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5156 }
5157
5158 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5159                                      intel_clock_t *reduced_clock)
5160 {
5161         struct drm_device *dev = crtc->base.dev;
5162         struct drm_i915_private *dev_priv = dev->dev_private;
5163         int pipe = crtc->pipe;
5164         u32 fp, fp2 = 0;
5165
5166         if (IS_PINEVIEW(dev)) {
5167                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5168                 if (reduced_clock)
5169                         fp2 = pnv_dpll_compute_fp(reduced_clock);
5170         } else {
5171                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5172                 if (reduced_clock)
5173                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
5174         }
5175
5176         I915_WRITE(FP0(pipe), fp);
5177         crtc->config.dpll_hw_state.fp0 = fp;
5178
5179         crtc->lowfreq_avail = false;
5180         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5181             reduced_clock && i915.powersave) {
5182                 I915_WRITE(FP1(pipe), fp2);
5183                 crtc->config.dpll_hw_state.fp1 = fp2;
5184                 crtc->lowfreq_avail = true;
5185         } else {
5186                 I915_WRITE(FP1(pipe), fp);
5187                 crtc->config.dpll_hw_state.fp1 = fp;
5188         }
5189 }
5190
5191 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5192                 pipe)
5193 {
5194         u32 reg_val;
5195
5196         /*
5197          * PLLB opamp always calibrates to max value of 0x3f, force enable it
5198          * and set it to a reasonable value instead.
5199          */
5200         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5201         reg_val &= 0xffffff00;
5202         reg_val |= 0x00000030;
5203         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5204
5205         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5206         reg_val &= 0x8cffffff;
5207         reg_val = 0x8c000000;
5208         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5209
5210         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5211         reg_val &= 0xffffff00;
5212         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5213
5214         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5215         reg_val &= 0x00ffffff;
5216         reg_val |= 0xb0000000;
5217         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5218 }
5219
5220 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5221                                          struct intel_link_m_n *m_n)
5222 {
5223         struct drm_device *dev = crtc->base.dev;
5224         struct drm_i915_private *dev_priv = dev->dev_private;
5225         int pipe = crtc->pipe;
5226
5227         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5228         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5229         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5230         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5231 }
5232
5233 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5234                                          struct intel_link_m_n *m_n)
5235 {
5236         struct drm_device *dev = crtc->base.dev;
5237         struct drm_i915_private *dev_priv = dev->dev_private;
5238         int pipe = crtc->pipe;
5239         enum transcoder transcoder = crtc->config.cpu_transcoder;
5240
5241         if (INTEL_INFO(dev)->gen >= 5) {
5242                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5243                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5244                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5245                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5246         } else {
5247                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5248                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5249                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5250                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5251         }
5252 }
5253
5254 static void intel_dp_set_m_n(struct intel_crtc *crtc)
5255 {
5256         if (crtc->config.has_pch_encoder)
5257                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5258         else
5259                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5260 }
5261
5262 static void vlv_update_pll(struct intel_crtc *crtc)
5263 {
5264         struct drm_device *dev = crtc->base.dev;
5265         struct drm_i915_private *dev_priv = dev->dev_private;
5266         int pipe = crtc->pipe;
5267         u32 dpll, mdiv;
5268         u32 bestn, bestm1, bestm2, bestp1, bestp2;
5269         u32 coreclk, reg_val, dpll_md;
5270
5271         mutex_lock(&dev_priv->dpio_lock);
5272
5273         bestn = crtc->config.dpll.n;
5274         bestm1 = crtc->config.dpll.m1;
5275         bestm2 = crtc->config.dpll.m2;
5276         bestp1 = crtc->config.dpll.p1;
5277         bestp2 = crtc->config.dpll.p2;
5278
5279         /* See eDP HDMI DPIO driver vbios notes doc */
5280
5281         /* PLL B needs special handling */
5282         if (pipe)
5283                 vlv_pllb_recal_opamp(dev_priv, pipe);
5284
5285         /* Set up Tx target for periodic Rcomp update */
5286         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5287
5288         /* Disable target IRef on PLL */
5289         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5290         reg_val &= 0x00ffffff;
5291         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5292
5293         /* Disable fast lock */
5294         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5295
5296         /* Set idtafcrecal before PLL is enabled */
5297         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5298         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5299         mdiv |= ((bestn << DPIO_N_SHIFT));
5300         mdiv |= (1 << DPIO_K_SHIFT);
5301
5302         /*
5303          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5304          * but we don't support that).
5305          * Note: don't use the DAC post divider as it seems unstable.
5306          */
5307         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5308         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5309
5310         mdiv |= DPIO_ENABLE_CALIBRATION;
5311         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5312
5313         /* Set HBR and RBR LPF coefficients */
5314         if (crtc->config.port_clock == 162000 ||
5315             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5316             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5317                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5318                                  0x009f0003);
5319         else
5320                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5321                                  0x00d0000f);
5322
5323         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5324             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5325                 /* Use SSC source */
5326                 if (!pipe)
5327                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5328                                          0x0df40000);
5329                 else
5330                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5331                                          0x0df70000);
5332         } else { /* HDMI or VGA */
5333                 /* Use bend source */
5334                 if (!pipe)
5335                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5336                                          0x0df70000);
5337                 else
5338                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5339                                          0x0df40000);
5340         }
5341
5342         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5343         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5344         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5345             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5346                 coreclk |= 0x01000000;
5347         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5348
5349         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5350
5351         /*
5352          * Enable DPIO clock input. We should never disable the reference
5353          * clock for pipe B, since VGA hotplug / manual detection depends
5354          * on it.
5355          */
5356         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5357                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5358         /* We should never disable this, set it here for state tracking */
5359         if (pipe == PIPE_B)
5360                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5361         dpll |= DPLL_VCO_ENABLE;
5362         crtc->config.dpll_hw_state.dpll = dpll;
5363
5364         dpll_md = (crtc->config.pixel_multiplier - 1)
5365                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5366         crtc->config.dpll_hw_state.dpll_md = dpll_md;
5367
5368         mutex_unlock(&dev_priv->dpio_lock);
5369 }
5370
5371 static void chv_update_pll(struct intel_crtc *crtc)
5372 {
5373         struct drm_device *dev = crtc->base.dev;
5374         struct drm_i915_private *dev_priv = dev->dev_private;
5375         int pipe = crtc->pipe;
5376         int dpll_reg = DPLL(crtc->pipe);
5377         enum dpio_channel port = vlv_pipe_to_channel(pipe);
5378         u32 val, loopfilter, intcoeff;
5379         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5380         int refclk;
5381
5382         mutex_lock(&dev_priv->dpio_lock);
5383
5384         bestn = crtc->config.dpll.n;
5385         bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5386         bestm1 = crtc->config.dpll.m1;
5387         bestm2 = crtc->config.dpll.m2 >> 22;
5388         bestp1 = crtc->config.dpll.p1;
5389         bestp2 = crtc->config.dpll.p2;
5390
5391         /*
5392          * Enable Refclk and SSC
5393          */
5394         val = I915_READ(dpll_reg);
5395         val |= (DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV);
5396         I915_WRITE(dpll_reg, val);
5397
5398         /* Propagate soft reset to data lane reset */
5399         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(port));
5400         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
5401         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), val);
5402
5403         /* Disable 10bit clock to display controller */
5404         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
5405         val &= ~DPIO_DCLKP_EN;
5406         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
5407
5408         /* p1 and p2 divider */
5409         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5410                         5 << DPIO_CHV_S1_DIV_SHIFT |
5411                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5412                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5413                         1 << DPIO_CHV_K_DIV_SHIFT);
5414
5415         /* Feedback post-divider - m2 */
5416         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5417
5418         /* Feedback refclk divider - n and m1 */
5419         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5420                         DPIO_CHV_M1_DIV_BY_2 |
5421                         1 << DPIO_CHV_N_DIV_SHIFT);
5422
5423         /* M2 fraction division */
5424         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5425
5426         /* M2 fraction division enable */
5427         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5428                        DPIO_CHV_FRAC_DIV_EN |
5429                        (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5430
5431         /* Loop filter */
5432         refclk = i9xx_get_refclk(&crtc->base, 0);
5433         loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5434                 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5435         if (refclk == 100000)
5436                 intcoeff = 11;
5437         else if (refclk == 38400)
5438                 intcoeff = 10;
5439         else
5440                 intcoeff = 9;
5441         loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5442         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5443
5444         /* AFC Recal */
5445         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5446                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5447                         DPIO_AFC_RECAL);
5448
5449         mutex_unlock(&dev_priv->dpio_lock);
5450 }
5451
5452 static void i9xx_update_pll(struct intel_crtc *crtc,
5453                             intel_clock_t *reduced_clock,
5454                             int num_connectors)
5455 {
5456         struct drm_device *dev = crtc->base.dev;
5457         struct drm_i915_private *dev_priv = dev->dev_private;
5458         u32 dpll;
5459         bool is_sdvo;
5460         struct dpll *clock = &crtc->config.dpll;
5461
5462         i9xx_update_pll_dividers(crtc, reduced_clock);
5463
5464         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5465                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5466
5467         dpll = DPLL_VGA_MODE_DIS;
5468
5469         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5470                 dpll |= DPLLB_MODE_LVDS;
5471         else
5472                 dpll |= DPLLB_MODE_DAC_SERIAL;
5473
5474         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5475                 dpll |= (crtc->config.pixel_multiplier - 1)
5476                         << SDVO_MULTIPLIER_SHIFT_HIRES;
5477         }
5478
5479         if (is_sdvo)
5480                 dpll |= DPLL_SDVO_HIGH_SPEED;
5481
5482         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5483                 dpll |= DPLL_SDVO_HIGH_SPEED;
5484
5485         /* compute bitmask from p1 value */
5486         if (IS_PINEVIEW(dev))
5487                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5488         else {
5489                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5490                 if (IS_G4X(dev) && reduced_clock)
5491                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5492         }
5493         switch (clock->p2) {
5494         case 5:
5495                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5496                 break;
5497         case 7:
5498                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5499                 break;
5500         case 10:
5501                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5502                 break;
5503         case 14:
5504                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5505                 break;
5506         }
5507         if (INTEL_INFO(dev)->gen >= 4)
5508                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5509
5510         if (crtc->config.sdvo_tv_clock)
5511                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5512         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5513                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5514                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5515         else
5516                 dpll |= PLL_REF_INPUT_DREFCLK;
5517
5518         dpll |= DPLL_VCO_ENABLE;
5519         crtc->config.dpll_hw_state.dpll = dpll;
5520
5521         if (INTEL_INFO(dev)->gen >= 4) {
5522                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5523                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5524                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5525         }
5526 }
5527
5528 static void i8xx_update_pll(struct intel_crtc *crtc,
5529                             intel_clock_t *reduced_clock,
5530                             int num_connectors)
5531 {
5532         struct drm_device *dev = crtc->base.dev;
5533         struct drm_i915_private *dev_priv = dev->dev_private;
5534         u32 dpll;
5535         struct dpll *clock = &crtc->config.dpll;
5536
5537         i9xx_update_pll_dividers(crtc, reduced_clock);
5538
5539         dpll = DPLL_VGA_MODE_DIS;
5540
5541         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5542                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5543         } else {
5544                 if (clock->p1 == 2)
5545                         dpll |= PLL_P1_DIVIDE_BY_TWO;
5546                 else
5547                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5548                 if (clock->p2 == 4)
5549                         dpll |= PLL_P2_DIVIDE_BY_4;
5550         }
5551
5552         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5553                 dpll |= DPLL_DVO_2X_MODE;
5554
5555         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5556                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5557                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5558         else
5559                 dpll |= PLL_REF_INPUT_DREFCLK;
5560
5561         dpll |= DPLL_VCO_ENABLE;
5562         crtc->config.dpll_hw_state.dpll = dpll;
5563 }
5564
5565 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5566 {
5567         struct drm_device *dev = intel_crtc->base.dev;
5568         struct drm_i915_private *dev_priv = dev->dev_private;
5569         enum pipe pipe = intel_crtc->pipe;
5570         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5571         struct drm_display_mode *adjusted_mode =
5572                 &intel_crtc->config.adjusted_mode;
5573         uint32_t crtc_vtotal, crtc_vblank_end;
5574         int vsyncshift = 0;
5575
5576         /* We need to be careful not to changed the adjusted mode, for otherwise
5577          * the hw state checker will get angry at the mismatch. */
5578         crtc_vtotal = adjusted_mode->crtc_vtotal;
5579         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5580
5581         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5582                 /* the chip adds 2 halflines automatically */
5583                 crtc_vtotal -= 1;
5584                 crtc_vblank_end -= 1;
5585
5586                 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5587                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5588                 else
5589                         vsyncshift = adjusted_mode->crtc_hsync_start -
5590                                 adjusted_mode->crtc_htotal / 2;
5591                 if (vsyncshift < 0)
5592                         vsyncshift += adjusted_mode->crtc_htotal;
5593         }
5594
5595         if (INTEL_INFO(dev)->gen > 3)
5596                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5597
5598         I915_WRITE(HTOTAL(cpu_transcoder),
5599                    (adjusted_mode->crtc_hdisplay - 1) |
5600                    ((adjusted_mode->crtc_htotal - 1) << 16));
5601         I915_WRITE(HBLANK(cpu_transcoder),
5602                    (adjusted_mode->crtc_hblank_start - 1) |
5603                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5604         I915_WRITE(HSYNC(cpu_transcoder),
5605                    (adjusted_mode->crtc_hsync_start - 1) |
5606                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5607
5608         I915_WRITE(VTOTAL(cpu_transcoder),
5609                    (adjusted_mode->crtc_vdisplay - 1) |
5610                    ((crtc_vtotal - 1) << 16));
5611         I915_WRITE(VBLANK(cpu_transcoder),
5612                    (adjusted_mode->crtc_vblank_start - 1) |
5613                    ((crtc_vblank_end - 1) << 16));
5614         I915_WRITE(VSYNC(cpu_transcoder),
5615                    (adjusted_mode->crtc_vsync_start - 1) |
5616                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5617
5618         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5619          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5620          * documented on the DDI_FUNC_CTL register description, EDP Input Select
5621          * bits. */
5622         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5623             (pipe == PIPE_B || pipe == PIPE_C))
5624                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5625
5626         /* pipesrc controls the size that is scaled from, which should
5627          * always be the user's requested size.
5628          */
5629         I915_WRITE(PIPESRC(pipe),
5630                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
5631                    (intel_crtc->config.pipe_src_h - 1));
5632 }
5633
5634 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5635                                    struct intel_crtc_config *pipe_config)
5636 {
5637         struct drm_device *dev = crtc->base.dev;
5638         struct drm_i915_private *dev_priv = dev->dev_private;
5639         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5640         uint32_t tmp;
5641
5642         tmp = I915_READ(HTOTAL(cpu_transcoder));
5643         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5644         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5645         tmp = I915_READ(HBLANK(cpu_transcoder));
5646         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5647         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5648         tmp = I915_READ(HSYNC(cpu_transcoder));
5649         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5650         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5651
5652         tmp = I915_READ(VTOTAL(cpu_transcoder));
5653         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5654         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5655         tmp = I915_READ(VBLANK(cpu_transcoder));
5656         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5657         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5658         tmp = I915_READ(VSYNC(cpu_transcoder));
5659         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5660         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5661
5662         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5663                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5664                 pipe_config->adjusted_mode.crtc_vtotal += 1;
5665                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5666         }
5667
5668         tmp = I915_READ(PIPESRC(crtc->pipe));
5669         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5670         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5671
5672         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5673         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5674 }
5675
5676 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5677                                  struct intel_crtc_config *pipe_config)
5678 {
5679         mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5680         mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5681         mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5682         mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5683
5684         mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5685         mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5686         mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5687         mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5688
5689         mode->flags = pipe_config->adjusted_mode.flags;
5690
5691         mode->clock = pipe_config->adjusted_mode.crtc_clock;
5692         mode->flags |= pipe_config->adjusted_mode.flags;
5693 }
5694
5695 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5696 {
5697         struct drm_device *dev = intel_crtc->base.dev;
5698         struct drm_i915_private *dev_priv = dev->dev_private;
5699         uint32_t pipeconf;
5700
5701         pipeconf = 0;
5702
5703         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5704             I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5705                 pipeconf |= PIPECONF_ENABLE;
5706
5707         if (intel_crtc->config.double_wide)
5708                 pipeconf |= PIPECONF_DOUBLE_WIDE;
5709
5710         /* only g4x and later have fancy bpc/dither controls */
5711         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5712                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5713                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5714                         pipeconf |= PIPECONF_DITHER_EN |
5715                                     PIPECONF_DITHER_TYPE_SP;
5716
5717                 switch (intel_crtc->config.pipe_bpp) {
5718                 case 18:
5719                         pipeconf |= PIPECONF_6BPC;
5720                         break;
5721                 case 24:
5722                         pipeconf |= PIPECONF_8BPC;
5723                         break;
5724                 case 30:
5725                         pipeconf |= PIPECONF_10BPC;
5726                         break;
5727                 default:
5728                         /* Case prevented by intel_choose_pipe_bpp_dither. */
5729                         BUG();
5730                 }
5731         }
5732
5733         if (HAS_PIPE_CXSR(dev)) {
5734                 if (intel_crtc->lowfreq_avail) {
5735                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5736                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5737                 } else {
5738                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5739                 }
5740         }
5741
5742         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
5743                 if (INTEL_INFO(dev)->gen < 4 ||
5744                     intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5745                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5746                 else
5747                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
5748         } else
5749                 pipeconf |= PIPECONF_PROGRESSIVE;
5750
5751         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5752                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5753
5754         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5755         POSTING_READ(PIPECONF(intel_crtc->pipe));
5756 }
5757
5758 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5759                               int x, int y,
5760                               struct drm_framebuffer *fb)
5761 {
5762         struct drm_device *dev = crtc->dev;
5763         struct drm_i915_private *dev_priv = dev->dev_private;
5764         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5765         int pipe = intel_crtc->pipe;
5766         int plane = intel_crtc->plane;
5767         int refclk, num_connectors = 0;
5768         intel_clock_t clock, reduced_clock;
5769         u32 dspcntr;
5770         bool ok, has_reduced_clock = false;
5771         bool is_lvds = false, is_dsi = false;
5772         struct intel_encoder *encoder;
5773         const intel_limit_t *limit;
5774         struct drm_framebuffer *old_fb;
5775         int ret;
5776
5777         for_each_encoder_on_crtc(dev, crtc, encoder) {
5778                 switch (encoder->type) {
5779                 case INTEL_OUTPUT_LVDS:
5780                         is_lvds = true;
5781                         break;
5782                 case INTEL_OUTPUT_DSI:
5783                         is_dsi = true;
5784                         break;
5785                 }
5786
5787                 num_connectors++;
5788         }
5789
5790         if (is_dsi)
5791                 goto skip_dpll;
5792
5793         if (!intel_crtc->config.clock_set) {
5794                 refclk = i9xx_get_refclk(crtc, num_connectors);
5795
5796                 /*
5797                  * Returns a set of divisors for the desired target clock with
5798                  * the given refclk, or FALSE.  The returned values represent
5799                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5800                  * 2) / p1 / p2.
5801                  */
5802                 limit = intel_limit(crtc, refclk);
5803                 ok = dev_priv->display.find_dpll(limit, crtc,
5804                                                  intel_crtc->config.port_clock,
5805                                                  refclk, NULL, &clock);
5806                 if (!ok) {
5807                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5808                         return -EINVAL;
5809                 }
5810
5811                 if (is_lvds && dev_priv->lvds_downclock_avail) {
5812                         /*
5813                          * Ensure we match the reduced clock's P to the target
5814                          * clock.  If the clocks don't match, we can't switch
5815                          * the display clock by using the FP0/FP1. In such case
5816                          * we will disable the LVDS downclock feature.
5817                          */
5818                         has_reduced_clock =
5819                                 dev_priv->display.find_dpll(limit, crtc,
5820                                                             dev_priv->lvds_downclock,
5821                                                             refclk, &clock,
5822                                                             &reduced_clock);
5823                 }
5824                 /* Compat-code for transition, will disappear. */
5825                 intel_crtc->config.dpll.n = clock.n;
5826                 intel_crtc->config.dpll.m1 = clock.m1;
5827                 intel_crtc->config.dpll.m2 = clock.m2;
5828                 intel_crtc->config.dpll.p1 = clock.p1;
5829                 intel_crtc->config.dpll.p2 = clock.p2;
5830         }
5831
5832         if (IS_GEN2(dev)) {
5833                 i8xx_update_pll(intel_crtc,
5834                                 has_reduced_clock ? &reduced_clock : NULL,
5835                                 num_connectors);
5836         } else if (IS_CHERRYVIEW(dev)) {
5837                 chv_update_pll(intel_crtc);
5838         } else if (IS_VALLEYVIEW(dev)) {
5839                 vlv_update_pll(intel_crtc);
5840         } else {
5841                 i9xx_update_pll(intel_crtc,
5842                                 has_reduced_clock ? &reduced_clock : NULL,
5843                                 num_connectors);
5844         }
5845
5846 skip_dpll:
5847         /* Set up the display plane register */
5848         dspcntr = DISPPLANE_GAMMA_ENABLE;
5849
5850         if (!IS_VALLEYVIEW(dev)) {
5851                 if (pipe == 0)
5852                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5853                 else
5854                         dspcntr |= DISPPLANE_SEL_PIPE_B;
5855         }
5856
5857         if (intel_crtc->config.has_dp_encoder)
5858                 intel_dp_set_m_n(intel_crtc);
5859
5860         intel_set_pipe_timings(intel_crtc);
5861
5862         /* pipesrc and dspsize control the size that is scaled from,
5863          * which should always be the user's requested size.
5864          */
5865         I915_WRITE(DSPSIZE(plane),
5866                    ((intel_crtc->config.pipe_src_h - 1) << 16) |
5867                    (intel_crtc->config.pipe_src_w - 1));
5868         I915_WRITE(DSPPOS(plane), 0);
5869
5870         i9xx_set_pipeconf(intel_crtc);
5871
5872         I915_WRITE(DSPCNTR(plane), dspcntr);
5873         POSTING_READ(DSPCNTR(plane));
5874
5875         mutex_lock(&dev->struct_mutex);
5876         ret = intel_pin_and_fence_fb_obj(dev,
5877                                          to_intel_framebuffer(fb)->obj,
5878                                          NULL);
5879         if (ret != 0) {
5880                 DRM_ERROR("pin & fence failed\n");
5881                 mutex_unlock(&dev->struct_mutex);
5882                 return ret;
5883         }
5884         old_fb = crtc->primary->fb;
5885         if (old_fb)
5886                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
5887         mutex_unlock(&dev->struct_mutex);
5888
5889         dev_priv->display.update_primary_plane(crtc, fb, x, y);
5890
5891         crtc->primary->fb = fb;
5892         crtc->x = x;
5893         crtc->y = y;
5894
5895         return 0;
5896 }
5897
5898 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5899                                  struct intel_crtc_config *pipe_config)
5900 {
5901         struct drm_device *dev = crtc->base.dev;
5902         struct drm_i915_private *dev_priv = dev->dev_private;
5903         uint32_t tmp;
5904
5905         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
5906                 return;
5907
5908         tmp = I915_READ(PFIT_CONTROL);
5909         if (!(tmp & PFIT_ENABLE))
5910                 return;
5911
5912         /* Check whether the pfit is attached to our pipe. */
5913         if (INTEL_INFO(dev)->gen < 4) {
5914                 if (crtc->pipe != PIPE_B)
5915                         return;
5916         } else {
5917                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5918                         return;
5919         }
5920
5921         pipe_config->gmch_pfit.control = tmp;
5922         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5923         if (INTEL_INFO(dev)->gen < 5)
5924                 pipe_config->gmch_pfit.lvds_border_bits =
5925                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5926 }
5927
5928 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5929                                struct intel_crtc_config *pipe_config)
5930 {
5931         struct drm_device *dev = crtc->base.dev;
5932         struct drm_i915_private *dev_priv = dev->dev_private;
5933         int pipe = pipe_config->cpu_transcoder;
5934         intel_clock_t clock;
5935         u32 mdiv;
5936         int refclk = 100000;
5937
5938         mutex_lock(&dev_priv->dpio_lock);
5939         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
5940         mutex_unlock(&dev_priv->dpio_lock);
5941
5942         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5943         clock.m2 = mdiv & DPIO_M2DIV_MASK;
5944         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5945         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5946         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5947
5948         vlv_clock(refclk, &clock);
5949
5950         /* clock.dot is the fast clock */
5951         pipe_config->port_clock = clock.dot / 5;
5952 }
5953
5954 static void i9xx_get_plane_config(struct intel_crtc *crtc,
5955                                   struct intel_plane_config *plane_config)
5956 {
5957         struct drm_device *dev = crtc->base.dev;
5958         struct drm_i915_private *dev_priv = dev->dev_private;
5959         u32 val, base, offset;
5960         int pipe = crtc->pipe, plane = crtc->plane;
5961         int fourcc, pixel_format;
5962         int aligned_height;
5963
5964         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
5965         if (!crtc->base.primary->fb) {
5966                 DRM_DEBUG_KMS("failed to alloc fb\n");
5967                 return;
5968         }
5969
5970         val = I915_READ(DSPCNTR(plane));
5971
5972         if (INTEL_INFO(dev)->gen >= 4)
5973                 if (val & DISPPLANE_TILED)
5974                         plane_config->tiled = true;
5975
5976         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
5977         fourcc = intel_format_to_fourcc(pixel_format);
5978         crtc->base.primary->fb->pixel_format = fourcc;
5979         crtc->base.primary->fb->bits_per_pixel =
5980                 drm_format_plane_cpp(fourcc, 0) * 8;
5981
5982         if (INTEL_INFO(dev)->gen >= 4) {
5983                 if (plane_config->tiled)
5984                         offset = I915_READ(DSPTILEOFF(plane));
5985                 else
5986                         offset = I915_READ(DSPLINOFF(plane));
5987                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
5988         } else {
5989                 base = I915_READ(DSPADDR(plane));
5990         }
5991         plane_config->base = base;
5992
5993         val = I915_READ(PIPESRC(pipe));
5994         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
5995         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
5996
5997         val = I915_READ(DSPSTRIDE(pipe));
5998         crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
5999
6000         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6001                                             plane_config->tiled);
6002
6003         plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
6004                                    aligned_height, PAGE_SIZE);
6005
6006         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6007                       pipe, plane, crtc->base.primary->fb->width,
6008                       crtc->base.primary->fb->height,
6009                       crtc->base.primary->fb->bits_per_pixel, base,
6010                       crtc->base.primary->fb->pitches[0],
6011                       plane_config->size);
6012
6013 }
6014
6015 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6016                                struct intel_crtc_config *pipe_config)
6017 {
6018         struct drm_device *dev = crtc->base.dev;
6019         struct drm_i915_private *dev_priv = dev->dev_private;
6020         int pipe = pipe_config->cpu_transcoder;
6021         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6022         intel_clock_t clock;
6023         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6024         int refclk = 100000;
6025
6026         mutex_lock(&dev_priv->dpio_lock);
6027         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6028         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6029         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6030         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6031         mutex_unlock(&dev_priv->dpio_lock);
6032
6033         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6034         clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6035         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6036         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6037         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6038
6039         chv_clock(refclk, &clock);
6040
6041         /* clock.dot is the fast clock */
6042         pipe_config->port_clock = clock.dot / 5;
6043 }
6044
6045 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6046                                  struct intel_crtc_config *pipe_config)
6047 {
6048         struct drm_device *dev = crtc->base.dev;
6049         struct drm_i915_private *dev_priv = dev->dev_private;
6050         uint32_t tmp;
6051
6052         if (!intel_display_power_enabled(dev_priv,
6053                                          POWER_DOMAIN_PIPE(crtc->pipe)))
6054                 return false;
6055
6056         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6057         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6058
6059         tmp = I915_READ(PIPECONF(crtc->pipe));
6060         if (!(tmp & PIPECONF_ENABLE))
6061                 return false;
6062
6063         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6064                 switch (tmp & PIPECONF_BPC_MASK) {
6065                 case PIPECONF_6BPC:
6066                         pipe_config->pipe_bpp = 18;
6067                         break;
6068                 case PIPECONF_8BPC:
6069                         pipe_config->pipe_bpp = 24;
6070                         break;
6071                 case PIPECONF_10BPC:
6072                         pipe_config->pipe_bpp = 30;
6073                         break;
6074                 default:
6075                         break;
6076                 }
6077         }
6078
6079         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6080                 pipe_config->limited_color_range = true;
6081
6082         if (INTEL_INFO(dev)->gen < 4)
6083                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6084
6085         intel_get_pipe_timings(crtc, pipe_config);
6086
6087         i9xx_get_pfit_config(crtc, pipe_config);
6088
6089         if (INTEL_INFO(dev)->gen >= 4) {
6090                 tmp = I915_READ(DPLL_MD(crtc->pipe));
6091                 pipe_config->pixel_multiplier =
6092                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6093                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6094                 pipe_config->dpll_hw_state.dpll_md = tmp;
6095         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6096                 tmp = I915_READ(DPLL(crtc->pipe));
6097                 pipe_config->pixel_multiplier =
6098                         ((tmp & SDVO_MULTIPLIER_MASK)
6099                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6100         } else {
6101                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6102                  * port and will be fixed up in the encoder->get_config
6103                  * function. */
6104                 pipe_config->pixel_multiplier = 1;
6105         }
6106         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6107         if (!IS_VALLEYVIEW(dev)) {
6108                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6109                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6110         } else {
6111                 /* Mask out read-only status bits. */
6112                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6113                                                      DPLL_PORTC_READY_MASK |
6114                                                      DPLL_PORTB_READY_MASK);
6115         }
6116
6117         if (IS_CHERRYVIEW(dev))
6118                 chv_crtc_clock_get(crtc, pipe_config);
6119         else if (IS_VALLEYVIEW(dev))
6120                 vlv_crtc_clock_get(crtc, pipe_config);
6121         else
6122                 i9xx_crtc_clock_get(crtc, pipe_config);
6123
6124         return true;
6125 }
6126
6127 static void ironlake_init_pch_refclk(struct drm_device *dev)
6128 {
6129         struct drm_i915_private *dev_priv = dev->dev_private;
6130         struct drm_mode_config *mode_config = &dev->mode_config;
6131         struct intel_encoder *encoder;
6132         u32 val, final;
6133         bool has_lvds = false;
6134         bool has_cpu_edp = false;
6135         bool has_panel = false;
6136         bool has_ck505 = false;
6137         bool can_ssc = false;
6138
6139         /* We need to take the global config into account */
6140         list_for_each_entry(encoder, &mode_config->encoder_list,
6141                             base.head) {
6142                 switch (encoder->type) {
6143                 case INTEL_OUTPUT_LVDS:
6144                         has_panel = true;
6145                         has_lvds = true;
6146                         break;
6147                 case INTEL_OUTPUT_EDP:
6148                         has_panel = true;
6149                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6150                                 has_cpu_edp = true;
6151                         break;
6152                 }
6153         }
6154
6155         if (HAS_PCH_IBX(dev)) {
6156                 has_ck505 = dev_priv->vbt.display_clock_mode;
6157                 can_ssc = has_ck505;
6158         } else {
6159                 has_ck505 = false;
6160                 can_ssc = true;
6161         }
6162
6163         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6164                       has_panel, has_lvds, has_ck505);
6165
6166         /* Ironlake: try to setup display ref clock before DPLL
6167          * enabling. This is only under driver's control after
6168          * PCH B stepping, previous chipset stepping should be
6169          * ignoring this setting.
6170          */
6171         val = I915_READ(PCH_DREF_CONTROL);
6172
6173         /* As we must carefully and slowly disable/enable each source in turn,
6174          * compute the final state we want first and check if we need to
6175          * make any changes at all.
6176          */
6177         final = val;
6178         final &= ~DREF_NONSPREAD_SOURCE_MASK;
6179         if (has_ck505)
6180                 final |= DREF_NONSPREAD_CK505_ENABLE;
6181         else
6182                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6183
6184         final &= ~DREF_SSC_SOURCE_MASK;
6185         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6186         final &= ~DREF_SSC1_ENABLE;
6187
6188         if (has_panel) {
6189                 final |= DREF_SSC_SOURCE_ENABLE;
6190
6191                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6192                         final |= DREF_SSC1_ENABLE;
6193
6194                 if (has_cpu_edp) {
6195                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
6196                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6197                         else
6198                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6199                 } else
6200                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6201         } else {
6202                 final |= DREF_SSC_SOURCE_DISABLE;
6203                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6204         }
6205
6206         if (final == val)
6207                 return;
6208
6209         /* Always enable nonspread source */
6210         val &= ~DREF_NONSPREAD_SOURCE_MASK;
6211
6212         if (has_ck505)
6213                 val |= DREF_NONSPREAD_CK505_ENABLE;
6214         else
6215                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6216
6217         if (has_panel) {
6218                 val &= ~DREF_SSC_SOURCE_MASK;
6219                 val |= DREF_SSC_SOURCE_ENABLE;
6220
6221                 /* SSC must be turned on before enabling the CPU output  */
6222                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6223                         DRM_DEBUG_KMS("Using SSC on panel\n");
6224                         val |= DREF_SSC1_ENABLE;
6225                 } else
6226                         val &= ~DREF_SSC1_ENABLE;
6227
6228                 /* Get SSC going before enabling the outputs */
6229                 I915_WRITE(PCH_DREF_CONTROL, val);
6230                 POSTING_READ(PCH_DREF_CONTROL);
6231                 udelay(200);
6232
6233                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6234
6235                 /* Enable CPU source on CPU attached eDP */
6236                 if (has_cpu_edp) {
6237                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6238                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
6239                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6240                         }
6241                         else
6242                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6243                 } else
6244                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6245
6246                 I915_WRITE(PCH_DREF_CONTROL, val);
6247                 POSTING_READ(PCH_DREF_CONTROL);
6248                 udelay(200);
6249         } else {
6250                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6251
6252                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6253
6254                 /* Turn off CPU output */
6255                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6256
6257                 I915_WRITE(PCH_DREF_CONTROL, val);
6258                 POSTING_READ(PCH_DREF_CONTROL);
6259                 udelay(200);
6260
6261                 /* Turn off the SSC source */
6262                 val &= ~DREF_SSC_SOURCE_MASK;
6263                 val |= DREF_SSC_SOURCE_DISABLE;
6264
6265                 /* Turn off SSC1 */
6266                 val &= ~DREF_SSC1_ENABLE;
6267
6268                 I915_WRITE(PCH_DREF_CONTROL, val);
6269                 POSTING_READ(PCH_DREF_CONTROL);
6270                 udelay(200);
6271         }
6272
6273         BUG_ON(val != final);
6274 }
6275
6276 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6277 {
6278         uint32_t tmp;
6279
6280         tmp = I915_READ(SOUTH_CHICKEN2);
6281         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6282         I915_WRITE(SOUTH_CHICKEN2, tmp);
6283
6284         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6285                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6286                 DRM_ERROR("FDI mPHY reset assert timeout\n");
6287
6288         tmp = I915_READ(SOUTH_CHICKEN2);
6289         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6290         I915_WRITE(SOUTH_CHICKEN2, tmp);
6291
6292         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6293                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6294                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6295 }
6296
6297 /* WaMPhyProgramming:hsw */
6298 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6299 {
6300         uint32_t tmp;
6301
6302         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6303         tmp &= ~(0xFF << 24);
6304         tmp |= (0x12 << 24);
6305         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6306
6307         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6308         tmp |= (1 << 11);
6309         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6310
6311         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6312         tmp |= (1 << 11);
6313         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6314
6315         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6316         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6317         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6318
6319         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6320         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6321         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6322
6323         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6324         tmp &= ~(7 << 13);
6325         tmp |= (5 << 13);
6326         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6327
6328         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6329         tmp &= ~(7 << 13);
6330         tmp |= (5 << 13);
6331         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6332
6333         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6334         tmp &= ~0xFF;
6335         tmp |= 0x1C;
6336         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6337
6338         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6339         tmp &= ~0xFF;
6340         tmp |= 0x1C;
6341         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6342
6343         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6344         tmp &= ~(0xFF << 16);
6345         tmp |= (0x1C << 16);
6346         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6347
6348         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6349         tmp &= ~(0xFF << 16);
6350         tmp |= (0x1C << 16);
6351         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6352
6353         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6354         tmp |= (1 << 27);
6355         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6356
6357         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6358         tmp |= (1 << 27);
6359         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6360
6361         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6362         tmp &= ~(0xF << 28);
6363         tmp |= (4 << 28);
6364         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6365
6366         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6367         tmp &= ~(0xF << 28);
6368         tmp |= (4 << 28);
6369         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6370 }
6371
6372 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6373  * Programming" based on the parameters passed:
6374  * - Sequence to enable CLKOUT_DP
6375  * - Sequence to enable CLKOUT_DP without spread
6376  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6377  */
6378 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6379                                  bool with_fdi)
6380 {
6381         struct drm_i915_private *dev_priv = dev->dev_private;
6382         uint32_t reg, tmp;
6383
6384         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6385                 with_spread = true;
6386         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6387                  with_fdi, "LP PCH doesn't have FDI\n"))
6388                 with_fdi = false;
6389
6390         mutex_lock(&dev_priv->dpio_lock);
6391
6392         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6393         tmp &= ~SBI_SSCCTL_DISABLE;
6394         tmp |= SBI_SSCCTL_PATHALT;
6395         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6396
6397         udelay(24);
6398
6399         if (with_spread) {
6400                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6401                 tmp &= ~SBI_SSCCTL_PATHALT;
6402                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6403
6404                 if (with_fdi) {
6405                         lpt_reset_fdi_mphy(dev_priv);
6406                         lpt_program_fdi_mphy(dev_priv);
6407                 }
6408         }
6409
6410         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6411                SBI_GEN0 : SBI_DBUFF0;
6412         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6413         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6414         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6415
6416         mutex_unlock(&dev_priv->dpio_lock);
6417 }
6418
6419 /* Sequence to disable CLKOUT_DP */
6420 static void lpt_disable_clkout_dp(struct drm_device *dev)
6421 {
6422         struct drm_i915_private *dev_priv = dev->dev_private;
6423         uint32_t reg, tmp;
6424
6425         mutex_lock(&dev_priv->dpio_lock);
6426
6427         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6428                SBI_GEN0 : SBI_DBUFF0;
6429         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6430         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6431         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6432
6433         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6434         if (!(tmp & SBI_SSCCTL_DISABLE)) {
6435                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6436                         tmp |= SBI_SSCCTL_PATHALT;
6437                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6438                         udelay(32);
6439                 }
6440                 tmp |= SBI_SSCCTL_DISABLE;
6441                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6442         }
6443
6444         mutex_unlock(&dev_priv->dpio_lock);
6445 }
6446
6447 static void lpt_init_pch_refclk(struct drm_device *dev)
6448 {
6449         struct drm_mode_config *mode_config = &dev->mode_config;
6450         struct intel_encoder *encoder;
6451         bool has_vga = false;
6452
6453         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
6454                 switch (encoder->type) {
6455                 case INTEL_OUTPUT_ANALOG:
6456                         has_vga = true;
6457                         break;
6458                 }
6459         }
6460
6461         if (has_vga)
6462                 lpt_enable_clkout_dp(dev, true, true);
6463         else
6464                 lpt_disable_clkout_dp(dev);
6465 }
6466
6467 /*
6468  * Initialize reference clocks when the driver loads
6469  */
6470 void intel_init_pch_refclk(struct drm_device *dev)
6471 {
6472         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6473                 ironlake_init_pch_refclk(dev);
6474         else if (HAS_PCH_LPT(dev))
6475                 lpt_init_pch_refclk(dev);
6476 }
6477
6478 static int ironlake_get_refclk(struct drm_crtc *crtc)
6479 {
6480         struct drm_device *dev = crtc->dev;
6481         struct drm_i915_private *dev_priv = dev->dev_private;
6482         struct intel_encoder *encoder;
6483         int num_connectors = 0;
6484         bool is_lvds = false;
6485
6486         for_each_encoder_on_crtc(dev, crtc, encoder) {
6487                 switch (encoder->type) {
6488                 case INTEL_OUTPUT_LVDS:
6489                         is_lvds = true;
6490                         break;
6491                 }
6492                 num_connectors++;
6493         }
6494
6495         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6496                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6497                               dev_priv->vbt.lvds_ssc_freq);
6498                 return dev_priv->vbt.lvds_ssc_freq;
6499         }
6500
6501         return 120000;
6502 }
6503
6504 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6505 {
6506         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6507         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6508         int pipe = intel_crtc->pipe;
6509         uint32_t val;
6510
6511         val = 0;
6512
6513         switch (intel_crtc->config.pipe_bpp) {
6514         case 18:
6515                 val |= PIPECONF_6BPC;
6516                 break;
6517         case 24:
6518                 val |= PIPECONF_8BPC;
6519                 break;
6520         case 30:
6521                 val |= PIPECONF_10BPC;
6522                 break;
6523         case 36:
6524                 val |= PIPECONF_12BPC;
6525                 break;
6526         default:
6527                 /* Case prevented by intel_choose_pipe_bpp_dither. */
6528                 BUG();
6529         }
6530
6531         if (intel_crtc->config.dither)
6532                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6533
6534         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6535                 val |= PIPECONF_INTERLACED_ILK;
6536         else
6537                 val |= PIPECONF_PROGRESSIVE;
6538
6539         if (intel_crtc->config.limited_color_range)
6540                 val |= PIPECONF_COLOR_RANGE_SELECT;
6541
6542         I915_WRITE(PIPECONF(pipe), val);
6543         POSTING_READ(PIPECONF(pipe));
6544 }
6545
6546 /*
6547  * Set up the pipe CSC unit.
6548  *
6549  * Currently only full range RGB to limited range RGB conversion
6550  * is supported, but eventually this should handle various
6551  * RGB<->YCbCr scenarios as well.
6552  */
6553 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6554 {
6555         struct drm_device *dev = crtc->dev;
6556         struct drm_i915_private *dev_priv = dev->dev_private;
6557         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6558         int pipe = intel_crtc->pipe;
6559         uint16_t coeff = 0x7800; /* 1.0 */
6560
6561         /*
6562          * TODO: Check what kind of values actually come out of the pipe
6563          * with these coeff/postoff values and adjust to get the best
6564          * accuracy. Perhaps we even need to take the bpc value into
6565          * consideration.
6566          */
6567
6568         if (intel_crtc->config.limited_color_range)
6569                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6570
6571         /*
6572          * GY/GU and RY/RU should be the other way around according
6573          * to BSpec, but reality doesn't agree. Just set them up in
6574          * a way that results in the correct picture.
6575          */
6576         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6577         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6578
6579         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6580         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6581
6582         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6583         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6584
6585         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6586         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6587         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6588
6589         if (INTEL_INFO(dev)->gen > 6) {
6590                 uint16_t postoff = 0;
6591
6592                 if (intel_crtc->config.limited_color_range)
6593                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
6594
6595                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6596                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6597                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6598
6599                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6600         } else {
6601                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6602
6603                 if (intel_crtc->config.limited_color_range)
6604                         mode |= CSC_BLACK_SCREEN_OFFSET;
6605
6606                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6607         }
6608 }
6609
6610 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6611 {
6612         struct drm_device *dev = crtc->dev;
6613         struct drm_i915_private *dev_priv = dev->dev_private;
6614         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6615         enum pipe pipe = intel_crtc->pipe;
6616         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6617         uint32_t val;
6618
6619         val = 0;
6620
6621         if (IS_HASWELL(dev) && intel_crtc->config.dither)
6622                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6623
6624         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6625                 val |= PIPECONF_INTERLACED_ILK;
6626         else
6627                 val |= PIPECONF_PROGRESSIVE;
6628
6629         I915_WRITE(PIPECONF(cpu_transcoder), val);
6630         POSTING_READ(PIPECONF(cpu_transcoder));
6631
6632         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6633         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6634
6635         if (IS_BROADWELL(dev)) {
6636                 val = 0;
6637
6638                 switch (intel_crtc->config.pipe_bpp) {
6639                 case 18:
6640                         val |= PIPEMISC_DITHER_6_BPC;
6641                         break;
6642                 case 24:
6643                         val |= PIPEMISC_DITHER_8_BPC;
6644                         break;
6645                 case 30:
6646                         val |= PIPEMISC_DITHER_10_BPC;
6647                         break;
6648                 case 36:
6649                         val |= PIPEMISC_DITHER_12_BPC;
6650                         break;
6651                 default:
6652                         /* Case prevented by pipe_config_set_bpp. */
6653                         BUG();
6654                 }
6655
6656                 if (intel_crtc->config.dither)
6657                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6658
6659                 I915_WRITE(PIPEMISC(pipe), val);
6660         }
6661 }
6662
6663 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6664                                     intel_clock_t *clock,
6665                                     bool *has_reduced_clock,
6666                                     intel_clock_t *reduced_clock)
6667 {
6668         struct drm_device *dev = crtc->dev;
6669         struct drm_i915_private *dev_priv = dev->dev_private;
6670         struct intel_encoder *intel_encoder;
6671         int refclk;
6672         const intel_limit_t *limit;
6673         bool ret, is_lvds = false;
6674
6675         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6676                 switch (intel_encoder->type) {
6677                 case INTEL_OUTPUT_LVDS:
6678                         is_lvds = true;
6679                         break;
6680                 }
6681         }
6682
6683         refclk = ironlake_get_refclk(crtc);
6684
6685         /*
6686          * Returns a set of divisors for the desired target clock with the given
6687          * refclk, or FALSE.  The returned values represent the clock equation:
6688          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6689          */
6690         limit = intel_limit(crtc, refclk);
6691         ret = dev_priv->display.find_dpll(limit, crtc,
6692                                           to_intel_crtc(crtc)->config.port_clock,
6693                                           refclk, NULL, clock);
6694         if (!ret)
6695                 return false;
6696
6697         if (is_lvds && dev_priv->lvds_downclock_avail) {
6698                 /*
6699                  * Ensure we match the reduced clock's P to the target clock.
6700                  * If the clocks don't match, we can't switch the display clock
6701                  * by using the FP0/FP1. In such case we will disable the LVDS
6702                  * downclock feature.
6703                 */
6704                 *has_reduced_clock =
6705                         dev_priv->display.find_dpll(limit, crtc,
6706                                                     dev_priv->lvds_downclock,
6707                                                     refclk, clock,
6708                                                     reduced_clock);
6709         }
6710
6711         return true;
6712 }
6713
6714 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6715 {
6716         /*
6717          * Account for spread spectrum to avoid
6718          * oversubscribing the link. Max center spread
6719          * is 2.5%; use 5% for safety's sake.
6720          */
6721         u32 bps = target_clock * bpp * 21 / 20;
6722         return DIV_ROUND_UP(bps, link_bw * 8);
6723 }
6724
6725 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6726 {
6727         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6728 }
6729
6730 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6731                                       u32 *fp,
6732                                       intel_clock_t *reduced_clock, u32 *fp2)
6733 {
6734         struct drm_crtc *crtc = &intel_crtc->base;
6735         struct drm_device *dev = crtc->dev;
6736         struct drm_i915_private *dev_priv = dev->dev_private;
6737         struct intel_encoder *intel_encoder;
6738         uint32_t dpll;
6739         int factor, num_connectors = 0;
6740         bool is_lvds = false, is_sdvo = false;
6741
6742         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6743                 switch (intel_encoder->type) {
6744                 case INTEL_OUTPUT_LVDS:
6745                         is_lvds = true;
6746                         break;
6747                 case INTEL_OUTPUT_SDVO:
6748                 case INTEL_OUTPUT_HDMI:
6749                         is_sdvo = true;
6750                         break;
6751                 }
6752
6753                 num_connectors++;
6754         }
6755
6756         /* Enable autotuning of the PLL clock (if permissible) */
6757         factor = 21;
6758         if (is_lvds) {
6759                 if ((intel_panel_use_ssc(dev_priv) &&
6760                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
6761                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6762                         factor = 25;
6763         } else if (intel_crtc->config.sdvo_tv_clock)
6764                 factor = 20;
6765
6766         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6767                 *fp |= FP_CB_TUNE;
6768
6769         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6770                 *fp2 |= FP_CB_TUNE;
6771
6772         dpll = 0;
6773
6774         if (is_lvds)
6775                 dpll |= DPLLB_MODE_LVDS;
6776         else
6777                 dpll |= DPLLB_MODE_DAC_SERIAL;
6778
6779         dpll |= (intel_crtc->config.pixel_multiplier - 1)
6780                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6781
6782         if (is_sdvo)
6783                 dpll |= DPLL_SDVO_HIGH_SPEED;
6784         if (intel_crtc->config.has_dp_encoder)
6785                 dpll |= DPLL_SDVO_HIGH_SPEED;
6786
6787         /* compute bitmask from p1 value */
6788         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6789         /* also FPA1 */
6790         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6791
6792         switch (intel_crtc->config.dpll.p2) {
6793         case 5:
6794                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6795                 break;
6796         case 7:
6797                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6798                 break;
6799         case 10:
6800                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6801                 break;
6802         case 14:
6803                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6804                 break;
6805         }
6806
6807         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6808                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6809         else
6810                 dpll |= PLL_REF_INPUT_DREFCLK;
6811
6812         return dpll | DPLL_VCO_ENABLE;
6813 }
6814
6815 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
6816                                   int x, int y,
6817                                   struct drm_framebuffer *fb)
6818 {
6819         struct drm_device *dev = crtc->dev;
6820         struct drm_i915_private *dev_priv = dev->dev_private;
6821         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6822         int pipe = intel_crtc->pipe;
6823         int plane = intel_crtc->plane;
6824         int num_connectors = 0;
6825         intel_clock_t clock, reduced_clock;
6826         u32 dpll = 0, fp = 0, fp2 = 0;
6827         bool ok, has_reduced_clock = false;
6828         bool is_lvds = false;
6829         struct intel_encoder *encoder;
6830         struct intel_shared_dpll *pll;
6831         struct drm_framebuffer *old_fb;
6832         int ret;
6833
6834         for_each_encoder_on_crtc(dev, crtc, encoder) {
6835                 switch (encoder->type) {
6836                 case INTEL_OUTPUT_LVDS:
6837                         is_lvds = true;
6838                         break;
6839                 }
6840
6841                 num_connectors++;
6842         }
6843
6844         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6845              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6846
6847         ok = ironlake_compute_clocks(crtc, &clock,
6848                                      &has_reduced_clock, &reduced_clock);
6849         if (!ok && !intel_crtc->config.clock_set) {
6850                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6851                 return -EINVAL;
6852         }
6853         /* Compat-code for transition, will disappear. */
6854         if (!intel_crtc->config.clock_set) {
6855                 intel_crtc->config.dpll.n = clock.n;
6856                 intel_crtc->config.dpll.m1 = clock.m1;
6857                 intel_crtc->config.dpll.m2 = clock.m2;
6858                 intel_crtc->config.dpll.p1 = clock.p1;
6859                 intel_crtc->config.dpll.p2 = clock.p2;
6860         }
6861
6862         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6863         if (intel_crtc->config.has_pch_encoder) {
6864                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6865                 if (has_reduced_clock)
6866                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6867
6868                 dpll = ironlake_compute_dpll(intel_crtc,
6869                                              &fp, &reduced_clock,
6870                                              has_reduced_clock ? &fp2 : NULL);
6871
6872                 intel_crtc->config.dpll_hw_state.dpll = dpll;
6873                 intel_crtc->config.dpll_hw_state.fp0 = fp;
6874                 if (has_reduced_clock)
6875                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
6876                 else
6877                         intel_crtc->config.dpll_hw_state.fp1 = fp;
6878
6879                 pll = intel_get_shared_dpll(intel_crtc);
6880                 if (pll == NULL) {
6881                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6882                                          pipe_name(pipe));
6883                         return -EINVAL;
6884                 }
6885         } else
6886                 intel_put_shared_dpll(intel_crtc);
6887
6888         if (intel_crtc->config.has_dp_encoder)
6889                 intel_dp_set_m_n(intel_crtc);
6890
6891         if (is_lvds && has_reduced_clock && i915.powersave)
6892                 intel_crtc->lowfreq_avail = true;
6893         else
6894                 intel_crtc->lowfreq_avail = false;
6895
6896         intel_set_pipe_timings(intel_crtc);
6897
6898         if (intel_crtc->config.has_pch_encoder) {
6899                 intel_cpu_transcoder_set_m_n(intel_crtc,
6900                                              &intel_crtc->config.fdi_m_n);
6901         }
6902
6903         ironlake_set_pipeconf(crtc);
6904
6905         /* Set up the display plane register */
6906         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
6907         POSTING_READ(DSPCNTR(plane));
6908
6909         mutex_lock(&dev->struct_mutex);
6910         ret = intel_pin_and_fence_fb_obj(dev,
6911                                          to_intel_framebuffer(fb)->obj,
6912                                          NULL);
6913         if (ret != 0) {
6914                 DRM_ERROR("pin & fence failed\n");
6915                 mutex_unlock(&dev->struct_mutex);
6916                 return ret;
6917         }
6918         old_fb = crtc->primary->fb;
6919         if (old_fb)
6920                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
6921         mutex_unlock(&dev->struct_mutex);
6922
6923         dev_priv->display.update_primary_plane(crtc, fb, x, y);
6924
6925         crtc->primary->fb = fb;
6926         crtc->x = x;
6927         crtc->y = y;
6928
6929         return 0;
6930 }
6931
6932 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6933                                          struct intel_link_m_n *m_n)
6934 {
6935         struct drm_device *dev = crtc->base.dev;
6936         struct drm_i915_private *dev_priv = dev->dev_private;
6937         enum pipe pipe = crtc->pipe;
6938
6939         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6940         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6941         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6942                 & ~TU_SIZE_MASK;
6943         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6944         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6945                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6946 }
6947
6948 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6949                                          enum transcoder transcoder,
6950                                          struct intel_link_m_n *m_n)
6951 {
6952         struct drm_device *dev = crtc->base.dev;
6953         struct drm_i915_private *dev_priv = dev->dev_private;
6954         enum pipe pipe = crtc->pipe;
6955
6956         if (INTEL_INFO(dev)->gen >= 5) {
6957                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6958                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6959                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6960                         & ~TU_SIZE_MASK;
6961                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6962                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6963                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6964         } else {
6965                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6966                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6967                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6968                         & ~TU_SIZE_MASK;
6969                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6970                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6971                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6972         }
6973 }
6974
6975 void intel_dp_get_m_n(struct intel_crtc *crtc,
6976                       struct intel_crtc_config *pipe_config)
6977 {
6978         if (crtc->config.has_pch_encoder)
6979                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6980         else
6981                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6982                                              &pipe_config->dp_m_n);
6983 }
6984
6985 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6986                                         struct intel_crtc_config *pipe_config)
6987 {
6988         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6989                                      &pipe_config->fdi_m_n);
6990 }
6991
6992 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6993                                      struct intel_crtc_config *pipe_config)
6994 {
6995         struct drm_device *dev = crtc->base.dev;
6996         struct drm_i915_private *dev_priv = dev->dev_private;
6997         uint32_t tmp;
6998
6999         tmp = I915_READ(PF_CTL(crtc->pipe));
7000
7001         if (tmp & PF_ENABLE) {
7002                 pipe_config->pch_pfit.enabled = true;
7003                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7004                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7005
7006                 /* We currently do not free assignements of panel fitters on
7007                  * ivb/hsw (since we don't use the higher upscaling modes which
7008                  * differentiates them) so just WARN about this case for now. */
7009                 if (IS_GEN7(dev)) {
7010                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7011                                 PF_PIPE_SEL_IVB(crtc->pipe));
7012                 }
7013         }
7014 }
7015
7016 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7017                                       struct intel_plane_config *plane_config)
7018 {
7019         struct drm_device *dev = crtc->base.dev;
7020         struct drm_i915_private *dev_priv = dev->dev_private;
7021         u32 val, base, offset;
7022         int pipe = crtc->pipe, plane = crtc->plane;
7023         int fourcc, pixel_format;
7024         int aligned_height;
7025
7026         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7027         if (!crtc->base.primary->fb) {
7028                 DRM_DEBUG_KMS("failed to alloc fb\n");
7029                 return;
7030         }
7031
7032         val = I915_READ(DSPCNTR(plane));
7033
7034         if (INTEL_INFO(dev)->gen >= 4)
7035                 if (val & DISPPLANE_TILED)
7036                         plane_config->tiled = true;
7037
7038         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7039         fourcc = intel_format_to_fourcc(pixel_format);
7040         crtc->base.primary->fb->pixel_format = fourcc;
7041         crtc->base.primary->fb->bits_per_pixel =
7042                 drm_format_plane_cpp(fourcc, 0) * 8;
7043
7044         base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7045         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7046                 offset = I915_READ(DSPOFFSET(plane));
7047         } else {
7048                 if (plane_config->tiled)
7049                         offset = I915_READ(DSPTILEOFF(plane));
7050                 else
7051                         offset = I915_READ(DSPLINOFF(plane));
7052         }
7053         plane_config->base = base;
7054
7055         val = I915_READ(PIPESRC(pipe));
7056         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7057         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7058
7059         val = I915_READ(DSPSTRIDE(pipe));
7060         crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
7061
7062         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7063                                             plane_config->tiled);
7064
7065         plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
7066                                    aligned_height, PAGE_SIZE);
7067
7068         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7069                       pipe, plane, crtc->base.primary->fb->width,
7070                       crtc->base.primary->fb->height,
7071                       crtc->base.primary->fb->bits_per_pixel, base,
7072                       crtc->base.primary->fb->pitches[0],
7073                       plane_config->size);
7074 }
7075
7076 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7077                                      struct intel_crtc_config *pipe_config)
7078 {
7079         struct drm_device *dev = crtc->base.dev;
7080         struct drm_i915_private *dev_priv = dev->dev_private;
7081         uint32_t tmp;
7082
7083         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7084         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7085
7086         tmp = I915_READ(PIPECONF(crtc->pipe));
7087         if (!(tmp & PIPECONF_ENABLE))
7088                 return false;
7089
7090         switch (tmp & PIPECONF_BPC_MASK) {
7091         case PIPECONF_6BPC:
7092                 pipe_config->pipe_bpp = 18;
7093                 break;
7094         case PIPECONF_8BPC:
7095                 pipe_config->pipe_bpp = 24;
7096                 break;
7097         case PIPECONF_10BPC:
7098                 pipe_config->pipe_bpp = 30;
7099                 break;
7100         case PIPECONF_12BPC:
7101                 pipe_config->pipe_bpp = 36;
7102                 break;
7103         default:
7104                 break;
7105         }
7106
7107         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7108                 pipe_config->limited_color_range = true;
7109
7110         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7111                 struct intel_shared_dpll *pll;
7112
7113                 pipe_config->has_pch_encoder = true;
7114
7115                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7116                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7117                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7118
7119                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7120
7121                 if (HAS_PCH_IBX(dev_priv->dev)) {
7122                         pipe_config->shared_dpll =
7123                                 (enum intel_dpll_id) crtc->pipe;
7124                 } else {
7125                         tmp = I915_READ(PCH_DPLL_SEL);
7126                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7127                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7128                         else
7129                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7130                 }
7131
7132                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7133
7134                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7135                                            &pipe_config->dpll_hw_state));
7136
7137                 tmp = pipe_config->dpll_hw_state.dpll;
7138                 pipe_config->pixel_multiplier =
7139                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7140                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7141
7142                 ironlake_pch_clock_get(crtc, pipe_config);
7143         } else {
7144                 pipe_config->pixel_multiplier = 1;
7145         }
7146
7147         intel_get_pipe_timings(crtc, pipe_config);
7148
7149         ironlake_get_pfit_config(crtc, pipe_config);
7150
7151         return true;
7152 }
7153
7154 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7155 {
7156         struct drm_device *dev = dev_priv->dev;
7157         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
7158         struct intel_crtc *crtc;
7159
7160         for_each_intel_crtc(dev, crtc)
7161                 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7162                      pipe_name(crtc->pipe));
7163
7164         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7165         WARN(plls->spll_refcount, "SPLL enabled\n");
7166         WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
7167         WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
7168         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7169         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7170              "CPU PWM1 enabled\n");
7171         WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7172              "CPU PWM2 enabled\n");
7173         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7174              "PCH PWM1 enabled\n");
7175         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7176              "Utility pin enabled\n");
7177         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7178
7179         /*
7180          * In theory we can still leave IRQs enabled, as long as only the HPD
7181          * interrupts remain enabled. We used to check for that, but since it's
7182          * gen-specific and since we only disable LCPLL after we fully disable
7183          * the interrupts, the check below should be enough.
7184          */
7185         WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n");
7186 }
7187
7188 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7189 {
7190         struct drm_device *dev = dev_priv->dev;
7191
7192         if (IS_HASWELL(dev)) {
7193                 mutex_lock(&dev_priv->rps.hw_lock);
7194                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7195                                             val))
7196                         DRM_ERROR("Failed to disable D_COMP\n");
7197                 mutex_unlock(&dev_priv->rps.hw_lock);
7198         } else {
7199                 I915_WRITE(D_COMP, val);
7200         }
7201         POSTING_READ(D_COMP);
7202 }
7203
7204 /*
7205  * This function implements pieces of two sequences from BSpec:
7206  * - Sequence for display software to disable LCPLL
7207  * - Sequence for display software to allow package C8+
7208  * The steps implemented here are just the steps that actually touch the LCPLL
7209  * register. Callers should take care of disabling all the display engine
7210  * functions, doing the mode unset, fixing interrupts, etc.
7211  */
7212 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7213                               bool switch_to_fclk, bool allow_power_down)
7214 {
7215         uint32_t val;
7216
7217         assert_can_disable_lcpll(dev_priv);
7218
7219         val = I915_READ(LCPLL_CTL);
7220
7221         if (switch_to_fclk) {
7222                 val |= LCPLL_CD_SOURCE_FCLK;
7223                 I915_WRITE(LCPLL_CTL, val);
7224
7225                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7226                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
7227                         DRM_ERROR("Switching to FCLK failed\n");
7228
7229                 val = I915_READ(LCPLL_CTL);
7230         }
7231
7232         val |= LCPLL_PLL_DISABLE;
7233         I915_WRITE(LCPLL_CTL, val);
7234         POSTING_READ(LCPLL_CTL);
7235
7236         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7237                 DRM_ERROR("LCPLL still locked\n");
7238
7239         val = I915_READ(D_COMP);
7240         val |= D_COMP_COMP_DISABLE;
7241         hsw_write_dcomp(dev_priv, val);
7242         ndelay(100);
7243
7244         if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
7245                 DRM_ERROR("D_COMP RCOMP still in progress\n");
7246
7247         if (allow_power_down) {
7248                 val = I915_READ(LCPLL_CTL);
7249                 val |= LCPLL_POWER_DOWN_ALLOW;
7250                 I915_WRITE(LCPLL_CTL, val);
7251                 POSTING_READ(LCPLL_CTL);
7252         }
7253 }
7254
7255 /*
7256  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7257  * source.
7258  */
7259 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7260 {
7261         uint32_t val;
7262         unsigned long irqflags;
7263
7264         val = I915_READ(LCPLL_CTL);
7265
7266         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7267                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7268                 return;
7269
7270         /*
7271          * Make sure we're not on PC8 state before disabling PC8, otherwise
7272          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7273          *
7274          * The other problem is that hsw_restore_lcpll() is called as part of
7275          * the runtime PM resume sequence, so we can't just call
7276          * gen6_gt_force_wake_get() because that function calls
7277          * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7278          * while we are on the resume sequence. So to solve this problem we have
7279          * to call special forcewake code that doesn't touch runtime PM and
7280          * doesn't enable the forcewake delayed work.
7281          */
7282         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7283         if (dev_priv->uncore.forcewake_count++ == 0)
7284                 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7285         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7286
7287         if (val & LCPLL_POWER_DOWN_ALLOW) {
7288                 val &= ~LCPLL_POWER_DOWN_ALLOW;
7289                 I915_WRITE(LCPLL_CTL, val);
7290                 POSTING_READ(LCPLL_CTL);
7291         }
7292
7293         val = I915_READ(D_COMP);
7294         val |= D_COMP_COMP_FORCE;
7295         val &= ~D_COMP_COMP_DISABLE;
7296         hsw_write_dcomp(dev_priv, val);
7297
7298         val = I915_READ(LCPLL_CTL);
7299         val &= ~LCPLL_PLL_DISABLE;
7300         I915_WRITE(LCPLL_CTL, val);
7301
7302         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7303                 DRM_ERROR("LCPLL not locked yet\n");
7304
7305         if (val & LCPLL_CD_SOURCE_FCLK) {
7306                 val = I915_READ(LCPLL_CTL);
7307                 val &= ~LCPLL_CD_SOURCE_FCLK;
7308                 I915_WRITE(LCPLL_CTL, val);
7309
7310                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7311                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7312                         DRM_ERROR("Switching back to LCPLL failed\n");
7313         }
7314
7315         /* See the big comment above. */
7316         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7317         if (--dev_priv->uncore.forcewake_count == 0)
7318                 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7319         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7320 }
7321
7322 /*
7323  * Package states C8 and deeper are really deep PC states that can only be
7324  * reached when all the devices on the system allow it, so even if the graphics
7325  * device allows PC8+, it doesn't mean the system will actually get to these
7326  * states. Our driver only allows PC8+ when going into runtime PM.
7327  *
7328  * The requirements for PC8+ are that all the outputs are disabled, the power
7329  * well is disabled and most interrupts are disabled, and these are also
7330  * requirements for runtime PM. When these conditions are met, we manually do
7331  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7332  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7333  * hang the machine.
7334  *
7335  * When we really reach PC8 or deeper states (not just when we allow it) we lose
7336  * the state of some registers, so when we come back from PC8+ we need to
7337  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7338  * need to take care of the registers kept by RC6. Notice that this happens even
7339  * if we don't put the device in PCI D3 state (which is what currently happens
7340  * because of the runtime PM support).
7341  *
7342  * For more, read "Display Sequences for Package C8" on the hardware
7343  * documentation.
7344  */
7345 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7346 {
7347         struct drm_device *dev = dev_priv->dev;
7348         uint32_t val;
7349
7350         DRM_DEBUG_KMS("Enabling package C8+\n");
7351
7352         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7353                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7354                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7355                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7356         }
7357
7358         lpt_disable_clkout_dp(dev);
7359         hsw_disable_lcpll(dev_priv, true, true);
7360 }
7361
7362 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7363 {
7364         struct drm_device *dev = dev_priv->dev;
7365         uint32_t val;
7366
7367         DRM_DEBUG_KMS("Disabling package C8+\n");
7368
7369         hsw_restore_lcpll(dev_priv);
7370         lpt_init_pch_refclk(dev);
7371
7372         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7373                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7374                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7375                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7376         }
7377
7378         intel_prepare_ddi(dev);
7379 }
7380
7381 static void snb_modeset_global_resources(struct drm_device *dev)
7382 {
7383         modeset_update_crtc_power_domains(dev);
7384 }
7385
7386 static void haswell_modeset_global_resources(struct drm_device *dev)
7387 {
7388         modeset_update_crtc_power_domains(dev);
7389 }
7390
7391 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7392                                  int x, int y,
7393                                  struct drm_framebuffer *fb)
7394 {
7395         struct drm_device *dev = crtc->dev;
7396         struct drm_i915_private *dev_priv = dev->dev_private;
7397         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7398         int plane = intel_crtc->plane;
7399         struct drm_framebuffer *old_fb;
7400         int ret;
7401
7402         if (!intel_ddi_pll_select(intel_crtc))
7403                 return -EINVAL;
7404         intel_ddi_pll_enable(intel_crtc);
7405
7406         if (intel_crtc->config.has_dp_encoder)
7407                 intel_dp_set_m_n(intel_crtc);
7408
7409         intel_crtc->lowfreq_avail = false;
7410
7411         intel_set_pipe_timings(intel_crtc);
7412
7413         if (intel_crtc->config.has_pch_encoder) {
7414                 intel_cpu_transcoder_set_m_n(intel_crtc,
7415                                              &intel_crtc->config.fdi_m_n);
7416         }
7417
7418         haswell_set_pipeconf(crtc);
7419
7420         intel_set_pipe_csc(crtc);
7421
7422         /* Set up the display plane register */
7423         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
7424         POSTING_READ(DSPCNTR(plane));
7425
7426         mutex_lock(&dev->struct_mutex);
7427         ret = intel_pin_and_fence_fb_obj(dev,
7428                                          to_intel_framebuffer(fb)->obj,
7429                                          NULL);
7430         if (ret != 0) {
7431                 DRM_ERROR("pin & fence failed\n");
7432                 mutex_unlock(&dev->struct_mutex);
7433                 return ret;
7434         }
7435         old_fb = crtc->primary->fb;
7436         if (old_fb)
7437                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
7438         mutex_unlock(&dev->struct_mutex);
7439
7440         dev_priv->display.update_primary_plane(crtc, fb, x, y);
7441
7442         crtc->primary->fb = fb;
7443         crtc->x = x;
7444         crtc->y = y;
7445
7446         return 0;
7447 }
7448
7449 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7450                                     struct intel_crtc_config *pipe_config)
7451 {
7452         struct drm_device *dev = crtc->base.dev;
7453         struct drm_i915_private *dev_priv = dev->dev_private;
7454         enum intel_display_power_domain pfit_domain;
7455         uint32_t tmp;
7456
7457         if (!intel_display_power_enabled(dev_priv,
7458                                          POWER_DOMAIN_PIPE(crtc->pipe)))
7459                 return false;
7460
7461         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7462         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7463
7464         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7465         if (tmp & TRANS_DDI_FUNC_ENABLE) {
7466                 enum pipe trans_edp_pipe;
7467                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7468                 default:
7469                         WARN(1, "unknown pipe linked to edp transcoder\n");
7470                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7471                 case TRANS_DDI_EDP_INPUT_A_ON:
7472                         trans_edp_pipe = PIPE_A;
7473                         break;
7474                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7475                         trans_edp_pipe = PIPE_B;
7476                         break;
7477                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7478                         trans_edp_pipe = PIPE_C;
7479                         break;
7480                 }
7481
7482                 if (trans_edp_pipe == crtc->pipe)
7483                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
7484         }
7485
7486         if (!intel_display_power_enabled(dev_priv,
7487                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7488                 return false;
7489
7490         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7491         if (!(tmp & PIPECONF_ENABLE))
7492                 return false;
7493
7494         /*
7495          * Haswell has only FDI/PCH transcoder A. It is which is connected to
7496          * DDI E. So just check whether this pipe is wired to DDI E and whether
7497          * the PCH transcoder is on.
7498          */
7499         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7500         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
7501             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7502                 pipe_config->has_pch_encoder = true;
7503
7504                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7505                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7506                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7507
7508                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7509         }
7510
7511         intel_get_pipe_timings(crtc, pipe_config);
7512
7513         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7514         if (intel_display_power_enabled(dev_priv, pfit_domain))
7515                 ironlake_get_pfit_config(crtc, pipe_config);
7516
7517         if (IS_HASWELL(dev))
7518                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7519                         (I915_READ(IPS_CTL) & IPS_ENABLE);
7520
7521         pipe_config->pixel_multiplier = 1;
7522
7523         return true;
7524 }
7525
7526 static struct {
7527         int clock;
7528         u32 config;
7529 } hdmi_audio_clock[] = {
7530         { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7531         { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7532         { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7533         { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7534         { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7535         { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7536         { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7537         { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7538         { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7539         { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7540 };
7541
7542 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7543 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7544 {
7545         int i;
7546
7547         for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7548                 if (mode->clock == hdmi_audio_clock[i].clock)
7549                         break;
7550         }
7551
7552         if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7553                 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7554                 i = 1;
7555         }
7556
7557         DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7558                       hdmi_audio_clock[i].clock,
7559                       hdmi_audio_clock[i].config);
7560
7561         return hdmi_audio_clock[i].config;
7562 }
7563
7564 static bool intel_eld_uptodate(struct drm_connector *connector,
7565                                int reg_eldv, uint32_t bits_eldv,
7566                                int reg_elda, uint32_t bits_elda,
7567                                int reg_edid)
7568 {
7569         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7570         uint8_t *eld = connector->eld;
7571         uint32_t i;
7572
7573         i = I915_READ(reg_eldv);
7574         i &= bits_eldv;
7575
7576         if (!eld[0])
7577                 return !i;
7578
7579         if (!i)
7580                 return false;
7581
7582         i = I915_READ(reg_elda);
7583         i &= ~bits_elda;
7584         I915_WRITE(reg_elda, i);
7585
7586         for (i = 0; i < eld[2]; i++)
7587                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7588                         return false;
7589
7590         return true;
7591 }
7592
7593 static void g4x_write_eld(struct drm_connector *connector,
7594                           struct drm_crtc *crtc,
7595                           struct drm_display_mode *mode)
7596 {
7597         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7598         uint8_t *eld = connector->eld;
7599         uint32_t eldv;
7600         uint32_t len;
7601         uint32_t i;
7602
7603         i = I915_READ(G4X_AUD_VID_DID);
7604
7605         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7606                 eldv = G4X_ELDV_DEVCL_DEVBLC;
7607         else
7608                 eldv = G4X_ELDV_DEVCTG;
7609
7610         if (intel_eld_uptodate(connector,
7611                                G4X_AUD_CNTL_ST, eldv,
7612                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7613                                G4X_HDMIW_HDMIEDID))
7614                 return;
7615
7616         i = I915_READ(G4X_AUD_CNTL_ST);
7617         i &= ~(eldv | G4X_ELD_ADDR);
7618         len = (i >> 9) & 0x1f;          /* ELD buffer size */
7619         I915_WRITE(G4X_AUD_CNTL_ST, i);
7620
7621         if (!eld[0])
7622                 return;
7623
7624         len = min_t(uint8_t, eld[2], len);
7625         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7626         for (i = 0; i < len; i++)
7627                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7628
7629         i = I915_READ(G4X_AUD_CNTL_ST);
7630         i |= eldv;
7631         I915_WRITE(G4X_AUD_CNTL_ST, i);
7632 }
7633
7634 static void haswell_write_eld(struct drm_connector *connector,
7635                               struct drm_crtc *crtc,
7636                               struct drm_display_mode *mode)
7637 {
7638         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7639         uint8_t *eld = connector->eld;
7640         uint32_t eldv;
7641         uint32_t i;
7642         int len;
7643         int pipe = to_intel_crtc(crtc)->pipe;
7644         int tmp;
7645
7646         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7647         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7648         int aud_config = HSW_AUD_CFG(pipe);
7649         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7650
7651         /* Audio output enable */
7652         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7653         tmp = I915_READ(aud_cntrl_st2);
7654         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7655         I915_WRITE(aud_cntrl_st2, tmp);
7656         POSTING_READ(aud_cntrl_st2);
7657
7658         assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
7659
7660         /* Set ELD valid state */
7661         tmp = I915_READ(aud_cntrl_st2);
7662         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7663         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7664         I915_WRITE(aud_cntrl_st2, tmp);
7665         tmp = I915_READ(aud_cntrl_st2);
7666         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7667
7668         /* Enable HDMI mode */
7669         tmp = I915_READ(aud_config);
7670         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7671         /* clear N_programing_enable and N_value_index */
7672         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7673         I915_WRITE(aud_config, tmp);
7674
7675         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7676
7677         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7678
7679         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7680                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7681                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7682                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7683         } else {
7684                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7685         }
7686
7687         if (intel_eld_uptodate(connector,
7688                                aud_cntrl_st2, eldv,
7689                                aud_cntl_st, IBX_ELD_ADDRESS,
7690                                hdmiw_hdmiedid))
7691                 return;
7692
7693         i = I915_READ(aud_cntrl_st2);
7694         i &= ~eldv;
7695         I915_WRITE(aud_cntrl_st2, i);
7696
7697         if (!eld[0])
7698                 return;
7699
7700         i = I915_READ(aud_cntl_st);
7701         i &= ~IBX_ELD_ADDRESS;
7702         I915_WRITE(aud_cntl_st, i);
7703         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
7704         DRM_DEBUG_DRIVER("port num:%d\n", i);
7705
7706         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7707         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7708         for (i = 0; i < len; i++)
7709                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7710
7711         i = I915_READ(aud_cntrl_st2);
7712         i |= eldv;
7713         I915_WRITE(aud_cntrl_st2, i);
7714
7715 }
7716
7717 static void ironlake_write_eld(struct drm_connector *connector,
7718                                struct drm_crtc *crtc,
7719                                struct drm_display_mode *mode)
7720 {
7721         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7722         uint8_t *eld = connector->eld;
7723         uint32_t eldv;
7724         uint32_t i;
7725         int len;
7726         int hdmiw_hdmiedid;
7727         int aud_config;
7728         int aud_cntl_st;
7729         int aud_cntrl_st2;
7730         int pipe = to_intel_crtc(crtc)->pipe;
7731
7732         if (HAS_PCH_IBX(connector->dev)) {
7733                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7734                 aud_config = IBX_AUD_CFG(pipe);
7735                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7736                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7737         } else if (IS_VALLEYVIEW(connector->dev)) {
7738                 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7739                 aud_config = VLV_AUD_CFG(pipe);
7740                 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7741                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7742         } else {
7743                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7744                 aud_config = CPT_AUD_CFG(pipe);
7745                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7746                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7747         }
7748
7749         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7750
7751         if (IS_VALLEYVIEW(connector->dev))  {
7752                 struct intel_encoder *intel_encoder;
7753                 struct intel_digital_port *intel_dig_port;
7754
7755                 intel_encoder = intel_attached_encoder(connector);
7756                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7757                 i = intel_dig_port->port;
7758         } else {
7759                 i = I915_READ(aud_cntl_st);
7760                 i = (i >> 29) & DIP_PORT_SEL_MASK;
7761                 /* DIP_Port_Select, 0x1 = PortB */
7762         }
7763
7764         if (!i) {
7765                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7766                 /* operate blindly on all ports */
7767                 eldv = IBX_ELD_VALIDB;
7768                 eldv |= IBX_ELD_VALIDB << 4;
7769                 eldv |= IBX_ELD_VALIDB << 8;
7770         } else {
7771                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7772                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7773         }
7774
7775         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7776                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7777                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7778                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7779         } else {
7780                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7781         }
7782
7783         if (intel_eld_uptodate(connector,
7784                                aud_cntrl_st2, eldv,
7785                                aud_cntl_st, IBX_ELD_ADDRESS,
7786                                hdmiw_hdmiedid))
7787                 return;
7788
7789         i = I915_READ(aud_cntrl_st2);
7790         i &= ~eldv;
7791         I915_WRITE(aud_cntrl_st2, i);
7792
7793         if (!eld[0])
7794                 return;
7795
7796         i = I915_READ(aud_cntl_st);
7797         i &= ~IBX_ELD_ADDRESS;
7798         I915_WRITE(aud_cntl_st, i);
7799
7800         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7801         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7802         for (i = 0; i < len; i++)
7803                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7804
7805         i = I915_READ(aud_cntrl_st2);
7806         i |= eldv;
7807         I915_WRITE(aud_cntrl_st2, i);
7808 }
7809
7810 void intel_write_eld(struct drm_encoder *encoder,
7811                      struct drm_display_mode *mode)
7812 {
7813         struct drm_crtc *crtc = encoder->crtc;
7814         struct drm_connector *connector;
7815         struct drm_device *dev = encoder->dev;
7816         struct drm_i915_private *dev_priv = dev->dev_private;
7817
7818         connector = drm_select_eld(encoder, mode);
7819         if (!connector)
7820                 return;
7821
7822         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7823                          connector->base.id,
7824                          drm_get_connector_name(connector),
7825                          connector->encoder->base.id,
7826                          drm_get_encoder_name(connector->encoder));
7827
7828         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7829
7830         if (dev_priv->display.write_eld)
7831                 dev_priv->display.write_eld(connector, crtc, mode);
7832 }
7833
7834 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7835 {
7836         struct drm_device *dev = crtc->dev;
7837         struct drm_i915_private *dev_priv = dev->dev_private;
7838         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7839         bool visible = base != 0;
7840         u32 cntl;
7841
7842         if (intel_crtc->cursor_visible == visible)
7843                 return;
7844
7845         cntl = I915_READ(_CURACNTR);
7846         if (visible) {
7847                 /* On these chipsets we can only modify the base whilst
7848                  * the cursor is disabled.
7849                  */
7850                 I915_WRITE(_CURABASE, base);
7851
7852                 cntl &= ~(CURSOR_FORMAT_MASK);
7853                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7854                 cntl |= CURSOR_ENABLE |
7855                         CURSOR_GAMMA_ENABLE |
7856                         CURSOR_FORMAT_ARGB;
7857         } else
7858                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
7859         I915_WRITE(_CURACNTR, cntl);
7860
7861         intel_crtc->cursor_visible = visible;
7862 }
7863
7864 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7865 {
7866         struct drm_device *dev = crtc->dev;
7867         struct drm_i915_private *dev_priv = dev->dev_private;
7868         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7869         int pipe = intel_crtc->pipe;
7870         bool visible = base != 0;
7871
7872         if (intel_crtc->cursor_visible != visible) {
7873                 int16_t width = intel_crtc->cursor_width;
7874                 uint32_t cntl = I915_READ(CURCNTR(pipe));
7875                 if (base) {
7876                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7877                         cntl |= MCURSOR_GAMMA_ENABLE;
7878
7879                         switch (width) {
7880                         case 64:
7881                                 cntl |= CURSOR_MODE_64_ARGB_AX;
7882                                 break;
7883                         case 128:
7884                                 cntl |= CURSOR_MODE_128_ARGB_AX;
7885                                 break;
7886                         case 256:
7887                                 cntl |= CURSOR_MODE_256_ARGB_AX;
7888                                 break;
7889                         default:
7890                                 WARN_ON(1);
7891                                 return;
7892                         }
7893                         cntl |= pipe << 28; /* Connect to correct pipe */
7894                 } else {
7895                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7896                         cntl |= CURSOR_MODE_DISABLE;
7897                 }
7898                 I915_WRITE(CURCNTR(pipe), cntl);
7899
7900                 intel_crtc->cursor_visible = visible;
7901         }
7902         /* and commit changes on next vblank */
7903         POSTING_READ(CURCNTR(pipe));
7904         I915_WRITE(CURBASE(pipe), base);
7905         POSTING_READ(CURBASE(pipe));
7906 }
7907
7908 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7909 {
7910         struct drm_device *dev = crtc->dev;
7911         struct drm_i915_private *dev_priv = dev->dev_private;
7912         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7913         int pipe = intel_crtc->pipe;
7914         bool visible = base != 0;
7915
7916         if (intel_crtc->cursor_visible != visible) {
7917                 int16_t width = intel_crtc->cursor_width;
7918                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7919                 if (base) {
7920                         cntl &= ~CURSOR_MODE;
7921                         cntl |= MCURSOR_GAMMA_ENABLE;
7922                         switch (width) {
7923                         case 64:
7924                                 cntl |= CURSOR_MODE_64_ARGB_AX;
7925                                 break;
7926                         case 128:
7927                                 cntl |= CURSOR_MODE_128_ARGB_AX;
7928                                 break;
7929                         case 256:
7930                                 cntl |= CURSOR_MODE_256_ARGB_AX;
7931                                 break;
7932                         default:
7933                                 WARN_ON(1);
7934                                 return;
7935                         }
7936                 } else {
7937                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7938                         cntl |= CURSOR_MODE_DISABLE;
7939                 }
7940                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7941                         cntl |= CURSOR_PIPE_CSC_ENABLE;
7942                         cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7943                 }
7944                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7945
7946                 intel_crtc->cursor_visible = visible;
7947         }
7948         /* and commit changes on next vblank */
7949         POSTING_READ(CURCNTR_IVB(pipe));
7950         I915_WRITE(CURBASE_IVB(pipe), base);
7951         POSTING_READ(CURBASE_IVB(pipe));
7952 }
7953
7954 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7955 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7956                                      bool on)
7957 {
7958         struct drm_device *dev = crtc->dev;
7959         struct drm_i915_private *dev_priv = dev->dev_private;
7960         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7961         int pipe = intel_crtc->pipe;
7962         int x = intel_crtc->cursor_x;
7963         int y = intel_crtc->cursor_y;
7964         u32 base = 0, pos = 0;
7965         bool visible;
7966
7967         if (on)
7968                 base = intel_crtc->cursor_addr;
7969
7970         if (x >= intel_crtc->config.pipe_src_w)
7971                 base = 0;
7972
7973         if (y >= intel_crtc->config.pipe_src_h)
7974                 base = 0;
7975
7976         if (x < 0) {
7977                 if (x + intel_crtc->cursor_width <= 0)
7978                         base = 0;
7979
7980                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7981                 x = -x;
7982         }
7983         pos |= x << CURSOR_X_SHIFT;
7984
7985         if (y < 0) {
7986                 if (y + intel_crtc->cursor_height <= 0)
7987                         base = 0;
7988
7989                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7990                 y = -y;
7991         }
7992         pos |= y << CURSOR_Y_SHIFT;
7993
7994         visible = base != 0;
7995         if (!visible && !intel_crtc->cursor_visible)
7996                 return;
7997
7998         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7999                 I915_WRITE(CURPOS_IVB(pipe), pos);
8000                 ivb_update_cursor(crtc, base);
8001         } else {
8002                 I915_WRITE(CURPOS(pipe), pos);
8003                 if (IS_845G(dev) || IS_I865G(dev))
8004                         i845_update_cursor(crtc, base);
8005                 else
8006                         i9xx_update_cursor(crtc, base);
8007         }
8008 }
8009
8010 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
8011                                  struct drm_file *file,
8012                                  uint32_t handle,
8013                                  uint32_t width, uint32_t height)
8014 {
8015         struct drm_device *dev = crtc->dev;
8016         struct drm_i915_private *dev_priv = dev->dev_private;
8017         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8018         struct drm_i915_gem_object *obj;
8019         unsigned old_width;
8020         uint32_t addr;
8021         int ret;
8022
8023         /* if we want to turn off the cursor ignore width and height */
8024         if (!handle) {
8025                 DRM_DEBUG_KMS("cursor off\n");
8026                 addr = 0;
8027                 obj = NULL;
8028                 mutex_lock(&dev->struct_mutex);
8029                 goto finish;
8030         }
8031
8032         /* Check for which cursor types we support */
8033         if (!((width == 64 && height == 64) ||
8034                         (width == 128 && height == 128 && !IS_GEN2(dev)) ||
8035                         (width == 256 && height == 256 && !IS_GEN2(dev)))) {
8036                 DRM_DEBUG("Cursor dimension not supported\n");
8037                 return -EINVAL;
8038         }
8039
8040         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
8041         if (&obj->base == NULL)
8042                 return -ENOENT;
8043
8044         if (obj->base.size < width * height * 4) {
8045                 DRM_DEBUG_KMS("buffer is to small\n");
8046                 ret = -ENOMEM;
8047                 goto fail;
8048         }
8049
8050         /* we only need to pin inside GTT if cursor is non-phy */
8051         mutex_lock(&dev->struct_mutex);
8052         if (!INTEL_INFO(dev)->cursor_needs_physical) {
8053                 unsigned alignment;
8054
8055                 if (obj->tiling_mode) {
8056                         DRM_DEBUG_KMS("cursor cannot be tiled\n");
8057                         ret = -EINVAL;
8058                         goto fail_locked;
8059                 }
8060
8061                 /* Note that the w/a also requires 2 PTE of padding following
8062                  * the bo. We currently fill all unused PTE with the shadow
8063                  * page and so we should always have valid PTE following the
8064                  * cursor preventing the VT-d warning.
8065                  */
8066                 alignment = 0;
8067                 if (need_vtd_wa(dev))
8068                         alignment = 64*1024;
8069
8070                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8071                 if (ret) {
8072                         DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8073                         goto fail_locked;
8074                 }
8075
8076                 ret = i915_gem_object_put_fence(obj);
8077                 if (ret) {
8078                         DRM_DEBUG_KMS("failed to release fence for cursor");
8079                         goto fail_unpin;
8080                 }
8081
8082                 addr = i915_gem_obj_ggtt_offset(obj);
8083         } else {
8084                 int align = IS_I830(dev) ? 16 * 1024 : 256;
8085                 ret = i915_gem_attach_phys_object(dev, obj,
8086                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
8087                                                   align);
8088                 if (ret) {
8089                         DRM_DEBUG_KMS("failed to attach phys object\n");
8090                         goto fail_locked;
8091                 }
8092                 addr = obj->phys_obj->handle->busaddr;
8093         }
8094
8095         if (IS_GEN2(dev))
8096                 I915_WRITE(CURSIZE, (height << 12) | width);
8097
8098  finish:
8099         if (intel_crtc->cursor_bo) {
8100                 if (INTEL_INFO(dev)->cursor_needs_physical) {
8101                         if (intel_crtc->cursor_bo != obj)
8102                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
8103                 } else
8104                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8105                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
8106         }
8107
8108         mutex_unlock(&dev->struct_mutex);
8109
8110         old_width = intel_crtc->cursor_width;
8111
8112         intel_crtc->cursor_addr = addr;
8113         intel_crtc->cursor_bo = obj;
8114         intel_crtc->cursor_width = width;
8115         intel_crtc->cursor_height = height;
8116
8117         if (intel_crtc->active) {
8118                 if (old_width != width)
8119                         intel_update_watermarks(crtc);
8120                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8121         }
8122
8123         return 0;
8124 fail_unpin:
8125         i915_gem_object_unpin_from_display_plane(obj);
8126 fail_locked:
8127         mutex_unlock(&dev->struct_mutex);
8128 fail:
8129         drm_gem_object_unreference_unlocked(&obj->base);
8130         return ret;
8131 }
8132
8133 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
8134 {
8135         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8136
8137         intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
8138         intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
8139
8140         if (intel_crtc->active)
8141                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8142
8143         return 0;
8144 }
8145
8146 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8147                                  u16 *blue, uint32_t start, uint32_t size)
8148 {
8149         int end = (start + size > 256) ? 256 : start + size, i;
8150         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8151
8152         for (i = start; i < end; i++) {
8153                 intel_crtc->lut_r[i] = red[i] >> 8;
8154                 intel_crtc->lut_g[i] = green[i] >> 8;
8155                 intel_crtc->lut_b[i] = blue[i] >> 8;
8156         }
8157
8158         intel_crtc_load_lut(crtc);
8159 }
8160
8161 /* VESA 640x480x72Hz mode to set on the pipe */
8162 static struct drm_display_mode load_detect_mode = {
8163         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8164                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8165 };
8166
8167 struct drm_framebuffer *
8168 __intel_framebuffer_create(struct drm_device *dev,
8169                            struct drm_mode_fb_cmd2 *mode_cmd,
8170                            struct drm_i915_gem_object *obj)
8171 {
8172         struct intel_framebuffer *intel_fb;
8173         int ret;
8174
8175         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8176         if (!intel_fb) {
8177                 drm_gem_object_unreference_unlocked(&obj->base);
8178                 return ERR_PTR(-ENOMEM);
8179         }
8180
8181         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8182         if (ret)
8183                 goto err;
8184
8185         return &intel_fb->base;
8186 err:
8187         drm_gem_object_unreference_unlocked(&obj->base);
8188         kfree(intel_fb);
8189
8190         return ERR_PTR(ret);
8191 }
8192
8193 static struct drm_framebuffer *
8194 intel_framebuffer_create(struct drm_device *dev,
8195                          struct drm_mode_fb_cmd2 *mode_cmd,
8196                          struct drm_i915_gem_object *obj)
8197 {
8198         struct drm_framebuffer *fb;
8199         int ret;
8200
8201         ret = i915_mutex_lock_interruptible(dev);
8202         if (ret)
8203                 return ERR_PTR(ret);
8204         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8205         mutex_unlock(&dev->struct_mutex);
8206
8207         return fb;
8208 }
8209
8210 static u32
8211 intel_framebuffer_pitch_for_width(int width, int bpp)
8212 {
8213         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8214         return ALIGN(pitch, 64);
8215 }
8216
8217 static u32
8218 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8219 {
8220         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8221         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
8222 }
8223
8224 static struct drm_framebuffer *
8225 intel_framebuffer_create_for_mode(struct drm_device *dev,
8226                                   struct drm_display_mode *mode,
8227                                   int depth, int bpp)
8228 {
8229         struct drm_i915_gem_object *obj;
8230         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8231
8232         obj = i915_gem_alloc_object(dev,
8233                                     intel_framebuffer_size_for_mode(mode, bpp));
8234         if (obj == NULL)
8235                 return ERR_PTR(-ENOMEM);
8236
8237         mode_cmd.width = mode->hdisplay;
8238         mode_cmd.height = mode->vdisplay;
8239         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8240                                                                 bpp);
8241         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8242
8243         return intel_framebuffer_create(dev, &mode_cmd, obj);
8244 }
8245
8246 static struct drm_framebuffer *
8247 mode_fits_in_fbdev(struct drm_device *dev,
8248                    struct drm_display_mode *mode)
8249 {
8250 #ifdef CONFIG_DRM_I915_FBDEV
8251         struct drm_i915_private *dev_priv = dev->dev_private;
8252         struct drm_i915_gem_object *obj;
8253         struct drm_framebuffer *fb;
8254
8255         if (!dev_priv->fbdev)
8256                 return NULL;
8257
8258         if (!dev_priv->fbdev->fb)
8259                 return NULL;
8260
8261         obj = dev_priv->fbdev->fb->obj;
8262         BUG_ON(!obj);
8263
8264         fb = &dev_priv->fbdev->fb->base;
8265         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8266                                                                fb->bits_per_pixel))
8267                 return NULL;
8268
8269         if (obj->base.size < mode->vdisplay * fb->pitches[0])
8270                 return NULL;
8271
8272         return fb;
8273 #else
8274         return NULL;
8275 #endif
8276 }
8277
8278 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8279                                 struct drm_display_mode *mode,
8280                                 struct intel_load_detect_pipe *old)
8281 {
8282         struct intel_crtc *intel_crtc;
8283         struct intel_encoder *intel_encoder =
8284                 intel_attached_encoder(connector);
8285         struct drm_crtc *possible_crtc;
8286         struct drm_encoder *encoder = &intel_encoder->base;
8287         struct drm_crtc *crtc = NULL;
8288         struct drm_device *dev = encoder->dev;
8289         struct drm_framebuffer *fb;
8290         int i = -1;
8291
8292         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8293                       connector->base.id, drm_get_connector_name(connector),
8294                       encoder->base.id, drm_get_encoder_name(encoder));
8295
8296         /*
8297          * Algorithm gets a little messy:
8298          *
8299          *   - if the connector already has an assigned crtc, use it (but make
8300          *     sure it's on first)
8301          *
8302          *   - try to find the first unused crtc that can drive this connector,
8303          *     and use that if we find one
8304          */
8305
8306         /* See if we already have a CRTC for this connector */
8307         if (encoder->crtc) {
8308                 crtc = encoder->crtc;
8309
8310                 mutex_lock(&crtc->mutex);
8311
8312                 old->dpms_mode = connector->dpms;
8313                 old->load_detect_temp = false;
8314
8315                 /* Make sure the crtc and connector are running */
8316                 if (connector->dpms != DRM_MODE_DPMS_ON)
8317                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8318
8319                 return true;
8320         }
8321
8322         /* Find an unused one (if possible) */
8323         for_each_crtc(dev, possible_crtc) {
8324                 i++;
8325                 if (!(encoder->possible_crtcs & (1 << i)))
8326                         continue;
8327                 if (!possible_crtc->enabled) {
8328                         crtc = possible_crtc;
8329                         break;
8330                 }
8331         }
8332
8333         /*
8334          * If we didn't find an unused CRTC, don't use any.
8335          */
8336         if (!crtc) {
8337                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8338                 return false;
8339         }
8340
8341         mutex_lock(&crtc->mutex);
8342         intel_encoder->new_crtc = to_intel_crtc(crtc);
8343         to_intel_connector(connector)->new_encoder = intel_encoder;
8344
8345         intel_crtc = to_intel_crtc(crtc);
8346         intel_crtc->new_enabled = true;
8347         intel_crtc->new_config = &intel_crtc->config;
8348         old->dpms_mode = connector->dpms;
8349         old->load_detect_temp = true;
8350         old->release_fb = NULL;
8351
8352         if (!mode)
8353                 mode = &load_detect_mode;
8354
8355         /* We need a framebuffer large enough to accommodate all accesses
8356          * that the plane may generate whilst we perform load detection.
8357          * We can not rely on the fbcon either being present (we get called
8358          * during its initialisation to detect all boot displays, or it may
8359          * not even exist) or that it is large enough to satisfy the
8360          * requested mode.
8361          */
8362         fb = mode_fits_in_fbdev(dev, mode);
8363         if (fb == NULL) {
8364                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8365                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8366                 old->release_fb = fb;
8367         } else
8368                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8369         if (IS_ERR(fb)) {
8370                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8371                 goto fail;
8372         }
8373
8374         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8375                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8376                 if (old->release_fb)
8377                         old->release_fb->funcs->destroy(old->release_fb);
8378                 goto fail;
8379         }
8380
8381         /* let the connector get through one full cycle before testing */
8382         intel_wait_for_vblank(dev, intel_crtc->pipe);
8383         return true;
8384
8385  fail:
8386         intel_crtc->new_enabled = crtc->enabled;
8387         if (intel_crtc->new_enabled)
8388                 intel_crtc->new_config = &intel_crtc->config;
8389         else
8390                 intel_crtc->new_config = NULL;
8391         mutex_unlock(&crtc->mutex);
8392         return false;
8393 }
8394
8395 void intel_release_load_detect_pipe(struct drm_connector *connector,
8396                                     struct intel_load_detect_pipe *old)
8397 {
8398         struct intel_encoder *intel_encoder =
8399                 intel_attached_encoder(connector);
8400         struct drm_encoder *encoder = &intel_encoder->base;
8401         struct drm_crtc *crtc = encoder->crtc;
8402         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8403
8404         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8405                       connector->base.id, drm_get_connector_name(connector),
8406                       encoder->base.id, drm_get_encoder_name(encoder));
8407
8408         if (old->load_detect_temp) {
8409                 to_intel_connector(connector)->new_encoder = NULL;
8410                 intel_encoder->new_crtc = NULL;
8411                 intel_crtc->new_enabled = false;
8412                 intel_crtc->new_config = NULL;
8413                 intel_set_mode(crtc, NULL, 0, 0, NULL);
8414
8415                 if (old->release_fb) {
8416                         drm_framebuffer_unregister_private(old->release_fb);
8417                         drm_framebuffer_unreference(old->release_fb);
8418                 }
8419
8420                 mutex_unlock(&crtc->mutex);
8421                 return;
8422         }
8423
8424         /* Switch crtc and encoder back off if necessary */
8425         if (old->dpms_mode != DRM_MODE_DPMS_ON)
8426                 connector->funcs->dpms(connector, old->dpms_mode);
8427
8428         mutex_unlock(&crtc->mutex);
8429 }
8430
8431 static int i9xx_pll_refclk(struct drm_device *dev,
8432                            const struct intel_crtc_config *pipe_config)
8433 {
8434         struct drm_i915_private *dev_priv = dev->dev_private;
8435         u32 dpll = pipe_config->dpll_hw_state.dpll;
8436
8437         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8438                 return dev_priv->vbt.lvds_ssc_freq;
8439         else if (HAS_PCH_SPLIT(dev))
8440                 return 120000;
8441         else if (!IS_GEN2(dev))
8442                 return 96000;
8443         else
8444                 return 48000;
8445 }
8446
8447 /* Returns the clock of the currently programmed mode of the given pipe. */
8448 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8449                                 struct intel_crtc_config *pipe_config)
8450 {
8451         struct drm_device *dev = crtc->base.dev;
8452         struct drm_i915_private *dev_priv = dev->dev_private;
8453         int pipe = pipe_config->cpu_transcoder;
8454         u32 dpll = pipe_config->dpll_hw_state.dpll;
8455         u32 fp;
8456         intel_clock_t clock;
8457         int refclk = i9xx_pll_refclk(dev, pipe_config);
8458
8459         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8460                 fp = pipe_config->dpll_hw_state.fp0;
8461         else
8462                 fp = pipe_config->dpll_hw_state.fp1;
8463
8464         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8465         if (IS_PINEVIEW(dev)) {
8466                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8467                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8468         } else {
8469                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8470                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8471         }
8472
8473         if (!IS_GEN2(dev)) {
8474                 if (IS_PINEVIEW(dev))
8475                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8476                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8477                 else
8478                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8479                                DPLL_FPA01_P1_POST_DIV_SHIFT);
8480
8481                 switch (dpll & DPLL_MODE_MASK) {
8482                 case DPLLB_MODE_DAC_SERIAL:
8483                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8484                                 5 : 10;
8485                         break;
8486                 case DPLLB_MODE_LVDS:
8487                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8488                                 7 : 14;
8489                         break;
8490                 default:
8491                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8492                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
8493                         return;
8494                 }
8495
8496                 if (IS_PINEVIEW(dev))
8497                         pineview_clock(refclk, &clock);
8498                 else
8499                         i9xx_clock(refclk, &clock);
8500         } else {
8501                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8502                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8503
8504                 if (is_lvds) {
8505                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8506                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
8507
8508                         if (lvds & LVDS_CLKB_POWER_UP)
8509                                 clock.p2 = 7;
8510                         else
8511                                 clock.p2 = 14;
8512                 } else {
8513                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
8514                                 clock.p1 = 2;
8515                         else {
8516                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8517                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8518                         }
8519                         if (dpll & PLL_P2_DIVIDE_BY_4)
8520                                 clock.p2 = 4;
8521                         else
8522                                 clock.p2 = 2;
8523                 }
8524
8525                 i9xx_clock(refclk, &clock);
8526         }
8527
8528         /*
8529          * This value includes pixel_multiplier. We will use
8530          * port_clock to compute adjusted_mode.crtc_clock in the
8531          * encoder's get_config() function.
8532          */
8533         pipe_config->port_clock = clock.dot;
8534 }
8535
8536 int intel_dotclock_calculate(int link_freq,
8537                              const struct intel_link_m_n *m_n)
8538 {
8539         /*
8540          * The calculation for the data clock is:
8541          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8542          * But we want to avoid losing precison if possible, so:
8543          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8544          *
8545          * and the link clock is simpler:
8546          * link_clock = (m * link_clock) / n
8547          */
8548
8549         if (!m_n->link_n)
8550                 return 0;
8551
8552         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8553 }
8554
8555 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8556                                    struct intel_crtc_config *pipe_config)
8557 {
8558         struct drm_device *dev = crtc->base.dev;
8559
8560         /* read out port_clock from the DPLL */
8561         i9xx_crtc_clock_get(crtc, pipe_config);
8562
8563         /*
8564          * This value does not include pixel_multiplier.
8565          * We will check that port_clock and adjusted_mode.crtc_clock
8566          * agree once we know their relationship in the encoder's
8567          * get_config() function.
8568          */
8569         pipe_config->adjusted_mode.crtc_clock =
8570                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8571                                          &pipe_config->fdi_m_n);
8572 }
8573
8574 /** Returns the currently programmed mode of the given pipe. */
8575 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8576                                              struct drm_crtc *crtc)
8577 {
8578         struct drm_i915_private *dev_priv = dev->dev_private;
8579         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8580         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8581         struct drm_display_mode *mode;
8582         struct intel_crtc_config pipe_config;
8583         int htot = I915_READ(HTOTAL(cpu_transcoder));
8584         int hsync = I915_READ(HSYNC(cpu_transcoder));
8585         int vtot = I915_READ(VTOTAL(cpu_transcoder));
8586         int vsync = I915_READ(VSYNC(cpu_transcoder));
8587         enum pipe pipe = intel_crtc->pipe;
8588
8589         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8590         if (!mode)
8591                 return NULL;
8592
8593         /*
8594          * Construct a pipe_config sufficient for getting the clock info
8595          * back out of crtc_clock_get.
8596          *
8597          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8598          * to use a real value here instead.
8599          */
8600         pipe_config.cpu_transcoder = (enum transcoder) pipe;
8601         pipe_config.pixel_multiplier = 1;
8602         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8603         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8604         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8605         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8606
8607         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8608         mode->hdisplay = (htot & 0xffff) + 1;
8609         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8610         mode->hsync_start = (hsync & 0xffff) + 1;
8611         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8612         mode->vdisplay = (vtot & 0xffff) + 1;
8613         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8614         mode->vsync_start = (vsync & 0xffff) + 1;
8615         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8616
8617         drm_mode_set_name(mode);
8618
8619         return mode;
8620 }
8621
8622 static void intel_increase_pllclock(struct drm_crtc *crtc)
8623 {
8624         struct drm_device *dev = crtc->dev;
8625         struct drm_i915_private *dev_priv = dev->dev_private;
8626         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8627         int pipe = intel_crtc->pipe;
8628         int dpll_reg = DPLL(pipe);
8629         int dpll;
8630
8631         if (HAS_PCH_SPLIT(dev))
8632                 return;
8633
8634         if (!dev_priv->lvds_downclock_avail)
8635                 return;
8636
8637         dpll = I915_READ(dpll_reg);
8638         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8639                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8640
8641                 assert_panel_unlocked(dev_priv, pipe);
8642
8643                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8644                 I915_WRITE(dpll_reg, dpll);
8645                 intel_wait_for_vblank(dev, pipe);
8646
8647                 dpll = I915_READ(dpll_reg);
8648                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8649                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8650         }
8651 }
8652
8653 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8654 {
8655         struct drm_device *dev = crtc->dev;
8656         struct drm_i915_private *dev_priv = dev->dev_private;
8657         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8658
8659         if (HAS_PCH_SPLIT(dev))
8660                 return;
8661
8662         if (!dev_priv->lvds_downclock_avail)
8663                 return;
8664
8665         /*
8666          * Since this is called by a timer, we should never get here in
8667          * the manual case.
8668          */
8669         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8670                 int pipe = intel_crtc->pipe;
8671                 int dpll_reg = DPLL(pipe);
8672                 int dpll;
8673
8674                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8675
8676                 assert_panel_unlocked(dev_priv, pipe);
8677
8678                 dpll = I915_READ(dpll_reg);
8679                 dpll |= DISPLAY_RATE_SELECT_FPA1;
8680                 I915_WRITE(dpll_reg, dpll);
8681                 intel_wait_for_vblank(dev, pipe);
8682                 dpll = I915_READ(dpll_reg);
8683                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8684                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8685         }
8686
8687 }
8688
8689 void intel_mark_busy(struct drm_device *dev)
8690 {
8691         struct drm_i915_private *dev_priv = dev->dev_private;
8692
8693         if (dev_priv->mm.busy)
8694                 return;
8695
8696         intel_runtime_pm_get(dev_priv);
8697         i915_update_gfx_val(dev_priv);
8698         dev_priv->mm.busy = true;
8699 }
8700
8701 void intel_mark_idle(struct drm_device *dev)
8702 {
8703         struct drm_i915_private *dev_priv = dev->dev_private;
8704         struct drm_crtc *crtc;
8705
8706         if (!dev_priv->mm.busy)
8707                 return;
8708
8709         dev_priv->mm.busy = false;
8710
8711         if (!i915.powersave)
8712                 goto out;
8713
8714         for_each_crtc(dev, crtc) {
8715                 if (!crtc->primary->fb)
8716                         continue;
8717
8718                 intel_decrease_pllclock(crtc);
8719         }
8720
8721         if (INTEL_INFO(dev)->gen >= 6)
8722                 gen6_rps_idle(dev->dev_private);
8723
8724 out:
8725         intel_runtime_pm_put(dev_priv);
8726 }
8727
8728 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
8729                         struct intel_ring_buffer *ring)
8730 {
8731         struct drm_device *dev = obj->base.dev;
8732         struct drm_crtc *crtc;
8733
8734         if (!i915.powersave)
8735                 return;
8736
8737         for_each_crtc(dev, crtc) {
8738                 if (!crtc->primary->fb)
8739                         continue;
8740
8741                 if (to_intel_framebuffer(crtc->primary->fb)->obj != obj)
8742                         continue;
8743
8744                 intel_increase_pllclock(crtc);
8745                 if (ring && intel_fbc_enabled(dev))
8746                         ring->fbc_dirty = true;
8747         }
8748 }
8749
8750 static void intel_crtc_destroy(struct drm_crtc *crtc)
8751 {
8752         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8753         struct drm_device *dev = crtc->dev;
8754         struct intel_unpin_work *work;
8755         unsigned long flags;
8756
8757         spin_lock_irqsave(&dev->event_lock, flags);
8758         work = intel_crtc->unpin_work;
8759         intel_crtc->unpin_work = NULL;
8760         spin_unlock_irqrestore(&dev->event_lock, flags);
8761
8762         if (work) {
8763                 cancel_work_sync(&work->work);
8764                 kfree(work);
8765         }
8766
8767         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
8768
8769         drm_crtc_cleanup(crtc);
8770
8771         kfree(intel_crtc);
8772 }
8773
8774 static void intel_unpin_work_fn(struct work_struct *__work)
8775 {
8776         struct intel_unpin_work *work =
8777                 container_of(__work, struct intel_unpin_work, work);
8778         struct drm_device *dev = work->crtc->dev;
8779
8780         mutex_lock(&dev->struct_mutex);
8781         intel_unpin_fb_obj(work->old_fb_obj);
8782         drm_gem_object_unreference(&work->pending_flip_obj->base);
8783         drm_gem_object_unreference(&work->old_fb_obj->base);
8784
8785         intel_update_fbc(dev);
8786         mutex_unlock(&dev->struct_mutex);
8787
8788         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8789         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8790
8791         kfree(work);
8792 }
8793
8794 static void do_intel_finish_page_flip(struct drm_device *dev,
8795                                       struct drm_crtc *crtc)
8796 {
8797         struct drm_i915_private *dev_priv = dev->dev_private;
8798         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8799         struct intel_unpin_work *work;
8800         unsigned long flags;
8801
8802         /* Ignore early vblank irqs */
8803         if (intel_crtc == NULL)
8804                 return;
8805
8806         spin_lock_irqsave(&dev->event_lock, flags);
8807         work = intel_crtc->unpin_work;
8808
8809         /* Ensure we don't miss a work->pending update ... */
8810         smp_rmb();
8811
8812         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8813                 spin_unlock_irqrestore(&dev->event_lock, flags);
8814                 return;
8815         }
8816
8817         /* and that the unpin work is consistent wrt ->pending. */
8818         smp_rmb();
8819
8820         intel_crtc->unpin_work = NULL;
8821
8822         if (work->event)
8823                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
8824
8825         drm_vblank_put(dev, intel_crtc->pipe);
8826
8827         spin_unlock_irqrestore(&dev->event_lock, flags);
8828
8829         wake_up_all(&dev_priv->pending_flip_queue);
8830
8831         queue_work(dev_priv->wq, &work->work);
8832
8833         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
8834 }
8835
8836 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8837 {
8838         struct drm_i915_private *dev_priv = dev->dev_private;
8839         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8840
8841         do_intel_finish_page_flip(dev, crtc);
8842 }
8843
8844 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8845 {
8846         struct drm_i915_private *dev_priv = dev->dev_private;
8847         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8848
8849         do_intel_finish_page_flip(dev, crtc);
8850 }
8851
8852 void intel_prepare_page_flip(struct drm_device *dev, int plane)
8853 {
8854         struct drm_i915_private *dev_priv = dev->dev_private;
8855         struct intel_crtc *intel_crtc =
8856                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8857         unsigned long flags;
8858
8859         /* NB: An MMIO update of the plane base pointer will also
8860          * generate a page-flip completion irq, i.e. every modeset
8861          * is also accompanied by a spurious intel_prepare_page_flip().
8862          */
8863         spin_lock_irqsave(&dev->event_lock, flags);
8864         if (intel_crtc->unpin_work)
8865                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
8866         spin_unlock_irqrestore(&dev->event_lock, flags);
8867 }
8868
8869 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8870 {
8871         /* Ensure that the work item is consistent when activating it ... */
8872         smp_wmb();
8873         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8874         /* and that it is marked active as soon as the irq could fire. */
8875         smp_wmb();
8876 }
8877
8878 static int intel_gen2_queue_flip(struct drm_device *dev,
8879                                  struct drm_crtc *crtc,
8880                                  struct drm_framebuffer *fb,
8881                                  struct drm_i915_gem_object *obj,
8882                                  uint32_t flags)
8883 {
8884         struct drm_i915_private *dev_priv = dev->dev_private;
8885         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8886         u32 flip_mask;
8887         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8888         int ret;
8889
8890         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8891         if (ret)
8892                 goto err;
8893
8894         ret = intel_ring_begin(ring, 6);
8895         if (ret)
8896                 goto err_unpin;
8897
8898         /* Can't queue multiple flips, so wait for the previous
8899          * one to finish before executing the next.
8900          */
8901         if (intel_crtc->plane)
8902                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8903         else
8904                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8905         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8906         intel_ring_emit(ring, MI_NOOP);
8907         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8908                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8909         intel_ring_emit(ring, fb->pitches[0]);
8910         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8911         intel_ring_emit(ring, 0); /* aux display base address, unused */
8912
8913         intel_mark_page_flip_active(intel_crtc);
8914         __intel_ring_advance(ring);
8915         return 0;
8916
8917 err_unpin:
8918         intel_unpin_fb_obj(obj);
8919 err:
8920         return ret;
8921 }
8922
8923 static int intel_gen3_queue_flip(struct drm_device *dev,
8924                                  struct drm_crtc *crtc,
8925                                  struct drm_framebuffer *fb,
8926                                  struct drm_i915_gem_object *obj,
8927                                  uint32_t flags)
8928 {
8929         struct drm_i915_private *dev_priv = dev->dev_private;
8930         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8931         u32 flip_mask;
8932         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8933         int ret;
8934
8935         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8936         if (ret)
8937                 goto err;
8938
8939         ret = intel_ring_begin(ring, 6);
8940         if (ret)
8941                 goto err_unpin;
8942
8943         if (intel_crtc->plane)
8944                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8945         else
8946                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8947         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8948         intel_ring_emit(ring, MI_NOOP);
8949         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8950                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8951         intel_ring_emit(ring, fb->pitches[0]);
8952         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8953         intel_ring_emit(ring, MI_NOOP);
8954
8955         intel_mark_page_flip_active(intel_crtc);
8956         __intel_ring_advance(ring);
8957         return 0;
8958
8959 err_unpin:
8960         intel_unpin_fb_obj(obj);
8961 err:
8962         return ret;
8963 }
8964
8965 static int intel_gen4_queue_flip(struct drm_device *dev,
8966                                  struct drm_crtc *crtc,
8967                                  struct drm_framebuffer *fb,
8968                                  struct drm_i915_gem_object *obj,
8969                                  uint32_t flags)
8970 {
8971         struct drm_i915_private *dev_priv = dev->dev_private;
8972         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8973         uint32_t pf, pipesrc;
8974         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8975         int ret;
8976
8977         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8978         if (ret)
8979                 goto err;
8980
8981         ret = intel_ring_begin(ring, 4);
8982         if (ret)
8983                 goto err_unpin;
8984
8985         /* i965+ uses the linear or tiled offsets from the
8986          * Display Registers (which do not change across a page-flip)
8987          * so we need only reprogram the base address.
8988          */
8989         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8990                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8991         intel_ring_emit(ring, fb->pitches[0]);
8992         intel_ring_emit(ring,
8993                         (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
8994                         obj->tiling_mode);
8995
8996         /* XXX Enabling the panel-fitter across page-flip is so far
8997          * untested on non-native modes, so ignore it for now.
8998          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8999          */
9000         pf = 0;
9001         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9002         intel_ring_emit(ring, pf | pipesrc);
9003
9004         intel_mark_page_flip_active(intel_crtc);
9005         __intel_ring_advance(ring);
9006         return 0;
9007
9008 err_unpin:
9009         intel_unpin_fb_obj(obj);
9010 err:
9011         return ret;
9012 }
9013
9014 static int intel_gen6_queue_flip(struct drm_device *dev,
9015                                  struct drm_crtc *crtc,
9016                                  struct drm_framebuffer *fb,
9017                                  struct drm_i915_gem_object *obj,
9018                                  uint32_t flags)
9019 {
9020         struct drm_i915_private *dev_priv = dev->dev_private;
9021         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9022         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
9023         uint32_t pf, pipesrc;
9024         int ret;
9025
9026         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9027         if (ret)
9028                 goto err;
9029
9030         ret = intel_ring_begin(ring, 4);
9031         if (ret)
9032                 goto err_unpin;
9033
9034         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9035                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9036         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9037         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
9038
9039         /* Contrary to the suggestions in the documentation,
9040          * "Enable Panel Fitter" does not seem to be required when page
9041          * flipping with a non-native mode, and worse causes a normal
9042          * modeset to fail.
9043          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9044          */
9045         pf = 0;
9046         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9047         intel_ring_emit(ring, pf | pipesrc);
9048
9049         intel_mark_page_flip_active(intel_crtc);
9050         __intel_ring_advance(ring);
9051         return 0;
9052
9053 err_unpin:
9054         intel_unpin_fb_obj(obj);
9055 err:
9056         return ret;
9057 }
9058
9059 static int intel_gen7_queue_flip(struct drm_device *dev,
9060                                  struct drm_crtc *crtc,
9061                                  struct drm_framebuffer *fb,
9062                                  struct drm_i915_gem_object *obj,
9063                                  uint32_t flags)
9064 {
9065         struct drm_i915_private *dev_priv = dev->dev_private;
9066         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9067         struct intel_ring_buffer *ring;
9068         uint32_t plane_bit = 0;
9069         int len, ret;
9070
9071         ring = obj->ring;
9072         if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
9073                 ring = &dev_priv->ring[BCS];
9074
9075         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9076         if (ret)
9077                 goto err;
9078
9079         switch(intel_crtc->plane) {
9080         case PLANE_A:
9081                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9082                 break;
9083         case PLANE_B:
9084                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9085                 break;
9086         case PLANE_C:
9087                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9088                 break;
9089         default:
9090                 WARN_ONCE(1, "unknown plane in flip command\n");
9091                 ret = -ENODEV;
9092                 goto err_unpin;
9093         }
9094
9095         len = 4;
9096         if (ring->id == RCS) {
9097                 len += 6;
9098                 /*
9099                  * On Gen 8, SRM is now taking an extra dword to accommodate
9100                  * 48bits addresses, and we need a NOOP for the batch size to
9101                  * stay even.
9102                  */
9103                 if (IS_GEN8(dev))
9104                         len += 2;
9105         }
9106
9107         /*
9108          * BSpec MI_DISPLAY_FLIP for IVB:
9109          * "The full packet must be contained within the same cache line."
9110          *
9111          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9112          * cacheline, if we ever start emitting more commands before
9113          * the MI_DISPLAY_FLIP we may need to first emit everything else,
9114          * then do the cacheline alignment, and finally emit the
9115          * MI_DISPLAY_FLIP.
9116          */
9117         ret = intel_ring_cacheline_align(ring);
9118         if (ret)
9119                 goto err_unpin;
9120
9121         ret = intel_ring_begin(ring, len);
9122         if (ret)
9123                 goto err_unpin;
9124
9125         /* Unmask the flip-done completion message. Note that the bspec says that
9126          * we should do this for both the BCS and RCS, and that we must not unmask
9127          * more than one flip event at any time (or ensure that one flip message
9128          * can be sent by waiting for flip-done prior to queueing new flips).
9129          * Experimentation says that BCS works despite DERRMR masking all
9130          * flip-done completion events and that unmasking all planes at once
9131          * for the RCS also doesn't appear to drop events. Setting the DERRMR
9132          * to zero does lead to lockups within MI_DISPLAY_FLIP.
9133          */
9134         if (ring->id == RCS) {
9135                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9136                 intel_ring_emit(ring, DERRMR);
9137                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9138                                         DERRMR_PIPEB_PRI_FLIP_DONE |
9139                                         DERRMR_PIPEC_PRI_FLIP_DONE));
9140                 if (IS_GEN8(dev))
9141                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9142                                               MI_SRM_LRM_GLOBAL_GTT);
9143                 else
9144                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9145                                               MI_SRM_LRM_GLOBAL_GTT);
9146                 intel_ring_emit(ring, DERRMR);
9147                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9148                 if (IS_GEN8(dev)) {
9149                         intel_ring_emit(ring, 0);
9150                         intel_ring_emit(ring, MI_NOOP);
9151                 }
9152         }
9153
9154         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9155         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9156         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
9157         intel_ring_emit(ring, (MI_NOOP));
9158
9159         intel_mark_page_flip_active(intel_crtc);
9160         __intel_ring_advance(ring);
9161         return 0;
9162
9163 err_unpin:
9164         intel_unpin_fb_obj(obj);
9165 err:
9166         return ret;
9167 }
9168
9169 static int intel_default_queue_flip(struct drm_device *dev,
9170                                     struct drm_crtc *crtc,
9171                                     struct drm_framebuffer *fb,
9172                                     struct drm_i915_gem_object *obj,
9173                                     uint32_t flags)
9174 {
9175         return -ENODEV;
9176 }
9177
9178 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9179                                 struct drm_framebuffer *fb,
9180                                 struct drm_pending_vblank_event *event,
9181                                 uint32_t page_flip_flags)
9182 {
9183         struct drm_device *dev = crtc->dev;
9184         struct drm_i915_private *dev_priv = dev->dev_private;
9185         struct drm_framebuffer *old_fb = crtc->primary->fb;
9186         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
9187         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9188         struct intel_unpin_work *work;
9189         unsigned long flags;
9190         int ret;
9191
9192         /* Can't change pixel format via MI display flips. */
9193         if (fb->pixel_format != crtc->primary->fb->pixel_format)
9194                 return -EINVAL;
9195
9196         /*
9197          * TILEOFF/LINOFF registers can't be changed via MI display flips.
9198          * Note that pitch changes could also affect these register.
9199          */
9200         if (INTEL_INFO(dev)->gen > 3 &&
9201             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9202              fb->pitches[0] != crtc->primary->fb->pitches[0]))
9203                 return -EINVAL;
9204
9205         if (i915_terminally_wedged(&dev_priv->gpu_error))
9206                 goto out_hang;
9207
9208         work = kzalloc(sizeof(*work), GFP_KERNEL);
9209         if (work == NULL)
9210                 return -ENOMEM;
9211
9212         work->event = event;
9213         work->crtc = crtc;
9214         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
9215         INIT_WORK(&work->work, intel_unpin_work_fn);
9216
9217         ret = drm_vblank_get(dev, intel_crtc->pipe);
9218         if (ret)
9219                 goto free_work;
9220
9221         /* We borrow the event spin lock for protecting unpin_work */
9222         spin_lock_irqsave(&dev->event_lock, flags);
9223         if (intel_crtc->unpin_work) {
9224                 spin_unlock_irqrestore(&dev->event_lock, flags);
9225                 kfree(work);
9226                 drm_vblank_put(dev, intel_crtc->pipe);
9227
9228                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9229                 return -EBUSY;
9230         }
9231         intel_crtc->unpin_work = work;
9232         spin_unlock_irqrestore(&dev->event_lock, flags);
9233
9234         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9235                 flush_workqueue(dev_priv->wq);
9236
9237         ret = i915_mutex_lock_interruptible(dev);
9238         if (ret)
9239                 goto cleanup;
9240
9241         /* Reference the objects for the scheduled work. */
9242         drm_gem_object_reference(&work->old_fb_obj->base);
9243         drm_gem_object_reference(&obj->base);
9244
9245         crtc->primary->fb = fb;
9246
9247         work->pending_flip_obj = obj;
9248
9249         work->enable_stall_check = true;
9250
9251         atomic_inc(&intel_crtc->unpin_work_count);
9252         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9253
9254         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
9255         if (ret)
9256                 goto cleanup_pending;
9257
9258         intel_disable_fbc(dev);
9259         intel_mark_fb_busy(obj, NULL);
9260         mutex_unlock(&dev->struct_mutex);
9261
9262         trace_i915_flip_request(intel_crtc->plane, obj);
9263
9264         return 0;
9265
9266 cleanup_pending:
9267         atomic_dec(&intel_crtc->unpin_work_count);
9268         crtc->primary->fb = old_fb;
9269         drm_gem_object_unreference(&work->old_fb_obj->base);
9270         drm_gem_object_unreference(&obj->base);
9271         mutex_unlock(&dev->struct_mutex);
9272
9273 cleanup:
9274         spin_lock_irqsave(&dev->event_lock, flags);
9275         intel_crtc->unpin_work = NULL;
9276         spin_unlock_irqrestore(&dev->event_lock, flags);
9277
9278         drm_vblank_put(dev, intel_crtc->pipe);
9279 free_work:
9280         kfree(work);
9281
9282         if (ret == -EIO) {
9283 out_hang:
9284                 intel_crtc_wait_for_pending_flips(crtc);
9285                 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9286                 if (ret == 0 && event)
9287                         drm_send_vblank_event(dev, intel_crtc->pipe, event);
9288         }
9289         return ret;
9290 }
9291
9292 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9293         .mode_set_base_atomic = intel_pipe_set_base_atomic,
9294         .load_lut = intel_crtc_load_lut,
9295 };
9296
9297 /**
9298  * intel_modeset_update_staged_output_state
9299  *
9300  * Updates the staged output configuration state, e.g. after we've read out the
9301  * current hw state.
9302  */
9303 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9304 {
9305         struct intel_crtc *crtc;
9306         struct intel_encoder *encoder;
9307         struct intel_connector *connector;
9308
9309         list_for_each_entry(connector, &dev->mode_config.connector_list,
9310                             base.head) {
9311                 connector->new_encoder =
9312                         to_intel_encoder(connector->base.encoder);
9313         }
9314
9315         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9316                             base.head) {
9317                 encoder->new_crtc =
9318                         to_intel_crtc(encoder->base.crtc);
9319         }
9320
9321         for_each_intel_crtc(dev, crtc) {
9322                 crtc->new_enabled = crtc->base.enabled;
9323
9324                 if (crtc->new_enabled)
9325                         crtc->new_config = &crtc->config;
9326                 else
9327                         crtc->new_config = NULL;
9328         }
9329 }
9330
9331 /**
9332  * intel_modeset_commit_output_state
9333  *
9334  * This function copies the stage display pipe configuration to the real one.
9335  */
9336 static void intel_modeset_commit_output_state(struct drm_device *dev)
9337 {
9338         struct intel_crtc *crtc;
9339         struct intel_encoder *encoder;
9340         struct intel_connector *connector;
9341
9342         list_for_each_entry(connector, &dev->mode_config.connector_list,
9343                             base.head) {
9344                 connector->base.encoder = &connector->new_encoder->base;
9345         }
9346
9347         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9348                             base.head) {
9349                 encoder->base.crtc = &encoder->new_crtc->base;
9350         }
9351
9352         for_each_intel_crtc(dev, crtc) {
9353                 crtc->base.enabled = crtc->new_enabled;
9354         }
9355 }
9356
9357 static void
9358 connected_sink_compute_bpp(struct intel_connector * connector,
9359                            struct intel_crtc_config *pipe_config)
9360 {
9361         int bpp = pipe_config->pipe_bpp;
9362
9363         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9364                 connector->base.base.id,
9365                 drm_get_connector_name(&connector->base));
9366
9367         /* Don't use an invalid EDID bpc value */
9368         if (connector->base.display_info.bpc &&
9369             connector->base.display_info.bpc * 3 < bpp) {
9370                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9371                               bpp, connector->base.display_info.bpc*3);
9372                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9373         }
9374
9375         /* Clamp bpp to 8 on screens without EDID 1.4 */
9376         if (connector->base.display_info.bpc == 0 && bpp > 24) {
9377                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9378                               bpp);
9379                 pipe_config->pipe_bpp = 24;
9380         }
9381 }
9382
9383 static int
9384 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9385                           struct drm_framebuffer *fb,
9386                           struct intel_crtc_config *pipe_config)
9387 {
9388         struct drm_device *dev = crtc->base.dev;
9389         struct intel_connector *connector;
9390         int bpp;
9391
9392         switch (fb->pixel_format) {
9393         case DRM_FORMAT_C8:
9394                 bpp = 8*3; /* since we go through a colormap */
9395                 break;
9396         case DRM_FORMAT_XRGB1555:
9397         case DRM_FORMAT_ARGB1555:
9398                 /* checked in intel_framebuffer_init already */
9399                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9400                         return -EINVAL;
9401         case DRM_FORMAT_RGB565:
9402                 bpp = 6*3; /* min is 18bpp */
9403                 break;
9404         case DRM_FORMAT_XBGR8888:
9405         case DRM_FORMAT_ABGR8888:
9406                 /* checked in intel_framebuffer_init already */
9407                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9408                         return -EINVAL;
9409         case DRM_FORMAT_XRGB8888:
9410         case DRM_FORMAT_ARGB8888:
9411                 bpp = 8*3;
9412                 break;
9413         case DRM_FORMAT_XRGB2101010:
9414         case DRM_FORMAT_ARGB2101010:
9415         case DRM_FORMAT_XBGR2101010:
9416         case DRM_FORMAT_ABGR2101010:
9417                 /* checked in intel_framebuffer_init already */
9418                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9419                         return -EINVAL;
9420                 bpp = 10*3;
9421                 break;
9422         /* TODO: gen4+ supports 16 bpc floating point, too. */
9423         default:
9424                 DRM_DEBUG_KMS("unsupported depth\n");
9425                 return -EINVAL;
9426         }
9427
9428         pipe_config->pipe_bpp = bpp;
9429
9430         /* Clamp display bpp to EDID value */
9431         list_for_each_entry(connector, &dev->mode_config.connector_list,
9432                             base.head) {
9433                 if (!connector->new_encoder ||
9434                     connector->new_encoder->new_crtc != crtc)
9435                         continue;
9436
9437                 connected_sink_compute_bpp(connector, pipe_config);
9438         }
9439
9440         return bpp;
9441 }
9442
9443 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9444 {
9445         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9446                         "type: 0x%x flags: 0x%x\n",
9447                 mode->crtc_clock,
9448                 mode->crtc_hdisplay, mode->crtc_hsync_start,
9449                 mode->crtc_hsync_end, mode->crtc_htotal,
9450                 mode->crtc_vdisplay, mode->crtc_vsync_start,
9451                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9452 }
9453
9454 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9455                                    struct intel_crtc_config *pipe_config,
9456                                    const char *context)
9457 {
9458         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9459                       context, pipe_name(crtc->pipe));
9460
9461         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9462         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9463                       pipe_config->pipe_bpp, pipe_config->dither);
9464         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9465                       pipe_config->has_pch_encoder,
9466                       pipe_config->fdi_lanes,
9467                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9468                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9469                       pipe_config->fdi_m_n.tu);
9470         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9471                       pipe_config->has_dp_encoder,
9472                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9473                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9474                       pipe_config->dp_m_n.tu);
9475         DRM_DEBUG_KMS("requested mode:\n");
9476         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9477         DRM_DEBUG_KMS("adjusted mode:\n");
9478         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9479         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9480         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9481         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9482                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9483         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9484                       pipe_config->gmch_pfit.control,
9485                       pipe_config->gmch_pfit.pgm_ratios,
9486                       pipe_config->gmch_pfit.lvds_border_bits);
9487         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9488                       pipe_config->pch_pfit.pos,
9489                       pipe_config->pch_pfit.size,
9490                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9491         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9492         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
9493 }
9494
9495 static bool encoders_cloneable(const struct intel_encoder *a,
9496                                const struct intel_encoder *b)
9497 {
9498         /* masks could be asymmetric, so check both ways */
9499         return a == b || (a->cloneable & (1 << b->type) &&
9500                           b->cloneable & (1 << a->type));
9501 }
9502
9503 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9504                                          struct intel_encoder *encoder)
9505 {
9506         struct drm_device *dev = crtc->base.dev;
9507         struct intel_encoder *source_encoder;
9508
9509         list_for_each_entry(source_encoder,
9510                             &dev->mode_config.encoder_list, base.head) {
9511                 if (source_encoder->new_crtc != crtc)
9512                         continue;
9513
9514                 if (!encoders_cloneable(encoder, source_encoder))
9515                         return false;
9516         }
9517
9518         return true;
9519 }
9520
9521 static bool check_encoder_cloning(struct intel_crtc *crtc)
9522 {
9523         struct drm_device *dev = crtc->base.dev;
9524         struct intel_encoder *encoder;
9525
9526         list_for_each_entry(encoder,
9527                             &dev->mode_config.encoder_list, base.head) {
9528                 if (encoder->new_crtc != crtc)
9529                         continue;
9530
9531                 if (!check_single_encoder_cloning(crtc, encoder))
9532                         return false;
9533         }
9534
9535         return true;
9536 }
9537
9538 static struct intel_crtc_config *
9539 intel_modeset_pipe_config(struct drm_crtc *crtc,
9540                           struct drm_framebuffer *fb,
9541                           struct drm_display_mode *mode)
9542 {
9543         struct drm_device *dev = crtc->dev;
9544         struct intel_encoder *encoder;
9545         struct intel_crtc_config *pipe_config;
9546         int plane_bpp, ret = -EINVAL;
9547         bool retry = true;
9548
9549         if (!check_encoder_cloning(to_intel_crtc(crtc))) {
9550                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
9551                 return ERR_PTR(-EINVAL);
9552         }
9553
9554         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9555         if (!pipe_config)
9556                 return ERR_PTR(-ENOMEM);
9557
9558         drm_mode_copy(&pipe_config->adjusted_mode, mode);
9559         drm_mode_copy(&pipe_config->requested_mode, mode);
9560
9561         pipe_config->cpu_transcoder =
9562                 (enum transcoder) to_intel_crtc(crtc)->pipe;
9563         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9564
9565         /*
9566          * Sanitize sync polarity flags based on requested ones. If neither
9567          * positive or negative polarity is requested, treat this as meaning
9568          * negative polarity.
9569          */
9570         if (!(pipe_config->adjusted_mode.flags &
9571               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
9572                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
9573
9574         if (!(pipe_config->adjusted_mode.flags &
9575               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
9576                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
9577
9578         /* Compute a starting value for pipe_config->pipe_bpp taking the source
9579          * plane pixel format and any sink constraints into account. Returns the
9580          * source plane bpp so that dithering can be selected on mismatches
9581          * after encoders and crtc also have had their say. */
9582         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
9583                                               fb, pipe_config);
9584         if (plane_bpp < 0)
9585                 goto fail;
9586
9587         /*
9588          * Determine the real pipe dimensions. Note that stereo modes can
9589          * increase the actual pipe size due to the frame doubling and
9590          * insertion of additional space for blanks between the frame. This
9591          * is stored in the crtc timings. We use the requested mode to do this
9592          * computation to clearly distinguish it from the adjusted mode, which
9593          * can be changed by the connectors in the below retry loop.
9594          */
9595         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
9596         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
9597         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
9598
9599 encoder_retry:
9600         /* Ensure the port clock defaults are reset when retrying. */
9601         pipe_config->port_clock = 0;
9602         pipe_config->pixel_multiplier = 1;
9603
9604         /* Fill in default crtc timings, allow encoders to overwrite them. */
9605         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
9606
9607         /* Pass our mode to the connectors and the CRTC to give them a chance to
9608          * adjust it according to limitations or connector properties, and also
9609          * a chance to reject the mode entirely.
9610          */
9611         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9612                             base.head) {
9613
9614                 if (&encoder->new_crtc->base != crtc)
9615                         continue;
9616
9617                 if (!(encoder->compute_config(encoder, pipe_config))) {
9618                         DRM_DEBUG_KMS("Encoder config failure\n");
9619                         goto fail;
9620                 }
9621         }
9622
9623         /* Set default port clock if not overwritten by the encoder. Needs to be
9624          * done afterwards in case the encoder adjusts the mode. */
9625         if (!pipe_config->port_clock)
9626                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
9627                         * pipe_config->pixel_multiplier;
9628
9629         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
9630         if (ret < 0) {
9631                 DRM_DEBUG_KMS("CRTC fixup failed\n");
9632                 goto fail;
9633         }
9634
9635         if (ret == RETRY) {
9636                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
9637                         ret = -EINVAL;
9638                         goto fail;
9639                 }
9640
9641                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9642                 retry = false;
9643                 goto encoder_retry;
9644         }
9645
9646         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
9647         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9648                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
9649
9650         return pipe_config;
9651 fail:
9652         kfree(pipe_config);
9653         return ERR_PTR(ret);
9654 }
9655
9656 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
9657  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9658 static void
9659 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
9660                              unsigned *prepare_pipes, unsigned *disable_pipes)
9661 {
9662         struct intel_crtc *intel_crtc;
9663         struct drm_device *dev = crtc->dev;
9664         struct intel_encoder *encoder;
9665         struct intel_connector *connector;
9666         struct drm_crtc *tmp_crtc;
9667
9668         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
9669
9670         /* Check which crtcs have changed outputs connected to them, these need
9671          * to be part of the prepare_pipes mask. We don't (yet) support global
9672          * modeset across multiple crtcs, so modeset_pipes will only have one
9673          * bit set at most. */
9674         list_for_each_entry(connector, &dev->mode_config.connector_list,
9675                             base.head) {
9676                 if (connector->base.encoder == &connector->new_encoder->base)
9677                         continue;
9678
9679                 if (connector->base.encoder) {
9680                         tmp_crtc = connector->base.encoder->crtc;
9681
9682                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9683                 }
9684
9685                 if (connector->new_encoder)
9686                         *prepare_pipes |=
9687                                 1 << connector->new_encoder->new_crtc->pipe;
9688         }
9689
9690         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9691                             base.head) {
9692                 if (encoder->base.crtc == &encoder->new_crtc->base)
9693                         continue;
9694
9695                 if (encoder->base.crtc) {
9696                         tmp_crtc = encoder->base.crtc;
9697
9698                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9699                 }
9700
9701                 if (encoder->new_crtc)
9702                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
9703         }
9704
9705         /* Check for pipes that will be enabled/disabled ... */
9706         for_each_intel_crtc(dev, intel_crtc) {
9707                 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
9708                         continue;
9709
9710                 if (!intel_crtc->new_enabled)
9711                         *disable_pipes |= 1 << intel_crtc->pipe;
9712                 else
9713                         *prepare_pipes |= 1 << intel_crtc->pipe;
9714         }
9715
9716
9717         /* set_mode is also used to update properties on life display pipes. */
9718         intel_crtc = to_intel_crtc(crtc);
9719         if (intel_crtc->new_enabled)
9720                 *prepare_pipes |= 1 << intel_crtc->pipe;
9721
9722         /*
9723          * For simplicity do a full modeset on any pipe where the output routing
9724          * changed. We could be more clever, but that would require us to be
9725          * more careful with calling the relevant encoder->mode_set functions.
9726          */
9727         if (*prepare_pipes)
9728                 *modeset_pipes = *prepare_pipes;
9729
9730         /* ... and mask these out. */
9731         *modeset_pipes &= ~(*disable_pipes);
9732         *prepare_pipes &= ~(*disable_pipes);
9733
9734         /*
9735          * HACK: We don't (yet) fully support global modesets. intel_set_config
9736          * obies this rule, but the modeset restore mode of
9737          * intel_modeset_setup_hw_state does not.
9738          */
9739         *modeset_pipes &= 1 << intel_crtc->pipe;
9740         *prepare_pipes &= 1 << intel_crtc->pipe;
9741
9742         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9743                       *modeset_pipes, *prepare_pipes, *disable_pipes);
9744 }
9745
9746 static bool intel_crtc_in_use(struct drm_crtc *crtc)
9747 {
9748         struct drm_encoder *encoder;
9749         struct drm_device *dev = crtc->dev;
9750
9751         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
9752                 if (encoder->crtc == crtc)
9753                         return true;
9754
9755         return false;
9756 }
9757
9758 static void
9759 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
9760 {
9761         struct intel_encoder *intel_encoder;
9762         struct intel_crtc *intel_crtc;
9763         struct drm_connector *connector;
9764
9765         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
9766                             base.head) {
9767                 if (!intel_encoder->base.crtc)
9768                         continue;
9769
9770                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
9771
9772                 if (prepare_pipes & (1 << intel_crtc->pipe))
9773                         intel_encoder->connectors_active = false;
9774         }
9775
9776         intel_modeset_commit_output_state(dev);
9777
9778         /* Double check state. */
9779         for_each_intel_crtc(dev, intel_crtc) {
9780                 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
9781                 WARN_ON(intel_crtc->new_config &&
9782                         intel_crtc->new_config != &intel_crtc->config);
9783                 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
9784         }
9785
9786         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9787                 if (!connector->encoder || !connector->encoder->crtc)
9788                         continue;
9789
9790                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
9791
9792                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
9793                         struct drm_property *dpms_property =
9794                                 dev->mode_config.dpms_property;
9795
9796                         connector->dpms = DRM_MODE_DPMS_ON;
9797                         drm_object_property_set_value(&connector->base,
9798                                                          dpms_property,
9799                                                          DRM_MODE_DPMS_ON);
9800
9801                         intel_encoder = to_intel_encoder(connector->encoder);
9802                         intel_encoder->connectors_active = true;
9803                 }
9804         }
9805
9806 }
9807
9808 static bool intel_fuzzy_clock_check(int clock1, int clock2)
9809 {
9810         int diff;
9811
9812         if (clock1 == clock2)
9813                 return true;
9814
9815         if (!clock1 || !clock2)
9816                 return false;
9817
9818         diff = abs(clock1 - clock2);
9819
9820         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
9821                 return true;
9822
9823         return false;
9824 }
9825
9826 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9827         list_for_each_entry((intel_crtc), \
9828                             &(dev)->mode_config.crtc_list, \
9829                             base.head) \
9830                 if (mask & (1 <<(intel_crtc)->pipe))
9831
9832 static bool
9833 intel_pipe_config_compare(struct drm_device *dev,
9834                           struct intel_crtc_config *current_config,
9835                           struct intel_crtc_config *pipe_config)
9836 {
9837 #define PIPE_CONF_CHECK_X(name) \
9838         if (current_config->name != pipe_config->name) { \
9839                 DRM_ERROR("mismatch in " #name " " \
9840                           "(expected 0x%08x, found 0x%08x)\n", \
9841                           current_config->name, \
9842                           pipe_config->name); \
9843                 return false; \
9844         }
9845
9846 #define PIPE_CONF_CHECK_I(name) \
9847         if (current_config->name != pipe_config->name) { \
9848                 DRM_ERROR("mismatch in " #name " " \
9849                           "(expected %i, found %i)\n", \
9850                           current_config->name, \
9851                           pipe_config->name); \
9852                 return false; \
9853         }
9854
9855 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
9856         if ((current_config->name ^ pipe_config->name) & (mask)) { \
9857                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
9858                           "(expected %i, found %i)\n", \
9859                           current_config->name & (mask), \
9860                           pipe_config->name & (mask)); \
9861                 return false; \
9862         }
9863
9864 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9865         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9866                 DRM_ERROR("mismatch in " #name " " \
9867                           "(expected %i, found %i)\n", \
9868                           current_config->name, \
9869                           pipe_config->name); \
9870                 return false; \
9871         }
9872
9873 #define PIPE_CONF_QUIRK(quirk)  \
9874         ((current_config->quirks | pipe_config->quirks) & (quirk))
9875
9876         PIPE_CONF_CHECK_I(cpu_transcoder);
9877
9878         PIPE_CONF_CHECK_I(has_pch_encoder);
9879         PIPE_CONF_CHECK_I(fdi_lanes);
9880         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9881         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9882         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9883         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9884         PIPE_CONF_CHECK_I(fdi_m_n.tu);
9885
9886         PIPE_CONF_CHECK_I(has_dp_encoder);
9887         PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9888         PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9889         PIPE_CONF_CHECK_I(dp_m_n.link_m);
9890         PIPE_CONF_CHECK_I(dp_m_n.link_n);
9891         PIPE_CONF_CHECK_I(dp_m_n.tu);
9892
9893         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9894         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9895         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9896         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9897         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9898         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9899
9900         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9901         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9902         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9903         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9904         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9905         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9906
9907         PIPE_CONF_CHECK_I(pixel_multiplier);
9908         PIPE_CONF_CHECK_I(has_hdmi_sink);
9909         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
9910             IS_VALLEYVIEW(dev))
9911                 PIPE_CONF_CHECK_I(limited_color_range);
9912
9913         PIPE_CONF_CHECK_I(has_audio);
9914
9915         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9916                               DRM_MODE_FLAG_INTERLACE);
9917
9918         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9919                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9920                                       DRM_MODE_FLAG_PHSYNC);
9921                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9922                                       DRM_MODE_FLAG_NHSYNC);
9923                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9924                                       DRM_MODE_FLAG_PVSYNC);
9925                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9926                                       DRM_MODE_FLAG_NVSYNC);
9927         }
9928
9929         PIPE_CONF_CHECK_I(pipe_src_w);
9930         PIPE_CONF_CHECK_I(pipe_src_h);
9931
9932         /*
9933          * FIXME: BIOS likes to set up a cloned config with lvds+external
9934          * screen. Since we don't yet re-compute the pipe config when moving
9935          * just the lvds port away to another pipe the sw tracking won't match.
9936          *
9937          * Proper atomic modesets with recomputed global state will fix this.
9938          * Until then just don't check gmch state for inherited modes.
9939          */
9940         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
9941                 PIPE_CONF_CHECK_I(gmch_pfit.control);
9942                 /* pfit ratios are autocomputed by the hw on gen4+ */
9943                 if (INTEL_INFO(dev)->gen < 4)
9944                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9945                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9946         }
9947
9948         PIPE_CONF_CHECK_I(pch_pfit.enabled);
9949         if (current_config->pch_pfit.enabled) {
9950                 PIPE_CONF_CHECK_I(pch_pfit.pos);
9951                 PIPE_CONF_CHECK_I(pch_pfit.size);
9952         }
9953
9954         /* BDW+ don't expose a synchronous way to read the state */
9955         if (IS_HASWELL(dev))
9956                 PIPE_CONF_CHECK_I(ips_enabled);
9957
9958         PIPE_CONF_CHECK_I(double_wide);
9959
9960         PIPE_CONF_CHECK_I(shared_dpll);
9961         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
9962         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
9963         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
9964         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
9965
9966         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
9967                 PIPE_CONF_CHECK_I(pipe_bpp);
9968
9969         PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
9970         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
9971
9972 #undef PIPE_CONF_CHECK_X
9973 #undef PIPE_CONF_CHECK_I
9974 #undef PIPE_CONF_CHECK_FLAGS
9975 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
9976 #undef PIPE_CONF_QUIRK
9977
9978         return true;
9979 }
9980
9981 static void
9982 check_connector_state(struct drm_device *dev)
9983 {
9984         struct intel_connector *connector;
9985
9986         list_for_each_entry(connector, &dev->mode_config.connector_list,
9987                             base.head) {
9988                 /* This also checks the encoder/connector hw state with the
9989                  * ->get_hw_state callbacks. */
9990                 intel_connector_check_state(connector);
9991
9992                 WARN(&connector->new_encoder->base != connector->base.encoder,
9993                      "connector's staged encoder doesn't match current encoder\n");
9994         }
9995 }
9996
9997 static void
9998 check_encoder_state(struct drm_device *dev)
9999 {
10000         struct intel_encoder *encoder;
10001         struct intel_connector *connector;
10002
10003         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10004                             base.head) {
10005                 bool enabled = false;
10006                 bool active = false;
10007                 enum pipe pipe, tracked_pipe;
10008
10009                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10010                               encoder->base.base.id,
10011                               drm_get_encoder_name(&encoder->base));
10012
10013                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10014                      "encoder's stage crtc doesn't match current crtc\n");
10015                 WARN(encoder->connectors_active && !encoder->base.crtc,
10016                      "encoder's active_connectors set, but no crtc\n");
10017
10018                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10019                                     base.head) {
10020                         if (connector->base.encoder != &encoder->base)
10021                                 continue;
10022                         enabled = true;
10023                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10024                                 active = true;
10025                 }
10026                 WARN(!!encoder->base.crtc != enabled,
10027                      "encoder's enabled state mismatch "
10028                      "(expected %i, found %i)\n",
10029                      !!encoder->base.crtc, enabled);
10030                 WARN(active && !encoder->base.crtc,
10031                      "active encoder with no crtc\n");
10032
10033                 WARN(encoder->connectors_active != active,
10034                      "encoder's computed active state doesn't match tracked active state "
10035                      "(expected %i, found %i)\n", active, encoder->connectors_active);
10036
10037                 active = encoder->get_hw_state(encoder, &pipe);
10038                 WARN(active != encoder->connectors_active,
10039                      "encoder's hw state doesn't match sw tracking "
10040                      "(expected %i, found %i)\n",
10041                      encoder->connectors_active, active);
10042
10043                 if (!encoder->base.crtc)
10044                         continue;
10045
10046                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10047                 WARN(active && pipe != tracked_pipe,
10048                      "active encoder's pipe doesn't match"
10049                      "(expected %i, found %i)\n",
10050                      tracked_pipe, pipe);
10051
10052         }
10053 }
10054
10055 static void
10056 check_crtc_state(struct drm_device *dev)
10057 {
10058         struct drm_i915_private *dev_priv = dev->dev_private;
10059         struct intel_crtc *crtc;
10060         struct intel_encoder *encoder;
10061         struct intel_crtc_config pipe_config;
10062
10063         for_each_intel_crtc(dev, crtc) {
10064                 bool enabled = false;
10065                 bool active = false;
10066
10067                 memset(&pipe_config, 0, sizeof(pipe_config));
10068
10069                 DRM_DEBUG_KMS("[CRTC:%d]\n",
10070                               crtc->base.base.id);
10071
10072                 WARN(crtc->active && !crtc->base.enabled,
10073                      "active crtc, but not enabled in sw tracking\n");
10074
10075                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10076                                     base.head) {
10077                         if (encoder->base.crtc != &crtc->base)
10078                                 continue;
10079                         enabled = true;
10080                         if (encoder->connectors_active)
10081                                 active = true;
10082                 }
10083
10084                 WARN(active != crtc->active,
10085                      "crtc's computed active state doesn't match tracked active state "
10086                      "(expected %i, found %i)\n", active, crtc->active);
10087                 WARN(enabled != crtc->base.enabled,
10088                      "crtc's computed enabled state doesn't match tracked enabled state "
10089                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10090
10091                 active = dev_priv->display.get_pipe_config(crtc,
10092                                                            &pipe_config);
10093
10094                 /* hw state is inconsistent with the pipe A quirk */
10095                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
10096                         active = crtc->active;
10097
10098                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10099                                     base.head) {
10100                         enum pipe pipe;
10101                         if (encoder->base.crtc != &crtc->base)
10102                                 continue;
10103                         if (encoder->get_hw_state(encoder, &pipe))
10104                                 encoder->get_config(encoder, &pipe_config);
10105                 }
10106
10107                 WARN(crtc->active != active,
10108                      "crtc active state doesn't match with hw state "
10109                      "(expected %i, found %i)\n", crtc->active, active);
10110
10111                 if (active &&
10112                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10113                         WARN(1, "pipe state doesn't match!\n");
10114                         intel_dump_pipe_config(crtc, &pipe_config,
10115                                                "[hw state]");
10116                         intel_dump_pipe_config(crtc, &crtc->config,
10117                                                "[sw state]");
10118                 }
10119         }
10120 }
10121
10122 static void
10123 check_shared_dpll_state(struct drm_device *dev)
10124 {
10125         struct drm_i915_private *dev_priv = dev->dev_private;
10126         struct intel_crtc *crtc;
10127         struct intel_dpll_hw_state dpll_hw_state;
10128         int i;
10129
10130         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10131                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10132                 int enabled_crtcs = 0, active_crtcs = 0;
10133                 bool active;
10134
10135                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10136
10137                 DRM_DEBUG_KMS("%s\n", pll->name);
10138
10139                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10140
10141                 WARN(pll->active > pll->refcount,
10142                      "more active pll users than references: %i vs %i\n",
10143                      pll->active, pll->refcount);
10144                 WARN(pll->active && !pll->on,
10145                      "pll in active use but not on in sw tracking\n");
10146                 WARN(pll->on && !pll->active,
10147                      "pll in on but not on in use in sw tracking\n");
10148                 WARN(pll->on != active,
10149                      "pll on state mismatch (expected %i, found %i)\n",
10150                      pll->on, active);
10151
10152                 for_each_intel_crtc(dev, crtc) {
10153                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10154                                 enabled_crtcs++;
10155                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10156                                 active_crtcs++;
10157                 }
10158                 WARN(pll->active != active_crtcs,
10159                      "pll active crtcs mismatch (expected %i, found %i)\n",
10160                      pll->active, active_crtcs);
10161                 WARN(pll->refcount != enabled_crtcs,
10162                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
10163                      pll->refcount, enabled_crtcs);
10164
10165                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10166                                        sizeof(dpll_hw_state)),
10167                      "pll hw state mismatch\n");
10168         }
10169 }
10170
10171 void
10172 intel_modeset_check_state(struct drm_device *dev)
10173 {
10174         check_connector_state(dev);
10175         check_encoder_state(dev);
10176         check_crtc_state(dev);
10177         check_shared_dpll_state(dev);
10178 }
10179
10180 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10181                                      int dotclock)
10182 {
10183         /*
10184          * FDI already provided one idea for the dotclock.
10185          * Yell if the encoder disagrees.
10186          */
10187         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10188              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10189              pipe_config->adjusted_mode.crtc_clock, dotclock);
10190 }
10191
10192 static int __intel_set_mode(struct drm_crtc *crtc,
10193                             struct drm_display_mode *mode,
10194                             int x, int y, struct drm_framebuffer *fb)
10195 {
10196         struct drm_device *dev = crtc->dev;
10197         struct drm_i915_private *dev_priv = dev->dev_private;
10198         struct drm_display_mode *saved_mode;
10199         struct intel_crtc_config *pipe_config = NULL;
10200         struct intel_crtc *intel_crtc;
10201         unsigned disable_pipes, prepare_pipes, modeset_pipes;
10202         int ret = 0;
10203
10204         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10205         if (!saved_mode)
10206                 return -ENOMEM;
10207
10208         intel_modeset_affected_pipes(crtc, &modeset_pipes,
10209                                      &prepare_pipes, &disable_pipes);
10210
10211         *saved_mode = crtc->mode;
10212
10213         /* Hack: Because we don't (yet) support global modeset on multiple
10214          * crtcs, we don't keep track of the new mode for more than one crtc.
10215          * Hence simply check whether any bit is set in modeset_pipes in all the
10216          * pieces of code that are not yet converted to deal with mutliple crtcs
10217          * changing their mode at the same time. */
10218         if (modeset_pipes) {
10219                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10220                 if (IS_ERR(pipe_config)) {
10221                         ret = PTR_ERR(pipe_config);
10222                         pipe_config = NULL;
10223
10224                         goto out;
10225                 }
10226                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10227                                        "[modeset]");
10228                 to_intel_crtc(crtc)->new_config = pipe_config;
10229         }
10230
10231         /*
10232          * See if the config requires any additional preparation, e.g.
10233          * to adjust global state with pipes off.  We need to do this
10234          * here so we can get the modeset_pipe updated config for the new
10235          * mode set on this crtc.  For other crtcs we need to use the
10236          * adjusted_mode bits in the crtc directly.
10237          */
10238         if (IS_VALLEYVIEW(dev)) {
10239                 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10240
10241                 /* may have added more to prepare_pipes than we should */
10242                 prepare_pipes &= ~disable_pipes;
10243         }
10244
10245         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10246                 intel_crtc_disable(&intel_crtc->base);
10247
10248         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10249                 if (intel_crtc->base.enabled)
10250                         dev_priv->display.crtc_disable(&intel_crtc->base);
10251         }
10252
10253         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10254          * to set it here already despite that we pass it down the callchain.
10255          */
10256         if (modeset_pipes) {
10257                 crtc->mode = *mode;
10258                 /* mode_set/enable/disable functions rely on a correct pipe
10259                  * config. */
10260                 to_intel_crtc(crtc)->config = *pipe_config;
10261                 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10262
10263                 /*
10264                  * Calculate and store various constants which
10265                  * are later needed by vblank and swap-completion
10266                  * timestamping. They are derived from true hwmode.
10267                  */
10268                 drm_calc_timestamping_constants(crtc,
10269                                                 &pipe_config->adjusted_mode);
10270         }
10271
10272         /* Only after disabling all output pipelines that will be changed can we
10273          * update the the output configuration. */
10274         intel_modeset_update_state(dev, prepare_pipes);
10275
10276         if (dev_priv->display.modeset_global_resources)
10277                 dev_priv->display.modeset_global_resources(dev);
10278
10279         /* Set up the DPLL and any encoders state that needs to adjust or depend
10280          * on the DPLL.
10281          */
10282         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10283                 ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
10284                                                       x, y, fb);
10285                 if (ret)
10286                         goto done;
10287         }
10288
10289         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10290         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
10291                 dev_priv->display.crtc_enable(&intel_crtc->base);
10292
10293         /* FIXME: add subpixel order */
10294 done:
10295         if (ret && crtc->enabled)
10296                 crtc->mode = *saved_mode;
10297
10298 out:
10299         kfree(pipe_config);
10300         kfree(saved_mode);
10301         return ret;
10302 }
10303
10304 static int intel_set_mode(struct drm_crtc *crtc,
10305                           struct drm_display_mode *mode,
10306                           int x, int y, struct drm_framebuffer *fb)
10307 {
10308         int ret;
10309
10310         ret = __intel_set_mode(crtc, mode, x, y, fb);
10311
10312         if (ret == 0)
10313                 intel_modeset_check_state(crtc->dev);
10314
10315         return ret;
10316 }
10317
10318 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10319 {
10320         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10321 }
10322
10323 #undef for_each_intel_crtc_masked
10324
10325 static void intel_set_config_free(struct intel_set_config *config)
10326 {
10327         if (!config)
10328                 return;
10329
10330         kfree(config->save_connector_encoders);
10331         kfree(config->save_encoder_crtcs);
10332         kfree(config->save_crtc_enabled);
10333         kfree(config);
10334 }
10335
10336 static int intel_set_config_save_state(struct drm_device *dev,
10337                                        struct intel_set_config *config)
10338 {
10339         struct drm_crtc *crtc;
10340         struct drm_encoder *encoder;
10341         struct drm_connector *connector;
10342         int count;
10343
10344         config->save_crtc_enabled =
10345                 kcalloc(dev->mode_config.num_crtc,
10346                         sizeof(bool), GFP_KERNEL);
10347         if (!config->save_crtc_enabled)
10348                 return -ENOMEM;
10349
10350         config->save_encoder_crtcs =
10351                 kcalloc(dev->mode_config.num_encoder,
10352                         sizeof(struct drm_crtc *), GFP_KERNEL);
10353         if (!config->save_encoder_crtcs)
10354                 return -ENOMEM;
10355
10356         config->save_connector_encoders =
10357                 kcalloc(dev->mode_config.num_connector,
10358                         sizeof(struct drm_encoder *), GFP_KERNEL);
10359         if (!config->save_connector_encoders)
10360                 return -ENOMEM;
10361
10362         /* Copy data. Note that driver private data is not affected.
10363          * Should anything bad happen only the expected state is
10364          * restored, not the drivers personal bookkeeping.
10365          */
10366         count = 0;
10367         for_each_crtc(dev, crtc) {
10368                 config->save_crtc_enabled[count++] = crtc->enabled;
10369         }
10370
10371         count = 0;
10372         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10373                 config->save_encoder_crtcs[count++] = encoder->crtc;
10374         }
10375
10376         count = 0;
10377         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10378                 config->save_connector_encoders[count++] = connector->encoder;
10379         }
10380
10381         return 0;
10382 }
10383
10384 static void intel_set_config_restore_state(struct drm_device *dev,
10385                                            struct intel_set_config *config)
10386 {
10387         struct intel_crtc *crtc;
10388         struct intel_encoder *encoder;
10389         struct intel_connector *connector;
10390         int count;
10391
10392         count = 0;
10393         for_each_intel_crtc(dev, crtc) {
10394                 crtc->new_enabled = config->save_crtc_enabled[count++];
10395
10396                 if (crtc->new_enabled)
10397                         crtc->new_config = &crtc->config;
10398                 else
10399                         crtc->new_config = NULL;
10400         }
10401
10402         count = 0;
10403         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10404                 encoder->new_crtc =
10405                         to_intel_crtc(config->save_encoder_crtcs[count++]);
10406         }
10407
10408         count = 0;
10409         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10410                 connector->new_encoder =
10411                         to_intel_encoder(config->save_connector_encoders[count++]);
10412         }
10413 }
10414
10415 static bool
10416 is_crtc_connector_off(struct drm_mode_set *set)
10417 {
10418         int i;
10419
10420         if (set->num_connectors == 0)
10421                 return false;
10422
10423         if (WARN_ON(set->connectors == NULL))
10424                 return false;
10425
10426         for (i = 0; i < set->num_connectors; i++)
10427                 if (set->connectors[i]->encoder &&
10428                     set->connectors[i]->encoder->crtc == set->crtc &&
10429                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
10430                         return true;
10431
10432         return false;
10433 }
10434
10435 static void
10436 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
10437                                       struct intel_set_config *config)
10438 {
10439
10440         /* We should be able to check here if the fb has the same properties
10441          * and then just flip_or_move it */
10442         if (is_crtc_connector_off(set)) {
10443                 config->mode_changed = true;
10444         } else if (set->crtc->primary->fb != set->fb) {
10445                 /* If we have no fb then treat it as a full mode set */
10446                 if (set->crtc->primary->fb == NULL) {
10447                         struct intel_crtc *intel_crtc =
10448                                 to_intel_crtc(set->crtc);
10449
10450                         if (intel_crtc->active && i915.fastboot) {
10451                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
10452                                 config->fb_changed = true;
10453                         } else {
10454                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
10455                                 config->mode_changed = true;
10456                         }
10457                 } else if (set->fb == NULL) {
10458                         config->mode_changed = true;
10459                 } else if (set->fb->pixel_format !=
10460                            set->crtc->primary->fb->pixel_format) {
10461                         config->mode_changed = true;
10462                 } else {
10463                         config->fb_changed = true;
10464                 }
10465         }
10466
10467         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
10468                 config->fb_changed = true;
10469
10470         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
10471                 DRM_DEBUG_KMS("modes are different, full mode set\n");
10472                 drm_mode_debug_printmodeline(&set->crtc->mode);
10473                 drm_mode_debug_printmodeline(set->mode);
10474                 config->mode_changed = true;
10475         }
10476
10477         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
10478                         set->crtc->base.id, config->mode_changed, config->fb_changed);
10479 }
10480
10481 static int
10482 intel_modeset_stage_output_state(struct drm_device *dev,
10483                                  struct drm_mode_set *set,
10484                                  struct intel_set_config *config)
10485 {
10486         struct intel_connector *connector;
10487         struct intel_encoder *encoder;
10488         struct intel_crtc *crtc;
10489         int ro;
10490
10491         /* The upper layers ensure that we either disable a crtc or have a list
10492          * of connectors. For paranoia, double-check this. */
10493         WARN_ON(!set->fb && (set->num_connectors != 0));
10494         WARN_ON(set->fb && (set->num_connectors == 0));
10495
10496         list_for_each_entry(connector, &dev->mode_config.connector_list,
10497                             base.head) {
10498                 /* Otherwise traverse passed in connector list and get encoders
10499                  * for them. */
10500                 for (ro = 0; ro < set->num_connectors; ro++) {
10501                         if (set->connectors[ro] == &connector->base) {
10502                                 connector->new_encoder = connector->encoder;
10503                                 break;
10504                         }
10505                 }
10506
10507                 /* If we disable the crtc, disable all its connectors. Also, if
10508                  * the connector is on the changing crtc but not on the new
10509                  * connector list, disable it. */
10510                 if ((!set->fb || ro == set->num_connectors) &&
10511                     connector->base.encoder &&
10512                     connector->base.encoder->crtc == set->crtc) {
10513                         connector->new_encoder = NULL;
10514
10515                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
10516                                 connector->base.base.id,
10517                                 drm_get_connector_name(&connector->base));
10518                 }
10519
10520
10521                 if (&connector->new_encoder->base != connector->base.encoder) {
10522                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
10523                         config->mode_changed = true;
10524                 }
10525         }
10526         /* connector->new_encoder is now updated for all connectors. */
10527
10528         /* Update crtc of enabled connectors. */
10529         list_for_each_entry(connector, &dev->mode_config.connector_list,
10530                             base.head) {
10531                 struct drm_crtc *new_crtc;
10532
10533                 if (!connector->new_encoder)
10534                         continue;
10535
10536                 new_crtc = connector->new_encoder->base.crtc;
10537
10538                 for (ro = 0; ro < set->num_connectors; ro++) {
10539                         if (set->connectors[ro] == &connector->base)
10540                                 new_crtc = set->crtc;
10541                 }
10542
10543                 /* Make sure the new CRTC will work with the encoder */
10544                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
10545                                          new_crtc)) {
10546                         return -EINVAL;
10547                 }
10548                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
10549
10550                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
10551                         connector->base.base.id,
10552                         drm_get_connector_name(&connector->base),
10553                         new_crtc->base.id);
10554         }
10555
10556         /* Check for any encoders that needs to be disabled. */
10557         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10558                             base.head) {
10559                 int num_connectors = 0;
10560                 list_for_each_entry(connector,
10561                                     &dev->mode_config.connector_list,
10562                                     base.head) {
10563                         if (connector->new_encoder == encoder) {
10564                                 WARN_ON(!connector->new_encoder->new_crtc);
10565                                 num_connectors++;
10566                         }
10567                 }
10568
10569                 if (num_connectors == 0)
10570                         encoder->new_crtc = NULL;
10571                 else if (num_connectors > 1)
10572                         return -EINVAL;
10573
10574                 /* Only now check for crtc changes so we don't miss encoders
10575                  * that will be disabled. */
10576                 if (&encoder->new_crtc->base != encoder->base.crtc) {
10577                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
10578                         config->mode_changed = true;
10579                 }
10580         }
10581         /* Now we've also updated encoder->new_crtc for all encoders. */
10582
10583         for_each_intel_crtc(dev, crtc) {
10584                 crtc->new_enabled = false;
10585
10586                 list_for_each_entry(encoder,
10587                                     &dev->mode_config.encoder_list,
10588                                     base.head) {
10589                         if (encoder->new_crtc == crtc) {
10590                                 crtc->new_enabled = true;
10591                                 break;
10592                         }
10593                 }
10594
10595                 if (crtc->new_enabled != crtc->base.enabled) {
10596                         DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
10597                                       crtc->new_enabled ? "en" : "dis");
10598                         config->mode_changed = true;
10599                 }
10600
10601                 if (crtc->new_enabled)
10602                         crtc->new_config = &crtc->config;
10603                 else
10604                         crtc->new_config = NULL;
10605         }
10606
10607         return 0;
10608 }
10609
10610 static void disable_crtc_nofb(struct intel_crtc *crtc)
10611 {
10612         struct drm_device *dev = crtc->base.dev;
10613         struct intel_encoder *encoder;
10614         struct intel_connector *connector;
10615
10616         DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
10617                       pipe_name(crtc->pipe));
10618
10619         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10620                 if (connector->new_encoder &&
10621                     connector->new_encoder->new_crtc == crtc)
10622                         connector->new_encoder = NULL;
10623         }
10624
10625         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10626                 if (encoder->new_crtc == crtc)
10627                         encoder->new_crtc = NULL;
10628         }
10629
10630         crtc->new_enabled = false;
10631         crtc->new_config = NULL;
10632 }
10633
10634 static int intel_crtc_set_config(struct drm_mode_set *set)
10635 {
10636         struct drm_device *dev;
10637         struct drm_mode_set save_set;
10638         struct intel_set_config *config;
10639         int ret;
10640
10641         BUG_ON(!set);
10642         BUG_ON(!set->crtc);
10643         BUG_ON(!set->crtc->helper_private);
10644
10645         /* Enforce sane interface api - has been abused by the fb helper. */
10646         BUG_ON(!set->mode && set->fb);
10647         BUG_ON(set->fb && set->num_connectors == 0);
10648
10649         if (set->fb) {
10650                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
10651                                 set->crtc->base.id, set->fb->base.id,
10652                                 (int)set->num_connectors, set->x, set->y);
10653         } else {
10654                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
10655         }
10656
10657         dev = set->crtc->dev;
10658
10659         ret = -ENOMEM;
10660         config = kzalloc(sizeof(*config), GFP_KERNEL);
10661         if (!config)
10662                 goto out_config;
10663
10664         ret = intel_set_config_save_state(dev, config);
10665         if (ret)
10666                 goto out_config;
10667
10668         save_set.crtc = set->crtc;
10669         save_set.mode = &set->crtc->mode;
10670         save_set.x = set->crtc->x;
10671         save_set.y = set->crtc->y;
10672         save_set.fb = set->crtc->primary->fb;
10673
10674         /* Compute whether we need a full modeset, only an fb base update or no
10675          * change at all. In the future we might also check whether only the
10676          * mode changed, e.g. for LVDS where we only change the panel fitter in
10677          * such cases. */
10678         intel_set_config_compute_mode_changes(set, config);
10679
10680         ret = intel_modeset_stage_output_state(dev, set, config);
10681         if (ret)
10682                 goto fail;
10683
10684         if (config->mode_changed) {
10685                 ret = intel_set_mode(set->crtc, set->mode,
10686                                      set->x, set->y, set->fb);
10687         } else if (config->fb_changed) {
10688                 intel_crtc_wait_for_pending_flips(set->crtc);
10689
10690                 ret = intel_pipe_set_base(set->crtc,
10691                                           set->x, set->y, set->fb);
10692                 /*
10693                  * In the fastboot case this may be our only check of the
10694                  * state after boot.  It would be better to only do it on
10695                  * the first update, but we don't have a nice way of doing that
10696                  * (and really, set_config isn't used much for high freq page
10697                  * flipping, so increasing its cost here shouldn't be a big
10698                  * deal).
10699                  */
10700                 if (i915.fastboot && ret == 0)
10701                         intel_modeset_check_state(set->crtc->dev);
10702         }
10703
10704         if (ret) {
10705                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
10706                               set->crtc->base.id, ret);
10707 fail:
10708                 intel_set_config_restore_state(dev, config);
10709
10710                 /*
10711                  * HACK: if the pipe was on, but we didn't have a framebuffer,
10712                  * force the pipe off to avoid oopsing in the modeset code
10713                  * due to fb==NULL. This should only happen during boot since
10714                  * we don't yet reconstruct the FB from the hardware state.
10715                  */
10716                 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
10717                         disable_crtc_nofb(to_intel_crtc(save_set.crtc));
10718
10719                 /* Try to restore the config */
10720                 if (config->mode_changed &&
10721                     intel_set_mode(save_set.crtc, save_set.mode,
10722                                    save_set.x, save_set.y, save_set.fb))
10723                         DRM_ERROR("failed to restore config after modeset failure\n");
10724         }
10725
10726 out_config:
10727         intel_set_config_free(config);
10728         return ret;
10729 }
10730
10731 static const struct drm_crtc_funcs intel_crtc_funcs = {
10732         .cursor_set = intel_crtc_cursor_set,
10733         .cursor_move = intel_crtc_cursor_move,
10734         .gamma_set = intel_crtc_gamma_set,
10735         .set_config = intel_crtc_set_config,
10736         .destroy = intel_crtc_destroy,
10737         .page_flip = intel_crtc_page_flip,
10738 };
10739
10740 static void intel_cpu_pll_init(struct drm_device *dev)
10741 {
10742         if (HAS_DDI(dev))
10743                 intel_ddi_pll_init(dev);
10744 }
10745
10746 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
10747                                       struct intel_shared_dpll *pll,
10748                                       struct intel_dpll_hw_state *hw_state)
10749 {
10750         uint32_t val;
10751
10752         val = I915_READ(PCH_DPLL(pll->id));
10753         hw_state->dpll = val;
10754         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
10755         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
10756
10757         return val & DPLL_VCO_ENABLE;
10758 }
10759
10760 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
10761                                   struct intel_shared_dpll *pll)
10762 {
10763         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
10764         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
10765 }
10766
10767 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
10768                                 struct intel_shared_dpll *pll)
10769 {
10770         /* PCH refclock must be enabled first */
10771         ibx_assert_pch_refclk_enabled(dev_priv);
10772
10773         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10774
10775         /* Wait for the clocks to stabilize. */
10776         POSTING_READ(PCH_DPLL(pll->id));
10777         udelay(150);
10778
10779         /* The pixel multiplier can only be updated once the
10780          * DPLL is enabled and the clocks are stable.
10781          *
10782          * So write it again.
10783          */
10784         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10785         POSTING_READ(PCH_DPLL(pll->id));
10786         udelay(200);
10787 }
10788
10789 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
10790                                  struct intel_shared_dpll *pll)
10791 {
10792         struct drm_device *dev = dev_priv->dev;
10793         struct intel_crtc *crtc;
10794
10795         /* Make sure no transcoder isn't still depending on us. */
10796         for_each_intel_crtc(dev, crtc) {
10797                 if (intel_crtc_to_shared_dpll(crtc) == pll)
10798                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
10799         }
10800
10801         I915_WRITE(PCH_DPLL(pll->id), 0);
10802         POSTING_READ(PCH_DPLL(pll->id));
10803         udelay(200);
10804 }
10805
10806 static char *ibx_pch_dpll_names[] = {
10807         "PCH DPLL A",
10808         "PCH DPLL B",
10809 };
10810
10811 static void ibx_pch_dpll_init(struct drm_device *dev)
10812 {
10813         struct drm_i915_private *dev_priv = dev->dev_private;
10814         int i;
10815
10816         dev_priv->num_shared_dpll = 2;
10817
10818         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10819                 dev_priv->shared_dplls[i].id = i;
10820                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
10821                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
10822                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
10823                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
10824                 dev_priv->shared_dplls[i].get_hw_state =
10825                         ibx_pch_dpll_get_hw_state;
10826         }
10827 }
10828
10829 static void intel_shared_dpll_init(struct drm_device *dev)
10830 {
10831         struct drm_i915_private *dev_priv = dev->dev_private;
10832
10833         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
10834                 ibx_pch_dpll_init(dev);
10835         else
10836                 dev_priv->num_shared_dpll = 0;
10837
10838         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
10839 }
10840
10841 static void intel_crtc_init(struct drm_device *dev, int pipe)
10842 {
10843         struct drm_i915_private *dev_priv = dev->dev_private;
10844         struct intel_crtc *intel_crtc;
10845         int i;
10846
10847         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
10848         if (intel_crtc == NULL)
10849                 return;
10850
10851         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
10852
10853         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
10854         for (i = 0; i < 256; i++) {
10855                 intel_crtc->lut_r[i] = i;
10856                 intel_crtc->lut_g[i] = i;
10857                 intel_crtc->lut_b[i] = i;
10858         }
10859
10860         /*
10861          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
10862          * is hooked to plane B. Hence we want plane A feeding pipe B.
10863          */
10864         intel_crtc->pipe = pipe;
10865         intel_crtc->plane = pipe;
10866         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
10867                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
10868                 intel_crtc->plane = !pipe;
10869         }
10870
10871         init_waitqueue_head(&intel_crtc->vbl_wait);
10872
10873         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
10874                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
10875         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
10876         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
10877
10878         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
10879 }
10880
10881 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
10882 {
10883         struct drm_encoder *encoder = connector->base.encoder;
10884
10885         WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex));
10886
10887         if (!encoder)
10888                 return INVALID_PIPE;
10889
10890         return to_intel_crtc(encoder->crtc)->pipe;
10891 }
10892
10893 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
10894                                 struct drm_file *file)
10895 {
10896         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
10897         struct drm_mode_object *drmmode_obj;
10898         struct intel_crtc *crtc;
10899
10900         if (!drm_core_check_feature(dev, DRIVER_MODESET))
10901                 return -ENODEV;
10902
10903         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
10904                         DRM_MODE_OBJECT_CRTC);
10905
10906         if (!drmmode_obj) {
10907                 DRM_ERROR("no such CRTC id\n");
10908                 return -ENOENT;
10909         }
10910
10911         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
10912         pipe_from_crtc_id->pipe = crtc->pipe;
10913
10914         return 0;
10915 }
10916
10917 static int intel_encoder_clones(struct intel_encoder *encoder)
10918 {
10919         struct drm_device *dev = encoder->base.dev;
10920         struct intel_encoder *source_encoder;
10921         int index_mask = 0;
10922         int entry = 0;
10923
10924         list_for_each_entry(source_encoder,
10925                             &dev->mode_config.encoder_list, base.head) {
10926                 if (encoders_cloneable(encoder, source_encoder))
10927                         index_mask |= (1 << entry);
10928
10929                 entry++;
10930         }
10931
10932         return index_mask;
10933 }
10934
10935 static bool has_edp_a(struct drm_device *dev)
10936 {
10937         struct drm_i915_private *dev_priv = dev->dev_private;
10938
10939         if (!IS_MOBILE(dev))
10940                 return false;
10941
10942         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
10943                 return false;
10944
10945         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
10946                 return false;
10947
10948         return true;
10949 }
10950
10951 const char *intel_output_name(int output)
10952 {
10953         static const char *names[] = {
10954                 [INTEL_OUTPUT_UNUSED] = "Unused",
10955                 [INTEL_OUTPUT_ANALOG] = "Analog",
10956                 [INTEL_OUTPUT_DVO] = "DVO",
10957                 [INTEL_OUTPUT_SDVO] = "SDVO",
10958                 [INTEL_OUTPUT_LVDS] = "LVDS",
10959                 [INTEL_OUTPUT_TVOUT] = "TV",
10960                 [INTEL_OUTPUT_HDMI] = "HDMI",
10961                 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
10962                 [INTEL_OUTPUT_EDP] = "eDP",
10963                 [INTEL_OUTPUT_DSI] = "DSI",
10964                 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
10965         };
10966
10967         if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
10968                 return "Invalid";
10969
10970         return names[output];
10971 }
10972
10973 static void intel_setup_outputs(struct drm_device *dev)
10974 {
10975         struct drm_i915_private *dev_priv = dev->dev_private;
10976         struct intel_encoder *encoder;
10977         bool dpd_is_edp = false;
10978
10979         intel_lvds_init(dev);
10980
10981         if (!IS_ULT(dev) && !IS_CHERRYVIEW(dev))
10982                 intel_crt_init(dev);
10983
10984         if (HAS_DDI(dev)) {
10985                 int found;
10986
10987                 /* Haswell uses DDI functions to detect digital outputs */
10988                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
10989                 /* DDI A only supports eDP */
10990                 if (found)
10991                         intel_ddi_init(dev, PORT_A);
10992
10993                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
10994                  * register */
10995                 found = I915_READ(SFUSE_STRAP);
10996
10997                 if (found & SFUSE_STRAP_DDIB_DETECTED)
10998                         intel_ddi_init(dev, PORT_B);
10999                 if (found & SFUSE_STRAP_DDIC_DETECTED)
11000                         intel_ddi_init(dev, PORT_C);
11001                 if (found & SFUSE_STRAP_DDID_DETECTED)
11002                         intel_ddi_init(dev, PORT_D);
11003         } else if (HAS_PCH_SPLIT(dev)) {
11004                 int found;
11005                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
11006
11007                 if (has_edp_a(dev))
11008                         intel_dp_init(dev, DP_A, PORT_A);
11009
11010                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
11011                         /* PCH SDVOB multiplex with HDMIB */
11012                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
11013                         if (!found)
11014                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
11015                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
11016                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
11017                 }
11018
11019                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
11020                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
11021
11022                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
11023                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
11024
11025                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
11026                         intel_dp_init(dev, PCH_DP_C, PORT_C);
11027
11028                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
11029                         intel_dp_init(dev, PCH_DP_D, PORT_D);
11030         } else if (IS_VALLEYVIEW(dev)) {
11031                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
11032                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
11033                                         PORT_B);
11034                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
11035                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
11036                 }
11037
11038                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
11039                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
11040                                         PORT_C);
11041                         if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
11042                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
11043                 }
11044
11045                 intel_dsi_init(dev);
11046         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
11047                 bool found = false;
11048
11049                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
11050                         DRM_DEBUG_KMS("probing SDVOB\n");
11051                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
11052                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
11053                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
11054                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
11055                         }
11056
11057                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
11058                                 intel_dp_init(dev, DP_B, PORT_B);
11059                 }
11060
11061                 /* Before G4X SDVOC doesn't have its own detect register */
11062
11063                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
11064                         DRM_DEBUG_KMS("probing SDVOC\n");
11065                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
11066                 }
11067
11068                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
11069
11070                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
11071                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
11072                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
11073                         }
11074                         if (SUPPORTS_INTEGRATED_DP(dev))
11075                                 intel_dp_init(dev, DP_C, PORT_C);
11076                 }
11077
11078                 if (SUPPORTS_INTEGRATED_DP(dev) &&
11079                     (I915_READ(DP_D) & DP_DETECTED))
11080                         intel_dp_init(dev, DP_D, PORT_D);
11081         } else if (IS_GEN2(dev))
11082                 intel_dvo_init(dev);
11083
11084         if (SUPPORTS_TV(dev))
11085                 intel_tv_init(dev);
11086
11087         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
11088                 encoder->base.possible_crtcs = encoder->crtc_mask;
11089                 encoder->base.possible_clones =
11090                         intel_encoder_clones(encoder);
11091         }
11092
11093         intel_init_pch_refclk(dev);
11094
11095         drm_helper_move_panel_connectors_to_head(dev);
11096 }
11097
11098 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
11099 {
11100         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11101
11102         drm_framebuffer_cleanup(fb);
11103         WARN_ON(!intel_fb->obj->framebuffer_references--);
11104         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
11105         kfree(intel_fb);
11106 }
11107
11108 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
11109                                                 struct drm_file *file,
11110                                                 unsigned int *handle)
11111 {
11112         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11113         struct drm_i915_gem_object *obj = intel_fb->obj;
11114
11115         return drm_gem_handle_create(file, &obj->base, handle);
11116 }
11117
11118 static const struct drm_framebuffer_funcs intel_fb_funcs = {
11119         .destroy = intel_user_framebuffer_destroy,
11120         .create_handle = intel_user_framebuffer_create_handle,
11121 };
11122
11123 static int intel_framebuffer_init(struct drm_device *dev,
11124                                   struct intel_framebuffer *intel_fb,
11125                                   struct drm_mode_fb_cmd2 *mode_cmd,
11126                                   struct drm_i915_gem_object *obj)
11127 {
11128         int aligned_height;
11129         int pitch_limit;
11130         int ret;
11131
11132         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
11133
11134         if (obj->tiling_mode == I915_TILING_Y) {
11135                 DRM_DEBUG("hardware does not support tiling Y\n");
11136                 return -EINVAL;
11137         }
11138
11139         if (mode_cmd->pitches[0] & 63) {
11140                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
11141                           mode_cmd->pitches[0]);
11142                 return -EINVAL;
11143         }
11144
11145         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
11146                 pitch_limit = 32*1024;
11147         } else if (INTEL_INFO(dev)->gen >= 4) {
11148                 if (obj->tiling_mode)
11149                         pitch_limit = 16*1024;
11150                 else
11151                         pitch_limit = 32*1024;
11152         } else if (INTEL_INFO(dev)->gen >= 3) {
11153                 if (obj->tiling_mode)
11154                         pitch_limit = 8*1024;
11155                 else
11156                         pitch_limit = 16*1024;
11157         } else
11158                 /* XXX DSPC is limited to 4k tiled */
11159                 pitch_limit = 8*1024;
11160
11161         if (mode_cmd->pitches[0] > pitch_limit) {
11162                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
11163                           obj->tiling_mode ? "tiled" : "linear",
11164                           mode_cmd->pitches[0], pitch_limit);
11165                 return -EINVAL;
11166         }
11167
11168         if (obj->tiling_mode != I915_TILING_NONE &&
11169             mode_cmd->pitches[0] != obj->stride) {
11170                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
11171                           mode_cmd->pitches[0], obj->stride);
11172                 return -EINVAL;
11173         }
11174
11175         /* Reject formats not supported by any plane early. */
11176         switch (mode_cmd->pixel_format) {
11177         case DRM_FORMAT_C8:
11178         case DRM_FORMAT_RGB565:
11179         case DRM_FORMAT_XRGB8888:
11180         case DRM_FORMAT_ARGB8888:
11181                 break;
11182         case DRM_FORMAT_XRGB1555:
11183         case DRM_FORMAT_ARGB1555:
11184                 if (INTEL_INFO(dev)->gen > 3) {
11185                         DRM_DEBUG("unsupported pixel format: %s\n",
11186                                   drm_get_format_name(mode_cmd->pixel_format));
11187                         return -EINVAL;
11188                 }
11189                 break;
11190         case DRM_FORMAT_XBGR8888:
11191         case DRM_FORMAT_ABGR8888:
11192         case DRM_FORMAT_XRGB2101010:
11193         case DRM_FORMAT_ARGB2101010:
11194         case DRM_FORMAT_XBGR2101010:
11195         case DRM_FORMAT_ABGR2101010:
11196                 if (INTEL_INFO(dev)->gen < 4) {
11197                         DRM_DEBUG("unsupported pixel format: %s\n",
11198                                   drm_get_format_name(mode_cmd->pixel_format));
11199                         return -EINVAL;
11200                 }
11201                 break;
11202         case DRM_FORMAT_YUYV:
11203         case DRM_FORMAT_UYVY:
11204         case DRM_FORMAT_YVYU:
11205         case DRM_FORMAT_VYUY:
11206                 if (INTEL_INFO(dev)->gen < 5) {
11207                         DRM_DEBUG("unsupported pixel format: %s\n",
11208                                   drm_get_format_name(mode_cmd->pixel_format));
11209                         return -EINVAL;
11210                 }
11211                 break;
11212         default:
11213                 DRM_DEBUG("unsupported pixel format: %s\n",
11214                           drm_get_format_name(mode_cmd->pixel_format));
11215                 return -EINVAL;
11216         }
11217
11218         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
11219         if (mode_cmd->offsets[0] != 0)
11220                 return -EINVAL;
11221
11222         aligned_height = intel_align_height(dev, mode_cmd->height,
11223                                             obj->tiling_mode);
11224         /* FIXME drm helper for size checks (especially planar formats)? */
11225         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
11226                 return -EINVAL;
11227
11228         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
11229         intel_fb->obj = obj;
11230         intel_fb->obj->framebuffer_references++;
11231
11232         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
11233         if (ret) {
11234                 DRM_ERROR("framebuffer init failed %d\n", ret);
11235                 return ret;
11236         }
11237
11238         return 0;
11239 }
11240
11241 static struct drm_framebuffer *
11242 intel_user_framebuffer_create(struct drm_device *dev,
11243                               struct drm_file *filp,
11244                               struct drm_mode_fb_cmd2 *mode_cmd)
11245 {
11246         struct drm_i915_gem_object *obj;
11247
11248         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
11249                                                 mode_cmd->handles[0]));
11250         if (&obj->base == NULL)
11251                 return ERR_PTR(-ENOENT);
11252
11253         return intel_framebuffer_create(dev, mode_cmd, obj);
11254 }
11255
11256 #ifndef CONFIG_DRM_I915_FBDEV
11257 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
11258 {
11259 }
11260 #endif
11261
11262 static const struct drm_mode_config_funcs intel_mode_funcs = {
11263         .fb_create = intel_user_framebuffer_create,
11264         .output_poll_changed = intel_fbdev_output_poll_changed,
11265 };
11266
11267 /* Set up chip specific display functions */
11268 static void intel_init_display(struct drm_device *dev)
11269 {
11270         struct drm_i915_private *dev_priv = dev->dev_private;
11271
11272         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
11273                 dev_priv->display.find_dpll = g4x_find_best_dpll;
11274         else if (IS_CHERRYVIEW(dev))
11275                 dev_priv->display.find_dpll = chv_find_best_dpll;
11276         else if (IS_VALLEYVIEW(dev))
11277                 dev_priv->display.find_dpll = vlv_find_best_dpll;
11278         else if (IS_PINEVIEW(dev))
11279                 dev_priv->display.find_dpll = pnv_find_best_dpll;
11280         else
11281                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
11282
11283         if (HAS_DDI(dev)) {
11284                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
11285                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
11286                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
11287                 dev_priv->display.crtc_enable = haswell_crtc_enable;
11288                 dev_priv->display.crtc_disable = haswell_crtc_disable;
11289                 dev_priv->display.off = haswell_crtc_off;
11290                 dev_priv->display.update_primary_plane =
11291                         ironlake_update_primary_plane;
11292         } else if (HAS_PCH_SPLIT(dev)) {
11293                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
11294                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
11295                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
11296                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
11297                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
11298                 dev_priv->display.off = ironlake_crtc_off;
11299                 dev_priv->display.update_primary_plane =
11300                         ironlake_update_primary_plane;
11301         } else if (IS_VALLEYVIEW(dev)) {
11302                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11303                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11304                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11305                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
11306                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11307                 dev_priv->display.off = i9xx_crtc_off;
11308                 dev_priv->display.update_primary_plane =
11309                         i9xx_update_primary_plane;
11310         } else {
11311                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11312                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11313                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11314                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
11315                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11316                 dev_priv->display.off = i9xx_crtc_off;
11317                 dev_priv->display.update_primary_plane =
11318                         i9xx_update_primary_plane;
11319         }
11320
11321         /* Returns the core display clock speed */
11322         if (IS_VALLEYVIEW(dev))
11323                 dev_priv->display.get_display_clock_speed =
11324                         valleyview_get_display_clock_speed;
11325         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
11326                 dev_priv->display.get_display_clock_speed =
11327                         i945_get_display_clock_speed;
11328         else if (IS_I915G(dev))
11329                 dev_priv->display.get_display_clock_speed =
11330                         i915_get_display_clock_speed;
11331         else if (IS_I945GM(dev) || IS_845G(dev))
11332                 dev_priv->display.get_display_clock_speed =
11333                         i9xx_misc_get_display_clock_speed;
11334         else if (IS_PINEVIEW(dev))
11335                 dev_priv->display.get_display_clock_speed =
11336                         pnv_get_display_clock_speed;
11337         else if (IS_I915GM(dev))
11338                 dev_priv->display.get_display_clock_speed =
11339                         i915gm_get_display_clock_speed;
11340         else if (IS_I865G(dev))
11341                 dev_priv->display.get_display_clock_speed =
11342                         i865_get_display_clock_speed;
11343         else if (IS_I85X(dev))
11344                 dev_priv->display.get_display_clock_speed =
11345                         i855_get_display_clock_speed;
11346         else /* 852, 830 */
11347                 dev_priv->display.get_display_clock_speed =
11348                         i830_get_display_clock_speed;
11349
11350         if (HAS_PCH_SPLIT(dev)) {
11351                 if (IS_GEN5(dev)) {
11352                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
11353                         dev_priv->display.write_eld = ironlake_write_eld;
11354                 } else if (IS_GEN6(dev)) {
11355                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
11356                         dev_priv->display.write_eld = ironlake_write_eld;
11357                         dev_priv->display.modeset_global_resources =
11358                                 snb_modeset_global_resources;
11359                 } else if (IS_IVYBRIDGE(dev)) {
11360                         /* FIXME: detect B0+ stepping and use auto training */
11361                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
11362                         dev_priv->display.write_eld = ironlake_write_eld;
11363                         dev_priv->display.modeset_global_resources =
11364                                 ivb_modeset_global_resources;
11365                 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
11366                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
11367                         dev_priv->display.write_eld = haswell_write_eld;
11368                         dev_priv->display.modeset_global_resources =
11369                                 haswell_modeset_global_resources;
11370                 }
11371         } else if (IS_G4X(dev)) {
11372                 dev_priv->display.write_eld = g4x_write_eld;
11373         } else if (IS_VALLEYVIEW(dev)) {
11374                 dev_priv->display.modeset_global_resources =
11375                         valleyview_modeset_global_resources;
11376                 dev_priv->display.write_eld = ironlake_write_eld;
11377         }
11378
11379         /* Default just returns -ENODEV to indicate unsupported */
11380         dev_priv->display.queue_flip = intel_default_queue_flip;
11381
11382         switch (INTEL_INFO(dev)->gen) {
11383         case 2:
11384                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
11385                 break;
11386
11387         case 3:
11388                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
11389                 break;
11390
11391         case 4:
11392         case 5:
11393                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
11394                 break;
11395
11396         case 6:
11397                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
11398                 break;
11399         case 7:
11400         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
11401                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
11402                 break;
11403         }
11404
11405         intel_panel_init_backlight_funcs(dev);
11406 }
11407
11408 /*
11409  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
11410  * resume, or other times.  This quirk makes sure that's the case for
11411  * affected systems.
11412  */
11413 static void quirk_pipea_force(struct drm_device *dev)
11414 {
11415         struct drm_i915_private *dev_priv = dev->dev_private;
11416
11417         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
11418         DRM_INFO("applying pipe a force quirk\n");
11419 }
11420
11421 /*
11422  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
11423  */
11424 static void quirk_ssc_force_disable(struct drm_device *dev)
11425 {
11426         struct drm_i915_private *dev_priv = dev->dev_private;
11427         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
11428         DRM_INFO("applying lvds SSC disable quirk\n");
11429 }
11430
11431 /*
11432  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
11433  * brightness value
11434  */
11435 static void quirk_invert_brightness(struct drm_device *dev)
11436 {
11437         struct drm_i915_private *dev_priv = dev->dev_private;
11438         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
11439         DRM_INFO("applying inverted panel brightness quirk\n");
11440 }
11441
11442 struct intel_quirk {
11443         int device;
11444         int subsystem_vendor;
11445         int subsystem_device;
11446         void (*hook)(struct drm_device *dev);
11447 };
11448
11449 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
11450 struct intel_dmi_quirk {
11451         void (*hook)(struct drm_device *dev);
11452         const struct dmi_system_id (*dmi_id_list)[];
11453 };
11454
11455 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
11456 {
11457         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
11458         return 1;
11459 }
11460
11461 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
11462         {
11463                 .dmi_id_list = &(const struct dmi_system_id[]) {
11464                         {
11465                                 .callback = intel_dmi_reverse_brightness,
11466                                 .ident = "NCR Corporation",
11467                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
11468                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
11469                                 },
11470                         },
11471                         { }  /* terminating entry */
11472                 },
11473                 .hook = quirk_invert_brightness,
11474         },
11475 };
11476
11477 static struct intel_quirk intel_quirks[] = {
11478         /* HP Mini needs pipe A force quirk (LP: #322104) */
11479         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
11480
11481         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
11482         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
11483
11484         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
11485         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
11486
11487         /* 830 needs to leave pipe A & dpll A up */
11488         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
11489
11490         /* Lenovo U160 cannot use SSC on LVDS */
11491         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
11492
11493         /* Sony Vaio Y cannot use SSC on LVDS */
11494         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
11495
11496         /* Acer Aspire 5734Z must invert backlight brightness */
11497         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
11498
11499         /* Acer/eMachines G725 */
11500         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
11501
11502         /* Acer/eMachines e725 */
11503         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
11504
11505         /* Acer/Packard Bell NCL20 */
11506         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
11507
11508         /* Acer Aspire 4736Z */
11509         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
11510
11511         /* Acer Aspire 5336 */
11512         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
11513 };
11514
11515 static void intel_init_quirks(struct drm_device *dev)
11516 {
11517         struct pci_dev *d = dev->pdev;
11518         int i;
11519
11520         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
11521                 struct intel_quirk *q = &intel_quirks[i];
11522
11523                 if (d->device == q->device &&
11524                     (d->subsystem_vendor == q->subsystem_vendor ||
11525                      q->subsystem_vendor == PCI_ANY_ID) &&
11526                     (d->subsystem_device == q->subsystem_device ||
11527                      q->subsystem_device == PCI_ANY_ID))
11528                         q->hook(dev);
11529         }
11530         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
11531                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
11532                         intel_dmi_quirks[i].hook(dev);
11533         }
11534 }
11535
11536 /* Disable the VGA plane that we never use */
11537 static void i915_disable_vga(struct drm_device *dev)
11538 {
11539         struct drm_i915_private *dev_priv = dev->dev_private;
11540         u8 sr1;
11541         u32 vga_reg = i915_vgacntrl_reg(dev);
11542
11543         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
11544         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
11545         outb(SR01, VGA_SR_INDEX);
11546         sr1 = inb(VGA_SR_DATA);
11547         outb(sr1 | 1<<5, VGA_SR_DATA);
11548         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
11549         udelay(300);
11550
11551         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
11552         POSTING_READ(vga_reg);
11553 }
11554
11555 void intel_modeset_init_hw(struct drm_device *dev)
11556 {
11557         intel_prepare_ddi(dev);
11558
11559         intel_init_clock_gating(dev);
11560
11561         intel_reset_dpio(dev);
11562
11563         intel_enable_gt_powersave(dev);
11564 }
11565
11566 void intel_modeset_suspend_hw(struct drm_device *dev)
11567 {
11568         intel_suspend_hw(dev);
11569 }
11570
11571 void intel_modeset_init(struct drm_device *dev)
11572 {
11573         struct drm_i915_private *dev_priv = dev->dev_private;
11574         int sprite, ret;
11575         enum pipe pipe;
11576         struct intel_crtc *crtc;
11577
11578         drm_mode_config_init(dev);
11579
11580         dev->mode_config.min_width = 0;
11581         dev->mode_config.min_height = 0;
11582
11583         dev->mode_config.preferred_depth = 24;
11584         dev->mode_config.prefer_shadow = 1;
11585
11586         dev->mode_config.funcs = &intel_mode_funcs;
11587
11588         intel_init_quirks(dev);
11589
11590         intel_init_pm(dev);
11591
11592         if (INTEL_INFO(dev)->num_pipes == 0)
11593                 return;
11594
11595         intel_init_display(dev);
11596
11597         if (IS_GEN2(dev)) {
11598                 dev->mode_config.max_width = 2048;
11599                 dev->mode_config.max_height = 2048;
11600         } else if (IS_GEN3(dev)) {
11601                 dev->mode_config.max_width = 4096;
11602                 dev->mode_config.max_height = 4096;
11603         } else {
11604                 dev->mode_config.max_width = 8192;
11605                 dev->mode_config.max_height = 8192;
11606         }
11607
11608         if (IS_GEN2(dev)) {
11609                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
11610                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
11611         } else {
11612                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
11613                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
11614         }
11615
11616         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
11617
11618         DRM_DEBUG_KMS("%d display pipe%s available.\n",
11619                       INTEL_INFO(dev)->num_pipes,
11620                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
11621
11622         for_each_pipe(pipe) {
11623                 intel_crtc_init(dev, pipe);
11624                 for_each_sprite(pipe, sprite) {
11625                         ret = intel_plane_init(dev, pipe, sprite);
11626                         if (ret)
11627                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
11628                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
11629                 }
11630         }
11631
11632         intel_init_dpio(dev);
11633         intel_reset_dpio(dev);
11634
11635         intel_cpu_pll_init(dev);
11636         intel_shared_dpll_init(dev);
11637
11638         /* Just disable it once at startup */
11639         i915_disable_vga(dev);
11640         intel_setup_outputs(dev);
11641
11642         /* Just in case the BIOS is doing something questionable. */
11643         intel_disable_fbc(dev);
11644
11645         mutex_lock(&dev->mode_config.mutex);
11646         intel_modeset_setup_hw_state(dev, false);
11647         mutex_unlock(&dev->mode_config.mutex);
11648
11649         for_each_intel_crtc(dev, crtc) {
11650                 if (!crtc->active)
11651                         continue;
11652
11653                 /*
11654                  * Note that reserving the BIOS fb up front prevents us
11655                  * from stuffing other stolen allocations like the ring
11656                  * on top.  This prevents some ugliness at boot time, and
11657                  * can even allow for smooth boot transitions if the BIOS
11658                  * fb is large enough for the active pipe configuration.
11659                  */
11660                 if (dev_priv->display.get_plane_config) {
11661                         dev_priv->display.get_plane_config(crtc,
11662                                                            &crtc->plane_config);
11663                         /*
11664                          * If the fb is shared between multiple heads, we'll
11665                          * just get the first one.
11666                          */
11667                         intel_find_plane_obj(crtc, &crtc->plane_config);
11668                 }
11669         }
11670 }
11671
11672 static void
11673 intel_connector_break_all_links(struct intel_connector *connector)
11674 {
11675         connector->base.dpms = DRM_MODE_DPMS_OFF;
11676         connector->base.encoder = NULL;
11677         connector->encoder->connectors_active = false;
11678         connector->encoder->base.crtc = NULL;
11679 }
11680
11681 static void intel_enable_pipe_a(struct drm_device *dev)
11682 {
11683         struct intel_connector *connector;
11684         struct drm_connector *crt = NULL;
11685         struct intel_load_detect_pipe load_detect_temp;
11686
11687         /* We can't just switch on the pipe A, we need to set things up with a
11688          * proper mode and output configuration. As a gross hack, enable pipe A
11689          * by enabling the load detect pipe once. */
11690         list_for_each_entry(connector,
11691                             &dev->mode_config.connector_list,
11692                             base.head) {
11693                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
11694                         crt = &connector->base;
11695                         break;
11696                 }
11697         }
11698
11699         if (!crt)
11700                 return;
11701
11702         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
11703                 intel_release_load_detect_pipe(crt, &load_detect_temp);
11704
11705
11706 }
11707
11708 static bool
11709 intel_check_plane_mapping(struct intel_crtc *crtc)
11710 {
11711         struct drm_device *dev = crtc->base.dev;
11712         struct drm_i915_private *dev_priv = dev->dev_private;
11713         u32 reg, val;
11714
11715         if (INTEL_INFO(dev)->num_pipes == 1)
11716                 return true;
11717
11718         reg = DSPCNTR(!crtc->plane);
11719         val = I915_READ(reg);
11720
11721         if ((val & DISPLAY_PLANE_ENABLE) &&
11722             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
11723                 return false;
11724
11725         return true;
11726 }
11727
11728 static void intel_sanitize_crtc(struct intel_crtc *crtc)
11729 {
11730         struct drm_device *dev = crtc->base.dev;
11731         struct drm_i915_private *dev_priv = dev->dev_private;
11732         u32 reg;
11733
11734         /* Clear any frame start delays used for debugging left by the BIOS */
11735         reg = PIPECONF(crtc->config.cpu_transcoder);
11736         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
11737
11738         /* We need to sanitize the plane -> pipe mapping first because this will
11739          * disable the crtc (and hence change the state) if it is wrong. Note
11740          * that gen4+ has a fixed plane -> pipe mapping.  */
11741         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
11742                 struct intel_connector *connector;
11743                 bool plane;
11744
11745                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
11746                               crtc->base.base.id);
11747
11748                 /* Pipe has the wrong plane attached and the plane is active.
11749                  * Temporarily change the plane mapping and disable everything
11750                  * ...  */
11751                 plane = crtc->plane;
11752                 crtc->plane = !plane;
11753                 dev_priv->display.crtc_disable(&crtc->base);
11754                 crtc->plane = plane;
11755
11756                 /* ... and break all links. */
11757                 list_for_each_entry(connector, &dev->mode_config.connector_list,
11758                                     base.head) {
11759                         if (connector->encoder->base.crtc != &crtc->base)
11760                                 continue;
11761
11762                         intel_connector_break_all_links(connector);
11763                 }
11764
11765                 WARN_ON(crtc->active);
11766                 crtc->base.enabled = false;
11767         }
11768
11769         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
11770             crtc->pipe == PIPE_A && !crtc->active) {
11771                 /* BIOS forgot to enable pipe A, this mostly happens after
11772                  * resume. Force-enable the pipe to fix this, the update_dpms
11773                  * call below we restore the pipe to the right state, but leave
11774                  * the required bits on. */
11775                 intel_enable_pipe_a(dev);
11776         }
11777
11778         /* Adjust the state of the output pipe according to whether we
11779          * have active connectors/encoders. */
11780         intel_crtc_update_dpms(&crtc->base);
11781
11782         if (crtc->active != crtc->base.enabled) {
11783                 struct intel_encoder *encoder;
11784
11785                 /* This can happen either due to bugs in the get_hw_state
11786                  * functions or because the pipe is force-enabled due to the
11787                  * pipe A quirk. */
11788                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
11789                               crtc->base.base.id,
11790                               crtc->base.enabled ? "enabled" : "disabled",
11791                               crtc->active ? "enabled" : "disabled");
11792
11793                 crtc->base.enabled = crtc->active;
11794
11795                 /* Because we only establish the connector -> encoder ->
11796                  * crtc links if something is active, this means the
11797                  * crtc is now deactivated. Break the links. connector
11798                  * -> encoder links are only establish when things are
11799                  *  actually up, hence no need to break them. */
11800                 WARN_ON(crtc->active);
11801
11802                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
11803                         WARN_ON(encoder->connectors_active);
11804                         encoder->base.crtc = NULL;
11805                 }
11806         }
11807         if (crtc->active) {
11808                 /*
11809                  * We start out with underrun reporting disabled to avoid races.
11810                  * For correct bookkeeping mark this on active crtcs.
11811                  *
11812                  * No protection against concurrent access is required - at
11813                  * worst a fifo underrun happens which also sets this to false.
11814                  */
11815                 crtc->cpu_fifo_underrun_disabled = true;
11816                 crtc->pch_fifo_underrun_disabled = true;
11817         }
11818 }
11819
11820 static void intel_sanitize_encoder(struct intel_encoder *encoder)
11821 {
11822         struct intel_connector *connector;
11823         struct drm_device *dev = encoder->base.dev;
11824
11825         /* We need to check both for a crtc link (meaning that the
11826          * encoder is active and trying to read from a pipe) and the
11827          * pipe itself being active. */
11828         bool has_active_crtc = encoder->base.crtc &&
11829                 to_intel_crtc(encoder->base.crtc)->active;
11830
11831         if (encoder->connectors_active && !has_active_crtc) {
11832                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
11833                               encoder->base.base.id,
11834                               drm_get_encoder_name(&encoder->base));
11835
11836                 /* Connector is active, but has no active pipe. This is
11837                  * fallout from our resume register restoring. Disable
11838                  * the encoder manually again. */
11839                 if (encoder->base.crtc) {
11840                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
11841                                       encoder->base.base.id,
11842                                       drm_get_encoder_name(&encoder->base));
11843                         encoder->disable(encoder);
11844                 }
11845
11846                 /* Inconsistent output/port/pipe state happens presumably due to
11847                  * a bug in one of the get_hw_state functions. Or someplace else
11848                  * in our code, like the register restore mess on resume. Clamp
11849                  * things to off as a safer default. */
11850                 list_for_each_entry(connector,
11851                                     &dev->mode_config.connector_list,
11852                                     base.head) {
11853                         if (connector->encoder != encoder)
11854                                 continue;
11855
11856                         intel_connector_break_all_links(connector);
11857                 }
11858         }
11859         /* Enabled encoders without active connectors will be fixed in
11860          * the crtc fixup. */
11861 }
11862
11863 void i915_redisable_vga_power_on(struct drm_device *dev)
11864 {
11865         struct drm_i915_private *dev_priv = dev->dev_private;
11866         u32 vga_reg = i915_vgacntrl_reg(dev);
11867
11868         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
11869                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
11870                 i915_disable_vga(dev);
11871         }
11872 }
11873
11874 void i915_redisable_vga(struct drm_device *dev)
11875 {
11876         struct drm_i915_private *dev_priv = dev->dev_private;
11877
11878         /* This function can be called both from intel_modeset_setup_hw_state or
11879          * at a very early point in our resume sequence, where the power well
11880          * structures are not yet restored. Since this function is at a very
11881          * paranoid "someone might have enabled VGA while we were not looking"
11882          * level, just check if the power well is enabled instead of trying to
11883          * follow the "don't touch the power well if we don't need it" policy
11884          * the rest of the driver uses. */
11885         if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
11886                 return;
11887
11888         i915_redisable_vga_power_on(dev);
11889 }
11890
11891 static bool primary_get_hw_state(struct intel_crtc *crtc)
11892 {
11893         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
11894
11895         if (!crtc->active)
11896                 return false;
11897
11898         return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
11899 }
11900
11901 static void intel_modeset_readout_hw_state(struct drm_device *dev)
11902 {
11903         struct drm_i915_private *dev_priv = dev->dev_private;
11904         enum pipe pipe;
11905         struct intel_crtc *crtc;
11906         struct intel_encoder *encoder;
11907         struct intel_connector *connector;
11908         int i;
11909
11910         for_each_intel_crtc(dev, crtc) {
11911                 memset(&crtc->config, 0, sizeof(crtc->config));
11912
11913                 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
11914
11915                 crtc->active = dev_priv->display.get_pipe_config(crtc,
11916                                                                  &crtc->config);
11917
11918                 crtc->base.enabled = crtc->active;
11919                 crtc->primary_enabled = primary_get_hw_state(crtc);
11920
11921                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
11922                               crtc->base.base.id,
11923                               crtc->active ? "enabled" : "disabled");
11924         }
11925
11926         /* FIXME: Smash this into the new shared dpll infrastructure. */
11927         if (HAS_DDI(dev))
11928                 intel_ddi_setup_hw_pll_state(dev);
11929
11930         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11931                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11932
11933                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
11934                 pll->active = 0;
11935                 for_each_intel_crtc(dev, crtc) {
11936                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11937                                 pll->active++;
11938                 }
11939                 pll->refcount = pll->active;
11940
11941                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
11942                               pll->name, pll->refcount, pll->on);
11943         }
11944
11945         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11946                             base.head) {
11947                 pipe = 0;
11948
11949                 if (encoder->get_hw_state(encoder, &pipe)) {
11950                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11951                         encoder->base.crtc = &crtc->base;
11952                         encoder->get_config(encoder, &crtc->config);
11953                 } else {
11954                         encoder->base.crtc = NULL;
11955                 }
11956
11957                 encoder->connectors_active = false;
11958                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
11959                               encoder->base.base.id,
11960                               drm_get_encoder_name(&encoder->base),
11961                               encoder->base.crtc ? "enabled" : "disabled",
11962                               pipe_name(pipe));
11963         }
11964
11965         list_for_each_entry(connector, &dev->mode_config.connector_list,
11966                             base.head) {
11967                 if (connector->get_hw_state(connector)) {
11968                         connector->base.dpms = DRM_MODE_DPMS_ON;
11969                         connector->encoder->connectors_active = true;
11970                         connector->base.encoder = &connector->encoder->base;
11971                 } else {
11972                         connector->base.dpms = DRM_MODE_DPMS_OFF;
11973                         connector->base.encoder = NULL;
11974                 }
11975                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
11976                               connector->base.base.id,
11977                               drm_get_connector_name(&connector->base),
11978                               connector->base.encoder ? "enabled" : "disabled");
11979         }
11980 }
11981
11982 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
11983  * and i915 state tracking structures. */
11984 void intel_modeset_setup_hw_state(struct drm_device *dev,
11985                                   bool force_restore)
11986 {
11987         struct drm_i915_private *dev_priv = dev->dev_private;
11988         enum pipe pipe;
11989         struct intel_crtc *crtc;
11990         struct intel_encoder *encoder;
11991         int i;
11992
11993         intel_modeset_readout_hw_state(dev);
11994
11995         /*
11996          * Now that we have the config, copy it to each CRTC struct
11997          * Note that this could go away if we move to using crtc_config
11998          * checking everywhere.
11999          */
12000         for_each_intel_crtc(dev, crtc) {
12001                 if (crtc->active && i915.fastboot) {
12002                         intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
12003                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
12004                                       crtc->base.base.id);
12005                         drm_mode_debug_printmodeline(&crtc->base.mode);
12006                 }
12007         }
12008
12009         /* HW state is read out, now we need to sanitize this mess. */
12010         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
12011                             base.head) {
12012                 intel_sanitize_encoder(encoder);
12013         }
12014
12015         for_each_pipe(pipe) {
12016                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
12017                 intel_sanitize_crtc(crtc);
12018                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
12019         }
12020
12021         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12022                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12023
12024                 if (!pll->on || pll->active)
12025                         continue;
12026
12027                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
12028
12029                 pll->disable(dev_priv, pll);
12030                 pll->on = false;
12031         }
12032
12033         if (HAS_PCH_SPLIT(dev))
12034                 ilk_wm_get_hw_state(dev);
12035
12036         if (force_restore) {
12037                 i915_redisable_vga(dev);
12038
12039                 /*
12040                  * We need to use raw interfaces for restoring state to avoid
12041                  * checking (bogus) intermediate states.
12042                  */
12043                 for_each_pipe(pipe) {
12044                         struct drm_crtc *crtc =
12045                                 dev_priv->pipe_to_crtc_mapping[pipe];
12046
12047                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
12048                                          crtc->primary->fb);
12049                 }
12050         } else {
12051                 intel_modeset_update_staged_output_state(dev);
12052         }
12053
12054         intel_modeset_check_state(dev);
12055 }
12056
12057 void intel_modeset_gem_init(struct drm_device *dev)
12058 {
12059         struct drm_crtc *c;
12060         struct intel_framebuffer *fb;
12061
12062         mutex_lock(&dev->struct_mutex);
12063         intel_init_gt_powersave(dev);
12064         mutex_unlock(&dev->struct_mutex);
12065
12066         intel_modeset_init_hw(dev);
12067
12068         intel_setup_overlay(dev);
12069
12070         /*
12071          * Make sure any fbs we allocated at startup are properly
12072          * pinned & fenced.  When we do the allocation it's too early
12073          * for this.
12074          */
12075         mutex_lock(&dev->struct_mutex);
12076         for_each_crtc(dev, c) {
12077                 if (!c->primary->fb)
12078                         continue;
12079
12080                 fb = to_intel_framebuffer(c->primary->fb);
12081                 if (intel_pin_and_fence_fb_obj(dev, fb->obj, NULL)) {
12082                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
12083                                   to_intel_crtc(c)->pipe);
12084                         drm_framebuffer_unreference(c->primary->fb);
12085                         c->primary->fb = NULL;
12086                 }
12087         }
12088         mutex_unlock(&dev->struct_mutex);
12089 }
12090
12091 void intel_connector_unregister(struct intel_connector *intel_connector)
12092 {
12093         struct drm_connector *connector = &intel_connector->base;
12094
12095         intel_panel_destroy_backlight(connector);
12096         drm_sysfs_connector_remove(connector);
12097 }
12098
12099 void intel_modeset_cleanup(struct drm_device *dev)
12100 {
12101         struct drm_i915_private *dev_priv = dev->dev_private;
12102         struct drm_crtc *crtc;
12103         struct drm_connector *connector;
12104
12105         /*
12106          * Interrupts and polling as the first thing to avoid creating havoc.
12107          * Too much stuff here (turning of rps, connectors, ...) would
12108          * experience fancy races otherwise.
12109          */
12110         drm_irq_uninstall(dev);
12111         cancel_work_sync(&dev_priv->hotplug_work);
12112         /*
12113          * Due to the hpd irq storm handling the hotplug work can re-arm the
12114          * poll handlers. Hence disable polling after hpd handling is shut down.
12115          */
12116         drm_kms_helper_poll_fini(dev);
12117
12118         mutex_lock(&dev->struct_mutex);
12119
12120         intel_unregister_dsm_handler();
12121
12122         for_each_crtc(dev, crtc) {
12123                 /* Skip inactive CRTCs */
12124                 if (!crtc->primary->fb)
12125                         continue;
12126
12127                 intel_increase_pllclock(crtc);
12128         }
12129
12130         intel_disable_fbc(dev);
12131
12132         intel_disable_gt_powersave(dev);
12133
12134         ironlake_teardown_rc6(dev);
12135
12136         mutex_unlock(&dev->struct_mutex);
12137
12138         /* flush any delayed tasks or pending work */
12139         flush_scheduled_work();
12140
12141         /* destroy the backlight and sysfs files before encoders/connectors */
12142         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12143                 struct intel_connector *intel_connector;
12144
12145                 intel_connector = to_intel_connector(connector);
12146                 intel_connector->unregister(intel_connector);
12147         }
12148
12149         drm_mode_config_cleanup(dev);
12150
12151         intel_cleanup_overlay(dev);
12152
12153         mutex_lock(&dev->struct_mutex);
12154         intel_cleanup_gt_powersave(dev);
12155         mutex_unlock(&dev->struct_mutex);
12156 }
12157
12158 /*
12159  * Return which encoder is currently attached for connector.
12160  */
12161 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
12162 {
12163         return &intel_attached_encoder(connector)->base;
12164 }
12165
12166 void intel_connector_attach_encoder(struct intel_connector *connector,
12167                                     struct intel_encoder *encoder)
12168 {
12169         connector->encoder = encoder;
12170         drm_mode_connector_attach_encoder(&connector->base,
12171                                           &encoder->base);
12172 }
12173
12174 /*
12175  * set vga decode state - true == enable VGA decode
12176  */
12177 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
12178 {
12179         struct drm_i915_private *dev_priv = dev->dev_private;
12180         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
12181         u16 gmch_ctrl;
12182
12183         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
12184                 DRM_ERROR("failed to read control word\n");
12185                 return -EIO;
12186         }
12187
12188         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
12189                 return 0;
12190
12191         if (state)
12192                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
12193         else
12194                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
12195
12196         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
12197                 DRM_ERROR("failed to write control word\n");
12198                 return -EIO;
12199         }
12200
12201         return 0;
12202 }
12203
12204 struct intel_display_error_state {
12205
12206         u32 power_well_driver;
12207
12208         int num_transcoders;
12209
12210         struct intel_cursor_error_state {
12211                 u32 control;
12212                 u32 position;
12213                 u32 base;
12214                 u32 size;
12215         } cursor[I915_MAX_PIPES];
12216
12217         struct intel_pipe_error_state {
12218                 bool power_domain_on;
12219                 u32 source;
12220                 u32 stat;
12221         } pipe[I915_MAX_PIPES];
12222
12223         struct intel_plane_error_state {
12224                 u32 control;
12225                 u32 stride;
12226                 u32 size;
12227                 u32 pos;
12228                 u32 addr;
12229                 u32 surface;
12230                 u32 tile_offset;
12231         } plane[I915_MAX_PIPES];
12232
12233         struct intel_transcoder_error_state {
12234                 bool power_domain_on;
12235                 enum transcoder cpu_transcoder;
12236
12237                 u32 conf;
12238
12239                 u32 htotal;
12240                 u32 hblank;
12241                 u32 hsync;
12242                 u32 vtotal;
12243                 u32 vblank;
12244                 u32 vsync;
12245         } transcoder[4];
12246 };
12247
12248 struct intel_display_error_state *
12249 intel_display_capture_error_state(struct drm_device *dev)
12250 {
12251         struct drm_i915_private *dev_priv = dev->dev_private;
12252         struct intel_display_error_state *error;
12253         int transcoders[] = {
12254                 TRANSCODER_A,
12255                 TRANSCODER_B,
12256                 TRANSCODER_C,
12257                 TRANSCODER_EDP,
12258         };
12259         int i;
12260
12261         if (INTEL_INFO(dev)->num_pipes == 0)
12262                 return NULL;
12263
12264         error = kzalloc(sizeof(*error), GFP_ATOMIC);
12265         if (error == NULL)
12266                 return NULL;
12267
12268         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
12269                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
12270
12271         for_each_pipe(i) {
12272                 error->pipe[i].power_domain_on =
12273                         intel_display_power_enabled_sw(dev_priv,
12274                                                        POWER_DOMAIN_PIPE(i));
12275                 if (!error->pipe[i].power_domain_on)
12276                         continue;
12277
12278                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
12279                         error->cursor[i].control = I915_READ(CURCNTR(i));
12280                         error->cursor[i].position = I915_READ(CURPOS(i));
12281                         error->cursor[i].base = I915_READ(CURBASE(i));
12282                 } else {
12283                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
12284                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
12285                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
12286                 }
12287
12288                 error->plane[i].control = I915_READ(DSPCNTR(i));
12289                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
12290                 if (INTEL_INFO(dev)->gen <= 3) {
12291                         error->plane[i].size = I915_READ(DSPSIZE(i));
12292                         error->plane[i].pos = I915_READ(DSPPOS(i));
12293                 }
12294                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
12295                         error->plane[i].addr = I915_READ(DSPADDR(i));
12296                 if (INTEL_INFO(dev)->gen >= 4) {
12297                         error->plane[i].surface = I915_READ(DSPSURF(i));
12298                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
12299                 }
12300
12301                 error->pipe[i].source = I915_READ(PIPESRC(i));
12302
12303                 if (!HAS_PCH_SPLIT(dev))
12304                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
12305         }
12306
12307         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
12308         if (HAS_DDI(dev_priv->dev))
12309                 error->num_transcoders++; /* Account for eDP. */
12310
12311         for (i = 0; i < error->num_transcoders; i++) {
12312                 enum transcoder cpu_transcoder = transcoders[i];
12313
12314                 error->transcoder[i].power_domain_on =
12315                         intel_display_power_enabled_sw(dev_priv,
12316                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
12317                 if (!error->transcoder[i].power_domain_on)
12318                         continue;
12319
12320                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
12321
12322                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
12323                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
12324                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
12325                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
12326                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
12327                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
12328                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
12329         }
12330
12331         return error;
12332 }
12333
12334 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
12335
12336 void
12337 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
12338                                 struct drm_device *dev,
12339                                 struct intel_display_error_state *error)
12340 {
12341         int i;
12342
12343         if (!error)
12344                 return;
12345
12346         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
12347         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
12348                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
12349                            error->power_well_driver);
12350         for_each_pipe(i) {
12351                 err_printf(m, "Pipe [%d]:\n", i);
12352                 err_printf(m, "  Power: %s\n",
12353                            error->pipe[i].power_domain_on ? "on" : "off");
12354                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
12355                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
12356
12357                 err_printf(m, "Plane [%d]:\n", i);
12358                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
12359                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
12360                 if (INTEL_INFO(dev)->gen <= 3) {
12361                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
12362                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
12363                 }
12364                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
12365                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
12366                 if (INTEL_INFO(dev)->gen >= 4) {
12367                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
12368                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
12369                 }
12370
12371                 err_printf(m, "Cursor [%d]:\n", i);
12372                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
12373                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
12374                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
12375         }
12376
12377         for (i = 0; i < error->num_transcoders; i++) {
12378                 err_printf(m, "CPU transcoder: %c\n",
12379                            transcoder_name(error->transcoder[i].cpu_transcoder));
12380                 err_printf(m, "  Power: %s\n",
12381                            error->transcoder[i].power_domain_on ? "on" : "off");
12382                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
12383                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
12384                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
12385                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
12386                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
12387                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
12388                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
12389         }
12390 }