drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc);
  46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  47
  48 typedef struct {
  49         int     min, max;
  50 } intel_range_t;
  51
  52 typedef struct {
  53         int     dot_limit;
  54         int     p2_slow, p2_fast;
  55 } intel_p2_t;
  56
  57 #define INTEL_P2_NUM                  2
  58 typedef struct intel_limit intel_limit_t;
  59 struct intel_limit {
  60         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  61         intel_p2_t          p2;
  62         /**
  63          * find_pll() - Find the best values for the PLL
  64          * @limit: limits for the PLL
  65          * @crtc: current CRTC
  66          * @target: target frequency in kHz
  67          * @refclk: reference clock frequency in kHz
  68          * @match_clock: if provided, @best_clock P divider must
  69          *               match the P divider from @match_clock
  70          *               used for LVDS downclocking
  71          * @best_clock: best PLL values found
  72          *
  73          * Returns true on success, false on failure.
  74          */
  75         bool (*find_pll)(const intel_limit_t *limit,
  76                          struct drm_crtc *crtc,
  77                          int target, int refclk,
  78                          intel_clock_t *match_clock,
  79                          intel_clock_t *best_clock);
  80 };
  81
  82 /* FDI */
  83 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  84
  85 int
  86 intel_pch_rawclk(struct drm_device *dev)
  87 {
  88         struct drm_i915_private *dev_priv = dev->dev_private;
  89
  90         WARN_ON(!HAS_PCH_SPLIT(dev));
  91
  92         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  93 }
  94
  95 static bool
  96 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  97                     int target, int refclk, intel_clock_t *match_clock,
  98                     intel_clock_t *best_clock);
  99 static bool
 100 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 101                         int target, int refclk, intel_clock_t *match_clock,
 102                         intel_clock_t *best_clock);
 103
 104 static bool
 105 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 106                         int target, int refclk, intel_clock_t *match_clock,
 107                         intel_clock_t *best_clock);
 108
 109 static inline u32 /* units of 100MHz */
 110 intel_fdi_link_freq(struct drm_device *dev)
 111 {
 112         if (IS_GEN5(dev)) {
 113                 struct drm_i915_private *dev_priv = dev->dev_private;
 114                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 115         } else
 116                 return 27;
 117 }
 118
 119 static const intel_limit_t intel_limits_i8xx_dvo = {
 120         .dot = { .min = 25000, .max = 350000 },
 121         .vco = { .min = 930000, .max = 1400000 },
 122         .n = { .min = 3, .max = 16 },
 123         .m = { .min = 96, .max = 140 },
 124         .m1 = { .min = 18, .max = 26 },
 125         .m2 = { .min = 6, .max = 16 },
 126         .p = { .min = 4, .max = 128 },
 127         .p1 = { .min = 2, .max = 33 },
 128         .p2 = { .dot_limit = 165000,
 129                 .p2_slow = 4, .p2_fast = 2 },
 130         .find_pll = intel_find_best_PLL,
 131 };
 132
 133 static const intel_limit_t intel_limits_i8xx_lvds = {
 134         .dot = { .min = 25000, .max = 350000 },
 135         .vco = { .min = 930000, .max = 1400000 },
 136         .n = { .min = 3, .max = 16 },
 137         .m = { .min = 96, .max = 140 },
 138         .m1 = { .min = 18, .max = 26 },
 139         .m2 = { .min = 6, .max = 16 },
 140         .p = { .min = 4, .max = 128 },
 141         .p1 = { .min = 1, .max = 6 },
 142         .p2 = { .dot_limit = 165000,
 143                 .p2_slow = 14, .p2_fast = 7 },
 144         .find_pll = intel_find_best_PLL,
 145 };
 146
 147 static const intel_limit_t intel_limits_i9xx_sdvo = {
 148         .dot = { .min = 20000, .max = 400000 },
 149         .vco = { .min = 1400000, .max = 2800000 },
 150         .n = { .min = 1, .max = 6 },
 151         .m = { .min = 70, .max = 120 },
 152         .m1 = { .min = 8, .max = 18 },
 153         .m2 = { .min = 3, .max = 7 },
 154         .p = { .min = 5, .max = 80 },
 155         .p1 = { .min = 1, .max = 8 },
 156         .p2 = { .dot_limit = 200000,
 157                 .p2_slow = 10, .p2_fast = 5 },
 158         .find_pll = intel_find_best_PLL,
 159 };
 160
 161 static const intel_limit_t intel_limits_i9xx_lvds = {
 162         .dot = { .min = 20000, .max = 400000 },
 163         .vco = { .min = 1400000, .max = 2800000 },
 164         .n = { .min = 1, .max = 6 },
 165         .m = { .min = 70, .max = 120 },
 166         .m1 = { .min = 8, .max = 18 },
 167         .m2 = { .min = 3, .max = 7 },
 168         .p = { .min = 7, .max = 98 },
 169         .p1 = { .min = 1, .max = 8 },
 170         .p2 = { .dot_limit = 112000,
 171                 .p2_slow = 14, .p2_fast = 7 },
 172         .find_pll = intel_find_best_PLL,
 173 };
 174
 175
 176 static const intel_limit_t intel_limits_g4x_sdvo = {
 177         .dot = { .min = 25000, .max = 270000 },
 178         .vco = { .min = 1750000, .max = 3500000},
 179         .n = { .min = 1, .max = 4 },
 180         .m = { .min = 104, .max = 138 },
 181         .m1 = { .min = 17, .max = 23 },
 182         .m2 = { .min = 5, .max = 11 },
 183         .p = { .min = 10, .max = 30 },
 184         .p1 = { .min = 1, .max = 3},
 185         .p2 = { .dot_limit = 270000,
 186                 .p2_slow = 10,
 187                 .p2_fast = 10
 188         },
 189         .find_pll = intel_g4x_find_best_PLL,
 190 };
 191
 192 static const intel_limit_t intel_limits_g4x_hdmi = {
 193         .dot = { .min = 22000, .max = 400000 },
 194         .vco = { .min = 1750000, .max = 3500000},
 195         .n = { .min = 1, .max = 4 },
 196         .m = { .min = 104, .max = 138 },
 197         .m1 = { .min = 16, .max = 23 },
 198         .m2 = { .min = 5, .max = 11 },
 199         .p = { .min = 5, .max = 80 },
 200         .p1 = { .min = 1, .max = 8},
 201         .p2 = { .dot_limit = 165000,
 202                 .p2_slow = 10, .p2_fast = 5 },
 203         .find_pll = intel_g4x_find_best_PLL,
 204 };
 205
 206 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 207         .dot = { .min = 20000, .max = 115000 },
 208         .vco = { .min = 1750000, .max = 3500000 },
 209         .n = { .min = 1, .max = 3 },
 210         .m = { .min = 104, .max = 138 },
 211         .m1 = { .min = 17, .max = 23 },
 212         .m2 = { .min = 5, .max = 11 },
 213         .p = { .min = 28, .max = 112 },
 214         .p1 = { .min = 2, .max = 8 },
 215         .p2 = { .dot_limit = 0,
 216                 .p2_slow = 14, .p2_fast = 14
 217         },
 218         .find_pll = intel_g4x_find_best_PLL,
 219 };
 220
 221 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 222         .dot = { .min = 80000, .max = 224000 },
 223         .vco = { .min = 1750000, .max = 3500000 },
 224         .n = { .min = 1, .max = 3 },
 225         .m = { .min = 104, .max = 138 },
 226         .m1 = { .min = 17, .max = 23 },
 227         .m2 = { .min = 5, .max = 11 },
 228         .p = { .min = 14, .max = 42 },
 229         .p1 = { .min = 2, .max = 6 },
 230         .p2 = { .dot_limit = 0,
 231                 .p2_slow = 7, .p2_fast = 7
 232         },
 233         .find_pll = intel_g4x_find_best_PLL,
 234 };
 235
 236 static const intel_limit_t intel_limits_pineview_sdvo = {
 237         .dot = { .min = 20000, .max = 400000},
 238         .vco = { .min = 1700000, .max = 3500000 },
 239         /* Pineview's Ncounter is a ring counter */
 240         .n = { .min = 3, .max = 6 },
 241         .m = { .min = 2, .max = 256 },
 242         /* Pineview only has one combined m divider, which we treat as m2. */
 243         .m1 = { .min = 0, .max = 0 },
 244         .m2 = { .min = 0, .max = 254 },
 245         .p = { .min = 5, .max = 80 },
 246         .p1 = { .min = 1, .max = 8 },
 247         .p2 = { .dot_limit = 200000,
 248                 .p2_slow = 10, .p2_fast = 5 },
 249         .find_pll = intel_find_best_PLL,
 250 };
 251
 252 static const intel_limit_t intel_limits_pineview_lvds = {
 253         .dot = { .min = 20000, .max = 400000 },
 254         .vco = { .min = 1700000, .max = 3500000 },
 255         .n = { .min = 3, .max = 6 },
 256         .m = { .min = 2, .max = 256 },
 257         .m1 = { .min = 0, .max = 0 },
 258         .m2 = { .min = 0, .max = 254 },
 259         .p = { .min = 7, .max = 112 },
 260         .p1 = { .min = 1, .max = 8 },
 261         .p2 = { .dot_limit = 112000,
 262                 .p2_slow = 14, .p2_fast = 14 },
 263         .find_pll = intel_find_best_PLL,
 264 };
 265
 266 /* Ironlake / Sandybridge
 267  *
 268  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 269  * the range value for them is (actual_value - 2).
 270  */
 271 static const intel_limit_t intel_limits_ironlake_dac = {
 272         .dot = { .min = 25000, .max = 350000 },
 273         .vco = { .min = 1760000, .max = 3510000 },
 274         .n = { .min = 1, .max = 5 },
 275         .m = { .min = 79, .max = 127 },
 276         .m1 = { .min = 12, .max = 22 },
 277         .m2 = { .min = 5, .max = 9 },
 278         .p = { .min = 5, .max = 80 },
 279         .p1 = { .min = 1, .max = 8 },
 280         .p2 = { .dot_limit = 225000,
 281                 .p2_slow = 10, .p2_fast = 5 },
 282         .find_pll = intel_g4x_find_best_PLL,
 283 };
 284
 285 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 286         .dot = { .min = 25000, .max = 350000 },
 287         .vco = { .min = 1760000, .max = 3510000 },
 288         .n = { .min = 1, .max = 3 },
 289         .m = { .min = 79, .max = 118 },
 290         .m1 = { .min = 12, .max = 22 },
 291         .m2 = { .min = 5, .max = 9 },
 292         .p = { .min = 28, .max = 112 },
 293         .p1 = { .min = 2, .max = 8 },
 294         .p2 = { .dot_limit = 225000,
 295                 .p2_slow = 14, .p2_fast = 14 },
 296         .find_pll = intel_g4x_find_best_PLL,
 297 };
 298
 299 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 300         .dot = { .min = 25000, .max = 350000 },
 301         .vco = { .min = 1760000, .max = 3510000 },
 302         .n = { .min = 1, .max = 3 },
 303         .m = { .min = 79, .max = 127 },
 304         .m1 = { .min = 12, .max = 22 },
 305         .m2 = { .min = 5, .max = 9 },
 306         .p = { .min = 14, .max = 56 },
 307         .p1 = { .min = 2, .max = 8 },
 308         .p2 = { .dot_limit = 225000,
 309                 .p2_slow = 7, .p2_fast = 7 },
 310         .find_pll = intel_g4x_find_best_PLL,
 311 };
 312
 313 /* LVDS 100mhz refclk limits. */
 314 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 315         .dot = { .min = 25000, .max = 350000 },
 316         .vco = { .min = 1760000, .max = 3510000 },
 317         .n = { .min = 1, .max = 2 },
 318         .m = { .min = 79, .max = 126 },
 319         .m1 = { .min = 12, .max = 22 },
 320         .m2 = { .min = 5, .max = 9 },
 321         .p = { .min = 28, .max = 112 },
 322         .p1 = { .min = 2, .max = 8 },
 323         .p2 = { .dot_limit = 225000,
 324                 .p2_slow = 14, .p2_fast = 14 },
 325         .find_pll = intel_g4x_find_best_PLL,
 326 };
 327
 328 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 329         .dot = { .min = 25000, .max = 350000 },
 330         .vco = { .min = 1760000, .max = 3510000 },
 331         .n = { .min = 1, .max = 3 },
 332         .m = { .min = 79, .max = 126 },
 333         .m1 = { .min = 12, .max = 22 },
 334         .m2 = { .min = 5, .max = 9 },
 335         .p = { .min = 14, .max = 42 },
 336         .p1 = { .min = 2, .max = 6 },
 337         .p2 = { .dot_limit = 225000,
 338                 .p2_slow = 7, .p2_fast = 7 },
 339         .find_pll = intel_g4x_find_best_PLL,
 340 };
 341
 342 static const intel_limit_t intel_limits_vlv_dac = {
 343         .dot = { .min = 25000, .max = 270000 },
 344         .vco = { .min = 4000000, .max = 6000000 },
 345         .n = { .min = 1, .max = 7 },
 346         .m = { .min = 22, .max = 450 }, /* guess */
 347         .m1 = { .min = 2, .max = 3 },
 348         .m2 = { .min = 11, .max = 156 },
 349         .p = { .min = 10, .max = 30 },
 350         .p1 = { .min = 1, .max = 3 },
 351         .p2 = { .dot_limit = 270000,
 352                 .p2_slow = 2, .p2_fast = 20 },
 353         .find_pll = intel_vlv_find_best_pll,
 354 };
 355
 356 static const intel_limit_t intel_limits_vlv_hdmi = {
 357         .dot = { .min = 25000, .max = 270000 },
 358         .vco = { .min = 4000000, .max = 6000000 },
 359         .n = { .min = 1, .max = 7 },
 360         .m = { .min = 60, .max = 300 }, /* guess */
 361         .m1 = { .min = 2, .max = 3 },
 362         .m2 = { .min = 11, .max = 156 },
 363         .p = { .min = 10, .max = 30 },
 364         .p1 = { .min = 2, .max = 3 },
 365         .p2 = { .dot_limit = 270000,
 366                 .p2_slow = 2, .p2_fast = 20 },
 367         .find_pll = intel_vlv_find_best_pll,
 368 };
 369
 370 static const intel_limit_t intel_limits_vlv_dp = {
 371         .dot = { .min = 25000, .max = 270000 },
 372         .vco = { .min = 4000000, .max = 6000000 },
 373         .n = { .min = 1, .max = 7 },
 374         .m = { .min = 22, .max = 450 },
 375         .m1 = { .min = 2, .max = 3 },
 376         .m2 = { .min = 11, .max = 156 },
 377         .p = { .min = 10, .max = 30 },
 378         .p1 = { .min = 1, .max = 3 },
 379         .p2 = { .dot_limit = 270000,
 380                 .p2_slow = 2, .p2_fast = 20 },
 381         .find_pll = intel_vlv_find_best_pll,
 382 };
 383
 384 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 385 {
 386         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
 387
 388         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 389                 DRM_ERROR("DPIO idle wait timed out\n");
 390                 return 0;
 391         }
 392
 393         I915_WRITE(DPIO_REG, reg);
 394         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 395                    DPIO_BYTE);
 396         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 397                 DRM_ERROR("DPIO read wait timed out\n");
 398                 return 0;
 399         }
 400
 401         return I915_READ(DPIO_DATA);
 402 }
 403
 404 void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val)
 405 {
 406         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
 407
 408         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 409                 DRM_ERROR("DPIO idle wait timed out\n");
 410                 return;
 411         }
 412
 413         I915_WRITE(DPIO_DATA, val);
 414         I915_WRITE(DPIO_REG, reg);
 415         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 416                    DPIO_BYTE);
 417         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 418                 DRM_ERROR("DPIO write wait timed out\n");
 419 }
 420
 421 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 422                                                 int refclk)
 423 {
 424         struct drm_device *dev = crtc->dev;
 425         const intel_limit_t *limit;
 426
 427         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 428                 if (intel_is_dual_link_lvds(dev)) {
 429                         if (refclk == 100000)
 430                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 431                         else
 432                                 limit = &intel_limits_ironlake_dual_lvds;
 433                 } else {
 434                         if (refclk == 100000)
 435                                 limit = &intel_limits_ironlake_single_lvds_100m;
 436                         else
 437                                 limit = &intel_limits_ironlake_single_lvds;
 438                 }
 439         } else
 440                 limit = &intel_limits_ironlake_dac;
 441
 442         return limit;
 443 }
 444
 445 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 446 {
 447         struct drm_device *dev = crtc->dev;
 448         const intel_limit_t *limit;
 449
 450         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 451                 if (intel_is_dual_link_lvds(dev))
 452                         limit = &intel_limits_g4x_dual_channel_lvds;
 453                 else
 454                         limit = &intel_limits_g4x_single_channel_lvds;
 455         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 456                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 457                 limit = &intel_limits_g4x_hdmi;
 458         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 459                 limit = &intel_limits_g4x_sdvo;
 460         } else /* The option is for other outputs */
 461                 limit = &intel_limits_i9xx_sdvo;
 462
 463         return limit;
 464 }
 465
 466 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 467 {
 468         struct drm_device *dev = crtc->dev;
 469         const intel_limit_t *limit;
 470
 471         if (HAS_PCH_SPLIT(dev))
 472                 limit = intel_ironlake_limit(crtc, refclk);
 473         else if (IS_G4X(dev)) {
 474                 limit = intel_g4x_limit(crtc);
 475         } else if (IS_PINEVIEW(dev)) {
 476                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 477                         limit = &intel_limits_pineview_lvds;
 478                 else
 479                         limit = &intel_limits_pineview_sdvo;
 480         } else if (IS_VALLEYVIEW(dev)) {
 481                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 482                         limit = &intel_limits_vlv_dac;
 483                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 484                         limit = &intel_limits_vlv_hdmi;
 485                 else
 486                         limit = &intel_limits_vlv_dp;
 487         } else if (!IS_GEN2(dev)) {
 488                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 489                         limit = &intel_limits_i9xx_lvds;
 490                 else
 491                         limit = &intel_limits_i9xx_sdvo;
 492         } else {
 493                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 494                         limit = &intel_limits_i8xx_lvds;
 495                 else
 496                         limit = &intel_limits_i8xx_dvo;
 497         }
 498         return limit;
 499 }
 500
 501 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 502 static void pineview_clock(int refclk, intel_clock_t *clock)
 503 {
 504         clock->m = clock->m2 + 2;
 505         clock->p = clock->p1 * clock->p2;
 506         clock->vco = refclk * clock->m / clock->n;
 507         clock->dot = clock->vco / clock->p;
 508 }
 509
 510 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 511 {
 512         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 513 }
 514
 515 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 516 {
 517         if (IS_PINEVIEW(dev)) {
 518                 pineview_clock(refclk, clock);
 519                 return;
 520         }
 521         clock->m = i9xx_dpll_compute_m(clock);
 522         clock->p = clock->p1 * clock->p2;
 523         clock->vco = refclk * clock->m / (clock->n + 2);
 524         clock->dot = clock->vco / clock->p;
 525 }
 526
 527 /**
 528  * Returns whether any output on the specified pipe is of the specified type
 529  */
 530 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 531 {
 532         struct drm_device *dev = crtc->dev;
 533         struct intel_encoder *encoder;
 534
 535         for_each_encoder_on_crtc(dev, crtc, encoder)
 536                 if (encoder->type == type)
 537                         return true;
 538
 539         return false;
 540 }
 541
 542 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 543 /**
 544  * Returns whether the given set of divisors are valid for a given refclk with
 545  * the given connectors.
 546  */
 547
 548 static bool intel_PLL_is_valid(struct drm_device *dev,
 549                                const intel_limit_t *limit,
 550                                const intel_clock_t *clock)
 551 {
 552         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 553                 INTELPllInvalid("p1 out of range\n");
 554         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 555                 INTELPllInvalid("p out of range\n");
 556         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 557                 INTELPllInvalid("m2 out of range\n");
 558         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 559                 INTELPllInvalid("m1 out of range\n");
 560         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 561                 INTELPllInvalid("m1 <= m2\n");
 562         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 563                 INTELPllInvalid("m out of range\n");
 564         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 565                 INTELPllInvalid("n out of range\n");
 566         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 567                 INTELPllInvalid("vco out of range\n");
 568         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 569          * connector, etc., rather than just a single range.
 570          */
 571         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 572                 INTELPllInvalid("dot out of range\n");
 573
 574         return true;
 575 }
 576
 577 static bool
 578 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 579                     int target, int refclk, intel_clock_t *match_clock,
 580                     intel_clock_t *best_clock)
 581
 582 {
 583         struct drm_device *dev = crtc->dev;
 584         intel_clock_t clock;
 585         int err = target;
 586
 587         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 588                 /*
 589                  * For LVDS just rely on its current settings for dual-channel.
 590                  * We haven't figured out how to reliably set up different
 591                  * single/dual channel state, if we even can.
 592                  */
 593                 if (intel_is_dual_link_lvds(dev))
 594                         clock.p2 = limit->p2.p2_fast;
 595                 else
 596                         clock.p2 = limit->p2.p2_slow;
 597         } else {
 598                 if (target < limit->p2.dot_limit)
 599                         clock.p2 = limit->p2.p2_slow;
 600                 else
 601                         clock.p2 = limit->p2.p2_fast;
 602         }
 603
 604         memset(best_clock, 0, sizeof(*best_clock));
 605
 606         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 607              clock.m1++) {
 608                 for (clock.m2 = limit->m2.min;
 609                      clock.m2 <= limit->m2.max; clock.m2++) {
 610                         /* m1 is always 0 in Pineview */
 611                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 612                                 break;
 613                         for (clock.n = limit->n.min;
 614                              clock.n <= limit->n.max; clock.n++) {
 615                                 for (clock.p1 = limit->p1.min;
 616                                         clock.p1 <= limit->p1.max; clock.p1++) {
 617                                         int this_err;
 618
 619                                         intel_clock(dev, refclk, &clock);
 620                                         if (!intel_PLL_is_valid(dev, limit,
 621                                                                 &clock))
 622                                                 continue;
 623                                         if (match_clock &&
 624                                             clock.p != match_clock->p)
 625                                                 continue;
 626
 627                                         this_err = abs(clock.dot - target);
 628                                         if (this_err < err) {
 629                                                 *best_clock = clock;
 630                                                 err = this_err;
 631                                         }
 632                                 }
 633                         }
 634                 }
 635         }
 636
 637         return (err != target);
 638 }
 639
 640 static bool
 641 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 642                         int target, int refclk, intel_clock_t *match_clock,
 643                         intel_clock_t *best_clock)
 644 {
 645         struct drm_device *dev = crtc->dev;
 646         intel_clock_t clock;
 647         int max_n;
 648         bool found;
 649         /* approximately equals target * 0.00585 */
 650         int err_most = (target >> 8) + (target >> 9);
 651         found = false;
 652
 653         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 654                 int lvds_reg;
 655
 656                 if (HAS_PCH_SPLIT(dev))
 657                         lvds_reg = PCH_LVDS;
 658                 else
 659                         lvds_reg = LVDS;
 660                 if (intel_is_dual_link_lvds(dev))
 661                         clock.p2 = limit->p2.p2_fast;
 662                 else
 663                         clock.p2 = limit->p2.p2_slow;
 664         } else {
 665                 if (target < limit->p2.dot_limit)
 666                         clock.p2 = limit->p2.p2_slow;
 667                 else
 668                         clock.p2 = limit->p2.p2_fast;
 669         }
 670
 671         memset(best_clock, 0, sizeof(*best_clock));
 672         max_n = limit->n.max;
 673         /* based on hardware requirement, prefer smaller n to precision */
 674         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 675                 /* based on hardware requirement, prefere larger m1,m2 */
 676                 for (clock.m1 = limit->m1.max;
 677                      clock.m1 >= limit->m1.min; clock.m1--) {
 678                         for (clock.m2 = limit->m2.max;
 679                              clock.m2 >= limit->m2.min; clock.m2--) {
 680                                 for (clock.p1 = limit->p1.max;
 681                                      clock.p1 >= limit->p1.min; clock.p1--) {
 682                                         int this_err;
 683
 684                                         intel_clock(dev, refclk, &clock);
 685                                         if (!intel_PLL_is_valid(dev, limit,
 686                                                                 &clock))
 687                                                 continue;
 688
 689                                         this_err = abs(clock.dot - target);
 690                                         if (this_err < err_most) {
 691                                                 *best_clock = clock;
 692                                                 err_most = this_err;
 693                                                 max_n = clock.n;
 694                                                 found = true;
 695                                         }
 696                                 }
 697                         }
 698                 }
 699         }
 700         return found;
 701 }
 702
 703 static bool
 704 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 705                         int target, int refclk, intel_clock_t *match_clock,
 706                         intel_clock_t *best_clock)
 707 {
 708         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 709         u32 m, n, fastclk;
 710         u32 updrate, minupdate, fracbits, p;
 711         unsigned long bestppm, ppm, absppm;
 712         int dotclk, flag;
 713
 714         flag = 0;
 715         dotclk = target * 1000;
 716         bestppm = 1000000;
 717         ppm = absppm = 0;
 718         fastclk = dotclk / (2*100);
 719         updrate = 0;
 720         minupdate = 19200;
 721         fracbits = 1;
 722         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 723         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 724
 725         /* based on hardware requirement, prefer smaller n to precision */
 726         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 727                 updrate = refclk / n;
 728                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 729                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 730                                 if (p2 > 10)
 731                                         p2 = p2 - 1;
 732                                 p = p1 * p2;
 733                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 734                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 735                                         m2 = (((2*(fastclk * p * n / m1 )) +
 736                                                refclk) / (2*refclk));
 737                                         m = m1 * m2;
 738                                         vco = updrate * m;
 739                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 740                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 741                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 742                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 743                                                         bestppm = 0;
 744                                                         flag = 1;
 745                                                 }
 746                                                 if (absppm < bestppm - 10) {
 747                                                         bestppm = absppm;
 748                                                         flag = 1;
 749                                                 }
 750                                                 if (flag) {
 751                                                         bestn = n;
 752                                                         bestm1 = m1;
 753                                                         bestm2 = m2;
 754                                                         bestp1 = p1;
 755                                                         bestp2 = p2;
 756                                                         flag = 0;
 757                                                 }
 758                                         }
 759                                 }
 760                         }
 761                 }
 762         }
 763         best_clock->n = bestn;
 764         best_clock->m1 = bestm1;
 765         best_clock->m2 = bestm2;
 766         best_clock->p1 = bestp1;
 767         best_clock->p2 = bestp2;
 768
 769         return true;
 770 }
 771
 772 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 773                                              enum pipe pipe)
 774 {
 775         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 776         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 777
 778         return intel_crtc->config.cpu_transcoder;
 779 }
 780
 781 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 782 {
 783         struct drm_i915_private *dev_priv = dev->dev_private;
 784         u32 frame, frame_reg = PIPEFRAME(pipe);
 785
 786         frame = I915_READ(frame_reg);
 787
 788         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 789                 DRM_DEBUG_KMS("vblank wait timed out\n");
 790 }
 791
 792 /**
 793  * intel_wait_for_vblank - wait for vblank on a given pipe
 794  * @dev: drm device
 795  * @pipe: pipe to wait for
 796  *
 797  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 798  * mode setting code.
 799  */
 800 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 801 {
 802         struct drm_i915_private *dev_priv = dev->dev_private;
 803         int pipestat_reg = PIPESTAT(pipe);
 804
 805         if (INTEL_INFO(dev)->gen >= 5) {
 806                 ironlake_wait_for_vblank(dev, pipe);
 807                 return;
 808         }
 809
 810         /* Clear existing vblank status. Note this will clear any other
 811          * sticky status fields as well.
 812          *
 813          * This races with i915_driver_irq_handler() with the result
 814          * that either function could miss a vblank event.  Here it is not
 815          * fatal, as we will either wait upon the next vblank interrupt or
 816          * timeout.  Generally speaking intel_wait_for_vblank() is only
 817          * called during modeset at which time the GPU should be idle and
 818          * should *not* be performing page flips and thus not waiting on
 819          * vblanks...
 820          * Currently, the result of us stealing a vblank from the irq
 821          * handler is that a single frame will be skipped during swapbuffers.
 822          */
 823         I915_WRITE(pipestat_reg,
 824                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 825
 826         /* Wait for vblank interrupt bit to set */
 827         if (wait_for(I915_READ(pipestat_reg) &
 828                      PIPE_VBLANK_INTERRUPT_STATUS,
 829                      50))
 830                 DRM_DEBUG_KMS("vblank wait timed out\n");
 831 }
 832
 833 /*
 834  * intel_wait_for_pipe_off - wait for pipe to turn off
 835  * @dev: drm device
 836  * @pipe: pipe to wait for
 837  *
 838  * After disabling a pipe, we can't wait for vblank in the usual way,
 839  * spinning on the vblank interrupt status bit, since we won't actually
 840  * see an interrupt when the pipe is disabled.
 841  *
 842  * On Gen4 and above:
 843  *   wait for the pipe register state bit to turn off
 844  *
 845  * Otherwise:
 846  *   wait for the display line value to settle (it usually
 847  *   ends up stopping at the start of the next frame).
 848  *
 849  */
 850 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 851 {
 852         struct drm_i915_private *dev_priv = dev->dev_private;
 853         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 854                                                                       pipe);
 855
 856         if (INTEL_INFO(dev)->gen >= 4) {
 857                 int reg = PIPECONF(cpu_transcoder);
 858
 859                 /* Wait for the Pipe State to go off */
 860                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 861                              100))
 862                         WARN(1, "pipe_off wait timed out\n");
 863         } else {
 864                 u32 last_line, line_mask;
 865                 int reg = PIPEDSL(pipe);
 866                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 867
 868                 if (IS_GEN2(dev))
 869                         line_mask = DSL_LINEMASK_GEN2;
 870                 else
 871                         line_mask = DSL_LINEMASK_GEN3;
 872
 873                 /* Wait for the display line to settle */
 874                 do {
 875                         last_line = I915_READ(reg) & line_mask;
 876                         mdelay(5);
 877                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 878                          time_after(timeout, jiffies));
 879                 if (time_after(jiffies, timeout))
 880                         WARN(1, "pipe_off wait timed out\n");
 881         }
 882 }
 883
 884 /*
 885  * ibx_digital_port_connected - is the specified port connected?
 886  * @dev_priv: i915 private structure
 887  * @port: the port to test
 888  *
 889  * Returns true if @port is connected, false otherwise.
 890  */
 891 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 892                                 struct intel_digital_port *port)
 893 {
 894         u32 bit;
 895
 896         if (HAS_PCH_IBX(dev_priv->dev)) {
 897                 switch(port->port) {
 898                 case PORT_B:
 899                         bit = SDE_PORTB_HOTPLUG;
 900                         break;
 901                 case PORT_C:
 902                         bit = SDE_PORTC_HOTPLUG;
 903                         break;
 904                 case PORT_D:
 905                         bit = SDE_PORTD_HOTPLUG;
 906                         break;
 907                 default:
 908                         return true;
 909                 }
 910         } else {
 911                 switch(port->port) {
 912                 case PORT_B:
 913                         bit = SDE_PORTB_HOTPLUG_CPT;
 914                         break;
 915                 case PORT_C:
 916                         bit = SDE_PORTC_HOTPLUG_CPT;
 917                         break;
 918                 case PORT_D:
 919                         bit = SDE_PORTD_HOTPLUG_CPT;
 920                         break;
 921                 default:
 922                         return true;
 923                 }
 924         }
 925
 926         return I915_READ(SDEISR) & bit;
 927 }
 928
 929 static const char *state_string(bool enabled)
 930 {
 931         return enabled ? "on" : "off";
 932 }
 933
 934 /* Only for pre-ILK configs */
 935 static void assert_pll(struct drm_i915_private *dev_priv,
 936                        enum pipe pipe, bool state)
 937 {
 938         int reg;
 939         u32 val;
 940         bool cur_state;
 941
 942         reg = DPLL(pipe);
 943         val = I915_READ(reg);
 944         cur_state = !!(val & DPLL_VCO_ENABLE);
 945         WARN(cur_state != state,
 946              "PLL state assertion failure (expected %s, current %s)\n",
 947              state_string(state), state_string(cur_state));
 948 }
 949 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 950 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 951
 952 /* For ILK+ */
 953 static void assert_pch_pll(struct drm_i915_private *dev_priv,
 954                            struct intel_pch_pll *pll,
 955                            struct intel_crtc *crtc,
 956                            bool state)
 957 {
 958         u32 val;
 959         bool cur_state;
 960
 961         if (HAS_PCH_LPT(dev_priv->dev)) {
 962                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 963                 return;
 964         }
 965
 966         if (WARN (!pll,
 967                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
 968                 return;
 969
 970         val = I915_READ(pll->pll_reg);
 971         cur_state = !!(val & DPLL_VCO_ENABLE);
 972         WARN(cur_state != state,
 973              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
 974              pll->pll_reg, state_string(state), state_string(cur_state), val);
 975
 976         /* Make sure the selected PLL is correctly attached to the transcoder */
 977         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
 978                 u32 pch_dpll;
 979
 980                 pch_dpll = I915_READ(PCH_DPLL_SEL);
 981                 cur_state = pll->pll_reg == _PCH_DPLL_B;
 982                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
 983                           "PLL[%d] not attached to this transcoder %c: %08x\n",
 984                           cur_state, pipe_name(crtc->pipe), pch_dpll)) {
 985                         cur_state = !!(val >> (4*crtc->pipe + 3));
 986                         WARN(cur_state != state,
 987                              "PLL[%d] not %s on this transcoder %c: %08x\n",
 988                              pll->pll_reg == _PCH_DPLL_B,
 989                              state_string(state),
 990                              pipe_name(crtc->pipe),
 991                              val);
 992                 }
 993         }
 994 }
 995 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
 996 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
 997
 998 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 999                           enum pipe pipe, bool state)
1000 {
1001         int reg;
1002         u32 val;
1003         bool cur_state;
1004         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1005                                                                       pipe);
1006
1007         if (HAS_DDI(dev_priv->dev)) {
1008                 /* DDI does not have a specific FDI_TX register */
1009                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1010                 val = I915_READ(reg);
1011                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1012         } else {
1013                 reg = FDI_TX_CTL(pipe);
1014                 val = I915_READ(reg);
1015                 cur_state = !!(val & FDI_TX_ENABLE);
1016         }
1017         WARN(cur_state != state,
1018              "FDI TX state assertion failure (expected %s, current %s)\n",
1019              state_string(state), state_string(cur_state));
1020 }
1021 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1022 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1023
1024 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1025                           enum pipe pipe, bool state)
1026 {
1027         int reg;
1028         u32 val;
1029         bool cur_state;
1030
1031         reg = FDI_RX_CTL(pipe);
1032         val = I915_READ(reg);
1033         cur_state = !!(val & FDI_RX_ENABLE);
1034         WARN(cur_state != state,
1035              "FDI RX state assertion failure (expected %s, current %s)\n",
1036              state_string(state), state_string(cur_state));
1037 }
1038 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1039 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1040
1041 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1042                                       enum pipe pipe)
1043 {
1044         int reg;
1045         u32 val;
1046
1047         /* ILK FDI PLL is always enabled */
1048         if (dev_priv->info->gen == 5)
1049                 return;
1050
1051         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1052         if (HAS_DDI(dev_priv->dev))
1053                 return;
1054
1055         reg = FDI_TX_CTL(pipe);
1056         val = I915_READ(reg);
1057         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1058 }
1059
1060 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1061                                       enum pipe pipe)
1062 {
1063         int reg;
1064         u32 val;
1065
1066         reg = FDI_RX_CTL(pipe);
1067         val = I915_READ(reg);
1068         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1069 }
1070
1071 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1072                                   enum pipe pipe)
1073 {
1074         int pp_reg, lvds_reg;
1075         u32 val;
1076         enum pipe panel_pipe = PIPE_A;
1077         bool locked = true;
1078
1079         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1080                 pp_reg = PCH_PP_CONTROL;
1081                 lvds_reg = PCH_LVDS;
1082         } else {
1083                 pp_reg = PP_CONTROL;
1084                 lvds_reg = LVDS;
1085         }
1086
1087         val = I915_READ(pp_reg);
1088         if (!(val & PANEL_POWER_ON) ||
1089             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1090                 locked = false;
1091
1092         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1093                 panel_pipe = PIPE_B;
1094
1095         WARN(panel_pipe == pipe && locked,
1096              "panel assertion failure, pipe %c regs locked\n",
1097              pipe_name(pipe));
1098 }
1099
1100 void assert_pipe(struct drm_i915_private *dev_priv,
1101                  enum pipe pipe, bool state)
1102 {
1103         int reg;
1104         u32 val;
1105         bool cur_state;
1106         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1107                                                                       pipe);
1108
1109         /* if we need the pipe A quirk it must be always on */
1110         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1111                 state = true;
1112
1113         if (!intel_using_power_well(dev_priv->dev) &&
1114             cpu_transcoder != TRANSCODER_EDP) {
1115                 cur_state = false;
1116         } else {
1117                 reg = PIPECONF(cpu_transcoder);
1118                 val = I915_READ(reg);
1119                 cur_state = !!(val & PIPECONF_ENABLE);
1120         }
1121
1122         WARN(cur_state != state,
1123              "pipe %c assertion failure (expected %s, current %s)\n",
1124              pipe_name(pipe), state_string(state), state_string(cur_state));
1125 }
1126
1127 static void assert_plane(struct drm_i915_private *dev_priv,
1128                          enum plane plane, bool state)
1129 {
1130         int reg;
1131         u32 val;
1132         bool cur_state;
1133
1134         reg = DSPCNTR(plane);
1135         val = I915_READ(reg);
1136         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1137         WARN(cur_state != state,
1138              "plane %c assertion failure (expected %s, current %s)\n",
1139              plane_name(plane), state_string(state), state_string(cur_state));
1140 }
1141
1142 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1143 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1144
1145 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1146                                    enum pipe pipe)
1147 {
1148         int reg, i;
1149         u32 val;
1150         int cur_pipe;
1151
1152         /* Planes are fixed to pipes on ILK+ */
1153         if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
1154                 reg = DSPCNTR(pipe);
1155                 val = I915_READ(reg);
1156                 WARN((val & DISPLAY_PLANE_ENABLE),
1157                      "plane %c assertion failure, should be disabled but not\n",
1158                      plane_name(pipe));
1159                 return;
1160         }
1161
1162         /* Need to check both planes against the pipe */
1163         for (i = 0; i < 2; i++) {
1164                 reg = DSPCNTR(i);
1165                 val = I915_READ(reg);
1166                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1167                         DISPPLANE_SEL_PIPE_SHIFT;
1168                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1169                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1170                      plane_name(i), pipe_name(pipe));
1171         }
1172 }
1173
1174 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1175                                     enum pipe pipe)
1176 {
1177         int reg, i;
1178         u32 val;
1179
1180         if (!IS_VALLEYVIEW(dev_priv->dev))
1181                 return;
1182
1183         /* Need to check both planes against the pipe */
1184         for (i = 0; i < dev_priv->num_plane; i++) {
1185                 reg = SPCNTR(pipe, i);
1186                 val = I915_READ(reg);
1187                 WARN((val & SP_ENABLE),
1188                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1189                      sprite_name(pipe, i), pipe_name(pipe));
1190         }
1191 }
1192
1193 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1194 {
1195         u32 val;
1196         bool enabled;
1197
1198         if (HAS_PCH_LPT(dev_priv->dev)) {
1199                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1200                 return;
1201         }
1202
1203         val = I915_READ(PCH_DREF_CONTROL);
1204         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1205                             DREF_SUPERSPREAD_SOURCE_MASK));
1206         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1207 }
1208
1209 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1210                                        enum pipe pipe)
1211 {
1212         int reg;
1213         u32 val;
1214         bool enabled;
1215
1216         reg = TRANSCONF(pipe);
1217         val = I915_READ(reg);
1218         enabled = !!(val & TRANS_ENABLE);
1219         WARN(enabled,
1220              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1221              pipe_name(pipe));
1222 }
1223
1224 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1225                             enum pipe pipe, u32 port_sel, u32 val)
1226 {
1227         if ((val & DP_PORT_EN) == 0)
1228                 return false;
1229
1230         if (HAS_PCH_CPT(dev_priv->dev)) {
1231                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1232                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1233                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1234                         return false;
1235         } else {
1236                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1237                         return false;
1238         }
1239         return true;
1240 }
1241
1242 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1243                               enum pipe pipe, u32 val)
1244 {
1245         if ((val & SDVO_ENABLE) == 0)
1246                 return false;
1247
1248         if (HAS_PCH_CPT(dev_priv->dev)) {
1249                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1250                         return false;
1251         } else {
1252                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1253                         return false;
1254         }
1255         return true;
1256 }
1257
1258 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1259                               enum pipe pipe, u32 val)
1260 {
1261         if ((val & LVDS_PORT_EN) == 0)
1262                 return false;
1263
1264         if (HAS_PCH_CPT(dev_priv->dev)) {
1265                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1266                         return false;
1267         } else {
1268                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1269                         return false;
1270         }
1271         return true;
1272 }
1273
1274 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1275                               enum pipe pipe, u32 val)
1276 {
1277         if ((val & ADPA_DAC_ENABLE) == 0)
1278                 return false;
1279         if (HAS_PCH_CPT(dev_priv->dev)) {
1280                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1281                         return false;
1282         } else {
1283                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1284                         return false;
1285         }
1286         return true;
1287 }
1288
1289 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1290                                    enum pipe pipe, int reg, u32 port_sel)
1291 {
1292         u32 val = I915_READ(reg);
1293         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1294              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1295              reg, pipe_name(pipe));
1296
1297         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1298              && (val & DP_PIPEB_SELECT),
1299              "IBX PCH dp port still using transcoder B\n");
1300 }
1301
1302 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1303                                      enum pipe pipe, int reg)
1304 {
1305         u32 val = I915_READ(reg);
1306         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1307              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1308              reg, pipe_name(pipe));
1309
1310         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1311              && (val & SDVO_PIPE_B_SELECT),
1312              "IBX PCH hdmi port still using transcoder B\n");
1313 }
1314
1315 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1316                                       enum pipe pipe)
1317 {
1318         int reg;
1319         u32 val;
1320
1321         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1322         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1323         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1324
1325         reg = PCH_ADPA;
1326         val = I915_READ(reg);
1327         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1328              "PCH VGA enabled on transcoder %c, should be disabled\n",
1329              pipe_name(pipe));
1330
1331         reg = PCH_LVDS;
1332         val = I915_READ(reg);
1333         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1334              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1335              pipe_name(pipe));
1336
1337         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1338         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1339         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1340 }
1341
1342 /**
1343  * intel_enable_pll - enable a PLL
1344  * @dev_priv: i915 private structure
1345  * @pipe: pipe PLL to enable
1346  *
1347  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1348  * make sure the PLL reg is writable first though, since the panel write
1349  * protect mechanism may be enabled.
1350  *
1351  * Note!  This is for pre-ILK only.
1352  *
1353  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1354  */
1355 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1356 {
1357         int reg;
1358         u32 val;
1359
1360         assert_pipe_disabled(dev_priv, pipe);
1361
1362         /* No really, not for ILK+ */
1363         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1364
1365         /* PLL is protected by panel, make sure we can write it */
1366         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1367                 assert_panel_unlocked(dev_priv, pipe);
1368
1369         reg = DPLL(pipe);
1370         val = I915_READ(reg);
1371         val |= DPLL_VCO_ENABLE;
1372
1373         /* We do this three times for luck */
1374         I915_WRITE(reg, val);
1375         POSTING_READ(reg);
1376         udelay(150); /* wait for warmup */
1377         I915_WRITE(reg, val);
1378         POSTING_READ(reg);
1379         udelay(150); /* wait for warmup */
1380         I915_WRITE(reg, val);
1381         POSTING_READ(reg);
1382         udelay(150); /* wait for warmup */
1383 }
1384
1385 /**
1386  * intel_disable_pll - disable a PLL
1387  * @dev_priv: i915 private structure
1388  * @pipe: pipe PLL to disable
1389  *
1390  * Disable the PLL for @pipe, making sure the pipe is off first.
1391  *
1392  * Note!  This is for pre-ILK only.
1393  */
1394 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1395 {
1396         int reg;
1397         u32 val;
1398
1399         /* Don't disable pipe A or pipe A PLLs if needed */
1400         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1401                 return;
1402
1403         /* Make sure the pipe isn't still relying on us */
1404         assert_pipe_disabled(dev_priv, pipe);
1405
1406         reg = DPLL(pipe);
1407         val = I915_READ(reg);
1408         val &= ~DPLL_VCO_ENABLE;
1409         I915_WRITE(reg, val);
1410         POSTING_READ(reg);
1411 }
1412
1413 /* SBI access */
1414 static void
1415 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1416                 enum intel_sbi_destination destination)
1417 {
1418         u32 tmp;
1419
1420         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1421
1422         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1423                                 100)) {
1424                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1425                 return;
1426         }
1427
1428         I915_WRITE(SBI_ADDR, (reg << 16));
1429         I915_WRITE(SBI_DATA, value);
1430
1431         if (destination == SBI_ICLK)
1432                 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1433         else
1434                 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1435         I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
1436
1437         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1438                                 100)) {
1439                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1440                 return;
1441         }
1442 }
1443
1444 static u32
1445 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1446                enum intel_sbi_destination destination)
1447 {
1448         u32 value = 0;
1449         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1450
1451         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1452                                 100)) {
1453                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1454                 return 0;
1455         }
1456
1457         I915_WRITE(SBI_ADDR, (reg << 16));
1458
1459         if (destination == SBI_ICLK)
1460                 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1461         else
1462                 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1463         I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
1464
1465         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1466                                 100)) {
1467                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1468                 return 0;
1469         }
1470
1471         return I915_READ(SBI_DATA);
1472 }
1473
1474 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1475 {
1476         u32 port_mask;
1477
1478         if (!port)
1479                 port_mask = DPLL_PORTB_READY_MASK;
1480         else
1481                 port_mask = DPLL_PORTC_READY_MASK;
1482
1483         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1484                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1485                      'B' + port, I915_READ(DPLL(0)));
1486 }
1487
1488 /**
1489  * ironlake_enable_pch_pll - enable PCH PLL
1490  * @dev_priv: i915 private structure
1491  * @pipe: pipe PLL to enable
1492  *
1493  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1494  * drives the transcoder clock.
1495  */
1496 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1497 {
1498         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1499         struct intel_pch_pll *pll;
1500         int reg;
1501         u32 val;
1502
1503         /* PCH PLLs only available on ILK, SNB and IVB */
1504         BUG_ON(dev_priv->info->gen < 5);
1505         pll = intel_crtc->pch_pll;
1506         if (pll == NULL)
1507                 return;
1508
1509         if (WARN_ON(pll->refcount == 0))
1510                 return;
1511
1512         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1513                       pll->pll_reg, pll->active, pll->on,
1514                       intel_crtc->base.base.id);
1515
1516         /* PCH refclock must be enabled first */
1517         assert_pch_refclk_enabled(dev_priv);
1518
1519         if (pll->active++ && pll->on) {
1520                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1521                 return;
1522         }
1523
1524         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1525
1526         reg = pll->pll_reg;
1527         val = I915_READ(reg);
1528         val |= DPLL_VCO_ENABLE;
1529         I915_WRITE(reg, val);
1530         POSTING_READ(reg);
1531         udelay(200);
1532
1533         pll->on = true;
1534 }
1535
1536 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1537 {
1538         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1539         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1540         int reg;
1541         u32 val;
1542
1543         /* PCH only available on ILK+ */
1544         BUG_ON(dev_priv->info->gen < 5);
1545         if (pll == NULL)
1546                return;
1547
1548         if (WARN_ON(pll->refcount == 0))
1549                 return;
1550
1551         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1552                       pll->pll_reg, pll->active, pll->on,
1553                       intel_crtc->base.base.id);
1554
1555         if (WARN_ON(pll->active == 0)) {
1556                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1557                 return;
1558         }
1559
1560         if (--pll->active) {
1561                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1562                 return;
1563         }
1564
1565         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1566
1567         /* Make sure transcoder isn't still depending on us */
1568         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1569
1570         reg = pll->pll_reg;
1571         val = I915_READ(reg);
1572         val &= ~DPLL_VCO_ENABLE;
1573         I915_WRITE(reg, val);
1574         POSTING_READ(reg);
1575         udelay(200);
1576
1577         pll->on = false;
1578 }
1579
1580 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1581                                            enum pipe pipe)
1582 {
1583         struct drm_device *dev = dev_priv->dev;
1584         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1585         uint32_t reg, val, pipeconf_val;
1586
1587         /* PCH only available on ILK+ */
1588         BUG_ON(dev_priv->info->gen < 5);
1589
1590         /* Make sure PCH DPLL is enabled */
1591         assert_pch_pll_enabled(dev_priv,
1592                                to_intel_crtc(crtc)->pch_pll,
1593                                to_intel_crtc(crtc));
1594
1595         /* FDI must be feeding us bits for PCH ports */
1596         assert_fdi_tx_enabled(dev_priv, pipe);
1597         assert_fdi_rx_enabled(dev_priv, pipe);
1598
1599         if (HAS_PCH_CPT(dev)) {
1600                 /* Workaround: Set the timing override bit before enabling the
1601                  * pch transcoder. */
1602                 reg = TRANS_CHICKEN2(pipe);
1603                 val = I915_READ(reg);
1604                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1605                 I915_WRITE(reg, val);
1606         }
1607
1608         reg = TRANSCONF(pipe);
1609         val = I915_READ(reg);
1610         pipeconf_val = I915_READ(PIPECONF(pipe));
1611
1612         if (HAS_PCH_IBX(dev_priv->dev)) {
1613                 /*
1614                  * make the BPC in transcoder be consistent with
1615                  * that in pipeconf reg.
1616                  */
1617                 val &= ~PIPECONF_BPC_MASK;
1618                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1619         }
1620
1621         val &= ~TRANS_INTERLACE_MASK;
1622         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1623                 if (HAS_PCH_IBX(dev_priv->dev) &&
1624                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1625                         val |= TRANS_LEGACY_INTERLACED_ILK;
1626                 else
1627                         val |= TRANS_INTERLACED;
1628         else
1629                 val |= TRANS_PROGRESSIVE;
1630
1631         I915_WRITE(reg, val | TRANS_ENABLE);
1632         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1633                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1634 }
1635
1636 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1637                                       enum transcoder cpu_transcoder)
1638 {
1639         u32 val, pipeconf_val;
1640
1641         /* PCH only available on ILK+ */
1642         BUG_ON(dev_priv->info->gen < 5);
1643
1644         /* FDI must be feeding us bits for PCH ports */
1645         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1646         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1647
1648         /* Workaround: set timing override bit. */
1649         val = I915_READ(_TRANSA_CHICKEN2);
1650         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1651         I915_WRITE(_TRANSA_CHICKEN2, val);
1652
1653         val = TRANS_ENABLE;
1654         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1655
1656         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1657             PIPECONF_INTERLACED_ILK)
1658                 val |= TRANS_INTERLACED;
1659         else
1660                 val |= TRANS_PROGRESSIVE;
1661
1662         I915_WRITE(TRANSCONF(TRANSCODER_A), val);
1663         if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1664                 DRM_ERROR("Failed to enable PCH transcoder\n");
1665 }
1666
1667 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1668                                             enum pipe pipe)
1669 {
1670         struct drm_device *dev = dev_priv->dev;
1671         uint32_t reg, val;
1672
1673         /* FDI relies on the transcoder */
1674         assert_fdi_tx_disabled(dev_priv, pipe);
1675         assert_fdi_rx_disabled(dev_priv, pipe);
1676
1677         /* Ports must be off as well */
1678         assert_pch_ports_disabled(dev_priv, pipe);
1679
1680         reg = TRANSCONF(pipe);
1681         val = I915_READ(reg);
1682         val &= ~TRANS_ENABLE;
1683         I915_WRITE(reg, val);
1684         /* wait for PCH transcoder off, transcoder state */
1685         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1686                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1687
1688         if (!HAS_PCH_IBX(dev)) {
1689                 /* Workaround: Clear the timing override chicken bit again. */
1690                 reg = TRANS_CHICKEN2(pipe);
1691                 val = I915_READ(reg);
1692                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1693                 I915_WRITE(reg, val);
1694         }
1695 }
1696
1697 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1698 {
1699         u32 val;
1700
1701         val = I915_READ(_TRANSACONF);
1702         val &= ~TRANS_ENABLE;
1703         I915_WRITE(_TRANSACONF, val);
1704         /* wait for PCH transcoder off, transcoder state */
1705         if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1706                 DRM_ERROR("Failed to disable PCH transcoder\n");
1707
1708         /* Workaround: clear timing override bit. */
1709         val = I915_READ(_TRANSA_CHICKEN2);
1710         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1711         I915_WRITE(_TRANSA_CHICKEN2, val);
1712 }
1713
1714 /**
1715  * intel_enable_pipe - enable a pipe, asserting requirements
1716  * @dev_priv: i915 private structure
1717  * @pipe: pipe to enable
1718  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1719  *
1720  * Enable @pipe, making sure that various hardware specific requirements
1721  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1722  *
1723  * @pipe should be %PIPE_A or %PIPE_B.
1724  *
1725  * Will wait until the pipe is actually running (i.e. first vblank) before
1726  * returning.
1727  */
1728 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1729                               bool pch_port)
1730 {
1731         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1732                                                                       pipe);
1733         enum pipe pch_transcoder;
1734         int reg;
1735         u32 val;
1736
1737         assert_planes_disabled(dev_priv, pipe);
1738         assert_sprites_disabled(dev_priv, pipe);
1739
1740         if (HAS_PCH_LPT(dev_priv->dev))
1741                 pch_transcoder = TRANSCODER_A;
1742         else
1743                 pch_transcoder = pipe;
1744
1745         /*
1746          * A pipe without a PLL won't actually be able to drive bits from
1747          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1748          * need the check.
1749          */
1750         if (!HAS_PCH_SPLIT(dev_priv->dev))
1751                 assert_pll_enabled(dev_priv, pipe);
1752         else {
1753                 if (pch_port) {
1754                         /* if driving the PCH, we need FDI enabled */
1755                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1756                         assert_fdi_tx_pll_enabled(dev_priv,
1757                                                   (enum pipe) cpu_transcoder);
1758                 }
1759                 /* FIXME: assert CPU port conditions for SNB+ */
1760         }
1761
1762         reg = PIPECONF(cpu_transcoder);
1763         val = I915_READ(reg);
1764         if (val & PIPECONF_ENABLE)
1765                 return;
1766
1767         I915_WRITE(reg, val | PIPECONF_ENABLE);
1768         intel_wait_for_vblank(dev_priv->dev, pipe);
1769 }
1770
1771 /**
1772  * intel_disable_pipe - disable a pipe, asserting requirements
1773  * @dev_priv: i915 private structure
1774  * @pipe: pipe to disable
1775  *
1776  * Disable @pipe, making sure that various hardware specific requirements
1777  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1778  *
1779  * @pipe should be %PIPE_A or %PIPE_B.
1780  *
1781  * Will wait until the pipe has shut down before returning.
1782  */
1783 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1784                                enum pipe pipe)
1785 {
1786         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1787                                                                       pipe);
1788         int reg;
1789         u32 val;
1790
1791         /*
1792          * Make sure planes won't keep trying to pump pixels to us,
1793          * or we might hang the display.
1794          */
1795         assert_planes_disabled(dev_priv, pipe);
1796         assert_sprites_disabled(dev_priv, pipe);
1797
1798         /* Don't disable pipe A or pipe A PLLs if needed */
1799         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1800                 return;
1801
1802         reg = PIPECONF(cpu_transcoder);
1803         val = I915_READ(reg);
1804         if ((val & PIPECONF_ENABLE) == 0)
1805                 return;
1806
1807         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1808         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1809 }
1810
1811 /*
1812  * Plane regs are double buffered, going from enabled->disabled needs a
1813  * trigger in order to latch.  The display address reg provides this.
1814  */
1815 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1816                                       enum plane plane)
1817 {
1818         if (dev_priv->info->gen >= 4)
1819                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1820         else
1821                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1822 }
1823
1824 /**
1825  * intel_enable_plane - enable a display plane on a given pipe
1826  * @dev_priv: i915 private structure
1827  * @plane: plane to enable
1828  * @pipe: pipe being fed
1829  *
1830  * Enable @plane on @pipe, making sure that @pipe is running first.
1831  */
1832 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1833                                enum plane plane, enum pipe pipe)
1834 {
1835         int reg;
1836         u32 val;
1837
1838         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1839         assert_pipe_enabled(dev_priv, pipe);
1840
1841         reg = DSPCNTR(plane);
1842         val = I915_READ(reg);
1843         if (val & DISPLAY_PLANE_ENABLE)
1844                 return;
1845
1846         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1847         intel_flush_display_plane(dev_priv, plane);
1848         intel_wait_for_vblank(dev_priv->dev, pipe);
1849 }
1850
1851 /**
1852  * intel_disable_plane - disable a display plane
1853  * @dev_priv: i915 private structure
1854  * @plane: plane to disable
1855  * @pipe: pipe consuming the data
1856  *
1857  * Disable @plane; should be an independent operation.
1858  */
1859 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1860                                 enum plane plane, enum pipe pipe)
1861 {
1862         int reg;
1863         u32 val;
1864
1865         reg = DSPCNTR(plane);
1866         val = I915_READ(reg);
1867         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1868                 return;
1869
1870         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1871         intel_flush_display_plane(dev_priv, plane);
1872         intel_wait_for_vblank(dev_priv->dev, pipe);
1873 }
1874
1875 static bool need_vtd_wa(struct drm_device *dev)
1876 {
1877 #ifdef CONFIG_INTEL_IOMMU
1878         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1879                 return true;
1880 #endif
1881         return false;
1882 }
1883
1884 int
1885 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1886                            struct drm_i915_gem_object *obj,
1887                            struct intel_ring_buffer *pipelined)
1888 {
1889         struct drm_i915_private *dev_priv = dev->dev_private;
1890         u32 alignment;
1891         int ret;
1892
1893         switch (obj->tiling_mode) {
1894         case I915_TILING_NONE:
1895                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1896                         alignment = 128 * 1024;
1897                 else if (INTEL_INFO(dev)->gen >= 4)
1898                         alignment = 4 * 1024;
1899                 else
1900                         alignment = 64 * 1024;
1901                 break;
1902         case I915_TILING_X:
1903                 /* pin() will align the object as required by fence */
1904                 alignment = 0;
1905                 break;
1906         case I915_TILING_Y:
1907                 /* Despite that we check this in framebuffer_init userspace can
1908                  * screw us over and change the tiling after the fact. Only
1909                  * pinned buffers can't change their tiling. */
1910                 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1911                 return -EINVAL;
1912         default:
1913                 BUG();
1914         }
1915
1916         /* Note that the w/a also requires 64 PTE of padding following the
1917          * bo. We currently fill all unused PTE with the shadow page and so
1918          * we should always have valid PTE following the scanout preventing
1919          * the VT-d warning.
1920          */
1921         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1922                 alignment = 256 * 1024;
1923
1924         dev_priv->mm.interruptible = false;
1925         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1926         if (ret)
1927                 goto err_interruptible;
1928
1929         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1930          * fence, whereas 965+ only requires a fence if using
1931          * framebuffer compression.  For simplicity, we always install
1932          * a fence as the cost is not that onerous.
1933          */
1934         ret = i915_gem_object_get_fence(obj);
1935         if (ret)
1936                 goto err_unpin;
1937
1938         i915_gem_object_pin_fence(obj);
1939
1940         dev_priv->mm.interruptible = true;
1941         return 0;
1942
1943 err_unpin:
1944         i915_gem_object_unpin(obj);
1945 err_interruptible:
1946         dev_priv->mm.interruptible = true;
1947         return ret;
1948 }
1949
1950 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1951 {
1952         i915_gem_object_unpin_fence(obj);
1953         i915_gem_object_unpin(obj);
1954 }
1955
1956 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1957  * is assumed to be a power-of-two. */
1958 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1959                                              unsigned int tiling_mode,
1960                                              unsigned int cpp,
1961                                              unsigned int pitch)
1962 {
1963         if (tiling_mode != I915_TILING_NONE) {
1964                 unsigned int tile_rows, tiles;
1965
1966                 tile_rows = *y / 8;
1967                 *y %= 8;
1968
1969                 tiles = *x / (512/cpp);
1970                 *x %= 512/cpp;
1971
1972                 return tile_rows * pitch * 8 + tiles * 4096;
1973         } else {
1974                 unsigned int offset;
1975
1976                 offset = *y * pitch + *x * cpp;
1977                 *y = 0;
1978                 *x = (offset & 4095) / cpp;
1979                 return offset & -4096;
1980         }
1981 }
1982
1983 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1984                              int x, int y)
1985 {
1986         struct drm_device *dev = crtc->dev;
1987         struct drm_i915_private *dev_priv = dev->dev_private;
1988         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1989         struct intel_framebuffer *intel_fb;
1990         struct drm_i915_gem_object *obj;
1991         int plane = intel_crtc->plane;
1992         unsigned long linear_offset;
1993         u32 dspcntr;
1994         u32 reg;
1995
1996         switch (plane) {
1997         case 0:
1998         case 1:
1999                 break;
2000         default:
2001                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2002                 return -EINVAL;
2003         }
2004
2005         intel_fb = to_intel_framebuffer(fb);
2006         obj = intel_fb->obj;
2007
2008         reg = DSPCNTR(plane);
2009         dspcntr = I915_READ(reg);
2010         /* Mask out pixel format bits in case we change it */
2011         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2012         switch (fb->pixel_format) {
2013         case DRM_FORMAT_C8:
2014                 dspcntr |= DISPPLANE_8BPP;
2015                 break;
2016         case DRM_FORMAT_XRGB1555:
2017         case DRM_FORMAT_ARGB1555:
2018                 dspcntr |= DISPPLANE_BGRX555;
2019                 break;
2020         case DRM_FORMAT_RGB565:
2021                 dspcntr |= DISPPLANE_BGRX565;
2022                 break;
2023         case DRM_FORMAT_XRGB8888:
2024         case DRM_FORMAT_ARGB8888:
2025                 dspcntr |= DISPPLANE_BGRX888;
2026                 break;
2027         case DRM_FORMAT_XBGR8888:
2028         case DRM_FORMAT_ABGR8888:
2029                 dspcntr |= DISPPLANE_RGBX888;
2030                 break;
2031         case DRM_FORMAT_XRGB2101010:
2032         case DRM_FORMAT_ARGB2101010:
2033                 dspcntr |= DISPPLANE_BGRX101010;
2034                 break;
2035         case DRM_FORMAT_XBGR2101010:
2036         case DRM_FORMAT_ABGR2101010:
2037                 dspcntr |= DISPPLANE_RGBX101010;
2038                 break;
2039         default:
2040                 BUG();
2041         }
2042
2043         if (INTEL_INFO(dev)->gen >= 4) {
2044                 if (obj->tiling_mode != I915_TILING_NONE)
2045                         dspcntr |= DISPPLANE_TILED;
2046                 else
2047                         dspcntr &= ~DISPPLANE_TILED;
2048         }
2049
2050         I915_WRITE(reg, dspcntr);
2051
2052         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2053
2054         if (INTEL_INFO(dev)->gen >= 4) {
2055                 intel_crtc->dspaddr_offset =
2056                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2057                                                        fb->bits_per_pixel / 8,
2058                                                        fb->pitches[0]);
2059                 linear_offset -= intel_crtc->dspaddr_offset;
2060         } else {
2061                 intel_crtc->dspaddr_offset = linear_offset;
2062         }
2063
2064         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2065                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2066         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2067         if (INTEL_INFO(dev)->gen >= 4) {
2068                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2069                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
2070                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2071                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2072         } else
2073                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2074         POSTING_READ(reg);
2075
2076         return 0;
2077 }
2078
2079 static int ironlake_update_plane(struct drm_crtc *crtc,
2080                                  struct drm_framebuffer *fb, int x, int y)
2081 {
2082         struct drm_device *dev = crtc->dev;
2083         struct drm_i915_private *dev_priv = dev->dev_private;
2084         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2085         struct intel_framebuffer *intel_fb;
2086         struct drm_i915_gem_object *obj;
2087         int plane = intel_crtc->plane;
2088         unsigned long linear_offset;
2089         u32 dspcntr;
2090         u32 reg;
2091
2092         switch (plane) {
2093         case 0:
2094         case 1:
2095         case 2:
2096                 break;
2097         default:
2098                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2099                 return -EINVAL;
2100         }
2101
2102         intel_fb = to_intel_framebuffer(fb);
2103         obj = intel_fb->obj;
2104
2105         reg = DSPCNTR(plane);
2106         dspcntr = I915_READ(reg);
2107         /* Mask out pixel format bits in case we change it */
2108         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2109         switch (fb->pixel_format) {
2110         case DRM_FORMAT_C8:
2111                 dspcntr |= DISPPLANE_8BPP;
2112                 break;
2113         case DRM_FORMAT_RGB565:
2114                 dspcntr |= DISPPLANE_BGRX565;
2115                 break;
2116         case DRM_FORMAT_XRGB8888:
2117         case DRM_FORMAT_ARGB8888:
2118                 dspcntr |= DISPPLANE_BGRX888;
2119                 break;
2120         case DRM_FORMAT_XBGR8888:
2121         case DRM_FORMAT_ABGR8888:
2122                 dspcntr |= DISPPLANE_RGBX888;
2123                 break;
2124         case DRM_FORMAT_XRGB2101010:
2125         case DRM_FORMAT_ARGB2101010:
2126                 dspcntr |= DISPPLANE_BGRX101010;
2127                 break;
2128         case DRM_FORMAT_XBGR2101010:
2129         case DRM_FORMAT_ABGR2101010:
2130                 dspcntr |= DISPPLANE_RGBX101010;
2131                 break;
2132         default:
2133                 BUG();
2134         }
2135
2136         if (obj->tiling_mode != I915_TILING_NONE)
2137                 dspcntr |= DISPPLANE_TILED;
2138         else
2139                 dspcntr &= ~DISPPLANE_TILED;
2140
2141         /* must disable */
2142         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2143
2144         I915_WRITE(reg, dspcntr);
2145
2146         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2147         intel_crtc->dspaddr_offset =
2148                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2149                                                fb->bits_per_pixel / 8,
2150                                                fb->pitches[0]);
2151         linear_offset -= intel_crtc->dspaddr_offset;
2152
2153         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2154                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2155         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2156         I915_MODIFY_DISPBASE(DSPSURF(plane),
2157                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2158         if (IS_HASWELL(dev)) {
2159                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2160         } else {
2161                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2162                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2163         }
2164         POSTING_READ(reg);
2165
2166         return 0;
2167 }
2168
2169 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2170 static int
2171 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2172                            int x, int y, enum mode_set_atomic state)
2173 {
2174         struct drm_device *dev = crtc->dev;
2175         struct drm_i915_private *dev_priv = dev->dev_private;
2176
2177         if (dev_priv->display.disable_fbc)
2178                 dev_priv->display.disable_fbc(dev);
2179         intel_increase_pllclock(crtc);
2180
2181         return dev_priv->display.update_plane(crtc, fb, x, y);
2182 }
2183
2184 void intel_display_handle_reset(struct drm_device *dev)
2185 {
2186         struct drm_i915_private *dev_priv = dev->dev_private;
2187         struct drm_crtc *crtc;
2188
2189         /*
2190          * Flips in the rings have been nuked by the reset,
2191          * so complete all pending flips so that user space
2192          * will get its events and not get stuck.
2193          *
2194          * Also update the base address of all primary
2195          * planes to the the last fb to make sure we're
2196          * showing the correct fb after a reset.
2197          *
2198          * Need to make two loops over the crtcs so that we
2199          * don't try to grab a crtc mutex before the
2200          * pending_flip_queue really got woken up.
2201          */
2202
2203         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2204                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2205                 enum plane plane = intel_crtc->plane;
2206
2207                 intel_prepare_page_flip(dev, plane);
2208                 intel_finish_page_flip_plane(dev, plane);
2209         }
2210
2211         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2212                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2213
2214                 mutex_lock(&crtc->mutex);
2215                 if (intel_crtc->active)
2216                         dev_priv->display.update_plane(crtc, crtc->fb,
2217                                                        crtc->x, crtc->y);
2218                 mutex_unlock(&crtc->mutex);
2219         }
2220 }
2221
2222 static int
2223 intel_finish_fb(struct drm_framebuffer *old_fb)
2224 {
2225         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2226         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2227         bool was_interruptible = dev_priv->mm.interruptible;
2228         int ret;
2229
2230         /* Big Hammer, we also need to ensure that any pending
2231          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2232          * current scanout is retired before unpinning the old
2233          * framebuffer.
2234          *
2235          * This should only fail upon a hung GPU, in which case we
2236          * can safely continue.
2237          */
2238         dev_priv->mm.interruptible = false;
2239         ret = i915_gem_object_finish_gpu(obj);
2240         dev_priv->mm.interruptible = was_interruptible;
2241
2242         return ret;
2243 }
2244
2245 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2246 {
2247         struct drm_device *dev = crtc->dev;
2248         struct drm_i915_master_private *master_priv;
2249         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2250
2251         if (!dev->primary->master)
2252                 return;
2253
2254         master_priv = dev->primary->master->driver_priv;
2255         if (!master_priv->sarea_priv)
2256                 return;
2257
2258         switch (intel_crtc->pipe) {
2259         case 0:
2260                 master_priv->sarea_priv->pipeA_x = x;
2261                 master_priv->sarea_priv->pipeA_y = y;
2262                 break;
2263         case 1:
2264                 master_priv->sarea_priv->pipeB_x = x;
2265                 master_priv->sarea_priv->pipeB_y = y;
2266                 break;
2267         default:
2268                 break;
2269         }
2270 }
2271
2272 static int
2273 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2274                     struct drm_framebuffer *fb)
2275 {
2276         struct drm_device *dev = crtc->dev;
2277         struct drm_i915_private *dev_priv = dev->dev_private;
2278         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2279         struct drm_framebuffer *old_fb;
2280         int ret;
2281
2282         /* no fb bound */
2283         if (!fb) {
2284                 DRM_ERROR("No FB bound\n");
2285                 return 0;
2286         }
2287
2288         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2289                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2290                           plane_name(intel_crtc->plane),
2291                           INTEL_INFO(dev)->num_pipes);
2292                 return -EINVAL;
2293         }
2294
2295         mutex_lock(&dev->struct_mutex);
2296         ret = intel_pin_and_fence_fb_obj(dev,
2297                                          to_intel_framebuffer(fb)->obj,
2298                                          NULL);
2299         if (ret != 0) {
2300                 mutex_unlock(&dev->struct_mutex);
2301                 DRM_ERROR("pin & fence failed\n");
2302                 return ret;
2303         }
2304
2305         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2306         if (ret) {
2307                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2308                 mutex_unlock(&dev->struct_mutex);
2309                 DRM_ERROR("failed to update base address\n");
2310                 return ret;
2311         }
2312
2313         old_fb = crtc->fb;
2314         crtc->fb = fb;
2315         crtc->x = x;
2316         crtc->y = y;
2317
2318         if (old_fb) {
2319                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2320                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2321         }
2322
2323         intel_update_fbc(dev);
2324         mutex_unlock(&dev->struct_mutex);
2325
2326         intel_crtc_update_sarea_pos(crtc, x, y);
2327
2328         return 0;
2329 }
2330
2331 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2332 {
2333         struct drm_device *dev = crtc->dev;
2334         struct drm_i915_private *dev_priv = dev->dev_private;
2335         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2336         int pipe = intel_crtc->pipe;
2337         u32 reg, temp;
2338
2339         /* enable normal train */
2340         reg = FDI_TX_CTL(pipe);
2341         temp = I915_READ(reg);
2342         if (IS_IVYBRIDGE(dev)) {
2343                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2344                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2345         } else {
2346                 temp &= ~FDI_LINK_TRAIN_NONE;
2347                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2348         }
2349         I915_WRITE(reg, temp);
2350
2351         reg = FDI_RX_CTL(pipe);
2352         temp = I915_READ(reg);
2353         if (HAS_PCH_CPT(dev)) {
2354                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2355                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2356         } else {
2357                 temp &= ~FDI_LINK_TRAIN_NONE;
2358                 temp |= FDI_LINK_TRAIN_NONE;
2359         }
2360         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2361
2362         /* wait one idle pattern time */
2363         POSTING_READ(reg);
2364         udelay(1000);
2365
2366         /* IVB wants error correction enabled */
2367         if (IS_IVYBRIDGE(dev))
2368                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2369                            FDI_FE_ERRC_ENABLE);
2370 }
2371
2372 static void ivb_modeset_global_resources(struct drm_device *dev)
2373 {
2374         struct drm_i915_private *dev_priv = dev->dev_private;
2375         struct intel_crtc *pipe_B_crtc =
2376                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2377         struct intel_crtc *pipe_C_crtc =
2378                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2379         uint32_t temp;
2380
2381         /* When everything is off disable fdi C so that we could enable fdi B
2382          * with all lanes. XXX: This misses the case where a pipe is not using
2383          * any pch resources and so doesn't need any fdi lanes. */
2384         if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2385                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2386                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2387
2388                 temp = I915_READ(SOUTH_CHICKEN1);
2389                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2390                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2391                 I915_WRITE(SOUTH_CHICKEN1, temp);
2392         }
2393 }
2394
2395 /* The FDI link training functions for ILK/Ibexpeak. */
2396 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2397 {
2398         struct drm_device *dev = crtc->dev;
2399         struct drm_i915_private *dev_priv = dev->dev_private;
2400         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2401         int pipe = intel_crtc->pipe;
2402         int plane = intel_crtc->plane;
2403         u32 reg, temp, tries;
2404
2405         /* FDI needs bits from pipe & plane first */
2406         assert_pipe_enabled(dev_priv, pipe);
2407         assert_plane_enabled(dev_priv, plane);
2408
2409         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2410            for train result */
2411         reg = FDI_RX_IMR(pipe);
2412         temp = I915_READ(reg);
2413         temp &= ~FDI_RX_SYMBOL_LOCK;
2414         temp &= ~FDI_RX_BIT_LOCK;
2415         I915_WRITE(reg, temp);
2416         I915_READ(reg);
2417         udelay(150);
2418
2419         /* enable CPU FDI TX and PCH FDI RX */
2420         reg = FDI_TX_CTL(pipe);
2421         temp = I915_READ(reg);
2422         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2423         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2424         temp &= ~FDI_LINK_TRAIN_NONE;
2425         temp |= FDI_LINK_TRAIN_PATTERN_1;
2426         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2427
2428         reg = FDI_RX_CTL(pipe);
2429         temp = I915_READ(reg);
2430         temp &= ~FDI_LINK_TRAIN_NONE;
2431         temp |= FDI_LINK_TRAIN_PATTERN_1;
2432         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2433
2434         POSTING_READ(reg);
2435         udelay(150);
2436
2437         /* Ironlake workaround, enable clock pointer after FDI enable*/
2438         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2439         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2440                    FDI_RX_PHASE_SYNC_POINTER_EN);
2441
2442         reg = FDI_RX_IIR(pipe);
2443         for (tries = 0; tries < 5; tries++) {
2444                 temp = I915_READ(reg);
2445                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2446
2447                 if ((temp & FDI_RX_BIT_LOCK)) {
2448                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2449                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2450                         break;
2451                 }
2452         }
2453         if (tries == 5)
2454                 DRM_ERROR("FDI train 1 fail!\n");
2455
2456         /* Train 2 */
2457         reg = FDI_TX_CTL(pipe);
2458         temp = I915_READ(reg);
2459         temp &= ~FDI_LINK_TRAIN_NONE;
2460         temp |= FDI_LINK_TRAIN_PATTERN_2;
2461         I915_WRITE(reg, temp);
2462
2463         reg = FDI_RX_CTL(pipe);
2464         temp = I915_READ(reg);
2465         temp &= ~FDI_LINK_TRAIN_NONE;
2466         temp |= FDI_LINK_TRAIN_PATTERN_2;
2467         I915_WRITE(reg, temp);
2468
2469         POSTING_READ(reg);
2470         udelay(150);
2471
2472         reg = FDI_RX_IIR(pipe);
2473         for (tries = 0; tries < 5; tries++) {
2474                 temp = I915_READ(reg);
2475                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2476
2477                 if (temp & FDI_RX_SYMBOL_LOCK) {
2478                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2479                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2480                         break;
2481                 }
2482         }
2483         if (tries == 5)
2484                 DRM_ERROR("FDI train 2 fail!\n");
2485
2486         DRM_DEBUG_KMS("FDI train done\n");
2487
2488 }
2489
2490 static const int snb_b_fdi_train_param[] = {
2491         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2492         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2493         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2494         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2495 };
2496
2497 /* The FDI link training functions for SNB/Cougarpoint. */
2498 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2499 {
2500         struct drm_device *dev = crtc->dev;
2501         struct drm_i915_private *dev_priv = dev->dev_private;
2502         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2503         int pipe = intel_crtc->pipe;
2504         u32 reg, temp, i, retry;
2505
2506         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2507            for train result */
2508         reg = FDI_RX_IMR(pipe);
2509         temp = I915_READ(reg);
2510         temp &= ~FDI_RX_SYMBOL_LOCK;
2511         temp &= ~FDI_RX_BIT_LOCK;
2512         I915_WRITE(reg, temp);
2513
2514         POSTING_READ(reg);
2515         udelay(150);
2516
2517         /* enable CPU FDI TX and PCH FDI RX */
2518         reg = FDI_TX_CTL(pipe);
2519         temp = I915_READ(reg);
2520         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2521         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2522         temp &= ~FDI_LINK_TRAIN_NONE;
2523         temp |= FDI_LINK_TRAIN_PATTERN_1;
2524         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2525         /* SNB-B */
2526         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2527         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2528
2529         I915_WRITE(FDI_RX_MISC(pipe),
2530                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2531
2532         reg = FDI_RX_CTL(pipe);
2533         temp = I915_READ(reg);
2534         if (HAS_PCH_CPT(dev)) {
2535                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2536                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2537         } else {
2538                 temp &= ~FDI_LINK_TRAIN_NONE;
2539                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2540         }
2541         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2542
2543         POSTING_READ(reg);
2544         udelay(150);
2545
2546         for (i = 0; i < 4; i++) {
2547                 reg = FDI_TX_CTL(pipe);
2548                 temp = I915_READ(reg);
2549                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2550                 temp |= snb_b_fdi_train_param[i];
2551                 I915_WRITE(reg, temp);
2552
2553                 POSTING_READ(reg);
2554                 udelay(500);
2555
2556                 for (retry = 0; retry < 5; retry++) {
2557                         reg = FDI_RX_IIR(pipe);
2558                         temp = I915_READ(reg);
2559                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2560                         if (temp & FDI_RX_BIT_LOCK) {
2561                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2562                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2563                                 break;
2564                         }
2565                         udelay(50);
2566                 }
2567                 if (retry < 5)
2568                         break;
2569         }
2570         if (i == 4)
2571                 DRM_ERROR("FDI train 1 fail!\n");
2572
2573         /* Train 2 */
2574         reg = FDI_TX_CTL(pipe);
2575         temp = I915_READ(reg);
2576         temp &= ~FDI_LINK_TRAIN_NONE;
2577         temp |= FDI_LINK_TRAIN_PATTERN_2;
2578         if (IS_GEN6(dev)) {
2579                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2580                 /* SNB-B */
2581                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2582         }
2583         I915_WRITE(reg, temp);
2584
2585         reg = FDI_RX_CTL(pipe);
2586         temp = I915_READ(reg);
2587         if (HAS_PCH_CPT(dev)) {
2588                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2589                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2590         } else {
2591                 temp &= ~FDI_LINK_TRAIN_NONE;
2592                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2593         }
2594         I915_WRITE(reg, temp);
2595
2596         POSTING_READ(reg);
2597         udelay(150);
2598
2599         for (i = 0; i < 4; i++) {
2600                 reg = FDI_TX_CTL(pipe);
2601                 temp = I915_READ(reg);
2602                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2603                 temp |= snb_b_fdi_train_param[i];
2604                 I915_WRITE(reg, temp);
2605
2606                 POSTING_READ(reg);
2607                 udelay(500);
2608
2609                 for (retry = 0; retry < 5; retry++) {
2610                         reg = FDI_RX_IIR(pipe);
2611                         temp = I915_READ(reg);
2612                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2613                         if (temp & FDI_RX_SYMBOL_LOCK) {
2614                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2615                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2616                                 break;
2617                         }
2618                         udelay(50);
2619                 }
2620                 if (retry < 5)
2621                         break;
2622         }
2623         if (i == 4)
2624                 DRM_ERROR("FDI train 2 fail!\n");
2625
2626         DRM_DEBUG_KMS("FDI train done.\n");
2627 }
2628
2629 /* Manual link training for Ivy Bridge A0 parts */
2630 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2631 {
2632         struct drm_device *dev = crtc->dev;
2633         struct drm_i915_private *dev_priv = dev->dev_private;
2634         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2635         int pipe = intel_crtc->pipe;
2636         u32 reg, temp, i;
2637
2638         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2639            for train result */
2640         reg = FDI_RX_IMR(pipe);
2641         temp = I915_READ(reg);
2642         temp &= ~FDI_RX_SYMBOL_LOCK;
2643         temp &= ~FDI_RX_BIT_LOCK;
2644         I915_WRITE(reg, temp);
2645
2646         POSTING_READ(reg);
2647         udelay(150);
2648
2649         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2650                       I915_READ(FDI_RX_IIR(pipe)));
2651
2652         /* enable CPU FDI TX and PCH FDI RX */
2653         reg = FDI_TX_CTL(pipe);
2654         temp = I915_READ(reg);
2655         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2656         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2657         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2658         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2659         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2660         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2661         temp |= FDI_COMPOSITE_SYNC;
2662         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2663
2664         I915_WRITE(FDI_RX_MISC(pipe),
2665                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2666
2667         reg = FDI_RX_CTL(pipe);
2668         temp = I915_READ(reg);
2669         temp &= ~FDI_LINK_TRAIN_AUTO;
2670         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2671         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2672         temp |= FDI_COMPOSITE_SYNC;
2673         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2674
2675         POSTING_READ(reg);
2676         udelay(150);
2677
2678         for (i = 0; i < 4; i++) {
2679                 reg = FDI_TX_CTL(pipe);
2680                 temp = I915_READ(reg);
2681                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2682                 temp |= snb_b_fdi_train_param[i];
2683                 I915_WRITE(reg, temp);
2684
2685                 POSTING_READ(reg);
2686                 udelay(500);
2687
2688                 reg = FDI_RX_IIR(pipe);
2689                 temp = I915_READ(reg);
2690                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2691
2692                 if (temp & FDI_RX_BIT_LOCK ||
2693                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2694                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2695                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2696                         break;
2697                 }
2698         }
2699         if (i == 4)
2700                 DRM_ERROR("FDI train 1 fail!\n");
2701
2702         /* Train 2 */
2703         reg = FDI_TX_CTL(pipe);
2704         temp = I915_READ(reg);
2705         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2706         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2707         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2708         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2709         I915_WRITE(reg, temp);
2710
2711         reg = FDI_RX_CTL(pipe);
2712         temp = I915_READ(reg);
2713         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2714         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2715         I915_WRITE(reg, temp);
2716
2717         POSTING_READ(reg);
2718         udelay(150);
2719
2720         for (i = 0; i < 4; i++) {
2721                 reg = FDI_TX_CTL(pipe);
2722                 temp = I915_READ(reg);
2723                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2724                 temp |= snb_b_fdi_train_param[i];
2725                 I915_WRITE(reg, temp);
2726
2727                 POSTING_READ(reg);
2728                 udelay(500);
2729
2730                 reg = FDI_RX_IIR(pipe);
2731                 temp = I915_READ(reg);
2732                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2733
2734                 if (temp & FDI_RX_SYMBOL_LOCK) {
2735                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2736                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2737                         break;
2738                 }
2739         }
2740         if (i == 4)
2741                 DRM_ERROR("FDI train 2 fail!\n");
2742
2743         DRM_DEBUG_KMS("FDI train done.\n");
2744 }
2745
2746 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2747 {
2748         struct drm_device *dev = intel_crtc->base.dev;
2749         struct drm_i915_private *dev_priv = dev->dev_private;
2750         int pipe = intel_crtc->pipe;
2751         u32 reg, temp;
2752
2753
2754         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2755         reg = FDI_RX_CTL(pipe);
2756         temp = I915_READ(reg);
2757         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2758         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2759         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2760         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2761
2762         POSTING_READ(reg);
2763         udelay(200);
2764
2765         /* Switch from Rawclk to PCDclk */
2766         temp = I915_READ(reg);
2767         I915_WRITE(reg, temp | FDI_PCDCLK);
2768
2769         POSTING_READ(reg);
2770         udelay(200);
2771
2772         /* Enable CPU FDI TX PLL, always on for Ironlake */
2773         reg = FDI_TX_CTL(pipe);
2774         temp = I915_READ(reg);
2775         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2776                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2777
2778                 POSTING_READ(reg);
2779                 udelay(100);
2780         }
2781 }
2782
2783 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2784 {
2785         struct drm_device *dev = intel_crtc->base.dev;
2786         struct drm_i915_private *dev_priv = dev->dev_private;
2787         int pipe = intel_crtc->pipe;
2788         u32 reg, temp;
2789
2790         /* Switch from PCDclk to Rawclk */
2791         reg = FDI_RX_CTL(pipe);
2792         temp = I915_READ(reg);
2793         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2794
2795         /* Disable CPU FDI TX PLL */
2796         reg = FDI_TX_CTL(pipe);
2797         temp = I915_READ(reg);
2798         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2799
2800         POSTING_READ(reg);
2801         udelay(100);
2802
2803         reg = FDI_RX_CTL(pipe);
2804         temp = I915_READ(reg);
2805         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2806
2807         /* Wait for the clocks to turn off. */
2808         POSTING_READ(reg);
2809         udelay(100);
2810 }
2811
2812 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2813 {
2814         struct drm_device *dev = crtc->dev;
2815         struct drm_i915_private *dev_priv = dev->dev_private;
2816         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2817         int pipe = intel_crtc->pipe;
2818         u32 reg, temp;
2819
2820         /* disable CPU FDI tx and PCH FDI rx */
2821         reg = FDI_TX_CTL(pipe);
2822         temp = I915_READ(reg);
2823         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2824         POSTING_READ(reg);
2825
2826         reg = FDI_RX_CTL(pipe);
2827         temp = I915_READ(reg);
2828         temp &= ~(0x7 << 16);
2829         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2830         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2831
2832         POSTING_READ(reg);
2833         udelay(100);
2834
2835         /* Ironlake workaround, disable clock pointer after downing FDI */
2836         if (HAS_PCH_IBX(dev)) {
2837                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2838         }
2839
2840         /* still set train pattern 1 */
2841         reg = FDI_TX_CTL(pipe);
2842         temp = I915_READ(reg);
2843         temp &= ~FDI_LINK_TRAIN_NONE;
2844         temp |= FDI_LINK_TRAIN_PATTERN_1;
2845         I915_WRITE(reg, temp);
2846
2847         reg = FDI_RX_CTL(pipe);
2848         temp = I915_READ(reg);
2849         if (HAS_PCH_CPT(dev)) {
2850                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2851                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2852         } else {
2853                 temp &= ~FDI_LINK_TRAIN_NONE;
2854                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2855         }
2856         /* BPC in FDI rx is consistent with that in PIPECONF */
2857         temp &= ~(0x07 << 16);
2858         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2859         I915_WRITE(reg, temp);
2860
2861         POSTING_READ(reg);
2862         udelay(100);
2863 }
2864
2865 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2866 {
2867         struct drm_device *dev = crtc->dev;
2868         struct drm_i915_private *dev_priv = dev->dev_private;
2869         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2870         unsigned long flags;
2871         bool pending;
2872
2873         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2874             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2875                 return false;
2876
2877         spin_lock_irqsave(&dev->event_lock, flags);
2878         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2879         spin_unlock_irqrestore(&dev->event_lock, flags);
2880
2881         return pending;
2882 }
2883
2884 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2885 {
2886         struct drm_device *dev = crtc->dev;
2887         struct drm_i915_private *dev_priv = dev->dev_private;
2888
2889         if (crtc->fb == NULL)
2890                 return;
2891
2892         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2893
2894         wait_event(dev_priv->pending_flip_queue,
2895                    !intel_crtc_has_pending_flip(crtc));
2896
2897         mutex_lock(&dev->struct_mutex);
2898         intel_finish_fb(crtc->fb);
2899         mutex_unlock(&dev->struct_mutex);
2900 }
2901
2902 /* Program iCLKIP clock to the desired frequency */
2903 static void lpt_program_iclkip(struct drm_crtc *crtc)
2904 {
2905         struct drm_device *dev = crtc->dev;
2906         struct drm_i915_private *dev_priv = dev->dev_private;
2907         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2908         u32 temp;
2909
2910         mutex_lock(&dev_priv->dpio_lock);
2911
2912         /* It is necessary to ungate the pixclk gate prior to programming
2913          * the divisors, and gate it back when it is done.
2914          */
2915         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2916
2917         /* Disable SSCCTL */
2918         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2919                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2920                                 SBI_SSCCTL_DISABLE,
2921                         SBI_ICLK);
2922
2923         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2924         if (crtc->mode.clock == 20000) {
2925                 auxdiv = 1;
2926                 divsel = 0x41;
2927                 phaseinc = 0x20;
2928         } else {
2929                 /* The iCLK virtual clock root frequency is in MHz,
2930                  * but the crtc->mode.clock in in KHz. To get the divisors,
2931                  * it is necessary to divide one by another, so we
2932                  * convert the virtual clock precision to KHz here for higher
2933                  * precision.
2934                  */
2935                 u32 iclk_virtual_root_freq = 172800 * 1000;
2936                 u32 iclk_pi_range = 64;
2937                 u32 desired_divisor, msb_divisor_value, pi_value;
2938
2939                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2940                 msb_divisor_value = desired_divisor / iclk_pi_range;
2941                 pi_value = desired_divisor % iclk_pi_range;
2942
2943                 auxdiv = 0;
2944                 divsel = msb_divisor_value - 2;
2945                 phaseinc = pi_value;
2946         }
2947
2948         /* This should not happen with any sane values */
2949         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2950                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2951         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2952                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2953
2954         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2955                         crtc->mode.clock,
2956                         auxdiv,
2957                         divsel,
2958                         phasedir,
2959                         phaseinc);
2960
2961         /* Program SSCDIVINTPHASE6 */
2962         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2963         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2964         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2965         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2966         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2967         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2968         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2969         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2970
2971         /* Program SSCAUXDIV */
2972         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2973         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2974         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2975         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2976
2977         /* Enable modulator and associated divider */
2978         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2979         temp &= ~SBI_SSCCTL_DISABLE;
2980         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2981
2982         /* Wait for initialization time */
2983         udelay(24);
2984
2985         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2986
2987         mutex_unlock(&dev_priv->dpio_lock);
2988 }
2989
2990 /*
2991  * Enable PCH resources required for PCH ports:
2992  *   - PCH PLLs
2993  *   - FDI training & RX/TX
2994  *   - update transcoder timings
2995  *   - DP transcoding bits
2996  *   - transcoder
2997  */
2998 static void ironlake_pch_enable(struct drm_crtc *crtc)
2999 {
3000         struct drm_device *dev = crtc->dev;
3001         struct drm_i915_private *dev_priv = dev->dev_private;
3002         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3003         int pipe = intel_crtc->pipe;
3004         u32 reg, temp;
3005
3006         assert_transcoder_disabled(dev_priv, pipe);
3007
3008         /* Write the TU size bits before fdi link training, so that error
3009          * detection works. */
3010         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3011                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3012
3013         /* For PCH output, training FDI link */
3014         dev_priv->display.fdi_link_train(crtc);
3015
3016         /* XXX: pch pll's can be enabled any time before we enable the PCH
3017          * transcoder, and we actually should do this to not upset any PCH
3018          * transcoder that already use the clock when we share it.
3019          *
3020          * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3021          * unconditionally resets the pll - we need that to have the right LVDS
3022          * enable sequence. */
3023         ironlake_enable_pch_pll(intel_crtc);
3024
3025         if (HAS_PCH_CPT(dev)) {
3026                 u32 sel;
3027
3028                 temp = I915_READ(PCH_DPLL_SEL);
3029                 switch (pipe) {
3030                 default:
3031                 case 0:
3032                         temp |= TRANSA_DPLL_ENABLE;
3033                         sel = TRANSA_DPLLB_SEL;
3034                         break;
3035                 case 1:
3036                         temp |= TRANSB_DPLL_ENABLE;
3037                         sel = TRANSB_DPLLB_SEL;
3038                         break;
3039                 case 2:
3040                         temp |= TRANSC_DPLL_ENABLE;
3041                         sel = TRANSC_DPLLB_SEL;
3042                         break;
3043                 }
3044                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3045                         temp |= sel;
3046                 else
3047                         temp &= ~sel;
3048                 I915_WRITE(PCH_DPLL_SEL, temp);
3049         }
3050
3051         /* set transcoder timing, panel must allow it */
3052         assert_panel_unlocked(dev_priv, pipe);
3053         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3054         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3055         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3056
3057         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3058         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3059         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3060         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3061
3062         intel_fdi_normal_train(crtc);
3063
3064         /* For PCH DP, enable TRANS_DP_CTL */
3065         if (HAS_PCH_CPT(dev) &&
3066             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3067              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3068                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3069                 reg = TRANS_DP_CTL(pipe);
3070                 temp = I915_READ(reg);
3071                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3072                           TRANS_DP_SYNC_MASK |
3073                           TRANS_DP_BPC_MASK);
3074                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3075                          TRANS_DP_ENH_FRAMING);
3076                 temp |= bpc << 9; /* same format but at 11:9 */
3077
3078                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3079                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3080                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3081                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3082
3083                 switch (intel_trans_dp_port_sel(crtc)) {
3084                 case PCH_DP_B:
3085                         temp |= TRANS_DP_PORT_SEL_B;
3086                         break;
3087                 case PCH_DP_C:
3088                         temp |= TRANS_DP_PORT_SEL_C;
3089                         break;
3090                 case PCH_DP_D:
3091                         temp |= TRANS_DP_PORT_SEL_D;
3092                         break;
3093                 default:
3094                         BUG();
3095                 }
3096
3097                 I915_WRITE(reg, temp);
3098         }
3099
3100         ironlake_enable_pch_transcoder(dev_priv, pipe);
3101 }
3102
3103 static void lpt_pch_enable(struct drm_crtc *crtc)
3104 {
3105         struct drm_device *dev = crtc->dev;
3106         struct drm_i915_private *dev_priv = dev->dev_private;
3107         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3108         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3109
3110         assert_transcoder_disabled(dev_priv, TRANSCODER_A);
3111
3112         lpt_program_iclkip(crtc);
3113
3114         /* Set transcoder timing. */
3115         I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3116         I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3117         I915_WRITE(_TRANS_HSYNC_A,  I915_READ(HSYNC(cpu_transcoder)));
3118
3119         I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3120         I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3121         I915_WRITE(_TRANS_VSYNC_A,  I915_READ(VSYNC(cpu_transcoder)));
3122         I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
3123
3124         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3125 }
3126
3127 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3128 {
3129         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3130
3131         if (pll == NULL)
3132                 return;
3133
3134         if (pll->refcount == 0) {
3135                 WARN(1, "bad PCH PLL refcount\n");
3136                 return;
3137         }
3138
3139         --pll->refcount;
3140         intel_crtc->pch_pll = NULL;
3141 }
3142
3143 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3144 {
3145         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3146         struct intel_pch_pll *pll;
3147         int i;
3148
3149         pll = intel_crtc->pch_pll;
3150         if (pll) {
3151                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3152                               intel_crtc->base.base.id, pll->pll_reg);
3153                 goto prepare;
3154         }
3155
3156         if (HAS_PCH_IBX(dev_priv->dev)) {
3157                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3158                 i = intel_crtc->pipe;
3159                 pll = &dev_priv->pch_plls[i];
3160
3161                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3162                               intel_crtc->base.base.id, pll->pll_reg);
3163
3164                 goto found;
3165         }
3166
3167         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3168                 pll = &dev_priv->pch_plls[i];
3169
3170                 /* Only want to check enabled timings first */
3171                 if (pll->refcount == 0)
3172                         continue;
3173
3174                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3175                     fp == I915_READ(pll->fp0_reg)) {
3176                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3177                                       intel_crtc->base.base.id,
3178                                       pll->pll_reg, pll->refcount, pll->active);
3179
3180                         goto found;
3181                 }
3182         }
3183
3184         /* Ok no matching timings, maybe there's a free one? */
3185         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3186                 pll = &dev_priv->pch_plls[i];
3187                 if (pll->refcount == 0) {
3188                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3189                                       intel_crtc->base.base.id, pll->pll_reg);
3190                         goto found;
3191                 }
3192         }
3193
3194         return NULL;
3195
3196 found:
3197         intel_crtc->pch_pll = pll;
3198         pll->refcount++;
3199         DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
3200 prepare: /* separate function? */
3201         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3202
3203         /* Wait for the clocks to stabilize before rewriting the regs */
3204         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3205         POSTING_READ(pll->pll_reg);
3206         udelay(150);
3207
3208         I915_WRITE(pll->fp0_reg, fp);
3209         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3210         pll->on = false;
3211         return pll;
3212 }
3213
3214 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3215 {
3216         struct drm_i915_private *dev_priv = dev->dev_private;
3217         int dslreg = PIPEDSL(pipe);
3218         u32 temp;
3219
3220         temp = I915_READ(dslreg);
3221         udelay(500);
3222         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3223                 if (wait_for(I915_READ(dslreg) != temp, 5))
3224                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3225         }
3226 }
3227
3228 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3229 {
3230         struct drm_device *dev = crtc->base.dev;
3231         struct drm_i915_private *dev_priv = dev->dev_private;
3232         int pipe = crtc->pipe;
3233
3234         if (crtc->config.pch_pfit.size &&
3235             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) {
3236                 /* Force use of hard-coded filter coefficients
3237                  * as some pre-programmed values are broken,
3238                  * e.g. x201.
3239                  */
3240                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3241                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3242                                                  PF_PIPE_SEL_IVB(pipe));
3243                 else
3244                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3245                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3246                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3247         }
3248 }
3249
3250 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3251 {
3252         struct drm_device *dev = crtc->dev;
3253         struct drm_i915_private *dev_priv = dev->dev_private;
3254         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3255         struct intel_encoder *encoder;
3256         int pipe = intel_crtc->pipe;
3257         int plane = intel_crtc->plane;
3258         u32 temp;
3259
3260         WARN_ON(!crtc->enabled);
3261
3262         if (intel_crtc->active)
3263                 return;
3264
3265         intel_crtc->active = true;
3266
3267         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3268         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3269
3270         intel_update_watermarks(dev);
3271
3272         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3273                 temp = I915_READ(PCH_LVDS);
3274                 if ((temp & LVDS_PORT_EN) == 0)
3275                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3276         }
3277
3278
3279         if (intel_crtc->config.has_pch_encoder) {
3280                 /* Note: FDI PLL enabling _must_ be done before we enable the
3281                  * cpu pipes, hence this is separate from all the other fdi/pch
3282                  * enabling. */
3283                 ironlake_fdi_pll_enable(intel_crtc);
3284         } else {
3285                 assert_fdi_tx_disabled(dev_priv, pipe);
3286                 assert_fdi_rx_disabled(dev_priv, pipe);
3287         }
3288
3289         for_each_encoder_on_crtc(dev, crtc, encoder)
3290                 if (encoder->pre_enable)
3291                         encoder->pre_enable(encoder);
3292
3293         /* Enable panel fitting for LVDS */
3294         ironlake_pfit_enable(intel_crtc);
3295
3296         /*
3297          * On ILK+ LUT must be loaded before the pipe is running but with
3298          * clocks enabled
3299          */
3300         intel_crtc_load_lut(crtc);
3301
3302         intel_enable_pipe(dev_priv, pipe,
3303                           intel_crtc->config.has_pch_encoder);
3304         intel_enable_plane(dev_priv, plane, pipe);
3305
3306         if (intel_crtc->config.has_pch_encoder)
3307                 ironlake_pch_enable(crtc);
3308
3309         mutex_lock(&dev->struct_mutex);
3310         intel_update_fbc(dev);
3311         mutex_unlock(&dev->struct_mutex);
3312
3313         intel_crtc_update_cursor(crtc, true);
3314
3315         for_each_encoder_on_crtc(dev, crtc, encoder)
3316                 encoder->enable(encoder);
3317
3318         if (HAS_PCH_CPT(dev))
3319                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3320
3321         /*
3322          * There seems to be a race in PCH platform hw (at least on some
3323          * outputs) where an enabled pipe still completes any pageflip right
3324          * away (as if the pipe is off) instead of waiting for vblank. As soon
3325          * as the first vblank happend, everything works as expected. Hence just
3326          * wait for one vblank before returning to avoid strange things
3327          * happening.
3328          */
3329         intel_wait_for_vblank(dev, intel_crtc->pipe);
3330 }
3331
3332 static void haswell_crtc_enable(struct drm_crtc *crtc)
3333 {
3334         struct drm_device *dev = crtc->dev;
3335         struct drm_i915_private *dev_priv = dev->dev_private;
3336         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3337         struct intel_encoder *encoder;
3338         int pipe = intel_crtc->pipe;
3339         int plane = intel_crtc->plane;
3340
3341         WARN_ON(!crtc->enabled);
3342
3343         if (intel_crtc->active)
3344                 return;
3345
3346         intel_crtc->active = true;
3347
3348         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3349         if (intel_crtc->config.has_pch_encoder)
3350                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3351
3352         intel_update_watermarks(dev);
3353
3354         if (intel_crtc->config.has_pch_encoder)
3355                 dev_priv->display.fdi_link_train(crtc);
3356
3357         for_each_encoder_on_crtc(dev, crtc, encoder)
3358                 if (encoder->pre_enable)
3359                         encoder->pre_enable(encoder);
3360
3361         intel_ddi_enable_pipe_clock(intel_crtc);
3362
3363         /* Enable panel fitting for eDP */
3364         ironlake_pfit_enable(intel_crtc);
3365
3366         /*
3367          * On ILK+ LUT must be loaded before the pipe is running but with
3368          * clocks enabled
3369          */
3370         intel_crtc_load_lut(crtc);
3371
3372         intel_ddi_set_pipe_settings(crtc);
3373         intel_ddi_enable_transcoder_func(crtc);
3374
3375         intel_enable_pipe(dev_priv, pipe,
3376                           intel_crtc->config.has_pch_encoder);
3377         intel_enable_plane(dev_priv, plane, pipe);
3378
3379         if (intel_crtc->config.has_pch_encoder)
3380                 lpt_pch_enable(crtc);
3381
3382         mutex_lock(&dev->struct_mutex);
3383         intel_update_fbc(dev);
3384         mutex_unlock(&dev->struct_mutex);
3385
3386         intel_crtc_update_cursor(crtc, true);
3387
3388         for_each_encoder_on_crtc(dev, crtc, encoder)
3389                 encoder->enable(encoder);
3390
3391         /*
3392          * There seems to be a race in PCH platform hw (at least on some
3393          * outputs) where an enabled pipe still completes any pageflip right
3394          * away (as if the pipe is off) instead of waiting for vblank. As soon
3395          * as the first vblank happend, everything works as expected. Hence just
3396          * wait for one vblank before returning to avoid strange things
3397          * happening.
3398          */
3399         intel_wait_for_vblank(dev, intel_crtc->pipe);
3400 }
3401
3402 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3403 {
3404         struct drm_device *dev = crtc->dev;
3405         struct drm_i915_private *dev_priv = dev->dev_private;
3406         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3407         struct intel_encoder *encoder;
3408         int pipe = intel_crtc->pipe;
3409         int plane = intel_crtc->plane;
3410         u32 reg, temp;
3411
3412
3413         if (!intel_crtc->active)
3414                 return;
3415
3416         for_each_encoder_on_crtc(dev, crtc, encoder)
3417                 encoder->disable(encoder);
3418
3419         intel_crtc_wait_for_pending_flips(crtc);
3420         drm_vblank_off(dev, pipe);
3421         intel_crtc_update_cursor(crtc, false);
3422
3423         intel_disable_plane(dev_priv, plane, pipe);
3424
3425         if (dev_priv->cfb_plane == plane)
3426                 intel_disable_fbc(dev);
3427
3428         intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3429         intel_disable_pipe(dev_priv, pipe);
3430
3431         /* Disable PF */
3432         I915_WRITE(PF_CTL(pipe), 0);
3433         I915_WRITE(PF_WIN_SZ(pipe), 0);
3434
3435         for_each_encoder_on_crtc(dev, crtc, encoder)
3436                 if (encoder->post_disable)
3437                         encoder->post_disable(encoder);
3438
3439         ironlake_fdi_disable(crtc);
3440
3441         ironlake_disable_pch_transcoder(dev_priv, pipe);
3442         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3443
3444         if (HAS_PCH_CPT(dev)) {
3445                 /* disable TRANS_DP_CTL */
3446                 reg = TRANS_DP_CTL(pipe);
3447                 temp = I915_READ(reg);
3448                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3449                 temp |= TRANS_DP_PORT_SEL_NONE;
3450                 I915_WRITE(reg, temp);
3451
3452                 /* disable DPLL_SEL */
3453                 temp = I915_READ(PCH_DPLL_SEL);
3454                 switch (pipe) {
3455                 case 0:
3456                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3457                         break;
3458                 case 1:
3459                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3460                         break;
3461                 case 2:
3462                         /* C shares PLL A or B */
3463                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3464                         break;
3465                 default:
3466                         BUG(); /* wtf */
3467                 }
3468                 I915_WRITE(PCH_DPLL_SEL, temp);
3469         }
3470
3471         /* disable PCH DPLL */
3472         intel_disable_pch_pll(intel_crtc);
3473
3474         ironlake_fdi_pll_disable(intel_crtc);
3475
3476         intel_crtc->active = false;
3477         intel_update_watermarks(dev);
3478
3479         mutex_lock(&dev->struct_mutex);
3480         intel_update_fbc(dev);
3481         mutex_unlock(&dev->struct_mutex);
3482 }
3483
3484 static void haswell_crtc_disable(struct drm_crtc *crtc)
3485 {
3486         struct drm_device *dev = crtc->dev;
3487         struct drm_i915_private *dev_priv = dev->dev_private;
3488         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3489         struct intel_encoder *encoder;
3490         int pipe = intel_crtc->pipe;
3491         int plane = intel_crtc->plane;
3492         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3493
3494         if (!intel_crtc->active)
3495                 return;
3496
3497         for_each_encoder_on_crtc(dev, crtc, encoder)
3498                 encoder->disable(encoder);
3499
3500         intel_crtc_wait_for_pending_flips(crtc);
3501         drm_vblank_off(dev, pipe);
3502         intel_crtc_update_cursor(crtc, false);
3503
3504         intel_disable_plane(dev_priv, plane, pipe);
3505
3506         if (dev_priv->cfb_plane == plane)
3507                 intel_disable_fbc(dev);
3508
3509         if (intel_crtc->config.has_pch_encoder)
3510                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3511         intel_disable_pipe(dev_priv, pipe);
3512
3513         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3514
3515         /* XXX: Once we have proper panel fitter state tracking implemented with
3516          * hardware state read/check support we should switch to only disable
3517          * the panel fitter when we know it's used. */
3518         if (intel_using_power_well(dev)) {
3519                 I915_WRITE(PF_CTL(pipe), 0);
3520                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3521         }
3522
3523         intel_ddi_disable_pipe_clock(intel_crtc);
3524
3525         for_each_encoder_on_crtc(dev, crtc, encoder)
3526                 if (encoder->post_disable)
3527                         encoder->post_disable(encoder);
3528
3529         if (intel_crtc->config.has_pch_encoder) {
3530                 lpt_disable_pch_transcoder(dev_priv);
3531                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3532                 intel_ddi_fdi_disable(crtc);
3533         }
3534
3535         intel_crtc->active = false;
3536         intel_update_watermarks(dev);
3537
3538         mutex_lock(&dev->struct_mutex);
3539         intel_update_fbc(dev);
3540         mutex_unlock(&dev->struct_mutex);
3541 }
3542
3543 static void ironlake_crtc_off(struct drm_crtc *crtc)
3544 {
3545         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3546         intel_put_pch_pll(intel_crtc);
3547 }
3548
3549 static void haswell_crtc_off(struct drm_crtc *crtc)
3550 {
3551         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3552
3553         /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3554          * start using it. */
3555         intel_crtc->config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
3556
3557         intel_ddi_put_crtc_pll(crtc);
3558 }
3559
3560 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3561 {
3562         if (!enable && intel_crtc->overlay) {
3563                 struct drm_device *dev = intel_crtc->base.dev;
3564                 struct drm_i915_private *dev_priv = dev->dev_private;
3565
3566                 mutex_lock(&dev->struct_mutex);
3567                 dev_priv->mm.interruptible = false;
3568                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3569                 dev_priv->mm.interruptible = true;
3570                 mutex_unlock(&dev->struct_mutex);
3571         }
3572
3573         /* Let userspace switch the overlay on again. In most cases userspace
3574          * has to recompute where to put it anyway.
3575          */
3576 }
3577
3578 /**
3579  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3580  * cursor plane briefly if not already running after enabling the display
3581  * plane.
3582  * This workaround avoids occasional blank screens when self refresh is
3583  * enabled.
3584  */
3585 static void
3586 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3587 {
3588         u32 cntl = I915_READ(CURCNTR(pipe));
3589
3590         if ((cntl & CURSOR_MODE) == 0) {
3591                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3592
3593                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3594                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3595                 intel_wait_for_vblank(dev_priv->dev, pipe);
3596                 I915_WRITE(CURCNTR(pipe), cntl);
3597                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3598                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3599         }
3600 }
3601
3602 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3603 {
3604         struct drm_device *dev = crtc->base.dev;
3605         struct drm_i915_private *dev_priv = dev->dev_private;
3606         struct intel_crtc_config *pipe_config = &crtc->config;
3607
3608         if (!(intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
3609               intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)))
3610                 return;
3611
3612         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3613         assert_pipe_disabled(dev_priv, crtc->pipe);
3614
3615         /*
3616          * Enable automatic panel scaling so that non-native modes
3617          * fill the screen.  The panel fitter should only be
3618          * adjusted whilst the pipe is disabled, according to
3619          * register description and PRM.
3620          */
3621         DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n",
3622                       pipe_config->gmch_pfit.control,
3623                       pipe_config->gmch_pfit.pgm_ratios);
3624
3625         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3626         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3627 }
3628
3629 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3630 {
3631         struct drm_device *dev = crtc->dev;
3632         struct drm_i915_private *dev_priv = dev->dev_private;
3633         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3634         struct intel_encoder *encoder;
3635         int pipe = intel_crtc->pipe;
3636         int plane = intel_crtc->plane;
3637
3638         WARN_ON(!crtc->enabled);
3639
3640         if (intel_crtc->active)
3641                 return;
3642
3643         intel_crtc->active = true;
3644         intel_update_watermarks(dev);
3645
3646         mutex_lock(&dev_priv->dpio_lock);
3647
3648         for_each_encoder_on_crtc(dev, crtc, encoder)
3649                 if (encoder->pre_pll_enable)
3650                         encoder->pre_pll_enable(encoder);
3651
3652         intel_enable_pll(dev_priv, pipe);
3653
3654         for_each_encoder_on_crtc(dev, crtc, encoder)
3655                 if (encoder->pre_enable)
3656                         encoder->pre_enable(encoder);
3657
3658         /* VLV wants encoder enabling _before_ the pipe is up. */
3659         for_each_encoder_on_crtc(dev, crtc, encoder)
3660                 encoder->enable(encoder);
3661
3662         /* Enable panel fitting for eDP */
3663         i9xx_pfit_enable(intel_crtc);
3664
3665         intel_enable_pipe(dev_priv, pipe, false);
3666         intel_enable_plane(dev_priv, plane, pipe);
3667
3668         intel_crtc_load_lut(crtc);
3669         intel_update_fbc(dev);
3670
3671         /* Give the overlay scaler a chance to enable if it's on this pipe */
3672         intel_crtc_dpms_overlay(intel_crtc, true);
3673         intel_crtc_update_cursor(crtc, true);
3674
3675         mutex_unlock(&dev_priv->dpio_lock);
3676 }
3677
3678 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3679 {
3680         struct drm_device *dev = crtc->dev;
3681         struct drm_i915_private *dev_priv = dev->dev_private;
3682         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3683         struct intel_encoder *encoder;
3684         int pipe = intel_crtc->pipe;
3685         int plane = intel_crtc->plane;
3686
3687         WARN_ON(!crtc->enabled);
3688
3689         if (intel_crtc->active)
3690                 return;
3691
3692         intel_crtc->active = true;
3693         intel_update_watermarks(dev);
3694
3695         intel_enable_pll(dev_priv, pipe);
3696
3697         for_each_encoder_on_crtc(dev, crtc, encoder)
3698                 if (encoder->pre_enable)
3699                         encoder->pre_enable(encoder);
3700
3701         /* Enable panel fitting for LVDS */
3702         i9xx_pfit_enable(intel_crtc);
3703
3704         intel_enable_pipe(dev_priv, pipe, false);
3705         intel_enable_plane(dev_priv, plane, pipe);
3706         if (IS_G4X(dev))
3707                 g4x_fixup_plane(dev_priv, pipe);
3708
3709         intel_crtc_load_lut(crtc);
3710         intel_update_fbc(dev);
3711
3712         /* Give the overlay scaler a chance to enable if it's on this pipe */
3713         intel_crtc_dpms_overlay(intel_crtc, true);
3714         intel_crtc_update_cursor(crtc, true);
3715
3716         for_each_encoder_on_crtc(dev, crtc, encoder)
3717                 encoder->enable(encoder);
3718 }
3719
3720 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3721 {
3722         struct drm_device *dev = crtc->base.dev;
3723         struct drm_i915_private *dev_priv = dev->dev_private;
3724         enum pipe pipe;
3725         uint32_t pctl = I915_READ(PFIT_CONTROL);
3726
3727         assert_pipe_disabled(dev_priv, crtc->pipe);
3728
3729         if (INTEL_INFO(dev)->gen >= 4)
3730                 pipe = (pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT;
3731         else
3732                 pipe = PIPE_B;
3733
3734         if (pipe == crtc->pipe) {
3735                 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", pctl);
3736                 I915_WRITE(PFIT_CONTROL, 0);
3737         }
3738 }
3739
3740 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3741 {
3742         struct drm_device *dev = crtc->dev;
3743         struct drm_i915_private *dev_priv = dev->dev_private;
3744         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3745         struct intel_encoder *encoder;
3746         int pipe = intel_crtc->pipe;
3747         int plane = intel_crtc->plane;
3748
3749         if (!intel_crtc->active)
3750                 return;
3751
3752         for_each_encoder_on_crtc(dev, crtc, encoder)
3753                 encoder->disable(encoder);
3754
3755         /* Give the overlay scaler a chance to disable if it's on this pipe */
3756         intel_crtc_wait_for_pending_flips(crtc);
3757         drm_vblank_off(dev, pipe);
3758         intel_crtc_dpms_overlay(intel_crtc, false);
3759         intel_crtc_update_cursor(crtc, false);
3760
3761         if (dev_priv->cfb_plane == plane)
3762                 intel_disable_fbc(dev);
3763
3764         intel_disable_plane(dev_priv, plane, pipe);
3765         intel_disable_pipe(dev_priv, pipe);
3766
3767         i9xx_pfit_disable(intel_crtc);
3768
3769         for_each_encoder_on_crtc(dev, crtc, encoder)
3770                 if (encoder->post_disable)
3771                         encoder->post_disable(encoder);
3772
3773         intel_disable_pll(dev_priv, pipe);
3774
3775         intel_crtc->active = false;
3776         intel_update_fbc(dev);
3777         intel_update_watermarks(dev);
3778 }
3779
3780 static void i9xx_crtc_off(struct drm_crtc *crtc)
3781 {
3782 }
3783
3784 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3785                                     bool enabled)
3786 {
3787         struct drm_device *dev = crtc->dev;
3788         struct drm_i915_master_private *master_priv;
3789         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3790         int pipe = intel_crtc->pipe;
3791
3792         if (!dev->primary->master)
3793                 return;
3794
3795         master_priv = dev->primary->master->driver_priv;
3796         if (!master_priv->sarea_priv)
3797                 return;
3798
3799         switch (pipe) {
3800         case 0:
3801                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3802                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3803                 break;
3804         case 1:
3805                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3806                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3807                 break;
3808         default:
3809                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3810                 break;
3811         }
3812 }
3813
3814 /**
3815  * Sets the power management mode of the pipe and plane.
3816  */
3817 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3818 {
3819         struct drm_device *dev = crtc->dev;
3820         struct drm_i915_private *dev_priv = dev->dev_private;
3821         struct intel_encoder *intel_encoder;
3822         bool enable = false;
3823
3824         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3825                 enable |= intel_encoder->connectors_active;
3826
3827         if (enable)
3828                 dev_priv->display.crtc_enable(crtc);
3829         else
3830                 dev_priv->display.crtc_disable(crtc);
3831
3832         intel_crtc_update_sarea(crtc, enable);
3833 }
3834
3835 static void intel_crtc_disable(struct drm_crtc *crtc)
3836 {
3837         struct drm_device *dev = crtc->dev;
3838         struct drm_connector *connector;
3839         struct drm_i915_private *dev_priv = dev->dev_private;
3840         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3841
3842         /* crtc should still be enabled when we disable it. */
3843         WARN_ON(!crtc->enabled);
3844
3845         intel_crtc->eld_vld = false;
3846         dev_priv->display.crtc_disable(crtc);
3847         intel_crtc_update_sarea(crtc, false);
3848         dev_priv->display.off(crtc);
3849
3850         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3851         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3852
3853         if (crtc->fb) {
3854                 mutex_lock(&dev->struct_mutex);
3855                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3856                 mutex_unlock(&dev->struct_mutex);
3857                 crtc->fb = NULL;
3858         }
3859
3860         /* Update computed state. */
3861         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3862                 if (!connector->encoder || !connector->encoder->crtc)
3863                         continue;
3864
3865                 if (connector->encoder->crtc != crtc)
3866                         continue;
3867
3868                 connector->dpms = DRM_MODE_DPMS_OFF;
3869                 to_intel_encoder(connector->encoder)->connectors_active = false;
3870         }
3871 }
3872
3873 void intel_modeset_disable(struct drm_device *dev)
3874 {
3875         struct drm_crtc *crtc;
3876
3877         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3878                 if (crtc->enabled)
3879                         intel_crtc_disable(crtc);
3880         }
3881 }
3882
3883 void intel_encoder_destroy(struct drm_encoder *encoder)
3884 {
3885         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3886
3887         drm_encoder_cleanup(encoder);
3888         kfree(intel_encoder);
3889 }
3890
3891 /* Simple dpms helper for encodres with just one connector, no cloning and only
3892  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3893  * state of the entire output pipe. */
3894 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3895 {
3896         if (mode == DRM_MODE_DPMS_ON) {
3897                 encoder->connectors_active = true;
3898
3899                 intel_crtc_update_dpms(encoder->base.crtc);
3900         } else {
3901                 encoder->connectors_active = false;
3902
3903                 intel_crtc_update_dpms(encoder->base.crtc);
3904         }
3905 }
3906
3907 /* Cross check the actual hw state with our own modeset state tracking (and it's
3908  * internal consistency). */
3909 static void intel_connector_check_state(struct intel_connector *connector)
3910 {
3911         if (connector->get_hw_state(connector)) {
3912                 struct intel_encoder *encoder = connector->encoder;
3913                 struct drm_crtc *crtc;
3914                 bool encoder_enabled;
3915                 enum pipe pipe;
3916
3917                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3918                               connector->base.base.id,
3919                               drm_get_connector_name(&connector->base));
3920
3921                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3922                      "wrong connector dpms state\n");
3923                 WARN(connector->base.encoder != &encoder->base,
3924                      "active connector not linked to encoder\n");
3925                 WARN(!encoder->connectors_active,
3926                      "encoder->connectors_active not set\n");
3927
3928                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3929                 WARN(!encoder_enabled, "encoder not enabled\n");
3930                 if (WARN_ON(!encoder->base.crtc))
3931                         return;
3932
3933                 crtc = encoder->base.crtc;
3934
3935                 WARN(!crtc->enabled, "crtc not enabled\n");
3936                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3937                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3938                      "encoder active on the wrong pipe\n");
3939         }
3940 }
3941
3942 /* Even simpler default implementation, if there's really no special case to
3943  * consider. */
3944 void intel_connector_dpms(struct drm_connector *connector, int mode)
3945 {
3946         struct intel_encoder *encoder = intel_attached_encoder(connector);
3947
3948         /* All the simple cases only support two dpms states. */
3949         if (mode != DRM_MODE_DPMS_ON)
3950                 mode = DRM_MODE_DPMS_OFF;
3951
3952         if (mode == connector->dpms)
3953                 return;
3954
3955         connector->dpms = mode;
3956
3957         /* Only need to change hw state when actually enabled */
3958         if (encoder->base.crtc)
3959                 intel_encoder_dpms(encoder, mode);
3960         else
3961                 WARN_ON(encoder->connectors_active != false);
3962
3963         intel_modeset_check_state(connector->dev);
3964 }
3965
3966 /* Simple connector->get_hw_state implementation for encoders that support only
3967  * one connector and no cloning and hence the encoder state determines the state
3968  * of the connector. */
3969 bool intel_connector_get_hw_state(struct intel_connector *connector)
3970 {
3971         enum pipe pipe = 0;
3972         struct intel_encoder *encoder = connector->encoder;
3973
3974         return encoder->get_hw_state(encoder, &pipe);
3975 }
3976
3977 static bool intel_crtc_compute_config(struct drm_crtc *crtc,
3978                                       struct intel_crtc_config *pipe_config)
3979 {
3980         struct drm_device *dev = crtc->dev;
3981         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
3982
3983         if (HAS_PCH_SPLIT(dev)) {
3984                 /* FDI link clock is fixed at 2.7G */
3985                 if (pipe_config->requested_mode.clock * 3
3986                     > IRONLAKE_FDI_FREQ * 4)
3987                         return false;
3988         }
3989
3990         /* All interlaced capable intel hw wants timings in frames. Note though
3991          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3992          * timings, so we need to be careful not to clobber these.*/
3993         if (!pipe_config->timings_set)
3994                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3995
3996         /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3997          * with a hsync front porch of 0.
3998          */
3999         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4000                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4001                 return false;
4002
4003         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4004                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4005         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4006                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4007                  * for lvds. */
4008                 pipe_config->pipe_bpp = 8*3;
4009         }
4010
4011         return true;
4012 }
4013
4014 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4015 {
4016         return 400000; /* FIXME */
4017 }
4018
4019 static int i945_get_display_clock_speed(struct drm_device *dev)
4020 {
4021         return 400000;
4022 }
4023
4024 static int i915_get_display_clock_speed(struct drm_device *dev)
4025 {
4026         return 333000;
4027 }
4028
4029 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4030 {
4031         return 200000;
4032 }
4033
4034 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4035 {
4036         u16 gcfgc = 0;
4037
4038         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4039
4040         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4041                 return 133000;
4042         else {
4043                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4044                 case GC_DISPLAY_CLOCK_333_MHZ:
4045                         return 333000;
4046                 default:
4047                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4048                         return 190000;
4049                 }
4050         }
4051 }
4052
4053 static int i865_get_display_clock_speed(struct drm_device *dev)
4054 {
4055         return 266000;
4056 }
4057
4058 static int i855_get_display_clock_speed(struct drm_device *dev)
4059 {
4060         u16 hpllcc = 0;
4061         /* Assume that the hardware is in the high speed state.  This
4062          * should be the default.
4063          */
4064         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4065         case GC_CLOCK_133_200:
4066         case GC_CLOCK_100_200:
4067                 return 200000;
4068         case GC_CLOCK_166_250:
4069                 return 250000;
4070         case GC_CLOCK_100_133:
4071                 return 133000;
4072         }
4073
4074         /* Shouldn't happen */
4075         return 0;
4076 }
4077
4078 static int i830_get_display_clock_speed(struct drm_device *dev)
4079 {
4080         return 133000;
4081 }
4082
4083 static void
4084 intel_reduce_ratio(uint32_t *num, uint32_t *den)
4085 {
4086         while (*num > 0xffffff || *den > 0xffffff) {
4087                 *num >>= 1;
4088                 *den >>= 1;
4089         }
4090 }
4091
4092 void
4093 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4094                        int pixel_clock, int link_clock,
4095                        struct intel_link_m_n *m_n)
4096 {
4097         m_n->tu = 64;
4098         m_n->gmch_m = bits_per_pixel * pixel_clock;
4099         m_n->gmch_n = link_clock * nlanes * 8;
4100         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4101         m_n->link_m = pixel_clock;
4102         m_n->link_n = link_clock;
4103         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
4104 }
4105
4106 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4107 {
4108         if (i915_panel_use_ssc >= 0)
4109                 return i915_panel_use_ssc != 0;
4110         return dev_priv->lvds_use_ssc
4111                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4112 }
4113
4114 static int vlv_get_refclk(struct drm_crtc *crtc)
4115 {
4116         struct drm_device *dev = crtc->dev;
4117         struct drm_i915_private *dev_priv = dev->dev_private;
4118         int refclk = 27000; /* for DP & HDMI */
4119
4120         return 100000; /* only one validated so far */
4121
4122         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4123                 refclk = 96000;
4124         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4125                 if (intel_panel_use_ssc(dev_priv))
4126                         refclk = 100000;
4127                 else
4128                         refclk = 96000;
4129         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4130                 refclk = 100000;
4131         }
4132
4133         return refclk;
4134 }
4135
4136 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4137 {
4138         struct drm_device *dev = crtc->dev;
4139         struct drm_i915_private *dev_priv = dev->dev_private;
4140         int refclk;
4141
4142         if (IS_VALLEYVIEW(dev)) {
4143                 refclk = vlv_get_refclk(crtc);
4144         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4145             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4146                 refclk = dev_priv->lvds_ssc_freq * 1000;
4147                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4148                               refclk / 1000);
4149         } else if (!IS_GEN2(dev)) {
4150                 refclk = 96000;
4151         } else {
4152                 refclk = 48000;
4153         }
4154
4155         return refclk;
4156 }
4157
4158 static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc *crtc)
4159 {
4160         unsigned dotclock = crtc->config.adjusted_mode.clock;
4161         struct dpll *clock = &crtc->config.dpll;
4162
4163         /* SDVO TV has fixed PLL values depend on its clock range,
4164            this mirrors vbios setting. */
4165         if (dotclock >= 100000 && dotclock < 140500) {
4166                 clock->p1 = 2;
4167                 clock->p2 = 10;
4168                 clock->n = 3;
4169                 clock->m1 = 16;
4170                 clock->m2 = 8;
4171         } else if (dotclock >= 140500 && dotclock <= 200000) {
4172                 clock->p1 = 1;
4173                 clock->p2 = 10;
4174                 clock->n = 6;
4175                 clock->m1 = 12;
4176                 clock->m2 = 8;
4177         }
4178
4179         crtc->config.clock_set = true;
4180 }
4181
4182 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4183 {
4184         return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2;
4185 }
4186
4187 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4188 {
4189         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4190 }
4191
4192 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4193                                      intel_clock_t *reduced_clock)
4194 {
4195         struct drm_device *dev = crtc->base.dev;
4196         struct drm_i915_private *dev_priv = dev->dev_private;
4197         int pipe = crtc->pipe;
4198         u32 fp, fp2 = 0;
4199
4200         if (IS_PINEVIEW(dev)) {
4201                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4202                 if (reduced_clock)
4203                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4204         } else {
4205                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4206                 if (reduced_clock)
4207                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4208         }
4209
4210         I915_WRITE(FP0(pipe), fp);
4211
4212         crtc->lowfreq_avail = false;
4213         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4214             reduced_clock && i915_powersave) {
4215                 I915_WRITE(FP1(pipe), fp2);
4216                 crtc->lowfreq_avail = true;
4217         } else {
4218                 I915_WRITE(FP1(pipe), fp);
4219         }
4220 }
4221
4222 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4223 {
4224         u32 reg_val;
4225
4226         /*
4227          * PLLB opamp always calibrates to max value of 0x3f, force enable it
4228          * and set it to a reasonable value instead.
4229          */
4230         reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4231         reg_val &= 0xffffff00;
4232         reg_val |= 0x00000030;
4233         intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4234
4235         reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4236         reg_val &= 0x8cffffff;
4237         reg_val = 0x8c000000;
4238         intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4239
4240         reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4241         reg_val &= 0xffffff00;
4242         intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4243
4244         reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4245         reg_val &= 0x00ffffff;
4246         reg_val |= 0xb0000000;
4247         intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4248 }
4249
4250 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4251 {
4252         if (crtc->config.has_pch_encoder)
4253                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4254         else
4255                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4256 }
4257
4258 static void vlv_update_pll(struct intel_crtc *crtc)
4259 {
4260         struct drm_device *dev = crtc->base.dev;
4261         struct drm_i915_private *dev_priv = dev->dev_private;
4262         struct drm_display_mode *adjusted_mode =
4263                 &crtc->config.adjusted_mode;
4264         struct intel_encoder *encoder;
4265         int pipe = crtc->pipe;
4266         u32 dpll, mdiv;
4267         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4268         bool is_hdmi;
4269         u32 coreclk, reg_val, dpll_md;
4270
4271         mutex_lock(&dev_priv->dpio_lock);
4272
4273         is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4274
4275         bestn = crtc->config.dpll.n;
4276         bestm1 = crtc->config.dpll.m1;
4277         bestm2 = crtc->config.dpll.m2;
4278         bestp1 = crtc->config.dpll.p1;
4279         bestp2 = crtc->config.dpll.p2;
4280
4281         /* See eDP HDMI DPIO driver vbios notes doc */
4282
4283         /* PLL B needs special handling */
4284         if (pipe)
4285                 vlv_pllb_recal_opamp(dev_priv);
4286
4287         /* Set up Tx target for periodic Rcomp update */
4288         intel_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4289
4290         /* Disable target IRef on PLL */
4291         reg_val = intel_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4292         reg_val &= 0x00ffffff;
4293         intel_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4294
4295         /* Disable fast lock */
4296         intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4297
4298         /* Set idtafcrecal before PLL is enabled */
4299         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4300         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4301         mdiv |= ((bestn << DPIO_N_SHIFT));
4302         mdiv |= (1 << DPIO_K_SHIFT);
4303         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI) ||
4304             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4305             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4306                 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4307         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4308
4309         mdiv |= DPIO_ENABLE_CALIBRATION;
4310         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4311
4312         /* Set HBR and RBR LPF coefficients */
4313         if (adjusted_mode->clock == 162000 ||
4314             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4315                 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4316                                  0x005f0021);
4317         else
4318                 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4319                                  0x00d0000f);
4320
4321         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4322             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4323                 /* Use SSC source */
4324                 if (!pipe)
4325                         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4326                                          0x0df40000);
4327                 else
4328                         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4329                                          0x0df70000);
4330         } else { /* HDMI or VGA */
4331                 /* Use bend source */
4332                 if (!pipe)
4333                         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4334                                          0x0df70000);
4335                 else
4336                         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4337                                          0x0df40000);
4338         }
4339
4340         coreclk = intel_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4341         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4342         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4343             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4344                 coreclk |= 0x01000000;
4345         intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4346
4347         intel_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4348
4349         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4350                 if (encoder->pre_pll_enable)
4351                         encoder->pre_pll_enable(encoder);
4352
4353         /* Enable DPIO clock input */
4354         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4355                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4356         if (pipe)
4357                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4358
4359         dpll |= DPLL_VCO_ENABLE;
4360         I915_WRITE(DPLL(pipe), dpll);
4361         POSTING_READ(DPLL(pipe));
4362         udelay(150);
4363
4364         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4365                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4366
4367         dpll_md = 0;
4368         if (crtc->config.pixel_multiplier > 1) {
4369                 dpll_md = (crtc->config.pixel_multiplier - 1)
4370                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4371         }
4372         I915_WRITE(DPLL_MD(pipe), dpll_md);
4373         POSTING_READ(DPLL_MD(pipe));
4374
4375         if (crtc->config.has_dp_encoder)
4376                 intel_dp_set_m_n(crtc);
4377
4378         mutex_unlock(&dev_priv->dpio_lock);
4379 }
4380
4381 static void i9xx_update_pll(struct intel_crtc *crtc,
4382                             intel_clock_t *reduced_clock,
4383                             int num_connectors)
4384 {
4385         struct drm_device *dev = crtc->base.dev;
4386         struct drm_i915_private *dev_priv = dev->dev_private;
4387         struct intel_encoder *encoder;
4388         int pipe = crtc->pipe;
4389         u32 dpll;
4390         bool is_sdvo;
4391         struct dpll *clock = &crtc->config.dpll;
4392
4393         i9xx_update_pll_dividers(crtc, reduced_clock);
4394
4395         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4396                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4397
4398         dpll = DPLL_VGA_MODE_DIS;
4399
4400         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4401                 dpll |= DPLLB_MODE_LVDS;
4402         else
4403                 dpll |= DPLLB_MODE_DAC_SERIAL;
4404
4405         if ((crtc->config.pixel_multiplier > 1) &&
4406             (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
4407                 dpll |= (crtc->config.pixel_multiplier - 1)
4408                         << SDVO_MULTIPLIER_SHIFT_HIRES;
4409         }
4410
4411         if (is_sdvo)
4412                 dpll |= DPLL_DVO_HIGH_SPEED;
4413
4414         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4415                 dpll |= DPLL_DVO_HIGH_SPEED;
4416
4417         /* compute bitmask from p1 value */
4418         if (IS_PINEVIEW(dev))
4419                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4420         else {
4421                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4422                 if (IS_G4X(dev) && reduced_clock)
4423                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4424         }
4425         switch (clock->p2) {
4426         case 5:
4427                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4428                 break;
4429         case 7:
4430                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4431                 break;
4432         case 10:
4433                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4434                 break;
4435         case 14:
4436                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4437                 break;
4438         }
4439         if (INTEL_INFO(dev)->gen >= 4)
4440                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4441
4442         if (is_sdvo && intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
4443                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4444         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
4445                 /* XXX: just matching BIOS for now */
4446                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4447                 dpll |= 3;
4448         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4449                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4450                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4451         else
4452                 dpll |= PLL_REF_INPUT_DREFCLK;
4453
4454         dpll |= DPLL_VCO_ENABLE;
4455         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4456         POSTING_READ(DPLL(pipe));
4457         udelay(150);
4458
4459         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4460                 if (encoder->pre_pll_enable)
4461                         encoder->pre_pll_enable(encoder);
4462
4463         if (crtc->config.has_dp_encoder)
4464                 intel_dp_set_m_n(crtc);
4465
4466         I915_WRITE(DPLL(pipe), dpll);
4467
4468         /* Wait for the clocks to stabilize. */
4469         POSTING_READ(DPLL(pipe));
4470         udelay(150);
4471
4472         if (INTEL_INFO(dev)->gen >= 4) {
4473                 u32 dpll_md = 0;
4474                 if (crtc->config.pixel_multiplier > 1) {
4475                         dpll_md = (crtc->config.pixel_multiplier - 1)
4476                                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4477                 }
4478                 I915_WRITE(DPLL_MD(pipe), dpll_md);
4479         } else {
4480                 /* The pixel multiplier can only be updated once the
4481                  * DPLL is enabled and the clocks are stable.
4482                  *
4483                  * So write it again.
4484                  */
4485                 I915_WRITE(DPLL(pipe), dpll);
4486         }
4487 }
4488
4489 static void i8xx_update_pll(struct intel_crtc *crtc,
4490                             struct drm_display_mode *adjusted_mode,
4491                             intel_clock_t *reduced_clock,
4492                             int num_connectors)
4493 {
4494         struct drm_device *dev = crtc->base.dev;
4495         struct drm_i915_private *dev_priv = dev->dev_private;
4496         struct intel_encoder *encoder;
4497         int pipe = crtc->pipe;
4498         u32 dpll;
4499         struct dpll *clock = &crtc->config.dpll;
4500
4501         i9xx_update_pll_dividers(crtc, reduced_clock);
4502
4503         dpll = DPLL_VGA_MODE_DIS;
4504
4505         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4506                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4507         } else {
4508                 if (clock->p1 == 2)
4509                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4510                 else
4511                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4512                 if (clock->p2 == 4)
4513                         dpll |= PLL_P2_DIVIDE_BY_4;
4514         }
4515
4516         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4517                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4518                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4519         else
4520                 dpll |= PLL_REF_INPUT_DREFCLK;
4521
4522         dpll |= DPLL_VCO_ENABLE;
4523         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4524         POSTING_READ(DPLL(pipe));
4525         udelay(150);
4526
4527         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4528                 if (encoder->pre_pll_enable)
4529                         encoder->pre_pll_enable(encoder);
4530
4531         I915_WRITE(DPLL(pipe), dpll);
4532
4533         /* Wait for the clocks to stabilize. */
4534         POSTING_READ(DPLL(pipe));
4535         udelay(150);
4536
4537         /* The pixel multiplier can only be updated once the
4538          * DPLL is enabled and the clocks are stable.
4539          *
4540          * So write it again.
4541          */
4542         I915_WRITE(DPLL(pipe), dpll);
4543 }
4544
4545 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4546                                    struct drm_display_mode *mode,
4547                                    struct drm_display_mode *adjusted_mode)
4548 {
4549         struct drm_device *dev = intel_crtc->base.dev;
4550         struct drm_i915_private *dev_priv = dev->dev_private;
4551         enum pipe pipe = intel_crtc->pipe;
4552         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4553         uint32_t vsyncshift;
4554
4555         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4556                 /* the chip adds 2 halflines automatically */
4557                 adjusted_mode->crtc_vtotal -= 1;
4558                 adjusted_mode->crtc_vblank_end -= 1;
4559                 vsyncshift = adjusted_mode->crtc_hsync_start
4560                              - adjusted_mode->crtc_htotal / 2;
4561         } else {
4562                 vsyncshift = 0;
4563         }
4564
4565         if (INTEL_INFO(dev)->gen > 3)
4566                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4567
4568         I915_WRITE(HTOTAL(cpu_transcoder),
4569                    (adjusted_mode->crtc_hdisplay - 1) |
4570                    ((adjusted_mode->crtc_htotal - 1) << 16));
4571         I915_WRITE(HBLANK(cpu_transcoder),
4572                    (adjusted_mode->crtc_hblank_start - 1) |
4573                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4574         I915_WRITE(HSYNC(cpu_transcoder),
4575                    (adjusted_mode->crtc_hsync_start - 1) |
4576                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4577
4578         I915_WRITE(VTOTAL(cpu_transcoder),
4579                    (adjusted_mode->crtc_vdisplay - 1) |
4580                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4581         I915_WRITE(VBLANK(cpu_transcoder),
4582                    (adjusted_mode->crtc_vblank_start - 1) |
4583                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4584         I915_WRITE(VSYNC(cpu_transcoder),
4585                    (adjusted_mode->crtc_vsync_start - 1) |
4586                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4587
4588         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4589          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4590          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4591          * bits. */
4592         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4593             (pipe == PIPE_B || pipe == PIPE_C))
4594                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4595
4596         /* pipesrc controls the size that is scaled from, which should
4597          * always be the user's requested size.
4598          */
4599         I915_WRITE(PIPESRC(pipe),
4600                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4601 }
4602
4603 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4604 {
4605         struct drm_device *dev = intel_crtc->base.dev;
4606         struct drm_i915_private *dev_priv = dev->dev_private;
4607         uint32_t pipeconf;
4608
4609         pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4610
4611         if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4612                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4613                  * core speed.
4614                  *
4615                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4616                  * pipe == 0 check?
4617                  */
4618                 if (intel_crtc->config.requested_mode.clock >
4619                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4620                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4621                 else
4622                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4623         }
4624
4625         /* only g4x and later have fancy bpc/dither controls */
4626         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4627                 pipeconf &= ~(PIPECONF_BPC_MASK |
4628                               PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4629
4630                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4631                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4632                         pipeconf |= PIPECONF_DITHER_EN |
4633                                     PIPECONF_DITHER_TYPE_SP;
4634
4635                 switch (intel_crtc->config.pipe_bpp) {
4636                 case 18:
4637                         pipeconf |= PIPECONF_6BPC;
4638                         break;
4639                 case 24:
4640                         pipeconf |= PIPECONF_8BPC;
4641                         break;
4642                 case 30:
4643                         pipeconf |= PIPECONF_10BPC;
4644                         break;
4645                 default:
4646                         /* Case prevented by intel_choose_pipe_bpp_dither. */
4647                         BUG();
4648                 }
4649         }
4650
4651         if (HAS_PIPE_CXSR(dev)) {
4652                 if (intel_crtc->lowfreq_avail) {
4653                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4654                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4655                 } else {
4656                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4657                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4658                 }
4659         }
4660
4661         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4662         if (!IS_GEN2(dev) &&
4663             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4664                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4665         else
4666                 pipeconf |= PIPECONF_PROGRESSIVE;
4667
4668         if (IS_VALLEYVIEW(dev)) {
4669                 if (intel_crtc->config.limited_color_range)
4670                         pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4671                 else
4672                         pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4673         }
4674
4675         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4676         POSTING_READ(PIPECONF(intel_crtc->pipe));
4677 }
4678
4679 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4680                               int x, int y,
4681                               struct drm_framebuffer *fb)
4682 {
4683         struct drm_device *dev = crtc->dev;
4684         struct drm_i915_private *dev_priv = dev->dev_private;
4685         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4686         struct drm_display_mode *adjusted_mode =
4687                 &intel_crtc->config.adjusted_mode;
4688         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4689         int pipe = intel_crtc->pipe;
4690         int plane = intel_crtc->plane;
4691         int refclk, num_connectors = 0;
4692         intel_clock_t clock, reduced_clock;
4693         u32 dspcntr;
4694         bool ok, has_reduced_clock = false, is_sdvo = false;
4695         bool is_lvds = false, is_tv = false;
4696         struct intel_encoder *encoder;
4697         const intel_limit_t *limit;
4698         int ret;
4699
4700         for_each_encoder_on_crtc(dev, crtc, encoder) {
4701                 switch (encoder->type) {
4702                 case INTEL_OUTPUT_LVDS:
4703                         is_lvds = true;
4704                         break;
4705                 case INTEL_OUTPUT_SDVO:
4706                 case INTEL_OUTPUT_HDMI:
4707                         is_sdvo = true;
4708                         if (encoder->needs_tv_clock)
4709                                 is_tv = true;
4710                         break;
4711                 case INTEL_OUTPUT_TVOUT:
4712                         is_tv = true;
4713                         break;
4714                 }
4715
4716                 num_connectors++;
4717         }
4718
4719         refclk = i9xx_get_refclk(crtc, num_connectors);
4720
4721         /*
4722          * Returns a set of divisors for the desired target clock with the given
4723          * refclk, or FALSE.  The returned values represent the clock equation:
4724          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4725          */
4726         limit = intel_limit(crtc, refclk);
4727         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4728                              &clock);
4729         if (!ok) {
4730                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4731                 return -EINVAL;
4732         }
4733
4734         /* Ensure that the cursor is valid for the new mode before changing... */
4735         intel_crtc_update_cursor(crtc, true);
4736
4737         if (is_lvds && dev_priv->lvds_downclock_avail) {
4738                 /*
4739                  * Ensure we match the reduced clock's P to the target clock.
4740                  * If the clocks don't match, we can't switch the display clock
4741                  * by using the FP0/FP1. In such case we will disable the LVDS
4742                  * downclock feature.
4743                 */
4744                 has_reduced_clock = limit->find_pll(limit, crtc,
4745                                                     dev_priv->lvds_downclock,
4746                                                     refclk,
4747                                                     &clock,
4748                                                     &reduced_clock);
4749         }
4750         /* Compat-code for transition, will disappear. */
4751         if (!intel_crtc->config.clock_set) {
4752                 intel_crtc->config.dpll.n = clock.n;
4753                 intel_crtc->config.dpll.m1 = clock.m1;
4754                 intel_crtc->config.dpll.m2 = clock.m2;
4755                 intel_crtc->config.dpll.p1 = clock.p1;
4756                 intel_crtc->config.dpll.p2 = clock.p2;
4757         }
4758
4759         if (is_sdvo && is_tv)
4760                 i9xx_adjust_sdvo_tv_clock(intel_crtc);
4761
4762         if (IS_GEN2(dev))
4763                 i8xx_update_pll(intel_crtc, adjusted_mode,
4764                                 has_reduced_clock ? &reduced_clock : NULL,
4765                                 num_connectors);
4766         else if (IS_VALLEYVIEW(dev))
4767                 vlv_update_pll(intel_crtc);
4768         else
4769                 i9xx_update_pll(intel_crtc,
4770                                 has_reduced_clock ? &reduced_clock : NULL,
4771                                 num_connectors);
4772
4773         /* Set up the display plane register */
4774         dspcntr = DISPPLANE_GAMMA_ENABLE;
4775
4776         if (!IS_VALLEYVIEW(dev)) {
4777                 if (pipe == 0)
4778                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4779                 else
4780                         dspcntr |= DISPPLANE_SEL_PIPE_B;
4781         }
4782
4783         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
4784         drm_mode_debug_printmodeline(mode);
4785
4786         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4787
4788         /* pipesrc and dspsize control the size that is scaled from,
4789          * which should always be the user's requested size.
4790          */
4791         I915_WRITE(DSPSIZE(plane),
4792                    ((mode->vdisplay - 1) << 16) |
4793                    (mode->hdisplay - 1));
4794         I915_WRITE(DSPPOS(plane), 0);
4795
4796         i9xx_set_pipeconf(intel_crtc);
4797
4798         I915_WRITE(DSPCNTR(plane), dspcntr);
4799         POSTING_READ(DSPCNTR(plane));
4800
4801         ret = intel_pipe_set_base(crtc, x, y, fb);
4802
4803         intel_update_watermarks(dev);
4804
4805         return ret;
4806 }
4807
4808 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4809                                  struct intel_crtc_config *pipe_config)
4810 {
4811         struct drm_device *dev = crtc->base.dev;
4812         struct drm_i915_private *dev_priv = dev->dev_private;
4813         uint32_t tmp;
4814
4815         tmp = I915_READ(PIPECONF(crtc->pipe));
4816         if (!(tmp & PIPECONF_ENABLE))
4817                 return false;
4818
4819         return true;
4820 }
4821
4822 static void ironlake_init_pch_refclk(struct drm_device *dev)
4823 {
4824         struct drm_i915_private *dev_priv = dev->dev_private;
4825         struct drm_mode_config *mode_config = &dev->mode_config;
4826         struct intel_encoder *encoder;
4827         u32 val, final;
4828         bool has_lvds = false;
4829         bool has_cpu_edp = false;
4830         bool has_pch_edp = false;
4831         bool has_panel = false;
4832         bool has_ck505 = false;
4833         bool can_ssc = false;
4834
4835         /* We need to take the global config into account */
4836         list_for_each_entry(encoder, &mode_config->encoder_list,
4837                             base.head) {
4838                 switch (encoder->type) {
4839                 case INTEL_OUTPUT_LVDS:
4840                         has_panel = true;
4841                         has_lvds = true;
4842                         break;
4843                 case INTEL_OUTPUT_EDP:
4844                         has_panel = true;
4845                         if (intel_encoder_is_pch_edp(&encoder->base))
4846                                 has_pch_edp = true;
4847                         else
4848                                 has_cpu_edp = true;
4849                         break;
4850                 }
4851         }
4852
4853         if (HAS_PCH_IBX(dev)) {
4854                 has_ck505 = dev_priv->display_clock_mode;
4855                 can_ssc = has_ck505;
4856         } else {
4857                 has_ck505 = false;
4858                 can_ssc = true;
4859         }
4860
4861         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4862                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4863                       has_ck505);
4864
4865         /* Ironlake: try to setup display ref clock before DPLL
4866          * enabling. This is only under driver's control after
4867          * PCH B stepping, previous chipset stepping should be
4868          * ignoring this setting.
4869          */
4870         val = I915_READ(PCH_DREF_CONTROL);
4871
4872         /* As we must carefully and slowly disable/enable each source in turn,
4873          * compute the final state we want first and check if we need to
4874          * make any changes at all.
4875          */
4876         final = val;
4877         final &= ~DREF_NONSPREAD_SOURCE_MASK;
4878         if (has_ck505)
4879                 final |= DREF_NONSPREAD_CK505_ENABLE;
4880         else
4881                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
4882
4883         final &= ~DREF_SSC_SOURCE_MASK;
4884         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4885         final &= ~DREF_SSC1_ENABLE;
4886
4887         if (has_panel) {
4888                 final |= DREF_SSC_SOURCE_ENABLE;
4889
4890                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4891                         final |= DREF_SSC1_ENABLE;
4892
4893                 if (has_cpu_edp) {
4894                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
4895                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4896                         else
4897                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4898                 } else
4899                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4900         } else {
4901                 final |= DREF_SSC_SOURCE_DISABLE;
4902                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4903         }
4904
4905         if (final == val)
4906                 return;
4907
4908         /* Always enable nonspread source */
4909         val &= ~DREF_NONSPREAD_SOURCE_MASK;
4910
4911         if (has_ck505)
4912                 val |= DREF_NONSPREAD_CK505_ENABLE;
4913         else
4914                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
4915
4916         if (has_panel) {
4917                 val &= ~DREF_SSC_SOURCE_MASK;
4918                 val |= DREF_SSC_SOURCE_ENABLE;
4919
4920                 /* SSC must be turned on before enabling the CPU output  */
4921                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4922                         DRM_DEBUG_KMS("Using SSC on panel\n");
4923                         val |= DREF_SSC1_ENABLE;
4924                 } else
4925                         val &= ~DREF_SSC1_ENABLE;
4926
4927                 /* Get SSC going before enabling the outputs */
4928                 I915_WRITE(PCH_DREF_CONTROL, val);
4929                 POSTING_READ(PCH_DREF_CONTROL);
4930                 udelay(200);
4931
4932                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4933
4934                 /* Enable CPU source on CPU attached eDP */
4935                 if (has_cpu_edp) {
4936                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4937                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4938                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4939                         }
4940                         else
4941                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4942                 } else
4943                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4944
4945                 I915_WRITE(PCH_DREF_CONTROL, val);
4946                 POSTING_READ(PCH_DREF_CONTROL);
4947                 udelay(200);
4948         } else {
4949                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4950
4951                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4952
4953                 /* Turn off CPU output */
4954                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4955
4956                 I915_WRITE(PCH_DREF_CONTROL, val);
4957                 POSTING_READ(PCH_DREF_CONTROL);
4958                 udelay(200);
4959
4960                 /* Turn off the SSC source */
4961                 val &= ~DREF_SSC_SOURCE_MASK;
4962                 val |= DREF_SSC_SOURCE_DISABLE;
4963
4964                 /* Turn off SSC1 */
4965                 val &= ~DREF_SSC1_ENABLE;
4966
4967                 I915_WRITE(PCH_DREF_CONTROL, val);
4968                 POSTING_READ(PCH_DREF_CONTROL);
4969                 udelay(200);
4970         }
4971
4972         BUG_ON(val != final);
4973 }
4974
4975 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4976 static void lpt_init_pch_refclk(struct drm_device *dev)
4977 {
4978         struct drm_i915_private *dev_priv = dev->dev_private;
4979         struct drm_mode_config *mode_config = &dev->mode_config;
4980         struct intel_encoder *encoder;
4981         bool has_vga = false;
4982         bool is_sdv = false;
4983         u32 tmp;
4984
4985         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4986                 switch (encoder->type) {
4987                 case INTEL_OUTPUT_ANALOG:
4988                         has_vga = true;
4989                         break;
4990                 }
4991         }
4992
4993         if (!has_vga)
4994                 return;
4995
4996         mutex_lock(&dev_priv->dpio_lock);
4997
4998         /* XXX: Rip out SDV support once Haswell ships for real. */
4999         if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5000                 is_sdv = true;
5001
5002         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5003         tmp &= ~SBI_SSCCTL_DISABLE;
5004         tmp |= SBI_SSCCTL_PATHALT;
5005         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5006
5007         udelay(24);
5008
5009         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5010         tmp &= ~SBI_SSCCTL_PATHALT;
5011         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5012
5013         if (!is_sdv) {
5014                 tmp = I915_READ(SOUTH_CHICKEN2);
5015                 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5016                 I915_WRITE(SOUTH_CHICKEN2, tmp);
5017
5018                 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5019                                        FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5020                         DRM_ERROR("FDI mPHY reset assert timeout\n");
5021
5022                 tmp = I915_READ(SOUTH_CHICKEN2);
5023                 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5024                 I915_WRITE(SOUTH_CHICKEN2, tmp);
5025
5026                 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5027                                         FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5028                                        100))
5029                         DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5030         }
5031
5032         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5033         tmp &= ~(0xFF << 24);
5034         tmp |= (0x12 << 24);
5035         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5036
5037         if (is_sdv) {
5038                 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5039                 tmp |= 0x7FFF;
5040                 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5041         }
5042
5043         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5044         tmp |= (1 << 11);
5045         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5046
5047         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5048         tmp |= (1 << 11);
5049         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5050
5051         if (is_sdv) {
5052                 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5053                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5054                 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5055
5056                 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5057                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5058                 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5059
5060                 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5061                 tmp |= (0x3F << 8);
5062                 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5063
5064                 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5065                 tmp |= (0x3F << 8);
5066                 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5067         }
5068
5069         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5070         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5071         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5072
5073         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5074         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5075         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5076
5077         if (!is_sdv) {
5078                 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5079                 tmp &= ~(7 << 13);
5080                 tmp |= (5 << 13);
5081                 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5082
5083                 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5084                 tmp &= ~(7 << 13);
5085                 tmp |= (5 << 13);
5086                 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5087         }
5088
5089         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5090         tmp &= ~0xFF;
5091         tmp |= 0x1C;
5092         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5093
5094         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5095         tmp &= ~0xFF;
5096         tmp |= 0x1C;
5097         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5098
5099         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5100         tmp &= ~(0xFF << 16);
5101         tmp |= (0x1C << 16);
5102         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5103
5104         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5105         tmp &= ~(0xFF << 16);
5106         tmp |= (0x1C << 16);
5107         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5108
5109         if (!is_sdv) {
5110                 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5111                 tmp |= (1 << 27);
5112                 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5113
5114                 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5115                 tmp |= (1 << 27);
5116                 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5117
5118                 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5119                 tmp &= ~(0xF << 28);
5120                 tmp |= (4 << 28);
5121                 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5122
5123                 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5124                 tmp &= ~(0xF << 28);
5125                 tmp |= (4 << 28);
5126                 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5127         }
5128
5129         /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5130         tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5131         tmp |= SBI_DBUFF0_ENABLE;
5132         intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5133
5134         mutex_unlock(&dev_priv->dpio_lock);
5135 }
5136
5137 /*
5138  * Initialize reference clocks when the driver loads
5139  */
5140 void intel_init_pch_refclk(struct drm_device *dev)
5141 {
5142         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5143                 ironlake_init_pch_refclk(dev);
5144         else if (HAS_PCH_LPT(dev))
5145                 lpt_init_pch_refclk(dev);
5146 }
5147
5148 static int ironlake_get_refclk(struct drm_crtc *crtc)
5149 {
5150         struct drm_device *dev = crtc->dev;
5151         struct drm_i915_private *dev_priv = dev->dev_private;
5152         struct intel_encoder *encoder;
5153         struct intel_encoder *edp_encoder = NULL;
5154         int num_connectors = 0;
5155         bool is_lvds = false;
5156
5157         for_each_encoder_on_crtc(dev, crtc, encoder) {
5158                 switch (encoder->type) {
5159                 case INTEL_OUTPUT_LVDS:
5160                         is_lvds = true;
5161                         break;
5162                 case INTEL_OUTPUT_EDP:
5163                         edp_encoder = encoder;
5164                         break;
5165                 }
5166                 num_connectors++;
5167         }
5168
5169         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5170                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5171                               dev_priv->lvds_ssc_freq);
5172                 return dev_priv->lvds_ssc_freq * 1000;
5173         }
5174
5175         return 120000;
5176 }
5177
5178 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5179 {
5180         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5181         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5182         int pipe = intel_crtc->pipe;
5183         uint32_t val;
5184
5185         val = I915_READ(PIPECONF(pipe));
5186
5187         val &= ~PIPECONF_BPC_MASK;
5188         switch (intel_crtc->config.pipe_bpp) {
5189         case 18:
5190                 val |= PIPECONF_6BPC;
5191                 break;
5192         case 24:
5193                 val |= PIPECONF_8BPC;
5194                 break;
5195         case 30:
5196                 val |= PIPECONF_10BPC;
5197                 break;
5198         case 36:
5199                 val |= PIPECONF_12BPC;
5200                 break;
5201         default:
5202                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5203                 BUG();
5204         }
5205
5206         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5207         if (intel_crtc->config.dither)
5208                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5209
5210         val &= ~PIPECONF_INTERLACE_MASK;
5211         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5212                 val |= PIPECONF_INTERLACED_ILK;
5213         else
5214                 val |= PIPECONF_PROGRESSIVE;
5215
5216         if (intel_crtc->config.limited_color_range)
5217                 val |= PIPECONF_COLOR_RANGE_SELECT;
5218         else
5219                 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5220
5221         I915_WRITE(PIPECONF(pipe), val);
5222         POSTING_READ(PIPECONF(pipe));
5223 }
5224
5225 /*
5226  * Set up the pipe CSC unit.
5227  *
5228  * Currently only full range RGB to limited range RGB conversion
5229  * is supported, but eventually this should handle various
5230  * RGB<->YCbCr scenarios as well.
5231  */
5232 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5233 {
5234         struct drm_device *dev = crtc->dev;
5235         struct drm_i915_private *dev_priv = dev->dev_private;
5236         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5237         int pipe = intel_crtc->pipe;
5238         uint16_t coeff = 0x7800; /* 1.0 */
5239
5240         /*
5241          * TODO: Check what kind of values actually come out of the pipe
5242          * with these coeff/postoff values and adjust to get the best
5243          * accuracy. Perhaps we even need to take the bpc value into
5244          * consideration.
5245          */
5246
5247         if (intel_crtc->config.limited_color_range)
5248                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5249
5250         /*
5251          * GY/GU and RY/RU should be the other way around according
5252          * to BSpec, but reality doesn't agree. Just set them up in
5253          * a way that results in the correct picture.
5254          */
5255         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5256         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5257
5258         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5259         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5260
5261         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5262         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5263
5264         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5265         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5266         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5267
5268         if (INTEL_INFO(dev)->gen > 6) {
5269                 uint16_t postoff = 0;
5270
5271                 if (intel_crtc->config.limited_color_range)
5272                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
5273
5274                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5275                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5276                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5277
5278                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5279         } else {
5280                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5281
5282                 if (intel_crtc->config.limited_color_range)
5283                         mode |= CSC_BLACK_SCREEN_OFFSET;
5284
5285                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5286         }
5287 }
5288
5289 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5290 {
5291         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5292         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5293         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5294         uint32_t val;
5295
5296         val = I915_READ(PIPECONF(cpu_transcoder));
5297
5298         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5299         if (intel_crtc->config.dither)
5300                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5301
5302         val &= ~PIPECONF_INTERLACE_MASK_HSW;
5303         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5304                 val |= PIPECONF_INTERLACED_ILK;
5305         else
5306                 val |= PIPECONF_PROGRESSIVE;
5307
5308         I915_WRITE(PIPECONF(cpu_transcoder), val);
5309         POSTING_READ(PIPECONF(cpu_transcoder));
5310 }
5311
5312 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5313                                     struct drm_display_mode *adjusted_mode,
5314                                     intel_clock_t *clock,
5315                                     bool *has_reduced_clock,
5316                                     intel_clock_t *reduced_clock)
5317 {
5318         struct drm_device *dev = crtc->dev;
5319         struct drm_i915_private *dev_priv = dev->dev_private;
5320         struct intel_encoder *intel_encoder;
5321         int refclk;
5322         const intel_limit_t *limit;
5323         bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5324
5325         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5326                 switch (intel_encoder->type) {
5327                 case INTEL_OUTPUT_LVDS:
5328                         is_lvds = true;
5329                         break;
5330                 case INTEL_OUTPUT_SDVO:
5331                 case INTEL_OUTPUT_HDMI:
5332                         is_sdvo = true;
5333                         if (intel_encoder->needs_tv_clock)
5334                                 is_tv = true;
5335                         break;
5336                 case INTEL_OUTPUT_TVOUT:
5337                         is_tv = true;
5338                         break;
5339                 }
5340         }
5341
5342         refclk = ironlake_get_refclk(crtc);
5343
5344         /*
5345          * Returns a set of divisors for the desired target clock with the given
5346          * refclk, or FALSE.  The returned values represent the clock equation:
5347          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5348          */
5349         limit = intel_limit(crtc, refclk);
5350         ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5351                               clock);
5352         if (!ret)
5353                 return false;
5354
5355         if (is_lvds && dev_priv->lvds_downclock_avail) {
5356                 /*
5357                  * Ensure we match the reduced clock's P to the target clock.
5358                  * If the clocks don't match, we can't switch the display clock
5359                  * by using the FP0/FP1. In such case we will disable the LVDS
5360                  * downclock feature.
5361                 */
5362                 *has_reduced_clock = limit->find_pll(limit, crtc,
5363                                                      dev_priv->lvds_downclock,
5364                                                      refclk,
5365                                                      clock,
5366                                                      reduced_clock);
5367         }
5368
5369         if (is_sdvo && is_tv)
5370                 i9xx_adjust_sdvo_tv_clock(to_intel_crtc(crtc));
5371
5372         return true;
5373 }
5374
5375 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5376 {
5377         struct drm_i915_private *dev_priv = dev->dev_private;
5378         uint32_t temp;
5379
5380         temp = I915_READ(SOUTH_CHICKEN1);
5381         if (temp & FDI_BC_BIFURCATION_SELECT)
5382                 return;
5383
5384         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5385         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5386
5387         temp |= FDI_BC_BIFURCATION_SELECT;
5388         DRM_DEBUG_KMS("enabling fdi C rx\n");
5389         I915_WRITE(SOUTH_CHICKEN1, temp);
5390         POSTING_READ(SOUTH_CHICKEN1);
5391 }
5392
5393 static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5394 {
5395         struct drm_device *dev = intel_crtc->base.dev;
5396         struct drm_i915_private *dev_priv = dev->dev_private;
5397         struct intel_crtc *pipe_B_crtc =
5398                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5399
5400         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5401                       pipe_name(intel_crtc->pipe), intel_crtc->config.fdi_lanes);
5402         if (intel_crtc->config.fdi_lanes > 4) {
5403                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5404                               pipe_name(intel_crtc->pipe), intel_crtc->config.fdi_lanes);
5405                 /* Clamp lanes to avoid programming the hw with bogus values. */
5406                 intel_crtc->config.fdi_lanes = 4;
5407
5408                 return false;
5409         }
5410
5411         if (INTEL_INFO(dev)->num_pipes == 2)
5412                 return true;
5413
5414         switch (intel_crtc->pipe) {
5415         case PIPE_A:
5416                 return true;
5417         case PIPE_B:
5418                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5419                     intel_crtc->config.fdi_lanes > 2) {
5420                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5421                                       pipe_name(intel_crtc->pipe), intel_crtc->config.fdi_lanes);
5422                         /* Clamp lanes to avoid programming the hw with bogus values. */
5423                         intel_crtc->config.fdi_lanes = 2;
5424
5425                         return false;
5426                 }
5427
5428                 if (intel_crtc->config.fdi_lanes > 2)
5429                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5430                 else
5431                         cpt_enable_fdi_bc_bifurcation(dev);
5432
5433                 return true;
5434         case PIPE_C:
5435                 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->config.fdi_lanes <= 2) {
5436                         if (intel_crtc->config.fdi_lanes > 2) {
5437                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5438                                               pipe_name(intel_crtc->pipe), intel_crtc->config.fdi_lanes);
5439                                 /* Clamp lanes to avoid programming the hw with bogus values. */
5440                                 intel_crtc->config.fdi_lanes = 2;
5441
5442                                 return false;
5443                         }
5444                 } else {
5445                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5446                         return false;
5447                 }
5448
5449                 cpt_enable_fdi_bc_bifurcation(dev);
5450
5451                 return true;
5452         default:
5453                 BUG();
5454         }
5455 }
5456
5457 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5458 {
5459         /*
5460          * Account for spread spectrum to avoid
5461          * oversubscribing the link. Max center spread
5462          * is 2.5%; use 5% for safety's sake.
5463          */
5464         u32 bps = target_clock * bpp * 21 / 20;
5465         return bps / (link_bw * 8) + 1;
5466 }
5467
5468 void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5469                                   struct intel_link_m_n *m_n)
5470 {
5471         struct drm_device *dev = crtc->base.dev;
5472         struct drm_i915_private *dev_priv = dev->dev_private;
5473         int pipe = crtc->pipe;
5474
5475         I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5476         I915_WRITE(TRANSDATA_N1(pipe), m_n->gmch_n);
5477         I915_WRITE(TRANSDPLINK_M1(pipe), m_n->link_m);
5478         I915_WRITE(TRANSDPLINK_N1(pipe), m_n->link_n);
5479 }
5480
5481 void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5482                                   struct intel_link_m_n *m_n)
5483 {
5484         struct drm_device *dev = crtc->base.dev;
5485         struct drm_i915_private *dev_priv = dev->dev_private;
5486         int pipe = crtc->pipe;
5487         enum transcoder transcoder = crtc->config.cpu_transcoder;
5488
5489         if (INTEL_INFO(dev)->gen >= 5) {
5490                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5491                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5492                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5493                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5494         } else {
5495                 I915_WRITE(PIPE_GMCH_DATA_M(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5496                 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n->gmch_n);
5497                 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n->link_m);
5498                 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n->link_n);
5499         }
5500 }
5501
5502 static void ironlake_fdi_compute_config(struct intel_crtc *intel_crtc)
5503 {
5504         struct drm_device *dev = intel_crtc->base.dev;
5505         struct drm_display_mode *adjusted_mode =
5506                 &intel_crtc->config.adjusted_mode;
5507         int target_clock, lane, link_bw;
5508
5509         /* FDI is a binary signal running at ~2.7GHz, encoding
5510          * each output octet as 10 bits. The actual frequency
5511          * is stored as a divider into a 100MHz clock, and the
5512          * mode pixel clock is stored in units of 1KHz.
5513          * Hence the bw of each lane in terms of the mode signal
5514          * is:
5515          */
5516         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5517
5518         if (intel_crtc->config.pixel_target_clock)
5519                 target_clock = intel_crtc->config.pixel_target_clock;
5520         else
5521                 target_clock = adjusted_mode->clock;
5522
5523         lane = ironlake_get_lanes_required(target_clock, link_bw,
5524                                            intel_crtc->config.pipe_bpp);
5525
5526         intel_crtc->config.fdi_lanes = lane;
5527
5528         if (intel_crtc->config.pixel_multiplier > 1)
5529                 link_bw *= intel_crtc->config.pixel_multiplier;
5530         intel_link_compute_m_n(intel_crtc->config.pipe_bpp, lane, target_clock,
5531                                link_bw, &intel_crtc->config.fdi_m_n);
5532 }
5533
5534 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5535 {
5536         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5537 }
5538
5539 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5540                                       u32 *fp,
5541                                       intel_clock_t *reduced_clock, u32 *fp2)
5542 {
5543         struct drm_crtc *crtc = &intel_crtc->base;
5544         struct drm_device *dev = crtc->dev;
5545         struct drm_i915_private *dev_priv = dev->dev_private;
5546         struct intel_encoder *intel_encoder;
5547         uint32_t dpll;
5548         int factor, num_connectors = 0;
5549         bool is_lvds = false, is_sdvo = false, is_tv = false;
5550
5551         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5552                 switch (intel_encoder->type) {
5553                 case INTEL_OUTPUT_LVDS:
5554                         is_lvds = true;
5555                         break;
5556                 case INTEL_OUTPUT_SDVO:
5557                 case INTEL_OUTPUT_HDMI:
5558                         is_sdvo = true;
5559                         if (intel_encoder->needs_tv_clock)
5560                                 is_tv = true;
5561                         break;
5562                 case INTEL_OUTPUT_TVOUT:
5563                         is_tv = true;
5564                         break;
5565                 }
5566
5567                 num_connectors++;
5568         }
5569
5570         /* Enable autotuning of the PLL clock (if permissible) */
5571         factor = 21;
5572         if (is_lvds) {
5573                 if ((intel_panel_use_ssc(dev_priv) &&
5574                      dev_priv->lvds_ssc_freq == 100) ||
5575                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5576                         factor = 25;
5577         } else if (is_sdvo && is_tv)
5578                 factor = 20;
5579
5580         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5581                 *fp |= FP_CB_TUNE;
5582
5583         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5584                 *fp2 |= FP_CB_TUNE;
5585
5586         dpll = 0;
5587
5588         if (is_lvds)
5589                 dpll |= DPLLB_MODE_LVDS;
5590         else
5591                 dpll |= DPLLB_MODE_DAC_SERIAL;
5592
5593         if (intel_crtc->config.pixel_multiplier > 1) {
5594                 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5595                         << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5596         }
5597
5598         if (is_sdvo)
5599                 dpll |= DPLL_DVO_HIGH_SPEED;
5600         if (intel_crtc->config.has_dp_encoder)
5601                 dpll |= DPLL_DVO_HIGH_SPEED;
5602
5603         /* compute bitmask from p1 value */
5604         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5605         /* also FPA1 */
5606         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5607
5608         switch (intel_crtc->config.dpll.p2) {
5609         case 5:
5610                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5611                 break;
5612         case 7:
5613                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5614                 break;
5615         case 10:
5616                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5617                 break;
5618         case 14:
5619                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5620                 break;
5621         }
5622
5623         if (is_sdvo && is_tv)
5624                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5625         else if (is_tv)
5626                 /* XXX: just matching BIOS for now */
5627                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5628                 dpll |= 3;
5629         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5630                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5631         else
5632                 dpll |= PLL_REF_INPUT_DREFCLK;
5633
5634         return dpll;
5635 }
5636
5637 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5638                                   int x, int y,
5639                                   struct drm_framebuffer *fb)
5640 {
5641         struct drm_device *dev = crtc->dev;
5642         struct drm_i915_private *dev_priv = dev->dev_private;
5643         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5644         struct drm_display_mode *adjusted_mode =
5645                 &intel_crtc->config.adjusted_mode;
5646         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5647         int pipe = intel_crtc->pipe;
5648         int plane = intel_crtc->plane;
5649         int num_connectors = 0;
5650         intel_clock_t clock, reduced_clock;
5651         u32 dpll = 0, fp = 0, fp2 = 0;
5652         bool ok, has_reduced_clock = false;
5653         bool is_lvds = false;
5654         struct intel_encoder *encoder;
5655         int ret;
5656         bool fdi_config_ok;
5657
5658         for_each_encoder_on_crtc(dev, crtc, encoder) {
5659                 switch (encoder->type) {
5660                 case INTEL_OUTPUT_LVDS:
5661                         is_lvds = true;
5662                         break;
5663                 }
5664
5665                 num_connectors++;
5666         }
5667
5668         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5669              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5670
5671         intel_crtc->config.cpu_transcoder = pipe;
5672
5673         ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5674                                      &has_reduced_clock, &reduced_clock);
5675         if (!ok) {
5676                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5677                 return -EINVAL;
5678         }
5679         /* Compat-code for transition, will disappear. */
5680         if (!intel_crtc->config.clock_set) {
5681                 intel_crtc->config.dpll.n = clock.n;
5682                 intel_crtc->config.dpll.m1 = clock.m1;
5683                 intel_crtc->config.dpll.m2 = clock.m2;
5684                 intel_crtc->config.dpll.p1 = clock.p1;
5685                 intel_crtc->config.dpll.p2 = clock.p2;
5686         }
5687
5688         /* Ensure that the cursor is valid for the new mode before changing... */
5689         intel_crtc_update_cursor(crtc, true);
5690
5691         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
5692         drm_mode_debug_printmodeline(mode);
5693
5694         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5695         if (intel_crtc->config.has_pch_encoder) {
5696                 struct intel_pch_pll *pll;
5697
5698                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5699                 if (has_reduced_clock)
5700                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5701
5702                 dpll = ironlake_compute_dpll(intel_crtc,
5703                                              &fp, &reduced_clock,
5704                                              has_reduced_clock ? &fp2 : NULL);
5705
5706                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5707                 if (pll == NULL) {
5708                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5709                                          pipe_name(pipe));
5710                         return -EINVAL;
5711                 }
5712         } else
5713                 intel_put_pch_pll(intel_crtc);
5714
5715         if (intel_crtc->config.has_dp_encoder)
5716                 intel_dp_set_m_n(intel_crtc);
5717
5718         for_each_encoder_on_crtc(dev, crtc, encoder)
5719                 if (encoder->pre_pll_enable)
5720                         encoder->pre_pll_enable(encoder);
5721
5722         if (intel_crtc->pch_pll) {
5723                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5724
5725                 /* Wait for the clocks to stabilize. */
5726                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5727                 udelay(150);
5728
5729                 /* The pixel multiplier can only be updated once the
5730                  * DPLL is enabled and the clocks are stable.
5731                  *
5732                  * So write it again.
5733                  */
5734                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5735         }
5736
5737         intel_crtc->lowfreq_avail = false;
5738         if (intel_crtc->pch_pll) {
5739                 if (is_lvds && has_reduced_clock && i915_powersave) {
5740                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5741                         intel_crtc->lowfreq_avail = true;
5742                 } else {
5743                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5744                 }
5745         }
5746
5747         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5748
5749         /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5750          * ironlake_check_fdi_lanes. */
5751         intel_crtc->config.fdi_lanes = 0;
5752         if (intel_crtc->config.has_pch_encoder) {
5753                 ironlake_fdi_compute_config(intel_crtc);
5754
5755                 intel_cpu_transcoder_set_m_n(intel_crtc,
5756                                              &intel_crtc->config.fdi_m_n);
5757         }
5758
5759         fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5760
5761         ironlake_set_pipeconf(crtc);
5762
5763         /* Set up the display plane register */
5764         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5765         POSTING_READ(DSPCNTR(plane));
5766
5767         ret = intel_pipe_set_base(crtc, x, y, fb);
5768
5769         intel_update_watermarks(dev);
5770
5771         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5772
5773         return fdi_config_ok ? ret : -EINVAL;
5774 }
5775
5776 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5777                                      struct intel_crtc_config *pipe_config)
5778 {
5779         struct drm_device *dev = crtc->base.dev;
5780         struct drm_i915_private *dev_priv = dev->dev_private;
5781         uint32_t tmp;
5782
5783         tmp = I915_READ(PIPECONF(crtc->pipe));
5784         if (!(tmp & PIPECONF_ENABLE))
5785                 return false;
5786
5787         if (I915_READ(TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5788                 pipe_config->has_pch_encoder = true;
5789
5790                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5791                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5792                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
5793         }
5794
5795         return true;
5796 }
5797
5798 static void haswell_modeset_global_resources(struct drm_device *dev)
5799 {
5800         struct drm_i915_private *dev_priv = dev->dev_private;
5801         bool enable = false;
5802         struct intel_crtc *crtc;
5803         struct intel_encoder *encoder;
5804
5805         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5806                 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5807                         enable = true;
5808                 /* XXX: Should check for edp transcoder here, but thanks to init
5809                  * sequence that's not yet available. Just in case desktop eDP
5810                  * on PORT D is possible on haswell, too. */
5811                 /* Even the eDP panel fitter is outside the always-on well. */
5812                 if (I915_READ(PF_WIN_SZ(crtc->pipe)))
5813                         enable = true;
5814         }
5815
5816         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5817                             base.head) {
5818                 if (encoder->type != INTEL_OUTPUT_EDP &&
5819                     encoder->connectors_active)
5820                         enable = true;
5821         }
5822
5823         intel_set_power_well(dev, enable);
5824 }
5825
5826 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5827                                  int x, int y,
5828                                  struct drm_framebuffer *fb)
5829 {
5830         struct drm_device *dev = crtc->dev;
5831         struct drm_i915_private *dev_priv = dev->dev_private;
5832         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5833         struct drm_display_mode *adjusted_mode =
5834                 &intel_crtc->config.adjusted_mode;
5835         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5836         int pipe = intel_crtc->pipe;
5837         int plane = intel_crtc->plane;
5838         int num_connectors = 0;
5839         bool is_cpu_edp = false;
5840         struct intel_encoder *encoder;
5841         int ret;
5842
5843         for_each_encoder_on_crtc(dev, crtc, encoder) {
5844                 switch (encoder->type) {
5845                 case INTEL_OUTPUT_EDP:
5846                         if (!intel_encoder_is_pch_edp(&encoder->base))
5847                                 is_cpu_edp = true;
5848                         break;
5849                 }
5850
5851                 num_connectors++;
5852         }
5853
5854         if (is_cpu_edp)
5855                 intel_crtc->config.cpu_transcoder = TRANSCODER_EDP;
5856         else
5857                 intel_crtc->config.cpu_transcoder = pipe;
5858
5859         /* We are not sure yet this won't happen. */
5860         WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5861              INTEL_PCH_TYPE(dev));
5862
5863         WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5864              num_connectors, pipe_name(pipe));
5865
5866         WARN_ON(I915_READ(PIPECONF(intel_crtc->config.cpu_transcoder)) &
5867                 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5868
5869         WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5870
5871         if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5872                 return -EINVAL;
5873
5874         /* Ensure that the cursor is valid for the new mode before changing... */
5875         intel_crtc_update_cursor(crtc, true);
5876
5877         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
5878         drm_mode_debug_printmodeline(mode);
5879
5880         if (intel_crtc->config.has_dp_encoder)
5881                 intel_dp_set_m_n(intel_crtc);
5882
5883         intel_crtc->lowfreq_avail = false;
5884
5885         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5886
5887         if (intel_crtc->config.has_pch_encoder) {
5888                 ironlake_fdi_compute_config(intel_crtc);
5889
5890                 intel_cpu_transcoder_set_m_n(intel_crtc,
5891                                              &intel_crtc->config.fdi_m_n);
5892         }
5893
5894         haswell_set_pipeconf(crtc);
5895
5896         intel_set_pipe_csc(crtc);
5897
5898         /* Set up the display plane register */
5899         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
5900         POSTING_READ(DSPCNTR(plane));
5901
5902         ret = intel_pipe_set_base(crtc, x, y, fb);
5903
5904         intel_update_watermarks(dev);
5905
5906         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5907
5908         return ret;
5909 }
5910
5911 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5912                                     struct intel_crtc_config *pipe_config)
5913 {
5914         struct drm_device *dev = crtc->base.dev;
5915         struct drm_i915_private *dev_priv = dev->dev_private;
5916         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
5917         uint32_t tmp;
5918
5919         if (!intel_using_power_well(dev_priv->dev) &&
5920             cpu_transcoder != TRANSCODER_EDP)
5921                 return false;
5922
5923         tmp = I915_READ(PIPECONF(cpu_transcoder));
5924         if (!(tmp & PIPECONF_ENABLE))
5925                 return false;
5926
5927         /*
5928          * Haswell has only FDI/PCH transcoder A. It is which is connected to
5929          * DDI E. So just check whether this pipe is wired to DDI E and whether
5930          * the PCH transcoder is on.
5931          */
5932         tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
5933         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
5934             I915_READ(TRANSCONF(PIPE_A)) & TRANS_ENABLE) {
5935                 pipe_config->has_pch_encoder = true;
5936
5937                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
5938                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5939                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
5940         }
5941
5942         return true;
5943 }
5944
5945 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5946                                int x, int y,
5947                                struct drm_framebuffer *fb)
5948 {
5949         struct drm_device *dev = crtc->dev;
5950         struct drm_i915_private *dev_priv = dev->dev_private;
5951         struct drm_encoder_helper_funcs *encoder_funcs;
5952         struct intel_encoder *encoder;
5953         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5954         struct drm_display_mode *adjusted_mode =
5955                 &intel_crtc->config.adjusted_mode;
5956         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5957         int pipe = intel_crtc->pipe;
5958         int ret;
5959
5960         drm_vblank_pre_modeset(dev, pipe);
5961
5962         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
5963
5964         drm_vblank_post_modeset(dev, pipe);
5965
5966         if (ret != 0)
5967                 return ret;
5968
5969         for_each_encoder_on_crtc(dev, crtc, encoder) {
5970                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5971                         encoder->base.base.id,
5972                         drm_get_encoder_name(&encoder->base),
5973                         mode->base.id, mode->name);
5974                 if (encoder->mode_set) {
5975                         encoder->mode_set(encoder);
5976                 } else {
5977                         encoder_funcs = encoder->base.helper_private;
5978                         encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5979                 }
5980         }
5981
5982         return 0;
5983 }
5984
5985 static bool intel_eld_uptodate(struct drm_connector *connector,
5986                                int reg_eldv, uint32_t bits_eldv,
5987                                int reg_elda, uint32_t bits_elda,
5988                                int reg_edid)
5989 {
5990         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5991         uint8_t *eld = connector->eld;
5992         uint32_t i;
5993
5994         i = I915_READ(reg_eldv);
5995         i &= bits_eldv;
5996
5997         if (!eld[0])
5998                 return !i;
5999
6000         if (!i)
6001                 return false;
6002
6003         i = I915_READ(reg_elda);
6004         i &= ~bits_elda;
6005         I915_WRITE(reg_elda, i);
6006
6007         for (i = 0; i < eld[2]; i++)
6008                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6009                         return false;
6010
6011         return true;
6012 }
6013
6014 static void g4x_write_eld(struct drm_connector *connector,
6015                           struct drm_crtc *crtc)
6016 {
6017         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6018         uint8_t *eld = connector->eld;
6019         uint32_t eldv;
6020         uint32_t len;
6021         uint32_t i;
6022
6023         i = I915_READ(G4X_AUD_VID_DID);
6024
6025         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6026                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6027         else
6028                 eldv = G4X_ELDV_DEVCTG;
6029
6030         if (intel_eld_uptodate(connector,
6031                                G4X_AUD_CNTL_ST, eldv,
6032                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6033                                G4X_HDMIW_HDMIEDID))
6034                 return;
6035
6036         i = I915_READ(G4X_AUD_CNTL_ST);
6037         i &= ~(eldv | G4X_ELD_ADDR);
6038         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6039         I915_WRITE(G4X_AUD_CNTL_ST, i);
6040
6041         if (!eld[0])
6042                 return;
6043
6044         len = min_t(uint8_t, eld[2], len);
6045         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6046         for (i = 0; i < len; i++)
6047                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6048
6049         i = I915_READ(G4X_AUD_CNTL_ST);
6050         i |= eldv;
6051         I915_WRITE(G4X_AUD_CNTL_ST, i);
6052 }
6053
6054 static void haswell_write_eld(struct drm_connector *connector,
6055                                      struct drm_crtc *crtc)
6056 {
6057         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6058         uint8_t *eld = connector->eld;
6059         struct drm_device *dev = crtc->dev;
6060         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6061         uint32_t eldv;
6062         uint32_t i;
6063         int len;
6064         int pipe = to_intel_crtc(crtc)->pipe;
6065         int tmp;
6066
6067         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6068         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6069         int aud_config = HSW_AUD_CFG(pipe);
6070         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6071
6072
6073         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6074
6075         /* Audio output enable */
6076         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6077         tmp = I915_READ(aud_cntrl_st2);
6078         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6079         I915_WRITE(aud_cntrl_st2, tmp);
6080
6081         /* Wait for 1 vertical blank */
6082         intel_wait_for_vblank(dev, pipe);
6083
6084         /* Set ELD valid state */
6085         tmp = I915_READ(aud_cntrl_st2);
6086         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6087         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6088         I915_WRITE(aud_cntrl_st2, tmp);
6089         tmp = I915_READ(aud_cntrl_st2);
6090         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6091
6092         /* Enable HDMI mode */
6093         tmp = I915_READ(aud_config);
6094         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6095         /* clear N_programing_enable and N_value_index */
6096         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6097         I915_WRITE(aud_config, tmp);
6098
6099         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6100
6101         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6102         intel_crtc->eld_vld = true;
6103
6104         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6105                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6106                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6107                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6108         } else
6109                 I915_WRITE(aud_config, 0);
6110
6111         if (intel_eld_uptodate(connector,
6112                                aud_cntrl_st2, eldv,
6113                                aud_cntl_st, IBX_ELD_ADDRESS,
6114                                hdmiw_hdmiedid))
6115                 return;
6116
6117         i = I915_READ(aud_cntrl_st2);
6118         i &= ~eldv;
6119         I915_WRITE(aud_cntrl_st2, i);
6120
6121         if (!eld[0])
6122                 return;
6123
6124         i = I915_READ(aud_cntl_st);
6125         i &= ~IBX_ELD_ADDRESS;
6126         I915_WRITE(aud_cntl_st, i);
6127         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6128         DRM_DEBUG_DRIVER("port num:%d\n", i);
6129
6130         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6131         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6132         for (i = 0; i < len; i++)
6133                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6134
6135         i = I915_READ(aud_cntrl_st2);
6136         i |= eldv;
6137         I915_WRITE(aud_cntrl_st2, i);
6138
6139 }
6140
6141 static void ironlake_write_eld(struct drm_connector *connector,
6142                                      struct drm_crtc *crtc)
6143 {
6144         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6145         uint8_t *eld = connector->eld;
6146         uint32_t eldv;
6147         uint32_t i;
6148         int len;
6149         int hdmiw_hdmiedid;
6150         int aud_config;
6151         int aud_cntl_st;
6152         int aud_cntrl_st2;
6153         int pipe = to_intel_crtc(crtc)->pipe;
6154
6155         if (HAS_PCH_IBX(connector->dev)) {
6156                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6157                 aud_config = IBX_AUD_CFG(pipe);
6158                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6159                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6160         } else {
6161                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6162                 aud_config = CPT_AUD_CFG(pipe);
6163                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6164                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6165         }
6166
6167         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6168
6169         i = I915_READ(aud_cntl_st);
6170         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6171         if (!i) {
6172                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6173                 /* operate blindly on all ports */
6174                 eldv = IBX_ELD_VALIDB;
6175                 eldv |= IBX_ELD_VALIDB << 4;
6176                 eldv |= IBX_ELD_VALIDB << 8;
6177         } else {
6178                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6179                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6180         }
6181
6182         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6183                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6184                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6185                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6186         } else
6187                 I915_WRITE(aud_config, 0);
6188
6189         if (intel_eld_uptodate(connector,
6190                                aud_cntrl_st2, eldv,
6191                                aud_cntl_st, IBX_ELD_ADDRESS,
6192                                hdmiw_hdmiedid))
6193                 return;
6194
6195         i = I915_READ(aud_cntrl_st2);
6196         i &= ~eldv;
6197         I915_WRITE(aud_cntrl_st2, i);
6198
6199         if (!eld[0])
6200                 return;
6201
6202         i = I915_READ(aud_cntl_st);
6203         i &= ~IBX_ELD_ADDRESS;
6204         I915_WRITE(aud_cntl_st, i);
6205
6206         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6207         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6208         for (i = 0; i < len; i++)
6209                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6210
6211         i = I915_READ(aud_cntrl_st2);
6212         i |= eldv;
6213         I915_WRITE(aud_cntrl_st2, i);
6214 }
6215
6216 void intel_write_eld(struct drm_encoder *encoder,
6217                      struct drm_display_mode *mode)
6218 {
6219         struct drm_crtc *crtc = encoder->crtc;
6220         struct drm_connector *connector;
6221         struct drm_device *dev = encoder->dev;
6222         struct drm_i915_private *dev_priv = dev->dev_private;
6223
6224         connector = drm_select_eld(encoder, mode);
6225         if (!connector)
6226                 return;
6227
6228         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6229                          connector->base.id,
6230                          drm_get_connector_name(connector),
6231                          connector->encoder->base.id,
6232                          drm_get_encoder_name(connector->encoder));
6233
6234         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6235
6236         if (dev_priv->display.write_eld)
6237                 dev_priv->display.write_eld(connector, crtc);
6238 }
6239
6240 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6241 void intel_crtc_load_lut(struct drm_crtc *crtc)
6242 {
6243         struct drm_device *dev = crtc->dev;
6244         struct drm_i915_private *dev_priv = dev->dev_private;
6245         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6246         int palreg = PALETTE(intel_crtc->pipe);
6247         int i;
6248
6249         /* The clocks have to be on to load the palette. */
6250         if (!crtc->enabled || !intel_crtc->active)
6251                 return;
6252
6253         /* use legacy palette for Ironlake */
6254         if (HAS_PCH_SPLIT(dev))
6255                 palreg = LGC_PALETTE(intel_crtc->pipe);
6256
6257         for (i = 0; i < 256; i++) {
6258                 I915_WRITE(palreg + 4 * i,
6259                            (intel_crtc->lut_r[i] << 16) |
6260                            (intel_crtc->lut_g[i] << 8) |
6261                            intel_crtc->lut_b[i]);
6262         }
6263 }
6264
6265 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6266 {
6267         struct drm_device *dev = crtc->dev;
6268         struct drm_i915_private *dev_priv = dev->dev_private;
6269         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6270         bool visible = base != 0;
6271         u32 cntl;
6272
6273         if (intel_crtc->cursor_visible == visible)
6274                 return;
6275
6276         cntl = I915_READ(_CURACNTR);
6277         if (visible) {
6278                 /* On these chipsets we can only modify the base whilst
6279                  * the cursor is disabled.
6280                  */
6281                 I915_WRITE(_CURABASE, base);
6282
6283                 cntl &= ~(CURSOR_FORMAT_MASK);
6284                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6285                 cntl |= CURSOR_ENABLE |
6286                         CURSOR_GAMMA_ENABLE |
6287                         CURSOR_FORMAT_ARGB;
6288         } else
6289                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6290         I915_WRITE(_CURACNTR, cntl);
6291
6292         intel_crtc->cursor_visible = visible;
6293 }
6294
6295 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6296 {
6297         struct drm_device *dev = crtc->dev;
6298         struct drm_i915_private *dev_priv = dev->dev_private;
6299         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6300         int pipe = intel_crtc->pipe;
6301         bool visible = base != 0;
6302
6303         if (intel_crtc->cursor_visible != visible) {
6304                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6305                 if (base) {
6306                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6307                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6308                         cntl |= pipe << 28; /* Connect to correct pipe */
6309                 } else {
6310                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6311                         cntl |= CURSOR_MODE_DISABLE;
6312                 }
6313                 I915_WRITE(CURCNTR(pipe), cntl);
6314
6315                 intel_crtc->cursor_visible = visible;
6316         }
6317         /* and commit changes on next vblank */
6318         I915_WRITE(CURBASE(pipe), base);
6319 }
6320
6321 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6322 {
6323         struct drm_device *dev = crtc->dev;
6324         struct drm_i915_private *dev_priv = dev->dev_private;
6325         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6326         int pipe = intel_crtc->pipe;
6327         bool visible = base != 0;
6328
6329         if (intel_crtc->cursor_visible != visible) {
6330                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6331                 if (base) {
6332                         cntl &= ~CURSOR_MODE;
6333                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6334                 } else {
6335                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6336                         cntl |= CURSOR_MODE_DISABLE;
6337                 }
6338                 if (IS_HASWELL(dev))
6339                         cntl |= CURSOR_PIPE_CSC_ENABLE;
6340                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6341
6342                 intel_crtc->cursor_visible = visible;
6343         }
6344         /* and commit changes on next vblank */
6345         I915_WRITE(CURBASE_IVB(pipe), base);
6346 }
6347
6348 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6349 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6350                                      bool on)
6351 {
6352         struct drm_device *dev = crtc->dev;
6353         struct drm_i915_private *dev_priv = dev->dev_private;
6354         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6355         int pipe = intel_crtc->pipe;
6356         int x = intel_crtc->cursor_x;
6357         int y = intel_crtc->cursor_y;
6358         u32 base, pos;
6359         bool visible;
6360
6361         pos = 0;
6362
6363         if (on && crtc->enabled && crtc->fb) {
6364                 base = intel_crtc->cursor_addr;
6365                 if (x > (int) crtc->fb->width)
6366                         base = 0;
6367
6368                 if (y > (int) crtc->fb->height)
6369                         base = 0;
6370         } else
6371                 base = 0;
6372
6373         if (x < 0) {
6374                 if (x + intel_crtc->cursor_width < 0)
6375                         base = 0;
6376
6377                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6378                 x = -x;
6379         }
6380         pos |= x << CURSOR_X_SHIFT;
6381
6382         if (y < 0) {
6383                 if (y + intel_crtc->cursor_height < 0)
6384                         base = 0;
6385
6386                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6387                 y = -y;
6388         }
6389         pos |= y << CURSOR_Y_SHIFT;
6390
6391         visible = base != 0;
6392         if (!visible && !intel_crtc->cursor_visible)
6393                 return;
6394
6395         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6396                 I915_WRITE(CURPOS_IVB(pipe), pos);
6397                 ivb_update_cursor(crtc, base);
6398         } else {
6399                 I915_WRITE(CURPOS(pipe), pos);
6400                 if (IS_845G(dev) || IS_I865G(dev))
6401                         i845_update_cursor(crtc, base);
6402                 else
6403                         i9xx_update_cursor(crtc, base);
6404         }
6405 }
6406
6407 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6408                                  struct drm_file *file,
6409                                  uint32_t handle,
6410                                  uint32_t width, uint32_t height)
6411 {
6412         struct drm_device *dev = crtc->dev;
6413         struct drm_i915_private *dev_priv = dev->dev_private;
6414         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6415         struct drm_i915_gem_object *obj;
6416         uint32_t addr;
6417         int ret;
6418
6419         /* if we want to turn off the cursor ignore width and height */
6420         if (!handle) {
6421                 DRM_DEBUG_KMS("cursor off\n");
6422                 addr = 0;
6423                 obj = NULL;
6424                 mutex_lock(&dev->struct_mutex);
6425                 goto finish;
6426         }
6427
6428         /* Currently we only support 64x64 cursors */
6429         if (width != 64 || height != 64) {
6430                 DRM_ERROR("we currently only support 64x64 cursors\n");
6431                 return -EINVAL;
6432         }
6433
6434         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6435         if (&obj->base == NULL)
6436                 return -ENOENT;
6437
6438         if (obj->base.size < width * height * 4) {
6439                 DRM_ERROR("buffer is to small\n");
6440                 ret = -ENOMEM;
6441                 goto fail;
6442         }
6443
6444         /* we only need to pin inside GTT if cursor is non-phy */
6445         mutex_lock(&dev->struct_mutex);
6446         if (!dev_priv->info->cursor_needs_physical) {
6447                 unsigned alignment;
6448
6449                 if (obj->tiling_mode) {
6450                         DRM_ERROR("cursor cannot be tiled\n");
6451                         ret = -EINVAL;
6452                         goto fail_locked;
6453                 }
6454
6455                 /* Note that the w/a also requires 2 PTE of padding following
6456                  * the bo. We currently fill all unused PTE with the shadow
6457                  * page and so we should always have valid PTE following the
6458                  * cursor preventing the VT-d warning.
6459                  */
6460                 alignment = 0;
6461                 if (need_vtd_wa(dev))
6462                         alignment = 64*1024;
6463
6464                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6465                 if (ret) {
6466                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6467                         goto fail_locked;
6468                 }
6469
6470                 ret = i915_gem_object_put_fence(obj);
6471                 if (ret) {
6472                         DRM_ERROR("failed to release fence for cursor");
6473                         goto fail_unpin;
6474                 }
6475
6476                 addr = obj->gtt_offset;
6477         } else {
6478                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6479                 ret = i915_gem_attach_phys_object(dev, obj,
6480                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6481                                                   align);
6482                 if (ret) {
6483                         DRM_ERROR("failed to attach phys object\n");
6484                         goto fail_locked;
6485                 }
6486                 addr = obj->phys_obj->handle->busaddr;
6487         }
6488
6489         if (IS_GEN2(dev))
6490                 I915_WRITE(CURSIZE, (height << 12) | width);
6491
6492  finish:
6493         if (intel_crtc->cursor_bo) {
6494                 if (dev_priv->info->cursor_needs_physical) {
6495                         if (intel_crtc->cursor_bo != obj)
6496                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6497                 } else
6498                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6499                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6500         }
6501
6502         mutex_unlock(&dev->struct_mutex);
6503
6504         intel_crtc->cursor_addr = addr;
6505         intel_crtc->cursor_bo = obj;
6506         intel_crtc->cursor_width = width;
6507         intel_crtc->cursor_height = height;
6508
6509         intel_crtc_update_cursor(crtc, true);
6510
6511         return 0;
6512 fail_unpin:
6513         i915_gem_object_unpin(obj);
6514 fail_locked:
6515         mutex_unlock(&dev->struct_mutex);
6516 fail:
6517         drm_gem_object_unreference_unlocked(&obj->base);
6518         return ret;
6519 }
6520
6521 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6522 {
6523         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6524
6525         intel_crtc->cursor_x = x;
6526         intel_crtc->cursor_y = y;
6527
6528         intel_crtc_update_cursor(crtc, true);
6529
6530         return 0;
6531 }
6532
6533 /** Sets the color ramps on behalf of RandR */
6534 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6535                                  u16 blue, int regno)
6536 {
6537         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6538
6539         intel_crtc->lut_r[regno] = red >> 8;
6540         intel_crtc->lut_g[regno] = green >> 8;
6541         intel_crtc->lut_b[regno] = blue >> 8;
6542 }
6543
6544 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6545                              u16 *blue, int regno)
6546 {
6547         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6548
6549         *red = intel_crtc->lut_r[regno] << 8;
6550         *green = intel_crtc->lut_g[regno] << 8;
6551         *blue = intel_crtc->lut_b[regno] << 8;
6552 }
6553
6554 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6555                                  u16 *blue, uint32_t start, uint32_t size)
6556 {
6557         int end = (start + size > 256) ? 256 : start + size, i;
6558         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6559
6560         for (i = start; i < end; i++) {
6561                 intel_crtc->lut_r[i] = red[i] >> 8;
6562                 intel_crtc->lut_g[i] = green[i] >> 8;
6563                 intel_crtc->lut_b[i] = blue[i] >> 8;
6564         }
6565
6566         intel_crtc_load_lut(crtc);
6567 }
6568
6569 /* VESA 640x480x72Hz mode to set on the pipe */
6570 static struct drm_display_mode load_detect_mode = {
6571         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6572                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6573 };
6574
6575 static struct drm_framebuffer *
6576 intel_framebuffer_create(struct drm_device *dev,
6577                          struct drm_mode_fb_cmd2 *mode_cmd,
6578                          struct drm_i915_gem_object *obj)
6579 {
6580         struct intel_framebuffer *intel_fb;
6581         int ret;
6582
6583         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6584         if (!intel_fb) {
6585                 drm_gem_object_unreference_unlocked(&obj->base);
6586                 return ERR_PTR(-ENOMEM);
6587         }
6588
6589         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6590         if (ret) {
6591                 drm_gem_object_unreference_unlocked(&obj->base);
6592                 kfree(intel_fb);
6593                 return ERR_PTR(ret);
6594         }
6595
6596         return &intel_fb->base;
6597 }
6598
6599 static u32
6600 intel_framebuffer_pitch_for_width(int width, int bpp)
6601 {
6602         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6603         return ALIGN(pitch, 64);
6604 }
6605
6606 static u32
6607 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6608 {
6609         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6610         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6611 }
6612
6613 static struct drm_framebuffer *
6614 intel_framebuffer_create_for_mode(struct drm_device *dev,
6615                                   struct drm_display_mode *mode,
6616                                   int depth, int bpp)
6617 {
6618         struct drm_i915_gem_object *obj;
6619         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6620
6621         obj = i915_gem_alloc_object(dev,
6622                                     intel_framebuffer_size_for_mode(mode, bpp));
6623         if (obj == NULL)
6624                 return ERR_PTR(-ENOMEM);
6625
6626         mode_cmd.width = mode->hdisplay;
6627         mode_cmd.height = mode->vdisplay;
6628         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6629                                                                 bpp);
6630         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6631
6632         return intel_framebuffer_create(dev, &mode_cmd, obj);
6633 }
6634
6635 static struct drm_framebuffer *
6636 mode_fits_in_fbdev(struct drm_device *dev,
6637                    struct drm_display_mode *mode)
6638 {
6639         struct drm_i915_private *dev_priv = dev->dev_private;
6640         struct drm_i915_gem_object *obj;
6641         struct drm_framebuffer *fb;
6642
6643         if (dev_priv->fbdev == NULL)
6644                 return NULL;
6645
6646         obj = dev_priv->fbdev->ifb.obj;
6647         if (obj == NULL)
6648                 return NULL;
6649
6650         fb = &dev_priv->fbdev->ifb.base;
6651         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6652                                                                fb->bits_per_pixel))
6653                 return NULL;
6654
6655         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6656                 return NULL;
6657
6658         return fb;
6659 }
6660
6661 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6662                                 struct drm_display_mode *mode,
6663                                 struct intel_load_detect_pipe *old)
6664 {
6665         struct intel_crtc *intel_crtc;
6666         struct intel_encoder *intel_encoder =
6667                 intel_attached_encoder(connector);
6668         struct drm_crtc *possible_crtc;
6669         struct drm_encoder *encoder = &intel_encoder->base;
6670         struct drm_crtc *crtc = NULL;
6671         struct drm_device *dev = encoder->dev;
6672         struct drm_framebuffer *fb;
6673         int i = -1;
6674
6675         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6676                       connector->base.id, drm_get_connector_name(connector),
6677                       encoder->base.id, drm_get_encoder_name(encoder));
6678
6679         /*
6680          * Algorithm gets a little messy:
6681          *
6682          *   - if the connector already has an assigned crtc, use it (but make
6683          *     sure it's on first)
6684          *
6685          *   - try to find the first unused crtc that can drive this connector,
6686          *     and use that if we find one
6687          */
6688
6689         /* See if we already have a CRTC for this connector */
6690         if (encoder->crtc) {
6691                 crtc = encoder->crtc;
6692
6693                 mutex_lock(&crtc->mutex);
6694
6695                 old->dpms_mode = connector->dpms;
6696                 old->load_detect_temp = false;
6697
6698                 /* Make sure the crtc and connector are running */
6699                 if (connector->dpms != DRM_MODE_DPMS_ON)
6700                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6701
6702                 return true;
6703         }
6704
6705         /* Find an unused one (if possible) */
6706         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6707                 i++;
6708                 if (!(encoder->possible_crtcs & (1 << i)))
6709                         continue;
6710                 if (!possible_crtc->enabled) {
6711                         crtc = possible_crtc;
6712                         break;
6713                 }
6714         }
6715
6716         /*
6717          * If we didn't find an unused CRTC, don't use any.
6718          */
6719         if (!crtc) {
6720                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6721                 return false;
6722         }
6723
6724         mutex_lock(&crtc->mutex);
6725         intel_encoder->new_crtc = to_intel_crtc(crtc);
6726         to_intel_connector(connector)->new_encoder = intel_encoder;
6727
6728         intel_crtc = to_intel_crtc(crtc);
6729         old->dpms_mode = connector->dpms;
6730         old->load_detect_temp = true;
6731         old->release_fb = NULL;
6732
6733         if (!mode)
6734                 mode = &load_detect_mode;
6735
6736         /* We need a framebuffer large enough to accommodate all accesses
6737          * that the plane may generate whilst we perform load detection.
6738          * We can not rely on the fbcon either being present (we get called
6739          * during its initialisation to detect all boot displays, or it may
6740          * not even exist) or that it is large enough to satisfy the
6741          * requested mode.
6742          */
6743         fb = mode_fits_in_fbdev(dev, mode);
6744         if (fb == NULL) {
6745                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6746                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6747                 old->release_fb = fb;
6748         } else
6749                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6750         if (IS_ERR(fb)) {
6751                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6752                 mutex_unlock(&crtc->mutex);
6753                 return false;
6754         }
6755
6756         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6757                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6758                 if (old->release_fb)
6759                         old->release_fb->funcs->destroy(old->release_fb);
6760                 mutex_unlock(&crtc->mutex);
6761                 return false;
6762         }
6763
6764         /* let the connector get through one full cycle before testing */
6765         intel_wait_for_vblank(dev, intel_crtc->pipe);
6766         return true;
6767 }
6768
6769 void intel_release_load_detect_pipe(struct drm_connector *connector,
6770                                     struct intel_load_detect_pipe *old)
6771 {
6772         struct intel_encoder *intel_encoder =
6773                 intel_attached_encoder(connector);
6774         struct drm_encoder *encoder = &intel_encoder->base;
6775         struct drm_crtc *crtc = encoder->crtc;
6776
6777         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6778                       connector->base.id, drm_get_connector_name(connector),
6779                       encoder->base.id, drm_get_encoder_name(encoder));
6780
6781         if (old->load_detect_temp) {
6782                 to_intel_connector(connector)->new_encoder = NULL;
6783                 intel_encoder->new_crtc = NULL;
6784                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6785
6786                 if (old->release_fb) {
6787                         drm_framebuffer_unregister_private(old->release_fb);
6788                         drm_framebuffer_unreference(old->release_fb);
6789                 }
6790
6791                 mutex_unlock(&crtc->mutex);
6792                 return;
6793         }
6794
6795         /* Switch crtc and encoder back off if necessary */
6796         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6797                 connector->funcs->dpms(connector, old->dpms_mode);
6798
6799         mutex_unlock(&crtc->mutex);
6800 }
6801
6802 /* Returns the clock of the currently programmed mode of the given pipe. */
6803 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6804 {
6805         struct drm_i915_private *dev_priv = dev->dev_private;
6806         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6807         int pipe = intel_crtc->pipe;
6808         u32 dpll = I915_READ(DPLL(pipe));
6809         u32 fp;
6810         intel_clock_t clock;
6811
6812         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6813                 fp = I915_READ(FP0(pipe));
6814         else
6815                 fp = I915_READ(FP1(pipe));
6816
6817         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6818         if (IS_PINEVIEW(dev)) {
6819                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6820                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6821         } else {
6822                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6823                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6824         }
6825
6826         if (!IS_GEN2(dev)) {
6827                 if (IS_PINEVIEW(dev))
6828                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6829                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6830                 else
6831                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6832                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6833
6834                 switch (dpll & DPLL_MODE_MASK) {
6835                 case DPLLB_MODE_DAC_SERIAL:
6836                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6837                                 5 : 10;
6838                         break;
6839                 case DPLLB_MODE_LVDS:
6840                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6841                                 7 : 14;
6842                         break;
6843                 default:
6844                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6845                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6846                         return 0;
6847                 }
6848
6849                 /* XXX: Handle the 100Mhz refclk */
6850                 intel_clock(dev, 96000, &clock);
6851         } else {
6852                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6853
6854                 if (is_lvds) {
6855                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6856                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6857                         clock.p2 = 14;
6858
6859                         if ((dpll & PLL_REF_INPUT_MASK) ==
6860                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6861                                 /* XXX: might not be 66MHz */
6862                                 intel_clock(dev, 66000, &clock);
6863                         } else
6864                                 intel_clock(dev, 48000, &clock);
6865                 } else {
6866                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6867                                 clock.p1 = 2;
6868                         else {
6869                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6870                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6871                         }
6872                         if (dpll & PLL_P2_DIVIDE_BY_4)
6873                                 clock.p2 = 4;
6874                         else
6875                                 clock.p2 = 2;
6876
6877                         intel_clock(dev, 48000, &clock);
6878                 }
6879         }
6880
6881         /* XXX: It would be nice to validate the clocks, but we can't reuse
6882          * i830PllIsValid() because it relies on the xf86_config connector
6883          * configuration being accurate, which it isn't necessarily.
6884          */
6885
6886         return clock.dot;
6887 }
6888
6889 /** Returns the currently programmed mode of the given pipe. */
6890 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6891                                              struct drm_crtc *crtc)
6892 {
6893         struct drm_i915_private *dev_priv = dev->dev_private;
6894         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6895         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6896         struct drm_display_mode *mode;
6897         int htot = I915_READ(HTOTAL(cpu_transcoder));
6898         int hsync = I915_READ(HSYNC(cpu_transcoder));
6899         int vtot = I915_READ(VTOTAL(cpu_transcoder));
6900         int vsync = I915_READ(VSYNC(cpu_transcoder));
6901
6902         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6903         if (!mode)
6904                 return NULL;
6905
6906         mode->clock = intel_crtc_clock_get(dev, crtc);
6907         mode->hdisplay = (htot & 0xffff) + 1;
6908         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6909         mode->hsync_start = (hsync & 0xffff) + 1;
6910         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6911         mode->vdisplay = (vtot & 0xffff) + 1;
6912         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6913         mode->vsync_start = (vsync & 0xffff) + 1;
6914         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6915
6916         drm_mode_set_name(mode);
6917
6918         return mode;
6919 }
6920
6921 static void intel_increase_pllclock(struct drm_crtc *crtc)
6922 {
6923         struct drm_device *dev = crtc->dev;
6924         drm_i915_private_t *dev_priv = dev->dev_private;
6925         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6926         int pipe = intel_crtc->pipe;
6927         int dpll_reg = DPLL(pipe);
6928         int dpll;
6929
6930         if (HAS_PCH_SPLIT(dev))
6931                 return;
6932
6933         if (!dev_priv->lvds_downclock_avail)
6934                 return;
6935
6936         dpll = I915_READ(dpll_reg);
6937         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6938                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6939
6940                 assert_panel_unlocked(dev_priv, pipe);
6941
6942                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6943                 I915_WRITE(dpll_reg, dpll);
6944                 intel_wait_for_vblank(dev, pipe);
6945
6946                 dpll = I915_READ(dpll_reg);
6947                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6948                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6949         }
6950 }
6951
6952 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6953 {
6954         struct drm_device *dev = crtc->dev;
6955         drm_i915_private_t *dev_priv = dev->dev_private;
6956         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6957
6958         if (HAS_PCH_SPLIT(dev))
6959                 return;
6960
6961         if (!dev_priv->lvds_downclock_avail)
6962                 return;
6963
6964         /*
6965          * Since this is called by a timer, we should never get here in
6966          * the manual case.
6967          */
6968         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6969                 int pipe = intel_crtc->pipe;
6970                 int dpll_reg = DPLL(pipe);
6971                 int dpll;
6972
6973                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6974
6975                 assert_panel_unlocked(dev_priv, pipe);
6976
6977                 dpll = I915_READ(dpll_reg);
6978                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6979                 I915_WRITE(dpll_reg, dpll);
6980                 intel_wait_for_vblank(dev, pipe);
6981                 dpll = I915_READ(dpll_reg);
6982                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6983                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6984         }
6985
6986 }
6987
6988 void intel_mark_busy(struct drm_device *dev)
6989 {
6990         i915_update_gfx_val(dev->dev_private);
6991 }
6992
6993 void intel_mark_idle(struct drm_device *dev)
6994 {
6995         struct drm_crtc *crtc;
6996
6997         if (!i915_powersave)
6998                 return;
6999
7000         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7001                 if (!crtc->fb)
7002                         continue;
7003
7004                 intel_decrease_pllclock(crtc);
7005         }
7006 }
7007
7008 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
7009 {
7010         struct drm_device *dev = obj->base.dev;
7011         struct drm_crtc *crtc;
7012
7013         if (!i915_powersave)
7014                 return;
7015
7016         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7017                 if (!crtc->fb)
7018                         continue;
7019
7020                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
7021                         intel_increase_pllclock(crtc);
7022         }
7023 }
7024
7025 static void intel_crtc_destroy(struct drm_crtc *crtc)
7026 {
7027         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7028         struct drm_device *dev = crtc->dev;
7029         struct intel_unpin_work *work;
7030         unsigned long flags;
7031
7032         spin_lock_irqsave(&dev->event_lock, flags);
7033         work = intel_crtc->unpin_work;
7034         intel_crtc->unpin_work = NULL;
7035         spin_unlock_irqrestore(&dev->event_lock, flags);
7036
7037         if (work) {
7038                 cancel_work_sync(&work->work);
7039                 kfree(work);
7040         }
7041
7042         drm_crtc_cleanup(crtc);
7043
7044         kfree(intel_crtc);
7045 }
7046
7047 static void intel_unpin_work_fn(struct work_struct *__work)
7048 {
7049         struct intel_unpin_work *work =
7050                 container_of(__work, struct intel_unpin_work, work);
7051         struct drm_device *dev = work->crtc->dev;
7052
7053         mutex_lock(&dev->struct_mutex);
7054         intel_unpin_fb_obj(work->old_fb_obj);
7055         drm_gem_object_unreference(&work->pending_flip_obj->base);
7056         drm_gem_object_unreference(&work->old_fb_obj->base);
7057
7058         intel_update_fbc(dev);
7059         mutex_unlock(&dev->struct_mutex);
7060
7061         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7062         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7063
7064         kfree(work);
7065 }
7066
7067 static void do_intel_finish_page_flip(struct drm_device *dev,
7068                                       struct drm_crtc *crtc)
7069 {
7070         drm_i915_private_t *dev_priv = dev->dev_private;
7071         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7072         struct intel_unpin_work *work;
7073         unsigned long flags;
7074
7075         /* Ignore early vblank irqs */
7076         if (intel_crtc == NULL)
7077                 return;
7078
7079         spin_lock_irqsave(&dev->event_lock, flags);
7080         work = intel_crtc->unpin_work;
7081
7082         /* Ensure we don't miss a work->pending update ... */
7083         smp_rmb();
7084
7085         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7086                 spin_unlock_irqrestore(&dev->event_lock, flags);
7087                 return;
7088         }
7089
7090         /* and that the unpin work is consistent wrt ->pending. */
7091         smp_rmb();
7092
7093         intel_crtc->unpin_work = NULL;
7094
7095         if (work->event)
7096                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7097
7098         drm_vblank_put(dev, intel_crtc->pipe);
7099
7100         spin_unlock_irqrestore(&dev->event_lock, flags);
7101
7102         wake_up_all(&dev_priv->pending_flip_queue);
7103
7104         queue_work(dev_priv->wq, &work->work);
7105
7106         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7107 }
7108
7109 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7110 {
7111         drm_i915_private_t *dev_priv = dev->dev_private;
7112         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7113
7114         do_intel_finish_page_flip(dev, crtc);
7115 }
7116
7117 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7118 {
7119         drm_i915_private_t *dev_priv = dev->dev_private;
7120         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7121
7122         do_intel_finish_page_flip(dev, crtc);
7123 }
7124
7125 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7126 {
7127         drm_i915_private_t *dev_priv = dev->dev_private;
7128         struct intel_crtc *intel_crtc =
7129                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7130         unsigned long flags;
7131
7132         /* NB: An MMIO update of the plane base pointer will also
7133          * generate a page-flip completion irq, i.e. every modeset
7134          * is also accompanied by a spurious intel_prepare_page_flip().
7135          */
7136         spin_lock_irqsave(&dev->event_lock, flags);
7137         if (intel_crtc->unpin_work)
7138                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7139         spin_unlock_irqrestore(&dev->event_lock, flags);
7140 }
7141
7142 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7143 {
7144         /* Ensure that the work item is consistent when activating it ... */
7145         smp_wmb();
7146         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7147         /* and that it is marked active as soon as the irq could fire. */
7148         smp_wmb();
7149 }
7150
7151 static int intel_gen2_queue_flip(struct drm_device *dev,
7152                                  struct drm_crtc *crtc,
7153                                  struct drm_framebuffer *fb,
7154                                  struct drm_i915_gem_object *obj)
7155 {
7156         struct drm_i915_private *dev_priv = dev->dev_private;
7157         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7158         u32 flip_mask;
7159         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7160         int ret;
7161
7162         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7163         if (ret)
7164                 goto err;
7165
7166         ret = intel_ring_begin(ring, 6);
7167         if (ret)
7168                 goto err_unpin;
7169
7170         /* Can't queue multiple flips, so wait for the previous
7171          * one to finish before executing the next.
7172          */
7173         if (intel_crtc->plane)
7174                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7175         else
7176                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7177         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7178         intel_ring_emit(ring, MI_NOOP);
7179         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7180                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7181         intel_ring_emit(ring, fb->pitches[0]);
7182         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7183         intel_ring_emit(ring, 0); /* aux display base address, unused */
7184
7185         intel_mark_page_flip_active(intel_crtc);
7186         intel_ring_advance(ring);
7187         return 0;
7188
7189 err_unpin:
7190         intel_unpin_fb_obj(obj);
7191 err:
7192         return ret;
7193 }
7194
7195 static int intel_gen3_queue_flip(struct drm_device *dev,
7196                                  struct drm_crtc *crtc,
7197                                  struct drm_framebuffer *fb,
7198                                  struct drm_i915_gem_object *obj)
7199 {
7200         struct drm_i915_private *dev_priv = dev->dev_private;
7201         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7202         u32 flip_mask;
7203         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7204         int ret;
7205
7206         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7207         if (ret)
7208                 goto err;
7209
7210         ret = intel_ring_begin(ring, 6);
7211         if (ret)
7212                 goto err_unpin;
7213
7214         if (intel_crtc->plane)
7215                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7216         else
7217                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7218         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7219         intel_ring_emit(ring, MI_NOOP);
7220         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7221                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7222         intel_ring_emit(ring, fb->pitches[0]);
7223         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7224         intel_ring_emit(ring, MI_NOOP);
7225
7226         intel_mark_page_flip_active(intel_crtc);
7227         intel_ring_advance(ring);
7228         return 0;
7229
7230 err_unpin:
7231         intel_unpin_fb_obj(obj);
7232 err:
7233         return ret;
7234 }
7235
7236 static int intel_gen4_queue_flip(struct drm_device *dev,
7237                                  struct drm_crtc *crtc,
7238                                  struct drm_framebuffer *fb,
7239                                  struct drm_i915_gem_object *obj)
7240 {
7241         struct drm_i915_private *dev_priv = dev->dev_private;
7242         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7243         uint32_t pf, pipesrc;
7244         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7245         int ret;
7246
7247         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7248         if (ret)
7249                 goto err;
7250
7251         ret = intel_ring_begin(ring, 4);
7252         if (ret)
7253                 goto err_unpin;
7254
7255         /* i965+ uses the linear or tiled offsets from the
7256          * Display Registers (which do not change across a page-flip)
7257          * so we need only reprogram the base address.
7258          */
7259         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7260                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7261         intel_ring_emit(ring, fb->pitches[0]);
7262         intel_ring_emit(ring,
7263                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7264                         obj->tiling_mode);
7265
7266         /* XXX Enabling the panel-fitter across page-flip is so far
7267          * untested on non-native modes, so ignore it for now.
7268          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7269          */
7270         pf = 0;
7271         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7272         intel_ring_emit(ring, pf | pipesrc);
7273
7274         intel_mark_page_flip_active(intel_crtc);
7275         intel_ring_advance(ring);
7276         return 0;
7277
7278 err_unpin:
7279         intel_unpin_fb_obj(obj);
7280 err:
7281         return ret;
7282 }
7283
7284 static int intel_gen6_queue_flip(struct drm_device *dev,
7285                                  struct drm_crtc *crtc,
7286                                  struct drm_framebuffer *fb,
7287                                  struct drm_i915_gem_object *obj)
7288 {
7289         struct drm_i915_private *dev_priv = dev->dev_private;
7290         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7291         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7292         uint32_t pf, pipesrc;
7293         int ret;
7294
7295         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7296         if (ret)
7297                 goto err;
7298
7299         ret = intel_ring_begin(ring, 4);
7300         if (ret)
7301                 goto err_unpin;
7302
7303         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7304                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7305         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7306         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7307
7308         /* Contrary to the suggestions in the documentation,
7309          * "Enable Panel Fitter" does not seem to be required when page
7310          * flipping with a non-native mode, and worse causes a normal
7311          * modeset to fail.
7312          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7313          */
7314         pf = 0;
7315         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7316         intel_ring_emit(ring, pf | pipesrc);
7317
7318         intel_mark_page_flip_active(intel_crtc);
7319         intel_ring_advance(ring);
7320         return 0;
7321
7322 err_unpin:
7323         intel_unpin_fb_obj(obj);
7324 err:
7325         return ret;
7326 }
7327
7328 /*
7329  * On gen7 we currently use the blit ring because (in early silicon at least)
7330  * the render ring doesn't give us interrpts for page flip completion, which
7331  * means clients will hang after the first flip is queued.  Fortunately the
7332  * blit ring generates interrupts properly, so use it instead.
7333  */
7334 static int intel_gen7_queue_flip(struct drm_device *dev,
7335                                  struct drm_crtc *crtc,
7336                                  struct drm_framebuffer *fb,
7337                                  struct drm_i915_gem_object *obj)
7338 {
7339         struct drm_i915_private *dev_priv = dev->dev_private;
7340         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7341         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7342         uint32_t plane_bit = 0;
7343         int ret;
7344
7345         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7346         if (ret)
7347                 goto err;
7348
7349         switch(intel_crtc->plane) {
7350         case PLANE_A:
7351                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7352                 break;
7353         case PLANE_B:
7354                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7355                 break;
7356         case PLANE_C:
7357                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7358                 break;
7359         default:
7360                 WARN_ONCE(1, "unknown plane in flip command\n");
7361                 ret = -ENODEV;
7362                 goto err_unpin;
7363         }
7364
7365         ret = intel_ring_begin(ring, 4);
7366         if (ret)
7367                 goto err_unpin;
7368
7369         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7370         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7371         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7372         intel_ring_emit(ring, (MI_NOOP));
7373
7374         intel_mark_page_flip_active(intel_crtc);
7375         intel_ring_advance(ring);
7376         return 0;
7377
7378 err_unpin:
7379         intel_unpin_fb_obj(obj);
7380 err:
7381         return ret;
7382 }
7383
7384 static int intel_default_queue_flip(struct drm_device *dev,
7385                                     struct drm_crtc *crtc,
7386                                     struct drm_framebuffer *fb,
7387                                     struct drm_i915_gem_object *obj)
7388 {
7389         return -ENODEV;
7390 }
7391
7392 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7393                                 struct drm_framebuffer *fb,
7394                                 struct drm_pending_vblank_event *event)
7395 {
7396         struct drm_device *dev = crtc->dev;
7397         struct drm_i915_private *dev_priv = dev->dev_private;
7398         struct drm_framebuffer *old_fb = crtc->fb;
7399         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7400         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7401         struct intel_unpin_work *work;
7402         unsigned long flags;
7403         int ret;
7404
7405         /* Can't change pixel format via MI display flips. */
7406         if (fb->pixel_format != crtc->fb->pixel_format)
7407                 return -EINVAL;
7408
7409         /*
7410          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7411          * Note that pitch changes could also affect these register.
7412          */
7413         if (INTEL_INFO(dev)->gen > 3 &&
7414             (fb->offsets[0] != crtc->fb->offsets[0] ||
7415              fb->pitches[0] != crtc->fb->pitches[0]))
7416                 return -EINVAL;
7417
7418         work = kzalloc(sizeof *work, GFP_KERNEL);
7419         if (work == NULL)
7420                 return -ENOMEM;
7421
7422         work->event = event;
7423         work->crtc = crtc;
7424         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7425         INIT_WORK(&work->work, intel_unpin_work_fn);
7426
7427         ret = drm_vblank_get(dev, intel_crtc->pipe);
7428         if (ret)
7429                 goto free_work;
7430
7431         /* We borrow the event spin lock for protecting unpin_work */
7432         spin_lock_irqsave(&dev->event_lock, flags);
7433         if (intel_crtc->unpin_work) {
7434                 spin_unlock_irqrestore(&dev->event_lock, flags);
7435                 kfree(work);
7436                 drm_vblank_put(dev, intel_crtc->pipe);
7437
7438                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7439                 return -EBUSY;
7440         }
7441         intel_crtc->unpin_work = work;
7442         spin_unlock_irqrestore(&dev->event_lock, flags);
7443
7444         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7445                 flush_workqueue(dev_priv->wq);
7446
7447         ret = i915_mutex_lock_interruptible(dev);
7448         if (ret)
7449                 goto cleanup;
7450
7451         /* Reference the objects for the scheduled work. */
7452         drm_gem_object_reference(&work->old_fb_obj->base);
7453         drm_gem_object_reference(&obj->base);
7454
7455         crtc->fb = fb;
7456
7457         work->pending_flip_obj = obj;
7458
7459         work->enable_stall_check = true;
7460
7461         atomic_inc(&intel_crtc->unpin_work_count);
7462         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7463
7464         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7465         if (ret)
7466                 goto cleanup_pending;
7467
7468         intel_disable_fbc(dev);
7469         intel_mark_fb_busy(obj);
7470         mutex_unlock(&dev->struct_mutex);
7471
7472         trace_i915_flip_request(intel_crtc->plane, obj);
7473
7474         return 0;
7475
7476 cleanup_pending:
7477         atomic_dec(&intel_crtc->unpin_work_count);
7478         crtc->fb = old_fb;
7479         drm_gem_object_unreference(&work->old_fb_obj->base);
7480         drm_gem_object_unreference(&obj->base);
7481         mutex_unlock(&dev->struct_mutex);
7482
7483 cleanup:
7484         spin_lock_irqsave(&dev->event_lock, flags);
7485         intel_crtc->unpin_work = NULL;
7486         spin_unlock_irqrestore(&dev->event_lock, flags);
7487
7488         drm_vblank_put(dev, intel_crtc->pipe);
7489 free_work:
7490         kfree(work);
7491
7492         return ret;
7493 }
7494
7495 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7496         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7497         .load_lut = intel_crtc_load_lut,
7498 };
7499
7500 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7501 {
7502         struct intel_encoder *other_encoder;
7503         struct drm_crtc *crtc = &encoder->new_crtc->base;
7504
7505         if (WARN_ON(!crtc))
7506                 return false;
7507
7508         list_for_each_entry(other_encoder,
7509                             &crtc->dev->mode_config.encoder_list,
7510                             base.head) {
7511
7512                 if (&other_encoder->new_crtc->base != crtc ||
7513                     encoder == other_encoder)
7514                         continue;
7515                 else
7516                         return true;
7517         }
7518
7519         return false;
7520 }
7521
7522 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7523                                   struct drm_crtc *crtc)
7524 {
7525         struct drm_device *dev;
7526         struct drm_crtc *tmp;
7527         int crtc_mask = 1;
7528
7529         WARN(!crtc, "checking null crtc?\n");
7530
7531         dev = crtc->dev;
7532
7533         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7534                 if (tmp == crtc)
7535                         break;
7536                 crtc_mask <<= 1;
7537         }
7538
7539         if (encoder->possible_crtcs & crtc_mask)
7540                 return true;
7541         return false;
7542 }
7543
7544 /**
7545  * intel_modeset_update_staged_output_state
7546  *
7547  * Updates the staged output configuration state, e.g. after we've read out the
7548  * current hw state.
7549  */
7550 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7551 {
7552         struct intel_encoder *encoder;
7553         struct intel_connector *connector;
7554
7555         list_for_each_entry(connector, &dev->mode_config.connector_list,
7556                             base.head) {
7557                 connector->new_encoder =
7558                         to_intel_encoder(connector->base.encoder);
7559         }
7560
7561         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7562                             base.head) {
7563                 encoder->new_crtc =
7564                         to_intel_crtc(encoder->base.crtc);
7565         }
7566 }
7567
7568 /**
7569  * intel_modeset_commit_output_state
7570  *
7571  * This function copies the stage display pipe configuration to the real one.
7572  */
7573 static void intel_modeset_commit_output_state(struct drm_device *dev)
7574 {
7575         struct intel_encoder *encoder;
7576         struct intel_connector *connector;
7577
7578         list_for_each_entry(connector, &dev->mode_config.connector_list,
7579                             base.head) {
7580                 connector->base.encoder = &connector->new_encoder->base;
7581         }
7582
7583         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7584                             base.head) {
7585                 encoder->base.crtc = &encoder->new_crtc->base;
7586         }
7587 }
7588
7589 static int
7590 pipe_config_set_bpp(struct drm_crtc *crtc,
7591                     struct drm_framebuffer *fb,
7592                     struct intel_crtc_config *pipe_config)
7593 {
7594         struct drm_device *dev = crtc->dev;
7595         struct drm_connector *connector;
7596         int bpp;
7597
7598         switch (fb->pixel_format) {
7599         case DRM_FORMAT_C8:
7600                 bpp = 8*3; /* since we go through a colormap */
7601                 break;
7602         case DRM_FORMAT_XRGB1555:
7603         case DRM_FORMAT_ARGB1555:
7604                 /* checked in intel_framebuffer_init already */
7605                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7606                         return -EINVAL;
7607         case DRM_FORMAT_RGB565:
7608                 bpp = 6*3; /* min is 18bpp */
7609                 break;
7610         case DRM_FORMAT_XBGR8888:
7611         case DRM_FORMAT_ABGR8888:
7612                 /* checked in intel_framebuffer_init already */
7613                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7614                         return -EINVAL;
7615         case DRM_FORMAT_XRGB8888:
7616         case DRM_FORMAT_ARGB8888:
7617                 bpp = 8*3;
7618                 break;
7619         case DRM_FORMAT_XRGB2101010:
7620         case DRM_FORMAT_ARGB2101010:
7621         case DRM_FORMAT_XBGR2101010:
7622         case DRM_FORMAT_ABGR2101010:
7623                 /* checked in intel_framebuffer_init already */
7624                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7625                         return -EINVAL;
7626                 bpp = 10*3;
7627                 break;
7628         /* TODO: gen4+ supports 16 bpc floating point, too. */
7629         default:
7630                 DRM_DEBUG_KMS("unsupported depth\n");
7631                 return -EINVAL;
7632         }
7633
7634         pipe_config->pipe_bpp = bpp;
7635
7636         /* Clamp display bpp to EDID value */
7637         list_for_each_entry(connector, &dev->mode_config.connector_list,
7638                             head) {
7639                 if (connector->encoder && connector->encoder->crtc != crtc)
7640                         continue;
7641
7642                 /* Don't use an invalid EDID bpc value */
7643                 if (connector->display_info.bpc &&
7644                     connector->display_info.bpc * 3 < bpp) {
7645                         DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7646                                       bpp, connector->display_info.bpc*3);
7647                         pipe_config->pipe_bpp = connector->display_info.bpc*3;
7648                 }
7649
7650                 /* Clamp bpp to 8 on screens without EDID 1.4 */
7651                 if (connector->display_info.bpc == 0 && bpp > 24) {
7652                         DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7653                                       bpp);
7654                         pipe_config->pipe_bpp = 24;
7655                 }
7656         }
7657
7658         return bpp;
7659 }
7660
7661 static struct intel_crtc_config *
7662 intel_modeset_pipe_config(struct drm_crtc *crtc,
7663                           struct drm_framebuffer *fb,
7664                           struct drm_display_mode *mode)
7665 {
7666         struct drm_device *dev = crtc->dev;
7667         struct drm_encoder_helper_funcs *encoder_funcs;
7668         struct intel_encoder *encoder;
7669         struct intel_crtc_config *pipe_config;
7670         int plane_bpp;
7671
7672         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7673         if (!pipe_config)
7674                 return ERR_PTR(-ENOMEM);
7675
7676         drm_mode_copy(&pipe_config->adjusted_mode, mode);
7677         drm_mode_copy(&pipe_config->requested_mode, mode);
7678
7679         plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
7680         if (plane_bpp < 0)
7681                 goto fail;
7682
7683         /* Pass our mode to the connectors and the CRTC to give them a chance to
7684          * adjust it according to limitations or connector properties, and also
7685          * a chance to reject the mode entirely.
7686          */
7687         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7688                             base.head) {
7689
7690                 if (&encoder->new_crtc->base != crtc)
7691                         continue;
7692
7693                 if (encoder->compute_config) {
7694                         if (!(encoder->compute_config(encoder, pipe_config))) {
7695                                 DRM_DEBUG_KMS("Encoder config failure\n");
7696                                 goto fail;
7697                         }
7698
7699                         continue;
7700                 }
7701
7702                 encoder_funcs = encoder->base.helper_private;
7703                 if (!(encoder_funcs->mode_fixup(&encoder->base,
7704                                                 &pipe_config->requested_mode,
7705                                                 &pipe_config->adjusted_mode))) {
7706                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7707                         goto fail;
7708                 }
7709         }
7710
7711         if (!(intel_crtc_compute_config(crtc, pipe_config))) {
7712                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7713                 goto fail;
7714         }
7715         DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7716
7717         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7718         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7719                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7720
7721         return pipe_config;
7722 fail:
7723         kfree(pipe_config);
7724         return ERR_PTR(-EINVAL);
7725 }
7726
7727 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7728  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7729 static void
7730 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7731                              unsigned *prepare_pipes, unsigned *disable_pipes)
7732 {
7733         struct intel_crtc *intel_crtc;
7734         struct drm_device *dev = crtc->dev;
7735         struct intel_encoder *encoder;
7736         struct intel_connector *connector;
7737         struct drm_crtc *tmp_crtc;
7738
7739         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7740
7741         /* Check which crtcs have changed outputs connected to them, these need
7742          * to be part of the prepare_pipes mask. We don't (yet) support global
7743          * modeset across multiple crtcs, so modeset_pipes will only have one
7744          * bit set at most. */
7745         list_for_each_entry(connector, &dev->mode_config.connector_list,
7746                             base.head) {
7747                 if (connector->base.encoder == &connector->new_encoder->base)
7748                         continue;
7749
7750                 if (connector->base.encoder) {
7751                         tmp_crtc = connector->base.encoder->crtc;
7752
7753                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7754                 }
7755
7756                 if (connector->new_encoder)
7757                         *prepare_pipes |=
7758                                 1 << connector->new_encoder->new_crtc->pipe;
7759         }
7760
7761         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7762                             base.head) {
7763                 if (encoder->base.crtc == &encoder->new_crtc->base)
7764                         continue;
7765
7766                 if (encoder->base.crtc) {
7767                         tmp_crtc = encoder->base.crtc;
7768
7769                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7770                 }
7771
7772                 if (encoder->new_crtc)
7773                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7774         }
7775
7776         /* Check for any pipes that will be fully disabled ... */
7777         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7778                             base.head) {
7779                 bool used = false;
7780
7781                 /* Don't try to disable disabled crtcs. */
7782                 if (!intel_crtc->base.enabled)
7783                         continue;
7784
7785                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7786                                     base.head) {
7787                         if (encoder->new_crtc == intel_crtc)
7788                                 used = true;
7789                 }
7790
7791                 if (!used)
7792                         *disable_pipes |= 1 << intel_crtc->pipe;
7793         }
7794
7795
7796         /* set_mode is also used to update properties on life display pipes. */
7797         intel_crtc = to_intel_crtc(crtc);
7798         if (crtc->enabled)
7799                 *prepare_pipes |= 1 << intel_crtc->pipe;
7800
7801         /*
7802          * For simplicity do a full modeset on any pipe where the output routing
7803          * changed. We could be more clever, but that would require us to be
7804          * more careful with calling the relevant encoder->mode_set functions.
7805          */
7806         if (*prepare_pipes)
7807                 *modeset_pipes = *prepare_pipes;
7808
7809         /* ... and mask these out. */
7810         *modeset_pipes &= ~(*disable_pipes);
7811         *prepare_pipes &= ~(*disable_pipes);
7812
7813         /*
7814          * HACK: We don't (yet) fully support global modesets. intel_set_config
7815          * obies this rule, but the modeset restore mode of
7816          * intel_modeset_setup_hw_state does not.
7817          */
7818         *modeset_pipes &= 1 << intel_crtc->pipe;
7819         *prepare_pipes &= 1 << intel_crtc->pipe;
7820
7821         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7822                       *modeset_pipes, *prepare_pipes, *disable_pipes);
7823 }
7824
7825 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7826 {
7827         struct drm_encoder *encoder;
7828         struct drm_device *dev = crtc->dev;
7829
7830         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7831                 if (encoder->crtc == crtc)
7832                         return true;
7833
7834         return false;
7835 }
7836
7837 static void
7838 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7839 {
7840         struct intel_encoder *intel_encoder;
7841         struct intel_crtc *intel_crtc;
7842         struct drm_connector *connector;
7843
7844         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7845                             base.head) {
7846                 if (!intel_encoder->base.crtc)
7847                         continue;
7848
7849                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7850
7851                 if (prepare_pipes & (1 << intel_crtc->pipe))
7852                         intel_encoder->connectors_active = false;
7853         }
7854
7855         intel_modeset_commit_output_state(dev);
7856
7857         /* Update computed state. */
7858         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7859                             base.head) {
7860                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7861         }
7862
7863         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7864                 if (!connector->encoder || !connector->encoder->crtc)
7865                         continue;
7866
7867                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7868
7869                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7870                         struct drm_property *dpms_property =
7871                                 dev->mode_config.dpms_property;
7872
7873                         connector->dpms = DRM_MODE_DPMS_ON;
7874                         drm_object_property_set_value(&connector->base,
7875                                                          dpms_property,
7876                                                          DRM_MODE_DPMS_ON);
7877
7878                         intel_encoder = to_intel_encoder(connector->encoder);
7879                         intel_encoder->connectors_active = true;
7880                 }
7881         }
7882
7883 }
7884
7885 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7886         list_for_each_entry((intel_crtc), \
7887                             &(dev)->mode_config.crtc_list, \
7888                             base.head) \
7889                 if (mask & (1 <<(intel_crtc)->pipe)) \
7890
7891 static bool
7892 intel_pipe_config_compare(struct intel_crtc_config *current_config,
7893                           struct intel_crtc_config *pipe_config)
7894 {
7895         if (current_config->has_pch_encoder != pipe_config->has_pch_encoder) {
7896                 DRM_ERROR("mismatch in has_pch_encoder "
7897                           "(expected %i, found %i)\n",
7898                           current_config->has_pch_encoder,
7899                           pipe_config->has_pch_encoder);
7900                 return false;
7901         }
7902
7903         if (current_config->fdi_lanes != pipe_config->fdi_lanes) {
7904                 DRM_ERROR("mismatch in fdi_lanes "
7905                           "(expected %i, found %i)\n",
7906                           current_config->fdi_lanes,
7907                           pipe_config->fdi_lanes);
7908                 return false;
7909         }
7910
7911         return true;
7912 }
7913
7914 void
7915 intel_modeset_check_state(struct drm_device *dev)
7916 {
7917         drm_i915_private_t *dev_priv = dev->dev_private;
7918         struct intel_crtc *crtc;
7919         struct intel_encoder *encoder;
7920         struct intel_connector *connector;
7921         struct intel_crtc_config pipe_config;
7922
7923         list_for_each_entry(connector, &dev->mode_config.connector_list,
7924                             base.head) {
7925                 /* This also checks the encoder/connector hw state with the
7926                  * ->get_hw_state callbacks. */
7927                 intel_connector_check_state(connector);
7928
7929                 WARN(&connector->new_encoder->base != connector->base.encoder,
7930                      "connector's staged encoder doesn't match current encoder\n");
7931         }
7932
7933         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7934                             base.head) {
7935                 bool enabled = false;
7936                 bool active = false;
7937                 enum pipe pipe, tracked_pipe;
7938
7939                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7940                               encoder->base.base.id,
7941                               drm_get_encoder_name(&encoder->base));
7942
7943                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7944                      "encoder's stage crtc doesn't match current crtc\n");
7945                 WARN(encoder->connectors_active && !encoder->base.crtc,
7946                      "encoder's active_connectors set, but no crtc\n");
7947
7948                 list_for_each_entry(connector, &dev->mode_config.connector_list,
7949                                     base.head) {
7950                         if (connector->base.encoder != &encoder->base)
7951                                 continue;
7952                         enabled = true;
7953                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7954                                 active = true;
7955                 }
7956                 WARN(!!encoder->base.crtc != enabled,
7957                      "encoder's enabled state mismatch "
7958                      "(expected %i, found %i)\n",
7959                      !!encoder->base.crtc, enabled);
7960                 WARN(active && !encoder->base.crtc,
7961                      "active encoder with no crtc\n");
7962
7963                 WARN(encoder->connectors_active != active,
7964                      "encoder's computed active state doesn't match tracked active state "
7965                      "(expected %i, found %i)\n", active, encoder->connectors_active);
7966
7967                 active = encoder->get_hw_state(encoder, &pipe);
7968                 WARN(active != encoder->connectors_active,
7969                      "encoder's hw state doesn't match sw tracking "
7970                      "(expected %i, found %i)\n",
7971                      encoder->connectors_active, active);
7972
7973                 if (!encoder->base.crtc)
7974                         continue;
7975
7976                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7977                 WARN(active && pipe != tracked_pipe,
7978                      "active encoder's pipe doesn't match"
7979                      "(expected %i, found %i)\n",
7980                      tracked_pipe, pipe);
7981
7982         }
7983
7984         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7985                             base.head) {
7986                 bool enabled = false;
7987                 bool active = false;
7988
7989                 DRM_DEBUG_KMS("[CRTC:%d]\n",
7990                               crtc->base.base.id);
7991
7992                 WARN(crtc->active && !crtc->base.enabled,
7993                      "active crtc, but not enabled in sw tracking\n");
7994
7995                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7996                                     base.head) {
7997                         if (encoder->base.crtc != &crtc->base)
7998                                 continue;
7999                         enabled = true;
8000                         if (encoder->connectors_active)
8001                                 active = true;
8002                 }
8003                 WARN(active != crtc->active,
8004                      "crtc's computed active state doesn't match tracked active state "
8005                      "(expected %i, found %i)\n", active, crtc->active);
8006                 WARN(enabled != crtc->base.enabled,
8007                      "crtc's computed enabled state doesn't match tracked enabled state "
8008                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8009
8010                 memset(&pipe_config, 0, sizeof(pipe_config));
8011                 pipe_config.cpu_transcoder = crtc->config.cpu_transcoder;
8012                 active = dev_priv->display.get_pipe_config(crtc,
8013                                                            &pipe_config);
8014                 WARN(crtc->active != active,
8015                      "crtc active state doesn't match with hw state "
8016                      "(expected %i, found %i)\n", crtc->active, active);
8017
8018                 WARN(active &&
8019                      !intel_pipe_config_compare(&crtc->config, &pipe_config),
8020                      "pipe state doesn't match!\n");
8021         }
8022 }
8023
8024 static int __intel_set_mode(struct drm_crtc *crtc,
8025                             struct drm_display_mode *mode,
8026                             int x, int y, struct drm_framebuffer *fb)
8027 {
8028         struct drm_device *dev = crtc->dev;
8029         drm_i915_private_t *dev_priv = dev->dev_private;
8030         struct drm_display_mode *saved_mode, *saved_hwmode;
8031         struct intel_crtc_config *pipe_config = NULL;
8032         struct intel_crtc *intel_crtc;
8033         unsigned disable_pipes, prepare_pipes, modeset_pipes;
8034         int ret = 0;
8035
8036         saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
8037         if (!saved_mode)
8038                 return -ENOMEM;
8039         saved_hwmode = saved_mode + 1;
8040
8041         intel_modeset_affected_pipes(crtc, &modeset_pipes,
8042                                      &prepare_pipes, &disable_pipes);
8043
8044         *saved_hwmode = crtc->hwmode;
8045         *saved_mode = crtc->mode;
8046
8047         /* Hack: Because we don't (yet) support global modeset on multiple
8048          * crtcs, we don't keep track of the new mode for more than one crtc.
8049          * Hence simply check whether any bit is set in modeset_pipes in all the
8050          * pieces of code that are not yet converted to deal with mutliple crtcs
8051          * changing their mode at the same time. */
8052         if (modeset_pipes) {
8053                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8054                 if (IS_ERR(pipe_config)) {
8055                         ret = PTR_ERR(pipe_config);
8056                         pipe_config = NULL;
8057
8058                         goto out;
8059                 }
8060         }
8061
8062         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8063                 intel_crtc_disable(&intel_crtc->base);
8064
8065         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8066                 if (intel_crtc->base.enabled)
8067                         dev_priv->display.crtc_disable(&intel_crtc->base);
8068         }
8069
8070         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8071          * to set it here already despite that we pass it down the callchain.
8072          */
8073         if (modeset_pipes) {
8074                 enum transcoder tmp = to_intel_crtc(crtc)->config.cpu_transcoder;
8075                 crtc->mode = *mode;
8076                 /* mode_set/enable/disable functions rely on a correct pipe
8077                  * config. */
8078                 to_intel_crtc(crtc)->config = *pipe_config;
8079                 to_intel_crtc(crtc)->config.cpu_transcoder = tmp;
8080         }
8081
8082         /* Only after disabling all output pipelines that will be changed can we
8083          * update the the output configuration. */
8084         intel_modeset_update_state(dev, prepare_pipes);
8085
8086         if (dev_priv->display.modeset_global_resources)
8087                 dev_priv->display.modeset_global_resources(dev);
8088
8089         /* Set up the DPLL and any encoders state that needs to adjust or depend
8090          * on the DPLL.
8091          */
8092         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8093                 ret = intel_crtc_mode_set(&intel_crtc->base,
8094                                           x, y, fb);
8095                 if (ret)
8096                         goto done;
8097         }
8098
8099         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8100         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8101                 dev_priv->display.crtc_enable(&intel_crtc->base);
8102
8103         if (modeset_pipes) {
8104                 /* Store real post-adjustment hardware mode. */
8105                 crtc->hwmode = pipe_config->adjusted_mode;
8106
8107                 /* Calculate and store various constants which
8108                  * are later needed by vblank and swap-completion
8109                  * timestamping. They are derived from true hwmode.
8110                  */
8111                 drm_calc_timestamping_constants(crtc);
8112         }
8113
8114         /* FIXME: add subpixel order */
8115 done:
8116         if (ret && crtc->enabled) {
8117                 crtc->hwmode = *saved_hwmode;
8118                 crtc->mode = *saved_mode;
8119         }
8120
8121 out:
8122         kfree(pipe_config);
8123         kfree(saved_mode);
8124         return ret;
8125 }
8126
8127 int intel_set_mode(struct drm_crtc *crtc,
8128                      struct drm_display_mode *mode,
8129                      int x, int y, struct drm_framebuffer *fb)
8130 {
8131         int ret;
8132
8133         ret = __intel_set_mode(crtc, mode, x, y, fb);
8134
8135         if (ret == 0)
8136                 intel_modeset_check_state(crtc->dev);
8137
8138         return ret;
8139 }
8140
8141 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8142 {
8143         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8144 }
8145
8146 #undef for_each_intel_crtc_masked
8147
8148 static void intel_set_config_free(struct intel_set_config *config)
8149 {
8150         if (!config)
8151                 return;
8152
8153         kfree(config->save_connector_encoders);
8154         kfree(config->save_encoder_crtcs);
8155         kfree(config);
8156 }
8157
8158 static int intel_set_config_save_state(struct drm_device *dev,
8159                                        struct intel_set_config *config)
8160 {
8161         struct drm_encoder *encoder;
8162         struct drm_connector *connector;
8163         int count;
8164
8165         config->save_encoder_crtcs =
8166                 kcalloc(dev->mode_config.num_encoder,
8167                         sizeof(struct drm_crtc *), GFP_KERNEL);
8168         if (!config->save_encoder_crtcs)
8169                 return -ENOMEM;
8170
8171         config->save_connector_encoders =
8172                 kcalloc(dev->mode_config.num_connector,
8173                         sizeof(struct drm_encoder *), GFP_KERNEL);
8174         if (!config->save_connector_encoders)
8175                 return -ENOMEM;
8176
8177         /* Copy data. Note that driver private data is not affected.
8178          * Should anything bad happen only the expected state is
8179          * restored, not the drivers personal bookkeeping.
8180          */
8181         count = 0;
8182         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8183                 config->save_encoder_crtcs[count++] = encoder->crtc;
8184         }
8185
8186         count = 0;
8187         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8188                 config->save_connector_encoders[count++] = connector->encoder;
8189         }
8190
8191         return 0;
8192 }
8193
8194 static void intel_set_config_restore_state(struct drm_device *dev,
8195                                            struct intel_set_config *config)
8196 {
8197         struct intel_encoder *encoder;
8198         struct intel_connector *connector;
8199         int count;
8200
8201         count = 0;
8202         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8203                 encoder->new_crtc =
8204                         to_intel_crtc(config->save_encoder_crtcs[count++]);
8205         }
8206
8207         count = 0;
8208         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8209                 connector->new_encoder =
8210                         to_intel_encoder(config->save_connector_encoders[count++]);
8211         }
8212 }
8213
8214 static void
8215 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8216                                       struct intel_set_config *config)
8217 {
8218
8219         /* We should be able to check here if the fb has the same properties
8220          * and then just flip_or_move it */
8221         if (set->crtc->fb != set->fb) {
8222                 /* If we have no fb then treat it as a full mode set */
8223                 if (set->crtc->fb == NULL) {
8224                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8225                         config->mode_changed = true;
8226                 } else if (set->fb == NULL) {
8227                         config->mode_changed = true;
8228                 } else if (set->fb->pixel_format !=
8229                            set->crtc->fb->pixel_format) {
8230                         config->mode_changed = true;
8231                 } else
8232                         config->fb_changed = true;
8233         }
8234
8235         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8236                 config->fb_changed = true;
8237
8238         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8239                 DRM_DEBUG_KMS("modes are different, full mode set\n");
8240                 drm_mode_debug_printmodeline(&set->crtc->mode);
8241                 drm_mode_debug_printmodeline(set->mode);
8242                 config->mode_changed = true;
8243         }
8244 }
8245
8246 static int
8247 intel_modeset_stage_output_state(struct drm_device *dev,
8248                                  struct drm_mode_set *set,
8249                                  struct intel_set_config *config)
8250 {
8251         struct drm_crtc *new_crtc;
8252         struct intel_connector *connector;
8253         struct intel_encoder *encoder;
8254         int count, ro;
8255
8256         /* The upper layers ensure that we either disable a crtc or have a list
8257          * of connectors. For paranoia, double-check this. */
8258         WARN_ON(!set->fb && (set->num_connectors != 0));
8259         WARN_ON(set->fb && (set->num_connectors == 0));
8260
8261         count = 0;
8262         list_for_each_entry(connector, &dev->mode_config.connector_list,
8263                             base.head) {
8264                 /* Otherwise traverse passed in connector list and get encoders
8265                  * for them. */
8266                 for (ro = 0; ro < set->num_connectors; ro++) {
8267                         if (set->connectors[ro] == &connector->base) {
8268                                 connector->new_encoder = connector->encoder;
8269                                 break;
8270                         }
8271                 }
8272
8273                 /* If we disable the crtc, disable all its connectors. Also, if
8274                  * the connector is on the changing crtc but not on the new
8275                  * connector list, disable it. */
8276                 if ((!set->fb || ro == set->num_connectors) &&
8277                     connector->base.encoder &&
8278                     connector->base.encoder->crtc == set->crtc) {
8279                         connector->new_encoder = NULL;
8280
8281                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8282                                 connector->base.base.id,
8283                                 drm_get_connector_name(&connector->base));
8284                 }
8285
8286
8287                 if (&connector->new_encoder->base != connector->base.encoder) {
8288                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8289                         config->mode_changed = true;
8290                 }
8291         }
8292         /* connector->new_encoder is now updated for all connectors. */
8293
8294         /* Update crtc of enabled connectors. */
8295         count = 0;
8296         list_for_each_entry(connector, &dev->mode_config.connector_list,
8297                             base.head) {
8298                 if (!connector->new_encoder)
8299                         continue;
8300
8301                 new_crtc = connector->new_encoder->base.crtc;
8302
8303                 for (ro = 0; ro < set->num_connectors; ro++) {
8304                         if (set->connectors[ro] == &connector->base)
8305                                 new_crtc = set->crtc;
8306                 }
8307
8308                 /* Make sure the new CRTC will work with the encoder */
8309                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8310                                            new_crtc)) {
8311                         return -EINVAL;
8312                 }
8313                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8314
8315                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8316                         connector->base.base.id,
8317                         drm_get_connector_name(&connector->base),
8318                         new_crtc->base.id);
8319         }
8320
8321         /* Check for any encoders that needs to be disabled. */
8322         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8323                             base.head) {
8324                 list_for_each_entry(connector,
8325                                     &dev->mode_config.connector_list,
8326                                     base.head) {
8327                         if (connector->new_encoder == encoder) {
8328                                 WARN_ON(!connector->new_encoder->new_crtc);
8329
8330                                 goto next_encoder;
8331                         }
8332                 }
8333                 encoder->new_crtc = NULL;
8334 next_encoder:
8335                 /* Only now check for crtc changes so we don't miss encoders
8336                  * that will be disabled. */
8337                 if (&encoder->new_crtc->base != encoder->base.crtc) {
8338                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8339                         config->mode_changed = true;
8340                 }
8341         }
8342         /* Now we've also updated encoder->new_crtc for all encoders. */
8343
8344         return 0;
8345 }
8346
8347 static int intel_crtc_set_config(struct drm_mode_set *set)
8348 {
8349         struct drm_device *dev;
8350         struct drm_mode_set save_set;
8351         struct intel_set_config *config;
8352         int ret;
8353
8354         BUG_ON(!set);
8355         BUG_ON(!set->crtc);
8356         BUG_ON(!set->crtc->helper_private);
8357
8358         /* Enforce sane interface api - has been abused by the fb helper. */
8359         BUG_ON(!set->mode && set->fb);
8360         BUG_ON(set->fb && set->num_connectors == 0);
8361
8362         if (set->fb) {
8363                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8364                                 set->crtc->base.id, set->fb->base.id,
8365                                 (int)set->num_connectors, set->x, set->y);
8366         } else {
8367                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8368         }
8369
8370         dev = set->crtc->dev;
8371
8372         ret = -ENOMEM;
8373         config = kzalloc(sizeof(*config), GFP_KERNEL);
8374         if (!config)
8375                 goto out_config;
8376
8377         ret = intel_set_config_save_state(dev, config);
8378         if (ret)
8379                 goto out_config;
8380
8381         save_set.crtc = set->crtc;
8382         save_set.mode = &set->crtc->mode;
8383         save_set.x = set->crtc->x;
8384         save_set.y = set->crtc->y;
8385         save_set.fb = set->crtc->fb;
8386
8387         /* Compute whether we need a full modeset, only an fb base update or no
8388          * change at all. In the future we might also check whether only the
8389          * mode changed, e.g. for LVDS where we only change the panel fitter in
8390          * such cases. */
8391         intel_set_config_compute_mode_changes(set, config);
8392
8393         ret = intel_modeset_stage_output_state(dev, set, config);
8394         if (ret)
8395                 goto fail;
8396
8397         if (config->mode_changed) {
8398                 if (set->mode) {
8399                         DRM_DEBUG_KMS("attempting to set mode from"
8400                                         " userspace\n");
8401                         drm_mode_debug_printmodeline(set->mode);
8402                 }
8403
8404                 ret = intel_set_mode(set->crtc, set->mode,
8405                                      set->x, set->y, set->fb);
8406                 if (ret) {
8407                         DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8408                                   set->crtc->base.id, ret);
8409                         goto fail;
8410                 }
8411         } else if (config->fb_changed) {
8412                 intel_crtc_wait_for_pending_flips(set->crtc);
8413
8414                 ret = intel_pipe_set_base(set->crtc,
8415                                           set->x, set->y, set->fb);
8416         }
8417
8418         intel_set_config_free(config);
8419
8420         return 0;
8421
8422 fail:
8423         intel_set_config_restore_state(dev, config);
8424
8425         /* Try to restore the config */
8426         if (config->mode_changed &&
8427             intel_set_mode(save_set.crtc, save_set.mode,
8428                            save_set.x, save_set.y, save_set.fb))
8429                 DRM_ERROR("failed to restore config after modeset failure\n");
8430
8431 out_config:
8432         intel_set_config_free(config);
8433         return ret;
8434 }
8435
8436 static const struct drm_crtc_funcs intel_crtc_funcs = {
8437         .cursor_set = intel_crtc_cursor_set,
8438         .cursor_move = intel_crtc_cursor_move,
8439         .gamma_set = intel_crtc_gamma_set,
8440         .set_config = intel_crtc_set_config,
8441         .destroy = intel_crtc_destroy,
8442         .page_flip = intel_crtc_page_flip,
8443 };
8444
8445 static void intel_cpu_pll_init(struct drm_device *dev)
8446 {
8447         if (HAS_DDI(dev))
8448                 intel_ddi_pll_init(dev);
8449 }
8450
8451 static void intel_pch_pll_init(struct drm_device *dev)
8452 {
8453         drm_i915_private_t *dev_priv = dev->dev_private;
8454         int i;
8455
8456         if (dev_priv->num_pch_pll == 0) {
8457                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8458                 return;
8459         }
8460
8461         for (i = 0; i < dev_priv->num_pch_pll; i++) {
8462                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8463                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8464                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8465         }
8466 }
8467
8468 static void intel_crtc_init(struct drm_device *dev, int pipe)
8469 {
8470         drm_i915_private_t *dev_priv = dev->dev_private;
8471         struct intel_crtc *intel_crtc;
8472         int i;
8473
8474         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8475         if (intel_crtc == NULL)
8476                 return;
8477
8478         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8479
8480         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8481         for (i = 0; i < 256; i++) {
8482                 intel_crtc->lut_r[i] = i;
8483                 intel_crtc->lut_g[i] = i;
8484                 intel_crtc->lut_b[i] = i;
8485         }
8486
8487         /* Swap pipes & planes for FBC on pre-965 */
8488         intel_crtc->pipe = pipe;
8489         intel_crtc->plane = pipe;
8490         intel_crtc->config.cpu_transcoder = pipe;
8491         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8492                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8493                 intel_crtc->plane = !pipe;
8494         }
8495
8496         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8497                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8498         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8499         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8500
8501         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8502 }
8503
8504 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8505                                 struct drm_file *file)
8506 {
8507         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8508         struct drm_mode_object *drmmode_obj;
8509         struct intel_crtc *crtc;
8510
8511         if (!drm_core_check_feature(dev, DRIVER_MODESET))
8512                 return -ENODEV;
8513
8514         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8515                         DRM_MODE_OBJECT_CRTC);
8516
8517         if (!drmmode_obj) {
8518                 DRM_ERROR("no such CRTC id\n");
8519                 return -EINVAL;
8520         }
8521
8522         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8523         pipe_from_crtc_id->pipe = crtc->pipe;
8524
8525         return 0;
8526 }
8527
8528 static int intel_encoder_clones(struct intel_encoder *encoder)
8529 {
8530         struct drm_device *dev = encoder->base.dev;
8531         struct intel_encoder *source_encoder;
8532         int index_mask = 0;
8533         int entry = 0;
8534
8535         list_for_each_entry(source_encoder,
8536                             &dev->mode_config.encoder_list, base.head) {
8537
8538                 if (encoder == source_encoder)
8539                         index_mask |= (1 << entry);
8540
8541                 /* Intel hw has only one MUX where enocoders could be cloned. */
8542                 if (encoder->cloneable && source_encoder->cloneable)
8543                         index_mask |= (1 << entry);
8544
8545                 entry++;
8546         }
8547
8548         return index_mask;
8549 }
8550
8551 static bool has_edp_a(struct drm_device *dev)
8552 {
8553         struct drm_i915_private *dev_priv = dev->dev_private;
8554
8555         if (!IS_MOBILE(dev))
8556                 return false;
8557
8558         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8559                 return false;
8560
8561         if (IS_GEN5(dev) &&
8562             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8563                 return false;
8564
8565         return true;
8566 }
8567
8568 static void intel_setup_outputs(struct drm_device *dev)
8569 {
8570         struct drm_i915_private *dev_priv = dev->dev_private;
8571         struct intel_encoder *encoder;
8572         bool dpd_is_edp = false;
8573         bool has_lvds;
8574
8575         has_lvds = intel_lvds_init(dev);
8576         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8577                 /* disable the panel fitter on everything but LVDS */
8578                 I915_WRITE(PFIT_CONTROL, 0);
8579         }
8580
8581         if (!IS_ULT(dev))
8582                 intel_crt_init(dev);
8583
8584         if (HAS_DDI(dev)) {
8585                 int found;
8586
8587                 /* Haswell uses DDI functions to detect digital outputs */
8588                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8589                 /* DDI A only supports eDP */
8590                 if (found)
8591                         intel_ddi_init(dev, PORT_A);
8592
8593                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8594                  * register */
8595                 found = I915_READ(SFUSE_STRAP);
8596
8597                 if (found & SFUSE_STRAP_DDIB_DETECTED)
8598                         intel_ddi_init(dev, PORT_B);
8599                 if (found & SFUSE_STRAP_DDIC_DETECTED)
8600                         intel_ddi_init(dev, PORT_C);
8601                 if (found & SFUSE_STRAP_DDID_DETECTED)
8602                         intel_ddi_init(dev, PORT_D);
8603         } else if (HAS_PCH_SPLIT(dev)) {
8604                 int found;
8605                 dpd_is_edp = intel_dpd_is_edp(dev);
8606
8607                 if (has_edp_a(dev))
8608                         intel_dp_init(dev, DP_A, PORT_A);
8609
8610                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
8611                         /* PCH SDVOB multiplex with HDMIB */
8612                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
8613                         if (!found)
8614                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
8615                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8616                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
8617                 }
8618
8619                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
8620                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
8621
8622                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
8623                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
8624
8625                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8626                         intel_dp_init(dev, PCH_DP_C, PORT_C);
8627
8628                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8629                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8630         } else if (IS_VALLEYVIEW(dev)) {
8631                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8632                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8633                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
8634
8635                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
8636                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8637                                         PORT_B);
8638                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8639                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
8640                 }
8641         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8642                 bool found = false;
8643
8644                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8645                         DRM_DEBUG_KMS("probing SDVOB\n");
8646                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
8647                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8648                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8649                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
8650                         }
8651
8652                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8653                                 DRM_DEBUG_KMS("probing DP_B\n");
8654                                 intel_dp_init(dev, DP_B, PORT_B);
8655                         }
8656                 }
8657
8658                 /* Before G4X SDVOC doesn't have its own detect register */
8659
8660                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8661                         DRM_DEBUG_KMS("probing SDVOC\n");
8662                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
8663                 }
8664
8665                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
8666
8667                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8668                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8669                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
8670                         }
8671                         if (SUPPORTS_INTEGRATED_DP(dev)) {
8672                                 DRM_DEBUG_KMS("probing DP_C\n");
8673                                 intel_dp_init(dev, DP_C, PORT_C);
8674                         }
8675                 }
8676
8677                 if (SUPPORTS_INTEGRATED_DP(dev) &&
8678                     (I915_READ(DP_D) & DP_DETECTED)) {
8679                         DRM_DEBUG_KMS("probing DP_D\n");
8680                         intel_dp_init(dev, DP_D, PORT_D);
8681                 }
8682         } else if (IS_GEN2(dev))
8683                 intel_dvo_init(dev);
8684
8685         if (SUPPORTS_TV(dev))
8686                 intel_tv_init(dev);
8687
8688         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8689                 encoder->base.possible_crtcs = encoder->crtc_mask;
8690                 encoder->base.possible_clones =
8691                         intel_encoder_clones(encoder);
8692         }
8693
8694         intel_init_pch_refclk(dev);
8695
8696         drm_helper_move_panel_connectors_to_head(dev);
8697 }
8698
8699 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8700 {
8701         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8702
8703         drm_framebuffer_cleanup(fb);
8704         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8705
8706         kfree(intel_fb);
8707 }
8708
8709 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8710                                                 struct drm_file *file,
8711                                                 unsigned int *handle)
8712 {
8713         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8714         struct drm_i915_gem_object *obj = intel_fb->obj;
8715
8716         return drm_gem_handle_create(file, &obj->base, handle);
8717 }
8718
8719 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8720         .destroy = intel_user_framebuffer_destroy,
8721         .create_handle = intel_user_framebuffer_create_handle,
8722 };
8723
8724 int intel_framebuffer_init(struct drm_device *dev,
8725                            struct intel_framebuffer *intel_fb,
8726                            struct drm_mode_fb_cmd2 *mode_cmd,
8727                            struct drm_i915_gem_object *obj)
8728 {
8729         int ret;
8730
8731         if (obj->tiling_mode == I915_TILING_Y) {
8732                 DRM_DEBUG("hardware does not support tiling Y\n");
8733                 return -EINVAL;
8734         }
8735
8736         if (mode_cmd->pitches[0] & 63) {
8737                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8738                           mode_cmd->pitches[0]);
8739                 return -EINVAL;
8740         }
8741
8742         /* FIXME <= Gen4 stride limits are bit unclear */
8743         if (mode_cmd->pitches[0] > 32768) {
8744                 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8745                           mode_cmd->pitches[0]);
8746                 return -EINVAL;
8747         }
8748
8749         if (obj->tiling_mode != I915_TILING_NONE &&
8750             mode_cmd->pitches[0] != obj->stride) {
8751                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8752                           mode_cmd->pitches[0], obj->stride);
8753                 return -EINVAL;
8754         }
8755
8756         /* Reject formats not supported by any plane early. */
8757         switch (mode_cmd->pixel_format) {
8758         case DRM_FORMAT_C8:
8759         case DRM_FORMAT_RGB565:
8760         case DRM_FORMAT_XRGB8888:
8761         case DRM_FORMAT_ARGB8888:
8762                 break;
8763         case DRM_FORMAT_XRGB1555:
8764         case DRM_FORMAT_ARGB1555:
8765                 if (INTEL_INFO(dev)->gen > 3) {
8766                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8767                         return -EINVAL;
8768                 }
8769                 break;
8770         case DRM_FORMAT_XBGR8888:
8771         case DRM_FORMAT_ABGR8888:
8772         case DRM_FORMAT_XRGB2101010:
8773         case DRM_FORMAT_ARGB2101010:
8774         case DRM_FORMAT_XBGR2101010:
8775         case DRM_FORMAT_ABGR2101010:
8776                 if (INTEL_INFO(dev)->gen < 4) {
8777                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8778                         return -EINVAL;
8779                 }
8780                 break;
8781         case DRM_FORMAT_YUYV:
8782         case DRM_FORMAT_UYVY:
8783         case DRM_FORMAT_YVYU:
8784         case DRM_FORMAT_VYUY:
8785                 if (INTEL_INFO(dev)->gen < 5) {
8786                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8787                         return -EINVAL;
8788                 }
8789                 break;
8790         default:
8791                 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8792                 return -EINVAL;
8793         }
8794
8795         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8796         if (mode_cmd->offsets[0] != 0)
8797                 return -EINVAL;
8798
8799         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8800         intel_fb->obj = obj;
8801
8802         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8803         if (ret) {
8804                 DRM_ERROR("framebuffer init failed %d\n", ret);
8805                 return ret;
8806         }
8807
8808         return 0;
8809 }
8810
8811 static struct drm_framebuffer *
8812 intel_user_framebuffer_create(struct drm_device *dev,
8813                               struct drm_file *filp,
8814                               struct drm_mode_fb_cmd2 *mode_cmd)
8815 {
8816         struct drm_i915_gem_object *obj;
8817
8818         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8819                                                 mode_cmd->handles[0]));
8820         if (&obj->base == NULL)
8821                 return ERR_PTR(-ENOENT);
8822
8823         return intel_framebuffer_create(dev, mode_cmd, obj);
8824 }
8825
8826 static const struct drm_mode_config_funcs intel_mode_funcs = {
8827         .fb_create = intel_user_framebuffer_create,
8828         .output_poll_changed = intel_fb_output_poll_changed,
8829 };
8830
8831 /* Set up chip specific display functions */
8832 static void intel_init_display(struct drm_device *dev)
8833 {
8834         struct drm_i915_private *dev_priv = dev->dev_private;
8835
8836         if (HAS_DDI(dev)) {
8837                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
8838                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8839                 dev_priv->display.crtc_enable = haswell_crtc_enable;
8840                 dev_priv->display.crtc_disable = haswell_crtc_disable;
8841                 dev_priv->display.off = haswell_crtc_off;
8842                 dev_priv->display.update_plane = ironlake_update_plane;
8843         } else if (HAS_PCH_SPLIT(dev)) {
8844                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
8845                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8846                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8847                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8848                 dev_priv->display.off = ironlake_crtc_off;
8849                 dev_priv->display.update_plane = ironlake_update_plane;
8850         } else if (IS_VALLEYVIEW(dev)) {
8851                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
8852                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8853                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
8854                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8855                 dev_priv->display.off = i9xx_crtc_off;
8856                 dev_priv->display.update_plane = i9xx_update_plane;
8857         } else {
8858                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
8859                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8860                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8861                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8862                 dev_priv->display.off = i9xx_crtc_off;
8863                 dev_priv->display.update_plane = i9xx_update_plane;
8864         }
8865
8866         /* Returns the core display clock speed */
8867         if (IS_VALLEYVIEW(dev))
8868                 dev_priv->display.get_display_clock_speed =
8869                         valleyview_get_display_clock_speed;
8870         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8871                 dev_priv->display.get_display_clock_speed =
8872                         i945_get_display_clock_speed;
8873         else if (IS_I915G(dev))
8874                 dev_priv->display.get_display_clock_speed =
8875                         i915_get_display_clock_speed;
8876         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8877                 dev_priv->display.get_display_clock_speed =
8878                         i9xx_misc_get_display_clock_speed;
8879         else if (IS_I915GM(dev))
8880                 dev_priv->display.get_display_clock_speed =
8881                         i915gm_get_display_clock_speed;
8882         else if (IS_I865G(dev))
8883                 dev_priv->display.get_display_clock_speed =
8884                         i865_get_display_clock_speed;
8885         else if (IS_I85X(dev))
8886                 dev_priv->display.get_display_clock_speed =
8887                         i855_get_display_clock_speed;
8888         else /* 852, 830 */
8889                 dev_priv->display.get_display_clock_speed =
8890                         i830_get_display_clock_speed;
8891
8892         if (HAS_PCH_SPLIT(dev)) {
8893                 if (IS_GEN5(dev)) {
8894                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8895                         dev_priv->display.write_eld = ironlake_write_eld;
8896                 } else if (IS_GEN6(dev)) {
8897                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8898                         dev_priv->display.write_eld = ironlake_write_eld;
8899                 } else if (IS_IVYBRIDGE(dev)) {
8900                         /* FIXME: detect B0+ stepping and use auto training */
8901                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8902                         dev_priv->display.write_eld = ironlake_write_eld;
8903                         dev_priv->display.modeset_global_resources =
8904                                 ivb_modeset_global_resources;
8905                 } else if (IS_HASWELL(dev)) {
8906                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8907                         dev_priv->display.write_eld = haswell_write_eld;
8908                         dev_priv->display.modeset_global_resources =
8909                                 haswell_modeset_global_resources;
8910                 }
8911         } else if (IS_G4X(dev)) {
8912                 dev_priv->display.write_eld = g4x_write_eld;
8913         }
8914
8915         /* Default just returns -ENODEV to indicate unsupported */
8916         dev_priv->display.queue_flip = intel_default_queue_flip;
8917
8918         switch (INTEL_INFO(dev)->gen) {
8919         case 2:
8920                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8921                 break;
8922
8923         case 3:
8924                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8925                 break;
8926
8927         case 4:
8928         case 5:
8929                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8930                 break;
8931
8932         case 6:
8933                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8934                 break;
8935         case 7:
8936                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8937                 break;
8938         }
8939 }
8940
8941 /*
8942  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8943  * resume, or other times.  This quirk makes sure that's the case for
8944  * affected systems.
8945  */
8946 static void quirk_pipea_force(struct drm_device *dev)
8947 {
8948         struct drm_i915_private *dev_priv = dev->dev_private;
8949
8950         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8951         DRM_INFO("applying pipe a force quirk\n");
8952 }
8953
8954 /*
8955  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8956  */
8957 static void quirk_ssc_force_disable(struct drm_device *dev)
8958 {
8959         struct drm_i915_private *dev_priv = dev->dev_private;
8960         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8961         DRM_INFO("applying lvds SSC disable quirk\n");
8962 }
8963
8964 /*
8965  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8966  * brightness value
8967  */
8968 static void quirk_invert_brightness(struct drm_device *dev)
8969 {
8970         struct drm_i915_private *dev_priv = dev->dev_private;
8971         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8972         DRM_INFO("applying inverted panel brightness quirk\n");
8973 }
8974
8975 struct intel_quirk {
8976         int device;
8977         int subsystem_vendor;
8978         int subsystem_device;
8979         void (*hook)(struct drm_device *dev);
8980 };
8981
8982 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8983 struct intel_dmi_quirk {
8984         void (*hook)(struct drm_device *dev);
8985         const struct dmi_system_id (*dmi_id_list)[];
8986 };
8987
8988 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8989 {
8990         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8991         return 1;
8992 }
8993
8994 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8995         {
8996                 .dmi_id_list = &(const struct dmi_system_id[]) {
8997                         {
8998                                 .callback = intel_dmi_reverse_brightness,
8999                                 .ident = "NCR Corporation",
9000                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9001                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
9002                                 },
9003                         },
9004                         { }  /* terminating entry */
9005                 },
9006                 .hook = quirk_invert_brightness,
9007         },
9008 };
9009
9010 static struct intel_quirk intel_quirks[] = {
9011         /* HP Mini needs pipe A force quirk (LP: #322104) */
9012         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9013
9014         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9015         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9016
9017         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9018         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9019
9020         /* 830/845 need to leave pipe A & dpll A up */
9021         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9022         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9023
9024         /* Lenovo U160 cannot use SSC on LVDS */
9025         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9026
9027         /* Sony Vaio Y cannot use SSC on LVDS */
9028         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9029
9030         /* Acer Aspire 5734Z must invert backlight brightness */
9031         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9032
9033         /* Acer/eMachines G725 */
9034         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
9035
9036         /* Acer/eMachines e725 */
9037         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
9038
9039         /* Acer/Packard Bell NCL20 */
9040         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
9041
9042         /* Acer Aspire 4736Z */
9043         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
9044 };
9045
9046 static void intel_init_quirks(struct drm_device *dev)
9047 {
9048         struct pci_dev *d = dev->pdev;
9049         int i;
9050
9051         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9052                 struct intel_quirk *q = &intel_quirks[i];
9053
9054                 if (d->device == q->device &&
9055                     (d->subsystem_vendor == q->subsystem_vendor ||
9056                      q->subsystem_vendor == PCI_ANY_ID) &&
9057                     (d->subsystem_device == q->subsystem_device ||
9058                      q->subsystem_device == PCI_ANY_ID))
9059                         q->hook(dev);
9060         }
9061         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9062                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9063                         intel_dmi_quirks[i].hook(dev);
9064         }
9065 }
9066
9067 /* Disable the VGA plane that we never use */
9068 static void i915_disable_vga(struct drm_device *dev)
9069 {
9070         struct drm_i915_private *dev_priv = dev->dev_private;
9071         u8 sr1;
9072         u32 vga_reg = i915_vgacntrl_reg(dev);
9073
9074         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9075         outb(SR01, VGA_SR_INDEX);
9076         sr1 = inb(VGA_SR_DATA);
9077         outb(sr1 | 1<<5, VGA_SR_DATA);
9078         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9079         udelay(300);
9080
9081         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9082         POSTING_READ(vga_reg);
9083 }
9084
9085 void intel_modeset_init_hw(struct drm_device *dev)
9086 {
9087         intel_init_power_well(dev);
9088
9089         intel_prepare_ddi(dev);
9090
9091         intel_init_clock_gating(dev);
9092
9093         mutex_lock(&dev->struct_mutex);
9094         intel_enable_gt_powersave(dev);
9095         mutex_unlock(&dev->struct_mutex);
9096 }
9097
9098 void intel_modeset_init(struct drm_device *dev)
9099 {
9100         struct drm_i915_private *dev_priv = dev->dev_private;
9101         int i, j, ret;
9102
9103         drm_mode_config_init(dev);
9104
9105         dev->mode_config.min_width = 0;
9106         dev->mode_config.min_height = 0;
9107
9108         dev->mode_config.preferred_depth = 24;
9109         dev->mode_config.prefer_shadow = 1;
9110
9111         dev->mode_config.funcs = &intel_mode_funcs;
9112
9113         intel_init_quirks(dev);
9114
9115         intel_init_pm(dev);
9116
9117         if (INTEL_INFO(dev)->num_pipes == 0)
9118                 return;
9119
9120         intel_init_display(dev);
9121
9122         if (IS_GEN2(dev)) {
9123                 dev->mode_config.max_width = 2048;
9124                 dev->mode_config.max_height = 2048;
9125         } else if (IS_GEN3(dev)) {
9126                 dev->mode_config.max_width = 4096;
9127                 dev->mode_config.max_height = 4096;
9128         } else {
9129                 dev->mode_config.max_width = 8192;
9130                 dev->mode_config.max_height = 8192;
9131         }
9132         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
9133
9134         DRM_DEBUG_KMS("%d display pipe%s available.\n",
9135                       INTEL_INFO(dev)->num_pipes,
9136                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
9137
9138         for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
9139                 intel_crtc_init(dev, i);
9140                 for (j = 0; j < dev_priv->num_plane; j++) {
9141                         ret = intel_plane_init(dev, i, j);
9142                         if (ret)
9143                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9144                                               pipe_name(i), sprite_name(i, j), ret);
9145                 }
9146         }
9147
9148         intel_cpu_pll_init(dev);
9149         intel_pch_pll_init(dev);
9150
9151         /* Just disable it once at startup */
9152         i915_disable_vga(dev);
9153         intel_setup_outputs(dev);
9154
9155         /* Just in case the BIOS is doing something questionable. */
9156         intel_disable_fbc(dev);
9157 }
9158
9159 static void
9160 intel_connector_break_all_links(struct intel_connector *connector)
9161 {
9162         connector->base.dpms = DRM_MODE_DPMS_OFF;
9163         connector->base.encoder = NULL;
9164         connector->encoder->connectors_active = false;
9165         connector->encoder->base.crtc = NULL;
9166 }
9167
9168 static void intel_enable_pipe_a(struct drm_device *dev)
9169 {
9170         struct intel_connector *connector;
9171         struct drm_connector *crt = NULL;
9172         struct intel_load_detect_pipe load_detect_temp;
9173
9174         /* We can't just switch on the pipe A, we need to set things up with a
9175          * proper mode and output configuration. As a gross hack, enable pipe A
9176          * by enabling the load detect pipe once. */
9177         list_for_each_entry(connector,
9178                             &dev->mode_config.connector_list,
9179                             base.head) {
9180                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9181                         crt = &connector->base;
9182                         break;
9183                 }
9184         }
9185
9186         if (!crt)
9187                 return;
9188
9189         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9190                 intel_release_load_detect_pipe(crt, &load_detect_temp);
9191
9192
9193 }
9194
9195 static bool
9196 intel_check_plane_mapping(struct intel_crtc *crtc)
9197 {
9198         struct drm_device *dev = crtc->base.dev;
9199         struct drm_i915_private *dev_priv = dev->dev_private;
9200         u32 reg, val;
9201
9202         if (INTEL_INFO(dev)->num_pipes == 1)
9203                 return true;
9204
9205         reg = DSPCNTR(!crtc->plane);
9206         val = I915_READ(reg);
9207
9208         if ((val & DISPLAY_PLANE_ENABLE) &&
9209             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9210                 return false;
9211
9212         return true;
9213 }
9214
9215 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9216 {
9217         struct drm_device *dev = crtc->base.dev;
9218         struct drm_i915_private *dev_priv = dev->dev_private;
9219         u32 reg;
9220
9221         /* Clear any frame start delays used for debugging left by the BIOS */
9222         reg = PIPECONF(crtc->config.cpu_transcoder);
9223         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9224
9225         /* We need to sanitize the plane -> pipe mapping first because this will
9226          * disable the crtc (and hence change the state) if it is wrong. Note
9227          * that gen4+ has a fixed plane -> pipe mapping.  */
9228         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9229                 struct intel_connector *connector;
9230                 bool plane;
9231
9232                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9233                               crtc->base.base.id);
9234
9235                 /* Pipe has the wrong plane attached and the plane is active.
9236                  * Temporarily change the plane mapping and disable everything
9237                  * ...  */
9238                 plane = crtc->plane;
9239                 crtc->plane = !plane;
9240                 dev_priv->display.crtc_disable(&crtc->base);
9241                 crtc->plane = plane;
9242
9243                 /* ... and break all links. */
9244                 list_for_each_entry(connector, &dev->mode_config.connector_list,
9245                                     base.head) {
9246                         if (connector->encoder->base.crtc != &crtc->base)
9247                                 continue;
9248
9249                         intel_connector_break_all_links(connector);
9250                 }
9251
9252                 WARN_ON(crtc->active);
9253                 crtc->base.enabled = false;
9254         }
9255
9256         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9257             crtc->pipe == PIPE_A && !crtc->active) {
9258                 /* BIOS forgot to enable pipe A, this mostly happens after
9259                  * resume. Force-enable the pipe to fix this, the update_dpms
9260                  * call below we restore the pipe to the right state, but leave
9261                  * the required bits on. */
9262                 intel_enable_pipe_a(dev);
9263         }
9264
9265         /* Adjust the state of the output pipe according to whether we
9266          * have active connectors/encoders. */
9267         intel_crtc_update_dpms(&crtc->base);
9268
9269         if (crtc->active != crtc->base.enabled) {
9270                 struct intel_encoder *encoder;
9271
9272                 /* This can happen either due to bugs in the get_hw_state
9273                  * functions or because the pipe is force-enabled due to the
9274                  * pipe A quirk. */
9275                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9276                               crtc->base.base.id,
9277                               crtc->base.enabled ? "enabled" : "disabled",
9278                               crtc->active ? "enabled" : "disabled");
9279
9280                 crtc->base.enabled = crtc->active;
9281
9282                 /* Because we only establish the connector -> encoder ->
9283                  * crtc links if something is active, this means the
9284                  * crtc is now deactivated. Break the links. connector
9285                  * -> encoder links are only establish when things are
9286                  *  actually up, hence no need to break them. */
9287                 WARN_ON(crtc->active);
9288
9289                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9290                         WARN_ON(encoder->connectors_active);
9291                         encoder->base.crtc = NULL;
9292                 }
9293         }
9294 }
9295
9296 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9297 {
9298         struct intel_connector *connector;
9299         struct drm_device *dev = encoder->base.dev;
9300
9301         /* We need to check both for a crtc link (meaning that the
9302          * encoder is active and trying to read from a pipe) and the
9303          * pipe itself being active. */
9304         bool has_active_crtc = encoder->base.crtc &&
9305                 to_intel_crtc(encoder->base.crtc)->active;
9306
9307         if (encoder->connectors_active && !has_active_crtc) {
9308                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9309                               encoder->base.base.id,
9310                               drm_get_encoder_name(&encoder->base));
9311
9312                 /* Connector is active, but has no active pipe. This is
9313                  * fallout from our resume register restoring. Disable
9314                  * the encoder manually again. */
9315                 if (encoder->base.crtc) {
9316                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9317                                       encoder->base.base.id,
9318                                       drm_get_encoder_name(&encoder->base));
9319                         encoder->disable(encoder);
9320                 }
9321
9322                 /* Inconsistent output/port/pipe state happens presumably due to
9323                  * a bug in one of the get_hw_state functions. Or someplace else
9324                  * in our code, like the register restore mess on resume. Clamp
9325                  * things to off as a safer default. */
9326                 list_for_each_entry(connector,
9327                                     &dev->mode_config.connector_list,
9328                                     base.head) {
9329                         if (connector->encoder != encoder)
9330                                 continue;
9331
9332                         intel_connector_break_all_links(connector);
9333                 }
9334         }
9335         /* Enabled encoders without active connectors will be fixed in
9336          * the crtc fixup. */
9337 }
9338
9339 void i915_redisable_vga(struct drm_device *dev)
9340 {
9341         struct drm_i915_private *dev_priv = dev->dev_private;
9342         u32 vga_reg = i915_vgacntrl_reg(dev);
9343
9344         if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9345                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9346                 i915_disable_vga(dev);
9347         }
9348 }
9349
9350 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9351  * and i915 state tracking structures. */
9352 void intel_modeset_setup_hw_state(struct drm_device *dev,
9353                                   bool force_restore)
9354 {
9355         struct drm_i915_private *dev_priv = dev->dev_private;
9356         enum pipe pipe;
9357         u32 tmp;
9358         struct drm_plane *plane;
9359         struct intel_crtc *crtc;
9360         struct intel_encoder *encoder;
9361         struct intel_connector *connector;
9362
9363         if (HAS_DDI(dev)) {
9364                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9365
9366                 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9367                         switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9368                         case TRANS_DDI_EDP_INPUT_A_ON:
9369                         case TRANS_DDI_EDP_INPUT_A_ONOFF:
9370                                 pipe = PIPE_A;
9371                                 break;
9372                         case TRANS_DDI_EDP_INPUT_B_ONOFF:
9373                                 pipe = PIPE_B;
9374                                 break;
9375                         case TRANS_DDI_EDP_INPUT_C_ONOFF:
9376                                 pipe = PIPE_C;
9377                                 break;
9378                         default:
9379                                 /* A bogus value has been programmed, disable
9380                                  * the transcoder */
9381                                 WARN(1, "Bogus eDP source %08x\n", tmp);
9382                                 intel_ddi_disable_transcoder_func(dev_priv,
9383                                                 TRANSCODER_EDP);
9384                                 goto setup_pipes;
9385                         }
9386
9387                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9388                         crtc->config.cpu_transcoder = TRANSCODER_EDP;
9389
9390                         DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9391                                       pipe_name(pipe));
9392                 }
9393         }
9394
9395 setup_pipes:
9396         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9397                             base.head) {
9398                 enum transcoder tmp = crtc->config.cpu_transcoder;
9399                 memset(&crtc->config, 0, sizeof(crtc->config));
9400                 crtc->config.cpu_transcoder = tmp;
9401
9402                 crtc->active = dev_priv->display.get_pipe_config(crtc,
9403                                                                  &crtc->config);
9404
9405                 crtc->base.enabled = crtc->active;
9406
9407                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9408                               crtc->base.base.id,
9409                               crtc->active ? "enabled" : "disabled");
9410         }
9411
9412         if (HAS_DDI(dev))
9413                 intel_ddi_setup_hw_pll_state(dev);
9414
9415         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9416                             base.head) {
9417                 pipe = 0;
9418
9419                 if (encoder->get_hw_state(encoder, &pipe)) {
9420                         encoder->base.crtc =
9421                                 dev_priv->pipe_to_crtc_mapping[pipe];
9422                 } else {
9423                         encoder->base.crtc = NULL;
9424                 }
9425
9426                 encoder->connectors_active = false;
9427                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9428                               encoder->base.base.id,
9429                               drm_get_encoder_name(&encoder->base),
9430                               encoder->base.crtc ? "enabled" : "disabled",
9431                               pipe);
9432         }
9433
9434         list_for_each_entry(connector, &dev->mode_config.connector_list,
9435                             base.head) {
9436                 if (connector->get_hw_state(connector)) {
9437                         connector->base.dpms = DRM_MODE_DPMS_ON;
9438                         connector->encoder->connectors_active = true;
9439                         connector->base.encoder = &connector->encoder->base;
9440                 } else {
9441                         connector->base.dpms = DRM_MODE_DPMS_OFF;
9442                         connector->base.encoder = NULL;
9443                 }
9444                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9445                               connector->base.base.id,
9446                               drm_get_connector_name(&connector->base),
9447                               connector->base.encoder ? "enabled" : "disabled");
9448         }
9449
9450         /* HW state is read out, now we need to sanitize this mess. */
9451         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9452                             base.head) {
9453                 intel_sanitize_encoder(encoder);
9454         }
9455
9456         for_each_pipe(pipe) {
9457                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9458                 intel_sanitize_crtc(crtc);
9459         }
9460
9461         if (force_restore) {
9462                 /*
9463                  * We need to use raw interfaces for restoring state to avoid
9464                  * checking (bogus) intermediate states.
9465                  */
9466                 for_each_pipe(pipe) {
9467                         struct drm_crtc *crtc =
9468                                 dev_priv->pipe_to_crtc_mapping[pipe];
9469
9470                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9471                                          crtc->fb);
9472                 }
9473                 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9474                         intel_plane_restore(plane);
9475
9476                 i915_redisable_vga(dev);
9477         } else {
9478                 intel_modeset_update_staged_output_state(dev);
9479         }
9480
9481         intel_modeset_check_state(dev);
9482
9483         drm_mode_config_reset(dev);
9484 }
9485
9486 void intel_modeset_gem_init(struct drm_device *dev)
9487 {
9488         intel_modeset_init_hw(dev);
9489
9490         intel_setup_overlay(dev);
9491
9492         intel_modeset_setup_hw_state(dev, false);
9493 }
9494
9495 void intel_modeset_cleanup(struct drm_device *dev)
9496 {
9497         struct drm_i915_private *dev_priv = dev->dev_private;
9498         struct drm_crtc *crtc;
9499         struct intel_crtc *intel_crtc;
9500
9501         /*
9502          * Interrupts and polling as the first thing to avoid creating havoc.
9503          * Too much stuff here (turning of rps, connectors, ...) would
9504          * experience fancy races otherwise.
9505          */
9506         drm_irq_uninstall(dev);
9507         cancel_work_sync(&dev_priv->hotplug_work);
9508         /*
9509          * Due to the hpd irq storm handling the hotplug work can re-arm the
9510          * poll handlers. Hence disable polling after hpd handling is shut down.
9511          */
9512         drm_kms_helper_poll_fini(dev);
9513
9514         mutex_lock(&dev->struct_mutex);
9515
9516         intel_unregister_dsm_handler();
9517
9518         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9519                 /* Skip inactive CRTCs */
9520                 if (!crtc->fb)
9521                         continue;
9522
9523                 intel_crtc = to_intel_crtc(crtc);
9524                 intel_increase_pllclock(crtc);
9525         }
9526
9527         intel_disable_fbc(dev);
9528
9529         intel_disable_gt_powersave(dev);
9530
9531         ironlake_teardown_rc6(dev);
9532
9533         mutex_unlock(&dev->struct_mutex);
9534
9535         /* flush any delayed tasks or pending work */
9536         flush_scheduled_work();
9537
9538         /* destroy backlight, if any, before the connectors */
9539         intel_panel_destroy_backlight(dev);
9540
9541         drm_mode_config_cleanup(dev);
9542
9543         intel_cleanup_overlay(dev);
9544 }
9545
9546 /*
9547  * Return which encoder is currently attached for connector.
9548  */
9549 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9550 {
9551         return &intel_attached_encoder(connector)->base;
9552 }
9553
9554 void intel_connector_attach_encoder(struct intel_connector *connector,
9555                                     struct intel_encoder *encoder)
9556 {
9557         connector->encoder = encoder;
9558         drm_mode_connector_attach_encoder(&connector->base,
9559                                           &encoder->base);
9560 }
9561
9562 /*
9563  * set vga decode state - true == enable VGA decode
9564  */
9565 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9566 {
9567         struct drm_i915_private *dev_priv = dev->dev_private;
9568         u16 gmch_ctrl;
9569
9570         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9571         if (state)
9572                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9573         else
9574                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9575         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9576         return 0;
9577 }
9578
9579 #ifdef CONFIG_DEBUG_FS
9580 #include <linux/seq_file.h>
9581
9582 struct intel_display_error_state {
9583         struct intel_cursor_error_state {
9584                 u32 control;
9585                 u32 position;
9586                 u32 base;
9587                 u32 size;
9588         } cursor[I915_MAX_PIPES];
9589
9590         struct intel_pipe_error_state {
9591                 u32 conf;
9592                 u32 source;
9593
9594                 u32 htotal;
9595                 u32 hblank;
9596                 u32 hsync;
9597                 u32 vtotal;
9598                 u32 vblank;
9599                 u32 vsync;
9600         } pipe[I915_MAX_PIPES];
9601
9602         struct intel_plane_error_state {
9603                 u32 control;
9604                 u32 stride;
9605                 u32 size;
9606                 u32 pos;
9607                 u32 addr;
9608                 u32 surface;
9609                 u32 tile_offset;
9610         } plane[I915_MAX_PIPES];
9611 };
9612
9613 struct intel_display_error_state *
9614 intel_display_capture_error_state(struct drm_device *dev)
9615 {
9616         drm_i915_private_t *dev_priv = dev->dev_private;
9617         struct intel_display_error_state *error;
9618         enum transcoder cpu_transcoder;
9619         int i;
9620
9621         error = kmalloc(sizeof(*error), GFP_ATOMIC);
9622         if (error == NULL)
9623                 return NULL;
9624
9625         for_each_pipe(i) {
9626                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9627
9628                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9629                         error->cursor[i].control = I915_READ(CURCNTR(i));
9630                         error->cursor[i].position = I915_READ(CURPOS(i));
9631                         error->cursor[i].base = I915_READ(CURBASE(i));
9632                 } else {
9633                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9634                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9635                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9636                 }
9637
9638                 error->plane[i].control = I915_READ(DSPCNTR(i));
9639                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9640                 if (INTEL_INFO(dev)->gen <= 3) {
9641                         error->plane[i].size = I915_READ(DSPSIZE(i));
9642                         error->plane[i].pos = I915_READ(DSPPOS(i));
9643                 }
9644                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9645                         error->plane[i].addr = I915_READ(DSPADDR(i));
9646                 if (INTEL_INFO(dev)->gen >= 4) {
9647                         error->plane[i].surface = I915_READ(DSPSURF(i));
9648                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9649                 }
9650
9651                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9652                 error->pipe[i].source = I915_READ(PIPESRC(i));
9653                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9654                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9655                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9656                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9657                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9658                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9659         }
9660
9661         return error;
9662 }
9663
9664 void
9665 intel_display_print_error_state(struct seq_file *m,
9666                                 struct drm_device *dev,
9667                                 struct intel_display_error_state *error)
9668 {
9669         int i;
9670
9671         seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
9672         for_each_pipe(i) {
9673                 seq_printf(m, "Pipe [%d]:\n", i);
9674                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9675                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9676                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9677                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9678                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9679                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9680                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9681                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9682
9683                 seq_printf(m, "Plane [%d]:\n", i);
9684                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9685                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9686                 if (INTEL_INFO(dev)->gen <= 3) {
9687                         seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9688                         seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
9689                 }
9690                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9691                         seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9692                 if (INTEL_INFO(dev)->gen >= 4) {
9693                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9694                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9695                 }
9696
9697                 seq_printf(m, "Cursor [%d]:\n", i);
9698                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9699                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
9700                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9701         }
9702 }
9703 #endif