drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 #define DIV_ROUND_CLOSEST_ULL(ll, d)    \
  45         ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
  46
  47 static void intel_increase_pllclock(struct drm_crtc *crtc);
  48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  49
  50 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  51                                 struct intel_crtc_config *pipe_config);
  52 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  53                                    struct intel_crtc_config *pipe_config);
  54
  55 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  56                           int x, int y, struct drm_framebuffer *old_fb);
  57 static int intel_framebuffer_init(struct drm_device *dev,
  58                                   struct intel_framebuffer *ifb,
  59                                   struct drm_mode_fb_cmd2 *mode_cmd,
  60                                   struct drm_i915_gem_object *obj);
  61
  62 typedef struct {
  63         int     min, max;
  64 } intel_range_t;
  65
  66 typedef struct {
  67         int     dot_limit;
  68         int     p2_slow, p2_fast;
  69 } intel_p2_t;
  70
  71 typedef struct intel_limit intel_limit_t;
  72 struct intel_limit {
  73         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  74         intel_p2_t          p2;
  75 };
  76
  77 int
  78 intel_pch_rawclk(struct drm_device *dev)
  79 {
  80         struct drm_i915_private *dev_priv = dev->dev_private;
  81
  82         WARN_ON(!HAS_PCH_SPLIT(dev));
  83
  84         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  85 }
  86
  87 static inline u32 /* units of 100MHz */
  88 intel_fdi_link_freq(struct drm_device *dev)
  89 {
  90         if (IS_GEN5(dev)) {
  91                 struct drm_i915_private *dev_priv = dev->dev_private;
  92                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  93         } else
  94                 return 27;
  95 }
  96
  97 static const intel_limit_t intel_limits_i8xx_dac = {
  98         .dot = { .min = 25000, .max = 350000 },
  99         .vco = { .min = 908000, .max = 1512000 },
 100         .n = { .min = 2, .max = 16 },
 101         .m = { .min = 96, .max = 140 },
 102         .m1 = { .min = 18, .max = 26 },
 103         .m2 = { .min = 6, .max = 16 },
 104         .p = { .min = 4, .max = 128 },
 105         .p1 = { .min = 2, .max = 33 },
 106         .p2 = { .dot_limit = 165000,
 107                 .p2_slow = 4, .p2_fast = 2 },
 108 };
 109
 110 static const intel_limit_t intel_limits_i8xx_dvo = {
 111         .dot = { .min = 25000, .max = 350000 },
 112         .vco = { .min = 908000, .max = 1512000 },
 113         .n = { .min = 2, .max = 16 },
 114         .m = { .min = 96, .max = 140 },
 115         .m1 = { .min = 18, .max = 26 },
 116         .m2 = { .min = 6, .max = 16 },
 117         .p = { .min = 4, .max = 128 },
 118         .p1 = { .min = 2, .max = 33 },
 119         .p2 = { .dot_limit = 165000,
 120                 .p2_slow = 4, .p2_fast = 4 },
 121 };
 122
 123 static const intel_limit_t intel_limits_i8xx_lvds = {
 124         .dot = { .min = 25000, .max = 350000 },
 125         .vco = { .min = 908000, .max = 1512000 },
 126         .n = { .min = 2, .max = 16 },
 127         .m = { .min = 96, .max = 140 },
 128         .m1 = { .min = 18, .max = 26 },
 129         .m2 = { .min = 6, .max = 16 },
 130         .p = { .min = 4, .max = 128 },
 131         .p1 = { .min = 1, .max = 6 },
 132         .p2 = { .dot_limit = 165000,
 133                 .p2_slow = 14, .p2_fast = 7 },
 134 };
 135
 136 static const intel_limit_t intel_limits_i9xx_sdvo = {
 137         .dot = { .min = 20000, .max = 400000 },
 138         .vco = { .min = 1400000, .max = 2800000 },
 139         .n = { .min = 1, .max = 6 },
 140         .m = { .min = 70, .max = 120 },
 141         .m1 = { .min = 8, .max = 18 },
 142         .m2 = { .min = 3, .max = 7 },
 143         .p = { .min = 5, .max = 80 },
 144         .p1 = { .min = 1, .max = 8 },
 145         .p2 = { .dot_limit = 200000,
 146                 .p2_slow = 10, .p2_fast = 5 },
 147 };
 148
 149 static const intel_limit_t intel_limits_i9xx_lvds = {
 150         .dot = { .min = 20000, .max = 400000 },
 151         .vco = { .min = 1400000, .max = 2800000 },
 152         .n = { .min = 1, .max = 6 },
 153         .m = { .min = 70, .max = 120 },
 154         .m1 = { .min = 8, .max = 18 },
 155         .m2 = { .min = 3, .max = 7 },
 156         .p = { .min = 7, .max = 98 },
 157         .p1 = { .min = 1, .max = 8 },
 158         .p2 = { .dot_limit = 112000,
 159                 .p2_slow = 14, .p2_fast = 7 },
 160 };
 161
 162
 163 static const intel_limit_t intel_limits_g4x_sdvo = {
 164         .dot = { .min = 25000, .max = 270000 },
 165         .vco = { .min = 1750000, .max = 3500000},
 166         .n = { .min = 1, .max = 4 },
 167         .m = { .min = 104, .max = 138 },
 168         .m1 = { .min = 17, .max = 23 },
 169         .m2 = { .min = 5, .max = 11 },
 170         .p = { .min = 10, .max = 30 },
 171         .p1 = { .min = 1, .max = 3},
 172         .p2 = { .dot_limit = 270000,
 173                 .p2_slow = 10,
 174                 .p2_fast = 10
 175         },
 176 };
 177
 178 static const intel_limit_t intel_limits_g4x_hdmi = {
 179         .dot = { .min = 22000, .max = 400000 },
 180         .vco = { .min = 1750000, .max = 3500000},
 181         .n = { .min = 1, .max = 4 },
 182         .m = { .min = 104, .max = 138 },
 183         .m1 = { .min = 16, .max = 23 },
 184         .m2 = { .min = 5, .max = 11 },
 185         .p = { .min = 5, .max = 80 },
 186         .p1 = { .min = 1, .max = 8},
 187         .p2 = { .dot_limit = 165000,
 188                 .p2_slow = 10, .p2_fast = 5 },
 189 };
 190
 191 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 192         .dot = { .min = 20000, .max = 115000 },
 193         .vco = { .min = 1750000, .max = 3500000 },
 194         .n = { .min = 1, .max = 3 },
 195         .m = { .min = 104, .max = 138 },
 196         .m1 = { .min = 17, .max = 23 },
 197         .m2 = { .min = 5, .max = 11 },
 198         .p = { .min = 28, .max = 112 },
 199         .p1 = { .min = 2, .max = 8 },
 200         .p2 = { .dot_limit = 0,
 201                 .p2_slow = 14, .p2_fast = 14
 202         },
 203 };
 204
 205 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 206         .dot = { .min = 80000, .max = 224000 },
 207         .vco = { .min = 1750000, .max = 3500000 },
 208         .n = { .min = 1, .max = 3 },
 209         .m = { .min = 104, .max = 138 },
 210         .m1 = { .min = 17, .max = 23 },
 211         .m2 = { .min = 5, .max = 11 },
 212         .p = { .min = 14, .max = 42 },
 213         .p1 = { .min = 2, .max = 6 },
 214         .p2 = { .dot_limit = 0,
 215                 .p2_slow = 7, .p2_fast = 7
 216         },
 217 };
 218
 219 static const intel_limit_t intel_limits_pineview_sdvo = {
 220         .dot = { .min = 20000, .max = 400000},
 221         .vco = { .min = 1700000, .max = 3500000 },
 222         /* Pineview's Ncounter is a ring counter */
 223         .n = { .min = 3, .max = 6 },
 224         .m = { .min = 2, .max = 256 },
 225         /* Pineview only has one combined m divider, which we treat as m2. */
 226         .m1 = { .min = 0, .max = 0 },
 227         .m2 = { .min = 0, .max = 254 },
 228         .p = { .min = 5, .max = 80 },
 229         .p1 = { .min = 1, .max = 8 },
 230         .p2 = { .dot_limit = 200000,
 231                 .p2_slow = 10, .p2_fast = 5 },
 232 };
 233
 234 static const intel_limit_t intel_limits_pineview_lvds = {
 235         .dot = { .min = 20000, .max = 400000 },
 236         .vco = { .min = 1700000, .max = 3500000 },
 237         .n = { .min = 3, .max = 6 },
 238         .m = { .min = 2, .max = 256 },
 239         .m1 = { .min = 0, .max = 0 },
 240         .m2 = { .min = 0, .max = 254 },
 241         .p = { .min = 7, .max = 112 },
 242         .p1 = { .min = 1, .max = 8 },
 243         .p2 = { .dot_limit = 112000,
 244                 .p2_slow = 14, .p2_fast = 14 },
 245 };
 246
 247 /* Ironlake / Sandybridge
 248  *
 249  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 250  * the range value for them is (actual_value - 2).
 251  */
 252 static const intel_limit_t intel_limits_ironlake_dac = {
 253         .dot = { .min = 25000, .max = 350000 },
 254         .vco = { .min = 1760000, .max = 3510000 },
 255         .n = { .min = 1, .max = 5 },
 256         .m = { .min = 79, .max = 127 },
 257         .m1 = { .min = 12, .max = 22 },
 258         .m2 = { .min = 5, .max = 9 },
 259         .p = { .min = 5, .max = 80 },
 260         .p1 = { .min = 1, .max = 8 },
 261         .p2 = { .dot_limit = 225000,
 262                 .p2_slow = 10, .p2_fast = 5 },
 263 };
 264
 265 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 266         .dot = { .min = 25000, .max = 350000 },
 267         .vco = { .min = 1760000, .max = 3510000 },
 268         .n = { .min = 1, .max = 3 },
 269         .m = { .min = 79, .max = 118 },
 270         .m1 = { .min = 12, .max = 22 },
 271         .m2 = { .min = 5, .max = 9 },
 272         .p = { .min = 28, .max = 112 },
 273         .p1 = { .min = 2, .max = 8 },
 274         .p2 = { .dot_limit = 225000,
 275                 .p2_slow = 14, .p2_fast = 14 },
 276 };
 277
 278 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 279         .dot = { .min = 25000, .max = 350000 },
 280         .vco = { .min = 1760000, .max = 3510000 },
 281         .n = { .min = 1, .max = 3 },
 282         .m = { .min = 79, .max = 127 },
 283         .m1 = { .min = 12, .max = 22 },
 284         .m2 = { .min = 5, .max = 9 },
 285         .p = { .min = 14, .max = 56 },
 286         .p1 = { .min = 2, .max = 8 },
 287         .p2 = { .dot_limit = 225000,
 288                 .p2_slow = 7, .p2_fast = 7 },
 289 };
 290
 291 /* LVDS 100mhz refclk limits. */
 292 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 293         .dot = { .min = 25000, .max = 350000 },
 294         .vco = { .min = 1760000, .max = 3510000 },
 295         .n = { .min = 1, .max = 2 },
 296         .m = { .min = 79, .max = 126 },
 297         .m1 = { .min = 12, .max = 22 },
 298         .m2 = { .min = 5, .max = 9 },
 299         .p = { .min = 28, .max = 112 },
 300         .p1 = { .min = 2, .max = 8 },
 301         .p2 = { .dot_limit = 225000,
 302                 .p2_slow = 14, .p2_fast = 14 },
 303 };
 304
 305 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 306         .dot = { .min = 25000, .max = 350000 },
 307         .vco = { .min = 1760000, .max = 3510000 },
 308         .n = { .min = 1, .max = 3 },
 309         .m = { .min = 79, .max = 126 },
 310         .m1 = { .min = 12, .max = 22 },
 311         .m2 = { .min = 5, .max = 9 },
 312         .p = { .min = 14, .max = 42 },
 313         .p1 = { .min = 2, .max = 6 },
 314         .p2 = { .dot_limit = 225000,
 315                 .p2_slow = 7, .p2_fast = 7 },
 316 };
 317
 318 static const intel_limit_t intel_limits_vlv = {
 319          /*
 320           * These are the data rate limits (measured in fast clocks)
 321           * since those are the strictest limits we have. The fast
 322           * clock and actual rate limits are more relaxed, so checking
 323           * them would make no difference.
 324           */
 325         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 326         .vco = { .min = 4000000, .max = 6000000 },
 327         .n = { .min = 1, .max = 7 },
 328         .m1 = { .min = 2, .max = 3 },
 329         .m2 = { .min = 11, .max = 156 },
 330         .p1 = { .min = 2, .max = 3 },
 331         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 332 };
 333
 334 static const intel_limit_t intel_limits_chv = {
 335         /*
 336          * These are the data rate limits (measured in fast clocks)
 337          * since those are the strictest limits we have.  The fast
 338          * clock and actual rate limits are more relaxed, so checking
 339          * them would make no difference.
 340          */
 341         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 342         .vco = { .min = 4860000, .max = 6700000 },
 343         .n = { .min = 1, .max = 1 },
 344         .m1 = { .min = 2, .max = 2 },
 345         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 346         .p1 = { .min = 2, .max = 4 },
 347         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 348 };
 349
 350 static void vlv_clock(int refclk, intel_clock_t *clock)
 351 {
 352         clock->m = clock->m1 * clock->m2;
 353         clock->p = clock->p1 * clock->p2;
 354         if (WARN_ON(clock->n == 0 || clock->p == 0))
 355                 return;
 356         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 357         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 358 }
 359
 360 /**
 361  * Returns whether any output on the specified pipe is of the specified type
 362  */
 363 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 364 {
 365         struct drm_device *dev = crtc->dev;
 366         struct intel_encoder *encoder;
 367
 368         for_each_encoder_on_crtc(dev, crtc, encoder)
 369                 if (encoder->type == type)
 370                         return true;
 371
 372         return false;
 373 }
 374
 375 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 376                                                 int refclk)
 377 {
 378         struct drm_device *dev = crtc->dev;
 379         const intel_limit_t *limit;
 380
 381         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 382                 if (intel_is_dual_link_lvds(dev)) {
 383                         if (refclk == 100000)
 384                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 385                         else
 386                                 limit = &intel_limits_ironlake_dual_lvds;
 387                 } else {
 388                         if (refclk == 100000)
 389                                 limit = &intel_limits_ironlake_single_lvds_100m;
 390                         else
 391                                 limit = &intel_limits_ironlake_single_lvds;
 392                 }
 393         } else
 394                 limit = &intel_limits_ironlake_dac;
 395
 396         return limit;
 397 }
 398
 399 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 400 {
 401         struct drm_device *dev = crtc->dev;
 402         const intel_limit_t *limit;
 403
 404         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 405                 if (intel_is_dual_link_lvds(dev))
 406                         limit = &intel_limits_g4x_dual_channel_lvds;
 407                 else
 408                         limit = &intel_limits_g4x_single_channel_lvds;
 409         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 410                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 411                 limit = &intel_limits_g4x_hdmi;
 412         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 413                 limit = &intel_limits_g4x_sdvo;
 414         } else /* The option is for other outputs */
 415                 limit = &intel_limits_i9xx_sdvo;
 416
 417         return limit;
 418 }
 419
 420 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 421 {
 422         struct drm_device *dev = crtc->dev;
 423         const intel_limit_t *limit;
 424
 425         if (HAS_PCH_SPLIT(dev))
 426                 limit = intel_ironlake_limit(crtc, refclk);
 427         else if (IS_G4X(dev)) {
 428                 limit = intel_g4x_limit(crtc);
 429         } else if (IS_PINEVIEW(dev)) {
 430                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 431                         limit = &intel_limits_pineview_lvds;
 432                 else
 433                         limit = &intel_limits_pineview_sdvo;
 434         } else if (IS_CHERRYVIEW(dev)) {
 435                 limit = &intel_limits_chv;
 436         } else if (IS_VALLEYVIEW(dev)) {
 437                 limit = &intel_limits_vlv;
 438         } else if (!IS_GEN2(dev)) {
 439                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 440                         limit = &intel_limits_i9xx_lvds;
 441                 else
 442                         limit = &intel_limits_i9xx_sdvo;
 443         } else {
 444                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 445                         limit = &intel_limits_i8xx_lvds;
 446                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 447                         limit = &intel_limits_i8xx_dvo;
 448                 else
 449                         limit = &intel_limits_i8xx_dac;
 450         }
 451         return limit;
 452 }
 453
 454 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 455 static void pineview_clock(int refclk, intel_clock_t *clock)
 456 {
 457         clock->m = clock->m2 + 2;
 458         clock->p = clock->p1 * clock->p2;
 459         if (WARN_ON(clock->n == 0 || clock->p == 0))
 460                 return;
 461         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 462         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 463 }
 464
 465 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 466 {
 467         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 468 }
 469
 470 static void i9xx_clock(int refclk, intel_clock_t *clock)
 471 {
 472         clock->m = i9xx_dpll_compute_m(clock);
 473         clock->p = clock->p1 * clock->p2;
 474         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 475                 return;
 476         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 477         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 478 }
 479
 480 static void chv_clock(int refclk, intel_clock_t *clock)
 481 {
 482         clock->m = clock->m1 * clock->m2;
 483         clock->p = clock->p1 * clock->p2;
 484         if (WARN_ON(clock->n == 0 || clock->p == 0))
 485                 return;
 486         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 487                         clock->n << 22);
 488         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 489 }
 490
 491 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 492 /**
 493  * Returns whether the given set of divisors are valid for a given refclk with
 494  * the given connectors.
 495  */
 496
 497 static bool intel_PLL_is_valid(struct drm_device *dev,
 498                                const intel_limit_t *limit,
 499                                const intel_clock_t *clock)
 500 {
 501         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 502                 INTELPllInvalid("n out of range\n");
 503         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 504                 INTELPllInvalid("p1 out of range\n");
 505         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 506                 INTELPllInvalid("m2 out of range\n");
 507         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 508                 INTELPllInvalid("m1 out of range\n");
 509
 510         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 511                 if (clock->m1 <= clock->m2)
 512                         INTELPllInvalid("m1 <= m2\n");
 513
 514         if (!IS_VALLEYVIEW(dev)) {
 515                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 516                         INTELPllInvalid("p out of range\n");
 517                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 518                         INTELPllInvalid("m out of range\n");
 519         }
 520
 521         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 522                 INTELPllInvalid("vco out of range\n");
 523         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 524          * connector, etc., rather than just a single range.
 525          */
 526         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 527                 INTELPllInvalid("dot out of range\n");
 528
 529         return true;
 530 }
 531
 532 static bool
 533 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 534                     int target, int refclk, intel_clock_t *match_clock,
 535                     intel_clock_t *best_clock)
 536 {
 537         struct drm_device *dev = crtc->dev;
 538         intel_clock_t clock;
 539         int err = target;
 540
 541         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 542                 /*
 543                  * For LVDS just rely on its current settings for dual-channel.
 544                  * We haven't figured out how to reliably set up different
 545                  * single/dual channel state, if we even can.
 546                  */
 547                 if (intel_is_dual_link_lvds(dev))
 548                         clock.p2 = limit->p2.p2_fast;
 549                 else
 550                         clock.p2 = limit->p2.p2_slow;
 551         } else {
 552                 if (target < limit->p2.dot_limit)
 553                         clock.p2 = limit->p2.p2_slow;
 554                 else
 555                         clock.p2 = limit->p2.p2_fast;
 556         }
 557
 558         memset(best_clock, 0, sizeof(*best_clock));
 559
 560         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 561              clock.m1++) {
 562                 for (clock.m2 = limit->m2.min;
 563                      clock.m2 <= limit->m2.max; clock.m2++) {
 564                         if (clock.m2 >= clock.m1)
 565                                 break;
 566                         for (clock.n = limit->n.min;
 567                              clock.n <= limit->n.max; clock.n++) {
 568                                 for (clock.p1 = limit->p1.min;
 569                                         clock.p1 <= limit->p1.max; clock.p1++) {
 570                                         int this_err;
 571
 572                                         i9xx_clock(refclk, &clock);
 573                                         if (!intel_PLL_is_valid(dev, limit,
 574                                                                 &clock))
 575                                                 continue;
 576                                         if (match_clock &&
 577                                             clock.p != match_clock->p)
 578                                                 continue;
 579
 580                                         this_err = abs(clock.dot - target);
 581                                         if (this_err < err) {
 582                                                 *best_clock = clock;
 583                                                 err = this_err;
 584                                         }
 585                                 }
 586                         }
 587                 }
 588         }
 589
 590         return (err != target);
 591 }
 592
 593 static bool
 594 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 595                    int target, int refclk, intel_clock_t *match_clock,
 596                    intel_clock_t *best_clock)
 597 {
 598         struct drm_device *dev = crtc->dev;
 599         intel_clock_t clock;
 600         int err = target;
 601
 602         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 603                 /*
 604                  * For LVDS just rely on its current settings for dual-channel.
 605                  * We haven't figured out how to reliably set up different
 606                  * single/dual channel state, if we even can.
 607                  */
 608                 if (intel_is_dual_link_lvds(dev))
 609                         clock.p2 = limit->p2.p2_fast;
 610                 else
 611                         clock.p2 = limit->p2.p2_slow;
 612         } else {
 613                 if (target < limit->p2.dot_limit)
 614                         clock.p2 = limit->p2.p2_slow;
 615                 else
 616                         clock.p2 = limit->p2.p2_fast;
 617         }
 618
 619         memset(best_clock, 0, sizeof(*best_clock));
 620
 621         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 622              clock.m1++) {
 623                 for (clock.m2 = limit->m2.min;
 624                      clock.m2 <= limit->m2.max; clock.m2++) {
 625                         for (clock.n = limit->n.min;
 626                              clock.n <= limit->n.max; clock.n++) {
 627                                 for (clock.p1 = limit->p1.min;
 628                                         clock.p1 <= limit->p1.max; clock.p1++) {
 629                                         int this_err;
 630
 631                                         pineview_clock(refclk, &clock);
 632                                         if (!intel_PLL_is_valid(dev, limit,
 633                                                                 &clock))
 634                                                 continue;
 635                                         if (match_clock &&
 636                                             clock.p != match_clock->p)
 637                                                 continue;
 638
 639                                         this_err = abs(clock.dot - target);
 640                                         if (this_err < err) {
 641                                                 *best_clock = clock;
 642                                                 err = this_err;
 643                                         }
 644                                 }
 645                         }
 646                 }
 647         }
 648
 649         return (err != target);
 650 }
 651
 652 static bool
 653 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 654                    int target, int refclk, intel_clock_t *match_clock,
 655                    intel_clock_t *best_clock)
 656 {
 657         struct drm_device *dev = crtc->dev;
 658         intel_clock_t clock;
 659         int max_n;
 660         bool found;
 661         /* approximately equals target * 0.00585 */
 662         int err_most = (target >> 8) + (target >> 9);
 663         found = false;
 664
 665         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 666                 if (intel_is_dual_link_lvds(dev))
 667                         clock.p2 = limit->p2.p2_fast;
 668                 else
 669                         clock.p2 = limit->p2.p2_slow;
 670         } else {
 671                 if (target < limit->p2.dot_limit)
 672                         clock.p2 = limit->p2.p2_slow;
 673                 else
 674                         clock.p2 = limit->p2.p2_fast;
 675         }
 676
 677         memset(best_clock, 0, sizeof(*best_clock));
 678         max_n = limit->n.max;
 679         /* based on hardware requirement, prefer smaller n to precision */
 680         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 681                 /* based on hardware requirement, prefere larger m1,m2 */
 682                 for (clock.m1 = limit->m1.max;
 683                      clock.m1 >= limit->m1.min; clock.m1--) {
 684                         for (clock.m2 = limit->m2.max;
 685                              clock.m2 >= limit->m2.min; clock.m2--) {
 686                                 for (clock.p1 = limit->p1.max;
 687                                      clock.p1 >= limit->p1.min; clock.p1--) {
 688                                         int this_err;
 689
 690                                         i9xx_clock(refclk, &clock);
 691                                         if (!intel_PLL_is_valid(dev, limit,
 692                                                                 &clock))
 693                                                 continue;
 694
 695                                         this_err = abs(clock.dot - target);
 696                                         if (this_err < err_most) {
 697                                                 *best_clock = clock;
 698                                                 err_most = this_err;
 699                                                 max_n = clock.n;
 700                                                 found = true;
 701                                         }
 702                                 }
 703                         }
 704                 }
 705         }
 706         return found;
 707 }
 708
 709 static bool
 710 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 711                    int target, int refclk, intel_clock_t *match_clock,
 712                    intel_clock_t *best_clock)
 713 {
 714         struct drm_device *dev = crtc->dev;
 715         intel_clock_t clock;
 716         unsigned int bestppm = 1000000;
 717         /* min update 19.2 MHz */
 718         int max_n = min(limit->n.max, refclk / 19200);
 719         bool found = false;
 720
 721         target *= 5; /* fast clock */
 722
 723         memset(best_clock, 0, sizeof(*best_clock));
 724
 725         /* based on hardware requirement, prefer smaller n to precision */
 726         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 727                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 728                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 729                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 730                                 clock.p = clock.p1 * clock.p2;
 731                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 732                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 733                                         unsigned int ppm, diff;
 734
 735                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 736                                                                      refclk * clock.m1);
 737
 738                                         vlv_clock(refclk, &clock);
 739
 740                                         if (!intel_PLL_is_valid(dev, limit,
 741                                                                 &clock))
 742                                                 continue;
 743
 744                                         diff = abs(clock.dot - target);
 745                                         ppm = div_u64(1000000ULL * diff, target);
 746
 747                                         if (ppm < 100 && clock.p > best_clock->p) {
 748                                                 bestppm = 0;
 749                                                 *best_clock = clock;
 750                                                 found = true;
 751                                         }
 752
 753                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 754                                                 bestppm = ppm;
 755                                                 *best_clock = clock;
 756                                                 found = true;
 757                                         }
 758                                 }
 759                         }
 760                 }
 761         }
 762
 763         return found;
 764 }
 765
 766 static bool
 767 chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 768                    int target, int refclk, intel_clock_t *match_clock,
 769                    intel_clock_t *best_clock)
 770 {
 771         struct drm_device *dev = crtc->dev;
 772         intel_clock_t clock;
 773         uint64_t m2;
 774         int found = false;
 775
 776         memset(best_clock, 0, sizeof(*best_clock));
 777
 778         /*
 779          * Based on hardware doc, the n always set to 1, and m1 always
 780          * set to 2.  If requires to support 200Mhz refclk, we need to
 781          * revisit this because n may not 1 anymore.
 782          */
 783         clock.n = 1, clock.m1 = 2;
 784         target *= 5;    /* fast clock */
 785
 786         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 787                 for (clock.p2 = limit->p2.p2_fast;
 788                                 clock.p2 >= limit->p2.p2_slow;
 789                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 790
 791                         clock.p = clock.p1 * clock.p2;
 792
 793                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 794                                         clock.n) << 22, refclk * clock.m1);
 795
 796                         if (m2 > INT_MAX/clock.m1)
 797                                 continue;
 798
 799                         clock.m2 = m2;
 800
 801                         chv_clock(refclk, &clock);
 802
 803                         if (!intel_PLL_is_valid(dev, limit, &clock))
 804                                 continue;
 805
 806                         /* based on hardware requirement, prefer bigger p
 807                          */
 808                         if (clock.p > best_clock->p) {
 809                                 *best_clock = clock;
 810                                 found = true;
 811                         }
 812                 }
 813         }
 814
 815         return found;
 816 }
 817
 818 bool intel_crtc_active(struct drm_crtc *crtc)
 819 {
 820         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 821
 822         /* Be paranoid as we can arrive here with only partial
 823          * state retrieved from the hardware during setup.
 824          *
 825          * We can ditch the adjusted_mode.crtc_clock check as soon
 826          * as Haswell has gained clock readout/fastboot support.
 827          *
 828          * We can ditch the crtc->primary->fb check as soon as we can
 829          * properly reconstruct framebuffers.
 830          */
 831         return intel_crtc->active && crtc->primary->fb &&
 832                 intel_crtc->config.adjusted_mode.crtc_clock;
 833 }
 834
 835 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 836                                              enum pipe pipe)
 837 {
 838         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 839         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 840
 841         return intel_crtc->config.cpu_transcoder;
 842 }
 843
 844 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
 845 {
 846         struct drm_i915_private *dev_priv = dev->dev_private;
 847         u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
 848
 849         frame = I915_READ(frame_reg);
 850
 851         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 852                 WARN(1, "vblank wait timed out\n");
 853 }
 854
 855 /**
 856  * intel_wait_for_vblank - wait for vblank on a given pipe
 857  * @dev: drm device
 858  * @pipe: pipe to wait for
 859  *
 860  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 861  * mode setting code.
 862  */
 863 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 864 {
 865         struct drm_i915_private *dev_priv = dev->dev_private;
 866         int pipestat_reg = PIPESTAT(pipe);
 867
 868         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 869                 g4x_wait_for_vblank(dev, pipe);
 870                 return;
 871         }
 872
 873         /* Clear existing vblank status. Note this will clear any other
 874          * sticky status fields as well.
 875          *
 876          * This races with i915_driver_irq_handler() with the result
 877          * that either function could miss a vblank event.  Here it is not
 878          * fatal, as we will either wait upon the next vblank interrupt or
 879          * timeout.  Generally speaking intel_wait_for_vblank() is only
 880          * called during modeset at which time the GPU should be idle and
 881          * should *not* be performing page flips and thus not waiting on
 882          * vblanks...
 883          * Currently, the result of us stealing a vblank from the irq
 884          * handler is that a single frame will be skipped during swapbuffers.
 885          */
 886         I915_WRITE(pipestat_reg,
 887                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 888
 889         /* Wait for vblank interrupt bit to set */
 890         if (wait_for(I915_READ(pipestat_reg) &
 891                      PIPE_VBLANK_INTERRUPT_STATUS,
 892                      50))
 893                 DRM_DEBUG_KMS("vblank wait timed out\n");
 894 }
 895
 896 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 897 {
 898         struct drm_i915_private *dev_priv = dev->dev_private;
 899         u32 reg = PIPEDSL(pipe);
 900         u32 line1, line2;
 901         u32 line_mask;
 902
 903         if (IS_GEN2(dev))
 904                 line_mask = DSL_LINEMASK_GEN2;
 905         else
 906                 line_mask = DSL_LINEMASK_GEN3;
 907
 908         line1 = I915_READ(reg) & line_mask;
 909         mdelay(5);
 910         line2 = I915_READ(reg) & line_mask;
 911
 912         return line1 == line2;
 913 }
 914
 915 /*
 916  * intel_wait_for_pipe_off - wait for pipe to turn off
 917  * @dev: drm device
 918  * @pipe: pipe to wait for
 919  *
 920  * After disabling a pipe, we can't wait for vblank in the usual way,
 921  * spinning on the vblank interrupt status bit, since we won't actually
 922  * see an interrupt when the pipe is disabled.
 923  *
 924  * On Gen4 and above:
 925  *   wait for the pipe register state bit to turn off
 926  *
 927  * Otherwise:
 928  *   wait for the display line value to settle (it usually
 929  *   ends up stopping at the start of the next frame).
 930  *
 931  */
 932 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 933 {
 934         struct drm_i915_private *dev_priv = dev->dev_private;
 935         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 936                                                                       pipe);
 937
 938         if (INTEL_INFO(dev)->gen >= 4) {
 939                 int reg = PIPECONF(cpu_transcoder);
 940
 941                 /* Wait for the Pipe State to go off */
 942                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 943                              100))
 944                         WARN(1, "pipe_off wait timed out\n");
 945         } else {
 946                 /* Wait for the display line to settle */
 947                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 948                         WARN(1, "pipe_off wait timed out\n");
 949         }
 950 }
 951
 952 /*
 953  * ibx_digital_port_connected - is the specified port connected?
 954  * @dev_priv: i915 private structure
 955  * @port: the port to test
 956  *
 957  * Returns true if @port is connected, false otherwise.
 958  */
 959 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 960                                 struct intel_digital_port *port)
 961 {
 962         u32 bit;
 963
 964         if (HAS_PCH_IBX(dev_priv->dev)) {
 965                 switch(port->port) {
 966                 case PORT_B:
 967                         bit = SDE_PORTB_HOTPLUG;
 968                         break;
 969                 case PORT_C:
 970                         bit = SDE_PORTC_HOTPLUG;
 971                         break;
 972                 case PORT_D:
 973                         bit = SDE_PORTD_HOTPLUG;
 974                         break;
 975                 default:
 976                         return true;
 977                 }
 978         } else {
 979                 switch(port->port) {
 980                 case PORT_B:
 981                         bit = SDE_PORTB_HOTPLUG_CPT;
 982                         break;
 983                 case PORT_C:
 984                         bit = SDE_PORTC_HOTPLUG_CPT;
 985                         break;
 986                 case PORT_D:
 987                         bit = SDE_PORTD_HOTPLUG_CPT;
 988                         break;
 989                 default:
 990                         return true;
 991                 }
 992         }
 993
 994         return I915_READ(SDEISR) & bit;
 995 }
 996
 997 static const char *state_string(bool enabled)
 998 {
 999         return enabled ? "on" : "off";
1000 }
1001
1002 /* Only for pre-ILK configs */
1003 void assert_pll(struct drm_i915_private *dev_priv,
1004                 enum pipe pipe, bool state)
1005 {
1006         int reg;
1007         u32 val;
1008         bool cur_state;
1009
1010         reg = DPLL(pipe);
1011         val = I915_READ(reg);
1012         cur_state = !!(val & DPLL_VCO_ENABLE);
1013         WARN(cur_state != state,
1014              "PLL state assertion failure (expected %s, current %s)\n",
1015              state_string(state), state_string(cur_state));
1016 }
1017
1018 /* XXX: the dsi pll is shared between MIPI DSI ports */
1019 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1020 {
1021         u32 val;
1022         bool cur_state;
1023
1024         mutex_lock(&dev_priv->dpio_lock);
1025         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1026         mutex_unlock(&dev_priv->dpio_lock);
1027
1028         cur_state = val & DSI_PLL_VCO_EN;
1029         WARN(cur_state != state,
1030              "DSI PLL state assertion failure (expected %s, current %s)\n",
1031              state_string(state), state_string(cur_state));
1032 }
1033 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1034 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1035
1036 struct intel_shared_dpll *
1037 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1038 {
1039         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1040
1041         if (crtc->config.shared_dpll < 0)
1042                 return NULL;
1043
1044         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1045 }
1046
1047 /* For ILK+ */
1048 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1049                         struct intel_shared_dpll *pll,
1050                         bool state)
1051 {
1052         bool cur_state;
1053         struct intel_dpll_hw_state hw_state;
1054
1055         if (HAS_PCH_LPT(dev_priv->dev)) {
1056                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1057                 return;
1058         }
1059
1060         if (WARN (!pll,
1061                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1062                 return;
1063
1064         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1065         WARN(cur_state != state,
1066              "%s assertion failure (expected %s, current %s)\n",
1067              pll->name, state_string(state), state_string(cur_state));
1068 }
1069
1070 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1071                           enum pipe pipe, bool state)
1072 {
1073         int reg;
1074         u32 val;
1075         bool cur_state;
1076         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1077                                                                       pipe);
1078
1079         if (HAS_DDI(dev_priv->dev)) {
1080                 /* DDI does not have a specific FDI_TX register */
1081                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1082                 val = I915_READ(reg);
1083                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1084         } else {
1085                 reg = FDI_TX_CTL(pipe);
1086                 val = I915_READ(reg);
1087                 cur_state = !!(val & FDI_TX_ENABLE);
1088         }
1089         WARN(cur_state != state,
1090              "FDI TX state assertion failure (expected %s, current %s)\n",
1091              state_string(state), state_string(cur_state));
1092 }
1093 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1094 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1095
1096 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1097                           enum pipe pipe, bool state)
1098 {
1099         int reg;
1100         u32 val;
1101         bool cur_state;
1102
1103         reg = FDI_RX_CTL(pipe);
1104         val = I915_READ(reg);
1105         cur_state = !!(val & FDI_RX_ENABLE);
1106         WARN(cur_state != state,
1107              "FDI RX state assertion failure (expected %s, current %s)\n",
1108              state_string(state), state_string(cur_state));
1109 }
1110 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1111 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1112
1113 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1114                                       enum pipe pipe)
1115 {
1116         int reg;
1117         u32 val;
1118
1119         /* ILK FDI PLL is always enabled */
1120         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1121                 return;
1122
1123         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1124         if (HAS_DDI(dev_priv->dev))
1125                 return;
1126
1127         reg = FDI_TX_CTL(pipe);
1128         val = I915_READ(reg);
1129         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1130 }
1131
1132 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1133                        enum pipe pipe, bool state)
1134 {
1135         int reg;
1136         u32 val;
1137         bool cur_state;
1138
1139         reg = FDI_RX_CTL(pipe);
1140         val = I915_READ(reg);
1141         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1142         WARN(cur_state != state,
1143              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1144              state_string(state), state_string(cur_state));
1145 }
1146
1147 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1148                                   enum pipe pipe)
1149 {
1150         int pp_reg, lvds_reg;
1151         u32 val;
1152         enum pipe panel_pipe = PIPE_A;
1153         bool locked = true;
1154
1155         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1156                 pp_reg = PCH_PP_CONTROL;
1157                 lvds_reg = PCH_LVDS;
1158         } else {
1159                 pp_reg = PP_CONTROL;
1160                 lvds_reg = LVDS;
1161         }
1162
1163         val = I915_READ(pp_reg);
1164         if (!(val & PANEL_POWER_ON) ||
1165             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1166                 locked = false;
1167
1168         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1169                 panel_pipe = PIPE_B;
1170
1171         WARN(panel_pipe == pipe && locked,
1172              "panel assertion failure, pipe %c regs locked\n",
1173              pipe_name(pipe));
1174 }
1175
1176 static void assert_cursor(struct drm_i915_private *dev_priv,
1177                           enum pipe pipe, bool state)
1178 {
1179         struct drm_device *dev = dev_priv->dev;
1180         bool cur_state;
1181
1182         if (IS_845G(dev) || IS_I865G(dev))
1183                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1184         else if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev))
1185                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1186         else
1187                 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1188
1189         WARN(cur_state != state,
1190              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1191              pipe_name(pipe), state_string(state), state_string(cur_state));
1192 }
1193 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1194 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1195
1196 void assert_pipe(struct drm_i915_private *dev_priv,
1197                  enum pipe pipe, bool state)
1198 {
1199         int reg;
1200         u32 val;
1201         bool cur_state;
1202         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1203                                                                       pipe);
1204
1205         /* if we need the pipe A quirk it must be always on */
1206         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1207                 state = true;
1208
1209         if (!intel_display_power_enabled(dev_priv,
1210                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1211                 cur_state = false;
1212         } else {
1213                 reg = PIPECONF(cpu_transcoder);
1214                 val = I915_READ(reg);
1215                 cur_state = !!(val & PIPECONF_ENABLE);
1216         }
1217
1218         WARN(cur_state != state,
1219              "pipe %c assertion failure (expected %s, current %s)\n",
1220              pipe_name(pipe), state_string(state), state_string(cur_state));
1221 }
1222
1223 static void assert_plane(struct drm_i915_private *dev_priv,
1224                          enum plane plane, bool state)
1225 {
1226         int reg;
1227         u32 val;
1228         bool cur_state;
1229
1230         reg = DSPCNTR(plane);
1231         val = I915_READ(reg);
1232         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1233         WARN(cur_state != state,
1234              "plane %c assertion failure (expected %s, current %s)\n",
1235              plane_name(plane), state_string(state), state_string(cur_state));
1236 }
1237
1238 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1239 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1240
1241 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1242                                    enum pipe pipe)
1243 {
1244         struct drm_device *dev = dev_priv->dev;
1245         int reg, i;
1246         u32 val;
1247         int cur_pipe;
1248
1249         /* Primary planes are fixed to pipes on gen4+ */
1250         if (INTEL_INFO(dev)->gen >= 4) {
1251                 reg = DSPCNTR(pipe);
1252                 val = I915_READ(reg);
1253                 WARN(val & DISPLAY_PLANE_ENABLE,
1254                      "plane %c assertion failure, should be disabled but not\n",
1255                      plane_name(pipe));
1256                 return;
1257         }
1258
1259         /* Need to check both planes against the pipe */
1260         for_each_pipe(i) {
1261                 reg = DSPCNTR(i);
1262                 val = I915_READ(reg);
1263                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1264                         DISPPLANE_SEL_PIPE_SHIFT;
1265                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1266                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1267                      plane_name(i), pipe_name(pipe));
1268         }
1269 }
1270
1271 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1272                                     enum pipe pipe)
1273 {
1274         struct drm_device *dev = dev_priv->dev;
1275         int reg, sprite;
1276         u32 val;
1277
1278         if (IS_VALLEYVIEW(dev)) {
1279                 for_each_sprite(pipe, sprite) {
1280                         reg = SPCNTR(pipe, sprite);
1281                         val = I915_READ(reg);
1282                         WARN(val & SP_ENABLE,
1283                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1284                              sprite_name(pipe, sprite), pipe_name(pipe));
1285                 }
1286         } else if (INTEL_INFO(dev)->gen >= 7) {
1287                 reg = SPRCTL(pipe);
1288                 val = I915_READ(reg);
1289                 WARN(val & SPRITE_ENABLE,
1290                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1291                      plane_name(pipe), pipe_name(pipe));
1292         } else if (INTEL_INFO(dev)->gen >= 5) {
1293                 reg = DVSCNTR(pipe);
1294                 val = I915_READ(reg);
1295                 WARN(val & DVS_ENABLE,
1296                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1297                      plane_name(pipe), pipe_name(pipe));
1298         }
1299 }
1300
1301 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1302 {
1303         u32 val;
1304         bool enabled;
1305
1306         WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1307
1308         val = I915_READ(PCH_DREF_CONTROL);
1309         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1310                             DREF_SUPERSPREAD_SOURCE_MASK));
1311         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1312 }
1313
1314 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1315                                            enum pipe pipe)
1316 {
1317         int reg;
1318         u32 val;
1319         bool enabled;
1320
1321         reg = PCH_TRANSCONF(pipe);
1322         val = I915_READ(reg);
1323         enabled = !!(val & TRANS_ENABLE);
1324         WARN(enabled,
1325              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1326              pipe_name(pipe));
1327 }
1328
1329 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1330                             enum pipe pipe, u32 port_sel, u32 val)
1331 {
1332         if ((val & DP_PORT_EN) == 0)
1333                 return false;
1334
1335         if (HAS_PCH_CPT(dev_priv->dev)) {
1336                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1337                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1338                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1339                         return false;
1340         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1341                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1342                         return false;
1343         } else {
1344                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1345                         return false;
1346         }
1347         return true;
1348 }
1349
1350 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1351                               enum pipe pipe, u32 val)
1352 {
1353         if ((val & SDVO_ENABLE) == 0)
1354                 return false;
1355
1356         if (HAS_PCH_CPT(dev_priv->dev)) {
1357                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1358                         return false;
1359         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1360                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1361                         return false;
1362         } else {
1363                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1364                         return false;
1365         }
1366         return true;
1367 }
1368
1369 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1370                               enum pipe pipe, u32 val)
1371 {
1372         if ((val & LVDS_PORT_EN) == 0)
1373                 return false;
1374
1375         if (HAS_PCH_CPT(dev_priv->dev)) {
1376                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1377                         return false;
1378         } else {
1379                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1380                         return false;
1381         }
1382         return true;
1383 }
1384
1385 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1386                               enum pipe pipe, u32 val)
1387 {
1388         if ((val & ADPA_DAC_ENABLE) == 0)
1389                 return false;
1390         if (HAS_PCH_CPT(dev_priv->dev)) {
1391                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1392                         return false;
1393         } else {
1394                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1395                         return false;
1396         }
1397         return true;
1398 }
1399
1400 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1401                                    enum pipe pipe, int reg, u32 port_sel)
1402 {
1403         u32 val = I915_READ(reg);
1404         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1405              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1406              reg, pipe_name(pipe));
1407
1408         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1409              && (val & DP_PIPEB_SELECT),
1410              "IBX PCH dp port still using transcoder B\n");
1411 }
1412
1413 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1414                                      enum pipe pipe, int reg)
1415 {
1416         u32 val = I915_READ(reg);
1417         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1418              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1419              reg, pipe_name(pipe));
1420
1421         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1422              && (val & SDVO_PIPE_B_SELECT),
1423              "IBX PCH hdmi port still using transcoder B\n");
1424 }
1425
1426 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1427                                       enum pipe pipe)
1428 {
1429         int reg;
1430         u32 val;
1431
1432         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1433         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1434         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1435
1436         reg = PCH_ADPA;
1437         val = I915_READ(reg);
1438         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1439              "PCH VGA enabled on transcoder %c, should be disabled\n",
1440              pipe_name(pipe));
1441
1442         reg = PCH_LVDS;
1443         val = I915_READ(reg);
1444         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1445              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1446              pipe_name(pipe));
1447
1448         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1449         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1450         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1451 }
1452
1453 static void intel_init_dpio(struct drm_device *dev)
1454 {
1455         struct drm_i915_private *dev_priv = dev->dev_private;
1456
1457         if (!IS_VALLEYVIEW(dev))
1458                 return;
1459
1460         /*
1461          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1462          * CHV x1 PHY (DP/HDMI D)
1463          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1464          */
1465         if (IS_CHERRYVIEW(dev)) {
1466                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1467                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1468         } else {
1469                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1470         }
1471 }
1472
1473 static void intel_reset_dpio(struct drm_device *dev)
1474 {
1475         struct drm_i915_private *dev_priv = dev->dev_private;
1476
1477         if (!IS_VALLEYVIEW(dev))
1478                 return;
1479
1480         /*
1481          * Enable the CRI clock source so we can get at the display and the
1482          * reference clock for VGA hotplug / manual detection.
1483          */
1484         I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
1485                    DPLL_REFA_CLK_ENABLE_VLV |
1486                    DPLL_INTEGRATED_CRI_CLK_VLV);
1487
1488         if (IS_CHERRYVIEW(dev)) {
1489                 enum dpio_phy phy;
1490                 u32 val;
1491
1492                 for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) {
1493                         /* Poll for phypwrgood signal */
1494                         if (wait_for(I915_READ(DISPLAY_PHY_STATUS) &
1495                                                 PHY_POWERGOOD(phy), 1))
1496                                 DRM_ERROR("Display PHY %d is not power up\n", phy);
1497
1498                         /*
1499                          * Deassert common lane reset for PHY.
1500                          *
1501                          * This should only be done on init and resume from S3
1502                          * with both PLLs disabled, or we risk losing DPIO and
1503                          * PLL synchronization.
1504                          */
1505                         val = I915_READ(DISPLAY_PHY_CONTROL);
1506                         I915_WRITE(DISPLAY_PHY_CONTROL,
1507                                 PHY_COM_LANE_RESET_DEASSERT(phy, val));
1508                 }
1509
1510         } else {
1511                 /*
1512                  * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1513                  *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1514                  *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1515                  *   b. The other bits such as sfr settings / modesel may all
1516                  *      be set to 0.
1517                  *
1518                  * This should only be done on init and resume from S3 with
1519                  * both PLLs disabled, or we risk losing DPIO and PLL
1520                  * synchronization.
1521                  */
1522                 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1523         }
1524 }
1525
1526 static void vlv_enable_pll(struct intel_crtc *crtc)
1527 {
1528         struct drm_device *dev = crtc->base.dev;
1529         struct drm_i915_private *dev_priv = dev->dev_private;
1530         int reg = DPLL(crtc->pipe);
1531         u32 dpll = crtc->config.dpll_hw_state.dpll;
1532
1533         assert_pipe_disabled(dev_priv, crtc->pipe);
1534
1535         /* No really, not for ILK+ */
1536         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1537
1538         /* PLL is protected by panel, make sure we can write it */
1539         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1540                 assert_panel_unlocked(dev_priv, crtc->pipe);
1541
1542         I915_WRITE(reg, dpll);
1543         POSTING_READ(reg);
1544         udelay(150);
1545
1546         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1547                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1548
1549         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1550         POSTING_READ(DPLL_MD(crtc->pipe));
1551
1552         /* We do this three times for luck */
1553         I915_WRITE(reg, dpll);
1554         POSTING_READ(reg);
1555         udelay(150); /* wait for warmup */
1556         I915_WRITE(reg, dpll);
1557         POSTING_READ(reg);
1558         udelay(150); /* wait for warmup */
1559         I915_WRITE(reg, dpll);
1560         POSTING_READ(reg);
1561         udelay(150); /* wait for warmup */
1562 }
1563
1564 static void chv_enable_pll(struct intel_crtc *crtc)
1565 {
1566         struct drm_device *dev = crtc->base.dev;
1567         struct drm_i915_private *dev_priv = dev->dev_private;
1568         int pipe = crtc->pipe;
1569         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1570         int dpll = DPLL(crtc->pipe);
1571         u32 tmp;
1572
1573         assert_pipe_disabled(dev_priv, crtc->pipe);
1574
1575         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1576
1577         mutex_lock(&dev_priv->dpio_lock);
1578
1579         /* Enable back the 10bit clock to display controller */
1580         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1581         tmp |= DPIO_DCLKP_EN;
1582         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1583
1584         /*
1585          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1586          */
1587         udelay(1);
1588
1589         /* Enable PLL */
1590         tmp = I915_READ(dpll);
1591         tmp |= DPLL_VCO_ENABLE;
1592         I915_WRITE(dpll, tmp);
1593
1594         /* Check PLL is locked */
1595         if (wait_for(((I915_READ(dpll) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1596                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1597
1598         /* Deassert soft data lane reset*/
1599         tmp = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(port));
1600         tmp |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1601         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), tmp);
1602
1603
1604         mutex_unlock(&dev_priv->dpio_lock);
1605 }
1606
1607 static void i9xx_enable_pll(struct intel_crtc *crtc)
1608 {
1609         struct drm_device *dev = crtc->base.dev;
1610         struct drm_i915_private *dev_priv = dev->dev_private;
1611         int reg = DPLL(crtc->pipe);
1612         u32 dpll = crtc->config.dpll_hw_state.dpll;
1613
1614         assert_pipe_disabled(dev_priv, crtc->pipe);
1615
1616         /* No really, not for ILK+ */
1617         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1618
1619         /* PLL is protected by panel, make sure we can write it */
1620         if (IS_MOBILE(dev) && !IS_I830(dev))
1621                 assert_panel_unlocked(dev_priv, crtc->pipe);
1622
1623         I915_WRITE(reg, dpll);
1624
1625         /* Wait for the clocks to stabilize. */
1626         POSTING_READ(reg);
1627         udelay(150);
1628
1629         if (INTEL_INFO(dev)->gen >= 4) {
1630                 I915_WRITE(DPLL_MD(crtc->pipe),
1631                            crtc->config.dpll_hw_state.dpll_md);
1632         } else {
1633                 /* The pixel multiplier can only be updated once the
1634                  * DPLL is enabled and the clocks are stable.
1635                  *
1636                  * So write it again.
1637                  */
1638                 I915_WRITE(reg, dpll);
1639         }
1640
1641         /* We do this three times for luck */
1642         I915_WRITE(reg, dpll);
1643         POSTING_READ(reg);
1644         udelay(150); /* wait for warmup */
1645         I915_WRITE(reg, dpll);
1646         POSTING_READ(reg);
1647         udelay(150); /* wait for warmup */
1648         I915_WRITE(reg, dpll);
1649         POSTING_READ(reg);
1650         udelay(150); /* wait for warmup */
1651 }
1652
1653 /**
1654  * i9xx_disable_pll - disable a PLL
1655  * @dev_priv: i915 private structure
1656  * @pipe: pipe PLL to disable
1657  *
1658  * Disable the PLL for @pipe, making sure the pipe is off first.
1659  *
1660  * Note!  This is for pre-ILK only.
1661  */
1662 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1663 {
1664         /* Don't disable pipe A or pipe A PLLs if needed */
1665         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1666                 return;
1667
1668         /* Make sure the pipe isn't still relying on us */
1669         assert_pipe_disabled(dev_priv, pipe);
1670
1671         I915_WRITE(DPLL(pipe), 0);
1672         POSTING_READ(DPLL(pipe));
1673 }
1674
1675 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1676 {
1677         u32 val = 0;
1678
1679         /* Make sure the pipe isn't still relying on us */
1680         assert_pipe_disabled(dev_priv, pipe);
1681
1682         /*
1683          * Leave integrated clock source and reference clock enabled for pipe B.
1684          * The latter is needed for VGA hotplug / manual detection.
1685          */
1686         if (pipe == PIPE_B)
1687                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1688         I915_WRITE(DPLL(pipe), val);
1689         POSTING_READ(DPLL(pipe));
1690
1691 }
1692
1693 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1694 {
1695         int dpll = DPLL(pipe);
1696         u32 val;
1697
1698         /* Set PLL en = 0 */
1699         val = I915_READ(dpll);
1700         val &= ~DPLL_VCO_ENABLE;
1701         I915_WRITE(dpll, val);
1702
1703 }
1704
1705 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1706                 struct intel_digital_port *dport)
1707 {
1708         u32 port_mask;
1709         int dpll_reg;
1710
1711         switch (dport->port) {
1712         case PORT_B:
1713                 port_mask = DPLL_PORTB_READY_MASK;
1714                 dpll_reg = DPLL(0);
1715                 break;
1716         case PORT_C:
1717                 port_mask = DPLL_PORTC_READY_MASK;
1718                 dpll_reg = DPLL(0);
1719                 break;
1720         case PORT_D:
1721                 port_mask = DPLL_PORTD_READY_MASK;
1722                 dpll_reg = DPIO_PHY_STATUS;
1723                 break;
1724         default:
1725                 BUG();
1726         }
1727
1728         if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1729                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1730                      port_name(dport->port), I915_READ(dpll_reg));
1731 }
1732
1733 /**
1734  * ironlake_enable_shared_dpll - enable PCH PLL
1735  * @dev_priv: i915 private structure
1736  * @pipe: pipe PLL to enable
1737  *
1738  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1739  * drives the transcoder clock.
1740  */
1741 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1742 {
1743         struct drm_device *dev = crtc->base.dev;
1744         struct drm_i915_private *dev_priv = dev->dev_private;
1745         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1746
1747         /* PCH PLLs only available on ILK, SNB and IVB */
1748         BUG_ON(INTEL_INFO(dev)->gen < 5);
1749         if (WARN_ON(pll == NULL))
1750                 return;
1751
1752         if (WARN_ON(pll->refcount == 0))
1753                 return;
1754
1755         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1756                       pll->name, pll->active, pll->on,
1757                       crtc->base.base.id);
1758
1759         if (pll->active++) {
1760                 WARN_ON(!pll->on);
1761                 assert_shared_dpll_enabled(dev_priv, pll);
1762                 return;
1763         }
1764         WARN_ON(pll->on);
1765
1766         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1767         pll->enable(dev_priv, pll);
1768         pll->on = true;
1769 }
1770
1771 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1772 {
1773         struct drm_device *dev = crtc->base.dev;
1774         struct drm_i915_private *dev_priv = dev->dev_private;
1775         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1776
1777         /* PCH only available on ILK+ */
1778         BUG_ON(INTEL_INFO(dev)->gen < 5);
1779         if (WARN_ON(pll == NULL))
1780                return;
1781
1782         if (WARN_ON(pll->refcount == 0))
1783                 return;
1784
1785         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1786                       pll->name, pll->active, pll->on,
1787                       crtc->base.base.id);
1788
1789         if (WARN_ON(pll->active == 0)) {
1790                 assert_shared_dpll_disabled(dev_priv, pll);
1791                 return;
1792         }
1793
1794         assert_shared_dpll_enabled(dev_priv, pll);
1795         WARN_ON(!pll->on);
1796         if (--pll->active)
1797                 return;
1798
1799         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1800         pll->disable(dev_priv, pll);
1801         pll->on = false;
1802 }
1803
1804 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1805                                            enum pipe pipe)
1806 {
1807         struct drm_device *dev = dev_priv->dev;
1808         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1809         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1810         uint32_t reg, val, pipeconf_val;
1811
1812         /* PCH only available on ILK+ */
1813         BUG_ON(INTEL_INFO(dev)->gen < 5);
1814
1815         /* Make sure PCH DPLL is enabled */
1816         assert_shared_dpll_enabled(dev_priv,
1817                                    intel_crtc_to_shared_dpll(intel_crtc));
1818
1819         /* FDI must be feeding us bits for PCH ports */
1820         assert_fdi_tx_enabled(dev_priv, pipe);
1821         assert_fdi_rx_enabled(dev_priv, pipe);
1822
1823         if (HAS_PCH_CPT(dev)) {
1824                 /* Workaround: Set the timing override bit before enabling the
1825                  * pch transcoder. */
1826                 reg = TRANS_CHICKEN2(pipe);
1827                 val = I915_READ(reg);
1828                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1829                 I915_WRITE(reg, val);
1830         }
1831
1832         reg = PCH_TRANSCONF(pipe);
1833         val = I915_READ(reg);
1834         pipeconf_val = I915_READ(PIPECONF(pipe));
1835
1836         if (HAS_PCH_IBX(dev_priv->dev)) {
1837                 /*
1838                  * make the BPC in transcoder be consistent with
1839                  * that in pipeconf reg.
1840                  */
1841                 val &= ~PIPECONF_BPC_MASK;
1842                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1843         }
1844
1845         val &= ~TRANS_INTERLACE_MASK;
1846         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1847                 if (HAS_PCH_IBX(dev_priv->dev) &&
1848                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1849                         val |= TRANS_LEGACY_INTERLACED_ILK;
1850                 else
1851                         val |= TRANS_INTERLACED;
1852         else
1853                 val |= TRANS_PROGRESSIVE;
1854
1855         I915_WRITE(reg, val | TRANS_ENABLE);
1856         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1857                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1858 }
1859
1860 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1861                                       enum transcoder cpu_transcoder)
1862 {
1863         u32 val, pipeconf_val;
1864
1865         /* PCH only available on ILK+ */
1866         BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1867
1868         /* FDI must be feeding us bits for PCH ports */
1869         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1870         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1871
1872         /* Workaround: set timing override bit. */
1873         val = I915_READ(_TRANSA_CHICKEN2);
1874         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1875         I915_WRITE(_TRANSA_CHICKEN2, val);
1876
1877         val = TRANS_ENABLE;
1878         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1879
1880         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1881             PIPECONF_INTERLACED_ILK)
1882                 val |= TRANS_INTERLACED;
1883         else
1884                 val |= TRANS_PROGRESSIVE;
1885
1886         I915_WRITE(LPT_TRANSCONF, val);
1887         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1888                 DRM_ERROR("Failed to enable PCH transcoder\n");
1889 }
1890
1891 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1892                                             enum pipe pipe)
1893 {
1894         struct drm_device *dev = dev_priv->dev;
1895         uint32_t reg, val;
1896
1897         /* FDI relies on the transcoder */
1898         assert_fdi_tx_disabled(dev_priv, pipe);
1899         assert_fdi_rx_disabled(dev_priv, pipe);
1900
1901         /* Ports must be off as well */
1902         assert_pch_ports_disabled(dev_priv, pipe);
1903
1904         reg = PCH_TRANSCONF(pipe);
1905         val = I915_READ(reg);
1906         val &= ~TRANS_ENABLE;
1907         I915_WRITE(reg, val);
1908         /* wait for PCH transcoder off, transcoder state */
1909         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1910                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1911
1912         if (!HAS_PCH_IBX(dev)) {
1913                 /* Workaround: Clear the timing override chicken bit again. */
1914                 reg = TRANS_CHICKEN2(pipe);
1915                 val = I915_READ(reg);
1916                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1917                 I915_WRITE(reg, val);
1918         }
1919 }
1920
1921 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1922 {
1923         u32 val;
1924
1925         val = I915_READ(LPT_TRANSCONF);
1926         val &= ~TRANS_ENABLE;
1927         I915_WRITE(LPT_TRANSCONF, val);
1928         /* wait for PCH transcoder off, transcoder state */
1929         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1930                 DRM_ERROR("Failed to disable PCH transcoder\n");
1931
1932         /* Workaround: clear timing override bit. */
1933         val = I915_READ(_TRANSA_CHICKEN2);
1934         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1935         I915_WRITE(_TRANSA_CHICKEN2, val);
1936 }
1937
1938 /**
1939  * intel_enable_pipe - enable a pipe, asserting requirements
1940  * @crtc: crtc responsible for the pipe
1941  *
1942  * Enable @crtc's pipe, making sure that various hardware specific requirements
1943  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1944  */
1945 static void intel_enable_pipe(struct intel_crtc *crtc)
1946 {
1947         struct drm_device *dev = crtc->base.dev;
1948         struct drm_i915_private *dev_priv = dev->dev_private;
1949         enum pipe pipe = crtc->pipe;
1950         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1951                                                                       pipe);
1952         enum pipe pch_transcoder;
1953         int reg;
1954         u32 val;
1955
1956         assert_planes_disabled(dev_priv, pipe);
1957         assert_cursor_disabled(dev_priv, pipe);
1958         assert_sprites_disabled(dev_priv, pipe);
1959
1960         if (HAS_PCH_LPT(dev_priv->dev))
1961                 pch_transcoder = TRANSCODER_A;
1962         else
1963                 pch_transcoder = pipe;
1964
1965         /*
1966          * A pipe without a PLL won't actually be able to drive bits from
1967          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1968          * need the check.
1969          */
1970         if (!HAS_PCH_SPLIT(dev_priv->dev))
1971                 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
1972                         assert_dsi_pll_enabled(dev_priv);
1973                 else
1974                         assert_pll_enabled(dev_priv, pipe);
1975         else {
1976                 if (crtc->config.has_pch_encoder) {
1977                         /* if driving the PCH, we need FDI enabled */
1978                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1979                         assert_fdi_tx_pll_enabled(dev_priv,
1980                                                   (enum pipe) cpu_transcoder);
1981                 }
1982                 /* FIXME: assert CPU port conditions for SNB+ */
1983         }
1984
1985         reg = PIPECONF(cpu_transcoder);
1986         val = I915_READ(reg);
1987         if (val & PIPECONF_ENABLE) {
1988                 WARN_ON(!(pipe == PIPE_A &&
1989                           dev_priv->quirks & QUIRK_PIPEA_FORCE));
1990                 return;
1991         }
1992
1993         I915_WRITE(reg, val | PIPECONF_ENABLE);
1994         POSTING_READ(reg);
1995 }
1996
1997 /**
1998  * intel_disable_pipe - disable a pipe, asserting requirements
1999  * @dev_priv: i915 private structure
2000  * @pipe: pipe to disable
2001  *
2002  * Disable @pipe, making sure that various hardware specific requirements
2003  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
2004  *
2005  * @pipe should be %PIPE_A or %PIPE_B.
2006  *
2007  * Will wait until the pipe has shut down before returning.
2008  */
2009 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
2010                                enum pipe pipe)
2011 {
2012         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2013                                                                       pipe);
2014         int reg;
2015         u32 val;
2016
2017         /*
2018          * Make sure planes won't keep trying to pump pixels to us,
2019          * or we might hang the display.
2020          */
2021         assert_planes_disabled(dev_priv, pipe);
2022         assert_cursor_disabled(dev_priv, pipe);
2023         assert_sprites_disabled(dev_priv, pipe);
2024
2025         /* Don't disable pipe A or pipe A PLLs if needed */
2026         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2027                 return;
2028
2029         reg = PIPECONF(cpu_transcoder);
2030         val = I915_READ(reg);
2031         if ((val & PIPECONF_ENABLE) == 0)
2032                 return;
2033
2034         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
2035         intel_wait_for_pipe_off(dev_priv->dev, pipe);
2036 }
2037
2038 /*
2039  * Plane regs are double buffered, going from enabled->disabled needs a
2040  * trigger in order to latch.  The display address reg provides this.
2041  */
2042 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2043                                enum plane plane)
2044 {
2045         struct drm_device *dev = dev_priv->dev;
2046         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2047
2048         I915_WRITE(reg, I915_READ(reg));
2049         POSTING_READ(reg);
2050 }
2051
2052 /**
2053  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2054  * @dev_priv: i915 private structure
2055  * @plane: plane to enable
2056  * @pipe: pipe being fed
2057  *
2058  * Enable @plane on @pipe, making sure that @pipe is running first.
2059  */
2060 static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
2061                                           enum plane plane, enum pipe pipe)
2062 {
2063         struct intel_crtc *intel_crtc =
2064                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2065         int reg;
2066         u32 val;
2067
2068         /* If the pipe isn't enabled, we can't pump pixels and may hang */
2069         assert_pipe_enabled(dev_priv, pipe);
2070
2071         if (intel_crtc->primary_enabled)
2072                 return;
2073
2074         intel_crtc->primary_enabled = true;
2075
2076         reg = DSPCNTR(plane);
2077         val = I915_READ(reg);
2078         WARN_ON(val & DISPLAY_PLANE_ENABLE);
2079
2080         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
2081         intel_flush_primary_plane(dev_priv, plane);
2082         intel_wait_for_vblank(dev_priv->dev, pipe);
2083 }
2084
2085 /**
2086  * intel_disable_primary_hw_plane - disable the primary hardware plane
2087  * @dev_priv: i915 private structure
2088  * @plane: plane to disable
2089  * @pipe: pipe consuming the data
2090  *
2091  * Disable @plane; should be an independent operation.
2092  */
2093 static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
2094                                            enum plane plane, enum pipe pipe)
2095 {
2096         struct intel_crtc *intel_crtc =
2097                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2098         int reg;
2099         u32 val;
2100
2101         if (!intel_crtc->primary_enabled)
2102                 return;
2103
2104         intel_crtc->primary_enabled = false;
2105
2106         reg = DSPCNTR(plane);
2107         val = I915_READ(reg);
2108         WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0);
2109
2110         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
2111         intel_flush_primary_plane(dev_priv, plane);
2112         intel_wait_for_vblank(dev_priv->dev, pipe);
2113 }
2114
2115 static bool need_vtd_wa(struct drm_device *dev)
2116 {
2117 #ifdef CONFIG_INTEL_IOMMU
2118         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2119                 return true;
2120 #endif
2121         return false;
2122 }
2123
2124 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2125 {
2126         int tile_height;
2127
2128         tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2129         return ALIGN(height, tile_height);
2130 }
2131
2132 int
2133 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2134                            struct drm_i915_gem_object *obj,
2135                            struct intel_ring_buffer *pipelined)
2136 {
2137         struct drm_i915_private *dev_priv = dev->dev_private;
2138         u32 alignment;
2139         int ret;
2140
2141         switch (obj->tiling_mode) {
2142         case I915_TILING_NONE:
2143                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2144                         alignment = 128 * 1024;
2145                 else if (INTEL_INFO(dev)->gen >= 4)
2146                         alignment = 4 * 1024;
2147                 else
2148                         alignment = 64 * 1024;
2149                 break;
2150         case I915_TILING_X:
2151                 /* pin() will align the object as required by fence */
2152                 alignment = 0;
2153                 break;
2154         case I915_TILING_Y:
2155                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2156                 return -EINVAL;
2157         default:
2158                 BUG();
2159         }
2160
2161         /* Note that the w/a also requires 64 PTE of padding following the
2162          * bo. We currently fill all unused PTE with the shadow page and so
2163          * we should always have valid PTE following the scanout preventing
2164          * the VT-d warning.
2165          */
2166         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2167                 alignment = 256 * 1024;
2168
2169         dev_priv->mm.interruptible = false;
2170         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2171         if (ret)
2172                 goto err_interruptible;
2173
2174         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2175          * fence, whereas 965+ only requires a fence if using
2176          * framebuffer compression.  For simplicity, we always install
2177          * a fence as the cost is not that onerous.
2178          */
2179         ret = i915_gem_object_get_fence(obj);
2180         if (ret)
2181                 goto err_unpin;
2182
2183         i915_gem_object_pin_fence(obj);
2184
2185         dev_priv->mm.interruptible = true;
2186         return 0;
2187
2188 err_unpin:
2189         i915_gem_object_unpin_from_display_plane(obj);
2190 err_interruptible:
2191         dev_priv->mm.interruptible = true;
2192         return ret;
2193 }
2194
2195 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2196 {
2197         i915_gem_object_unpin_fence(obj);
2198         i915_gem_object_unpin_from_display_plane(obj);
2199 }
2200
2201 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2202  * is assumed to be a power-of-two. */
2203 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2204                                              unsigned int tiling_mode,
2205                                              unsigned int cpp,
2206                                              unsigned int pitch)
2207 {
2208         if (tiling_mode != I915_TILING_NONE) {
2209                 unsigned int tile_rows, tiles;
2210
2211                 tile_rows = *y / 8;
2212                 *y %= 8;
2213
2214                 tiles = *x / (512/cpp);
2215                 *x %= 512/cpp;
2216
2217                 return tile_rows * pitch * 8 + tiles * 4096;
2218         } else {
2219                 unsigned int offset;
2220
2221                 offset = *y * pitch + *x * cpp;
2222                 *y = 0;
2223                 *x = (offset & 4095) / cpp;
2224                 return offset & -4096;
2225         }
2226 }
2227
2228 int intel_format_to_fourcc(int format)
2229 {
2230         switch (format) {
2231         case DISPPLANE_8BPP:
2232                 return DRM_FORMAT_C8;
2233         case DISPPLANE_BGRX555:
2234                 return DRM_FORMAT_XRGB1555;
2235         case DISPPLANE_BGRX565:
2236                 return DRM_FORMAT_RGB565;
2237         default:
2238         case DISPPLANE_BGRX888:
2239                 return DRM_FORMAT_XRGB8888;
2240         case DISPPLANE_RGBX888:
2241                 return DRM_FORMAT_XBGR8888;
2242         case DISPPLANE_BGRX101010:
2243                 return DRM_FORMAT_XRGB2101010;
2244         case DISPPLANE_RGBX101010:
2245                 return DRM_FORMAT_XBGR2101010;
2246         }
2247 }
2248
2249 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2250                                   struct intel_plane_config *plane_config)
2251 {
2252         struct drm_device *dev = crtc->base.dev;
2253         struct drm_i915_gem_object *obj = NULL;
2254         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2255         u32 base = plane_config->base;
2256
2257         if (plane_config->size == 0)
2258                 return false;
2259
2260         obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2261                                                              plane_config->size);
2262         if (!obj)
2263                 return false;
2264
2265         if (plane_config->tiled) {
2266                 obj->tiling_mode = I915_TILING_X;
2267                 obj->stride = crtc->base.primary->fb->pitches[0];
2268         }
2269
2270         mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2271         mode_cmd.width = crtc->base.primary->fb->width;
2272         mode_cmd.height = crtc->base.primary->fb->height;
2273         mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2274
2275         mutex_lock(&dev->struct_mutex);
2276
2277         if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2278                                    &mode_cmd, obj)) {
2279                 DRM_DEBUG_KMS("intel fb init failed\n");
2280                 goto out_unref_obj;
2281         }
2282
2283         mutex_unlock(&dev->struct_mutex);
2284
2285         DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2286         return true;
2287
2288 out_unref_obj:
2289         drm_gem_object_unreference(&obj->base);
2290         mutex_unlock(&dev->struct_mutex);
2291         return false;
2292 }
2293
2294 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2295                                  struct intel_plane_config *plane_config)
2296 {
2297         struct drm_device *dev = intel_crtc->base.dev;
2298         struct drm_crtc *c;
2299         struct intel_crtc *i;
2300         struct intel_framebuffer *fb;
2301
2302         if (!intel_crtc->base.primary->fb)
2303                 return;
2304
2305         if (intel_alloc_plane_obj(intel_crtc, plane_config))
2306                 return;
2307
2308         kfree(intel_crtc->base.primary->fb);
2309         intel_crtc->base.primary->fb = NULL;
2310
2311         /*
2312          * Failed to alloc the obj, check to see if we should share
2313          * an fb with another CRTC instead
2314          */
2315         list_for_each_entry(c, &dev->mode_config.crtc_list, head) {
2316                 i = to_intel_crtc(c);
2317
2318                 if (c == &intel_crtc->base)
2319                         continue;
2320
2321                 if (!i->active || !c->primary->fb)
2322                         continue;
2323
2324                 fb = to_intel_framebuffer(c->primary->fb);
2325                 if (i915_gem_obj_ggtt_offset(fb->obj) == plane_config->base) {
2326                         drm_framebuffer_reference(c->primary->fb);
2327                         intel_crtc->base.primary->fb = c->primary->fb;
2328                         break;
2329                 }
2330         }
2331 }
2332
2333 static int i9xx_update_primary_plane(struct drm_crtc *crtc,
2334                                      struct drm_framebuffer *fb,
2335                                      int x, int y)
2336 {
2337         struct drm_device *dev = crtc->dev;
2338         struct drm_i915_private *dev_priv = dev->dev_private;
2339         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2340         struct intel_framebuffer *intel_fb;
2341         struct drm_i915_gem_object *obj;
2342         int plane = intel_crtc->plane;
2343         unsigned long linear_offset;
2344         u32 dspcntr;
2345         u32 reg;
2346
2347         intel_fb = to_intel_framebuffer(fb);
2348         obj = intel_fb->obj;
2349
2350         reg = DSPCNTR(plane);
2351         dspcntr = I915_READ(reg);
2352         /* Mask out pixel format bits in case we change it */
2353         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2354         switch (fb->pixel_format) {
2355         case DRM_FORMAT_C8:
2356                 dspcntr |= DISPPLANE_8BPP;
2357                 break;
2358         case DRM_FORMAT_XRGB1555:
2359         case DRM_FORMAT_ARGB1555:
2360                 dspcntr |= DISPPLANE_BGRX555;
2361                 break;
2362         case DRM_FORMAT_RGB565:
2363                 dspcntr |= DISPPLANE_BGRX565;
2364                 break;
2365         case DRM_FORMAT_XRGB8888:
2366         case DRM_FORMAT_ARGB8888:
2367                 dspcntr |= DISPPLANE_BGRX888;
2368                 break;
2369         case DRM_FORMAT_XBGR8888:
2370         case DRM_FORMAT_ABGR8888:
2371                 dspcntr |= DISPPLANE_RGBX888;
2372                 break;
2373         case DRM_FORMAT_XRGB2101010:
2374         case DRM_FORMAT_ARGB2101010:
2375                 dspcntr |= DISPPLANE_BGRX101010;
2376                 break;
2377         case DRM_FORMAT_XBGR2101010:
2378         case DRM_FORMAT_ABGR2101010:
2379                 dspcntr |= DISPPLANE_RGBX101010;
2380                 break;
2381         default:
2382                 BUG();
2383         }
2384
2385         if (INTEL_INFO(dev)->gen >= 4) {
2386                 if (obj->tiling_mode != I915_TILING_NONE)
2387                         dspcntr |= DISPPLANE_TILED;
2388                 else
2389                         dspcntr &= ~DISPPLANE_TILED;
2390         }
2391
2392         if (IS_G4X(dev))
2393                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2394
2395         I915_WRITE(reg, dspcntr);
2396
2397         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2398
2399         if (INTEL_INFO(dev)->gen >= 4) {
2400                 intel_crtc->dspaddr_offset =
2401                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2402                                                        fb->bits_per_pixel / 8,
2403                                                        fb->pitches[0]);
2404                 linear_offset -= intel_crtc->dspaddr_offset;
2405         } else {
2406                 intel_crtc->dspaddr_offset = linear_offset;
2407         }
2408
2409         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2410                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2411                       fb->pitches[0]);
2412         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2413         if (INTEL_INFO(dev)->gen >= 4) {
2414                 I915_WRITE(DSPSURF(plane),
2415                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2416                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2417                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2418         } else
2419                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2420         POSTING_READ(reg);
2421
2422         return 0;
2423 }
2424
2425 static int ironlake_update_primary_plane(struct drm_crtc *crtc,
2426                                          struct drm_framebuffer *fb,
2427                                          int x, int y)
2428 {
2429         struct drm_device *dev = crtc->dev;
2430         struct drm_i915_private *dev_priv = dev->dev_private;
2431         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2432         struct intel_framebuffer *intel_fb;
2433         struct drm_i915_gem_object *obj;
2434         int plane = intel_crtc->plane;
2435         unsigned long linear_offset;
2436         u32 dspcntr;
2437         u32 reg;
2438
2439         intel_fb = to_intel_framebuffer(fb);
2440         obj = intel_fb->obj;
2441
2442         reg = DSPCNTR(plane);
2443         dspcntr = I915_READ(reg);
2444         /* Mask out pixel format bits in case we change it */
2445         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2446         switch (fb->pixel_format) {
2447         case DRM_FORMAT_C8:
2448                 dspcntr |= DISPPLANE_8BPP;
2449                 break;
2450         case DRM_FORMAT_RGB565:
2451                 dspcntr |= DISPPLANE_BGRX565;
2452                 break;
2453         case DRM_FORMAT_XRGB8888:
2454         case DRM_FORMAT_ARGB8888:
2455                 dspcntr |= DISPPLANE_BGRX888;
2456                 break;
2457         case DRM_FORMAT_XBGR8888:
2458         case DRM_FORMAT_ABGR8888:
2459                 dspcntr |= DISPPLANE_RGBX888;
2460                 break;
2461         case DRM_FORMAT_XRGB2101010:
2462         case DRM_FORMAT_ARGB2101010:
2463                 dspcntr |= DISPPLANE_BGRX101010;
2464                 break;
2465         case DRM_FORMAT_XBGR2101010:
2466         case DRM_FORMAT_ABGR2101010:
2467                 dspcntr |= DISPPLANE_RGBX101010;
2468                 break;
2469         default:
2470                 BUG();
2471         }
2472
2473         if (obj->tiling_mode != I915_TILING_NONE)
2474                 dspcntr |= DISPPLANE_TILED;
2475         else
2476                 dspcntr &= ~DISPPLANE_TILED;
2477
2478         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2479                 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2480         else
2481                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2482
2483         I915_WRITE(reg, dspcntr);
2484
2485         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2486         intel_crtc->dspaddr_offset =
2487                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2488                                                fb->bits_per_pixel / 8,
2489                                                fb->pitches[0]);
2490         linear_offset -= intel_crtc->dspaddr_offset;
2491
2492         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2493                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2494                       fb->pitches[0]);
2495         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2496         I915_WRITE(DSPSURF(plane),
2497                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2498         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2499                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2500         } else {
2501                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2502                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2503         }
2504         POSTING_READ(reg);
2505
2506         return 0;
2507 }
2508
2509 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2510 static int
2511 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2512                            int x, int y, enum mode_set_atomic state)
2513 {
2514         struct drm_device *dev = crtc->dev;
2515         struct drm_i915_private *dev_priv = dev->dev_private;
2516
2517         if (dev_priv->display.disable_fbc)
2518                 dev_priv->display.disable_fbc(dev);
2519         intel_increase_pllclock(crtc);
2520
2521         return dev_priv->display.update_primary_plane(crtc, fb, x, y);
2522 }
2523
2524 void intel_display_handle_reset(struct drm_device *dev)
2525 {
2526         struct drm_i915_private *dev_priv = dev->dev_private;
2527         struct drm_crtc *crtc;
2528
2529         /*
2530          * Flips in the rings have been nuked by the reset,
2531          * so complete all pending flips so that user space
2532          * will get its events and not get stuck.
2533          *
2534          * Also update the base address of all primary
2535          * planes to the the last fb to make sure we're
2536          * showing the correct fb after a reset.
2537          *
2538          * Need to make two loops over the crtcs so that we
2539          * don't try to grab a crtc mutex before the
2540          * pending_flip_queue really got woken up.
2541          */
2542
2543         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2544                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2545                 enum plane plane = intel_crtc->plane;
2546
2547                 intel_prepare_page_flip(dev, plane);
2548                 intel_finish_page_flip_plane(dev, plane);
2549         }
2550
2551         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2552                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2553
2554                 mutex_lock(&crtc->mutex);
2555                 /*
2556                  * FIXME: Once we have proper support for primary planes (and
2557                  * disabling them without disabling the entire crtc) allow again
2558                  * a NULL crtc->primary->fb.
2559                  */
2560                 if (intel_crtc->active && crtc->primary->fb)
2561                         dev_priv->display.update_primary_plane(crtc,
2562                                                                crtc->primary->fb,
2563                                                                crtc->x,
2564                                                                crtc->y);
2565                 mutex_unlock(&crtc->mutex);
2566         }
2567 }
2568
2569 static int
2570 intel_finish_fb(struct drm_framebuffer *old_fb)
2571 {
2572         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2573         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2574         bool was_interruptible = dev_priv->mm.interruptible;
2575         int ret;
2576
2577         /* Big Hammer, we also need to ensure that any pending
2578          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2579          * current scanout is retired before unpinning the old
2580          * framebuffer.
2581          *
2582          * This should only fail upon a hung GPU, in which case we
2583          * can safely continue.
2584          */
2585         dev_priv->mm.interruptible = false;
2586         ret = i915_gem_object_finish_gpu(obj);
2587         dev_priv->mm.interruptible = was_interruptible;
2588
2589         return ret;
2590 }
2591
2592 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2593 {
2594         struct drm_device *dev = crtc->dev;
2595         struct drm_i915_private *dev_priv = dev->dev_private;
2596         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2597         unsigned long flags;
2598         bool pending;
2599
2600         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2601             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2602                 return false;
2603
2604         spin_lock_irqsave(&dev->event_lock, flags);
2605         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2606         spin_unlock_irqrestore(&dev->event_lock, flags);
2607
2608         return pending;
2609 }
2610
2611 static int
2612 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2613                     struct drm_framebuffer *fb)
2614 {
2615         struct drm_device *dev = crtc->dev;
2616         struct drm_i915_private *dev_priv = dev->dev_private;
2617         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2618         struct drm_framebuffer *old_fb;
2619         int ret;
2620
2621         if (intel_crtc_has_pending_flip(crtc)) {
2622                 DRM_ERROR("pipe is still busy with an old pageflip\n");
2623                 return -EBUSY;
2624         }
2625
2626         /* no fb bound */
2627         if (!fb) {
2628                 DRM_ERROR("No FB bound\n");
2629                 return 0;
2630         }
2631
2632         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2633                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2634                           plane_name(intel_crtc->plane),
2635                           INTEL_INFO(dev)->num_pipes);
2636                 return -EINVAL;
2637         }
2638
2639         mutex_lock(&dev->struct_mutex);
2640         ret = intel_pin_and_fence_fb_obj(dev,
2641                                          to_intel_framebuffer(fb)->obj,
2642                                          NULL);
2643         mutex_unlock(&dev->struct_mutex);
2644         if (ret != 0) {
2645                 DRM_ERROR("pin & fence failed\n");
2646                 return ret;
2647         }
2648
2649         /*
2650          * Update pipe size and adjust fitter if needed: the reason for this is
2651          * that in compute_mode_changes we check the native mode (not the pfit
2652          * mode) to see if we can flip rather than do a full mode set. In the
2653          * fastboot case, we'll flip, but if we don't update the pipesrc and
2654          * pfit state, we'll end up with a big fb scanned out into the wrong
2655          * sized surface.
2656          *
2657          * To fix this properly, we need to hoist the checks up into
2658          * compute_mode_changes (or above), check the actual pfit state and
2659          * whether the platform allows pfit disable with pipe active, and only
2660          * then update the pipesrc and pfit state, even on the flip path.
2661          */
2662         if (i915.fastboot) {
2663                 const struct drm_display_mode *adjusted_mode =
2664                         &intel_crtc->config.adjusted_mode;
2665
2666                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2667                            ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2668                            (adjusted_mode->crtc_vdisplay - 1));
2669                 if (!intel_crtc->config.pch_pfit.enabled &&
2670                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2671                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2672                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2673                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2674                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2675                 }
2676                 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2677                 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2678         }
2679
2680         ret = dev_priv->display.update_primary_plane(crtc, fb, x, y);
2681         if (ret) {
2682                 mutex_lock(&dev->struct_mutex);
2683                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2684                 mutex_unlock(&dev->struct_mutex);
2685                 DRM_ERROR("failed to update base address\n");
2686                 return ret;
2687         }
2688
2689         old_fb = crtc->primary->fb;
2690         crtc->primary->fb = fb;
2691         crtc->x = x;
2692         crtc->y = y;
2693
2694         if (old_fb) {
2695                 if (intel_crtc->active && old_fb != fb)
2696                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2697                 mutex_lock(&dev->struct_mutex);
2698                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2699                 mutex_unlock(&dev->struct_mutex);
2700         }
2701
2702         mutex_lock(&dev->struct_mutex);
2703         intel_update_fbc(dev);
2704         intel_edp_psr_update(dev);
2705         mutex_unlock(&dev->struct_mutex);
2706
2707         return 0;
2708 }
2709
2710 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2711 {
2712         struct drm_device *dev = crtc->dev;
2713         struct drm_i915_private *dev_priv = dev->dev_private;
2714         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2715         int pipe = intel_crtc->pipe;
2716         u32 reg, temp;
2717
2718         /* enable normal train */
2719         reg = FDI_TX_CTL(pipe);
2720         temp = I915_READ(reg);
2721         if (IS_IVYBRIDGE(dev)) {
2722                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2723                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2724         } else {
2725                 temp &= ~FDI_LINK_TRAIN_NONE;
2726                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2727         }
2728         I915_WRITE(reg, temp);
2729
2730         reg = FDI_RX_CTL(pipe);
2731         temp = I915_READ(reg);
2732         if (HAS_PCH_CPT(dev)) {
2733                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2734                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2735         } else {
2736                 temp &= ~FDI_LINK_TRAIN_NONE;
2737                 temp |= FDI_LINK_TRAIN_NONE;
2738         }
2739         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2740
2741         /* wait one idle pattern time */
2742         POSTING_READ(reg);
2743         udelay(1000);
2744
2745         /* IVB wants error correction enabled */
2746         if (IS_IVYBRIDGE(dev))
2747                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2748                            FDI_FE_ERRC_ENABLE);
2749 }
2750
2751 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2752 {
2753         return crtc->base.enabled && crtc->active &&
2754                 crtc->config.has_pch_encoder;
2755 }
2756
2757 static void ivb_modeset_global_resources(struct drm_device *dev)
2758 {
2759         struct drm_i915_private *dev_priv = dev->dev_private;
2760         struct intel_crtc *pipe_B_crtc =
2761                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2762         struct intel_crtc *pipe_C_crtc =
2763                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2764         uint32_t temp;
2765
2766         /*
2767          * When everything is off disable fdi C so that we could enable fdi B
2768          * with all lanes. Note that we don't care about enabled pipes without
2769          * an enabled pch encoder.
2770          */
2771         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2772             !pipe_has_enabled_pch(pipe_C_crtc)) {
2773                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2774                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2775
2776                 temp = I915_READ(SOUTH_CHICKEN1);
2777                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2778                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2779                 I915_WRITE(SOUTH_CHICKEN1, temp);
2780         }
2781 }
2782
2783 /* The FDI link training functions for ILK/Ibexpeak. */
2784 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2785 {
2786         struct drm_device *dev = crtc->dev;
2787         struct drm_i915_private *dev_priv = dev->dev_private;
2788         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2789         int pipe = intel_crtc->pipe;
2790         u32 reg, temp, tries;
2791
2792         /* FDI needs bits from pipe first */
2793         assert_pipe_enabled(dev_priv, pipe);
2794
2795         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2796            for train result */
2797         reg = FDI_RX_IMR(pipe);
2798         temp = I915_READ(reg);
2799         temp &= ~FDI_RX_SYMBOL_LOCK;
2800         temp &= ~FDI_RX_BIT_LOCK;
2801         I915_WRITE(reg, temp);
2802         I915_READ(reg);
2803         udelay(150);
2804
2805         /* enable CPU FDI TX and PCH FDI RX */
2806         reg = FDI_TX_CTL(pipe);
2807         temp = I915_READ(reg);
2808         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2809         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2810         temp &= ~FDI_LINK_TRAIN_NONE;
2811         temp |= FDI_LINK_TRAIN_PATTERN_1;
2812         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2813
2814         reg = FDI_RX_CTL(pipe);
2815         temp = I915_READ(reg);
2816         temp &= ~FDI_LINK_TRAIN_NONE;
2817         temp |= FDI_LINK_TRAIN_PATTERN_1;
2818         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2819
2820         POSTING_READ(reg);
2821         udelay(150);
2822
2823         /* Ironlake workaround, enable clock pointer after FDI enable*/
2824         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2825         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2826                    FDI_RX_PHASE_SYNC_POINTER_EN);
2827
2828         reg = FDI_RX_IIR(pipe);
2829         for (tries = 0; tries < 5; tries++) {
2830                 temp = I915_READ(reg);
2831                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2832
2833                 if ((temp & FDI_RX_BIT_LOCK)) {
2834                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2835                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2836                         break;
2837                 }
2838         }
2839         if (tries == 5)
2840                 DRM_ERROR("FDI train 1 fail!\n");
2841
2842         /* Train 2 */
2843         reg = FDI_TX_CTL(pipe);
2844         temp = I915_READ(reg);
2845         temp &= ~FDI_LINK_TRAIN_NONE;
2846         temp |= FDI_LINK_TRAIN_PATTERN_2;
2847         I915_WRITE(reg, temp);
2848
2849         reg = FDI_RX_CTL(pipe);
2850         temp = I915_READ(reg);
2851         temp &= ~FDI_LINK_TRAIN_NONE;
2852         temp |= FDI_LINK_TRAIN_PATTERN_2;
2853         I915_WRITE(reg, temp);
2854
2855         POSTING_READ(reg);
2856         udelay(150);
2857
2858         reg = FDI_RX_IIR(pipe);
2859         for (tries = 0; tries < 5; tries++) {
2860                 temp = I915_READ(reg);
2861                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2862
2863                 if (temp & FDI_RX_SYMBOL_LOCK) {
2864                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2865                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2866                         break;
2867                 }
2868         }
2869         if (tries == 5)
2870                 DRM_ERROR("FDI train 2 fail!\n");
2871
2872         DRM_DEBUG_KMS("FDI train done\n");
2873
2874 }
2875
2876 static const int snb_b_fdi_train_param[] = {
2877         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2878         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2879         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2880         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2881 };
2882
2883 /* The FDI link training functions for SNB/Cougarpoint. */
2884 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2885 {
2886         struct drm_device *dev = crtc->dev;
2887         struct drm_i915_private *dev_priv = dev->dev_private;
2888         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2889         int pipe = intel_crtc->pipe;
2890         u32 reg, temp, i, retry;
2891
2892         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2893            for train result */
2894         reg = FDI_RX_IMR(pipe);
2895         temp = I915_READ(reg);
2896         temp &= ~FDI_RX_SYMBOL_LOCK;
2897         temp &= ~FDI_RX_BIT_LOCK;
2898         I915_WRITE(reg, temp);
2899
2900         POSTING_READ(reg);
2901         udelay(150);
2902
2903         /* enable CPU FDI TX and PCH FDI RX */
2904         reg = FDI_TX_CTL(pipe);
2905         temp = I915_READ(reg);
2906         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2907         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2908         temp &= ~FDI_LINK_TRAIN_NONE;
2909         temp |= FDI_LINK_TRAIN_PATTERN_1;
2910         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2911         /* SNB-B */
2912         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2913         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2914
2915         I915_WRITE(FDI_RX_MISC(pipe),
2916                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2917
2918         reg = FDI_RX_CTL(pipe);
2919         temp = I915_READ(reg);
2920         if (HAS_PCH_CPT(dev)) {
2921                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2922                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2923         } else {
2924                 temp &= ~FDI_LINK_TRAIN_NONE;
2925                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2926         }
2927         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2928
2929         POSTING_READ(reg);
2930         udelay(150);
2931
2932         for (i = 0; i < 4; i++) {
2933                 reg = FDI_TX_CTL(pipe);
2934                 temp = I915_READ(reg);
2935                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2936                 temp |= snb_b_fdi_train_param[i];
2937                 I915_WRITE(reg, temp);
2938
2939                 POSTING_READ(reg);
2940                 udelay(500);
2941
2942                 for (retry = 0; retry < 5; retry++) {
2943                         reg = FDI_RX_IIR(pipe);
2944                         temp = I915_READ(reg);
2945                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2946                         if (temp & FDI_RX_BIT_LOCK) {
2947                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2948                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2949                                 break;
2950                         }
2951                         udelay(50);
2952                 }
2953                 if (retry < 5)
2954                         break;
2955         }
2956         if (i == 4)
2957                 DRM_ERROR("FDI train 1 fail!\n");
2958
2959         /* Train 2 */
2960         reg = FDI_TX_CTL(pipe);
2961         temp = I915_READ(reg);
2962         temp &= ~FDI_LINK_TRAIN_NONE;
2963         temp |= FDI_LINK_TRAIN_PATTERN_2;
2964         if (IS_GEN6(dev)) {
2965                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2966                 /* SNB-B */
2967                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2968         }
2969         I915_WRITE(reg, temp);
2970
2971         reg = FDI_RX_CTL(pipe);
2972         temp = I915_READ(reg);
2973         if (HAS_PCH_CPT(dev)) {
2974                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2975                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2976         } else {
2977                 temp &= ~FDI_LINK_TRAIN_NONE;
2978                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2979         }
2980         I915_WRITE(reg, temp);
2981
2982         POSTING_READ(reg);
2983         udelay(150);
2984
2985         for (i = 0; i < 4; i++) {
2986                 reg = FDI_TX_CTL(pipe);
2987                 temp = I915_READ(reg);
2988                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2989                 temp |= snb_b_fdi_train_param[i];
2990                 I915_WRITE(reg, temp);
2991
2992                 POSTING_READ(reg);
2993                 udelay(500);
2994
2995                 for (retry = 0; retry < 5; retry++) {
2996                         reg = FDI_RX_IIR(pipe);
2997                         temp = I915_READ(reg);
2998                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2999                         if (temp & FDI_RX_SYMBOL_LOCK) {
3000                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3001                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3002                                 break;
3003                         }
3004                         udelay(50);
3005                 }
3006                 if (retry < 5)
3007                         break;
3008         }
3009         if (i == 4)
3010                 DRM_ERROR("FDI train 2 fail!\n");
3011
3012         DRM_DEBUG_KMS("FDI train done.\n");
3013 }
3014
3015 /* Manual link training for Ivy Bridge A0 parts */
3016 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3017 {
3018         struct drm_device *dev = crtc->dev;
3019         struct drm_i915_private *dev_priv = dev->dev_private;
3020         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3021         int pipe = intel_crtc->pipe;
3022         u32 reg, temp, i, j;
3023
3024         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3025            for train result */
3026         reg = FDI_RX_IMR(pipe);
3027         temp = I915_READ(reg);
3028         temp &= ~FDI_RX_SYMBOL_LOCK;
3029         temp &= ~FDI_RX_BIT_LOCK;
3030         I915_WRITE(reg, temp);
3031
3032         POSTING_READ(reg);
3033         udelay(150);
3034
3035         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3036                       I915_READ(FDI_RX_IIR(pipe)));
3037
3038         /* Try each vswing and preemphasis setting twice before moving on */
3039         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3040                 /* disable first in case we need to retry */
3041                 reg = FDI_TX_CTL(pipe);
3042                 temp = I915_READ(reg);
3043                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3044                 temp &= ~FDI_TX_ENABLE;
3045                 I915_WRITE(reg, temp);
3046
3047                 reg = FDI_RX_CTL(pipe);
3048                 temp = I915_READ(reg);
3049                 temp &= ~FDI_LINK_TRAIN_AUTO;
3050                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3051                 temp &= ~FDI_RX_ENABLE;
3052                 I915_WRITE(reg, temp);
3053
3054                 /* enable CPU FDI TX and PCH FDI RX */
3055                 reg = FDI_TX_CTL(pipe);
3056                 temp = I915_READ(reg);
3057                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3058                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3059                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3060                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3061                 temp |= snb_b_fdi_train_param[j/2];
3062                 temp |= FDI_COMPOSITE_SYNC;
3063                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3064
3065                 I915_WRITE(FDI_RX_MISC(pipe),
3066                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3067
3068                 reg = FDI_RX_CTL(pipe);
3069                 temp = I915_READ(reg);
3070                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3071                 temp |= FDI_COMPOSITE_SYNC;
3072                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3073
3074                 POSTING_READ(reg);
3075                 udelay(1); /* should be 0.5us */
3076
3077                 for (i = 0; i < 4; i++) {
3078                         reg = FDI_RX_IIR(pipe);
3079                         temp = I915_READ(reg);
3080                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3081
3082                         if (temp & FDI_RX_BIT_LOCK ||
3083                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3084                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3085                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3086                                               i);
3087                                 break;
3088                         }
3089                         udelay(1); /* should be 0.5us */
3090                 }
3091                 if (i == 4) {
3092                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3093                         continue;
3094                 }
3095
3096                 /* Train 2 */
3097                 reg = FDI_TX_CTL(pipe);
3098                 temp = I915_READ(reg);
3099                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3100                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3101                 I915_WRITE(reg, temp);
3102
3103                 reg = FDI_RX_CTL(pipe);
3104                 temp = I915_READ(reg);
3105                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3106                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3107                 I915_WRITE(reg, temp);
3108
3109                 POSTING_READ(reg);
3110                 udelay(2); /* should be 1.5us */
3111
3112                 for (i = 0; i < 4; i++) {
3113                         reg = FDI_RX_IIR(pipe);
3114                         temp = I915_READ(reg);
3115                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3116
3117                         if (temp & FDI_RX_SYMBOL_LOCK ||
3118                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3119                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3120                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3121                                               i);
3122                                 goto train_done;
3123                         }
3124                         udelay(2); /* should be 1.5us */
3125                 }
3126                 if (i == 4)
3127                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3128         }
3129
3130 train_done:
3131         DRM_DEBUG_KMS("FDI train done.\n");
3132 }
3133
3134 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3135 {
3136         struct drm_device *dev = intel_crtc->base.dev;
3137         struct drm_i915_private *dev_priv = dev->dev_private;
3138         int pipe = intel_crtc->pipe;
3139         u32 reg, temp;
3140
3141
3142         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3143         reg = FDI_RX_CTL(pipe);
3144         temp = I915_READ(reg);
3145         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3146         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3147         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3148         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3149
3150         POSTING_READ(reg);
3151         udelay(200);
3152
3153         /* Switch from Rawclk to PCDclk */
3154         temp = I915_READ(reg);
3155         I915_WRITE(reg, temp | FDI_PCDCLK);
3156
3157         POSTING_READ(reg);
3158         udelay(200);
3159
3160         /* Enable CPU FDI TX PLL, always on for Ironlake */
3161         reg = FDI_TX_CTL(pipe);
3162         temp = I915_READ(reg);
3163         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3164                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3165
3166                 POSTING_READ(reg);
3167                 udelay(100);
3168         }
3169 }
3170
3171 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3172 {
3173         struct drm_device *dev = intel_crtc->base.dev;
3174         struct drm_i915_private *dev_priv = dev->dev_private;
3175         int pipe = intel_crtc->pipe;
3176         u32 reg, temp;
3177
3178         /* Switch from PCDclk to Rawclk */
3179         reg = FDI_RX_CTL(pipe);
3180         temp = I915_READ(reg);
3181         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3182
3183         /* Disable CPU FDI TX PLL */
3184         reg = FDI_TX_CTL(pipe);
3185         temp = I915_READ(reg);
3186         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3187
3188         POSTING_READ(reg);
3189         udelay(100);
3190
3191         reg = FDI_RX_CTL(pipe);
3192         temp = I915_READ(reg);
3193         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3194
3195         /* Wait for the clocks to turn off. */
3196         POSTING_READ(reg);
3197         udelay(100);
3198 }
3199
3200 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3201 {
3202         struct drm_device *dev = crtc->dev;
3203         struct drm_i915_private *dev_priv = dev->dev_private;
3204         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3205         int pipe = intel_crtc->pipe;
3206         u32 reg, temp;
3207
3208         /* disable CPU FDI tx and PCH FDI rx */
3209         reg = FDI_TX_CTL(pipe);
3210         temp = I915_READ(reg);
3211         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3212         POSTING_READ(reg);
3213
3214         reg = FDI_RX_CTL(pipe);
3215         temp = I915_READ(reg);
3216         temp &= ~(0x7 << 16);
3217         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3218         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3219
3220         POSTING_READ(reg);
3221         udelay(100);
3222
3223         /* Ironlake workaround, disable clock pointer after downing FDI */
3224         if (HAS_PCH_IBX(dev)) {
3225                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3226         }
3227
3228         /* still set train pattern 1 */
3229         reg = FDI_TX_CTL(pipe);
3230         temp = I915_READ(reg);
3231         temp &= ~FDI_LINK_TRAIN_NONE;
3232         temp |= FDI_LINK_TRAIN_PATTERN_1;
3233         I915_WRITE(reg, temp);
3234
3235         reg = FDI_RX_CTL(pipe);
3236         temp = I915_READ(reg);
3237         if (HAS_PCH_CPT(dev)) {
3238                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3239                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3240         } else {
3241                 temp &= ~FDI_LINK_TRAIN_NONE;
3242                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3243         }
3244         /* BPC in FDI rx is consistent with that in PIPECONF */
3245         temp &= ~(0x07 << 16);
3246         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3247         I915_WRITE(reg, temp);
3248
3249         POSTING_READ(reg);
3250         udelay(100);
3251 }
3252
3253 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3254 {
3255         struct intel_crtc *crtc;
3256
3257         /* Note that we don't need to be called with mode_config.lock here
3258          * as our list of CRTC objects is static for the lifetime of the
3259          * device and so cannot disappear as we iterate. Similarly, we can
3260          * happily treat the predicates as racy, atomic checks as userspace
3261          * cannot claim and pin a new fb without at least acquring the
3262          * struct_mutex and so serialising with us.
3263          */
3264         for_each_intel_crtc(dev, crtc) {
3265                 if (atomic_read(&crtc->unpin_work_count) == 0)
3266                         continue;
3267
3268                 if (crtc->unpin_work)
3269                         intel_wait_for_vblank(dev, crtc->pipe);
3270
3271                 return true;
3272         }
3273
3274         return false;
3275 }
3276
3277 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3278 {
3279         struct drm_device *dev = crtc->dev;
3280         struct drm_i915_private *dev_priv = dev->dev_private;
3281
3282         if (crtc->primary->fb == NULL)
3283                 return;
3284
3285         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3286
3287         wait_event(dev_priv->pending_flip_queue,
3288                    !intel_crtc_has_pending_flip(crtc));
3289
3290         mutex_lock(&dev->struct_mutex);
3291         intel_finish_fb(crtc->primary->fb);
3292         mutex_unlock(&dev->struct_mutex);
3293 }
3294
3295 /* Program iCLKIP clock to the desired frequency */
3296 static void lpt_program_iclkip(struct drm_crtc *crtc)
3297 {
3298         struct drm_device *dev = crtc->dev;
3299         struct drm_i915_private *dev_priv = dev->dev_private;
3300         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3301         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3302         u32 temp;
3303
3304         mutex_lock(&dev_priv->dpio_lock);
3305
3306         /* It is necessary to ungate the pixclk gate prior to programming
3307          * the divisors, and gate it back when it is done.
3308          */
3309         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3310
3311         /* Disable SSCCTL */
3312         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3313                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3314                                 SBI_SSCCTL_DISABLE,
3315                         SBI_ICLK);
3316
3317         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3318         if (clock == 20000) {
3319                 auxdiv = 1;
3320                 divsel = 0x41;
3321                 phaseinc = 0x20;
3322         } else {
3323                 /* The iCLK virtual clock root frequency is in MHz,
3324                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3325                  * divisors, it is necessary to divide one by another, so we
3326                  * convert the virtual clock precision to KHz here for higher
3327                  * precision.
3328                  */
3329                 u32 iclk_virtual_root_freq = 172800 * 1000;
3330                 u32 iclk_pi_range = 64;
3331                 u32 desired_divisor, msb_divisor_value, pi_value;
3332
3333                 desired_divisor = (iclk_virtual_root_freq / clock);
3334                 msb_divisor_value = desired_divisor / iclk_pi_range;
3335                 pi_value = desired_divisor % iclk_pi_range;
3336
3337                 auxdiv = 0;
3338                 divsel = msb_divisor_value - 2;
3339                 phaseinc = pi_value;
3340         }
3341
3342         /* This should not happen with any sane values */
3343         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3344                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3345         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3346                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3347
3348         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3349                         clock,
3350                         auxdiv,
3351                         divsel,
3352                         phasedir,
3353                         phaseinc);
3354
3355         /* Program SSCDIVINTPHASE6 */
3356         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3357         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3358         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3359         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3360         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3361         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3362         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3363         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3364
3365         /* Program SSCAUXDIV */
3366         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3367         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3368         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3369         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3370
3371         /* Enable modulator and associated divider */
3372         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3373         temp &= ~SBI_SSCCTL_DISABLE;
3374         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3375
3376         /* Wait for initialization time */
3377         udelay(24);
3378
3379         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3380
3381         mutex_unlock(&dev_priv->dpio_lock);
3382 }
3383
3384 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3385                                                 enum pipe pch_transcoder)
3386 {
3387         struct drm_device *dev = crtc->base.dev;
3388         struct drm_i915_private *dev_priv = dev->dev_private;
3389         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3390
3391         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3392                    I915_READ(HTOTAL(cpu_transcoder)));
3393         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3394                    I915_READ(HBLANK(cpu_transcoder)));
3395         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3396                    I915_READ(HSYNC(cpu_transcoder)));
3397
3398         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3399                    I915_READ(VTOTAL(cpu_transcoder)));
3400         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3401                    I915_READ(VBLANK(cpu_transcoder)));
3402         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3403                    I915_READ(VSYNC(cpu_transcoder)));
3404         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3405                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3406 }
3407
3408 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3409 {
3410         struct drm_i915_private *dev_priv = dev->dev_private;
3411         uint32_t temp;
3412
3413         temp = I915_READ(SOUTH_CHICKEN1);
3414         if (temp & FDI_BC_BIFURCATION_SELECT)
3415                 return;
3416
3417         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3418         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3419
3420         temp |= FDI_BC_BIFURCATION_SELECT;
3421         DRM_DEBUG_KMS("enabling fdi C rx\n");
3422         I915_WRITE(SOUTH_CHICKEN1, temp);
3423         POSTING_READ(SOUTH_CHICKEN1);
3424 }
3425
3426 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3427 {
3428         struct drm_device *dev = intel_crtc->base.dev;
3429         struct drm_i915_private *dev_priv = dev->dev_private;
3430
3431         switch (intel_crtc->pipe) {
3432         case PIPE_A:
3433                 break;
3434         case PIPE_B:
3435                 if (intel_crtc->config.fdi_lanes > 2)
3436                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3437                 else
3438                         cpt_enable_fdi_bc_bifurcation(dev);
3439
3440                 break;
3441         case PIPE_C:
3442                 cpt_enable_fdi_bc_bifurcation(dev);
3443
3444                 break;
3445         default:
3446                 BUG();
3447         }
3448 }
3449
3450 /*
3451  * Enable PCH resources required for PCH ports:
3452  *   - PCH PLLs
3453  *   - FDI training & RX/TX
3454  *   - update transcoder timings
3455  *   - DP transcoding bits
3456  *   - transcoder
3457  */
3458 static void ironlake_pch_enable(struct drm_crtc *crtc)
3459 {
3460         struct drm_device *dev = crtc->dev;
3461         struct drm_i915_private *dev_priv = dev->dev_private;
3462         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3463         int pipe = intel_crtc->pipe;
3464         u32 reg, temp;
3465
3466         assert_pch_transcoder_disabled(dev_priv, pipe);
3467
3468         if (IS_IVYBRIDGE(dev))
3469                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3470
3471         /* Write the TU size bits before fdi link training, so that error
3472          * detection works. */
3473         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3474                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3475
3476         /* For PCH output, training FDI link */
3477         dev_priv->display.fdi_link_train(crtc);
3478
3479         /* We need to program the right clock selection before writing the pixel
3480          * mutliplier into the DPLL. */
3481         if (HAS_PCH_CPT(dev)) {
3482                 u32 sel;
3483
3484                 temp = I915_READ(PCH_DPLL_SEL);
3485                 temp |= TRANS_DPLL_ENABLE(pipe);
3486                 sel = TRANS_DPLLB_SEL(pipe);
3487                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3488                         temp |= sel;
3489                 else
3490                         temp &= ~sel;
3491                 I915_WRITE(PCH_DPLL_SEL, temp);
3492         }
3493
3494         /* XXX: pch pll's can be enabled any time before we enable the PCH
3495          * transcoder, and we actually should do this to not upset any PCH
3496          * transcoder that already use the clock when we share it.
3497          *
3498          * Note that enable_shared_dpll tries to do the right thing, but
3499          * get_shared_dpll unconditionally resets the pll - we need that to have
3500          * the right LVDS enable sequence. */
3501         ironlake_enable_shared_dpll(intel_crtc);
3502
3503         /* set transcoder timing, panel must allow it */
3504         assert_panel_unlocked(dev_priv, pipe);
3505         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3506
3507         intel_fdi_normal_train(crtc);
3508
3509         /* For PCH DP, enable TRANS_DP_CTL */
3510         if (HAS_PCH_CPT(dev) &&
3511             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3512              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3513                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3514                 reg = TRANS_DP_CTL(pipe);
3515                 temp = I915_READ(reg);
3516                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3517                           TRANS_DP_SYNC_MASK |
3518                           TRANS_DP_BPC_MASK);
3519                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3520                          TRANS_DP_ENH_FRAMING);
3521                 temp |= bpc << 9; /* same format but at 11:9 */
3522
3523                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3524                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3525                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3526                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3527
3528                 switch (intel_trans_dp_port_sel(crtc)) {
3529                 case PCH_DP_B:
3530                         temp |= TRANS_DP_PORT_SEL_B;
3531                         break;
3532                 case PCH_DP_C:
3533                         temp |= TRANS_DP_PORT_SEL_C;
3534                         break;
3535                 case PCH_DP_D:
3536                         temp |= TRANS_DP_PORT_SEL_D;
3537                         break;
3538                 default:
3539                         BUG();
3540                 }
3541
3542                 I915_WRITE(reg, temp);
3543         }
3544
3545         ironlake_enable_pch_transcoder(dev_priv, pipe);
3546 }
3547
3548 static void lpt_pch_enable(struct drm_crtc *crtc)
3549 {
3550         struct drm_device *dev = crtc->dev;
3551         struct drm_i915_private *dev_priv = dev->dev_private;
3552         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3553         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3554
3555         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3556
3557         lpt_program_iclkip(crtc);
3558
3559         /* Set transcoder timing. */
3560         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3561
3562         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3563 }
3564
3565 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3566 {
3567         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3568
3569         if (pll == NULL)
3570                 return;
3571
3572         if (pll->refcount == 0) {
3573                 WARN(1, "bad %s refcount\n", pll->name);
3574                 return;
3575         }
3576
3577         if (--pll->refcount == 0) {
3578                 WARN_ON(pll->on);
3579                 WARN_ON(pll->active);
3580         }
3581
3582         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3583 }
3584
3585 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3586 {
3587         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3588         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3589         enum intel_dpll_id i;
3590
3591         if (pll) {
3592                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3593                               crtc->base.base.id, pll->name);
3594                 intel_put_shared_dpll(crtc);
3595         }
3596
3597         if (HAS_PCH_IBX(dev_priv->dev)) {
3598                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3599                 i = (enum intel_dpll_id) crtc->pipe;
3600                 pll = &dev_priv->shared_dplls[i];
3601
3602                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3603                               crtc->base.base.id, pll->name);
3604
3605                 goto found;
3606         }
3607
3608         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3609                 pll = &dev_priv->shared_dplls[i];
3610
3611                 /* Only want to check enabled timings first */
3612                 if (pll->refcount == 0)
3613                         continue;
3614
3615                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3616                            sizeof(pll->hw_state)) == 0) {
3617                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3618                                       crtc->base.base.id,
3619                                       pll->name, pll->refcount, pll->active);
3620
3621                         goto found;
3622                 }
3623         }
3624
3625         /* Ok no matching timings, maybe there's a free one? */
3626         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3627                 pll = &dev_priv->shared_dplls[i];
3628                 if (pll->refcount == 0) {
3629                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3630                                       crtc->base.base.id, pll->name);
3631                         goto found;
3632                 }
3633         }
3634
3635         return NULL;
3636
3637 found:
3638         crtc->config.shared_dpll = i;
3639         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3640                          pipe_name(crtc->pipe));
3641
3642         if (pll->active == 0) {
3643                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3644                        sizeof(pll->hw_state));
3645
3646                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3647                 WARN_ON(pll->on);
3648                 assert_shared_dpll_disabled(dev_priv, pll);
3649
3650                 pll->mode_set(dev_priv, pll);
3651         }
3652         pll->refcount++;
3653
3654         return pll;
3655 }
3656
3657 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3658 {
3659         struct drm_i915_private *dev_priv = dev->dev_private;
3660         int dslreg = PIPEDSL(pipe);
3661         u32 temp;
3662
3663         temp = I915_READ(dslreg);
3664         udelay(500);
3665         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3666                 if (wait_for(I915_READ(dslreg) != temp, 5))
3667                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3668         }
3669 }
3670
3671 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3672 {
3673         struct drm_device *dev = crtc->base.dev;
3674         struct drm_i915_private *dev_priv = dev->dev_private;
3675         int pipe = crtc->pipe;
3676
3677         if (crtc->config.pch_pfit.enabled) {
3678                 /* Force use of hard-coded filter coefficients
3679                  * as some pre-programmed values are broken,
3680                  * e.g. x201.
3681                  */
3682                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3683                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3684                                                  PF_PIPE_SEL_IVB(pipe));
3685                 else
3686                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3687                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3688                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3689         }
3690 }
3691
3692 static void intel_enable_planes(struct drm_crtc *crtc)
3693 {
3694         struct drm_device *dev = crtc->dev;
3695         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3696         struct drm_plane *plane;
3697         struct intel_plane *intel_plane;
3698
3699         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3700                 intel_plane = to_intel_plane(plane);
3701                 if (intel_plane->pipe == pipe)
3702                         intel_plane_restore(&intel_plane->base);
3703         }
3704 }
3705
3706 static void intel_disable_planes(struct drm_crtc *crtc)
3707 {
3708         struct drm_device *dev = crtc->dev;
3709         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3710         struct drm_plane *plane;
3711         struct intel_plane *intel_plane;
3712
3713         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3714                 intel_plane = to_intel_plane(plane);
3715                 if (intel_plane->pipe == pipe)
3716                         intel_plane_disable(&intel_plane->base);
3717         }
3718 }
3719
3720 void hsw_enable_ips(struct intel_crtc *crtc)
3721 {
3722         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3723
3724         if (!crtc->config.ips_enabled)
3725                 return;
3726
3727         /* We can only enable IPS after we enable a plane and wait for a vblank.
3728          * We guarantee that the plane is enabled by calling intel_enable_ips
3729          * only after intel_enable_plane. And intel_enable_plane already waits
3730          * for a vblank, so all we need to do here is to enable the IPS bit. */
3731         assert_plane_enabled(dev_priv, crtc->plane);
3732         if (IS_BROADWELL(crtc->base.dev)) {
3733                 mutex_lock(&dev_priv->rps.hw_lock);
3734                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3735                 mutex_unlock(&dev_priv->rps.hw_lock);
3736                 /* Quoting Art Runyan: "its not safe to expect any particular
3737                  * value in IPS_CTL bit 31 after enabling IPS through the
3738                  * mailbox." Moreover, the mailbox may return a bogus state,
3739                  * so we need to just enable it and continue on.
3740                  */
3741         } else {
3742                 I915_WRITE(IPS_CTL, IPS_ENABLE);
3743                 /* The bit only becomes 1 in the next vblank, so this wait here
3744                  * is essentially intel_wait_for_vblank. If we don't have this
3745                  * and don't wait for vblanks until the end of crtc_enable, then
3746                  * the HW state readout code will complain that the expected
3747                  * IPS_CTL value is not the one we read. */
3748                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3749                         DRM_ERROR("Timed out waiting for IPS enable\n");
3750         }
3751 }
3752
3753 void hsw_disable_ips(struct intel_crtc *crtc)
3754 {
3755         struct drm_device *dev = crtc->base.dev;
3756         struct drm_i915_private *dev_priv = dev->dev_private;
3757
3758         if (!crtc->config.ips_enabled)
3759                 return;
3760
3761         assert_plane_enabled(dev_priv, crtc->plane);
3762         if (IS_BROADWELL(dev)) {
3763                 mutex_lock(&dev_priv->rps.hw_lock);
3764                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3765                 mutex_unlock(&dev_priv->rps.hw_lock);
3766                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3767                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3768                         DRM_ERROR("Timed out waiting for IPS disable\n");
3769         } else {
3770                 I915_WRITE(IPS_CTL, 0);
3771                 POSTING_READ(IPS_CTL);
3772         }
3773
3774         /* We need to wait for a vblank before we can disable the plane. */
3775         intel_wait_for_vblank(dev, crtc->pipe);
3776 }
3777
3778 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3779 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3780 {
3781         struct drm_device *dev = crtc->dev;
3782         struct drm_i915_private *dev_priv = dev->dev_private;
3783         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3784         enum pipe pipe = intel_crtc->pipe;
3785         int palreg = PALETTE(pipe);
3786         int i;
3787         bool reenable_ips = false;
3788
3789         /* The clocks have to be on to load the palette. */
3790         if (!crtc->enabled || !intel_crtc->active)
3791                 return;
3792
3793         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3794                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3795                         assert_dsi_pll_enabled(dev_priv);
3796                 else
3797                         assert_pll_enabled(dev_priv, pipe);
3798         }
3799
3800         /* use legacy palette for Ironlake */
3801         if (HAS_PCH_SPLIT(dev))
3802                 palreg = LGC_PALETTE(pipe);
3803
3804         /* Workaround : Do not read or write the pipe palette/gamma data while
3805          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3806          */
3807         if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3808             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3809              GAMMA_MODE_MODE_SPLIT)) {
3810                 hsw_disable_ips(intel_crtc);
3811                 reenable_ips = true;
3812         }
3813
3814         for (i = 0; i < 256; i++) {
3815                 I915_WRITE(palreg + 4 * i,
3816                            (intel_crtc->lut_r[i] << 16) |
3817                            (intel_crtc->lut_g[i] << 8) |
3818                            intel_crtc->lut_b[i]);
3819         }
3820
3821         if (reenable_ips)
3822                 hsw_enable_ips(intel_crtc);
3823 }
3824
3825 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3826 {
3827         if (!enable && intel_crtc->overlay) {
3828                 struct drm_device *dev = intel_crtc->base.dev;
3829                 struct drm_i915_private *dev_priv = dev->dev_private;
3830
3831                 mutex_lock(&dev->struct_mutex);
3832                 dev_priv->mm.interruptible = false;
3833                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3834                 dev_priv->mm.interruptible = true;
3835                 mutex_unlock(&dev->struct_mutex);
3836         }
3837
3838         /* Let userspace switch the overlay on again. In most cases userspace
3839          * has to recompute where to put it anyway.
3840          */
3841 }
3842
3843 /**
3844  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3845  * cursor plane briefly if not already running after enabling the display
3846  * plane.
3847  * This workaround avoids occasional blank screens when self refresh is
3848  * enabled.
3849  */
3850 static void
3851 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3852 {
3853         u32 cntl = I915_READ(CURCNTR(pipe));
3854
3855         if ((cntl & CURSOR_MODE) == 0) {
3856                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3857
3858                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3859                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3860                 intel_wait_for_vblank(dev_priv->dev, pipe);
3861                 I915_WRITE(CURCNTR(pipe), cntl);
3862                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3863                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3864         }
3865 }
3866
3867 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
3868 {
3869         struct drm_device *dev = crtc->dev;
3870         struct drm_i915_private *dev_priv = dev->dev_private;
3871         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3872         int pipe = intel_crtc->pipe;
3873         int plane = intel_crtc->plane;
3874
3875         intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3876         intel_enable_planes(crtc);
3877         /* The fixup needs to happen before cursor is enabled */
3878         if (IS_G4X(dev))
3879                 g4x_fixup_plane(dev_priv, pipe);
3880         intel_crtc_update_cursor(crtc, true);
3881         intel_crtc_dpms_overlay(intel_crtc, true);
3882
3883         hsw_enable_ips(intel_crtc);
3884
3885         mutex_lock(&dev->struct_mutex);
3886         intel_update_fbc(dev);
3887         mutex_unlock(&dev->struct_mutex);
3888 }
3889
3890 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
3891 {
3892         struct drm_device *dev = crtc->dev;
3893         struct drm_i915_private *dev_priv = dev->dev_private;
3894         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3895         int pipe = intel_crtc->pipe;
3896         int plane = intel_crtc->plane;
3897
3898         intel_crtc_wait_for_pending_flips(crtc);
3899         drm_vblank_off(dev, pipe);
3900
3901         if (dev_priv->fbc.plane == plane)
3902                 intel_disable_fbc(dev);
3903
3904         hsw_disable_ips(intel_crtc);
3905
3906         intel_crtc_dpms_overlay(intel_crtc, false);
3907         intel_crtc_update_cursor(crtc, false);
3908         intel_disable_planes(crtc);
3909         intel_disable_primary_hw_plane(dev_priv, plane, pipe);
3910 }
3911
3912 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3913 {
3914         struct drm_device *dev = crtc->dev;
3915         struct drm_i915_private *dev_priv = dev->dev_private;
3916         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3917         struct intel_encoder *encoder;
3918         int pipe = intel_crtc->pipe;
3919
3920         WARN_ON(!crtc->enabled);
3921
3922         if (intel_crtc->active)
3923                 return;
3924
3925         intel_crtc->active = true;
3926
3927         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3928         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3929
3930         for_each_encoder_on_crtc(dev, crtc, encoder)
3931                 if (encoder->pre_enable)
3932                         encoder->pre_enable(encoder);
3933
3934         if (intel_crtc->config.has_pch_encoder) {
3935                 /* Note: FDI PLL enabling _must_ be done before we enable the
3936                  * cpu pipes, hence this is separate from all the other fdi/pch
3937                  * enabling. */
3938                 ironlake_fdi_pll_enable(intel_crtc);
3939         } else {
3940                 assert_fdi_tx_disabled(dev_priv, pipe);
3941                 assert_fdi_rx_disabled(dev_priv, pipe);
3942         }
3943
3944         ironlake_pfit_enable(intel_crtc);
3945
3946         /*
3947          * On ILK+ LUT must be loaded before the pipe is running but with
3948          * clocks enabled
3949          */
3950         intel_crtc_load_lut(crtc);
3951
3952         intel_update_watermarks(crtc);
3953         intel_enable_pipe(intel_crtc);
3954
3955         if (intel_crtc->config.has_pch_encoder)
3956                 ironlake_pch_enable(crtc);
3957
3958         for_each_encoder_on_crtc(dev, crtc, encoder)
3959                 encoder->enable(encoder);
3960
3961         if (HAS_PCH_CPT(dev))
3962                 cpt_verify_modeset(dev, intel_crtc->pipe);
3963
3964         intel_crtc_enable_planes(crtc);
3965
3966         /*
3967          * There seems to be a race in PCH platform hw (at least on some
3968          * outputs) where an enabled pipe still completes any pageflip right
3969          * away (as if the pipe is off) instead of waiting for vblank. As soon
3970          * as the first vblank happend, everything works as expected. Hence just
3971          * wait for one vblank before returning to avoid strange things
3972          * happening.
3973          */
3974         intel_wait_for_vblank(dev, intel_crtc->pipe);
3975 }
3976
3977 /* IPS only exists on ULT machines and is tied to pipe A. */
3978 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3979 {
3980         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3981 }
3982
3983 /*
3984  * This implements the workaround described in the "notes" section of the mode
3985  * set sequence documentation. When going from no pipes or single pipe to
3986  * multiple pipes, and planes are enabled after the pipe, we need to wait at
3987  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3988  */
3989 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3990 {
3991         struct drm_device *dev = crtc->base.dev;
3992         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3993
3994         /* We want to get the other_active_crtc only if there's only 1 other
3995          * active crtc. */
3996         for_each_intel_crtc(dev, crtc_it) {
3997                 if (!crtc_it->active || crtc_it == crtc)
3998                         continue;
3999
4000                 if (other_active_crtc)
4001                         return;
4002
4003                 other_active_crtc = crtc_it;
4004         }
4005         if (!other_active_crtc)
4006                 return;
4007
4008         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4009         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4010 }
4011
4012 static void haswell_crtc_enable(struct drm_crtc *crtc)
4013 {
4014         struct drm_device *dev = crtc->dev;
4015         struct drm_i915_private *dev_priv = dev->dev_private;
4016         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4017         struct intel_encoder *encoder;
4018         int pipe = intel_crtc->pipe;
4019
4020         WARN_ON(!crtc->enabled);
4021
4022         if (intel_crtc->active)
4023                 return;
4024
4025         intel_crtc->active = true;
4026
4027         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4028         if (intel_crtc->config.has_pch_encoder)
4029                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4030
4031         if (intel_crtc->config.has_pch_encoder)
4032                 dev_priv->display.fdi_link_train(crtc);
4033
4034         for_each_encoder_on_crtc(dev, crtc, encoder)
4035                 if (encoder->pre_enable)
4036                         encoder->pre_enable(encoder);
4037
4038         intel_ddi_enable_pipe_clock(intel_crtc);
4039
4040         ironlake_pfit_enable(intel_crtc);
4041
4042         /*
4043          * On ILK+ LUT must be loaded before the pipe is running but with
4044          * clocks enabled
4045          */
4046         intel_crtc_load_lut(crtc);
4047
4048         intel_ddi_set_pipe_settings(crtc);
4049         intel_ddi_enable_transcoder_func(crtc);
4050
4051         intel_update_watermarks(crtc);
4052         intel_enable_pipe(intel_crtc);
4053
4054         if (intel_crtc->config.has_pch_encoder)
4055                 lpt_pch_enable(crtc);
4056
4057         for_each_encoder_on_crtc(dev, crtc, encoder) {
4058                 encoder->enable(encoder);
4059                 intel_opregion_notify_encoder(encoder, true);
4060         }
4061
4062         /* If we change the relative order between pipe/planes enabling, we need
4063          * to change the workaround. */
4064         haswell_mode_set_planes_workaround(intel_crtc);
4065         intel_crtc_enable_planes(crtc);
4066 }
4067
4068 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4069 {
4070         struct drm_device *dev = crtc->base.dev;
4071         struct drm_i915_private *dev_priv = dev->dev_private;
4072         int pipe = crtc->pipe;
4073
4074         /* To avoid upsetting the power well on haswell only disable the pfit if
4075          * it's in use. The hw state code will make sure we get this right. */
4076         if (crtc->config.pch_pfit.enabled) {
4077                 I915_WRITE(PF_CTL(pipe), 0);
4078                 I915_WRITE(PF_WIN_POS(pipe), 0);
4079                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4080         }
4081 }
4082
4083 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4084 {
4085         struct drm_device *dev = crtc->dev;
4086         struct drm_i915_private *dev_priv = dev->dev_private;
4087         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4088         struct intel_encoder *encoder;
4089         int pipe = intel_crtc->pipe;
4090         u32 reg, temp;
4091
4092         if (!intel_crtc->active)
4093                 return;
4094
4095         intel_crtc_disable_planes(crtc);
4096
4097         for_each_encoder_on_crtc(dev, crtc, encoder)
4098                 encoder->disable(encoder);
4099
4100         if (intel_crtc->config.has_pch_encoder)
4101                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4102
4103         intel_disable_pipe(dev_priv, pipe);
4104
4105         ironlake_pfit_disable(intel_crtc);
4106
4107         for_each_encoder_on_crtc(dev, crtc, encoder)
4108                 if (encoder->post_disable)
4109                         encoder->post_disable(encoder);
4110
4111         if (intel_crtc->config.has_pch_encoder) {
4112                 ironlake_fdi_disable(crtc);
4113
4114                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4115                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4116
4117                 if (HAS_PCH_CPT(dev)) {
4118                         /* disable TRANS_DP_CTL */
4119                         reg = TRANS_DP_CTL(pipe);
4120                         temp = I915_READ(reg);
4121                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4122                                   TRANS_DP_PORT_SEL_MASK);
4123                         temp |= TRANS_DP_PORT_SEL_NONE;
4124                         I915_WRITE(reg, temp);
4125
4126                         /* disable DPLL_SEL */
4127                         temp = I915_READ(PCH_DPLL_SEL);
4128                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4129                         I915_WRITE(PCH_DPLL_SEL, temp);
4130                 }
4131
4132                 /* disable PCH DPLL */
4133                 intel_disable_shared_dpll(intel_crtc);
4134
4135                 ironlake_fdi_pll_disable(intel_crtc);
4136         }
4137
4138         intel_crtc->active = false;
4139         intel_update_watermarks(crtc);
4140
4141         mutex_lock(&dev->struct_mutex);
4142         intel_update_fbc(dev);
4143         mutex_unlock(&dev->struct_mutex);
4144 }
4145
4146 static void haswell_crtc_disable(struct drm_crtc *crtc)
4147 {
4148         struct drm_device *dev = crtc->dev;
4149         struct drm_i915_private *dev_priv = dev->dev_private;
4150         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4151         struct intel_encoder *encoder;
4152         int pipe = intel_crtc->pipe;
4153         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4154
4155         if (!intel_crtc->active)
4156                 return;
4157
4158         intel_crtc_disable_planes(crtc);
4159
4160         for_each_encoder_on_crtc(dev, crtc, encoder) {
4161                 intel_opregion_notify_encoder(encoder, false);
4162                 encoder->disable(encoder);
4163         }
4164
4165         if (intel_crtc->config.has_pch_encoder)
4166                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4167         intel_disable_pipe(dev_priv, pipe);
4168
4169         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4170
4171         ironlake_pfit_disable(intel_crtc);
4172
4173         intel_ddi_disable_pipe_clock(intel_crtc);
4174
4175         for_each_encoder_on_crtc(dev, crtc, encoder)
4176                 if (encoder->post_disable)
4177                         encoder->post_disable(encoder);
4178
4179         if (intel_crtc->config.has_pch_encoder) {
4180                 lpt_disable_pch_transcoder(dev_priv);
4181                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4182                 intel_ddi_fdi_disable(crtc);
4183         }
4184
4185         intel_crtc->active = false;
4186         intel_update_watermarks(crtc);
4187
4188         mutex_lock(&dev->struct_mutex);
4189         intel_update_fbc(dev);
4190         mutex_unlock(&dev->struct_mutex);
4191 }
4192
4193 static void ironlake_crtc_off(struct drm_crtc *crtc)
4194 {
4195         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4196         intel_put_shared_dpll(intel_crtc);
4197 }
4198
4199 static void haswell_crtc_off(struct drm_crtc *crtc)
4200 {
4201         intel_ddi_put_crtc_pll(crtc);
4202 }
4203
4204 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4205 {
4206         struct drm_device *dev = crtc->base.dev;
4207         struct drm_i915_private *dev_priv = dev->dev_private;
4208         struct intel_crtc_config *pipe_config = &crtc->config;
4209
4210         if (!crtc->config.gmch_pfit.control)
4211                 return;
4212
4213         /*
4214          * The panel fitter should only be adjusted whilst the pipe is disabled,
4215          * according to register description and PRM.
4216          */
4217         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4218         assert_pipe_disabled(dev_priv, crtc->pipe);
4219
4220         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4221         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4222
4223         /* Border color in case we don't scale up to the full screen. Black by
4224          * default, change to something else for debugging. */
4225         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4226 }
4227
4228 #define for_each_power_domain(domain, mask)                             \
4229         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4230                 if ((1 << (domain)) & (mask))
4231
4232 enum intel_display_power_domain
4233 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4234 {
4235         struct drm_device *dev = intel_encoder->base.dev;
4236         struct intel_digital_port *intel_dig_port;
4237
4238         switch (intel_encoder->type) {
4239         case INTEL_OUTPUT_UNKNOWN:
4240                 /* Only DDI platforms should ever use this output type */
4241                 WARN_ON_ONCE(!HAS_DDI(dev));
4242         case INTEL_OUTPUT_DISPLAYPORT:
4243         case INTEL_OUTPUT_HDMI:
4244         case INTEL_OUTPUT_EDP:
4245                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4246                 switch (intel_dig_port->port) {
4247                 case PORT_A:
4248                         return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4249                 case PORT_B:
4250                         return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4251                 case PORT_C:
4252                         return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4253                 case PORT_D:
4254                         return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4255                 default:
4256                         WARN_ON_ONCE(1);
4257                         return POWER_DOMAIN_PORT_OTHER;
4258                 }
4259         case INTEL_OUTPUT_ANALOG:
4260                 return POWER_DOMAIN_PORT_CRT;
4261         case INTEL_OUTPUT_DSI:
4262                 return POWER_DOMAIN_PORT_DSI;
4263         default:
4264                 return POWER_DOMAIN_PORT_OTHER;
4265         }
4266 }
4267
4268 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4269 {
4270         struct drm_device *dev = crtc->dev;
4271         struct intel_encoder *intel_encoder;
4272         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4273         enum pipe pipe = intel_crtc->pipe;
4274         bool pfit_enabled = intel_crtc->config.pch_pfit.enabled;
4275         unsigned long mask;
4276         enum transcoder transcoder;
4277
4278         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4279
4280         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4281         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4282         if (pfit_enabled)
4283                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4284
4285         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4286                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4287
4288         return mask;
4289 }
4290
4291 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4292                                   bool enable)
4293 {
4294         if (dev_priv->power_domains.init_power_on == enable)
4295                 return;
4296
4297         if (enable)
4298                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4299         else
4300                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4301
4302         dev_priv->power_domains.init_power_on = enable;
4303 }
4304
4305 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4306 {
4307         struct drm_i915_private *dev_priv = dev->dev_private;
4308         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4309         struct intel_crtc *crtc;
4310
4311         /*
4312          * First get all needed power domains, then put all unneeded, to avoid
4313          * any unnecessary toggling of the power wells.
4314          */
4315         for_each_intel_crtc(dev, crtc) {
4316                 enum intel_display_power_domain domain;
4317
4318                 if (!crtc->base.enabled)
4319                         continue;
4320
4321                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4322
4323                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4324                         intel_display_power_get(dev_priv, domain);
4325         }
4326
4327         for_each_intel_crtc(dev, crtc) {
4328                 enum intel_display_power_domain domain;
4329
4330                 for_each_power_domain(domain, crtc->enabled_power_domains)
4331                         intel_display_power_put(dev_priv, domain);
4332
4333                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4334         }
4335
4336         intel_display_set_init_power(dev_priv, false);
4337 }
4338
4339 int valleyview_get_vco(struct drm_i915_private *dev_priv)
4340 {
4341         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4342
4343         /* Obtain SKU information */
4344         mutex_lock(&dev_priv->dpio_lock);
4345         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4346                 CCK_FUSE_HPLL_FREQ_MASK;
4347         mutex_unlock(&dev_priv->dpio_lock);
4348
4349         return vco_freq[hpll_freq];
4350 }
4351
4352 /* Adjust CDclk dividers to allow high res or save power if possible */
4353 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4354 {
4355         struct drm_i915_private *dev_priv = dev->dev_private;
4356         u32 val, cmd;
4357
4358         WARN_ON(valleyview_cur_cdclk(dev_priv) != dev_priv->vlv_cdclk_freq);
4359         dev_priv->vlv_cdclk_freq = cdclk;
4360
4361         if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
4362                 cmd = 2;
4363         else if (cdclk == 266)
4364                 cmd = 1;
4365         else
4366                 cmd = 0;
4367
4368         mutex_lock(&dev_priv->rps.hw_lock);
4369         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4370         val &= ~DSPFREQGUAR_MASK;
4371         val |= (cmd << DSPFREQGUAR_SHIFT);
4372         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4373         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4374                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4375                      50)) {
4376                 DRM_ERROR("timed out waiting for CDclk change\n");
4377         }
4378         mutex_unlock(&dev_priv->rps.hw_lock);
4379
4380         if (cdclk == 400) {
4381                 u32 divider, vco;
4382
4383                 vco = valleyview_get_vco(dev_priv);
4384                 divider = ((vco << 1) / cdclk) - 1;
4385
4386                 mutex_lock(&dev_priv->dpio_lock);
4387                 /* adjust cdclk divider */
4388                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4389                 val &= ~0xf;
4390                 val |= divider;
4391                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4392                 mutex_unlock(&dev_priv->dpio_lock);
4393         }
4394
4395         mutex_lock(&dev_priv->dpio_lock);
4396         /* adjust self-refresh exit latency value */
4397         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4398         val &= ~0x7f;
4399
4400         /*
4401          * For high bandwidth configs, we set a higher latency in the bunit
4402          * so that the core display fetch happens in time to avoid underruns.
4403          */
4404         if (cdclk == 400)
4405                 val |= 4500 / 250; /* 4.5 usec */
4406         else
4407                 val |= 3000 / 250; /* 3.0 usec */
4408         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4409         mutex_unlock(&dev_priv->dpio_lock);
4410
4411         /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4412         intel_i2c_reset(dev);
4413 }
4414
4415 int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4416 {
4417         int cur_cdclk, vco;
4418         int divider;
4419
4420         vco = valleyview_get_vco(dev_priv);
4421
4422         mutex_lock(&dev_priv->dpio_lock);
4423         divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4424         mutex_unlock(&dev_priv->dpio_lock);
4425
4426         divider &= 0xf;
4427
4428         cur_cdclk = (vco << 1) / (divider + 1);
4429
4430         return cur_cdclk;
4431 }
4432
4433 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4434                                  int max_pixclk)
4435 {
4436         /*
4437          * Really only a few cases to deal with, as only 4 CDclks are supported:
4438          *   200MHz
4439          *   267MHz
4440          *   320MHz
4441          *   400MHz
4442          * So we check to see whether we're above 90% of the lower bin and
4443          * adjust if needed.
4444          */
4445         if (max_pixclk > 288000) {
4446                 return 400;
4447         } else if (max_pixclk > 240000) {
4448                 return 320;
4449         } else
4450                 return 266;
4451         /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4452 }
4453
4454 /* compute the max pixel clock for new configuration */
4455 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4456 {
4457         struct drm_device *dev = dev_priv->dev;
4458         struct intel_crtc *intel_crtc;
4459         int max_pixclk = 0;
4460
4461         for_each_intel_crtc(dev, intel_crtc) {
4462                 if (intel_crtc->new_enabled)
4463                         max_pixclk = max(max_pixclk,
4464                                          intel_crtc->new_config->adjusted_mode.crtc_clock);
4465         }
4466
4467         return max_pixclk;
4468 }
4469
4470 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4471                                             unsigned *prepare_pipes)
4472 {
4473         struct drm_i915_private *dev_priv = dev->dev_private;
4474         struct intel_crtc *intel_crtc;
4475         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4476
4477         if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4478             dev_priv->vlv_cdclk_freq)
4479                 return;
4480
4481         /* disable/enable all currently active pipes while we change cdclk */
4482         for_each_intel_crtc(dev, intel_crtc)
4483                 if (intel_crtc->base.enabled)
4484                         *prepare_pipes |= (1 << intel_crtc->pipe);
4485 }
4486
4487 static void valleyview_modeset_global_resources(struct drm_device *dev)
4488 {
4489         struct drm_i915_private *dev_priv = dev->dev_private;
4490         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4491         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4492
4493         if (req_cdclk != dev_priv->vlv_cdclk_freq)
4494                 valleyview_set_cdclk(dev, req_cdclk);
4495         modeset_update_crtc_power_domains(dev);
4496 }
4497
4498 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4499 {
4500         struct drm_device *dev = crtc->dev;
4501         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4502         struct intel_encoder *encoder;
4503         int pipe = intel_crtc->pipe;
4504         bool is_dsi;
4505
4506         WARN_ON(!crtc->enabled);
4507
4508         if (intel_crtc->active)
4509                 return;
4510
4511         intel_crtc->active = true;
4512
4513         for_each_encoder_on_crtc(dev, crtc, encoder)
4514                 if (encoder->pre_pll_enable)
4515                         encoder->pre_pll_enable(encoder);
4516
4517         is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4518
4519         if (!is_dsi) {
4520                 if (IS_CHERRYVIEW(dev))
4521                         chv_enable_pll(intel_crtc);
4522                 else
4523                         vlv_enable_pll(intel_crtc);
4524         }
4525
4526         for_each_encoder_on_crtc(dev, crtc, encoder)
4527                 if (encoder->pre_enable)
4528                         encoder->pre_enable(encoder);
4529
4530         i9xx_pfit_enable(intel_crtc);
4531
4532         intel_crtc_load_lut(crtc);
4533
4534         intel_update_watermarks(crtc);
4535         intel_enable_pipe(intel_crtc);
4536         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4537
4538         for_each_encoder_on_crtc(dev, crtc, encoder)
4539                 encoder->enable(encoder);
4540
4541         intel_crtc_enable_planes(crtc);
4542 }
4543
4544 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4545 {
4546         struct drm_device *dev = crtc->dev;
4547         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4548         struct intel_encoder *encoder;
4549         int pipe = intel_crtc->pipe;
4550
4551         WARN_ON(!crtc->enabled);
4552
4553         if (intel_crtc->active)
4554                 return;
4555
4556         intel_crtc->active = true;
4557
4558         for_each_encoder_on_crtc(dev, crtc, encoder)
4559                 if (encoder->pre_enable)
4560                         encoder->pre_enable(encoder);
4561
4562         i9xx_enable_pll(intel_crtc);
4563
4564         i9xx_pfit_enable(intel_crtc);
4565
4566         intel_crtc_load_lut(crtc);
4567
4568         intel_update_watermarks(crtc);
4569         intel_enable_pipe(intel_crtc);
4570         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4571
4572         for_each_encoder_on_crtc(dev, crtc, encoder)
4573                 encoder->enable(encoder);
4574
4575         intel_crtc_enable_planes(crtc);
4576 }
4577
4578 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4579 {
4580         struct drm_device *dev = crtc->base.dev;
4581         struct drm_i915_private *dev_priv = dev->dev_private;
4582
4583         if (!crtc->config.gmch_pfit.control)
4584                 return;
4585
4586         assert_pipe_disabled(dev_priv, crtc->pipe);
4587
4588         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4589                          I915_READ(PFIT_CONTROL));
4590         I915_WRITE(PFIT_CONTROL, 0);
4591 }
4592
4593 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4594 {
4595         struct drm_device *dev = crtc->dev;
4596         struct drm_i915_private *dev_priv = dev->dev_private;
4597         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4598         struct intel_encoder *encoder;
4599         int pipe = intel_crtc->pipe;
4600
4601         if (!intel_crtc->active)
4602                 return;
4603
4604         intel_crtc_disable_planes(crtc);
4605
4606         for_each_encoder_on_crtc(dev, crtc, encoder)
4607                 encoder->disable(encoder);
4608
4609         intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4610         intel_disable_pipe(dev_priv, pipe);
4611
4612         i9xx_pfit_disable(intel_crtc);
4613
4614         for_each_encoder_on_crtc(dev, crtc, encoder)
4615                 if (encoder->post_disable)
4616                         encoder->post_disable(encoder);
4617
4618         if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4619                 if (IS_CHERRYVIEW(dev))
4620                         chv_disable_pll(dev_priv, pipe);
4621                 else if (IS_VALLEYVIEW(dev))
4622                         vlv_disable_pll(dev_priv, pipe);
4623                 else
4624                         i9xx_disable_pll(dev_priv, pipe);
4625         }
4626
4627         intel_crtc->active = false;
4628         intel_update_watermarks(crtc);
4629
4630         intel_update_fbc(dev);
4631 }
4632
4633 static void i9xx_crtc_off(struct drm_crtc *crtc)
4634 {
4635 }
4636
4637 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4638                                     bool enabled)
4639 {
4640         struct drm_device *dev = crtc->dev;
4641         struct drm_i915_master_private *master_priv;
4642         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4643         int pipe = intel_crtc->pipe;
4644
4645         if (!dev->primary->master)
4646                 return;
4647
4648         master_priv = dev->primary->master->driver_priv;
4649         if (!master_priv->sarea_priv)
4650                 return;
4651
4652         switch (pipe) {
4653         case 0:
4654                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4655                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4656                 break;
4657         case 1:
4658                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4659                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4660                 break;
4661         default:
4662                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4663                 break;
4664         }
4665 }
4666
4667 /**
4668  * Sets the power management mode of the pipe and plane.
4669  */
4670 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4671 {
4672         struct drm_device *dev = crtc->dev;
4673         struct drm_i915_private *dev_priv = dev->dev_private;
4674         struct intel_encoder *intel_encoder;
4675         bool enable = false;
4676
4677         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4678                 enable |= intel_encoder->connectors_active;
4679
4680         if (enable)
4681                 dev_priv->display.crtc_enable(crtc);
4682         else
4683                 dev_priv->display.crtc_disable(crtc);
4684
4685         intel_crtc_update_sarea(crtc, enable);
4686 }
4687
4688 static void intel_crtc_disable(struct drm_crtc *crtc)
4689 {
4690         struct drm_device *dev = crtc->dev;
4691         struct drm_connector *connector;
4692         struct drm_i915_private *dev_priv = dev->dev_private;
4693         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4694
4695         /* crtc should still be enabled when we disable it. */
4696         WARN_ON(!crtc->enabled);
4697
4698         dev_priv->display.crtc_disable(crtc);
4699         intel_crtc->eld_vld = false;
4700         intel_crtc_update_sarea(crtc, false);
4701         dev_priv->display.off(crtc);
4702
4703         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4704         assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4705         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4706
4707         if (crtc->primary->fb) {
4708                 mutex_lock(&dev->struct_mutex);
4709                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->primary->fb)->obj);
4710                 mutex_unlock(&dev->struct_mutex);
4711                 crtc->primary->fb = NULL;
4712         }
4713
4714         /* Update computed state. */
4715         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4716                 if (!connector->encoder || !connector->encoder->crtc)
4717                         continue;
4718
4719                 if (connector->encoder->crtc != crtc)
4720                         continue;
4721
4722                 connector->dpms = DRM_MODE_DPMS_OFF;
4723                 to_intel_encoder(connector->encoder)->connectors_active = false;
4724         }
4725 }
4726
4727 void intel_encoder_destroy(struct drm_encoder *encoder)
4728 {
4729         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4730
4731         drm_encoder_cleanup(encoder);
4732         kfree(intel_encoder);
4733 }
4734
4735 /* Simple dpms helper for encoders with just one connector, no cloning and only
4736  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4737  * state of the entire output pipe. */
4738 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4739 {
4740         if (mode == DRM_MODE_DPMS_ON) {
4741                 encoder->connectors_active = true;
4742
4743                 intel_crtc_update_dpms(encoder->base.crtc);
4744         } else {
4745                 encoder->connectors_active = false;
4746
4747                 intel_crtc_update_dpms(encoder->base.crtc);
4748         }
4749 }
4750
4751 /* Cross check the actual hw state with our own modeset state tracking (and it's
4752  * internal consistency). */
4753 static void intel_connector_check_state(struct intel_connector *connector)
4754 {
4755         if (connector->get_hw_state(connector)) {
4756                 struct intel_encoder *encoder = connector->encoder;
4757                 struct drm_crtc *crtc;
4758                 bool encoder_enabled;
4759                 enum pipe pipe;
4760
4761                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4762                               connector->base.base.id,
4763                               drm_get_connector_name(&connector->base));
4764
4765                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4766                      "wrong connector dpms state\n");
4767                 WARN(connector->base.encoder != &encoder->base,
4768                      "active connector not linked to encoder\n");
4769                 WARN(!encoder->connectors_active,
4770                      "encoder->connectors_active not set\n");
4771
4772                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4773                 WARN(!encoder_enabled, "encoder not enabled\n");
4774                 if (WARN_ON(!encoder->base.crtc))
4775                         return;
4776
4777                 crtc = encoder->base.crtc;
4778
4779                 WARN(!crtc->enabled, "crtc not enabled\n");
4780                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4781                 WARN(pipe != to_intel_crtc(crtc)->pipe,
4782                      "encoder active on the wrong pipe\n");
4783         }
4784 }
4785
4786 /* Even simpler default implementation, if there's really no special case to
4787  * consider. */
4788 void intel_connector_dpms(struct drm_connector *connector, int mode)
4789 {
4790         /* All the simple cases only support two dpms states. */
4791         if (mode != DRM_MODE_DPMS_ON)
4792                 mode = DRM_MODE_DPMS_OFF;
4793
4794         if (mode == connector->dpms)
4795                 return;
4796
4797         connector->dpms = mode;
4798
4799         /* Only need to change hw state when actually enabled */
4800         if (connector->encoder)
4801                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
4802
4803         intel_modeset_check_state(connector->dev);
4804 }
4805
4806 /* Simple connector->get_hw_state implementation for encoders that support only
4807  * one connector and no cloning and hence the encoder state determines the state
4808  * of the connector. */
4809 bool intel_connector_get_hw_state(struct intel_connector *connector)
4810 {
4811         enum pipe pipe = 0;
4812         struct intel_encoder *encoder = connector->encoder;
4813
4814         return encoder->get_hw_state(encoder, &pipe);
4815 }
4816
4817 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4818                                      struct intel_crtc_config *pipe_config)
4819 {
4820         struct drm_i915_private *dev_priv = dev->dev_private;
4821         struct intel_crtc *pipe_B_crtc =
4822                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4823
4824         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4825                       pipe_name(pipe), pipe_config->fdi_lanes);
4826         if (pipe_config->fdi_lanes > 4) {
4827                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4828                               pipe_name(pipe), pipe_config->fdi_lanes);
4829                 return false;
4830         }
4831
4832         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4833                 if (pipe_config->fdi_lanes > 2) {
4834                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4835                                       pipe_config->fdi_lanes);
4836                         return false;
4837                 } else {
4838                         return true;
4839                 }
4840         }
4841
4842         if (INTEL_INFO(dev)->num_pipes == 2)
4843                 return true;
4844
4845         /* Ivybridge 3 pipe is really complicated */
4846         switch (pipe) {
4847         case PIPE_A:
4848                 return true;
4849         case PIPE_B:
4850                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4851                     pipe_config->fdi_lanes > 2) {
4852                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4853                                       pipe_name(pipe), pipe_config->fdi_lanes);
4854                         return false;
4855                 }
4856                 return true;
4857         case PIPE_C:
4858                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4859                     pipe_B_crtc->config.fdi_lanes <= 2) {
4860                         if (pipe_config->fdi_lanes > 2) {
4861                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4862                                               pipe_name(pipe), pipe_config->fdi_lanes);
4863                                 return false;
4864                         }
4865                 } else {
4866                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4867                         return false;
4868                 }
4869                 return true;
4870         default:
4871                 BUG();
4872         }
4873 }
4874
4875 #define RETRY 1
4876 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4877                                        struct intel_crtc_config *pipe_config)
4878 {
4879         struct drm_device *dev = intel_crtc->base.dev;
4880         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4881         int lane, link_bw, fdi_dotclock;
4882         bool setup_ok, needs_recompute = false;
4883
4884 retry:
4885         /* FDI is a binary signal running at ~2.7GHz, encoding
4886          * each output octet as 10 bits. The actual frequency
4887          * is stored as a divider into a 100MHz clock, and the
4888          * mode pixel clock is stored in units of 1KHz.
4889          * Hence the bw of each lane in terms of the mode signal
4890          * is:
4891          */
4892         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4893
4894         fdi_dotclock = adjusted_mode->crtc_clock;
4895
4896         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4897                                            pipe_config->pipe_bpp);
4898
4899         pipe_config->fdi_lanes = lane;
4900
4901         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4902                                link_bw, &pipe_config->fdi_m_n);
4903
4904         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4905                                             intel_crtc->pipe, pipe_config);
4906         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4907                 pipe_config->pipe_bpp -= 2*3;
4908                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4909                               pipe_config->pipe_bpp);
4910                 needs_recompute = true;
4911                 pipe_config->bw_constrained = true;
4912
4913                 goto retry;
4914         }
4915
4916         if (needs_recompute)
4917                 return RETRY;
4918
4919         return setup_ok ? 0 : -EINVAL;
4920 }
4921
4922 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4923                                    struct intel_crtc_config *pipe_config)
4924 {
4925         pipe_config->ips_enabled = i915.enable_ips &&
4926                                    hsw_crtc_supports_ips(crtc) &&
4927                                    pipe_config->pipe_bpp <= 24;
4928 }
4929
4930 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4931                                      struct intel_crtc_config *pipe_config)
4932 {
4933         struct drm_device *dev = crtc->base.dev;
4934         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4935
4936         /* FIXME should check pixel clock limits on all platforms */
4937         if (INTEL_INFO(dev)->gen < 4) {
4938                 struct drm_i915_private *dev_priv = dev->dev_private;
4939                 int clock_limit =
4940                         dev_priv->display.get_display_clock_speed(dev);
4941
4942                 /*
4943                  * Enable pixel doubling when the dot clock
4944                  * is > 90% of the (display) core speed.
4945                  *
4946                  * GDG double wide on either pipe,
4947                  * otherwise pipe A only.
4948                  */
4949                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4950                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
4951                         clock_limit *= 2;
4952                         pipe_config->double_wide = true;
4953                 }
4954
4955                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
4956                         return -EINVAL;
4957         }
4958
4959         /*
4960          * Pipe horizontal size must be even in:
4961          * - DVO ganged mode
4962          * - LVDS dual channel mode
4963          * - Double wide pipe
4964          */
4965         if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4966              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4967                 pipe_config->pipe_src_w &= ~1;
4968
4969         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4970          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4971          */
4972         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4973                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4974                 return -EINVAL;
4975
4976         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4977                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4978         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4979                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4980                  * for lvds. */
4981                 pipe_config->pipe_bpp = 8*3;
4982         }
4983
4984         if (HAS_IPS(dev))
4985                 hsw_compute_ips_config(crtc, pipe_config);
4986
4987         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4988          * clock survives for now. */
4989         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4990                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4991
4992         if (pipe_config->has_pch_encoder)
4993                 return ironlake_fdi_compute_config(crtc, pipe_config);
4994
4995         return 0;
4996 }
4997
4998 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4999 {
5000         return 400000; /* FIXME */
5001 }
5002
5003 static int i945_get_display_clock_speed(struct drm_device *dev)
5004 {
5005         return 400000;
5006 }
5007
5008 static int i915_get_display_clock_speed(struct drm_device *dev)
5009 {
5010         return 333000;
5011 }
5012
5013 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5014 {
5015         return 200000;
5016 }
5017
5018 static int pnv_get_display_clock_speed(struct drm_device *dev)
5019 {
5020         u16 gcfgc = 0;
5021
5022         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5023
5024         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5025         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5026                 return 267000;
5027         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5028                 return 333000;
5029         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5030                 return 444000;
5031         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5032                 return 200000;
5033         default:
5034                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5035         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5036                 return 133000;
5037         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5038                 return 167000;
5039         }
5040 }
5041
5042 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5043 {
5044         u16 gcfgc = 0;
5045
5046         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5047
5048         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5049                 return 133000;
5050         else {
5051                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5052                 case GC_DISPLAY_CLOCK_333_MHZ:
5053                         return 333000;
5054                 default:
5055                 case GC_DISPLAY_CLOCK_190_200_MHZ:
5056                         return 190000;
5057                 }
5058         }
5059 }
5060
5061 static int i865_get_display_clock_speed(struct drm_device *dev)
5062 {
5063         return 266000;
5064 }
5065
5066 static int i855_get_display_clock_speed(struct drm_device *dev)
5067 {
5068         u16 hpllcc = 0;
5069         /* Assume that the hardware is in the high speed state.  This
5070          * should be the default.
5071          */
5072         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5073         case GC_CLOCK_133_200:
5074         case GC_CLOCK_100_200:
5075                 return 200000;
5076         case GC_CLOCK_166_250:
5077                 return 250000;
5078         case GC_CLOCK_100_133:
5079                 return 133000;
5080         }
5081
5082         /* Shouldn't happen */
5083         return 0;
5084 }
5085
5086 static int i830_get_display_clock_speed(struct drm_device *dev)
5087 {
5088         return 133000;
5089 }
5090
5091 static void
5092 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5093 {
5094         while (*num > DATA_LINK_M_N_MASK ||
5095                *den > DATA_LINK_M_N_MASK) {
5096                 *num >>= 1;
5097                 *den >>= 1;
5098         }
5099 }
5100
5101 static void compute_m_n(unsigned int m, unsigned int n,
5102                         uint32_t *ret_m, uint32_t *ret_n)
5103 {
5104         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5105         *ret_m = div_u64((uint64_t) m * *ret_n, n);
5106         intel_reduce_m_n_ratio(ret_m, ret_n);
5107 }
5108
5109 void
5110 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5111                        int pixel_clock, int link_clock,
5112                        struct intel_link_m_n *m_n)
5113 {
5114         m_n->tu = 64;
5115
5116         compute_m_n(bits_per_pixel * pixel_clock,
5117                     link_clock * nlanes * 8,
5118                     &m_n->gmch_m, &m_n->gmch_n);
5119
5120         compute_m_n(pixel_clock, link_clock,
5121                     &m_n->link_m, &m_n->link_n);
5122 }
5123
5124 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5125 {
5126         if (i915.panel_use_ssc >= 0)
5127                 return i915.panel_use_ssc != 0;
5128         return dev_priv->vbt.lvds_use_ssc
5129                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5130 }
5131
5132 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5133 {
5134         struct drm_device *dev = crtc->dev;
5135         struct drm_i915_private *dev_priv = dev->dev_private;
5136         int refclk;
5137
5138         if (IS_VALLEYVIEW(dev)) {
5139                 refclk = 100000;
5140         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5141             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5142                 refclk = dev_priv->vbt.lvds_ssc_freq;
5143                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5144         } else if (!IS_GEN2(dev)) {
5145                 refclk = 96000;
5146         } else {
5147                 refclk = 48000;
5148         }
5149
5150         return refclk;
5151 }
5152
5153 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5154 {
5155         return (1 << dpll->n) << 16 | dpll->m2;
5156 }
5157
5158 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5159 {
5160         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5161 }
5162
5163 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5164                                      intel_clock_t *reduced_clock)
5165 {
5166         struct drm_device *dev = crtc->base.dev;
5167         struct drm_i915_private *dev_priv = dev->dev_private;
5168         int pipe = crtc->pipe;
5169         u32 fp, fp2 = 0;
5170
5171         if (IS_PINEVIEW(dev)) {
5172                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5173                 if (reduced_clock)
5174                         fp2 = pnv_dpll_compute_fp(reduced_clock);
5175         } else {
5176                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5177                 if (reduced_clock)
5178                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
5179         }
5180
5181         I915_WRITE(FP0(pipe), fp);
5182         crtc->config.dpll_hw_state.fp0 = fp;
5183
5184         crtc->lowfreq_avail = false;
5185         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5186             reduced_clock && i915.powersave) {
5187                 I915_WRITE(FP1(pipe), fp2);
5188                 crtc->config.dpll_hw_state.fp1 = fp2;
5189                 crtc->lowfreq_avail = true;
5190         } else {
5191                 I915_WRITE(FP1(pipe), fp);
5192                 crtc->config.dpll_hw_state.fp1 = fp;
5193         }
5194 }
5195
5196 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5197                 pipe)
5198 {
5199         u32 reg_val;
5200
5201         /*
5202          * PLLB opamp always calibrates to max value of 0x3f, force enable it
5203          * and set it to a reasonable value instead.
5204          */
5205         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5206         reg_val &= 0xffffff00;
5207         reg_val |= 0x00000030;
5208         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5209
5210         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5211         reg_val &= 0x8cffffff;
5212         reg_val = 0x8c000000;
5213         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5214
5215         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5216         reg_val &= 0xffffff00;
5217         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5218
5219         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5220         reg_val &= 0x00ffffff;
5221         reg_val |= 0xb0000000;
5222         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5223 }
5224
5225 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5226                                          struct intel_link_m_n *m_n)
5227 {
5228         struct drm_device *dev = crtc->base.dev;
5229         struct drm_i915_private *dev_priv = dev->dev_private;
5230         int pipe = crtc->pipe;
5231
5232         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5233         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5234         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5235         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5236 }
5237
5238 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5239                                          struct intel_link_m_n *m_n)
5240 {
5241         struct drm_device *dev = crtc->base.dev;
5242         struct drm_i915_private *dev_priv = dev->dev_private;
5243         int pipe = crtc->pipe;
5244         enum transcoder transcoder = crtc->config.cpu_transcoder;
5245
5246         if (INTEL_INFO(dev)->gen >= 5) {
5247                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5248                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5249                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5250                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5251         } else {
5252                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5253                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5254                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5255                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5256         }
5257 }
5258
5259 static void intel_dp_set_m_n(struct intel_crtc *crtc)
5260 {
5261         if (crtc->config.has_pch_encoder)
5262                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5263         else
5264                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5265 }
5266
5267 static void vlv_update_pll(struct intel_crtc *crtc)
5268 {
5269         struct drm_device *dev = crtc->base.dev;
5270         struct drm_i915_private *dev_priv = dev->dev_private;
5271         int pipe = crtc->pipe;
5272         u32 dpll, mdiv;
5273         u32 bestn, bestm1, bestm2, bestp1, bestp2;
5274         u32 coreclk, reg_val, dpll_md;
5275
5276         mutex_lock(&dev_priv->dpio_lock);
5277
5278         bestn = crtc->config.dpll.n;
5279         bestm1 = crtc->config.dpll.m1;
5280         bestm2 = crtc->config.dpll.m2;
5281         bestp1 = crtc->config.dpll.p1;
5282         bestp2 = crtc->config.dpll.p2;
5283
5284         /* See eDP HDMI DPIO driver vbios notes doc */
5285
5286         /* PLL B needs special handling */
5287         if (pipe)
5288                 vlv_pllb_recal_opamp(dev_priv, pipe);
5289
5290         /* Set up Tx target for periodic Rcomp update */
5291         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5292
5293         /* Disable target IRef on PLL */
5294         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5295         reg_val &= 0x00ffffff;
5296         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5297
5298         /* Disable fast lock */
5299         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5300
5301         /* Set idtafcrecal before PLL is enabled */
5302         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5303         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5304         mdiv |= ((bestn << DPIO_N_SHIFT));
5305         mdiv |= (1 << DPIO_K_SHIFT);
5306
5307         /*
5308          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5309          * but we don't support that).
5310          * Note: don't use the DAC post divider as it seems unstable.
5311          */
5312         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5313         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5314
5315         mdiv |= DPIO_ENABLE_CALIBRATION;
5316         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5317
5318         /* Set HBR and RBR LPF coefficients */
5319         if (crtc->config.port_clock == 162000 ||
5320             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5321             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5322                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5323                                  0x009f0003);
5324         else
5325                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5326                                  0x00d0000f);
5327
5328         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5329             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5330                 /* Use SSC source */
5331                 if (!pipe)
5332                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5333                                          0x0df40000);
5334                 else
5335                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5336                                          0x0df70000);
5337         } else { /* HDMI or VGA */
5338                 /* Use bend source */
5339                 if (!pipe)
5340                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5341                                          0x0df70000);
5342                 else
5343                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5344                                          0x0df40000);
5345         }
5346
5347         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5348         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5349         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5350             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5351                 coreclk |= 0x01000000;
5352         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5353
5354         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5355
5356         /*
5357          * Enable DPIO clock input. We should never disable the reference
5358          * clock for pipe B, since VGA hotplug / manual detection depends
5359          * on it.
5360          */
5361         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5362                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5363         /* We should never disable this, set it here for state tracking */
5364         if (pipe == PIPE_B)
5365                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5366         dpll |= DPLL_VCO_ENABLE;
5367         crtc->config.dpll_hw_state.dpll = dpll;
5368
5369         dpll_md = (crtc->config.pixel_multiplier - 1)
5370                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5371         crtc->config.dpll_hw_state.dpll_md = dpll_md;
5372
5373         mutex_unlock(&dev_priv->dpio_lock);
5374 }
5375
5376 static void chv_update_pll(struct intel_crtc *crtc)
5377 {
5378         struct drm_device *dev = crtc->base.dev;
5379         struct drm_i915_private *dev_priv = dev->dev_private;
5380         int pipe = crtc->pipe;
5381         int dpll_reg = DPLL(crtc->pipe);
5382         enum dpio_channel port = vlv_pipe_to_channel(pipe);
5383         u32 val, loopfilter, intcoeff;
5384         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5385         int refclk;
5386
5387         mutex_lock(&dev_priv->dpio_lock);
5388
5389         bestn = crtc->config.dpll.n;
5390         bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5391         bestm1 = crtc->config.dpll.m1;
5392         bestm2 = crtc->config.dpll.m2 >> 22;
5393         bestp1 = crtc->config.dpll.p1;
5394         bestp2 = crtc->config.dpll.p2;
5395
5396         /*
5397          * Enable Refclk and SSC
5398          */
5399         val = I915_READ(dpll_reg);
5400         val |= (DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV);
5401         I915_WRITE(dpll_reg, val);
5402
5403         /* Propagate soft reset to data lane reset */
5404         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(port));
5405         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
5406         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), val);
5407
5408         /* Disable 10bit clock to display controller */
5409         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
5410         val &= ~DPIO_DCLKP_EN;
5411         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
5412
5413         /* p1 and p2 divider */
5414         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5415                         5 << DPIO_CHV_S1_DIV_SHIFT |
5416                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5417                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5418                         1 << DPIO_CHV_K_DIV_SHIFT);
5419
5420         /* Feedback post-divider - m2 */
5421         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5422
5423         /* Feedback refclk divider - n and m1 */
5424         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5425                         DPIO_CHV_M1_DIV_BY_2 |
5426                         1 << DPIO_CHV_N_DIV_SHIFT);
5427
5428         /* M2 fraction division */
5429         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5430
5431         /* M2 fraction division enable */
5432         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5433                        DPIO_CHV_FRAC_DIV_EN |
5434                        (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5435
5436         /* Loop filter */
5437         refclk = i9xx_get_refclk(&crtc->base, 0);
5438         loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5439                 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5440         if (refclk == 100000)
5441                 intcoeff = 11;
5442         else if (refclk == 38400)
5443                 intcoeff = 10;
5444         else
5445                 intcoeff = 9;
5446         loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5447         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5448
5449         /* AFC Recal */
5450         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5451                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5452                         DPIO_AFC_RECAL);
5453
5454         mutex_unlock(&dev_priv->dpio_lock);
5455 }
5456
5457 static void i9xx_update_pll(struct intel_crtc *crtc,
5458                             intel_clock_t *reduced_clock,
5459                             int num_connectors)
5460 {
5461         struct drm_device *dev = crtc->base.dev;
5462         struct drm_i915_private *dev_priv = dev->dev_private;
5463         u32 dpll;
5464         bool is_sdvo;
5465         struct dpll *clock = &crtc->config.dpll;
5466
5467         i9xx_update_pll_dividers(crtc, reduced_clock);
5468
5469         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5470                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5471
5472         dpll = DPLL_VGA_MODE_DIS;
5473
5474         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5475                 dpll |= DPLLB_MODE_LVDS;
5476         else
5477                 dpll |= DPLLB_MODE_DAC_SERIAL;
5478
5479         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5480                 dpll |= (crtc->config.pixel_multiplier - 1)
5481                         << SDVO_MULTIPLIER_SHIFT_HIRES;
5482         }
5483
5484         if (is_sdvo)
5485                 dpll |= DPLL_SDVO_HIGH_SPEED;
5486
5487         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5488                 dpll |= DPLL_SDVO_HIGH_SPEED;
5489
5490         /* compute bitmask from p1 value */
5491         if (IS_PINEVIEW(dev))
5492                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5493         else {
5494                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5495                 if (IS_G4X(dev) && reduced_clock)
5496                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5497         }
5498         switch (clock->p2) {
5499         case 5:
5500                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5501                 break;
5502         case 7:
5503                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5504                 break;
5505         case 10:
5506                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5507                 break;
5508         case 14:
5509                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5510                 break;
5511         }
5512         if (INTEL_INFO(dev)->gen >= 4)
5513                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5514
5515         if (crtc->config.sdvo_tv_clock)
5516                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5517         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5518                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5519                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5520         else
5521                 dpll |= PLL_REF_INPUT_DREFCLK;
5522
5523         dpll |= DPLL_VCO_ENABLE;
5524         crtc->config.dpll_hw_state.dpll = dpll;
5525
5526         if (INTEL_INFO(dev)->gen >= 4) {
5527                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5528                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5529                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5530         }
5531 }
5532
5533 static void i8xx_update_pll(struct intel_crtc *crtc,
5534                             intel_clock_t *reduced_clock,
5535                             int num_connectors)
5536 {
5537         struct drm_device *dev = crtc->base.dev;
5538         struct drm_i915_private *dev_priv = dev->dev_private;
5539         u32 dpll;
5540         struct dpll *clock = &crtc->config.dpll;
5541
5542         i9xx_update_pll_dividers(crtc, reduced_clock);
5543
5544         dpll = DPLL_VGA_MODE_DIS;
5545
5546         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5547                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5548         } else {
5549                 if (clock->p1 == 2)
5550                         dpll |= PLL_P1_DIVIDE_BY_TWO;
5551                 else
5552                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5553                 if (clock->p2 == 4)
5554                         dpll |= PLL_P2_DIVIDE_BY_4;
5555         }
5556
5557         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5558                 dpll |= DPLL_DVO_2X_MODE;
5559
5560         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5561                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5562                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5563         else
5564                 dpll |= PLL_REF_INPUT_DREFCLK;
5565
5566         dpll |= DPLL_VCO_ENABLE;
5567         crtc->config.dpll_hw_state.dpll = dpll;
5568 }
5569
5570 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5571 {
5572         struct drm_device *dev = intel_crtc->base.dev;
5573         struct drm_i915_private *dev_priv = dev->dev_private;
5574         enum pipe pipe = intel_crtc->pipe;
5575         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5576         struct drm_display_mode *adjusted_mode =
5577                 &intel_crtc->config.adjusted_mode;
5578         uint32_t crtc_vtotal, crtc_vblank_end;
5579         int vsyncshift = 0;
5580
5581         /* We need to be careful not to changed the adjusted mode, for otherwise
5582          * the hw state checker will get angry at the mismatch. */
5583         crtc_vtotal = adjusted_mode->crtc_vtotal;
5584         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5585
5586         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5587                 /* the chip adds 2 halflines automatically */
5588                 crtc_vtotal -= 1;
5589                 crtc_vblank_end -= 1;
5590
5591                 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5592                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5593                 else
5594                         vsyncshift = adjusted_mode->crtc_hsync_start -
5595                                 adjusted_mode->crtc_htotal / 2;
5596                 if (vsyncshift < 0)
5597                         vsyncshift += adjusted_mode->crtc_htotal;
5598         }
5599
5600         if (INTEL_INFO(dev)->gen > 3)
5601                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5602
5603         I915_WRITE(HTOTAL(cpu_transcoder),
5604                    (adjusted_mode->crtc_hdisplay - 1) |
5605                    ((adjusted_mode->crtc_htotal - 1) << 16));
5606         I915_WRITE(HBLANK(cpu_transcoder),
5607                    (adjusted_mode->crtc_hblank_start - 1) |
5608                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5609         I915_WRITE(HSYNC(cpu_transcoder),
5610                    (adjusted_mode->crtc_hsync_start - 1) |
5611                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5612
5613         I915_WRITE(VTOTAL(cpu_transcoder),
5614                    (adjusted_mode->crtc_vdisplay - 1) |
5615                    ((crtc_vtotal - 1) << 16));
5616         I915_WRITE(VBLANK(cpu_transcoder),
5617                    (adjusted_mode->crtc_vblank_start - 1) |
5618                    ((crtc_vblank_end - 1) << 16));
5619         I915_WRITE(VSYNC(cpu_transcoder),
5620                    (adjusted_mode->crtc_vsync_start - 1) |
5621                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5622
5623         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5624          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5625          * documented on the DDI_FUNC_CTL register description, EDP Input Select
5626          * bits. */
5627         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5628             (pipe == PIPE_B || pipe == PIPE_C))
5629                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5630
5631         /* pipesrc controls the size that is scaled from, which should
5632          * always be the user's requested size.
5633          */
5634         I915_WRITE(PIPESRC(pipe),
5635                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
5636                    (intel_crtc->config.pipe_src_h - 1));
5637 }
5638
5639 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5640                                    struct intel_crtc_config *pipe_config)
5641 {
5642         struct drm_device *dev = crtc->base.dev;
5643         struct drm_i915_private *dev_priv = dev->dev_private;
5644         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5645         uint32_t tmp;
5646
5647         tmp = I915_READ(HTOTAL(cpu_transcoder));
5648         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5649         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5650         tmp = I915_READ(HBLANK(cpu_transcoder));
5651         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5652         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5653         tmp = I915_READ(HSYNC(cpu_transcoder));
5654         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5655         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5656
5657         tmp = I915_READ(VTOTAL(cpu_transcoder));
5658         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5659         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5660         tmp = I915_READ(VBLANK(cpu_transcoder));
5661         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5662         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5663         tmp = I915_READ(VSYNC(cpu_transcoder));
5664         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5665         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5666
5667         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5668                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5669                 pipe_config->adjusted_mode.crtc_vtotal += 1;
5670                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5671         }
5672
5673         tmp = I915_READ(PIPESRC(crtc->pipe));
5674         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5675         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5676
5677         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5678         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5679 }
5680
5681 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5682                                  struct intel_crtc_config *pipe_config)
5683 {
5684         mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5685         mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5686         mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5687         mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5688
5689         mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5690         mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5691         mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5692         mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5693
5694         mode->flags = pipe_config->adjusted_mode.flags;
5695
5696         mode->clock = pipe_config->adjusted_mode.crtc_clock;
5697         mode->flags |= pipe_config->adjusted_mode.flags;
5698 }
5699
5700 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5701 {
5702         struct drm_device *dev = intel_crtc->base.dev;
5703         struct drm_i915_private *dev_priv = dev->dev_private;
5704         uint32_t pipeconf;
5705
5706         pipeconf = 0;
5707
5708         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5709             I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5710                 pipeconf |= PIPECONF_ENABLE;
5711
5712         if (intel_crtc->config.double_wide)
5713                 pipeconf |= PIPECONF_DOUBLE_WIDE;
5714
5715         /* only g4x and later have fancy bpc/dither controls */
5716         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5717                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5718                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5719                         pipeconf |= PIPECONF_DITHER_EN |
5720                                     PIPECONF_DITHER_TYPE_SP;
5721
5722                 switch (intel_crtc->config.pipe_bpp) {
5723                 case 18:
5724                         pipeconf |= PIPECONF_6BPC;
5725                         break;
5726                 case 24:
5727                         pipeconf |= PIPECONF_8BPC;
5728                         break;
5729                 case 30:
5730                         pipeconf |= PIPECONF_10BPC;
5731                         break;
5732                 default:
5733                         /* Case prevented by intel_choose_pipe_bpp_dither. */
5734                         BUG();
5735                 }
5736         }
5737
5738         if (HAS_PIPE_CXSR(dev)) {
5739                 if (intel_crtc->lowfreq_avail) {
5740                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5741                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5742                 } else {
5743                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5744                 }
5745         }
5746
5747         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
5748                 if (INTEL_INFO(dev)->gen < 4 ||
5749                     intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5750                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5751                 else
5752                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
5753         } else
5754                 pipeconf |= PIPECONF_PROGRESSIVE;
5755
5756         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5757                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5758
5759         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5760         POSTING_READ(PIPECONF(intel_crtc->pipe));
5761 }
5762
5763 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5764                               int x, int y,
5765                               struct drm_framebuffer *fb)
5766 {
5767         struct drm_device *dev = crtc->dev;
5768         struct drm_i915_private *dev_priv = dev->dev_private;
5769         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5770         int pipe = intel_crtc->pipe;
5771         int plane = intel_crtc->plane;
5772         int refclk, num_connectors = 0;
5773         intel_clock_t clock, reduced_clock;
5774         u32 dspcntr;
5775         bool ok, has_reduced_clock = false;
5776         bool is_lvds = false, is_dsi = false;
5777         struct intel_encoder *encoder;
5778         const intel_limit_t *limit;
5779         int ret;
5780
5781         for_each_encoder_on_crtc(dev, crtc, encoder) {
5782                 switch (encoder->type) {
5783                 case INTEL_OUTPUT_LVDS:
5784                         is_lvds = true;
5785                         break;
5786                 case INTEL_OUTPUT_DSI:
5787                         is_dsi = true;
5788                         break;
5789                 }
5790
5791                 num_connectors++;
5792         }
5793
5794         if (is_dsi)
5795                 goto skip_dpll;
5796
5797         if (!intel_crtc->config.clock_set) {
5798                 refclk = i9xx_get_refclk(crtc, num_connectors);
5799
5800                 /*
5801                  * Returns a set of divisors for the desired target clock with
5802                  * the given refclk, or FALSE.  The returned values represent
5803                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5804                  * 2) / p1 / p2.
5805                  */
5806                 limit = intel_limit(crtc, refclk);
5807                 ok = dev_priv->display.find_dpll(limit, crtc,
5808                                                  intel_crtc->config.port_clock,
5809                                                  refclk, NULL, &clock);
5810                 if (!ok) {
5811                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5812                         return -EINVAL;
5813                 }
5814
5815                 if (is_lvds && dev_priv->lvds_downclock_avail) {
5816                         /*
5817                          * Ensure we match the reduced clock's P to the target
5818                          * clock.  If the clocks don't match, we can't switch
5819                          * the display clock by using the FP0/FP1. In such case
5820                          * we will disable the LVDS downclock feature.
5821                          */
5822                         has_reduced_clock =
5823                                 dev_priv->display.find_dpll(limit, crtc,
5824                                                             dev_priv->lvds_downclock,
5825                                                             refclk, &clock,
5826                                                             &reduced_clock);
5827                 }
5828                 /* Compat-code for transition, will disappear. */
5829                 intel_crtc->config.dpll.n = clock.n;
5830                 intel_crtc->config.dpll.m1 = clock.m1;
5831                 intel_crtc->config.dpll.m2 = clock.m2;
5832                 intel_crtc->config.dpll.p1 = clock.p1;
5833                 intel_crtc->config.dpll.p2 = clock.p2;
5834         }
5835
5836         if (IS_GEN2(dev)) {
5837                 i8xx_update_pll(intel_crtc,
5838                                 has_reduced_clock ? &reduced_clock : NULL,
5839                                 num_connectors);
5840         } else if (IS_CHERRYVIEW(dev)) {
5841                 chv_update_pll(intel_crtc);
5842         } else if (IS_VALLEYVIEW(dev)) {
5843                 vlv_update_pll(intel_crtc);
5844         } else {
5845                 i9xx_update_pll(intel_crtc,
5846                                 has_reduced_clock ? &reduced_clock : NULL,
5847                                 num_connectors);
5848         }
5849
5850 skip_dpll:
5851         /* Set up the display plane register */
5852         dspcntr = DISPPLANE_GAMMA_ENABLE;
5853
5854         if (!IS_VALLEYVIEW(dev)) {
5855                 if (pipe == 0)
5856                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5857                 else
5858                         dspcntr |= DISPPLANE_SEL_PIPE_B;
5859         }
5860
5861         if (intel_crtc->config.has_dp_encoder)
5862                 intel_dp_set_m_n(intel_crtc);
5863
5864         intel_set_pipe_timings(intel_crtc);
5865
5866         /* pipesrc and dspsize control the size that is scaled from,
5867          * which should always be the user's requested size.
5868          */
5869         I915_WRITE(DSPSIZE(plane),
5870                    ((intel_crtc->config.pipe_src_h - 1) << 16) |
5871                    (intel_crtc->config.pipe_src_w - 1));
5872         I915_WRITE(DSPPOS(plane), 0);
5873
5874         i9xx_set_pipeconf(intel_crtc);
5875
5876         I915_WRITE(DSPCNTR(plane), dspcntr);
5877         POSTING_READ(DSPCNTR(plane));
5878
5879         ret = intel_pipe_set_base(crtc, x, y, fb);
5880
5881         return ret;
5882 }
5883
5884 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5885                                  struct intel_crtc_config *pipe_config)
5886 {
5887         struct drm_device *dev = crtc->base.dev;
5888         struct drm_i915_private *dev_priv = dev->dev_private;
5889         uint32_t tmp;
5890
5891         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
5892                 return;
5893
5894         tmp = I915_READ(PFIT_CONTROL);
5895         if (!(tmp & PFIT_ENABLE))
5896                 return;
5897
5898         /* Check whether the pfit is attached to our pipe. */
5899         if (INTEL_INFO(dev)->gen < 4) {
5900                 if (crtc->pipe != PIPE_B)
5901                         return;
5902         } else {
5903                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5904                         return;
5905         }
5906
5907         pipe_config->gmch_pfit.control = tmp;
5908         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5909         if (INTEL_INFO(dev)->gen < 5)
5910                 pipe_config->gmch_pfit.lvds_border_bits =
5911                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5912 }
5913
5914 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5915                                struct intel_crtc_config *pipe_config)
5916 {
5917         struct drm_device *dev = crtc->base.dev;
5918         struct drm_i915_private *dev_priv = dev->dev_private;
5919         int pipe = pipe_config->cpu_transcoder;
5920         intel_clock_t clock;
5921         u32 mdiv;
5922         int refclk = 100000;
5923
5924         mutex_lock(&dev_priv->dpio_lock);
5925         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
5926         mutex_unlock(&dev_priv->dpio_lock);
5927
5928         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5929         clock.m2 = mdiv & DPIO_M2DIV_MASK;
5930         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5931         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5932         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5933
5934         vlv_clock(refclk, &clock);
5935
5936         /* clock.dot is the fast clock */
5937         pipe_config->port_clock = clock.dot / 5;
5938 }
5939
5940 static void i9xx_get_plane_config(struct intel_crtc *crtc,
5941                                   struct intel_plane_config *plane_config)
5942 {
5943         struct drm_device *dev = crtc->base.dev;
5944         struct drm_i915_private *dev_priv = dev->dev_private;
5945         u32 val, base, offset;
5946         int pipe = crtc->pipe, plane = crtc->plane;
5947         int fourcc, pixel_format;
5948         int aligned_height;
5949
5950         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
5951         if (!crtc->base.primary->fb) {
5952                 DRM_DEBUG_KMS("failed to alloc fb\n");
5953                 return;
5954         }
5955
5956         val = I915_READ(DSPCNTR(plane));
5957
5958         if (INTEL_INFO(dev)->gen >= 4)
5959                 if (val & DISPPLANE_TILED)
5960                         plane_config->tiled = true;
5961
5962         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
5963         fourcc = intel_format_to_fourcc(pixel_format);
5964         crtc->base.primary->fb->pixel_format = fourcc;
5965         crtc->base.primary->fb->bits_per_pixel =
5966                 drm_format_plane_cpp(fourcc, 0) * 8;
5967
5968         if (INTEL_INFO(dev)->gen >= 4) {
5969                 if (plane_config->tiled)
5970                         offset = I915_READ(DSPTILEOFF(plane));
5971                 else
5972                         offset = I915_READ(DSPLINOFF(plane));
5973                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
5974         } else {
5975                 base = I915_READ(DSPADDR(plane));
5976         }
5977         plane_config->base = base;
5978
5979         val = I915_READ(PIPESRC(pipe));
5980         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
5981         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
5982
5983         val = I915_READ(DSPSTRIDE(pipe));
5984         crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
5985
5986         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
5987                                             plane_config->tiled);
5988
5989         plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
5990                                    aligned_height, PAGE_SIZE);
5991
5992         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
5993                       pipe, plane, crtc->base.primary->fb->width,
5994                       crtc->base.primary->fb->height,
5995                       crtc->base.primary->fb->bits_per_pixel, base,
5996                       crtc->base.primary->fb->pitches[0],
5997                       plane_config->size);
5998
5999 }
6000
6001 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6002                                struct intel_crtc_config *pipe_config)
6003 {
6004         struct drm_device *dev = crtc->base.dev;
6005         struct drm_i915_private *dev_priv = dev->dev_private;
6006         int pipe = pipe_config->cpu_transcoder;
6007         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6008         intel_clock_t clock;
6009         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6010         int refclk = 100000;
6011
6012         mutex_lock(&dev_priv->dpio_lock);
6013         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6014         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6015         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6016         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6017         mutex_unlock(&dev_priv->dpio_lock);
6018
6019         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6020         clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6021         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6022         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6023         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6024
6025         chv_clock(refclk, &clock);
6026
6027         /* clock.dot is the fast clock */
6028         pipe_config->port_clock = clock.dot / 5;
6029 }
6030
6031 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6032                                  struct intel_crtc_config *pipe_config)
6033 {
6034         struct drm_device *dev = crtc->base.dev;
6035         struct drm_i915_private *dev_priv = dev->dev_private;
6036         uint32_t tmp;
6037
6038         if (!intel_display_power_enabled(dev_priv,
6039                                          POWER_DOMAIN_PIPE(crtc->pipe)))
6040                 return false;
6041
6042         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6043         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6044
6045         tmp = I915_READ(PIPECONF(crtc->pipe));
6046         if (!(tmp & PIPECONF_ENABLE))
6047                 return false;
6048
6049         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6050                 switch (tmp & PIPECONF_BPC_MASK) {
6051                 case PIPECONF_6BPC:
6052                         pipe_config->pipe_bpp = 18;
6053                         break;
6054                 case PIPECONF_8BPC:
6055                         pipe_config->pipe_bpp = 24;
6056                         break;
6057                 case PIPECONF_10BPC:
6058                         pipe_config->pipe_bpp = 30;
6059                         break;
6060                 default:
6061                         break;
6062                 }
6063         }
6064
6065         if (INTEL_INFO(dev)->gen < 4)
6066                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6067
6068         intel_get_pipe_timings(crtc, pipe_config);
6069
6070         i9xx_get_pfit_config(crtc, pipe_config);
6071
6072         if (INTEL_INFO(dev)->gen >= 4) {
6073                 tmp = I915_READ(DPLL_MD(crtc->pipe));
6074                 pipe_config->pixel_multiplier =
6075                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6076                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6077                 pipe_config->dpll_hw_state.dpll_md = tmp;
6078         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6079                 tmp = I915_READ(DPLL(crtc->pipe));
6080                 pipe_config->pixel_multiplier =
6081                         ((tmp & SDVO_MULTIPLIER_MASK)
6082                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6083         } else {
6084                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6085                  * port and will be fixed up in the encoder->get_config
6086                  * function. */
6087                 pipe_config->pixel_multiplier = 1;
6088         }
6089         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6090         if (!IS_VALLEYVIEW(dev)) {
6091                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6092                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6093         } else {
6094                 /* Mask out read-only status bits. */
6095                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6096                                                      DPLL_PORTC_READY_MASK |
6097                                                      DPLL_PORTB_READY_MASK);
6098         }
6099
6100         if (IS_CHERRYVIEW(dev))
6101                 chv_crtc_clock_get(crtc, pipe_config);
6102         else if (IS_VALLEYVIEW(dev))
6103                 vlv_crtc_clock_get(crtc, pipe_config);
6104         else
6105                 i9xx_crtc_clock_get(crtc, pipe_config);
6106
6107         return true;
6108 }
6109
6110 static void ironlake_init_pch_refclk(struct drm_device *dev)
6111 {
6112         struct drm_i915_private *dev_priv = dev->dev_private;
6113         struct drm_mode_config *mode_config = &dev->mode_config;
6114         struct intel_encoder *encoder;
6115         u32 val, final;
6116         bool has_lvds = false;
6117         bool has_cpu_edp = false;
6118         bool has_panel = false;
6119         bool has_ck505 = false;
6120         bool can_ssc = false;
6121
6122         /* We need to take the global config into account */
6123         list_for_each_entry(encoder, &mode_config->encoder_list,
6124                             base.head) {
6125                 switch (encoder->type) {
6126                 case INTEL_OUTPUT_LVDS:
6127                         has_panel = true;
6128                         has_lvds = true;
6129                         break;
6130                 case INTEL_OUTPUT_EDP:
6131                         has_panel = true;
6132                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6133                                 has_cpu_edp = true;
6134                         break;
6135                 }
6136         }
6137
6138         if (HAS_PCH_IBX(dev)) {
6139                 has_ck505 = dev_priv->vbt.display_clock_mode;
6140                 can_ssc = has_ck505;
6141         } else {
6142                 has_ck505 = false;
6143                 can_ssc = true;
6144         }
6145
6146         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6147                       has_panel, has_lvds, has_ck505);
6148
6149         /* Ironlake: try to setup display ref clock before DPLL
6150          * enabling. This is only under driver's control after
6151          * PCH B stepping, previous chipset stepping should be
6152          * ignoring this setting.
6153          */
6154         val = I915_READ(PCH_DREF_CONTROL);
6155
6156         /* As we must carefully and slowly disable/enable each source in turn,
6157          * compute the final state we want first and check if we need to
6158          * make any changes at all.
6159          */
6160         final = val;
6161         final &= ~DREF_NONSPREAD_SOURCE_MASK;
6162         if (has_ck505)
6163                 final |= DREF_NONSPREAD_CK505_ENABLE;
6164         else
6165                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6166
6167         final &= ~DREF_SSC_SOURCE_MASK;
6168         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6169         final &= ~DREF_SSC1_ENABLE;
6170
6171         if (has_panel) {
6172                 final |= DREF_SSC_SOURCE_ENABLE;
6173
6174                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6175                         final |= DREF_SSC1_ENABLE;
6176
6177                 if (has_cpu_edp) {
6178                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
6179                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6180                         else
6181                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6182                 } else
6183                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6184         } else {
6185                 final |= DREF_SSC_SOURCE_DISABLE;
6186                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6187         }
6188
6189         if (final == val)
6190                 return;
6191
6192         /* Always enable nonspread source */
6193         val &= ~DREF_NONSPREAD_SOURCE_MASK;
6194
6195         if (has_ck505)
6196                 val |= DREF_NONSPREAD_CK505_ENABLE;
6197         else
6198                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6199
6200         if (has_panel) {
6201                 val &= ~DREF_SSC_SOURCE_MASK;
6202                 val |= DREF_SSC_SOURCE_ENABLE;
6203
6204                 /* SSC must be turned on before enabling the CPU output  */
6205                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6206                         DRM_DEBUG_KMS("Using SSC on panel\n");
6207                         val |= DREF_SSC1_ENABLE;
6208                 } else
6209                         val &= ~DREF_SSC1_ENABLE;
6210
6211                 /* Get SSC going before enabling the outputs */
6212                 I915_WRITE(PCH_DREF_CONTROL, val);
6213                 POSTING_READ(PCH_DREF_CONTROL);
6214                 udelay(200);
6215
6216                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6217
6218                 /* Enable CPU source on CPU attached eDP */
6219                 if (has_cpu_edp) {
6220                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6221                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
6222                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6223                         }
6224                         else
6225                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6226                 } else
6227                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6228
6229                 I915_WRITE(PCH_DREF_CONTROL, val);
6230                 POSTING_READ(PCH_DREF_CONTROL);
6231                 udelay(200);
6232         } else {
6233                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6234
6235                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6236
6237                 /* Turn off CPU output */
6238                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6239
6240                 I915_WRITE(PCH_DREF_CONTROL, val);
6241                 POSTING_READ(PCH_DREF_CONTROL);
6242                 udelay(200);
6243
6244                 /* Turn off the SSC source */
6245                 val &= ~DREF_SSC_SOURCE_MASK;
6246                 val |= DREF_SSC_SOURCE_DISABLE;
6247
6248                 /* Turn off SSC1 */
6249                 val &= ~DREF_SSC1_ENABLE;
6250
6251                 I915_WRITE(PCH_DREF_CONTROL, val);
6252                 POSTING_READ(PCH_DREF_CONTROL);
6253                 udelay(200);
6254         }
6255
6256         BUG_ON(val != final);
6257 }
6258
6259 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6260 {
6261         uint32_t tmp;
6262
6263         tmp = I915_READ(SOUTH_CHICKEN2);
6264         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6265         I915_WRITE(SOUTH_CHICKEN2, tmp);
6266
6267         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6268                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6269                 DRM_ERROR("FDI mPHY reset assert timeout\n");
6270
6271         tmp = I915_READ(SOUTH_CHICKEN2);
6272         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6273         I915_WRITE(SOUTH_CHICKEN2, tmp);
6274
6275         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6276                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6277                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6278 }
6279
6280 /* WaMPhyProgramming:hsw */
6281 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6282 {
6283         uint32_t tmp;
6284
6285         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6286         tmp &= ~(0xFF << 24);
6287         tmp |= (0x12 << 24);
6288         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6289
6290         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6291         tmp |= (1 << 11);
6292         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6293
6294         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6295         tmp |= (1 << 11);
6296         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6297
6298         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6299         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6300         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6301
6302         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6303         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6304         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6305
6306         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6307         tmp &= ~(7 << 13);
6308         tmp |= (5 << 13);
6309         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6310
6311         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6312         tmp &= ~(7 << 13);
6313         tmp |= (5 << 13);
6314         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6315
6316         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6317         tmp &= ~0xFF;
6318         tmp |= 0x1C;
6319         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6320
6321         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6322         tmp &= ~0xFF;
6323         tmp |= 0x1C;
6324         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6325
6326         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6327         tmp &= ~(0xFF << 16);
6328         tmp |= (0x1C << 16);
6329         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6330
6331         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6332         tmp &= ~(0xFF << 16);
6333         tmp |= (0x1C << 16);
6334         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6335
6336         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6337         tmp |= (1 << 27);
6338         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6339
6340         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6341         tmp |= (1 << 27);
6342         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6343
6344         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6345         tmp &= ~(0xF << 28);
6346         tmp |= (4 << 28);
6347         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6348
6349         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6350         tmp &= ~(0xF << 28);
6351         tmp |= (4 << 28);
6352         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6353 }
6354
6355 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6356  * Programming" based on the parameters passed:
6357  * - Sequence to enable CLKOUT_DP
6358  * - Sequence to enable CLKOUT_DP without spread
6359  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6360  */
6361 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6362                                  bool with_fdi)
6363 {
6364         struct drm_i915_private *dev_priv = dev->dev_private;
6365         uint32_t reg, tmp;
6366
6367         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6368                 with_spread = true;
6369         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6370                  with_fdi, "LP PCH doesn't have FDI\n"))
6371                 with_fdi = false;
6372
6373         mutex_lock(&dev_priv->dpio_lock);
6374
6375         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6376         tmp &= ~SBI_SSCCTL_DISABLE;
6377         tmp |= SBI_SSCCTL_PATHALT;
6378         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6379
6380         udelay(24);
6381
6382         if (with_spread) {
6383                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6384                 tmp &= ~SBI_SSCCTL_PATHALT;
6385                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6386
6387                 if (with_fdi) {
6388                         lpt_reset_fdi_mphy(dev_priv);
6389                         lpt_program_fdi_mphy(dev_priv);
6390                 }
6391         }
6392
6393         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6394                SBI_GEN0 : SBI_DBUFF0;
6395         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6396         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6397         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6398
6399         mutex_unlock(&dev_priv->dpio_lock);
6400 }
6401
6402 /* Sequence to disable CLKOUT_DP */
6403 static void lpt_disable_clkout_dp(struct drm_device *dev)
6404 {
6405         struct drm_i915_private *dev_priv = dev->dev_private;
6406         uint32_t reg, tmp;
6407
6408         mutex_lock(&dev_priv->dpio_lock);
6409
6410         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6411                SBI_GEN0 : SBI_DBUFF0;
6412         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6413         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6414         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6415
6416         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6417         if (!(tmp & SBI_SSCCTL_DISABLE)) {
6418                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6419                         tmp |= SBI_SSCCTL_PATHALT;
6420                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6421                         udelay(32);
6422                 }
6423                 tmp |= SBI_SSCCTL_DISABLE;
6424                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6425         }
6426
6427         mutex_unlock(&dev_priv->dpio_lock);
6428 }
6429
6430 static void lpt_init_pch_refclk(struct drm_device *dev)
6431 {
6432         struct drm_mode_config *mode_config = &dev->mode_config;
6433         struct intel_encoder *encoder;
6434         bool has_vga = false;
6435
6436         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
6437                 switch (encoder->type) {
6438                 case INTEL_OUTPUT_ANALOG:
6439                         has_vga = true;
6440                         break;
6441                 }
6442         }
6443
6444         if (has_vga)
6445                 lpt_enable_clkout_dp(dev, true, true);
6446         else
6447                 lpt_disable_clkout_dp(dev);
6448 }
6449
6450 /*
6451  * Initialize reference clocks when the driver loads
6452  */
6453 void intel_init_pch_refclk(struct drm_device *dev)
6454 {
6455         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6456                 ironlake_init_pch_refclk(dev);
6457         else if (HAS_PCH_LPT(dev))
6458                 lpt_init_pch_refclk(dev);
6459 }
6460
6461 static int ironlake_get_refclk(struct drm_crtc *crtc)
6462 {
6463         struct drm_device *dev = crtc->dev;
6464         struct drm_i915_private *dev_priv = dev->dev_private;
6465         struct intel_encoder *encoder;
6466         int num_connectors = 0;
6467         bool is_lvds = false;
6468
6469         for_each_encoder_on_crtc(dev, crtc, encoder) {
6470                 switch (encoder->type) {
6471                 case INTEL_OUTPUT_LVDS:
6472                         is_lvds = true;
6473                         break;
6474                 }
6475                 num_connectors++;
6476         }
6477
6478         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6479                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6480                               dev_priv->vbt.lvds_ssc_freq);
6481                 return dev_priv->vbt.lvds_ssc_freq;
6482         }
6483
6484         return 120000;
6485 }
6486
6487 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6488 {
6489         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6490         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6491         int pipe = intel_crtc->pipe;
6492         uint32_t val;
6493
6494         val = 0;
6495
6496         switch (intel_crtc->config.pipe_bpp) {
6497         case 18:
6498                 val |= PIPECONF_6BPC;
6499                 break;
6500         case 24:
6501                 val |= PIPECONF_8BPC;
6502                 break;
6503         case 30:
6504                 val |= PIPECONF_10BPC;
6505                 break;
6506         case 36:
6507                 val |= PIPECONF_12BPC;
6508                 break;
6509         default:
6510                 /* Case prevented by intel_choose_pipe_bpp_dither. */
6511                 BUG();
6512         }
6513
6514         if (intel_crtc->config.dither)
6515                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6516
6517         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6518                 val |= PIPECONF_INTERLACED_ILK;
6519         else
6520                 val |= PIPECONF_PROGRESSIVE;
6521
6522         if (intel_crtc->config.limited_color_range)
6523                 val |= PIPECONF_COLOR_RANGE_SELECT;
6524
6525         I915_WRITE(PIPECONF(pipe), val);
6526         POSTING_READ(PIPECONF(pipe));
6527 }
6528
6529 /*
6530  * Set up the pipe CSC unit.
6531  *
6532  * Currently only full range RGB to limited range RGB conversion
6533  * is supported, but eventually this should handle various
6534  * RGB<->YCbCr scenarios as well.
6535  */
6536 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6537 {
6538         struct drm_device *dev = crtc->dev;
6539         struct drm_i915_private *dev_priv = dev->dev_private;
6540         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6541         int pipe = intel_crtc->pipe;
6542         uint16_t coeff = 0x7800; /* 1.0 */
6543
6544         /*
6545          * TODO: Check what kind of values actually come out of the pipe
6546          * with these coeff/postoff values and adjust to get the best
6547          * accuracy. Perhaps we even need to take the bpc value into
6548          * consideration.
6549          */
6550
6551         if (intel_crtc->config.limited_color_range)
6552                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6553
6554         /*
6555          * GY/GU and RY/RU should be the other way around according
6556          * to BSpec, but reality doesn't agree. Just set them up in
6557          * a way that results in the correct picture.
6558          */
6559         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6560         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6561
6562         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6563         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6564
6565         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6566         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6567
6568         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6569         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6570         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6571
6572         if (INTEL_INFO(dev)->gen > 6) {
6573                 uint16_t postoff = 0;
6574
6575                 if (intel_crtc->config.limited_color_range)
6576                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
6577
6578                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6579                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6580                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6581
6582                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6583         } else {
6584                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6585
6586                 if (intel_crtc->config.limited_color_range)
6587                         mode |= CSC_BLACK_SCREEN_OFFSET;
6588
6589                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6590         }
6591 }
6592
6593 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6594 {
6595         struct drm_device *dev = crtc->dev;
6596         struct drm_i915_private *dev_priv = dev->dev_private;
6597         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6598         enum pipe pipe = intel_crtc->pipe;
6599         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6600         uint32_t val;
6601
6602         val = 0;
6603
6604         if (IS_HASWELL(dev) && intel_crtc->config.dither)
6605                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6606
6607         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6608                 val |= PIPECONF_INTERLACED_ILK;
6609         else
6610                 val |= PIPECONF_PROGRESSIVE;
6611
6612         I915_WRITE(PIPECONF(cpu_transcoder), val);
6613         POSTING_READ(PIPECONF(cpu_transcoder));
6614
6615         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6616         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6617
6618         if (IS_BROADWELL(dev)) {
6619                 val = 0;
6620
6621                 switch (intel_crtc->config.pipe_bpp) {
6622                 case 18:
6623                         val |= PIPEMISC_DITHER_6_BPC;
6624                         break;
6625                 case 24:
6626                         val |= PIPEMISC_DITHER_8_BPC;
6627                         break;
6628                 case 30:
6629                         val |= PIPEMISC_DITHER_10_BPC;
6630                         break;
6631                 case 36:
6632                         val |= PIPEMISC_DITHER_12_BPC;
6633                         break;
6634                 default:
6635                         /* Case prevented by pipe_config_set_bpp. */
6636                         BUG();
6637                 }
6638
6639                 if (intel_crtc->config.dither)
6640                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6641
6642                 I915_WRITE(PIPEMISC(pipe), val);
6643         }
6644 }
6645
6646 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6647                                     intel_clock_t *clock,
6648                                     bool *has_reduced_clock,
6649                                     intel_clock_t *reduced_clock)
6650 {
6651         struct drm_device *dev = crtc->dev;
6652         struct drm_i915_private *dev_priv = dev->dev_private;
6653         struct intel_encoder *intel_encoder;
6654         int refclk;
6655         const intel_limit_t *limit;
6656         bool ret, is_lvds = false;
6657
6658         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6659                 switch (intel_encoder->type) {
6660                 case INTEL_OUTPUT_LVDS:
6661                         is_lvds = true;
6662                         break;
6663                 }
6664         }
6665
6666         refclk = ironlake_get_refclk(crtc);
6667
6668         /*
6669          * Returns a set of divisors for the desired target clock with the given
6670          * refclk, or FALSE.  The returned values represent the clock equation:
6671          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6672          */
6673         limit = intel_limit(crtc, refclk);
6674         ret = dev_priv->display.find_dpll(limit, crtc,
6675                                           to_intel_crtc(crtc)->config.port_clock,
6676                                           refclk, NULL, clock);
6677         if (!ret)
6678                 return false;
6679
6680         if (is_lvds && dev_priv->lvds_downclock_avail) {
6681                 /*
6682                  * Ensure we match the reduced clock's P to the target clock.
6683                  * If the clocks don't match, we can't switch the display clock
6684                  * by using the FP0/FP1. In such case we will disable the LVDS
6685                  * downclock feature.
6686                 */
6687                 *has_reduced_clock =
6688                         dev_priv->display.find_dpll(limit, crtc,
6689                                                     dev_priv->lvds_downclock,
6690                                                     refclk, clock,
6691                                                     reduced_clock);
6692         }
6693
6694         return true;
6695 }
6696
6697 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6698 {
6699         /*
6700          * Account for spread spectrum to avoid
6701          * oversubscribing the link. Max center spread
6702          * is 2.5%; use 5% for safety's sake.
6703          */
6704         u32 bps = target_clock * bpp * 21 / 20;
6705         return DIV_ROUND_UP(bps, link_bw * 8);
6706 }
6707
6708 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6709 {
6710         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6711 }
6712
6713 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6714                                       u32 *fp,
6715                                       intel_clock_t *reduced_clock, u32 *fp2)
6716 {
6717         struct drm_crtc *crtc = &intel_crtc->base;
6718         struct drm_device *dev = crtc->dev;
6719         struct drm_i915_private *dev_priv = dev->dev_private;
6720         struct intel_encoder *intel_encoder;
6721         uint32_t dpll;
6722         int factor, num_connectors = 0;
6723         bool is_lvds = false, is_sdvo = false;
6724
6725         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6726                 switch (intel_encoder->type) {
6727                 case INTEL_OUTPUT_LVDS:
6728                         is_lvds = true;
6729                         break;
6730                 case INTEL_OUTPUT_SDVO:
6731                 case INTEL_OUTPUT_HDMI:
6732                         is_sdvo = true;
6733                         break;
6734                 }
6735
6736                 num_connectors++;
6737         }
6738
6739         /* Enable autotuning of the PLL clock (if permissible) */
6740         factor = 21;
6741         if (is_lvds) {
6742                 if ((intel_panel_use_ssc(dev_priv) &&
6743                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
6744                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6745                         factor = 25;
6746         } else if (intel_crtc->config.sdvo_tv_clock)
6747                 factor = 20;
6748
6749         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6750                 *fp |= FP_CB_TUNE;
6751
6752         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6753                 *fp2 |= FP_CB_TUNE;
6754
6755         dpll = 0;
6756
6757         if (is_lvds)
6758                 dpll |= DPLLB_MODE_LVDS;
6759         else
6760                 dpll |= DPLLB_MODE_DAC_SERIAL;
6761
6762         dpll |= (intel_crtc->config.pixel_multiplier - 1)
6763                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6764
6765         if (is_sdvo)
6766                 dpll |= DPLL_SDVO_HIGH_SPEED;
6767         if (intel_crtc->config.has_dp_encoder)
6768                 dpll |= DPLL_SDVO_HIGH_SPEED;
6769
6770         /* compute bitmask from p1 value */
6771         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6772         /* also FPA1 */
6773         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6774
6775         switch (intel_crtc->config.dpll.p2) {
6776         case 5:
6777                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6778                 break;
6779         case 7:
6780                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6781                 break;
6782         case 10:
6783                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6784                 break;
6785         case 14:
6786                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6787                 break;
6788         }
6789
6790         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6791                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6792         else
6793                 dpll |= PLL_REF_INPUT_DREFCLK;
6794
6795         return dpll | DPLL_VCO_ENABLE;
6796 }
6797
6798 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
6799                                   int x, int y,
6800                                   struct drm_framebuffer *fb)
6801 {
6802         struct drm_device *dev = crtc->dev;
6803         struct drm_i915_private *dev_priv = dev->dev_private;
6804         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6805         int pipe = intel_crtc->pipe;
6806         int plane = intel_crtc->plane;
6807         int num_connectors = 0;
6808         intel_clock_t clock, reduced_clock;
6809         u32 dpll = 0, fp = 0, fp2 = 0;
6810         bool ok, has_reduced_clock = false;
6811         bool is_lvds = false;
6812         struct intel_encoder *encoder;
6813         struct intel_shared_dpll *pll;
6814         int ret;
6815
6816         for_each_encoder_on_crtc(dev, crtc, encoder) {
6817                 switch (encoder->type) {
6818                 case INTEL_OUTPUT_LVDS:
6819                         is_lvds = true;
6820                         break;
6821                 }
6822
6823                 num_connectors++;
6824         }
6825
6826         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6827              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6828
6829         ok = ironlake_compute_clocks(crtc, &clock,
6830                                      &has_reduced_clock, &reduced_clock);
6831         if (!ok && !intel_crtc->config.clock_set) {
6832                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6833                 return -EINVAL;
6834         }
6835         /* Compat-code for transition, will disappear. */
6836         if (!intel_crtc->config.clock_set) {
6837                 intel_crtc->config.dpll.n = clock.n;
6838                 intel_crtc->config.dpll.m1 = clock.m1;
6839                 intel_crtc->config.dpll.m2 = clock.m2;
6840                 intel_crtc->config.dpll.p1 = clock.p1;
6841                 intel_crtc->config.dpll.p2 = clock.p2;
6842         }
6843
6844         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6845         if (intel_crtc->config.has_pch_encoder) {
6846                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6847                 if (has_reduced_clock)
6848                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6849
6850                 dpll = ironlake_compute_dpll(intel_crtc,
6851                                              &fp, &reduced_clock,
6852                                              has_reduced_clock ? &fp2 : NULL);
6853
6854                 intel_crtc->config.dpll_hw_state.dpll = dpll;
6855                 intel_crtc->config.dpll_hw_state.fp0 = fp;
6856                 if (has_reduced_clock)
6857                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
6858                 else
6859                         intel_crtc->config.dpll_hw_state.fp1 = fp;
6860
6861                 pll = intel_get_shared_dpll(intel_crtc);
6862                 if (pll == NULL) {
6863                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6864                                          pipe_name(pipe));
6865                         return -EINVAL;
6866                 }
6867         } else
6868                 intel_put_shared_dpll(intel_crtc);
6869
6870         if (intel_crtc->config.has_dp_encoder)
6871                 intel_dp_set_m_n(intel_crtc);
6872
6873         if (is_lvds && has_reduced_clock && i915.powersave)
6874                 intel_crtc->lowfreq_avail = true;
6875         else
6876                 intel_crtc->lowfreq_avail = false;
6877
6878         intel_set_pipe_timings(intel_crtc);
6879
6880         if (intel_crtc->config.has_pch_encoder) {
6881                 intel_cpu_transcoder_set_m_n(intel_crtc,
6882                                              &intel_crtc->config.fdi_m_n);
6883         }
6884
6885         ironlake_set_pipeconf(crtc);
6886
6887         /* Set up the display plane register */
6888         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
6889         POSTING_READ(DSPCNTR(plane));
6890
6891         ret = intel_pipe_set_base(crtc, x, y, fb);
6892
6893         return ret;
6894 }
6895
6896 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6897                                          struct intel_link_m_n *m_n)
6898 {
6899         struct drm_device *dev = crtc->base.dev;
6900         struct drm_i915_private *dev_priv = dev->dev_private;
6901         enum pipe pipe = crtc->pipe;
6902
6903         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6904         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6905         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6906                 & ~TU_SIZE_MASK;
6907         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6908         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6909                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6910 }
6911
6912 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6913                                          enum transcoder transcoder,
6914                                          struct intel_link_m_n *m_n)
6915 {
6916         struct drm_device *dev = crtc->base.dev;
6917         struct drm_i915_private *dev_priv = dev->dev_private;
6918         enum pipe pipe = crtc->pipe;
6919
6920         if (INTEL_INFO(dev)->gen >= 5) {
6921                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6922                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6923                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6924                         & ~TU_SIZE_MASK;
6925                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6926                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6927                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6928         } else {
6929                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6930                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6931                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6932                         & ~TU_SIZE_MASK;
6933                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6934                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6935                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6936         }
6937 }
6938
6939 void intel_dp_get_m_n(struct intel_crtc *crtc,
6940                       struct intel_crtc_config *pipe_config)
6941 {
6942         if (crtc->config.has_pch_encoder)
6943                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6944         else
6945                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6946                                              &pipe_config->dp_m_n);
6947 }
6948
6949 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6950                                         struct intel_crtc_config *pipe_config)
6951 {
6952         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6953                                      &pipe_config->fdi_m_n);
6954 }
6955
6956 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6957                                      struct intel_crtc_config *pipe_config)
6958 {
6959         struct drm_device *dev = crtc->base.dev;
6960         struct drm_i915_private *dev_priv = dev->dev_private;
6961         uint32_t tmp;
6962
6963         tmp = I915_READ(PF_CTL(crtc->pipe));
6964
6965         if (tmp & PF_ENABLE) {
6966                 pipe_config->pch_pfit.enabled = true;
6967                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6968                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
6969
6970                 /* We currently do not free assignements of panel fitters on
6971                  * ivb/hsw (since we don't use the higher upscaling modes which
6972                  * differentiates them) so just WARN about this case for now. */
6973                 if (IS_GEN7(dev)) {
6974                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6975                                 PF_PIPE_SEL_IVB(crtc->pipe));
6976                 }
6977         }
6978 }
6979
6980 static void ironlake_get_plane_config(struct intel_crtc *crtc,
6981                                       struct intel_plane_config *plane_config)
6982 {
6983         struct drm_device *dev = crtc->base.dev;
6984         struct drm_i915_private *dev_priv = dev->dev_private;
6985         u32 val, base, offset;
6986         int pipe = crtc->pipe, plane = crtc->plane;
6987         int fourcc, pixel_format;
6988         int aligned_height;
6989
6990         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6991         if (!crtc->base.primary->fb) {
6992                 DRM_DEBUG_KMS("failed to alloc fb\n");
6993                 return;
6994         }
6995
6996         val = I915_READ(DSPCNTR(plane));
6997
6998         if (INTEL_INFO(dev)->gen >= 4)
6999                 if (val & DISPPLANE_TILED)
7000                         plane_config->tiled = true;
7001
7002         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7003         fourcc = intel_format_to_fourcc(pixel_format);
7004         crtc->base.primary->fb->pixel_format = fourcc;
7005         crtc->base.primary->fb->bits_per_pixel =
7006                 drm_format_plane_cpp(fourcc, 0) * 8;
7007
7008         base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7009         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7010                 offset = I915_READ(DSPOFFSET(plane));
7011         } else {
7012                 if (plane_config->tiled)
7013                         offset = I915_READ(DSPTILEOFF(plane));
7014                 else
7015                         offset = I915_READ(DSPLINOFF(plane));
7016         }
7017         plane_config->base = base;
7018
7019         val = I915_READ(PIPESRC(pipe));
7020         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7021         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7022
7023         val = I915_READ(DSPSTRIDE(pipe));
7024         crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
7025
7026         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7027                                             plane_config->tiled);
7028
7029         plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
7030                                    aligned_height, PAGE_SIZE);
7031
7032         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7033                       pipe, plane, crtc->base.primary->fb->width,
7034                       crtc->base.primary->fb->height,
7035                       crtc->base.primary->fb->bits_per_pixel, base,
7036                       crtc->base.primary->fb->pitches[0],
7037                       plane_config->size);
7038 }
7039
7040 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7041                                      struct intel_crtc_config *pipe_config)
7042 {
7043         struct drm_device *dev = crtc->base.dev;
7044         struct drm_i915_private *dev_priv = dev->dev_private;
7045         uint32_t tmp;
7046
7047         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7048         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7049
7050         tmp = I915_READ(PIPECONF(crtc->pipe));
7051         if (!(tmp & PIPECONF_ENABLE))
7052                 return false;
7053
7054         switch (tmp & PIPECONF_BPC_MASK) {
7055         case PIPECONF_6BPC:
7056                 pipe_config->pipe_bpp = 18;
7057                 break;
7058         case PIPECONF_8BPC:
7059                 pipe_config->pipe_bpp = 24;
7060                 break;
7061         case PIPECONF_10BPC:
7062                 pipe_config->pipe_bpp = 30;
7063                 break;
7064         case PIPECONF_12BPC:
7065                 pipe_config->pipe_bpp = 36;
7066                 break;
7067         default:
7068                 break;
7069         }
7070
7071         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7072                 struct intel_shared_dpll *pll;
7073
7074                 pipe_config->has_pch_encoder = true;
7075
7076                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7077                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7078                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7079
7080                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7081
7082                 if (HAS_PCH_IBX(dev_priv->dev)) {
7083                         pipe_config->shared_dpll =
7084                                 (enum intel_dpll_id) crtc->pipe;
7085                 } else {
7086                         tmp = I915_READ(PCH_DPLL_SEL);
7087                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7088                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7089                         else
7090                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7091                 }
7092
7093                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7094
7095                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7096                                            &pipe_config->dpll_hw_state));
7097
7098                 tmp = pipe_config->dpll_hw_state.dpll;
7099                 pipe_config->pixel_multiplier =
7100                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7101                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7102
7103                 ironlake_pch_clock_get(crtc, pipe_config);
7104         } else {
7105                 pipe_config->pixel_multiplier = 1;
7106         }
7107
7108         intel_get_pipe_timings(crtc, pipe_config);
7109
7110         ironlake_get_pfit_config(crtc, pipe_config);
7111
7112         return true;
7113 }
7114
7115 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7116 {
7117         struct drm_device *dev = dev_priv->dev;
7118         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
7119         struct intel_crtc *crtc;
7120
7121         for_each_intel_crtc(dev, crtc)
7122                 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7123                      pipe_name(crtc->pipe));
7124
7125         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7126         WARN(plls->spll_refcount, "SPLL enabled\n");
7127         WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
7128         WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
7129         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7130         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7131              "CPU PWM1 enabled\n");
7132         WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7133              "CPU PWM2 enabled\n");
7134         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7135              "PCH PWM1 enabled\n");
7136         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7137              "Utility pin enabled\n");
7138         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7139
7140         /*
7141          * In theory we can still leave IRQs enabled, as long as only the HPD
7142          * interrupts remain enabled. We used to check for that, but since it's
7143          * gen-specific and since we only disable LCPLL after we fully disable
7144          * the interrupts, the check below should be enough.
7145          */
7146         WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n");
7147 }
7148
7149 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7150 {
7151         struct drm_device *dev = dev_priv->dev;
7152
7153         if (IS_HASWELL(dev)) {
7154                 mutex_lock(&dev_priv->rps.hw_lock);
7155                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7156                                             val))
7157                         DRM_ERROR("Failed to disable D_COMP\n");
7158                 mutex_unlock(&dev_priv->rps.hw_lock);
7159         } else {
7160                 I915_WRITE(D_COMP, val);
7161         }
7162         POSTING_READ(D_COMP);
7163 }
7164
7165 /*
7166  * This function implements pieces of two sequences from BSpec:
7167  * - Sequence for display software to disable LCPLL
7168  * - Sequence for display software to allow package C8+
7169  * The steps implemented here are just the steps that actually touch the LCPLL
7170  * register. Callers should take care of disabling all the display engine
7171  * functions, doing the mode unset, fixing interrupts, etc.
7172  */
7173 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7174                               bool switch_to_fclk, bool allow_power_down)
7175 {
7176         uint32_t val;
7177
7178         assert_can_disable_lcpll(dev_priv);
7179
7180         val = I915_READ(LCPLL_CTL);
7181
7182         if (switch_to_fclk) {
7183                 val |= LCPLL_CD_SOURCE_FCLK;
7184                 I915_WRITE(LCPLL_CTL, val);
7185
7186                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7187                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
7188                         DRM_ERROR("Switching to FCLK failed\n");
7189
7190                 val = I915_READ(LCPLL_CTL);
7191         }
7192
7193         val |= LCPLL_PLL_DISABLE;
7194         I915_WRITE(LCPLL_CTL, val);
7195         POSTING_READ(LCPLL_CTL);
7196
7197         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7198                 DRM_ERROR("LCPLL still locked\n");
7199
7200         val = I915_READ(D_COMP);
7201         val |= D_COMP_COMP_DISABLE;
7202         hsw_write_dcomp(dev_priv, val);
7203         ndelay(100);
7204
7205         if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
7206                 DRM_ERROR("D_COMP RCOMP still in progress\n");
7207
7208         if (allow_power_down) {
7209                 val = I915_READ(LCPLL_CTL);
7210                 val |= LCPLL_POWER_DOWN_ALLOW;
7211                 I915_WRITE(LCPLL_CTL, val);
7212                 POSTING_READ(LCPLL_CTL);
7213         }
7214 }
7215
7216 /*
7217  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7218  * source.
7219  */
7220 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7221 {
7222         uint32_t val;
7223         unsigned long irqflags;
7224
7225         val = I915_READ(LCPLL_CTL);
7226
7227         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7228                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7229                 return;
7230
7231         /*
7232          * Make sure we're not on PC8 state before disabling PC8, otherwise
7233          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7234          *
7235          * The other problem is that hsw_restore_lcpll() is called as part of
7236          * the runtime PM resume sequence, so we can't just call
7237          * gen6_gt_force_wake_get() because that function calls
7238          * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7239          * while we are on the resume sequence. So to solve this problem we have
7240          * to call special forcewake code that doesn't touch runtime PM and
7241          * doesn't enable the forcewake delayed work.
7242          */
7243         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7244         if (dev_priv->uncore.forcewake_count++ == 0)
7245                 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7246         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7247
7248         if (val & LCPLL_POWER_DOWN_ALLOW) {
7249                 val &= ~LCPLL_POWER_DOWN_ALLOW;
7250                 I915_WRITE(LCPLL_CTL, val);
7251                 POSTING_READ(LCPLL_CTL);
7252         }
7253
7254         val = I915_READ(D_COMP);
7255         val |= D_COMP_COMP_FORCE;
7256         val &= ~D_COMP_COMP_DISABLE;
7257         hsw_write_dcomp(dev_priv, val);
7258
7259         val = I915_READ(LCPLL_CTL);
7260         val &= ~LCPLL_PLL_DISABLE;
7261         I915_WRITE(LCPLL_CTL, val);
7262
7263         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7264                 DRM_ERROR("LCPLL not locked yet\n");
7265
7266         if (val & LCPLL_CD_SOURCE_FCLK) {
7267                 val = I915_READ(LCPLL_CTL);
7268                 val &= ~LCPLL_CD_SOURCE_FCLK;
7269                 I915_WRITE(LCPLL_CTL, val);
7270
7271                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7272                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7273                         DRM_ERROR("Switching back to LCPLL failed\n");
7274         }
7275
7276         /* See the big comment above. */
7277         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7278         if (--dev_priv->uncore.forcewake_count == 0)
7279                 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7280         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7281 }
7282
7283 /*
7284  * Package states C8 and deeper are really deep PC states that can only be
7285  * reached when all the devices on the system allow it, so even if the graphics
7286  * device allows PC8+, it doesn't mean the system will actually get to these
7287  * states. Our driver only allows PC8+ when going into runtime PM.
7288  *
7289  * The requirements for PC8+ are that all the outputs are disabled, the power
7290  * well is disabled and most interrupts are disabled, and these are also
7291  * requirements for runtime PM. When these conditions are met, we manually do
7292  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7293  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7294  * hang the machine.
7295  *
7296  * When we really reach PC8 or deeper states (not just when we allow it) we lose
7297  * the state of some registers, so when we come back from PC8+ we need to
7298  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7299  * need to take care of the registers kept by RC6. Notice that this happens even
7300  * if we don't put the device in PCI D3 state (which is what currently happens
7301  * because of the runtime PM support).
7302  *
7303  * For more, read "Display Sequences for Package C8" on the hardware
7304  * documentation.
7305  */
7306 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7307 {
7308         struct drm_device *dev = dev_priv->dev;
7309         uint32_t val;
7310
7311         DRM_DEBUG_KMS("Enabling package C8+\n");
7312
7313         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7314                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7315                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7316                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7317         }
7318
7319         lpt_disable_clkout_dp(dev);
7320         hsw_disable_lcpll(dev_priv, true, true);
7321 }
7322
7323 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7324 {
7325         struct drm_device *dev = dev_priv->dev;
7326         uint32_t val;
7327
7328         DRM_DEBUG_KMS("Disabling package C8+\n");
7329
7330         hsw_restore_lcpll(dev_priv);
7331         lpt_init_pch_refclk(dev);
7332
7333         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7334                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7335                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7336                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7337         }
7338
7339         intel_prepare_ddi(dev);
7340 }
7341
7342 static void snb_modeset_global_resources(struct drm_device *dev)
7343 {
7344         modeset_update_crtc_power_domains(dev);
7345 }
7346
7347 static void haswell_modeset_global_resources(struct drm_device *dev)
7348 {
7349         modeset_update_crtc_power_domains(dev);
7350 }
7351
7352 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7353                                  int x, int y,
7354                                  struct drm_framebuffer *fb)
7355 {
7356         struct drm_device *dev = crtc->dev;
7357         struct drm_i915_private *dev_priv = dev->dev_private;
7358         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7359         int plane = intel_crtc->plane;
7360         int ret;
7361
7362         if (!intel_ddi_pll_select(intel_crtc))
7363                 return -EINVAL;
7364         intel_ddi_pll_enable(intel_crtc);
7365
7366         if (intel_crtc->config.has_dp_encoder)
7367                 intel_dp_set_m_n(intel_crtc);
7368
7369         intel_crtc->lowfreq_avail = false;
7370
7371         intel_set_pipe_timings(intel_crtc);
7372
7373         if (intel_crtc->config.has_pch_encoder) {
7374                 intel_cpu_transcoder_set_m_n(intel_crtc,
7375                                              &intel_crtc->config.fdi_m_n);
7376         }
7377
7378         haswell_set_pipeconf(crtc);
7379
7380         intel_set_pipe_csc(crtc);
7381
7382         /* Set up the display plane register */
7383         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
7384         POSTING_READ(DSPCNTR(plane));
7385
7386         ret = intel_pipe_set_base(crtc, x, y, fb);
7387
7388         return ret;
7389 }
7390
7391 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7392                                     struct intel_crtc_config *pipe_config)
7393 {
7394         struct drm_device *dev = crtc->base.dev;
7395         struct drm_i915_private *dev_priv = dev->dev_private;
7396         enum intel_display_power_domain pfit_domain;
7397         uint32_t tmp;
7398
7399         if (!intel_display_power_enabled(dev_priv,
7400                                          POWER_DOMAIN_PIPE(crtc->pipe)))
7401                 return false;
7402
7403         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7404         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7405
7406         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7407         if (tmp & TRANS_DDI_FUNC_ENABLE) {
7408                 enum pipe trans_edp_pipe;
7409                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7410                 default:
7411                         WARN(1, "unknown pipe linked to edp transcoder\n");
7412                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7413                 case TRANS_DDI_EDP_INPUT_A_ON:
7414                         trans_edp_pipe = PIPE_A;
7415                         break;
7416                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7417                         trans_edp_pipe = PIPE_B;
7418                         break;
7419                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7420                         trans_edp_pipe = PIPE_C;
7421                         break;
7422                 }
7423
7424                 if (trans_edp_pipe == crtc->pipe)
7425                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
7426         }
7427
7428         if (!intel_display_power_enabled(dev_priv,
7429                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7430                 return false;
7431
7432         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7433         if (!(tmp & PIPECONF_ENABLE))
7434                 return false;
7435
7436         /*
7437          * Haswell has only FDI/PCH transcoder A. It is which is connected to
7438          * DDI E. So just check whether this pipe is wired to DDI E and whether
7439          * the PCH transcoder is on.
7440          */
7441         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7442         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
7443             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7444                 pipe_config->has_pch_encoder = true;
7445
7446                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7447                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7448                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7449
7450                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7451         }
7452
7453         intel_get_pipe_timings(crtc, pipe_config);
7454
7455         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7456         if (intel_display_power_enabled(dev_priv, pfit_domain))
7457                 ironlake_get_pfit_config(crtc, pipe_config);
7458
7459         if (IS_HASWELL(dev))
7460                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7461                         (I915_READ(IPS_CTL) & IPS_ENABLE);
7462
7463         pipe_config->pixel_multiplier = 1;
7464
7465         return true;
7466 }
7467
7468 static int intel_crtc_mode_set(struct drm_crtc *crtc,
7469                                int x, int y,
7470                                struct drm_framebuffer *fb)
7471 {
7472         struct drm_device *dev = crtc->dev;
7473         struct drm_i915_private *dev_priv = dev->dev_private;
7474         struct intel_encoder *encoder;
7475         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7476         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
7477         int pipe = intel_crtc->pipe;
7478         int ret;
7479
7480         drm_vblank_pre_modeset(dev, pipe);
7481
7482         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
7483
7484         drm_vblank_post_modeset(dev, pipe);
7485
7486         if (ret != 0)
7487                 return ret;
7488
7489         for_each_encoder_on_crtc(dev, crtc, encoder) {
7490                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7491                         encoder->base.base.id,
7492                         drm_get_encoder_name(&encoder->base),
7493                         mode->base.id, mode->name);
7494
7495                 if (encoder->mode_set)
7496                         encoder->mode_set(encoder);
7497         }
7498
7499         return 0;
7500 }
7501
7502 static struct {
7503         int clock;
7504         u32 config;
7505 } hdmi_audio_clock[] = {
7506         { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7507         { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7508         { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7509         { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7510         { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7511         { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7512         { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7513         { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7514         { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7515         { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7516 };
7517
7518 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7519 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7520 {
7521         int i;
7522
7523         for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7524                 if (mode->clock == hdmi_audio_clock[i].clock)
7525                         break;
7526         }
7527
7528         if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7529                 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7530                 i = 1;
7531         }
7532
7533         DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7534                       hdmi_audio_clock[i].clock,
7535                       hdmi_audio_clock[i].config);
7536
7537         return hdmi_audio_clock[i].config;
7538 }
7539
7540 static bool intel_eld_uptodate(struct drm_connector *connector,
7541                                int reg_eldv, uint32_t bits_eldv,
7542                                int reg_elda, uint32_t bits_elda,
7543                                int reg_edid)
7544 {
7545         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7546         uint8_t *eld = connector->eld;
7547         uint32_t i;
7548
7549         i = I915_READ(reg_eldv);
7550         i &= bits_eldv;
7551
7552         if (!eld[0])
7553                 return !i;
7554
7555         if (!i)
7556                 return false;
7557
7558         i = I915_READ(reg_elda);
7559         i &= ~bits_elda;
7560         I915_WRITE(reg_elda, i);
7561
7562         for (i = 0; i < eld[2]; i++)
7563                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7564                         return false;
7565
7566         return true;
7567 }
7568
7569 static void g4x_write_eld(struct drm_connector *connector,
7570                           struct drm_crtc *crtc,
7571                           struct drm_display_mode *mode)
7572 {
7573         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7574         uint8_t *eld = connector->eld;
7575         uint32_t eldv;
7576         uint32_t len;
7577         uint32_t i;
7578
7579         i = I915_READ(G4X_AUD_VID_DID);
7580
7581         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7582                 eldv = G4X_ELDV_DEVCL_DEVBLC;
7583         else
7584                 eldv = G4X_ELDV_DEVCTG;
7585
7586         if (intel_eld_uptodate(connector,
7587                                G4X_AUD_CNTL_ST, eldv,
7588                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7589                                G4X_HDMIW_HDMIEDID))
7590                 return;
7591
7592         i = I915_READ(G4X_AUD_CNTL_ST);
7593         i &= ~(eldv | G4X_ELD_ADDR);
7594         len = (i >> 9) & 0x1f;          /* ELD buffer size */
7595         I915_WRITE(G4X_AUD_CNTL_ST, i);
7596
7597         if (!eld[0])
7598                 return;
7599
7600         len = min_t(uint8_t, eld[2], len);
7601         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7602         for (i = 0; i < len; i++)
7603                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7604
7605         i = I915_READ(G4X_AUD_CNTL_ST);
7606         i |= eldv;
7607         I915_WRITE(G4X_AUD_CNTL_ST, i);
7608 }
7609
7610 static void haswell_write_eld(struct drm_connector *connector,
7611                               struct drm_crtc *crtc,
7612                               struct drm_display_mode *mode)
7613 {
7614         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7615         uint8_t *eld = connector->eld;
7616         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7617         uint32_t eldv;
7618         uint32_t i;
7619         int len;
7620         int pipe = to_intel_crtc(crtc)->pipe;
7621         int tmp;
7622
7623         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7624         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7625         int aud_config = HSW_AUD_CFG(pipe);
7626         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7627
7628         /* Audio output enable */
7629         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7630         tmp = I915_READ(aud_cntrl_st2);
7631         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7632         I915_WRITE(aud_cntrl_st2, tmp);
7633         POSTING_READ(aud_cntrl_st2);
7634
7635         assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
7636
7637         /* Set ELD valid state */
7638         tmp = I915_READ(aud_cntrl_st2);
7639         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7640         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7641         I915_WRITE(aud_cntrl_st2, tmp);
7642         tmp = I915_READ(aud_cntrl_st2);
7643         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7644
7645         /* Enable HDMI mode */
7646         tmp = I915_READ(aud_config);
7647         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7648         /* clear N_programing_enable and N_value_index */
7649         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7650         I915_WRITE(aud_config, tmp);
7651
7652         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7653
7654         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7655         intel_crtc->eld_vld = true;
7656
7657         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7658                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7659                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7660                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7661         } else {
7662                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7663         }
7664
7665         if (intel_eld_uptodate(connector,
7666                                aud_cntrl_st2, eldv,
7667                                aud_cntl_st, IBX_ELD_ADDRESS,
7668                                hdmiw_hdmiedid))
7669                 return;
7670
7671         i = I915_READ(aud_cntrl_st2);
7672         i &= ~eldv;
7673         I915_WRITE(aud_cntrl_st2, i);
7674
7675         if (!eld[0])
7676                 return;
7677
7678         i = I915_READ(aud_cntl_st);
7679         i &= ~IBX_ELD_ADDRESS;
7680         I915_WRITE(aud_cntl_st, i);
7681         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
7682         DRM_DEBUG_DRIVER("port num:%d\n", i);
7683
7684         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7685         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7686         for (i = 0; i < len; i++)
7687                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7688
7689         i = I915_READ(aud_cntrl_st2);
7690         i |= eldv;
7691         I915_WRITE(aud_cntrl_st2, i);
7692
7693 }
7694
7695 static void ironlake_write_eld(struct drm_connector *connector,
7696                                struct drm_crtc *crtc,
7697                                struct drm_display_mode *mode)
7698 {
7699         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7700         uint8_t *eld = connector->eld;
7701         uint32_t eldv;
7702         uint32_t i;
7703         int len;
7704         int hdmiw_hdmiedid;
7705         int aud_config;
7706         int aud_cntl_st;
7707         int aud_cntrl_st2;
7708         int pipe = to_intel_crtc(crtc)->pipe;
7709
7710         if (HAS_PCH_IBX(connector->dev)) {
7711                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7712                 aud_config = IBX_AUD_CFG(pipe);
7713                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7714                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7715         } else if (IS_VALLEYVIEW(connector->dev)) {
7716                 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7717                 aud_config = VLV_AUD_CFG(pipe);
7718                 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7719                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7720         } else {
7721                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7722                 aud_config = CPT_AUD_CFG(pipe);
7723                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7724                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7725         }
7726
7727         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7728
7729         if (IS_VALLEYVIEW(connector->dev))  {
7730                 struct intel_encoder *intel_encoder;
7731                 struct intel_digital_port *intel_dig_port;
7732
7733                 intel_encoder = intel_attached_encoder(connector);
7734                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7735                 i = intel_dig_port->port;
7736         } else {
7737                 i = I915_READ(aud_cntl_st);
7738                 i = (i >> 29) & DIP_PORT_SEL_MASK;
7739                 /* DIP_Port_Select, 0x1 = PortB */
7740         }
7741
7742         if (!i) {
7743                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7744                 /* operate blindly on all ports */
7745                 eldv = IBX_ELD_VALIDB;
7746                 eldv |= IBX_ELD_VALIDB << 4;
7747                 eldv |= IBX_ELD_VALIDB << 8;
7748         } else {
7749                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7750                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7751         }
7752
7753         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7754                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7755                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7756                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7757         } else {
7758                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7759         }
7760
7761         if (intel_eld_uptodate(connector,
7762                                aud_cntrl_st2, eldv,
7763                                aud_cntl_st, IBX_ELD_ADDRESS,
7764                                hdmiw_hdmiedid))
7765                 return;
7766
7767         i = I915_READ(aud_cntrl_st2);
7768         i &= ~eldv;
7769         I915_WRITE(aud_cntrl_st2, i);
7770
7771         if (!eld[0])
7772                 return;
7773
7774         i = I915_READ(aud_cntl_st);
7775         i &= ~IBX_ELD_ADDRESS;
7776         I915_WRITE(aud_cntl_st, i);
7777
7778         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7779         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7780         for (i = 0; i < len; i++)
7781                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7782
7783         i = I915_READ(aud_cntrl_st2);
7784         i |= eldv;
7785         I915_WRITE(aud_cntrl_st2, i);
7786 }
7787
7788 void intel_write_eld(struct drm_encoder *encoder,
7789                      struct drm_display_mode *mode)
7790 {
7791         struct drm_crtc *crtc = encoder->crtc;
7792         struct drm_connector *connector;
7793         struct drm_device *dev = encoder->dev;
7794         struct drm_i915_private *dev_priv = dev->dev_private;
7795
7796         connector = drm_select_eld(encoder, mode);
7797         if (!connector)
7798                 return;
7799
7800         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7801                          connector->base.id,
7802                          drm_get_connector_name(connector),
7803                          connector->encoder->base.id,
7804                          drm_get_encoder_name(connector->encoder));
7805
7806         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7807
7808         if (dev_priv->display.write_eld)
7809                 dev_priv->display.write_eld(connector, crtc, mode);
7810 }
7811
7812 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7813 {
7814         struct drm_device *dev = crtc->dev;
7815         struct drm_i915_private *dev_priv = dev->dev_private;
7816         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7817         bool visible = base != 0;
7818         u32 cntl;
7819
7820         if (intel_crtc->cursor_visible == visible)
7821                 return;
7822
7823         cntl = I915_READ(_CURACNTR);
7824         if (visible) {
7825                 /* On these chipsets we can only modify the base whilst
7826                  * the cursor is disabled.
7827                  */
7828                 I915_WRITE(_CURABASE, base);
7829
7830                 cntl &= ~(CURSOR_FORMAT_MASK);
7831                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7832                 cntl |= CURSOR_ENABLE |
7833                         CURSOR_GAMMA_ENABLE |
7834                         CURSOR_FORMAT_ARGB;
7835         } else
7836                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
7837         I915_WRITE(_CURACNTR, cntl);
7838
7839         intel_crtc->cursor_visible = visible;
7840 }
7841
7842 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7843 {
7844         struct drm_device *dev = crtc->dev;
7845         struct drm_i915_private *dev_priv = dev->dev_private;
7846         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7847         int pipe = intel_crtc->pipe;
7848         bool visible = base != 0;
7849
7850         if (intel_crtc->cursor_visible != visible) {
7851                 int16_t width = intel_crtc->cursor_width;
7852                 uint32_t cntl = I915_READ(CURCNTR(pipe));
7853                 if (base) {
7854                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7855                         cntl |= MCURSOR_GAMMA_ENABLE;
7856
7857                         switch (width) {
7858                         case 64:
7859                                 cntl |= CURSOR_MODE_64_ARGB_AX;
7860                                 break;
7861                         case 128:
7862                                 cntl |= CURSOR_MODE_128_ARGB_AX;
7863                                 break;
7864                         case 256:
7865                                 cntl |= CURSOR_MODE_256_ARGB_AX;
7866                                 break;
7867                         default:
7868                                 WARN_ON(1);
7869                                 return;
7870                         }
7871                         cntl |= pipe << 28; /* Connect to correct pipe */
7872                 } else {
7873                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7874                         cntl |= CURSOR_MODE_DISABLE;
7875                 }
7876                 I915_WRITE(CURCNTR(pipe), cntl);
7877
7878                 intel_crtc->cursor_visible = visible;
7879         }
7880         /* and commit changes on next vblank */
7881         POSTING_READ(CURCNTR(pipe));
7882         I915_WRITE(CURBASE(pipe), base);
7883         POSTING_READ(CURBASE(pipe));
7884 }
7885
7886 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7887 {
7888         struct drm_device *dev = crtc->dev;
7889         struct drm_i915_private *dev_priv = dev->dev_private;
7890         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7891         int pipe = intel_crtc->pipe;
7892         bool visible = base != 0;
7893
7894         if (intel_crtc->cursor_visible != visible) {
7895                 int16_t width = intel_crtc->cursor_width;
7896                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7897                 if (base) {
7898                         cntl &= ~CURSOR_MODE;
7899                         cntl |= MCURSOR_GAMMA_ENABLE;
7900                         switch (width) {
7901                         case 64:
7902                                 cntl |= CURSOR_MODE_64_ARGB_AX;
7903                                 break;
7904                         case 128:
7905                                 cntl |= CURSOR_MODE_128_ARGB_AX;
7906                                 break;
7907                         case 256:
7908                                 cntl |= CURSOR_MODE_256_ARGB_AX;
7909                                 break;
7910                         default:
7911                                 WARN_ON(1);
7912                                 return;
7913                         }
7914                 } else {
7915                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7916                         cntl |= CURSOR_MODE_DISABLE;
7917                 }
7918                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7919                         cntl |= CURSOR_PIPE_CSC_ENABLE;
7920                         cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7921                 }
7922                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7923
7924                 intel_crtc->cursor_visible = visible;
7925         }
7926         /* and commit changes on next vblank */
7927         POSTING_READ(CURCNTR_IVB(pipe));
7928         I915_WRITE(CURBASE_IVB(pipe), base);
7929         POSTING_READ(CURBASE_IVB(pipe));
7930 }
7931
7932 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7933 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7934                                      bool on)
7935 {
7936         struct drm_device *dev = crtc->dev;
7937         struct drm_i915_private *dev_priv = dev->dev_private;
7938         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7939         int pipe = intel_crtc->pipe;
7940         int x = intel_crtc->cursor_x;
7941         int y = intel_crtc->cursor_y;
7942         u32 base = 0, pos = 0;
7943         bool visible;
7944
7945         if (on)
7946                 base = intel_crtc->cursor_addr;
7947
7948         if (x >= intel_crtc->config.pipe_src_w)
7949                 base = 0;
7950
7951         if (y >= intel_crtc->config.pipe_src_h)
7952                 base = 0;
7953
7954         if (x < 0) {
7955                 if (x + intel_crtc->cursor_width <= 0)
7956                         base = 0;
7957
7958                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7959                 x = -x;
7960         }
7961         pos |= x << CURSOR_X_SHIFT;
7962
7963         if (y < 0) {
7964                 if (y + intel_crtc->cursor_height <= 0)
7965                         base = 0;
7966
7967                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7968                 y = -y;
7969         }
7970         pos |= y << CURSOR_Y_SHIFT;
7971
7972         visible = base != 0;
7973         if (!visible && !intel_crtc->cursor_visible)
7974                 return;
7975
7976         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7977                 I915_WRITE(CURPOS_IVB(pipe), pos);
7978                 ivb_update_cursor(crtc, base);
7979         } else {
7980                 I915_WRITE(CURPOS(pipe), pos);
7981                 if (IS_845G(dev) || IS_I865G(dev))
7982                         i845_update_cursor(crtc, base);
7983                 else
7984                         i9xx_update_cursor(crtc, base);
7985         }
7986 }
7987
7988 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
7989                                  struct drm_file *file,
7990                                  uint32_t handle,
7991                                  uint32_t width, uint32_t height)
7992 {
7993         struct drm_device *dev = crtc->dev;
7994         struct drm_i915_private *dev_priv = dev->dev_private;
7995         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7996         struct drm_i915_gem_object *obj;
7997         unsigned old_width;
7998         uint32_t addr;
7999         int ret;
8000
8001         /* if we want to turn off the cursor ignore width and height */
8002         if (!handle) {
8003                 DRM_DEBUG_KMS("cursor off\n");
8004                 addr = 0;
8005                 obj = NULL;
8006                 mutex_lock(&dev->struct_mutex);
8007                 goto finish;
8008         }
8009
8010         /* Check for which cursor types we support */
8011         if (!((width == 64 && height == 64) ||
8012                         (width == 128 && height == 128 && !IS_GEN2(dev)) ||
8013                         (width == 256 && height == 256 && !IS_GEN2(dev)))) {
8014                 DRM_DEBUG("Cursor dimension not supported\n");
8015                 return -EINVAL;
8016         }
8017
8018         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
8019         if (&obj->base == NULL)
8020                 return -ENOENT;
8021
8022         if (obj->base.size < width * height * 4) {
8023                 DRM_DEBUG_KMS("buffer is to small\n");
8024                 ret = -ENOMEM;
8025                 goto fail;
8026         }
8027
8028         /* we only need to pin inside GTT if cursor is non-phy */
8029         mutex_lock(&dev->struct_mutex);
8030         if (!INTEL_INFO(dev)->cursor_needs_physical) {
8031                 unsigned alignment;
8032
8033                 if (obj->tiling_mode) {
8034                         DRM_DEBUG_KMS("cursor cannot be tiled\n");
8035                         ret = -EINVAL;
8036                         goto fail_locked;
8037                 }
8038
8039                 /* Note that the w/a also requires 2 PTE of padding following
8040                  * the bo. We currently fill all unused PTE with the shadow
8041                  * page and so we should always have valid PTE following the
8042                  * cursor preventing the VT-d warning.
8043                  */
8044                 alignment = 0;
8045                 if (need_vtd_wa(dev))
8046                         alignment = 64*1024;
8047
8048                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8049                 if (ret) {
8050                         DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8051                         goto fail_locked;
8052                 }
8053
8054                 ret = i915_gem_object_put_fence(obj);
8055                 if (ret) {
8056                         DRM_DEBUG_KMS("failed to release fence for cursor");
8057                         goto fail_unpin;
8058                 }
8059
8060                 addr = i915_gem_obj_ggtt_offset(obj);
8061         } else {
8062                 int align = IS_I830(dev) ? 16 * 1024 : 256;
8063                 ret = i915_gem_attach_phys_object(dev, obj,
8064                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
8065                                                   align);
8066                 if (ret) {
8067                         DRM_DEBUG_KMS("failed to attach phys object\n");
8068                         goto fail_locked;
8069                 }
8070                 addr = obj->phys_obj->handle->busaddr;
8071         }
8072
8073         if (IS_GEN2(dev))
8074                 I915_WRITE(CURSIZE, (height << 12) | width);
8075
8076  finish:
8077         if (intel_crtc->cursor_bo) {
8078                 if (INTEL_INFO(dev)->cursor_needs_physical) {
8079                         if (intel_crtc->cursor_bo != obj)
8080                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
8081                 } else
8082                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8083                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
8084         }
8085
8086         mutex_unlock(&dev->struct_mutex);
8087
8088         old_width = intel_crtc->cursor_width;
8089
8090         intel_crtc->cursor_addr = addr;
8091         intel_crtc->cursor_bo = obj;
8092         intel_crtc->cursor_width = width;
8093         intel_crtc->cursor_height = height;
8094
8095         if (intel_crtc->active) {
8096                 if (old_width != width)
8097                         intel_update_watermarks(crtc);
8098                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8099         }
8100
8101         return 0;
8102 fail_unpin:
8103         i915_gem_object_unpin_from_display_plane(obj);
8104 fail_locked:
8105         mutex_unlock(&dev->struct_mutex);
8106 fail:
8107         drm_gem_object_unreference_unlocked(&obj->base);
8108         return ret;
8109 }
8110
8111 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
8112 {
8113         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8114
8115         intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
8116         intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
8117
8118         if (intel_crtc->active)
8119                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8120
8121         return 0;
8122 }
8123
8124 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8125                                  u16 *blue, uint32_t start, uint32_t size)
8126 {
8127         int end = (start + size > 256) ? 256 : start + size, i;
8128         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8129
8130         for (i = start; i < end; i++) {
8131                 intel_crtc->lut_r[i] = red[i] >> 8;
8132                 intel_crtc->lut_g[i] = green[i] >> 8;
8133                 intel_crtc->lut_b[i] = blue[i] >> 8;
8134         }
8135
8136         intel_crtc_load_lut(crtc);
8137 }
8138
8139 /* VESA 640x480x72Hz mode to set on the pipe */
8140 static struct drm_display_mode load_detect_mode = {
8141         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8142                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8143 };
8144
8145 struct drm_framebuffer *
8146 __intel_framebuffer_create(struct drm_device *dev,
8147                            struct drm_mode_fb_cmd2 *mode_cmd,
8148                            struct drm_i915_gem_object *obj)
8149 {
8150         struct intel_framebuffer *intel_fb;
8151         int ret;
8152
8153         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8154         if (!intel_fb) {
8155                 drm_gem_object_unreference_unlocked(&obj->base);
8156                 return ERR_PTR(-ENOMEM);
8157         }
8158
8159         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8160         if (ret)
8161                 goto err;
8162
8163         return &intel_fb->base;
8164 err:
8165         drm_gem_object_unreference_unlocked(&obj->base);
8166         kfree(intel_fb);
8167
8168         return ERR_PTR(ret);
8169 }
8170
8171 static struct drm_framebuffer *
8172 intel_framebuffer_create(struct drm_device *dev,
8173                          struct drm_mode_fb_cmd2 *mode_cmd,
8174                          struct drm_i915_gem_object *obj)
8175 {
8176         struct drm_framebuffer *fb;
8177         int ret;
8178
8179         ret = i915_mutex_lock_interruptible(dev);
8180         if (ret)
8181                 return ERR_PTR(ret);
8182         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8183         mutex_unlock(&dev->struct_mutex);
8184
8185         return fb;
8186 }
8187
8188 static u32
8189 intel_framebuffer_pitch_for_width(int width, int bpp)
8190 {
8191         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8192         return ALIGN(pitch, 64);
8193 }
8194
8195 static u32
8196 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8197 {
8198         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8199         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
8200 }
8201
8202 static struct drm_framebuffer *
8203 intel_framebuffer_create_for_mode(struct drm_device *dev,
8204                                   struct drm_display_mode *mode,
8205                                   int depth, int bpp)
8206 {
8207         struct drm_i915_gem_object *obj;
8208         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8209
8210         obj = i915_gem_alloc_object(dev,
8211                                     intel_framebuffer_size_for_mode(mode, bpp));
8212         if (obj == NULL)
8213                 return ERR_PTR(-ENOMEM);
8214
8215         mode_cmd.width = mode->hdisplay;
8216         mode_cmd.height = mode->vdisplay;
8217         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8218                                                                 bpp);
8219         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8220
8221         return intel_framebuffer_create(dev, &mode_cmd, obj);
8222 }
8223
8224 static struct drm_framebuffer *
8225 mode_fits_in_fbdev(struct drm_device *dev,
8226                    struct drm_display_mode *mode)
8227 {
8228 #ifdef CONFIG_DRM_I915_FBDEV
8229         struct drm_i915_private *dev_priv = dev->dev_private;
8230         struct drm_i915_gem_object *obj;
8231         struct drm_framebuffer *fb;
8232
8233         if (!dev_priv->fbdev)
8234                 return NULL;
8235
8236         if (!dev_priv->fbdev->fb)
8237                 return NULL;
8238
8239         obj = dev_priv->fbdev->fb->obj;
8240         BUG_ON(!obj);
8241
8242         fb = &dev_priv->fbdev->fb->base;
8243         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8244                                                                fb->bits_per_pixel))
8245                 return NULL;
8246
8247         if (obj->base.size < mode->vdisplay * fb->pitches[0])
8248                 return NULL;
8249
8250         return fb;
8251 #else
8252         return NULL;
8253 #endif
8254 }
8255
8256 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8257                                 struct drm_display_mode *mode,
8258                                 struct intel_load_detect_pipe *old)
8259 {
8260         struct intel_crtc *intel_crtc;
8261         struct intel_encoder *intel_encoder =
8262                 intel_attached_encoder(connector);
8263         struct drm_crtc *possible_crtc;
8264         struct drm_encoder *encoder = &intel_encoder->base;
8265         struct drm_crtc *crtc = NULL;
8266         struct drm_device *dev = encoder->dev;
8267         struct drm_framebuffer *fb;
8268         int i = -1;
8269
8270         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8271                       connector->base.id, drm_get_connector_name(connector),
8272                       encoder->base.id, drm_get_encoder_name(encoder));
8273
8274         /*
8275          * Algorithm gets a little messy:
8276          *
8277          *   - if the connector already has an assigned crtc, use it (but make
8278          *     sure it's on first)
8279          *
8280          *   - try to find the first unused crtc that can drive this connector,
8281          *     and use that if we find one
8282          */
8283
8284         /* See if we already have a CRTC for this connector */
8285         if (encoder->crtc) {
8286                 crtc = encoder->crtc;
8287
8288                 mutex_lock(&crtc->mutex);
8289
8290                 old->dpms_mode = connector->dpms;
8291                 old->load_detect_temp = false;
8292
8293                 /* Make sure the crtc and connector are running */
8294                 if (connector->dpms != DRM_MODE_DPMS_ON)
8295                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8296
8297                 return true;
8298         }
8299
8300         /* Find an unused one (if possible) */
8301         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
8302                 i++;
8303                 if (!(encoder->possible_crtcs & (1 << i)))
8304                         continue;
8305                 if (!possible_crtc->enabled) {
8306                         crtc = possible_crtc;
8307                         break;
8308                 }
8309         }
8310
8311         /*
8312          * If we didn't find an unused CRTC, don't use any.
8313          */
8314         if (!crtc) {
8315                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8316                 return false;
8317         }
8318
8319         mutex_lock(&crtc->mutex);
8320         intel_encoder->new_crtc = to_intel_crtc(crtc);
8321         to_intel_connector(connector)->new_encoder = intel_encoder;
8322
8323         intel_crtc = to_intel_crtc(crtc);
8324         intel_crtc->new_enabled = true;
8325         intel_crtc->new_config = &intel_crtc->config;
8326         old->dpms_mode = connector->dpms;
8327         old->load_detect_temp = true;
8328         old->release_fb = NULL;
8329
8330         if (!mode)
8331                 mode = &load_detect_mode;
8332
8333         /* We need a framebuffer large enough to accommodate all accesses
8334          * that the plane may generate whilst we perform load detection.
8335          * We can not rely on the fbcon either being present (we get called
8336          * during its initialisation to detect all boot displays, or it may
8337          * not even exist) or that it is large enough to satisfy the
8338          * requested mode.
8339          */
8340         fb = mode_fits_in_fbdev(dev, mode);
8341         if (fb == NULL) {
8342                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8343                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8344                 old->release_fb = fb;
8345         } else
8346                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8347         if (IS_ERR(fb)) {
8348                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8349                 goto fail;
8350         }
8351
8352         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8353                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8354                 if (old->release_fb)
8355                         old->release_fb->funcs->destroy(old->release_fb);
8356                 goto fail;
8357         }
8358
8359         /* let the connector get through one full cycle before testing */
8360         intel_wait_for_vblank(dev, intel_crtc->pipe);
8361         return true;
8362
8363  fail:
8364         intel_crtc->new_enabled = crtc->enabled;
8365         if (intel_crtc->new_enabled)
8366                 intel_crtc->new_config = &intel_crtc->config;
8367         else
8368                 intel_crtc->new_config = NULL;
8369         mutex_unlock(&crtc->mutex);
8370         return false;
8371 }
8372
8373 void intel_release_load_detect_pipe(struct drm_connector *connector,
8374                                     struct intel_load_detect_pipe *old)
8375 {
8376         struct intel_encoder *intel_encoder =
8377                 intel_attached_encoder(connector);
8378         struct drm_encoder *encoder = &intel_encoder->base;
8379         struct drm_crtc *crtc = encoder->crtc;
8380         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8381
8382         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8383                       connector->base.id, drm_get_connector_name(connector),
8384                       encoder->base.id, drm_get_encoder_name(encoder));
8385
8386         if (old->load_detect_temp) {
8387                 to_intel_connector(connector)->new_encoder = NULL;
8388                 intel_encoder->new_crtc = NULL;
8389                 intel_crtc->new_enabled = false;
8390                 intel_crtc->new_config = NULL;
8391                 intel_set_mode(crtc, NULL, 0, 0, NULL);
8392
8393                 if (old->release_fb) {
8394                         drm_framebuffer_unregister_private(old->release_fb);
8395                         drm_framebuffer_unreference(old->release_fb);
8396                 }
8397
8398                 mutex_unlock(&crtc->mutex);
8399                 return;
8400         }
8401
8402         /* Switch crtc and encoder back off if necessary */
8403         if (old->dpms_mode != DRM_MODE_DPMS_ON)
8404                 connector->funcs->dpms(connector, old->dpms_mode);
8405
8406         mutex_unlock(&crtc->mutex);
8407 }
8408
8409 static int i9xx_pll_refclk(struct drm_device *dev,
8410                            const struct intel_crtc_config *pipe_config)
8411 {
8412         struct drm_i915_private *dev_priv = dev->dev_private;
8413         u32 dpll = pipe_config->dpll_hw_state.dpll;
8414
8415         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8416                 return dev_priv->vbt.lvds_ssc_freq;
8417         else if (HAS_PCH_SPLIT(dev))
8418                 return 120000;
8419         else if (!IS_GEN2(dev))
8420                 return 96000;
8421         else
8422                 return 48000;
8423 }
8424
8425 /* Returns the clock of the currently programmed mode of the given pipe. */
8426 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8427                                 struct intel_crtc_config *pipe_config)
8428 {
8429         struct drm_device *dev = crtc->base.dev;
8430         struct drm_i915_private *dev_priv = dev->dev_private;
8431         int pipe = pipe_config->cpu_transcoder;
8432         u32 dpll = pipe_config->dpll_hw_state.dpll;
8433         u32 fp;
8434         intel_clock_t clock;
8435         int refclk = i9xx_pll_refclk(dev, pipe_config);
8436
8437         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8438                 fp = pipe_config->dpll_hw_state.fp0;
8439         else
8440                 fp = pipe_config->dpll_hw_state.fp1;
8441
8442         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8443         if (IS_PINEVIEW(dev)) {
8444                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8445                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8446         } else {
8447                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8448                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8449         }
8450
8451         if (!IS_GEN2(dev)) {
8452                 if (IS_PINEVIEW(dev))
8453                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8454                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8455                 else
8456                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8457                                DPLL_FPA01_P1_POST_DIV_SHIFT);
8458
8459                 switch (dpll & DPLL_MODE_MASK) {
8460                 case DPLLB_MODE_DAC_SERIAL:
8461                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8462                                 5 : 10;
8463                         break;
8464                 case DPLLB_MODE_LVDS:
8465                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8466                                 7 : 14;
8467                         break;
8468                 default:
8469                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8470                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
8471                         return;
8472                 }
8473
8474                 if (IS_PINEVIEW(dev))
8475                         pineview_clock(refclk, &clock);
8476                 else
8477                         i9xx_clock(refclk, &clock);
8478         } else {
8479                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8480                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8481
8482                 if (is_lvds) {
8483                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8484                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
8485
8486                         if (lvds & LVDS_CLKB_POWER_UP)
8487                                 clock.p2 = 7;
8488                         else
8489                                 clock.p2 = 14;
8490                 } else {
8491                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
8492                                 clock.p1 = 2;
8493                         else {
8494                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8495                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8496                         }
8497                         if (dpll & PLL_P2_DIVIDE_BY_4)
8498                                 clock.p2 = 4;
8499                         else
8500                                 clock.p2 = 2;
8501                 }
8502
8503                 i9xx_clock(refclk, &clock);
8504         }
8505
8506         /*
8507          * This value includes pixel_multiplier. We will use
8508          * port_clock to compute adjusted_mode.crtc_clock in the
8509          * encoder's get_config() function.
8510          */
8511         pipe_config->port_clock = clock.dot;
8512 }
8513
8514 int intel_dotclock_calculate(int link_freq,
8515                              const struct intel_link_m_n *m_n)
8516 {
8517         /*
8518          * The calculation for the data clock is:
8519          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8520          * But we want to avoid losing precison if possible, so:
8521          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8522          *
8523          * and the link clock is simpler:
8524          * link_clock = (m * link_clock) / n
8525          */
8526
8527         if (!m_n->link_n)
8528                 return 0;
8529
8530         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8531 }
8532
8533 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8534                                    struct intel_crtc_config *pipe_config)
8535 {
8536         struct drm_device *dev = crtc->base.dev;
8537
8538         /* read out port_clock from the DPLL */
8539         i9xx_crtc_clock_get(crtc, pipe_config);
8540
8541         /*
8542          * This value does not include pixel_multiplier.
8543          * We will check that port_clock and adjusted_mode.crtc_clock
8544          * agree once we know their relationship in the encoder's
8545          * get_config() function.
8546          */
8547         pipe_config->adjusted_mode.crtc_clock =
8548                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8549                                          &pipe_config->fdi_m_n);
8550 }
8551
8552 /** Returns the currently programmed mode of the given pipe. */
8553 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8554                                              struct drm_crtc *crtc)
8555 {
8556         struct drm_i915_private *dev_priv = dev->dev_private;
8557         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8558         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8559         struct drm_display_mode *mode;
8560         struct intel_crtc_config pipe_config;
8561         int htot = I915_READ(HTOTAL(cpu_transcoder));
8562         int hsync = I915_READ(HSYNC(cpu_transcoder));
8563         int vtot = I915_READ(VTOTAL(cpu_transcoder));
8564         int vsync = I915_READ(VSYNC(cpu_transcoder));
8565         enum pipe pipe = intel_crtc->pipe;
8566
8567         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8568         if (!mode)
8569                 return NULL;
8570
8571         /*
8572          * Construct a pipe_config sufficient for getting the clock info
8573          * back out of crtc_clock_get.
8574          *
8575          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8576          * to use a real value here instead.
8577          */
8578         pipe_config.cpu_transcoder = (enum transcoder) pipe;
8579         pipe_config.pixel_multiplier = 1;
8580         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8581         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8582         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8583         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8584
8585         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8586         mode->hdisplay = (htot & 0xffff) + 1;
8587         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8588         mode->hsync_start = (hsync & 0xffff) + 1;
8589         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8590         mode->vdisplay = (vtot & 0xffff) + 1;
8591         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8592         mode->vsync_start = (vsync & 0xffff) + 1;
8593         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8594
8595         drm_mode_set_name(mode);
8596
8597         return mode;
8598 }
8599
8600 static void intel_increase_pllclock(struct drm_crtc *crtc)
8601 {
8602         struct drm_device *dev = crtc->dev;
8603         struct drm_i915_private *dev_priv = dev->dev_private;
8604         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8605         int pipe = intel_crtc->pipe;
8606         int dpll_reg = DPLL(pipe);
8607         int dpll;
8608
8609         if (HAS_PCH_SPLIT(dev))
8610                 return;
8611
8612         if (!dev_priv->lvds_downclock_avail)
8613                 return;
8614
8615         dpll = I915_READ(dpll_reg);
8616         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8617                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8618
8619                 assert_panel_unlocked(dev_priv, pipe);
8620
8621                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8622                 I915_WRITE(dpll_reg, dpll);
8623                 intel_wait_for_vblank(dev, pipe);
8624
8625                 dpll = I915_READ(dpll_reg);
8626                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8627                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8628         }
8629 }
8630
8631 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8632 {
8633         struct drm_device *dev = crtc->dev;
8634         struct drm_i915_private *dev_priv = dev->dev_private;
8635         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8636
8637         if (HAS_PCH_SPLIT(dev))
8638                 return;
8639
8640         if (!dev_priv->lvds_downclock_avail)
8641                 return;
8642
8643         /*
8644          * Since this is called by a timer, we should never get here in
8645          * the manual case.
8646          */
8647         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8648                 int pipe = intel_crtc->pipe;
8649                 int dpll_reg = DPLL(pipe);
8650                 int dpll;
8651
8652                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8653
8654                 assert_panel_unlocked(dev_priv, pipe);
8655
8656                 dpll = I915_READ(dpll_reg);
8657                 dpll |= DISPLAY_RATE_SELECT_FPA1;
8658                 I915_WRITE(dpll_reg, dpll);
8659                 intel_wait_for_vblank(dev, pipe);
8660                 dpll = I915_READ(dpll_reg);
8661                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8662                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8663         }
8664
8665 }
8666
8667 void intel_mark_busy(struct drm_device *dev)
8668 {
8669         struct drm_i915_private *dev_priv = dev->dev_private;
8670
8671         if (dev_priv->mm.busy)
8672                 return;
8673
8674         intel_runtime_pm_get(dev_priv);
8675         i915_update_gfx_val(dev_priv);
8676         dev_priv->mm.busy = true;
8677 }
8678
8679 void intel_mark_idle(struct drm_device *dev)
8680 {
8681         struct drm_i915_private *dev_priv = dev->dev_private;
8682         struct drm_crtc *crtc;
8683
8684         if (!dev_priv->mm.busy)
8685                 return;
8686
8687         dev_priv->mm.busy = false;
8688
8689         if (!i915.powersave)
8690                 goto out;
8691
8692         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8693                 if (!crtc->primary->fb)
8694                         continue;
8695
8696                 intel_decrease_pllclock(crtc);
8697         }
8698
8699         if (INTEL_INFO(dev)->gen >= 6)
8700                 gen6_rps_idle(dev->dev_private);
8701
8702 out:
8703         intel_runtime_pm_put(dev_priv);
8704 }
8705
8706 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
8707                         struct intel_ring_buffer *ring)
8708 {
8709         struct drm_device *dev = obj->base.dev;
8710         struct drm_crtc *crtc;
8711
8712         if (!i915.powersave)
8713                 return;
8714
8715         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8716                 if (!crtc->primary->fb)
8717                         continue;
8718
8719                 if (to_intel_framebuffer(crtc->primary->fb)->obj != obj)
8720                         continue;
8721
8722                 intel_increase_pllclock(crtc);
8723                 if (ring && intel_fbc_enabled(dev))
8724                         ring->fbc_dirty = true;
8725         }
8726 }
8727
8728 static void intel_crtc_destroy(struct drm_crtc *crtc)
8729 {
8730         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8731         struct drm_device *dev = crtc->dev;
8732         struct intel_unpin_work *work;
8733         unsigned long flags;
8734
8735         spin_lock_irqsave(&dev->event_lock, flags);
8736         work = intel_crtc->unpin_work;
8737         intel_crtc->unpin_work = NULL;
8738         spin_unlock_irqrestore(&dev->event_lock, flags);
8739
8740         if (work) {
8741                 cancel_work_sync(&work->work);
8742                 kfree(work);
8743         }
8744
8745         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
8746
8747         drm_crtc_cleanup(crtc);
8748
8749         kfree(intel_crtc);
8750 }
8751
8752 static void intel_unpin_work_fn(struct work_struct *__work)
8753 {
8754         struct intel_unpin_work *work =
8755                 container_of(__work, struct intel_unpin_work, work);
8756         struct drm_device *dev = work->crtc->dev;
8757
8758         mutex_lock(&dev->struct_mutex);
8759         intel_unpin_fb_obj(work->old_fb_obj);
8760         drm_gem_object_unreference(&work->pending_flip_obj->base);
8761         drm_gem_object_unreference(&work->old_fb_obj->base);
8762
8763         intel_update_fbc(dev);
8764         mutex_unlock(&dev->struct_mutex);
8765
8766         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8767         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8768
8769         kfree(work);
8770 }
8771
8772 static void do_intel_finish_page_flip(struct drm_device *dev,
8773                                       struct drm_crtc *crtc)
8774 {
8775         struct drm_i915_private *dev_priv = dev->dev_private;
8776         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8777         struct intel_unpin_work *work;
8778         unsigned long flags;
8779
8780         /* Ignore early vblank irqs */
8781         if (intel_crtc == NULL)
8782                 return;
8783
8784         spin_lock_irqsave(&dev->event_lock, flags);
8785         work = intel_crtc->unpin_work;
8786
8787         /* Ensure we don't miss a work->pending update ... */
8788         smp_rmb();
8789
8790         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8791                 spin_unlock_irqrestore(&dev->event_lock, flags);
8792                 return;
8793         }
8794
8795         /* and that the unpin work is consistent wrt ->pending. */
8796         smp_rmb();
8797
8798         intel_crtc->unpin_work = NULL;
8799
8800         if (work->event)
8801                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
8802
8803         drm_vblank_put(dev, intel_crtc->pipe);
8804
8805         spin_unlock_irqrestore(&dev->event_lock, flags);
8806
8807         wake_up_all(&dev_priv->pending_flip_queue);
8808
8809         queue_work(dev_priv->wq, &work->work);
8810
8811         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
8812 }
8813
8814 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8815 {
8816         struct drm_i915_private *dev_priv = dev->dev_private;
8817         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8818
8819         do_intel_finish_page_flip(dev, crtc);
8820 }
8821
8822 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8823 {
8824         struct drm_i915_private *dev_priv = dev->dev_private;
8825         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8826
8827         do_intel_finish_page_flip(dev, crtc);
8828 }
8829
8830 void intel_prepare_page_flip(struct drm_device *dev, int plane)
8831 {
8832         struct drm_i915_private *dev_priv = dev->dev_private;
8833         struct intel_crtc *intel_crtc =
8834                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8835         unsigned long flags;
8836
8837         /* NB: An MMIO update of the plane base pointer will also
8838          * generate a page-flip completion irq, i.e. every modeset
8839          * is also accompanied by a spurious intel_prepare_page_flip().
8840          */
8841         spin_lock_irqsave(&dev->event_lock, flags);
8842         if (intel_crtc->unpin_work)
8843                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
8844         spin_unlock_irqrestore(&dev->event_lock, flags);
8845 }
8846
8847 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8848 {
8849         /* Ensure that the work item is consistent when activating it ... */
8850         smp_wmb();
8851         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8852         /* and that it is marked active as soon as the irq could fire. */
8853         smp_wmb();
8854 }
8855
8856 static int intel_gen2_queue_flip(struct drm_device *dev,
8857                                  struct drm_crtc *crtc,
8858                                  struct drm_framebuffer *fb,
8859                                  struct drm_i915_gem_object *obj,
8860                                  uint32_t flags)
8861 {
8862         struct drm_i915_private *dev_priv = dev->dev_private;
8863         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8864         u32 flip_mask;
8865         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8866         int ret;
8867
8868         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8869         if (ret)
8870                 goto err;
8871
8872         ret = intel_ring_begin(ring, 6);
8873         if (ret)
8874                 goto err_unpin;
8875
8876         /* Can't queue multiple flips, so wait for the previous
8877          * one to finish before executing the next.
8878          */
8879         if (intel_crtc->plane)
8880                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8881         else
8882                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8883         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8884         intel_ring_emit(ring, MI_NOOP);
8885         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8886                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8887         intel_ring_emit(ring, fb->pitches[0]);
8888         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8889         intel_ring_emit(ring, 0); /* aux display base address, unused */
8890
8891         intel_mark_page_flip_active(intel_crtc);
8892         __intel_ring_advance(ring);
8893         return 0;
8894
8895 err_unpin:
8896         intel_unpin_fb_obj(obj);
8897 err:
8898         return ret;
8899 }
8900
8901 static int intel_gen3_queue_flip(struct drm_device *dev,
8902                                  struct drm_crtc *crtc,
8903                                  struct drm_framebuffer *fb,
8904                                  struct drm_i915_gem_object *obj,
8905                                  uint32_t flags)
8906 {
8907         struct drm_i915_private *dev_priv = dev->dev_private;
8908         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8909         u32 flip_mask;
8910         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8911         int ret;
8912
8913         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8914         if (ret)
8915                 goto err;
8916
8917         ret = intel_ring_begin(ring, 6);
8918         if (ret)
8919                 goto err_unpin;
8920
8921         if (intel_crtc->plane)
8922                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8923         else
8924                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8925         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8926         intel_ring_emit(ring, MI_NOOP);
8927         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8928                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8929         intel_ring_emit(ring, fb->pitches[0]);
8930         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8931         intel_ring_emit(ring, MI_NOOP);
8932
8933         intel_mark_page_flip_active(intel_crtc);
8934         __intel_ring_advance(ring);
8935         return 0;
8936
8937 err_unpin:
8938         intel_unpin_fb_obj(obj);
8939 err:
8940         return ret;
8941 }
8942
8943 static int intel_gen4_queue_flip(struct drm_device *dev,
8944                                  struct drm_crtc *crtc,
8945                                  struct drm_framebuffer *fb,
8946                                  struct drm_i915_gem_object *obj,
8947                                  uint32_t flags)
8948 {
8949         struct drm_i915_private *dev_priv = dev->dev_private;
8950         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8951         uint32_t pf, pipesrc;
8952         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8953         int ret;
8954
8955         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8956         if (ret)
8957                 goto err;
8958
8959         ret = intel_ring_begin(ring, 4);
8960         if (ret)
8961                 goto err_unpin;
8962
8963         /* i965+ uses the linear or tiled offsets from the
8964          * Display Registers (which do not change across a page-flip)
8965          * so we need only reprogram the base address.
8966          */
8967         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8968                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8969         intel_ring_emit(ring, fb->pitches[0]);
8970         intel_ring_emit(ring,
8971                         (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
8972                         obj->tiling_mode);
8973
8974         /* XXX Enabling the panel-fitter across page-flip is so far
8975          * untested on non-native modes, so ignore it for now.
8976          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8977          */
8978         pf = 0;
8979         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8980         intel_ring_emit(ring, pf | pipesrc);
8981
8982         intel_mark_page_flip_active(intel_crtc);
8983         __intel_ring_advance(ring);
8984         return 0;
8985
8986 err_unpin:
8987         intel_unpin_fb_obj(obj);
8988 err:
8989         return ret;
8990 }
8991
8992 static int intel_gen6_queue_flip(struct drm_device *dev,
8993                                  struct drm_crtc *crtc,
8994                                  struct drm_framebuffer *fb,
8995                                  struct drm_i915_gem_object *obj,
8996                                  uint32_t flags)
8997 {
8998         struct drm_i915_private *dev_priv = dev->dev_private;
8999         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9000         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
9001         uint32_t pf, pipesrc;
9002         int ret;
9003
9004         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9005         if (ret)
9006                 goto err;
9007
9008         ret = intel_ring_begin(ring, 4);
9009         if (ret)
9010                 goto err_unpin;
9011
9012         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9013                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9014         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9015         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
9016
9017         /* Contrary to the suggestions in the documentation,
9018          * "Enable Panel Fitter" does not seem to be required when page
9019          * flipping with a non-native mode, and worse causes a normal
9020          * modeset to fail.
9021          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9022          */
9023         pf = 0;
9024         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9025         intel_ring_emit(ring, pf | pipesrc);
9026
9027         intel_mark_page_flip_active(intel_crtc);
9028         __intel_ring_advance(ring);
9029         return 0;
9030
9031 err_unpin:
9032         intel_unpin_fb_obj(obj);
9033 err:
9034         return ret;
9035 }
9036
9037 static int intel_gen7_queue_flip(struct drm_device *dev,
9038                                  struct drm_crtc *crtc,
9039                                  struct drm_framebuffer *fb,
9040                                  struct drm_i915_gem_object *obj,
9041                                  uint32_t flags)
9042 {
9043         struct drm_i915_private *dev_priv = dev->dev_private;
9044         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9045         struct intel_ring_buffer *ring;
9046         uint32_t plane_bit = 0;
9047         int len, ret;
9048
9049         ring = obj->ring;
9050         if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
9051                 ring = &dev_priv->ring[BCS];
9052
9053         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9054         if (ret)
9055                 goto err;
9056
9057         switch(intel_crtc->plane) {
9058         case PLANE_A:
9059                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9060                 break;
9061         case PLANE_B:
9062                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9063                 break;
9064         case PLANE_C:
9065                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9066                 break;
9067         default:
9068                 WARN_ONCE(1, "unknown plane in flip command\n");
9069                 ret = -ENODEV;
9070                 goto err_unpin;
9071         }
9072
9073         len = 4;
9074         if (ring->id == RCS) {
9075                 len += 6;
9076                 /*
9077                  * On Gen 8, SRM is now taking an extra dword to accommodate
9078                  * 48bits addresses, and we need a NOOP for the batch size to
9079                  * stay even.
9080                  */
9081                 if (IS_GEN8(dev))
9082                         len += 2;
9083         }
9084
9085         /*
9086          * BSpec MI_DISPLAY_FLIP for IVB:
9087          * "The full packet must be contained within the same cache line."
9088          *
9089          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9090          * cacheline, if we ever start emitting more commands before
9091          * the MI_DISPLAY_FLIP we may need to first emit everything else,
9092          * then do the cacheline alignment, and finally emit the
9093          * MI_DISPLAY_FLIP.
9094          */
9095         ret = intel_ring_cacheline_align(ring);
9096         if (ret)
9097                 goto err_unpin;
9098
9099         ret = intel_ring_begin(ring, len);
9100         if (ret)
9101                 goto err_unpin;
9102
9103         /* Unmask the flip-done completion message. Note that the bspec says that
9104          * we should do this for both the BCS and RCS, and that we must not unmask
9105          * more than one flip event at any time (or ensure that one flip message
9106          * can be sent by waiting for flip-done prior to queueing new flips).
9107          * Experimentation says that BCS works despite DERRMR masking all
9108          * flip-done completion events and that unmasking all planes at once
9109          * for the RCS also doesn't appear to drop events. Setting the DERRMR
9110          * to zero does lead to lockups within MI_DISPLAY_FLIP.
9111          */
9112         if (ring->id == RCS) {
9113                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9114                 intel_ring_emit(ring, DERRMR);
9115                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9116                                         DERRMR_PIPEB_PRI_FLIP_DONE |
9117                                         DERRMR_PIPEC_PRI_FLIP_DONE));
9118                 if (IS_GEN8(dev))
9119                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9120                                               MI_SRM_LRM_GLOBAL_GTT);
9121                 else
9122                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9123                                               MI_SRM_LRM_GLOBAL_GTT);
9124                 intel_ring_emit(ring, DERRMR);
9125                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9126                 if (IS_GEN8(dev)) {
9127                         intel_ring_emit(ring, 0);
9128                         intel_ring_emit(ring, MI_NOOP);
9129                 }
9130         }
9131
9132         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9133         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9134         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
9135         intel_ring_emit(ring, (MI_NOOP));
9136
9137         intel_mark_page_flip_active(intel_crtc);
9138         __intel_ring_advance(ring);
9139         return 0;
9140
9141 err_unpin:
9142         intel_unpin_fb_obj(obj);
9143 err:
9144         return ret;
9145 }
9146
9147 static int intel_default_queue_flip(struct drm_device *dev,
9148                                     struct drm_crtc *crtc,
9149                                     struct drm_framebuffer *fb,
9150                                     struct drm_i915_gem_object *obj,
9151                                     uint32_t flags)
9152 {
9153         return -ENODEV;
9154 }
9155
9156 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9157                                 struct drm_framebuffer *fb,
9158                                 struct drm_pending_vblank_event *event,
9159                                 uint32_t page_flip_flags)
9160 {
9161         struct drm_device *dev = crtc->dev;
9162         struct drm_i915_private *dev_priv = dev->dev_private;
9163         struct drm_framebuffer *old_fb = crtc->primary->fb;
9164         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
9165         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9166         struct intel_unpin_work *work;
9167         unsigned long flags;
9168         int ret;
9169
9170         /* Can't change pixel format via MI display flips. */
9171         if (fb->pixel_format != crtc->primary->fb->pixel_format)
9172                 return -EINVAL;
9173
9174         /*
9175          * TILEOFF/LINOFF registers can't be changed via MI display flips.
9176          * Note that pitch changes could also affect these register.
9177          */
9178         if (INTEL_INFO(dev)->gen > 3 &&
9179             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9180              fb->pitches[0] != crtc->primary->fb->pitches[0]))
9181                 return -EINVAL;
9182
9183         if (i915_terminally_wedged(&dev_priv->gpu_error))
9184                 goto out_hang;
9185
9186         work = kzalloc(sizeof(*work), GFP_KERNEL);
9187         if (work == NULL)
9188                 return -ENOMEM;
9189
9190         work->event = event;
9191         work->crtc = crtc;
9192         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
9193         INIT_WORK(&work->work, intel_unpin_work_fn);
9194
9195         ret = drm_vblank_get(dev, intel_crtc->pipe);
9196         if (ret)
9197                 goto free_work;
9198
9199         /* We borrow the event spin lock for protecting unpin_work */
9200         spin_lock_irqsave(&dev->event_lock, flags);
9201         if (intel_crtc->unpin_work) {
9202                 spin_unlock_irqrestore(&dev->event_lock, flags);
9203                 kfree(work);
9204                 drm_vblank_put(dev, intel_crtc->pipe);
9205
9206                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9207                 return -EBUSY;
9208         }
9209         intel_crtc->unpin_work = work;
9210         spin_unlock_irqrestore(&dev->event_lock, flags);
9211
9212         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9213                 flush_workqueue(dev_priv->wq);
9214
9215         ret = i915_mutex_lock_interruptible(dev);
9216         if (ret)
9217                 goto cleanup;
9218
9219         /* Reference the objects for the scheduled work. */
9220         drm_gem_object_reference(&work->old_fb_obj->base);
9221         drm_gem_object_reference(&obj->base);
9222
9223         crtc->primary->fb = fb;
9224
9225         work->pending_flip_obj = obj;
9226
9227         work->enable_stall_check = true;
9228
9229         atomic_inc(&intel_crtc->unpin_work_count);
9230         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9231
9232         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
9233         if (ret)
9234                 goto cleanup_pending;
9235
9236         intel_disable_fbc(dev);
9237         intel_mark_fb_busy(obj, NULL);
9238         mutex_unlock(&dev->struct_mutex);
9239
9240         trace_i915_flip_request(intel_crtc->plane, obj);
9241
9242         return 0;
9243
9244 cleanup_pending:
9245         atomic_dec(&intel_crtc->unpin_work_count);
9246         crtc->primary->fb = old_fb;
9247         drm_gem_object_unreference(&work->old_fb_obj->base);
9248         drm_gem_object_unreference(&obj->base);
9249         mutex_unlock(&dev->struct_mutex);
9250
9251 cleanup:
9252         spin_lock_irqsave(&dev->event_lock, flags);
9253         intel_crtc->unpin_work = NULL;
9254         spin_unlock_irqrestore(&dev->event_lock, flags);
9255
9256         drm_vblank_put(dev, intel_crtc->pipe);
9257 free_work:
9258         kfree(work);
9259
9260         if (ret == -EIO) {
9261 out_hang:
9262                 intel_crtc_wait_for_pending_flips(crtc);
9263                 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9264                 if (ret == 0 && event)
9265                         drm_send_vblank_event(dev, intel_crtc->pipe, event);
9266         }
9267         return ret;
9268 }
9269
9270 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9271         .mode_set_base_atomic = intel_pipe_set_base_atomic,
9272         .load_lut = intel_crtc_load_lut,
9273 };
9274
9275 /**
9276  * intel_modeset_update_staged_output_state
9277  *
9278  * Updates the staged output configuration state, e.g. after we've read out the
9279  * current hw state.
9280  */
9281 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9282 {
9283         struct intel_crtc *crtc;
9284         struct intel_encoder *encoder;
9285         struct intel_connector *connector;
9286
9287         list_for_each_entry(connector, &dev->mode_config.connector_list,
9288                             base.head) {
9289                 connector->new_encoder =
9290                         to_intel_encoder(connector->base.encoder);
9291         }
9292
9293         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9294                             base.head) {
9295                 encoder->new_crtc =
9296                         to_intel_crtc(encoder->base.crtc);
9297         }
9298
9299         for_each_intel_crtc(dev, crtc) {
9300                 crtc->new_enabled = crtc->base.enabled;
9301
9302                 if (crtc->new_enabled)
9303                         crtc->new_config = &crtc->config;
9304                 else
9305                         crtc->new_config = NULL;
9306         }
9307 }
9308
9309 /**
9310  * intel_modeset_commit_output_state
9311  *
9312  * This function copies the stage display pipe configuration to the real one.
9313  */
9314 static void intel_modeset_commit_output_state(struct drm_device *dev)
9315 {
9316         struct intel_crtc *crtc;
9317         struct intel_encoder *encoder;
9318         struct intel_connector *connector;
9319
9320         list_for_each_entry(connector, &dev->mode_config.connector_list,
9321                             base.head) {
9322                 connector->base.encoder = &connector->new_encoder->base;
9323         }
9324
9325         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9326                             base.head) {
9327                 encoder->base.crtc = &encoder->new_crtc->base;
9328         }
9329
9330         for_each_intel_crtc(dev, crtc) {
9331                 crtc->base.enabled = crtc->new_enabled;
9332         }
9333 }
9334
9335 static void
9336 connected_sink_compute_bpp(struct intel_connector * connector,
9337                            struct intel_crtc_config *pipe_config)
9338 {
9339         int bpp = pipe_config->pipe_bpp;
9340
9341         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9342                 connector->base.base.id,
9343                 drm_get_connector_name(&connector->base));
9344
9345         /* Don't use an invalid EDID bpc value */
9346         if (connector->base.display_info.bpc &&
9347             connector->base.display_info.bpc * 3 < bpp) {
9348                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9349                               bpp, connector->base.display_info.bpc*3);
9350                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9351         }
9352
9353         /* Clamp bpp to 8 on screens without EDID 1.4 */
9354         if (connector->base.display_info.bpc == 0 && bpp > 24) {
9355                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9356                               bpp);
9357                 pipe_config->pipe_bpp = 24;
9358         }
9359 }
9360
9361 static int
9362 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9363                           struct drm_framebuffer *fb,
9364                           struct intel_crtc_config *pipe_config)
9365 {
9366         struct drm_device *dev = crtc->base.dev;
9367         struct intel_connector *connector;
9368         int bpp;
9369
9370         switch (fb->pixel_format) {
9371         case DRM_FORMAT_C8:
9372                 bpp = 8*3; /* since we go through a colormap */
9373                 break;
9374         case DRM_FORMAT_XRGB1555:
9375         case DRM_FORMAT_ARGB1555:
9376                 /* checked in intel_framebuffer_init already */
9377                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9378                         return -EINVAL;
9379         case DRM_FORMAT_RGB565:
9380                 bpp = 6*3; /* min is 18bpp */
9381                 break;
9382         case DRM_FORMAT_XBGR8888:
9383         case DRM_FORMAT_ABGR8888:
9384                 /* checked in intel_framebuffer_init already */
9385                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9386                         return -EINVAL;
9387         case DRM_FORMAT_XRGB8888:
9388         case DRM_FORMAT_ARGB8888:
9389                 bpp = 8*3;
9390                 break;
9391         case DRM_FORMAT_XRGB2101010:
9392         case DRM_FORMAT_ARGB2101010:
9393         case DRM_FORMAT_XBGR2101010:
9394         case DRM_FORMAT_ABGR2101010:
9395                 /* checked in intel_framebuffer_init already */
9396                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9397                         return -EINVAL;
9398                 bpp = 10*3;
9399                 break;
9400         /* TODO: gen4+ supports 16 bpc floating point, too. */
9401         default:
9402                 DRM_DEBUG_KMS("unsupported depth\n");
9403                 return -EINVAL;
9404         }
9405
9406         pipe_config->pipe_bpp = bpp;
9407
9408         /* Clamp display bpp to EDID value */
9409         list_for_each_entry(connector, &dev->mode_config.connector_list,
9410                             base.head) {
9411                 if (!connector->new_encoder ||
9412                     connector->new_encoder->new_crtc != crtc)
9413                         continue;
9414
9415                 connected_sink_compute_bpp(connector, pipe_config);
9416         }
9417
9418         return bpp;
9419 }
9420
9421 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9422 {
9423         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9424                         "type: 0x%x flags: 0x%x\n",
9425                 mode->crtc_clock,
9426                 mode->crtc_hdisplay, mode->crtc_hsync_start,
9427                 mode->crtc_hsync_end, mode->crtc_htotal,
9428                 mode->crtc_vdisplay, mode->crtc_vsync_start,
9429                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9430 }
9431
9432 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9433                                    struct intel_crtc_config *pipe_config,
9434                                    const char *context)
9435 {
9436         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9437                       context, pipe_name(crtc->pipe));
9438
9439         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9440         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9441                       pipe_config->pipe_bpp, pipe_config->dither);
9442         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9443                       pipe_config->has_pch_encoder,
9444                       pipe_config->fdi_lanes,
9445                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9446                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9447                       pipe_config->fdi_m_n.tu);
9448         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9449                       pipe_config->has_dp_encoder,
9450                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9451                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9452                       pipe_config->dp_m_n.tu);
9453         DRM_DEBUG_KMS("requested mode:\n");
9454         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9455         DRM_DEBUG_KMS("adjusted mode:\n");
9456         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9457         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9458         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9459         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9460                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9461         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9462                       pipe_config->gmch_pfit.control,
9463                       pipe_config->gmch_pfit.pgm_ratios,
9464                       pipe_config->gmch_pfit.lvds_border_bits);
9465         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9466                       pipe_config->pch_pfit.pos,
9467                       pipe_config->pch_pfit.size,
9468                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9469         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9470         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
9471 }
9472
9473 static bool encoders_cloneable(const struct intel_encoder *a,
9474                                const struct intel_encoder *b)
9475 {
9476         /* masks could be asymmetric, so check both ways */
9477         return a == b || (a->cloneable & (1 << b->type) &&
9478                           b->cloneable & (1 << a->type));
9479 }
9480
9481 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9482                                          struct intel_encoder *encoder)
9483 {
9484         struct drm_device *dev = crtc->base.dev;
9485         struct intel_encoder *source_encoder;
9486
9487         list_for_each_entry(source_encoder,
9488                             &dev->mode_config.encoder_list, base.head) {
9489                 if (source_encoder->new_crtc != crtc)
9490                         continue;
9491
9492                 if (!encoders_cloneable(encoder, source_encoder))
9493                         return false;
9494         }
9495
9496         return true;
9497 }
9498
9499 static bool check_encoder_cloning(struct intel_crtc *crtc)
9500 {
9501         struct drm_device *dev = crtc->base.dev;
9502         struct intel_encoder *encoder;
9503
9504         list_for_each_entry(encoder,
9505                             &dev->mode_config.encoder_list, base.head) {
9506                 if (encoder->new_crtc != crtc)
9507                         continue;
9508
9509                 if (!check_single_encoder_cloning(crtc, encoder))
9510                         return false;
9511         }
9512
9513         return true;
9514 }
9515
9516 static struct intel_crtc_config *
9517 intel_modeset_pipe_config(struct drm_crtc *crtc,
9518                           struct drm_framebuffer *fb,
9519                           struct drm_display_mode *mode)
9520 {
9521         struct drm_device *dev = crtc->dev;
9522         struct intel_encoder *encoder;
9523         struct intel_crtc_config *pipe_config;
9524         int plane_bpp, ret = -EINVAL;
9525         bool retry = true;
9526
9527         if (!check_encoder_cloning(to_intel_crtc(crtc))) {
9528                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
9529                 return ERR_PTR(-EINVAL);
9530         }
9531
9532         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9533         if (!pipe_config)
9534                 return ERR_PTR(-ENOMEM);
9535
9536         drm_mode_copy(&pipe_config->adjusted_mode, mode);
9537         drm_mode_copy(&pipe_config->requested_mode, mode);
9538
9539         pipe_config->cpu_transcoder =
9540                 (enum transcoder) to_intel_crtc(crtc)->pipe;
9541         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9542
9543         /*
9544          * Sanitize sync polarity flags based on requested ones. If neither
9545          * positive or negative polarity is requested, treat this as meaning
9546          * negative polarity.
9547          */
9548         if (!(pipe_config->adjusted_mode.flags &
9549               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
9550                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
9551
9552         if (!(pipe_config->adjusted_mode.flags &
9553               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
9554                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
9555
9556         /* Compute a starting value for pipe_config->pipe_bpp taking the source
9557          * plane pixel format and any sink constraints into account. Returns the
9558          * source plane bpp so that dithering can be selected on mismatches
9559          * after encoders and crtc also have had their say. */
9560         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
9561                                               fb, pipe_config);
9562         if (plane_bpp < 0)
9563                 goto fail;
9564
9565         /*
9566          * Determine the real pipe dimensions. Note that stereo modes can
9567          * increase the actual pipe size due to the frame doubling and
9568          * insertion of additional space for blanks between the frame. This
9569          * is stored in the crtc timings. We use the requested mode to do this
9570          * computation to clearly distinguish it from the adjusted mode, which
9571          * can be changed by the connectors in the below retry loop.
9572          */
9573         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
9574         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
9575         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
9576
9577 encoder_retry:
9578         /* Ensure the port clock defaults are reset when retrying. */
9579         pipe_config->port_clock = 0;
9580         pipe_config->pixel_multiplier = 1;
9581
9582         /* Fill in default crtc timings, allow encoders to overwrite them. */
9583         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
9584
9585         /* Pass our mode to the connectors and the CRTC to give them a chance to
9586          * adjust it according to limitations or connector properties, and also
9587          * a chance to reject the mode entirely.
9588          */
9589         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9590                             base.head) {
9591
9592                 if (&encoder->new_crtc->base != crtc)
9593                         continue;
9594
9595                 if (!(encoder->compute_config(encoder, pipe_config))) {
9596                         DRM_DEBUG_KMS("Encoder config failure\n");
9597                         goto fail;
9598                 }
9599         }
9600
9601         /* Set default port clock if not overwritten by the encoder. Needs to be
9602          * done afterwards in case the encoder adjusts the mode. */
9603         if (!pipe_config->port_clock)
9604                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
9605                         * pipe_config->pixel_multiplier;
9606
9607         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
9608         if (ret < 0) {
9609                 DRM_DEBUG_KMS("CRTC fixup failed\n");
9610                 goto fail;
9611         }
9612
9613         if (ret == RETRY) {
9614                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
9615                         ret = -EINVAL;
9616                         goto fail;
9617                 }
9618
9619                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9620                 retry = false;
9621                 goto encoder_retry;
9622         }
9623
9624         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
9625         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9626                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
9627
9628         return pipe_config;
9629 fail:
9630         kfree(pipe_config);
9631         return ERR_PTR(ret);
9632 }
9633
9634 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
9635  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9636 static void
9637 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
9638                              unsigned *prepare_pipes, unsigned *disable_pipes)
9639 {
9640         struct intel_crtc *intel_crtc;
9641         struct drm_device *dev = crtc->dev;
9642         struct intel_encoder *encoder;
9643         struct intel_connector *connector;
9644         struct drm_crtc *tmp_crtc;
9645
9646         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
9647
9648         /* Check which crtcs have changed outputs connected to them, these need
9649          * to be part of the prepare_pipes mask. We don't (yet) support global
9650          * modeset across multiple crtcs, so modeset_pipes will only have one
9651          * bit set at most. */
9652         list_for_each_entry(connector, &dev->mode_config.connector_list,
9653                             base.head) {
9654                 if (connector->base.encoder == &connector->new_encoder->base)
9655                         continue;
9656
9657                 if (connector->base.encoder) {
9658                         tmp_crtc = connector->base.encoder->crtc;
9659
9660                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9661                 }
9662
9663                 if (connector->new_encoder)
9664                         *prepare_pipes |=
9665                                 1 << connector->new_encoder->new_crtc->pipe;
9666         }
9667
9668         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9669                             base.head) {
9670                 if (encoder->base.crtc == &encoder->new_crtc->base)
9671                         continue;
9672
9673                 if (encoder->base.crtc) {
9674                         tmp_crtc = encoder->base.crtc;
9675
9676                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9677                 }
9678
9679                 if (encoder->new_crtc)
9680                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
9681         }
9682
9683         /* Check for pipes that will be enabled/disabled ... */
9684         for_each_intel_crtc(dev, intel_crtc) {
9685                 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
9686                         continue;
9687
9688                 if (!intel_crtc->new_enabled)
9689                         *disable_pipes |= 1 << intel_crtc->pipe;
9690                 else
9691                         *prepare_pipes |= 1 << intel_crtc->pipe;
9692         }
9693
9694
9695         /* set_mode is also used to update properties on life display pipes. */
9696         intel_crtc = to_intel_crtc(crtc);
9697         if (intel_crtc->new_enabled)
9698                 *prepare_pipes |= 1 << intel_crtc->pipe;
9699
9700         /*
9701          * For simplicity do a full modeset on any pipe where the output routing
9702          * changed. We could be more clever, but that would require us to be
9703          * more careful with calling the relevant encoder->mode_set functions.
9704          */
9705         if (*prepare_pipes)
9706                 *modeset_pipes = *prepare_pipes;
9707
9708         /* ... and mask these out. */
9709         *modeset_pipes &= ~(*disable_pipes);
9710         *prepare_pipes &= ~(*disable_pipes);
9711
9712         /*
9713          * HACK: We don't (yet) fully support global modesets. intel_set_config
9714          * obies this rule, but the modeset restore mode of
9715          * intel_modeset_setup_hw_state does not.
9716          */
9717         *modeset_pipes &= 1 << intel_crtc->pipe;
9718         *prepare_pipes &= 1 << intel_crtc->pipe;
9719
9720         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9721                       *modeset_pipes, *prepare_pipes, *disable_pipes);
9722 }
9723
9724 static bool intel_crtc_in_use(struct drm_crtc *crtc)
9725 {
9726         struct drm_encoder *encoder;
9727         struct drm_device *dev = crtc->dev;
9728
9729         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
9730                 if (encoder->crtc == crtc)
9731                         return true;
9732
9733         return false;
9734 }
9735
9736 static void
9737 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
9738 {
9739         struct intel_encoder *intel_encoder;
9740         struct intel_crtc *intel_crtc;
9741         struct drm_connector *connector;
9742
9743         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
9744                             base.head) {
9745                 if (!intel_encoder->base.crtc)
9746                         continue;
9747
9748                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
9749
9750                 if (prepare_pipes & (1 << intel_crtc->pipe))
9751                         intel_encoder->connectors_active = false;
9752         }
9753
9754         intel_modeset_commit_output_state(dev);
9755
9756         /* Double check state. */
9757         for_each_intel_crtc(dev, intel_crtc) {
9758                 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
9759                 WARN_ON(intel_crtc->new_config &&
9760                         intel_crtc->new_config != &intel_crtc->config);
9761                 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
9762         }
9763
9764         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9765                 if (!connector->encoder || !connector->encoder->crtc)
9766                         continue;
9767
9768                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
9769
9770                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
9771                         struct drm_property *dpms_property =
9772                                 dev->mode_config.dpms_property;
9773
9774                         connector->dpms = DRM_MODE_DPMS_ON;
9775                         drm_object_property_set_value(&connector->base,
9776                                                          dpms_property,
9777                                                          DRM_MODE_DPMS_ON);
9778
9779                         intel_encoder = to_intel_encoder(connector->encoder);
9780                         intel_encoder->connectors_active = true;
9781                 }
9782         }
9783
9784 }
9785
9786 static bool intel_fuzzy_clock_check(int clock1, int clock2)
9787 {
9788         int diff;
9789
9790         if (clock1 == clock2)
9791                 return true;
9792
9793         if (!clock1 || !clock2)
9794                 return false;
9795
9796         diff = abs(clock1 - clock2);
9797
9798         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
9799                 return true;
9800
9801         return false;
9802 }
9803
9804 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9805         list_for_each_entry((intel_crtc), \
9806                             &(dev)->mode_config.crtc_list, \
9807                             base.head) \
9808                 if (mask & (1 <<(intel_crtc)->pipe))
9809
9810 static bool
9811 intel_pipe_config_compare(struct drm_device *dev,
9812                           struct intel_crtc_config *current_config,
9813                           struct intel_crtc_config *pipe_config)
9814 {
9815 #define PIPE_CONF_CHECK_X(name) \
9816         if (current_config->name != pipe_config->name) { \
9817                 DRM_ERROR("mismatch in " #name " " \
9818                           "(expected 0x%08x, found 0x%08x)\n", \
9819                           current_config->name, \
9820                           pipe_config->name); \
9821                 return false; \
9822         }
9823
9824 #define PIPE_CONF_CHECK_I(name) \
9825         if (current_config->name != pipe_config->name) { \
9826                 DRM_ERROR("mismatch in " #name " " \
9827                           "(expected %i, found %i)\n", \
9828                           current_config->name, \
9829                           pipe_config->name); \
9830                 return false; \
9831         }
9832
9833 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
9834         if ((current_config->name ^ pipe_config->name) & (mask)) { \
9835                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
9836                           "(expected %i, found %i)\n", \
9837                           current_config->name & (mask), \
9838                           pipe_config->name & (mask)); \
9839                 return false; \
9840         }
9841
9842 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9843         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9844                 DRM_ERROR("mismatch in " #name " " \
9845                           "(expected %i, found %i)\n", \
9846                           current_config->name, \
9847                           pipe_config->name); \
9848                 return false; \
9849         }
9850
9851 #define PIPE_CONF_QUIRK(quirk)  \
9852         ((current_config->quirks | pipe_config->quirks) & (quirk))
9853
9854         PIPE_CONF_CHECK_I(cpu_transcoder);
9855
9856         PIPE_CONF_CHECK_I(has_pch_encoder);
9857         PIPE_CONF_CHECK_I(fdi_lanes);
9858         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9859         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9860         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9861         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9862         PIPE_CONF_CHECK_I(fdi_m_n.tu);
9863
9864         PIPE_CONF_CHECK_I(has_dp_encoder);
9865         PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9866         PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9867         PIPE_CONF_CHECK_I(dp_m_n.link_m);
9868         PIPE_CONF_CHECK_I(dp_m_n.link_n);
9869         PIPE_CONF_CHECK_I(dp_m_n.tu);
9870
9871         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9872         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9873         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9874         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9875         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9876         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9877
9878         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9879         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9880         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9881         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9882         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9883         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9884
9885         PIPE_CONF_CHECK_I(pixel_multiplier);
9886
9887         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9888                               DRM_MODE_FLAG_INTERLACE);
9889
9890         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9891                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9892                                       DRM_MODE_FLAG_PHSYNC);
9893                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9894                                       DRM_MODE_FLAG_NHSYNC);
9895                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9896                                       DRM_MODE_FLAG_PVSYNC);
9897                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9898                                       DRM_MODE_FLAG_NVSYNC);
9899         }
9900
9901         PIPE_CONF_CHECK_I(pipe_src_w);
9902         PIPE_CONF_CHECK_I(pipe_src_h);
9903
9904         /*
9905          * FIXME: BIOS likes to set up a cloned config with lvds+external
9906          * screen. Since we don't yet re-compute the pipe config when moving
9907          * just the lvds port away to another pipe the sw tracking won't match.
9908          *
9909          * Proper atomic modesets with recomputed global state will fix this.
9910          * Until then just don't check gmch state for inherited modes.
9911          */
9912         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
9913                 PIPE_CONF_CHECK_I(gmch_pfit.control);
9914                 /* pfit ratios are autocomputed by the hw on gen4+ */
9915                 if (INTEL_INFO(dev)->gen < 4)
9916                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9917                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9918         }
9919
9920         PIPE_CONF_CHECK_I(pch_pfit.enabled);
9921         if (current_config->pch_pfit.enabled) {
9922                 PIPE_CONF_CHECK_I(pch_pfit.pos);
9923                 PIPE_CONF_CHECK_I(pch_pfit.size);
9924         }
9925
9926         /* BDW+ don't expose a synchronous way to read the state */
9927         if (IS_HASWELL(dev))
9928                 PIPE_CONF_CHECK_I(ips_enabled);
9929
9930         PIPE_CONF_CHECK_I(double_wide);
9931
9932         PIPE_CONF_CHECK_I(shared_dpll);
9933         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
9934         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
9935         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
9936         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
9937
9938         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
9939                 PIPE_CONF_CHECK_I(pipe_bpp);
9940
9941         PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
9942         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
9943
9944 #undef PIPE_CONF_CHECK_X
9945 #undef PIPE_CONF_CHECK_I
9946 #undef PIPE_CONF_CHECK_FLAGS
9947 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
9948 #undef PIPE_CONF_QUIRK
9949
9950         return true;
9951 }
9952
9953 static void
9954 check_connector_state(struct drm_device *dev)
9955 {
9956         struct intel_connector *connector;
9957
9958         list_for_each_entry(connector, &dev->mode_config.connector_list,
9959                             base.head) {
9960                 /* This also checks the encoder/connector hw state with the
9961                  * ->get_hw_state callbacks. */
9962                 intel_connector_check_state(connector);
9963
9964                 WARN(&connector->new_encoder->base != connector->base.encoder,
9965                      "connector's staged encoder doesn't match current encoder\n");
9966         }
9967 }
9968
9969 static void
9970 check_encoder_state(struct drm_device *dev)
9971 {
9972         struct intel_encoder *encoder;
9973         struct intel_connector *connector;
9974
9975         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9976                             base.head) {
9977                 bool enabled = false;
9978                 bool active = false;
9979                 enum pipe pipe, tracked_pipe;
9980
9981                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
9982                               encoder->base.base.id,
9983                               drm_get_encoder_name(&encoder->base));
9984
9985                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
9986                      "encoder's stage crtc doesn't match current crtc\n");
9987                 WARN(encoder->connectors_active && !encoder->base.crtc,
9988                      "encoder's active_connectors set, but no crtc\n");
9989
9990                 list_for_each_entry(connector, &dev->mode_config.connector_list,
9991                                     base.head) {
9992                         if (connector->base.encoder != &encoder->base)
9993                                 continue;
9994                         enabled = true;
9995                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
9996                                 active = true;
9997                 }
9998                 WARN(!!encoder->base.crtc != enabled,
9999                      "encoder's enabled state mismatch "
10000                      "(expected %i, found %i)\n",
10001                      !!encoder->base.crtc, enabled);
10002                 WARN(active && !encoder->base.crtc,
10003                      "active encoder with no crtc\n");
10004
10005                 WARN(encoder->connectors_active != active,
10006                      "encoder's computed active state doesn't match tracked active state "
10007                      "(expected %i, found %i)\n", active, encoder->connectors_active);
10008
10009                 active = encoder->get_hw_state(encoder, &pipe);
10010                 WARN(active != encoder->connectors_active,
10011                      "encoder's hw state doesn't match sw tracking "
10012                      "(expected %i, found %i)\n",
10013                      encoder->connectors_active, active);
10014
10015                 if (!encoder->base.crtc)
10016                         continue;
10017
10018                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10019                 WARN(active && pipe != tracked_pipe,
10020                      "active encoder's pipe doesn't match"
10021                      "(expected %i, found %i)\n",
10022                      tracked_pipe, pipe);
10023
10024         }
10025 }
10026
10027 static void
10028 check_crtc_state(struct drm_device *dev)
10029 {
10030         struct drm_i915_private *dev_priv = dev->dev_private;
10031         struct intel_crtc *crtc;
10032         struct intel_encoder *encoder;
10033         struct intel_crtc_config pipe_config;
10034
10035         for_each_intel_crtc(dev, crtc) {
10036                 bool enabled = false;
10037                 bool active = false;
10038
10039                 memset(&pipe_config, 0, sizeof(pipe_config));
10040
10041                 DRM_DEBUG_KMS("[CRTC:%d]\n",
10042                               crtc->base.base.id);
10043
10044                 WARN(crtc->active && !crtc->base.enabled,
10045                      "active crtc, but not enabled in sw tracking\n");
10046
10047                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10048                                     base.head) {
10049                         if (encoder->base.crtc != &crtc->base)
10050                                 continue;
10051                         enabled = true;
10052                         if (encoder->connectors_active)
10053                                 active = true;
10054                 }
10055
10056                 WARN(active != crtc->active,
10057                      "crtc's computed active state doesn't match tracked active state "
10058                      "(expected %i, found %i)\n", active, crtc->active);
10059                 WARN(enabled != crtc->base.enabled,
10060                      "crtc's computed enabled state doesn't match tracked enabled state "
10061                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10062
10063                 active = dev_priv->display.get_pipe_config(crtc,
10064                                                            &pipe_config);
10065
10066                 /* hw state is inconsistent with the pipe A quirk */
10067                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
10068                         active = crtc->active;
10069
10070                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10071                                     base.head) {
10072                         enum pipe pipe;
10073                         if (encoder->base.crtc != &crtc->base)
10074                                 continue;
10075                         if (encoder->get_hw_state(encoder, &pipe))
10076                                 encoder->get_config(encoder, &pipe_config);
10077                 }
10078
10079                 WARN(crtc->active != active,
10080                      "crtc active state doesn't match with hw state "
10081                      "(expected %i, found %i)\n", crtc->active, active);
10082
10083                 if (active &&
10084                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10085                         WARN(1, "pipe state doesn't match!\n");
10086                         intel_dump_pipe_config(crtc, &pipe_config,
10087                                                "[hw state]");
10088                         intel_dump_pipe_config(crtc, &crtc->config,
10089                                                "[sw state]");
10090                 }
10091         }
10092 }
10093
10094 static void
10095 check_shared_dpll_state(struct drm_device *dev)
10096 {
10097         struct drm_i915_private *dev_priv = dev->dev_private;
10098         struct intel_crtc *crtc;
10099         struct intel_dpll_hw_state dpll_hw_state;
10100         int i;
10101
10102         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10103                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10104                 int enabled_crtcs = 0, active_crtcs = 0;
10105                 bool active;
10106
10107                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10108
10109                 DRM_DEBUG_KMS("%s\n", pll->name);
10110
10111                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10112
10113                 WARN(pll->active > pll->refcount,
10114                      "more active pll users than references: %i vs %i\n",
10115                      pll->active, pll->refcount);
10116                 WARN(pll->active && !pll->on,
10117                      "pll in active use but not on in sw tracking\n");
10118                 WARN(pll->on && !pll->active,
10119                      "pll in on but not on in use in sw tracking\n");
10120                 WARN(pll->on != active,
10121                      "pll on state mismatch (expected %i, found %i)\n",
10122                      pll->on, active);
10123
10124                 for_each_intel_crtc(dev, crtc) {
10125                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10126                                 enabled_crtcs++;
10127                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10128                                 active_crtcs++;
10129                 }
10130                 WARN(pll->active != active_crtcs,
10131                      "pll active crtcs mismatch (expected %i, found %i)\n",
10132                      pll->active, active_crtcs);
10133                 WARN(pll->refcount != enabled_crtcs,
10134                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
10135                      pll->refcount, enabled_crtcs);
10136
10137                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10138                                        sizeof(dpll_hw_state)),
10139                      "pll hw state mismatch\n");
10140         }
10141 }
10142
10143 void
10144 intel_modeset_check_state(struct drm_device *dev)
10145 {
10146         check_connector_state(dev);
10147         check_encoder_state(dev);
10148         check_crtc_state(dev);
10149         check_shared_dpll_state(dev);
10150 }
10151
10152 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10153                                      int dotclock)
10154 {
10155         /*
10156          * FDI already provided one idea for the dotclock.
10157          * Yell if the encoder disagrees.
10158          */
10159         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10160              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10161              pipe_config->adjusted_mode.crtc_clock, dotclock);
10162 }
10163
10164 static int __intel_set_mode(struct drm_crtc *crtc,
10165                             struct drm_display_mode *mode,
10166                             int x, int y, struct drm_framebuffer *fb)
10167 {
10168         struct drm_device *dev = crtc->dev;
10169         struct drm_i915_private *dev_priv = dev->dev_private;
10170         struct drm_display_mode *saved_mode;
10171         struct intel_crtc_config *pipe_config = NULL;
10172         struct intel_crtc *intel_crtc;
10173         unsigned disable_pipes, prepare_pipes, modeset_pipes;
10174         int ret = 0;
10175
10176         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10177         if (!saved_mode)
10178                 return -ENOMEM;
10179
10180         intel_modeset_affected_pipes(crtc, &modeset_pipes,
10181                                      &prepare_pipes, &disable_pipes);
10182
10183         *saved_mode = crtc->mode;
10184
10185         /* Hack: Because we don't (yet) support global modeset on multiple
10186          * crtcs, we don't keep track of the new mode for more than one crtc.
10187          * Hence simply check whether any bit is set in modeset_pipes in all the
10188          * pieces of code that are not yet converted to deal with mutliple crtcs
10189          * changing their mode at the same time. */
10190         if (modeset_pipes) {
10191                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10192                 if (IS_ERR(pipe_config)) {
10193                         ret = PTR_ERR(pipe_config);
10194                         pipe_config = NULL;
10195
10196                         goto out;
10197                 }
10198                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10199                                        "[modeset]");
10200                 to_intel_crtc(crtc)->new_config = pipe_config;
10201         }
10202
10203         /*
10204          * See if the config requires any additional preparation, e.g.
10205          * to adjust global state with pipes off.  We need to do this
10206          * here so we can get the modeset_pipe updated config for the new
10207          * mode set on this crtc.  For other crtcs we need to use the
10208          * adjusted_mode bits in the crtc directly.
10209          */
10210         if (IS_VALLEYVIEW(dev)) {
10211                 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10212
10213                 /* may have added more to prepare_pipes than we should */
10214                 prepare_pipes &= ~disable_pipes;
10215         }
10216
10217         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10218                 intel_crtc_disable(&intel_crtc->base);
10219
10220         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10221                 if (intel_crtc->base.enabled)
10222                         dev_priv->display.crtc_disable(&intel_crtc->base);
10223         }
10224
10225         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10226          * to set it here already despite that we pass it down the callchain.
10227          */
10228         if (modeset_pipes) {
10229                 crtc->mode = *mode;
10230                 /* mode_set/enable/disable functions rely on a correct pipe
10231                  * config. */
10232                 to_intel_crtc(crtc)->config = *pipe_config;
10233                 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10234
10235                 /*
10236                  * Calculate and store various constants which
10237                  * are later needed by vblank and swap-completion
10238                  * timestamping. They are derived from true hwmode.
10239                  */
10240                 drm_calc_timestamping_constants(crtc,
10241                                                 &pipe_config->adjusted_mode);
10242         }
10243
10244         /* Only after disabling all output pipelines that will be changed can we
10245          * update the the output configuration. */
10246         intel_modeset_update_state(dev, prepare_pipes);
10247
10248         if (dev_priv->display.modeset_global_resources)
10249                 dev_priv->display.modeset_global_resources(dev);
10250
10251         /* Set up the DPLL and any encoders state that needs to adjust or depend
10252          * on the DPLL.
10253          */
10254         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10255                 ret = intel_crtc_mode_set(&intel_crtc->base,
10256                                           x, y, fb);
10257                 if (ret)
10258                         goto done;
10259         }
10260
10261         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10262         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
10263                 dev_priv->display.crtc_enable(&intel_crtc->base);
10264
10265         /* FIXME: add subpixel order */
10266 done:
10267         if (ret && crtc->enabled)
10268                 crtc->mode = *saved_mode;
10269
10270 out:
10271         kfree(pipe_config);
10272         kfree(saved_mode);
10273         return ret;
10274 }
10275
10276 static int intel_set_mode(struct drm_crtc *crtc,
10277                           struct drm_display_mode *mode,
10278                           int x, int y, struct drm_framebuffer *fb)
10279 {
10280         int ret;
10281
10282         ret = __intel_set_mode(crtc, mode, x, y, fb);
10283
10284         if (ret == 0)
10285                 intel_modeset_check_state(crtc->dev);
10286
10287         return ret;
10288 }
10289
10290 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10291 {
10292         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10293 }
10294
10295 #undef for_each_intel_crtc_masked
10296
10297 static void intel_set_config_free(struct intel_set_config *config)
10298 {
10299         if (!config)
10300                 return;
10301
10302         kfree(config->save_connector_encoders);
10303         kfree(config->save_encoder_crtcs);
10304         kfree(config->save_crtc_enabled);
10305         kfree(config);
10306 }
10307
10308 static int intel_set_config_save_state(struct drm_device *dev,
10309                                        struct intel_set_config *config)
10310 {
10311         struct drm_crtc *crtc;
10312         struct drm_encoder *encoder;
10313         struct drm_connector *connector;
10314         int count;
10315
10316         config->save_crtc_enabled =
10317                 kcalloc(dev->mode_config.num_crtc,
10318                         sizeof(bool), GFP_KERNEL);
10319         if (!config->save_crtc_enabled)
10320                 return -ENOMEM;
10321
10322         config->save_encoder_crtcs =
10323                 kcalloc(dev->mode_config.num_encoder,
10324                         sizeof(struct drm_crtc *), GFP_KERNEL);
10325         if (!config->save_encoder_crtcs)
10326                 return -ENOMEM;
10327
10328         config->save_connector_encoders =
10329                 kcalloc(dev->mode_config.num_connector,
10330                         sizeof(struct drm_encoder *), GFP_KERNEL);
10331         if (!config->save_connector_encoders)
10332                 return -ENOMEM;
10333
10334         /* Copy data. Note that driver private data is not affected.
10335          * Should anything bad happen only the expected state is
10336          * restored, not the drivers personal bookkeeping.
10337          */
10338         count = 0;
10339         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10340                 config->save_crtc_enabled[count++] = crtc->enabled;
10341         }
10342
10343         count = 0;
10344         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10345                 config->save_encoder_crtcs[count++] = encoder->crtc;
10346         }
10347
10348         count = 0;
10349         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10350                 config->save_connector_encoders[count++] = connector->encoder;
10351         }
10352
10353         return 0;
10354 }
10355
10356 static void intel_set_config_restore_state(struct drm_device *dev,
10357                                            struct intel_set_config *config)
10358 {
10359         struct intel_crtc *crtc;
10360         struct intel_encoder *encoder;
10361         struct intel_connector *connector;
10362         int count;
10363
10364         count = 0;
10365         for_each_intel_crtc(dev, crtc) {
10366                 crtc->new_enabled = config->save_crtc_enabled[count++];
10367
10368                 if (crtc->new_enabled)
10369                         crtc->new_config = &crtc->config;
10370                 else
10371                         crtc->new_config = NULL;
10372         }
10373
10374         count = 0;
10375         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10376                 encoder->new_crtc =
10377                         to_intel_crtc(config->save_encoder_crtcs[count++]);
10378         }
10379
10380         count = 0;
10381         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10382                 connector->new_encoder =
10383                         to_intel_encoder(config->save_connector_encoders[count++]);
10384         }
10385 }
10386
10387 static bool
10388 is_crtc_connector_off(struct drm_mode_set *set)
10389 {
10390         int i;
10391
10392         if (set->num_connectors == 0)
10393                 return false;
10394
10395         if (WARN_ON(set->connectors == NULL))
10396                 return false;
10397
10398         for (i = 0; i < set->num_connectors; i++)
10399                 if (set->connectors[i]->encoder &&
10400                     set->connectors[i]->encoder->crtc == set->crtc &&
10401                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
10402                         return true;
10403
10404         return false;
10405 }
10406
10407 static void
10408 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
10409                                       struct intel_set_config *config)
10410 {
10411
10412         /* We should be able to check here if the fb has the same properties
10413          * and then just flip_or_move it */
10414         if (is_crtc_connector_off(set)) {
10415                 config->mode_changed = true;
10416         } else if (set->crtc->primary->fb != set->fb) {
10417                 /* If we have no fb then treat it as a full mode set */
10418                 if (set->crtc->primary->fb == NULL) {
10419                         struct intel_crtc *intel_crtc =
10420                                 to_intel_crtc(set->crtc);
10421
10422                         if (intel_crtc->active && i915.fastboot) {
10423                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
10424                                 config->fb_changed = true;
10425                         } else {
10426                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
10427                                 config->mode_changed = true;
10428                         }
10429                 } else if (set->fb == NULL) {
10430                         config->mode_changed = true;
10431                 } else if (set->fb->pixel_format !=
10432                            set->crtc->primary->fb->pixel_format) {
10433                         config->mode_changed = true;
10434                 } else {
10435                         config->fb_changed = true;
10436                 }
10437         }
10438
10439         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
10440                 config->fb_changed = true;
10441
10442         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
10443                 DRM_DEBUG_KMS("modes are different, full mode set\n");
10444                 drm_mode_debug_printmodeline(&set->crtc->mode);
10445                 drm_mode_debug_printmodeline(set->mode);
10446                 config->mode_changed = true;
10447         }
10448
10449         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
10450                         set->crtc->base.id, config->mode_changed, config->fb_changed);
10451 }
10452
10453 static int
10454 intel_modeset_stage_output_state(struct drm_device *dev,
10455                                  struct drm_mode_set *set,
10456                                  struct intel_set_config *config)
10457 {
10458         struct intel_connector *connector;
10459         struct intel_encoder *encoder;
10460         struct intel_crtc *crtc;
10461         int ro;
10462
10463         /* The upper layers ensure that we either disable a crtc or have a list
10464          * of connectors. For paranoia, double-check this. */
10465         WARN_ON(!set->fb && (set->num_connectors != 0));
10466         WARN_ON(set->fb && (set->num_connectors == 0));
10467
10468         list_for_each_entry(connector, &dev->mode_config.connector_list,
10469                             base.head) {
10470                 /* Otherwise traverse passed in connector list and get encoders
10471                  * for them. */
10472                 for (ro = 0; ro < set->num_connectors; ro++) {
10473                         if (set->connectors[ro] == &connector->base) {
10474                                 connector->new_encoder = connector->encoder;
10475                                 break;
10476                         }
10477                 }
10478
10479                 /* If we disable the crtc, disable all its connectors. Also, if
10480                  * the connector is on the changing crtc but not on the new
10481                  * connector list, disable it. */
10482                 if ((!set->fb || ro == set->num_connectors) &&
10483                     connector->base.encoder &&
10484                     connector->base.encoder->crtc == set->crtc) {
10485                         connector->new_encoder = NULL;
10486
10487                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
10488                                 connector->base.base.id,
10489                                 drm_get_connector_name(&connector->base));
10490                 }
10491
10492
10493                 if (&connector->new_encoder->base != connector->base.encoder) {
10494                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
10495                         config->mode_changed = true;
10496                 }
10497         }
10498         /* connector->new_encoder is now updated for all connectors. */
10499
10500         /* Update crtc of enabled connectors. */
10501         list_for_each_entry(connector, &dev->mode_config.connector_list,
10502                             base.head) {
10503                 struct drm_crtc *new_crtc;
10504
10505                 if (!connector->new_encoder)
10506                         continue;
10507
10508                 new_crtc = connector->new_encoder->base.crtc;
10509
10510                 for (ro = 0; ro < set->num_connectors; ro++) {
10511                         if (set->connectors[ro] == &connector->base)
10512                                 new_crtc = set->crtc;
10513                 }
10514
10515                 /* Make sure the new CRTC will work with the encoder */
10516                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
10517                                          new_crtc)) {
10518                         return -EINVAL;
10519                 }
10520                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
10521
10522                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
10523                         connector->base.base.id,
10524                         drm_get_connector_name(&connector->base),
10525                         new_crtc->base.id);
10526         }
10527
10528         /* Check for any encoders that needs to be disabled. */
10529         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10530                             base.head) {
10531                 int num_connectors = 0;
10532                 list_for_each_entry(connector,
10533                                     &dev->mode_config.connector_list,
10534                                     base.head) {
10535                         if (connector->new_encoder == encoder) {
10536                                 WARN_ON(!connector->new_encoder->new_crtc);
10537                                 num_connectors++;
10538                         }
10539                 }
10540
10541                 if (num_connectors == 0)
10542                         encoder->new_crtc = NULL;
10543                 else if (num_connectors > 1)
10544                         return -EINVAL;
10545
10546                 /* Only now check for crtc changes so we don't miss encoders
10547                  * that will be disabled. */
10548                 if (&encoder->new_crtc->base != encoder->base.crtc) {
10549                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
10550                         config->mode_changed = true;
10551                 }
10552         }
10553         /* Now we've also updated encoder->new_crtc for all encoders. */
10554
10555         for_each_intel_crtc(dev, crtc) {
10556                 crtc->new_enabled = false;
10557
10558                 list_for_each_entry(encoder,
10559                                     &dev->mode_config.encoder_list,
10560                                     base.head) {
10561                         if (encoder->new_crtc == crtc) {
10562                                 crtc->new_enabled = true;
10563                                 break;
10564                         }
10565                 }
10566
10567                 if (crtc->new_enabled != crtc->base.enabled) {
10568                         DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
10569                                       crtc->new_enabled ? "en" : "dis");
10570                         config->mode_changed = true;
10571                 }
10572
10573                 if (crtc->new_enabled)
10574                         crtc->new_config = &crtc->config;
10575                 else
10576                         crtc->new_config = NULL;
10577         }
10578
10579         return 0;
10580 }
10581
10582 static void disable_crtc_nofb(struct intel_crtc *crtc)
10583 {
10584         struct drm_device *dev = crtc->base.dev;
10585         struct intel_encoder *encoder;
10586         struct intel_connector *connector;
10587
10588         DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
10589                       pipe_name(crtc->pipe));
10590
10591         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10592                 if (connector->new_encoder &&
10593                     connector->new_encoder->new_crtc == crtc)
10594                         connector->new_encoder = NULL;
10595         }
10596
10597         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10598                 if (encoder->new_crtc == crtc)
10599                         encoder->new_crtc = NULL;
10600         }
10601
10602         crtc->new_enabled = false;
10603         crtc->new_config = NULL;
10604 }
10605
10606 static int intel_crtc_set_config(struct drm_mode_set *set)
10607 {
10608         struct drm_device *dev;
10609         struct drm_mode_set save_set;
10610         struct intel_set_config *config;
10611         int ret;
10612
10613         BUG_ON(!set);
10614         BUG_ON(!set->crtc);
10615         BUG_ON(!set->crtc->helper_private);
10616
10617         /* Enforce sane interface api - has been abused by the fb helper. */
10618         BUG_ON(!set->mode && set->fb);
10619         BUG_ON(set->fb && set->num_connectors == 0);
10620
10621         if (set->fb) {
10622                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
10623                                 set->crtc->base.id, set->fb->base.id,
10624                                 (int)set->num_connectors, set->x, set->y);
10625         } else {
10626                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
10627         }
10628
10629         dev = set->crtc->dev;
10630
10631         ret = -ENOMEM;
10632         config = kzalloc(sizeof(*config), GFP_KERNEL);
10633         if (!config)
10634                 goto out_config;
10635
10636         ret = intel_set_config_save_state(dev, config);
10637         if (ret)
10638                 goto out_config;
10639
10640         save_set.crtc = set->crtc;
10641         save_set.mode = &set->crtc->mode;
10642         save_set.x = set->crtc->x;
10643         save_set.y = set->crtc->y;
10644         save_set.fb = set->crtc->primary->fb;
10645
10646         /* Compute whether we need a full modeset, only an fb base update or no
10647          * change at all. In the future we might also check whether only the
10648          * mode changed, e.g. for LVDS where we only change the panel fitter in
10649          * such cases. */
10650         intel_set_config_compute_mode_changes(set, config);
10651
10652         ret = intel_modeset_stage_output_state(dev, set, config);
10653         if (ret)
10654                 goto fail;
10655
10656         if (config->mode_changed) {
10657                 ret = intel_set_mode(set->crtc, set->mode,
10658                                      set->x, set->y, set->fb);
10659         } else if (config->fb_changed) {
10660                 intel_crtc_wait_for_pending_flips(set->crtc);
10661
10662                 ret = intel_pipe_set_base(set->crtc,
10663                                           set->x, set->y, set->fb);
10664                 /*
10665                  * In the fastboot case this may be our only check of the
10666                  * state after boot.  It would be better to only do it on
10667                  * the first update, but we don't have a nice way of doing that
10668                  * (and really, set_config isn't used much for high freq page
10669                  * flipping, so increasing its cost here shouldn't be a big
10670                  * deal).
10671                  */
10672                 if (i915.fastboot && ret == 0)
10673                         intel_modeset_check_state(set->crtc->dev);
10674         }
10675
10676         if (ret) {
10677                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
10678                               set->crtc->base.id, ret);
10679 fail:
10680                 intel_set_config_restore_state(dev, config);
10681
10682                 /*
10683                  * HACK: if the pipe was on, but we didn't have a framebuffer,
10684                  * force the pipe off to avoid oopsing in the modeset code
10685                  * due to fb==NULL. This should only happen during boot since
10686                  * we don't yet reconstruct the FB from the hardware state.
10687                  */
10688                 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
10689                         disable_crtc_nofb(to_intel_crtc(save_set.crtc));
10690
10691                 /* Try to restore the config */
10692                 if (config->mode_changed &&
10693                     intel_set_mode(save_set.crtc, save_set.mode,
10694                                    save_set.x, save_set.y, save_set.fb))
10695                         DRM_ERROR("failed to restore config after modeset failure\n");
10696         }
10697
10698 out_config:
10699         intel_set_config_free(config);
10700         return ret;
10701 }
10702
10703 static const struct drm_crtc_funcs intel_crtc_funcs = {
10704         .cursor_set = intel_crtc_cursor_set,
10705         .cursor_move = intel_crtc_cursor_move,
10706         .gamma_set = intel_crtc_gamma_set,
10707         .set_config = intel_crtc_set_config,
10708         .destroy = intel_crtc_destroy,
10709         .page_flip = intel_crtc_page_flip,
10710 };
10711
10712 static void intel_cpu_pll_init(struct drm_device *dev)
10713 {
10714         if (HAS_DDI(dev))
10715                 intel_ddi_pll_init(dev);
10716 }
10717
10718 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
10719                                       struct intel_shared_dpll *pll,
10720                                       struct intel_dpll_hw_state *hw_state)
10721 {
10722         uint32_t val;
10723
10724         val = I915_READ(PCH_DPLL(pll->id));
10725         hw_state->dpll = val;
10726         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
10727         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
10728
10729         return val & DPLL_VCO_ENABLE;
10730 }
10731
10732 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
10733                                   struct intel_shared_dpll *pll)
10734 {
10735         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
10736         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
10737 }
10738
10739 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
10740                                 struct intel_shared_dpll *pll)
10741 {
10742         /* PCH refclock must be enabled first */
10743         ibx_assert_pch_refclk_enabled(dev_priv);
10744
10745         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10746
10747         /* Wait for the clocks to stabilize. */
10748         POSTING_READ(PCH_DPLL(pll->id));
10749         udelay(150);
10750
10751         /* The pixel multiplier can only be updated once the
10752          * DPLL is enabled and the clocks are stable.
10753          *
10754          * So write it again.
10755          */
10756         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10757         POSTING_READ(PCH_DPLL(pll->id));
10758         udelay(200);
10759 }
10760
10761 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
10762                                  struct intel_shared_dpll *pll)
10763 {
10764         struct drm_device *dev = dev_priv->dev;
10765         struct intel_crtc *crtc;
10766
10767         /* Make sure no transcoder isn't still depending on us. */
10768         for_each_intel_crtc(dev, crtc) {
10769                 if (intel_crtc_to_shared_dpll(crtc) == pll)
10770                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
10771         }
10772
10773         I915_WRITE(PCH_DPLL(pll->id), 0);
10774         POSTING_READ(PCH_DPLL(pll->id));
10775         udelay(200);
10776 }
10777
10778 static char *ibx_pch_dpll_names[] = {
10779         "PCH DPLL A",
10780         "PCH DPLL B",
10781 };
10782
10783 static void ibx_pch_dpll_init(struct drm_device *dev)
10784 {
10785         struct drm_i915_private *dev_priv = dev->dev_private;
10786         int i;
10787
10788         dev_priv->num_shared_dpll = 2;
10789
10790         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10791                 dev_priv->shared_dplls[i].id = i;
10792                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
10793                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
10794                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
10795                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
10796                 dev_priv->shared_dplls[i].get_hw_state =
10797                         ibx_pch_dpll_get_hw_state;
10798         }
10799 }
10800
10801 static void intel_shared_dpll_init(struct drm_device *dev)
10802 {
10803         struct drm_i915_private *dev_priv = dev->dev_private;
10804
10805         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
10806                 ibx_pch_dpll_init(dev);
10807         else
10808                 dev_priv->num_shared_dpll = 0;
10809
10810         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
10811 }
10812
10813 static void intel_crtc_init(struct drm_device *dev, int pipe)
10814 {
10815         struct drm_i915_private *dev_priv = dev->dev_private;
10816         struct intel_crtc *intel_crtc;
10817         int i;
10818
10819         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
10820         if (intel_crtc == NULL)
10821                 return;
10822
10823         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
10824
10825         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
10826         for (i = 0; i < 256; i++) {
10827                 intel_crtc->lut_r[i] = i;
10828                 intel_crtc->lut_g[i] = i;
10829                 intel_crtc->lut_b[i] = i;
10830         }
10831
10832         /*
10833          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
10834          * is hooked to plane B. Hence we want plane A feeding pipe B.
10835          */
10836         intel_crtc->pipe = pipe;
10837         intel_crtc->plane = pipe;
10838         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
10839                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
10840                 intel_crtc->plane = !pipe;
10841         }
10842
10843         init_waitqueue_head(&intel_crtc->vbl_wait);
10844
10845         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
10846                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
10847         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
10848         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
10849
10850         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
10851 }
10852
10853 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
10854 {
10855         struct drm_encoder *encoder = connector->base.encoder;
10856
10857         WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex));
10858
10859         if (!encoder)
10860                 return INVALID_PIPE;
10861
10862         return to_intel_crtc(encoder->crtc)->pipe;
10863 }
10864
10865 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
10866                                 struct drm_file *file)
10867 {
10868         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
10869         struct drm_mode_object *drmmode_obj;
10870         struct intel_crtc *crtc;
10871
10872         if (!drm_core_check_feature(dev, DRIVER_MODESET))
10873                 return -ENODEV;
10874
10875         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
10876                         DRM_MODE_OBJECT_CRTC);
10877
10878         if (!drmmode_obj) {
10879                 DRM_ERROR("no such CRTC id\n");
10880                 return -ENOENT;
10881         }
10882
10883         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
10884         pipe_from_crtc_id->pipe = crtc->pipe;
10885
10886         return 0;
10887 }
10888
10889 static int intel_encoder_clones(struct intel_encoder *encoder)
10890 {
10891         struct drm_device *dev = encoder->base.dev;
10892         struct intel_encoder *source_encoder;
10893         int index_mask = 0;
10894         int entry = 0;
10895
10896         list_for_each_entry(source_encoder,
10897                             &dev->mode_config.encoder_list, base.head) {
10898                 if (encoders_cloneable(encoder, source_encoder))
10899                         index_mask |= (1 << entry);
10900
10901                 entry++;
10902         }
10903
10904         return index_mask;
10905 }
10906
10907 static bool has_edp_a(struct drm_device *dev)
10908 {
10909         struct drm_i915_private *dev_priv = dev->dev_private;
10910
10911         if (!IS_MOBILE(dev))
10912                 return false;
10913
10914         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
10915                 return false;
10916
10917         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
10918                 return false;
10919
10920         return true;
10921 }
10922
10923 const char *intel_output_name(int output)
10924 {
10925         static const char *names[] = {
10926                 [INTEL_OUTPUT_UNUSED] = "Unused",
10927                 [INTEL_OUTPUT_ANALOG] = "Analog",
10928                 [INTEL_OUTPUT_DVO] = "DVO",
10929                 [INTEL_OUTPUT_SDVO] = "SDVO",
10930                 [INTEL_OUTPUT_LVDS] = "LVDS",
10931                 [INTEL_OUTPUT_TVOUT] = "TV",
10932                 [INTEL_OUTPUT_HDMI] = "HDMI",
10933                 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
10934                 [INTEL_OUTPUT_EDP] = "eDP",
10935                 [INTEL_OUTPUT_DSI] = "DSI",
10936                 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
10937         };
10938
10939         if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
10940                 return "Invalid";
10941
10942         return names[output];
10943 }
10944
10945 static void intel_setup_outputs(struct drm_device *dev)
10946 {
10947         struct drm_i915_private *dev_priv = dev->dev_private;
10948         struct intel_encoder *encoder;
10949         bool dpd_is_edp = false;
10950
10951         intel_lvds_init(dev);
10952
10953         if (!IS_ULT(dev) && !IS_CHERRYVIEW(dev))
10954                 intel_crt_init(dev);
10955
10956         if (HAS_DDI(dev)) {
10957                 int found;
10958
10959                 /* Haswell uses DDI functions to detect digital outputs */
10960                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
10961                 /* DDI A only supports eDP */
10962                 if (found)
10963                         intel_ddi_init(dev, PORT_A);
10964
10965                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
10966                  * register */
10967                 found = I915_READ(SFUSE_STRAP);
10968
10969                 if (found & SFUSE_STRAP_DDIB_DETECTED)
10970                         intel_ddi_init(dev, PORT_B);
10971                 if (found & SFUSE_STRAP_DDIC_DETECTED)
10972                         intel_ddi_init(dev, PORT_C);
10973                 if (found & SFUSE_STRAP_DDID_DETECTED)
10974                         intel_ddi_init(dev, PORT_D);
10975         } else if (HAS_PCH_SPLIT(dev)) {
10976                 int found;
10977                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
10978
10979                 if (has_edp_a(dev))
10980                         intel_dp_init(dev, DP_A, PORT_A);
10981
10982                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
10983                         /* PCH SDVOB multiplex with HDMIB */
10984                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
10985                         if (!found)
10986                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
10987                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
10988                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
10989                 }
10990
10991                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
10992                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
10993
10994                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
10995                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
10996
10997                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
10998                         intel_dp_init(dev, PCH_DP_C, PORT_C);
10999
11000                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
11001                         intel_dp_init(dev, PCH_DP_D, PORT_D);
11002         } else if (IS_VALLEYVIEW(dev)) {
11003                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
11004                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
11005                                         PORT_B);
11006                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
11007                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
11008                 }
11009
11010                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
11011                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
11012                                         PORT_C);
11013                         if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
11014                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
11015                 }
11016
11017                 intel_dsi_init(dev);
11018         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
11019                 bool found = false;
11020
11021                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
11022                         DRM_DEBUG_KMS("probing SDVOB\n");
11023                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
11024                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
11025                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
11026                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
11027                         }
11028
11029                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
11030                                 intel_dp_init(dev, DP_B, PORT_B);
11031                 }
11032
11033                 /* Before G4X SDVOC doesn't have its own detect register */
11034
11035                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
11036                         DRM_DEBUG_KMS("probing SDVOC\n");
11037                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
11038                 }
11039
11040                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
11041
11042                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
11043                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
11044                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
11045                         }
11046                         if (SUPPORTS_INTEGRATED_DP(dev))
11047                                 intel_dp_init(dev, DP_C, PORT_C);
11048                 }
11049
11050                 if (SUPPORTS_INTEGRATED_DP(dev) &&
11051                     (I915_READ(DP_D) & DP_DETECTED))
11052                         intel_dp_init(dev, DP_D, PORT_D);
11053         } else if (IS_GEN2(dev))
11054                 intel_dvo_init(dev);
11055
11056         if (SUPPORTS_TV(dev))
11057                 intel_tv_init(dev);
11058
11059         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
11060                 encoder->base.possible_crtcs = encoder->crtc_mask;
11061                 encoder->base.possible_clones =
11062                         intel_encoder_clones(encoder);
11063         }
11064
11065         intel_init_pch_refclk(dev);
11066
11067         drm_helper_move_panel_connectors_to_head(dev);
11068 }
11069
11070 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
11071 {
11072         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11073
11074         drm_framebuffer_cleanup(fb);
11075         WARN_ON(!intel_fb->obj->framebuffer_references--);
11076         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
11077         kfree(intel_fb);
11078 }
11079
11080 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
11081                                                 struct drm_file *file,
11082                                                 unsigned int *handle)
11083 {
11084         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11085         struct drm_i915_gem_object *obj = intel_fb->obj;
11086
11087         return drm_gem_handle_create(file, &obj->base, handle);
11088 }
11089
11090 static const struct drm_framebuffer_funcs intel_fb_funcs = {
11091         .destroy = intel_user_framebuffer_destroy,
11092         .create_handle = intel_user_framebuffer_create_handle,
11093 };
11094
11095 static int intel_framebuffer_init(struct drm_device *dev,
11096                                   struct intel_framebuffer *intel_fb,
11097                                   struct drm_mode_fb_cmd2 *mode_cmd,
11098                                   struct drm_i915_gem_object *obj)
11099 {
11100         int aligned_height;
11101         int pitch_limit;
11102         int ret;
11103
11104         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
11105
11106         if (obj->tiling_mode == I915_TILING_Y) {
11107                 DRM_DEBUG("hardware does not support tiling Y\n");
11108                 return -EINVAL;
11109         }
11110
11111         if (mode_cmd->pitches[0] & 63) {
11112                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
11113                           mode_cmd->pitches[0]);
11114                 return -EINVAL;
11115         }
11116
11117         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
11118                 pitch_limit = 32*1024;
11119         } else if (INTEL_INFO(dev)->gen >= 4) {
11120                 if (obj->tiling_mode)
11121                         pitch_limit = 16*1024;
11122                 else
11123                         pitch_limit = 32*1024;
11124         } else if (INTEL_INFO(dev)->gen >= 3) {
11125                 if (obj->tiling_mode)
11126                         pitch_limit = 8*1024;
11127                 else
11128                         pitch_limit = 16*1024;
11129         } else
11130                 /* XXX DSPC is limited to 4k tiled */
11131                 pitch_limit = 8*1024;
11132
11133         if (mode_cmd->pitches[0] > pitch_limit) {
11134                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
11135                           obj->tiling_mode ? "tiled" : "linear",
11136                           mode_cmd->pitches[0], pitch_limit);
11137                 return -EINVAL;
11138         }
11139
11140         if (obj->tiling_mode != I915_TILING_NONE &&
11141             mode_cmd->pitches[0] != obj->stride) {
11142                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
11143                           mode_cmd->pitches[0], obj->stride);
11144                 return -EINVAL;
11145         }
11146
11147         /* Reject formats not supported by any plane early. */
11148         switch (mode_cmd->pixel_format) {
11149         case DRM_FORMAT_C8:
11150         case DRM_FORMAT_RGB565:
11151         case DRM_FORMAT_XRGB8888:
11152         case DRM_FORMAT_ARGB8888:
11153                 break;
11154         case DRM_FORMAT_XRGB1555:
11155         case DRM_FORMAT_ARGB1555:
11156                 if (INTEL_INFO(dev)->gen > 3) {
11157                         DRM_DEBUG("unsupported pixel format: %s\n",
11158                                   drm_get_format_name(mode_cmd->pixel_format));
11159                         return -EINVAL;
11160                 }
11161                 break;
11162         case DRM_FORMAT_XBGR8888:
11163         case DRM_FORMAT_ABGR8888:
11164         case DRM_FORMAT_XRGB2101010:
11165         case DRM_FORMAT_ARGB2101010:
11166         case DRM_FORMAT_XBGR2101010:
11167         case DRM_FORMAT_ABGR2101010:
11168                 if (INTEL_INFO(dev)->gen < 4) {
11169                         DRM_DEBUG("unsupported pixel format: %s\n",
11170                                   drm_get_format_name(mode_cmd->pixel_format));
11171                         return -EINVAL;
11172                 }
11173                 break;
11174         case DRM_FORMAT_YUYV:
11175         case DRM_FORMAT_UYVY:
11176         case DRM_FORMAT_YVYU:
11177         case DRM_FORMAT_VYUY:
11178                 if (INTEL_INFO(dev)->gen < 5) {
11179                         DRM_DEBUG("unsupported pixel format: %s\n",
11180                                   drm_get_format_name(mode_cmd->pixel_format));
11181                         return -EINVAL;
11182                 }
11183                 break;
11184         default:
11185                 DRM_DEBUG("unsupported pixel format: %s\n",
11186                           drm_get_format_name(mode_cmd->pixel_format));
11187                 return -EINVAL;
11188         }
11189
11190         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
11191         if (mode_cmd->offsets[0] != 0)
11192                 return -EINVAL;
11193
11194         aligned_height = intel_align_height(dev, mode_cmd->height,
11195                                             obj->tiling_mode);
11196         /* FIXME drm helper for size checks (especially planar formats)? */
11197         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
11198                 return -EINVAL;
11199
11200         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
11201         intel_fb->obj = obj;
11202         intel_fb->obj->framebuffer_references++;
11203
11204         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
11205         if (ret) {
11206                 DRM_ERROR("framebuffer init failed %d\n", ret);
11207                 return ret;
11208         }
11209
11210         return 0;
11211 }
11212
11213 static struct drm_framebuffer *
11214 intel_user_framebuffer_create(struct drm_device *dev,
11215                               struct drm_file *filp,
11216                               struct drm_mode_fb_cmd2 *mode_cmd)
11217 {
11218         struct drm_i915_gem_object *obj;
11219
11220         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
11221                                                 mode_cmd->handles[0]));
11222         if (&obj->base == NULL)
11223                 return ERR_PTR(-ENOENT);
11224
11225         return intel_framebuffer_create(dev, mode_cmd, obj);
11226 }
11227
11228 #ifndef CONFIG_DRM_I915_FBDEV
11229 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
11230 {
11231 }
11232 #endif
11233
11234 static const struct drm_mode_config_funcs intel_mode_funcs = {
11235         .fb_create = intel_user_framebuffer_create,
11236         .output_poll_changed = intel_fbdev_output_poll_changed,
11237 };
11238
11239 /* Set up chip specific display functions */
11240 static void intel_init_display(struct drm_device *dev)
11241 {
11242         struct drm_i915_private *dev_priv = dev->dev_private;
11243
11244         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
11245                 dev_priv->display.find_dpll = g4x_find_best_dpll;
11246         else if (IS_CHERRYVIEW(dev))
11247                 dev_priv->display.find_dpll = chv_find_best_dpll;
11248         else if (IS_VALLEYVIEW(dev))
11249                 dev_priv->display.find_dpll = vlv_find_best_dpll;
11250         else if (IS_PINEVIEW(dev))
11251                 dev_priv->display.find_dpll = pnv_find_best_dpll;
11252         else
11253                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
11254
11255         if (HAS_DDI(dev)) {
11256                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
11257                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
11258                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
11259                 dev_priv->display.crtc_enable = haswell_crtc_enable;
11260                 dev_priv->display.crtc_disable = haswell_crtc_disable;
11261                 dev_priv->display.off = haswell_crtc_off;
11262                 dev_priv->display.update_primary_plane =
11263                         ironlake_update_primary_plane;
11264         } else if (HAS_PCH_SPLIT(dev)) {
11265                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
11266                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
11267                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
11268                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
11269                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
11270                 dev_priv->display.off = ironlake_crtc_off;
11271                 dev_priv->display.update_primary_plane =
11272                         ironlake_update_primary_plane;
11273         } else if (IS_VALLEYVIEW(dev)) {
11274                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11275                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11276                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11277                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
11278                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11279                 dev_priv->display.off = i9xx_crtc_off;
11280                 dev_priv->display.update_primary_plane =
11281                         i9xx_update_primary_plane;
11282         } else {
11283                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11284                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11285                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11286                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
11287                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11288                 dev_priv->display.off = i9xx_crtc_off;
11289                 dev_priv->display.update_primary_plane =
11290                         i9xx_update_primary_plane;
11291         }
11292
11293         /* Returns the core display clock speed */
11294         if (IS_VALLEYVIEW(dev))
11295                 dev_priv->display.get_display_clock_speed =
11296                         valleyview_get_display_clock_speed;
11297         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
11298                 dev_priv->display.get_display_clock_speed =
11299                         i945_get_display_clock_speed;
11300         else if (IS_I915G(dev))
11301                 dev_priv->display.get_display_clock_speed =
11302                         i915_get_display_clock_speed;
11303         else if (IS_I945GM(dev) || IS_845G(dev))
11304                 dev_priv->display.get_display_clock_speed =
11305                         i9xx_misc_get_display_clock_speed;
11306         else if (IS_PINEVIEW(dev))
11307                 dev_priv->display.get_display_clock_speed =
11308                         pnv_get_display_clock_speed;
11309         else if (IS_I915GM(dev))
11310                 dev_priv->display.get_display_clock_speed =
11311                         i915gm_get_display_clock_speed;
11312         else if (IS_I865G(dev))
11313                 dev_priv->display.get_display_clock_speed =
11314                         i865_get_display_clock_speed;
11315         else if (IS_I85X(dev))
11316                 dev_priv->display.get_display_clock_speed =
11317                         i855_get_display_clock_speed;
11318         else /* 852, 830 */
11319                 dev_priv->display.get_display_clock_speed =
11320                         i830_get_display_clock_speed;
11321
11322         if (HAS_PCH_SPLIT(dev)) {
11323                 if (IS_GEN5(dev)) {
11324                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
11325                         dev_priv->display.write_eld = ironlake_write_eld;
11326                 } else if (IS_GEN6(dev)) {
11327                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
11328                         dev_priv->display.write_eld = ironlake_write_eld;
11329                         dev_priv->display.modeset_global_resources =
11330                                 snb_modeset_global_resources;
11331                 } else if (IS_IVYBRIDGE(dev)) {
11332                         /* FIXME: detect B0+ stepping and use auto training */
11333                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
11334                         dev_priv->display.write_eld = ironlake_write_eld;
11335                         dev_priv->display.modeset_global_resources =
11336                                 ivb_modeset_global_resources;
11337                 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
11338                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
11339                         dev_priv->display.write_eld = haswell_write_eld;
11340                         dev_priv->display.modeset_global_resources =
11341                                 haswell_modeset_global_resources;
11342                 }
11343         } else if (IS_G4X(dev)) {
11344                 dev_priv->display.write_eld = g4x_write_eld;
11345         } else if (IS_VALLEYVIEW(dev)) {
11346                 dev_priv->display.modeset_global_resources =
11347                         valleyview_modeset_global_resources;
11348                 dev_priv->display.write_eld = ironlake_write_eld;
11349         }
11350
11351         /* Default just returns -ENODEV to indicate unsupported */
11352         dev_priv->display.queue_flip = intel_default_queue_flip;
11353
11354         switch (INTEL_INFO(dev)->gen) {
11355         case 2:
11356                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
11357                 break;
11358
11359         case 3:
11360                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
11361                 break;
11362
11363         case 4:
11364         case 5:
11365                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
11366                 break;
11367
11368         case 6:
11369                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
11370                 break;
11371         case 7:
11372         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
11373                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
11374                 break;
11375         }
11376
11377         intel_panel_init_backlight_funcs(dev);
11378 }
11379
11380 /*
11381  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
11382  * resume, or other times.  This quirk makes sure that's the case for
11383  * affected systems.
11384  */
11385 static void quirk_pipea_force(struct drm_device *dev)
11386 {
11387         struct drm_i915_private *dev_priv = dev->dev_private;
11388
11389         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
11390         DRM_INFO("applying pipe a force quirk\n");
11391 }
11392
11393 /*
11394  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
11395  */
11396 static void quirk_ssc_force_disable(struct drm_device *dev)
11397 {
11398         struct drm_i915_private *dev_priv = dev->dev_private;
11399         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
11400         DRM_INFO("applying lvds SSC disable quirk\n");
11401 }
11402
11403 /*
11404  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
11405  * brightness value
11406  */
11407 static void quirk_invert_brightness(struct drm_device *dev)
11408 {
11409         struct drm_i915_private *dev_priv = dev->dev_private;
11410         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
11411         DRM_INFO("applying inverted panel brightness quirk\n");
11412 }
11413
11414 struct intel_quirk {
11415         int device;
11416         int subsystem_vendor;
11417         int subsystem_device;
11418         void (*hook)(struct drm_device *dev);
11419 };
11420
11421 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
11422 struct intel_dmi_quirk {
11423         void (*hook)(struct drm_device *dev);
11424         const struct dmi_system_id (*dmi_id_list)[];
11425 };
11426
11427 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
11428 {
11429         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
11430         return 1;
11431 }
11432
11433 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
11434         {
11435                 .dmi_id_list = &(const struct dmi_system_id[]) {
11436                         {
11437                                 .callback = intel_dmi_reverse_brightness,
11438                                 .ident = "NCR Corporation",
11439                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
11440                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
11441                                 },
11442                         },
11443                         { }  /* terminating entry */
11444                 },
11445                 .hook = quirk_invert_brightness,
11446         },
11447 };
11448
11449 static struct intel_quirk intel_quirks[] = {
11450         /* HP Mini needs pipe A force quirk (LP: #322104) */
11451         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
11452
11453         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
11454         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
11455
11456         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
11457         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
11458
11459         /* 830 needs to leave pipe A & dpll A up */
11460         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
11461
11462         /* Lenovo U160 cannot use SSC on LVDS */
11463         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
11464
11465         /* Sony Vaio Y cannot use SSC on LVDS */
11466         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
11467
11468         /* Acer Aspire 5734Z must invert backlight brightness */
11469         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
11470
11471         /* Acer/eMachines G725 */
11472         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
11473
11474         /* Acer/eMachines e725 */
11475         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
11476
11477         /* Acer/Packard Bell NCL20 */
11478         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
11479
11480         /* Acer Aspire 4736Z */
11481         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
11482
11483         /* Acer Aspire 5336 */
11484         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
11485 };
11486
11487 static void intel_init_quirks(struct drm_device *dev)
11488 {
11489         struct pci_dev *d = dev->pdev;
11490         int i;
11491
11492         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
11493                 struct intel_quirk *q = &intel_quirks[i];
11494
11495                 if (d->device == q->device &&
11496                     (d->subsystem_vendor == q->subsystem_vendor ||
11497                      q->subsystem_vendor == PCI_ANY_ID) &&
11498                     (d->subsystem_device == q->subsystem_device ||
11499                      q->subsystem_device == PCI_ANY_ID))
11500                         q->hook(dev);
11501         }
11502         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
11503                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
11504                         intel_dmi_quirks[i].hook(dev);
11505         }
11506 }
11507
11508 /* Disable the VGA plane that we never use */
11509 static void i915_disable_vga(struct drm_device *dev)
11510 {
11511         struct drm_i915_private *dev_priv = dev->dev_private;
11512         u8 sr1;
11513         u32 vga_reg = i915_vgacntrl_reg(dev);
11514
11515         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
11516         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
11517         outb(SR01, VGA_SR_INDEX);
11518         sr1 = inb(VGA_SR_DATA);
11519         outb(sr1 | 1<<5, VGA_SR_DATA);
11520         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
11521         udelay(300);
11522
11523         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
11524         POSTING_READ(vga_reg);
11525 }
11526
11527 void intel_modeset_init_hw(struct drm_device *dev)
11528 {
11529         intel_prepare_ddi(dev);
11530
11531         intel_init_clock_gating(dev);
11532
11533         intel_reset_dpio(dev);
11534
11535         intel_enable_gt_powersave(dev);
11536 }
11537
11538 void intel_modeset_suspend_hw(struct drm_device *dev)
11539 {
11540         intel_suspend_hw(dev);
11541 }
11542
11543 void intel_modeset_init(struct drm_device *dev)
11544 {
11545         struct drm_i915_private *dev_priv = dev->dev_private;
11546         int sprite, ret;
11547         enum pipe pipe;
11548         struct intel_crtc *crtc;
11549
11550         drm_mode_config_init(dev);
11551
11552         dev->mode_config.min_width = 0;
11553         dev->mode_config.min_height = 0;
11554
11555         dev->mode_config.preferred_depth = 24;
11556         dev->mode_config.prefer_shadow = 1;
11557
11558         dev->mode_config.funcs = &intel_mode_funcs;
11559
11560         intel_init_quirks(dev);
11561
11562         intel_init_pm(dev);
11563
11564         if (INTEL_INFO(dev)->num_pipes == 0)
11565                 return;
11566
11567         intel_init_display(dev);
11568
11569         if (IS_GEN2(dev)) {
11570                 dev->mode_config.max_width = 2048;
11571                 dev->mode_config.max_height = 2048;
11572         } else if (IS_GEN3(dev)) {
11573                 dev->mode_config.max_width = 4096;
11574                 dev->mode_config.max_height = 4096;
11575         } else {
11576                 dev->mode_config.max_width = 8192;
11577                 dev->mode_config.max_height = 8192;
11578         }
11579
11580         if (IS_GEN2(dev)) {
11581                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
11582                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
11583         } else {
11584                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
11585                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
11586         }
11587
11588         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
11589
11590         DRM_DEBUG_KMS("%d display pipe%s available.\n",
11591                       INTEL_INFO(dev)->num_pipes,
11592                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
11593
11594         for_each_pipe(pipe) {
11595                 intel_crtc_init(dev, pipe);
11596                 for_each_sprite(pipe, sprite) {
11597                         ret = intel_plane_init(dev, pipe, sprite);
11598                         if (ret)
11599                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
11600                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
11601                 }
11602         }
11603
11604         intel_init_dpio(dev);
11605         intel_reset_dpio(dev);
11606
11607         intel_cpu_pll_init(dev);
11608         intel_shared_dpll_init(dev);
11609
11610         /* Just disable it once at startup */
11611         i915_disable_vga(dev);
11612         intel_setup_outputs(dev);
11613
11614         /* Just in case the BIOS is doing something questionable. */
11615         intel_disable_fbc(dev);
11616
11617         mutex_lock(&dev->mode_config.mutex);
11618         intel_modeset_setup_hw_state(dev, false);
11619         mutex_unlock(&dev->mode_config.mutex);
11620
11621         for_each_intel_crtc(dev, crtc) {
11622                 if (!crtc->active)
11623                         continue;
11624
11625                 /*
11626                  * Note that reserving the BIOS fb up front prevents us
11627                  * from stuffing other stolen allocations like the ring
11628                  * on top.  This prevents some ugliness at boot time, and
11629                  * can even allow for smooth boot transitions if the BIOS
11630                  * fb is large enough for the active pipe configuration.
11631                  */
11632                 if (dev_priv->display.get_plane_config) {
11633                         dev_priv->display.get_plane_config(crtc,
11634                                                            &crtc->plane_config);
11635                         /*
11636                          * If the fb is shared between multiple heads, we'll
11637                          * just get the first one.
11638                          */
11639                         intel_find_plane_obj(crtc, &crtc->plane_config);
11640                 }
11641         }
11642 }
11643
11644 static void
11645 intel_connector_break_all_links(struct intel_connector *connector)
11646 {
11647         connector->base.dpms = DRM_MODE_DPMS_OFF;
11648         connector->base.encoder = NULL;
11649         connector->encoder->connectors_active = false;
11650         connector->encoder->base.crtc = NULL;
11651 }
11652
11653 static void intel_enable_pipe_a(struct drm_device *dev)
11654 {
11655         struct intel_connector *connector;
11656         struct drm_connector *crt = NULL;
11657         struct intel_load_detect_pipe load_detect_temp;
11658
11659         /* We can't just switch on the pipe A, we need to set things up with a
11660          * proper mode and output configuration. As a gross hack, enable pipe A
11661          * by enabling the load detect pipe once. */
11662         list_for_each_entry(connector,
11663                             &dev->mode_config.connector_list,
11664                             base.head) {
11665                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
11666                         crt = &connector->base;
11667                         break;
11668                 }
11669         }
11670
11671         if (!crt)
11672                 return;
11673
11674         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
11675                 intel_release_load_detect_pipe(crt, &load_detect_temp);
11676
11677
11678 }
11679
11680 static bool
11681 intel_check_plane_mapping(struct intel_crtc *crtc)
11682 {
11683         struct drm_device *dev = crtc->base.dev;
11684         struct drm_i915_private *dev_priv = dev->dev_private;
11685         u32 reg, val;
11686
11687         if (INTEL_INFO(dev)->num_pipes == 1)
11688                 return true;
11689
11690         reg = DSPCNTR(!crtc->plane);
11691         val = I915_READ(reg);
11692
11693         if ((val & DISPLAY_PLANE_ENABLE) &&
11694             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
11695                 return false;
11696
11697         return true;
11698 }
11699
11700 static void intel_sanitize_crtc(struct intel_crtc *crtc)
11701 {
11702         struct drm_device *dev = crtc->base.dev;
11703         struct drm_i915_private *dev_priv = dev->dev_private;
11704         u32 reg;
11705
11706         /* Clear any frame start delays used for debugging left by the BIOS */
11707         reg = PIPECONF(crtc->config.cpu_transcoder);
11708         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
11709
11710         /* We need to sanitize the plane -> pipe mapping first because this will
11711          * disable the crtc (and hence change the state) if it is wrong. Note
11712          * that gen4+ has a fixed plane -> pipe mapping.  */
11713         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
11714                 struct intel_connector *connector;
11715                 bool plane;
11716
11717                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
11718                               crtc->base.base.id);
11719
11720                 /* Pipe has the wrong plane attached and the plane is active.
11721                  * Temporarily change the plane mapping and disable everything
11722                  * ...  */
11723                 plane = crtc->plane;
11724                 crtc->plane = !plane;
11725                 dev_priv->display.crtc_disable(&crtc->base);
11726                 crtc->plane = plane;
11727
11728                 /* ... and break all links. */
11729                 list_for_each_entry(connector, &dev->mode_config.connector_list,
11730                                     base.head) {
11731                         if (connector->encoder->base.crtc != &crtc->base)
11732                                 continue;
11733
11734                         intel_connector_break_all_links(connector);
11735                 }
11736
11737                 WARN_ON(crtc->active);
11738                 crtc->base.enabled = false;
11739         }
11740
11741         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
11742             crtc->pipe == PIPE_A && !crtc->active) {
11743                 /* BIOS forgot to enable pipe A, this mostly happens after
11744                  * resume. Force-enable the pipe to fix this, the update_dpms
11745                  * call below we restore the pipe to the right state, but leave
11746                  * the required bits on. */
11747                 intel_enable_pipe_a(dev);
11748         }
11749
11750         /* Adjust the state of the output pipe according to whether we
11751          * have active connectors/encoders. */
11752         intel_crtc_update_dpms(&crtc->base);
11753
11754         if (crtc->active != crtc->base.enabled) {
11755                 struct intel_encoder *encoder;
11756
11757                 /* This can happen either due to bugs in the get_hw_state
11758                  * functions or because the pipe is force-enabled due to the
11759                  * pipe A quirk. */
11760                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
11761                               crtc->base.base.id,
11762                               crtc->base.enabled ? "enabled" : "disabled",
11763                               crtc->active ? "enabled" : "disabled");
11764
11765                 crtc->base.enabled = crtc->active;
11766
11767                 /* Because we only establish the connector -> encoder ->
11768                  * crtc links if something is active, this means the
11769                  * crtc is now deactivated. Break the links. connector
11770                  * -> encoder links are only establish when things are
11771                  *  actually up, hence no need to break them. */
11772                 WARN_ON(crtc->active);
11773
11774                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
11775                         WARN_ON(encoder->connectors_active);
11776                         encoder->base.crtc = NULL;
11777                 }
11778         }
11779         if (crtc->active) {
11780                 /*
11781                  * We start out with underrun reporting disabled to avoid races.
11782                  * For correct bookkeeping mark this on active crtcs.
11783                  *
11784                  * No protection against concurrent access is required - at
11785                  * worst a fifo underrun happens which also sets this to false.
11786                  */
11787                 crtc->cpu_fifo_underrun_disabled = true;
11788                 crtc->pch_fifo_underrun_disabled = true;
11789         }
11790 }
11791
11792 static void intel_sanitize_encoder(struct intel_encoder *encoder)
11793 {
11794         struct intel_connector *connector;
11795         struct drm_device *dev = encoder->base.dev;
11796
11797         /* We need to check both for a crtc link (meaning that the
11798          * encoder is active and trying to read from a pipe) and the
11799          * pipe itself being active. */
11800         bool has_active_crtc = encoder->base.crtc &&
11801                 to_intel_crtc(encoder->base.crtc)->active;
11802
11803         if (encoder->connectors_active && !has_active_crtc) {
11804                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
11805                               encoder->base.base.id,
11806                               drm_get_encoder_name(&encoder->base));
11807
11808                 /* Connector is active, but has no active pipe. This is
11809                  * fallout from our resume register restoring. Disable
11810                  * the encoder manually again. */
11811                 if (encoder->base.crtc) {
11812                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
11813                                       encoder->base.base.id,
11814                                       drm_get_encoder_name(&encoder->base));
11815                         encoder->disable(encoder);
11816                 }
11817
11818                 /* Inconsistent output/port/pipe state happens presumably due to
11819                  * a bug in one of the get_hw_state functions. Or someplace else
11820                  * in our code, like the register restore mess on resume. Clamp
11821                  * things to off as a safer default. */
11822                 list_for_each_entry(connector,
11823                                     &dev->mode_config.connector_list,
11824                                     base.head) {
11825                         if (connector->encoder != encoder)
11826                                 continue;
11827
11828                         intel_connector_break_all_links(connector);
11829                 }
11830         }
11831         /* Enabled encoders without active connectors will be fixed in
11832          * the crtc fixup. */
11833 }
11834
11835 void i915_redisable_vga_power_on(struct drm_device *dev)
11836 {
11837         struct drm_i915_private *dev_priv = dev->dev_private;
11838         u32 vga_reg = i915_vgacntrl_reg(dev);
11839
11840         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
11841                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
11842                 i915_disable_vga(dev);
11843         }
11844 }
11845
11846 void i915_redisable_vga(struct drm_device *dev)
11847 {
11848         struct drm_i915_private *dev_priv = dev->dev_private;
11849
11850         /* This function can be called both from intel_modeset_setup_hw_state or
11851          * at a very early point in our resume sequence, where the power well
11852          * structures are not yet restored. Since this function is at a very
11853          * paranoid "someone might have enabled VGA while we were not looking"
11854          * level, just check if the power well is enabled instead of trying to
11855          * follow the "don't touch the power well if we don't need it" policy
11856          * the rest of the driver uses. */
11857         if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
11858                 return;
11859
11860         i915_redisable_vga_power_on(dev);
11861 }
11862
11863 static bool primary_get_hw_state(struct intel_crtc *crtc)
11864 {
11865         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
11866
11867         if (!crtc->active)
11868                 return false;
11869
11870         return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
11871 }
11872
11873 static void intel_modeset_readout_hw_state(struct drm_device *dev)
11874 {
11875         struct drm_i915_private *dev_priv = dev->dev_private;
11876         enum pipe pipe;
11877         struct intel_crtc *crtc;
11878         struct intel_encoder *encoder;
11879         struct intel_connector *connector;
11880         int i;
11881
11882         for_each_intel_crtc(dev, crtc) {
11883                 memset(&crtc->config, 0, sizeof(crtc->config));
11884
11885                 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
11886
11887                 crtc->active = dev_priv->display.get_pipe_config(crtc,
11888                                                                  &crtc->config);
11889
11890                 crtc->base.enabled = crtc->active;
11891                 crtc->primary_enabled = primary_get_hw_state(crtc);
11892
11893                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
11894                               crtc->base.base.id,
11895                               crtc->active ? "enabled" : "disabled");
11896         }
11897
11898         /* FIXME: Smash this into the new shared dpll infrastructure. */
11899         if (HAS_DDI(dev))
11900                 intel_ddi_setup_hw_pll_state(dev);
11901
11902         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11903                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11904
11905                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
11906                 pll->active = 0;
11907                 for_each_intel_crtc(dev, crtc) {
11908                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11909                                 pll->active++;
11910                 }
11911                 pll->refcount = pll->active;
11912
11913                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
11914                               pll->name, pll->refcount, pll->on);
11915         }
11916
11917         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11918                             base.head) {
11919                 pipe = 0;
11920
11921                 if (encoder->get_hw_state(encoder, &pipe)) {
11922                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11923                         encoder->base.crtc = &crtc->base;
11924                         encoder->get_config(encoder, &crtc->config);
11925                 } else {
11926                         encoder->base.crtc = NULL;
11927                 }
11928
11929                 encoder->connectors_active = false;
11930                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
11931                               encoder->base.base.id,
11932                               drm_get_encoder_name(&encoder->base),
11933                               encoder->base.crtc ? "enabled" : "disabled",
11934                               pipe_name(pipe));
11935         }
11936
11937         list_for_each_entry(connector, &dev->mode_config.connector_list,
11938                             base.head) {
11939                 if (connector->get_hw_state(connector)) {
11940                         connector->base.dpms = DRM_MODE_DPMS_ON;
11941                         connector->encoder->connectors_active = true;
11942                         connector->base.encoder = &connector->encoder->base;
11943                 } else {
11944                         connector->base.dpms = DRM_MODE_DPMS_OFF;
11945                         connector->base.encoder = NULL;
11946                 }
11947                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
11948                               connector->base.base.id,
11949                               drm_get_connector_name(&connector->base),
11950                               connector->base.encoder ? "enabled" : "disabled");
11951         }
11952 }
11953
11954 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
11955  * and i915 state tracking structures. */
11956 void intel_modeset_setup_hw_state(struct drm_device *dev,
11957                                   bool force_restore)
11958 {
11959         struct drm_i915_private *dev_priv = dev->dev_private;
11960         enum pipe pipe;
11961         struct intel_crtc *crtc;
11962         struct intel_encoder *encoder;
11963         int i;
11964
11965         intel_modeset_readout_hw_state(dev);
11966
11967         /*
11968          * Now that we have the config, copy it to each CRTC struct
11969          * Note that this could go away if we move to using crtc_config
11970          * checking everywhere.
11971          */
11972         for_each_intel_crtc(dev, crtc) {
11973                 if (crtc->active && i915.fastboot) {
11974                         intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
11975                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
11976                                       crtc->base.base.id);
11977                         drm_mode_debug_printmodeline(&crtc->base.mode);
11978                 }
11979         }
11980
11981         /* HW state is read out, now we need to sanitize this mess. */
11982         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11983                             base.head) {
11984                 intel_sanitize_encoder(encoder);
11985         }
11986
11987         for_each_pipe(pipe) {
11988                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11989                 intel_sanitize_crtc(crtc);
11990                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
11991         }
11992
11993         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11994                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11995
11996                 if (!pll->on || pll->active)
11997                         continue;
11998
11999                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
12000
12001                 pll->disable(dev_priv, pll);
12002                 pll->on = false;
12003         }
12004
12005         if (HAS_PCH_SPLIT(dev))
12006                 ilk_wm_get_hw_state(dev);
12007
12008         if (force_restore) {
12009                 i915_redisable_vga(dev);
12010
12011                 /*
12012                  * We need to use raw interfaces for restoring state to avoid
12013                  * checking (bogus) intermediate states.
12014                  */
12015                 for_each_pipe(pipe) {
12016                         struct drm_crtc *crtc =
12017                                 dev_priv->pipe_to_crtc_mapping[pipe];
12018
12019                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
12020                                          crtc->primary->fb);
12021                 }
12022         } else {
12023                 intel_modeset_update_staged_output_state(dev);
12024         }
12025
12026         intel_modeset_check_state(dev);
12027 }
12028
12029 void intel_modeset_gem_init(struct drm_device *dev)
12030 {
12031         struct drm_crtc *c;
12032         struct intel_framebuffer *fb;
12033
12034         mutex_lock(&dev->struct_mutex);
12035         intel_init_gt_powersave(dev);
12036         mutex_unlock(&dev->struct_mutex);
12037
12038         intel_modeset_init_hw(dev);
12039
12040         intel_setup_overlay(dev);
12041
12042         /*
12043          * Make sure any fbs we allocated at startup are properly
12044          * pinned & fenced.  When we do the allocation it's too early
12045          * for this.
12046          */
12047         mutex_lock(&dev->struct_mutex);
12048         list_for_each_entry(c, &dev->mode_config.crtc_list, head) {
12049                 if (!c->primary->fb)
12050                         continue;
12051
12052                 fb = to_intel_framebuffer(c->primary->fb);
12053                 if (intel_pin_and_fence_fb_obj(dev, fb->obj, NULL)) {
12054                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
12055                                   to_intel_crtc(c)->pipe);
12056                         drm_framebuffer_unreference(c->primary->fb);
12057                         c->primary->fb = NULL;
12058                 }
12059         }
12060         mutex_unlock(&dev->struct_mutex);
12061 }
12062
12063 void intel_connector_unregister(struct intel_connector *intel_connector)
12064 {
12065         struct drm_connector *connector = &intel_connector->base;
12066
12067         intel_panel_destroy_backlight(connector);
12068         drm_sysfs_connector_remove(connector);
12069 }
12070
12071 void intel_modeset_cleanup(struct drm_device *dev)
12072 {
12073         struct drm_i915_private *dev_priv = dev->dev_private;
12074         struct drm_crtc *crtc;
12075         struct drm_connector *connector;
12076
12077         /*
12078          * Interrupts and polling as the first thing to avoid creating havoc.
12079          * Too much stuff here (turning of rps, connectors, ...) would
12080          * experience fancy races otherwise.
12081          */
12082         drm_irq_uninstall(dev);
12083         cancel_work_sync(&dev_priv->hotplug_work);
12084         /*
12085          * Due to the hpd irq storm handling the hotplug work can re-arm the
12086          * poll handlers. Hence disable polling after hpd handling is shut down.
12087          */
12088         drm_kms_helper_poll_fini(dev);
12089
12090         mutex_lock(&dev->struct_mutex);
12091
12092         intel_unregister_dsm_handler();
12093
12094         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
12095                 /* Skip inactive CRTCs */
12096                 if (!crtc->primary->fb)
12097                         continue;
12098
12099                 intel_increase_pllclock(crtc);
12100         }
12101
12102         intel_disable_fbc(dev);
12103
12104         intel_disable_gt_powersave(dev);
12105
12106         ironlake_teardown_rc6(dev);
12107
12108         mutex_unlock(&dev->struct_mutex);
12109
12110         /* flush any delayed tasks or pending work */
12111         flush_scheduled_work();
12112
12113         /* destroy the backlight and sysfs files before encoders/connectors */
12114         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12115                 struct intel_connector *intel_connector;
12116
12117                 intel_connector = to_intel_connector(connector);
12118                 intel_connector->unregister(intel_connector);
12119         }
12120
12121         drm_mode_config_cleanup(dev);
12122
12123         intel_cleanup_overlay(dev);
12124
12125         mutex_lock(&dev->struct_mutex);
12126         intel_cleanup_gt_powersave(dev);
12127         mutex_unlock(&dev->struct_mutex);
12128 }
12129
12130 /*
12131  * Return which encoder is currently attached for connector.
12132  */
12133 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
12134 {
12135         return &intel_attached_encoder(connector)->base;
12136 }
12137
12138 void intel_connector_attach_encoder(struct intel_connector *connector,
12139                                     struct intel_encoder *encoder)
12140 {
12141         connector->encoder = encoder;
12142         drm_mode_connector_attach_encoder(&connector->base,
12143                                           &encoder->base);
12144 }
12145
12146 /*
12147  * set vga decode state - true == enable VGA decode
12148  */
12149 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
12150 {
12151         struct drm_i915_private *dev_priv = dev->dev_private;
12152         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
12153         u16 gmch_ctrl;
12154
12155         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
12156                 DRM_ERROR("failed to read control word\n");
12157                 return -EIO;
12158         }
12159
12160         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
12161                 return 0;
12162
12163         if (state)
12164                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
12165         else
12166                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
12167
12168         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
12169                 DRM_ERROR("failed to write control word\n");
12170                 return -EIO;
12171         }
12172
12173         return 0;
12174 }
12175
12176 struct intel_display_error_state {
12177
12178         u32 power_well_driver;
12179
12180         int num_transcoders;
12181
12182         struct intel_cursor_error_state {
12183                 u32 control;
12184                 u32 position;
12185                 u32 base;
12186                 u32 size;
12187         } cursor[I915_MAX_PIPES];
12188
12189         struct intel_pipe_error_state {
12190                 bool power_domain_on;
12191                 u32 source;
12192                 u32 stat;
12193         } pipe[I915_MAX_PIPES];
12194
12195         struct intel_plane_error_state {
12196                 u32 control;
12197                 u32 stride;
12198                 u32 size;
12199                 u32 pos;
12200                 u32 addr;
12201                 u32 surface;
12202                 u32 tile_offset;
12203         } plane[I915_MAX_PIPES];
12204
12205         struct intel_transcoder_error_state {
12206                 bool power_domain_on;
12207                 enum transcoder cpu_transcoder;
12208
12209                 u32 conf;
12210
12211                 u32 htotal;
12212                 u32 hblank;
12213                 u32 hsync;
12214                 u32 vtotal;
12215                 u32 vblank;
12216                 u32 vsync;
12217         } transcoder[4];
12218 };
12219
12220 struct intel_display_error_state *
12221 intel_display_capture_error_state(struct drm_device *dev)
12222 {
12223         struct drm_i915_private *dev_priv = dev->dev_private;
12224         struct intel_display_error_state *error;
12225         int transcoders[] = {
12226                 TRANSCODER_A,
12227                 TRANSCODER_B,
12228                 TRANSCODER_C,
12229                 TRANSCODER_EDP,
12230         };
12231         int i;
12232
12233         if (INTEL_INFO(dev)->num_pipes == 0)
12234                 return NULL;
12235
12236         error = kzalloc(sizeof(*error), GFP_ATOMIC);
12237         if (error == NULL)
12238                 return NULL;
12239
12240         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
12241                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
12242
12243         for_each_pipe(i) {
12244                 error->pipe[i].power_domain_on =
12245                         intel_display_power_enabled_sw(dev_priv,
12246                                                        POWER_DOMAIN_PIPE(i));
12247                 if (!error->pipe[i].power_domain_on)
12248                         continue;
12249
12250                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
12251                         error->cursor[i].control = I915_READ(CURCNTR(i));
12252                         error->cursor[i].position = I915_READ(CURPOS(i));
12253                         error->cursor[i].base = I915_READ(CURBASE(i));
12254                 } else {
12255                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
12256                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
12257                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
12258                 }
12259
12260                 error->plane[i].control = I915_READ(DSPCNTR(i));
12261                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
12262                 if (INTEL_INFO(dev)->gen <= 3) {
12263                         error->plane[i].size = I915_READ(DSPSIZE(i));
12264                         error->plane[i].pos = I915_READ(DSPPOS(i));
12265                 }
12266                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
12267                         error->plane[i].addr = I915_READ(DSPADDR(i));
12268                 if (INTEL_INFO(dev)->gen >= 4) {
12269                         error->plane[i].surface = I915_READ(DSPSURF(i));
12270                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
12271                 }
12272
12273                 error->pipe[i].source = I915_READ(PIPESRC(i));
12274
12275                 if (!HAS_PCH_SPLIT(dev))
12276                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
12277         }
12278
12279         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
12280         if (HAS_DDI(dev_priv->dev))
12281                 error->num_transcoders++; /* Account for eDP. */
12282
12283         for (i = 0; i < error->num_transcoders; i++) {
12284                 enum transcoder cpu_transcoder = transcoders[i];
12285
12286                 error->transcoder[i].power_domain_on =
12287                         intel_display_power_enabled_sw(dev_priv,
12288                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
12289                 if (!error->transcoder[i].power_domain_on)
12290                         continue;
12291
12292                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
12293
12294                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
12295                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
12296                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
12297                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
12298                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
12299                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
12300                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
12301         }
12302
12303         return error;
12304 }
12305
12306 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
12307
12308 void
12309 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
12310                                 struct drm_device *dev,
12311                                 struct intel_display_error_state *error)
12312 {
12313         int i;
12314
12315         if (!error)
12316                 return;
12317
12318         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
12319         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
12320                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
12321                            error->power_well_driver);
12322         for_each_pipe(i) {
12323                 err_printf(m, "Pipe [%d]:\n", i);
12324                 err_printf(m, "  Power: %s\n",
12325                            error->pipe[i].power_domain_on ? "on" : "off");
12326                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
12327                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
12328
12329                 err_printf(m, "Plane [%d]:\n", i);
12330                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
12331                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
12332                 if (INTEL_INFO(dev)->gen <= 3) {
12333                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
12334                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
12335                 }
12336                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
12337                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
12338                 if (INTEL_INFO(dev)->gen >= 4) {
12339                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
12340                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
12341                 }
12342
12343                 err_printf(m, "Cursor [%d]:\n", i);
12344                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
12345                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
12346                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
12347         }
12348
12349         for (i = 0; i < error->num_transcoders; i++) {
12350                 err_printf(m, "CPU transcoder: %c\n",
12351                            transcoder_name(error->transcoder[i].cpu_transcoder));
12352                 err_printf(m, "  Power: %s\n",
12353                            error->transcoder[i].power_domain_on ? "on" : "off");
12354                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
12355                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
12356                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
12357                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
12358                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
12359                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
12360                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
12361         }
12362 }