drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc);
  46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  47
  48 typedef struct {
  49         /* given values */
  50         int n;
  51         int m1, m2;
  52         int p1, p2;
  53         /* derived values */
  54         int     dot;
  55         int     vco;
  56         int     m;
  57         int     p;
  58 } intel_clock_t;
  59
  60 typedef struct {
  61         int     min, max;
  62 } intel_range_t;
  63
  64 typedef struct {
  65         int     dot_limit;
  66         int     p2_slow, p2_fast;
  67 } intel_p2_t;
  68
  69 #define INTEL_P2_NUM                  2
  70 typedef struct intel_limit intel_limit_t;
  71 struct intel_limit {
  72         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  73         intel_p2_t          p2;
  74         /**
  75          * find_pll() - Find the best values for the PLL
  76          * @limit: limits for the PLL
  77          * @crtc: current CRTC
  78          * @target: target frequency in kHz
  79          * @refclk: reference clock frequency in kHz
  80          * @match_clock: if provided, @best_clock P divider must
  81          *               match the P divider from @match_clock
  82          *               used for LVDS downclocking
  83          * @best_clock: best PLL values found
  84          *
  85          * Returns true on success, false on failure.
  86          */
  87         bool (*find_pll)(const intel_limit_t *limit,
  88                          struct drm_crtc *crtc,
  89                          int target, int refclk,
  90                          intel_clock_t *match_clock,
  91                          intel_clock_t *best_clock);
  92 };
  93
  94 /* FDI */
  95 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  96
  97 int
  98 intel_pch_rawclk(struct drm_device *dev)
  99 {
 100         struct drm_i915_private *dev_priv = dev->dev_private;
 101
 102         WARN_ON(!HAS_PCH_SPLIT(dev));
 103
 104         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 105 }
 106
 107 static bool
 108 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 109                     int target, int refclk, intel_clock_t *match_clock,
 110                     intel_clock_t *best_clock);
 111 static bool
 112 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 113                         int target, int refclk, intel_clock_t *match_clock,
 114                         intel_clock_t *best_clock);
 115
 116 static bool
 117 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 118                       int target, int refclk, intel_clock_t *match_clock,
 119                       intel_clock_t *best_clock);
 120 static bool
 121 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 122                            int target, int refclk, intel_clock_t *match_clock,
 123                            intel_clock_t *best_clock);
 124
 125 static bool
 126 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 127                         int target, int refclk, intel_clock_t *match_clock,
 128                         intel_clock_t *best_clock);
 129
 130 static inline u32 /* units of 100MHz */
 131 intel_fdi_link_freq(struct drm_device *dev)
 132 {
 133         if (IS_GEN5(dev)) {
 134                 struct drm_i915_private *dev_priv = dev->dev_private;
 135                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 136         } else
 137                 return 27;
 138 }
 139
 140 static const intel_limit_t intel_limits_i8xx_dvo = {
 141         .dot = { .min = 25000, .max = 350000 },
 142         .vco = { .min = 930000, .max = 1400000 },
 143         .n = { .min = 3, .max = 16 },
 144         .m = { .min = 96, .max = 140 },
 145         .m1 = { .min = 18, .max = 26 },
 146         .m2 = { .min = 6, .max = 16 },
 147         .p = { .min = 4, .max = 128 },
 148         .p1 = { .min = 2, .max = 33 },
 149         .p2 = { .dot_limit = 165000,
 150                 .p2_slow = 4, .p2_fast = 2 },
 151         .find_pll = intel_find_best_PLL,
 152 };
 153
 154 static const intel_limit_t intel_limits_i8xx_lvds = {
 155         .dot = { .min = 25000, .max = 350000 },
 156         .vco = { .min = 930000, .max = 1400000 },
 157         .n = { .min = 3, .max = 16 },
 158         .m = { .min = 96, .max = 140 },
 159         .m1 = { .min = 18, .max = 26 },
 160         .m2 = { .min = 6, .max = 16 },
 161         .p = { .min = 4, .max = 128 },
 162         .p1 = { .min = 1, .max = 6 },
 163         .p2 = { .dot_limit = 165000,
 164                 .p2_slow = 14, .p2_fast = 7 },
 165         .find_pll = intel_find_best_PLL,
 166 };
 167
 168 static const intel_limit_t intel_limits_i9xx_sdvo = {
 169         .dot = { .min = 20000, .max = 400000 },
 170         .vco = { .min = 1400000, .max = 2800000 },
 171         .n = { .min = 1, .max = 6 },
 172         .m = { .min = 70, .max = 120 },
 173         .m1 = { .min = 8, .max = 18 },
 174         .m2 = { .min = 3, .max = 7 },
 175         .p = { .min = 5, .max = 80 },
 176         .p1 = { .min = 1, .max = 8 },
 177         .p2 = { .dot_limit = 200000,
 178                 .p2_slow = 10, .p2_fast = 5 },
 179         .find_pll = intel_find_best_PLL,
 180 };
 181
 182 static const intel_limit_t intel_limits_i9xx_lvds = {
 183         .dot = { .min = 20000, .max = 400000 },
 184         .vco = { .min = 1400000, .max = 2800000 },
 185         .n = { .min = 1, .max = 6 },
 186         .m = { .min = 70, .max = 120 },
 187         .m1 = { .min = 8, .max = 18 },
 188         .m2 = { .min = 3, .max = 7 },
 189         .p = { .min = 7, .max = 98 },
 190         .p1 = { .min = 1, .max = 8 },
 191         .p2 = { .dot_limit = 112000,
 192                 .p2_slow = 14, .p2_fast = 7 },
 193         .find_pll = intel_find_best_PLL,
 194 };
 195
 196
 197 static const intel_limit_t intel_limits_g4x_sdvo = {
 198         .dot = { .min = 25000, .max = 270000 },
 199         .vco = { .min = 1750000, .max = 3500000},
 200         .n = { .min = 1, .max = 4 },
 201         .m = { .min = 104, .max = 138 },
 202         .m1 = { .min = 17, .max = 23 },
 203         .m2 = { .min = 5, .max = 11 },
 204         .p = { .min = 10, .max = 30 },
 205         .p1 = { .min = 1, .max = 3},
 206         .p2 = { .dot_limit = 270000,
 207                 .p2_slow = 10,
 208                 .p2_fast = 10
 209         },
 210         .find_pll = intel_g4x_find_best_PLL,
 211 };
 212
 213 static const intel_limit_t intel_limits_g4x_hdmi = {
 214         .dot = { .min = 22000, .max = 400000 },
 215         .vco = { .min = 1750000, .max = 3500000},
 216         .n = { .min = 1, .max = 4 },
 217         .m = { .min = 104, .max = 138 },
 218         .m1 = { .min = 16, .max = 23 },
 219         .m2 = { .min = 5, .max = 11 },
 220         .p = { .min = 5, .max = 80 },
 221         .p1 = { .min = 1, .max = 8},
 222         .p2 = { .dot_limit = 165000,
 223                 .p2_slow = 10, .p2_fast = 5 },
 224         .find_pll = intel_g4x_find_best_PLL,
 225 };
 226
 227 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 228         .dot = { .min = 20000, .max = 115000 },
 229         .vco = { .min = 1750000, .max = 3500000 },
 230         .n = { .min = 1, .max = 3 },
 231         .m = { .min = 104, .max = 138 },
 232         .m1 = { .min = 17, .max = 23 },
 233         .m2 = { .min = 5, .max = 11 },
 234         .p = { .min = 28, .max = 112 },
 235         .p1 = { .min = 2, .max = 8 },
 236         .p2 = { .dot_limit = 0,
 237                 .p2_slow = 14, .p2_fast = 14
 238         },
 239         .find_pll = intel_g4x_find_best_PLL,
 240 };
 241
 242 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 243         .dot = { .min = 80000, .max = 224000 },
 244         .vco = { .min = 1750000, .max = 3500000 },
 245         .n = { .min = 1, .max = 3 },
 246         .m = { .min = 104, .max = 138 },
 247         .m1 = { .min = 17, .max = 23 },
 248         .m2 = { .min = 5, .max = 11 },
 249         .p = { .min = 14, .max = 42 },
 250         .p1 = { .min = 2, .max = 6 },
 251         .p2 = { .dot_limit = 0,
 252                 .p2_slow = 7, .p2_fast = 7
 253         },
 254         .find_pll = intel_g4x_find_best_PLL,
 255 };
 256
 257 static const intel_limit_t intel_limits_g4x_display_port = {
 258         .dot = { .min = 161670, .max = 227000 },
 259         .vco = { .min = 1750000, .max = 3500000},
 260         .n = { .min = 1, .max = 2 },
 261         .m = { .min = 97, .max = 108 },
 262         .m1 = { .min = 0x10, .max = 0x12 },
 263         .m2 = { .min = 0x05, .max = 0x06 },
 264         .p = { .min = 10, .max = 20 },
 265         .p1 = { .min = 1, .max = 2},
 266         .p2 = { .dot_limit = 0,
 267                 .p2_slow = 10, .p2_fast = 10 },
 268         .find_pll = intel_find_pll_g4x_dp,
 269 };
 270
 271 static const intel_limit_t intel_limits_pineview_sdvo = {
 272         .dot = { .min = 20000, .max = 400000},
 273         .vco = { .min = 1700000, .max = 3500000 },
 274         /* Pineview's Ncounter is a ring counter */
 275         .n = { .min = 3, .max = 6 },
 276         .m = { .min = 2, .max = 256 },
 277         /* Pineview only has one combined m divider, which we treat as m2. */
 278         .m1 = { .min = 0, .max = 0 },
 279         .m2 = { .min = 0, .max = 254 },
 280         .p = { .min = 5, .max = 80 },
 281         .p1 = { .min = 1, .max = 8 },
 282         .p2 = { .dot_limit = 200000,
 283                 .p2_slow = 10, .p2_fast = 5 },
 284         .find_pll = intel_find_best_PLL,
 285 };
 286
 287 static const intel_limit_t intel_limits_pineview_lvds = {
 288         .dot = { .min = 20000, .max = 400000 },
 289         .vco = { .min = 1700000, .max = 3500000 },
 290         .n = { .min = 3, .max = 6 },
 291         .m = { .min = 2, .max = 256 },
 292         .m1 = { .min = 0, .max = 0 },
 293         .m2 = { .min = 0, .max = 254 },
 294         .p = { .min = 7, .max = 112 },
 295         .p1 = { .min = 1, .max = 8 },
 296         .p2 = { .dot_limit = 112000,
 297                 .p2_slow = 14, .p2_fast = 14 },
 298         .find_pll = intel_find_best_PLL,
 299 };
 300
 301 /* Ironlake / Sandybridge
 302  *
 303  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 304  * the range value for them is (actual_value - 2).
 305  */
 306 static const intel_limit_t intel_limits_ironlake_dac = {
 307         .dot = { .min = 25000, .max = 350000 },
 308         .vco = { .min = 1760000, .max = 3510000 },
 309         .n = { .min = 1, .max = 5 },
 310         .m = { .min = 79, .max = 127 },
 311         .m1 = { .min = 12, .max = 22 },
 312         .m2 = { .min = 5, .max = 9 },
 313         .p = { .min = 5, .max = 80 },
 314         .p1 = { .min = 1, .max = 8 },
 315         .p2 = { .dot_limit = 225000,
 316                 .p2_slow = 10, .p2_fast = 5 },
 317         .find_pll = intel_g4x_find_best_PLL,
 318 };
 319
 320 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 321         .dot = { .min = 25000, .max = 350000 },
 322         .vco = { .min = 1760000, .max = 3510000 },
 323         .n = { .min = 1, .max = 3 },
 324         .m = { .min = 79, .max = 118 },
 325         .m1 = { .min = 12, .max = 22 },
 326         .m2 = { .min = 5, .max = 9 },
 327         .p = { .min = 28, .max = 112 },
 328         .p1 = { .min = 2, .max = 8 },
 329         .p2 = { .dot_limit = 225000,
 330                 .p2_slow = 14, .p2_fast = 14 },
 331         .find_pll = intel_g4x_find_best_PLL,
 332 };
 333
 334 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 335         .dot = { .min = 25000, .max = 350000 },
 336         .vco = { .min = 1760000, .max = 3510000 },
 337         .n = { .min = 1, .max = 3 },
 338         .m = { .min = 79, .max = 127 },
 339         .m1 = { .min = 12, .max = 22 },
 340         .m2 = { .min = 5, .max = 9 },
 341         .p = { .min = 14, .max = 56 },
 342         .p1 = { .min = 2, .max = 8 },
 343         .p2 = { .dot_limit = 225000,
 344                 .p2_slow = 7, .p2_fast = 7 },
 345         .find_pll = intel_g4x_find_best_PLL,
 346 };
 347
 348 /* LVDS 100mhz refclk limits. */
 349 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 350         .dot = { .min = 25000, .max = 350000 },
 351         .vco = { .min = 1760000, .max = 3510000 },
 352         .n = { .min = 1, .max = 2 },
 353         .m = { .min = 79, .max = 126 },
 354         .m1 = { .min = 12, .max = 22 },
 355         .m2 = { .min = 5, .max = 9 },
 356         .p = { .min = 28, .max = 112 },
 357         .p1 = { .min = 2, .max = 8 },
 358         .p2 = { .dot_limit = 225000,
 359                 .p2_slow = 14, .p2_fast = 14 },
 360         .find_pll = intel_g4x_find_best_PLL,
 361 };
 362
 363 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 364         .dot = { .min = 25000, .max = 350000 },
 365         .vco = { .min = 1760000, .max = 3510000 },
 366         .n = { .min = 1, .max = 3 },
 367         .m = { .min = 79, .max = 126 },
 368         .m1 = { .min = 12, .max = 22 },
 369         .m2 = { .min = 5, .max = 9 },
 370         .p = { .min = 14, .max = 42 },
 371         .p1 = { .min = 2, .max = 6 },
 372         .p2 = { .dot_limit = 225000,
 373                 .p2_slow = 7, .p2_fast = 7 },
 374         .find_pll = intel_g4x_find_best_PLL,
 375 };
 376
 377 static const intel_limit_t intel_limits_ironlake_display_port = {
 378         .dot = { .min = 25000, .max = 350000 },
 379         .vco = { .min = 1760000, .max = 3510000},
 380         .n = { .min = 1, .max = 2 },
 381         .m = { .min = 81, .max = 90 },
 382         .m1 = { .min = 12, .max = 22 },
 383         .m2 = { .min = 5, .max = 9 },
 384         .p = { .min = 10, .max = 20 },
 385         .p1 = { .min = 1, .max = 2},
 386         .p2 = { .dot_limit = 0,
 387                 .p2_slow = 10, .p2_fast = 10 },
 388         .find_pll = intel_find_pll_ironlake_dp,
 389 };
 390
 391 static const intel_limit_t intel_limits_vlv_dac = {
 392         .dot = { .min = 25000, .max = 270000 },
 393         .vco = { .min = 4000000, .max = 6000000 },
 394         .n = { .min = 1, .max = 7 },
 395         .m = { .min = 22, .max = 450 }, /* guess */
 396         .m1 = { .min = 2, .max = 3 },
 397         .m2 = { .min = 11, .max = 156 },
 398         .p = { .min = 10, .max = 30 },
 399         .p1 = { .min = 2, .max = 3 },
 400         .p2 = { .dot_limit = 270000,
 401                 .p2_slow = 2, .p2_fast = 20 },
 402         .find_pll = intel_vlv_find_best_pll,
 403 };
 404
 405 static const intel_limit_t intel_limits_vlv_hdmi = {
 406         .dot = { .min = 20000, .max = 165000 },
 407         .vco = { .min = 4000000, .max = 5994000},
 408         .n = { .min = 1, .max = 7 },
 409         .m = { .min = 60, .max = 300 }, /* guess */
 410         .m1 = { .min = 2, .max = 3 },
 411         .m2 = { .min = 11, .max = 156 },
 412         .p = { .min = 10, .max = 30 },
 413         .p1 = { .min = 2, .max = 3 },
 414         .p2 = { .dot_limit = 270000,
 415                 .p2_slow = 2, .p2_fast = 20 },
 416         .find_pll = intel_vlv_find_best_pll,
 417 };
 418
 419 static const intel_limit_t intel_limits_vlv_dp = {
 420         .dot = { .min = 25000, .max = 270000 },
 421         .vco = { .min = 4000000, .max = 6000000 },
 422         .n = { .min = 1, .max = 7 },
 423         .m = { .min = 22, .max = 450 },
 424         .m1 = { .min = 2, .max = 3 },
 425         .m2 = { .min = 11, .max = 156 },
 426         .p = { .min = 10, .max = 30 },
 427         .p1 = { .min = 2, .max = 3 },
 428         .p2 = { .dot_limit = 270000,
 429                 .p2_slow = 2, .p2_fast = 20 },
 430         .find_pll = intel_vlv_find_best_pll,
 431 };
 432
 433 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 434 {
 435         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
 436
 437         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 438                 DRM_ERROR("DPIO idle wait timed out\n");
 439                 return 0;
 440         }
 441
 442         I915_WRITE(DPIO_REG, reg);
 443         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 444                    DPIO_BYTE);
 445         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 446                 DRM_ERROR("DPIO read wait timed out\n");
 447                 return 0;
 448         }
 449
 450         return I915_READ(DPIO_DATA);
 451 }
 452
 453 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
 454                              u32 val)
 455 {
 456         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
 457
 458         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 459                 DRM_ERROR("DPIO idle wait timed out\n");
 460                 return;
 461         }
 462
 463         I915_WRITE(DPIO_DATA, val);
 464         I915_WRITE(DPIO_REG, reg);
 465         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 466                    DPIO_BYTE);
 467         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 468                 DRM_ERROR("DPIO write wait timed out\n");
 469 }
 470
 471 static void vlv_init_dpio(struct drm_device *dev)
 472 {
 473         struct drm_i915_private *dev_priv = dev->dev_private;
 474
 475         /* Reset the DPIO config */
 476         I915_WRITE(DPIO_CTL, 0);
 477         POSTING_READ(DPIO_CTL);
 478         I915_WRITE(DPIO_CTL, 1);
 479         POSTING_READ(DPIO_CTL);
 480 }
 481
 482 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 483                                                 int refclk)
 484 {
 485         struct drm_device *dev = crtc->dev;
 486         const intel_limit_t *limit;
 487
 488         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 489                 if (intel_is_dual_link_lvds(dev)) {
 490                         if (refclk == 100000)
 491                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 492                         else
 493                                 limit = &intel_limits_ironlake_dual_lvds;
 494                 } else {
 495                         if (refclk == 100000)
 496                                 limit = &intel_limits_ironlake_single_lvds_100m;
 497                         else
 498                                 limit = &intel_limits_ironlake_single_lvds;
 499                 }
 500         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 501                    intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
 502                 limit = &intel_limits_ironlake_display_port;
 503         else
 504                 limit = &intel_limits_ironlake_dac;
 505
 506         return limit;
 507 }
 508
 509 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 510 {
 511         struct drm_device *dev = crtc->dev;
 512         const intel_limit_t *limit;
 513
 514         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 515                 if (intel_is_dual_link_lvds(dev))
 516                         limit = &intel_limits_g4x_dual_channel_lvds;
 517                 else
 518                         limit = &intel_limits_g4x_single_channel_lvds;
 519         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 520                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 521                 limit = &intel_limits_g4x_hdmi;
 522         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 523                 limit = &intel_limits_g4x_sdvo;
 524         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 525                 limit = &intel_limits_g4x_display_port;
 526         } else /* The option is for other outputs */
 527                 limit = &intel_limits_i9xx_sdvo;
 528
 529         return limit;
 530 }
 531
 532 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 533 {
 534         struct drm_device *dev = crtc->dev;
 535         const intel_limit_t *limit;
 536
 537         if (HAS_PCH_SPLIT(dev))
 538                 limit = intel_ironlake_limit(crtc, refclk);
 539         else if (IS_G4X(dev)) {
 540                 limit = intel_g4x_limit(crtc);
 541         } else if (IS_PINEVIEW(dev)) {
 542                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 543                         limit = &intel_limits_pineview_lvds;
 544                 else
 545                         limit = &intel_limits_pineview_sdvo;
 546         } else if (IS_VALLEYVIEW(dev)) {
 547                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 548                         limit = &intel_limits_vlv_dac;
 549                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 550                         limit = &intel_limits_vlv_hdmi;
 551                 else
 552                         limit = &intel_limits_vlv_dp;
 553         } else if (!IS_GEN2(dev)) {
 554                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 555                         limit = &intel_limits_i9xx_lvds;
 556                 else
 557                         limit = &intel_limits_i9xx_sdvo;
 558         } else {
 559                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 560                         limit = &intel_limits_i8xx_lvds;
 561                 else
 562                         limit = &intel_limits_i8xx_dvo;
 563         }
 564         return limit;
 565 }
 566
 567 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 568 static void pineview_clock(int refclk, intel_clock_t *clock)
 569 {
 570         clock->m = clock->m2 + 2;
 571         clock->p = clock->p1 * clock->p2;
 572         clock->vco = refclk * clock->m / clock->n;
 573         clock->dot = clock->vco / clock->p;
 574 }
 575
 576 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 577 {
 578         if (IS_PINEVIEW(dev)) {
 579                 pineview_clock(refclk, clock);
 580                 return;
 581         }
 582         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 583         clock->p = clock->p1 * clock->p2;
 584         clock->vco = refclk * clock->m / (clock->n + 2);
 585         clock->dot = clock->vco / clock->p;
 586 }
 587
 588 /**
 589  * Returns whether any output on the specified pipe is of the specified type
 590  */
 591 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 592 {
 593         struct drm_device *dev = crtc->dev;
 594         struct intel_encoder *encoder;
 595
 596         for_each_encoder_on_crtc(dev, crtc, encoder)
 597                 if (encoder->type == type)
 598                         return true;
 599
 600         return false;
 601 }
 602
 603 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 604 /**
 605  * Returns whether the given set of divisors are valid for a given refclk with
 606  * the given connectors.
 607  */
 608
 609 static bool intel_PLL_is_valid(struct drm_device *dev,
 610                                const intel_limit_t *limit,
 611                                const intel_clock_t *clock)
 612 {
 613         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 614                 INTELPllInvalid("p1 out of range\n");
 615         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 616                 INTELPllInvalid("p out of range\n");
 617         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 618                 INTELPllInvalid("m2 out of range\n");
 619         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 620                 INTELPllInvalid("m1 out of range\n");
 621         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 622                 INTELPllInvalid("m1 <= m2\n");
 623         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 624                 INTELPllInvalid("m out of range\n");
 625         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 626                 INTELPllInvalid("n out of range\n");
 627         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 628                 INTELPllInvalid("vco out of range\n");
 629         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 630          * connector, etc., rather than just a single range.
 631          */
 632         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 633                 INTELPllInvalid("dot out of range\n");
 634
 635         return true;
 636 }
 637
 638 static bool
 639 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 640                     int target, int refclk, intel_clock_t *match_clock,
 641                     intel_clock_t *best_clock)
 642
 643 {
 644         struct drm_device *dev = crtc->dev;
 645         intel_clock_t clock;
 646         int err = target;
 647
 648         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 649                 /*
 650                  * For LVDS just rely on its current settings for dual-channel.
 651                  * We haven't figured out how to reliably set up different
 652                  * single/dual channel state, if we even can.
 653                  */
 654                 if (intel_is_dual_link_lvds(dev))
 655                         clock.p2 = limit->p2.p2_fast;
 656                 else
 657                         clock.p2 = limit->p2.p2_slow;
 658         } else {
 659                 if (target < limit->p2.dot_limit)
 660                         clock.p2 = limit->p2.p2_slow;
 661                 else
 662                         clock.p2 = limit->p2.p2_fast;
 663         }
 664
 665         memset(best_clock, 0, sizeof(*best_clock));
 666
 667         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 668              clock.m1++) {
 669                 for (clock.m2 = limit->m2.min;
 670                      clock.m2 <= limit->m2.max; clock.m2++) {
 671                         /* m1 is always 0 in Pineview */
 672                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 673                                 break;
 674                         for (clock.n = limit->n.min;
 675                              clock.n <= limit->n.max; clock.n++) {
 676                                 for (clock.p1 = limit->p1.min;
 677                                         clock.p1 <= limit->p1.max; clock.p1++) {
 678                                         int this_err;
 679
 680                                         intel_clock(dev, refclk, &clock);
 681                                         if (!intel_PLL_is_valid(dev, limit,
 682                                                                 &clock))
 683                                                 continue;
 684                                         if (match_clock &&
 685                                             clock.p != match_clock->p)
 686                                                 continue;
 687
 688                                         this_err = abs(clock.dot - target);
 689                                         if (this_err < err) {
 690                                                 *best_clock = clock;
 691                                                 err = this_err;
 692                                         }
 693                                 }
 694                         }
 695                 }
 696         }
 697
 698         return (err != target);
 699 }
 700
 701 static bool
 702 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 703                         int target, int refclk, intel_clock_t *match_clock,
 704                         intel_clock_t *best_clock)
 705 {
 706         struct drm_device *dev = crtc->dev;
 707         intel_clock_t clock;
 708         int max_n;
 709         bool found;
 710         /* approximately equals target * 0.00585 */
 711         int err_most = (target >> 8) + (target >> 9);
 712         found = false;
 713
 714         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 715                 int lvds_reg;
 716
 717                 if (HAS_PCH_SPLIT(dev))
 718                         lvds_reg = PCH_LVDS;
 719                 else
 720                         lvds_reg = LVDS;
 721                 if (intel_is_dual_link_lvds(dev))
 722                         clock.p2 = limit->p2.p2_fast;
 723                 else
 724                         clock.p2 = limit->p2.p2_slow;
 725         } else {
 726                 if (target < limit->p2.dot_limit)
 727                         clock.p2 = limit->p2.p2_slow;
 728                 else
 729                         clock.p2 = limit->p2.p2_fast;
 730         }
 731
 732         memset(best_clock, 0, sizeof(*best_clock));
 733         max_n = limit->n.max;
 734         /* based on hardware requirement, prefer smaller n to precision */
 735         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 736                 /* based on hardware requirement, prefere larger m1,m2 */
 737                 for (clock.m1 = limit->m1.max;
 738                      clock.m1 >= limit->m1.min; clock.m1--) {
 739                         for (clock.m2 = limit->m2.max;
 740                              clock.m2 >= limit->m2.min; clock.m2--) {
 741                                 for (clock.p1 = limit->p1.max;
 742                                      clock.p1 >= limit->p1.min; clock.p1--) {
 743                                         int this_err;
 744
 745                                         intel_clock(dev, refclk, &clock);
 746                                         if (!intel_PLL_is_valid(dev, limit,
 747                                                                 &clock))
 748                                                 continue;
 749                                         if (match_clock &&
 750                                             clock.p != match_clock->p)
 751                                                 continue;
 752
 753                                         this_err = abs(clock.dot - target);
 754                                         if (this_err < err_most) {
 755                                                 *best_clock = clock;
 756                                                 err_most = this_err;
 757                                                 max_n = clock.n;
 758                                                 found = true;
 759                                         }
 760                                 }
 761                         }
 762                 }
 763         }
 764         return found;
 765 }
 766
 767 static bool
 768 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 769                            int target, int refclk, intel_clock_t *match_clock,
 770                            intel_clock_t *best_clock)
 771 {
 772         struct drm_device *dev = crtc->dev;
 773         intel_clock_t clock;
 774
 775         if (target < 200000) {
 776                 clock.n = 1;
 777                 clock.p1 = 2;
 778                 clock.p2 = 10;
 779                 clock.m1 = 12;
 780                 clock.m2 = 9;
 781         } else {
 782                 clock.n = 2;
 783                 clock.p1 = 1;
 784                 clock.p2 = 10;
 785                 clock.m1 = 14;
 786                 clock.m2 = 8;
 787         }
 788         intel_clock(dev, refclk, &clock);
 789         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 790         return true;
 791 }
 792
 793 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 794 static bool
 795 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 796                       int target, int refclk, intel_clock_t *match_clock,
 797                       intel_clock_t *best_clock)
 798 {
 799         intel_clock_t clock;
 800         if (target < 200000) {
 801                 clock.p1 = 2;
 802                 clock.p2 = 10;
 803                 clock.n = 2;
 804                 clock.m1 = 23;
 805                 clock.m2 = 8;
 806         } else {
 807                 clock.p1 = 1;
 808                 clock.p2 = 10;
 809                 clock.n = 1;
 810                 clock.m1 = 14;
 811                 clock.m2 = 2;
 812         }
 813         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 814         clock.p = (clock.p1 * clock.p2);
 815         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 816         clock.vco = 0;
 817         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 818         return true;
 819 }
 820 static bool
 821 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 822                         int target, int refclk, intel_clock_t *match_clock,
 823                         intel_clock_t *best_clock)
 824 {
 825         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 826         u32 m, n, fastclk;
 827         u32 updrate, minupdate, fracbits, p;
 828         unsigned long bestppm, ppm, absppm;
 829         int dotclk, flag;
 830
 831         flag = 0;
 832         dotclk = target * 1000;
 833         bestppm = 1000000;
 834         ppm = absppm = 0;
 835         fastclk = dotclk / (2*100);
 836         updrate = 0;
 837         minupdate = 19200;
 838         fracbits = 1;
 839         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 840         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 841
 842         /* based on hardware requirement, prefer smaller n to precision */
 843         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 844                 updrate = refclk / n;
 845                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 846                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 847                                 if (p2 > 10)
 848                                         p2 = p2 - 1;
 849                                 p = p1 * p2;
 850                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 851                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 852                                         m2 = (((2*(fastclk * p * n / m1 )) +
 853                                                refclk) / (2*refclk));
 854                                         m = m1 * m2;
 855                                         vco = updrate * m;
 856                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 857                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 858                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 859                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 860                                                         bestppm = 0;
 861                                                         flag = 1;
 862                                                 }
 863                                                 if (absppm < bestppm - 10) {
 864                                                         bestppm = absppm;
 865                                                         flag = 1;
 866                                                 }
 867                                                 if (flag) {
 868                                                         bestn = n;
 869                                                         bestm1 = m1;
 870                                                         bestm2 = m2;
 871                                                         bestp1 = p1;
 872                                                         bestp2 = p2;
 873                                                         flag = 0;
 874                                                 }
 875                                         }
 876                                 }
 877                         }
 878                 }
 879         }
 880         best_clock->n = bestn;
 881         best_clock->m1 = bestm1;
 882         best_clock->m2 = bestm2;
 883         best_clock->p1 = bestp1;
 884         best_clock->p2 = bestp2;
 885
 886         return true;
 887 }
 888
 889 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 890                                              enum pipe pipe)
 891 {
 892         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 893         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 894
 895         return intel_crtc->cpu_transcoder;
 896 }
 897
 898 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 899 {
 900         struct drm_i915_private *dev_priv = dev->dev_private;
 901         u32 frame, frame_reg = PIPEFRAME(pipe);
 902
 903         frame = I915_READ(frame_reg);
 904
 905         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 906                 DRM_DEBUG_KMS("vblank wait timed out\n");
 907 }
 908
 909 /**
 910  * intel_wait_for_vblank - wait for vblank on a given pipe
 911  * @dev: drm device
 912  * @pipe: pipe to wait for
 913  *
 914  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 915  * mode setting code.
 916  */
 917 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 918 {
 919         struct drm_i915_private *dev_priv = dev->dev_private;
 920         int pipestat_reg = PIPESTAT(pipe);
 921
 922         if (INTEL_INFO(dev)->gen >= 5) {
 923                 ironlake_wait_for_vblank(dev, pipe);
 924                 return;
 925         }
 926
 927         /* Clear existing vblank status. Note this will clear any other
 928          * sticky status fields as well.
 929          *
 930          * This races with i915_driver_irq_handler() with the result
 931          * that either function could miss a vblank event.  Here it is not
 932          * fatal, as we will either wait upon the next vblank interrupt or
 933          * timeout.  Generally speaking intel_wait_for_vblank() is only
 934          * called during modeset at which time the GPU should be idle and
 935          * should *not* be performing page flips and thus not waiting on
 936          * vblanks...
 937          * Currently, the result of us stealing a vblank from the irq
 938          * handler is that a single frame will be skipped during swapbuffers.
 939          */
 940         I915_WRITE(pipestat_reg,
 941                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 942
 943         /* Wait for vblank interrupt bit to set */
 944         if (wait_for(I915_READ(pipestat_reg) &
 945                      PIPE_VBLANK_INTERRUPT_STATUS,
 946                      50))
 947                 DRM_DEBUG_KMS("vblank wait timed out\n");
 948 }
 949
 950 /*
 951  * intel_wait_for_pipe_off - wait for pipe to turn off
 952  * @dev: drm device
 953  * @pipe: pipe to wait for
 954  *
 955  * After disabling a pipe, we can't wait for vblank in the usual way,
 956  * spinning on the vblank interrupt status bit, since we won't actually
 957  * see an interrupt when the pipe is disabled.
 958  *
 959  * On Gen4 and above:
 960  *   wait for the pipe register state bit to turn off
 961  *
 962  * Otherwise:
 963  *   wait for the display line value to settle (it usually
 964  *   ends up stopping at the start of the next frame).
 965  *
 966  */
 967 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 968 {
 969         struct drm_i915_private *dev_priv = dev->dev_private;
 970         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 971                                                                       pipe);
 972
 973         if (INTEL_INFO(dev)->gen >= 4) {
 974                 int reg = PIPECONF(cpu_transcoder);
 975
 976                 /* Wait for the Pipe State to go off */
 977                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 978                              100))
 979                         WARN(1, "pipe_off wait timed out\n");
 980         } else {
 981                 u32 last_line, line_mask;
 982                 int reg = PIPEDSL(pipe);
 983                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 984
 985                 if (IS_GEN2(dev))
 986                         line_mask = DSL_LINEMASK_GEN2;
 987                 else
 988                         line_mask = DSL_LINEMASK_GEN3;
 989
 990                 /* Wait for the display line to settle */
 991                 do {
 992                         last_line = I915_READ(reg) & line_mask;
 993                         mdelay(5);
 994                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 995                          time_after(timeout, jiffies));
 996                 if (time_after(jiffies, timeout))
 997                         WARN(1, "pipe_off wait timed out\n");
 998         }
 999 }
1000
1001 /*
1002  * ibx_digital_port_connected - is the specified port connected?
1003  * @dev_priv: i915 private structure
1004  * @port: the port to test
1005  *
1006  * Returns true if @port is connected, false otherwise.
1007  */
1008 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1009                                 struct intel_digital_port *port)
1010 {
1011         u32 bit;
1012
1013         if (HAS_PCH_IBX(dev_priv->dev)) {
1014                 switch(port->port) {
1015                 case PORT_B:
1016                         bit = SDE_PORTB_HOTPLUG;
1017                         break;
1018                 case PORT_C:
1019                         bit = SDE_PORTC_HOTPLUG;
1020                         break;
1021                 case PORT_D:
1022                         bit = SDE_PORTD_HOTPLUG;
1023                         break;
1024                 default:
1025                         return true;
1026                 }
1027         } else {
1028                 switch(port->port) {
1029                 case PORT_B:
1030                         bit = SDE_PORTB_HOTPLUG_CPT;
1031                         break;
1032                 case PORT_C:
1033                         bit = SDE_PORTC_HOTPLUG_CPT;
1034                         break;
1035                 case PORT_D:
1036                         bit = SDE_PORTD_HOTPLUG_CPT;
1037                         break;
1038                 default:
1039                         return true;
1040                 }
1041         }
1042
1043         return I915_READ(SDEISR) & bit;
1044 }
1045
1046 static const char *state_string(bool enabled)
1047 {
1048         return enabled ? "on" : "off";
1049 }
1050
1051 /* Only for pre-ILK configs */
1052 static void assert_pll(struct drm_i915_private *dev_priv,
1053                        enum pipe pipe, bool state)
1054 {
1055         int reg;
1056         u32 val;
1057         bool cur_state;
1058
1059         reg = DPLL(pipe);
1060         val = I915_READ(reg);
1061         cur_state = !!(val & DPLL_VCO_ENABLE);
1062         WARN(cur_state != state,
1063              "PLL state assertion failure (expected %s, current %s)\n",
1064              state_string(state), state_string(cur_state));
1065 }
1066 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1067 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1068
1069 /* For ILK+ */
1070 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1071                            struct intel_pch_pll *pll,
1072                            struct intel_crtc *crtc,
1073                            bool state)
1074 {
1075         u32 val;
1076         bool cur_state;
1077
1078         if (HAS_PCH_LPT(dev_priv->dev)) {
1079                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1080                 return;
1081         }
1082
1083         if (WARN (!pll,
1084                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
1085                 return;
1086
1087         val = I915_READ(pll->pll_reg);
1088         cur_state = !!(val & DPLL_VCO_ENABLE);
1089         WARN(cur_state != state,
1090              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1091              pll->pll_reg, state_string(state), state_string(cur_state), val);
1092
1093         /* Make sure the selected PLL is correctly attached to the transcoder */
1094         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1095                 u32 pch_dpll;
1096
1097                 pch_dpll = I915_READ(PCH_DPLL_SEL);
1098                 cur_state = pll->pll_reg == _PCH_DPLL_B;
1099                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1100                           "PLL[%d] not attached to this transcoder %d: %08x\n",
1101                           cur_state, crtc->pipe, pch_dpll)) {
1102                         cur_state = !!(val >> (4*crtc->pipe + 3));
1103                         WARN(cur_state != state,
1104                              "PLL[%d] not %s on this transcoder %d: %08x\n",
1105                              pll->pll_reg == _PCH_DPLL_B,
1106                              state_string(state),
1107                              crtc->pipe,
1108                              val);
1109                 }
1110         }
1111 }
1112 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1113 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1114
1115 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1116                           enum pipe pipe, bool state)
1117 {
1118         int reg;
1119         u32 val;
1120         bool cur_state;
1121         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1122                                                                       pipe);
1123
1124         if (HAS_DDI(dev_priv->dev)) {
1125                 /* DDI does not have a specific FDI_TX register */
1126                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1127                 val = I915_READ(reg);
1128                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1129         } else {
1130                 reg = FDI_TX_CTL(pipe);
1131                 val = I915_READ(reg);
1132                 cur_state = !!(val & FDI_TX_ENABLE);
1133         }
1134         WARN(cur_state != state,
1135              "FDI TX state assertion failure (expected %s, current %s)\n",
1136              state_string(state), state_string(cur_state));
1137 }
1138 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1139 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1140
1141 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1142                           enum pipe pipe, bool state)
1143 {
1144         int reg;
1145         u32 val;
1146         bool cur_state;
1147
1148         reg = FDI_RX_CTL(pipe);
1149         val = I915_READ(reg);
1150         cur_state = !!(val & FDI_RX_ENABLE);
1151         WARN(cur_state != state,
1152              "FDI RX state assertion failure (expected %s, current %s)\n",
1153              state_string(state), state_string(cur_state));
1154 }
1155 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1156 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1157
1158 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1159                                       enum pipe pipe)
1160 {
1161         int reg;
1162         u32 val;
1163
1164         /* ILK FDI PLL is always enabled */
1165         if (dev_priv->info->gen == 5)
1166                 return;
1167
1168         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1169         if (HAS_DDI(dev_priv->dev))
1170                 return;
1171
1172         reg = FDI_TX_CTL(pipe);
1173         val = I915_READ(reg);
1174         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1175 }
1176
1177 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1178                                       enum pipe pipe)
1179 {
1180         int reg;
1181         u32 val;
1182
1183         reg = FDI_RX_CTL(pipe);
1184         val = I915_READ(reg);
1185         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1186 }
1187
1188 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1189                                   enum pipe pipe)
1190 {
1191         int pp_reg, lvds_reg;
1192         u32 val;
1193         enum pipe panel_pipe = PIPE_A;
1194         bool locked = true;
1195
1196         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1197                 pp_reg = PCH_PP_CONTROL;
1198                 lvds_reg = PCH_LVDS;
1199         } else {
1200                 pp_reg = PP_CONTROL;
1201                 lvds_reg = LVDS;
1202         }
1203
1204         val = I915_READ(pp_reg);
1205         if (!(val & PANEL_POWER_ON) ||
1206             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1207                 locked = false;
1208
1209         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1210                 panel_pipe = PIPE_B;
1211
1212         WARN(panel_pipe == pipe && locked,
1213              "panel assertion failure, pipe %c regs locked\n",
1214              pipe_name(pipe));
1215 }
1216
1217 void assert_pipe(struct drm_i915_private *dev_priv,
1218                  enum pipe pipe, bool state)
1219 {
1220         int reg;
1221         u32 val;
1222         bool cur_state;
1223         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1224                                                                       pipe);
1225
1226         /* if we need the pipe A quirk it must be always on */
1227         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1228                 state = true;
1229
1230         if (!intel_using_power_well(dev_priv->dev) &&
1231             cpu_transcoder != TRANSCODER_EDP) {
1232                 cur_state = false;
1233         } else {
1234                 reg = PIPECONF(cpu_transcoder);
1235                 val = I915_READ(reg);
1236                 cur_state = !!(val & PIPECONF_ENABLE);
1237         }
1238
1239         WARN(cur_state != state,
1240              "pipe %c assertion failure (expected %s, current %s)\n",
1241              pipe_name(pipe), state_string(state), state_string(cur_state));
1242 }
1243
1244 static void assert_plane(struct drm_i915_private *dev_priv,
1245                          enum plane plane, bool state)
1246 {
1247         int reg;
1248         u32 val;
1249         bool cur_state;
1250
1251         reg = DSPCNTR(plane);
1252         val = I915_READ(reg);
1253         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1254         WARN(cur_state != state,
1255              "plane %c assertion failure (expected %s, current %s)\n",
1256              plane_name(plane), state_string(state), state_string(cur_state));
1257 }
1258
1259 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1261
1262 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1263                                    enum pipe pipe)
1264 {
1265         int reg, i;
1266         u32 val;
1267         int cur_pipe;
1268
1269         /* Planes are fixed to pipes on ILK+ */
1270         if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
1271                 reg = DSPCNTR(pipe);
1272                 val = I915_READ(reg);
1273                 WARN((val & DISPLAY_PLANE_ENABLE),
1274                      "plane %c assertion failure, should be disabled but not\n",
1275                      plane_name(pipe));
1276                 return;
1277         }
1278
1279         /* Need to check both planes against the pipe */
1280         for (i = 0; i < 2; i++) {
1281                 reg = DSPCNTR(i);
1282                 val = I915_READ(reg);
1283                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1284                         DISPPLANE_SEL_PIPE_SHIFT;
1285                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1286                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1287                      plane_name(i), pipe_name(pipe));
1288         }
1289 }
1290
1291 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1292                                     enum pipe pipe)
1293 {
1294         int reg, i;
1295         u32 val;
1296
1297         if (!IS_VALLEYVIEW(dev_priv->dev))
1298                 return;
1299
1300         /* Need to check both planes against the pipe */
1301         for (i = 0; i < dev_priv->num_plane; i++) {
1302                 reg = SPCNTR(pipe, i);
1303                 val = I915_READ(reg);
1304                 WARN((val & SP_ENABLE),
1305                      "sprite %d assertion failure, should be off on pipe %c but is still active\n",
1306                      pipe * 2 + i, pipe_name(pipe));
1307         }
1308 }
1309
1310 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1311 {
1312         u32 val;
1313         bool enabled;
1314
1315         if (HAS_PCH_LPT(dev_priv->dev)) {
1316                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1317                 return;
1318         }
1319
1320         val = I915_READ(PCH_DREF_CONTROL);
1321         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1322                             DREF_SUPERSPREAD_SOURCE_MASK));
1323         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1324 }
1325
1326 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1327                                        enum pipe pipe)
1328 {
1329         int reg;
1330         u32 val;
1331         bool enabled;
1332
1333         reg = TRANSCONF(pipe);
1334         val = I915_READ(reg);
1335         enabled = !!(val & TRANS_ENABLE);
1336         WARN(enabled,
1337              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1338              pipe_name(pipe));
1339 }
1340
1341 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1342                             enum pipe pipe, u32 port_sel, u32 val)
1343 {
1344         if ((val & DP_PORT_EN) == 0)
1345                 return false;
1346
1347         if (HAS_PCH_CPT(dev_priv->dev)) {
1348                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1349                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1350                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1351                         return false;
1352         } else {
1353                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1354                         return false;
1355         }
1356         return true;
1357 }
1358
1359 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1360                               enum pipe pipe, u32 val)
1361 {
1362         if ((val & SDVO_ENABLE) == 0)
1363                 return false;
1364
1365         if (HAS_PCH_CPT(dev_priv->dev)) {
1366                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1367                         return false;
1368         } else {
1369                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1370                         return false;
1371         }
1372         return true;
1373 }
1374
1375 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1376                               enum pipe pipe, u32 val)
1377 {
1378         if ((val & LVDS_PORT_EN) == 0)
1379                 return false;
1380
1381         if (HAS_PCH_CPT(dev_priv->dev)) {
1382                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1383                         return false;
1384         } else {
1385                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1386                         return false;
1387         }
1388         return true;
1389 }
1390
1391 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1392                               enum pipe pipe, u32 val)
1393 {
1394         if ((val & ADPA_DAC_ENABLE) == 0)
1395                 return false;
1396         if (HAS_PCH_CPT(dev_priv->dev)) {
1397                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1398                         return false;
1399         } else {
1400                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1401                         return false;
1402         }
1403         return true;
1404 }
1405
1406 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1407                                    enum pipe pipe, int reg, u32 port_sel)
1408 {
1409         u32 val = I915_READ(reg);
1410         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1411              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1412              reg, pipe_name(pipe));
1413
1414         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1415              && (val & DP_PIPEB_SELECT),
1416              "IBX PCH dp port still using transcoder B\n");
1417 }
1418
1419 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1420                                      enum pipe pipe, int reg)
1421 {
1422         u32 val = I915_READ(reg);
1423         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1424              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1425              reg, pipe_name(pipe));
1426
1427         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1428              && (val & SDVO_PIPE_B_SELECT),
1429              "IBX PCH hdmi port still using transcoder B\n");
1430 }
1431
1432 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1433                                       enum pipe pipe)
1434 {
1435         int reg;
1436         u32 val;
1437
1438         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1439         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1440         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1441
1442         reg = PCH_ADPA;
1443         val = I915_READ(reg);
1444         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1445              "PCH VGA enabled on transcoder %c, should be disabled\n",
1446              pipe_name(pipe));
1447
1448         reg = PCH_LVDS;
1449         val = I915_READ(reg);
1450         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1451              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1452              pipe_name(pipe));
1453
1454         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1455         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1456         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1457 }
1458
1459 /**
1460  * intel_enable_pll - enable a PLL
1461  * @dev_priv: i915 private structure
1462  * @pipe: pipe PLL to enable
1463  *
1464  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1465  * make sure the PLL reg is writable first though, since the panel write
1466  * protect mechanism may be enabled.
1467  *
1468  * Note!  This is for pre-ILK only.
1469  *
1470  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1471  */
1472 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1473 {
1474         int reg;
1475         u32 val;
1476
1477         /* No really, not for ILK+ */
1478         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1479
1480         /* PLL is protected by panel, make sure we can write it */
1481         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1482                 assert_panel_unlocked(dev_priv, pipe);
1483
1484         reg = DPLL(pipe);
1485         val = I915_READ(reg);
1486         val |= DPLL_VCO_ENABLE;
1487
1488         /* We do this three times for luck */
1489         I915_WRITE(reg, val);
1490         POSTING_READ(reg);
1491         udelay(150); /* wait for warmup */
1492         I915_WRITE(reg, val);
1493         POSTING_READ(reg);
1494         udelay(150); /* wait for warmup */
1495         I915_WRITE(reg, val);
1496         POSTING_READ(reg);
1497         udelay(150); /* wait for warmup */
1498 }
1499
1500 /**
1501  * intel_disable_pll - disable a PLL
1502  * @dev_priv: i915 private structure
1503  * @pipe: pipe PLL to disable
1504  *
1505  * Disable the PLL for @pipe, making sure the pipe is off first.
1506  *
1507  * Note!  This is for pre-ILK only.
1508  */
1509 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1510 {
1511         int reg;
1512         u32 val;
1513
1514         /* Don't disable pipe A or pipe A PLLs if needed */
1515         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1516                 return;
1517
1518         /* Make sure the pipe isn't still relying on us */
1519         assert_pipe_disabled(dev_priv, pipe);
1520
1521         reg = DPLL(pipe);
1522         val = I915_READ(reg);
1523         val &= ~DPLL_VCO_ENABLE;
1524         I915_WRITE(reg, val);
1525         POSTING_READ(reg);
1526 }
1527
1528 /* SBI access */
1529 static void
1530 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1531                 enum intel_sbi_destination destination)
1532 {
1533         u32 tmp;
1534
1535         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1536
1537         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1538                                 100)) {
1539                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1540                 return;
1541         }
1542
1543         I915_WRITE(SBI_ADDR, (reg << 16));
1544         I915_WRITE(SBI_DATA, value);
1545
1546         if (destination == SBI_ICLK)
1547                 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1548         else
1549                 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1550         I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
1551
1552         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1553                                 100)) {
1554                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1555                 return;
1556         }
1557 }
1558
1559 static u32
1560 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1561                enum intel_sbi_destination destination)
1562 {
1563         u32 value = 0;
1564         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1565
1566         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1567                                 100)) {
1568                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1569                 return 0;
1570         }
1571
1572         I915_WRITE(SBI_ADDR, (reg << 16));
1573
1574         if (destination == SBI_ICLK)
1575                 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1576         else
1577                 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1578         I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
1579
1580         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1581                                 100)) {
1582                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1583                 return 0;
1584         }
1585
1586         return I915_READ(SBI_DATA);
1587 }
1588
1589 /**
1590  * ironlake_enable_pch_pll - enable PCH PLL
1591  * @dev_priv: i915 private structure
1592  * @pipe: pipe PLL to enable
1593  *
1594  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1595  * drives the transcoder clock.
1596  */
1597 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1598 {
1599         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1600         struct intel_pch_pll *pll;
1601         int reg;
1602         u32 val;
1603
1604         /* PCH PLLs only available on ILK, SNB and IVB */
1605         BUG_ON(dev_priv->info->gen < 5);
1606         pll = intel_crtc->pch_pll;
1607         if (pll == NULL)
1608                 return;
1609
1610         if (WARN_ON(pll->refcount == 0))
1611                 return;
1612
1613         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1614                       pll->pll_reg, pll->active, pll->on,
1615                       intel_crtc->base.base.id);
1616
1617         /* PCH refclock must be enabled first */
1618         assert_pch_refclk_enabled(dev_priv);
1619
1620         if (pll->active++ && pll->on) {
1621                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1622                 return;
1623         }
1624
1625         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1626
1627         reg = pll->pll_reg;
1628         val = I915_READ(reg);
1629         val |= DPLL_VCO_ENABLE;
1630         I915_WRITE(reg, val);
1631         POSTING_READ(reg);
1632         udelay(200);
1633
1634         pll->on = true;
1635 }
1636
1637 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1638 {
1639         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1640         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1641         int reg;
1642         u32 val;
1643
1644         /* PCH only available on ILK+ */
1645         BUG_ON(dev_priv->info->gen < 5);
1646         if (pll == NULL)
1647                return;
1648
1649         if (WARN_ON(pll->refcount == 0))
1650                 return;
1651
1652         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1653                       pll->pll_reg, pll->active, pll->on,
1654                       intel_crtc->base.base.id);
1655
1656         if (WARN_ON(pll->active == 0)) {
1657                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1658                 return;
1659         }
1660
1661         if (--pll->active) {
1662                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1663                 return;
1664         }
1665
1666         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1667
1668         /* Make sure transcoder isn't still depending on us */
1669         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1670
1671         reg = pll->pll_reg;
1672         val = I915_READ(reg);
1673         val &= ~DPLL_VCO_ENABLE;
1674         I915_WRITE(reg, val);
1675         POSTING_READ(reg);
1676         udelay(200);
1677
1678         pll->on = false;
1679 }
1680
1681 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1682                                            enum pipe pipe)
1683 {
1684         struct drm_device *dev = dev_priv->dev;
1685         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1686         uint32_t reg, val, pipeconf_val;
1687
1688         /* PCH only available on ILK+ */
1689         BUG_ON(dev_priv->info->gen < 5);
1690
1691         /* Make sure PCH DPLL is enabled */
1692         assert_pch_pll_enabled(dev_priv,
1693                                to_intel_crtc(crtc)->pch_pll,
1694                                to_intel_crtc(crtc));
1695
1696         /* FDI must be feeding us bits for PCH ports */
1697         assert_fdi_tx_enabled(dev_priv, pipe);
1698         assert_fdi_rx_enabled(dev_priv, pipe);
1699
1700         if (HAS_PCH_CPT(dev)) {
1701                 /* Workaround: Set the timing override bit before enabling the
1702                  * pch transcoder. */
1703                 reg = TRANS_CHICKEN2(pipe);
1704                 val = I915_READ(reg);
1705                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1706                 I915_WRITE(reg, val);
1707         }
1708
1709         reg = TRANSCONF(pipe);
1710         val = I915_READ(reg);
1711         pipeconf_val = I915_READ(PIPECONF(pipe));
1712
1713         if (HAS_PCH_IBX(dev_priv->dev)) {
1714                 /*
1715                  * make the BPC in transcoder be consistent with
1716                  * that in pipeconf reg.
1717                  */
1718                 val &= ~PIPECONF_BPC_MASK;
1719                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1720         }
1721
1722         val &= ~TRANS_INTERLACE_MASK;
1723         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1724                 if (HAS_PCH_IBX(dev_priv->dev) &&
1725                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1726                         val |= TRANS_LEGACY_INTERLACED_ILK;
1727                 else
1728                         val |= TRANS_INTERLACED;
1729         else
1730                 val |= TRANS_PROGRESSIVE;
1731
1732         I915_WRITE(reg, val | TRANS_ENABLE);
1733         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1734                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1735 }
1736
1737 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1738                                       enum transcoder cpu_transcoder)
1739 {
1740         u32 val, pipeconf_val;
1741
1742         /* PCH only available on ILK+ */
1743         BUG_ON(dev_priv->info->gen < 5);
1744
1745         /* FDI must be feeding us bits for PCH ports */
1746         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1747         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1748
1749         /* Workaround: set timing override bit. */
1750         val = I915_READ(_TRANSA_CHICKEN2);
1751         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1752         I915_WRITE(_TRANSA_CHICKEN2, val);
1753
1754         val = TRANS_ENABLE;
1755         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1756
1757         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1758             PIPECONF_INTERLACED_ILK)
1759                 val |= TRANS_INTERLACED;
1760         else
1761                 val |= TRANS_PROGRESSIVE;
1762
1763         I915_WRITE(TRANSCONF(TRANSCODER_A), val);
1764         if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1765                 DRM_ERROR("Failed to enable PCH transcoder\n");
1766 }
1767
1768 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1769                                             enum pipe pipe)
1770 {
1771         struct drm_device *dev = dev_priv->dev;
1772         uint32_t reg, val;
1773
1774         /* FDI relies on the transcoder */
1775         assert_fdi_tx_disabled(dev_priv, pipe);
1776         assert_fdi_rx_disabled(dev_priv, pipe);
1777
1778         /* Ports must be off as well */
1779         assert_pch_ports_disabled(dev_priv, pipe);
1780
1781         reg = TRANSCONF(pipe);
1782         val = I915_READ(reg);
1783         val &= ~TRANS_ENABLE;
1784         I915_WRITE(reg, val);
1785         /* wait for PCH transcoder off, transcoder state */
1786         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1787                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1788
1789         if (!HAS_PCH_IBX(dev)) {
1790                 /* Workaround: Clear the timing override chicken bit again. */
1791                 reg = TRANS_CHICKEN2(pipe);
1792                 val = I915_READ(reg);
1793                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1794                 I915_WRITE(reg, val);
1795         }
1796 }
1797
1798 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1799 {
1800         u32 val;
1801
1802         val = I915_READ(_TRANSACONF);
1803         val &= ~TRANS_ENABLE;
1804         I915_WRITE(_TRANSACONF, val);
1805         /* wait for PCH transcoder off, transcoder state */
1806         if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1807                 DRM_ERROR("Failed to disable PCH transcoder\n");
1808
1809         /* Workaround: clear timing override bit. */
1810         val = I915_READ(_TRANSA_CHICKEN2);
1811         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1812         I915_WRITE(_TRANSA_CHICKEN2, val);
1813 }
1814
1815 /**
1816  * intel_enable_pipe - enable a pipe, asserting requirements
1817  * @dev_priv: i915 private structure
1818  * @pipe: pipe to enable
1819  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1820  *
1821  * Enable @pipe, making sure that various hardware specific requirements
1822  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1823  *
1824  * @pipe should be %PIPE_A or %PIPE_B.
1825  *
1826  * Will wait until the pipe is actually running (i.e. first vblank) before
1827  * returning.
1828  */
1829 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1830                               bool pch_port)
1831 {
1832         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1833                                                                       pipe);
1834         enum pipe pch_transcoder;
1835         int reg;
1836         u32 val;
1837
1838         if (HAS_PCH_LPT(dev_priv->dev))
1839                 pch_transcoder = TRANSCODER_A;
1840         else
1841                 pch_transcoder = pipe;
1842
1843         /*
1844          * A pipe without a PLL won't actually be able to drive bits from
1845          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1846          * need the check.
1847          */
1848         if (!HAS_PCH_SPLIT(dev_priv->dev))
1849                 assert_pll_enabled(dev_priv, pipe);
1850         else {
1851                 if (pch_port) {
1852                         /* if driving the PCH, we need FDI enabled */
1853                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1854                         assert_fdi_tx_pll_enabled(dev_priv,
1855                                                   (enum pipe) cpu_transcoder);
1856                 }
1857                 /* FIXME: assert CPU port conditions for SNB+ */
1858         }
1859
1860         reg = PIPECONF(cpu_transcoder);
1861         val = I915_READ(reg);
1862         if (val & PIPECONF_ENABLE)
1863                 return;
1864
1865         I915_WRITE(reg, val | PIPECONF_ENABLE);
1866         intel_wait_for_vblank(dev_priv->dev, pipe);
1867 }
1868
1869 /**
1870  * intel_disable_pipe - disable a pipe, asserting requirements
1871  * @dev_priv: i915 private structure
1872  * @pipe: pipe to disable
1873  *
1874  * Disable @pipe, making sure that various hardware specific requirements
1875  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1876  *
1877  * @pipe should be %PIPE_A or %PIPE_B.
1878  *
1879  * Will wait until the pipe has shut down before returning.
1880  */
1881 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1882                                enum pipe pipe)
1883 {
1884         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1885                                                                       pipe);
1886         int reg;
1887         u32 val;
1888
1889         /*
1890          * Make sure planes won't keep trying to pump pixels to us,
1891          * or we might hang the display.
1892          */
1893         assert_planes_disabled(dev_priv, pipe);
1894         assert_sprites_disabled(dev_priv, pipe);
1895
1896         /* Don't disable pipe A or pipe A PLLs if needed */
1897         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1898                 return;
1899
1900         reg = PIPECONF(cpu_transcoder);
1901         val = I915_READ(reg);
1902         if ((val & PIPECONF_ENABLE) == 0)
1903                 return;
1904
1905         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1906         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1907 }
1908
1909 /*
1910  * Plane regs are double buffered, going from enabled->disabled needs a
1911  * trigger in order to latch.  The display address reg provides this.
1912  */
1913 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1914                                       enum plane plane)
1915 {
1916         if (dev_priv->info->gen >= 4)
1917                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1918         else
1919                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1920 }
1921
1922 /**
1923  * intel_enable_plane - enable a display plane on a given pipe
1924  * @dev_priv: i915 private structure
1925  * @plane: plane to enable
1926  * @pipe: pipe being fed
1927  *
1928  * Enable @plane on @pipe, making sure that @pipe is running first.
1929  */
1930 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1931                                enum plane plane, enum pipe pipe)
1932 {
1933         int reg;
1934         u32 val;
1935
1936         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1937         assert_pipe_enabled(dev_priv, pipe);
1938
1939         reg = DSPCNTR(plane);
1940         val = I915_READ(reg);
1941         if (val & DISPLAY_PLANE_ENABLE)
1942                 return;
1943
1944         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1945         intel_flush_display_plane(dev_priv, plane);
1946         intel_wait_for_vblank(dev_priv->dev, pipe);
1947 }
1948
1949 /**
1950  * intel_disable_plane - disable a display plane
1951  * @dev_priv: i915 private structure
1952  * @plane: plane to disable
1953  * @pipe: pipe consuming the data
1954  *
1955  * Disable @plane; should be an independent operation.
1956  */
1957 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1958                                 enum plane plane, enum pipe pipe)
1959 {
1960         int reg;
1961         u32 val;
1962
1963         reg = DSPCNTR(plane);
1964         val = I915_READ(reg);
1965         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1966                 return;
1967
1968         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1969         intel_flush_display_plane(dev_priv, plane);
1970         intel_wait_for_vblank(dev_priv->dev, pipe);
1971 }
1972
1973 static bool need_vtd_wa(struct drm_device *dev)
1974 {
1975 #ifdef CONFIG_INTEL_IOMMU
1976         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1977                 return true;
1978 #endif
1979         return false;
1980 }
1981
1982 int
1983 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1984                            struct drm_i915_gem_object *obj,
1985                            struct intel_ring_buffer *pipelined)
1986 {
1987         struct drm_i915_private *dev_priv = dev->dev_private;
1988         u32 alignment;
1989         int ret;
1990
1991         switch (obj->tiling_mode) {
1992         case I915_TILING_NONE:
1993                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1994                         alignment = 128 * 1024;
1995                 else if (INTEL_INFO(dev)->gen >= 4)
1996                         alignment = 4 * 1024;
1997                 else
1998                         alignment = 64 * 1024;
1999                 break;
2000         case I915_TILING_X:
2001                 /* pin() will align the object as required by fence */
2002                 alignment = 0;
2003                 break;
2004         case I915_TILING_Y:
2005                 /* Despite that we check this in framebuffer_init userspace can
2006                  * screw us over and change the tiling after the fact. Only
2007                  * pinned buffers can't change their tiling. */
2008                 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
2009                 return -EINVAL;
2010         default:
2011                 BUG();
2012         }
2013
2014         /* Note that the w/a also requires 64 PTE of padding following the
2015          * bo. We currently fill all unused PTE with the shadow page and so
2016          * we should always have valid PTE following the scanout preventing
2017          * the VT-d warning.
2018          */
2019         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2020                 alignment = 256 * 1024;
2021
2022         dev_priv->mm.interruptible = false;
2023         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2024         if (ret)
2025                 goto err_interruptible;
2026
2027         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2028          * fence, whereas 965+ only requires a fence if using
2029          * framebuffer compression.  For simplicity, we always install
2030          * a fence as the cost is not that onerous.
2031          */
2032         ret = i915_gem_object_get_fence(obj);
2033         if (ret)
2034                 goto err_unpin;
2035
2036         i915_gem_object_pin_fence(obj);
2037
2038         dev_priv->mm.interruptible = true;
2039         return 0;
2040
2041 err_unpin:
2042         i915_gem_object_unpin(obj);
2043 err_interruptible:
2044         dev_priv->mm.interruptible = true;
2045         return ret;
2046 }
2047
2048 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2049 {
2050         i915_gem_object_unpin_fence(obj);
2051         i915_gem_object_unpin(obj);
2052 }
2053
2054 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2055  * is assumed to be a power-of-two. */
2056 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2057                                              unsigned int tiling_mode,
2058                                              unsigned int cpp,
2059                                              unsigned int pitch)
2060 {
2061         if (tiling_mode != I915_TILING_NONE) {
2062                 unsigned int tile_rows, tiles;
2063
2064                 tile_rows = *y / 8;
2065                 *y %= 8;
2066
2067                 tiles = *x / (512/cpp);
2068                 *x %= 512/cpp;
2069
2070                 return tile_rows * pitch * 8 + tiles * 4096;
2071         } else {
2072                 unsigned int offset;
2073
2074                 offset = *y * pitch + *x * cpp;
2075                 *y = 0;
2076                 *x = (offset & 4095) / cpp;
2077                 return offset & -4096;
2078         }
2079 }
2080
2081 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2082                              int x, int y)
2083 {
2084         struct drm_device *dev = crtc->dev;
2085         struct drm_i915_private *dev_priv = dev->dev_private;
2086         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2087         struct intel_framebuffer *intel_fb;
2088         struct drm_i915_gem_object *obj;
2089         int plane = intel_crtc->plane;
2090         unsigned long linear_offset;
2091         u32 dspcntr;
2092         u32 reg;
2093
2094         switch (plane) {
2095         case 0:
2096         case 1:
2097                 break;
2098         default:
2099                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2100                 return -EINVAL;
2101         }
2102
2103         intel_fb = to_intel_framebuffer(fb);
2104         obj = intel_fb->obj;
2105
2106         reg = DSPCNTR(plane);
2107         dspcntr = I915_READ(reg);
2108         /* Mask out pixel format bits in case we change it */
2109         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2110         switch (fb->pixel_format) {
2111         case DRM_FORMAT_C8:
2112                 dspcntr |= DISPPLANE_8BPP;
2113                 break;
2114         case DRM_FORMAT_XRGB1555:
2115         case DRM_FORMAT_ARGB1555:
2116                 dspcntr |= DISPPLANE_BGRX555;
2117                 break;
2118         case DRM_FORMAT_RGB565:
2119                 dspcntr |= DISPPLANE_BGRX565;
2120                 break;
2121         case DRM_FORMAT_XRGB8888:
2122         case DRM_FORMAT_ARGB8888:
2123                 dspcntr |= DISPPLANE_BGRX888;
2124                 break;
2125         case DRM_FORMAT_XBGR8888:
2126         case DRM_FORMAT_ABGR8888:
2127                 dspcntr |= DISPPLANE_RGBX888;
2128                 break;
2129         case DRM_FORMAT_XRGB2101010:
2130         case DRM_FORMAT_ARGB2101010:
2131                 dspcntr |= DISPPLANE_BGRX101010;
2132                 break;
2133         case DRM_FORMAT_XBGR2101010:
2134         case DRM_FORMAT_ABGR2101010:
2135                 dspcntr |= DISPPLANE_RGBX101010;
2136                 break;
2137         default:
2138                 BUG();
2139         }
2140
2141         if (INTEL_INFO(dev)->gen >= 4) {
2142                 if (obj->tiling_mode != I915_TILING_NONE)
2143                         dspcntr |= DISPPLANE_TILED;
2144                 else
2145                         dspcntr &= ~DISPPLANE_TILED;
2146         }
2147
2148         I915_WRITE(reg, dspcntr);
2149
2150         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2151
2152         if (INTEL_INFO(dev)->gen >= 4) {
2153                 intel_crtc->dspaddr_offset =
2154                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2155                                                        fb->bits_per_pixel / 8,
2156                                                        fb->pitches[0]);
2157                 linear_offset -= intel_crtc->dspaddr_offset;
2158         } else {
2159                 intel_crtc->dspaddr_offset = linear_offset;
2160         }
2161
2162         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2163                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2164         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2165         if (INTEL_INFO(dev)->gen >= 4) {
2166                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2167                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
2168                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2169                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2170         } else
2171                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2172         POSTING_READ(reg);
2173
2174         return 0;
2175 }
2176
2177 static int ironlake_update_plane(struct drm_crtc *crtc,
2178                                  struct drm_framebuffer *fb, int x, int y)
2179 {
2180         struct drm_device *dev = crtc->dev;
2181         struct drm_i915_private *dev_priv = dev->dev_private;
2182         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2183         struct intel_framebuffer *intel_fb;
2184         struct drm_i915_gem_object *obj;
2185         int plane = intel_crtc->plane;
2186         unsigned long linear_offset;
2187         u32 dspcntr;
2188         u32 reg;
2189
2190         switch (plane) {
2191         case 0:
2192         case 1:
2193         case 2:
2194                 break;
2195         default:
2196                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2197                 return -EINVAL;
2198         }
2199
2200         intel_fb = to_intel_framebuffer(fb);
2201         obj = intel_fb->obj;
2202
2203         reg = DSPCNTR(plane);
2204         dspcntr = I915_READ(reg);
2205         /* Mask out pixel format bits in case we change it */
2206         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2207         switch (fb->pixel_format) {
2208         case DRM_FORMAT_C8:
2209                 dspcntr |= DISPPLANE_8BPP;
2210                 break;
2211         case DRM_FORMAT_RGB565:
2212                 dspcntr |= DISPPLANE_BGRX565;
2213                 break;
2214         case DRM_FORMAT_XRGB8888:
2215         case DRM_FORMAT_ARGB8888:
2216                 dspcntr |= DISPPLANE_BGRX888;
2217                 break;
2218         case DRM_FORMAT_XBGR8888:
2219         case DRM_FORMAT_ABGR8888:
2220                 dspcntr |= DISPPLANE_RGBX888;
2221                 break;
2222         case DRM_FORMAT_XRGB2101010:
2223         case DRM_FORMAT_ARGB2101010:
2224                 dspcntr |= DISPPLANE_BGRX101010;
2225                 break;
2226         case DRM_FORMAT_XBGR2101010:
2227         case DRM_FORMAT_ABGR2101010:
2228                 dspcntr |= DISPPLANE_RGBX101010;
2229                 break;
2230         default:
2231                 BUG();
2232         }
2233
2234         if (obj->tiling_mode != I915_TILING_NONE)
2235                 dspcntr |= DISPPLANE_TILED;
2236         else
2237                 dspcntr &= ~DISPPLANE_TILED;
2238
2239         /* must disable */
2240         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2241
2242         I915_WRITE(reg, dspcntr);
2243
2244         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2245         intel_crtc->dspaddr_offset =
2246                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2247                                                fb->bits_per_pixel / 8,
2248                                                fb->pitches[0]);
2249         linear_offset -= intel_crtc->dspaddr_offset;
2250
2251         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2252                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2253         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2254         I915_MODIFY_DISPBASE(DSPSURF(plane),
2255                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2256         if (IS_HASWELL(dev)) {
2257                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2258         } else {
2259                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2260                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2261         }
2262         POSTING_READ(reg);
2263
2264         return 0;
2265 }
2266
2267 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2268 static int
2269 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2270                            int x, int y, enum mode_set_atomic state)
2271 {
2272         struct drm_device *dev = crtc->dev;
2273         struct drm_i915_private *dev_priv = dev->dev_private;
2274
2275         if (dev_priv->display.disable_fbc)
2276                 dev_priv->display.disable_fbc(dev);
2277         intel_increase_pllclock(crtc);
2278
2279         return dev_priv->display.update_plane(crtc, fb, x, y);
2280 }
2281
2282 void intel_display_handle_reset(struct drm_device *dev)
2283 {
2284         struct drm_i915_private *dev_priv = dev->dev_private;
2285         struct drm_crtc *crtc;
2286
2287         /*
2288          * Flips in the rings have been nuked by the reset,
2289          * so complete all pending flips so that user space
2290          * will get its events and not get stuck.
2291          *
2292          * Also update the base address of all primary
2293          * planes to the the last fb to make sure we're
2294          * showing the correct fb after a reset.
2295          *
2296          * Need to make two loops over the crtcs so that we
2297          * don't try to grab a crtc mutex before the
2298          * pending_flip_queue really got woken up.
2299          */
2300
2301         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2302                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2303                 enum plane plane = intel_crtc->plane;
2304
2305                 intel_prepare_page_flip(dev, plane);
2306                 intel_finish_page_flip_plane(dev, plane);
2307         }
2308
2309         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2310                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2311
2312                 mutex_lock(&crtc->mutex);
2313                 if (intel_crtc->active)
2314                         dev_priv->display.update_plane(crtc, crtc->fb,
2315                                                        crtc->x, crtc->y);
2316                 mutex_unlock(&crtc->mutex);
2317         }
2318 }
2319
2320 static int
2321 intel_finish_fb(struct drm_framebuffer *old_fb)
2322 {
2323         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2324         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2325         bool was_interruptible = dev_priv->mm.interruptible;
2326         int ret;
2327
2328         /* Big Hammer, we also need to ensure that any pending
2329          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2330          * current scanout is retired before unpinning the old
2331          * framebuffer.
2332          *
2333          * This should only fail upon a hung GPU, in which case we
2334          * can safely continue.
2335          */
2336         dev_priv->mm.interruptible = false;
2337         ret = i915_gem_object_finish_gpu(obj);
2338         dev_priv->mm.interruptible = was_interruptible;
2339
2340         return ret;
2341 }
2342
2343 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2344 {
2345         struct drm_device *dev = crtc->dev;
2346         struct drm_i915_master_private *master_priv;
2347         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2348
2349         if (!dev->primary->master)
2350                 return;
2351
2352         master_priv = dev->primary->master->driver_priv;
2353         if (!master_priv->sarea_priv)
2354                 return;
2355
2356         switch (intel_crtc->pipe) {
2357         case 0:
2358                 master_priv->sarea_priv->pipeA_x = x;
2359                 master_priv->sarea_priv->pipeA_y = y;
2360                 break;
2361         case 1:
2362                 master_priv->sarea_priv->pipeB_x = x;
2363                 master_priv->sarea_priv->pipeB_y = y;
2364                 break;
2365         default:
2366                 break;
2367         }
2368 }
2369
2370 static int
2371 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2372                     struct drm_framebuffer *fb)
2373 {
2374         struct drm_device *dev = crtc->dev;
2375         struct drm_i915_private *dev_priv = dev->dev_private;
2376         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2377         struct drm_framebuffer *old_fb;
2378         int ret;
2379
2380         /* no fb bound */
2381         if (!fb) {
2382                 DRM_ERROR("No FB bound\n");
2383                 return 0;
2384         }
2385
2386         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2387                 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2388                                 intel_crtc->plane,
2389                                 INTEL_INFO(dev)->num_pipes);
2390                 return -EINVAL;
2391         }
2392
2393         mutex_lock(&dev->struct_mutex);
2394         ret = intel_pin_and_fence_fb_obj(dev,
2395                                          to_intel_framebuffer(fb)->obj,
2396                                          NULL);
2397         if (ret != 0) {
2398                 mutex_unlock(&dev->struct_mutex);
2399                 DRM_ERROR("pin & fence failed\n");
2400                 return ret;
2401         }
2402
2403         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2404         if (ret) {
2405                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2406                 mutex_unlock(&dev->struct_mutex);
2407                 DRM_ERROR("failed to update base address\n");
2408                 return ret;
2409         }
2410
2411         old_fb = crtc->fb;
2412         crtc->fb = fb;
2413         crtc->x = x;
2414         crtc->y = y;
2415
2416         if (old_fb) {
2417                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2418                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2419         }
2420
2421         intel_update_fbc(dev);
2422         mutex_unlock(&dev->struct_mutex);
2423
2424         intel_crtc_update_sarea_pos(crtc, x, y);
2425
2426         return 0;
2427 }
2428
2429 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2430 {
2431         struct drm_device *dev = crtc->dev;
2432         struct drm_i915_private *dev_priv = dev->dev_private;
2433         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2434         int pipe = intel_crtc->pipe;
2435         u32 reg, temp;
2436
2437         /* enable normal train */
2438         reg = FDI_TX_CTL(pipe);
2439         temp = I915_READ(reg);
2440         if (IS_IVYBRIDGE(dev)) {
2441                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2442                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2443         } else {
2444                 temp &= ~FDI_LINK_TRAIN_NONE;
2445                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2446         }
2447         I915_WRITE(reg, temp);
2448
2449         reg = FDI_RX_CTL(pipe);
2450         temp = I915_READ(reg);
2451         if (HAS_PCH_CPT(dev)) {
2452                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2453                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2454         } else {
2455                 temp &= ~FDI_LINK_TRAIN_NONE;
2456                 temp |= FDI_LINK_TRAIN_NONE;
2457         }
2458         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2459
2460         /* wait one idle pattern time */
2461         POSTING_READ(reg);
2462         udelay(1000);
2463
2464         /* IVB wants error correction enabled */
2465         if (IS_IVYBRIDGE(dev))
2466                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2467                            FDI_FE_ERRC_ENABLE);
2468 }
2469
2470 static void ivb_modeset_global_resources(struct drm_device *dev)
2471 {
2472         struct drm_i915_private *dev_priv = dev->dev_private;
2473         struct intel_crtc *pipe_B_crtc =
2474                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2475         struct intel_crtc *pipe_C_crtc =
2476                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2477         uint32_t temp;
2478
2479         /* When everything is off disable fdi C so that we could enable fdi B
2480          * with all lanes. XXX: This misses the case where a pipe is not using
2481          * any pch resources and so doesn't need any fdi lanes. */
2482         if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2483                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2484                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2485
2486                 temp = I915_READ(SOUTH_CHICKEN1);
2487                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2488                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2489                 I915_WRITE(SOUTH_CHICKEN1, temp);
2490         }
2491 }
2492
2493 /* The FDI link training functions for ILK/Ibexpeak. */
2494 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2495 {
2496         struct drm_device *dev = crtc->dev;
2497         struct drm_i915_private *dev_priv = dev->dev_private;
2498         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2499         int pipe = intel_crtc->pipe;
2500         int plane = intel_crtc->plane;
2501         u32 reg, temp, tries;
2502
2503         /* FDI needs bits from pipe & plane first */
2504         assert_pipe_enabled(dev_priv, pipe);
2505         assert_plane_enabled(dev_priv, plane);
2506
2507         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2508            for train result */
2509         reg = FDI_RX_IMR(pipe);
2510         temp = I915_READ(reg);
2511         temp &= ~FDI_RX_SYMBOL_LOCK;
2512         temp &= ~FDI_RX_BIT_LOCK;
2513         I915_WRITE(reg, temp);
2514         I915_READ(reg);
2515         udelay(150);
2516
2517         /* enable CPU FDI TX and PCH FDI RX */
2518         reg = FDI_TX_CTL(pipe);
2519         temp = I915_READ(reg);
2520         temp &= ~(7 << 19);
2521         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2522         temp &= ~FDI_LINK_TRAIN_NONE;
2523         temp |= FDI_LINK_TRAIN_PATTERN_1;
2524         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2525
2526         reg = FDI_RX_CTL(pipe);
2527         temp = I915_READ(reg);
2528         temp &= ~FDI_LINK_TRAIN_NONE;
2529         temp |= FDI_LINK_TRAIN_PATTERN_1;
2530         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2531
2532         POSTING_READ(reg);
2533         udelay(150);
2534
2535         /* Ironlake workaround, enable clock pointer after FDI enable*/
2536         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2537         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2538                    FDI_RX_PHASE_SYNC_POINTER_EN);
2539
2540         reg = FDI_RX_IIR(pipe);
2541         for (tries = 0; tries < 5; tries++) {
2542                 temp = I915_READ(reg);
2543                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2544
2545                 if ((temp & FDI_RX_BIT_LOCK)) {
2546                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2547                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2548                         break;
2549                 }
2550         }
2551         if (tries == 5)
2552                 DRM_ERROR("FDI train 1 fail!\n");
2553
2554         /* Train 2 */
2555         reg = FDI_TX_CTL(pipe);
2556         temp = I915_READ(reg);
2557         temp &= ~FDI_LINK_TRAIN_NONE;
2558         temp |= FDI_LINK_TRAIN_PATTERN_2;
2559         I915_WRITE(reg, temp);
2560
2561         reg = FDI_RX_CTL(pipe);
2562         temp = I915_READ(reg);
2563         temp &= ~FDI_LINK_TRAIN_NONE;
2564         temp |= FDI_LINK_TRAIN_PATTERN_2;
2565         I915_WRITE(reg, temp);
2566
2567         POSTING_READ(reg);
2568         udelay(150);
2569
2570         reg = FDI_RX_IIR(pipe);
2571         for (tries = 0; tries < 5; tries++) {
2572                 temp = I915_READ(reg);
2573                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2574
2575                 if (temp & FDI_RX_SYMBOL_LOCK) {
2576                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2577                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2578                         break;
2579                 }
2580         }
2581         if (tries == 5)
2582                 DRM_ERROR("FDI train 2 fail!\n");
2583
2584         DRM_DEBUG_KMS("FDI train done\n");
2585
2586 }
2587
2588 static const int snb_b_fdi_train_param[] = {
2589         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2590         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2591         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2592         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2593 };
2594
2595 /* The FDI link training functions for SNB/Cougarpoint. */
2596 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2597 {
2598         struct drm_device *dev = crtc->dev;
2599         struct drm_i915_private *dev_priv = dev->dev_private;
2600         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2601         int pipe = intel_crtc->pipe;
2602         u32 reg, temp, i, retry;
2603
2604         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2605            for train result */
2606         reg = FDI_RX_IMR(pipe);
2607         temp = I915_READ(reg);
2608         temp &= ~FDI_RX_SYMBOL_LOCK;
2609         temp &= ~FDI_RX_BIT_LOCK;
2610         I915_WRITE(reg, temp);
2611
2612         POSTING_READ(reg);
2613         udelay(150);
2614
2615         /* enable CPU FDI TX and PCH FDI RX */
2616         reg = FDI_TX_CTL(pipe);
2617         temp = I915_READ(reg);
2618         temp &= ~(7 << 19);
2619         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2620         temp &= ~FDI_LINK_TRAIN_NONE;
2621         temp |= FDI_LINK_TRAIN_PATTERN_1;
2622         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2623         /* SNB-B */
2624         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2625         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2626
2627         I915_WRITE(FDI_RX_MISC(pipe),
2628                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2629
2630         reg = FDI_RX_CTL(pipe);
2631         temp = I915_READ(reg);
2632         if (HAS_PCH_CPT(dev)) {
2633                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2634                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2635         } else {
2636                 temp &= ~FDI_LINK_TRAIN_NONE;
2637                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2638         }
2639         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2640
2641         POSTING_READ(reg);
2642         udelay(150);
2643
2644         for (i = 0; i < 4; i++) {
2645                 reg = FDI_TX_CTL(pipe);
2646                 temp = I915_READ(reg);
2647                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2648                 temp |= snb_b_fdi_train_param[i];
2649                 I915_WRITE(reg, temp);
2650
2651                 POSTING_READ(reg);
2652                 udelay(500);
2653
2654                 for (retry = 0; retry < 5; retry++) {
2655                         reg = FDI_RX_IIR(pipe);
2656                         temp = I915_READ(reg);
2657                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2658                         if (temp & FDI_RX_BIT_LOCK) {
2659                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2660                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2661                                 break;
2662                         }
2663                         udelay(50);
2664                 }
2665                 if (retry < 5)
2666                         break;
2667         }
2668         if (i == 4)
2669                 DRM_ERROR("FDI train 1 fail!\n");
2670
2671         /* Train 2 */
2672         reg = FDI_TX_CTL(pipe);
2673         temp = I915_READ(reg);
2674         temp &= ~FDI_LINK_TRAIN_NONE;
2675         temp |= FDI_LINK_TRAIN_PATTERN_2;
2676         if (IS_GEN6(dev)) {
2677                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2678                 /* SNB-B */
2679                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2680         }
2681         I915_WRITE(reg, temp);
2682
2683         reg = FDI_RX_CTL(pipe);
2684         temp = I915_READ(reg);
2685         if (HAS_PCH_CPT(dev)) {
2686                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2687                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2688         } else {
2689                 temp &= ~FDI_LINK_TRAIN_NONE;
2690                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2691         }
2692         I915_WRITE(reg, temp);
2693
2694         POSTING_READ(reg);
2695         udelay(150);
2696
2697         for (i = 0; i < 4; i++) {
2698                 reg = FDI_TX_CTL(pipe);
2699                 temp = I915_READ(reg);
2700                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2701                 temp |= snb_b_fdi_train_param[i];
2702                 I915_WRITE(reg, temp);
2703
2704                 POSTING_READ(reg);
2705                 udelay(500);
2706
2707                 for (retry = 0; retry < 5; retry++) {
2708                         reg = FDI_RX_IIR(pipe);
2709                         temp = I915_READ(reg);
2710                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2711                         if (temp & FDI_RX_SYMBOL_LOCK) {
2712                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2713                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2714                                 break;
2715                         }
2716                         udelay(50);
2717                 }
2718                 if (retry < 5)
2719                         break;
2720         }
2721         if (i == 4)
2722                 DRM_ERROR("FDI train 2 fail!\n");
2723
2724         DRM_DEBUG_KMS("FDI train done.\n");
2725 }
2726
2727 /* Manual link training for Ivy Bridge A0 parts */
2728 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2729 {
2730         struct drm_device *dev = crtc->dev;
2731         struct drm_i915_private *dev_priv = dev->dev_private;
2732         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2733         int pipe = intel_crtc->pipe;
2734         u32 reg, temp, i;
2735
2736         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2737            for train result */
2738         reg = FDI_RX_IMR(pipe);
2739         temp = I915_READ(reg);
2740         temp &= ~FDI_RX_SYMBOL_LOCK;
2741         temp &= ~FDI_RX_BIT_LOCK;
2742         I915_WRITE(reg, temp);
2743
2744         POSTING_READ(reg);
2745         udelay(150);
2746
2747         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2748                       I915_READ(FDI_RX_IIR(pipe)));
2749
2750         /* enable CPU FDI TX and PCH FDI RX */
2751         reg = FDI_TX_CTL(pipe);
2752         temp = I915_READ(reg);
2753         temp &= ~(7 << 19);
2754         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2755         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2756         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2757         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2758         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2759         temp |= FDI_COMPOSITE_SYNC;
2760         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2761
2762         I915_WRITE(FDI_RX_MISC(pipe),
2763                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2764
2765         reg = FDI_RX_CTL(pipe);
2766         temp = I915_READ(reg);
2767         temp &= ~FDI_LINK_TRAIN_AUTO;
2768         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2769         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2770         temp |= FDI_COMPOSITE_SYNC;
2771         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2772
2773         POSTING_READ(reg);
2774         udelay(150);
2775
2776         for (i = 0; i < 4; i++) {
2777                 reg = FDI_TX_CTL(pipe);
2778                 temp = I915_READ(reg);
2779                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2780                 temp |= snb_b_fdi_train_param[i];
2781                 I915_WRITE(reg, temp);
2782
2783                 POSTING_READ(reg);
2784                 udelay(500);
2785
2786                 reg = FDI_RX_IIR(pipe);
2787                 temp = I915_READ(reg);
2788                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2789
2790                 if (temp & FDI_RX_BIT_LOCK ||
2791                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2792                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2793                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2794                         break;
2795                 }
2796         }
2797         if (i == 4)
2798                 DRM_ERROR("FDI train 1 fail!\n");
2799
2800         /* Train 2 */
2801         reg = FDI_TX_CTL(pipe);
2802         temp = I915_READ(reg);
2803         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2804         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2805         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2806         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2807         I915_WRITE(reg, temp);
2808
2809         reg = FDI_RX_CTL(pipe);
2810         temp = I915_READ(reg);
2811         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2812         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2813         I915_WRITE(reg, temp);
2814
2815         POSTING_READ(reg);
2816         udelay(150);
2817
2818         for (i = 0; i < 4; i++) {
2819                 reg = FDI_TX_CTL(pipe);
2820                 temp = I915_READ(reg);
2821                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2822                 temp |= snb_b_fdi_train_param[i];
2823                 I915_WRITE(reg, temp);
2824
2825                 POSTING_READ(reg);
2826                 udelay(500);
2827
2828                 reg = FDI_RX_IIR(pipe);
2829                 temp = I915_READ(reg);
2830                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2831
2832                 if (temp & FDI_RX_SYMBOL_LOCK) {
2833                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2834                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2835                         break;
2836                 }
2837         }
2838         if (i == 4)
2839                 DRM_ERROR("FDI train 2 fail!\n");
2840
2841         DRM_DEBUG_KMS("FDI train done.\n");
2842 }
2843
2844 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2845 {
2846         struct drm_device *dev = intel_crtc->base.dev;
2847         struct drm_i915_private *dev_priv = dev->dev_private;
2848         int pipe = intel_crtc->pipe;
2849         u32 reg, temp;
2850
2851
2852         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2853         reg = FDI_RX_CTL(pipe);
2854         temp = I915_READ(reg);
2855         temp &= ~((0x7 << 19) | (0x7 << 16));
2856         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2857         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2858         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2859
2860         POSTING_READ(reg);
2861         udelay(200);
2862
2863         /* Switch from Rawclk to PCDclk */
2864         temp = I915_READ(reg);
2865         I915_WRITE(reg, temp | FDI_PCDCLK);
2866
2867         POSTING_READ(reg);
2868         udelay(200);
2869
2870         /* Enable CPU FDI TX PLL, always on for Ironlake */
2871         reg = FDI_TX_CTL(pipe);
2872         temp = I915_READ(reg);
2873         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2874                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2875
2876                 POSTING_READ(reg);
2877                 udelay(100);
2878         }
2879 }
2880
2881 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2882 {
2883         struct drm_device *dev = intel_crtc->base.dev;
2884         struct drm_i915_private *dev_priv = dev->dev_private;
2885         int pipe = intel_crtc->pipe;
2886         u32 reg, temp;
2887
2888         /* Switch from PCDclk to Rawclk */
2889         reg = FDI_RX_CTL(pipe);
2890         temp = I915_READ(reg);
2891         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2892
2893         /* Disable CPU FDI TX PLL */
2894         reg = FDI_TX_CTL(pipe);
2895         temp = I915_READ(reg);
2896         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2897
2898         POSTING_READ(reg);
2899         udelay(100);
2900
2901         reg = FDI_RX_CTL(pipe);
2902         temp = I915_READ(reg);
2903         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2904
2905         /* Wait for the clocks to turn off. */
2906         POSTING_READ(reg);
2907         udelay(100);
2908 }
2909
2910 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2911 {
2912         struct drm_device *dev = crtc->dev;
2913         struct drm_i915_private *dev_priv = dev->dev_private;
2914         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2915         int pipe = intel_crtc->pipe;
2916         u32 reg, temp;
2917
2918         /* disable CPU FDI tx and PCH FDI rx */
2919         reg = FDI_TX_CTL(pipe);
2920         temp = I915_READ(reg);
2921         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2922         POSTING_READ(reg);
2923
2924         reg = FDI_RX_CTL(pipe);
2925         temp = I915_READ(reg);
2926         temp &= ~(0x7 << 16);
2927         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2928         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2929
2930         POSTING_READ(reg);
2931         udelay(100);
2932
2933         /* Ironlake workaround, disable clock pointer after downing FDI */
2934         if (HAS_PCH_IBX(dev)) {
2935                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2936         }
2937
2938         /* still set train pattern 1 */
2939         reg = FDI_TX_CTL(pipe);
2940         temp = I915_READ(reg);
2941         temp &= ~FDI_LINK_TRAIN_NONE;
2942         temp |= FDI_LINK_TRAIN_PATTERN_1;
2943         I915_WRITE(reg, temp);
2944
2945         reg = FDI_RX_CTL(pipe);
2946         temp = I915_READ(reg);
2947         if (HAS_PCH_CPT(dev)) {
2948                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2949                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2950         } else {
2951                 temp &= ~FDI_LINK_TRAIN_NONE;
2952                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2953         }
2954         /* BPC in FDI rx is consistent with that in PIPECONF */
2955         temp &= ~(0x07 << 16);
2956         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2957         I915_WRITE(reg, temp);
2958
2959         POSTING_READ(reg);
2960         udelay(100);
2961 }
2962
2963 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2964 {
2965         struct drm_device *dev = crtc->dev;
2966         struct drm_i915_private *dev_priv = dev->dev_private;
2967         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2968         unsigned long flags;
2969         bool pending;
2970
2971         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2972             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2973                 return false;
2974
2975         spin_lock_irqsave(&dev->event_lock, flags);
2976         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2977         spin_unlock_irqrestore(&dev->event_lock, flags);
2978
2979         return pending;
2980 }
2981
2982 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2983 {
2984         struct drm_device *dev = crtc->dev;
2985         struct drm_i915_private *dev_priv = dev->dev_private;
2986
2987         if (crtc->fb == NULL)
2988                 return;
2989
2990         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2991
2992         wait_event(dev_priv->pending_flip_queue,
2993                    !intel_crtc_has_pending_flip(crtc));
2994
2995         mutex_lock(&dev->struct_mutex);
2996         intel_finish_fb(crtc->fb);
2997         mutex_unlock(&dev->struct_mutex);
2998 }
2999
3000 /* Program iCLKIP clock to the desired frequency */
3001 static void lpt_program_iclkip(struct drm_crtc *crtc)
3002 {
3003         struct drm_device *dev = crtc->dev;
3004         struct drm_i915_private *dev_priv = dev->dev_private;
3005         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3006         u32 temp;
3007
3008         mutex_lock(&dev_priv->dpio_lock);
3009
3010         /* It is necessary to ungate the pixclk gate prior to programming
3011          * the divisors, and gate it back when it is done.
3012          */
3013         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3014
3015         /* Disable SSCCTL */
3016         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3017                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3018                                 SBI_SSCCTL_DISABLE,
3019                         SBI_ICLK);
3020
3021         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3022         if (crtc->mode.clock == 20000) {
3023                 auxdiv = 1;
3024                 divsel = 0x41;
3025                 phaseinc = 0x20;
3026         } else {
3027                 /* The iCLK virtual clock root frequency is in MHz,
3028                  * but the crtc->mode.clock in in KHz. To get the divisors,
3029                  * it is necessary to divide one by another, so we
3030                  * convert the virtual clock precision to KHz here for higher
3031                  * precision.
3032                  */
3033                 u32 iclk_virtual_root_freq = 172800 * 1000;
3034                 u32 iclk_pi_range = 64;
3035                 u32 desired_divisor, msb_divisor_value, pi_value;
3036
3037                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3038                 msb_divisor_value = desired_divisor / iclk_pi_range;
3039                 pi_value = desired_divisor % iclk_pi_range;
3040
3041                 auxdiv = 0;
3042                 divsel = msb_divisor_value - 2;
3043                 phaseinc = pi_value;
3044         }
3045
3046         /* This should not happen with any sane values */
3047         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3048                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3049         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3050                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3051
3052         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3053                         crtc->mode.clock,
3054                         auxdiv,
3055                         divsel,
3056                         phasedir,
3057                         phaseinc);
3058
3059         /* Program SSCDIVINTPHASE6 */
3060         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3061         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3062         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3063         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3064         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3065         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3066         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3067         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3068
3069         /* Program SSCAUXDIV */
3070         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3071         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3072         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3073         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3074
3075         /* Enable modulator and associated divider */
3076         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3077         temp &= ~SBI_SSCCTL_DISABLE;
3078         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3079
3080         /* Wait for initialization time */
3081         udelay(24);
3082
3083         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3084
3085         mutex_unlock(&dev_priv->dpio_lock);
3086 }
3087
3088 /*
3089  * Enable PCH resources required for PCH ports:
3090  *   - PCH PLLs
3091  *   - FDI training & RX/TX
3092  *   - update transcoder timings
3093  *   - DP transcoding bits
3094  *   - transcoder
3095  */
3096 static void ironlake_pch_enable(struct drm_crtc *crtc)
3097 {
3098         struct drm_device *dev = crtc->dev;
3099         struct drm_i915_private *dev_priv = dev->dev_private;
3100         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3101         int pipe = intel_crtc->pipe;
3102         u32 reg, temp;
3103
3104         assert_transcoder_disabled(dev_priv, pipe);
3105
3106         /* Write the TU size bits before fdi link training, so that error
3107          * detection works. */
3108         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3109                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3110
3111         /* For PCH output, training FDI link */
3112         dev_priv->display.fdi_link_train(crtc);
3113
3114         /* XXX: pch pll's can be enabled any time before we enable the PCH
3115          * transcoder, and we actually should do this to not upset any PCH
3116          * transcoder that already use the clock when we share it.
3117          *
3118          * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3119          * unconditionally resets the pll - we need that to have the right LVDS
3120          * enable sequence. */
3121         ironlake_enable_pch_pll(intel_crtc);
3122
3123         if (HAS_PCH_CPT(dev)) {
3124                 u32 sel;
3125
3126                 temp = I915_READ(PCH_DPLL_SEL);
3127                 switch (pipe) {
3128                 default:
3129                 case 0:
3130                         temp |= TRANSA_DPLL_ENABLE;
3131                         sel = TRANSA_DPLLB_SEL;
3132                         break;
3133                 case 1:
3134                         temp |= TRANSB_DPLL_ENABLE;
3135                         sel = TRANSB_DPLLB_SEL;
3136                         break;
3137                 case 2:
3138                         temp |= TRANSC_DPLL_ENABLE;
3139                         sel = TRANSC_DPLLB_SEL;
3140                         break;
3141                 }
3142                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3143                         temp |= sel;
3144                 else
3145                         temp &= ~sel;
3146                 I915_WRITE(PCH_DPLL_SEL, temp);
3147         }
3148
3149         /* set transcoder timing, panel must allow it */
3150         assert_panel_unlocked(dev_priv, pipe);
3151         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3152         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3153         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3154
3155         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3156         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3157         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3158         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3159
3160         intel_fdi_normal_train(crtc);
3161
3162         /* For PCH DP, enable TRANS_DP_CTL */
3163         if (HAS_PCH_CPT(dev) &&
3164             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3165              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3166                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3167                 reg = TRANS_DP_CTL(pipe);
3168                 temp = I915_READ(reg);
3169                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3170                           TRANS_DP_SYNC_MASK |
3171                           TRANS_DP_BPC_MASK);
3172                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3173                          TRANS_DP_ENH_FRAMING);
3174                 temp |= bpc << 9; /* same format but at 11:9 */
3175
3176                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3177                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3178                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3179                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3180
3181                 switch (intel_trans_dp_port_sel(crtc)) {
3182                 case PCH_DP_B:
3183                         temp |= TRANS_DP_PORT_SEL_B;
3184                         break;
3185                 case PCH_DP_C:
3186                         temp |= TRANS_DP_PORT_SEL_C;
3187                         break;
3188                 case PCH_DP_D:
3189                         temp |= TRANS_DP_PORT_SEL_D;
3190                         break;
3191                 default:
3192                         BUG();
3193                 }
3194
3195                 I915_WRITE(reg, temp);
3196         }
3197
3198         ironlake_enable_pch_transcoder(dev_priv, pipe);
3199 }
3200
3201 static void lpt_pch_enable(struct drm_crtc *crtc)
3202 {
3203         struct drm_device *dev = crtc->dev;
3204         struct drm_i915_private *dev_priv = dev->dev_private;
3205         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3206         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3207
3208         assert_transcoder_disabled(dev_priv, TRANSCODER_A);
3209
3210         lpt_program_iclkip(crtc);
3211
3212         /* Set transcoder timing. */
3213         I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3214         I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3215         I915_WRITE(_TRANS_HSYNC_A,  I915_READ(HSYNC(cpu_transcoder)));
3216
3217         I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3218         I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3219         I915_WRITE(_TRANS_VSYNC_A,  I915_READ(VSYNC(cpu_transcoder)));
3220         I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
3221
3222         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3223 }
3224
3225 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3226 {
3227         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3228
3229         if (pll == NULL)
3230                 return;
3231
3232         if (pll->refcount == 0) {
3233                 WARN(1, "bad PCH PLL refcount\n");
3234                 return;
3235         }
3236
3237         --pll->refcount;
3238         intel_crtc->pch_pll = NULL;
3239 }
3240
3241 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3242 {
3243         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3244         struct intel_pch_pll *pll;
3245         int i;
3246
3247         pll = intel_crtc->pch_pll;
3248         if (pll) {
3249                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3250                               intel_crtc->base.base.id, pll->pll_reg);
3251                 goto prepare;
3252         }
3253
3254         if (HAS_PCH_IBX(dev_priv->dev)) {
3255                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3256                 i = intel_crtc->pipe;
3257                 pll = &dev_priv->pch_plls[i];
3258
3259                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3260                               intel_crtc->base.base.id, pll->pll_reg);
3261
3262                 goto found;
3263         }
3264
3265         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3266                 pll = &dev_priv->pch_plls[i];
3267
3268                 /* Only want to check enabled timings first */
3269                 if (pll->refcount == 0)
3270                         continue;
3271
3272                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3273                     fp == I915_READ(pll->fp0_reg)) {
3274                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3275                                       intel_crtc->base.base.id,
3276                                       pll->pll_reg, pll->refcount, pll->active);
3277
3278                         goto found;
3279                 }
3280         }
3281
3282         /* Ok no matching timings, maybe there's a free one? */
3283         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3284                 pll = &dev_priv->pch_plls[i];
3285                 if (pll->refcount == 0) {
3286                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3287                                       intel_crtc->base.base.id, pll->pll_reg);
3288                         goto found;
3289                 }
3290         }
3291
3292         return NULL;
3293
3294 found:
3295         intel_crtc->pch_pll = pll;
3296         pll->refcount++;
3297         DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3298 prepare: /* separate function? */
3299         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3300
3301         /* Wait for the clocks to stabilize before rewriting the regs */
3302         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3303         POSTING_READ(pll->pll_reg);
3304         udelay(150);
3305
3306         I915_WRITE(pll->fp0_reg, fp);
3307         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3308         pll->on = false;
3309         return pll;
3310 }
3311
3312 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3313 {
3314         struct drm_i915_private *dev_priv = dev->dev_private;
3315         int dslreg = PIPEDSL(pipe);
3316         u32 temp;
3317
3318         temp = I915_READ(dslreg);
3319         udelay(500);
3320         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3321                 if (wait_for(I915_READ(dslreg) != temp, 5))
3322                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3323         }
3324 }
3325
3326 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3327 {
3328         struct drm_device *dev = crtc->dev;
3329         struct drm_i915_private *dev_priv = dev->dev_private;
3330         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3331         struct intel_encoder *encoder;
3332         int pipe = intel_crtc->pipe;
3333         int plane = intel_crtc->plane;
3334         u32 temp;
3335
3336         WARN_ON(!crtc->enabled);
3337
3338         if (intel_crtc->active)
3339                 return;
3340
3341         intel_crtc->active = true;
3342         intel_update_watermarks(dev);
3343
3344         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3345                 temp = I915_READ(PCH_LVDS);
3346                 if ((temp & LVDS_PORT_EN) == 0)
3347                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3348         }
3349
3350
3351         if (intel_crtc->config.has_pch_encoder) {
3352                 /* Note: FDI PLL enabling _must_ be done before we enable the
3353                  * cpu pipes, hence this is separate from all the other fdi/pch
3354                  * enabling. */
3355                 ironlake_fdi_pll_enable(intel_crtc);
3356         } else {
3357                 assert_fdi_tx_disabled(dev_priv, pipe);
3358                 assert_fdi_rx_disabled(dev_priv, pipe);
3359         }
3360
3361         for_each_encoder_on_crtc(dev, crtc, encoder)
3362                 if (encoder->pre_enable)
3363                         encoder->pre_enable(encoder);
3364
3365         /* Enable panel fitting for LVDS */
3366         if (dev_priv->pch_pf_size &&
3367             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3368              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3369                 /* Force use of hard-coded filter coefficients
3370                  * as some pre-programmed values are broken,
3371                  * e.g. x201.
3372                  */
3373                 if (IS_IVYBRIDGE(dev))
3374                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3375                                                  PF_PIPE_SEL_IVB(pipe));
3376                 else
3377                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3378                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3379                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3380         }
3381
3382         /*
3383          * On ILK+ LUT must be loaded before the pipe is running but with
3384          * clocks enabled
3385          */
3386         intel_crtc_load_lut(crtc);
3387
3388         intel_enable_pipe(dev_priv, pipe,
3389                           intel_crtc->config.has_pch_encoder);
3390         intel_enable_plane(dev_priv, plane, pipe);
3391
3392         if (intel_crtc->config.has_pch_encoder)
3393                 ironlake_pch_enable(crtc);
3394
3395         mutex_lock(&dev->struct_mutex);
3396         intel_update_fbc(dev);
3397         mutex_unlock(&dev->struct_mutex);
3398
3399         intel_crtc_update_cursor(crtc, true);
3400
3401         for_each_encoder_on_crtc(dev, crtc, encoder)
3402                 encoder->enable(encoder);
3403
3404         if (HAS_PCH_CPT(dev))
3405                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3406
3407         /*
3408          * There seems to be a race in PCH platform hw (at least on some
3409          * outputs) where an enabled pipe still completes any pageflip right
3410          * away (as if the pipe is off) instead of waiting for vblank. As soon
3411          * as the first vblank happend, everything works as expected. Hence just
3412          * wait for one vblank before returning to avoid strange things
3413          * happening.
3414          */
3415         intel_wait_for_vblank(dev, intel_crtc->pipe);
3416 }
3417
3418 static void haswell_crtc_enable(struct drm_crtc *crtc)
3419 {
3420         struct drm_device *dev = crtc->dev;
3421         struct drm_i915_private *dev_priv = dev->dev_private;
3422         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3423         struct intel_encoder *encoder;
3424         int pipe = intel_crtc->pipe;
3425         int plane = intel_crtc->plane;
3426
3427         WARN_ON(!crtc->enabled);
3428
3429         if (intel_crtc->active)
3430                 return;
3431
3432         intel_crtc->active = true;
3433         intel_update_watermarks(dev);
3434
3435         if (intel_crtc->config.has_pch_encoder)
3436                 dev_priv->display.fdi_link_train(crtc);
3437
3438         for_each_encoder_on_crtc(dev, crtc, encoder)
3439                 if (encoder->pre_enable)
3440                         encoder->pre_enable(encoder);
3441
3442         intel_ddi_enable_pipe_clock(intel_crtc);
3443
3444         /* Enable panel fitting for eDP */
3445         if (dev_priv->pch_pf_size &&
3446             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3447                 /* Force use of hard-coded filter coefficients
3448                  * as some pre-programmed values are broken,
3449                  * e.g. x201.
3450                  */
3451                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3452                                          PF_PIPE_SEL_IVB(pipe));
3453                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3454                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3455         }
3456
3457         /*
3458          * On ILK+ LUT must be loaded before the pipe is running but with
3459          * clocks enabled
3460          */
3461         intel_crtc_load_lut(crtc);
3462
3463         intel_ddi_set_pipe_settings(crtc);
3464         intel_ddi_enable_transcoder_func(crtc);
3465
3466         intel_enable_pipe(dev_priv, pipe,
3467                           intel_crtc->config.has_pch_encoder);
3468         intel_enable_plane(dev_priv, plane, pipe);
3469
3470         if (intel_crtc->config.has_pch_encoder)
3471                 lpt_pch_enable(crtc);
3472
3473         mutex_lock(&dev->struct_mutex);
3474         intel_update_fbc(dev);
3475         mutex_unlock(&dev->struct_mutex);
3476
3477         intel_crtc_update_cursor(crtc, true);
3478
3479         for_each_encoder_on_crtc(dev, crtc, encoder)
3480                 encoder->enable(encoder);
3481
3482         /*
3483          * There seems to be a race in PCH platform hw (at least on some
3484          * outputs) where an enabled pipe still completes any pageflip right
3485          * away (as if the pipe is off) instead of waiting for vblank. As soon
3486          * as the first vblank happend, everything works as expected. Hence just
3487          * wait for one vblank before returning to avoid strange things
3488          * happening.
3489          */
3490         intel_wait_for_vblank(dev, intel_crtc->pipe);
3491 }
3492
3493 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3494 {
3495         struct drm_device *dev = crtc->dev;
3496         struct drm_i915_private *dev_priv = dev->dev_private;
3497         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3498         struct intel_encoder *encoder;
3499         int pipe = intel_crtc->pipe;
3500         int plane = intel_crtc->plane;
3501         u32 reg, temp;
3502
3503
3504         if (!intel_crtc->active)
3505                 return;
3506
3507         for_each_encoder_on_crtc(dev, crtc, encoder)
3508                 encoder->disable(encoder);
3509
3510         intel_crtc_wait_for_pending_flips(crtc);
3511         drm_vblank_off(dev, pipe);
3512         intel_crtc_update_cursor(crtc, false);
3513
3514         intel_disable_plane(dev_priv, plane, pipe);
3515
3516         if (dev_priv->cfb_plane == plane)
3517                 intel_disable_fbc(dev);
3518
3519         intel_disable_pipe(dev_priv, pipe);
3520
3521         /* Disable PF */
3522         I915_WRITE(PF_CTL(pipe), 0);
3523         I915_WRITE(PF_WIN_SZ(pipe), 0);
3524
3525         for_each_encoder_on_crtc(dev, crtc, encoder)
3526                 if (encoder->post_disable)
3527                         encoder->post_disable(encoder);
3528
3529         ironlake_fdi_disable(crtc);
3530
3531         ironlake_disable_pch_transcoder(dev_priv, pipe);
3532
3533         if (HAS_PCH_CPT(dev)) {
3534                 /* disable TRANS_DP_CTL */
3535                 reg = TRANS_DP_CTL(pipe);
3536                 temp = I915_READ(reg);
3537                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3538                 temp |= TRANS_DP_PORT_SEL_NONE;
3539                 I915_WRITE(reg, temp);
3540
3541                 /* disable DPLL_SEL */
3542                 temp = I915_READ(PCH_DPLL_SEL);
3543                 switch (pipe) {
3544                 case 0:
3545                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3546                         break;
3547                 case 1:
3548                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3549                         break;
3550                 case 2:
3551                         /* C shares PLL A or B */
3552                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3553                         break;
3554                 default:
3555                         BUG(); /* wtf */
3556                 }
3557                 I915_WRITE(PCH_DPLL_SEL, temp);
3558         }
3559
3560         /* disable PCH DPLL */
3561         intel_disable_pch_pll(intel_crtc);
3562
3563         ironlake_fdi_pll_disable(intel_crtc);
3564
3565         intel_crtc->active = false;
3566         intel_update_watermarks(dev);
3567
3568         mutex_lock(&dev->struct_mutex);
3569         intel_update_fbc(dev);
3570         mutex_unlock(&dev->struct_mutex);
3571 }
3572
3573 static void haswell_crtc_disable(struct drm_crtc *crtc)
3574 {
3575         struct drm_device *dev = crtc->dev;
3576         struct drm_i915_private *dev_priv = dev->dev_private;
3577         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3578         struct intel_encoder *encoder;
3579         int pipe = intel_crtc->pipe;
3580         int plane = intel_crtc->plane;
3581         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3582
3583         if (!intel_crtc->active)
3584                 return;
3585
3586         for_each_encoder_on_crtc(dev, crtc, encoder)
3587                 encoder->disable(encoder);
3588
3589         intel_crtc_wait_for_pending_flips(crtc);
3590         drm_vblank_off(dev, pipe);
3591         intel_crtc_update_cursor(crtc, false);
3592
3593         intel_disable_plane(dev_priv, plane, pipe);
3594
3595         if (dev_priv->cfb_plane == plane)
3596                 intel_disable_fbc(dev);
3597
3598         intel_disable_pipe(dev_priv, pipe);
3599
3600         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3601
3602         /* XXX: Once we have proper panel fitter state tracking implemented with
3603          * hardware state read/check support we should switch to only disable
3604          * the panel fitter when we know it's used. */
3605         if (intel_using_power_well(dev)) {
3606                 I915_WRITE(PF_CTL(pipe), 0);
3607                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3608         }
3609
3610         intel_ddi_disable_pipe_clock(intel_crtc);
3611
3612         for_each_encoder_on_crtc(dev, crtc, encoder)
3613                 if (encoder->post_disable)
3614                         encoder->post_disable(encoder);
3615
3616         if (intel_crtc->config.has_pch_encoder) {
3617                 lpt_disable_pch_transcoder(dev_priv);
3618                 intel_ddi_fdi_disable(crtc);
3619         }
3620
3621         intel_crtc->active = false;
3622         intel_update_watermarks(dev);
3623
3624         mutex_lock(&dev->struct_mutex);
3625         intel_update_fbc(dev);
3626         mutex_unlock(&dev->struct_mutex);
3627 }
3628
3629 static void ironlake_crtc_off(struct drm_crtc *crtc)
3630 {
3631         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3632         intel_put_pch_pll(intel_crtc);
3633 }
3634
3635 static void haswell_crtc_off(struct drm_crtc *crtc)
3636 {
3637         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3638
3639         /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3640          * start using it. */
3641         intel_crtc->cpu_transcoder = (enum transcoder) intel_crtc->pipe;
3642
3643         intel_ddi_put_crtc_pll(crtc);
3644 }
3645
3646 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3647 {
3648         if (!enable && intel_crtc->overlay) {
3649                 struct drm_device *dev = intel_crtc->base.dev;
3650                 struct drm_i915_private *dev_priv = dev->dev_private;
3651
3652                 mutex_lock(&dev->struct_mutex);
3653                 dev_priv->mm.interruptible = false;
3654                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3655                 dev_priv->mm.interruptible = true;
3656                 mutex_unlock(&dev->struct_mutex);
3657         }
3658
3659         /* Let userspace switch the overlay on again. In most cases userspace
3660          * has to recompute where to put it anyway.
3661          */
3662 }
3663
3664 /**
3665  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3666  * cursor plane briefly if not already running after enabling the display
3667  * plane.
3668  * This workaround avoids occasional blank screens when self refresh is
3669  * enabled.
3670  */
3671 static void
3672 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3673 {
3674         u32 cntl = I915_READ(CURCNTR(pipe));
3675
3676         if ((cntl & CURSOR_MODE) == 0) {
3677                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3678
3679                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3680                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3681                 intel_wait_for_vblank(dev_priv->dev, pipe);
3682                 I915_WRITE(CURCNTR(pipe), cntl);
3683                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3684                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3685         }
3686 }
3687
3688 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3689 {
3690         struct drm_device *dev = crtc->dev;
3691         struct drm_i915_private *dev_priv = dev->dev_private;
3692         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3693         struct intel_encoder *encoder;
3694         int pipe = intel_crtc->pipe;
3695         int plane = intel_crtc->plane;
3696
3697         WARN_ON(!crtc->enabled);
3698
3699         if (intel_crtc->active)
3700                 return;
3701
3702         intel_crtc->active = true;
3703         intel_update_watermarks(dev);
3704
3705         intel_enable_pll(dev_priv, pipe);
3706
3707         for_each_encoder_on_crtc(dev, crtc, encoder)
3708                 if (encoder->pre_enable)
3709                         encoder->pre_enable(encoder);
3710
3711         intel_enable_pipe(dev_priv, pipe, false);
3712         intel_enable_plane(dev_priv, plane, pipe);
3713         if (IS_G4X(dev))
3714                 g4x_fixup_plane(dev_priv, pipe);
3715
3716         intel_crtc_load_lut(crtc);
3717         intel_update_fbc(dev);
3718
3719         /* Give the overlay scaler a chance to enable if it's on this pipe */
3720         intel_crtc_dpms_overlay(intel_crtc, true);
3721         intel_crtc_update_cursor(crtc, true);
3722
3723         for_each_encoder_on_crtc(dev, crtc, encoder)
3724                 encoder->enable(encoder);
3725 }
3726
3727 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3728 {
3729         struct drm_device *dev = crtc->dev;
3730         struct drm_i915_private *dev_priv = dev->dev_private;
3731         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3732         struct intel_encoder *encoder;
3733         int pipe = intel_crtc->pipe;
3734         int plane = intel_crtc->plane;
3735         u32 pctl;
3736
3737
3738         if (!intel_crtc->active)
3739                 return;
3740
3741         for_each_encoder_on_crtc(dev, crtc, encoder)
3742                 encoder->disable(encoder);
3743
3744         /* Give the overlay scaler a chance to disable if it's on this pipe */
3745         intel_crtc_wait_for_pending_flips(crtc);
3746         drm_vblank_off(dev, pipe);
3747         intel_crtc_dpms_overlay(intel_crtc, false);
3748         intel_crtc_update_cursor(crtc, false);
3749
3750         if (dev_priv->cfb_plane == plane)
3751                 intel_disable_fbc(dev);
3752
3753         intel_disable_plane(dev_priv, plane, pipe);
3754         intel_disable_pipe(dev_priv, pipe);
3755
3756         /* Disable pannel fitter if it is on this pipe. */
3757         pctl = I915_READ(PFIT_CONTROL);
3758         if ((pctl & PFIT_ENABLE) &&
3759             ((pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT) == pipe)
3760                 I915_WRITE(PFIT_CONTROL, 0);
3761
3762         intel_disable_pll(dev_priv, pipe);
3763
3764         intel_crtc->active = false;
3765         intel_update_fbc(dev);
3766         intel_update_watermarks(dev);
3767 }
3768
3769 static void i9xx_crtc_off(struct drm_crtc *crtc)
3770 {
3771 }
3772
3773 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3774                                     bool enabled)
3775 {
3776         struct drm_device *dev = crtc->dev;
3777         struct drm_i915_master_private *master_priv;
3778         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3779         int pipe = intel_crtc->pipe;
3780
3781         if (!dev->primary->master)
3782                 return;
3783
3784         master_priv = dev->primary->master->driver_priv;
3785         if (!master_priv->sarea_priv)
3786                 return;
3787
3788         switch (pipe) {
3789         case 0:
3790                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3791                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3792                 break;
3793         case 1:
3794                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3795                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3796                 break;
3797         default:
3798                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3799                 break;
3800         }
3801 }
3802
3803 /**
3804  * Sets the power management mode of the pipe and plane.
3805  */
3806 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3807 {
3808         struct drm_device *dev = crtc->dev;
3809         struct drm_i915_private *dev_priv = dev->dev_private;
3810         struct intel_encoder *intel_encoder;
3811         bool enable = false;
3812
3813         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3814                 enable |= intel_encoder->connectors_active;
3815
3816         if (enable)
3817                 dev_priv->display.crtc_enable(crtc);
3818         else
3819                 dev_priv->display.crtc_disable(crtc);
3820
3821         intel_crtc_update_sarea(crtc, enable);
3822 }
3823
3824 static void intel_crtc_disable(struct drm_crtc *crtc)
3825 {
3826         struct drm_device *dev = crtc->dev;
3827         struct drm_connector *connector;
3828         struct drm_i915_private *dev_priv = dev->dev_private;
3829         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3830
3831         /* crtc should still be enabled when we disable it. */
3832         WARN_ON(!crtc->enabled);
3833
3834         intel_crtc->eld_vld = false;
3835         dev_priv->display.crtc_disable(crtc);
3836         intel_crtc_update_sarea(crtc, false);
3837         dev_priv->display.off(crtc);
3838
3839         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3840         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3841
3842         if (crtc->fb) {
3843                 mutex_lock(&dev->struct_mutex);
3844                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3845                 mutex_unlock(&dev->struct_mutex);
3846                 crtc->fb = NULL;
3847         }
3848
3849         /* Update computed state. */
3850         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3851                 if (!connector->encoder || !connector->encoder->crtc)
3852                         continue;
3853
3854                 if (connector->encoder->crtc != crtc)
3855                         continue;
3856
3857                 connector->dpms = DRM_MODE_DPMS_OFF;
3858                 to_intel_encoder(connector->encoder)->connectors_active = false;
3859         }
3860 }
3861
3862 void intel_modeset_disable(struct drm_device *dev)
3863 {
3864         struct drm_crtc *crtc;
3865
3866         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3867                 if (crtc->enabled)
3868                         intel_crtc_disable(crtc);
3869         }
3870 }
3871
3872 void intel_encoder_destroy(struct drm_encoder *encoder)
3873 {
3874         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3875
3876         drm_encoder_cleanup(encoder);
3877         kfree(intel_encoder);
3878 }
3879
3880 /* Simple dpms helper for encodres with just one connector, no cloning and only
3881  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3882  * state of the entire output pipe. */
3883 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3884 {
3885         if (mode == DRM_MODE_DPMS_ON) {
3886                 encoder->connectors_active = true;
3887
3888                 intel_crtc_update_dpms(encoder->base.crtc);
3889         } else {
3890                 encoder->connectors_active = false;
3891
3892                 intel_crtc_update_dpms(encoder->base.crtc);
3893         }
3894 }
3895
3896 /* Cross check the actual hw state with our own modeset state tracking (and it's
3897  * internal consistency). */
3898 static void intel_connector_check_state(struct intel_connector *connector)
3899 {
3900         if (connector->get_hw_state(connector)) {
3901                 struct intel_encoder *encoder = connector->encoder;
3902                 struct drm_crtc *crtc;
3903                 bool encoder_enabled;
3904                 enum pipe pipe;
3905
3906                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3907                               connector->base.base.id,
3908                               drm_get_connector_name(&connector->base));
3909
3910                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3911                      "wrong connector dpms state\n");
3912                 WARN(connector->base.encoder != &encoder->base,
3913                      "active connector not linked to encoder\n");
3914                 WARN(!encoder->connectors_active,
3915                      "encoder->connectors_active not set\n");
3916
3917                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3918                 WARN(!encoder_enabled, "encoder not enabled\n");
3919                 if (WARN_ON(!encoder->base.crtc))
3920                         return;
3921
3922                 crtc = encoder->base.crtc;
3923
3924                 WARN(!crtc->enabled, "crtc not enabled\n");
3925                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3926                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3927                      "encoder active on the wrong pipe\n");
3928         }
3929 }
3930
3931 /* Even simpler default implementation, if there's really no special case to
3932  * consider. */
3933 void intel_connector_dpms(struct drm_connector *connector, int mode)
3934 {
3935         struct intel_encoder *encoder = intel_attached_encoder(connector);
3936
3937         /* All the simple cases only support two dpms states. */
3938         if (mode != DRM_MODE_DPMS_ON)
3939                 mode = DRM_MODE_DPMS_OFF;
3940
3941         if (mode == connector->dpms)
3942                 return;
3943
3944         connector->dpms = mode;
3945
3946         /* Only need to change hw state when actually enabled */
3947         if (encoder->base.crtc)
3948                 intel_encoder_dpms(encoder, mode);
3949         else
3950                 WARN_ON(encoder->connectors_active != false);
3951
3952         intel_modeset_check_state(connector->dev);
3953 }
3954
3955 /* Simple connector->get_hw_state implementation for encoders that support only
3956  * one connector and no cloning and hence the encoder state determines the state
3957  * of the connector. */
3958 bool intel_connector_get_hw_state(struct intel_connector *connector)
3959 {
3960         enum pipe pipe = 0;
3961         struct intel_encoder *encoder = connector->encoder;
3962
3963         return encoder->get_hw_state(encoder, &pipe);
3964 }
3965
3966 static bool intel_crtc_compute_config(struct drm_crtc *crtc,
3967                                       struct intel_crtc_config *pipe_config)
3968 {
3969         struct drm_device *dev = crtc->dev;
3970         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
3971
3972         if (HAS_PCH_SPLIT(dev)) {
3973                 /* FDI link clock is fixed at 2.7G */
3974                 if (pipe_config->requested_mode.clock * 3
3975                     > IRONLAKE_FDI_FREQ * 4)
3976                         return false;
3977         }
3978
3979         /* All interlaced capable intel hw wants timings in frames. Note though
3980          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3981          * timings, so we need to be careful not to clobber these.*/
3982         if (!pipe_config->timings_set)
3983                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3984
3985         /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3986          * with a hsync front porch of 0.
3987          */
3988         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3989                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3990                 return false;
3991
3992         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10) {
3993                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
3994         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8) {
3995                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
3996                  * for lvds. */
3997                 pipe_config->pipe_bpp = 8*3;
3998         }
3999
4000         return true;
4001 }
4002
4003 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4004 {
4005         return 400000; /* FIXME */
4006 }
4007
4008 static int i945_get_display_clock_speed(struct drm_device *dev)
4009 {
4010         return 400000;
4011 }
4012
4013 static int i915_get_display_clock_speed(struct drm_device *dev)
4014 {
4015         return 333000;
4016 }
4017
4018 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4019 {
4020         return 200000;
4021 }
4022
4023 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4024 {
4025         u16 gcfgc = 0;
4026
4027         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4028
4029         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4030                 return 133000;
4031         else {
4032                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4033                 case GC_DISPLAY_CLOCK_333_MHZ:
4034                         return 333000;
4035                 default:
4036                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4037                         return 190000;
4038                 }
4039         }
4040 }
4041
4042 static int i865_get_display_clock_speed(struct drm_device *dev)
4043 {
4044         return 266000;
4045 }
4046
4047 static int i855_get_display_clock_speed(struct drm_device *dev)
4048 {
4049         u16 hpllcc = 0;
4050         /* Assume that the hardware is in the high speed state.  This
4051          * should be the default.
4052          */
4053         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4054         case GC_CLOCK_133_200:
4055         case GC_CLOCK_100_200:
4056                 return 200000;
4057         case GC_CLOCK_166_250:
4058                 return 250000;
4059         case GC_CLOCK_100_133:
4060                 return 133000;
4061         }
4062
4063         /* Shouldn't happen */
4064         return 0;
4065 }
4066
4067 static int i830_get_display_clock_speed(struct drm_device *dev)
4068 {
4069         return 133000;
4070 }
4071
4072 static void
4073 intel_reduce_ratio(uint32_t *num, uint32_t *den)
4074 {
4075         while (*num > 0xffffff || *den > 0xffffff) {
4076                 *num >>= 1;
4077                 *den >>= 1;
4078         }
4079 }
4080
4081 void
4082 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4083                        int pixel_clock, int link_clock,
4084                        struct intel_link_m_n *m_n)
4085 {
4086         m_n->tu = 64;
4087         m_n->gmch_m = bits_per_pixel * pixel_clock;
4088         m_n->gmch_n = link_clock * nlanes * 8;
4089         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4090         m_n->link_m = pixel_clock;
4091         m_n->link_n = link_clock;
4092         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
4093 }
4094
4095 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4096 {
4097         if (i915_panel_use_ssc >= 0)
4098                 return i915_panel_use_ssc != 0;
4099         return dev_priv->lvds_use_ssc
4100                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4101 }
4102
4103 static int vlv_get_refclk(struct drm_crtc *crtc)
4104 {
4105         struct drm_device *dev = crtc->dev;
4106         struct drm_i915_private *dev_priv = dev->dev_private;
4107         int refclk = 27000; /* for DP & HDMI */
4108
4109         return 100000; /* only one validated so far */
4110
4111         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4112                 refclk = 96000;
4113         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4114                 if (intel_panel_use_ssc(dev_priv))
4115                         refclk = 100000;
4116                 else
4117                         refclk = 96000;
4118         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4119                 refclk = 100000;
4120         }
4121
4122         return refclk;
4123 }
4124
4125 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4126 {
4127         struct drm_device *dev = crtc->dev;
4128         struct drm_i915_private *dev_priv = dev->dev_private;
4129         int refclk;
4130
4131         if (IS_VALLEYVIEW(dev)) {
4132                 refclk = vlv_get_refclk(crtc);
4133         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4134             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4135                 refclk = dev_priv->lvds_ssc_freq * 1000;
4136                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4137                               refclk / 1000);
4138         } else if (!IS_GEN2(dev)) {
4139                 refclk = 96000;
4140         } else {
4141                 refclk = 48000;
4142         }
4143
4144         return refclk;
4145 }
4146
4147 static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc *crtc)
4148 {
4149         unsigned dotclock = crtc->config.adjusted_mode.clock;
4150         struct dpll *clock = &crtc->config.dpll;
4151
4152         /* SDVO TV has fixed PLL values depend on its clock range,
4153            this mirrors vbios setting. */
4154         if (dotclock >= 100000 && dotclock < 140500) {
4155                 clock->p1 = 2;
4156                 clock->p2 = 10;
4157                 clock->n = 3;
4158                 clock->m1 = 16;
4159                 clock->m2 = 8;
4160         } else if (dotclock >= 140500 && dotclock <= 200000) {
4161                 clock->p1 = 1;
4162                 clock->p2 = 10;
4163                 clock->n = 6;
4164                 clock->m1 = 12;
4165                 clock->m2 = 8;
4166         }
4167
4168         crtc->config.clock_set = true;
4169 }
4170
4171 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4172                                      intel_clock_t *reduced_clock)
4173 {
4174         struct drm_device *dev = crtc->base.dev;
4175         struct drm_i915_private *dev_priv = dev->dev_private;
4176         int pipe = crtc->pipe;
4177         u32 fp, fp2 = 0;
4178         struct dpll *clock = &crtc->config.dpll;
4179
4180         if (IS_PINEVIEW(dev)) {
4181                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4182                 if (reduced_clock)
4183                         fp2 = (1 << reduced_clock->n) << 16 |
4184                                 reduced_clock->m1 << 8 | reduced_clock->m2;
4185         } else {
4186                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4187                 if (reduced_clock)
4188                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4189                                 reduced_clock->m2;
4190         }
4191
4192         I915_WRITE(FP0(pipe), fp);
4193
4194         crtc->lowfreq_avail = false;
4195         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4196             reduced_clock && i915_powersave) {
4197                 I915_WRITE(FP1(pipe), fp2);
4198                 crtc->lowfreq_avail = true;
4199         } else {
4200                 I915_WRITE(FP1(pipe), fp);
4201         }
4202 }
4203
4204 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4205 {
4206         if (crtc->config.has_pch_encoder)
4207                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4208         else
4209                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4210 }
4211
4212 static void vlv_update_pll(struct intel_crtc *crtc)
4213 {
4214         struct drm_device *dev = crtc->base.dev;
4215         struct drm_i915_private *dev_priv = dev->dev_private;
4216         int pipe = crtc->pipe;
4217         u32 dpll, mdiv, pdiv;
4218         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4219         bool is_sdvo;
4220         u32 temp;
4221
4222         mutex_lock(&dev_priv->dpio_lock);
4223
4224         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4225                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4226
4227         dpll = DPLL_VGA_MODE_DIS;
4228         dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4229         dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4230         dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4231
4232         I915_WRITE(DPLL(pipe), dpll);
4233         POSTING_READ(DPLL(pipe));
4234
4235         bestn = crtc->config.dpll.n;
4236         bestm1 = crtc->config.dpll.m1;
4237         bestm2 = crtc->config.dpll.m2;
4238         bestp1 = crtc->config.dpll.p1;
4239         bestp2 = crtc->config.dpll.p2;
4240
4241         /*
4242          * In Valleyview PLL and program lane counter registers are exposed
4243          * through DPIO interface
4244          */
4245         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4246         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4247         mdiv |= ((bestn << DPIO_N_SHIFT));
4248         mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4249         mdiv |= (1 << DPIO_K_SHIFT);
4250         mdiv |= DPIO_ENABLE_CALIBRATION;
4251         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4252
4253         intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4254
4255         pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4256                 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4257                 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4258                 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4259         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4260
4261         intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4262
4263         dpll |= DPLL_VCO_ENABLE;
4264         I915_WRITE(DPLL(pipe), dpll);
4265         POSTING_READ(DPLL(pipe));
4266         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4267                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4268
4269         intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4270
4271         if (crtc->config.has_dp_encoder)
4272                 intel_dp_set_m_n(crtc);
4273
4274         I915_WRITE(DPLL(pipe), dpll);
4275
4276         /* Wait for the clocks to stabilize. */
4277         POSTING_READ(DPLL(pipe));
4278         udelay(150);
4279
4280         temp = 0;
4281         if (is_sdvo) {
4282                 temp = 0;
4283                 if (crtc->config.pixel_multiplier > 1) {
4284                         temp = (crtc->config.pixel_multiplier - 1)
4285                                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4286                 }
4287         }
4288         I915_WRITE(DPLL_MD(pipe), temp);
4289         POSTING_READ(DPLL_MD(pipe));
4290
4291         /* Now program lane control registers */
4292         if(intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)
4293            || intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
4294                 temp = 0x1000C4;
4295                 if(pipe == 1)
4296                         temp |= (1 << 21);
4297                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4298         }
4299
4300         if(intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) {
4301                 temp = 0x1000C4;
4302                 if(pipe == 1)
4303                         temp |= (1 << 21);
4304                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4305         }
4306
4307         mutex_unlock(&dev_priv->dpio_lock);
4308 }
4309
4310 static void i9xx_update_pll(struct intel_crtc *crtc,
4311                             intel_clock_t *reduced_clock,
4312                             int num_connectors)
4313 {
4314         struct drm_device *dev = crtc->base.dev;
4315         struct drm_i915_private *dev_priv = dev->dev_private;
4316         struct intel_encoder *encoder;
4317         int pipe = crtc->pipe;
4318         u32 dpll;
4319         bool is_sdvo;
4320         struct dpll *clock = &crtc->config.dpll;
4321
4322         i9xx_update_pll_dividers(crtc, reduced_clock);
4323
4324         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4325                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4326
4327         dpll = DPLL_VGA_MODE_DIS;
4328
4329         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4330                 dpll |= DPLLB_MODE_LVDS;
4331         else
4332                 dpll |= DPLLB_MODE_DAC_SERIAL;
4333
4334         if (is_sdvo) {
4335                 if ((crtc->config.pixel_multiplier > 1) &&
4336                     (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
4337                         dpll |= (crtc->config.pixel_multiplier - 1)
4338                                 << SDVO_MULTIPLIER_SHIFT_HIRES;
4339                 }
4340                 dpll |= DPLL_DVO_HIGH_SPEED;
4341         }
4342         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4343                 dpll |= DPLL_DVO_HIGH_SPEED;
4344
4345         /* compute bitmask from p1 value */
4346         if (IS_PINEVIEW(dev))
4347                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4348         else {
4349                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4350                 if (IS_G4X(dev) && reduced_clock)
4351                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4352         }
4353         switch (clock->p2) {
4354         case 5:
4355                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4356                 break;
4357         case 7:
4358                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4359                 break;
4360         case 10:
4361                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4362                 break;
4363         case 14:
4364                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4365                 break;
4366         }
4367         if (INTEL_INFO(dev)->gen >= 4)
4368                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4369
4370         if (is_sdvo && intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
4371                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4372         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
4373                 /* XXX: just matching BIOS for now */
4374                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4375                 dpll |= 3;
4376         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4377                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4378                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4379         else
4380                 dpll |= PLL_REF_INPUT_DREFCLK;
4381
4382         dpll |= DPLL_VCO_ENABLE;
4383         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4384         POSTING_READ(DPLL(pipe));
4385         udelay(150);
4386
4387         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4388                 if (encoder->pre_pll_enable)
4389                         encoder->pre_pll_enable(encoder);
4390
4391         if (crtc->config.has_dp_encoder)
4392                 intel_dp_set_m_n(crtc);
4393
4394         I915_WRITE(DPLL(pipe), dpll);
4395
4396         /* Wait for the clocks to stabilize. */
4397         POSTING_READ(DPLL(pipe));
4398         udelay(150);
4399
4400         if (INTEL_INFO(dev)->gen >= 4) {
4401                 u32 temp = 0;
4402                 if (is_sdvo) {
4403                         temp = 0;
4404                         if (crtc->config.pixel_multiplier > 1) {
4405                                 temp = (crtc->config.pixel_multiplier - 1)
4406                                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4407                         }
4408                 }
4409                 I915_WRITE(DPLL_MD(pipe), temp);
4410         } else {
4411                 /* The pixel multiplier can only be updated once the
4412                  * DPLL is enabled and the clocks are stable.
4413                  *
4414                  * So write it again.
4415                  */
4416                 I915_WRITE(DPLL(pipe), dpll);
4417         }
4418 }
4419
4420 static void i8xx_update_pll(struct intel_crtc *crtc,
4421                             struct drm_display_mode *adjusted_mode,
4422                             intel_clock_t *reduced_clock,
4423                             int num_connectors)
4424 {
4425         struct drm_device *dev = crtc->base.dev;
4426         struct drm_i915_private *dev_priv = dev->dev_private;
4427         struct intel_encoder *encoder;
4428         int pipe = crtc->pipe;
4429         u32 dpll;
4430         struct dpll *clock = &crtc->config.dpll;
4431
4432         i9xx_update_pll_dividers(crtc, reduced_clock);
4433
4434         dpll = DPLL_VGA_MODE_DIS;
4435
4436         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4437                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4438         } else {
4439                 if (clock->p1 == 2)
4440                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4441                 else
4442                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4443                 if (clock->p2 == 4)
4444                         dpll |= PLL_P2_DIVIDE_BY_4;
4445         }
4446
4447         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4448                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4449                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4450         else
4451                 dpll |= PLL_REF_INPUT_DREFCLK;
4452
4453         dpll |= DPLL_VCO_ENABLE;
4454         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4455         POSTING_READ(DPLL(pipe));
4456         udelay(150);
4457
4458         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4459                 if (encoder->pre_pll_enable)
4460                         encoder->pre_pll_enable(encoder);
4461
4462         I915_WRITE(DPLL(pipe), dpll);
4463
4464         /* Wait for the clocks to stabilize. */
4465         POSTING_READ(DPLL(pipe));
4466         udelay(150);
4467
4468         /* The pixel multiplier can only be updated once the
4469          * DPLL is enabled and the clocks are stable.
4470          *
4471          * So write it again.
4472          */
4473         I915_WRITE(DPLL(pipe), dpll);
4474 }
4475
4476 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4477                                    struct drm_display_mode *mode,
4478                                    struct drm_display_mode *adjusted_mode)
4479 {
4480         struct drm_device *dev = intel_crtc->base.dev;
4481         struct drm_i915_private *dev_priv = dev->dev_private;
4482         enum pipe pipe = intel_crtc->pipe;
4483         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4484         uint32_t vsyncshift;
4485
4486         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4487                 /* the chip adds 2 halflines automatically */
4488                 adjusted_mode->crtc_vtotal -= 1;
4489                 adjusted_mode->crtc_vblank_end -= 1;
4490                 vsyncshift = adjusted_mode->crtc_hsync_start
4491                              - adjusted_mode->crtc_htotal / 2;
4492         } else {
4493                 vsyncshift = 0;
4494         }
4495
4496         if (INTEL_INFO(dev)->gen > 3)
4497                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4498
4499         I915_WRITE(HTOTAL(cpu_transcoder),
4500                    (adjusted_mode->crtc_hdisplay - 1) |
4501                    ((adjusted_mode->crtc_htotal - 1) << 16));
4502         I915_WRITE(HBLANK(cpu_transcoder),
4503                    (adjusted_mode->crtc_hblank_start - 1) |
4504                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4505         I915_WRITE(HSYNC(cpu_transcoder),
4506                    (adjusted_mode->crtc_hsync_start - 1) |
4507                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4508
4509         I915_WRITE(VTOTAL(cpu_transcoder),
4510                    (adjusted_mode->crtc_vdisplay - 1) |
4511                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4512         I915_WRITE(VBLANK(cpu_transcoder),
4513                    (adjusted_mode->crtc_vblank_start - 1) |
4514                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4515         I915_WRITE(VSYNC(cpu_transcoder),
4516                    (adjusted_mode->crtc_vsync_start - 1) |
4517                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4518
4519         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4520          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4521          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4522          * bits. */
4523         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4524             (pipe == PIPE_B || pipe == PIPE_C))
4525                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4526
4527         /* pipesrc controls the size that is scaled from, which should
4528          * always be the user's requested size.
4529          */
4530         I915_WRITE(PIPESRC(pipe),
4531                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4532 }
4533
4534 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4535 {
4536         struct drm_device *dev = intel_crtc->base.dev;
4537         struct drm_i915_private *dev_priv = dev->dev_private;
4538         uint32_t pipeconf;
4539
4540         pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4541
4542         if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4543                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4544                  * core speed.
4545                  *
4546                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4547                  * pipe == 0 check?
4548                  */
4549                 if (intel_crtc->config.requested_mode.clock >
4550                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4551                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4552                 else
4553                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4554         }
4555
4556         /* default to 8bpc */
4557         pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
4558         if (intel_crtc->config.has_dp_encoder) {
4559                 if (intel_crtc->config.dither) {
4560                         pipeconf |= PIPECONF_6BPC |
4561                                     PIPECONF_DITHER_EN |
4562                                     PIPECONF_DITHER_TYPE_SP;
4563                 }
4564         }
4565
4566         if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(&intel_crtc->base,
4567                                                       INTEL_OUTPUT_EDP)) {
4568                 if (intel_crtc->config.dither) {
4569                         pipeconf |= PIPECONF_6BPC |
4570                                         PIPECONF_ENABLE |
4571                                         I965_PIPECONF_ACTIVE;
4572                 }
4573         }
4574
4575         if (HAS_PIPE_CXSR(dev)) {
4576                 if (intel_crtc->lowfreq_avail) {
4577                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4578                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4579                 } else {
4580                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4581                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4582                 }
4583         }
4584
4585         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4586         if (!IS_GEN2(dev) &&
4587             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4588                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4589         else
4590                 pipeconf |= PIPECONF_PROGRESSIVE;
4591
4592         if (IS_VALLEYVIEW(dev)) {
4593                 if (intel_crtc->config.limited_color_range)
4594                         pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4595                 else
4596                         pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4597         }
4598
4599         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4600         POSTING_READ(PIPECONF(intel_crtc->pipe));
4601 }
4602
4603 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4604                               int x, int y,
4605                               struct drm_framebuffer *fb)
4606 {
4607         struct drm_device *dev = crtc->dev;
4608         struct drm_i915_private *dev_priv = dev->dev_private;
4609         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4610         struct drm_display_mode *adjusted_mode =
4611                 &intel_crtc->config.adjusted_mode;
4612         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4613         int pipe = intel_crtc->pipe;
4614         int plane = intel_crtc->plane;
4615         int refclk, num_connectors = 0;
4616         intel_clock_t clock, reduced_clock;
4617         u32 dspcntr;
4618         bool ok, has_reduced_clock = false, is_sdvo = false;
4619         bool is_lvds = false, is_tv = false;
4620         struct intel_encoder *encoder;
4621         const intel_limit_t *limit;
4622         int ret;
4623
4624         for_each_encoder_on_crtc(dev, crtc, encoder) {
4625                 switch (encoder->type) {
4626                 case INTEL_OUTPUT_LVDS:
4627                         is_lvds = true;
4628                         break;
4629                 case INTEL_OUTPUT_SDVO:
4630                 case INTEL_OUTPUT_HDMI:
4631                         is_sdvo = true;
4632                         if (encoder->needs_tv_clock)
4633                                 is_tv = true;
4634                         break;
4635                 case INTEL_OUTPUT_TVOUT:
4636                         is_tv = true;
4637                         break;
4638                 }
4639
4640                 num_connectors++;
4641         }
4642
4643         refclk = i9xx_get_refclk(crtc, num_connectors);
4644
4645         /*
4646          * Returns a set of divisors for the desired target clock with the given
4647          * refclk, or FALSE.  The returned values represent the clock equation:
4648          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4649          */
4650         limit = intel_limit(crtc, refclk);
4651         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4652                              &clock);
4653         if (!ok) {
4654                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4655                 return -EINVAL;
4656         }
4657
4658         /* Ensure that the cursor is valid for the new mode before changing... */
4659         intel_crtc_update_cursor(crtc, true);
4660
4661         if (is_lvds && dev_priv->lvds_downclock_avail) {
4662                 /*
4663                  * Ensure we match the reduced clock's P to the target clock.
4664                  * If the clocks don't match, we can't switch the display clock
4665                  * by using the FP0/FP1. In such case we will disable the LVDS
4666                  * downclock feature.
4667                 */
4668                 has_reduced_clock = limit->find_pll(limit, crtc,
4669                                                     dev_priv->lvds_downclock,
4670                                                     refclk,
4671                                                     &clock,
4672                                                     &reduced_clock);
4673         }
4674         /* Compat-code for transition, will disappear. */
4675         if (!intel_crtc->config.clock_set) {
4676                 intel_crtc->config.dpll.n = clock.n;
4677                 intel_crtc->config.dpll.m1 = clock.m1;
4678                 intel_crtc->config.dpll.m2 = clock.m2;
4679                 intel_crtc->config.dpll.p1 = clock.p1;
4680                 intel_crtc->config.dpll.p2 = clock.p2;
4681         }
4682
4683         if (is_sdvo && is_tv)
4684                 i9xx_adjust_sdvo_tv_clock(intel_crtc);
4685
4686         if (IS_GEN2(dev))
4687                 i8xx_update_pll(intel_crtc, adjusted_mode,
4688                                 has_reduced_clock ? &reduced_clock : NULL,
4689                                 num_connectors);
4690         else if (IS_VALLEYVIEW(dev))
4691                 vlv_update_pll(intel_crtc);
4692         else
4693                 i9xx_update_pll(intel_crtc,
4694                                 has_reduced_clock ? &reduced_clock : NULL,
4695                                 num_connectors);
4696
4697         /* Set up the display plane register */
4698         dspcntr = DISPPLANE_GAMMA_ENABLE;
4699
4700         if (!IS_VALLEYVIEW(dev)) {
4701                 if (pipe == 0)
4702                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4703                 else
4704                         dspcntr |= DISPPLANE_SEL_PIPE_B;
4705         }
4706
4707         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4708         drm_mode_debug_printmodeline(mode);
4709
4710         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4711
4712         /* pipesrc and dspsize control the size that is scaled from,
4713          * which should always be the user's requested size.
4714          */
4715         I915_WRITE(DSPSIZE(plane),
4716                    ((mode->vdisplay - 1) << 16) |
4717                    (mode->hdisplay - 1));
4718         I915_WRITE(DSPPOS(plane), 0);
4719
4720         i9xx_set_pipeconf(intel_crtc);
4721
4722         intel_enable_pipe(dev_priv, pipe, false);
4723
4724         intel_wait_for_vblank(dev, pipe);
4725
4726         I915_WRITE(DSPCNTR(plane), dspcntr);
4727         POSTING_READ(DSPCNTR(plane));
4728
4729         ret = intel_pipe_set_base(crtc, x, y, fb);
4730
4731         intel_update_watermarks(dev);
4732
4733         return ret;
4734 }
4735
4736 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4737                                  struct intel_crtc_config *pipe_config)
4738 {
4739         struct drm_device *dev = crtc->base.dev;
4740         struct drm_i915_private *dev_priv = dev->dev_private;
4741         uint32_t tmp;
4742
4743         tmp = I915_READ(PIPECONF(crtc->pipe));
4744         if (!(tmp & PIPECONF_ENABLE))
4745                 return false;
4746
4747         return true;
4748 }
4749
4750 static void ironlake_init_pch_refclk(struct drm_device *dev)
4751 {
4752         struct drm_i915_private *dev_priv = dev->dev_private;
4753         struct drm_mode_config *mode_config = &dev->mode_config;
4754         struct intel_encoder *encoder;
4755         u32 val, final;
4756         bool has_lvds = false;
4757         bool has_cpu_edp = false;
4758         bool has_pch_edp = false;
4759         bool has_panel = false;
4760         bool has_ck505 = false;
4761         bool can_ssc = false;
4762
4763         /* We need to take the global config into account */
4764         list_for_each_entry(encoder, &mode_config->encoder_list,
4765                             base.head) {
4766                 switch (encoder->type) {
4767                 case INTEL_OUTPUT_LVDS:
4768                         has_panel = true;
4769                         has_lvds = true;
4770                         break;
4771                 case INTEL_OUTPUT_EDP:
4772                         has_panel = true;
4773                         if (intel_encoder_is_pch_edp(&encoder->base))
4774                                 has_pch_edp = true;
4775                         else
4776                                 has_cpu_edp = true;
4777                         break;
4778                 }
4779         }
4780
4781         if (HAS_PCH_IBX(dev)) {
4782                 has_ck505 = dev_priv->display_clock_mode;
4783                 can_ssc = has_ck505;
4784         } else {
4785                 has_ck505 = false;
4786                 can_ssc = true;
4787         }
4788
4789         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4790                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4791                       has_ck505);
4792
4793         /* Ironlake: try to setup display ref clock before DPLL
4794          * enabling. This is only under driver's control after
4795          * PCH B stepping, previous chipset stepping should be
4796          * ignoring this setting.
4797          */
4798         val = I915_READ(PCH_DREF_CONTROL);
4799
4800         /* As we must carefully and slowly disable/enable each source in turn,
4801          * compute the final state we want first and check if we need to
4802          * make any changes at all.
4803          */
4804         final = val;
4805         final &= ~DREF_NONSPREAD_SOURCE_MASK;
4806         if (has_ck505)
4807                 final |= DREF_NONSPREAD_CK505_ENABLE;
4808         else
4809                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
4810
4811         final &= ~DREF_SSC_SOURCE_MASK;
4812         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4813         final &= ~DREF_SSC1_ENABLE;
4814
4815         if (has_panel) {
4816                 final |= DREF_SSC_SOURCE_ENABLE;
4817
4818                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4819                         final |= DREF_SSC1_ENABLE;
4820
4821                 if (has_cpu_edp) {
4822                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
4823                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4824                         else
4825                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4826                 } else
4827                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4828         } else {
4829                 final |= DREF_SSC_SOURCE_DISABLE;
4830                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4831         }
4832
4833         if (final == val)
4834                 return;
4835
4836         /* Always enable nonspread source */
4837         val &= ~DREF_NONSPREAD_SOURCE_MASK;
4838
4839         if (has_ck505)
4840                 val |= DREF_NONSPREAD_CK505_ENABLE;
4841         else
4842                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
4843
4844         if (has_panel) {
4845                 val &= ~DREF_SSC_SOURCE_MASK;
4846                 val |= DREF_SSC_SOURCE_ENABLE;
4847
4848                 /* SSC must be turned on before enabling the CPU output  */
4849                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4850                         DRM_DEBUG_KMS("Using SSC on panel\n");
4851                         val |= DREF_SSC1_ENABLE;
4852                 } else
4853                         val &= ~DREF_SSC1_ENABLE;
4854
4855                 /* Get SSC going before enabling the outputs */
4856                 I915_WRITE(PCH_DREF_CONTROL, val);
4857                 POSTING_READ(PCH_DREF_CONTROL);
4858                 udelay(200);
4859
4860                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4861
4862                 /* Enable CPU source on CPU attached eDP */
4863                 if (has_cpu_edp) {
4864                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4865                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4866                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4867                         }
4868                         else
4869                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4870                 } else
4871                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4872
4873                 I915_WRITE(PCH_DREF_CONTROL, val);
4874                 POSTING_READ(PCH_DREF_CONTROL);
4875                 udelay(200);
4876         } else {
4877                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4878
4879                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4880
4881                 /* Turn off CPU output */
4882                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4883
4884                 I915_WRITE(PCH_DREF_CONTROL, val);
4885                 POSTING_READ(PCH_DREF_CONTROL);
4886                 udelay(200);
4887
4888                 /* Turn off the SSC source */
4889                 val &= ~DREF_SSC_SOURCE_MASK;
4890                 val |= DREF_SSC_SOURCE_DISABLE;
4891
4892                 /* Turn off SSC1 */
4893                 val &= ~DREF_SSC1_ENABLE;
4894
4895                 I915_WRITE(PCH_DREF_CONTROL, val);
4896                 POSTING_READ(PCH_DREF_CONTROL);
4897                 udelay(200);
4898         }
4899
4900         BUG_ON(val != final);
4901 }
4902
4903 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4904 static void lpt_init_pch_refclk(struct drm_device *dev)
4905 {
4906         struct drm_i915_private *dev_priv = dev->dev_private;
4907         struct drm_mode_config *mode_config = &dev->mode_config;
4908         struct intel_encoder *encoder;
4909         bool has_vga = false;
4910         bool is_sdv = false;
4911         u32 tmp;
4912
4913         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4914                 switch (encoder->type) {
4915                 case INTEL_OUTPUT_ANALOG:
4916                         has_vga = true;
4917                         break;
4918                 }
4919         }
4920
4921         if (!has_vga)
4922                 return;
4923
4924         mutex_lock(&dev_priv->dpio_lock);
4925
4926         /* XXX: Rip out SDV support once Haswell ships for real. */
4927         if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
4928                 is_sdv = true;
4929
4930         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4931         tmp &= ~SBI_SSCCTL_DISABLE;
4932         tmp |= SBI_SSCCTL_PATHALT;
4933         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4934
4935         udelay(24);
4936
4937         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4938         tmp &= ~SBI_SSCCTL_PATHALT;
4939         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4940
4941         if (!is_sdv) {
4942                 tmp = I915_READ(SOUTH_CHICKEN2);
4943                 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
4944                 I915_WRITE(SOUTH_CHICKEN2, tmp);
4945
4946                 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
4947                                        FDI_MPHY_IOSFSB_RESET_STATUS, 100))
4948                         DRM_ERROR("FDI mPHY reset assert timeout\n");
4949
4950                 tmp = I915_READ(SOUTH_CHICKEN2);
4951                 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
4952                 I915_WRITE(SOUTH_CHICKEN2, tmp);
4953
4954                 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
4955                                         FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
4956                                        100))
4957                         DRM_ERROR("FDI mPHY reset de-assert timeout\n");
4958         }
4959
4960         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
4961         tmp &= ~(0xFF << 24);
4962         tmp |= (0x12 << 24);
4963         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
4964
4965         if (is_sdv) {
4966                 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
4967                 tmp |= 0x7FFF;
4968                 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
4969         }
4970
4971         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
4972         tmp |= (1 << 11);
4973         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
4974
4975         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
4976         tmp |= (1 << 11);
4977         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
4978
4979         if (is_sdv) {
4980                 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
4981                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4982                 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
4983
4984                 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
4985                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4986                 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
4987
4988                 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
4989                 tmp |= (0x3F << 8);
4990                 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
4991
4992                 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
4993                 tmp |= (0x3F << 8);
4994                 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
4995         }
4996
4997         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
4998         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
4999         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5000
5001         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5002         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5003         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5004
5005         if (!is_sdv) {
5006                 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5007                 tmp &= ~(7 << 13);
5008                 tmp |= (5 << 13);
5009                 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5010
5011                 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5012                 tmp &= ~(7 << 13);
5013                 tmp |= (5 << 13);
5014                 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5015         }
5016
5017         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5018         tmp &= ~0xFF;
5019         tmp |= 0x1C;
5020         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5021
5022         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5023         tmp &= ~0xFF;
5024         tmp |= 0x1C;
5025         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5026
5027         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5028         tmp &= ~(0xFF << 16);
5029         tmp |= (0x1C << 16);
5030         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5031
5032         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5033         tmp &= ~(0xFF << 16);
5034         tmp |= (0x1C << 16);
5035         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5036
5037         if (!is_sdv) {
5038                 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5039                 tmp |= (1 << 27);
5040                 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5041
5042                 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5043                 tmp |= (1 << 27);
5044                 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5045
5046                 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5047                 tmp &= ~(0xF << 28);
5048                 tmp |= (4 << 28);
5049                 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5050
5051                 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5052                 tmp &= ~(0xF << 28);
5053                 tmp |= (4 << 28);
5054                 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5055         }
5056
5057         /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5058         tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5059         tmp |= SBI_DBUFF0_ENABLE;
5060         intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5061
5062         mutex_unlock(&dev_priv->dpio_lock);
5063 }
5064
5065 /*
5066  * Initialize reference clocks when the driver loads
5067  */
5068 void intel_init_pch_refclk(struct drm_device *dev)
5069 {
5070         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5071                 ironlake_init_pch_refclk(dev);
5072         else if (HAS_PCH_LPT(dev))
5073                 lpt_init_pch_refclk(dev);
5074 }
5075
5076 static int ironlake_get_refclk(struct drm_crtc *crtc)
5077 {
5078         struct drm_device *dev = crtc->dev;
5079         struct drm_i915_private *dev_priv = dev->dev_private;
5080         struct intel_encoder *encoder;
5081         struct intel_encoder *edp_encoder = NULL;
5082         int num_connectors = 0;
5083         bool is_lvds = false;
5084
5085         for_each_encoder_on_crtc(dev, crtc, encoder) {
5086                 switch (encoder->type) {
5087                 case INTEL_OUTPUT_LVDS:
5088                         is_lvds = true;
5089                         break;
5090                 case INTEL_OUTPUT_EDP:
5091                         edp_encoder = encoder;
5092                         break;
5093                 }
5094                 num_connectors++;
5095         }
5096
5097         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5098                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5099                               dev_priv->lvds_ssc_freq);
5100                 return dev_priv->lvds_ssc_freq * 1000;
5101         }
5102
5103         return 120000;
5104 }
5105
5106 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5107                                   struct drm_display_mode *adjusted_mode,
5108                                   bool dither)
5109 {
5110         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5111         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5112         int pipe = intel_crtc->pipe;
5113         uint32_t val;
5114
5115         val = I915_READ(PIPECONF(pipe));
5116
5117         val &= ~PIPECONF_BPC_MASK;
5118         switch (intel_crtc->config.pipe_bpp) {
5119         case 18:
5120                 val |= PIPECONF_6BPC;
5121                 break;
5122         case 24:
5123                 val |= PIPECONF_8BPC;
5124                 break;
5125         case 30:
5126                 val |= PIPECONF_10BPC;
5127                 break;
5128         case 36:
5129                 val |= PIPECONF_12BPC;
5130                 break;
5131         default:
5132                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5133                 BUG();
5134         }
5135
5136         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5137         if (dither)
5138                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5139
5140         val &= ~PIPECONF_INTERLACE_MASK;
5141         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5142                 val |= PIPECONF_INTERLACED_ILK;
5143         else
5144                 val |= PIPECONF_PROGRESSIVE;
5145
5146         if (intel_crtc->config.limited_color_range)
5147                 val |= PIPECONF_COLOR_RANGE_SELECT;
5148         else
5149                 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5150
5151         I915_WRITE(PIPECONF(pipe), val);
5152         POSTING_READ(PIPECONF(pipe));
5153 }
5154
5155 /*
5156  * Set up the pipe CSC unit.
5157  *
5158  * Currently only full range RGB to limited range RGB conversion
5159  * is supported, but eventually this should handle various
5160  * RGB<->YCbCr scenarios as well.
5161  */
5162 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5163 {
5164         struct drm_device *dev = crtc->dev;
5165         struct drm_i915_private *dev_priv = dev->dev_private;
5166         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5167         int pipe = intel_crtc->pipe;
5168         uint16_t coeff = 0x7800; /* 1.0 */
5169
5170         /*
5171          * TODO: Check what kind of values actually come out of the pipe
5172          * with these coeff/postoff values and adjust to get the best
5173          * accuracy. Perhaps we even need to take the bpc value into
5174          * consideration.
5175          */
5176
5177         if (intel_crtc->config.limited_color_range)
5178                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5179
5180         /*
5181          * GY/GU and RY/RU should be the other way around according
5182          * to BSpec, but reality doesn't agree. Just set them up in
5183          * a way that results in the correct picture.
5184          */
5185         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5186         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5187
5188         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5189         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5190
5191         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5192         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5193
5194         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5195         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5196         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5197
5198         if (INTEL_INFO(dev)->gen > 6) {
5199                 uint16_t postoff = 0;
5200
5201                 if (intel_crtc->config.limited_color_range)
5202                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
5203
5204                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5205                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5206                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5207
5208                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5209         } else {
5210                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5211
5212                 if (intel_crtc->config.limited_color_range)
5213                         mode |= CSC_BLACK_SCREEN_OFFSET;
5214
5215                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5216         }
5217 }
5218
5219 static void haswell_set_pipeconf(struct drm_crtc *crtc,
5220                                  struct drm_display_mode *adjusted_mode,
5221                                  bool dither)
5222 {
5223         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5224         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5225         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5226         uint32_t val;
5227
5228         val = I915_READ(PIPECONF(cpu_transcoder));
5229
5230         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5231         if (dither)
5232                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5233
5234         val &= ~PIPECONF_INTERLACE_MASK_HSW;
5235         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5236                 val |= PIPECONF_INTERLACED_ILK;
5237         else
5238                 val |= PIPECONF_PROGRESSIVE;
5239
5240         I915_WRITE(PIPECONF(cpu_transcoder), val);
5241         POSTING_READ(PIPECONF(cpu_transcoder));
5242 }
5243
5244 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5245                                     struct drm_display_mode *adjusted_mode,
5246                                     intel_clock_t *clock,
5247                                     bool *has_reduced_clock,
5248                                     intel_clock_t *reduced_clock)
5249 {
5250         struct drm_device *dev = crtc->dev;
5251         struct drm_i915_private *dev_priv = dev->dev_private;
5252         struct intel_encoder *intel_encoder;
5253         int refclk;
5254         const intel_limit_t *limit;
5255         bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5256
5257         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5258                 switch (intel_encoder->type) {
5259                 case INTEL_OUTPUT_LVDS:
5260                         is_lvds = true;
5261                         break;
5262                 case INTEL_OUTPUT_SDVO:
5263                 case INTEL_OUTPUT_HDMI:
5264                         is_sdvo = true;
5265                         if (intel_encoder->needs_tv_clock)
5266                                 is_tv = true;
5267                         break;
5268                 case INTEL_OUTPUT_TVOUT:
5269                         is_tv = true;
5270                         break;
5271                 }
5272         }
5273
5274         refclk = ironlake_get_refclk(crtc);
5275
5276         /*
5277          * Returns a set of divisors for the desired target clock with the given
5278          * refclk, or FALSE.  The returned values represent the clock equation:
5279          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5280          */
5281         limit = intel_limit(crtc, refclk);
5282         ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5283                               clock);
5284         if (!ret)
5285                 return false;
5286
5287         if (is_lvds && dev_priv->lvds_downclock_avail) {
5288                 /*
5289                  * Ensure we match the reduced clock's P to the target clock.
5290                  * If the clocks don't match, we can't switch the display clock
5291                  * by using the FP0/FP1. In such case we will disable the LVDS
5292                  * downclock feature.
5293                 */
5294                 *has_reduced_clock = limit->find_pll(limit, crtc,
5295                                                      dev_priv->lvds_downclock,
5296                                                      refclk,
5297                                                      clock,
5298                                                      reduced_clock);
5299         }
5300
5301         if (is_sdvo && is_tv)
5302                 i9xx_adjust_sdvo_tv_clock(to_intel_crtc(crtc));
5303
5304         return true;
5305 }
5306
5307 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5308 {
5309         struct drm_i915_private *dev_priv = dev->dev_private;
5310         uint32_t temp;
5311
5312         temp = I915_READ(SOUTH_CHICKEN1);
5313         if (temp & FDI_BC_BIFURCATION_SELECT)
5314                 return;
5315
5316         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5317         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5318
5319         temp |= FDI_BC_BIFURCATION_SELECT;
5320         DRM_DEBUG_KMS("enabling fdi C rx\n");
5321         I915_WRITE(SOUTH_CHICKEN1, temp);
5322         POSTING_READ(SOUTH_CHICKEN1);
5323 }
5324
5325 static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5326 {
5327         struct drm_device *dev = intel_crtc->base.dev;
5328         struct drm_i915_private *dev_priv = dev->dev_private;
5329         struct intel_crtc *pipe_B_crtc =
5330                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5331
5332         DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5333                       intel_crtc->pipe, intel_crtc->fdi_lanes);
5334         if (intel_crtc->fdi_lanes > 4) {
5335                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5336                               intel_crtc->pipe, intel_crtc->fdi_lanes);
5337                 /* Clamp lanes to avoid programming the hw with bogus values. */
5338                 intel_crtc->fdi_lanes = 4;
5339
5340                 return false;
5341         }
5342
5343         if (INTEL_INFO(dev)->num_pipes == 2)
5344                 return true;
5345
5346         switch (intel_crtc->pipe) {
5347         case PIPE_A:
5348                 return true;
5349         case PIPE_B:
5350                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5351                     intel_crtc->fdi_lanes > 2) {
5352                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5353                                       intel_crtc->pipe, intel_crtc->fdi_lanes);
5354                         /* Clamp lanes to avoid programming the hw with bogus values. */
5355                         intel_crtc->fdi_lanes = 2;
5356
5357                         return false;
5358                 }
5359
5360                 if (intel_crtc->fdi_lanes > 2)
5361                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5362                 else
5363                         cpt_enable_fdi_bc_bifurcation(dev);
5364
5365                 return true;
5366         case PIPE_C:
5367                 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5368                         if (intel_crtc->fdi_lanes > 2) {
5369                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5370                                               intel_crtc->pipe, intel_crtc->fdi_lanes);
5371                                 /* Clamp lanes to avoid programming the hw with bogus values. */
5372                                 intel_crtc->fdi_lanes = 2;
5373
5374                                 return false;
5375                         }
5376                 } else {
5377                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5378                         return false;
5379                 }
5380
5381                 cpt_enable_fdi_bc_bifurcation(dev);
5382
5383                 return true;
5384         default:
5385                 BUG();
5386         }
5387 }
5388
5389 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5390 {
5391         /*
5392          * Account for spread spectrum to avoid
5393          * oversubscribing the link. Max center spread
5394          * is 2.5%; use 5% for safety's sake.
5395          */
5396         u32 bps = target_clock * bpp * 21 / 20;
5397         return bps / (link_bw * 8) + 1;
5398 }
5399
5400 void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5401                                   struct intel_link_m_n *m_n)
5402 {
5403         struct drm_device *dev = crtc->base.dev;
5404         struct drm_i915_private *dev_priv = dev->dev_private;
5405         int pipe = crtc->pipe;
5406
5407         I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5408         I915_WRITE(TRANSDATA_N1(pipe), m_n->gmch_n);
5409         I915_WRITE(TRANSDPLINK_M1(pipe), m_n->link_m);
5410         I915_WRITE(TRANSDPLINK_N1(pipe), m_n->link_n);
5411 }
5412
5413 void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5414                                   struct intel_link_m_n *m_n)
5415 {
5416         struct drm_device *dev = crtc->base.dev;
5417         struct drm_i915_private *dev_priv = dev->dev_private;
5418         int pipe = crtc->pipe;
5419         enum transcoder transcoder = crtc->cpu_transcoder;
5420
5421         if (INTEL_INFO(dev)->gen >= 5) {
5422                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5423                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5424                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5425                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5426         } else {
5427                 I915_WRITE(PIPE_GMCH_DATA_M(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5428                 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n->gmch_n);
5429                 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n->link_m);
5430                 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n->link_n);
5431         }
5432 }
5433
5434 static void ironlake_fdi_set_m_n(struct drm_crtc *crtc)
5435 {
5436         struct drm_device *dev = crtc->dev;
5437         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5438         struct drm_display_mode *adjusted_mode =
5439                 &intel_crtc->config.adjusted_mode;
5440         struct intel_link_m_n m_n = {0};
5441         int target_clock, lane, link_bw;
5442
5443         /* FDI is a binary signal running at ~2.7GHz, encoding
5444          * each output octet as 10 bits. The actual frequency
5445          * is stored as a divider into a 100MHz clock, and the
5446          * mode pixel clock is stored in units of 1KHz.
5447          * Hence the bw of each lane in terms of the mode signal
5448          * is:
5449          */
5450         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5451
5452         if (intel_crtc->config.pixel_target_clock)
5453                 target_clock = intel_crtc->config.pixel_target_clock;
5454         else
5455                 target_clock = adjusted_mode->clock;
5456
5457         lane = ironlake_get_lanes_required(target_clock, link_bw,
5458                                            intel_crtc->config.pipe_bpp);
5459
5460         intel_crtc->fdi_lanes = lane;
5461
5462         if (intel_crtc->config.pixel_multiplier > 1)
5463                 link_bw *= intel_crtc->config.pixel_multiplier;
5464         intel_link_compute_m_n(intel_crtc->config.pipe_bpp, lane, target_clock,
5465                                link_bw, &m_n);
5466
5467         intel_cpu_transcoder_set_m_n(intel_crtc, &m_n);
5468 }
5469
5470 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5471                                       intel_clock_t *clock, u32 *fp,
5472                                       intel_clock_t *reduced_clock, u32 *fp2)
5473 {
5474         struct drm_crtc *crtc = &intel_crtc->base;
5475         struct drm_device *dev = crtc->dev;
5476         struct drm_i915_private *dev_priv = dev->dev_private;
5477         struct intel_encoder *intel_encoder;
5478         uint32_t dpll;
5479         int factor, num_connectors = 0;
5480         bool is_lvds = false, is_sdvo = false, is_tv = false;
5481
5482         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5483                 switch (intel_encoder->type) {
5484                 case INTEL_OUTPUT_LVDS:
5485                         is_lvds = true;
5486                         break;
5487                 case INTEL_OUTPUT_SDVO:
5488                 case INTEL_OUTPUT_HDMI:
5489                         is_sdvo = true;
5490                         if (intel_encoder->needs_tv_clock)
5491                                 is_tv = true;
5492                         break;
5493                 case INTEL_OUTPUT_TVOUT:
5494                         is_tv = true;
5495                         break;
5496                 }
5497
5498                 num_connectors++;
5499         }
5500
5501         /* Enable autotuning of the PLL clock (if permissible) */
5502         factor = 21;
5503         if (is_lvds) {
5504                 if ((intel_panel_use_ssc(dev_priv) &&
5505                      dev_priv->lvds_ssc_freq == 100) ||
5506                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5507                         factor = 25;
5508         } else if (is_sdvo && is_tv)
5509                 factor = 20;
5510
5511         if (clock->m < factor * clock->n)
5512                 *fp |= FP_CB_TUNE;
5513
5514         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5515                 *fp2 |= FP_CB_TUNE;
5516
5517         dpll = 0;
5518
5519         if (is_lvds)
5520                 dpll |= DPLLB_MODE_LVDS;
5521         else
5522                 dpll |= DPLLB_MODE_DAC_SERIAL;
5523         if (is_sdvo) {
5524                 if (intel_crtc->config.pixel_multiplier > 1) {
5525                         dpll |= (intel_crtc->config.pixel_multiplier - 1)
5526                                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5527                 }
5528                 dpll |= DPLL_DVO_HIGH_SPEED;
5529         }
5530         if (intel_crtc->config.has_dp_encoder &&
5531             intel_crtc->config.has_pch_encoder)
5532                 dpll |= DPLL_DVO_HIGH_SPEED;
5533
5534         /* compute bitmask from p1 value */
5535         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5536         /* also FPA1 */
5537         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5538
5539         switch (clock->p2) {
5540         case 5:
5541                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5542                 break;
5543         case 7:
5544                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5545                 break;
5546         case 10:
5547                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5548                 break;
5549         case 14:
5550                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5551                 break;
5552         }
5553
5554         if (is_sdvo && is_tv)
5555                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5556         else if (is_tv)
5557                 /* XXX: just matching BIOS for now */
5558                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5559                 dpll |= 3;
5560         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5561                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5562         else
5563                 dpll |= PLL_REF_INPUT_DREFCLK;
5564
5565         return dpll;
5566 }
5567
5568 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5569                                   int x, int y,
5570                                   struct drm_framebuffer *fb)
5571 {
5572         struct drm_device *dev = crtc->dev;
5573         struct drm_i915_private *dev_priv = dev->dev_private;
5574         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5575         struct drm_display_mode *adjusted_mode =
5576                 &intel_crtc->config.adjusted_mode;
5577         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5578         int pipe = intel_crtc->pipe;
5579         int plane = intel_crtc->plane;
5580         int num_connectors = 0;
5581         intel_clock_t clock, reduced_clock;
5582         u32 dpll, fp = 0, fp2 = 0;
5583         bool ok, has_reduced_clock = false;
5584         bool is_lvds = false;
5585         struct intel_encoder *encoder;
5586         int ret;
5587         bool dither, fdi_config_ok;
5588
5589         for_each_encoder_on_crtc(dev, crtc, encoder) {
5590                 switch (encoder->type) {
5591                 case INTEL_OUTPUT_LVDS:
5592                         is_lvds = true;
5593                         break;
5594                 }
5595
5596                 num_connectors++;
5597         }
5598
5599         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5600              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5601
5602         intel_crtc->cpu_transcoder = pipe;
5603
5604         ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5605                                      &has_reduced_clock, &reduced_clock);
5606         if (!ok) {
5607                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5608                 return -EINVAL;
5609         }
5610         /* Compat-code for transition, will disappear. */
5611         if (!intel_crtc->config.clock_set) {
5612                 intel_crtc->config.dpll.n = clock.n;
5613                 intel_crtc->config.dpll.m1 = clock.m1;
5614                 intel_crtc->config.dpll.m2 = clock.m2;
5615                 intel_crtc->config.dpll.p1 = clock.p1;
5616                 intel_crtc->config.dpll.p2 = clock.p2;
5617         }
5618
5619         /* Ensure that the cursor is valid for the new mode before changing... */
5620         intel_crtc_update_cursor(crtc, true);
5621
5622         /* determine panel color depth */
5623         dither = intel_crtc->config.dither;
5624         if (is_lvds && dev_priv->lvds_dither)
5625                 dither = true;
5626
5627         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5628         if (has_reduced_clock)
5629                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5630                         reduced_clock.m2;
5631
5632         dpll = ironlake_compute_dpll(intel_crtc, &clock, &fp, &reduced_clock,
5633                                      has_reduced_clock ? &fp2 : NULL);
5634
5635         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5636         drm_mode_debug_printmodeline(mode);
5637
5638         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5639         if (intel_crtc->config.has_pch_encoder) {
5640                 struct intel_pch_pll *pll;
5641
5642                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5643                 if (pll == NULL) {
5644                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5645                                          pipe);
5646                         return -EINVAL;
5647                 }
5648         } else
5649                 intel_put_pch_pll(intel_crtc);
5650
5651         if (intel_crtc->config.has_dp_encoder)
5652                 intel_dp_set_m_n(intel_crtc);
5653
5654         for_each_encoder_on_crtc(dev, crtc, encoder)
5655                 if (encoder->pre_pll_enable)
5656                         encoder->pre_pll_enable(encoder);
5657
5658         if (intel_crtc->pch_pll) {
5659                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5660
5661                 /* Wait for the clocks to stabilize. */
5662                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5663                 udelay(150);
5664
5665                 /* The pixel multiplier can only be updated once the
5666                  * DPLL is enabled and the clocks are stable.
5667                  *
5668                  * So write it again.
5669                  */
5670                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5671         }
5672
5673         intel_crtc->lowfreq_avail = false;
5674         if (intel_crtc->pch_pll) {
5675                 if (is_lvds && has_reduced_clock && i915_powersave) {
5676                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5677                         intel_crtc->lowfreq_avail = true;
5678                 } else {
5679                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5680                 }
5681         }
5682
5683         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5684
5685         /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5686          * ironlake_check_fdi_lanes. */
5687         intel_crtc->fdi_lanes = 0;
5688         if (intel_crtc->config.has_pch_encoder)
5689                 ironlake_fdi_set_m_n(crtc);
5690
5691         fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5692
5693         ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5694
5695         intel_wait_for_vblank(dev, pipe);
5696
5697         /* Set up the display plane register */
5698         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5699         POSTING_READ(DSPCNTR(plane));
5700
5701         ret = intel_pipe_set_base(crtc, x, y, fb);
5702
5703         intel_update_watermarks(dev);
5704
5705         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5706
5707         return fdi_config_ok ? ret : -EINVAL;
5708 }
5709
5710 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5711                                      struct intel_crtc_config *pipe_config)
5712 {
5713         struct drm_device *dev = crtc->base.dev;
5714         struct drm_i915_private *dev_priv = dev->dev_private;
5715         uint32_t tmp;
5716
5717         tmp = I915_READ(PIPECONF(crtc->pipe));
5718         if (!(tmp & PIPECONF_ENABLE))
5719                 return false;
5720
5721         if (I915_READ(TRANSCONF(crtc->pipe)) & TRANS_ENABLE)
5722                 pipe_config->has_pch_encoder = true;
5723
5724         return true;
5725 }
5726
5727 static void haswell_modeset_global_resources(struct drm_device *dev)
5728 {
5729         struct drm_i915_private *dev_priv = dev->dev_private;
5730         bool enable = false;
5731         struct intel_crtc *crtc;
5732         struct intel_encoder *encoder;
5733
5734         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5735                 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5736                         enable = true;
5737                 /* XXX: Should check for edp transcoder here, but thanks to init
5738                  * sequence that's not yet available. Just in case desktop eDP
5739                  * on PORT D is possible on haswell, too. */
5740         }
5741
5742         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5743                             base.head) {
5744                 if (encoder->type != INTEL_OUTPUT_EDP &&
5745                     encoder->connectors_active)
5746                         enable = true;
5747         }
5748
5749         /* Even the eDP panel fitter is outside the always-on well. */
5750         if (dev_priv->pch_pf_size)
5751                 enable = true;
5752
5753         intel_set_power_well(dev, enable);
5754 }
5755
5756 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5757                                  int x, int y,
5758                                  struct drm_framebuffer *fb)
5759 {
5760         struct drm_device *dev = crtc->dev;
5761         struct drm_i915_private *dev_priv = dev->dev_private;
5762         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5763         struct drm_display_mode *adjusted_mode =
5764                 &intel_crtc->config.adjusted_mode;
5765         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5766         int pipe = intel_crtc->pipe;
5767         int plane = intel_crtc->plane;
5768         int num_connectors = 0;
5769         bool is_cpu_edp = false;
5770         struct intel_encoder *encoder;
5771         int ret;
5772         bool dither;
5773
5774         for_each_encoder_on_crtc(dev, crtc, encoder) {
5775                 switch (encoder->type) {
5776                 case INTEL_OUTPUT_EDP:
5777                         if (!intel_encoder_is_pch_edp(&encoder->base))
5778                                 is_cpu_edp = true;
5779                         break;
5780                 }
5781
5782                 num_connectors++;
5783         }
5784
5785         if (is_cpu_edp)
5786                 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5787         else
5788                 intel_crtc->cpu_transcoder = pipe;
5789
5790         /* We are not sure yet this won't happen. */
5791         WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5792              INTEL_PCH_TYPE(dev));
5793
5794         WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5795              num_connectors, pipe_name(pipe));
5796
5797         WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
5798                 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5799
5800         WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5801
5802         if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5803                 return -EINVAL;
5804
5805         /* Ensure that the cursor is valid for the new mode before changing... */
5806         intel_crtc_update_cursor(crtc, true);
5807
5808         /* determine panel color depth */
5809         dither = intel_crtc->config.dither;
5810
5811         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5812         drm_mode_debug_printmodeline(mode);
5813
5814         if (intel_crtc->config.has_dp_encoder)
5815                 intel_dp_set_m_n(intel_crtc);
5816
5817         intel_crtc->lowfreq_avail = false;
5818
5819         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5820
5821         if (intel_crtc->config.has_pch_encoder)
5822                 ironlake_fdi_set_m_n(crtc);
5823
5824         haswell_set_pipeconf(crtc, adjusted_mode, dither);
5825
5826         intel_set_pipe_csc(crtc);
5827
5828         /* Set up the display plane register */
5829         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
5830         POSTING_READ(DSPCNTR(plane));
5831
5832         ret = intel_pipe_set_base(crtc, x, y, fb);
5833
5834         intel_update_watermarks(dev);
5835
5836         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5837
5838         return ret;
5839 }
5840
5841 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5842                                     struct intel_crtc_config *pipe_config)
5843 {
5844         struct drm_device *dev = crtc->base.dev;
5845         struct drm_i915_private *dev_priv = dev->dev_private;
5846         uint32_t tmp;
5847
5848         tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
5849         if (!(tmp & PIPECONF_ENABLE))
5850                 return false;
5851
5852         /*
5853          * aswell has only FDI/PCH transcoder A. It is which is connected to
5854          * DDI E. So just check whether this pipe is wired to DDI E and whether
5855          * the PCH transcoder is on.
5856          */
5857         tmp = I915_READ(TRANS_DDI_FUNC_CTL(crtc->pipe));
5858         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
5859             I915_READ(TRANSCONF(PIPE_A)) & TRANS_ENABLE)
5860                 pipe_config->has_pch_encoder = true;
5861
5862
5863         return true;
5864 }
5865
5866 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5867                                int x, int y,
5868                                struct drm_framebuffer *fb)
5869 {
5870         struct drm_device *dev = crtc->dev;
5871         struct drm_i915_private *dev_priv = dev->dev_private;
5872         struct drm_encoder_helper_funcs *encoder_funcs;
5873         struct intel_encoder *encoder;
5874         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5875         struct drm_display_mode *adjusted_mode =
5876                 &intel_crtc->config.adjusted_mode;
5877         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5878         int pipe = intel_crtc->pipe;
5879         int ret;
5880
5881         drm_vblank_pre_modeset(dev, pipe);
5882
5883         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
5884
5885         drm_vblank_post_modeset(dev, pipe);
5886
5887         if (ret != 0)
5888                 return ret;
5889
5890         for_each_encoder_on_crtc(dev, crtc, encoder) {
5891                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5892                         encoder->base.base.id,
5893                         drm_get_encoder_name(&encoder->base),
5894                         mode->base.id, mode->name);
5895                 if (encoder->mode_set) {
5896                         encoder->mode_set(encoder);
5897                 } else {
5898                         encoder_funcs = encoder->base.helper_private;
5899                         encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5900                 }
5901         }
5902
5903         return 0;
5904 }
5905
5906 static bool intel_eld_uptodate(struct drm_connector *connector,
5907                                int reg_eldv, uint32_t bits_eldv,
5908                                int reg_elda, uint32_t bits_elda,
5909                                int reg_edid)
5910 {
5911         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5912         uint8_t *eld = connector->eld;
5913         uint32_t i;
5914
5915         i = I915_READ(reg_eldv);
5916         i &= bits_eldv;
5917
5918         if (!eld[0])
5919                 return !i;
5920
5921         if (!i)
5922                 return false;
5923
5924         i = I915_READ(reg_elda);
5925         i &= ~bits_elda;
5926         I915_WRITE(reg_elda, i);
5927
5928         for (i = 0; i < eld[2]; i++)
5929                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5930                         return false;
5931
5932         return true;
5933 }
5934
5935 static void g4x_write_eld(struct drm_connector *connector,
5936                           struct drm_crtc *crtc)
5937 {
5938         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5939         uint8_t *eld = connector->eld;
5940         uint32_t eldv;
5941         uint32_t len;
5942         uint32_t i;
5943
5944         i = I915_READ(G4X_AUD_VID_DID);
5945
5946         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5947                 eldv = G4X_ELDV_DEVCL_DEVBLC;
5948         else
5949                 eldv = G4X_ELDV_DEVCTG;
5950
5951         if (intel_eld_uptodate(connector,
5952                                G4X_AUD_CNTL_ST, eldv,
5953                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5954                                G4X_HDMIW_HDMIEDID))
5955                 return;
5956
5957         i = I915_READ(G4X_AUD_CNTL_ST);
5958         i &= ~(eldv | G4X_ELD_ADDR);
5959         len = (i >> 9) & 0x1f;          /* ELD buffer size */
5960         I915_WRITE(G4X_AUD_CNTL_ST, i);
5961
5962         if (!eld[0])
5963                 return;
5964
5965         len = min_t(uint8_t, eld[2], len);
5966         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5967         for (i = 0; i < len; i++)
5968                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5969
5970         i = I915_READ(G4X_AUD_CNTL_ST);
5971         i |= eldv;
5972         I915_WRITE(G4X_AUD_CNTL_ST, i);
5973 }
5974
5975 static void haswell_write_eld(struct drm_connector *connector,
5976                                      struct drm_crtc *crtc)
5977 {
5978         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5979         uint8_t *eld = connector->eld;
5980         struct drm_device *dev = crtc->dev;
5981         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5982         uint32_t eldv;
5983         uint32_t i;
5984         int len;
5985         int pipe = to_intel_crtc(crtc)->pipe;
5986         int tmp;
5987
5988         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5989         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5990         int aud_config = HSW_AUD_CFG(pipe);
5991         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5992
5993
5994         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5995
5996         /* Audio output enable */
5997         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5998         tmp = I915_READ(aud_cntrl_st2);
5999         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6000         I915_WRITE(aud_cntrl_st2, tmp);
6001
6002         /* Wait for 1 vertical blank */
6003         intel_wait_for_vblank(dev, pipe);
6004
6005         /* Set ELD valid state */
6006         tmp = I915_READ(aud_cntrl_st2);
6007         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6008         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6009         I915_WRITE(aud_cntrl_st2, tmp);
6010         tmp = I915_READ(aud_cntrl_st2);
6011         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6012
6013         /* Enable HDMI mode */
6014         tmp = I915_READ(aud_config);
6015         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6016         /* clear N_programing_enable and N_value_index */
6017         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6018         I915_WRITE(aud_config, tmp);
6019
6020         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6021
6022         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6023         intel_crtc->eld_vld = true;
6024
6025         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6026                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6027                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6028                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6029         } else
6030                 I915_WRITE(aud_config, 0);
6031
6032         if (intel_eld_uptodate(connector,
6033                                aud_cntrl_st2, eldv,
6034                                aud_cntl_st, IBX_ELD_ADDRESS,
6035                                hdmiw_hdmiedid))
6036                 return;
6037
6038         i = I915_READ(aud_cntrl_st2);
6039         i &= ~eldv;
6040         I915_WRITE(aud_cntrl_st2, i);
6041
6042         if (!eld[0])
6043                 return;
6044
6045         i = I915_READ(aud_cntl_st);
6046         i &= ~IBX_ELD_ADDRESS;
6047         I915_WRITE(aud_cntl_st, i);
6048         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6049         DRM_DEBUG_DRIVER("port num:%d\n", i);
6050
6051         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6052         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6053         for (i = 0; i < len; i++)
6054                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6055
6056         i = I915_READ(aud_cntrl_st2);
6057         i |= eldv;
6058         I915_WRITE(aud_cntrl_st2, i);
6059
6060 }
6061
6062 static void ironlake_write_eld(struct drm_connector *connector,
6063                                      struct drm_crtc *crtc)
6064 {
6065         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6066         uint8_t *eld = connector->eld;
6067         uint32_t eldv;
6068         uint32_t i;
6069         int len;
6070         int hdmiw_hdmiedid;
6071         int aud_config;
6072         int aud_cntl_st;
6073         int aud_cntrl_st2;
6074         int pipe = to_intel_crtc(crtc)->pipe;
6075
6076         if (HAS_PCH_IBX(connector->dev)) {
6077                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6078                 aud_config = IBX_AUD_CFG(pipe);
6079                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6080                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6081         } else {
6082                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6083                 aud_config = CPT_AUD_CFG(pipe);
6084                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6085                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6086         }
6087
6088         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6089
6090         i = I915_READ(aud_cntl_st);
6091         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6092         if (!i) {
6093                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6094                 /* operate blindly on all ports */
6095                 eldv = IBX_ELD_VALIDB;
6096                 eldv |= IBX_ELD_VALIDB << 4;
6097                 eldv |= IBX_ELD_VALIDB << 8;
6098         } else {
6099                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6100                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6101         }
6102
6103         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6104                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6105                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6106                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6107         } else
6108                 I915_WRITE(aud_config, 0);
6109
6110         if (intel_eld_uptodate(connector,
6111                                aud_cntrl_st2, eldv,
6112                                aud_cntl_st, IBX_ELD_ADDRESS,
6113                                hdmiw_hdmiedid))
6114                 return;
6115
6116         i = I915_READ(aud_cntrl_st2);
6117         i &= ~eldv;
6118         I915_WRITE(aud_cntrl_st2, i);
6119
6120         if (!eld[0])
6121                 return;
6122
6123         i = I915_READ(aud_cntl_st);
6124         i &= ~IBX_ELD_ADDRESS;
6125         I915_WRITE(aud_cntl_st, i);
6126
6127         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6128         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6129         for (i = 0; i < len; i++)
6130                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6131
6132         i = I915_READ(aud_cntrl_st2);
6133         i |= eldv;
6134         I915_WRITE(aud_cntrl_st2, i);
6135 }
6136
6137 void intel_write_eld(struct drm_encoder *encoder,
6138                      struct drm_display_mode *mode)
6139 {
6140         struct drm_crtc *crtc = encoder->crtc;
6141         struct drm_connector *connector;
6142         struct drm_device *dev = encoder->dev;
6143         struct drm_i915_private *dev_priv = dev->dev_private;
6144
6145         connector = drm_select_eld(encoder, mode);
6146         if (!connector)
6147                 return;
6148
6149         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6150                          connector->base.id,
6151                          drm_get_connector_name(connector),
6152                          connector->encoder->base.id,
6153                          drm_get_encoder_name(connector->encoder));
6154
6155         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6156
6157         if (dev_priv->display.write_eld)
6158                 dev_priv->display.write_eld(connector, crtc);
6159 }
6160
6161 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6162 void intel_crtc_load_lut(struct drm_crtc *crtc)
6163 {
6164         struct drm_device *dev = crtc->dev;
6165         struct drm_i915_private *dev_priv = dev->dev_private;
6166         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6167         int palreg = PALETTE(intel_crtc->pipe);
6168         int i;
6169
6170         /* The clocks have to be on to load the palette. */
6171         if (!crtc->enabled || !intel_crtc->active)
6172                 return;
6173
6174         /* use legacy palette for Ironlake */
6175         if (HAS_PCH_SPLIT(dev))
6176                 palreg = LGC_PALETTE(intel_crtc->pipe);
6177
6178         for (i = 0; i < 256; i++) {
6179                 I915_WRITE(palreg + 4 * i,
6180                            (intel_crtc->lut_r[i] << 16) |
6181                            (intel_crtc->lut_g[i] << 8) |
6182                            intel_crtc->lut_b[i]);
6183         }
6184 }
6185
6186 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6187 {
6188         struct drm_device *dev = crtc->dev;
6189         struct drm_i915_private *dev_priv = dev->dev_private;
6190         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6191         bool visible = base != 0;
6192         u32 cntl;
6193
6194         if (intel_crtc->cursor_visible == visible)
6195                 return;
6196
6197         cntl = I915_READ(_CURACNTR);
6198         if (visible) {
6199                 /* On these chipsets we can only modify the base whilst
6200                  * the cursor is disabled.
6201                  */
6202                 I915_WRITE(_CURABASE, base);
6203
6204                 cntl &= ~(CURSOR_FORMAT_MASK);
6205                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6206                 cntl |= CURSOR_ENABLE |
6207                         CURSOR_GAMMA_ENABLE |
6208                         CURSOR_FORMAT_ARGB;
6209         } else
6210                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6211         I915_WRITE(_CURACNTR, cntl);
6212
6213         intel_crtc->cursor_visible = visible;
6214 }
6215
6216 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6217 {
6218         struct drm_device *dev = crtc->dev;
6219         struct drm_i915_private *dev_priv = dev->dev_private;
6220         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6221         int pipe = intel_crtc->pipe;
6222         bool visible = base != 0;
6223
6224         if (intel_crtc->cursor_visible != visible) {
6225                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6226                 if (base) {
6227                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6228                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6229                         cntl |= pipe << 28; /* Connect to correct pipe */
6230                 } else {
6231                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6232                         cntl |= CURSOR_MODE_DISABLE;
6233                 }
6234                 I915_WRITE(CURCNTR(pipe), cntl);
6235
6236                 intel_crtc->cursor_visible = visible;
6237         }
6238         /* and commit changes on next vblank */
6239         I915_WRITE(CURBASE(pipe), base);
6240 }
6241
6242 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6243 {
6244         struct drm_device *dev = crtc->dev;
6245         struct drm_i915_private *dev_priv = dev->dev_private;
6246         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6247         int pipe = intel_crtc->pipe;
6248         bool visible = base != 0;
6249
6250         if (intel_crtc->cursor_visible != visible) {
6251                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6252                 if (base) {
6253                         cntl &= ~CURSOR_MODE;
6254                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6255                 } else {
6256                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6257                         cntl |= CURSOR_MODE_DISABLE;
6258                 }
6259                 if (IS_HASWELL(dev))
6260                         cntl |= CURSOR_PIPE_CSC_ENABLE;
6261                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6262
6263                 intel_crtc->cursor_visible = visible;
6264         }
6265         /* and commit changes on next vblank */
6266         I915_WRITE(CURBASE_IVB(pipe), base);
6267 }
6268
6269 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6270 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6271                                      bool on)
6272 {
6273         struct drm_device *dev = crtc->dev;
6274         struct drm_i915_private *dev_priv = dev->dev_private;
6275         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6276         int pipe = intel_crtc->pipe;
6277         int x = intel_crtc->cursor_x;
6278         int y = intel_crtc->cursor_y;
6279         u32 base, pos;
6280         bool visible;
6281
6282         pos = 0;
6283
6284         if (on && crtc->enabled && crtc->fb) {
6285                 base = intel_crtc->cursor_addr;
6286                 if (x > (int) crtc->fb->width)
6287                         base = 0;
6288
6289                 if (y > (int) crtc->fb->height)
6290                         base = 0;
6291         } else
6292                 base = 0;
6293
6294         if (x < 0) {
6295                 if (x + intel_crtc->cursor_width < 0)
6296                         base = 0;
6297
6298                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6299                 x = -x;
6300         }
6301         pos |= x << CURSOR_X_SHIFT;
6302
6303         if (y < 0) {
6304                 if (y + intel_crtc->cursor_height < 0)
6305                         base = 0;
6306
6307                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6308                 y = -y;
6309         }
6310         pos |= y << CURSOR_Y_SHIFT;
6311
6312         visible = base != 0;
6313         if (!visible && !intel_crtc->cursor_visible)
6314                 return;
6315
6316         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6317                 I915_WRITE(CURPOS_IVB(pipe), pos);
6318                 ivb_update_cursor(crtc, base);
6319         } else {
6320                 I915_WRITE(CURPOS(pipe), pos);
6321                 if (IS_845G(dev) || IS_I865G(dev))
6322                         i845_update_cursor(crtc, base);
6323                 else
6324                         i9xx_update_cursor(crtc, base);
6325         }
6326 }
6327
6328 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6329                                  struct drm_file *file,
6330                                  uint32_t handle,
6331                                  uint32_t width, uint32_t height)
6332 {
6333         struct drm_device *dev = crtc->dev;
6334         struct drm_i915_private *dev_priv = dev->dev_private;
6335         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6336         struct drm_i915_gem_object *obj;
6337         uint32_t addr;
6338         int ret;
6339
6340         /* if we want to turn off the cursor ignore width and height */
6341         if (!handle) {
6342                 DRM_DEBUG_KMS("cursor off\n");
6343                 addr = 0;
6344                 obj = NULL;
6345                 mutex_lock(&dev->struct_mutex);
6346                 goto finish;
6347         }
6348
6349         /* Currently we only support 64x64 cursors */
6350         if (width != 64 || height != 64) {
6351                 DRM_ERROR("we currently only support 64x64 cursors\n");
6352                 return -EINVAL;
6353         }
6354
6355         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6356         if (&obj->base == NULL)
6357                 return -ENOENT;
6358
6359         if (obj->base.size < width * height * 4) {
6360                 DRM_ERROR("buffer is to small\n");
6361                 ret = -ENOMEM;
6362                 goto fail;
6363         }
6364
6365         /* we only need to pin inside GTT if cursor is non-phy */
6366         mutex_lock(&dev->struct_mutex);
6367         if (!dev_priv->info->cursor_needs_physical) {
6368                 unsigned alignment;
6369
6370                 if (obj->tiling_mode) {
6371                         DRM_ERROR("cursor cannot be tiled\n");
6372                         ret = -EINVAL;
6373                         goto fail_locked;
6374                 }
6375
6376                 /* Note that the w/a also requires 2 PTE of padding following
6377                  * the bo. We currently fill all unused PTE with the shadow
6378                  * page and so we should always have valid PTE following the
6379                  * cursor preventing the VT-d warning.
6380                  */
6381                 alignment = 0;
6382                 if (need_vtd_wa(dev))
6383                         alignment = 64*1024;
6384
6385                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6386                 if (ret) {
6387                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6388                         goto fail_locked;
6389                 }
6390
6391                 ret = i915_gem_object_put_fence(obj);
6392                 if (ret) {
6393                         DRM_ERROR("failed to release fence for cursor");
6394                         goto fail_unpin;
6395                 }
6396
6397                 addr = obj->gtt_offset;
6398         } else {
6399                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6400                 ret = i915_gem_attach_phys_object(dev, obj,
6401                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6402                                                   align);
6403                 if (ret) {
6404                         DRM_ERROR("failed to attach phys object\n");
6405                         goto fail_locked;
6406                 }
6407                 addr = obj->phys_obj->handle->busaddr;
6408         }
6409
6410         if (IS_GEN2(dev))
6411                 I915_WRITE(CURSIZE, (height << 12) | width);
6412
6413  finish:
6414         if (intel_crtc->cursor_bo) {
6415                 if (dev_priv->info->cursor_needs_physical) {
6416                         if (intel_crtc->cursor_bo != obj)
6417                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6418                 } else
6419                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6420                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6421         }
6422
6423         mutex_unlock(&dev->struct_mutex);
6424
6425         intel_crtc->cursor_addr = addr;
6426         intel_crtc->cursor_bo = obj;
6427         intel_crtc->cursor_width = width;
6428         intel_crtc->cursor_height = height;
6429
6430         intel_crtc_update_cursor(crtc, true);
6431
6432         return 0;
6433 fail_unpin:
6434         i915_gem_object_unpin(obj);
6435 fail_locked:
6436         mutex_unlock(&dev->struct_mutex);
6437 fail:
6438         drm_gem_object_unreference_unlocked(&obj->base);
6439         return ret;
6440 }
6441
6442 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6443 {
6444         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6445
6446         intel_crtc->cursor_x = x;
6447         intel_crtc->cursor_y = y;
6448
6449         intel_crtc_update_cursor(crtc, true);
6450
6451         return 0;
6452 }
6453
6454 /** Sets the color ramps on behalf of RandR */
6455 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6456                                  u16 blue, int regno)
6457 {
6458         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6459
6460         intel_crtc->lut_r[regno] = red >> 8;
6461         intel_crtc->lut_g[regno] = green >> 8;
6462         intel_crtc->lut_b[regno] = blue >> 8;
6463 }
6464
6465 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6466                              u16 *blue, int regno)
6467 {
6468         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6469
6470         *red = intel_crtc->lut_r[regno] << 8;
6471         *green = intel_crtc->lut_g[regno] << 8;
6472         *blue = intel_crtc->lut_b[regno] << 8;
6473 }
6474
6475 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6476                                  u16 *blue, uint32_t start, uint32_t size)
6477 {
6478         int end = (start + size > 256) ? 256 : start + size, i;
6479         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6480
6481         for (i = start; i < end; i++) {
6482                 intel_crtc->lut_r[i] = red[i] >> 8;
6483                 intel_crtc->lut_g[i] = green[i] >> 8;
6484                 intel_crtc->lut_b[i] = blue[i] >> 8;
6485         }
6486
6487         intel_crtc_load_lut(crtc);
6488 }
6489
6490 /* VESA 640x480x72Hz mode to set on the pipe */
6491 static struct drm_display_mode load_detect_mode = {
6492         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6493                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6494 };
6495
6496 static struct drm_framebuffer *
6497 intel_framebuffer_create(struct drm_device *dev,
6498                          struct drm_mode_fb_cmd2 *mode_cmd,
6499                          struct drm_i915_gem_object *obj)
6500 {
6501         struct intel_framebuffer *intel_fb;
6502         int ret;
6503
6504         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6505         if (!intel_fb) {
6506                 drm_gem_object_unreference_unlocked(&obj->base);
6507                 return ERR_PTR(-ENOMEM);
6508         }
6509
6510         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6511         if (ret) {
6512                 drm_gem_object_unreference_unlocked(&obj->base);
6513                 kfree(intel_fb);
6514                 return ERR_PTR(ret);
6515         }
6516
6517         return &intel_fb->base;
6518 }
6519
6520 static u32
6521 intel_framebuffer_pitch_for_width(int width, int bpp)
6522 {
6523         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6524         return ALIGN(pitch, 64);
6525 }
6526
6527 static u32
6528 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6529 {
6530         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6531         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6532 }
6533
6534 static struct drm_framebuffer *
6535 intel_framebuffer_create_for_mode(struct drm_device *dev,
6536                                   struct drm_display_mode *mode,
6537                                   int depth, int bpp)
6538 {
6539         struct drm_i915_gem_object *obj;
6540         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6541
6542         obj = i915_gem_alloc_object(dev,
6543                                     intel_framebuffer_size_for_mode(mode, bpp));
6544         if (obj == NULL)
6545                 return ERR_PTR(-ENOMEM);
6546
6547         mode_cmd.width = mode->hdisplay;
6548         mode_cmd.height = mode->vdisplay;
6549         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6550                                                                 bpp);
6551         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6552
6553         return intel_framebuffer_create(dev, &mode_cmd, obj);
6554 }
6555
6556 static struct drm_framebuffer *
6557 mode_fits_in_fbdev(struct drm_device *dev,
6558                    struct drm_display_mode *mode)
6559 {
6560         struct drm_i915_private *dev_priv = dev->dev_private;
6561         struct drm_i915_gem_object *obj;
6562         struct drm_framebuffer *fb;
6563
6564         if (dev_priv->fbdev == NULL)
6565                 return NULL;
6566
6567         obj = dev_priv->fbdev->ifb.obj;
6568         if (obj == NULL)
6569                 return NULL;
6570
6571         fb = &dev_priv->fbdev->ifb.base;
6572         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6573                                                                fb->bits_per_pixel))
6574                 return NULL;
6575
6576         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6577                 return NULL;
6578
6579         return fb;
6580 }
6581
6582 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6583                                 struct drm_display_mode *mode,
6584                                 struct intel_load_detect_pipe *old)
6585 {
6586         struct intel_crtc *intel_crtc;
6587         struct intel_encoder *intel_encoder =
6588                 intel_attached_encoder(connector);
6589         struct drm_crtc *possible_crtc;
6590         struct drm_encoder *encoder = &intel_encoder->base;
6591         struct drm_crtc *crtc = NULL;
6592         struct drm_device *dev = encoder->dev;
6593         struct drm_framebuffer *fb;
6594         int i = -1;
6595
6596         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6597                       connector->base.id, drm_get_connector_name(connector),
6598                       encoder->base.id, drm_get_encoder_name(encoder));
6599
6600         /*
6601          * Algorithm gets a little messy:
6602          *
6603          *   - if the connector already has an assigned crtc, use it (but make
6604          *     sure it's on first)
6605          *
6606          *   - try to find the first unused crtc that can drive this connector,
6607          *     and use that if we find one
6608          */
6609
6610         /* See if we already have a CRTC for this connector */
6611         if (encoder->crtc) {
6612                 crtc = encoder->crtc;
6613
6614                 mutex_lock(&crtc->mutex);
6615
6616                 old->dpms_mode = connector->dpms;
6617                 old->load_detect_temp = false;
6618
6619                 /* Make sure the crtc and connector are running */
6620                 if (connector->dpms != DRM_MODE_DPMS_ON)
6621                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6622
6623                 return true;
6624         }
6625
6626         /* Find an unused one (if possible) */
6627         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6628                 i++;
6629                 if (!(encoder->possible_crtcs & (1 << i)))
6630                         continue;
6631                 if (!possible_crtc->enabled) {
6632                         crtc = possible_crtc;
6633                         break;
6634                 }
6635         }
6636
6637         /*
6638          * If we didn't find an unused CRTC, don't use any.
6639          */
6640         if (!crtc) {
6641                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6642                 return false;
6643         }
6644
6645         mutex_lock(&crtc->mutex);
6646         intel_encoder->new_crtc = to_intel_crtc(crtc);
6647         to_intel_connector(connector)->new_encoder = intel_encoder;
6648
6649         intel_crtc = to_intel_crtc(crtc);
6650         old->dpms_mode = connector->dpms;
6651         old->load_detect_temp = true;
6652         old->release_fb = NULL;
6653
6654         if (!mode)
6655                 mode = &load_detect_mode;
6656
6657         /* We need a framebuffer large enough to accommodate all accesses
6658          * that the plane may generate whilst we perform load detection.
6659          * We can not rely on the fbcon either being present (we get called
6660          * during its initialisation to detect all boot displays, or it may
6661          * not even exist) or that it is large enough to satisfy the
6662          * requested mode.
6663          */
6664         fb = mode_fits_in_fbdev(dev, mode);
6665         if (fb == NULL) {
6666                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6667                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6668                 old->release_fb = fb;
6669         } else
6670                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6671         if (IS_ERR(fb)) {
6672                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6673                 mutex_unlock(&crtc->mutex);
6674                 return false;
6675         }
6676
6677         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6678                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6679                 if (old->release_fb)
6680                         old->release_fb->funcs->destroy(old->release_fb);
6681                 mutex_unlock(&crtc->mutex);
6682                 return false;
6683         }
6684
6685         /* let the connector get through one full cycle before testing */
6686         intel_wait_for_vblank(dev, intel_crtc->pipe);
6687         return true;
6688 }
6689
6690 void intel_release_load_detect_pipe(struct drm_connector *connector,
6691                                     struct intel_load_detect_pipe *old)
6692 {
6693         struct intel_encoder *intel_encoder =
6694                 intel_attached_encoder(connector);
6695         struct drm_encoder *encoder = &intel_encoder->base;
6696         struct drm_crtc *crtc = encoder->crtc;
6697
6698         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6699                       connector->base.id, drm_get_connector_name(connector),
6700                       encoder->base.id, drm_get_encoder_name(encoder));
6701
6702         if (old->load_detect_temp) {
6703                 to_intel_connector(connector)->new_encoder = NULL;
6704                 intel_encoder->new_crtc = NULL;
6705                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6706
6707                 if (old->release_fb) {
6708                         drm_framebuffer_unregister_private(old->release_fb);
6709                         drm_framebuffer_unreference(old->release_fb);
6710                 }
6711
6712                 mutex_unlock(&crtc->mutex);
6713                 return;
6714         }
6715
6716         /* Switch crtc and encoder back off if necessary */
6717         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6718                 connector->funcs->dpms(connector, old->dpms_mode);
6719
6720         mutex_unlock(&crtc->mutex);
6721 }
6722
6723 /* Returns the clock of the currently programmed mode of the given pipe. */
6724 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6725 {
6726         struct drm_i915_private *dev_priv = dev->dev_private;
6727         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6728         int pipe = intel_crtc->pipe;
6729         u32 dpll = I915_READ(DPLL(pipe));
6730         u32 fp;
6731         intel_clock_t clock;
6732
6733         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6734                 fp = I915_READ(FP0(pipe));
6735         else
6736                 fp = I915_READ(FP1(pipe));
6737
6738         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6739         if (IS_PINEVIEW(dev)) {
6740                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6741                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6742         } else {
6743                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6744                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6745         }
6746
6747         if (!IS_GEN2(dev)) {
6748                 if (IS_PINEVIEW(dev))
6749                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6750                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6751                 else
6752                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6753                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6754
6755                 switch (dpll & DPLL_MODE_MASK) {
6756                 case DPLLB_MODE_DAC_SERIAL:
6757                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6758                                 5 : 10;
6759                         break;
6760                 case DPLLB_MODE_LVDS:
6761                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6762                                 7 : 14;
6763                         break;
6764                 default:
6765                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6766                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6767                         return 0;
6768                 }
6769
6770                 /* XXX: Handle the 100Mhz refclk */
6771                 intel_clock(dev, 96000, &clock);
6772         } else {
6773                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6774
6775                 if (is_lvds) {
6776                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6777                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6778                         clock.p2 = 14;
6779
6780                         if ((dpll & PLL_REF_INPUT_MASK) ==
6781                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6782                                 /* XXX: might not be 66MHz */
6783                                 intel_clock(dev, 66000, &clock);
6784                         } else
6785                                 intel_clock(dev, 48000, &clock);
6786                 } else {
6787                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6788                                 clock.p1 = 2;
6789                         else {
6790                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6791                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6792                         }
6793                         if (dpll & PLL_P2_DIVIDE_BY_4)
6794                                 clock.p2 = 4;
6795                         else
6796                                 clock.p2 = 2;
6797
6798                         intel_clock(dev, 48000, &clock);
6799                 }
6800         }
6801
6802         /* XXX: It would be nice to validate the clocks, but we can't reuse
6803          * i830PllIsValid() because it relies on the xf86_config connector
6804          * configuration being accurate, which it isn't necessarily.
6805          */
6806
6807         return clock.dot;
6808 }
6809
6810 /** Returns the currently programmed mode of the given pipe. */
6811 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6812                                              struct drm_crtc *crtc)
6813 {
6814         struct drm_i915_private *dev_priv = dev->dev_private;
6815         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6816         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
6817         struct drm_display_mode *mode;
6818         int htot = I915_READ(HTOTAL(cpu_transcoder));
6819         int hsync = I915_READ(HSYNC(cpu_transcoder));
6820         int vtot = I915_READ(VTOTAL(cpu_transcoder));
6821         int vsync = I915_READ(VSYNC(cpu_transcoder));
6822
6823         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6824         if (!mode)
6825                 return NULL;
6826
6827         mode->clock = intel_crtc_clock_get(dev, crtc);
6828         mode->hdisplay = (htot & 0xffff) + 1;
6829         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6830         mode->hsync_start = (hsync & 0xffff) + 1;
6831         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6832         mode->vdisplay = (vtot & 0xffff) + 1;
6833         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6834         mode->vsync_start = (vsync & 0xffff) + 1;
6835         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6836
6837         drm_mode_set_name(mode);
6838
6839         return mode;
6840 }
6841
6842 static void intel_increase_pllclock(struct drm_crtc *crtc)
6843 {
6844         struct drm_device *dev = crtc->dev;
6845         drm_i915_private_t *dev_priv = dev->dev_private;
6846         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6847         int pipe = intel_crtc->pipe;
6848         int dpll_reg = DPLL(pipe);
6849         int dpll;
6850
6851         if (HAS_PCH_SPLIT(dev))
6852                 return;
6853
6854         if (!dev_priv->lvds_downclock_avail)
6855                 return;
6856
6857         dpll = I915_READ(dpll_reg);
6858         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6859                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6860
6861                 assert_panel_unlocked(dev_priv, pipe);
6862
6863                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6864                 I915_WRITE(dpll_reg, dpll);
6865                 intel_wait_for_vblank(dev, pipe);
6866
6867                 dpll = I915_READ(dpll_reg);
6868                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6869                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6870         }
6871 }
6872
6873 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6874 {
6875         struct drm_device *dev = crtc->dev;
6876         drm_i915_private_t *dev_priv = dev->dev_private;
6877         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6878
6879         if (HAS_PCH_SPLIT(dev))
6880                 return;
6881
6882         if (!dev_priv->lvds_downclock_avail)
6883                 return;
6884
6885         /*
6886          * Since this is called by a timer, we should never get here in
6887          * the manual case.
6888          */
6889         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6890                 int pipe = intel_crtc->pipe;
6891                 int dpll_reg = DPLL(pipe);
6892                 int dpll;
6893
6894                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6895
6896                 assert_panel_unlocked(dev_priv, pipe);
6897
6898                 dpll = I915_READ(dpll_reg);
6899                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6900                 I915_WRITE(dpll_reg, dpll);
6901                 intel_wait_for_vblank(dev, pipe);
6902                 dpll = I915_READ(dpll_reg);
6903                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6904                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6905         }
6906
6907 }
6908
6909 void intel_mark_busy(struct drm_device *dev)
6910 {
6911         i915_update_gfx_val(dev->dev_private);
6912 }
6913
6914 void intel_mark_idle(struct drm_device *dev)
6915 {
6916         struct drm_crtc *crtc;
6917
6918         if (!i915_powersave)
6919                 return;
6920
6921         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6922                 if (!crtc->fb)
6923                         continue;
6924
6925                 intel_decrease_pllclock(crtc);
6926         }
6927 }
6928
6929 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6930 {
6931         struct drm_device *dev = obj->base.dev;
6932         struct drm_crtc *crtc;
6933
6934         if (!i915_powersave)
6935                 return;
6936
6937         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6938                 if (!crtc->fb)
6939                         continue;
6940
6941                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6942                         intel_increase_pllclock(crtc);
6943         }
6944 }
6945
6946 static void intel_crtc_destroy(struct drm_crtc *crtc)
6947 {
6948         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6949         struct drm_device *dev = crtc->dev;
6950         struct intel_unpin_work *work;
6951         unsigned long flags;
6952
6953         spin_lock_irqsave(&dev->event_lock, flags);
6954         work = intel_crtc->unpin_work;
6955         intel_crtc->unpin_work = NULL;
6956         spin_unlock_irqrestore(&dev->event_lock, flags);
6957
6958         if (work) {
6959                 cancel_work_sync(&work->work);
6960                 kfree(work);
6961         }
6962
6963         drm_crtc_cleanup(crtc);
6964
6965         kfree(intel_crtc);
6966 }
6967
6968 static void intel_unpin_work_fn(struct work_struct *__work)
6969 {
6970         struct intel_unpin_work *work =
6971                 container_of(__work, struct intel_unpin_work, work);
6972         struct drm_device *dev = work->crtc->dev;
6973
6974         mutex_lock(&dev->struct_mutex);
6975         intel_unpin_fb_obj(work->old_fb_obj);
6976         drm_gem_object_unreference(&work->pending_flip_obj->base);
6977         drm_gem_object_unreference(&work->old_fb_obj->base);
6978
6979         intel_update_fbc(dev);
6980         mutex_unlock(&dev->struct_mutex);
6981
6982         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
6983         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
6984
6985         kfree(work);
6986 }
6987
6988 static void do_intel_finish_page_flip(struct drm_device *dev,
6989                                       struct drm_crtc *crtc)
6990 {
6991         drm_i915_private_t *dev_priv = dev->dev_private;
6992         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6993         struct intel_unpin_work *work;
6994         unsigned long flags;
6995
6996         /* Ignore early vblank irqs */
6997         if (intel_crtc == NULL)
6998                 return;
6999
7000         spin_lock_irqsave(&dev->event_lock, flags);
7001         work = intel_crtc->unpin_work;
7002
7003         /* Ensure we don't miss a work->pending update ... */
7004         smp_rmb();
7005
7006         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7007                 spin_unlock_irqrestore(&dev->event_lock, flags);
7008                 return;
7009         }
7010
7011         /* and that the unpin work is consistent wrt ->pending. */
7012         smp_rmb();
7013
7014         intel_crtc->unpin_work = NULL;
7015
7016         if (work->event)
7017                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7018
7019         drm_vblank_put(dev, intel_crtc->pipe);
7020
7021         spin_unlock_irqrestore(&dev->event_lock, flags);
7022
7023         wake_up_all(&dev_priv->pending_flip_queue);
7024
7025         queue_work(dev_priv->wq, &work->work);
7026
7027         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7028 }
7029
7030 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7031 {
7032         drm_i915_private_t *dev_priv = dev->dev_private;
7033         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7034
7035         do_intel_finish_page_flip(dev, crtc);
7036 }
7037
7038 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7039 {
7040         drm_i915_private_t *dev_priv = dev->dev_private;
7041         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7042
7043         do_intel_finish_page_flip(dev, crtc);
7044 }
7045
7046 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7047 {
7048         drm_i915_private_t *dev_priv = dev->dev_private;
7049         struct intel_crtc *intel_crtc =
7050                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7051         unsigned long flags;
7052
7053         /* NB: An MMIO update of the plane base pointer will also
7054          * generate a page-flip completion irq, i.e. every modeset
7055          * is also accompanied by a spurious intel_prepare_page_flip().
7056          */
7057         spin_lock_irqsave(&dev->event_lock, flags);
7058         if (intel_crtc->unpin_work)
7059                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7060         spin_unlock_irqrestore(&dev->event_lock, flags);
7061 }
7062
7063 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7064 {
7065         /* Ensure that the work item is consistent when activating it ... */
7066         smp_wmb();
7067         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7068         /* and that it is marked active as soon as the irq could fire. */
7069         smp_wmb();
7070 }
7071
7072 static int intel_gen2_queue_flip(struct drm_device *dev,
7073                                  struct drm_crtc *crtc,
7074                                  struct drm_framebuffer *fb,
7075                                  struct drm_i915_gem_object *obj)
7076 {
7077         struct drm_i915_private *dev_priv = dev->dev_private;
7078         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7079         u32 flip_mask;
7080         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7081         int ret;
7082
7083         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7084         if (ret)
7085                 goto err;
7086
7087         ret = intel_ring_begin(ring, 6);
7088         if (ret)
7089                 goto err_unpin;
7090
7091         /* Can't queue multiple flips, so wait for the previous
7092          * one to finish before executing the next.
7093          */
7094         if (intel_crtc->plane)
7095                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7096         else
7097                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7098         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7099         intel_ring_emit(ring, MI_NOOP);
7100         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7101                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7102         intel_ring_emit(ring, fb->pitches[0]);
7103         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7104         intel_ring_emit(ring, 0); /* aux display base address, unused */
7105
7106         intel_mark_page_flip_active(intel_crtc);
7107         intel_ring_advance(ring);
7108         return 0;
7109
7110 err_unpin:
7111         intel_unpin_fb_obj(obj);
7112 err:
7113         return ret;
7114 }
7115
7116 static int intel_gen3_queue_flip(struct drm_device *dev,
7117                                  struct drm_crtc *crtc,
7118                                  struct drm_framebuffer *fb,
7119                                  struct drm_i915_gem_object *obj)
7120 {
7121         struct drm_i915_private *dev_priv = dev->dev_private;
7122         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7123         u32 flip_mask;
7124         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7125         int ret;
7126
7127         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7128         if (ret)
7129                 goto err;
7130
7131         ret = intel_ring_begin(ring, 6);
7132         if (ret)
7133                 goto err_unpin;
7134
7135         if (intel_crtc->plane)
7136                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7137         else
7138                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7139         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7140         intel_ring_emit(ring, MI_NOOP);
7141         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7142                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7143         intel_ring_emit(ring, fb->pitches[0]);
7144         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7145         intel_ring_emit(ring, MI_NOOP);
7146
7147         intel_mark_page_flip_active(intel_crtc);
7148         intel_ring_advance(ring);
7149         return 0;
7150
7151 err_unpin:
7152         intel_unpin_fb_obj(obj);
7153 err:
7154         return ret;
7155 }
7156
7157 static int intel_gen4_queue_flip(struct drm_device *dev,
7158                                  struct drm_crtc *crtc,
7159                                  struct drm_framebuffer *fb,
7160                                  struct drm_i915_gem_object *obj)
7161 {
7162         struct drm_i915_private *dev_priv = dev->dev_private;
7163         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7164         uint32_t pf, pipesrc;
7165         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7166         int ret;
7167
7168         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7169         if (ret)
7170                 goto err;
7171
7172         ret = intel_ring_begin(ring, 4);
7173         if (ret)
7174                 goto err_unpin;
7175
7176         /* i965+ uses the linear or tiled offsets from the
7177          * Display Registers (which do not change across a page-flip)
7178          * so we need only reprogram the base address.
7179          */
7180         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7181                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7182         intel_ring_emit(ring, fb->pitches[0]);
7183         intel_ring_emit(ring,
7184                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7185                         obj->tiling_mode);
7186
7187         /* XXX Enabling the panel-fitter across page-flip is so far
7188          * untested on non-native modes, so ignore it for now.
7189          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7190          */
7191         pf = 0;
7192         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7193         intel_ring_emit(ring, pf | pipesrc);
7194
7195         intel_mark_page_flip_active(intel_crtc);
7196         intel_ring_advance(ring);
7197         return 0;
7198
7199 err_unpin:
7200         intel_unpin_fb_obj(obj);
7201 err:
7202         return ret;
7203 }
7204
7205 static int intel_gen6_queue_flip(struct drm_device *dev,
7206                                  struct drm_crtc *crtc,
7207                                  struct drm_framebuffer *fb,
7208                                  struct drm_i915_gem_object *obj)
7209 {
7210         struct drm_i915_private *dev_priv = dev->dev_private;
7211         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7212         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7213         uint32_t pf, pipesrc;
7214         int ret;
7215
7216         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7217         if (ret)
7218                 goto err;
7219
7220         ret = intel_ring_begin(ring, 4);
7221         if (ret)
7222                 goto err_unpin;
7223
7224         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7225                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7226         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7227         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7228
7229         /* Contrary to the suggestions in the documentation,
7230          * "Enable Panel Fitter" does not seem to be required when page
7231          * flipping with a non-native mode, and worse causes a normal
7232          * modeset to fail.
7233          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7234          */
7235         pf = 0;
7236         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7237         intel_ring_emit(ring, pf | pipesrc);
7238
7239         intel_mark_page_flip_active(intel_crtc);
7240         intel_ring_advance(ring);
7241         return 0;
7242
7243 err_unpin:
7244         intel_unpin_fb_obj(obj);
7245 err:
7246         return ret;
7247 }
7248
7249 /*
7250  * On gen7 we currently use the blit ring because (in early silicon at least)
7251  * the render ring doesn't give us interrpts for page flip completion, which
7252  * means clients will hang after the first flip is queued.  Fortunately the
7253  * blit ring generates interrupts properly, so use it instead.
7254  */
7255 static int intel_gen7_queue_flip(struct drm_device *dev,
7256                                  struct drm_crtc *crtc,
7257                                  struct drm_framebuffer *fb,
7258                                  struct drm_i915_gem_object *obj)
7259 {
7260         struct drm_i915_private *dev_priv = dev->dev_private;
7261         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7262         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7263         uint32_t plane_bit = 0;
7264         int ret;
7265
7266         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7267         if (ret)
7268                 goto err;
7269
7270         switch(intel_crtc->plane) {
7271         case PLANE_A:
7272                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7273                 break;
7274         case PLANE_B:
7275                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7276                 break;
7277         case PLANE_C:
7278                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7279                 break;
7280         default:
7281                 WARN_ONCE(1, "unknown plane in flip command\n");
7282                 ret = -ENODEV;
7283                 goto err_unpin;
7284         }
7285
7286         ret = intel_ring_begin(ring, 4);
7287         if (ret)
7288                 goto err_unpin;
7289
7290         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7291         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7292         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7293         intel_ring_emit(ring, (MI_NOOP));
7294
7295         intel_mark_page_flip_active(intel_crtc);
7296         intel_ring_advance(ring);
7297         return 0;
7298
7299 err_unpin:
7300         intel_unpin_fb_obj(obj);
7301 err:
7302         return ret;
7303 }
7304
7305 static int intel_default_queue_flip(struct drm_device *dev,
7306                                     struct drm_crtc *crtc,
7307                                     struct drm_framebuffer *fb,
7308                                     struct drm_i915_gem_object *obj)
7309 {
7310         return -ENODEV;
7311 }
7312
7313 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7314                                 struct drm_framebuffer *fb,
7315                                 struct drm_pending_vblank_event *event)
7316 {
7317         struct drm_device *dev = crtc->dev;
7318         struct drm_i915_private *dev_priv = dev->dev_private;
7319         struct drm_framebuffer *old_fb = crtc->fb;
7320         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7321         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7322         struct intel_unpin_work *work;
7323         unsigned long flags;
7324         int ret;
7325
7326         /* Can't change pixel format via MI display flips. */
7327         if (fb->pixel_format != crtc->fb->pixel_format)
7328                 return -EINVAL;
7329
7330         /*
7331          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7332          * Note that pitch changes could also affect these register.
7333          */
7334         if (INTEL_INFO(dev)->gen > 3 &&
7335             (fb->offsets[0] != crtc->fb->offsets[0] ||
7336              fb->pitches[0] != crtc->fb->pitches[0]))
7337                 return -EINVAL;
7338
7339         work = kzalloc(sizeof *work, GFP_KERNEL);
7340         if (work == NULL)
7341                 return -ENOMEM;
7342
7343         work->event = event;
7344         work->crtc = crtc;
7345         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7346         INIT_WORK(&work->work, intel_unpin_work_fn);
7347
7348         ret = drm_vblank_get(dev, intel_crtc->pipe);
7349         if (ret)
7350                 goto free_work;
7351
7352         /* We borrow the event spin lock for protecting unpin_work */
7353         spin_lock_irqsave(&dev->event_lock, flags);
7354         if (intel_crtc->unpin_work) {
7355                 spin_unlock_irqrestore(&dev->event_lock, flags);
7356                 kfree(work);
7357                 drm_vblank_put(dev, intel_crtc->pipe);
7358
7359                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7360                 return -EBUSY;
7361         }
7362         intel_crtc->unpin_work = work;
7363         spin_unlock_irqrestore(&dev->event_lock, flags);
7364
7365         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7366                 flush_workqueue(dev_priv->wq);
7367
7368         ret = i915_mutex_lock_interruptible(dev);
7369         if (ret)
7370                 goto cleanup;
7371
7372         /* Reference the objects for the scheduled work. */
7373         drm_gem_object_reference(&work->old_fb_obj->base);
7374         drm_gem_object_reference(&obj->base);
7375
7376         crtc->fb = fb;
7377
7378         work->pending_flip_obj = obj;
7379
7380         work->enable_stall_check = true;
7381
7382         atomic_inc(&intel_crtc->unpin_work_count);
7383         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7384
7385         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7386         if (ret)
7387                 goto cleanup_pending;
7388
7389         intel_disable_fbc(dev);
7390         intel_mark_fb_busy(obj);
7391         mutex_unlock(&dev->struct_mutex);
7392
7393         trace_i915_flip_request(intel_crtc->plane, obj);
7394
7395         return 0;
7396
7397 cleanup_pending:
7398         atomic_dec(&intel_crtc->unpin_work_count);
7399         crtc->fb = old_fb;
7400         drm_gem_object_unreference(&work->old_fb_obj->base);
7401         drm_gem_object_unreference(&obj->base);
7402         mutex_unlock(&dev->struct_mutex);
7403
7404 cleanup:
7405         spin_lock_irqsave(&dev->event_lock, flags);
7406         intel_crtc->unpin_work = NULL;
7407         spin_unlock_irqrestore(&dev->event_lock, flags);
7408
7409         drm_vblank_put(dev, intel_crtc->pipe);
7410 free_work:
7411         kfree(work);
7412
7413         return ret;
7414 }
7415
7416 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7417         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7418         .load_lut = intel_crtc_load_lut,
7419 };
7420
7421 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7422 {
7423         struct intel_encoder *other_encoder;
7424         struct drm_crtc *crtc = &encoder->new_crtc->base;
7425
7426         if (WARN_ON(!crtc))
7427                 return false;
7428
7429         list_for_each_entry(other_encoder,
7430                             &crtc->dev->mode_config.encoder_list,
7431                             base.head) {
7432
7433                 if (&other_encoder->new_crtc->base != crtc ||
7434                     encoder == other_encoder)
7435                         continue;
7436                 else
7437                         return true;
7438         }
7439
7440         return false;
7441 }
7442
7443 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7444                                   struct drm_crtc *crtc)
7445 {
7446         struct drm_device *dev;
7447         struct drm_crtc *tmp;
7448         int crtc_mask = 1;
7449
7450         WARN(!crtc, "checking null crtc?\n");
7451
7452         dev = crtc->dev;
7453
7454         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7455                 if (tmp == crtc)
7456                         break;
7457                 crtc_mask <<= 1;
7458         }
7459
7460         if (encoder->possible_crtcs & crtc_mask)
7461                 return true;
7462         return false;
7463 }
7464
7465 /**
7466  * intel_modeset_update_staged_output_state
7467  *
7468  * Updates the staged output configuration state, e.g. after we've read out the
7469  * current hw state.
7470  */
7471 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7472 {
7473         struct intel_encoder *encoder;
7474         struct intel_connector *connector;
7475
7476         list_for_each_entry(connector, &dev->mode_config.connector_list,
7477                             base.head) {
7478                 connector->new_encoder =
7479                         to_intel_encoder(connector->base.encoder);
7480         }
7481
7482         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7483                             base.head) {
7484                 encoder->new_crtc =
7485                         to_intel_crtc(encoder->base.crtc);
7486         }
7487 }
7488
7489 /**
7490  * intel_modeset_commit_output_state
7491  *
7492  * This function copies the stage display pipe configuration to the real one.
7493  */
7494 static void intel_modeset_commit_output_state(struct drm_device *dev)
7495 {
7496         struct intel_encoder *encoder;
7497         struct intel_connector *connector;
7498
7499         list_for_each_entry(connector, &dev->mode_config.connector_list,
7500                             base.head) {
7501                 connector->base.encoder = &connector->new_encoder->base;
7502         }
7503
7504         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7505                             base.head) {
7506                 encoder->base.crtc = &encoder->new_crtc->base;
7507         }
7508 }
7509
7510 static int
7511 pipe_config_set_bpp(struct drm_crtc *crtc,
7512                     struct drm_framebuffer *fb,
7513                     struct intel_crtc_config *pipe_config)
7514 {
7515         struct drm_device *dev = crtc->dev;
7516         struct drm_connector *connector;
7517         int bpp;
7518
7519         switch (fb->pixel_format) {
7520         case DRM_FORMAT_C8:
7521                 bpp = 8*3; /* since we go through a colormap */
7522                 break;
7523         case DRM_FORMAT_XRGB1555:
7524         case DRM_FORMAT_ARGB1555:
7525                 /* checked in intel_framebuffer_init already */
7526                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7527                         return -EINVAL;
7528         case DRM_FORMAT_RGB565:
7529                 bpp = 6*3; /* min is 18bpp */
7530                 break;
7531         case DRM_FORMAT_XBGR8888:
7532         case DRM_FORMAT_ABGR8888:
7533                 /* checked in intel_framebuffer_init already */
7534                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7535                         return -EINVAL;
7536         case DRM_FORMAT_XRGB8888:
7537         case DRM_FORMAT_ARGB8888:
7538                 bpp = 8*3;
7539                 break;
7540         case DRM_FORMAT_XRGB2101010:
7541         case DRM_FORMAT_ARGB2101010:
7542         case DRM_FORMAT_XBGR2101010:
7543         case DRM_FORMAT_ABGR2101010:
7544                 /* checked in intel_framebuffer_init already */
7545                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7546                         return -EINVAL;
7547                 bpp = 10*3;
7548                 break;
7549         /* TODO: gen4+ supports 16 bpc floating point, too. */
7550         default:
7551                 DRM_DEBUG_KMS("unsupported depth\n");
7552                 return -EINVAL;
7553         }
7554
7555         pipe_config->pipe_bpp = bpp;
7556
7557         /* Clamp display bpp to EDID value */
7558         list_for_each_entry(connector, &dev->mode_config.connector_list,
7559                             head) {
7560                 if (connector->encoder && connector->encoder->crtc != crtc)
7561                         continue;
7562
7563                 /* Don't use an invalid EDID bpc value */
7564                 if (connector->display_info.bpc &&
7565                     connector->display_info.bpc * 3 < bpp) {
7566                         DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7567                                       bpp, connector->display_info.bpc*3);
7568                         pipe_config->pipe_bpp = connector->display_info.bpc*3;
7569                 }
7570         }
7571
7572         return bpp;
7573 }
7574
7575 static struct intel_crtc_config *
7576 intel_modeset_pipe_config(struct drm_crtc *crtc,
7577                           struct drm_framebuffer *fb,
7578                           struct drm_display_mode *mode)
7579 {
7580         struct drm_device *dev = crtc->dev;
7581         struct drm_encoder_helper_funcs *encoder_funcs;
7582         struct intel_encoder *encoder;
7583         struct intel_crtc_config *pipe_config;
7584         int plane_bpp;
7585
7586         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7587         if (!pipe_config)
7588                 return ERR_PTR(-ENOMEM);
7589
7590         drm_mode_copy(&pipe_config->adjusted_mode, mode);
7591         drm_mode_copy(&pipe_config->requested_mode, mode);
7592
7593         plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
7594         if (plane_bpp < 0)
7595                 goto fail;
7596
7597         /* Pass our mode to the connectors and the CRTC to give them a chance to
7598          * adjust it according to limitations or connector properties, and also
7599          * a chance to reject the mode entirely.
7600          */
7601         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7602                             base.head) {
7603
7604                 if (&encoder->new_crtc->base != crtc)
7605                         continue;
7606
7607                 if (encoder->compute_config) {
7608                         if (!(encoder->compute_config(encoder, pipe_config))) {
7609                                 DRM_DEBUG_KMS("Encoder config failure\n");
7610                                 goto fail;
7611                         }
7612
7613                         continue;
7614                 }
7615
7616                 encoder_funcs = encoder->base.helper_private;
7617                 if (!(encoder_funcs->mode_fixup(&encoder->base,
7618                                                 &pipe_config->requested_mode,
7619                                                 &pipe_config->adjusted_mode))) {
7620                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7621                         goto fail;
7622                 }
7623         }
7624
7625         if (!(intel_crtc_compute_config(crtc, pipe_config))) {
7626                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7627                 goto fail;
7628         }
7629         DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7630
7631         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7632         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7633                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7634
7635         return pipe_config;
7636 fail:
7637         kfree(pipe_config);
7638         return ERR_PTR(-EINVAL);
7639 }
7640
7641 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7642  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7643 static void
7644 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7645                              unsigned *prepare_pipes, unsigned *disable_pipes)
7646 {
7647         struct intel_crtc *intel_crtc;
7648         struct drm_device *dev = crtc->dev;
7649         struct intel_encoder *encoder;
7650         struct intel_connector *connector;
7651         struct drm_crtc *tmp_crtc;
7652
7653         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7654
7655         /* Check which crtcs have changed outputs connected to them, these need
7656          * to be part of the prepare_pipes mask. We don't (yet) support global
7657          * modeset across multiple crtcs, so modeset_pipes will only have one
7658          * bit set at most. */
7659         list_for_each_entry(connector, &dev->mode_config.connector_list,
7660                             base.head) {
7661                 if (connector->base.encoder == &connector->new_encoder->base)
7662                         continue;
7663
7664                 if (connector->base.encoder) {
7665                         tmp_crtc = connector->base.encoder->crtc;
7666
7667                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7668                 }
7669
7670                 if (connector->new_encoder)
7671                         *prepare_pipes |=
7672                                 1 << connector->new_encoder->new_crtc->pipe;
7673         }
7674
7675         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7676                             base.head) {
7677                 if (encoder->base.crtc == &encoder->new_crtc->base)
7678                         continue;
7679
7680                 if (encoder->base.crtc) {
7681                         tmp_crtc = encoder->base.crtc;
7682
7683                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7684                 }
7685
7686                 if (encoder->new_crtc)
7687                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7688         }
7689
7690         /* Check for any pipes that will be fully disabled ... */
7691         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7692                             base.head) {
7693                 bool used = false;
7694
7695                 /* Don't try to disable disabled crtcs. */
7696                 if (!intel_crtc->base.enabled)
7697                         continue;
7698
7699                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7700                                     base.head) {
7701                         if (encoder->new_crtc == intel_crtc)
7702                                 used = true;
7703                 }
7704
7705                 if (!used)
7706                         *disable_pipes |= 1 << intel_crtc->pipe;
7707         }
7708
7709
7710         /* set_mode is also used to update properties on life display pipes. */
7711         intel_crtc = to_intel_crtc(crtc);
7712         if (crtc->enabled)
7713                 *prepare_pipes |= 1 << intel_crtc->pipe;
7714
7715         /* We only support modeset on one single crtc, hence we need to do that
7716          * only for the passed in crtc iff we change anything else than just
7717          * disable crtcs.
7718          *
7719          * This is actually not true, to be fully compatible with the old crtc
7720          * helper we automatically disable _any_ output (i.e. doesn't need to be
7721          * connected to the crtc we're modesetting on) if it's disconnected.
7722          * Which is a rather nutty api (since changed the output configuration
7723          * without userspace's explicit request can lead to confusion), but
7724          * alas. Hence we currently need to modeset on all pipes we prepare. */
7725         if (*prepare_pipes)
7726                 *modeset_pipes = *prepare_pipes;
7727
7728         /* ... and mask these out. */
7729         *modeset_pipes &= ~(*disable_pipes);
7730         *prepare_pipes &= ~(*disable_pipes);
7731 }
7732
7733 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7734 {
7735         struct drm_encoder *encoder;
7736         struct drm_device *dev = crtc->dev;
7737
7738         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7739                 if (encoder->crtc == crtc)
7740                         return true;
7741
7742         return false;
7743 }
7744
7745 static void
7746 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7747 {
7748         struct intel_encoder *intel_encoder;
7749         struct intel_crtc *intel_crtc;
7750         struct drm_connector *connector;
7751
7752         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7753                             base.head) {
7754                 if (!intel_encoder->base.crtc)
7755                         continue;
7756
7757                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7758
7759                 if (prepare_pipes & (1 << intel_crtc->pipe))
7760                         intel_encoder->connectors_active = false;
7761         }
7762
7763         intel_modeset_commit_output_state(dev);
7764
7765         /* Update computed state. */
7766         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7767                             base.head) {
7768                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7769         }
7770
7771         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7772                 if (!connector->encoder || !connector->encoder->crtc)
7773                         continue;
7774
7775                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7776
7777                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7778                         struct drm_property *dpms_property =
7779                                 dev->mode_config.dpms_property;
7780
7781                         connector->dpms = DRM_MODE_DPMS_ON;
7782                         drm_object_property_set_value(&connector->base,
7783                                                          dpms_property,
7784                                                          DRM_MODE_DPMS_ON);
7785
7786                         intel_encoder = to_intel_encoder(connector->encoder);
7787                         intel_encoder->connectors_active = true;
7788                 }
7789         }
7790
7791 }
7792
7793 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7794         list_for_each_entry((intel_crtc), \
7795                             &(dev)->mode_config.crtc_list, \
7796                             base.head) \
7797                 if (mask & (1 <<(intel_crtc)->pipe)) \
7798
7799 static bool
7800 intel_pipe_config_compare(struct intel_crtc_config *current_config,
7801                           struct intel_crtc_config *pipe_config)
7802 {
7803         if (current_config->has_pch_encoder != pipe_config->has_pch_encoder) {
7804                 DRM_ERROR("mismatch in has_pch_encoder "
7805                           "(expected %i, found %i)\n",
7806                           current_config->has_pch_encoder,
7807                           pipe_config->has_pch_encoder);
7808                 return false;
7809         }
7810
7811         return true;
7812 }
7813
7814 void
7815 intel_modeset_check_state(struct drm_device *dev)
7816 {
7817         drm_i915_private_t *dev_priv = dev->dev_private;
7818         struct intel_crtc *crtc;
7819         struct intel_encoder *encoder;
7820         struct intel_connector *connector;
7821         struct intel_crtc_config pipe_config;
7822
7823         list_for_each_entry(connector, &dev->mode_config.connector_list,
7824                             base.head) {
7825                 /* This also checks the encoder/connector hw state with the
7826                  * ->get_hw_state callbacks. */
7827                 intel_connector_check_state(connector);
7828
7829                 WARN(&connector->new_encoder->base != connector->base.encoder,
7830                      "connector's staged encoder doesn't match current encoder\n");
7831         }
7832
7833         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7834                             base.head) {
7835                 bool enabled = false;
7836                 bool active = false;
7837                 enum pipe pipe, tracked_pipe;
7838
7839                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7840                               encoder->base.base.id,
7841                               drm_get_encoder_name(&encoder->base));
7842
7843                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7844                      "encoder's stage crtc doesn't match current crtc\n");
7845                 WARN(encoder->connectors_active && !encoder->base.crtc,
7846                      "encoder's active_connectors set, but no crtc\n");
7847
7848                 list_for_each_entry(connector, &dev->mode_config.connector_list,
7849                                     base.head) {
7850                         if (connector->base.encoder != &encoder->base)
7851                                 continue;
7852                         enabled = true;
7853                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7854                                 active = true;
7855                 }
7856                 WARN(!!encoder->base.crtc != enabled,
7857                      "encoder's enabled state mismatch "
7858                      "(expected %i, found %i)\n",
7859                      !!encoder->base.crtc, enabled);
7860                 WARN(active && !encoder->base.crtc,
7861                      "active encoder with no crtc\n");
7862
7863                 WARN(encoder->connectors_active != active,
7864                      "encoder's computed active state doesn't match tracked active state "
7865                      "(expected %i, found %i)\n", active, encoder->connectors_active);
7866
7867                 active = encoder->get_hw_state(encoder, &pipe);
7868                 WARN(active != encoder->connectors_active,
7869                      "encoder's hw state doesn't match sw tracking "
7870                      "(expected %i, found %i)\n",
7871                      encoder->connectors_active, active);
7872
7873                 if (!encoder->base.crtc)
7874                         continue;
7875
7876                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7877                 WARN(active && pipe != tracked_pipe,
7878                      "active encoder's pipe doesn't match"
7879                      "(expected %i, found %i)\n",
7880                      tracked_pipe, pipe);
7881
7882         }
7883
7884         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7885                             base.head) {
7886                 bool enabled = false;
7887                 bool active = false;
7888
7889                 DRM_DEBUG_KMS("[CRTC:%d]\n",
7890                               crtc->base.base.id);
7891
7892                 WARN(crtc->active && !crtc->base.enabled,
7893                      "active crtc, but not enabled in sw tracking\n");
7894
7895                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7896                                     base.head) {
7897                         if (encoder->base.crtc != &crtc->base)
7898                                 continue;
7899                         enabled = true;
7900                         if (encoder->connectors_active)
7901                                 active = true;
7902                 }
7903                 WARN(active != crtc->active,
7904                      "crtc's computed active state doesn't match tracked active state "
7905                      "(expected %i, found %i)\n", active, crtc->active);
7906                 WARN(enabled != crtc->base.enabled,
7907                      "crtc's computed enabled state doesn't match tracked enabled state "
7908                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7909
7910                 memset(&pipe_config, 0, sizeof(pipe_config));
7911                 active = dev_priv->display.get_pipe_config(crtc,
7912                                                            &pipe_config);
7913                 WARN(crtc->active != active,
7914                      "crtc active state doesn't match with hw state "
7915                      "(expected %i, found %i)\n", crtc->active, active);
7916
7917                 WARN(active &&
7918                      !intel_pipe_config_compare(&crtc->config, &pipe_config),
7919                      "pipe state doesn't match!\n");
7920         }
7921 }
7922
7923 static int __intel_set_mode(struct drm_crtc *crtc,
7924                             struct drm_display_mode *mode,
7925                             int x, int y, struct drm_framebuffer *fb)
7926 {
7927         struct drm_device *dev = crtc->dev;
7928         drm_i915_private_t *dev_priv = dev->dev_private;
7929         struct drm_display_mode *saved_mode, *saved_hwmode;
7930         struct intel_crtc_config *pipe_config = NULL;
7931         struct intel_crtc *intel_crtc;
7932         unsigned disable_pipes, prepare_pipes, modeset_pipes;
7933         int ret = 0;
7934
7935         saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
7936         if (!saved_mode)
7937                 return -ENOMEM;
7938         saved_hwmode = saved_mode + 1;
7939
7940         intel_modeset_affected_pipes(crtc, &modeset_pipes,
7941                                      &prepare_pipes, &disable_pipes);
7942
7943         *saved_hwmode = crtc->hwmode;
7944         *saved_mode = crtc->mode;
7945
7946         /* Hack: Because we don't (yet) support global modeset on multiple
7947          * crtcs, we don't keep track of the new mode for more than one crtc.
7948          * Hence simply check whether any bit is set in modeset_pipes in all the
7949          * pieces of code that are not yet converted to deal with mutliple crtcs
7950          * changing their mode at the same time. */
7951         if (modeset_pipes) {
7952                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
7953                 if (IS_ERR(pipe_config)) {
7954                         ret = PTR_ERR(pipe_config);
7955                         pipe_config = NULL;
7956
7957                         goto out;
7958                 }
7959         }
7960
7961         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7962                       modeset_pipes, prepare_pipes, disable_pipes);
7963
7964         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7965                 intel_crtc_disable(&intel_crtc->base);
7966
7967         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7968                 if (intel_crtc->base.enabled)
7969                         dev_priv->display.crtc_disable(&intel_crtc->base);
7970         }
7971
7972         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7973          * to set it here already despite that we pass it down the callchain.
7974          */
7975         if (modeset_pipes) {
7976                 crtc->mode = *mode;
7977                 /* mode_set/enable/disable functions rely on a correct pipe
7978                  * config. */
7979                 to_intel_crtc(crtc)->config = *pipe_config;
7980         }
7981
7982         /* Only after disabling all output pipelines that will be changed can we
7983          * update the the output configuration. */
7984         intel_modeset_update_state(dev, prepare_pipes);
7985
7986         if (dev_priv->display.modeset_global_resources)
7987                 dev_priv->display.modeset_global_resources(dev);
7988
7989         /* Set up the DPLL and any encoders state that needs to adjust or depend
7990          * on the DPLL.
7991          */
7992         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7993                 ret = intel_crtc_mode_set(&intel_crtc->base,
7994                                           x, y, fb);
7995                 if (ret)
7996                         goto done;
7997         }
7998
7999         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8000         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8001                 dev_priv->display.crtc_enable(&intel_crtc->base);
8002
8003         if (modeset_pipes) {
8004                 /* Store real post-adjustment hardware mode. */
8005                 crtc->hwmode = pipe_config->adjusted_mode;
8006
8007                 /* Calculate and store various constants which
8008                  * are later needed by vblank and swap-completion
8009                  * timestamping. They are derived from true hwmode.
8010                  */
8011                 drm_calc_timestamping_constants(crtc);
8012         }
8013
8014         /* FIXME: add subpixel order */
8015 done:
8016         if (ret && crtc->enabled) {
8017                 crtc->hwmode = *saved_hwmode;
8018                 crtc->mode = *saved_mode;
8019         }
8020
8021 out:
8022         kfree(pipe_config);
8023         kfree(saved_mode);
8024         return ret;
8025 }
8026
8027 int intel_set_mode(struct drm_crtc *crtc,
8028                      struct drm_display_mode *mode,
8029                      int x, int y, struct drm_framebuffer *fb)
8030 {
8031         int ret;
8032
8033         ret = __intel_set_mode(crtc, mode, x, y, fb);
8034
8035         if (ret == 0)
8036                 intel_modeset_check_state(crtc->dev);
8037
8038         return ret;
8039 }
8040
8041 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8042 {
8043         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8044 }
8045
8046 #undef for_each_intel_crtc_masked
8047
8048 static void intel_set_config_free(struct intel_set_config *config)
8049 {
8050         if (!config)
8051                 return;
8052
8053         kfree(config->save_connector_encoders);
8054         kfree(config->save_encoder_crtcs);
8055         kfree(config);
8056 }
8057
8058 static int intel_set_config_save_state(struct drm_device *dev,
8059                                        struct intel_set_config *config)
8060 {
8061         struct drm_encoder *encoder;
8062         struct drm_connector *connector;
8063         int count;
8064
8065         config->save_encoder_crtcs =
8066                 kcalloc(dev->mode_config.num_encoder,
8067                         sizeof(struct drm_crtc *), GFP_KERNEL);
8068         if (!config->save_encoder_crtcs)
8069                 return -ENOMEM;
8070
8071         config->save_connector_encoders =
8072                 kcalloc(dev->mode_config.num_connector,
8073                         sizeof(struct drm_encoder *), GFP_KERNEL);
8074         if (!config->save_connector_encoders)
8075                 return -ENOMEM;
8076
8077         /* Copy data. Note that driver private data is not affected.
8078          * Should anything bad happen only the expected state is
8079          * restored, not the drivers personal bookkeeping.
8080          */
8081         count = 0;
8082         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8083                 config->save_encoder_crtcs[count++] = encoder->crtc;
8084         }
8085
8086         count = 0;
8087         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8088                 config->save_connector_encoders[count++] = connector->encoder;
8089         }
8090
8091         return 0;
8092 }
8093
8094 static void intel_set_config_restore_state(struct drm_device *dev,
8095                                            struct intel_set_config *config)
8096 {
8097         struct intel_encoder *encoder;
8098         struct intel_connector *connector;
8099         int count;
8100
8101         count = 0;
8102         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8103                 encoder->new_crtc =
8104                         to_intel_crtc(config->save_encoder_crtcs[count++]);
8105         }
8106
8107         count = 0;
8108         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8109                 connector->new_encoder =
8110                         to_intel_encoder(config->save_connector_encoders[count++]);
8111         }
8112 }
8113
8114 static void
8115 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8116                                       struct intel_set_config *config)
8117 {
8118
8119         /* We should be able to check here if the fb has the same properties
8120          * and then just flip_or_move it */
8121         if (set->crtc->fb != set->fb) {
8122                 /* If we have no fb then treat it as a full mode set */
8123                 if (set->crtc->fb == NULL) {
8124                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8125                         config->mode_changed = true;
8126                 } else if (set->fb == NULL) {
8127                         config->mode_changed = true;
8128                 } else if (set->fb->pixel_format !=
8129                            set->crtc->fb->pixel_format) {
8130                         config->mode_changed = true;
8131                 } else
8132                         config->fb_changed = true;
8133         }
8134
8135         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8136                 config->fb_changed = true;
8137
8138         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8139                 DRM_DEBUG_KMS("modes are different, full mode set\n");
8140                 drm_mode_debug_printmodeline(&set->crtc->mode);
8141                 drm_mode_debug_printmodeline(set->mode);
8142                 config->mode_changed = true;
8143         }
8144 }
8145
8146 static int
8147 intel_modeset_stage_output_state(struct drm_device *dev,
8148                                  struct drm_mode_set *set,
8149                                  struct intel_set_config *config)
8150 {
8151         struct drm_crtc *new_crtc;
8152         struct intel_connector *connector;
8153         struct intel_encoder *encoder;
8154         int count, ro;
8155
8156         /* The upper layers ensure that we either disable a crtc or have a list
8157          * of connectors. For paranoia, double-check this. */
8158         WARN_ON(!set->fb && (set->num_connectors != 0));
8159         WARN_ON(set->fb && (set->num_connectors == 0));
8160
8161         count = 0;
8162         list_for_each_entry(connector, &dev->mode_config.connector_list,
8163                             base.head) {
8164                 /* Otherwise traverse passed in connector list and get encoders
8165                  * for them. */
8166                 for (ro = 0; ro < set->num_connectors; ro++) {
8167                         if (set->connectors[ro] == &connector->base) {
8168                                 connector->new_encoder = connector->encoder;
8169                                 break;
8170                         }
8171                 }
8172
8173                 /* If we disable the crtc, disable all its connectors. Also, if
8174                  * the connector is on the changing crtc but not on the new
8175                  * connector list, disable it. */
8176                 if ((!set->fb || ro == set->num_connectors) &&
8177                     connector->base.encoder &&
8178                     connector->base.encoder->crtc == set->crtc) {
8179                         connector->new_encoder = NULL;
8180
8181                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8182                                 connector->base.base.id,
8183                                 drm_get_connector_name(&connector->base));
8184                 }
8185
8186
8187                 if (&connector->new_encoder->base != connector->base.encoder) {
8188                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8189                         config->mode_changed = true;
8190                 }
8191         }
8192         /* connector->new_encoder is now updated for all connectors. */
8193
8194         /* Update crtc of enabled connectors. */
8195         count = 0;
8196         list_for_each_entry(connector, &dev->mode_config.connector_list,
8197                             base.head) {
8198                 if (!connector->new_encoder)
8199                         continue;
8200
8201                 new_crtc = connector->new_encoder->base.crtc;
8202
8203                 for (ro = 0; ro < set->num_connectors; ro++) {
8204                         if (set->connectors[ro] == &connector->base)
8205                                 new_crtc = set->crtc;
8206                 }
8207
8208                 /* Make sure the new CRTC will work with the encoder */
8209                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8210                                            new_crtc)) {
8211                         return -EINVAL;
8212                 }
8213                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8214
8215                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8216                         connector->base.base.id,
8217                         drm_get_connector_name(&connector->base),
8218                         new_crtc->base.id);
8219         }
8220
8221         /* Check for any encoders that needs to be disabled. */
8222         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8223                             base.head) {
8224                 list_for_each_entry(connector,
8225                                     &dev->mode_config.connector_list,
8226                                     base.head) {
8227                         if (connector->new_encoder == encoder) {
8228                                 WARN_ON(!connector->new_encoder->new_crtc);
8229
8230                                 goto next_encoder;
8231                         }
8232                 }
8233                 encoder->new_crtc = NULL;
8234 next_encoder:
8235                 /* Only now check for crtc changes so we don't miss encoders
8236                  * that will be disabled. */
8237                 if (&encoder->new_crtc->base != encoder->base.crtc) {
8238                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8239                         config->mode_changed = true;
8240                 }
8241         }
8242         /* Now we've also updated encoder->new_crtc for all encoders. */
8243
8244         return 0;
8245 }
8246
8247 static int intel_crtc_set_config(struct drm_mode_set *set)
8248 {
8249         struct drm_device *dev;
8250         struct drm_mode_set save_set;
8251         struct intel_set_config *config;
8252         int ret;
8253
8254         BUG_ON(!set);
8255         BUG_ON(!set->crtc);
8256         BUG_ON(!set->crtc->helper_private);
8257
8258         /* Enforce sane interface api - has been abused by the fb helper. */
8259         BUG_ON(!set->mode && set->fb);
8260         BUG_ON(set->fb && set->num_connectors == 0);
8261
8262         if (set->fb) {
8263                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8264                                 set->crtc->base.id, set->fb->base.id,
8265                                 (int)set->num_connectors, set->x, set->y);
8266         } else {
8267                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8268         }
8269
8270         dev = set->crtc->dev;
8271
8272         ret = -ENOMEM;
8273         config = kzalloc(sizeof(*config), GFP_KERNEL);
8274         if (!config)
8275                 goto out_config;
8276
8277         ret = intel_set_config_save_state(dev, config);
8278         if (ret)
8279                 goto out_config;
8280
8281         save_set.crtc = set->crtc;
8282         save_set.mode = &set->crtc->mode;
8283         save_set.x = set->crtc->x;
8284         save_set.y = set->crtc->y;
8285         save_set.fb = set->crtc->fb;
8286
8287         /* Compute whether we need a full modeset, only an fb base update or no
8288          * change at all. In the future we might also check whether only the
8289          * mode changed, e.g. for LVDS where we only change the panel fitter in
8290          * such cases. */
8291         intel_set_config_compute_mode_changes(set, config);
8292
8293         ret = intel_modeset_stage_output_state(dev, set, config);
8294         if (ret)
8295                 goto fail;
8296
8297         if (config->mode_changed) {
8298                 if (set->mode) {
8299                         DRM_DEBUG_KMS("attempting to set mode from"
8300                                         " userspace\n");
8301                         drm_mode_debug_printmodeline(set->mode);
8302                 }
8303
8304                 ret = intel_set_mode(set->crtc, set->mode,
8305                                      set->x, set->y, set->fb);
8306                 if (ret) {
8307                         DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8308                                   set->crtc->base.id, ret);
8309                         goto fail;
8310                 }
8311         } else if (config->fb_changed) {
8312                 intel_crtc_wait_for_pending_flips(set->crtc);
8313
8314                 ret = intel_pipe_set_base(set->crtc,
8315                                           set->x, set->y, set->fb);
8316         }
8317
8318         intel_set_config_free(config);
8319
8320         return 0;
8321
8322 fail:
8323         intel_set_config_restore_state(dev, config);
8324
8325         /* Try to restore the config */
8326         if (config->mode_changed &&
8327             intel_set_mode(save_set.crtc, save_set.mode,
8328                            save_set.x, save_set.y, save_set.fb))
8329                 DRM_ERROR("failed to restore config after modeset failure\n");
8330
8331 out_config:
8332         intel_set_config_free(config);
8333         return ret;
8334 }
8335
8336 static const struct drm_crtc_funcs intel_crtc_funcs = {
8337         .cursor_set = intel_crtc_cursor_set,
8338         .cursor_move = intel_crtc_cursor_move,
8339         .gamma_set = intel_crtc_gamma_set,
8340         .set_config = intel_crtc_set_config,
8341         .destroy = intel_crtc_destroy,
8342         .page_flip = intel_crtc_page_flip,
8343 };
8344
8345 static void intel_cpu_pll_init(struct drm_device *dev)
8346 {
8347         if (HAS_DDI(dev))
8348                 intel_ddi_pll_init(dev);
8349 }
8350
8351 static void intel_pch_pll_init(struct drm_device *dev)
8352 {
8353         drm_i915_private_t *dev_priv = dev->dev_private;
8354         int i;
8355
8356         if (dev_priv->num_pch_pll == 0) {
8357                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8358                 return;
8359         }
8360
8361         for (i = 0; i < dev_priv->num_pch_pll; i++) {
8362                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8363                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8364                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8365         }
8366 }
8367
8368 static void intel_crtc_init(struct drm_device *dev, int pipe)
8369 {
8370         drm_i915_private_t *dev_priv = dev->dev_private;
8371         struct intel_crtc *intel_crtc;
8372         int i;
8373
8374         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8375         if (intel_crtc == NULL)
8376                 return;
8377
8378         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8379
8380         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8381         for (i = 0; i < 256; i++) {
8382                 intel_crtc->lut_r[i] = i;
8383                 intel_crtc->lut_g[i] = i;
8384                 intel_crtc->lut_b[i] = i;
8385         }
8386
8387         /* Swap pipes & planes for FBC on pre-965 */
8388         intel_crtc->pipe = pipe;
8389         intel_crtc->plane = pipe;
8390         intel_crtc->cpu_transcoder = pipe;
8391         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8392                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8393                 intel_crtc->plane = !pipe;
8394         }
8395
8396         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8397                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8398         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8399         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8400
8401         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8402 }
8403
8404 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8405                                 struct drm_file *file)
8406 {
8407         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8408         struct drm_mode_object *drmmode_obj;
8409         struct intel_crtc *crtc;
8410
8411         if (!drm_core_check_feature(dev, DRIVER_MODESET))
8412                 return -ENODEV;
8413
8414         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8415                         DRM_MODE_OBJECT_CRTC);
8416
8417         if (!drmmode_obj) {
8418                 DRM_ERROR("no such CRTC id\n");
8419                 return -EINVAL;
8420         }
8421
8422         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8423         pipe_from_crtc_id->pipe = crtc->pipe;
8424
8425         return 0;
8426 }
8427
8428 static int intel_encoder_clones(struct intel_encoder *encoder)
8429 {
8430         struct drm_device *dev = encoder->base.dev;
8431         struct intel_encoder *source_encoder;
8432         int index_mask = 0;
8433         int entry = 0;
8434
8435         list_for_each_entry(source_encoder,
8436                             &dev->mode_config.encoder_list, base.head) {
8437
8438                 if (encoder == source_encoder)
8439                         index_mask |= (1 << entry);
8440
8441                 /* Intel hw has only one MUX where enocoders could be cloned. */
8442                 if (encoder->cloneable && source_encoder->cloneable)
8443                         index_mask |= (1 << entry);
8444
8445                 entry++;
8446         }
8447
8448         return index_mask;
8449 }
8450
8451 static bool has_edp_a(struct drm_device *dev)
8452 {
8453         struct drm_i915_private *dev_priv = dev->dev_private;
8454
8455         if (!IS_MOBILE(dev))
8456                 return false;
8457
8458         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8459                 return false;
8460
8461         if (IS_GEN5(dev) &&
8462             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8463                 return false;
8464
8465         return true;
8466 }
8467
8468 static void intel_setup_outputs(struct drm_device *dev)
8469 {
8470         struct drm_i915_private *dev_priv = dev->dev_private;
8471         struct intel_encoder *encoder;
8472         bool dpd_is_edp = false;
8473         bool has_lvds;
8474
8475         has_lvds = intel_lvds_init(dev);
8476         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8477                 /* disable the panel fitter on everything but LVDS */
8478                 I915_WRITE(PFIT_CONTROL, 0);
8479         }
8480
8481         if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
8482                 intel_crt_init(dev);
8483
8484         if (HAS_DDI(dev)) {
8485                 int found;
8486
8487                 /* Haswell uses DDI functions to detect digital outputs */
8488                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8489                 /* DDI A only supports eDP */
8490                 if (found)
8491                         intel_ddi_init(dev, PORT_A);
8492
8493                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8494                  * register */
8495                 found = I915_READ(SFUSE_STRAP);
8496
8497                 if (found & SFUSE_STRAP_DDIB_DETECTED)
8498                         intel_ddi_init(dev, PORT_B);
8499                 if (found & SFUSE_STRAP_DDIC_DETECTED)
8500                         intel_ddi_init(dev, PORT_C);
8501                 if (found & SFUSE_STRAP_DDID_DETECTED)
8502                         intel_ddi_init(dev, PORT_D);
8503         } else if (HAS_PCH_SPLIT(dev)) {
8504                 int found;
8505                 dpd_is_edp = intel_dpd_is_edp(dev);
8506
8507                 if (has_edp_a(dev))
8508                         intel_dp_init(dev, DP_A, PORT_A);
8509
8510                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
8511                         /* PCH SDVOB multiplex with HDMIB */
8512                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
8513                         if (!found)
8514                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
8515                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8516                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
8517                 }
8518
8519                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
8520                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
8521
8522                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
8523                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
8524
8525                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8526                         intel_dp_init(dev, PCH_DP_C, PORT_C);
8527
8528                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8529                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8530         } else if (IS_VALLEYVIEW(dev)) {
8531                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8532                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8533                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
8534
8535                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
8536                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8537                                         PORT_B);
8538                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8539                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
8540                 }
8541         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8542                 bool found = false;
8543
8544                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8545                         DRM_DEBUG_KMS("probing SDVOB\n");
8546                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
8547                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8548                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8549                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
8550                         }
8551
8552                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8553                                 DRM_DEBUG_KMS("probing DP_B\n");
8554                                 intel_dp_init(dev, DP_B, PORT_B);
8555                         }
8556                 }
8557
8558                 /* Before G4X SDVOC doesn't have its own detect register */
8559
8560                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8561                         DRM_DEBUG_KMS("probing SDVOC\n");
8562                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
8563                 }
8564
8565                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
8566
8567                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8568                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8569                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
8570                         }
8571                         if (SUPPORTS_INTEGRATED_DP(dev)) {
8572                                 DRM_DEBUG_KMS("probing DP_C\n");
8573                                 intel_dp_init(dev, DP_C, PORT_C);
8574                         }
8575                 }
8576
8577                 if (SUPPORTS_INTEGRATED_DP(dev) &&
8578                     (I915_READ(DP_D) & DP_DETECTED)) {
8579                         DRM_DEBUG_KMS("probing DP_D\n");
8580                         intel_dp_init(dev, DP_D, PORT_D);
8581                 }
8582         } else if (IS_GEN2(dev))
8583                 intel_dvo_init(dev);
8584
8585         if (SUPPORTS_TV(dev))
8586                 intel_tv_init(dev);
8587
8588         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8589                 encoder->base.possible_crtcs = encoder->crtc_mask;
8590                 encoder->base.possible_clones =
8591                         intel_encoder_clones(encoder);
8592         }
8593
8594         intel_init_pch_refclk(dev);
8595
8596         drm_helper_move_panel_connectors_to_head(dev);
8597 }
8598
8599 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8600 {
8601         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8602
8603         drm_framebuffer_cleanup(fb);
8604         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8605
8606         kfree(intel_fb);
8607 }
8608
8609 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8610                                                 struct drm_file *file,
8611                                                 unsigned int *handle)
8612 {
8613         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8614         struct drm_i915_gem_object *obj = intel_fb->obj;
8615
8616         return drm_gem_handle_create(file, &obj->base, handle);
8617 }
8618
8619 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8620         .destroy = intel_user_framebuffer_destroy,
8621         .create_handle = intel_user_framebuffer_create_handle,
8622 };
8623
8624 int intel_framebuffer_init(struct drm_device *dev,
8625                            struct intel_framebuffer *intel_fb,
8626                            struct drm_mode_fb_cmd2 *mode_cmd,
8627                            struct drm_i915_gem_object *obj)
8628 {
8629         int ret;
8630
8631         if (obj->tiling_mode == I915_TILING_Y) {
8632                 DRM_DEBUG("hardware does not support tiling Y\n");
8633                 return -EINVAL;
8634         }
8635
8636         if (mode_cmd->pitches[0] & 63) {
8637                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8638                           mode_cmd->pitches[0]);
8639                 return -EINVAL;
8640         }
8641
8642         /* FIXME <= Gen4 stride limits are bit unclear */
8643         if (mode_cmd->pitches[0] > 32768) {
8644                 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8645                           mode_cmd->pitches[0]);
8646                 return -EINVAL;
8647         }
8648
8649         if (obj->tiling_mode != I915_TILING_NONE &&
8650             mode_cmd->pitches[0] != obj->stride) {
8651                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8652                           mode_cmd->pitches[0], obj->stride);
8653                 return -EINVAL;
8654         }
8655
8656         /* Reject formats not supported by any plane early. */
8657         switch (mode_cmd->pixel_format) {
8658         case DRM_FORMAT_C8:
8659         case DRM_FORMAT_RGB565:
8660         case DRM_FORMAT_XRGB8888:
8661         case DRM_FORMAT_ARGB8888:
8662                 break;
8663         case DRM_FORMAT_XRGB1555:
8664         case DRM_FORMAT_ARGB1555:
8665                 if (INTEL_INFO(dev)->gen > 3) {
8666                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8667                         return -EINVAL;
8668                 }
8669                 break;
8670         case DRM_FORMAT_XBGR8888:
8671         case DRM_FORMAT_ABGR8888:
8672         case DRM_FORMAT_XRGB2101010:
8673         case DRM_FORMAT_ARGB2101010:
8674         case DRM_FORMAT_XBGR2101010:
8675         case DRM_FORMAT_ABGR2101010:
8676                 if (INTEL_INFO(dev)->gen < 4) {
8677                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8678                         return -EINVAL;
8679                 }
8680                 break;
8681         case DRM_FORMAT_YUYV:
8682         case DRM_FORMAT_UYVY:
8683         case DRM_FORMAT_YVYU:
8684         case DRM_FORMAT_VYUY:
8685                 if (INTEL_INFO(dev)->gen < 5) {
8686                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8687                         return -EINVAL;
8688                 }
8689                 break;
8690         default:
8691                 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8692                 return -EINVAL;
8693         }
8694
8695         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8696         if (mode_cmd->offsets[0] != 0)
8697                 return -EINVAL;
8698
8699         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8700         intel_fb->obj = obj;
8701
8702         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8703         if (ret) {
8704                 DRM_ERROR("framebuffer init failed %d\n", ret);
8705                 return ret;
8706         }
8707
8708         return 0;
8709 }
8710
8711 static struct drm_framebuffer *
8712 intel_user_framebuffer_create(struct drm_device *dev,
8713                               struct drm_file *filp,
8714                               struct drm_mode_fb_cmd2 *mode_cmd)
8715 {
8716         struct drm_i915_gem_object *obj;
8717
8718         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8719                                                 mode_cmd->handles[0]));
8720         if (&obj->base == NULL)
8721                 return ERR_PTR(-ENOENT);
8722
8723         return intel_framebuffer_create(dev, mode_cmd, obj);
8724 }
8725
8726 static const struct drm_mode_config_funcs intel_mode_funcs = {
8727         .fb_create = intel_user_framebuffer_create,
8728         .output_poll_changed = intel_fb_output_poll_changed,
8729 };
8730
8731 /* Set up chip specific display functions */
8732 static void intel_init_display(struct drm_device *dev)
8733 {
8734         struct drm_i915_private *dev_priv = dev->dev_private;
8735
8736         if (HAS_DDI(dev)) {
8737                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
8738                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8739                 dev_priv->display.crtc_enable = haswell_crtc_enable;
8740                 dev_priv->display.crtc_disable = haswell_crtc_disable;
8741                 dev_priv->display.off = haswell_crtc_off;
8742                 dev_priv->display.update_plane = ironlake_update_plane;
8743         } else if (HAS_PCH_SPLIT(dev)) {
8744                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
8745                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8746                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8747                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8748                 dev_priv->display.off = ironlake_crtc_off;
8749                 dev_priv->display.update_plane = ironlake_update_plane;
8750         } else {
8751                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
8752                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8753                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8754                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8755                 dev_priv->display.off = i9xx_crtc_off;
8756                 dev_priv->display.update_plane = i9xx_update_plane;
8757         }
8758
8759         /* Returns the core display clock speed */
8760         if (IS_VALLEYVIEW(dev))
8761                 dev_priv->display.get_display_clock_speed =
8762                         valleyview_get_display_clock_speed;
8763         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8764                 dev_priv->display.get_display_clock_speed =
8765                         i945_get_display_clock_speed;
8766         else if (IS_I915G(dev))
8767                 dev_priv->display.get_display_clock_speed =
8768                         i915_get_display_clock_speed;
8769         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8770                 dev_priv->display.get_display_clock_speed =
8771                         i9xx_misc_get_display_clock_speed;
8772         else if (IS_I915GM(dev))
8773                 dev_priv->display.get_display_clock_speed =
8774                         i915gm_get_display_clock_speed;
8775         else if (IS_I865G(dev))
8776                 dev_priv->display.get_display_clock_speed =
8777                         i865_get_display_clock_speed;
8778         else if (IS_I85X(dev))
8779                 dev_priv->display.get_display_clock_speed =
8780                         i855_get_display_clock_speed;
8781         else /* 852, 830 */
8782                 dev_priv->display.get_display_clock_speed =
8783                         i830_get_display_clock_speed;
8784
8785         if (HAS_PCH_SPLIT(dev)) {
8786                 if (IS_GEN5(dev)) {
8787                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8788                         dev_priv->display.write_eld = ironlake_write_eld;
8789                 } else if (IS_GEN6(dev)) {
8790                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8791                         dev_priv->display.write_eld = ironlake_write_eld;
8792                 } else if (IS_IVYBRIDGE(dev)) {
8793                         /* FIXME: detect B0+ stepping and use auto training */
8794                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8795                         dev_priv->display.write_eld = ironlake_write_eld;
8796                         dev_priv->display.modeset_global_resources =
8797                                 ivb_modeset_global_resources;
8798                 } else if (IS_HASWELL(dev)) {
8799                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8800                         dev_priv->display.write_eld = haswell_write_eld;
8801                         dev_priv->display.modeset_global_resources =
8802                                 haswell_modeset_global_resources;
8803                 }
8804         } else if (IS_G4X(dev)) {
8805                 dev_priv->display.write_eld = g4x_write_eld;
8806         }
8807
8808         /* Default just returns -ENODEV to indicate unsupported */
8809         dev_priv->display.queue_flip = intel_default_queue_flip;
8810
8811         switch (INTEL_INFO(dev)->gen) {
8812         case 2:
8813                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8814                 break;
8815
8816         case 3:
8817                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8818                 break;
8819
8820         case 4:
8821         case 5:
8822                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8823                 break;
8824
8825         case 6:
8826                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8827                 break;
8828         case 7:
8829                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8830                 break;
8831         }
8832 }
8833
8834 /*
8835  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8836  * resume, or other times.  This quirk makes sure that's the case for
8837  * affected systems.
8838  */
8839 static void quirk_pipea_force(struct drm_device *dev)
8840 {
8841         struct drm_i915_private *dev_priv = dev->dev_private;
8842
8843         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8844         DRM_INFO("applying pipe a force quirk\n");
8845 }
8846
8847 /*
8848  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8849  */
8850 static void quirk_ssc_force_disable(struct drm_device *dev)
8851 {
8852         struct drm_i915_private *dev_priv = dev->dev_private;
8853         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8854         DRM_INFO("applying lvds SSC disable quirk\n");
8855 }
8856
8857 /*
8858  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8859  * brightness value
8860  */
8861 static void quirk_invert_brightness(struct drm_device *dev)
8862 {
8863         struct drm_i915_private *dev_priv = dev->dev_private;
8864         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8865         DRM_INFO("applying inverted panel brightness quirk\n");
8866 }
8867
8868 struct intel_quirk {
8869         int device;
8870         int subsystem_vendor;
8871         int subsystem_device;
8872         void (*hook)(struct drm_device *dev);
8873 };
8874
8875 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8876 struct intel_dmi_quirk {
8877         void (*hook)(struct drm_device *dev);
8878         const struct dmi_system_id (*dmi_id_list)[];
8879 };
8880
8881 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8882 {
8883         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8884         return 1;
8885 }
8886
8887 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8888         {
8889                 .dmi_id_list = &(const struct dmi_system_id[]) {
8890                         {
8891                                 .callback = intel_dmi_reverse_brightness,
8892                                 .ident = "NCR Corporation",
8893                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8894                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
8895                                 },
8896                         },
8897                         { }  /* terminating entry */
8898                 },
8899                 .hook = quirk_invert_brightness,
8900         },
8901 };
8902
8903 static struct intel_quirk intel_quirks[] = {
8904         /* HP Mini needs pipe A force quirk (LP: #322104) */
8905         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8906
8907         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8908         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8909
8910         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8911         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8912
8913         /* 830/845 need to leave pipe A & dpll A up */
8914         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8915         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8916
8917         /* Lenovo U160 cannot use SSC on LVDS */
8918         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8919
8920         /* Sony Vaio Y cannot use SSC on LVDS */
8921         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8922
8923         /* Acer Aspire 5734Z must invert backlight brightness */
8924         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8925
8926         /* Acer/eMachines G725 */
8927         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
8928
8929         /* Acer/eMachines e725 */
8930         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
8931
8932         /* Acer/Packard Bell NCL20 */
8933         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
8934
8935         /* Acer Aspire 4736Z */
8936         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
8937 };
8938
8939 static void intel_init_quirks(struct drm_device *dev)
8940 {
8941         struct pci_dev *d = dev->pdev;
8942         int i;
8943
8944         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8945                 struct intel_quirk *q = &intel_quirks[i];
8946
8947                 if (d->device == q->device &&
8948                     (d->subsystem_vendor == q->subsystem_vendor ||
8949                      q->subsystem_vendor == PCI_ANY_ID) &&
8950                     (d->subsystem_device == q->subsystem_device ||
8951                      q->subsystem_device == PCI_ANY_ID))
8952                         q->hook(dev);
8953         }
8954         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8955                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8956                         intel_dmi_quirks[i].hook(dev);
8957         }
8958 }
8959
8960 /* Disable the VGA plane that we never use */
8961 static void i915_disable_vga(struct drm_device *dev)
8962 {
8963         struct drm_i915_private *dev_priv = dev->dev_private;
8964         u8 sr1;
8965         u32 vga_reg = i915_vgacntrl_reg(dev);
8966
8967         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8968         outb(SR01, VGA_SR_INDEX);
8969         sr1 = inb(VGA_SR_DATA);
8970         outb(sr1 | 1<<5, VGA_SR_DATA);
8971         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8972         udelay(300);
8973
8974         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8975         POSTING_READ(vga_reg);
8976 }
8977
8978 void intel_modeset_init_hw(struct drm_device *dev)
8979 {
8980         intel_init_power_well(dev);
8981
8982         intel_prepare_ddi(dev);
8983
8984         intel_init_clock_gating(dev);
8985
8986         mutex_lock(&dev->struct_mutex);
8987         intel_enable_gt_powersave(dev);
8988         mutex_unlock(&dev->struct_mutex);
8989 }
8990
8991 void intel_modeset_init(struct drm_device *dev)
8992 {
8993         struct drm_i915_private *dev_priv = dev->dev_private;
8994         int i, j, ret;
8995
8996         drm_mode_config_init(dev);
8997
8998         dev->mode_config.min_width = 0;
8999         dev->mode_config.min_height = 0;
9000
9001         dev->mode_config.preferred_depth = 24;
9002         dev->mode_config.prefer_shadow = 1;
9003
9004         dev->mode_config.funcs = &intel_mode_funcs;
9005
9006         intel_init_quirks(dev);
9007
9008         intel_init_pm(dev);
9009
9010         if (INTEL_INFO(dev)->num_pipes == 0)
9011                 return;
9012
9013         intel_init_display(dev);
9014
9015         if (IS_GEN2(dev)) {
9016                 dev->mode_config.max_width = 2048;
9017                 dev->mode_config.max_height = 2048;
9018         } else if (IS_GEN3(dev)) {
9019                 dev->mode_config.max_width = 4096;
9020                 dev->mode_config.max_height = 4096;
9021         } else {
9022                 dev->mode_config.max_width = 8192;
9023                 dev->mode_config.max_height = 8192;
9024         }
9025         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
9026
9027         DRM_DEBUG_KMS("%d display pipe%s available.\n",
9028                       INTEL_INFO(dev)->num_pipes,
9029                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
9030
9031         for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
9032                 intel_crtc_init(dev, i);
9033                 for (j = 0; j < dev_priv->num_plane; j++) {
9034                         ret = intel_plane_init(dev, i, j);
9035                         if (ret)
9036                                 DRM_DEBUG_KMS("pipe %d plane %d init failed: %d\n",
9037                                               i, j, ret);
9038                 }
9039         }
9040
9041         intel_cpu_pll_init(dev);
9042         intel_pch_pll_init(dev);
9043
9044         /* Just disable it once at startup */
9045         i915_disable_vga(dev);
9046         intel_setup_outputs(dev);
9047
9048         /* Just in case the BIOS is doing something questionable. */
9049         intel_disable_fbc(dev);
9050 }
9051
9052 static void
9053 intel_connector_break_all_links(struct intel_connector *connector)
9054 {
9055         connector->base.dpms = DRM_MODE_DPMS_OFF;
9056         connector->base.encoder = NULL;
9057         connector->encoder->connectors_active = false;
9058         connector->encoder->base.crtc = NULL;
9059 }
9060
9061 static void intel_enable_pipe_a(struct drm_device *dev)
9062 {
9063         struct intel_connector *connector;
9064         struct drm_connector *crt = NULL;
9065         struct intel_load_detect_pipe load_detect_temp;
9066
9067         /* We can't just switch on the pipe A, we need to set things up with a
9068          * proper mode and output configuration. As a gross hack, enable pipe A
9069          * by enabling the load detect pipe once. */
9070         list_for_each_entry(connector,
9071                             &dev->mode_config.connector_list,
9072                             base.head) {
9073                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9074                         crt = &connector->base;
9075                         break;
9076                 }
9077         }
9078
9079         if (!crt)
9080                 return;
9081
9082         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9083                 intel_release_load_detect_pipe(crt, &load_detect_temp);
9084
9085
9086 }
9087
9088 static bool
9089 intel_check_plane_mapping(struct intel_crtc *crtc)
9090 {
9091         struct drm_device *dev = crtc->base.dev;
9092         struct drm_i915_private *dev_priv = dev->dev_private;
9093         u32 reg, val;
9094
9095         if (INTEL_INFO(dev)->num_pipes == 1)
9096                 return true;
9097
9098         reg = DSPCNTR(!crtc->plane);
9099         val = I915_READ(reg);
9100
9101         if ((val & DISPLAY_PLANE_ENABLE) &&
9102             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9103                 return false;
9104
9105         return true;
9106 }
9107
9108 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9109 {
9110         struct drm_device *dev = crtc->base.dev;
9111         struct drm_i915_private *dev_priv = dev->dev_private;
9112         u32 reg;
9113
9114         /* Clear any frame start delays used for debugging left by the BIOS */
9115         reg = PIPECONF(crtc->cpu_transcoder);
9116         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9117
9118         /* We need to sanitize the plane -> pipe mapping first because this will
9119          * disable the crtc (and hence change the state) if it is wrong. Note
9120          * that gen4+ has a fixed plane -> pipe mapping.  */
9121         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9122                 struct intel_connector *connector;
9123                 bool plane;
9124
9125                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9126                               crtc->base.base.id);
9127
9128                 /* Pipe has the wrong plane attached and the plane is active.
9129                  * Temporarily change the plane mapping and disable everything
9130                  * ...  */
9131                 plane = crtc->plane;
9132                 crtc->plane = !plane;
9133                 dev_priv->display.crtc_disable(&crtc->base);
9134                 crtc->plane = plane;
9135
9136                 /* ... and break all links. */
9137                 list_for_each_entry(connector, &dev->mode_config.connector_list,
9138                                     base.head) {
9139                         if (connector->encoder->base.crtc != &crtc->base)
9140                                 continue;
9141
9142                         intel_connector_break_all_links(connector);
9143                 }
9144
9145                 WARN_ON(crtc->active);
9146                 crtc->base.enabled = false;
9147         }
9148
9149         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9150             crtc->pipe == PIPE_A && !crtc->active) {
9151                 /* BIOS forgot to enable pipe A, this mostly happens after
9152                  * resume. Force-enable the pipe to fix this, the update_dpms
9153                  * call below we restore the pipe to the right state, but leave
9154                  * the required bits on. */
9155                 intel_enable_pipe_a(dev);
9156         }
9157
9158         /* Adjust the state of the output pipe according to whether we
9159          * have active connectors/encoders. */
9160         intel_crtc_update_dpms(&crtc->base);
9161
9162         if (crtc->active != crtc->base.enabled) {
9163                 struct intel_encoder *encoder;
9164
9165                 /* This can happen either due to bugs in the get_hw_state
9166                  * functions or because the pipe is force-enabled due to the
9167                  * pipe A quirk. */
9168                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9169                               crtc->base.base.id,
9170                               crtc->base.enabled ? "enabled" : "disabled",
9171                               crtc->active ? "enabled" : "disabled");
9172
9173                 crtc->base.enabled = crtc->active;
9174
9175                 /* Because we only establish the connector -> encoder ->
9176                  * crtc links if something is active, this means the
9177                  * crtc is now deactivated. Break the links. connector
9178                  * -> encoder links are only establish when things are
9179                  *  actually up, hence no need to break them. */
9180                 WARN_ON(crtc->active);
9181
9182                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9183                         WARN_ON(encoder->connectors_active);
9184                         encoder->base.crtc = NULL;
9185                 }
9186         }
9187 }
9188
9189 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9190 {
9191         struct intel_connector *connector;
9192         struct drm_device *dev = encoder->base.dev;
9193
9194         /* We need to check both for a crtc link (meaning that the
9195          * encoder is active and trying to read from a pipe) and the
9196          * pipe itself being active. */
9197         bool has_active_crtc = encoder->base.crtc &&
9198                 to_intel_crtc(encoder->base.crtc)->active;
9199
9200         if (encoder->connectors_active && !has_active_crtc) {
9201                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9202                               encoder->base.base.id,
9203                               drm_get_encoder_name(&encoder->base));
9204
9205                 /* Connector is active, but has no active pipe. This is
9206                  * fallout from our resume register restoring. Disable
9207                  * the encoder manually again. */
9208                 if (encoder->base.crtc) {
9209                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9210                                       encoder->base.base.id,
9211                                       drm_get_encoder_name(&encoder->base));
9212                         encoder->disable(encoder);
9213                 }
9214
9215                 /* Inconsistent output/port/pipe state happens presumably due to
9216                  * a bug in one of the get_hw_state functions. Or someplace else
9217                  * in our code, like the register restore mess on resume. Clamp
9218                  * things to off as a safer default. */
9219                 list_for_each_entry(connector,
9220                                     &dev->mode_config.connector_list,
9221                                     base.head) {
9222                         if (connector->encoder != encoder)
9223                                 continue;
9224
9225                         intel_connector_break_all_links(connector);
9226                 }
9227         }
9228         /* Enabled encoders without active connectors will be fixed in
9229          * the crtc fixup. */
9230 }
9231
9232 void i915_redisable_vga(struct drm_device *dev)
9233 {
9234         struct drm_i915_private *dev_priv = dev->dev_private;
9235         u32 vga_reg = i915_vgacntrl_reg(dev);
9236
9237         if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9238                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9239                 i915_disable_vga(dev);
9240         }
9241 }
9242
9243 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9244  * and i915 state tracking structures. */
9245 void intel_modeset_setup_hw_state(struct drm_device *dev,
9246                                   bool force_restore)
9247 {
9248         struct drm_i915_private *dev_priv = dev->dev_private;
9249         enum pipe pipe;
9250         u32 tmp;
9251         struct drm_plane *plane;
9252         struct intel_crtc *crtc;
9253         struct intel_encoder *encoder;
9254         struct intel_connector *connector;
9255
9256         if (HAS_DDI(dev)) {
9257                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9258
9259                 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9260                         switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9261                         case TRANS_DDI_EDP_INPUT_A_ON:
9262                         case TRANS_DDI_EDP_INPUT_A_ONOFF:
9263                                 pipe = PIPE_A;
9264                                 break;
9265                         case TRANS_DDI_EDP_INPUT_B_ONOFF:
9266                                 pipe = PIPE_B;
9267                                 break;
9268                         case TRANS_DDI_EDP_INPUT_C_ONOFF:
9269                                 pipe = PIPE_C;
9270                                 break;
9271                         default:
9272                                 /* A bogus value has been programmed, disable
9273                                  * the transcoder */
9274                                 WARN(1, "Bogus eDP source %08x\n", tmp);
9275                                 intel_ddi_disable_transcoder_func(dev_priv,
9276                                                 TRANSCODER_EDP);
9277                                 goto setup_pipes;
9278                         }
9279
9280                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9281                         crtc->cpu_transcoder = TRANSCODER_EDP;
9282
9283                         DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9284                                       pipe_name(pipe));
9285                 }
9286         }
9287
9288 setup_pipes:
9289         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9290                             base.head) {
9291                 memset(&crtc->config, 0, sizeof(crtc->config));
9292                 crtc->active = dev_priv->display.get_pipe_config(crtc,
9293                                                                  &crtc->config);
9294
9295                 crtc->base.enabled = crtc->active;
9296
9297                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9298                               crtc->base.base.id,
9299                               crtc->active ? "enabled" : "disabled");
9300         }
9301
9302         if (HAS_DDI(dev))
9303                 intel_ddi_setup_hw_pll_state(dev);
9304
9305         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9306                             base.head) {
9307                 pipe = 0;
9308
9309                 if (encoder->get_hw_state(encoder, &pipe)) {
9310                         encoder->base.crtc =
9311                                 dev_priv->pipe_to_crtc_mapping[pipe];
9312                 } else {
9313                         encoder->base.crtc = NULL;
9314                 }
9315
9316                 encoder->connectors_active = false;
9317                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9318                               encoder->base.base.id,
9319                               drm_get_encoder_name(&encoder->base),
9320                               encoder->base.crtc ? "enabled" : "disabled",
9321                               pipe);
9322         }
9323
9324         list_for_each_entry(connector, &dev->mode_config.connector_list,
9325                             base.head) {
9326                 if (connector->get_hw_state(connector)) {
9327                         connector->base.dpms = DRM_MODE_DPMS_ON;
9328                         connector->encoder->connectors_active = true;
9329                         connector->base.encoder = &connector->encoder->base;
9330                 } else {
9331                         connector->base.dpms = DRM_MODE_DPMS_OFF;
9332                         connector->base.encoder = NULL;
9333                 }
9334                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9335                               connector->base.base.id,
9336                               drm_get_connector_name(&connector->base),
9337                               connector->base.encoder ? "enabled" : "disabled");
9338         }
9339
9340         /* HW state is read out, now we need to sanitize this mess. */
9341         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9342                             base.head) {
9343                 intel_sanitize_encoder(encoder);
9344         }
9345
9346         for_each_pipe(pipe) {
9347                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9348                 intel_sanitize_crtc(crtc);
9349         }
9350
9351         if (force_restore) {
9352                 /*
9353                  * We need to use raw interfaces for restoring state to avoid
9354                  * checking (bogus) intermediate states.
9355                  */
9356                 for_each_pipe(pipe) {
9357                         struct drm_crtc *crtc =
9358                                 dev_priv->pipe_to_crtc_mapping[pipe];
9359
9360                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9361                                          crtc->fb);
9362                 }
9363                 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9364                         intel_plane_restore(plane);
9365
9366                 i915_redisable_vga(dev);
9367         } else {
9368                 intel_modeset_update_staged_output_state(dev);
9369         }
9370
9371         intel_modeset_check_state(dev);
9372
9373         drm_mode_config_reset(dev);
9374 }
9375
9376 void intel_modeset_gem_init(struct drm_device *dev)
9377 {
9378         intel_modeset_init_hw(dev);
9379
9380         intel_setup_overlay(dev);
9381
9382         intel_modeset_setup_hw_state(dev, false);
9383 }
9384
9385 void intel_modeset_cleanup(struct drm_device *dev)
9386 {
9387         struct drm_i915_private *dev_priv = dev->dev_private;
9388         struct drm_crtc *crtc;
9389         struct intel_crtc *intel_crtc;
9390
9391         drm_kms_helper_poll_fini(dev);
9392         mutex_lock(&dev->struct_mutex);
9393
9394         intel_unregister_dsm_handler();
9395
9396
9397         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9398                 /* Skip inactive CRTCs */
9399                 if (!crtc->fb)
9400                         continue;
9401
9402                 intel_crtc = to_intel_crtc(crtc);
9403                 intel_increase_pllclock(crtc);
9404         }
9405
9406         intel_disable_fbc(dev);
9407
9408         intel_disable_gt_powersave(dev);
9409
9410         ironlake_teardown_rc6(dev);
9411
9412         if (IS_VALLEYVIEW(dev))
9413                 vlv_init_dpio(dev);
9414
9415         mutex_unlock(&dev->struct_mutex);
9416
9417         /* Disable the irq before mode object teardown, for the irq might
9418          * enqueue unpin/hotplug work. */
9419         drm_irq_uninstall(dev);
9420         cancel_work_sync(&dev_priv->hotplug_work);
9421         cancel_work_sync(&dev_priv->rps.work);
9422
9423         /* flush any delayed tasks or pending work */
9424         flush_scheduled_work();
9425
9426         /* destroy backlight, if any, before the connectors */
9427         intel_panel_destroy_backlight(dev);
9428
9429         drm_mode_config_cleanup(dev);
9430
9431         intel_cleanup_overlay(dev);
9432 }
9433
9434 /*
9435  * Return which encoder is currently attached for connector.
9436  */
9437 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9438 {
9439         return &intel_attached_encoder(connector)->base;
9440 }
9441
9442 void intel_connector_attach_encoder(struct intel_connector *connector,
9443                                     struct intel_encoder *encoder)
9444 {
9445         connector->encoder = encoder;
9446         drm_mode_connector_attach_encoder(&connector->base,
9447                                           &encoder->base);
9448 }
9449
9450 /*
9451  * set vga decode state - true == enable VGA decode
9452  */
9453 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9454 {
9455         struct drm_i915_private *dev_priv = dev->dev_private;
9456         u16 gmch_ctrl;
9457
9458         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9459         if (state)
9460                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9461         else
9462                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9463         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9464         return 0;
9465 }
9466
9467 #ifdef CONFIG_DEBUG_FS
9468 #include <linux/seq_file.h>
9469
9470 struct intel_display_error_state {
9471         struct intel_cursor_error_state {
9472                 u32 control;
9473                 u32 position;
9474                 u32 base;
9475                 u32 size;
9476         } cursor[I915_MAX_PIPES];
9477
9478         struct intel_pipe_error_state {
9479                 u32 conf;
9480                 u32 source;
9481
9482                 u32 htotal;
9483                 u32 hblank;
9484                 u32 hsync;
9485                 u32 vtotal;
9486                 u32 vblank;
9487                 u32 vsync;
9488         } pipe[I915_MAX_PIPES];
9489
9490         struct intel_plane_error_state {
9491                 u32 control;
9492                 u32 stride;
9493                 u32 size;
9494                 u32 pos;
9495                 u32 addr;
9496                 u32 surface;
9497                 u32 tile_offset;
9498         } plane[I915_MAX_PIPES];
9499 };
9500
9501 struct intel_display_error_state *
9502 intel_display_capture_error_state(struct drm_device *dev)
9503 {
9504         drm_i915_private_t *dev_priv = dev->dev_private;
9505         struct intel_display_error_state *error;
9506         enum transcoder cpu_transcoder;
9507         int i;
9508
9509         error = kmalloc(sizeof(*error), GFP_ATOMIC);
9510         if (error == NULL)
9511                 return NULL;
9512
9513         for_each_pipe(i) {
9514                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9515
9516                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9517                         error->cursor[i].control = I915_READ(CURCNTR(i));
9518                         error->cursor[i].position = I915_READ(CURPOS(i));
9519                         error->cursor[i].base = I915_READ(CURBASE(i));
9520                 } else {
9521                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9522                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9523                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9524                 }
9525
9526                 error->plane[i].control = I915_READ(DSPCNTR(i));
9527                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9528                 if (INTEL_INFO(dev)->gen <= 3) {
9529                         error->plane[i].size = I915_READ(DSPSIZE(i));
9530                         error->plane[i].pos = I915_READ(DSPPOS(i));
9531                 }
9532                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9533                         error->plane[i].addr = I915_READ(DSPADDR(i));
9534                 if (INTEL_INFO(dev)->gen >= 4) {
9535                         error->plane[i].surface = I915_READ(DSPSURF(i));
9536                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9537                 }
9538
9539                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9540                 error->pipe[i].source = I915_READ(PIPESRC(i));
9541                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9542                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9543                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9544                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9545                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9546                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9547         }
9548
9549         return error;
9550 }
9551
9552 void
9553 intel_display_print_error_state(struct seq_file *m,
9554                                 struct drm_device *dev,
9555                                 struct intel_display_error_state *error)
9556 {
9557         int i;
9558
9559         seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
9560         for_each_pipe(i) {
9561                 seq_printf(m, "Pipe [%d]:\n", i);
9562                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9563                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9564                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9565                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9566                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9567                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9568                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9569                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9570
9571                 seq_printf(m, "Plane [%d]:\n", i);
9572                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9573                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9574                 if (INTEL_INFO(dev)->gen <= 3) {
9575                         seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9576                         seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
9577                 }
9578                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9579                         seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9580                 if (INTEL_INFO(dev)->gen >= 4) {
9581                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9582                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9583                 }
9584
9585                 seq_printf(m, "Cursor [%d]:\n", i);
9586                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9587                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
9588                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9589         }
9590 }
9591 #endif