2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
45 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
47 static void intel_increase_pllclock(struct drm_crtc *crtc);
48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
50 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
51 struct intel_crtc_config *pipe_config);
52 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
53 struct intel_crtc_config *pipe_config);
55 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
56 int x, int y, struct drm_framebuffer *old_fb);
57 static int intel_framebuffer_init(struct drm_device *dev,
58 struct intel_framebuffer *ifb,
59 struct drm_mode_fb_cmd2 *mode_cmd,
60 struct drm_i915_gem_object *obj);
71 typedef struct intel_limit intel_limit_t;
73 intel_range_t dot, vco, n, m, m1, m2, p, p1;
78 intel_pch_rawclk(struct drm_device *dev)
80 struct drm_i915_private *dev_priv = dev->dev_private;
82 WARN_ON(!HAS_PCH_SPLIT(dev));
84 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
87 static inline u32 /* units of 100MHz */
88 intel_fdi_link_freq(struct drm_device *dev)
91 struct drm_i915_private *dev_priv = dev->dev_private;
92 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
97 static const intel_limit_t intel_limits_i8xx_dac = {
98 .dot = { .min = 25000, .max = 350000 },
99 .vco = { .min = 908000, .max = 1512000 },
100 .n = { .min = 2, .max = 16 },
101 .m = { .min = 96, .max = 140 },
102 .m1 = { .min = 18, .max = 26 },
103 .m2 = { .min = 6, .max = 16 },
104 .p = { .min = 4, .max = 128 },
105 .p1 = { .min = 2, .max = 33 },
106 .p2 = { .dot_limit = 165000,
107 .p2_slow = 4, .p2_fast = 2 },
110 static const intel_limit_t intel_limits_i8xx_dvo = {
111 .dot = { .min = 25000, .max = 350000 },
112 .vco = { .min = 908000, .max = 1512000 },
113 .n = { .min = 2, .max = 16 },
114 .m = { .min = 96, .max = 140 },
115 .m1 = { .min = 18, .max = 26 },
116 .m2 = { .min = 6, .max = 16 },
117 .p = { .min = 4, .max = 128 },
118 .p1 = { .min = 2, .max = 33 },
119 .p2 = { .dot_limit = 165000,
120 .p2_slow = 4, .p2_fast = 4 },
123 static const intel_limit_t intel_limits_i8xx_lvds = {
124 .dot = { .min = 25000, .max = 350000 },
125 .vco = { .min = 908000, .max = 1512000 },
126 .n = { .min = 2, .max = 16 },
127 .m = { .min = 96, .max = 140 },
128 .m1 = { .min = 18, .max = 26 },
129 .m2 = { .min = 6, .max = 16 },
130 .p = { .min = 4, .max = 128 },
131 .p1 = { .min = 1, .max = 6 },
132 .p2 = { .dot_limit = 165000,
133 .p2_slow = 14, .p2_fast = 7 },
136 static const intel_limit_t intel_limits_i9xx_sdvo = {
137 .dot = { .min = 20000, .max = 400000 },
138 .vco = { .min = 1400000, .max = 2800000 },
139 .n = { .min = 1, .max = 6 },
140 .m = { .min = 70, .max = 120 },
141 .m1 = { .min = 8, .max = 18 },
142 .m2 = { .min = 3, .max = 7 },
143 .p = { .min = 5, .max = 80 },
144 .p1 = { .min = 1, .max = 8 },
145 .p2 = { .dot_limit = 200000,
146 .p2_slow = 10, .p2_fast = 5 },
149 static const intel_limit_t intel_limits_i9xx_lvds = {
150 .dot = { .min = 20000, .max = 400000 },
151 .vco = { .min = 1400000, .max = 2800000 },
152 .n = { .min = 1, .max = 6 },
153 .m = { .min = 70, .max = 120 },
154 .m1 = { .min = 8, .max = 18 },
155 .m2 = { .min = 3, .max = 7 },
156 .p = { .min = 7, .max = 98 },
157 .p1 = { .min = 1, .max = 8 },
158 .p2 = { .dot_limit = 112000,
159 .p2_slow = 14, .p2_fast = 7 },
163 static const intel_limit_t intel_limits_g4x_sdvo = {
164 .dot = { .min = 25000, .max = 270000 },
165 .vco = { .min = 1750000, .max = 3500000},
166 .n = { .min = 1, .max = 4 },
167 .m = { .min = 104, .max = 138 },
168 .m1 = { .min = 17, .max = 23 },
169 .m2 = { .min = 5, .max = 11 },
170 .p = { .min = 10, .max = 30 },
171 .p1 = { .min = 1, .max = 3},
172 .p2 = { .dot_limit = 270000,
178 static const intel_limit_t intel_limits_g4x_hdmi = {
179 .dot = { .min = 22000, .max = 400000 },
180 .vco = { .min = 1750000, .max = 3500000},
181 .n = { .min = 1, .max = 4 },
182 .m = { .min = 104, .max = 138 },
183 .m1 = { .min = 16, .max = 23 },
184 .m2 = { .min = 5, .max = 11 },
185 .p = { .min = 5, .max = 80 },
186 .p1 = { .min = 1, .max = 8},
187 .p2 = { .dot_limit = 165000,
188 .p2_slow = 10, .p2_fast = 5 },
191 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
192 .dot = { .min = 20000, .max = 115000 },
193 .vco = { .min = 1750000, .max = 3500000 },
194 .n = { .min = 1, .max = 3 },
195 .m = { .min = 104, .max = 138 },
196 .m1 = { .min = 17, .max = 23 },
197 .m2 = { .min = 5, .max = 11 },
198 .p = { .min = 28, .max = 112 },
199 .p1 = { .min = 2, .max = 8 },
200 .p2 = { .dot_limit = 0,
201 .p2_slow = 14, .p2_fast = 14
205 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
206 .dot = { .min = 80000, .max = 224000 },
207 .vco = { .min = 1750000, .max = 3500000 },
208 .n = { .min = 1, .max = 3 },
209 .m = { .min = 104, .max = 138 },
210 .m1 = { .min = 17, .max = 23 },
211 .m2 = { .min = 5, .max = 11 },
212 .p = { .min = 14, .max = 42 },
213 .p1 = { .min = 2, .max = 6 },
214 .p2 = { .dot_limit = 0,
215 .p2_slow = 7, .p2_fast = 7
219 static const intel_limit_t intel_limits_pineview_sdvo = {
220 .dot = { .min = 20000, .max = 400000},
221 .vco = { .min = 1700000, .max = 3500000 },
222 /* Pineview's Ncounter is a ring counter */
223 .n = { .min = 3, .max = 6 },
224 .m = { .min = 2, .max = 256 },
225 /* Pineview only has one combined m divider, which we treat as m2. */
226 .m1 = { .min = 0, .max = 0 },
227 .m2 = { .min = 0, .max = 254 },
228 .p = { .min = 5, .max = 80 },
229 .p1 = { .min = 1, .max = 8 },
230 .p2 = { .dot_limit = 200000,
231 .p2_slow = 10, .p2_fast = 5 },
234 static const intel_limit_t intel_limits_pineview_lvds = {
235 .dot = { .min = 20000, .max = 400000 },
236 .vco = { .min = 1700000, .max = 3500000 },
237 .n = { .min = 3, .max = 6 },
238 .m = { .min = 2, .max = 256 },
239 .m1 = { .min = 0, .max = 0 },
240 .m2 = { .min = 0, .max = 254 },
241 .p = { .min = 7, .max = 112 },
242 .p1 = { .min = 1, .max = 8 },
243 .p2 = { .dot_limit = 112000,
244 .p2_slow = 14, .p2_fast = 14 },
247 /* Ironlake / Sandybridge
249 * We calculate clock using (register_value + 2) for N/M1/M2, so here
250 * the range value for them is (actual_value - 2).
252 static const intel_limit_t intel_limits_ironlake_dac = {
253 .dot = { .min = 25000, .max = 350000 },
254 .vco = { .min = 1760000, .max = 3510000 },
255 .n = { .min = 1, .max = 5 },
256 .m = { .min = 79, .max = 127 },
257 .m1 = { .min = 12, .max = 22 },
258 .m2 = { .min = 5, .max = 9 },
259 .p = { .min = 5, .max = 80 },
260 .p1 = { .min = 1, .max = 8 },
261 .p2 = { .dot_limit = 225000,
262 .p2_slow = 10, .p2_fast = 5 },
265 static const intel_limit_t intel_limits_ironlake_single_lvds = {
266 .dot = { .min = 25000, .max = 350000 },
267 .vco = { .min = 1760000, .max = 3510000 },
268 .n = { .min = 1, .max = 3 },
269 .m = { .min = 79, .max = 118 },
270 .m1 = { .min = 12, .max = 22 },
271 .m2 = { .min = 5, .max = 9 },
272 .p = { .min = 28, .max = 112 },
273 .p1 = { .min = 2, .max = 8 },
274 .p2 = { .dot_limit = 225000,
275 .p2_slow = 14, .p2_fast = 14 },
278 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
279 .dot = { .min = 25000, .max = 350000 },
280 .vco = { .min = 1760000, .max = 3510000 },
281 .n = { .min = 1, .max = 3 },
282 .m = { .min = 79, .max = 127 },
283 .m1 = { .min = 12, .max = 22 },
284 .m2 = { .min = 5, .max = 9 },
285 .p = { .min = 14, .max = 56 },
286 .p1 = { .min = 2, .max = 8 },
287 .p2 = { .dot_limit = 225000,
288 .p2_slow = 7, .p2_fast = 7 },
291 /* LVDS 100mhz refclk limits. */
292 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
293 .dot = { .min = 25000, .max = 350000 },
294 .vco = { .min = 1760000, .max = 3510000 },
295 .n = { .min = 1, .max = 2 },
296 .m = { .min = 79, .max = 126 },
297 .m1 = { .min = 12, .max = 22 },
298 .m2 = { .min = 5, .max = 9 },
299 .p = { .min = 28, .max = 112 },
300 .p1 = { .min = 2, .max = 8 },
301 .p2 = { .dot_limit = 225000,
302 .p2_slow = 14, .p2_fast = 14 },
305 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
306 .dot = { .min = 25000, .max = 350000 },
307 .vco = { .min = 1760000, .max = 3510000 },
308 .n = { .min = 1, .max = 3 },
309 .m = { .min = 79, .max = 126 },
310 .m1 = { .min = 12, .max = 22 },
311 .m2 = { .min = 5, .max = 9 },
312 .p = { .min = 14, .max = 42 },
313 .p1 = { .min = 2, .max = 6 },
314 .p2 = { .dot_limit = 225000,
315 .p2_slow = 7, .p2_fast = 7 },
318 static const intel_limit_t intel_limits_vlv = {
320 * These are the data rate limits (measured in fast clocks)
321 * since those are the strictest limits we have. The fast
322 * clock and actual rate limits are more relaxed, so checking
323 * them would make no difference.
325 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
326 .vco = { .min = 4000000, .max = 6000000 },
327 .n = { .min = 1, .max = 7 },
328 .m1 = { .min = 2, .max = 3 },
329 .m2 = { .min = 11, .max = 156 },
330 .p1 = { .min = 2, .max = 3 },
331 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
334 static const intel_limit_t intel_limits_chv = {
336 * These are the data rate limits (measured in fast clocks)
337 * since those are the strictest limits we have. The fast
338 * clock and actual rate limits are more relaxed, so checking
339 * them would make no difference.
341 .dot = { .min = 25000 * 5, .max = 540000 * 5},
342 .vco = { .min = 4860000, .max = 6700000 },
343 .n = { .min = 1, .max = 1 },
344 .m1 = { .min = 2, .max = 2 },
345 .m2 = { .min = 24 << 22, .max = 175 << 22 },
346 .p1 = { .min = 2, .max = 4 },
347 .p2 = { .p2_slow = 1, .p2_fast = 14 },
350 static void vlv_clock(int refclk, intel_clock_t *clock)
352 clock->m = clock->m1 * clock->m2;
353 clock->p = clock->p1 * clock->p2;
354 if (WARN_ON(clock->n == 0 || clock->p == 0))
356 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
357 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
361 * Returns whether any output on the specified pipe is of the specified type
363 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
365 struct drm_device *dev = crtc->dev;
366 struct intel_encoder *encoder;
368 for_each_encoder_on_crtc(dev, crtc, encoder)
369 if (encoder->type == type)
375 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
378 struct drm_device *dev = crtc->dev;
379 const intel_limit_t *limit;
381 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
382 if (intel_is_dual_link_lvds(dev)) {
383 if (refclk == 100000)
384 limit = &intel_limits_ironlake_dual_lvds_100m;
386 limit = &intel_limits_ironlake_dual_lvds;
388 if (refclk == 100000)
389 limit = &intel_limits_ironlake_single_lvds_100m;
391 limit = &intel_limits_ironlake_single_lvds;
394 limit = &intel_limits_ironlake_dac;
399 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
401 struct drm_device *dev = crtc->dev;
402 const intel_limit_t *limit;
404 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
405 if (intel_is_dual_link_lvds(dev))
406 limit = &intel_limits_g4x_dual_channel_lvds;
408 limit = &intel_limits_g4x_single_channel_lvds;
409 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
410 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
411 limit = &intel_limits_g4x_hdmi;
412 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
413 limit = &intel_limits_g4x_sdvo;
414 } else /* The option is for other outputs */
415 limit = &intel_limits_i9xx_sdvo;
420 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
422 struct drm_device *dev = crtc->dev;
423 const intel_limit_t *limit;
425 if (HAS_PCH_SPLIT(dev))
426 limit = intel_ironlake_limit(crtc, refclk);
427 else if (IS_G4X(dev)) {
428 limit = intel_g4x_limit(crtc);
429 } else if (IS_PINEVIEW(dev)) {
430 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
431 limit = &intel_limits_pineview_lvds;
433 limit = &intel_limits_pineview_sdvo;
434 } else if (IS_CHERRYVIEW(dev)) {
435 limit = &intel_limits_chv;
436 } else if (IS_VALLEYVIEW(dev)) {
437 limit = &intel_limits_vlv;
438 } else if (!IS_GEN2(dev)) {
439 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
440 limit = &intel_limits_i9xx_lvds;
442 limit = &intel_limits_i9xx_sdvo;
444 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
445 limit = &intel_limits_i8xx_lvds;
446 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
447 limit = &intel_limits_i8xx_dvo;
449 limit = &intel_limits_i8xx_dac;
454 /* m1 is reserved as 0 in Pineview, n is a ring counter */
455 static void pineview_clock(int refclk, intel_clock_t *clock)
457 clock->m = clock->m2 + 2;
458 clock->p = clock->p1 * clock->p2;
459 if (WARN_ON(clock->n == 0 || clock->p == 0))
461 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
462 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
465 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
467 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
470 static void i9xx_clock(int refclk, intel_clock_t *clock)
472 clock->m = i9xx_dpll_compute_m(clock);
473 clock->p = clock->p1 * clock->p2;
474 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
476 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
477 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
480 static void chv_clock(int refclk, intel_clock_t *clock)
482 clock->m = clock->m1 * clock->m2;
483 clock->p = clock->p1 * clock->p2;
484 if (WARN_ON(clock->n == 0 || clock->p == 0))
486 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
488 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
491 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
493 * Returns whether the given set of divisors are valid for a given refclk with
494 * the given connectors.
497 static bool intel_PLL_is_valid(struct drm_device *dev,
498 const intel_limit_t *limit,
499 const intel_clock_t *clock)
501 if (clock->n < limit->n.min || limit->n.max < clock->n)
502 INTELPllInvalid("n out of range\n");
503 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
504 INTELPllInvalid("p1 out of range\n");
505 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
506 INTELPllInvalid("m2 out of range\n");
507 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
508 INTELPllInvalid("m1 out of range\n");
510 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
511 if (clock->m1 <= clock->m2)
512 INTELPllInvalid("m1 <= m2\n");
514 if (!IS_VALLEYVIEW(dev)) {
515 if (clock->p < limit->p.min || limit->p.max < clock->p)
516 INTELPllInvalid("p out of range\n");
517 if (clock->m < limit->m.min || limit->m.max < clock->m)
518 INTELPllInvalid("m out of range\n");
521 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
522 INTELPllInvalid("vco out of range\n");
523 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
524 * connector, etc., rather than just a single range.
526 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
527 INTELPllInvalid("dot out of range\n");
533 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
534 int target, int refclk, intel_clock_t *match_clock,
535 intel_clock_t *best_clock)
537 struct drm_device *dev = crtc->dev;
541 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
543 * For LVDS just rely on its current settings for dual-channel.
544 * We haven't figured out how to reliably set up different
545 * single/dual channel state, if we even can.
547 if (intel_is_dual_link_lvds(dev))
548 clock.p2 = limit->p2.p2_fast;
550 clock.p2 = limit->p2.p2_slow;
552 if (target < limit->p2.dot_limit)
553 clock.p2 = limit->p2.p2_slow;
555 clock.p2 = limit->p2.p2_fast;
558 memset(best_clock, 0, sizeof(*best_clock));
560 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
562 for (clock.m2 = limit->m2.min;
563 clock.m2 <= limit->m2.max; clock.m2++) {
564 if (clock.m2 >= clock.m1)
566 for (clock.n = limit->n.min;
567 clock.n <= limit->n.max; clock.n++) {
568 for (clock.p1 = limit->p1.min;
569 clock.p1 <= limit->p1.max; clock.p1++) {
572 i9xx_clock(refclk, &clock);
573 if (!intel_PLL_is_valid(dev, limit,
577 clock.p != match_clock->p)
580 this_err = abs(clock.dot - target);
581 if (this_err < err) {
590 return (err != target);
594 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
595 int target, int refclk, intel_clock_t *match_clock,
596 intel_clock_t *best_clock)
598 struct drm_device *dev = crtc->dev;
602 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
604 * For LVDS just rely on its current settings for dual-channel.
605 * We haven't figured out how to reliably set up different
606 * single/dual channel state, if we even can.
608 if (intel_is_dual_link_lvds(dev))
609 clock.p2 = limit->p2.p2_fast;
611 clock.p2 = limit->p2.p2_slow;
613 if (target < limit->p2.dot_limit)
614 clock.p2 = limit->p2.p2_slow;
616 clock.p2 = limit->p2.p2_fast;
619 memset(best_clock, 0, sizeof(*best_clock));
621 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
623 for (clock.m2 = limit->m2.min;
624 clock.m2 <= limit->m2.max; clock.m2++) {
625 for (clock.n = limit->n.min;
626 clock.n <= limit->n.max; clock.n++) {
627 for (clock.p1 = limit->p1.min;
628 clock.p1 <= limit->p1.max; clock.p1++) {
631 pineview_clock(refclk, &clock);
632 if (!intel_PLL_is_valid(dev, limit,
636 clock.p != match_clock->p)
639 this_err = abs(clock.dot - target);
640 if (this_err < err) {
649 return (err != target);
653 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
654 int target, int refclk, intel_clock_t *match_clock,
655 intel_clock_t *best_clock)
657 struct drm_device *dev = crtc->dev;
661 /* approximately equals target * 0.00585 */
662 int err_most = (target >> 8) + (target >> 9);
665 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
666 if (intel_is_dual_link_lvds(dev))
667 clock.p2 = limit->p2.p2_fast;
669 clock.p2 = limit->p2.p2_slow;
671 if (target < limit->p2.dot_limit)
672 clock.p2 = limit->p2.p2_slow;
674 clock.p2 = limit->p2.p2_fast;
677 memset(best_clock, 0, sizeof(*best_clock));
678 max_n = limit->n.max;
679 /* based on hardware requirement, prefer smaller n to precision */
680 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
681 /* based on hardware requirement, prefere larger m1,m2 */
682 for (clock.m1 = limit->m1.max;
683 clock.m1 >= limit->m1.min; clock.m1--) {
684 for (clock.m2 = limit->m2.max;
685 clock.m2 >= limit->m2.min; clock.m2--) {
686 for (clock.p1 = limit->p1.max;
687 clock.p1 >= limit->p1.min; clock.p1--) {
690 i9xx_clock(refclk, &clock);
691 if (!intel_PLL_is_valid(dev, limit,
695 this_err = abs(clock.dot - target);
696 if (this_err < err_most) {
710 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
711 int target, int refclk, intel_clock_t *match_clock,
712 intel_clock_t *best_clock)
714 struct drm_device *dev = crtc->dev;
716 unsigned int bestppm = 1000000;
717 /* min update 19.2 MHz */
718 int max_n = min(limit->n.max, refclk / 19200);
721 target *= 5; /* fast clock */
723 memset(best_clock, 0, sizeof(*best_clock));
725 /* based on hardware requirement, prefer smaller n to precision */
726 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
727 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
728 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
729 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
730 clock.p = clock.p1 * clock.p2;
731 /* based on hardware requirement, prefer bigger m1,m2 values */
732 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
733 unsigned int ppm, diff;
735 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
738 vlv_clock(refclk, &clock);
740 if (!intel_PLL_is_valid(dev, limit,
744 diff = abs(clock.dot - target);
745 ppm = div_u64(1000000ULL * diff, target);
747 if (ppm < 100 && clock.p > best_clock->p) {
753 if (bestppm >= 10 && ppm < bestppm - 10) {
767 chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
768 int target, int refclk, intel_clock_t *match_clock,
769 intel_clock_t *best_clock)
771 struct drm_device *dev = crtc->dev;
776 memset(best_clock, 0, sizeof(*best_clock));
779 * Based on hardware doc, the n always set to 1, and m1 always
780 * set to 2. If requires to support 200Mhz refclk, we need to
781 * revisit this because n may not 1 anymore.
783 clock.n = 1, clock.m1 = 2;
784 target *= 5; /* fast clock */
786 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
787 for (clock.p2 = limit->p2.p2_fast;
788 clock.p2 >= limit->p2.p2_slow;
789 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
791 clock.p = clock.p1 * clock.p2;
793 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
794 clock.n) << 22, refclk * clock.m1);
796 if (m2 > INT_MAX/clock.m1)
801 chv_clock(refclk, &clock);
803 if (!intel_PLL_is_valid(dev, limit, &clock))
806 /* based on hardware requirement, prefer bigger p
808 if (clock.p > best_clock->p) {
818 bool intel_crtc_active(struct drm_crtc *crtc)
820 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
822 /* Be paranoid as we can arrive here with only partial
823 * state retrieved from the hardware during setup.
825 * We can ditch the adjusted_mode.crtc_clock check as soon
826 * as Haswell has gained clock readout/fastboot support.
828 * We can ditch the crtc->primary->fb check as soon as we can
829 * properly reconstruct framebuffers.
831 return intel_crtc->active && crtc->primary->fb &&
832 intel_crtc->config.adjusted_mode.crtc_clock;
835 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
838 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
839 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
841 return intel_crtc->config.cpu_transcoder;
844 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
846 struct drm_i915_private *dev_priv = dev->dev_private;
847 u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
849 frame = I915_READ(frame_reg);
851 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
852 WARN(1, "vblank wait timed out\n");
856 * intel_wait_for_vblank - wait for vblank on a given pipe
858 * @pipe: pipe to wait for
860 * Wait for vblank to occur on a given pipe. Needed for various bits of
863 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
865 struct drm_i915_private *dev_priv = dev->dev_private;
866 int pipestat_reg = PIPESTAT(pipe);
868 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
869 g4x_wait_for_vblank(dev, pipe);
873 /* Clear existing vblank status. Note this will clear any other
874 * sticky status fields as well.
876 * This races with i915_driver_irq_handler() with the result
877 * that either function could miss a vblank event. Here it is not
878 * fatal, as we will either wait upon the next vblank interrupt or
879 * timeout. Generally speaking intel_wait_for_vblank() is only
880 * called during modeset at which time the GPU should be idle and
881 * should *not* be performing page flips and thus not waiting on
883 * Currently, the result of us stealing a vblank from the irq
884 * handler is that a single frame will be skipped during swapbuffers.
886 I915_WRITE(pipestat_reg,
887 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
889 /* Wait for vblank interrupt bit to set */
890 if (wait_for(I915_READ(pipestat_reg) &
891 PIPE_VBLANK_INTERRUPT_STATUS,
893 DRM_DEBUG_KMS("vblank wait timed out\n");
896 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
898 struct drm_i915_private *dev_priv = dev->dev_private;
899 u32 reg = PIPEDSL(pipe);
904 line_mask = DSL_LINEMASK_GEN2;
906 line_mask = DSL_LINEMASK_GEN3;
908 line1 = I915_READ(reg) & line_mask;
910 line2 = I915_READ(reg) & line_mask;
912 return line1 == line2;
916 * intel_wait_for_pipe_off - wait for pipe to turn off
918 * @pipe: pipe to wait for
920 * After disabling a pipe, we can't wait for vblank in the usual way,
921 * spinning on the vblank interrupt status bit, since we won't actually
922 * see an interrupt when the pipe is disabled.
925 * wait for the pipe register state bit to turn off
928 * wait for the display line value to settle (it usually
929 * ends up stopping at the start of the next frame).
932 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
934 struct drm_i915_private *dev_priv = dev->dev_private;
935 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
938 if (INTEL_INFO(dev)->gen >= 4) {
939 int reg = PIPECONF(cpu_transcoder);
941 /* Wait for the Pipe State to go off */
942 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
944 WARN(1, "pipe_off wait timed out\n");
946 /* Wait for the display line to settle */
947 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
948 WARN(1, "pipe_off wait timed out\n");
953 * ibx_digital_port_connected - is the specified port connected?
954 * @dev_priv: i915 private structure
955 * @port: the port to test
957 * Returns true if @port is connected, false otherwise.
959 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
960 struct intel_digital_port *port)
964 if (HAS_PCH_IBX(dev_priv->dev)) {
965 switch (port->port) {
967 bit = SDE_PORTB_HOTPLUG;
970 bit = SDE_PORTC_HOTPLUG;
973 bit = SDE_PORTD_HOTPLUG;
979 switch (port->port) {
981 bit = SDE_PORTB_HOTPLUG_CPT;
984 bit = SDE_PORTC_HOTPLUG_CPT;
987 bit = SDE_PORTD_HOTPLUG_CPT;
994 return I915_READ(SDEISR) & bit;
997 static const char *state_string(bool enabled)
999 return enabled ? "on" : "off";
1002 /* Only for pre-ILK configs */
1003 void assert_pll(struct drm_i915_private *dev_priv,
1004 enum pipe pipe, bool state)
1011 val = I915_READ(reg);
1012 cur_state = !!(val & DPLL_VCO_ENABLE);
1013 WARN(cur_state != state,
1014 "PLL state assertion failure (expected %s, current %s)\n",
1015 state_string(state), state_string(cur_state));
1018 /* XXX: the dsi pll is shared between MIPI DSI ports */
1019 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1024 mutex_lock(&dev_priv->dpio_lock);
1025 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1026 mutex_unlock(&dev_priv->dpio_lock);
1028 cur_state = val & DSI_PLL_VCO_EN;
1029 WARN(cur_state != state,
1030 "DSI PLL state assertion failure (expected %s, current %s)\n",
1031 state_string(state), state_string(cur_state));
1033 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1034 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1036 struct intel_shared_dpll *
1037 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1039 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1041 if (crtc->config.shared_dpll < 0)
1044 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1048 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1049 struct intel_shared_dpll *pll,
1053 struct intel_dpll_hw_state hw_state;
1055 if (HAS_PCH_LPT(dev_priv->dev)) {
1056 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1061 "asserting DPLL %s with no DPLL\n", state_string(state)))
1064 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1065 WARN(cur_state != state,
1066 "%s assertion failure (expected %s, current %s)\n",
1067 pll->name, state_string(state), state_string(cur_state));
1070 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1071 enum pipe pipe, bool state)
1076 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1079 if (HAS_DDI(dev_priv->dev)) {
1080 /* DDI does not have a specific FDI_TX register */
1081 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1082 val = I915_READ(reg);
1083 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1085 reg = FDI_TX_CTL(pipe);
1086 val = I915_READ(reg);
1087 cur_state = !!(val & FDI_TX_ENABLE);
1089 WARN(cur_state != state,
1090 "FDI TX state assertion failure (expected %s, current %s)\n",
1091 state_string(state), state_string(cur_state));
1093 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1094 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1096 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1097 enum pipe pipe, bool state)
1103 reg = FDI_RX_CTL(pipe);
1104 val = I915_READ(reg);
1105 cur_state = !!(val & FDI_RX_ENABLE);
1106 WARN(cur_state != state,
1107 "FDI RX state assertion failure (expected %s, current %s)\n",
1108 state_string(state), state_string(cur_state));
1110 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1111 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1113 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1119 /* ILK FDI PLL is always enabled */
1120 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1123 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1124 if (HAS_DDI(dev_priv->dev))
1127 reg = FDI_TX_CTL(pipe);
1128 val = I915_READ(reg);
1129 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1132 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1133 enum pipe pipe, bool state)
1139 reg = FDI_RX_CTL(pipe);
1140 val = I915_READ(reg);
1141 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1142 WARN(cur_state != state,
1143 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1144 state_string(state), state_string(cur_state));
1147 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1150 int pp_reg, lvds_reg;
1152 enum pipe panel_pipe = PIPE_A;
1155 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1156 pp_reg = PCH_PP_CONTROL;
1157 lvds_reg = PCH_LVDS;
1159 pp_reg = PP_CONTROL;
1163 val = I915_READ(pp_reg);
1164 if (!(val & PANEL_POWER_ON) ||
1165 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1168 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1169 panel_pipe = PIPE_B;
1171 WARN(panel_pipe == pipe && locked,
1172 "panel assertion failure, pipe %c regs locked\n",
1176 static void assert_cursor(struct drm_i915_private *dev_priv,
1177 enum pipe pipe, bool state)
1179 struct drm_device *dev = dev_priv->dev;
1182 if (IS_845G(dev) || IS_I865G(dev))
1183 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1184 else if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev))
1185 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1187 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1189 WARN(cur_state != state,
1190 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1191 pipe_name(pipe), state_string(state), state_string(cur_state));
1193 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1194 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1196 void assert_pipe(struct drm_i915_private *dev_priv,
1197 enum pipe pipe, bool state)
1202 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1205 /* if we need the pipe A quirk it must be always on */
1206 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1209 if (!intel_display_power_enabled(dev_priv,
1210 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1213 reg = PIPECONF(cpu_transcoder);
1214 val = I915_READ(reg);
1215 cur_state = !!(val & PIPECONF_ENABLE);
1218 WARN(cur_state != state,
1219 "pipe %c assertion failure (expected %s, current %s)\n",
1220 pipe_name(pipe), state_string(state), state_string(cur_state));
1223 static void assert_plane(struct drm_i915_private *dev_priv,
1224 enum plane plane, bool state)
1230 reg = DSPCNTR(plane);
1231 val = I915_READ(reg);
1232 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1233 WARN(cur_state != state,
1234 "plane %c assertion failure (expected %s, current %s)\n",
1235 plane_name(plane), state_string(state), state_string(cur_state));
1238 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1239 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1241 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1244 struct drm_device *dev = dev_priv->dev;
1249 /* Primary planes are fixed to pipes on gen4+ */
1250 if (INTEL_INFO(dev)->gen >= 4) {
1251 reg = DSPCNTR(pipe);
1252 val = I915_READ(reg);
1253 WARN(val & DISPLAY_PLANE_ENABLE,
1254 "plane %c assertion failure, should be disabled but not\n",
1259 /* Need to check both planes against the pipe */
1262 val = I915_READ(reg);
1263 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1264 DISPPLANE_SEL_PIPE_SHIFT;
1265 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1266 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1267 plane_name(i), pipe_name(pipe));
1271 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1274 struct drm_device *dev = dev_priv->dev;
1278 if (IS_VALLEYVIEW(dev)) {
1279 for_each_sprite(pipe, sprite) {
1280 reg = SPCNTR(pipe, sprite);
1281 val = I915_READ(reg);
1282 WARN(val & SP_ENABLE,
1283 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1284 sprite_name(pipe, sprite), pipe_name(pipe));
1286 } else if (INTEL_INFO(dev)->gen >= 7) {
1288 val = I915_READ(reg);
1289 WARN(val & SPRITE_ENABLE,
1290 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1291 plane_name(pipe), pipe_name(pipe));
1292 } else if (INTEL_INFO(dev)->gen >= 5) {
1293 reg = DVSCNTR(pipe);
1294 val = I915_READ(reg);
1295 WARN(val & DVS_ENABLE,
1296 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1297 plane_name(pipe), pipe_name(pipe));
1301 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1306 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1308 val = I915_READ(PCH_DREF_CONTROL);
1309 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1310 DREF_SUPERSPREAD_SOURCE_MASK));
1311 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1314 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1321 reg = PCH_TRANSCONF(pipe);
1322 val = I915_READ(reg);
1323 enabled = !!(val & TRANS_ENABLE);
1325 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1329 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1330 enum pipe pipe, u32 port_sel, u32 val)
1332 if ((val & DP_PORT_EN) == 0)
1335 if (HAS_PCH_CPT(dev_priv->dev)) {
1336 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1337 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1338 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1340 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1341 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1344 if ((val & DP_PIPE_MASK) != (pipe << 30))
1350 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1351 enum pipe pipe, u32 val)
1353 if ((val & SDVO_ENABLE) == 0)
1356 if (HAS_PCH_CPT(dev_priv->dev)) {
1357 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1359 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1360 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1363 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1369 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1370 enum pipe pipe, u32 val)
1372 if ((val & LVDS_PORT_EN) == 0)
1375 if (HAS_PCH_CPT(dev_priv->dev)) {
1376 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1379 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1385 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1386 enum pipe pipe, u32 val)
1388 if ((val & ADPA_DAC_ENABLE) == 0)
1390 if (HAS_PCH_CPT(dev_priv->dev)) {
1391 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1394 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1400 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1401 enum pipe pipe, int reg, u32 port_sel)
1403 u32 val = I915_READ(reg);
1404 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1405 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1406 reg, pipe_name(pipe));
1408 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1409 && (val & DP_PIPEB_SELECT),
1410 "IBX PCH dp port still using transcoder B\n");
1413 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1414 enum pipe pipe, int reg)
1416 u32 val = I915_READ(reg);
1417 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1418 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1419 reg, pipe_name(pipe));
1421 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1422 && (val & SDVO_PIPE_B_SELECT),
1423 "IBX PCH hdmi port still using transcoder B\n");
1426 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1432 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1433 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1434 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1437 val = I915_READ(reg);
1438 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1439 "PCH VGA enabled on transcoder %c, should be disabled\n",
1443 val = I915_READ(reg);
1444 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1445 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1448 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1449 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1450 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1453 static void intel_init_dpio(struct drm_device *dev)
1455 struct drm_i915_private *dev_priv = dev->dev_private;
1457 if (!IS_VALLEYVIEW(dev))
1461 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1462 * CHV x1 PHY (DP/HDMI D)
1463 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1465 if (IS_CHERRYVIEW(dev)) {
1466 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1467 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1469 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1473 static void intel_reset_dpio(struct drm_device *dev)
1475 struct drm_i915_private *dev_priv = dev->dev_private;
1477 if (!IS_VALLEYVIEW(dev))
1481 * Enable the CRI clock source so we can get at the display and the
1482 * reference clock for VGA hotplug / manual detection.
1484 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
1485 DPLL_REFA_CLK_ENABLE_VLV |
1486 DPLL_INTEGRATED_CRI_CLK_VLV);
1488 if (IS_CHERRYVIEW(dev)) {
1492 for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) {
1493 /* Poll for phypwrgood signal */
1494 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) &
1495 PHY_POWERGOOD(phy), 1))
1496 DRM_ERROR("Display PHY %d is not power up\n", phy);
1499 * Deassert common lane reset for PHY.
1501 * This should only be done on init and resume from S3
1502 * with both PLLs disabled, or we risk losing DPIO and
1503 * PLL synchronization.
1505 val = I915_READ(DISPLAY_PHY_CONTROL);
1506 I915_WRITE(DISPLAY_PHY_CONTROL,
1507 PHY_COM_LANE_RESET_DEASSERT(phy, val));
1512 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1513 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
1514 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
1515 * b. The other bits such as sfr settings / modesel may all
1518 * This should only be done on init and resume from S3 with
1519 * both PLLs disabled, or we risk losing DPIO and PLL
1522 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1526 static void vlv_enable_pll(struct intel_crtc *crtc)
1528 struct drm_device *dev = crtc->base.dev;
1529 struct drm_i915_private *dev_priv = dev->dev_private;
1530 int reg = DPLL(crtc->pipe);
1531 u32 dpll = crtc->config.dpll_hw_state.dpll;
1533 assert_pipe_disabled(dev_priv, crtc->pipe);
1535 /* No really, not for ILK+ */
1536 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1538 /* PLL is protected by panel, make sure we can write it */
1539 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1540 assert_panel_unlocked(dev_priv, crtc->pipe);
1542 I915_WRITE(reg, dpll);
1546 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1547 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1549 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1550 POSTING_READ(DPLL_MD(crtc->pipe));
1552 /* We do this three times for luck */
1553 I915_WRITE(reg, dpll);
1555 udelay(150); /* wait for warmup */
1556 I915_WRITE(reg, dpll);
1558 udelay(150); /* wait for warmup */
1559 I915_WRITE(reg, dpll);
1561 udelay(150); /* wait for warmup */
1564 static void chv_enable_pll(struct intel_crtc *crtc)
1566 struct drm_device *dev = crtc->base.dev;
1567 struct drm_i915_private *dev_priv = dev->dev_private;
1568 int pipe = crtc->pipe;
1569 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1570 int dpll = DPLL(crtc->pipe);
1573 assert_pipe_disabled(dev_priv, crtc->pipe);
1575 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1577 mutex_lock(&dev_priv->dpio_lock);
1579 /* Enable back the 10bit clock to display controller */
1580 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1581 tmp |= DPIO_DCLKP_EN;
1582 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1585 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1590 tmp = I915_READ(dpll);
1591 tmp |= DPLL_VCO_ENABLE;
1592 I915_WRITE(dpll, tmp);
1594 /* Check PLL is locked */
1595 if (wait_for(((I915_READ(dpll) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1596 DRM_ERROR("PLL %d failed to lock\n", pipe);
1598 /* Deassert soft data lane reset*/
1599 tmp = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(port));
1600 tmp |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1601 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), tmp);
1604 mutex_unlock(&dev_priv->dpio_lock);
1607 static void i9xx_enable_pll(struct intel_crtc *crtc)
1609 struct drm_device *dev = crtc->base.dev;
1610 struct drm_i915_private *dev_priv = dev->dev_private;
1611 int reg = DPLL(crtc->pipe);
1612 u32 dpll = crtc->config.dpll_hw_state.dpll;
1614 assert_pipe_disabled(dev_priv, crtc->pipe);
1616 /* No really, not for ILK+ */
1617 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1619 /* PLL is protected by panel, make sure we can write it */
1620 if (IS_MOBILE(dev) && !IS_I830(dev))
1621 assert_panel_unlocked(dev_priv, crtc->pipe);
1623 I915_WRITE(reg, dpll);
1625 /* Wait for the clocks to stabilize. */
1629 if (INTEL_INFO(dev)->gen >= 4) {
1630 I915_WRITE(DPLL_MD(crtc->pipe),
1631 crtc->config.dpll_hw_state.dpll_md);
1633 /* The pixel multiplier can only be updated once the
1634 * DPLL is enabled and the clocks are stable.
1636 * So write it again.
1638 I915_WRITE(reg, dpll);
1641 /* We do this three times for luck */
1642 I915_WRITE(reg, dpll);
1644 udelay(150); /* wait for warmup */
1645 I915_WRITE(reg, dpll);
1647 udelay(150); /* wait for warmup */
1648 I915_WRITE(reg, dpll);
1650 udelay(150); /* wait for warmup */
1654 * i9xx_disable_pll - disable a PLL
1655 * @dev_priv: i915 private structure
1656 * @pipe: pipe PLL to disable
1658 * Disable the PLL for @pipe, making sure the pipe is off first.
1660 * Note! This is for pre-ILK only.
1662 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1664 /* Don't disable pipe A or pipe A PLLs if needed */
1665 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1668 /* Make sure the pipe isn't still relying on us */
1669 assert_pipe_disabled(dev_priv, pipe);
1671 I915_WRITE(DPLL(pipe), 0);
1672 POSTING_READ(DPLL(pipe));
1675 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1679 /* Make sure the pipe isn't still relying on us */
1680 assert_pipe_disabled(dev_priv, pipe);
1683 * Leave integrated clock source and reference clock enabled for pipe B.
1684 * The latter is needed for VGA hotplug / manual detection.
1687 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1688 I915_WRITE(DPLL(pipe), val);
1689 POSTING_READ(DPLL(pipe));
1693 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1695 int dpll = DPLL(pipe);
1698 /* Set PLL en = 0 */
1699 val = I915_READ(dpll);
1700 val &= ~DPLL_VCO_ENABLE;
1701 I915_WRITE(dpll, val);
1705 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1706 struct intel_digital_port *dport)
1711 switch (dport->port) {
1713 port_mask = DPLL_PORTB_READY_MASK;
1717 port_mask = DPLL_PORTC_READY_MASK;
1721 port_mask = DPLL_PORTD_READY_MASK;
1722 dpll_reg = DPIO_PHY_STATUS;
1728 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1729 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1730 port_name(dport->port), I915_READ(dpll_reg));
1734 * ironlake_enable_shared_dpll - enable PCH PLL
1735 * @dev_priv: i915 private structure
1736 * @pipe: pipe PLL to enable
1738 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1739 * drives the transcoder clock.
1741 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1743 struct drm_device *dev = crtc->base.dev;
1744 struct drm_i915_private *dev_priv = dev->dev_private;
1745 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1747 /* PCH PLLs only available on ILK, SNB and IVB */
1748 BUG_ON(INTEL_INFO(dev)->gen < 5);
1749 if (WARN_ON(pll == NULL))
1752 if (WARN_ON(pll->refcount == 0))
1755 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1756 pll->name, pll->active, pll->on,
1757 crtc->base.base.id);
1759 if (pll->active++) {
1761 assert_shared_dpll_enabled(dev_priv, pll);
1766 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1767 pll->enable(dev_priv, pll);
1771 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1773 struct drm_device *dev = crtc->base.dev;
1774 struct drm_i915_private *dev_priv = dev->dev_private;
1775 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1777 /* PCH only available on ILK+ */
1778 BUG_ON(INTEL_INFO(dev)->gen < 5);
1779 if (WARN_ON(pll == NULL))
1782 if (WARN_ON(pll->refcount == 0))
1785 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1786 pll->name, pll->active, pll->on,
1787 crtc->base.base.id);
1789 if (WARN_ON(pll->active == 0)) {
1790 assert_shared_dpll_disabled(dev_priv, pll);
1794 assert_shared_dpll_enabled(dev_priv, pll);
1799 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1800 pll->disable(dev_priv, pll);
1804 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1807 struct drm_device *dev = dev_priv->dev;
1808 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1809 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1810 uint32_t reg, val, pipeconf_val;
1812 /* PCH only available on ILK+ */
1813 BUG_ON(INTEL_INFO(dev)->gen < 5);
1815 /* Make sure PCH DPLL is enabled */
1816 assert_shared_dpll_enabled(dev_priv,
1817 intel_crtc_to_shared_dpll(intel_crtc));
1819 /* FDI must be feeding us bits for PCH ports */
1820 assert_fdi_tx_enabled(dev_priv, pipe);
1821 assert_fdi_rx_enabled(dev_priv, pipe);
1823 if (HAS_PCH_CPT(dev)) {
1824 /* Workaround: Set the timing override bit before enabling the
1825 * pch transcoder. */
1826 reg = TRANS_CHICKEN2(pipe);
1827 val = I915_READ(reg);
1828 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1829 I915_WRITE(reg, val);
1832 reg = PCH_TRANSCONF(pipe);
1833 val = I915_READ(reg);
1834 pipeconf_val = I915_READ(PIPECONF(pipe));
1836 if (HAS_PCH_IBX(dev_priv->dev)) {
1838 * make the BPC in transcoder be consistent with
1839 * that in pipeconf reg.
1841 val &= ~PIPECONF_BPC_MASK;
1842 val |= pipeconf_val & PIPECONF_BPC_MASK;
1845 val &= ~TRANS_INTERLACE_MASK;
1846 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1847 if (HAS_PCH_IBX(dev_priv->dev) &&
1848 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1849 val |= TRANS_LEGACY_INTERLACED_ILK;
1851 val |= TRANS_INTERLACED;
1853 val |= TRANS_PROGRESSIVE;
1855 I915_WRITE(reg, val | TRANS_ENABLE);
1856 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1857 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1860 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1861 enum transcoder cpu_transcoder)
1863 u32 val, pipeconf_val;
1865 /* PCH only available on ILK+ */
1866 BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1868 /* FDI must be feeding us bits for PCH ports */
1869 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1870 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1872 /* Workaround: set timing override bit. */
1873 val = I915_READ(_TRANSA_CHICKEN2);
1874 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1875 I915_WRITE(_TRANSA_CHICKEN2, val);
1878 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1880 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1881 PIPECONF_INTERLACED_ILK)
1882 val |= TRANS_INTERLACED;
1884 val |= TRANS_PROGRESSIVE;
1886 I915_WRITE(LPT_TRANSCONF, val);
1887 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1888 DRM_ERROR("Failed to enable PCH transcoder\n");
1891 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1894 struct drm_device *dev = dev_priv->dev;
1897 /* FDI relies on the transcoder */
1898 assert_fdi_tx_disabled(dev_priv, pipe);
1899 assert_fdi_rx_disabled(dev_priv, pipe);
1901 /* Ports must be off as well */
1902 assert_pch_ports_disabled(dev_priv, pipe);
1904 reg = PCH_TRANSCONF(pipe);
1905 val = I915_READ(reg);
1906 val &= ~TRANS_ENABLE;
1907 I915_WRITE(reg, val);
1908 /* wait for PCH transcoder off, transcoder state */
1909 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1910 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1912 if (!HAS_PCH_IBX(dev)) {
1913 /* Workaround: Clear the timing override chicken bit again. */
1914 reg = TRANS_CHICKEN2(pipe);
1915 val = I915_READ(reg);
1916 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1917 I915_WRITE(reg, val);
1921 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1925 val = I915_READ(LPT_TRANSCONF);
1926 val &= ~TRANS_ENABLE;
1927 I915_WRITE(LPT_TRANSCONF, val);
1928 /* wait for PCH transcoder off, transcoder state */
1929 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1930 DRM_ERROR("Failed to disable PCH transcoder\n");
1932 /* Workaround: clear timing override bit. */
1933 val = I915_READ(_TRANSA_CHICKEN2);
1934 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1935 I915_WRITE(_TRANSA_CHICKEN2, val);
1939 * intel_enable_pipe - enable a pipe, asserting requirements
1940 * @crtc: crtc responsible for the pipe
1942 * Enable @crtc's pipe, making sure that various hardware specific requirements
1943 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1945 static void intel_enable_pipe(struct intel_crtc *crtc)
1947 struct drm_device *dev = crtc->base.dev;
1948 struct drm_i915_private *dev_priv = dev->dev_private;
1949 enum pipe pipe = crtc->pipe;
1950 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1952 enum pipe pch_transcoder;
1956 assert_planes_disabled(dev_priv, pipe);
1957 assert_cursor_disabled(dev_priv, pipe);
1958 assert_sprites_disabled(dev_priv, pipe);
1960 if (HAS_PCH_LPT(dev_priv->dev))
1961 pch_transcoder = TRANSCODER_A;
1963 pch_transcoder = pipe;
1966 * A pipe without a PLL won't actually be able to drive bits from
1967 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1970 if (!HAS_PCH_SPLIT(dev_priv->dev))
1971 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
1972 assert_dsi_pll_enabled(dev_priv);
1974 assert_pll_enabled(dev_priv, pipe);
1976 if (crtc->config.has_pch_encoder) {
1977 /* if driving the PCH, we need FDI enabled */
1978 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1979 assert_fdi_tx_pll_enabled(dev_priv,
1980 (enum pipe) cpu_transcoder);
1982 /* FIXME: assert CPU port conditions for SNB+ */
1985 reg = PIPECONF(cpu_transcoder);
1986 val = I915_READ(reg);
1987 if (val & PIPECONF_ENABLE) {
1988 WARN_ON(!(pipe == PIPE_A &&
1989 dev_priv->quirks & QUIRK_PIPEA_FORCE));
1993 I915_WRITE(reg, val | PIPECONF_ENABLE);
1998 * intel_disable_pipe - disable a pipe, asserting requirements
1999 * @dev_priv: i915 private structure
2000 * @pipe: pipe to disable
2002 * Disable @pipe, making sure that various hardware specific requirements
2003 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
2005 * @pipe should be %PIPE_A or %PIPE_B.
2007 * Will wait until the pipe has shut down before returning.
2009 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
2012 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2018 * Make sure planes won't keep trying to pump pixels to us,
2019 * or we might hang the display.
2021 assert_planes_disabled(dev_priv, pipe);
2022 assert_cursor_disabled(dev_priv, pipe);
2023 assert_sprites_disabled(dev_priv, pipe);
2025 /* Don't disable pipe A or pipe A PLLs if needed */
2026 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2029 reg = PIPECONF(cpu_transcoder);
2030 val = I915_READ(reg);
2031 if ((val & PIPECONF_ENABLE) == 0)
2034 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
2035 intel_wait_for_pipe_off(dev_priv->dev, pipe);
2039 * Plane regs are double buffered, going from enabled->disabled needs a
2040 * trigger in order to latch. The display address reg provides this.
2042 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2045 struct drm_device *dev = dev_priv->dev;
2046 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2048 I915_WRITE(reg, I915_READ(reg));
2053 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2054 * @dev_priv: i915 private structure
2055 * @plane: plane to enable
2056 * @pipe: pipe being fed
2058 * Enable @plane on @pipe, making sure that @pipe is running first.
2060 static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
2061 enum plane plane, enum pipe pipe)
2063 struct intel_crtc *intel_crtc =
2064 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2068 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2069 assert_pipe_enabled(dev_priv, pipe);
2071 if (intel_crtc->primary_enabled)
2074 intel_crtc->primary_enabled = true;
2076 reg = DSPCNTR(plane);
2077 val = I915_READ(reg);
2078 WARN_ON(val & DISPLAY_PLANE_ENABLE);
2080 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
2081 intel_flush_primary_plane(dev_priv, plane);
2082 intel_wait_for_vblank(dev_priv->dev, pipe);
2086 * intel_disable_primary_hw_plane - disable the primary hardware plane
2087 * @dev_priv: i915 private structure
2088 * @plane: plane to disable
2089 * @pipe: pipe consuming the data
2091 * Disable @plane; should be an independent operation.
2093 static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
2094 enum plane plane, enum pipe pipe)
2096 struct intel_crtc *intel_crtc =
2097 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2101 if (!intel_crtc->primary_enabled)
2104 intel_crtc->primary_enabled = false;
2106 reg = DSPCNTR(plane);
2107 val = I915_READ(reg);
2108 WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0);
2110 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
2111 intel_flush_primary_plane(dev_priv, plane);
2112 intel_wait_for_vblank(dev_priv->dev, pipe);
2115 static bool need_vtd_wa(struct drm_device *dev)
2117 #ifdef CONFIG_INTEL_IOMMU
2118 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2124 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2128 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2129 return ALIGN(height, tile_height);
2133 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2134 struct drm_i915_gem_object *obj,
2135 struct intel_ring_buffer *pipelined)
2137 struct drm_i915_private *dev_priv = dev->dev_private;
2141 switch (obj->tiling_mode) {
2142 case I915_TILING_NONE:
2143 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2144 alignment = 128 * 1024;
2145 else if (INTEL_INFO(dev)->gen >= 4)
2146 alignment = 4 * 1024;
2148 alignment = 64 * 1024;
2151 /* pin() will align the object as required by fence */
2155 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2161 /* Note that the w/a also requires 64 PTE of padding following the
2162 * bo. We currently fill all unused PTE with the shadow page and so
2163 * we should always have valid PTE following the scanout preventing
2166 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2167 alignment = 256 * 1024;
2169 dev_priv->mm.interruptible = false;
2170 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2172 goto err_interruptible;
2174 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2175 * fence, whereas 965+ only requires a fence if using
2176 * framebuffer compression. For simplicity, we always install
2177 * a fence as the cost is not that onerous.
2179 ret = i915_gem_object_get_fence(obj);
2183 i915_gem_object_pin_fence(obj);
2185 dev_priv->mm.interruptible = true;
2189 i915_gem_object_unpin_from_display_plane(obj);
2191 dev_priv->mm.interruptible = true;
2195 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2197 i915_gem_object_unpin_fence(obj);
2198 i915_gem_object_unpin_from_display_plane(obj);
2201 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2202 * is assumed to be a power-of-two. */
2203 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2204 unsigned int tiling_mode,
2208 if (tiling_mode != I915_TILING_NONE) {
2209 unsigned int tile_rows, tiles;
2214 tiles = *x / (512/cpp);
2217 return tile_rows * pitch * 8 + tiles * 4096;
2219 unsigned int offset;
2221 offset = *y * pitch + *x * cpp;
2223 *x = (offset & 4095) / cpp;
2224 return offset & -4096;
2228 int intel_format_to_fourcc(int format)
2231 case DISPPLANE_8BPP:
2232 return DRM_FORMAT_C8;
2233 case DISPPLANE_BGRX555:
2234 return DRM_FORMAT_XRGB1555;
2235 case DISPPLANE_BGRX565:
2236 return DRM_FORMAT_RGB565;
2238 case DISPPLANE_BGRX888:
2239 return DRM_FORMAT_XRGB8888;
2240 case DISPPLANE_RGBX888:
2241 return DRM_FORMAT_XBGR8888;
2242 case DISPPLANE_BGRX101010:
2243 return DRM_FORMAT_XRGB2101010;
2244 case DISPPLANE_RGBX101010:
2245 return DRM_FORMAT_XBGR2101010;
2249 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2250 struct intel_plane_config *plane_config)
2252 struct drm_device *dev = crtc->base.dev;
2253 struct drm_i915_gem_object *obj = NULL;
2254 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2255 u32 base = plane_config->base;
2257 if (plane_config->size == 0)
2260 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2261 plane_config->size);
2265 if (plane_config->tiled) {
2266 obj->tiling_mode = I915_TILING_X;
2267 obj->stride = crtc->base.primary->fb->pitches[0];
2270 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2271 mode_cmd.width = crtc->base.primary->fb->width;
2272 mode_cmd.height = crtc->base.primary->fb->height;
2273 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2275 mutex_lock(&dev->struct_mutex);
2277 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2279 DRM_DEBUG_KMS("intel fb init failed\n");
2283 mutex_unlock(&dev->struct_mutex);
2285 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2289 drm_gem_object_unreference(&obj->base);
2290 mutex_unlock(&dev->struct_mutex);
2294 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2295 struct intel_plane_config *plane_config)
2297 struct drm_device *dev = intel_crtc->base.dev;
2299 struct intel_crtc *i;
2300 struct intel_framebuffer *fb;
2302 if (!intel_crtc->base.primary->fb)
2305 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2308 kfree(intel_crtc->base.primary->fb);
2309 intel_crtc->base.primary->fb = NULL;
2312 * Failed to alloc the obj, check to see if we should share
2313 * an fb with another CRTC instead
2315 for_each_crtc(dev, c) {
2316 i = to_intel_crtc(c);
2318 if (c == &intel_crtc->base)
2321 if (!i->active || !c->primary->fb)
2324 fb = to_intel_framebuffer(c->primary->fb);
2325 if (i915_gem_obj_ggtt_offset(fb->obj) == plane_config->base) {
2326 drm_framebuffer_reference(c->primary->fb);
2327 intel_crtc->base.primary->fb = c->primary->fb;
2333 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2334 struct drm_framebuffer *fb,
2337 struct drm_device *dev = crtc->dev;
2338 struct drm_i915_private *dev_priv = dev->dev_private;
2339 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2340 struct intel_framebuffer *intel_fb;
2341 struct drm_i915_gem_object *obj;
2342 int plane = intel_crtc->plane;
2343 unsigned long linear_offset;
2347 intel_fb = to_intel_framebuffer(fb);
2348 obj = intel_fb->obj;
2350 reg = DSPCNTR(plane);
2351 dspcntr = I915_READ(reg);
2352 /* Mask out pixel format bits in case we change it */
2353 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2354 switch (fb->pixel_format) {
2356 dspcntr |= DISPPLANE_8BPP;
2358 case DRM_FORMAT_XRGB1555:
2359 case DRM_FORMAT_ARGB1555:
2360 dspcntr |= DISPPLANE_BGRX555;
2362 case DRM_FORMAT_RGB565:
2363 dspcntr |= DISPPLANE_BGRX565;
2365 case DRM_FORMAT_XRGB8888:
2366 case DRM_FORMAT_ARGB8888:
2367 dspcntr |= DISPPLANE_BGRX888;
2369 case DRM_FORMAT_XBGR8888:
2370 case DRM_FORMAT_ABGR8888:
2371 dspcntr |= DISPPLANE_RGBX888;
2373 case DRM_FORMAT_XRGB2101010:
2374 case DRM_FORMAT_ARGB2101010:
2375 dspcntr |= DISPPLANE_BGRX101010;
2377 case DRM_FORMAT_XBGR2101010:
2378 case DRM_FORMAT_ABGR2101010:
2379 dspcntr |= DISPPLANE_RGBX101010;
2385 if (INTEL_INFO(dev)->gen >= 4) {
2386 if (obj->tiling_mode != I915_TILING_NONE)
2387 dspcntr |= DISPPLANE_TILED;
2389 dspcntr &= ~DISPPLANE_TILED;
2393 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2395 I915_WRITE(reg, dspcntr);
2397 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2399 if (INTEL_INFO(dev)->gen >= 4) {
2400 intel_crtc->dspaddr_offset =
2401 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2402 fb->bits_per_pixel / 8,
2404 linear_offset -= intel_crtc->dspaddr_offset;
2406 intel_crtc->dspaddr_offset = linear_offset;
2409 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2410 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2412 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2413 if (INTEL_INFO(dev)->gen >= 4) {
2414 I915_WRITE(DSPSURF(plane),
2415 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2416 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2417 I915_WRITE(DSPLINOFF(plane), linear_offset);
2419 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2423 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2424 struct drm_framebuffer *fb,
2427 struct drm_device *dev = crtc->dev;
2428 struct drm_i915_private *dev_priv = dev->dev_private;
2429 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2430 struct intel_framebuffer *intel_fb;
2431 struct drm_i915_gem_object *obj;
2432 int plane = intel_crtc->plane;
2433 unsigned long linear_offset;
2437 intel_fb = to_intel_framebuffer(fb);
2438 obj = intel_fb->obj;
2440 reg = DSPCNTR(plane);
2441 dspcntr = I915_READ(reg);
2442 /* Mask out pixel format bits in case we change it */
2443 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2444 switch (fb->pixel_format) {
2446 dspcntr |= DISPPLANE_8BPP;
2448 case DRM_FORMAT_RGB565:
2449 dspcntr |= DISPPLANE_BGRX565;
2451 case DRM_FORMAT_XRGB8888:
2452 case DRM_FORMAT_ARGB8888:
2453 dspcntr |= DISPPLANE_BGRX888;
2455 case DRM_FORMAT_XBGR8888:
2456 case DRM_FORMAT_ABGR8888:
2457 dspcntr |= DISPPLANE_RGBX888;
2459 case DRM_FORMAT_XRGB2101010:
2460 case DRM_FORMAT_ARGB2101010:
2461 dspcntr |= DISPPLANE_BGRX101010;
2463 case DRM_FORMAT_XBGR2101010:
2464 case DRM_FORMAT_ABGR2101010:
2465 dspcntr |= DISPPLANE_RGBX101010;
2471 if (obj->tiling_mode != I915_TILING_NONE)
2472 dspcntr |= DISPPLANE_TILED;
2474 dspcntr &= ~DISPPLANE_TILED;
2476 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2477 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2479 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2481 I915_WRITE(reg, dspcntr);
2483 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2484 intel_crtc->dspaddr_offset =
2485 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2486 fb->bits_per_pixel / 8,
2488 linear_offset -= intel_crtc->dspaddr_offset;
2490 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2491 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2493 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2494 I915_WRITE(DSPSURF(plane),
2495 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2496 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2497 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2499 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2500 I915_WRITE(DSPLINOFF(plane), linear_offset);
2505 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2507 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2508 int x, int y, enum mode_set_atomic state)
2510 struct drm_device *dev = crtc->dev;
2511 struct drm_i915_private *dev_priv = dev->dev_private;
2513 if (dev_priv->display.disable_fbc)
2514 dev_priv->display.disable_fbc(dev);
2515 intel_increase_pllclock(crtc);
2517 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2522 void intel_display_handle_reset(struct drm_device *dev)
2524 struct drm_i915_private *dev_priv = dev->dev_private;
2525 struct drm_crtc *crtc;
2528 * Flips in the rings have been nuked by the reset,
2529 * so complete all pending flips so that user space
2530 * will get its events and not get stuck.
2532 * Also update the base address of all primary
2533 * planes to the the last fb to make sure we're
2534 * showing the correct fb after a reset.
2536 * Need to make two loops over the crtcs so that we
2537 * don't try to grab a crtc mutex before the
2538 * pending_flip_queue really got woken up.
2541 for_each_crtc(dev, crtc) {
2542 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2543 enum plane plane = intel_crtc->plane;
2545 intel_prepare_page_flip(dev, plane);
2546 intel_finish_page_flip_plane(dev, plane);
2549 for_each_crtc(dev, crtc) {
2550 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2552 mutex_lock(&crtc->mutex);
2554 * FIXME: Once we have proper support for primary planes (and
2555 * disabling them without disabling the entire crtc) allow again
2556 * a NULL crtc->primary->fb.
2558 if (intel_crtc->active && crtc->primary->fb)
2559 dev_priv->display.update_primary_plane(crtc,
2563 mutex_unlock(&crtc->mutex);
2568 intel_finish_fb(struct drm_framebuffer *old_fb)
2570 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2571 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2572 bool was_interruptible = dev_priv->mm.interruptible;
2575 /* Big Hammer, we also need to ensure that any pending
2576 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2577 * current scanout is retired before unpinning the old
2580 * This should only fail upon a hung GPU, in which case we
2581 * can safely continue.
2583 dev_priv->mm.interruptible = false;
2584 ret = i915_gem_object_finish_gpu(obj);
2585 dev_priv->mm.interruptible = was_interruptible;
2590 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2592 struct drm_device *dev = crtc->dev;
2593 struct drm_i915_private *dev_priv = dev->dev_private;
2594 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2595 unsigned long flags;
2598 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2599 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2602 spin_lock_irqsave(&dev->event_lock, flags);
2603 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2604 spin_unlock_irqrestore(&dev->event_lock, flags);
2610 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2611 struct drm_framebuffer *fb)
2613 struct drm_device *dev = crtc->dev;
2614 struct drm_i915_private *dev_priv = dev->dev_private;
2615 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2616 struct drm_framebuffer *old_fb;
2619 if (intel_crtc_has_pending_flip(crtc)) {
2620 DRM_ERROR("pipe is still busy with an old pageflip\n");
2626 DRM_ERROR("No FB bound\n");
2630 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2631 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2632 plane_name(intel_crtc->plane),
2633 INTEL_INFO(dev)->num_pipes);
2637 mutex_lock(&dev->struct_mutex);
2638 ret = intel_pin_and_fence_fb_obj(dev,
2639 to_intel_framebuffer(fb)->obj,
2641 mutex_unlock(&dev->struct_mutex);
2643 DRM_ERROR("pin & fence failed\n");
2648 * Update pipe size and adjust fitter if needed: the reason for this is
2649 * that in compute_mode_changes we check the native mode (not the pfit
2650 * mode) to see if we can flip rather than do a full mode set. In the
2651 * fastboot case, we'll flip, but if we don't update the pipesrc and
2652 * pfit state, we'll end up with a big fb scanned out into the wrong
2655 * To fix this properly, we need to hoist the checks up into
2656 * compute_mode_changes (or above), check the actual pfit state and
2657 * whether the platform allows pfit disable with pipe active, and only
2658 * then update the pipesrc and pfit state, even on the flip path.
2660 if (i915.fastboot) {
2661 const struct drm_display_mode *adjusted_mode =
2662 &intel_crtc->config.adjusted_mode;
2664 I915_WRITE(PIPESRC(intel_crtc->pipe),
2665 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2666 (adjusted_mode->crtc_vdisplay - 1));
2667 if (!intel_crtc->config.pch_pfit.enabled &&
2668 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2669 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2670 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2671 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2672 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2674 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2675 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2678 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2680 old_fb = crtc->primary->fb;
2681 crtc->primary->fb = fb;
2686 if (intel_crtc->active && old_fb != fb)
2687 intel_wait_for_vblank(dev, intel_crtc->pipe);
2688 mutex_lock(&dev->struct_mutex);
2689 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2690 mutex_unlock(&dev->struct_mutex);
2693 mutex_lock(&dev->struct_mutex);
2694 intel_update_fbc(dev);
2695 intel_edp_psr_update(dev);
2696 mutex_unlock(&dev->struct_mutex);
2701 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2703 struct drm_device *dev = crtc->dev;
2704 struct drm_i915_private *dev_priv = dev->dev_private;
2705 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2706 int pipe = intel_crtc->pipe;
2709 /* enable normal train */
2710 reg = FDI_TX_CTL(pipe);
2711 temp = I915_READ(reg);
2712 if (IS_IVYBRIDGE(dev)) {
2713 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2714 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2716 temp &= ~FDI_LINK_TRAIN_NONE;
2717 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2719 I915_WRITE(reg, temp);
2721 reg = FDI_RX_CTL(pipe);
2722 temp = I915_READ(reg);
2723 if (HAS_PCH_CPT(dev)) {
2724 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2725 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2727 temp &= ~FDI_LINK_TRAIN_NONE;
2728 temp |= FDI_LINK_TRAIN_NONE;
2730 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2732 /* wait one idle pattern time */
2736 /* IVB wants error correction enabled */
2737 if (IS_IVYBRIDGE(dev))
2738 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2739 FDI_FE_ERRC_ENABLE);
2742 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2744 return crtc->base.enabled && crtc->active &&
2745 crtc->config.has_pch_encoder;
2748 static void ivb_modeset_global_resources(struct drm_device *dev)
2750 struct drm_i915_private *dev_priv = dev->dev_private;
2751 struct intel_crtc *pipe_B_crtc =
2752 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2753 struct intel_crtc *pipe_C_crtc =
2754 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2758 * When everything is off disable fdi C so that we could enable fdi B
2759 * with all lanes. Note that we don't care about enabled pipes without
2760 * an enabled pch encoder.
2762 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2763 !pipe_has_enabled_pch(pipe_C_crtc)) {
2764 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2765 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2767 temp = I915_READ(SOUTH_CHICKEN1);
2768 temp &= ~FDI_BC_BIFURCATION_SELECT;
2769 DRM_DEBUG_KMS("disabling fdi C rx\n");
2770 I915_WRITE(SOUTH_CHICKEN1, temp);
2774 /* The FDI link training functions for ILK/Ibexpeak. */
2775 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2777 struct drm_device *dev = crtc->dev;
2778 struct drm_i915_private *dev_priv = dev->dev_private;
2779 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2780 int pipe = intel_crtc->pipe;
2781 u32 reg, temp, tries;
2783 /* FDI needs bits from pipe first */
2784 assert_pipe_enabled(dev_priv, pipe);
2786 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2788 reg = FDI_RX_IMR(pipe);
2789 temp = I915_READ(reg);
2790 temp &= ~FDI_RX_SYMBOL_LOCK;
2791 temp &= ~FDI_RX_BIT_LOCK;
2792 I915_WRITE(reg, temp);
2796 /* enable CPU FDI TX and PCH FDI RX */
2797 reg = FDI_TX_CTL(pipe);
2798 temp = I915_READ(reg);
2799 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2800 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2801 temp &= ~FDI_LINK_TRAIN_NONE;
2802 temp |= FDI_LINK_TRAIN_PATTERN_1;
2803 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2805 reg = FDI_RX_CTL(pipe);
2806 temp = I915_READ(reg);
2807 temp &= ~FDI_LINK_TRAIN_NONE;
2808 temp |= FDI_LINK_TRAIN_PATTERN_1;
2809 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2814 /* Ironlake workaround, enable clock pointer after FDI enable*/
2815 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2816 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2817 FDI_RX_PHASE_SYNC_POINTER_EN);
2819 reg = FDI_RX_IIR(pipe);
2820 for (tries = 0; tries < 5; tries++) {
2821 temp = I915_READ(reg);
2822 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2824 if ((temp & FDI_RX_BIT_LOCK)) {
2825 DRM_DEBUG_KMS("FDI train 1 done.\n");
2826 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2831 DRM_ERROR("FDI train 1 fail!\n");
2834 reg = FDI_TX_CTL(pipe);
2835 temp = I915_READ(reg);
2836 temp &= ~FDI_LINK_TRAIN_NONE;
2837 temp |= FDI_LINK_TRAIN_PATTERN_2;
2838 I915_WRITE(reg, temp);
2840 reg = FDI_RX_CTL(pipe);
2841 temp = I915_READ(reg);
2842 temp &= ~FDI_LINK_TRAIN_NONE;
2843 temp |= FDI_LINK_TRAIN_PATTERN_2;
2844 I915_WRITE(reg, temp);
2849 reg = FDI_RX_IIR(pipe);
2850 for (tries = 0; tries < 5; tries++) {
2851 temp = I915_READ(reg);
2852 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2854 if (temp & FDI_RX_SYMBOL_LOCK) {
2855 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2856 DRM_DEBUG_KMS("FDI train 2 done.\n");
2861 DRM_ERROR("FDI train 2 fail!\n");
2863 DRM_DEBUG_KMS("FDI train done\n");
2867 static const int snb_b_fdi_train_param[] = {
2868 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2869 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2870 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2871 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2874 /* The FDI link training functions for SNB/Cougarpoint. */
2875 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2877 struct drm_device *dev = crtc->dev;
2878 struct drm_i915_private *dev_priv = dev->dev_private;
2879 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2880 int pipe = intel_crtc->pipe;
2881 u32 reg, temp, i, retry;
2883 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2885 reg = FDI_RX_IMR(pipe);
2886 temp = I915_READ(reg);
2887 temp &= ~FDI_RX_SYMBOL_LOCK;
2888 temp &= ~FDI_RX_BIT_LOCK;
2889 I915_WRITE(reg, temp);
2894 /* enable CPU FDI TX and PCH FDI RX */
2895 reg = FDI_TX_CTL(pipe);
2896 temp = I915_READ(reg);
2897 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2898 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2899 temp &= ~FDI_LINK_TRAIN_NONE;
2900 temp |= FDI_LINK_TRAIN_PATTERN_1;
2901 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2903 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2904 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2906 I915_WRITE(FDI_RX_MISC(pipe),
2907 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2909 reg = FDI_RX_CTL(pipe);
2910 temp = I915_READ(reg);
2911 if (HAS_PCH_CPT(dev)) {
2912 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2913 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2915 temp &= ~FDI_LINK_TRAIN_NONE;
2916 temp |= FDI_LINK_TRAIN_PATTERN_1;
2918 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2923 for (i = 0; i < 4; i++) {
2924 reg = FDI_TX_CTL(pipe);
2925 temp = I915_READ(reg);
2926 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2927 temp |= snb_b_fdi_train_param[i];
2928 I915_WRITE(reg, temp);
2933 for (retry = 0; retry < 5; retry++) {
2934 reg = FDI_RX_IIR(pipe);
2935 temp = I915_READ(reg);
2936 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2937 if (temp & FDI_RX_BIT_LOCK) {
2938 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2939 DRM_DEBUG_KMS("FDI train 1 done.\n");
2948 DRM_ERROR("FDI train 1 fail!\n");
2951 reg = FDI_TX_CTL(pipe);
2952 temp = I915_READ(reg);
2953 temp &= ~FDI_LINK_TRAIN_NONE;
2954 temp |= FDI_LINK_TRAIN_PATTERN_2;
2956 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2958 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2960 I915_WRITE(reg, temp);
2962 reg = FDI_RX_CTL(pipe);
2963 temp = I915_READ(reg);
2964 if (HAS_PCH_CPT(dev)) {
2965 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2966 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2968 temp &= ~FDI_LINK_TRAIN_NONE;
2969 temp |= FDI_LINK_TRAIN_PATTERN_2;
2971 I915_WRITE(reg, temp);
2976 for (i = 0; i < 4; i++) {
2977 reg = FDI_TX_CTL(pipe);
2978 temp = I915_READ(reg);
2979 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2980 temp |= snb_b_fdi_train_param[i];
2981 I915_WRITE(reg, temp);
2986 for (retry = 0; retry < 5; retry++) {
2987 reg = FDI_RX_IIR(pipe);
2988 temp = I915_READ(reg);
2989 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2990 if (temp & FDI_RX_SYMBOL_LOCK) {
2991 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2992 DRM_DEBUG_KMS("FDI train 2 done.\n");
3001 DRM_ERROR("FDI train 2 fail!\n");
3003 DRM_DEBUG_KMS("FDI train done.\n");
3006 /* Manual link training for Ivy Bridge A0 parts */
3007 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3009 struct drm_device *dev = crtc->dev;
3010 struct drm_i915_private *dev_priv = dev->dev_private;
3011 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3012 int pipe = intel_crtc->pipe;
3013 u32 reg, temp, i, j;
3015 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3017 reg = FDI_RX_IMR(pipe);
3018 temp = I915_READ(reg);
3019 temp &= ~FDI_RX_SYMBOL_LOCK;
3020 temp &= ~FDI_RX_BIT_LOCK;
3021 I915_WRITE(reg, temp);
3026 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3027 I915_READ(FDI_RX_IIR(pipe)));
3029 /* Try each vswing and preemphasis setting twice before moving on */
3030 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3031 /* disable first in case we need to retry */
3032 reg = FDI_TX_CTL(pipe);
3033 temp = I915_READ(reg);
3034 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3035 temp &= ~FDI_TX_ENABLE;
3036 I915_WRITE(reg, temp);
3038 reg = FDI_RX_CTL(pipe);
3039 temp = I915_READ(reg);
3040 temp &= ~FDI_LINK_TRAIN_AUTO;
3041 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3042 temp &= ~FDI_RX_ENABLE;
3043 I915_WRITE(reg, temp);
3045 /* enable CPU FDI TX and PCH FDI RX */
3046 reg = FDI_TX_CTL(pipe);
3047 temp = I915_READ(reg);
3048 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3049 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3050 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3051 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3052 temp |= snb_b_fdi_train_param[j/2];
3053 temp |= FDI_COMPOSITE_SYNC;
3054 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3056 I915_WRITE(FDI_RX_MISC(pipe),
3057 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3059 reg = FDI_RX_CTL(pipe);
3060 temp = I915_READ(reg);
3061 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3062 temp |= FDI_COMPOSITE_SYNC;
3063 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3066 udelay(1); /* should be 0.5us */
3068 for (i = 0; i < 4; i++) {
3069 reg = FDI_RX_IIR(pipe);
3070 temp = I915_READ(reg);
3071 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3073 if (temp & FDI_RX_BIT_LOCK ||
3074 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3075 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3076 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3080 udelay(1); /* should be 0.5us */
3083 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3088 reg = FDI_TX_CTL(pipe);
3089 temp = I915_READ(reg);
3090 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3091 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3092 I915_WRITE(reg, temp);
3094 reg = FDI_RX_CTL(pipe);
3095 temp = I915_READ(reg);
3096 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3097 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3098 I915_WRITE(reg, temp);
3101 udelay(2); /* should be 1.5us */
3103 for (i = 0; i < 4; i++) {
3104 reg = FDI_RX_IIR(pipe);
3105 temp = I915_READ(reg);
3106 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3108 if (temp & FDI_RX_SYMBOL_LOCK ||
3109 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3110 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3111 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3115 udelay(2); /* should be 1.5us */
3118 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3122 DRM_DEBUG_KMS("FDI train done.\n");
3125 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3127 struct drm_device *dev = intel_crtc->base.dev;
3128 struct drm_i915_private *dev_priv = dev->dev_private;
3129 int pipe = intel_crtc->pipe;
3133 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3134 reg = FDI_RX_CTL(pipe);
3135 temp = I915_READ(reg);
3136 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3137 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3138 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3139 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3144 /* Switch from Rawclk to PCDclk */
3145 temp = I915_READ(reg);
3146 I915_WRITE(reg, temp | FDI_PCDCLK);
3151 /* Enable CPU FDI TX PLL, always on for Ironlake */
3152 reg = FDI_TX_CTL(pipe);
3153 temp = I915_READ(reg);
3154 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3155 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3162 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3164 struct drm_device *dev = intel_crtc->base.dev;
3165 struct drm_i915_private *dev_priv = dev->dev_private;
3166 int pipe = intel_crtc->pipe;
3169 /* Switch from PCDclk to Rawclk */
3170 reg = FDI_RX_CTL(pipe);
3171 temp = I915_READ(reg);
3172 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3174 /* Disable CPU FDI TX PLL */
3175 reg = FDI_TX_CTL(pipe);
3176 temp = I915_READ(reg);
3177 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3182 reg = FDI_RX_CTL(pipe);
3183 temp = I915_READ(reg);
3184 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3186 /* Wait for the clocks to turn off. */
3191 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3193 struct drm_device *dev = crtc->dev;
3194 struct drm_i915_private *dev_priv = dev->dev_private;
3195 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3196 int pipe = intel_crtc->pipe;
3199 /* disable CPU FDI tx and PCH FDI rx */
3200 reg = FDI_TX_CTL(pipe);
3201 temp = I915_READ(reg);
3202 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3205 reg = FDI_RX_CTL(pipe);
3206 temp = I915_READ(reg);
3207 temp &= ~(0x7 << 16);
3208 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3209 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3214 /* Ironlake workaround, disable clock pointer after downing FDI */
3215 if (HAS_PCH_IBX(dev))
3216 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3218 /* still set train pattern 1 */
3219 reg = FDI_TX_CTL(pipe);
3220 temp = I915_READ(reg);
3221 temp &= ~FDI_LINK_TRAIN_NONE;
3222 temp |= FDI_LINK_TRAIN_PATTERN_1;
3223 I915_WRITE(reg, temp);
3225 reg = FDI_RX_CTL(pipe);
3226 temp = I915_READ(reg);
3227 if (HAS_PCH_CPT(dev)) {
3228 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3229 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3231 temp &= ~FDI_LINK_TRAIN_NONE;
3232 temp |= FDI_LINK_TRAIN_PATTERN_1;
3234 /* BPC in FDI rx is consistent with that in PIPECONF */
3235 temp &= ~(0x07 << 16);
3236 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3237 I915_WRITE(reg, temp);
3243 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3245 struct intel_crtc *crtc;
3247 /* Note that we don't need to be called with mode_config.lock here
3248 * as our list of CRTC objects is static for the lifetime of the
3249 * device and so cannot disappear as we iterate. Similarly, we can
3250 * happily treat the predicates as racy, atomic checks as userspace
3251 * cannot claim and pin a new fb without at least acquring the
3252 * struct_mutex and so serialising with us.
3254 for_each_intel_crtc(dev, crtc) {
3255 if (atomic_read(&crtc->unpin_work_count) == 0)
3258 if (crtc->unpin_work)
3259 intel_wait_for_vblank(dev, crtc->pipe);
3267 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3269 struct drm_device *dev = crtc->dev;
3270 struct drm_i915_private *dev_priv = dev->dev_private;
3272 if (crtc->primary->fb == NULL)
3275 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3277 wait_event(dev_priv->pending_flip_queue,
3278 !intel_crtc_has_pending_flip(crtc));
3280 mutex_lock(&dev->struct_mutex);
3281 intel_finish_fb(crtc->primary->fb);
3282 mutex_unlock(&dev->struct_mutex);
3285 /* Program iCLKIP clock to the desired frequency */
3286 static void lpt_program_iclkip(struct drm_crtc *crtc)
3288 struct drm_device *dev = crtc->dev;
3289 struct drm_i915_private *dev_priv = dev->dev_private;
3290 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3291 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3294 mutex_lock(&dev_priv->dpio_lock);
3296 /* It is necessary to ungate the pixclk gate prior to programming
3297 * the divisors, and gate it back when it is done.
3299 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3301 /* Disable SSCCTL */
3302 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3303 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3307 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3308 if (clock == 20000) {
3313 /* The iCLK virtual clock root frequency is in MHz,
3314 * but the adjusted_mode->crtc_clock in in KHz. To get the
3315 * divisors, it is necessary to divide one by another, so we
3316 * convert the virtual clock precision to KHz here for higher
3319 u32 iclk_virtual_root_freq = 172800 * 1000;
3320 u32 iclk_pi_range = 64;
3321 u32 desired_divisor, msb_divisor_value, pi_value;
3323 desired_divisor = (iclk_virtual_root_freq / clock);
3324 msb_divisor_value = desired_divisor / iclk_pi_range;
3325 pi_value = desired_divisor % iclk_pi_range;
3328 divsel = msb_divisor_value - 2;
3329 phaseinc = pi_value;
3332 /* This should not happen with any sane values */
3333 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3334 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3335 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3336 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3338 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3345 /* Program SSCDIVINTPHASE6 */
3346 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3347 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3348 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3349 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3350 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3351 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3352 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3353 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3355 /* Program SSCAUXDIV */
3356 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3357 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3358 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3359 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3361 /* Enable modulator and associated divider */
3362 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3363 temp &= ~SBI_SSCCTL_DISABLE;
3364 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3366 /* Wait for initialization time */
3369 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3371 mutex_unlock(&dev_priv->dpio_lock);
3374 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3375 enum pipe pch_transcoder)
3377 struct drm_device *dev = crtc->base.dev;
3378 struct drm_i915_private *dev_priv = dev->dev_private;
3379 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3381 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3382 I915_READ(HTOTAL(cpu_transcoder)));
3383 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3384 I915_READ(HBLANK(cpu_transcoder)));
3385 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3386 I915_READ(HSYNC(cpu_transcoder)));
3388 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3389 I915_READ(VTOTAL(cpu_transcoder)));
3390 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3391 I915_READ(VBLANK(cpu_transcoder)));
3392 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3393 I915_READ(VSYNC(cpu_transcoder)));
3394 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3395 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3398 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3400 struct drm_i915_private *dev_priv = dev->dev_private;
3403 temp = I915_READ(SOUTH_CHICKEN1);
3404 if (temp & FDI_BC_BIFURCATION_SELECT)
3407 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3408 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3410 temp |= FDI_BC_BIFURCATION_SELECT;
3411 DRM_DEBUG_KMS("enabling fdi C rx\n");
3412 I915_WRITE(SOUTH_CHICKEN1, temp);
3413 POSTING_READ(SOUTH_CHICKEN1);
3416 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3418 struct drm_device *dev = intel_crtc->base.dev;
3419 struct drm_i915_private *dev_priv = dev->dev_private;
3421 switch (intel_crtc->pipe) {
3425 if (intel_crtc->config.fdi_lanes > 2)
3426 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3428 cpt_enable_fdi_bc_bifurcation(dev);
3432 cpt_enable_fdi_bc_bifurcation(dev);
3441 * Enable PCH resources required for PCH ports:
3443 * - FDI training & RX/TX
3444 * - update transcoder timings
3445 * - DP transcoding bits
3448 static void ironlake_pch_enable(struct drm_crtc *crtc)
3450 struct drm_device *dev = crtc->dev;
3451 struct drm_i915_private *dev_priv = dev->dev_private;
3452 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3453 int pipe = intel_crtc->pipe;
3456 assert_pch_transcoder_disabled(dev_priv, pipe);
3458 if (IS_IVYBRIDGE(dev))
3459 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3461 /* Write the TU size bits before fdi link training, so that error
3462 * detection works. */
3463 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3464 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3466 /* For PCH output, training FDI link */
3467 dev_priv->display.fdi_link_train(crtc);
3469 /* We need to program the right clock selection before writing the pixel
3470 * mutliplier into the DPLL. */
3471 if (HAS_PCH_CPT(dev)) {
3474 temp = I915_READ(PCH_DPLL_SEL);
3475 temp |= TRANS_DPLL_ENABLE(pipe);
3476 sel = TRANS_DPLLB_SEL(pipe);
3477 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3481 I915_WRITE(PCH_DPLL_SEL, temp);
3484 /* XXX: pch pll's can be enabled any time before we enable the PCH
3485 * transcoder, and we actually should do this to not upset any PCH
3486 * transcoder that already use the clock when we share it.
3488 * Note that enable_shared_dpll tries to do the right thing, but
3489 * get_shared_dpll unconditionally resets the pll - we need that to have
3490 * the right LVDS enable sequence. */
3491 ironlake_enable_shared_dpll(intel_crtc);
3493 /* set transcoder timing, panel must allow it */
3494 assert_panel_unlocked(dev_priv, pipe);
3495 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3497 intel_fdi_normal_train(crtc);
3499 /* For PCH DP, enable TRANS_DP_CTL */
3500 if (HAS_PCH_CPT(dev) &&
3501 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3502 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3503 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3504 reg = TRANS_DP_CTL(pipe);
3505 temp = I915_READ(reg);
3506 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3507 TRANS_DP_SYNC_MASK |
3509 temp |= (TRANS_DP_OUTPUT_ENABLE |
3510 TRANS_DP_ENH_FRAMING);
3511 temp |= bpc << 9; /* same format but at 11:9 */
3513 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3514 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3515 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3516 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3518 switch (intel_trans_dp_port_sel(crtc)) {
3520 temp |= TRANS_DP_PORT_SEL_B;
3523 temp |= TRANS_DP_PORT_SEL_C;
3526 temp |= TRANS_DP_PORT_SEL_D;
3532 I915_WRITE(reg, temp);
3535 ironlake_enable_pch_transcoder(dev_priv, pipe);
3538 static void lpt_pch_enable(struct drm_crtc *crtc)
3540 struct drm_device *dev = crtc->dev;
3541 struct drm_i915_private *dev_priv = dev->dev_private;
3542 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3543 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3545 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3547 lpt_program_iclkip(crtc);
3549 /* Set transcoder timing. */
3550 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3552 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3555 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3557 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3562 if (pll->refcount == 0) {
3563 WARN(1, "bad %s refcount\n", pll->name);
3567 if (--pll->refcount == 0) {
3569 WARN_ON(pll->active);
3572 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3575 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3577 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3578 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3579 enum intel_dpll_id i;
3582 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3583 crtc->base.base.id, pll->name);
3584 intel_put_shared_dpll(crtc);
3587 if (HAS_PCH_IBX(dev_priv->dev)) {
3588 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3589 i = (enum intel_dpll_id) crtc->pipe;
3590 pll = &dev_priv->shared_dplls[i];
3592 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3593 crtc->base.base.id, pll->name);
3598 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3599 pll = &dev_priv->shared_dplls[i];
3601 /* Only want to check enabled timings first */
3602 if (pll->refcount == 0)
3605 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3606 sizeof(pll->hw_state)) == 0) {
3607 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3609 pll->name, pll->refcount, pll->active);
3615 /* Ok no matching timings, maybe there's a free one? */
3616 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3617 pll = &dev_priv->shared_dplls[i];
3618 if (pll->refcount == 0) {
3619 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3620 crtc->base.base.id, pll->name);
3628 crtc->config.shared_dpll = i;
3629 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3630 pipe_name(crtc->pipe));
3632 if (pll->active == 0) {
3633 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3634 sizeof(pll->hw_state));
3636 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3638 assert_shared_dpll_disabled(dev_priv, pll);
3640 pll->mode_set(dev_priv, pll);
3647 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3649 struct drm_i915_private *dev_priv = dev->dev_private;
3650 int dslreg = PIPEDSL(pipe);
3653 temp = I915_READ(dslreg);
3655 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3656 if (wait_for(I915_READ(dslreg) != temp, 5))
3657 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3661 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3663 struct drm_device *dev = crtc->base.dev;
3664 struct drm_i915_private *dev_priv = dev->dev_private;
3665 int pipe = crtc->pipe;
3667 if (crtc->config.pch_pfit.enabled) {
3668 /* Force use of hard-coded filter coefficients
3669 * as some pre-programmed values are broken,
3672 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3673 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3674 PF_PIPE_SEL_IVB(pipe));
3676 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3677 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3678 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3682 static void intel_enable_planes(struct drm_crtc *crtc)
3684 struct drm_device *dev = crtc->dev;
3685 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3686 struct drm_plane *plane;
3687 struct intel_plane *intel_plane;
3689 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3690 intel_plane = to_intel_plane(plane);
3691 if (intel_plane->pipe == pipe)
3692 intel_plane_restore(&intel_plane->base);
3696 static void intel_disable_planes(struct drm_crtc *crtc)
3698 struct drm_device *dev = crtc->dev;
3699 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3700 struct drm_plane *plane;
3701 struct intel_plane *intel_plane;
3703 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3704 intel_plane = to_intel_plane(plane);
3705 if (intel_plane->pipe == pipe)
3706 intel_plane_disable(&intel_plane->base);
3710 void hsw_enable_ips(struct intel_crtc *crtc)
3712 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3714 if (!crtc->config.ips_enabled)
3717 /* We can only enable IPS after we enable a plane and wait for a vblank.
3718 * We guarantee that the plane is enabled by calling intel_enable_ips
3719 * only after intel_enable_plane. And intel_enable_plane already waits
3720 * for a vblank, so all we need to do here is to enable the IPS bit. */
3721 assert_plane_enabled(dev_priv, crtc->plane);
3722 if (IS_BROADWELL(crtc->base.dev)) {
3723 mutex_lock(&dev_priv->rps.hw_lock);
3724 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3725 mutex_unlock(&dev_priv->rps.hw_lock);
3726 /* Quoting Art Runyan: "its not safe to expect any particular
3727 * value in IPS_CTL bit 31 after enabling IPS through the
3728 * mailbox." Moreover, the mailbox may return a bogus state,
3729 * so we need to just enable it and continue on.
3732 I915_WRITE(IPS_CTL, IPS_ENABLE);
3733 /* The bit only becomes 1 in the next vblank, so this wait here
3734 * is essentially intel_wait_for_vblank. If we don't have this
3735 * and don't wait for vblanks until the end of crtc_enable, then
3736 * the HW state readout code will complain that the expected
3737 * IPS_CTL value is not the one we read. */
3738 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3739 DRM_ERROR("Timed out waiting for IPS enable\n");
3743 void hsw_disable_ips(struct intel_crtc *crtc)
3745 struct drm_device *dev = crtc->base.dev;
3746 struct drm_i915_private *dev_priv = dev->dev_private;
3748 if (!crtc->config.ips_enabled)
3751 assert_plane_enabled(dev_priv, crtc->plane);
3752 if (IS_BROADWELL(dev)) {
3753 mutex_lock(&dev_priv->rps.hw_lock);
3754 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3755 mutex_unlock(&dev_priv->rps.hw_lock);
3756 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3757 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3758 DRM_ERROR("Timed out waiting for IPS disable\n");
3760 I915_WRITE(IPS_CTL, 0);
3761 POSTING_READ(IPS_CTL);
3764 /* We need to wait for a vblank before we can disable the plane. */
3765 intel_wait_for_vblank(dev, crtc->pipe);
3768 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3769 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3771 struct drm_device *dev = crtc->dev;
3772 struct drm_i915_private *dev_priv = dev->dev_private;
3773 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3774 enum pipe pipe = intel_crtc->pipe;
3775 int palreg = PALETTE(pipe);
3777 bool reenable_ips = false;
3779 /* The clocks have to be on to load the palette. */
3780 if (!crtc->enabled || !intel_crtc->active)
3783 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3784 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3785 assert_dsi_pll_enabled(dev_priv);
3787 assert_pll_enabled(dev_priv, pipe);
3790 /* use legacy palette for Ironlake */
3791 if (HAS_PCH_SPLIT(dev))
3792 palreg = LGC_PALETTE(pipe);
3794 /* Workaround : Do not read or write the pipe palette/gamma data while
3795 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3797 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3798 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3799 GAMMA_MODE_MODE_SPLIT)) {
3800 hsw_disable_ips(intel_crtc);
3801 reenable_ips = true;
3804 for (i = 0; i < 256; i++) {
3805 I915_WRITE(palreg + 4 * i,
3806 (intel_crtc->lut_r[i] << 16) |
3807 (intel_crtc->lut_g[i] << 8) |
3808 intel_crtc->lut_b[i]);
3812 hsw_enable_ips(intel_crtc);
3815 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3817 if (!enable && intel_crtc->overlay) {
3818 struct drm_device *dev = intel_crtc->base.dev;
3819 struct drm_i915_private *dev_priv = dev->dev_private;
3821 mutex_lock(&dev->struct_mutex);
3822 dev_priv->mm.interruptible = false;
3823 (void) intel_overlay_switch_off(intel_crtc->overlay);
3824 dev_priv->mm.interruptible = true;
3825 mutex_unlock(&dev->struct_mutex);
3828 /* Let userspace switch the overlay on again. In most cases userspace
3829 * has to recompute where to put it anyway.
3834 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3835 * cursor plane briefly if not already running after enabling the display
3837 * This workaround avoids occasional blank screens when self refresh is
3841 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3843 u32 cntl = I915_READ(CURCNTR(pipe));
3845 if ((cntl & CURSOR_MODE) == 0) {
3846 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3848 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3849 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3850 intel_wait_for_vblank(dev_priv->dev, pipe);
3851 I915_WRITE(CURCNTR(pipe), cntl);
3852 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3853 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3857 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
3859 struct drm_device *dev = crtc->dev;
3860 struct drm_i915_private *dev_priv = dev->dev_private;
3861 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3862 int pipe = intel_crtc->pipe;
3863 int plane = intel_crtc->plane;
3865 intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3866 intel_enable_planes(crtc);
3867 /* The fixup needs to happen before cursor is enabled */
3869 g4x_fixup_plane(dev_priv, pipe);
3870 intel_crtc_update_cursor(crtc, true);
3871 intel_crtc_dpms_overlay(intel_crtc, true);
3873 hsw_enable_ips(intel_crtc);
3875 mutex_lock(&dev->struct_mutex);
3876 intel_update_fbc(dev);
3877 intel_edp_psr_update(dev);
3878 mutex_unlock(&dev->struct_mutex);
3881 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
3883 struct drm_device *dev = crtc->dev;
3884 struct drm_i915_private *dev_priv = dev->dev_private;
3885 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3886 int pipe = intel_crtc->pipe;
3887 int plane = intel_crtc->plane;
3889 intel_crtc_wait_for_pending_flips(crtc);
3890 drm_vblank_off(dev, pipe);
3892 if (dev_priv->fbc.plane == plane)
3893 intel_disable_fbc(dev);
3895 hsw_disable_ips(intel_crtc);
3897 intel_crtc_dpms_overlay(intel_crtc, false);
3898 intel_crtc_update_cursor(crtc, false);
3899 intel_disable_planes(crtc);
3900 intel_disable_primary_hw_plane(dev_priv, plane, pipe);
3903 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3905 struct drm_device *dev = crtc->dev;
3906 struct drm_i915_private *dev_priv = dev->dev_private;
3907 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3908 struct intel_encoder *encoder;
3909 int pipe = intel_crtc->pipe;
3911 WARN_ON(!crtc->enabled);
3913 if (intel_crtc->active)
3916 intel_crtc->active = true;
3918 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3919 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3921 for_each_encoder_on_crtc(dev, crtc, encoder)
3922 if (encoder->pre_enable)
3923 encoder->pre_enable(encoder);
3925 if (intel_crtc->config.has_pch_encoder) {
3926 /* Note: FDI PLL enabling _must_ be done before we enable the
3927 * cpu pipes, hence this is separate from all the other fdi/pch
3929 ironlake_fdi_pll_enable(intel_crtc);
3931 assert_fdi_tx_disabled(dev_priv, pipe);
3932 assert_fdi_rx_disabled(dev_priv, pipe);
3935 ironlake_pfit_enable(intel_crtc);
3938 * On ILK+ LUT must be loaded before the pipe is running but with
3941 intel_crtc_load_lut(crtc);
3943 intel_update_watermarks(crtc);
3944 intel_enable_pipe(intel_crtc);
3946 if (intel_crtc->config.has_pch_encoder)
3947 ironlake_pch_enable(crtc);
3949 for_each_encoder_on_crtc(dev, crtc, encoder)
3950 encoder->enable(encoder);
3952 if (HAS_PCH_CPT(dev))
3953 cpt_verify_modeset(dev, intel_crtc->pipe);
3955 intel_crtc_enable_planes(crtc);
3958 * There seems to be a race in PCH platform hw (at least on some
3959 * outputs) where an enabled pipe still completes any pageflip right
3960 * away (as if the pipe is off) instead of waiting for vblank. As soon
3961 * as the first vblank happend, everything works as expected. Hence just
3962 * wait for one vblank before returning to avoid strange things
3965 intel_wait_for_vblank(dev, intel_crtc->pipe);
3968 /* IPS only exists on ULT machines and is tied to pipe A. */
3969 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3971 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3975 * This implements the workaround described in the "notes" section of the mode
3976 * set sequence documentation. When going from no pipes or single pipe to
3977 * multiple pipes, and planes are enabled after the pipe, we need to wait at
3978 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3980 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3982 struct drm_device *dev = crtc->base.dev;
3983 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3985 /* We want to get the other_active_crtc only if there's only 1 other
3987 for_each_intel_crtc(dev, crtc_it) {
3988 if (!crtc_it->active || crtc_it == crtc)
3991 if (other_active_crtc)
3994 other_active_crtc = crtc_it;
3996 if (!other_active_crtc)
3999 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4000 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4003 static void haswell_crtc_enable(struct drm_crtc *crtc)
4005 struct drm_device *dev = crtc->dev;
4006 struct drm_i915_private *dev_priv = dev->dev_private;
4007 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4008 struct intel_encoder *encoder;
4009 int pipe = intel_crtc->pipe;
4011 WARN_ON(!crtc->enabled);
4013 if (intel_crtc->active)
4016 intel_crtc->active = true;
4018 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4019 if (intel_crtc->config.has_pch_encoder)
4020 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4022 if (intel_crtc->config.has_pch_encoder)
4023 dev_priv->display.fdi_link_train(crtc);
4025 for_each_encoder_on_crtc(dev, crtc, encoder)
4026 if (encoder->pre_enable)
4027 encoder->pre_enable(encoder);
4029 intel_ddi_enable_pipe_clock(intel_crtc);
4031 ironlake_pfit_enable(intel_crtc);
4034 * On ILK+ LUT must be loaded before the pipe is running but with
4037 intel_crtc_load_lut(crtc);
4039 intel_ddi_set_pipe_settings(crtc);
4040 intel_ddi_enable_transcoder_func(crtc);
4042 intel_update_watermarks(crtc);
4043 intel_enable_pipe(intel_crtc);
4045 if (intel_crtc->config.has_pch_encoder)
4046 lpt_pch_enable(crtc);
4048 for_each_encoder_on_crtc(dev, crtc, encoder) {
4049 encoder->enable(encoder);
4050 intel_opregion_notify_encoder(encoder, true);
4053 /* If we change the relative order between pipe/planes enabling, we need
4054 * to change the workaround. */
4055 haswell_mode_set_planes_workaround(intel_crtc);
4056 intel_crtc_enable_planes(crtc);
4059 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4061 struct drm_device *dev = crtc->base.dev;
4062 struct drm_i915_private *dev_priv = dev->dev_private;
4063 int pipe = crtc->pipe;
4065 /* To avoid upsetting the power well on haswell only disable the pfit if
4066 * it's in use. The hw state code will make sure we get this right. */
4067 if (crtc->config.pch_pfit.enabled) {
4068 I915_WRITE(PF_CTL(pipe), 0);
4069 I915_WRITE(PF_WIN_POS(pipe), 0);
4070 I915_WRITE(PF_WIN_SZ(pipe), 0);
4074 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4076 struct drm_device *dev = crtc->dev;
4077 struct drm_i915_private *dev_priv = dev->dev_private;
4078 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4079 struct intel_encoder *encoder;
4080 int pipe = intel_crtc->pipe;
4083 if (!intel_crtc->active)
4086 intel_crtc_disable_planes(crtc);
4088 for_each_encoder_on_crtc(dev, crtc, encoder)
4089 encoder->disable(encoder);
4091 if (intel_crtc->config.has_pch_encoder)
4092 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4094 intel_disable_pipe(dev_priv, pipe);
4096 ironlake_pfit_disable(intel_crtc);
4098 for_each_encoder_on_crtc(dev, crtc, encoder)
4099 if (encoder->post_disable)
4100 encoder->post_disable(encoder);
4102 if (intel_crtc->config.has_pch_encoder) {
4103 ironlake_fdi_disable(crtc);
4105 ironlake_disable_pch_transcoder(dev_priv, pipe);
4106 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4108 if (HAS_PCH_CPT(dev)) {
4109 /* disable TRANS_DP_CTL */
4110 reg = TRANS_DP_CTL(pipe);
4111 temp = I915_READ(reg);
4112 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4113 TRANS_DP_PORT_SEL_MASK);
4114 temp |= TRANS_DP_PORT_SEL_NONE;
4115 I915_WRITE(reg, temp);
4117 /* disable DPLL_SEL */
4118 temp = I915_READ(PCH_DPLL_SEL);
4119 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4120 I915_WRITE(PCH_DPLL_SEL, temp);
4123 /* disable PCH DPLL */
4124 intel_disable_shared_dpll(intel_crtc);
4126 ironlake_fdi_pll_disable(intel_crtc);
4129 intel_crtc->active = false;
4130 intel_update_watermarks(crtc);
4132 mutex_lock(&dev->struct_mutex);
4133 intel_update_fbc(dev);
4134 intel_edp_psr_update(dev);
4135 mutex_unlock(&dev->struct_mutex);
4138 static void haswell_crtc_disable(struct drm_crtc *crtc)
4140 struct drm_device *dev = crtc->dev;
4141 struct drm_i915_private *dev_priv = dev->dev_private;
4142 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4143 struct intel_encoder *encoder;
4144 int pipe = intel_crtc->pipe;
4145 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4147 if (!intel_crtc->active)
4150 intel_crtc_disable_planes(crtc);
4152 for_each_encoder_on_crtc(dev, crtc, encoder) {
4153 intel_opregion_notify_encoder(encoder, false);
4154 encoder->disable(encoder);
4157 if (intel_crtc->config.has_pch_encoder)
4158 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4159 intel_disable_pipe(dev_priv, pipe);
4161 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4163 ironlake_pfit_disable(intel_crtc);
4165 intel_ddi_disable_pipe_clock(intel_crtc);
4167 for_each_encoder_on_crtc(dev, crtc, encoder)
4168 if (encoder->post_disable)
4169 encoder->post_disable(encoder);
4171 if (intel_crtc->config.has_pch_encoder) {
4172 lpt_disable_pch_transcoder(dev_priv);
4173 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4174 intel_ddi_fdi_disable(crtc);
4177 intel_crtc->active = false;
4178 intel_update_watermarks(crtc);
4180 mutex_lock(&dev->struct_mutex);
4181 intel_update_fbc(dev);
4182 intel_edp_psr_update(dev);
4183 mutex_unlock(&dev->struct_mutex);
4186 static void ironlake_crtc_off(struct drm_crtc *crtc)
4188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4189 intel_put_shared_dpll(intel_crtc);
4192 static void haswell_crtc_off(struct drm_crtc *crtc)
4194 intel_ddi_put_crtc_pll(crtc);
4197 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4199 struct drm_device *dev = crtc->base.dev;
4200 struct drm_i915_private *dev_priv = dev->dev_private;
4201 struct intel_crtc_config *pipe_config = &crtc->config;
4203 if (!crtc->config.gmch_pfit.control)
4207 * The panel fitter should only be adjusted whilst the pipe is disabled,
4208 * according to register description and PRM.
4210 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4211 assert_pipe_disabled(dev_priv, crtc->pipe);
4213 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4214 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4216 /* Border color in case we don't scale up to the full screen. Black by
4217 * default, change to something else for debugging. */
4218 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4221 #define for_each_power_domain(domain, mask) \
4222 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4223 if ((1 << (domain)) & (mask))
4225 enum intel_display_power_domain
4226 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4228 struct drm_device *dev = intel_encoder->base.dev;
4229 struct intel_digital_port *intel_dig_port;
4231 switch (intel_encoder->type) {
4232 case INTEL_OUTPUT_UNKNOWN:
4233 /* Only DDI platforms should ever use this output type */
4234 WARN_ON_ONCE(!HAS_DDI(dev));
4235 case INTEL_OUTPUT_DISPLAYPORT:
4236 case INTEL_OUTPUT_HDMI:
4237 case INTEL_OUTPUT_EDP:
4238 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4239 switch (intel_dig_port->port) {
4241 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4243 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4245 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4247 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4250 return POWER_DOMAIN_PORT_OTHER;
4252 case INTEL_OUTPUT_ANALOG:
4253 return POWER_DOMAIN_PORT_CRT;
4254 case INTEL_OUTPUT_DSI:
4255 return POWER_DOMAIN_PORT_DSI;
4257 return POWER_DOMAIN_PORT_OTHER;
4261 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4263 struct drm_device *dev = crtc->dev;
4264 struct intel_encoder *intel_encoder;
4265 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4266 enum pipe pipe = intel_crtc->pipe;
4267 bool pfit_enabled = intel_crtc->config.pch_pfit.enabled;
4269 enum transcoder transcoder;
4271 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4273 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4274 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4276 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4278 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4279 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4284 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4287 if (dev_priv->power_domains.init_power_on == enable)
4291 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4293 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4295 dev_priv->power_domains.init_power_on = enable;
4298 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4300 struct drm_i915_private *dev_priv = dev->dev_private;
4301 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4302 struct intel_crtc *crtc;
4305 * First get all needed power domains, then put all unneeded, to avoid
4306 * any unnecessary toggling of the power wells.
4308 for_each_intel_crtc(dev, crtc) {
4309 enum intel_display_power_domain domain;
4311 if (!crtc->base.enabled)
4314 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4316 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4317 intel_display_power_get(dev_priv, domain);
4320 for_each_intel_crtc(dev, crtc) {
4321 enum intel_display_power_domain domain;
4323 for_each_power_domain(domain, crtc->enabled_power_domains)
4324 intel_display_power_put(dev_priv, domain);
4326 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4329 intel_display_set_init_power(dev_priv, false);
4332 int valleyview_get_vco(struct drm_i915_private *dev_priv)
4334 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4336 /* Obtain SKU information */
4337 mutex_lock(&dev_priv->dpio_lock);
4338 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4339 CCK_FUSE_HPLL_FREQ_MASK;
4340 mutex_unlock(&dev_priv->dpio_lock);
4342 return vco_freq[hpll_freq];
4345 /* Adjust CDclk dividers to allow high res or save power if possible */
4346 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4348 struct drm_i915_private *dev_priv = dev->dev_private;
4351 WARN_ON(valleyview_cur_cdclk(dev_priv) != dev_priv->vlv_cdclk_freq);
4352 dev_priv->vlv_cdclk_freq = cdclk;
4354 if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
4356 else if (cdclk == 266)
4361 mutex_lock(&dev_priv->rps.hw_lock);
4362 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4363 val &= ~DSPFREQGUAR_MASK;
4364 val |= (cmd << DSPFREQGUAR_SHIFT);
4365 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4366 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4367 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4369 DRM_ERROR("timed out waiting for CDclk change\n");
4371 mutex_unlock(&dev_priv->rps.hw_lock);
4376 vco = valleyview_get_vco(dev_priv);
4377 divider = ((vco << 1) / cdclk) - 1;
4379 mutex_lock(&dev_priv->dpio_lock);
4380 /* adjust cdclk divider */
4381 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4384 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4385 mutex_unlock(&dev_priv->dpio_lock);
4388 mutex_lock(&dev_priv->dpio_lock);
4389 /* adjust self-refresh exit latency value */
4390 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4394 * For high bandwidth configs, we set a higher latency in the bunit
4395 * so that the core display fetch happens in time to avoid underruns.
4398 val |= 4500 / 250; /* 4.5 usec */
4400 val |= 3000 / 250; /* 3.0 usec */
4401 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4402 mutex_unlock(&dev_priv->dpio_lock);
4404 /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4405 intel_i2c_reset(dev);
4408 int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4413 vco = valleyview_get_vco(dev_priv);
4415 mutex_lock(&dev_priv->dpio_lock);
4416 divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4417 mutex_unlock(&dev_priv->dpio_lock);
4421 cur_cdclk = (vco << 1) / (divider + 1);
4426 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4430 * Really only a few cases to deal with, as only 4 CDclks are supported:
4435 * So we check to see whether we're above 90% of the lower bin and
4438 if (max_pixclk > 288000) {
4440 } else if (max_pixclk > 240000) {
4444 /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4447 /* compute the max pixel clock for new configuration */
4448 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4450 struct drm_device *dev = dev_priv->dev;
4451 struct intel_crtc *intel_crtc;
4454 for_each_intel_crtc(dev, intel_crtc) {
4455 if (intel_crtc->new_enabled)
4456 max_pixclk = max(max_pixclk,
4457 intel_crtc->new_config->adjusted_mode.crtc_clock);
4463 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4464 unsigned *prepare_pipes)
4466 struct drm_i915_private *dev_priv = dev->dev_private;
4467 struct intel_crtc *intel_crtc;
4468 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4470 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4471 dev_priv->vlv_cdclk_freq)
4474 /* disable/enable all currently active pipes while we change cdclk */
4475 for_each_intel_crtc(dev, intel_crtc)
4476 if (intel_crtc->base.enabled)
4477 *prepare_pipes |= (1 << intel_crtc->pipe);
4480 static void valleyview_modeset_global_resources(struct drm_device *dev)
4482 struct drm_i915_private *dev_priv = dev->dev_private;
4483 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4484 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4486 if (req_cdclk != dev_priv->vlv_cdclk_freq)
4487 valleyview_set_cdclk(dev, req_cdclk);
4488 modeset_update_crtc_power_domains(dev);
4491 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4493 struct drm_device *dev = crtc->dev;
4494 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4495 struct intel_encoder *encoder;
4496 int pipe = intel_crtc->pipe;
4499 WARN_ON(!crtc->enabled);
4501 if (intel_crtc->active)
4504 intel_crtc->active = true;
4506 for_each_encoder_on_crtc(dev, crtc, encoder)
4507 if (encoder->pre_pll_enable)
4508 encoder->pre_pll_enable(encoder);
4510 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4513 if (IS_CHERRYVIEW(dev))
4514 chv_enable_pll(intel_crtc);
4516 vlv_enable_pll(intel_crtc);
4519 for_each_encoder_on_crtc(dev, crtc, encoder)
4520 if (encoder->pre_enable)
4521 encoder->pre_enable(encoder);
4523 i9xx_pfit_enable(intel_crtc);
4525 intel_crtc_load_lut(crtc);
4527 intel_update_watermarks(crtc);
4528 intel_enable_pipe(intel_crtc);
4529 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4531 for_each_encoder_on_crtc(dev, crtc, encoder)
4532 encoder->enable(encoder);
4534 intel_crtc_enable_planes(crtc);
4537 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4539 struct drm_device *dev = crtc->dev;
4540 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4541 struct intel_encoder *encoder;
4542 int pipe = intel_crtc->pipe;
4544 WARN_ON(!crtc->enabled);
4546 if (intel_crtc->active)
4549 intel_crtc->active = true;
4551 for_each_encoder_on_crtc(dev, crtc, encoder)
4552 if (encoder->pre_enable)
4553 encoder->pre_enable(encoder);
4555 i9xx_enable_pll(intel_crtc);
4557 i9xx_pfit_enable(intel_crtc);
4559 intel_crtc_load_lut(crtc);
4561 intel_update_watermarks(crtc);
4562 intel_enable_pipe(intel_crtc);
4563 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4565 for_each_encoder_on_crtc(dev, crtc, encoder)
4566 encoder->enable(encoder);
4568 intel_crtc_enable_planes(crtc);
4571 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4573 struct drm_device *dev = crtc->base.dev;
4574 struct drm_i915_private *dev_priv = dev->dev_private;
4576 if (!crtc->config.gmch_pfit.control)
4579 assert_pipe_disabled(dev_priv, crtc->pipe);
4581 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4582 I915_READ(PFIT_CONTROL));
4583 I915_WRITE(PFIT_CONTROL, 0);
4586 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4588 struct drm_device *dev = crtc->dev;
4589 struct drm_i915_private *dev_priv = dev->dev_private;
4590 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4591 struct intel_encoder *encoder;
4592 int pipe = intel_crtc->pipe;
4594 if (!intel_crtc->active)
4597 intel_crtc_disable_planes(crtc);
4599 for_each_encoder_on_crtc(dev, crtc, encoder)
4600 encoder->disable(encoder);
4602 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4603 intel_disable_pipe(dev_priv, pipe);
4605 i9xx_pfit_disable(intel_crtc);
4607 for_each_encoder_on_crtc(dev, crtc, encoder)
4608 if (encoder->post_disable)
4609 encoder->post_disable(encoder);
4611 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4612 if (IS_CHERRYVIEW(dev))
4613 chv_disable_pll(dev_priv, pipe);
4614 else if (IS_VALLEYVIEW(dev))
4615 vlv_disable_pll(dev_priv, pipe);
4617 i9xx_disable_pll(dev_priv, pipe);
4620 intel_crtc->active = false;
4621 intel_update_watermarks(crtc);
4623 mutex_lock(&dev->struct_mutex);
4624 intel_update_fbc(dev);
4625 intel_edp_psr_update(dev);
4626 mutex_unlock(&dev->struct_mutex);
4629 static void i9xx_crtc_off(struct drm_crtc *crtc)
4633 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4636 struct drm_device *dev = crtc->dev;
4637 struct drm_i915_master_private *master_priv;
4638 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4639 int pipe = intel_crtc->pipe;
4641 if (!dev->primary->master)
4644 master_priv = dev->primary->master->driver_priv;
4645 if (!master_priv->sarea_priv)
4650 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4651 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4654 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4655 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4658 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4664 * Sets the power management mode of the pipe and plane.
4666 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4668 struct drm_device *dev = crtc->dev;
4669 struct drm_i915_private *dev_priv = dev->dev_private;
4670 struct intel_encoder *intel_encoder;
4671 bool enable = false;
4673 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4674 enable |= intel_encoder->connectors_active;
4677 dev_priv->display.crtc_enable(crtc);
4679 dev_priv->display.crtc_disable(crtc);
4681 intel_crtc_update_sarea(crtc, enable);
4684 static void intel_crtc_disable(struct drm_crtc *crtc)
4686 struct drm_device *dev = crtc->dev;
4687 struct drm_connector *connector;
4688 struct drm_i915_private *dev_priv = dev->dev_private;
4690 /* crtc should still be enabled when we disable it. */
4691 WARN_ON(!crtc->enabled);
4693 dev_priv->display.crtc_disable(crtc);
4694 intel_crtc_update_sarea(crtc, false);
4695 dev_priv->display.off(crtc);
4697 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4698 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4699 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4701 if (crtc->primary->fb) {
4702 mutex_lock(&dev->struct_mutex);
4703 intel_unpin_fb_obj(to_intel_framebuffer(crtc->primary->fb)->obj);
4704 mutex_unlock(&dev->struct_mutex);
4705 crtc->primary->fb = NULL;
4708 /* Update computed state. */
4709 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4710 if (!connector->encoder || !connector->encoder->crtc)
4713 if (connector->encoder->crtc != crtc)
4716 connector->dpms = DRM_MODE_DPMS_OFF;
4717 to_intel_encoder(connector->encoder)->connectors_active = false;
4721 void intel_encoder_destroy(struct drm_encoder *encoder)
4723 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4725 drm_encoder_cleanup(encoder);
4726 kfree(intel_encoder);
4729 /* Simple dpms helper for encoders with just one connector, no cloning and only
4730 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4731 * state of the entire output pipe. */
4732 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4734 if (mode == DRM_MODE_DPMS_ON) {
4735 encoder->connectors_active = true;
4737 intel_crtc_update_dpms(encoder->base.crtc);
4739 encoder->connectors_active = false;
4741 intel_crtc_update_dpms(encoder->base.crtc);
4745 /* Cross check the actual hw state with our own modeset state tracking (and it's
4746 * internal consistency). */
4747 static void intel_connector_check_state(struct intel_connector *connector)
4749 if (connector->get_hw_state(connector)) {
4750 struct intel_encoder *encoder = connector->encoder;
4751 struct drm_crtc *crtc;
4752 bool encoder_enabled;
4755 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4756 connector->base.base.id,
4757 drm_get_connector_name(&connector->base));
4759 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4760 "wrong connector dpms state\n");
4761 WARN(connector->base.encoder != &encoder->base,
4762 "active connector not linked to encoder\n");
4763 WARN(!encoder->connectors_active,
4764 "encoder->connectors_active not set\n");
4766 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4767 WARN(!encoder_enabled, "encoder not enabled\n");
4768 if (WARN_ON(!encoder->base.crtc))
4771 crtc = encoder->base.crtc;
4773 WARN(!crtc->enabled, "crtc not enabled\n");
4774 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4775 WARN(pipe != to_intel_crtc(crtc)->pipe,
4776 "encoder active on the wrong pipe\n");
4780 /* Even simpler default implementation, if there's really no special case to
4782 void intel_connector_dpms(struct drm_connector *connector, int mode)
4784 /* All the simple cases only support two dpms states. */
4785 if (mode != DRM_MODE_DPMS_ON)
4786 mode = DRM_MODE_DPMS_OFF;
4788 if (mode == connector->dpms)
4791 connector->dpms = mode;
4793 /* Only need to change hw state when actually enabled */
4794 if (connector->encoder)
4795 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
4797 intel_modeset_check_state(connector->dev);
4800 /* Simple connector->get_hw_state implementation for encoders that support only
4801 * one connector and no cloning and hence the encoder state determines the state
4802 * of the connector. */
4803 bool intel_connector_get_hw_state(struct intel_connector *connector)
4806 struct intel_encoder *encoder = connector->encoder;
4808 return encoder->get_hw_state(encoder, &pipe);
4811 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4812 struct intel_crtc_config *pipe_config)
4814 struct drm_i915_private *dev_priv = dev->dev_private;
4815 struct intel_crtc *pipe_B_crtc =
4816 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4818 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4819 pipe_name(pipe), pipe_config->fdi_lanes);
4820 if (pipe_config->fdi_lanes > 4) {
4821 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4822 pipe_name(pipe), pipe_config->fdi_lanes);
4826 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4827 if (pipe_config->fdi_lanes > 2) {
4828 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4829 pipe_config->fdi_lanes);
4836 if (INTEL_INFO(dev)->num_pipes == 2)
4839 /* Ivybridge 3 pipe is really complicated */
4844 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4845 pipe_config->fdi_lanes > 2) {
4846 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4847 pipe_name(pipe), pipe_config->fdi_lanes);
4852 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4853 pipe_B_crtc->config.fdi_lanes <= 2) {
4854 if (pipe_config->fdi_lanes > 2) {
4855 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4856 pipe_name(pipe), pipe_config->fdi_lanes);
4860 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4870 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4871 struct intel_crtc_config *pipe_config)
4873 struct drm_device *dev = intel_crtc->base.dev;
4874 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4875 int lane, link_bw, fdi_dotclock;
4876 bool setup_ok, needs_recompute = false;
4879 /* FDI is a binary signal running at ~2.7GHz, encoding
4880 * each output octet as 10 bits. The actual frequency
4881 * is stored as a divider into a 100MHz clock, and the
4882 * mode pixel clock is stored in units of 1KHz.
4883 * Hence the bw of each lane in terms of the mode signal
4886 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4888 fdi_dotclock = adjusted_mode->crtc_clock;
4890 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4891 pipe_config->pipe_bpp);
4893 pipe_config->fdi_lanes = lane;
4895 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4896 link_bw, &pipe_config->fdi_m_n);
4898 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4899 intel_crtc->pipe, pipe_config);
4900 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4901 pipe_config->pipe_bpp -= 2*3;
4902 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4903 pipe_config->pipe_bpp);
4904 needs_recompute = true;
4905 pipe_config->bw_constrained = true;
4910 if (needs_recompute)
4913 return setup_ok ? 0 : -EINVAL;
4916 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4917 struct intel_crtc_config *pipe_config)
4919 pipe_config->ips_enabled = i915.enable_ips &&
4920 hsw_crtc_supports_ips(crtc) &&
4921 pipe_config->pipe_bpp <= 24;
4924 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4925 struct intel_crtc_config *pipe_config)
4927 struct drm_device *dev = crtc->base.dev;
4928 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4930 /* FIXME should check pixel clock limits on all platforms */
4931 if (INTEL_INFO(dev)->gen < 4) {
4932 struct drm_i915_private *dev_priv = dev->dev_private;
4934 dev_priv->display.get_display_clock_speed(dev);
4937 * Enable pixel doubling when the dot clock
4938 * is > 90% of the (display) core speed.
4940 * GDG double wide on either pipe,
4941 * otherwise pipe A only.
4943 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4944 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
4946 pipe_config->double_wide = true;
4949 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
4954 * Pipe horizontal size must be even in:
4956 * - LVDS dual channel mode
4957 * - Double wide pipe
4959 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4960 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4961 pipe_config->pipe_src_w &= ~1;
4963 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4964 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4966 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4967 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4970 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4971 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4972 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4973 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4975 pipe_config->pipe_bpp = 8*3;
4979 hsw_compute_ips_config(crtc, pipe_config);
4981 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4982 * clock survives for now. */
4983 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4984 pipe_config->shared_dpll = crtc->config.shared_dpll;
4986 if (pipe_config->has_pch_encoder)
4987 return ironlake_fdi_compute_config(crtc, pipe_config);
4992 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4994 return 400000; /* FIXME */
4997 static int i945_get_display_clock_speed(struct drm_device *dev)
5002 static int i915_get_display_clock_speed(struct drm_device *dev)
5007 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5012 static int pnv_get_display_clock_speed(struct drm_device *dev)
5016 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5018 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5019 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5021 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5023 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5025 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5028 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5029 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5031 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5036 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5040 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5042 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5045 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5046 case GC_DISPLAY_CLOCK_333_MHZ:
5049 case GC_DISPLAY_CLOCK_190_200_MHZ:
5055 static int i865_get_display_clock_speed(struct drm_device *dev)
5060 static int i855_get_display_clock_speed(struct drm_device *dev)
5063 /* Assume that the hardware is in the high speed state. This
5064 * should be the default.
5066 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5067 case GC_CLOCK_133_200:
5068 case GC_CLOCK_100_200:
5070 case GC_CLOCK_166_250:
5072 case GC_CLOCK_100_133:
5076 /* Shouldn't happen */
5080 static int i830_get_display_clock_speed(struct drm_device *dev)
5086 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5088 while (*num > DATA_LINK_M_N_MASK ||
5089 *den > DATA_LINK_M_N_MASK) {
5095 static void compute_m_n(unsigned int m, unsigned int n,
5096 uint32_t *ret_m, uint32_t *ret_n)
5098 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5099 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5100 intel_reduce_m_n_ratio(ret_m, ret_n);
5104 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5105 int pixel_clock, int link_clock,
5106 struct intel_link_m_n *m_n)
5110 compute_m_n(bits_per_pixel * pixel_clock,
5111 link_clock * nlanes * 8,
5112 &m_n->gmch_m, &m_n->gmch_n);
5114 compute_m_n(pixel_clock, link_clock,
5115 &m_n->link_m, &m_n->link_n);
5118 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5120 if (i915.panel_use_ssc >= 0)
5121 return i915.panel_use_ssc != 0;
5122 return dev_priv->vbt.lvds_use_ssc
5123 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5126 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5128 struct drm_device *dev = crtc->dev;
5129 struct drm_i915_private *dev_priv = dev->dev_private;
5132 if (IS_VALLEYVIEW(dev)) {
5134 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5135 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5136 refclk = dev_priv->vbt.lvds_ssc_freq;
5137 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5138 } else if (!IS_GEN2(dev)) {
5147 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5149 return (1 << dpll->n) << 16 | dpll->m2;
5152 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5154 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5157 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5158 intel_clock_t *reduced_clock)
5160 struct drm_device *dev = crtc->base.dev;
5161 struct drm_i915_private *dev_priv = dev->dev_private;
5162 int pipe = crtc->pipe;
5165 if (IS_PINEVIEW(dev)) {
5166 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5168 fp2 = pnv_dpll_compute_fp(reduced_clock);
5170 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5172 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5175 I915_WRITE(FP0(pipe), fp);
5176 crtc->config.dpll_hw_state.fp0 = fp;
5178 crtc->lowfreq_avail = false;
5179 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5180 reduced_clock && i915.powersave) {
5181 I915_WRITE(FP1(pipe), fp2);
5182 crtc->config.dpll_hw_state.fp1 = fp2;
5183 crtc->lowfreq_avail = true;
5185 I915_WRITE(FP1(pipe), fp);
5186 crtc->config.dpll_hw_state.fp1 = fp;
5190 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5196 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5197 * and set it to a reasonable value instead.
5199 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5200 reg_val &= 0xffffff00;
5201 reg_val |= 0x00000030;
5202 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5204 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5205 reg_val &= 0x8cffffff;
5206 reg_val = 0x8c000000;
5207 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5209 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5210 reg_val &= 0xffffff00;
5211 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5213 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5214 reg_val &= 0x00ffffff;
5215 reg_val |= 0xb0000000;
5216 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5219 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5220 struct intel_link_m_n *m_n)
5222 struct drm_device *dev = crtc->base.dev;
5223 struct drm_i915_private *dev_priv = dev->dev_private;
5224 int pipe = crtc->pipe;
5226 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5227 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5228 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5229 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5232 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5233 struct intel_link_m_n *m_n)
5235 struct drm_device *dev = crtc->base.dev;
5236 struct drm_i915_private *dev_priv = dev->dev_private;
5237 int pipe = crtc->pipe;
5238 enum transcoder transcoder = crtc->config.cpu_transcoder;
5240 if (INTEL_INFO(dev)->gen >= 5) {
5241 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5242 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5243 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5244 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5246 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5247 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5248 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5249 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5253 static void intel_dp_set_m_n(struct intel_crtc *crtc)
5255 if (crtc->config.has_pch_encoder)
5256 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5258 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5261 static void vlv_update_pll(struct intel_crtc *crtc)
5263 struct drm_device *dev = crtc->base.dev;
5264 struct drm_i915_private *dev_priv = dev->dev_private;
5265 int pipe = crtc->pipe;
5267 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5268 u32 coreclk, reg_val, dpll_md;
5270 mutex_lock(&dev_priv->dpio_lock);
5272 bestn = crtc->config.dpll.n;
5273 bestm1 = crtc->config.dpll.m1;
5274 bestm2 = crtc->config.dpll.m2;
5275 bestp1 = crtc->config.dpll.p1;
5276 bestp2 = crtc->config.dpll.p2;
5278 /* See eDP HDMI DPIO driver vbios notes doc */
5280 /* PLL B needs special handling */
5282 vlv_pllb_recal_opamp(dev_priv, pipe);
5284 /* Set up Tx target for periodic Rcomp update */
5285 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5287 /* Disable target IRef on PLL */
5288 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5289 reg_val &= 0x00ffffff;
5290 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5292 /* Disable fast lock */
5293 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5295 /* Set idtafcrecal before PLL is enabled */
5296 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5297 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5298 mdiv |= ((bestn << DPIO_N_SHIFT));
5299 mdiv |= (1 << DPIO_K_SHIFT);
5302 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5303 * but we don't support that).
5304 * Note: don't use the DAC post divider as it seems unstable.
5306 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5307 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5309 mdiv |= DPIO_ENABLE_CALIBRATION;
5310 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5312 /* Set HBR and RBR LPF coefficients */
5313 if (crtc->config.port_clock == 162000 ||
5314 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5315 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5316 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5319 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5322 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5323 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5324 /* Use SSC source */
5326 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5329 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5331 } else { /* HDMI or VGA */
5332 /* Use bend source */
5334 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5337 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5341 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5342 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5343 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5344 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5345 coreclk |= 0x01000000;
5346 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5348 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5351 * Enable DPIO clock input. We should never disable the reference
5352 * clock for pipe B, since VGA hotplug / manual detection depends
5355 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5356 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5357 /* We should never disable this, set it here for state tracking */
5359 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5360 dpll |= DPLL_VCO_ENABLE;
5361 crtc->config.dpll_hw_state.dpll = dpll;
5363 dpll_md = (crtc->config.pixel_multiplier - 1)
5364 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5365 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5367 mutex_unlock(&dev_priv->dpio_lock);
5370 static void chv_update_pll(struct intel_crtc *crtc)
5372 struct drm_device *dev = crtc->base.dev;
5373 struct drm_i915_private *dev_priv = dev->dev_private;
5374 int pipe = crtc->pipe;
5375 int dpll_reg = DPLL(crtc->pipe);
5376 enum dpio_channel port = vlv_pipe_to_channel(pipe);
5377 u32 val, loopfilter, intcoeff;
5378 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5381 mutex_lock(&dev_priv->dpio_lock);
5383 bestn = crtc->config.dpll.n;
5384 bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5385 bestm1 = crtc->config.dpll.m1;
5386 bestm2 = crtc->config.dpll.m2 >> 22;
5387 bestp1 = crtc->config.dpll.p1;
5388 bestp2 = crtc->config.dpll.p2;
5391 * Enable Refclk and SSC
5393 val = I915_READ(dpll_reg);
5394 val |= (DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV);
5395 I915_WRITE(dpll_reg, val);
5397 /* Propagate soft reset to data lane reset */
5398 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(port));
5399 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
5400 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), val);
5402 /* Disable 10bit clock to display controller */
5403 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
5404 val &= ~DPIO_DCLKP_EN;
5405 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
5407 /* p1 and p2 divider */
5408 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5409 5 << DPIO_CHV_S1_DIV_SHIFT |
5410 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5411 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5412 1 << DPIO_CHV_K_DIV_SHIFT);
5414 /* Feedback post-divider - m2 */
5415 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5417 /* Feedback refclk divider - n and m1 */
5418 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5419 DPIO_CHV_M1_DIV_BY_2 |
5420 1 << DPIO_CHV_N_DIV_SHIFT);
5422 /* M2 fraction division */
5423 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5425 /* M2 fraction division enable */
5426 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5427 DPIO_CHV_FRAC_DIV_EN |
5428 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5431 refclk = i9xx_get_refclk(&crtc->base, 0);
5432 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5433 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5434 if (refclk == 100000)
5436 else if (refclk == 38400)
5440 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5441 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5444 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5445 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5448 mutex_unlock(&dev_priv->dpio_lock);
5451 static void i9xx_update_pll(struct intel_crtc *crtc,
5452 intel_clock_t *reduced_clock,
5455 struct drm_device *dev = crtc->base.dev;
5456 struct drm_i915_private *dev_priv = dev->dev_private;
5459 struct dpll *clock = &crtc->config.dpll;
5461 i9xx_update_pll_dividers(crtc, reduced_clock);
5463 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5464 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5466 dpll = DPLL_VGA_MODE_DIS;
5468 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5469 dpll |= DPLLB_MODE_LVDS;
5471 dpll |= DPLLB_MODE_DAC_SERIAL;
5473 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5474 dpll |= (crtc->config.pixel_multiplier - 1)
5475 << SDVO_MULTIPLIER_SHIFT_HIRES;
5479 dpll |= DPLL_SDVO_HIGH_SPEED;
5481 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5482 dpll |= DPLL_SDVO_HIGH_SPEED;
5484 /* compute bitmask from p1 value */
5485 if (IS_PINEVIEW(dev))
5486 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5488 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5489 if (IS_G4X(dev) && reduced_clock)
5490 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5492 switch (clock->p2) {
5494 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5497 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5500 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5503 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5506 if (INTEL_INFO(dev)->gen >= 4)
5507 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5509 if (crtc->config.sdvo_tv_clock)
5510 dpll |= PLL_REF_INPUT_TVCLKINBC;
5511 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5512 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5513 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5515 dpll |= PLL_REF_INPUT_DREFCLK;
5517 dpll |= DPLL_VCO_ENABLE;
5518 crtc->config.dpll_hw_state.dpll = dpll;
5520 if (INTEL_INFO(dev)->gen >= 4) {
5521 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5522 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5523 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5527 static void i8xx_update_pll(struct intel_crtc *crtc,
5528 intel_clock_t *reduced_clock,
5531 struct drm_device *dev = crtc->base.dev;
5532 struct drm_i915_private *dev_priv = dev->dev_private;
5534 struct dpll *clock = &crtc->config.dpll;
5536 i9xx_update_pll_dividers(crtc, reduced_clock);
5538 dpll = DPLL_VGA_MODE_DIS;
5540 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5541 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5544 dpll |= PLL_P1_DIVIDE_BY_TWO;
5546 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5548 dpll |= PLL_P2_DIVIDE_BY_4;
5551 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5552 dpll |= DPLL_DVO_2X_MODE;
5554 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5555 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5556 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5558 dpll |= PLL_REF_INPUT_DREFCLK;
5560 dpll |= DPLL_VCO_ENABLE;
5561 crtc->config.dpll_hw_state.dpll = dpll;
5564 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5566 struct drm_device *dev = intel_crtc->base.dev;
5567 struct drm_i915_private *dev_priv = dev->dev_private;
5568 enum pipe pipe = intel_crtc->pipe;
5569 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5570 struct drm_display_mode *adjusted_mode =
5571 &intel_crtc->config.adjusted_mode;
5572 uint32_t crtc_vtotal, crtc_vblank_end;
5575 /* We need to be careful not to changed the adjusted mode, for otherwise
5576 * the hw state checker will get angry at the mismatch. */
5577 crtc_vtotal = adjusted_mode->crtc_vtotal;
5578 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5580 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5581 /* the chip adds 2 halflines automatically */
5583 crtc_vblank_end -= 1;
5585 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5586 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5588 vsyncshift = adjusted_mode->crtc_hsync_start -
5589 adjusted_mode->crtc_htotal / 2;
5591 vsyncshift += adjusted_mode->crtc_htotal;
5594 if (INTEL_INFO(dev)->gen > 3)
5595 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5597 I915_WRITE(HTOTAL(cpu_transcoder),
5598 (adjusted_mode->crtc_hdisplay - 1) |
5599 ((adjusted_mode->crtc_htotal - 1) << 16));
5600 I915_WRITE(HBLANK(cpu_transcoder),
5601 (adjusted_mode->crtc_hblank_start - 1) |
5602 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5603 I915_WRITE(HSYNC(cpu_transcoder),
5604 (adjusted_mode->crtc_hsync_start - 1) |
5605 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5607 I915_WRITE(VTOTAL(cpu_transcoder),
5608 (adjusted_mode->crtc_vdisplay - 1) |
5609 ((crtc_vtotal - 1) << 16));
5610 I915_WRITE(VBLANK(cpu_transcoder),
5611 (adjusted_mode->crtc_vblank_start - 1) |
5612 ((crtc_vblank_end - 1) << 16));
5613 I915_WRITE(VSYNC(cpu_transcoder),
5614 (adjusted_mode->crtc_vsync_start - 1) |
5615 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5617 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5618 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5619 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5621 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5622 (pipe == PIPE_B || pipe == PIPE_C))
5623 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5625 /* pipesrc controls the size that is scaled from, which should
5626 * always be the user's requested size.
5628 I915_WRITE(PIPESRC(pipe),
5629 ((intel_crtc->config.pipe_src_w - 1) << 16) |
5630 (intel_crtc->config.pipe_src_h - 1));
5633 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5634 struct intel_crtc_config *pipe_config)
5636 struct drm_device *dev = crtc->base.dev;
5637 struct drm_i915_private *dev_priv = dev->dev_private;
5638 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5641 tmp = I915_READ(HTOTAL(cpu_transcoder));
5642 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5643 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5644 tmp = I915_READ(HBLANK(cpu_transcoder));
5645 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5646 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5647 tmp = I915_READ(HSYNC(cpu_transcoder));
5648 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5649 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5651 tmp = I915_READ(VTOTAL(cpu_transcoder));
5652 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5653 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5654 tmp = I915_READ(VBLANK(cpu_transcoder));
5655 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5656 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5657 tmp = I915_READ(VSYNC(cpu_transcoder));
5658 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5659 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5661 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5662 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5663 pipe_config->adjusted_mode.crtc_vtotal += 1;
5664 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5667 tmp = I915_READ(PIPESRC(crtc->pipe));
5668 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5669 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5671 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5672 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5675 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5676 struct intel_crtc_config *pipe_config)
5678 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5679 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5680 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5681 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5683 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5684 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5685 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5686 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5688 mode->flags = pipe_config->adjusted_mode.flags;
5690 mode->clock = pipe_config->adjusted_mode.crtc_clock;
5691 mode->flags |= pipe_config->adjusted_mode.flags;
5694 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5696 struct drm_device *dev = intel_crtc->base.dev;
5697 struct drm_i915_private *dev_priv = dev->dev_private;
5702 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5703 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5704 pipeconf |= PIPECONF_ENABLE;
5706 if (intel_crtc->config.double_wide)
5707 pipeconf |= PIPECONF_DOUBLE_WIDE;
5709 /* only g4x and later have fancy bpc/dither controls */
5710 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5711 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5712 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5713 pipeconf |= PIPECONF_DITHER_EN |
5714 PIPECONF_DITHER_TYPE_SP;
5716 switch (intel_crtc->config.pipe_bpp) {
5718 pipeconf |= PIPECONF_6BPC;
5721 pipeconf |= PIPECONF_8BPC;
5724 pipeconf |= PIPECONF_10BPC;
5727 /* Case prevented by intel_choose_pipe_bpp_dither. */
5732 if (HAS_PIPE_CXSR(dev)) {
5733 if (intel_crtc->lowfreq_avail) {
5734 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5735 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5737 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5741 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
5742 if (INTEL_INFO(dev)->gen < 4 ||
5743 intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5744 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5746 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
5748 pipeconf |= PIPECONF_PROGRESSIVE;
5750 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5751 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5753 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5754 POSTING_READ(PIPECONF(intel_crtc->pipe));
5757 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5759 struct drm_framebuffer *fb)
5761 struct drm_device *dev = crtc->dev;
5762 struct drm_i915_private *dev_priv = dev->dev_private;
5763 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5764 int pipe = intel_crtc->pipe;
5765 int plane = intel_crtc->plane;
5766 int refclk, num_connectors = 0;
5767 intel_clock_t clock, reduced_clock;
5769 bool ok, has_reduced_clock = false;
5770 bool is_lvds = false, is_dsi = false;
5771 struct intel_encoder *encoder;
5772 const intel_limit_t *limit;
5774 for_each_encoder_on_crtc(dev, crtc, encoder) {
5775 switch (encoder->type) {
5776 case INTEL_OUTPUT_LVDS:
5779 case INTEL_OUTPUT_DSI:
5790 if (!intel_crtc->config.clock_set) {
5791 refclk = i9xx_get_refclk(crtc, num_connectors);
5794 * Returns a set of divisors for the desired target clock with
5795 * the given refclk, or FALSE. The returned values represent
5796 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5799 limit = intel_limit(crtc, refclk);
5800 ok = dev_priv->display.find_dpll(limit, crtc,
5801 intel_crtc->config.port_clock,
5802 refclk, NULL, &clock);
5804 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5808 if (is_lvds && dev_priv->lvds_downclock_avail) {
5810 * Ensure we match the reduced clock's P to the target
5811 * clock. If the clocks don't match, we can't switch
5812 * the display clock by using the FP0/FP1. In such case
5813 * we will disable the LVDS downclock feature.
5816 dev_priv->display.find_dpll(limit, crtc,
5817 dev_priv->lvds_downclock,
5821 /* Compat-code for transition, will disappear. */
5822 intel_crtc->config.dpll.n = clock.n;
5823 intel_crtc->config.dpll.m1 = clock.m1;
5824 intel_crtc->config.dpll.m2 = clock.m2;
5825 intel_crtc->config.dpll.p1 = clock.p1;
5826 intel_crtc->config.dpll.p2 = clock.p2;
5830 i8xx_update_pll(intel_crtc,
5831 has_reduced_clock ? &reduced_clock : NULL,
5833 } else if (IS_CHERRYVIEW(dev)) {
5834 chv_update_pll(intel_crtc);
5835 } else if (IS_VALLEYVIEW(dev)) {
5836 vlv_update_pll(intel_crtc);
5838 i9xx_update_pll(intel_crtc,
5839 has_reduced_clock ? &reduced_clock : NULL,
5844 /* Set up the display plane register */
5845 dspcntr = DISPPLANE_GAMMA_ENABLE;
5847 if (!IS_VALLEYVIEW(dev)) {
5849 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5851 dspcntr |= DISPPLANE_SEL_PIPE_B;
5854 if (intel_crtc->config.has_dp_encoder)
5855 intel_dp_set_m_n(intel_crtc);
5857 intel_set_pipe_timings(intel_crtc);
5859 /* pipesrc and dspsize control the size that is scaled from,
5860 * which should always be the user's requested size.
5862 I915_WRITE(DSPSIZE(plane),
5863 ((intel_crtc->config.pipe_src_h - 1) << 16) |
5864 (intel_crtc->config.pipe_src_w - 1));
5865 I915_WRITE(DSPPOS(plane), 0);
5867 i9xx_set_pipeconf(intel_crtc);
5869 I915_WRITE(DSPCNTR(plane), dspcntr);
5870 POSTING_READ(DSPCNTR(plane));
5872 dev_priv->display.update_primary_plane(crtc, fb, x, y);
5877 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5878 struct intel_crtc_config *pipe_config)
5880 struct drm_device *dev = crtc->base.dev;
5881 struct drm_i915_private *dev_priv = dev->dev_private;
5884 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
5887 tmp = I915_READ(PFIT_CONTROL);
5888 if (!(tmp & PFIT_ENABLE))
5891 /* Check whether the pfit is attached to our pipe. */
5892 if (INTEL_INFO(dev)->gen < 4) {
5893 if (crtc->pipe != PIPE_B)
5896 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5900 pipe_config->gmch_pfit.control = tmp;
5901 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5902 if (INTEL_INFO(dev)->gen < 5)
5903 pipe_config->gmch_pfit.lvds_border_bits =
5904 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5907 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5908 struct intel_crtc_config *pipe_config)
5910 struct drm_device *dev = crtc->base.dev;
5911 struct drm_i915_private *dev_priv = dev->dev_private;
5912 int pipe = pipe_config->cpu_transcoder;
5913 intel_clock_t clock;
5915 int refclk = 100000;
5917 mutex_lock(&dev_priv->dpio_lock);
5918 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
5919 mutex_unlock(&dev_priv->dpio_lock);
5921 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5922 clock.m2 = mdiv & DPIO_M2DIV_MASK;
5923 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5924 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5925 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5927 vlv_clock(refclk, &clock);
5929 /* clock.dot is the fast clock */
5930 pipe_config->port_clock = clock.dot / 5;
5933 static void i9xx_get_plane_config(struct intel_crtc *crtc,
5934 struct intel_plane_config *plane_config)
5936 struct drm_device *dev = crtc->base.dev;
5937 struct drm_i915_private *dev_priv = dev->dev_private;
5938 u32 val, base, offset;
5939 int pipe = crtc->pipe, plane = crtc->plane;
5940 int fourcc, pixel_format;
5943 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
5944 if (!crtc->base.primary->fb) {
5945 DRM_DEBUG_KMS("failed to alloc fb\n");
5949 val = I915_READ(DSPCNTR(plane));
5951 if (INTEL_INFO(dev)->gen >= 4)
5952 if (val & DISPPLANE_TILED)
5953 plane_config->tiled = true;
5955 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
5956 fourcc = intel_format_to_fourcc(pixel_format);
5957 crtc->base.primary->fb->pixel_format = fourcc;
5958 crtc->base.primary->fb->bits_per_pixel =
5959 drm_format_plane_cpp(fourcc, 0) * 8;
5961 if (INTEL_INFO(dev)->gen >= 4) {
5962 if (plane_config->tiled)
5963 offset = I915_READ(DSPTILEOFF(plane));
5965 offset = I915_READ(DSPLINOFF(plane));
5966 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
5968 base = I915_READ(DSPADDR(plane));
5970 plane_config->base = base;
5972 val = I915_READ(PIPESRC(pipe));
5973 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
5974 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
5976 val = I915_READ(DSPSTRIDE(pipe));
5977 crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
5979 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
5980 plane_config->tiled);
5982 plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
5983 aligned_height, PAGE_SIZE);
5985 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
5986 pipe, plane, crtc->base.primary->fb->width,
5987 crtc->base.primary->fb->height,
5988 crtc->base.primary->fb->bits_per_pixel, base,
5989 crtc->base.primary->fb->pitches[0],
5990 plane_config->size);
5994 static void chv_crtc_clock_get(struct intel_crtc *crtc,
5995 struct intel_crtc_config *pipe_config)
5997 struct drm_device *dev = crtc->base.dev;
5998 struct drm_i915_private *dev_priv = dev->dev_private;
5999 int pipe = pipe_config->cpu_transcoder;
6000 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6001 intel_clock_t clock;
6002 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6003 int refclk = 100000;
6005 mutex_lock(&dev_priv->dpio_lock);
6006 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6007 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6008 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6009 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6010 mutex_unlock(&dev_priv->dpio_lock);
6012 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6013 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6014 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6015 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6016 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6018 chv_clock(refclk, &clock);
6020 /* clock.dot is the fast clock */
6021 pipe_config->port_clock = clock.dot / 5;
6024 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6025 struct intel_crtc_config *pipe_config)
6027 struct drm_device *dev = crtc->base.dev;
6028 struct drm_i915_private *dev_priv = dev->dev_private;
6031 if (!intel_display_power_enabled(dev_priv,
6032 POWER_DOMAIN_PIPE(crtc->pipe)))
6035 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6036 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6038 tmp = I915_READ(PIPECONF(crtc->pipe));
6039 if (!(tmp & PIPECONF_ENABLE))
6042 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6043 switch (tmp & PIPECONF_BPC_MASK) {
6045 pipe_config->pipe_bpp = 18;
6048 pipe_config->pipe_bpp = 24;
6050 case PIPECONF_10BPC:
6051 pipe_config->pipe_bpp = 30;
6058 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6059 pipe_config->limited_color_range = true;
6061 if (INTEL_INFO(dev)->gen < 4)
6062 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6064 intel_get_pipe_timings(crtc, pipe_config);
6066 i9xx_get_pfit_config(crtc, pipe_config);
6068 if (INTEL_INFO(dev)->gen >= 4) {
6069 tmp = I915_READ(DPLL_MD(crtc->pipe));
6070 pipe_config->pixel_multiplier =
6071 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6072 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6073 pipe_config->dpll_hw_state.dpll_md = tmp;
6074 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6075 tmp = I915_READ(DPLL(crtc->pipe));
6076 pipe_config->pixel_multiplier =
6077 ((tmp & SDVO_MULTIPLIER_MASK)
6078 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6080 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6081 * port and will be fixed up in the encoder->get_config
6083 pipe_config->pixel_multiplier = 1;
6085 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6086 if (!IS_VALLEYVIEW(dev)) {
6087 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6088 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6090 /* Mask out read-only status bits. */
6091 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6092 DPLL_PORTC_READY_MASK |
6093 DPLL_PORTB_READY_MASK);
6096 if (IS_CHERRYVIEW(dev))
6097 chv_crtc_clock_get(crtc, pipe_config);
6098 else if (IS_VALLEYVIEW(dev))
6099 vlv_crtc_clock_get(crtc, pipe_config);
6101 i9xx_crtc_clock_get(crtc, pipe_config);
6106 static void ironlake_init_pch_refclk(struct drm_device *dev)
6108 struct drm_i915_private *dev_priv = dev->dev_private;
6109 struct drm_mode_config *mode_config = &dev->mode_config;
6110 struct intel_encoder *encoder;
6112 bool has_lvds = false;
6113 bool has_cpu_edp = false;
6114 bool has_panel = false;
6115 bool has_ck505 = false;
6116 bool can_ssc = false;
6118 /* We need to take the global config into account */
6119 list_for_each_entry(encoder, &mode_config->encoder_list,
6121 switch (encoder->type) {
6122 case INTEL_OUTPUT_LVDS:
6126 case INTEL_OUTPUT_EDP:
6128 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6134 if (HAS_PCH_IBX(dev)) {
6135 has_ck505 = dev_priv->vbt.display_clock_mode;
6136 can_ssc = has_ck505;
6142 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6143 has_panel, has_lvds, has_ck505);
6145 /* Ironlake: try to setup display ref clock before DPLL
6146 * enabling. This is only under driver's control after
6147 * PCH B stepping, previous chipset stepping should be
6148 * ignoring this setting.
6150 val = I915_READ(PCH_DREF_CONTROL);
6152 /* As we must carefully and slowly disable/enable each source in turn,
6153 * compute the final state we want first and check if we need to
6154 * make any changes at all.
6157 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6159 final |= DREF_NONSPREAD_CK505_ENABLE;
6161 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6163 final &= ~DREF_SSC_SOURCE_MASK;
6164 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6165 final &= ~DREF_SSC1_ENABLE;
6168 final |= DREF_SSC_SOURCE_ENABLE;
6170 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6171 final |= DREF_SSC1_ENABLE;
6174 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6175 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6177 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6179 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6181 final |= DREF_SSC_SOURCE_DISABLE;
6182 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6188 /* Always enable nonspread source */
6189 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6192 val |= DREF_NONSPREAD_CK505_ENABLE;
6194 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6197 val &= ~DREF_SSC_SOURCE_MASK;
6198 val |= DREF_SSC_SOURCE_ENABLE;
6200 /* SSC must be turned on before enabling the CPU output */
6201 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6202 DRM_DEBUG_KMS("Using SSC on panel\n");
6203 val |= DREF_SSC1_ENABLE;
6205 val &= ~DREF_SSC1_ENABLE;
6207 /* Get SSC going before enabling the outputs */
6208 I915_WRITE(PCH_DREF_CONTROL, val);
6209 POSTING_READ(PCH_DREF_CONTROL);
6212 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6214 /* Enable CPU source on CPU attached eDP */
6216 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6217 DRM_DEBUG_KMS("Using SSC on eDP\n");
6218 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6220 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6222 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6224 I915_WRITE(PCH_DREF_CONTROL, val);
6225 POSTING_READ(PCH_DREF_CONTROL);
6228 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6230 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6232 /* Turn off CPU output */
6233 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6235 I915_WRITE(PCH_DREF_CONTROL, val);
6236 POSTING_READ(PCH_DREF_CONTROL);
6239 /* Turn off the SSC source */
6240 val &= ~DREF_SSC_SOURCE_MASK;
6241 val |= DREF_SSC_SOURCE_DISABLE;
6244 val &= ~DREF_SSC1_ENABLE;
6246 I915_WRITE(PCH_DREF_CONTROL, val);
6247 POSTING_READ(PCH_DREF_CONTROL);
6251 BUG_ON(val != final);
6254 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6258 tmp = I915_READ(SOUTH_CHICKEN2);
6259 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6260 I915_WRITE(SOUTH_CHICKEN2, tmp);
6262 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6263 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6264 DRM_ERROR("FDI mPHY reset assert timeout\n");
6266 tmp = I915_READ(SOUTH_CHICKEN2);
6267 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6268 I915_WRITE(SOUTH_CHICKEN2, tmp);
6270 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6271 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6272 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6275 /* WaMPhyProgramming:hsw */
6276 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6280 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6281 tmp &= ~(0xFF << 24);
6282 tmp |= (0x12 << 24);
6283 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6285 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6287 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6289 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6291 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6293 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6294 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6295 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6297 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6298 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6299 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6301 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6304 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6306 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6309 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6311 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6314 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6316 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6319 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6321 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6322 tmp &= ~(0xFF << 16);
6323 tmp |= (0x1C << 16);
6324 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6326 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6327 tmp &= ~(0xFF << 16);
6328 tmp |= (0x1C << 16);
6329 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6331 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6333 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6335 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6337 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6339 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6340 tmp &= ~(0xF << 28);
6342 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6344 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6345 tmp &= ~(0xF << 28);
6347 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6350 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6351 * Programming" based on the parameters passed:
6352 * - Sequence to enable CLKOUT_DP
6353 * - Sequence to enable CLKOUT_DP without spread
6354 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6356 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6359 struct drm_i915_private *dev_priv = dev->dev_private;
6362 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6364 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6365 with_fdi, "LP PCH doesn't have FDI\n"))
6368 mutex_lock(&dev_priv->dpio_lock);
6370 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6371 tmp &= ~SBI_SSCCTL_DISABLE;
6372 tmp |= SBI_SSCCTL_PATHALT;
6373 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6378 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6379 tmp &= ~SBI_SSCCTL_PATHALT;
6380 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6383 lpt_reset_fdi_mphy(dev_priv);
6384 lpt_program_fdi_mphy(dev_priv);
6388 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6389 SBI_GEN0 : SBI_DBUFF0;
6390 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6391 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6392 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6394 mutex_unlock(&dev_priv->dpio_lock);
6397 /* Sequence to disable CLKOUT_DP */
6398 static void lpt_disable_clkout_dp(struct drm_device *dev)
6400 struct drm_i915_private *dev_priv = dev->dev_private;
6403 mutex_lock(&dev_priv->dpio_lock);
6405 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6406 SBI_GEN0 : SBI_DBUFF0;
6407 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6408 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6409 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6411 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6412 if (!(tmp & SBI_SSCCTL_DISABLE)) {
6413 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6414 tmp |= SBI_SSCCTL_PATHALT;
6415 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6418 tmp |= SBI_SSCCTL_DISABLE;
6419 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6422 mutex_unlock(&dev_priv->dpio_lock);
6425 static void lpt_init_pch_refclk(struct drm_device *dev)
6427 struct drm_mode_config *mode_config = &dev->mode_config;
6428 struct intel_encoder *encoder;
6429 bool has_vga = false;
6431 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
6432 switch (encoder->type) {
6433 case INTEL_OUTPUT_ANALOG:
6440 lpt_enable_clkout_dp(dev, true, true);
6442 lpt_disable_clkout_dp(dev);
6446 * Initialize reference clocks when the driver loads
6448 void intel_init_pch_refclk(struct drm_device *dev)
6450 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6451 ironlake_init_pch_refclk(dev);
6452 else if (HAS_PCH_LPT(dev))
6453 lpt_init_pch_refclk(dev);
6456 static int ironlake_get_refclk(struct drm_crtc *crtc)
6458 struct drm_device *dev = crtc->dev;
6459 struct drm_i915_private *dev_priv = dev->dev_private;
6460 struct intel_encoder *encoder;
6461 int num_connectors = 0;
6462 bool is_lvds = false;
6464 for_each_encoder_on_crtc(dev, crtc, encoder) {
6465 switch (encoder->type) {
6466 case INTEL_OUTPUT_LVDS:
6473 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6474 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6475 dev_priv->vbt.lvds_ssc_freq);
6476 return dev_priv->vbt.lvds_ssc_freq;
6482 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6484 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6485 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6486 int pipe = intel_crtc->pipe;
6491 switch (intel_crtc->config.pipe_bpp) {
6493 val |= PIPECONF_6BPC;
6496 val |= PIPECONF_8BPC;
6499 val |= PIPECONF_10BPC;
6502 val |= PIPECONF_12BPC;
6505 /* Case prevented by intel_choose_pipe_bpp_dither. */
6509 if (intel_crtc->config.dither)
6510 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6512 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6513 val |= PIPECONF_INTERLACED_ILK;
6515 val |= PIPECONF_PROGRESSIVE;
6517 if (intel_crtc->config.limited_color_range)
6518 val |= PIPECONF_COLOR_RANGE_SELECT;
6520 I915_WRITE(PIPECONF(pipe), val);
6521 POSTING_READ(PIPECONF(pipe));
6525 * Set up the pipe CSC unit.
6527 * Currently only full range RGB to limited range RGB conversion
6528 * is supported, but eventually this should handle various
6529 * RGB<->YCbCr scenarios as well.
6531 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6533 struct drm_device *dev = crtc->dev;
6534 struct drm_i915_private *dev_priv = dev->dev_private;
6535 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6536 int pipe = intel_crtc->pipe;
6537 uint16_t coeff = 0x7800; /* 1.0 */
6540 * TODO: Check what kind of values actually come out of the pipe
6541 * with these coeff/postoff values and adjust to get the best
6542 * accuracy. Perhaps we even need to take the bpc value into
6546 if (intel_crtc->config.limited_color_range)
6547 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6550 * GY/GU and RY/RU should be the other way around according
6551 * to BSpec, but reality doesn't agree. Just set them up in
6552 * a way that results in the correct picture.
6554 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6555 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6557 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6558 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6560 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6561 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6563 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6564 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6565 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6567 if (INTEL_INFO(dev)->gen > 6) {
6568 uint16_t postoff = 0;
6570 if (intel_crtc->config.limited_color_range)
6571 postoff = (16 * (1 << 12) / 255) & 0x1fff;
6573 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6574 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6575 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6577 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6579 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6581 if (intel_crtc->config.limited_color_range)
6582 mode |= CSC_BLACK_SCREEN_OFFSET;
6584 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6588 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6590 struct drm_device *dev = crtc->dev;
6591 struct drm_i915_private *dev_priv = dev->dev_private;
6592 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6593 enum pipe pipe = intel_crtc->pipe;
6594 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6599 if (IS_HASWELL(dev) && intel_crtc->config.dither)
6600 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6602 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6603 val |= PIPECONF_INTERLACED_ILK;
6605 val |= PIPECONF_PROGRESSIVE;
6607 I915_WRITE(PIPECONF(cpu_transcoder), val);
6608 POSTING_READ(PIPECONF(cpu_transcoder));
6610 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6611 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6613 if (IS_BROADWELL(dev)) {
6616 switch (intel_crtc->config.pipe_bpp) {
6618 val |= PIPEMISC_DITHER_6_BPC;
6621 val |= PIPEMISC_DITHER_8_BPC;
6624 val |= PIPEMISC_DITHER_10_BPC;
6627 val |= PIPEMISC_DITHER_12_BPC;
6630 /* Case prevented by pipe_config_set_bpp. */
6634 if (intel_crtc->config.dither)
6635 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6637 I915_WRITE(PIPEMISC(pipe), val);
6641 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6642 intel_clock_t *clock,
6643 bool *has_reduced_clock,
6644 intel_clock_t *reduced_clock)
6646 struct drm_device *dev = crtc->dev;
6647 struct drm_i915_private *dev_priv = dev->dev_private;
6648 struct intel_encoder *intel_encoder;
6650 const intel_limit_t *limit;
6651 bool ret, is_lvds = false;
6653 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6654 switch (intel_encoder->type) {
6655 case INTEL_OUTPUT_LVDS:
6661 refclk = ironlake_get_refclk(crtc);
6664 * Returns a set of divisors for the desired target clock with the given
6665 * refclk, or FALSE. The returned values represent the clock equation:
6666 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6668 limit = intel_limit(crtc, refclk);
6669 ret = dev_priv->display.find_dpll(limit, crtc,
6670 to_intel_crtc(crtc)->config.port_clock,
6671 refclk, NULL, clock);
6675 if (is_lvds && dev_priv->lvds_downclock_avail) {
6677 * Ensure we match the reduced clock's P to the target clock.
6678 * If the clocks don't match, we can't switch the display clock
6679 * by using the FP0/FP1. In such case we will disable the LVDS
6680 * downclock feature.
6682 *has_reduced_clock =
6683 dev_priv->display.find_dpll(limit, crtc,
6684 dev_priv->lvds_downclock,
6692 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6695 * Account for spread spectrum to avoid
6696 * oversubscribing the link. Max center spread
6697 * is 2.5%; use 5% for safety's sake.
6699 u32 bps = target_clock * bpp * 21 / 20;
6700 return DIV_ROUND_UP(bps, link_bw * 8);
6703 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6705 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6708 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6710 intel_clock_t *reduced_clock, u32 *fp2)
6712 struct drm_crtc *crtc = &intel_crtc->base;
6713 struct drm_device *dev = crtc->dev;
6714 struct drm_i915_private *dev_priv = dev->dev_private;
6715 struct intel_encoder *intel_encoder;
6717 int factor, num_connectors = 0;
6718 bool is_lvds = false, is_sdvo = false;
6720 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6721 switch (intel_encoder->type) {
6722 case INTEL_OUTPUT_LVDS:
6725 case INTEL_OUTPUT_SDVO:
6726 case INTEL_OUTPUT_HDMI:
6734 /* Enable autotuning of the PLL clock (if permissible) */
6737 if ((intel_panel_use_ssc(dev_priv) &&
6738 dev_priv->vbt.lvds_ssc_freq == 100000) ||
6739 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6741 } else if (intel_crtc->config.sdvo_tv_clock)
6744 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6747 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6753 dpll |= DPLLB_MODE_LVDS;
6755 dpll |= DPLLB_MODE_DAC_SERIAL;
6757 dpll |= (intel_crtc->config.pixel_multiplier - 1)
6758 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6761 dpll |= DPLL_SDVO_HIGH_SPEED;
6762 if (intel_crtc->config.has_dp_encoder)
6763 dpll |= DPLL_SDVO_HIGH_SPEED;
6765 /* compute bitmask from p1 value */
6766 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6768 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6770 switch (intel_crtc->config.dpll.p2) {
6772 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6775 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6778 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6781 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6785 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6786 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6788 dpll |= PLL_REF_INPUT_DREFCLK;
6790 return dpll | DPLL_VCO_ENABLE;
6793 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
6795 struct drm_framebuffer *fb)
6797 struct drm_device *dev = crtc->dev;
6798 struct drm_i915_private *dev_priv = dev->dev_private;
6799 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6800 int pipe = intel_crtc->pipe;
6801 int plane = intel_crtc->plane;
6802 int num_connectors = 0;
6803 intel_clock_t clock, reduced_clock;
6804 u32 dpll = 0, fp = 0, fp2 = 0;
6805 bool ok, has_reduced_clock = false;
6806 bool is_lvds = false;
6807 struct intel_encoder *encoder;
6808 struct intel_shared_dpll *pll;
6810 for_each_encoder_on_crtc(dev, crtc, encoder) {
6811 switch (encoder->type) {
6812 case INTEL_OUTPUT_LVDS:
6820 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6821 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6823 ok = ironlake_compute_clocks(crtc, &clock,
6824 &has_reduced_clock, &reduced_clock);
6825 if (!ok && !intel_crtc->config.clock_set) {
6826 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6829 /* Compat-code for transition, will disappear. */
6830 if (!intel_crtc->config.clock_set) {
6831 intel_crtc->config.dpll.n = clock.n;
6832 intel_crtc->config.dpll.m1 = clock.m1;
6833 intel_crtc->config.dpll.m2 = clock.m2;
6834 intel_crtc->config.dpll.p1 = clock.p1;
6835 intel_crtc->config.dpll.p2 = clock.p2;
6838 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6839 if (intel_crtc->config.has_pch_encoder) {
6840 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6841 if (has_reduced_clock)
6842 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6844 dpll = ironlake_compute_dpll(intel_crtc,
6845 &fp, &reduced_clock,
6846 has_reduced_clock ? &fp2 : NULL);
6848 intel_crtc->config.dpll_hw_state.dpll = dpll;
6849 intel_crtc->config.dpll_hw_state.fp0 = fp;
6850 if (has_reduced_clock)
6851 intel_crtc->config.dpll_hw_state.fp1 = fp2;
6853 intel_crtc->config.dpll_hw_state.fp1 = fp;
6855 pll = intel_get_shared_dpll(intel_crtc);
6857 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6862 intel_put_shared_dpll(intel_crtc);
6864 if (intel_crtc->config.has_dp_encoder)
6865 intel_dp_set_m_n(intel_crtc);
6867 if (is_lvds && has_reduced_clock && i915.powersave)
6868 intel_crtc->lowfreq_avail = true;
6870 intel_crtc->lowfreq_avail = false;
6872 intel_set_pipe_timings(intel_crtc);
6874 if (intel_crtc->config.has_pch_encoder) {
6875 intel_cpu_transcoder_set_m_n(intel_crtc,
6876 &intel_crtc->config.fdi_m_n);
6879 ironlake_set_pipeconf(crtc);
6881 /* Set up the display plane register */
6882 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
6883 POSTING_READ(DSPCNTR(plane));
6885 dev_priv->display.update_primary_plane(crtc, fb, x, y);
6890 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6891 struct intel_link_m_n *m_n)
6893 struct drm_device *dev = crtc->base.dev;
6894 struct drm_i915_private *dev_priv = dev->dev_private;
6895 enum pipe pipe = crtc->pipe;
6897 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6898 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6899 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6901 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6902 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6903 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6906 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6907 enum transcoder transcoder,
6908 struct intel_link_m_n *m_n)
6910 struct drm_device *dev = crtc->base.dev;
6911 struct drm_i915_private *dev_priv = dev->dev_private;
6912 enum pipe pipe = crtc->pipe;
6914 if (INTEL_INFO(dev)->gen >= 5) {
6915 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6916 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6917 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6919 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6920 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6921 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6923 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6924 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6925 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6927 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6928 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6929 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6933 void intel_dp_get_m_n(struct intel_crtc *crtc,
6934 struct intel_crtc_config *pipe_config)
6936 if (crtc->config.has_pch_encoder)
6937 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6939 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6940 &pipe_config->dp_m_n);
6943 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6944 struct intel_crtc_config *pipe_config)
6946 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6947 &pipe_config->fdi_m_n);
6950 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6951 struct intel_crtc_config *pipe_config)
6953 struct drm_device *dev = crtc->base.dev;
6954 struct drm_i915_private *dev_priv = dev->dev_private;
6957 tmp = I915_READ(PF_CTL(crtc->pipe));
6959 if (tmp & PF_ENABLE) {
6960 pipe_config->pch_pfit.enabled = true;
6961 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6962 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
6964 /* We currently do not free assignements of panel fitters on
6965 * ivb/hsw (since we don't use the higher upscaling modes which
6966 * differentiates them) so just WARN about this case for now. */
6968 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6969 PF_PIPE_SEL_IVB(crtc->pipe));
6974 static void ironlake_get_plane_config(struct intel_crtc *crtc,
6975 struct intel_plane_config *plane_config)
6977 struct drm_device *dev = crtc->base.dev;
6978 struct drm_i915_private *dev_priv = dev->dev_private;
6979 u32 val, base, offset;
6980 int pipe = crtc->pipe, plane = crtc->plane;
6981 int fourcc, pixel_format;
6984 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6985 if (!crtc->base.primary->fb) {
6986 DRM_DEBUG_KMS("failed to alloc fb\n");
6990 val = I915_READ(DSPCNTR(plane));
6992 if (INTEL_INFO(dev)->gen >= 4)
6993 if (val & DISPPLANE_TILED)
6994 plane_config->tiled = true;
6996 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6997 fourcc = intel_format_to_fourcc(pixel_format);
6998 crtc->base.primary->fb->pixel_format = fourcc;
6999 crtc->base.primary->fb->bits_per_pixel =
7000 drm_format_plane_cpp(fourcc, 0) * 8;
7002 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7003 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7004 offset = I915_READ(DSPOFFSET(plane));
7006 if (plane_config->tiled)
7007 offset = I915_READ(DSPTILEOFF(plane));
7009 offset = I915_READ(DSPLINOFF(plane));
7011 plane_config->base = base;
7013 val = I915_READ(PIPESRC(pipe));
7014 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7015 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7017 val = I915_READ(DSPSTRIDE(pipe));
7018 crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
7020 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7021 plane_config->tiled);
7023 plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
7024 aligned_height, PAGE_SIZE);
7026 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7027 pipe, plane, crtc->base.primary->fb->width,
7028 crtc->base.primary->fb->height,
7029 crtc->base.primary->fb->bits_per_pixel, base,
7030 crtc->base.primary->fb->pitches[0],
7031 plane_config->size);
7034 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7035 struct intel_crtc_config *pipe_config)
7037 struct drm_device *dev = crtc->base.dev;
7038 struct drm_i915_private *dev_priv = dev->dev_private;
7041 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7042 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7044 tmp = I915_READ(PIPECONF(crtc->pipe));
7045 if (!(tmp & PIPECONF_ENABLE))
7048 switch (tmp & PIPECONF_BPC_MASK) {
7050 pipe_config->pipe_bpp = 18;
7053 pipe_config->pipe_bpp = 24;
7055 case PIPECONF_10BPC:
7056 pipe_config->pipe_bpp = 30;
7058 case PIPECONF_12BPC:
7059 pipe_config->pipe_bpp = 36;
7065 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7066 pipe_config->limited_color_range = true;
7068 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7069 struct intel_shared_dpll *pll;
7071 pipe_config->has_pch_encoder = true;
7073 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7074 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7075 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7077 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7079 if (HAS_PCH_IBX(dev_priv->dev)) {
7080 pipe_config->shared_dpll =
7081 (enum intel_dpll_id) crtc->pipe;
7083 tmp = I915_READ(PCH_DPLL_SEL);
7084 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7085 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7087 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7090 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7092 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7093 &pipe_config->dpll_hw_state));
7095 tmp = pipe_config->dpll_hw_state.dpll;
7096 pipe_config->pixel_multiplier =
7097 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7098 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7100 ironlake_pch_clock_get(crtc, pipe_config);
7102 pipe_config->pixel_multiplier = 1;
7105 intel_get_pipe_timings(crtc, pipe_config);
7107 ironlake_get_pfit_config(crtc, pipe_config);
7112 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7114 struct drm_device *dev = dev_priv->dev;
7115 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
7116 struct intel_crtc *crtc;
7118 for_each_intel_crtc(dev, crtc)
7119 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7120 pipe_name(crtc->pipe));
7122 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7123 WARN(plls->spll_refcount, "SPLL enabled\n");
7124 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
7125 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
7126 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7127 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7128 "CPU PWM1 enabled\n");
7129 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7130 "CPU PWM2 enabled\n");
7131 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7132 "PCH PWM1 enabled\n");
7133 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7134 "Utility pin enabled\n");
7135 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7138 * In theory we can still leave IRQs enabled, as long as only the HPD
7139 * interrupts remain enabled. We used to check for that, but since it's
7140 * gen-specific and since we only disable LCPLL after we fully disable
7141 * the interrupts, the check below should be enough.
7143 WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n");
7146 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7148 struct drm_device *dev = dev_priv->dev;
7150 if (IS_HASWELL(dev)) {
7151 mutex_lock(&dev_priv->rps.hw_lock);
7152 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7154 DRM_ERROR("Failed to disable D_COMP\n");
7155 mutex_unlock(&dev_priv->rps.hw_lock);
7157 I915_WRITE(D_COMP, val);
7159 POSTING_READ(D_COMP);
7163 * This function implements pieces of two sequences from BSpec:
7164 * - Sequence for display software to disable LCPLL
7165 * - Sequence for display software to allow package C8+
7166 * The steps implemented here are just the steps that actually touch the LCPLL
7167 * register. Callers should take care of disabling all the display engine
7168 * functions, doing the mode unset, fixing interrupts, etc.
7170 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7171 bool switch_to_fclk, bool allow_power_down)
7175 assert_can_disable_lcpll(dev_priv);
7177 val = I915_READ(LCPLL_CTL);
7179 if (switch_to_fclk) {
7180 val |= LCPLL_CD_SOURCE_FCLK;
7181 I915_WRITE(LCPLL_CTL, val);
7183 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7184 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7185 DRM_ERROR("Switching to FCLK failed\n");
7187 val = I915_READ(LCPLL_CTL);
7190 val |= LCPLL_PLL_DISABLE;
7191 I915_WRITE(LCPLL_CTL, val);
7192 POSTING_READ(LCPLL_CTL);
7194 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7195 DRM_ERROR("LCPLL still locked\n");
7197 val = I915_READ(D_COMP);
7198 val |= D_COMP_COMP_DISABLE;
7199 hsw_write_dcomp(dev_priv, val);
7202 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
7203 DRM_ERROR("D_COMP RCOMP still in progress\n");
7205 if (allow_power_down) {
7206 val = I915_READ(LCPLL_CTL);
7207 val |= LCPLL_POWER_DOWN_ALLOW;
7208 I915_WRITE(LCPLL_CTL, val);
7209 POSTING_READ(LCPLL_CTL);
7214 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7217 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7220 unsigned long irqflags;
7222 val = I915_READ(LCPLL_CTL);
7224 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7225 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7229 * Make sure we're not on PC8 state before disabling PC8, otherwise
7230 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7232 * The other problem is that hsw_restore_lcpll() is called as part of
7233 * the runtime PM resume sequence, so we can't just call
7234 * gen6_gt_force_wake_get() because that function calls
7235 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7236 * while we are on the resume sequence. So to solve this problem we have
7237 * to call special forcewake code that doesn't touch runtime PM and
7238 * doesn't enable the forcewake delayed work.
7240 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7241 if (dev_priv->uncore.forcewake_count++ == 0)
7242 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7243 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7245 if (val & LCPLL_POWER_DOWN_ALLOW) {
7246 val &= ~LCPLL_POWER_DOWN_ALLOW;
7247 I915_WRITE(LCPLL_CTL, val);
7248 POSTING_READ(LCPLL_CTL);
7251 val = I915_READ(D_COMP);
7252 val |= D_COMP_COMP_FORCE;
7253 val &= ~D_COMP_COMP_DISABLE;
7254 hsw_write_dcomp(dev_priv, val);
7256 val = I915_READ(LCPLL_CTL);
7257 val &= ~LCPLL_PLL_DISABLE;
7258 I915_WRITE(LCPLL_CTL, val);
7260 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7261 DRM_ERROR("LCPLL not locked yet\n");
7263 if (val & LCPLL_CD_SOURCE_FCLK) {
7264 val = I915_READ(LCPLL_CTL);
7265 val &= ~LCPLL_CD_SOURCE_FCLK;
7266 I915_WRITE(LCPLL_CTL, val);
7268 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7269 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7270 DRM_ERROR("Switching back to LCPLL failed\n");
7273 /* See the big comment above. */
7274 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7275 if (--dev_priv->uncore.forcewake_count == 0)
7276 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7277 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7281 * Package states C8 and deeper are really deep PC states that can only be
7282 * reached when all the devices on the system allow it, so even if the graphics
7283 * device allows PC8+, it doesn't mean the system will actually get to these
7284 * states. Our driver only allows PC8+ when going into runtime PM.
7286 * The requirements for PC8+ are that all the outputs are disabled, the power
7287 * well is disabled and most interrupts are disabled, and these are also
7288 * requirements for runtime PM. When these conditions are met, we manually do
7289 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7290 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7293 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7294 * the state of some registers, so when we come back from PC8+ we need to
7295 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7296 * need to take care of the registers kept by RC6. Notice that this happens even
7297 * if we don't put the device in PCI D3 state (which is what currently happens
7298 * because of the runtime PM support).
7300 * For more, read "Display Sequences for Package C8" on the hardware
7303 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7305 struct drm_device *dev = dev_priv->dev;
7308 DRM_DEBUG_KMS("Enabling package C8+\n");
7310 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7311 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7312 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7313 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7316 lpt_disable_clkout_dp(dev);
7317 hsw_disable_lcpll(dev_priv, true, true);
7320 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7322 struct drm_device *dev = dev_priv->dev;
7325 DRM_DEBUG_KMS("Disabling package C8+\n");
7327 hsw_restore_lcpll(dev_priv);
7328 lpt_init_pch_refclk(dev);
7330 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7331 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7332 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7333 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7336 intel_prepare_ddi(dev);
7339 static void snb_modeset_global_resources(struct drm_device *dev)
7341 modeset_update_crtc_power_domains(dev);
7344 static void haswell_modeset_global_resources(struct drm_device *dev)
7346 modeset_update_crtc_power_domains(dev);
7349 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7351 struct drm_framebuffer *fb)
7353 struct drm_device *dev = crtc->dev;
7354 struct drm_i915_private *dev_priv = dev->dev_private;
7355 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7356 int plane = intel_crtc->plane;
7358 if (!intel_ddi_pll_select(intel_crtc))
7360 intel_ddi_pll_enable(intel_crtc);
7362 if (intel_crtc->config.has_dp_encoder)
7363 intel_dp_set_m_n(intel_crtc);
7365 intel_crtc->lowfreq_avail = false;
7367 intel_set_pipe_timings(intel_crtc);
7369 if (intel_crtc->config.has_pch_encoder) {
7370 intel_cpu_transcoder_set_m_n(intel_crtc,
7371 &intel_crtc->config.fdi_m_n);
7374 haswell_set_pipeconf(crtc);
7376 intel_set_pipe_csc(crtc);
7378 /* Set up the display plane register */
7379 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
7380 POSTING_READ(DSPCNTR(plane));
7382 dev_priv->display.update_primary_plane(crtc, fb, x, y);
7387 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7388 struct intel_crtc_config *pipe_config)
7390 struct drm_device *dev = crtc->base.dev;
7391 struct drm_i915_private *dev_priv = dev->dev_private;
7392 enum intel_display_power_domain pfit_domain;
7395 if (!intel_display_power_enabled(dev_priv,
7396 POWER_DOMAIN_PIPE(crtc->pipe)))
7399 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7400 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7402 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7403 if (tmp & TRANS_DDI_FUNC_ENABLE) {
7404 enum pipe trans_edp_pipe;
7405 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7407 WARN(1, "unknown pipe linked to edp transcoder\n");
7408 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7409 case TRANS_DDI_EDP_INPUT_A_ON:
7410 trans_edp_pipe = PIPE_A;
7412 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7413 trans_edp_pipe = PIPE_B;
7415 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7416 trans_edp_pipe = PIPE_C;
7420 if (trans_edp_pipe == crtc->pipe)
7421 pipe_config->cpu_transcoder = TRANSCODER_EDP;
7424 if (!intel_display_power_enabled(dev_priv,
7425 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7428 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7429 if (!(tmp & PIPECONF_ENABLE))
7433 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7434 * DDI E. So just check whether this pipe is wired to DDI E and whether
7435 * the PCH transcoder is on.
7437 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7438 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
7439 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7440 pipe_config->has_pch_encoder = true;
7442 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7443 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7444 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7446 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7449 intel_get_pipe_timings(crtc, pipe_config);
7451 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7452 if (intel_display_power_enabled(dev_priv, pfit_domain))
7453 ironlake_get_pfit_config(crtc, pipe_config);
7455 if (IS_HASWELL(dev))
7456 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7457 (I915_READ(IPS_CTL) & IPS_ENABLE);
7459 pipe_config->pixel_multiplier = 1;
7467 } hdmi_audio_clock[] = {
7468 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7469 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7470 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7471 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7472 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7473 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7474 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7475 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7476 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7477 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7480 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7481 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7485 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7486 if (mode->clock == hdmi_audio_clock[i].clock)
7490 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7491 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7495 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7496 hdmi_audio_clock[i].clock,
7497 hdmi_audio_clock[i].config);
7499 return hdmi_audio_clock[i].config;
7502 static bool intel_eld_uptodate(struct drm_connector *connector,
7503 int reg_eldv, uint32_t bits_eldv,
7504 int reg_elda, uint32_t bits_elda,
7507 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7508 uint8_t *eld = connector->eld;
7511 i = I915_READ(reg_eldv);
7520 i = I915_READ(reg_elda);
7522 I915_WRITE(reg_elda, i);
7524 for (i = 0; i < eld[2]; i++)
7525 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7531 static void g4x_write_eld(struct drm_connector *connector,
7532 struct drm_crtc *crtc,
7533 struct drm_display_mode *mode)
7535 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7536 uint8_t *eld = connector->eld;
7541 i = I915_READ(G4X_AUD_VID_DID);
7543 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7544 eldv = G4X_ELDV_DEVCL_DEVBLC;
7546 eldv = G4X_ELDV_DEVCTG;
7548 if (intel_eld_uptodate(connector,
7549 G4X_AUD_CNTL_ST, eldv,
7550 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7551 G4X_HDMIW_HDMIEDID))
7554 i = I915_READ(G4X_AUD_CNTL_ST);
7555 i &= ~(eldv | G4X_ELD_ADDR);
7556 len = (i >> 9) & 0x1f; /* ELD buffer size */
7557 I915_WRITE(G4X_AUD_CNTL_ST, i);
7562 len = min_t(uint8_t, eld[2], len);
7563 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7564 for (i = 0; i < len; i++)
7565 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7567 i = I915_READ(G4X_AUD_CNTL_ST);
7569 I915_WRITE(G4X_AUD_CNTL_ST, i);
7572 static void haswell_write_eld(struct drm_connector *connector,
7573 struct drm_crtc *crtc,
7574 struct drm_display_mode *mode)
7576 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7577 uint8_t *eld = connector->eld;
7581 int pipe = to_intel_crtc(crtc)->pipe;
7584 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7585 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7586 int aud_config = HSW_AUD_CFG(pipe);
7587 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7589 /* Audio output enable */
7590 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7591 tmp = I915_READ(aud_cntrl_st2);
7592 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7593 I915_WRITE(aud_cntrl_st2, tmp);
7594 POSTING_READ(aud_cntrl_st2);
7596 assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
7598 /* Set ELD valid state */
7599 tmp = I915_READ(aud_cntrl_st2);
7600 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7601 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7602 I915_WRITE(aud_cntrl_st2, tmp);
7603 tmp = I915_READ(aud_cntrl_st2);
7604 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7606 /* Enable HDMI mode */
7607 tmp = I915_READ(aud_config);
7608 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7609 /* clear N_programing_enable and N_value_index */
7610 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7611 I915_WRITE(aud_config, tmp);
7613 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7615 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7617 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7618 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7619 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7620 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7622 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7625 if (intel_eld_uptodate(connector,
7626 aud_cntrl_st2, eldv,
7627 aud_cntl_st, IBX_ELD_ADDRESS,
7631 i = I915_READ(aud_cntrl_st2);
7633 I915_WRITE(aud_cntrl_st2, i);
7638 i = I915_READ(aud_cntl_st);
7639 i &= ~IBX_ELD_ADDRESS;
7640 I915_WRITE(aud_cntl_st, i);
7641 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
7642 DRM_DEBUG_DRIVER("port num:%d\n", i);
7644 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7645 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7646 for (i = 0; i < len; i++)
7647 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7649 i = I915_READ(aud_cntrl_st2);
7651 I915_WRITE(aud_cntrl_st2, i);
7655 static void ironlake_write_eld(struct drm_connector *connector,
7656 struct drm_crtc *crtc,
7657 struct drm_display_mode *mode)
7659 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7660 uint8_t *eld = connector->eld;
7668 int pipe = to_intel_crtc(crtc)->pipe;
7670 if (HAS_PCH_IBX(connector->dev)) {
7671 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7672 aud_config = IBX_AUD_CFG(pipe);
7673 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7674 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7675 } else if (IS_VALLEYVIEW(connector->dev)) {
7676 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7677 aud_config = VLV_AUD_CFG(pipe);
7678 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7679 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7681 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7682 aud_config = CPT_AUD_CFG(pipe);
7683 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7684 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7687 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7689 if (IS_VALLEYVIEW(connector->dev)) {
7690 struct intel_encoder *intel_encoder;
7691 struct intel_digital_port *intel_dig_port;
7693 intel_encoder = intel_attached_encoder(connector);
7694 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7695 i = intel_dig_port->port;
7697 i = I915_READ(aud_cntl_st);
7698 i = (i >> 29) & DIP_PORT_SEL_MASK;
7699 /* DIP_Port_Select, 0x1 = PortB */
7703 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7704 /* operate blindly on all ports */
7705 eldv = IBX_ELD_VALIDB;
7706 eldv |= IBX_ELD_VALIDB << 4;
7707 eldv |= IBX_ELD_VALIDB << 8;
7709 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7710 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7713 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7714 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7715 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7716 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7718 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7721 if (intel_eld_uptodate(connector,
7722 aud_cntrl_st2, eldv,
7723 aud_cntl_st, IBX_ELD_ADDRESS,
7727 i = I915_READ(aud_cntrl_st2);
7729 I915_WRITE(aud_cntrl_st2, i);
7734 i = I915_READ(aud_cntl_st);
7735 i &= ~IBX_ELD_ADDRESS;
7736 I915_WRITE(aud_cntl_st, i);
7738 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7739 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7740 for (i = 0; i < len; i++)
7741 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7743 i = I915_READ(aud_cntrl_st2);
7745 I915_WRITE(aud_cntrl_st2, i);
7748 void intel_write_eld(struct drm_encoder *encoder,
7749 struct drm_display_mode *mode)
7751 struct drm_crtc *crtc = encoder->crtc;
7752 struct drm_connector *connector;
7753 struct drm_device *dev = encoder->dev;
7754 struct drm_i915_private *dev_priv = dev->dev_private;
7756 connector = drm_select_eld(encoder, mode);
7760 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7762 drm_get_connector_name(connector),
7763 connector->encoder->base.id,
7764 drm_get_encoder_name(connector->encoder));
7766 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7768 if (dev_priv->display.write_eld)
7769 dev_priv->display.write_eld(connector, crtc, mode);
7772 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7774 struct drm_device *dev = crtc->dev;
7775 struct drm_i915_private *dev_priv = dev->dev_private;
7776 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7777 bool visible = base != 0;
7780 if (intel_crtc->cursor_visible == visible)
7783 cntl = I915_READ(_CURACNTR);
7785 /* On these chipsets we can only modify the base whilst
7786 * the cursor is disabled.
7788 I915_WRITE(_CURABASE, base);
7790 cntl &= ~(CURSOR_FORMAT_MASK);
7791 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7792 cntl |= CURSOR_ENABLE |
7793 CURSOR_GAMMA_ENABLE |
7796 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
7797 I915_WRITE(_CURACNTR, cntl);
7799 intel_crtc->cursor_visible = visible;
7802 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7804 struct drm_device *dev = crtc->dev;
7805 struct drm_i915_private *dev_priv = dev->dev_private;
7806 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7807 int pipe = intel_crtc->pipe;
7808 bool visible = base != 0;
7810 if (intel_crtc->cursor_visible != visible) {
7811 int16_t width = intel_crtc->cursor_width;
7812 uint32_t cntl = I915_READ(CURCNTR(pipe));
7814 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7815 cntl |= MCURSOR_GAMMA_ENABLE;
7819 cntl |= CURSOR_MODE_64_ARGB_AX;
7822 cntl |= CURSOR_MODE_128_ARGB_AX;
7825 cntl |= CURSOR_MODE_256_ARGB_AX;
7831 cntl |= pipe << 28; /* Connect to correct pipe */
7833 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7834 cntl |= CURSOR_MODE_DISABLE;
7836 I915_WRITE(CURCNTR(pipe), cntl);
7838 intel_crtc->cursor_visible = visible;
7840 /* and commit changes on next vblank */
7841 POSTING_READ(CURCNTR(pipe));
7842 I915_WRITE(CURBASE(pipe), base);
7843 POSTING_READ(CURBASE(pipe));
7846 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7848 struct drm_device *dev = crtc->dev;
7849 struct drm_i915_private *dev_priv = dev->dev_private;
7850 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7851 int pipe = intel_crtc->pipe;
7852 bool visible = base != 0;
7854 if (intel_crtc->cursor_visible != visible) {
7855 int16_t width = intel_crtc->cursor_width;
7856 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7858 cntl &= ~CURSOR_MODE;
7859 cntl |= MCURSOR_GAMMA_ENABLE;
7862 cntl |= CURSOR_MODE_64_ARGB_AX;
7865 cntl |= CURSOR_MODE_128_ARGB_AX;
7868 cntl |= CURSOR_MODE_256_ARGB_AX;
7875 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7876 cntl |= CURSOR_MODE_DISABLE;
7878 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7879 cntl |= CURSOR_PIPE_CSC_ENABLE;
7880 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7882 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7884 intel_crtc->cursor_visible = visible;
7886 /* and commit changes on next vblank */
7887 POSTING_READ(CURCNTR_IVB(pipe));
7888 I915_WRITE(CURBASE_IVB(pipe), base);
7889 POSTING_READ(CURBASE_IVB(pipe));
7892 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7893 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7896 struct drm_device *dev = crtc->dev;
7897 struct drm_i915_private *dev_priv = dev->dev_private;
7898 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7899 int pipe = intel_crtc->pipe;
7900 int x = intel_crtc->cursor_x;
7901 int y = intel_crtc->cursor_y;
7902 u32 base = 0, pos = 0;
7906 base = intel_crtc->cursor_addr;
7908 if (x >= intel_crtc->config.pipe_src_w)
7911 if (y >= intel_crtc->config.pipe_src_h)
7915 if (x + intel_crtc->cursor_width <= 0)
7918 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7921 pos |= x << CURSOR_X_SHIFT;
7924 if (y + intel_crtc->cursor_height <= 0)
7927 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7930 pos |= y << CURSOR_Y_SHIFT;
7932 visible = base != 0;
7933 if (!visible && !intel_crtc->cursor_visible)
7936 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7937 I915_WRITE(CURPOS_IVB(pipe), pos);
7938 ivb_update_cursor(crtc, base);
7940 I915_WRITE(CURPOS(pipe), pos);
7941 if (IS_845G(dev) || IS_I865G(dev))
7942 i845_update_cursor(crtc, base);
7944 i9xx_update_cursor(crtc, base);
7948 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
7949 struct drm_file *file,
7951 uint32_t width, uint32_t height)
7953 struct drm_device *dev = crtc->dev;
7954 struct drm_i915_private *dev_priv = dev->dev_private;
7955 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7956 struct drm_i915_gem_object *obj;
7961 /* if we want to turn off the cursor ignore width and height */
7963 DRM_DEBUG_KMS("cursor off\n");
7966 mutex_lock(&dev->struct_mutex);
7970 /* Check for which cursor types we support */
7971 if (!((width == 64 && height == 64) ||
7972 (width == 128 && height == 128 && !IS_GEN2(dev)) ||
7973 (width == 256 && height == 256 && !IS_GEN2(dev)))) {
7974 DRM_DEBUG("Cursor dimension not supported\n");
7978 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
7979 if (&obj->base == NULL)
7982 if (obj->base.size < width * height * 4) {
7983 DRM_DEBUG_KMS("buffer is to small\n");
7988 /* we only need to pin inside GTT if cursor is non-phy */
7989 mutex_lock(&dev->struct_mutex);
7990 if (!INTEL_INFO(dev)->cursor_needs_physical) {
7993 if (obj->tiling_mode) {
7994 DRM_DEBUG_KMS("cursor cannot be tiled\n");
7999 /* Note that the w/a also requires 2 PTE of padding following
8000 * the bo. We currently fill all unused PTE with the shadow
8001 * page and so we should always have valid PTE following the
8002 * cursor preventing the VT-d warning.
8005 if (need_vtd_wa(dev))
8006 alignment = 64*1024;
8008 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8010 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8014 ret = i915_gem_object_put_fence(obj);
8016 DRM_DEBUG_KMS("failed to release fence for cursor");
8020 addr = i915_gem_obj_ggtt_offset(obj);
8022 int align = IS_I830(dev) ? 16 * 1024 : 256;
8023 ret = i915_gem_attach_phys_object(dev, obj,
8024 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
8027 DRM_DEBUG_KMS("failed to attach phys object\n");
8030 addr = obj->phys_obj->handle->busaddr;
8034 I915_WRITE(CURSIZE, (height << 12) | width);
8037 if (intel_crtc->cursor_bo) {
8038 if (INTEL_INFO(dev)->cursor_needs_physical) {
8039 if (intel_crtc->cursor_bo != obj)
8040 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
8042 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8043 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
8046 mutex_unlock(&dev->struct_mutex);
8048 old_width = intel_crtc->cursor_width;
8050 intel_crtc->cursor_addr = addr;
8051 intel_crtc->cursor_bo = obj;
8052 intel_crtc->cursor_width = width;
8053 intel_crtc->cursor_height = height;
8055 if (intel_crtc->active) {
8056 if (old_width != width)
8057 intel_update_watermarks(crtc);
8058 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8063 i915_gem_object_unpin_from_display_plane(obj);
8065 mutex_unlock(&dev->struct_mutex);
8067 drm_gem_object_unreference_unlocked(&obj->base);
8071 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
8073 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8075 intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
8076 intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
8078 if (intel_crtc->active)
8079 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8084 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8085 u16 *blue, uint32_t start, uint32_t size)
8087 int end = (start + size > 256) ? 256 : start + size, i;
8088 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8090 for (i = start; i < end; i++) {
8091 intel_crtc->lut_r[i] = red[i] >> 8;
8092 intel_crtc->lut_g[i] = green[i] >> 8;
8093 intel_crtc->lut_b[i] = blue[i] >> 8;
8096 intel_crtc_load_lut(crtc);
8099 /* VESA 640x480x72Hz mode to set on the pipe */
8100 static struct drm_display_mode load_detect_mode = {
8101 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8102 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8105 struct drm_framebuffer *
8106 __intel_framebuffer_create(struct drm_device *dev,
8107 struct drm_mode_fb_cmd2 *mode_cmd,
8108 struct drm_i915_gem_object *obj)
8110 struct intel_framebuffer *intel_fb;
8113 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8115 drm_gem_object_unreference_unlocked(&obj->base);
8116 return ERR_PTR(-ENOMEM);
8119 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8123 return &intel_fb->base;
8125 drm_gem_object_unreference_unlocked(&obj->base);
8128 return ERR_PTR(ret);
8131 static struct drm_framebuffer *
8132 intel_framebuffer_create(struct drm_device *dev,
8133 struct drm_mode_fb_cmd2 *mode_cmd,
8134 struct drm_i915_gem_object *obj)
8136 struct drm_framebuffer *fb;
8139 ret = i915_mutex_lock_interruptible(dev);
8141 return ERR_PTR(ret);
8142 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8143 mutex_unlock(&dev->struct_mutex);
8149 intel_framebuffer_pitch_for_width(int width, int bpp)
8151 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8152 return ALIGN(pitch, 64);
8156 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8158 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8159 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
8162 static struct drm_framebuffer *
8163 intel_framebuffer_create_for_mode(struct drm_device *dev,
8164 struct drm_display_mode *mode,
8167 struct drm_i915_gem_object *obj;
8168 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8170 obj = i915_gem_alloc_object(dev,
8171 intel_framebuffer_size_for_mode(mode, bpp));
8173 return ERR_PTR(-ENOMEM);
8175 mode_cmd.width = mode->hdisplay;
8176 mode_cmd.height = mode->vdisplay;
8177 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8179 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8181 return intel_framebuffer_create(dev, &mode_cmd, obj);
8184 static struct drm_framebuffer *
8185 mode_fits_in_fbdev(struct drm_device *dev,
8186 struct drm_display_mode *mode)
8188 #ifdef CONFIG_DRM_I915_FBDEV
8189 struct drm_i915_private *dev_priv = dev->dev_private;
8190 struct drm_i915_gem_object *obj;
8191 struct drm_framebuffer *fb;
8193 if (!dev_priv->fbdev)
8196 if (!dev_priv->fbdev->fb)
8199 obj = dev_priv->fbdev->fb->obj;
8202 fb = &dev_priv->fbdev->fb->base;
8203 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8204 fb->bits_per_pixel))
8207 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8216 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8217 struct drm_display_mode *mode,
8218 struct intel_load_detect_pipe *old)
8220 struct intel_crtc *intel_crtc;
8221 struct intel_encoder *intel_encoder =
8222 intel_attached_encoder(connector);
8223 struct drm_crtc *possible_crtc;
8224 struct drm_encoder *encoder = &intel_encoder->base;
8225 struct drm_crtc *crtc = NULL;
8226 struct drm_device *dev = encoder->dev;
8227 struct drm_framebuffer *fb;
8230 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8231 connector->base.id, drm_get_connector_name(connector),
8232 encoder->base.id, drm_get_encoder_name(encoder));
8235 * Algorithm gets a little messy:
8237 * - if the connector already has an assigned crtc, use it (but make
8238 * sure it's on first)
8240 * - try to find the first unused crtc that can drive this connector,
8241 * and use that if we find one
8244 /* See if we already have a CRTC for this connector */
8245 if (encoder->crtc) {
8246 crtc = encoder->crtc;
8248 mutex_lock(&crtc->mutex);
8250 old->dpms_mode = connector->dpms;
8251 old->load_detect_temp = false;
8253 /* Make sure the crtc and connector are running */
8254 if (connector->dpms != DRM_MODE_DPMS_ON)
8255 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8260 /* Find an unused one (if possible) */
8261 for_each_crtc(dev, possible_crtc) {
8263 if (!(encoder->possible_crtcs & (1 << i)))
8265 if (!possible_crtc->enabled) {
8266 crtc = possible_crtc;
8272 * If we didn't find an unused CRTC, don't use any.
8275 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8279 mutex_lock(&crtc->mutex);
8280 intel_encoder->new_crtc = to_intel_crtc(crtc);
8281 to_intel_connector(connector)->new_encoder = intel_encoder;
8283 intel_crtc = to_intel_crtc(crtc);
8284 intel_crtc->new_enabled = true;
8285 intel_crtc->new_config = &intel_crtc->config;
8286 old->dpms_mode = connector->dpms;
8287 old->load_detect_temp = true;
8288 old->release_fb = NULL;
8291 mode = &load_detect_mode;
8293 /* We need a framebuffer large enough to accommodate all accesses
8294 * that the plane may generate whilst we perform load detection.
8295 * We can not rely on the fbcon either being present (we get called
8296 * during its initialisation to detect all boot displays, or it may
8297 * not even exist) or that it is large enough to satisfy the
8300 fb = mode_fits_in_fbdev(dev, mode);
8302 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8303 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8304 old->release_fb = fb;
8306 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8308 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8312 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8313 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8314 if (old->release_fb)
8315 old->release_fb->funcs->destroy(old->release_fb);
8319 /* let the connector get through one full cycle before testing */
8320 intel_wait_for_vblank(dev, intel_crtc->pipe);
8324 intel_crtc->new_enabled = crtc->enabled;
8325 if (intel_crtc->new_enabled)
8326 intel_crtc->new_config = &intel_crtc->config;
8328 intel_crtc->new_config = NULL;
8329 mutex_unlock(&crtc->mutex);
8333 void intel_release_load_detect_pipe(struct drm_connector *connector,
8334 struct intel_load_detect_pipe *old)
8336 struct intel_encoder *intel_encoder =
8337 intel_attached_encoder(connector);
8338 struct drm_encoder *encoder = &intel_encoder->base;
8339 struct drm_crtc *crtc = encoder->crtc;
8340 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8342 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8343 connector->base.id, drm_get_connector_name(connector),
8344 encoder->base.id, drm_get_encoder_name(encoder));
8346 if (old->load_detect_temp) {
8347 to_intel_connector(connector)->new_encoder = NULL;
8348 intel_encoder->new_crtc = NULL;
8349 intel_crtc->new_enabled = false;
8350 intel_crtc->new_config = NULL;
8351 intel_set_mode(crtc, NULL, 0, 0, NULL);
8353 if (old->release_fb) {
8354 drm_framebuffer_unregister_private(old->release_fb);
8355 drm_framebuffer_unreference(old->release_fb);
8358 mutex_unlock(&crtc->mutex);
8362 /* Switch crtc and encoder back off if necessary */
8363 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8364 connector->funcs->dpms(connector, old->dpms_mode);
8366 mutex_unlock(&crtc->mutex);
8369 static int i9xx_pll_refclk(struct drm_device *dev,
8370 const struct intel_crtc_config *pipe_config)
8372 struct drm_i915_private *dev_priv = dev->dev_private;
8373 u32 dpll = pipe_config->dpll_hw_state.dpll;
8375 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8376 return dev_priv->vbt.lvds_ssc_freq;
8377 else if (HAS_PCH_SPLIT(dev))
8379 else if (!IS_GEN2(dev))
8385 /* Returns the clock of the currently programmed mode of the given pipe. */
8386 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8387 struct intel_crtc_config *pipe_config)
8389 struct drm_device *dev = crtc->base.dev;
8390 struct drm_i915_private *dev_priv = dev->dev_private;
8391 int pipe = pipe_config->cpu_transcoder;
8392 u32 dpll = pipe_config->dpll_hw_state.dpll;
8394 intel_clock_t clock;
8395 int refclk = i9xx_pll_refclk(dev, pipe_config);
8397 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8398 fp = pipe_config->dpll_hw_state.fp0;
8400 fp = pipe_config->dpll_hw_state.fp1;
8402 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8403 if (IS_PINEVIEW(dev)) {
8404 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8405 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8407 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8408 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8411 if (!IS_GEN2(dev)) {
8412 if (IS_PINEVIEW(dev))
8413 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8414 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8416 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8417 DPLL_FPA01_P1_POST_DIV_SHIFT);
8419 switch (dpll & DPLL_MODE_MASK) {
8420 case DPLLB_MODE_DAC_SERIAL:
8421 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8424 case DPLLB_MODE_LVDS:
8425 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8429 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8430 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8434 if (IS_PINEVIEW(dev))
8435 pineview_clock(refclk, &clock);
8437 i9xx_clock(refclk, &clock);
8439 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8440 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8443 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8444 DPLL_FPA01_P1_POST_DIV_SHIFT);
8446 if (lvds & LVDS_CLKB_POWER_UP)
8451 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8454 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8455 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8457 if (dpll & PLL_P2_DIVIDE_BY_4)
8463 i9xx_clock(refclk, &clock);
8467 * This value includes pixel_multiplier. We will use
8468 * port_clock to compute adjusted_mode.crtc_clock in the
8469 * encoder's get_config() function.
8471 pipe_config->port_clock = clock.dot;
8474 int intel_dotclock_calculate(int link_freq,
8475 const struct intel_link_m_n *m_n)
8478 * The calculation for the data clock is:
8479 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8480 * But we want to avoid losing precison if possible, so:
8481 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8483 * and the link clock is simpler:
8484 * link_clock = (m * link_clock) / n
8490 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8493 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8494 struct intel_crtc_config *pipe_config)
8496 struct drm_device *dev = crtc->base.dev;
8498 /* read out port_clock from the DPLL */
8499 i9xx_crtc_clock_get(crtc, pipe_config);
8502 * This value does not include pixel_multiplier.
8503 * We will check that port_clock and adjusted_mode.crtc_clock
8504 * agree once we know their relationship in the encoder's
8505 * get_config() function.
8507 pipe_config->adjusted_mode.crtc_clock =
8508 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8509 &pipe_config->fdi_m_n);
8512 /** Returns the currently programmed mode of the given pipe. */
8513 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8514 struct drm_crtc *crtc)
8516 struct drm_i915_private *dev_priv = dev->dev_private;
8517 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8518 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8519 struct drm_display_mode *mode;
8520 struct intel_crtc_config pipe_config;
8521 int htot = I915_READ(HTOTAL(cpu_transcoder));
8522 int hsync = I915_READ(HSYNC(cpu_transcoder));
8523 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8524 int vsync = I915_READ(VSYNC(cpu_transcoder));
8525 enum pipe pipe = intel_crtc->pipe;
8527 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8532 * Construct a pipe_config sufficient for getting the clock info
8533 * back out of crtc_clock_get.
8535 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8536 * to use a real value here instead.
8538 pipe_config.cpu_transcoder = (enum transcoder) pipe;
8539 pipe_config.pixel_multiplier = 1;
8540 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8541 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8542 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8543 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8545 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8546 mode->hdisplay = (htot & 0xffff) + 1;
8547 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8548 mode->hsync_start = (hsync & 0xffff) + 1;
8549 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8550 mode->vdisplay = (vtot & 0xffff) + 1;
8551 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8552 mode->vsync_start = (vsync & 0xffff) + 1;
8553 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8555 drm_mode_set_name(mode);
8560 static void intel_increase_pllclock(struct drm_crtc *crtc)
8562 struct drm_device *dev = crtc->dev;
8563 struct drm_i915_private *dev_priv = dev->dev_private;
8564 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8565 int pipe = intel_crtc->pipe;
8566 int dpll_reg = DPLL(pipe);
8569 if (HAS_PCH_SPLIT(dev))
8572 if (!dev_priv->lvds_downclock_avail)
8575 dpll = I915_READ(dpll_reg);
8576 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8577 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8579 assert_panel_unlocked(dev_priv, pipe);
8581 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8582 I915_WRITE(dpll_reg, dpll);
8583 intel_wait_for_vblank(dev, pipe);
8585 dpll = I915_READ(dpll_reg);
8586 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8587 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8591 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8593 struct drm_device *dev = crtc->dev;
8594 struct drm_i915_private *dev_priv = dev->dev_private;
8595 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8597 if (HAS_PCH_SPLIT(dev))
8600 if (!dev_priv->lvds_downclock_avail)
8604 * Since this is called by a timer, we should never get here in
8607 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8608 int pipe = intel_crtc->pipe;
8609 int dpll_reg = DPLL(pipe);
8612 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8614 assert_panel_unlocked(dev_priv, pipe);
8616 dpll = I915_READ(dpll_reg);
8617 dpll |= DISPLAY_RATE_SELECT_FPA1;
8618 I915_WRITE(dpll_reg, dpll);
8619 intel_wait_for_vblank(dev, pipe);
8620 dpll = I915_READ(dpll_reg);
8621 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8622 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8627 void intel_mark_busy(struct drm_device *dev)
8629 struct drm_i915_private *dev_priv = dev->dev_private;
8631 if (dev_priv->mm.busy)
8634 intel_runtime_pm_get(dev_priv);
8635 i915_update_gfx_val(dev_priv);
8636 dev_priv->mm.busy = true;
8639 void intel_mark_idle(struct drm_device *dev)
8641 struct drm_i915_private *dev_priv = dev->dev_private;
8642 struct drm_crtc *crtc;
8644 if (!dev_priv->mm.busy)
8647 dev_priv->mm.busy = false;
8649 if (!i915.powersave)
8652 for_each_crtc(dev, crtc) {
8653 if (!crtc->primary->fb)
8656 intel_decrease_pllclock(crtc);
8659 if (INTEL_INFO(dev)->gen >= 6)
8660 gen6_rps_idle(dev->dev_private);
8663 intel_runtime_pm_put(dev_priv);
8666 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
8667 struct intel_ring_buffer *ring)
8669 struct drm_device *dev = obj->base.dev;
8670 struct drm_crtc *crtc;
8672 if (!i915.powersave)
8675 for_each_crtc(dev, crtc) {
8676 if (!crtc->primary->fb)
8679 if (to_intel_framebuffer(crtc->primary->fb)->obj != obj)
8682 intel_increase_pllclock(crtc);
8683 if (ring && intel_fbc_enabled(dev))
8684 ring->fbc_dirty = true;
8688 static void intel_crtc_destroy(struct drm_crtc *crtc)
8690 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8691 struct drm_device *dev = crtc->dev;
8692 struct intel_unpin_work *work;
8693 unsigned long flags;
8695 spin_lock_irqsave(&dev->event_lock, flags);
8696 work = intel_crtc->unpin_work;
8697 intel_crtc->unpin_work = NULL;
8698 spin_unlock_irqrestore(&dev->event_lock, flags);
8701 cancel_work_sync(&work->work);
8705 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
8707 drm_crtc_cleanup(crtc);
8712 static void intel_unpin_work_fn(struct work_struct *__work)
8714 struct intel_unpin_work *work =
8715 container_of(__work, struct intel_unpin_work, work);
8716 struct drm_device *dev = work->crtc->dev;
8718 mutex_lock(&dev->struct_mutex);
8719 intel_unpin_fb_obj(work->old_fb_obj);
8720 drm_gem_object_unreference(&work->pending_flip_obj->base);
8721 drm_gem_object_unreference(&work->old_fb_obj->base);
8723 intel_update_fbc(dev);
8724 mutex_unlock(&dev->struct_mutex);
8726 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8727 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8732 static void do_intel_finish_page_flip(struct drm_device *dev,
8733 struct drm_crtc *crtc)
8735 struct drm_i915_private *dev_priv = dev->dev_private;
8736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8737 struct intel_unpin_work *work;
8738 unsigned long flags;
8740 /* Ignore early vblank irqs */
8741 if (intel_crtc == NULL)
8744 spin_lock_irqsave(&dev->event_lock, flags);
8745 work = intel_crtc->unpin_work;
8747 /* Ensure we don't miss a work->pending update ... */
8750 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8751 spin_unlock_irqrestore(&dev->event_lock, flags);
8755 /* and that the unpin work is consistent wrt ->pending. */
8758 intel_crtc->unpin_work = NULL;
8761 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
8763 drm_vblank_put(dev, intel_crtc->pipe);
8765 spin_unlock_irqrestore(&dev->event_lock, flags);
8767 wake_up_all(&dev_priv->pending_flip_queue);
8769 queue_work(dev_priv->wq, &work->work);
8771 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
8774 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8776 struct drm_i915_private *dev_priv = dev->dev_private;
8777 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8779 do_intel_finish_page_flip(dev, crtc);
8782 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8784 struct drm_i915_private *dev_priv = dev->dev_private;
8785 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8787 do_intel_finish_page_flip(dev, crtc);
8790 void intel_prepare_page_flip(struct drm_device *dev, int plane)
8792 struct drm_i915_private *dev_priv = dev->dev_private;
8793 struct intel_crtc *intel_crtc =
8794 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8795 unsigned long flags;
8797 /* NB: An MMIO update of the plane base pointer will also
8798 * generate a page-flip completion irq, i.e. every modeset
8799 * is also accompanied by a spurious intel_prepare_page_flip().
8801 spin_lock_irqsave(&dev->event_lock, flags);
8802 if (intel_crtc->unpin_work)
8803 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
8804 spin_unlock_irqrestore(&dev->event_lock, flags);
8807 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8809 /* Ensure that the work item is consistent when activating it ... */
8811 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8812 /* and that it is marked active as soon as the irq could fire. */
8816 static int intel_gen2_queue_flip(struct drm_device *dev,
8817 struct drm_crtc *crtc,
8818 struct drm_framebuffer *fb,
8819 struct drm_i915_gem_object *obj,
8822 struct drm_i915_private *dev_priv = dev->dev_private;
8823 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8825 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8828 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8832 ret = intel_ring_begin(ring, 6);
8836 /* Can't queue multiple flips, so wait for the previous
8837 * one to finish before executing the next.
8839 if (intel_crtc->plane)
8840 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8842 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8843 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8844 intel_ring_emit(ring, MI_NOOP);
8845 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8846 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8847 intel_ring_emit(ring, fb->pitches[0]);
8848 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8849 intel_ring_emit(ring, 0); /* aux display base address, unused */
8851 intel_mark_page_flip_active(intel_crtc);
8852 __intel_ring_advance(ring);
8856 intel_unpin_fb_obj(obj);
8861 static int intel_gen3_queue_flip(struct drm_device *dev,
8862 struct drm_crtc *crtc,
8863 struct drm_framebuffer *fb,
8864 struct drm_i915_gem_object *obj,
8867 struct drm_i915_private *dev_priv = dev->dev_private;
8868 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8870 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8873 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8877 ret = intel_ring_begin(ring, 6);
8881 if (intel_crtc->plane)
8882 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8884 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8885 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8886 intel_ring_emit(ring, MI_NOOP);
8887 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8888 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8889 intel_ring_emit(ring, fb->pitches[0]);
8890 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8891 intel_ring_emit(ring, MI_NOOP);
8893 intel_mark_page_flip_active(intel_crtc);
8894 __intel_ring_advance(ring);
8898 intel_unpin_fb_obj(obj);
8903 static int intel_gen4_queue_flip(struct drm_device *dev,
8904 struct drm_crtc *crtc,
8905 struct drm_framebuffer *fb,
8906 struct drm_i915_gem_object *obj,
8909 struct drm_i915_private *dev_priv = dev->dev_private;
8910 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8911 uint32_t pf, pipesrc;
8912 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8915 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8919 ret = intel_ring_begin(ring, 4);
8923 /* i965+ uses the linear or tiled offsets from the
8924 * Display Registers (which do not change across a page-flip)
8925 * so we need only reprogram the base address.
8927 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8928 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8929 intel_ring_emit(ring, fb->pitches[0]);
8930 intel_ring_emit(ring,
8931 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
8934 /* XXX Enabling the panel-fitter across page-flip is so far
8935 * untested on non-native modes, so ignore it for now.
8936 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8939 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8940 intel_ring_emit(ring, pf | pipesrc);
8942 intel_mark_page_flip_active(intel_crtc);
8943 __intel_ring_advance(ring);
8947 intel_unpin_fb_obj(obj);
8952 static int intel_gen6_queue_flip(struct drm_device *dev,
8953 struct drm_crtc *crtc,
8954 struct drm_framebuffer *fb,
8955 struct drm_i915_gem_object *obj,
8958 struct drm_i915_private *dev_priv = dev->dev_private;
8959 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8960 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8961 uint32_t pf, pipesrc;
8964 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8968 ret = intel_ring_begin(ring, 4);
8972 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8973 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8974 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
8975 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8977 /* Contrary to the suggestions in the documentation,
8978 * "Enable Panel Fitter" does not seem to be required when page
8979 * flipping with a non-native mode, and worse causes a normal
8981 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8984 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8985 intel_ring_emit(ring, pf | pipesrc);
8987 intel_mark_page_flip_active(intel_crtc);
8988 __intel_ring_advance(ring);
8992 intel_unpin_fb_obj(obj);
8997 static int intel_gen7_queue_flip(struct drm_device *dev,
8998 struct drm_crtc *crtc,
8999 struct drm_framebuffer *fb,
9000 struct drm_i915_gem_object *obj,
9003 struct drm_i915_private *dev_priv = dev->dev_private;
9004 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9005 struct intel_ring_buffer *ring;
9006 uint32_t plane_bit = 0;
9010 if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
9011 ring = &dev_priv->ring[BCS];
9013 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9017 switch (intel_crtc->plane) {
9019 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9022 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9025 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9028 WARN_ONCE(1, "unknown plane in flip command\n");
9034 if (ring->id == RCS) {
9037 * On Gen 8, SRM is now taking an extra dword to accommodate
9038 * 48bits addresses, and we need a NOOP for the batch size to
9046 * BSpec MI_DISPLAY_FLIP for IVB:
9047 * "The full packet must be contained within the same cache line."
9049 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9050 * cacheline, if we ever start emitting more commands before
9051 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9052 * then do the cacheline alignment, and finally emit the
9055 ret = intel_ring_cacheline_align(ring);
9059 ret = intel_ring_begin(ring, len);
9063 /* Unmask the flip-done completion message. Note that the bspec says that
9064 * we should do this for both the BCS and RCS, and that we must not unmask
9065 * more than one flip event at any time (or ensure that one flip message
9066 * can be sent by waiting for flip-done prior to queueing new flips).
9067 * Experimentation says that BCS works despite DERRMR masking all
9068 * flip-done completion events and that unmasking all planes at once
9069 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9070 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9072 if (ring->id == RCS) {
9073 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9074 intel_ring_emit(ring, DERRMR);
9075 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9076 DERRMR_PIPEB_PRI_FLIP_DONE |
9077 DERRMR_PIPEC_PRI_FLIP_DONE));
9079 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9080 MI_SRM_LRM_GLOBAL_GTT);
9082 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9083 MI_SRM_LRM_GLOBAL_GTT);
9084 intel_ring_emit(ring, DERRMR);
9085 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9087 intel_ring_emit(ring, 0);
9088 intel_ring_emit(ring, MI_NOOP);
9092 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9093 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9094 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
9095 intel_ring_emit(ring, (MI_NOOP));
9097 intel_mark_page_flip_active(intel_crtc);
9098 __intel_ring_advance(ring);
9102 intel_unpin_fb_obj(obj);
9107 static int intel_default_queue_flip(struct drm_device *dev,
9108 struct drm_crtc *crtc,
9109 struct drm_framebuffer *fb,
9110 struct drm_i915_gem_object *obj,
9116 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9117 struct drm_framebuffer *fb,
9118 struct drm_pending_vblank_event *event,
9119 uint32_t page_flip_flags)
9121 struct drm_device *dev = crtc->dev;
9122 struct drm_i915_private *dev_priv = dev->dev_private;
9123 struct drm_framebuffer *old_fb = crtc->primary->fb;
9124 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
9125 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9126 struct intel_unpin_work *work;
9127 unsigned long flags;
9130 /* Can't change pixel format via MI display flips. */
9131 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9135 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9136 * Note that pitch changes could also affect these register.
9138 if (INTEL_INFO(dev)->gen > 3 &&
9139 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9140 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9143 if (i915_terminally_wedged(&dev_priv->gpu_error))
9146 work = kzalloc(sizeof(*work), GFP_KERNEL);
9150 work->event = event;
9152 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
9153 INIT_WORK(&work->work, intel_unpin_work_fn);
9155 ret = drm_vblank_get(dev, intel_crtc->pipe);
9159 /* We borrow the event spin lock for protecting unpin_work */
9160 spin_lock_irqsave(&dev->event_lock, flags);
9161 if (intel_crtc->unpin_work) {
9162 spin_unlock_irqrestore(&dev->event_lock, flags);
9164 drm_vblank_put(dev, intel_crtc->pipe);
9166 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9169 intel_crtc->unpin_work = work;
9170 spin_unlock_irqrestore(&dev->event_lock, flags);
9172 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9173 flush_workqueue(dev_priv->wq);
9175 ret = i915_mutex_lock_interruptible(dev);
9179 /* Reference the objects for the scheduled work. */
9180 drm_gem_object_reference(&work->old_fb_obj->base);
9181 drm_gem_object_reference(&obj->base);
9183 crtc->primary->fb = fb;
9185 work->pending_flip_obj = obj;
9187 work->enable_stall_check = true;
9189 atomic_inc(&intel_crtc->unpin_work_count);
9190 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9192 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
9194 goto cleanup_pending;
9196 intel_disable_fbc(dev);
9197 intel_mark_fb_busy(obj, NULL);
9198 mutex_unlock(&dev->struct_mutex);
9200 trace_i915_flip_request(intel_crtc->plane, obj);
9205 atomic_dec(&intel_crtc->unpin_work_count);
9206 crtc->primary->fb = old_fb;
9207 drm_gem_object_unreference(&work->old_fb_obj->base);
9208 drm_gem_object_unreference(&obj->base);
9209 mutex_unlock(&dev->struct_mutex);
9212 spin_lock_irqsave(&dev->event_lock, flags);
9213 intel_crtc->unpin_work = NULL;
9214 spin_unlock_irqrestore(&dev->event_lock, flags);
9216 drm_vblank_put(dev, intel_crtc->pipe);
9222 intel_crtc_wait_for_pending_flips(crtc);
9223 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9224 if (ret == 0 && event)
9225 drm_send_vblank_event(dev, intel_crtc->pipe, event);
9230 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9231 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9232 .load_lut = intel_crtc_load_lut,
9236 * intel_modeset_update_staged_output_state
9238 * Updates the staged output configuration state, e.g. after we've read out the
9241 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9243 struct intel_crtc *crtc;
9244 struct intel_encoder *encoder;
9245 struct intel_connector *connector;
9247 list_for_each_entry(connector, &dev->mode_config.connector_list,
9249 connector->new_encoder =
9250 to_intel_encoder(connector->base.encoder);
9253 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9256 to_intel_crtc(encoder->base.crtc);
9259 for_each_intel_crtc(dev, crtc) {
9260 crtc->new_enabled = crtc->base.enabled;
9262 if (crtc->new_enabled)
9263 crtc->new_config = &crtc->config;
9265 crtc->new_config = NULL;
9270 * intel_modeset_commit_output_state
9272 * This function copies the stage display pipe configuration to the real one.
9274 static void intel_modeset_commit_output_state(struct drm_device *dev)
9276 struct intel_crtc *crtc;
9277 struct intel_encoder *encoder;
9278 struct intel_connector *connector;
9280 list_for_each_entry(connector, &dev->mode_config.connector_list,
9282 connector->base.encoder = &connector->new_encoder->base;
9285 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9287 encoder->base.crtc = &encoder->new_crtc->base;
9290 for_each_intel_crtc(dev, crtc) {
9291 crtc->base.enabled = crtc->new_enabled;
9296 connected_sink_compute_bpp(struct intel_connector *connector,
9297 struct intel_crtc_config *pipe_config)
9299 int bpp = pipe_config->pipe_bpp;
9301 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9302 connector->base.base.id,
9303 drm_get_connector_name(&connector->base));
9305 /* Don't use an invalid EDID bpc value */
9306 if (connector->base.display_info.bpc &&
9307 connector->base.display_info.bpc * 3 < bpp) {
9308 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9309 bpp, connector->base.display_info.bpc*3);
9310 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9313 /* Clamp bpp to 8 on screens without EDID 1.4 */
9314 if (connector->base.display_info.bpc == 0 && bpp > 24) {
9315 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9317 pipe_config->pipe_bpp = 24;
9322 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9323 struct drm_framebuffer *fb,
9324 struct intel_crtc_config *pipe_config)
9326 struct drm_device *dev = crtc->base.dev;
9327 struct intel_connector *connector;
9330 switch (fb->pixel_format) {
9332 bpp = 8*3; /* since we go through a colormap */
9334 case DRM_FORMAT_XRGB1555:
9335 case DRM_FORMAT_ARGB1555:
9336 /* checked in intel_framebuffer_init already */
9337 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9339 case DRM_FORMAT_RGB565:
9340 bpp = 6*3; /* min is 18bpp */
9342 case DRM_FORMAT_XBGR8888:
9343 case DRM_FORMAT_ABGR8888:
9344 /* checked in intel_framebuffer_init already */
9345 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9347 case DRM_FORMAT_XRGB8888:
9348 case DRM_FORMAT_ARGB8888:
9351 case DRM_FORMAT_XRGB2101010:
9352 case DRM_FORMAT_ARGB2101010:
9353 case DRM_FORMAT_XBGR2101010:
9354 case DRM_FORMAT_ABGR2101010:
9355 /* checked in intel_framebuffer_init already */
9356 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9360 /* TODO: gen4+ supports 16 bpc floating point, too. */
9362 DRM_DEBUG_KMS("unsupported depth\n");
9366 pipe_config->pipe_bpp = bpp;
9368 /* Clamp display bpp to EDID value */
9369 list_for_each_entry(connector, &dev->mode_config.connector_list,
9371 if (!connector->new_encoder ||
9372 connector->new_encoder->new_crtc != crtc)
9375 connected_sink_compute_bpp(connector, pipe_config);
9381 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9383 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9384 "type: 0x%x flags: 0x%x\n",
9386 mode->crtc_hdisplay, mode->crtc_hsync_start,
9387 mode->crtc_hsync_end, mode->crtc_htotal,
9388 mode->crtc_vdisplay, mode->crtc_vsync_start,
9389 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9392 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9393 struct intel_crtc_config *pipe_config,
9394 const char *context)
9396 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9397 context, pipe_name(crtc->pipe));
9399 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9400 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9401 pipe_config->pipe_bpp, pipe_config->dither);
9402 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9403 pipe_config->has_pch_encoder,
9404 pipe_config->fdi_lanes,
9405 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9406 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9407 pipe_config->fdi_m_n.tu);
9408 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9409 pipe_config->has_dp_encoder,
9410 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9411 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9412 pipe_config->dp_m_n.tu);
9413 DRM_DEBUG_KMS("requested mode:\n");
9414 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9415 DRM_DEBUG_KMS("adjusted mode:\n");
9416 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9417 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9418 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9419 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9420 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9421 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9422 pipe_config->gmch_pfit.control,
9423 pipe_config->gmch_pfit.pgm_ratios,
9424 pipe_config->gmch_pfit.lvds_border_bits);
9425 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9426 pipe_config->pch_pfit.pos,
9427 pipe_config->pch_pfit.size,
9428 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9429 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9430 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
9433 static bool encoders_cloneable(const struct intel_encoder *a,
9434 const struct intel_encoder *b)
9436 /* masks could be asymmetric, so check both ways */
9437 return a == b || (a->cloneable & (1 << b->type) &&
9438 b->cloneable & (1 << a->type));
9441 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9442 struct intel_encoder *encoder)
9444 struct drm_device *dev = crtc->base.dev;
9445 struct intel_encoder *source_encoder;
9447 list_for_each_entry(source_encoder,
9448 &dev->mode_config.encoder_list, base.head) {
9449 if (source_encoder->new_crtc != crtc)
9452 if (!encoders_cloneable(encoder, source_encoder))
9459 static bool check_encoder_cloning(struct intel_crtc *crtc)
9461 struct drm_device *dev = crtc->base.dev;
9462 struct intel_encoder *encoder;
9464 list_for_each_entry(encoder,
9465 &dev->mode_config.encoder_list, base.head) {
9466 if (encoder->new_crtc != crtc)
9469 if (!check_single_encoder_cloning(crtc, encoder))
9476 static struct intel_crtc_config *
9477 intel_modeset_pipe_config(struct drm_crtc *crtc,
9478 struct drm_framebuffer *fb,
9479 struct drm_display_mode *mode)
9481 struct drm_device *dev = crtc->dev;
9482 struct intel_encoder *encoder;
9483 struct intel_crtc_config *pipe_config;
9484 int plane_bpp, ret = -EINVAL;
9487 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
9488 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
9489 return ERR_PTR(-EINVAL);
9492 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9494 return ERR_PTR(-ENOMEM);
9496 drm_mode_copy(&pipe_config->adjusted_mode, mode);
9497 drm_mode_copy(&pipe_config->requested_mode, mode);
9499 pipe_config->cpu_transcoder =
9500 (enum transcoder) to_intel_crtc(crtc)->pipe;
9501 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9504 * Sanitize sync polarity flags based on requested ones. If neither
9505 * positive or negative polarity is requested, treat this as meaning
9506 * negative polarity.
9508 if (!(pipe_config->adjusted_mode.flags &
9509 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
9510 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
9512 if (!(pipe_config->adjusted_mode.flags &
9513 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
9514 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
9516 /* Compute a starting value for pipe_config->pipe_bpp taking the source
9517 * plane pixel format and any sink constraints into account. Returns the
9518 * source plane bpp so that dithering can be selected on mismatches
9519 * after encoders and crtc also have had their say. */
9520 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
9526 * Determine the real pipe dimensions. Note that stereo modes can
9527 * increase the actual pipe size due to the frame doubling and
9528 * insertion of additional space for blanks between the frame. This
9529 * is stored in the crtc timings. We use the requested mode to do this
9530 * computation to clearly distinguish it from the adjusted mode, which
9531 * can be changed by the connectors in the below retry loop.
9533 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
9534 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
9535 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
9538 /* Ensure the port clock defaults are reset when retrying. */
9539 pipe_config->port_clock = 0;
9540 pipe_config->pixel_multiplier = 1;
9542 /* Fill in default crtc timings, allow encoders to overwrite them. */
9543 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
9545 /* Pass our mode to the connectors and the CRTC to give them a chance to
9546 * adjust it according to limitations or connector properties, and also
9547 * a chance to reject the mode entirely.
9549 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9552 if (&encoder->new_crtc->base != crtc)
9555 if (!(encoder->compute_config(encoder, pipe_config))) {
9556 DRM_DEBUG_KMS("Encoder config failure\n");
9561 /* Set default port clock if not overwritten by the encoder. Needs to be
9562 * done afterwards in case the encoder adjusts the mode. */
9563 if (!pipe_config->port_clock)
9564 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
9565 * pipe_config->pixel_multiplier;
9567 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
9569 DRM_DEBUG_KMS("CRTC fixup failed\n");
9574 if (WARN(!retry, "loop in pipe configuration computation\n")) {
9579 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9584 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
9585 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9586 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
9591 return ERR_PTR(ret);
9594 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
9595 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9597 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
9598 unsigned *prepare_pipes, unsigned *disable_pipes)
9600 struct intel_crtc *intel_crtc;
9601 struct drm_device *dev = crtc->dev;
9602 struct intel_encoder *encoder;
9603 struct intel_connector *connector;
9604 struct drm_crtc *tmp_crtc;
9606 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
9608 /* Check which crtcs have changed outputs connected to them, these need
9609 * to be part of the prepare_pipes mask. We don't (yet) support global
9610 * modeset across multiple crtcs, so modeset_pipes will only have one
9611 * bit set at most. */
9612 list_for_each_entry(connector, &dev->mode_config.connector_list,
9614 if (connector->base.encoder == &connector->new_encoder->base)
9617 if (connector->base.encoder) {
9618 tmp_crtc = connector->base.encoder->crtc;
9620 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9623 if (connector->new_encoder)
9625 1 << connector->new_encoder->new_crtc->pipe;
9628 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9630 if (encoder->base.crtc == &encoder->new_crtc->base)
9633 if (encoder->base.crtc) {
9634 tmp_crtc = encoder->base.crtc;
9636 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9639 if (encoder->new_crtc)
9640 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
9643 /* Check for pipes that will be enabled/disabled ... */
9644 for_each_intel_crtc(dev, intel_crtc) {
9645 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
9648 if (!intel_crtc->new_enabled)
9649 *disable_pipes |= 1 << intel_crtc->pipe;
9651 *prepare_pipes |= 1 << intel_crtc->pipe;
9655 /* set_mode is also used to update properties on life display pipes. */
9656 intel_crtc = to_intel_crtc(crtc);
9657 if (intel_crtc->new_enabled)
9658 *prepare_pipes |= 1 << intel_crtc->pipe;
9661 * For simplicity do a full modeset on any pipe where the output routing
9662 * changed. We could be more clever, but that would require us to be
9663 * more careful with calling the relevant encoder->mode_set functions.
9666 *modeset_pipes = *prepare_pipes;
9668 /* ... and mask these out. */
9669 *modeset_pipes &= ~(*disable_pipes);
9670 *prepare_pipes &= ~(*disable_pipes);
9673 * HACK: We don't (yet) fully support global modesets. intel_set_config
9674 * obies this rule, but the modeset restore mode of
9675 * intel_modeset_setup_hw_state does not.
9677 *modeset_pipes &= 1 << intel_crtc->pipe;
9678 *prepare_pipes &= 1 << intel_crtc->pipe;
9680 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9681 *modeset_pipes, *prepare_pipes, *disable_pipes);
9684 static bool intel_crtc_in_use(struct drm_crtc *crtc)
9686 struct drm_encoder *encoder;
9687 struct drm_device *dev = crtc->dev;
9689 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
9690 if (encoder->crtc == crtc)
9697 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
9699 struct intel_encoder *intel_encoder;
9700 struct intel_crtc *intel_crtc;
9701 struct drm_connector *connector;
9703 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
9705 if (!intel_encoder->base.crtc)
9708 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
9710 if (prepare_pipes & (1 << intel_crtc->pipe))
9711 intel_encoder->connectors_active = false;
9714 intel_modeset_commit_output_state(dev);
9716 /* Double check state. */
9717 for_each_intel_crtc(dev, intel_crtc) {
9718 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
9719 WARN_ON(intel_crtc->new_config &&
9720 intel_crtc->new_config != &intel_crtc->config);
9721 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
9724 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9725 if (!connector->encoder || !connector->encoder->crtc)
9728 intel_crtc = to_intel_crtc(connector->encoder->crtc);
9730 if (prepare_pipes & (1 << intel_crtc->pipe)) {
9731 struct drm_property *dpms_property =
9732 dev->mode_config.dpms_property;
9734 connector->dpms = DRM_MODE_DPMS_ON;
9735 drm_object_property_set_value(&connector->base,
9739 intel_encoder = to_intel_encoder(connector->encoder);
9740 intel_encoder->connectors_active = true;
9746 static bool intel_fuzzy_clock_check(int clock1, int clock2)
9750 if (clock1 == clock2)
9753 if (!clock1 || !clock2)
9756 diff = abs(clock1 - clock2);
9758 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
9764 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9765 list_for_each_entry((intel_crtc), \
9766 &(dev)->mode_config.crtc_list, \
9768 if (mask & (1 <<(intel_crtc)->pipe))
9771 intel_pipe_config_compare(struct drm_device *dev,
9772 struct intel_crtc_config *current_config,
9773 struct intel_crtc_config *pipe_config)
9775 #define PIPE_CONF_CHECK_X(name) \
9776 if (current_config->name != pipe_config->name) { \
9777 DRM_ERROR("mismatch in " #name " " \
9778 "(expected 0x%08x, found 0x%08x)\n", \
9779 current_config->name, \
9780 pipe_config->name); \
9784 #define PIPE_CONF_CHECK_I(name) \
9785 if (current_config->name != pipe_config->name) { \
9786 DRM_ERROR("mismatch in " #name " " \
9787 "(expected %i, found %i)\n", \
9788 current_config->name, \
9789 pipe_config->name); \
9793 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
9794 if ((current_config->name ^ pipe_config->name) & (mask)) { \
9795 DRM_ERROR("mismatch in " #name "(" #mask ") " \
9796 "(expected %i, found %i)\n", \
9797 current_config->name & (mask), \
9798 pipe_config->name & (mask)); \
9802 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9803 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9804 DRM_ERROR("mismatch in " #name " " \
9805 "(expected %i, found %i)\n", \
9806 current_config->name, \
9807 pipe_config->name); \
9811 #define PIPE_CONF_QUIRK(quirk) \
9812 ((current_config->quirks | pipe_config->quirks) & (quirk))
9814 PIPE_CONF_CHECK_I(cpu_transcoder);
9816 PIPE_CONF_CHECK_I(has_pch_encoder);
9817 PIPE_CONF_CHECK_I(fdi_lanes);
9818 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9819 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9820 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9821 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9822 PIPE_CONF_CHECK_I(fdi_m_n.tu);
9824 PIPE_CONF_CHECK_I(has_dp_encoder);
9825 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9826 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9827 PIPE_CONF_CHECK_I(dp_m_n.link_m);
9828 PIPE_CONF_CHECK_I(dp_m_n.link_n);
9829 PIPE_CONF_CHECK_I(dp_m_n.tu);
9831 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9832 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9833 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9834 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9835 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9836 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9838 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9839 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9840 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9841 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9842 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9843 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9845 PIPE_CONF_CHECK_I(pixel_multiplier);
9846 PIPE_CONF_CHECK_I(has_hdmi_sink);
9847 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
9849 PIPE_CONF_CHECK_I(limited_color_range);
9851 PIPE_CONF_CHECK_I(has_audio);
9853 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9854 DRM_MODE_FLAG_INTERLACE);
9856 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9857 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9858 DRM_MODE_FLAG_PHSYNC);
9859 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9860 DRM_MODE_FLAG_NHSYNC);
9861 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9862 DRM_MODE_FLAG_PVSYNC);
9863 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9864 DRM_MODE_FLAG_NVSYNC);
9867 PIPE_CONF_CHECK_I(pipe_src_w);
9868 PIPE_CONF_CHECK_I(pipe_src_h);
9871 * FIXME: BIOS likes to set up a cloned config with lvds+external
9872 * screen. Since we don't yet re-compute the pipe config when moving
9873 * just the lvds port away to another pipe the sw tracking won't match.
9875 * Proper atomic modesets with recomputed global state will fix this.
9876 * Until then just don't check gmch state for inherited modes.
9878 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
9879 PIPE_CONF_CHECK_I(gmch_pfit.control);
9880 /* pfit ratios are autocomputed by the hw on gen4+ */
9881 if (INTEL_INFO(dev)->gen < 4)
9882 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9883 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9886 PIPE_CONF_CHECK_I(pch_pfit.enabled);
9887 if (current_config->pch_pfit.enabled) {
9888 PIPE_CONF_CHECK_I(pch_pfit.pos);
9889 PIPE_CONF_CHECK_I(pch_pfit.size);
9892 /* BDW+ don't expose a synchronous way to read the state */
9893 if (IS_HASWELL(dev))
9894 PIPE_CONF_CHECK_I(ips_enabled);
9896 PIPE_CONF_CHECK_I(double_wide);
9898 PIPE_CONF_CHECK_I(shared_dpll);
9899 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
9900 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
9901 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
9902 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
9904 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
9905 PIPE_CONF_CHECK_I(pipe_bpp);
9907 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
9908 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
9910 #undef PIPE_CONF_CHECK_X
9911 #undef PIPE_CONF_CHECK_I
9912 #undef PIPE_CONF_CHECK_FLAGS
9913 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
9914 #undef PIPE_CONF_QUIRK
9920 check_connector_state(struct drm_device *dev)
9922 struct intel_connector *connector;
9924 list_for_each_entry(connector, &dev->mode_config.connector_list,
9926 /* This also checks the encoder/connector hw state with the
9927 * ->get_hw_state callbacks. */
9928 intel_connector_check_state(connector);
9930 WARN(&connector->new_encoder->base != connector->base.encoder,
9931 "connector's staged encoder doesn't match current encoder\n");
9936 check_encoder_state(struct drm_device *dev)
9938 struct intel_encoder *encoder;
9939 struct intel_connector *connector;
9941 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9943 bool enabled = false;
9944 bool active = false;
9945 enum pipe pipe, tracked_pipe;
9947 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
9948 encoder->base.base.id,
9949 drm_get_encoder_name(&encoder->base));
9951 WARN(&encoder->new_crtc->base != encoder->base.crtc,
9952 "encoder's stage crtc doesn't match current crtc\n");
9953 WARN(encoder->connectors_active && !encoder->base.crtc,
9954 "encoder's active_connectors set, but no crtc\n");
9956 list_for_each_entry(connector, &dev->mode_config.connector_list,
9958 if (connector->base.encoder != &encoder->base)
9961 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
9964 WARN(!!encoder->base.crtc != enabled,
9965 "encoder's enabled state mismatch "
9966 "(expected %i, found %i)\n",
9967 !!encoder->base.crtc, enabled);
9968 WARN(active && !encoder->base.crtc,
9969 "active encoder with no crtc\n");
9971 WARN(encoder->connectors_active != active,
9972 "encoder's computed active state doesn't match tracked active state "
9973 "(expected %i, found %i)\n", active, encoder->connectors_active);
9975 active = encoder->get_hw_state(encoder, &pipe);
9976 WARN(active != encoder->connectors_active,
9977 "encoder's hw state doesn't match sw tracking "
9978 "(expected %i, found %i)\n",
9979 encoder->connectors_active, active);
9981 if (!encoder->base.crtc)
9984 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9985 WARN(active && pipe != tracked_pipe,
9986 "active encoder's pipe doesn't match"
9987 "(expected %i, found %i)\n",
9988 tracked_pipe, pipe);
9994 check_crtc_state(struct drm_device *dev)
9996 struct drm_i915_private *dev_priv = dev->dev_private;
9997 struct intel_crtc *crtc;
9998 struct intel_encoder *encoder;
9999 struct intel_crtc_config pipe_config;
10001 for_each_intel_crtc(dev, crtc) {
10002 bool enabled = false;
10003 bool active = false;
10005 memset(&pipe_config, 0, sizeof(pipe_config));
10007 DRM_DEBUG_KMS("[CRTC:%d]\n",
10008 crtc->base.base.id);
10010 WARN(crtc->active && !crtc->base.enabled,
10011 "active crtc, but not enabled in sw tracking\n");
10013 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10015 if (encoder->base.crtc != &crtc->base)
10018 if (encoder->connectors_active)
10022 WARN(active != crtc->active,
10023 "crtc's computed active state doesn't match tracked active state "
10024 "(expected %i, found %i)\n", active, crtc->active);
10025 WARN(enabled != crtc->base.enabled,
10026 "crtc's computed enabled state doesn't match tracked enabled state "
10027 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10029 active = dev_priv->display.get_pipe_config(crtc,
10032 /* hw state is inconsistent with the pipe A quirk */
10033 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
10034 active = crtc->active;
10036 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10039 if (encoder->base.crtc != &crtc->base)
10041 if (encoder->get_hw_state(encoder, &pipe))
10042 encoder->get_config(encoder, &pipe_config);
10045 WARN(crtc->active != active,
10046 "crtc active state doesn't match with hw state "
10047 "(expected %i, found %i)\n", crtc->active, active);
10050 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10051 WARN(1, "pipe state doesn't match!\n");
10052 intel_dump_pipe_config(crtc, &pipe_config,
10054 intel_dump_pipe_config(crtc, &crtc->config,
10061 check_shared_dpll_state(struct drm_device *dev)
10063 struct drm_i915_private *dev_priv = dev->dev_private;
10064 struct intel_crtc *crtc;
10065 struct intel_dpll_hw_state dpll_hw_state;
10068 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10069 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10070 int enabled_crtcs = 0, active_crtcs = 0;
10073 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10075 DRM_DEBUG_KMS("%s\n", pll->name);
10077 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10079 WARN(pll->active > pll->refcount,
10080 "more active pll users than references: %i vs %i\n",
10081 pll->active, pll->refcount);
10082 WARN(pll->active && !pll->on,
10083 "pll in active use but not on in sw tracking\n");
10084 WARN(pll->on && !pll->active,
10085 "pll in on but not on in use in sw tracking\n");
10086 WARN(pll->on != active,
10087 "pll on state mismatch (expected %i, found %i)\n",
10090 for_each_intel_crtc(dev, crtc) {
10091 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10093 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10096 WARN(pll->active != active_crtcs,
10097 "pll active crtcs mismatch (expected %i, found %i)\n",
10098 pll->active, active_crtcs);
10099 WARN(pll->refcount != enabled_crtcs,
10100 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10101 pll->refcount, enabled_crtcs);
10103 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10104 sizeof(dpll_hw_state)),
10105 "pll hw state mismatch\n");
10110 intel_modeset_check_state(struct drm_device *dev)
10112 check_connector_state(dev);
10113 check_encoder_state(dev);
10114 check_crtc_state(dev);
10115 check_shared_dpll_state(dev);
10118 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10122 * FDI already provided one idea for the dotclock.
10123 * Yell if the encoder disagrees.
10125 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10126 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10127 pipe_config->adjusted_mode.crtc_clock, dotclock);
10130 static int __intel_set_mode(struct drm_crtc *crtc,
10131 struct drm_display_mode *mode,
10132 int x, int y, struct drm_framebuffer *fb)
10134 struct drm_device *dev = crtc->dev;
10135 struct drm_i915_private *dev_priv = dev->dev_private;
10136 struct drm_display_mode *saved_mode;
10137 struct intel_crtc_config *pipe_config = NULL;
10138 struct intel_crtc *intel_crtc;
10139 unsigned disable_pipes, prepare_pipes, modeset_pipes;
10142 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10146 intel_modeset_affected_pipes(crtc, &modeset_pipes,
10147 &prepare_pipes, &disable_pipes);
10149 *saved_mode = crtc->mode;
10151 /* Hack: Because we don't (yet) support global modeset on multiple
10152 * crtcs, we don't keep track of the new mode for more than one crtc.
10153 * Hence simply check whether any bit is set in modeset_pipes in all the
10154 * pieces of code that are not yet converted to deal with mutliple crtcs
10155 * changing their mode at the same time. */
10156 if (modeset_pipes) {
10157 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10158 if (IS_ERR(pipe_config)) {
10159 ret = PTR_ERR(pipe_config);
10160 pipe_config = NULL;
10164 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10166 to_intel_crtc(crtc)->new_config = pipe_config;
10170 * See if the config requires any additional preparation, e.g.
10171 * to adjust global state with pipes off. We need to do this
10172 * here so we can get the modeset_pipe updated config for the new
10173 * mode set on this crtc. For other crtcs we need to use the
10174 * adjusted_mode bits in the crtc directly.
10176 if (IS_VALLEYVIEW(dev)) {
10177 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10179 /* may have added more to prepare_pipes than we should */
10180 prepare_pipes &= ~disable_pipes;
10183 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10184 intel_crtc_disable(&intel_crtc->base);
10186 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10187 if (intel_crtc->base.enabled)
10188 dev_priv->display.crtc_disable(&intel_crtc->base);
10191 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10192 * to set it here already despite that we pass it down the callchain.
10194 if (modeset_pipes) {
10195 crtc->mode = *mode;
10196 /* mode_set/enable/disable functions rely on a correct pipe
10198 to_intel_crtc(crtc)->config = *pipe_config;
10199 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10202 * Calculate and store various constants which
10203 * are later needed by vblank and swap-completion
10204 * timestamping. They are derived from true hwmode.
10206 drm_calc_timestamping_constants(crtc,
10207 &pipe_config->adjusted_mode);
10210 /* Only after disabling all output pipelines that will be changed can we
10211 * update the the output configuration. */
10212 intel_modeset_update_state(dev, prepare_pipes);
10214 if (dev_priv->display.modeset_global_resources)
10215 dev_priv->display.modeset_global_resources(dev);
10217 /* Set up the DPLL and any encoders state that needs to adjust or depend
10220 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10221 struct drm_framebuffer *old_fb;
10223 mutex_lock(&dev->struct_mutex);
10224 ret = intel_pin_and_fence_fb_obj(dev,
10225 to_intel_framebuffer(fb)->obj,
10228 DRM_ERROR("pin & fence failed\n");
10229 mutex_unlock(&dev->struct_mutex);
10232 old_fb = crtc->primary->fb;
10234 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
10235 mutex_unlock(&dev->struct_mutex);
10237 crtc->primary->fb = fb;
10241 ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
10247 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10248 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
10249 dev_priv->display.crtc_enable(&intel_crtc->base);
10251 /* FIXME: add subpixel order */
10253 if (ret && crtc->enabled)
10254 crtc->mode = *saved_mode;
10257 kfree(pipe_config);
10262 static int intel_set_mode(struct drm_crtc *crtc,
10263 struct drm_display_mode *mode,
10264 int x, int y, struct drm_framebuffer *fb)
10268 ret = __intel_set_mode(crtc, mode, x, y, fb);
10271 intel_modeset_check_state(crtc->dev);
10276 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10278 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10281 #undef for_each_intel_crtc_masked
10283 static void intel_set_config_free(struct intel_set_config *config)
10288 kfree(config->save_connector_encoders);
10289 kfree(config->save_encoder_crtcs);
10290 kfree(config->save_crtc_enabled);
10294 static int intel_set_config_save_state(struct drm_device *dev,
10295 struct intel_set_config *config)
10297 struct drm_crtc *crtc;
10298 struct drm_encoder *encoder;
10299 struct drm_connector *connector;
10302 config->save_crtc_enabled =
10303 kcalloc(dev->mode_config.num_crtc,
10304 sizeof(bool), GFP_KERNEL);
10305 if (!config->save_crtc_enabled)
10308 config->save_encoder_crtcs =
10309 kcalloc(dev->mode_config.num_encoder,
10310 sizeof(struct drm_crtc *), GFP_KERNEL);
10311 if (!config->save_encoder_crtcs)
10314 config->save_connector_encoders =
10315 kcalloc(dev->mode_config.num_connector,
10316 sizeof(struct drm_encoder *), GFP_KERNEL);
10317 if (!config->save_connector_encoders)
10320 /* Copy data. Note that driver private data is not affected.
10321 * Should anything bad happen only the expected state is
10322 * restored, not the drivers personal bookkeeping.
10325 for_each_crtc(dev, crtc) {
10326 config->save_crtc_enabled[count++] = crtc->enabled;
10330 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10331 config->save_encoder_crtcs[count++] = encoder->crtc;
10335 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10336 config->save_connector_encoders[count++] = connector->encoder;
10342 static void intel_set_config_restore_state(struct drm_device *dev,
10343 struct intel_set_config *config)
10345 struct intel_crtc *crtc;
10346 struct intel_encoder *encoder;
10347 struct intel_connector *connector;
10351 for_each_intel_crtc(dev, crtc) {
10352 crtc->new_enabled = config->save_crtc_enabled[count++];
10354 if (crtc->new_enabled)
10355 crtc->new_config = &crtc->config;
10357 crtc->new_config = NULL;
10361 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10362 encoder->new_crtc =
10363 to_intel_crtc(config->save_encoder_crtcs[count++]);
10367 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10368 connector->new_encoder =
10369 to_intel_encoder(config->save_connector_encoders[count++]);
10374 is_crtc_connector_off(struct drm_mode_set *set)
10378 if (set->num_connectors == 0)
10381 if (WARN_ON(set->connectors == NULL))
10384 for (i = 0; i < set->num_connectors; i++)
10385 if (set->connectors[i]->encoder &&
10386 set->connectors[i]->encoder->crtc == set->crtc &&
10387 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
10394 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
10395 struct intel_set_config *config)
10398 /* We should be able to check here if the fb has the same properties
10399 * and then just flip_or_move it */
10400 if (is_crtc_connector_off(set)) {
10401 config->mode_changed = true;
10402 } else if (set->crtc->primary->fb != set->fb) {
10403 /* If we have no fb then treat it as a full mode set */
10404 if (set->crtc->primary->fb == NULL) {
10405 struct intel_crtc *intel_crtc =
10406 to_intel_crtc(set->crtc);
10408 if (intel_crtc->active && i915.fastboot) {
10409 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
10410 config->fb_changed = true;
10412 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
10413 config->mode_changed = true;
10415 } else if (set->fb == NULL) {
10416 config->mode_changed = true;
10417 } else if (set->fb->pixel_format !=
10418 set->crtc->primary->fb->pixel_format) {
10419 config->mode_changed = true;
10421 config->fb_changed = true;
10425 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
10426 config->fb_changed = true;
10428 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
10429 DRM_DEBUG_KMS("modes are different, full mode set\n");
10430 drm_mode_debug_printmodeline(&set->crtc->mode);
10431 drm_mode_debug_printmodeline(set->mode);
10432 config->mode_changed = true;
10435 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
10436 set->crtc->base.id, config->mode_changed, config->fb_changed);
10440 intel_modeset_stage_output_state(struct drm_device *dev,
10441 struct drm_mode_set *set,
10442 struct intel_set_config *config)
10444 struct intel_connector *connector;
10445 struct intel_encoder *encoder;
10446 struct intel_crtc *crtc;
10449 /* The upper layers ensure that we either disable a crtc or have a list
10450 * of connectors. For paranoia, double-check this. */
10451 WARN_ON(!set->fb && (set->num_connectors != 0));
10452 WARN_ON(set->fb && (set->num_connectors == 0));
10454 list_for_each_entry(connector, &dev->mode_config.connector_list,
10456 /* Otherwise traverse passed in connector list and get encoders
10458 for (ro = 0; ro < set->num_connectors; ro++) {
10459 if (set->connectors[ro] == &connector->base) {
10460 connector->new_encoder = connector->encoder;
10465 /* If we disable the crtc, disable all its connectors. Also, if
10466 * the connector is on the changing crtc but not on the new
10467 * connector list, disable it. */
10468 if ((!set->fb || ro == set->num_connectors) &&
10469 connector->base.encoder &&
10470 connector->base.encoder->crtc == set->crtc) {
10471 connector->new_encoder = NULL;
10473 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
10474 connector->base.base.id,
10475 drm_get_connector_name(&connector->base));
10479 if (&connector->new_encoder->base != connector->base.encoder) {
10480 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
10481 config->mode_changed = true;
10484 /* connector->new_encoder is now updated for all connectors. */
10486 /* Update crtc of enabled connectors. */
10487 list_for_each_entry(connector, &dev->mode_config.connector_list,
10489 struct drm_crtc *new_crtc;
10491 if (!connector->new_encoder)
10494 new_crtc = connector->new_encoder->base.crtc;
10496 for (ro = 0; ro < set->num_connectors; ro++) {
10497 if (set->connectors[ro] == &connector->base)
10498 new_crtc = set->crtc;
10501 /* Make sure the new CRTC will work with the encoder */
10502 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
10506 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
10508 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
10509 connector->base.base.id,
10510 drm_get_connector_name(&connector->base),
10511 new_crtc->base.id);
10514 /* Check for any encoders that needs to be disabled. */
10515 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10517 int num_connectors = 0;
10518 list_for_each_entry(connector,
10519 &dev->mode_config.connector_list,
10521 if (connector->new_encoder == encoder) {
10522 WARN_ON(!connector->new_encoder->new_crtc);
10527 if (num_connectors == 0)
10528 encoder->new_crtc = NULL;
10529 else if (num_connectors > 1)
10532 /* Only now check for crtc changes so we don't miss encoders
10533 * that will be disabled. */
10534 if (&encoder->new_crtc->base != encoder->base.crtc) {
10535 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
10536 config->mode_changed = true;
10539 /* Now we've also updated encoder->new_crtc for all encoders. */
10541 for_each_intel_crtc(dev, crtc) {
10542 crtc->new_enabled = false;
10544 list_for_each_entry(encoder,
10545 &dev->mode_config.encoder_list,
10547 if (encoder->new_crtc == crtc) {
10548 crtc->new_enabled = true;
10553 if (crtc->new_enabled != crtc->base.enabled) {
10554 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
10555 crtc->new_enabled ? "en" : "dis");
10556 config->mode_changed = true;
10559 if (crtc->new_enabled)
10560 crtc->new_config = &crtc->config;
10562 crtc->new_config = NULL;
10568 static void disable_crtc_nofb(struct intel_crtc *crtc)
10570 struct drm_device *dev = crtc->base.dev;
10571 struct intel_encoder *encoder;
10572 struct intel_connector *connector;
10574 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
10575 pipe_name(crtc->pipe));
10577 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10578 if (connector->new_encoder &&
10579 connector->new_encoder->new_crtc == crtc)
10580 connector->new_encoder = NULL;
10583 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10584 if (encoder->new_crtc == crtc)
10585 encoder->new_crtc = NULL;
10588 crtc->new_enabled = false;
10589 crtc->new_config = NULL;
10592 static int intel_crtc_set_config(struct drm_mode_set *set)
10594 struct drm_device *dev;
10595 struct drm_mode_set save_set;
10596 struct intel_set_config *config;
10600 BUG_ON(!set->crtc);
10601 BUG_ON(!set->crtc->helper_private);
10603 /* Enforce sane interface api - has been abused by the fb helper. */
10604 BUG_ON(!set->mode && set->fb);
10605 BUG_ON(set->fb && set->num_connectors == 0);
10608 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
10609 set->crtc->base.id, set->fb->base.id,
10610 (int)set->num_connectors, set->x, set->y);
10612 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
10615 dev = set->crtc->dev;
10618 config = kzalloc(sizeof(*config), GFP_KERNEL);
10622 ret = intel_set_config_save_state(dev, config);
10626 save_set.crtc = set->crtc;
10627 save_set.mode = &set->crtc->mode;
10628 save_set.x = set->crtc->x;
10629 save_set.y = set->crtc->y;
10630 save_set.fb = set->crtc->primary->fb;
10632 /* Compute whether we need a full modeset, only an fb base update or no
10633 * change at all. In the future we might also check whether only the
10634 * mode changed, e.g. for LVDS where we only change the panel fitter in
10636 intel_set_config_compute_mode_changes(set, config);
10638 ret = intel_modeset_stage_output_state(dev, set, config);
10642 if (config->mode_changed) {
10643 ret = intel_set_mode(set->crtc, set->mode,
10644 set->x, set->y, set->fb);
10645 } else if (config->fb_changed) {
10646 intel_crtc_wait_for_pending_flips(set->crtc);
10648 ret = intel_pipe_set_base(set->crtc,
10649 set->x, set->y, set->fb);
10651 * In the fastboot case this may be our only check of the
10652 * state after boot. It would be better to only do it on
10653 * the first update, but we don't have a nice way of doing that
10654 * (and really, set_config isn't used much for high freq page
10655 * flipping, so increasing its cost here shouldn't be a big
10658 if (i915.fastboot && ret == 0)
10659 intel_modeset_check_state(set->crtc->dev);
10663 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
10664 set->crtc->base.id, ret);
10666 intel_set_config_restore_state(dev, config);
10669 * HACK: if the pipe was on, but we didn't have a framebuffer,
10670 * force the pipe off to avoid oopsing in the modeset code
10671 * due to fb==NULL. This should only happen during boot since
10672 * we don't yet reconstruct the FB from the hardware state.
10674 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
10675 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
10677 /* Try to restore the config */
10678 if (config->mode_changed &&
10679 intel_set_mode(save_set.crtc, save_set.mode,
10680 save_set.x, save_set.y, save_set.fb))
10681 DRM_ERROR("failed to restore config after modeset failure\n");
10685 intel_set_config_free(config);
10689 static const struct drm_crtc_funcs intel_crtc_funcs = {
10690 .cursor_set = intel_crtc_cursor_set,
10691 .cursor_move = intel_crtc_cursor_move,
10692 .gamma_set = intel_crtc_gamma_set,
10693 .set_config = intel_crtc_set_config,
10694 .destroy = intel_crtc_destroy,
10695 .page_flip = intel_crtc_page_flip,
10698 static void intel_cpu_pll_init(struct drm_device *dev)
10701 intel_ddi_pll_init(dev);
10704 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
10705 struct intel_shared_dpll *pll,
10706 struct intel_dpll_hw_state *hw_state)
10710 val = I915_READ(PCH_DPLL(pll->id));
10711 hw_state->dpll = val;
10712 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
10713 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
10715 return val & DPLL_VCO_ENABLE;
10718 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
10719 struct intel_shared_dpll *pll)
10721 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
10722 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
10725 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
10726 struct intel_shared_dpll *pll)
10728 /* PCH refclock must be enabled first */
10729 ibx_assert_pch_refclk_enabled(dev_priv);
10731 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10733 /* Wait for the clocks to stabilize. */
10734 POSTING_READ(PCH_DPLL(pll->id));
10737 /* The pixel multiplier can only be updated once the
10738 * DPLL is enabled and the clocks are stable.
10740 * So write it again.
10742 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10743 POSTING_READ(PCH_DPLL(pll->id));
10747 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
10748 struct intel_shared_dpll *pll)
10750 struct drm_device *dev = dev_priv->dev;
10751 struct intel_crtc *crtc;
10753 /* Make sure no transcoder isn't still depending on us. */
10754 for_each_intel_crtc(dev, crtc) {
10755 if (intel_crtc_to_shared_dpll(crtc) == pll)
10756 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
10759 I915_WRITE(PCH_DPLL(pll->id), 0);
10760 POSTING_READ(PCH_DPLL(pll->id));
10764 static char *ibx_pch_dpll_names[] = {
10769 static void ibx_pch_dpll_init(struct drm_device *dev)
10771 struct drm_i915_private *dev_priv = dev->dev_private;
10774 dev_priv->num_shared_dpll = 2;
10776 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10777 dev_priv->shared_dplls[i].id = i;
10778 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
10779 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
10780 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
10781 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
10782 dev_priv->shared_dplls[i].get_hw_state =
10783 ibx_pch_dpll_get_hw_state;
10787 static void intel_shared_dpll_init(struct drm_device *dev)
10789 struct drm_i915_private *dev_priv = dev->dev_private;
10791 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
10792 ibx_pch_dpll_init(dev);
10794 dev_priv->num_shared_dpll = 0;
10796 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
10799 static void intel_crtc_init(struct drm_device *dev, int pipe)
10801 struct drm_i915_private *dev_priv = dev->dev_private;
10802 struct intel_crtc *intel_crtc;
10805 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
10806 if (intel_crtc == NULL)
10809 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
10811 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
10812 for (i = 0; i < 256; i++) {
10813 intel_crtc->lut_r[i] = i;
10814 intel_crtc->lut_g[i] = i;
10815 intel_crtc->lut_b[i] = i;
10819 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
10820 * is hooked to plane B. Hence we want plane A feeding pipe B.
10822 intel_crtc->pipe = pipe;
10823 intel_crtc->plane = pipe;
10824 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
10825 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
10826 intel_crtc->plane = !pipe;
10829 init_waitqueue_head(&intel_crtc->vbl_wait);
10831 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
10832 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
10833 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
10834 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
10836 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
10839 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
10841 struct drm_encoder *encoder = connector->base.encoder;
10843 WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex));
10846 return INVALID_PIPE;
10848 return to_intel_crtc(encoder->crtc)->pipe;
10851 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
10852 struct drm_file *file)
10854 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
10855 struct drm_mode_object *drmmode_obj;
10856 struct intel_crtc *crtc;
10858 if (!drm_core_check_feature(dev, DRIVER_MODESET))
10861 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
10862 DRM_MODE_OBJECT_CRTC);
10864 if (!drmmode_obj) {
10865 DRM_ERROR("no such CRTC id\n");
10869 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
10870 pipe_from_crtc_id->pipe = crtc->pipe;
10875 static int intel_encoder_clones(struct intel_encoder *encoder)
10877 struct drm_device *dev = encoder->base.dev;
10878 struct intel_encoder *source_encoder;
10879 int index_mask = 0;
10882 list_for_each_entry(source_encoder,
10883 &dev->mode_config.encoder_list, base.head) {
10884 if (encoders_cloneable(encoder, source_encoder))
10885 index_mask |= (1 << entry);
10893 static bool has_edp_a(struct drm_device *dev)
10895 struct drm_i915_private *dev_priv = dev->dev_private;
10897 if (!IS_MOBILE(dev))
10900 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
10903 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
10909 const char *intel_output_name(int output)
10911 static const char *names[] = {
10912 [INTEL_OUTPUT_UNUSED] = "Unused",
10913 [INTEL_OUTPUT_ANALOG] = "Analog",
10914 [INTEL_OUTPUT_DVO] = "DVO",
10915 [INTEL_OUTPUT_SDVO] = "SDVO",
10916 [INTEL_OUTPUT_LVDS] = "LVDS",
10917 [INTEL_OUTPUT_TVOUT] = "TV",
10918 [INTEL_OUTPUT_HDMI] = "HDMI",
10919 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
10920 [INTEL_OUTPUT_EDP] = "eDP",
10921 [INTEL_OUTPUT_DSI] = "DSI",
10922 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
10925 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
10928 return names[output];
10931 static void intel_setup_outputs(struct drm_device *dev)
10933 struct drm_i915_private *dev_priv = dev->dev_private;
10934 struct intel_encoder *encoder;
10935 bool dpd_is_edp = false;
10937 intel_lvds_init(dev);
10939 if (!IS_ULT(dev) && !IS_CHERRYVIEW(dev))
10940 intel_crt_init(dev);
10942 if (HAS_DDI(dev)) {
10945 /* Haswell uses DDI functions to detect digital outputs */
10946 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
10947 /* DDI A only supports eDP */
10949 intel_ddi_init(dev, PORT_A);
10951 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
10953 found = I915_READ(SFUSE_STRAP);
10955 if (found & SFUSE_STRAP_DDIB_DETECTED)
10956 intel_ddi_init(dev, PORT_B);
10957 if (found & SFUSE_STRAP_DDIC_DETECTED)
10958 intel_ddi_init(dev, PORT_C);
10959 if (found & SFUSE_STRAP_DDID_DETECTED)
10960 intel_ddi_init(dev, PORT_D);
10961 } else if (HAS_PCH_SPLIT(dev)) {
10963 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
10965 if (has_edp_a(dev))
10966 intel_dp_init(dev, DP_A, PORT_A);
10968 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
10969 /* PCH SDVOB multiplex with HDMIB */
10970 found = intel_sdvo_init(dev, PCH_SDVOB, true);
10972 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
10973 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
10974 intel_dp_init(dev, PCH_DP_B, PORT_B);
10977 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
10978 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
10980 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
10981 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
10983 if (I915_READ(PCH_DP_C) & DP_DETECTED)
10984 intel_dp_init(dev, PCH_DP_C, PORT_C);
10986 if (I915_READ(PCH_DP_D) & DP_DETECTED)
10987 intel_dp_init(dev, PCH_DP_D, PORT_D);
10988 } else if (IS_VALLEYVIEW(dev)) {
10989 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
10990 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
10992 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
10993 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
10996 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
10997 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
10999 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
11000 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
11003 intel_dsi_init(dev);
11004 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
11005 bool found = false;
11007 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
11008 DRM_DEBUG_KMS("probing SDVOB\n");
11009 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
11010 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
11011 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
11012 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
11015 if (!found && SUPPORTS_INTEGRATED_DP(dev))
11016 intel_dp_init(dev, DP_B, PORT_B);
11019 /* Before G4X SDVOC doesn't have its own detect register */
11021 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
11022 DRM_DEBUG_KMS("probing SDVOC\n");
11023 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
11026 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
11028 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
11029 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
11030 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
11032 if (SUPPORTS_INTEGRATED_DP(dev))
11033 intel_dp_init(dev, DP_C, PORT_C);
11036 if (SUPPORTS_INTEGRATED_DP(dev) &&
11037 (I915_READ(DP_D) & DP_DETECTED))
11038 intel_dp_init(dev, DP_D, PORT_D);
11039 } else if (IS_GEN2(dev))
11040 intel_dvo_init(dev);
11042 if (SUPPORTS_TV(dev))
11043 intel_tv_init(dev);
11045 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
11046 encoder->base.possible_crtcs = encoder->crtc_mask;
11047 encoder->base.possible_clones =
11048 intel_encoder_clones(encoder);
11051 intel_init_pch_refclk(dev);
11053 drm_helper_move_panel_connectors_to_head(dev);
11056 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
11058 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11060 drm_framebuffer_cleanup(fb);
11061 WARN_ON(!intel_fb->obj->framebuffer_references--);
11062 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
11066 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
11067 struct drm_file *file,
11068 unsigned int *handle)
11070 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11071 struct drm_i915_gem_object *obj = intel_fb->obj;
11073 return drm_gem_handle_create(file, &obj->base, handle);
11076 static const struct drm_framebuffer_funcs intel_fb_funcs = {
11077 .destroy = intel_user_framebuffer_destroy,
11078 .create_handle = intel_user_framebuffer_create_handle,
11081 static int intel_framebuffer_init(struct drm_device *dev,
11082 struct intel_framebuffer *intel_fb,
11083 struct drm_mode_fb_cmd2 *mode_cmd,
11084 struct drm_i915_gem_object *obj)
11086 int aligned_height;
11090 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
11092 if (obj->tiling_mode == I915_TILING_Y) {
11093 DRM_DEBUG("hardware does not support tiling Y\n");
11097 if (mode_cmd->pitches[0] & 63) {
11098 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
11099 mode_cmd->pitches[0]);
11103 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
11104 pitch_limit = 32*1024;
11105 } else if (INTEL_INFO(dev)->gen >= 4) {
11106 if (obj->tiling_mode)
11107 pitch_limit = 16*1024;
11109 pitch_limit = 32*1024;
11110 } else if (INTEL_INFO(dev)->gen >= 3) {
11111 if (obj->tiling_mode)
11112 pitch_limit = 8*1024;
11114 pitch_limit = 16*1024;
11116 /* XXX DSPC is limited to 4k tiled */
11117 pitch_limit = 8*1024;
11119 if (mode_cmd->pitches[0] > pitch_limit) {
11120 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
11121 obj->tiling_mode ? "tiled" : "linear",
11122 mode_cmd->pitches[0], pitch_limit);
11126 if (obj->tiling_mode != I915_TILING_NONE &&
11127 mode_cmd->pitches[0] != obj->stride) {
11128 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
11129 mode_cmd->pitches[0], obj->stride);
11133 /* Reject formats not supported by any plane early. */
11134 switch (mode_cmd->pixel_format) {
11135 case DRM_FORMAT_C8:
11136 case DRM_FORMAT_RGB565:
11137 case DRM_FORMAT_XRGB8888:
11138 case DRM_FORMAT_ARGB8888:
11140 case DRM_FORMAT_XRGB1555:
11141 case DRM_FORMAT_ARGB1555:
11142 if (INTEL_INFO(dev)->gen > 3) {
11143 DRM_DEBUG("unsupported pixel format: %s\n",
11144 drm_get_format_name(mode_cmd->pixel_format));
11148 case DRM_FORMAT_XBGR8888:
11149 case DRM_FORMAT_ABGR8888:
11150 case DRM_FORMAT_XRGB2101010:
11151 case DRM_FORMAT_ARGB2101010:
11152 case DRM_FORMAT_XBGR2101010:
11153 case DRM_FORMAT_ABGR2101010:
11154 if (INTEL_INFO(dev)->gen < 4) {
11155 DRM_DEBUG("unsupported pixel format: %s\n",
11156 drm_get_format_name(mode_cmd->pixel_format));
11160 case DRM_FORMAT_YUYV:
11161 case DRM_FORMAT_UYVY:
11162 case DRM_FORMAT_YVYU:
11163 case DRM_FORMAT_VYUY:
11164 if (INTEL_INFO(dev)->gen < 5) {
11165 DRM_DEBUG("unsupported pixel format: %s\n",
11166 drm_get_format_name(mode_cmd->pixel_format));
11171 DRM_DEBUG("unsupported pixel format: %s\n",
11172 drm_get_format_name(mode_cmd->pixel_format));
11176 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
11177 if (mode_cmd->offsets[0] != 0)
11180 aligned_height = intel_align_height(dev, mode_cmd->height,
11182 /* FIXME drm helper for size checks (especially planar formats)? */
11183 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
11186 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
11187 intel_fb->obj = obj;
11188 intel_fb->obj->framebuffer_references++;
11190 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
11192 DRM_ERROR("framebuffer init failed %d\n", ret);
11199 static struct drm_framebuffer *
11200 intel_user_framebuffer_create(struct drm_device *dev,
11201 struct drm_file *filp,
11202 struct drm_mode_fb_cmd2 *mode_cmd)
11204 struct drm_i915_gem_object *obj;
11206 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
11207 mode_cmd->handles[0]));
11208 if (&obj->base == NULL)
11209 return ERR_PTR(-ENOENT);
11211 return intel_framebuffer_create(dev, mode_cmd, obj);
11214 #ifndef CONFIG_DRM_I915_FBDEV
11215 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
11220 static const struct drm_mode_config_funcs intel_mode_funcs = {
11221 .fb_create = intel_user_framebuffer_create,
11222 .output_poll_changed = intel_fbdev_output_poll_changed,
11225 /* Set up chip specific display functions */
11226 static void intel_init_display(struct drm_device *dev)
11228 struct drm_i915_private *dev_priv = dev->dev_private;
11230 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
11231 dev_priv->display.find_dpll = g4x_find_best_dpll;
11232 else if (IS_CHERRYVIEW(dev))
11233 dev_priv->display.find_dpll = chv_find_best_dpll;
11234 else if (IS_VALLEYVIEW(dev))
11235 dev_priv->display.find_dpll = vlv_find_best_dpll;
11236 else if (IS_PINEVIEW(dev))
11237 dev_priv->display.find_dpll = pnv_find_best_dpll;
11239 dev_priv->display.find_dpll = i9xx_find_best_dpll;
11241 if (HAS_DDI(dev)) {
11242 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
11243 dev_priv->display.get_plane_config = ironlake_get_plane_config;
11244 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
11245 dev_priv->display.crtc_enable = haswell_crtc_enable;
11246 dev_priv->display.crtc_disable = haswell_crtc_disable;
11247 dev_priv->display.off = haswell_crtc_off;
11248 dev_priv->display.update_primary_plane =
11249 ironlake_update_primary_plane;
11250 } else if (HAS_PCH_SPLIT(dev)) {
11251 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
11252 dev_priv->display.get_plane_config = ironlake_get_plane_config;
11253 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
11254 dev_priv->display.crtc_enable = ironlake_crtc_enable;
11255 dev_priv->display.crtc_disable = ironlake_crtc_disable;
11256 dev_priv->display.off = ironlake_crtc_off;
11257 dev_priv->display.update_primary_plane =
11258 ironlake_update_primary_plane;
11259 } else if (IS_VALLEYVIEW(dev)) {
11260 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11261 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11262 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11263 dev_priv->display.crtc_enable = valleyview_crtc_enable;
11264 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11265 dev_priv->display.off = i9xx_crtc_off;
11266 dev_priv->display.update_primary_plane =
11267 i9xx_update_primary_plane;
11269 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11270 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11271 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11272 dev_priv->display.crtc_enable = i9xx_crtc_enable;
11273 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11274 dev_priv->display.off = i9xx_crtc_off;
11275 dev_priv->display.update_primary_plane =
11276 i9xx_update_primary_plane;
11279 /* Returns the core display clock speed */
11280 if (IS_VALLEYVIEW(dev))
11281 dev_priv->display.get_display_clock_speed =
11282 valleyview_get_display_clock_speed;
11283 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
11284 dev_priv->display.get_display_clock_speed =
11285 i945_get_display_clock_speed;
11286 else if (IS_I915G(dev))
11287 dev_priv->display.get_display_clock_speed =
11288 i915_get_display_clock_speed;
11289 else if (IS_I945GM(dev) || IS_845G(dev))
11290 dev_priv->display.get_display_clock_speed =
11291 i9xx_misc_get_display_clock_speed;
11292 else if (IS_PINEVIEW(dev))
11293 dev_priv->display.get_display_clock_speed =
11294 pnv_get_display_clock_speed;
11295 else if (IS_I915GM(dev))
11296 dev_priv->display.get_display_clock_speed =
11297 i915gm_get_display_clock_speed;
11298 else if (IS_I865G(dev))
11299 dev_priv->display.get_display_clock_speed =
11300 i865_get_display_clock_speed;
11301 else if (IS_I85X(dev))
11302 dev_priv->display.get_display_clock_speed =
11303 i855_get_display_clock_speed;
11304 else /* 852, 830 */
11305 dev_priv->display.get_display_clock_speed =
11306 i830_get_display_clock_speed;
11308 if (HAS_PCH_SPLIT(dev)) {
11309 if (IS_GEN5(dev)) {
11310 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
11311 dev_priv->display.write_eld = ironlake_write_eld;
11312 } else if (IS_GEN6(dev)) {
11313 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
11314 dev_priv->display.write_eld = ironlake_write_eld;
11315 dev_priv->display.modeset_global_resources =
11316 snb_modeset_global_resources;
11317 } else if (IS_IVYBRIDGE(dev)) {
11318 /* FIXME: detect B0+ stepping and use auto training */
11319 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
11320 dev_priv->display.write_eld = ironlake_write_eld;
11321 dev_priv->display.modeset_global_resources =
11322 ivb_modeset_global_resources;
11323 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
11324 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
11325 dev_priv->display.write_eld = haswell_write_eld;
11326 dev_priv->display.modeset_global_resources =
11327 haswell_modeset_global_resources;
11329 } else if (IS_G4X(dev)) {
11330 dev_priv->display.write_eld = g4x_write_eld;
11331 } else if (IS_VALLEYVIEW(dev)) {
11332 dev_priv->display.modeset_global_resources =
11333 valleyview_modeset_global_resources;
11334 dev_priv->display.write_eld = ironlake_write_eld;
11337 /* Default just returns -ENODEV to indicate unsupported */
11338 dev_priv->display.queue_flip = intel_default_queue_flip;
11340 switch (INTEL_INFO(dev)->gen) {
11342 dev_priv->display.queue_flip = intel_gen2_queue_flip;
11346 dev_priv->display.queue_flip = intel_gen3_queue_flip;
11351 dev_priv->display.queue_flip = intel_gen4_queue_flip;
11355 dev_priv->display.queue_flip = intel_gen6_queue_flip;
11358 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
11359 dev_priv->display.queue_flip = intel_gen7_queue_flip;
11363 intel_panel_init_backlight_funcs(dev);
11367 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
11368 * resume, or other times. This quirk makes sure that's the case for
11369 * affected systems.
11371 static void quirk_pipea_force(struct drm_device *dev)
11373 struct drm_i915_private *dev_priv = dev->dev_private;
11375 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
11376 DRM_INFO("applying pipe a force quirk\n");
11380 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
11382 static void quirk_ssc_force_disable(struct drm_device *dev)
11384 struct drm_i915_private *dev_priv = dev->dev_private;
11385 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
11386 DRM_INFO("applying lvds SSC disable quirk\n");
11390 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
11393 static void quirk_invert_brightness(struct drm_device *dev)
11395 struct drm_i915_private *dev_priv = dev->dev_private;
11396 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
11397 DRM_INFO("applying inverted panel brightness quirk\n");
11400 struct intel_quirk {
11402 int subsystem_vendor;
11403 int subsystem_device;
11404 void (*hook)(struct drm_device *dev);
11407 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
11408 struct intel_dmi_quirk {
11409 void (*hook)(struct drm_device *dev);
11410 const struct dmi_system_id (*dmi_id_list)[];
11413 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
11415 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
11419 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
11421 .dmi_id_list = &(const struct dmi_system_id[]) {
11423 .callback = intel_dmi_reverse_brightness,
11424 .ident = "NCR Corporation",
11425 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
11426 DMI_MATCH(DMI_PRODUCT_NAME, ""),
11429 { } /* terminating entry */
11431 .hook = quirk_invert_brightness,
11435 static struct intel_quirk intel_quirks[] = {
11436 /* HP Mini needs pipe A force quirk (LP: #322104) */
11437 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
11439 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
11440 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
11442 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
11443 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
11445 /* 830 needs to leave pipe A & dpll A up */
11446 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
11448 /* Lenovo U160 cannot use SSC on LVDS */
11449 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
11451 /* Sony Vaio Y cannot use SSC on LVDS */
11452 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
11454 /* Acer Aspire 5734Z must invert backlight brightness */
11455 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
11457 /* Acer/eMachines G725 */
11458 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
11460 /* Acer/eMachines e725 */
11461 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
11463 /* Acer/Packard Bell NCL20 */
11464 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
11466 /* Acer Aspire 4736Z */
11467 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
11469 /* Acer Aspire 5336 */
11470 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
11473 static void intel_init_quirks(struct drm_device *dev)
11475 struct pci_dev *d = dev->pdev;
11478 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
11479 struct intel_quirk *q = &intel_quirks[i];
11481 if (d->device == q->device &&
11482 (d->subsystem_vendor == q->subsystem_vendor ||
11483 q->subsystem_vendor == PCI_ANY_ID) &&
11484 (d->subsystem_device == q->subsystem_device ||
11485 q->subsystem_device == PCI_ANY_ID))
11488 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
11489 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
11490 intel_dmi_quirks[i].hook(dev);
11494 /* Disable the VGA plane that we never use */
11495 static void i915_disable_vga(struct drm_device *dev)
11497 struct drm_i915_private *dev_priv = dev->dev_private;
11499 u32 vga_reg = i915_vgacntrl_reg(dev);
11501 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
11502 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
11503 outb(SR01, VGA_SR_INDEX);
11504 sr1 = inb(VGA_SR_DATA);
11505 outb(sr1 | 1<<5, VGA_SR_DATA);
11506 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
11509 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
11510 POSTING_READ(vga_reg);
11513 void intel_modeset_init_hw(struct drm_device *dev)
11515 intel_prepare_ddi(dev);
11517 intel_init_clock_gating(dev);
11519 intel_reset_dpio(dev);
11521 intel_enable_gt_powersave(dev);
11524 void intel_modeset_suspend_hw(struct drm_device *dev)
11526 intel_suspend_hw(dev);
11529 void intel_modeset_init(struct drm_device *dev)
11531 struct drm_i915_private *dev_priv = dev->dev_private;
11534 struct intel_crtc *crtc;
11536 drm_mode_config_init(dev);
11538 dev->mode_config.min_width = 0;
11539 dev->mode_config.min_height = 0;
11541 dev->mode_config.preferred_depth = 24;
11542 dev->mode_config.prefer_shadow = 1;
11544 dev->mode_config.funcs = &intel_mode_funcs;
11546 intel_init_quirks(dev);
11548 intel_init_pm(dev);
11550 if (INTEL_INFO(dev)->num_pipes == 0)
11553 intel_init_display(dev);
11555 if (IS_GEN2(dev)) {
11556 dev->mode_config.max_width = 2048;
11557 dev->mode_config.max_height = 2048;
11558 } else if (IS_GEN3(dev)) {
11559 dev->mode_config.max_width = 4096;
11560 dev->mode_config.max_height = 4096;
11562 dev->mode_config.max_width = 8192;
11563 dev->mode_config.max_height = 8192;
11566 if (IS_GEN2(dev)) {
11567 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
11568 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
11570 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
11571 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
11574 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
11576 DRM_DEBUG_KMS("%d display pipe%s available.\n",
11577 INTEL_INFO(dev)->num_pipes,
11578 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
11580 for_each_pipe(pipe) {
11581 intel_crtc_init(dev, pipe);
11582 for_each_sprite(pipe, sprite) {
11583 ret = intel_plane_init(dev, pipe, sprite);
11585 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
11586 pipe_name(pipe), sprite_name(pipe, sprite), ret);
11590 intel_init_dpio(dev);
11591 intel_reset_dpio(dev);
11593 intel_cpu_pll_init(dev);
11594 intel_shared_dpll_init(dev);
11596 /* Just disable it once at startup */
11597 i915_disable_vga(dev);
11598 intel_setup_outputs(dev);
11600 /* Just in case the BIOS is doing something questionable. */
11601 intel_disable_fbc(dev);
11603 mutex_lock(&dev->mode_config.mutex);
11604 intel_modeset_setup_hw_state(dev, false);
11605 mutex_unlock(&dev->mode_config.mutex);
11607 for_each_intel_crtc(dev, crtc) {
11612 * Note that reserving the BIOS fb up front prevents us
11613 * from stuffing other stolen allocations like the ring
11614 * on top. This prevents some ugliness at boot time, and
11615 * can even allow for smooth boot transitions if the BIOS
11616 * fb is large enough for the active pipe configuration.
11618 if (dev_priv->display.get_plane_config) {
11619 dev_priv->display.get_plane_config(crtc,
11620 &crtc->plane_config);
11622 * If the fb is shared between multiple heads, we'll
11623 * just get the first one.
11625 intel_find_plane_obj(crtc, &crtc->plane_config);
11631 intel_connector_break_all_links(struct intel_connector *connector)
11633 connector->base.dpms = DRM_MODE_DPMS_OFF;
11634 connector->base.encoder = NULL;
11635 connector->encoder->connectors_active = false;
11636 connector->encoder->base.crtc = NULL;
11639 static void intel_enable_pipe_a(struct drm_device *dev)
11641 struct intel_connector *connector;
11642 struct drm_connector *crt = NULL;
11643 struct intel_load_detect_pipe load_detect_temp;
11645 /* We can't just switch on the pipe A, we need to set things up with a
11646 * proper mode and output configuration. As a gross hack, enable pipe A
11647 * by enabling the load detect pipe once. */
11648 list_for_each_entry(connector,
11649 &dev->mode_config.connector_list,
11651 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
11652 crt = &connector->base;
11660 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
11661 intel_release_load_detect_pipe(crt, &load_detect_temp);
11667 intel_check_plane_mapping(struct intel_crtc *crtc)
11669 struct drm_device *dev = crtc->base.dev;
11670 struct drm_i915_private *dev_priv = dev->dev_private;
11673 if (INTEL_INFO(dev)->num_pipes == 1)
11676 reg = DSPCNTR(!crtc->plane);
11677 val = I915_READ(reg);
11679 if ((val & DISPLAY_PLANE_ENABLE) &&
11680 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
11686 static void intel_sanitize_crtc(struct intel_crtc *crtc)
11688 struct drm_device *dev = crtc->base.dev;
11689 struct drm_i915_private *dev_priv = dev->dev_private;
11692 /* Clear any frame start delays used for debugging left by the BIOS */
11693 reg = PIPECONF(crtc->config.cpu_transcoder);
11694 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
11696 /* We need to sanitize the plane -> pipe mapping first because this will
11697 * disable the crtc (and hence change the state) if it is wrong. Note
11698 * that gen4+ has a fixed plane -> pipe mapping. */
11699 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
11700 struct intel_connector *connector;
11703 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
11704 crtc->base.base.id);
11706 /* Pipe has the wrong plane attached and the plane is active.
11707 * Temporarily change the plane mapping and disable everything
11709 plane = crtc->plane;
11710 crtc->plane = !plane;
11711 dev_priv->display.crtc_disable(&crtc->base);
11712 crtc->plane = plane;
11714 /* ... and break all links. */
11715 list_for_each_entry(connector, &dev->mode_config.connector_list,
11717 if (connector->encoder->base.crtc != &crtc->base)
11720 intel_connector_break_all_links(connector);
11723 WARN_ON(crtc->active);
11724 crtc->base.enabled = false;
11727 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
11728 crtc->pipe == PIPE_A && !crtc->active) {
11729 /* BIOS forgot to enable pipe A, this mostly happens after
11730 * resume. Force-enable the pipe to fix this, the update_dpms
11731 * call below we restore the pipe to the right state, but leave
11732 * the required bits on. */
11733 intel_enable_pipe_a(dev);
11736 /* Adjust the state of the output pipe according to whether we
11737 * have active connectors/encoders. */
11738 intel_crtc_update_dpms(&crtc->base);
11740 if (crtc->active != crtc->base.enabled) {
11741 struct intel_encoder *encoder;
11743 /* This can happen either due to bugs in the get_hw_state
11744 * functions or because the pipe is force-enabled due to the
11746 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
11747 crtc->base.base.id,
11748 crtc->base.enabled ? "enabled" : "disabled",
11749 crtc->active ? "enabled" : "disabled");
11751 crtc->base.enabled = crtc->active;
11753 /* Because we only establish the connector -> encoder ->
11754 * crtc links if something is active, this means the
11755 * crtc is now deactivated. Break the links. connector
11756 * -> encoder links are only establish when things are
11757 * actually up, hence no need to break them. */
11758 WARN_ON(crtc->active);
11760 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
11761 WARN_ON(encoder->connectors_active);
11762 encoder->base.crtc = NULL;
11765 if (crtc->active) {
11767 * We start out with underrun reporting disabled to avoid races.
11768 * For correct bookkeeping mark this on active crtcs.
11770 * No protection against concurrent access is required - at
11771 * worst a fifo underrun happens which also sets this to false.
11773 crtc->cpu_fifo_underrun_disabled = true;
11774 crtc->pch_fifo_underrun_disabled = true;
11778 static void intel_sanitize_encoder(struct intel_encoder *encoder)
11780 struct intel_connector *connector;
11781 struct drm_device *dev = encoder->base.dev;
11783 /* We need to check both for a crtc link (meaning that the
11784 * encoder is active and trying to read from a pipe) and the
11785 * pipe itself being active. */
11786 bool has_active_crtc = encoder->base.crtc &&
11787 to_intel_crtc(encoder->base.crtc)->active;
11789 if (encoder->connectors_active && !has_active_crtc) {
11790 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
11791 encoder->base.base.id,
11792 drm_get_encoder_name(&encoder->base));
11794 /* Connector is active, but has no active pipe. This is
11795 * fallout from our resume register restoring. Disable
11796 * the encoder manually again. */
11797 if (encoder->base.crtc) {
11798 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
11799 encoder->base.base.id,
11800 drm_get_encoder_name(&encoder->base));
11801 encoder->disable(encoder);
11804 /* Inconsistent output/port/pipe state happens presumably due to
11805 * a bug in one of the get_hw_state functions. Or someplace else
11806 * in our code, like the register restore mess on resume. Clamp
11807 * things to off as a safer default. */
11808 list_for_each_entry(connector,
11809 &dev->mode_config.connector_list,
11811 if (connector->encoder != encoder)
11814 intel_connector_break_all_links(connector);
11817 /* Enabled encoders without active connectors will be fixed in
11818 * the crtc fixup. */
11821 void i915_redisable_vga_power_on(struct drm_device *dev)
11823 struct drm_i915_private *dev_priv = dev->dev_private;
11824 u32 vga_reg = i915_vgacntrl_reg(dev);
11826 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
11827 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
11828 i915_disable_vga(dev);
11832 void i915_redisable_vga(struct drm_device *dev)
11834 struct drm_i915_private *dev_priv = dev->dev_private;
11836 /* This function can be called both from intel_modeset_setup_hw_state or
11837 * at a very early point in our resume sequence, where the power well
11838 * structures are not yet restored. Since this function is at a very
11839 * paranoid "someone might have enabled VGA while we were not looking"
11840 * level, just check if the power well is enabled instead of trying to
11841 * follow the "don't touch the power well if we don't need it" policy
11842 * the rest of the driver uses. */
11843 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
11846 i915_redisable_vga_power_on(dev);
11849 static bool primary_get_hw_state(struct intel_crtc *crtc)
11851 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
11856 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
11859 static void intel_modeset_readout_hw_state(struct drm_device *dev)
11861 struct drm_i915_private *dev_priv = dev->dev_private;
11863 struct intel_crtc *crtc;
11864 struct intel_encoder *encoder;
11865 struct intel_connector *connector;
11868 for_each_intel_crtc(dev, crtc) {
11869 memset(&crtc->config, 0, sizeof(crtc->config));
11871 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
11873 crtc->active = dev_priv->display.get_pipe_config(crtc,
11876 crtc->base.enabled = crtc->active;
11877 crtc->primary_enabled = primary_get_hw_state(crtc);
11879 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
11880 crtc->base.base.id,
11881 crtc->active ? "enabled" : "disabled");
11884 /* FIXME: Smash this into the new shared dpll infrastructure. */
11886 intel_ddi_setup_hw_pll_state(dev);
11888 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11889 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11891 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
11893 for_each_intel_crtc(dev, crtc) {
11894 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11897 pll->refcount = pll->active;
11899 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
11900 pll->name, pll->refcount, pll->on);
11903 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11907 if (encoder->get_hw_state(encoder, &pipe)) {
11908 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11909 encoder->base.crtc = &crtc->base;
11910 encoder->get_config(encoder, &crtc->config);
11912 encoder->base.crtc = NULL;
11915 encoder->connectors_active = false;
11916 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
11917 encoder->base.base.id,
11918 drm_get_encoder_name(&encoder->base),
11919 encoder->base.crtc ? "enabled" : "disabled",
11923 list_for_each_entry(connector, &dev->mode_config.connector_list,
11925 if (connector->get_hw_state(connector)) {
11926 connector->base.dpms = DRM_MODE_DPMS_ON;
11927 connector->encoder->connectors_active = true;
11928 connector->base.encoder = &connector->encoder->base;
11930 connector->base.dpms = DRM_MODE_DPMS_OFF;
11931 connector->base.encoder = NULL;
11933 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
11934 connector->base.base.id,
11935 drm_get_connector_name(&connector->base),
11936 connector->base.encoder ? "enabled" : "disabled");
11940 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
11941 * and i915 state tracking structures. */
11942 void intel_modeset_setup_hw_state(struct drm_device *dev,
11943 bool force_restore)
11945 struct drm_i915_private *dev_priv = dev->dev_private;
11947 struct intel_crtc *crtc;
11948 struct intel_encoder *encoder;
11951 intel_modeset_readout_hw_state(dev);
11954 * Now that we have the config, copy it to each CRTC struct
11955 * Note that this could go away if we move to using crtc_config
11956 * checking everywhere.
11958 for_each_intel_crtc(dev, crtc) {
11959 if (crtc->active && i915.fastboot) {
11960 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
11961 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
11962 crtc->base.base.id);
11963 drm_mode_debug_printmodeline(&crtc->base.mode);
11967 /* HW state is read out, now we need to sanitize this mess. */
11968 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11970 intel_sanitize_encoder(encoder);
11973 for_each_pipe(pipe) {
11974 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11975 intel_sanitize_crtc(crtc);
11976 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
11979 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11980 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11982 if (!pll->on || pll->active)
11985 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
11987 pll->disable(dev_priv, pll);
11991 if (HAS_PCH_SPLIT(dev))
11992 ilk_wm_get_hw_state(dev);
11994 if (force_restore) {
11995 i915_redisable_vga(dev);
11998 * We need to use raw interfaces for restoring state to avoid
11999 * checking (bogus) intermediate states.
12001 for_each_pipe(pipe) {
12002 struct drm_crtc *crtc =
12003 dev_priv->pipe_to_crtc_mapping[pipe];
12005 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
12006 crtc->primary->fb);
12009 intel_modeset_update_staged_output_state(dev);
12012 intel_modeset_check_state(dev);
12015 void intel_modeset_gem_init(struct drm_device *dev)
12017 struct drm_crtc *c;
12018 struct intel_framebuffer *fb;
12020 mutex_lock(&dev->struct_mutex);
12021 intel_init_gt_powersave(dev);
12022 mutex_unlock(&dev->struct_mutex);
12024 intel_modeset_init_hw(dev);
12026 intel_setup_overlay(dev);
12029 * Make sure any fbs we allocated at startup are properly
12030 * pinned & fenced. When we do the allocation it's too early
12033 mutex_lock(&dev->struct_mutex);
12034 for_each_crtc(dev, c) {
12035 if (!c->primary->fb)
12038 fb = to_intel_framebuffer(c->primary->fb);
12039 if (intel_pin_and_fence_fb_obj(dev, fb->obj, NULL)) {
12040 DRM_ERROR("failed to pin boot fb on pipe %d\n",
12041 to_intel_crtc(c)->pipe);
12042 drm_framebuffer_unreference(c->primary->fb);
12043 c->primary->fb = NULL;
12046 mutex_unlock(&dev->struct_mutex);
12049 void intel_connector_unregister(struct intel_connector *intel_connector)
12051 struct drm_connector *connector = &intel_connector->base;
12053 intel_panel_destroy_backlight(connector);
12054 drm_sysfs_connector_remove(connector);
12057 void intel_modeset_cleanup(struct drm_device *dev)
12059 struct drm_i915_private *dev_priv = dev->dev_private;
12060 struct drm_crtc *crtc;
12061 struct drm_connector *connector;
12064 * Interrupts and polling as the first thing to avoid creating havoc.
12065 * Too much stuff here (turning of rps, connectors, ...) would
12066 * experience fancy races otherwise.
12068 drm_irq_uninstall(dev);
12069 cancel_work_sync(&dev_priv->hotplug_work);
12071 * Due to the hpd irq storm handling the hotplug work can re-arm the
12072 * poll handlers. Hence disable polling after hpd handling is shut down.
12074 drm_kms_helper_poll_fini(dev);
12076 mutex_lock(&dev->struct_mutex);
12078 intel_unregister_dsm_handler();
12080 for_each_crtc(dev, crtc) {
12081 /* Skip inactive CRTCs */
12082 if (!crtc->primary->fb)
12085 intel_increase_pllclock(crtc);
12088 intel_disable_fbc(dev);
12090 intel_disable_gt_powersave(dev);
12092 ironlake_teardown_rc6(dev);
12094 mutex_unlock(&dev->struct_mutex);
12096 /* flush any delayed tasks or pending work */
12097 flush_scheduled_work();
12099 /* destroy the backlight and sysfs files before encoders/connectors */
12100 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12101 struct intel_connector *intel_connector;
12103 intel_connector = to_intel_connector(connector);
12104 intel_connector->unregister(intel_connector);
12107 drm_mode_config_cleanup(dev);
12109 intel_cleanup_overlay(dev);
12111 mutex_lock(&dev->struct_mutex);
12112 intel_cleanup_gt_powersave(dev);
12113 mutex_unlock(&dev->struct_mutex);
12117 * Return which encoder is currently attached for connector.
12119 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
12121 return &intel_attached_encoder(connector)->base;
12124 void intel_connector_attach_encoder(struct intel_connector *connector,
12125 struct intel_encoder *encoder)
12127 connector->encoder = encoder;
12128 drm_mode_connector_attach_encoder(&connector->base,
12133 * set vga decode state - true == enable VGA decode
12135 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
12137 struct drm_i915_private *dev_priv = dev->dev_private;
12138 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
12141 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
12142 DRM_ERROR("failed to read control word\n");
12146 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
12150 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
12152 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
12154 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
12155 DRM_ERROR("failed to write control word\n");
12162 struct intel_display_error_state {
12164 u32 power_well_driver;
12166 int num_transcoders;
12168 struct intel_cursor_error_state {
12173 } cursor[I915_MAX_PIPES];
12175 struct intel_pipe_error_state {
12176 bool power_domain_on;
12179 } pipe[I915_MAX_PIPES];
12181 struct intel_plane_error_state {
12189 } plane[I915_MAX_PIPES];
12191 struct intel_transcoder_error_state {
12192 bool power_domain_on;
12193 enum transcoder cpu_transcoder;
12206 struct intel_display_error_state *
12207 intel_display_capture_error_state(struct drm_device *dev)
12209 struct drm_i915_private *dev_priv = dev->dev_private;
12210 struct intel_display_error_state *error;
12211 int transcoders[] = {
12219 if (INTEL_INFO(dev)->num_pipes == 0)
12222 error = kzalloc(sizeof(*error), GFP_ATOMIC);
12226 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
12227 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
12230 error->pipe[i].power_domain_on =
12231 intel_display_power_enabled_sw(dev_priv,
12232 POWER_DOMAIN_PIPE(i));
12233 if (!error->pipe[i].power_domain_on)
12236 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
12237 error->cursor[i].control = I915_READ(CURCNTR(i));
12238 error->cursor[i].position = I915_READ(CURPOS(i));
12239 error->cursor[i].base = I915_READ(CURBASE(i));
12241 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
12242 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
12243 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
12246 error->plane[i].control = I915_READ(DSPCNTR(i));
12247 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
12248 if (INTEL_INFO(dev)->gen <= 3) {
12249 error->plane[i].size = I915_READ(DSPSIZE(i));
12250 error->plane[i].pos = I915_READ(DSPPOS(i));
12252 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
12253 error->plane[i].addr = I915_READ(DSPADDR(i));
12254 if (INTEL_INFO(dev)->gen >= 4) {
12255 error->plane[i].surface = I915_READ(DSPSURF(i));
12256 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
12259 error->pipe[i].source = I915_READ(PIPESRC(i));
12261 if (!HAS_PCH_SPLIT(dev))
12262 error->pipe[i].stat = I915_READ(PIPESTAT(i));
12265 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
12266 if (HAS_DDI(dev_priv->dev))
12267 error->num_transcoders++; /* Account for eDP. */
12269 for (i = 0; i < error->num_transcoders; i++) {
12270 enum transcoder cpu_transcoder = transcoders[i];
12272 error->transcoder[i].power_domain_on =
12273 intel_display_power_enabled_sw(dev_priv,
12274 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
12275 if (!error->transcoder[i].power_domain_on)
12278 error->transcoder[i].cpu_transcoder = cpu_transcoder;
12280 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
12281 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
12282 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
12283 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
12284 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
12285 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
12286 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
12292 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
12295 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
12296 struct drm_device *dev,
12297 struct intel_display_error_state *error)
12304 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
12305 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
12306 err_printf(m, "PWR_WELL_CTL2: %08x\n",
12307 error->power_well_driver);
12309 err_printf(m, "Pipe [%d]:\n", i);
12310 err_printf(m, " Power: %s\n",
12311 error->pipe[i].power_domain_on ? "on" : "off");
12312 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
12313 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
12315 err_printf(m, "Plane [%d]:\n", i);
12316 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
12317 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
12318 if (INTEL_INFO(dev)->gen <= 3) {
12319 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
12320 err_printf(m, " POS: %08x\n", error->plane[i].pos);
12322 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
12323 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
12324 if (INTEL_INFO(dev)->gen >= 4) {
12325 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
12326 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
12329 err_printf(m, "Cursor [%d]:\n", i);
12330 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
12331 err_printf(m, " POS: %08x\n", error->cursor[i].position);
12332 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
12335 for (i = 0; i < error->num_transcoders; i++) {
12336 err_printf(m, "CPU transcoder: %c\n",
12337 transcoder_name(error->transcoder[i].cpu_transcoder));
12338 err_printf(m, " Power: %s\n",
12339 error->transcoder[i].power_domain_on ? "on" : "off");
12340 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
12341 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
12342 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
12343 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
12344 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
12345 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
12346 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);