2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
45 static void intel_increase_pllclock(struct drm_crtc *crtc);
46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
57 #define INTEL_P2_NUM 2
58 typedef struct intel_limit intel_limit_t;
60 intel_range_t dot, vco, n, m, m1, m2, p, p1;
63 * find_pll() - Find the best values for the PLL
64 * @limit: limits for the PLL
66 * @target: target frequency in kHz
67 * @refclk: reference clock frequency in kHz
68 * @match_clock: if provided, @best_clock P divider must
69 * match the P divider from @match_clock
70 * used for LVDS downclocking
71 * @best_clock: best PLL values found
73 * Returns true on success, false on failure.
75 bool (*find_pll)(const intel_limit_t *limit,
76 struct drm_crtc *crtc,
77 int target, int refclk,
78 intel_clock_t *match_clock,
79 intel_clock_t *best_clock);
83 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
86 intel_pch_rawclk(struct drm_device *dev)
88 struct drm_i915_private *dev_priv = dev->dev_private;
90 WARN_ON(!HAS_PCH_SPLIT(dev));
92 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
96 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
97 int target, int refclk, intel_clock_t *match_clock,
98 intel_clock_t *best_clock);
100 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
101 int target, int refclk, intel_clock_t *match_clock,
102 intel_clock_t *best_clock);
105 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
106 int target, int refclk, intel_clock_t *match_clock,
107 intel_clock_t *best_clock);
109 static inline u32 /* units of 100MHz */
110 intel_fdi_link_freq(struct drm_device *dev)
113 struct drm_i915_private *dev_priv = dev->dev_private;
114 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
119 static const intel_limit_t intel_limits_i8xx_dvo = {
120 .dot = { .min = 25000, .max = 350000 },
121 .vco = { .min = 930000, .max = 1400000 },
122 .n = { .min = 3, .max = 16 },
123 .m = { .min = 96, .max = 140 },
124 .m1 = { .min = 18, .max = 26 },
125 .m2 = { .min = 6, .max = 16 },
126 .p = { .min = 4, .max = 128 },
127 .p1 = { .min = 2, .max = 33 },
128 .p2 = { .dot_limit = 165000,
129 .p2_slow = 4, .p2_fast = 2 },
130 .find_pll = intel_find_best_PLL,
133 static const intel_limit_t intel_limits_i8xx_lvds = {
134 .dot = { .min = 25000, .max = 350000 },
135 .vco = { .min = 930000, .max = 1400000 },
136 .n = { .min = 3, .max = 16 },
137 .m = { .min = 96, .max = 140 },
138 .m1 = { .min = 18, .max = 26 },
139 .m2 = { .min = 6, .max = 16 },
140 .p = { .min = 4, .max = 128 },
141 .p1 = { .min = 1, .max = 6 },
142 .p2 = { .dot_limit = 165000,
143 .p2_slow = 14, .p2_fast = 7 },
144 .find_pll = intel_find_best_PLL,
147 static const intel_limit_t intel_limits_i9xx_sdvo = {
148 .dot = { .min = 20000, .max = 400000 },
149 .vco = { .min = 1400000, .max = 2800000 },
150 .n = { .min = 1, .max = 6 },
151 .m = { .min = 70, .max = 120 },
152 .m1 = { .min = 8, .max = 18 },
153 .m2 = { .min = 3, .max = 7 },
154 .p = { .min = 5, .max = 80 },
155 .p1 = { .min = 1, .max = 8 },
156 .p2 = { .dot_limit = 200000,
157 .p2_slow = 10, .p2_fast = 5 },
158 .find_pll = intel_find_best_PLL,
161 static const intel_limit_t intel_limits_i9xx_lvds = {
162 .dot = { .min = 20000, .max = 400000 },
163 .vco = { .min = 1400000, .max = 2800000 },
164 .n = { .min = 1, .max = 6 },
165 .m = { .min = 70, .max = 120 },
166 .m1 = { .min = 8, .max = 18 },
167 .m2 = { .min = 3, .max = 7 },
168 .p = { .min = 7, .max = 98 },
169 .p1 = { .min = 1, .max = 8 },
170 .p2 = { .dot_limit = 112000,
171 .p2_slow = 14, .p2_fast = 7 },
172 .find_pll = intel_find_best_PLL,
176 static const intel_limit_t intel_limits_g4x_sdvo = {
177 .dot = { .min = 25000, .max = 270000 },
178 .vco = { .min = 1750000, .max = 3500000},
179 .n = { .min = 1, .max = 4 },
180 .m = { .min = 104, .max = 138 },
181 .m1 = { .min = 17, .max = 23 },
182 .m2 = { .min = 5, .max = 11 },
183 .p = { .min = 10, .max = 30 },
184 .p1 = { .min = 1, .max = 3},
185 .p2 = { .dot_limit = 270000,
189 .find_pll = intel_g4x_find_best_PLL,
192 static const intel_limit_t intel_limits_g4x_hdmi = {
193 .dot = { .min = 22000, .max = 400000 },
194 .vco = { .min = 1750000, .max = 3500000},
195 .n = { .min = 1, .max = 4 },
196 .m = { .min = 104, .max = 138 },
197 .m1 = { .min = 16, .max = 23 },
198 .m2 = { .min = 5, .max = 11 },
199 .p = { .min = 5, .max = 80 },
200 .p1 = { .min = 1, .max = 8},
201 .p2 = { .dot_limit = 165000,
202 .p2_slow = 10, .p2_fast = 5 },
203 .find_pll = intel_g4x_find_best_PLL,
206 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
207 .dot = { .min = 20000, .max = 115000 },
208 .vco = { .min = 1750000, .max = 3500000 },
209 .n = { .min = 1, .max = 3 },
210 .m = { .min = 104, .max = 138 },
211 .m1 = { .min = 17, .max = 23 },
212 .m2 = { .min = 5, .max = 11 },
213 .p = { .min = 28, .max = 112 },
214 .p1 = { .min = 2, .max = 8 },
215 .p2 = { .dot_limit = 0,
216 .p2_slow = 14, .p2_fast = 14
218 .find_pll = intel_g4x_find_best_PLL,
221 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
222 .dot = { .min = 80000, .max = 224000 },
223 .vco = { .min = 1750000, .max = 3500000 },
224 .n = { .min = 1, .max = 3 },
225 .m = { .min = 104, .max = 138 },
226 .m1 = { .min = 17, .max = 23 },
227 .m2 = { .min = 5, .max = 11 },
228 .p = { .min = 14, .max = 42 },
229 .p1 = { .min = 2, .max = 6 },
230 .p2 = { .dot_limit = 0,
231 .p2_slow = 7, .p2_fast = 7
233 .find_pll = intel_g4x_find_best_PLL,
236 static const intel_limit_t intel_limits_pineview_sdvo = {
237 .dot = { .min = 20000, .max = 400000},
238 .vco = { .min = 1700000, .max = 3500000 },
239 /* Pineview's Ncounter is a ring counter */
240 .n = { .min = 3, .max = 6 },
241 .m = { .min = 2, .max = 256 },
242 /* Pineview only has one combined m divider, which we treat as m2. */
243 .m1 = { .min = 0, .max = 0 },
244 .m2 = { .min = 0, .max = 254 },
245 .p = { .min = 5, .max = 80 },
246 .p1 = { .min = 1, .max = 8 },
247 .p2 = { .dot_limit = 200000,
248 .p2_slow = 10, .p2_fast = 5 },
249 .find_pll = intel_find_best_PLL,
252 static const intel_limit_t intel_limits_pineview_lvds = {
253 .dot = { .min = 20000, .max = 400000 },
254 .vco = { .min = 1700000, .max = 3500000 },
255 .n = { .min = 3, .max = 6 },
256 .m = { .min = 2, .max = 256 },
257 .m1 = { .min = 0, .max = 0 },
258 .m2 = { .min = 0, .max = 254 },
259 .p = { .min = 7, .max = 112 },
260 .p1 = { .min = 1, .max = 8 },
261 .p2 = { .dot_limit = 112000,
262 .p2_slow = 14, .p2_fast = 14 },
263 .find_pll = intel_find_best_PLL,
266 /* Ironlake / Sandybridge
268 * We calculate clock using (register_value + 2) for N/M1/M2, so here
269 * the range value for them is (actual_value - 2).
271 static const intel_limit_t intel_limits_ironlake_dac = {
272 .dot = { .min = 25000, .max = 350000 },
273 .vco = { .min = 1760000, .max = 3510000 },
274 .n = { .min = 1, .max = 5 },
275 .m = { .min = 79, .max = 127 },
276 .m1 = { .min = 12, .max = 22 },
277 .m2 = { .min = 5, .max = 9 },
278 .p = { .min = 5, .max = 80 },
279 .p1 = { .min = 1, .max = 8 },
280 .p2 = { .dot_limit = 225000,
281 .p2_slow = 10, .p2_fast = 5 },
282 .find_pll = intel_g4x_find_best_PLL,
285 static const intel_limit_t intel_limits_ironlake_single_lvds = {
286 .dot = { .min = 25000, .max = 350000 },
287 .vco = { .min = 1760000, .max = 3510000 },
288 .n = { .min = 1, .max = 3 },
289 .m = { .min = 79, .max = 118 },
290 .m1 = { .min = 12, .max = 22 },
291 .m2 = { .min = 5, .max = 9 },
292 .p = { .min = 28, .max = 112 },
293 .p1 = { .min = 2, .max = 8 },
294 .p2 = { .dot_limit = 225000,
295 .p2_slow = 14, .p2_fast = 14 },
296 .find_pll = intel_g4x_find_best_PLL,
299 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
300 .dot = { .min = 25000, .max = 350000 },
301 .vco = { .min = 1760000, .max = 3510000 },
302 .n = { .min = 1, .max = 3 },
303 .m = { .min = 79, .max = 127 },
304 .m1 = { .min = 12, .max = 22 },
305 .m2 = { .min = 5, .max = 9 },
306 .p = { .min = 14, .max = 56 },
307 .p1 = { .min = 2, .max = 8 },
308 .p2 = { .dot_limit = 225000,
309 .p2_slow = 7, .p2_fast = 7 },
310 .find_pll = intel_g4x_find_best_PLL,
313 /* LVDS 100mhz refclk limits. */
314 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
315 .dot = { .min = 25000, .max = 350000 },
316 .vco = { .min = 1760000, .max = 3510000 },
317 .n = { .min = 1, .max = 2 },
318 .m = { .min = 79, .max = 126 },
319 .m1 = { .min = 12, .max = 22 },
320 .m2 = { .min = 5, .max = 9 },
321 .p = { .min = 28, .max = 112 },
322 .p1 = { .min = 2, .max = 8 },
323 .p2 = { .dot_limit = 225000,
324 .p2_slow = 14, .p2_fast = 14 },
325 .find_pll = intel_g4x_find_best_PLL,
328 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
329 .dot = { .min = 25000, .max = 350000 },
330 .vco = { .min = 1760000, .max = 3510000 },
331 .n = { .min = 1, .max = 3 },
332 .m = { .min = 79, .max = 126 },
333 .m1 = { .min = 12, .max = 22 },
334 .m2 = { .min = 5, .max = 9 },
335 .p = { .min = 14, .max = 42 },
336 .p1 = { .min = 2, .max = 6 },
337 .p2 = { .dot_limit = 225000,
338 .p2_slow = 7, .p2_fast = 7 },
339 .find_pll = intel_g4x_find_best_PLL,
342 static const intel_limit_t intel_limits_vlv_dac = {
343 .dot = { .min = 25000, .max = 270000 },
344 .vco = { .min = 4000000, .max = 6000000 },
345 .n = { .min = 1, .max = 7 },
346 .m = { .min = 22, .max = 450 }, /* guess */
347 .m1 = { .min = 2, .max = 3 },
348 .m2 = { .min = 11, .max = 156 },
349 .p = { .min = 10, .max = 30 },
350 .p1 = { .min = 1, .max = 3 },
351 .p2 = { .dot_limit = 270000,
352 .p2_slow = 2, .p2_fast = 20 },
353 .find_pll = intel_vlv_find_best_pll,
356 static const intel_limit_t intel_limits_vlv_hdmi = {
357 .dot = { .min = 25000, .max = 270000 },
358 .vco = { .min = 4000000, .max = 6000000 },
359 .n = { .min = 1, .max = 7 },
360 .m = { .min = 60, .max = 300 }, /* guess */
361 .m1 = { .min = 2, .max = 3 },
362 .m2 = { .min = 11, .max = 156 },
363 .p = { .min = 10, .max = 30 },
364 .p1 = { .min = 2, .max = 3 },
365 .p2 = { .dot_limit = 270000,
366 .p2_slow = 2, .p2_fast = 20 },
367 .find_pll = intel_vlv_find_best_pll,
370 static const intel_limit_t intel_limits_vlv_dp = {
371 .dot = { .min = 25000, .max = 270000 },
372 .vco = { .min = 4000000, .max = 6000000 },
373 .n = { .min = 1, .max = 7 },
374 .m = { .min = 22, .max = 450 },
375 .m1 = { .min = 2, .max = 3 },
376 .m2 = { .min = 11, .max = 156 },
377 .p = { .min = 10, .max = 30 },
378 .p1 = { .min = 1, .max = 3 },
379 .p2 = { .dot_limit = 270000,
380 .p2_slow = 2, .p2_fast = 20 },
381 .find_pll = intel_vlv_find_best_pll,
384 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
386 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
388 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
389 DRM_ERROR("DPIO idle wait timed out\n");
393 I915_WRITE(DPIO_REG, reg);
394 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
396 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
397 DRM_ERROR("DPIO read wait timed out\n");
401 return I915_READ(DPIO_DATA);
404 void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val)
406 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
408 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
409 DRM_ERROR("DPIO idle wait timed out\n");
413 I915_WRITE(DPIO_DATA, val);
414 I915_WRITE(DPIO_REG, reg);
415 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
417 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
418 DRM_ERROR("DPIO write wait timed out\n");
421 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
424 struct drm_device *dev = crtc->dev;
425 const intel_limit_t *limit;
427 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
428 if (intel_is_dual_link_lvds(dev)) {
429 if (refclk == 100000)
430 limit = &intel_limits_ironlake_dual_lvds_100m;
432 limit = &intel_limits_ironlake_dual_lvds;
434 if (refclk == 100000)
435 limit = &intel_limits_ironlake_single_lvds_100m;
437 limit = &intel_limits_ironlake_single_lvds;
440 limit = &intel_limits_ironlake_dac;
445 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
447 struct drm_device *dev = crtc->dev;
448 const intel_limit_t *limit;
450 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
451 if (intel_is_dual_link_lvds(dev))
452 limit = &intel_limits_g4x_dual_channel_lvds;
454 limit = &intel_limits_g4x_single_channel_lvds;
455 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
456 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
457 limit = &intel_limits_g4x_hdmi;
458 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
459 limit = &intel_limits_g4x_sdvo;
460 } else /* The option is for other outputs */
461 limit = &intel_limits_i9xx_sdvo;
466 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
468 struct drm_device *dev = crtc->dev;
469 const intel_limit_t *limit;
471 if (HAS_PCH_SPLIT(dev))
472 limit = intel_ironlake_limit(crtc, refclk);
473 else if (IS_G4X(dev)) {
474 limit = intel_g4x_limit(crtc);
475 } else if (IS_PINEVIEW(dev)) {
476 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
477 limit = &intel_limits_pineview_lvds;
479 limit = &intel_limits_pineview_sdvo;
480 } else if (IS_VALLEYVIEW(dev)) {
481 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
482 limit = &intel_limits_vlv_dac;
483 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
484 limit = &intel_limits_vlv_hdmi;
486 limit = &intel_limits_vlv_dp;
487 } else if (!IS_GEN2(dev)) {
488 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
489 limit = &intel_limits_i9xx_lvds;
491 limit = &intel_limits_i9xx_sdvo;
493 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
494 limit = &intel_limits_i8xx_lvds;
496 limit = &intel_limits_i8xx_dvo;
501 /* m1 is reserved as 0 in Pineview, n is a ring counter */
502 static void pineview_clock(int refclk, intel_clock_t *clock)
504 clock->m = clock->m2 + 2;
505 clock->p = clock->p1 * clock->p2;
506 clock->vco = refclk * clock->m / clock->n;
507 clock->dot = clock->vco / clock->p;
510 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
512 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
515 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
517 if (IS_PINEVIEW(dev)) {
518 pineview_clock(refclk, clock);
521 clock->m = i9xx_dpll_compute_m(clock);
522 clock->p = clock->p1 * clock->p2;
523 clock->vco = refclk * clock->m / (clock->n + 2);
524 clock->dot = clock->vco / clock->p;
528 * Returns whether any output on the specified pipe is of the specified type
530 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
532 struct drm_device *dev = crtc->dev;
533 struct intel_encoder *encoder;
535 for_each_encoder_on_crtc(dev, crtc, encoder)
536 if (encoder->type == type)
542 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
544 * Returns whether the given set of divisors are valid for a given refclk with
545 * the given connectors.
548 static bool intel_PLL_is_valid(struct drm_device *dev,
549 const intel_limit_t *limit,
550 const intel_clock_t *clock)
552 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
553 INTELPllInvalid("p1 out of range\n");
554 if (clock->p < limit->p.min || limit->p.max < clock->p)
555 INTELPllInvalid("p out of range\n");
556 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
557 INTELPllInvalid("m2 out of range\n");
558 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
559 INTELPllInvalid("m1 out of range\n");
560 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
561 INTELPllInvalid("m1 <= m2\n");
562 if (clock->m < limit->m.min || limit->m.max < clock->m)
563 INTELPllInvalid("m out of range\n");
564 if (clock->n < limit->n.min || limit->n.max < clock->n)
565 INTELPllInvalid("n out of range\n");
566 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
567 INTELPllInvalid("vco out of range\n");
568 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
569 * connector, etc., rather than just a single range.
571 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
572 INTELPllInvalid("dot out of range\n");
578 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
579 int target, int refclk, intel_clock_t *match_clock,
580 intel_clock_t *best_clock)
583 struct drm_device *dev = crtc->dev;
587 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
589 * For LVDS just rely on its current settings for dual-channel.
590 * We haven't figured out how to reliably set up different
591 * single/dual channel state, if we even can.
593 if (intel_is_dual_link_lvds(dev))
594 clock.p2 = limit->p2.p2_fast;
596 clock.p2 = limit->p2.p2_slow;
598 if (target < limit->p2.dot_limit)
599 clock.p2 = limit->p2.p2_slow;
601 clock.p2 = limit->p2.p2_fast;
604 memset(best_clock, 0, sizeof(*best_clock));
606 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
608 for (clock.m2 = limit->m2.min;
609 clock.m2 <= limit->m2.max; clock.m2++) {
610 /* m1 is always 0 in Pineview */
611 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
613 for (clock.n = limit->n.min;
614 clock.n <= limit->n.max; clock.n++) {
615 for (clock.p1 = limit->p1.min;
616 clock.p1 <= limit->p1.max; clock.p1++) {
619 intel_clock(dev, refclk, &clock);
620 if (!intel_PLL_is_valid(dev, limit,
624 clock.p != match_clock->p)
627 this_err = abs(clock.dot - target);
628 if (this_err < err) {
637 return (err != target);
641 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
642 int target, int refclk, intel_clock_t *match_clock,
643 intel_clock_t *best_clock)
645 struct drm_device *dev = crtc->dev;
649 /* approximately equals target * 0.00585 */
650 int err_most = (target >> 8) + (target >> 9);
653 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
656 if (HAS_PCH_SPLIT(dev))
660 if (intel_is_dual_link_lvds(dev))
661 clock.p2 = limit->p2.p2_fast;
663 clock.p2 = limit->p2.p2_slow;
665 if (target < limit->p2.dot_limit)
666 clock.p2 = limit->p2.p2_slow;
668 clock.p2 = limit->p2.p2_fast;
671 memset(best_clock, 0, sizeof(*best_clock));
672 max_n = limit->n.max;
673 /* based on hardware requirement, prefer smaller n to precision */
674 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
675 /* based on hardware requirement, prefere larger m1,m2 */
676 for (clock.m1 = limit->m1.max;
677 clock.m1 >= limit->m1.min; clock.m1--) {
678 for (clock.m2 = limit->m2.max;
679 clock.m2 >= limit->m2.min; clock.m2--) {
680 for (clock.p1 = limit->p1.max;
681 clock.p1 >= limit->p1.min; clock.p1--) {
684 intel_clock(dev, refclk, &clock);
685 if (!intel_PLL_is_valid(dev, limit,
689 this_err = abs(clock.dot - target);
690 if (this_err < err_most) {
704 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
705 int target, int refclk, intel_clock_t *match_clock,
706 intel_clock_t *best_clock)
708 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
710 u32 updrate, minupdate, fracbits, p;
711 unsigned long bestppm, ppm, absppm;
715 dotclk = target * 1000;
718 fastclk = dotclk / (2*100);
722 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
723 bestm1 = bestm2 = bestp1 = bestp2 = 0;
725 /* based on hardware requirement, prefer smaller n to precision */
726 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
727 updrate = refclk / n;
728 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
729 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
733 /* based on hardware requirement, prefer bigger m1,m2 values */
734 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
735 m2 = (((2*(fastclk * p * n / m1 )) +
736 refclk) / (2*refclk));
739 if (vco >= limit->vco.min && vco < limit->vco.max) {
740 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
741 absppm = (ppm > 0) ? ppm : (-ppm);
742 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
746 if (absppm < bestppm - 10) {
763 best_clock->n = bestn;
764 best_clock->m1 = bestm1;
765 best_clock->m2 = bestm2;
766 best_clock->p1 = bestp1;
767 best_clock->p2 = bestp2;
772 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
775 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
776 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
778 return intel_crtc->config.cpu_transcoder;
781 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
783 struct drm_i915_private *dev_priv = dev->dev_private;
784 u32 frame, frame_reg = PIPEFRAME(pipe);
786 frame = I915_READ(frame_reg);
788 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
789 DRM_DEBUG_KMS("vblank wait timed out\n");
793 * intel_wait_for_vblank - wait for vblank on a given pipe
795 * @pipe: pipe to wait for
797 * Wait for vblank to occur on a given pipe. Needed for various bits of
800 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
802 struct drm_i915_private *dev_priv = dev->dev_private;
803 int pipestat_reg = PIPESTAT(pipe);
805 if (INTEL_INFO(dev)->gen >= 5) {
806 ironlake_wait_for_vblank(dev, pipe);
810 /* Clear existing vblank status. Note this will clear any other
811 * sticky status fields as well.
813 * This races with i915_driver_irq_handler() with the result
814 * that either function could miss a vblank event. Here it is not
815 * fatal, as we will either wait upon the next vblank interrupt or
816 * timeout. Generally speaking intel_wait_for_vblank() is only
817 * called during modeset at which time the GPU should be idle and
818 * should *not* be performing page flips and thus not waiting on
820 * Currently, the result of us stealing a vblank from the irq
821 * handler is that a single frame will be skipped during swapbuffers.
823 I915_WRITE(pipestat_reg,
824 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
826 /* Wait for vblank interrupt bit to set */
827 if (wait_for(I915_READ(pipestat_reg) &
828 PIPE_VBLANK_INTERRUPT_STATUS,
830 DRM_DEBUG_KMS("vblank wait timed out\n");
834 * intel_wait_for_pipe_off - wait for pipe to turn off
836 * @pipe: pipe to wait for
838 * After disabling a pipe, we can't wait for vblank in the usual way,
839 * spinning on the vblank interrupt status bit, since we won't actually
840 * see an interrupt when the pipe is disabled.
843 * wait for the pipe register state bit to turn off
846 * wait for the display line value to settle (it usually
847 * ends up stopping at the start of the next frame).
850 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
852 struct drm_i915_private *dev_priv = dev->dev_private;
853 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
856 if (INTEL_INFO(dev)->gen >= 4) {
857 int reg = PIPECONF(cpu_transcoder);
859 /* Wait for the Pipe State to go off */
860 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
862 WARN(1, "pipe_off wait timed out\n");
864 u32 last_line, line_mask;
865 int reg = PIPEDSL(pipe);
866 unsigned long timeout = jiffies + msecs_to_jiffies(100);
869 line_mask = DSL_LINEMASK_GEN2;
871 line_mask = DSL_LINEMASK_GEN3;
873 /* Wait for the display line to settle */
875 last_line = I915_READ(reg) & line_mask;
877 } while (((I915_READ(reg) & line_mask) != last_line) &&
878 time_after(timeout, jiffies));
879 if (time_after(jiffies, timeout))
880 WARN(1, "pipe_off wait timed out\n");
885 * ibx_digital_port_connected - is the specified port connected?
886 * @dev_priv: i915 private structure
887 * @port: the port to test
889 * Returns true if @port is connected, false otherwise.
891 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
892 struct intel_digital_port *port)
896 if (HAS_PCH_IBX(dev_priv->dev)) {
899 bit = SDE_PORTB_HOTPLUG;
902 bit = SDE_PORTC_HOTPLUG;
905 bit = SDE_PORTD_HOTPLUG;
913 bit = SDE_PORTB_HOTPLUG_CPT;
916 bit = SDE_PORTC_HOTPLUG_CPT;
919 bit = SDE_PORTD_HOTPLUG_CPT;
926 return I915_READ(SDEISR) & bit;
929 static const char *state_string(bool enabled)
931 return enabled ? "on" : "off";
934 /* Only for pre-ILK configs */
935 static void assert_pll(struct drm_i915_private *dev_priv,
936 enum pipe pipe, bool state)
943 val = I915_READ(reg);
944 cur_state = !!(val & DPLL_VCO_ENABLE);
945 WARN(cur_state != state,
946 "PLL state assertion failure (expected %s, current %s)\n",
947 state_string(state), state_string(cur_state));
949 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
950 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
953 static void assert_pch_pll(struct drm_i915_private *dev_priv,
954 struct intel_pch_pll *pll,
955 struct intel_crtc *crtc,
961 if (HAS_PCH_LPT(dev_priv->dev)) {
962 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
967 "asserting PCH PLL %s with no PLL\n", state_string(state)))
970 val = I915_READ(pll->pll_reg);
971 cur_state = !!(val & DPLL_VCO_ENABLE);
972 WARN(cur_state != state,
973 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
974 pll->pll_reg, state_string(state), state_string(cur_state), val);
976 /* Make sure the selected PLL is correctly attached to the transcoder */
977 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
980 pch_dpll = I915_READ(PCH_DPLL_SEL);
981 cur_state = pll->pll_reg == _PCH_DPLL_B;
982 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
983 "PLL[%d] not attached to this transcoder %c: %08x\n",
984 cur_state, pipe_name(crtc->pipe), pch_dpll)) {
985 cur_state = !!(val >> (4*crtc->pipe + 3));
986 WARN(cur_state != state,
987 "PLL[%d] not %s on this transcoder %c: %08x\n",
988 pll->pll_reg == _PCH_DPLL_B,
990 pipe_name(crtc->pipe),
995 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
996 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
998 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
999 enum pipe pipe, bool state)
1004 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1007 if (HAS_DDI(dev_priv->dev)) {
1008 /* DDI does not have a specific FDI_TX register */
1009 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1010 val = I915_READ(reg);
1011 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1013 reg = FDI_TX_CTL(pipe);
1014 val = I915_READ(reg);
1015 cur_state = !!(val & FDI_TX_ENABLE);
1017 WARN(cur_state != state,
1018 "FDI TX state assertion failure (expected %s, current %s)\n",
1019 state_string(state), state_string(cur_state));
1021 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1022 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1024 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1025 enum pipe pipe, bool state)
1031 reg = FDI_RX_CTL(pipe);
1032 val = I915_READ(reg);
1033 cur_state = !!(val & FDI_RX_ENABLE);
1034 WARN(cur_state != state,
1035 "FDI RX state assertion failure (expected %s, current %s)\n",
1036 state_string(state), state_string(cur_state));
1038 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1039 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1041 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1047 /* ILK FDI PLL is always enabled */
1048 if (dev_priv->info->gen == 5)
1051 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1052 if (HAS_DDI(dev_priv->dev))
1055 reg = FDI_TX_CTL(pipe);
1056 val = I915_READ(reg);
1057 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1060 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1066 reg = FDI_RX_CTL(pipe);
1067 val = I915_READ(reg);
1068 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1071 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1074 int pp_reg, lvds_reg;
1076 enum pipe panel_pipe = PIPE_A;
1079 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1080 pp_reg = PCH_PP_CONTROL;
1081 lvds_reg = PCH_LVDS;
1083 pp_reg = PP_CONTROL;
1087 val = I915_READ(pp_reg);
1088 if (!(val & PANEL_POWER_ON) ||
1089 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1092 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1093 panel_pipe = PIPE_B;
1095 WARN(panel_pipe == pipe && locked,
1096 "panel assertion failure, pipe %c regs locked\n",
1100 void assert_pipe(struct drm_i915_private *dev_priv,
1101 enum pipe pipe, bool state)
1106 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1109 /* if we need the pipe A quirk it must be always on */
1110 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1113 if (!intel_using_power_well(dev_priv->dev) &&
1114 cpu_transcoder != TRANSCODER_EDP) {
1117 reg = PIPECONF(cpu_transcoder);
1118 val = I915_READ(reg);
1119 cur_state = !!(val & PIPECONF_ENABLE);
1122 WARN(cur_state != state,
1123 "pipe %c assertion failure (expected %s, current %s)\n",
1124 pipe_name(pipe), state_string(state), state_string(cur_state));
1127 static void assert_plane(struct drm_i915_private *dev_priv,
1128 enum plane plane, bool state)
1134 reg = DSPCNTR(plane);
1135 val = I915_READ(reg);
1136 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1137 WARN(cur_state != state,
1138 "plane %c assertion failure (expected %s, current %s)\n",
1139 plane_name(plane), state_string(state), state_string(cur_state));
1142 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1143 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1145 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1152 /* Planes are fixed to pipes on ILK+ */
1153 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
1154 reg = DSPCNTR(pipe);
1155 val = I915_READ(reg);
1156 WARN((val & DISPLAY_PLANE_ENABLE),
1157 "plane %c assertion failure, should be disabled but not\n",
1162 /* Need to check both planes against the pipe */
1163 for (i = 0; i < 2; i++) {
1165 val = I915_READ(reg);
1166 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1167 DISPPLANE_SEL_PIPE_SHIFT;
1168 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1169 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1170 plane_name(i), pipe_name(pipe));
1174 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1180 if (!IS_VALLEYVIEW(dev_priv->dev))
1183 /* Need to check both planes against the pipe */
1184 for (i = 0; i < dev_priv->num_plane; i++) {
1185 reg = SPCNTR(pipe, i);
1186 val = I915_READ(reg);
1187 WARN((val & SP_ENABLE),
1188 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1189 sprite_name(pipe, i), pipe_name(pipe));
1193 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1198 if (HAS_PCH_LPT(dev_priv->dev)) {
1199 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1203 val = I915_READ(PCH_DREF_CONTROL);
1204 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1205 DREF_SUPERSPREAD_SOURCE_MASK));
1206 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1209 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1216 reg = TRANSCONF(pipe);
1217 val = I915_READ(reg);
1218 enabled = !!(val & TRANS_ENABLE);
1220 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1224 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1225 enum pipe pipe, u32 port_sel, u32 val)
1227 if ((val & DP_PORT_EN) == 0)
1230 if (HAS_PCH_CPT(dev_priv->dev)) {
1231 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1232 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1233 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1236 if ((val & DP_PIPE_MASK) != (pipe << 30))
1242 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1243 enum pipe pipe, u32 val)
1245 if ((val & SDVO_ENABLE) == 0)
1248 if (HAS_PCH_CPT(dev_priv->dev)) {
1249 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1252 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1258 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1259 enum pipe pipe, u32 val)
1261 if ((val & LVDS_PORT_EN) == 0)
1264 if (HAS_PCH_CPT(dev_priv->dev)) {
1265 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1268 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1274 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1275 enum pipe pipe, u32 val)
1277 if ((val & ADPA_DAC_ENABLE) == 0)
1279 if (HAS_PCH_CPT(dev_priv->dev)) {
1280 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1283 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1289 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1290 enum pipe pipe, int reg, u32 port_sel)
1292 u32 val = I915_READ(reg);
1293 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1294 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1295 reg, pipe_name(pipe));
1297 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1298 && (val & DP_PIPEB_SELECT),
1299 "IBX PCH dp port still using transcoder B\n");
1302 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1303 enum pipe pipe, int reg)
1305 u32 val = I915_READ(reg);
1306 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1307 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1308 reg, pipe_name(pipe));
1310 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1311 && (val & SDVO_PIPE_B_SELECT),
1312 "IBX PCH hdmi port still using transcoder B\n");
1315 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1321 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1322 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1323 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1326 val = I915_READ(reg);
1327 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1328 "PCH VGA enabled on transcoder %c, should be disabled\n",
1332 val = I915_READ(reg);
1333 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1334 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1337 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1338 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1339 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1343 * intel_enable_pll - enable a PLL
1344 * @dev_priv: i915 private structure
1345 * @pipe: pipe PLL to enable
1347 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1348 * make sure the PLL reg is writable first though, since the panel write
1349 * protect mechanism may be enabled.
1351 * Note! This is for pre-ILK only.
1353 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1355 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1360 assert_pipe_disabled(dev_priv, pipe);
1362 /* No really, not for ILK+ */
1363 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1365 /* PLL is protected by panel, make sure we can write it */
1366 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1367 assert_panel_unlocked(dev_priv, pipe);
1370 val = I915_READ(reg);
1371 val |= DPLL_VCO_ENABLE;
1373 /* We do this three times for luck */
1374 I915_WRITE(reg, val);
1376 udelay(150); /* wait for warmup */
1377 I915_WRITE(reg, val);
1379 udelay(150); /* wait for warmup */
1380 I915_WRITE(reg, val);
1382 udelay(150); /* wait for warmup */
1386 * intel_disable_pll - disable a PLL
1387 * @dev_priv: i915 private structure
1388 * @pipe: pipe PLL to disable
1390 * Disable the PLL for @pipe, making sure the pipe is off first.
1392 * Note! This is for pre-ILK only.
1394 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1399 /* Don't disable pipe A or pipe A PLLs if needed */
1400 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1403 /* Make sure the pipe isn't still relying on us */
1404 assert_pipe_disabled(dev_priv, pipe);
1407 val = I915_READ(reg);
1408 val &= ~DPLL_VCO_ENABLE;
1409 I915_WRITE(reg, val);
1415 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1416 enum intel_sbi_destination destination)
1420 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1422 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1424 DRM_ERROR("timeout waiting for SBI to become ready\n");
1428 I915_WRITE(SBI_ADDR, (reg << 16));
1429 I915_WRITE(SBI_DATA, value);
1431 if (destination == SBI_ICLK)
1432 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1434 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1435 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
1437 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1439 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1445 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1446 enum intel_sbi_destination destination)
1449 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1451 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1453 DRM_ERROR("timeout waiting for SBI to become ready\n");
1457 I915_WRITE(SBI_ADDR, (reg << 16));
1459 if (destination == SBI_ICLK)
1460 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1462 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1463 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
1465 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1467 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1471 return I915_READ(SBI_DATA);
1474 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1479 port_mask = DPLL_PORTB_READY_MASK;
1481 port_mask = DPLL_PORTC_READY_MASK;
1483 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1484 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1485 'B' + port, I915_READ(DPLL(0)));
1489 * ironlake_enable_pch_pll - enable PCH PLL
1490 * @dev_priv: i915 private structure
1491 * @pipe: pipe PLL to enable
1493 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1494 * drives the transcoder clock.
1496 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1498 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1499 struct intel_pch_pll *pll;
1503 /* PCH PLLs only available on ILK, SNB and IVB */
1504 BUG_ON(dev_priv->info->gen < 5);
1505 pll = intel_crtc->pch_pll;
1509 if (WARN_ON(pll->refcount == 0))
1512 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1513 pll->pll_reg, pll->active, pll->on,
1514 intel_crtc->base.base.id);
1516 /* PCH refclock must be enabled first */
1517 assert_pch_refclk_enabled(dev_priv);
1519 if (pll->active++ && pll->on) {
1520 assert_pch_pll_enabled(dev_priv, pll, NULL);
1524 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1527 val = I915_READ(reg);
1528 val |= DPLL_VCO_ENABLE;
1529 I915_WRITE(reg, val);
1536 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1538 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1539 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1543 /* PCH only available on ILK+ */
1544 BUG_ON(dev_priv->info->gen < 5);
1548 if (WARN_ON(pll->refcount == 0))
1551 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1552 pll->pll_reg, pll->active, pll->on,
1553 intel_crtc->base.base.id);
1555 if (WARN_ON(pll->active == 0)) {
1556 assert_pch_pll_disabled(dev_priv, pll, NULL);
1560 if (--pll->active) {
1561 assert_pch_pll_enabled(dev_priv, pll, NULL);
1565 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1567 /* Make sure transcoder isn't still depending on us */
1568 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1571 val = I915_READ(reg);
1572 val &= ~DPLL_VCO_ENABLE;
1573 I915_WRITE(reg, val);
1580 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1583 struct drm_device *dev = dev_priv->dev;
1584 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1585 uint32_t reg, val, pipeconf_val;
1587 /* PCH only available on ILK+ */
1588 BUG_ON(dev_priv->info->gen < 5);
1590 /* Make sure PCH DPLL is enabled */
1591 assert_pch_pll_enabled(dev_priv,
1592 to_intel_crtc(crtc)->pch_pll,
1593 to_intel_crtc(crtc));
1595 /* FDI must be feeding us bits for PCH ports */
1596 assert_fdi_tx_enabled(dev_priv, pipe);
1597 assert_fdi_rx_enabled(dev_priv, pipe);
1599 if (HAS_PCH_CPT(dev)) {
1600 /* Workaround: Set the timing override bit before enabling the
1601 * pch transcoder. */
1602 reg = TRANS_CHICKEN2(pipe);
1603 val = I915_READ(reg);
1604 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1605 I915_WRITE(reg, val);
1608 reg = TRANSCONF(pipe);
1609 val = I915_READ(reg);
1610 pipeconf_val = I915_READ(PIPECONF(pipe));
1612 if (HAS_PCH_IBX(dev_priv->dev)) {
1614 * make the BPC in transcoder be consistent with
1615 * that in pipeconf reg.
1617 val &= ~PIPECONF_BPC_MASK;
1618 val |= pipeconf_val & PIPECONF_BPC_MASK;
1621 val &= ~TRANS_INTERLACE_MASK;
1622 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1623 if (HAS_PCH_IBX(dev_priv->dev) &&
1624 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1625 val |= TRANS_LEGACY_INTERLACED_ILK;
1627 val |= TRANS_INTERLACED;
1629 val |= TRANS_PROGRESSIVE;
1631 I915_WRITE(reg, val | TRANS_ENABLE);
1632 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1633 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1636 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1637 enum transcoder cpu_transcoder)
1639 u32 val, pipeconf_val;
1641 /* PCH only available on ILK+ */
1642 BUG_ON(dev_priv->info->gen < 5);
1644 /* FDI must be feeding us bits for PCH ports */
1645 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1646 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1648 /* Workaround: set timing override bit. */
1649 val = I915_READ(_TRANSA_CHICKEN2);
1650 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1651 I915_WRITE(_TRANSA_CHICKEN2, val);
1654 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1656 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1657 PIPECONF_INTERLACED_ILK)
1658 val |= TRANS_INTERLACED;
1660 val |= TRANS_PROGRESSIVE;
1662 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
1663 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1664 DRM_ERROR("Failed to enable PCH transcoder\n");
1667 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1670 struct drm_device *dev = dev_priv->dev;
1673 /* FDI relies on the transcoder */
1674 assert_fdi_tx_disabled(dev_priv, pipe);
1675 assert_fdi_rx_disabled(dev_priv, pipe);
1677 /* Ports must be off as well */
1678 assert_pch_ports_disabled(dev_priv, pipe);
1680 reg = TRANSCONF(pipe);
1681 val = I915_READ(reg);
1682 val &= ~TRANS_ENABLE;
1683 I915_WRITE(reg, val);
1684 /* wait for PCH transcoder off, transcoder state */
1685 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1686 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1688 if (!HAS_PCH_IBX(dev)) {
1689 /* Workaround: Clear the timing override chicken bit again. */
1690 reg = TRANS_CHICKEN2(pipe);
1691 val = I915_READ(reg);
1692 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1693 I915_WRITE(reg, val);
1697 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1701 val = I915_READ(_TRANSACONF);
1702 val &= ~TRANS_ENABLE;
1703 I915_WRITE(_TRANSACONF, val);
1704 /* wait for PCH transcoder off, transcoder state */
1705 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1706 DRM_ERROR("Failed to disable PCH transcoder\n");
1708 /* Workaround: clear timing override bit. */
1709 val = I915_READ(_TRANSA_CHICKEN2);
1710 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1711 I915_WRITE(_TRANSA_CHICKEN2, val);
1715 * intel_enable_pipe - enable a pipe, asserting requirements
1716 * @dev_priv: i915 private structure
1717 * @pipe: pipe to enable
1718 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1720 * Enable @pipe, making sure that various hardware specific requirements
1721 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1723 * @pipe should be %PIPE_A or %PIPE_B.
1725 * Will wait until the pipe is actually running (i.e. first vblank) before
1728 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1731 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1733 enum pipe pch_transcoder;
1737 assert_planes_disabled(dev_priv, pipe);
1738 assert_sprites_disabled(dev_priv, pipe);
1740 if (HAS_PCH_LPT(dev_priv->dev))
1741 pch_transcoder = TRANSCODER_A;
1743 pch_transcoder = pipe;
1746 * A pipe without a PLL won't actually be able to drive bits from
1747 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1750 if (!HAS_PCH_SPLIT(dev_priv->dev))
1751 assert_pll_enabled(dev_priv, pipe);
1754 /* if driving the PCH, we need FDI enabled */
1755 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1756 assert_fdi_tx_pll_enabled(dev_priv,
1757 (enum pipe) cpu_transcoder);
1759 /* FIXME: assert CPU port conditions for SNB+ */
1762 reg = PIPECONF(cpu_transcoder);
1763 val = I915_READ(reg);
1764 if (val & PIPECONF_ENABLE)
1767 I915_WRITE(reg, val | PIPECONF_ENABLE);
1768 intel_wait_for_vblank(dev_priv->dev, pipe);
1772 * intel_disable_pipe - disable a pipe, asserting requirements
1773 * @dev_priv: i915 private structure
1774 * @pipe: pipe to disable
1776 * Disable @pipe, making sure that various hardware specific requirements
1777 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1779 * @pipe should be %PIPE_A or %PIPE_B.
1781 * Will wait until the pipe has shut down before returning.
1783 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1786 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1792 * Make sure planes won't keep trying to pump pixels to us,
1793 * or we might hang the display.
1795 assert_planes_disabled(dev_priv, pipe);
1796 assert_sprites_disabled(dev_priv, pipe);
1798 /* Don't disable pipe A or pipe A PLLs if needed */
1799 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1802 reg = PIPECONF(cpu_transcoder);
1803 val = I915_READ(reg);
1804 if ((val & PIPECONF_ENABLE) == 0)
1807 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1808 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1812 * Plane regs are double buffered, going from enabled->disabled needs a
1813 * trigger in order to latch. The display address reg provides this.
1815 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1818 if (dev_priv->info->gen >= 4)
1819 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1821 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1825 * intel_enable_plane - enable a display plane on a given pipe
1826 * @dev_priv: i915 private structure
1827 * @plane: plane to enable
1828 * @pipe: pipe being fed
1830 * Enable @plane on @pipe, making sure that @pipe is running first.
1832 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1833 enum plane plane, enum pipe pipe)
1838 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1839 assert_pipe_enabled(dev_priv, pipe);
1841 reg = DSPCNTR(plane);
1842 val = I915_READ(reg);
1843 if (val & DISPLAY_PLANE_ENABLE)
1846 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1847 intel_flush_display_plane(dev_priv, plane);
1848 intel_wait_for_vblank(dev_priv->dev, pipe);
1852 * intel_disable_plane - disable a display plane
1853 * @dev_priv: i915 private structure
1854 * @plane: plane to disable
1855 * @pipe: pipe consuming the data
1857 * Disable @plane; should be an independent operation.
1859 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1860 enum plane plane, enum pipe pipe)
1865 reg = DSPCNTR(plane);
1866 val = I915_READ(reg);
1867 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1870 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1871 intel_flush_display_plane(dev_priv, plane);
1872 intel_wait_for_vblank(dev_priv->dev, pipe);
1875 static bool need_vtd_wa(struct drm_device *dev)
1877 #ifdef CONFIG_INTEL_IOMMU
1878 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1885 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1886 struct drm_i915_gem_object *obj,
1887 struct intel_ring_buffer *pipelined)
1889 struct drm_i915_private *dev_priv = dev->dev_private;
1893 switch (obj->tiling_mode) {
1894 case I915_TILING_NONE:
1895 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1896 alignment = 128 * 1024;
1897 else if (INTEL_INFO(dev)->gen >= 4)
1898 alignment = 4 * 1024;
1900 alignment = 64 * 1024;
1903 /* pin() will align the object as required by fence */
1907 /* Despite that we check this in framebuffer_init userspace can
1908 * screw us over and change the tiling after the fact. Only
1909 * pinned buffers can't change their tiling. */
1910 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1916 /* Note that the w/a also requires 64 PTE of padding following the
1917 * bo. We currently fill all unused PTE with the shadow page and so
1918 * we should always have valid PTE following the scanout preventing
1921 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1922 alignment = 256 * 1024;
1924 dev_priv->mm.interruptible = false;
1925 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1927 goto err_interruptible;
1929 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1930 * fence, whereas 965+ only requires a fence if using
1931 * framebuffer compression. For simplicity, we always install
1932 * a fence as the cost is not that onerous.
1934 ret = i915_gem_object_get_fence(obj);
1938 i915_gem_object_pin_fence(obj);
1940 dev_priv->mm.interruptible = true;
1944 i915_gem_object_unpin(obj);
1946 dev_priv->mm.interruptible = true;
1950 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1952 i915_gem_object_unpin_fence(obj);
1953 i915_gem_object_unpin(obj);
1956 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1957 * is assumed to be a power-of-two. */
1958 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1959 unsigned int tiling_mode,
1963 if (tiling_mode != I915_TILING_NONE) {
1964 unsigned int tile_rows, tiles;
1969 tiles = *x / (512/cpp);
1972 return tile_rows * pitch * 8 + tiles * 4096;
1974 unsigned int offset;
1976 offset = *y * pitch + *x * cpp;
1978 *x = (offset & 4095) / cpp;
1979 return offset & -4096;
1983 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1986 struct drm_device *dev = crtc->dev;
1987 struct drm_i915_private *dev_priv = dev->dev_private;
1988 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1989 struct intel_framebuffer *intel_fb;
1990 struct drm_i915_gem_object *obj;
1991 int plane = intel_crtc->plane;
1992 unsigned long linear_offset;
2001 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2005 intel_fb = to_intel_framebuffer(fb);
2006 obj = intel_fb->obj;
2008 reg = DSPCNTR(plane);
2009 dspcntr = I915_READ(reg);
2010 /* Mask out pixel format bits in case we change it */
2011 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2012 switch (fb->pixel_format) {
2014 dspcntr |= DISPPLANE_8BPP;
2016 case DRM_FORMAT_XRGB1555:
2017 case DRM_FORMAT_ARGB1555:
2018 dspcntr |= DISPPLANE_BGRX555;
2020 case DRM_FORMAT_RGB565:
2021 dspcntr |= DISPPLANE_BGRX565;
2023 case DRM_FORMAT_XRGB8888:
2024 case DRM_FORMAT_ARGB8888:
2025 dspcntr |= DISPPLANE_BGRX888;
2027 case DRM_FORMAT_XBGR8888:
2028 case DRM_FORMAT_ABGR8888:
2029 dspcntr |= DISPPLANE_RGBX888;
2031 case DRM_FORMAT_XRGB2101010:
2032 case DRM_FORMAT_ARGB2101010:
2033 dspcntr |= DISPPLANE_BGRX101010;
2035 case DRM_FORMAT_XBGR2101010:
2036 case DRM_FORMAT_ABGR2101010:
2037 dspcntr |= DISPPLANE_RGBX101010;
2043 if (INTEL_INFO(dev)->gen >= 4) {
2044 if (obj->tiling_mode != I915_TILING_NONE)
2045 dspcntr |= DISPPLANE_TILED;
2047 dspcntr &= ~DISPPLANE_TILED;
2050 I915_WRITE(reg, dspcntr);
2052 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2054 if (INTEL_INFO(dev)->gen >= 4) {
2055 intel_crtc->dspaddr_offset =
2056 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2057 fb->bits_per_pixel / 8,
2059 linear_offset -= intel_crtc->dspaddr_offset;
2061 intel_crtc->dspaddr_offset = linear_offset;
2064 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2065 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2066 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2067 if (INTEL_INFO(dev)->gen >= 4) {
2068 I915_MODIFY_DISPBASE(DSPSURF(plane),
2069 obj->gtt_offset + intel_crtc->dspaddr_offset);
2070 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2071 I915_WRITE(DSPLINOFF(plane), linear_offset);
2073 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2079 static int ironlake_update_plane(struct drm_crtc *crtc,
2080 struct drm_framebuffer *fb, int x, int y)
2082 struct drm_device *dev = crtc->dev;
2083 struct drm_i915_private *dev_priv = dev->dev_private;
2084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2085 struct intel_framebuffer *intel_fb;
2086 struct drm_i915_gem_object *obj;
2087 int plane = intel_crtc->plane;
2088 unsigned long linear_offset;
2098 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2102 intel_fb = to_intel_framebuffer(fb);
2103 obj = intel_fb->obj;
2105 reg = DSPCNTR(plane);
2106 dspcntr = I915_READ(reg);
2107 /* Mask out pixel format bits in case we change it */
2108 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2109 switch (fb->pixel_format) {
2111 dspcntr |= DISPPLANE_8BPP;
2113 case DRM_FORMAT_RGB565:
2114 dspcntr |= DISPPLANE_BGRX565;
2116 case DRM_FORMAT_XRGB8888:
2117 case DRM_FORMAT_ARGB8888:
2118 dspcntr |= DISPPLANE_BGRX888;
2120 case DRM_FORMAT_XBGR8888:
2121 case DRM_FORMAT_ABGR8888:
2122 dspcntr |= DISPPLANE_RGBX888;
2124 case DRM_FORMAT_XRGB2101010:
2125 case DRM_FORMAT_ARGB2101010:
2126 dspcntr |= DISPPLANE_BGRX101010;
2128 case DRM_FORMAT_XBGR2101010:
2129 case DRM_FORMAT_ABGR2101010:
2130 dspcntr |= DISPPLANE_RGBX101010;
2136 if (obj->tiling_mode != I915_TILING_NONE)
2137 dspcntr |= DISPPLANE_TILED;
2139 dspcntr &= ~DISPPLANE_TILED;
2142 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2144 I915_WRITE(reg, dspcntr);
2146 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2147 intel_crtc->dspaddr_offset =
2148 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2149 fb->bits_per_pixel / 8,
2151 linear_offset -= intel_crtc->dspaddr_offset;
2153 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2154 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2155 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2156 I915_MODIFY_DISPBASE(DSPSURF(plane),
2157 obj->gtt_offset + intel_crtc->dspaddr_offset);
2158 if (IS_HASWELL(dev)) {
2159 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2161 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2162 I915_WRITE(DSPLINOFF(plane), linear_offset);
2169 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2171 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2172 int x, int y, enum mode_set_atomic state)
2174 struct drm_device *dev = crtc->dev;
2175 struct drm_i915_private *dev_priv = dev->dev_private;
2177 if (dev_priv->display.disable_fbc)
2178 dev_priv->display.disable_fbc(dev);
2179 intel_increase_pllclock(crtc);
2181 return dev_priv->display.update_plane(crtc, fb, x, y);
2184 void intel_display_handle_reset(struct drm_device *dev)
2186 struct drm_i915_private *dev_priv = dev->dev_private;
2187 struct drm_crtc *crtc;
2190 * Flips in the rings have been nuked by the reset,
2191 * so complete all pending flips so that user space
2192 * will get its events and not get stuck.
2194 * Also update the base address of all primary
2195 * planes to the the last fb to make sure we're
2196 * showing the correct fb after a reset.
2198 * Need to make two loops over the crtcs so that we
2199 * don't try to grab a crtc mutex before the
2200 * pending_flip_queue really got woken up.
2203 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2204 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2205 enum plane plane = intel_crtc->plane;
2207 intel_prepare_page_flip(dev, plane);
2208 intel_finish_page_flip_plane(dev, plane);
2211 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2212 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2214 mutex_lock(&crtc->mutex);
2215 if (intel_crtc->active)
2216 dev_priv->display.update_plane(crtc, crtc->fb,
2218 mutex_unlock(&crtc->mutex);
2223 intel_finish_fb(struct drm_framebuffer *old_fb)
2225 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2226 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2227 bool was_interruptible = dev_priv->mm.interruptible;
2230 /* Big Hammer, we also need to ensure that any pending
2231 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2232 * current scanout is retired before unpinning the old
2235 * This should only fail upon a hung GPU, in which case we
2236 * can safely continue.
2238 dev_priv->mm.interruptible = false;
2239 ret = i915_gem_object_finish_gpu(obj);
2240 dev_priv->mm.interruptible = was_interruptible;
2245 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2247 struct drm_device *dev = crtc->dev;
2248 struct drm_i915_master_private *master_priv;
2249 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2251 if (!dev->primary->master)
2254 master_priv = dev->primary->master->driver_priv;
2255 if (!master_priv->sarea_priv)
2258 switch (intel_crtc->pipe) {
2260 master_priv->sarea_priv->pipeA_x = x;
2261 master_priv->sarea_priv->pipeA_y = y;
2264 master_priv->sarea_priv->pipeB_x = x;
2265 master_priv->sarea_priv->pipeB_y = y;
2273 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2274 struct drm_framebuffer *fb)
2276 struct drm_device *dev = crtc->dev;
2277 struct drm_i915_private *dev_priv = dev->dev_private;
2278 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2279 struct drm_framebuffer *old_fb;
2284 DRM_ERROR("No FB bound\n");
2288 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2289 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2290 plane_name(intel_crtc->plane),
2291 INTEL_INFO(dev)->num_pipes);
2295 mutex_lock(&dev->struct_mutex);
2296 ret = intel_pin_and_fence_fb_obj(dev,
2297 to_intel_framebuffer(fb)->obj,
2300 mutex_unlock(&dev->struct_mutex);
2301 DRM_ERROR("pin & fence failed\n");
2305 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2307 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2308 mutex_unlock(&dev->struct_mutex);
2309 DRM_ERROR("failed to update base address\n");
2319 intel_wait_for_vblank(dev, intel_crtc->pipe);
2320 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2323 intel_update_fbc(dev);
2324 mutex_unlock(&dev->struct_mutex);
2326 intel_crtc_update_sarea_pos(crtc, x, y);
2331 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2333 struct drm_device *dev = crtc->dev;
2334 struct drm_i915_private *dev_priv = dev->dev_private;
2335 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2336 int pipe = intel_crtc->pipe;
2339 /* enable normal train */
2340 reg = FDI_TX_CTL(pipe);
2341 temp = I915_READ(reg);
2342 if (IS_IVYBRIDGE(dev)) {
2343 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2344 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2346 temp &= ~FDI_LINK_TRAIN_NONE;
2347 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2349 I915_WRITE(reg, temp);
2351 reg = FDI_RX_CTL(pipe);
2352 temp = I915_READ(reg);
2353 if (HAS_PCH_CPT(dev)) {
2354 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2355 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2357 temp &= ~FDI_LINK_TRAIN_NONE;
2358 temp |= FDI_LINK_TRAIN_NONE;
2360 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2362 /* wait one idle pattern time */
2366 /* IVB wants error correction enabled */
2367 if (IS_IVYBRIDGE(dev))
2368 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2369 FDI_FE_ERRC_ENABLE);
2372 static void ivb_modeset_global_resources(struct drm_device *dev)
2374 struct drm_i915_private *dev_priv = dev->dev_private;
2375 struct intel_crtc *pipe_B_crtc =
2376 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2377 struct intel_crtc *pipe_C_crtc =
2378 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2381 /* When everything is off disable fdi C so that we could enable fdi B
2382 * with all lanes. XXX: This misses the case where a pipe is not using
2383 * any pch resources and so doesn't need any fdi lanes. */
2384 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2385 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2386 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2388 temp = I915_READ(SOUTH_CHICKEN1);
2389 temp &= ~FDI_BC_BIFURCATION_SELECT;
2390 DRM_DEBUG_KMS("disabling fdi C rx\n");
2391 I915_WRITE(SOUTH_CHICKEN1, temp);
2395 /* The FDI link training functions for ILK/Ibexpeak. */
2396 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2398 struct drm_device *dev = crtc->dev;
2399 struct drm_i915_private *dev_priv = dev->dev_private;
2400 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2401 int pipe = intel_crtc->pipe;
2402 int plane = intel_crtc->plane;
2403 u32 reg, temp, tries;
2405 /* FDI needs bits from pipe & plane first */
2406 assert_pipe_enabled(dev_priv, pipe);
2407 assert_plane_enabled(dev_priv, plane);
2409 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2411 reg = FDI_RX_IMR(pipe);
2412 temp = I915_READ(reg);
2413 temp &= ~FDI_RX_SYMBOL_LOCK;
2414 temp &= ~FDI_RX_BIT_LOCK;
2415 I915_WRITE(reg, temp);
2419 /* enable CPU FDI TX and PCH FDI RX */
2420 reg = FDI_TX_CTL(pipe);
2421 temp = I915_READ(reg);
2422 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2423 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2424 temp &= ~FDI_LINK_TRAIN_NONE;
2425 temp |= FDI_LINK_TRAIN_PATTERN_1;
2426 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2428 reg = FDI_RX_CTL(pipe);
2429 temp = I915_READ(reg);
2430 temp &= ~FDI_LINK_TRAIN_NONE;
2431 temp |= FDI_LINK_TRAIN_PATTERN_1;
2432 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2437 /* Ironlake workaround, enable clock pointer after FDI enable*/
2438 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2439 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2440 FDI_RX_PHASE_SYNC_POINTER_EN);
2442 reg = FDI_RX_IIR(pipe);
2443 for (tries = 0; tries < 5; tries++) {
2444 temp = I915_READ(reg);
2445 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2447 if ((temp & FDI_RX_BIT_LOCK)) {
2448 DRM_DEBUG_KMS("FDI train 1 done.\n");
2449 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2454 DRM_ERROR("FDI train 1 fail!\n");
2457 reg = FDI_TX_CTL(pipe);
2458 temp = I915_READ(reg);
2459 temp &= ~FDI_LINK_TRAIN_NONE;
2460 temp |= FDI_LINK_TRAIN_PATTERN_2;
2461 I915_WRITE(reg, temp);
2463 reg = FDI_RX_CTL(pipe);
2464 temp = I915_READ(reg);
2465 temp &= ~FDI_LINK_TRAIN_NONE;
2466 temp |= FDI_LINK_TRAIN_PATTERN_2;
2467 I915_WRITE(reg, temp);
2472 reg = FDI_RX_IIR(pipe);
2473 for (tries = 0; tries < 5; tries++) {
2474 temp = I915_READ(reg);
2475 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2477 if (temp & FDI_RX_SYMBOL_LOCK) {
2478 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2479 DRM_DEBUG_KMS("FDI train 2 done.\n");
2484 DRM_ERROR("FDI train 2 fail!\n");
2486 DRM_DEBUG_KMS("FDI train done\n");
2490 static const int snb_b_fdi_train_param[] = {
2491 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2492 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2493 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2494 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2497 /* The FDI link training functions for SNB/Cougarpoint. */
2498 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2500 struct drm_device *dev = crtc->dev;
2501 struct drm_i915_private *dev_priv = dev->dev_private;
2502 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2503 int pipe = intel_crtc->pipe;
2504 u32 reg, temp, i, retry;
2506 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2508 reg = FDI_RX_IMR(pipe);
2509 temp = I915_READ(reg);
2510 temp &= ~FDI_RX_SYMBOL_LOCK;
2511 temp &= ~FDI_RX_BIT_LOCK;
2512 I915_WRITE(reg, temp);
2517 /* enable CPU FDI TX and PCH FDI RX */
2518 reg = FDI_TX_CTL(pipe);
2519 temp = I915_READ(reg);
2520 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2521 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2522 temp &= ~FDI_LINK_TRAIN_NONE;
2523 temp |= FDI_LINK_TRAIN_PATTERN_1;
2524 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2526 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2527 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2529 I915_WRITE(FDI_RX_MISC(pipe),
2530 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2532 reg = FDI_RX_CTL(pipe);
2533 temp = I915_READ(reg);
2534 if (HAS_PCH_CPT(dev)) {
2535 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2536 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2538 temp &= ~FDI_LINK_TRAIN_NONE;
2539 temp |= FDI_LINK_TRAIN_PATTERN_1;
2541 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2546 for (i = 0; i < 4; i++) {
2547 reg = FDI_TX_CTL(pipe);
2548 temp = I915_READ(reg);
2549 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2550 temp |= snb_b_fdi_train_param[i];
2551 I915_WRITE(reg, temp);
2556 for (retry = 0; retry < 5; retry++) {
2557 reg = FDI_RX_IIR(pipe);
2558 temp = I915_READ(reg);
2559 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2560 if (temp & FDI_RX_BIT_LOCK) {
2561 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2562 DRM_DEBUG_KMS("FDI train 1 done.\n");
2571 DRM_ERROR("FDI train 1 fail!\n");
2574 reg = FDI_TX_CTL(pipe);
2575 temp = I915_READ(reg);
2576 temp &= ~FDI_LINK_TRAIN_NONE;
2577 temp |= FDI_LINK_TRAIN_PATTERN_2;
2579 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2581 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2583 I915_WRITE(reg, temp);
2585 reg = FDI_RX_CTL(pipe);
2586 temp = I915_READ(reg);
2587 if (HAS_PCH_CPT(dev)) {
2588 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2589 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2591 temp &= ~FDI_LINK_TRAIN_NONE;
2592 temp |= FDI_LINK_TRAIN_PATTERN_2;
2594 I915_WRITE(reg, temp);
2599 for (i = 0; i < 4; i++) {
2600 reg = FDI_TX_CTL(pipe);
2601 temp = I915_READ(reg);
2602 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2603 temp |= snb_b_fdi_train_param[i];
2604 I915_WRITE(reg, temp);
2609 for (retry = 0; retry < 5; retry++) {
2610 reg = FDI_RX_IIR(pipe);
2611 temp = I915_READ(reg);
2612 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2613 if (temp & FDI_RX_SYMBOL_LOCK) {
2614 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2615 DRM_DEBUG_KMS("FDI train 2 done.\n");
2624 DRM_ERROR("FDI train 2 fail!\n");
2626 DRM_DEBUG_KMS("FDI train done.\n");
2629 /* Manual link training for Ivy Bridge A0 parts */
2630 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2632 struct drm_device *dev = crtc->dev;
2633 struct drm_i915_private *dev_priv = dev->dev_private;
2634 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2635 int pipe = intel_crtc->pipe;
2638 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2640 reg = FDI_RX_IMR(pipe);
2641 temp = I915_READ(reg);
2642 temp &= ~FDI_RX_SYMBOL_LOCK;
2643 temp &= ~FDI_RX_BIT_LOCK;
2644 I915_WRITE(reg, temp);
2649 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2650 I915_READ(FDI_RX_IIR(pipe)));
2652 /* enable CPU FDI TX and PCH FDI RX */
2653 reg = FDI_TX_CTL(pipe);
2654 temp = I915_READ(reg);
2655 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2656 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2657 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2658 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2659 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2660 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2661 temp |= FDI_COMPOSITE_SYNC;
2662 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2664 I915_WRITE(FDI_RX_MISC(pipe),
2665 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2667 reg = FDI_RX_CTL(pipe);
2668 temp = I915_READ(reg);
2669 temp &= ~FDI_LINK_TRAIN_AUTO;
2670 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2671 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2672 temp |= FDI_COMPOSITE_SYNC;
2673 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2678 for (i = 0; i < 4; i++) {
2679 reg = FDI_TX_CTL(pipe);
2680 temp = I915_READ(reg);
2681 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2682 temp |= snb_b_fdi_train_param[i];
2683 I915_WRITE(reg, temp);
2688 reg = FDI_RX_IIR(pipe);
2689 temp = I915_READ(reg);
2690 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2692 if (temp & FDI_RX_BIT_LOCK ||
2693 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2694 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2695 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2700 DRM_ERROR("FDI train 1 fail!\n");
2703 reg = FDI_TX_CTL(pipe);
2704 temp = I915_READ(reg);
2705 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2706 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2707 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2708 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2709 I915_WRITE(reg, temp);
2711 reg = FDI_RX_CTL(pipe);
2712 temp = I915_READ(reg);
2713 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2714 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2715 I915_WRITE(reg, temp);
2720 for (i = 0; i < 4; i++) {
2721 reg = FDI_TX_CTL(pipe);
2722 temp = I915_READ(reg);
2723 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2724 temp |= snb_b_fdi_train_param[i];
2725 I915_WRITE(reg, temp);
2730 reg = FDI_RX_IIR(pipe);
2731 temp = I915_READ(reg);
2732 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2734 if (temp & FDI_RX_SYMBOL_LOCK) {
2735 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2736 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2741 DRM_ERROR("FDI train 2 fail!\n");
2743 DRM_DEBUG_KMS("FDI train done.\n");
2746 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2748 struct drm_device *dev = intel_crtc->base.dev;
2749 struct drm_i915_private *dev_priv = dev->dev_private;
2750 int pipe = intel_crtc->pipe;
2754 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2755 reg = FDI_RX_CTL(pipe);
2756 temp = I915_READ(reg);
2757 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2758 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2759 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2760 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2765 /* Switch from Rawclk to PCDclk */
2766 temp = I915_READ(reg);
2767 I915_WRITE(reg, temp | FDI_PCDCLK);
2772 /* Enable CPU FDI TX PLL, always on for Ironlake */
2773 reg = FDI_TX_CTL(pipe);
2774 temp = I915_READ(reg);
2775 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2776 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2783 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2785 struct drm_device *dev = intel_crtc->base.dev;
2786 struct drm_i915_private *dev_priv = dev->dev_private;
2787 int pipe = intel_crtc->pipe;
2790 /* Switch from PCDclk to Rawclk */
2791 reg = FDI_RX_CTL(pipe);
2792 temp = I915_READ(reg);
2793 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2795 /* Disable CPU FDI TX PLL */
2796 reg = FDI_TX_CTL(pipe);
2797 temp = I915_READ(reg);
2798 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2803 reg = FDI_RX_CTL(pipe);
2804 temp = I915_READ(reg);
2805 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2807 /* Wait for the clocks to turn off. */
2812 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2814 struct drm_device *dev = crtc->dev;
2815 struct drm_i915_private *dev_priv = dev->dev_private;
2816 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2817 int pipe = intel_crtc->pipe;
2820 /* disable CPU FDI tx and PCH FDI rx */
2821 reg = FDI_TX_CTL(pipe);
2822 temp = I915_READ(reg);
2823 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2826 reg = FDI_RX_CTL(pipe);
2827 temp = I915_READ(reg);
2828 temp &= ~(0x7 << 16);
2829 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2830 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2835 /* Ironlake workaround, disable clock pointer after downing FDI */
2836 if (HAS_PCH_IBX(dev)) {
2837 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2840 /* still set train pattern 1 */
2841 reg = FDI_TX_CTL(pipe);
2842 temp = I915_READ(reg);
2843 temp &= ~FDI_LINK_TRAIN_NONE;
2844 temp |= FDI_LINK_TRAIN_PATTERN_1;
2845 I915_WRITE(reg, temp);
2847 reg = FDI_RX_CTL(pipe);
2848 temp = I915_READ(reg);
2849 if (HAS_PCH_CPT(dev)) {
2850 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2851 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2853 temp &= ~FDI_LINK_TRAIN_NONE;
2854 temp |= FDI_LINK_TRAIN_PATTERN_1;
2856 /* BPC in FDI rx is consistent with that in PIPECONF */
2857 temp &= ~(0x07 << 16);
2858 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2859 I915_WRITE(reg, temp);
2865 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2867 struct drm_device *dev = crtc->dev;
2868 struct drm_i915_private *dev_priv = dev->dev_private;
2869 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2870 unsigned long flags;
2873 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2874 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2877 spin_lock_irqsave(&dev->event_lock, flags);
2878 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2879 spin_unlock_irqrestore(&dev->event_lock, flags);
2884 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2886 struct drm_device *dev = crtc->dev;
2887 struct drm_i915_private *dev_priv = dev->dev_private;
2889 if (crtc->fb == NULL)
2892 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2894 wait_event(dev_priv->pending_flip_queue,
2895 !intel_crtc_has_pending_flip(crtc));
2897 mutex_lock(&dev->struct_mutex);
2898 intel_finish_fb(crtc->fb);
2899 mutex_unlock(&dev->struct_mutex);
2902 /* Program iCLKIP clock to the desired frequency */
2903 static void lpt_program_iclkip(struct drm_crtc *crtc)
2905 struct drm_device *dev = crtc->dev;
2906 struct drm_i915_private *dev_priv = dev->dev_private;
2907 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2910 mutex_lock(&dev_priv->dpio_lock);
2912 /* It is necessary to ungate the pixclk gate prior to programming
2913 * the divisors, and gate it back when it is done.
2915 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2917 /* Disable SSCCTL */
2918 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2919 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2923 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2924 if (crtc->mode.clock == 20000) {
2929 /* The iCLK virtual clock root frequency is in MHz,
2930 * but the crtc->mode.clock in in KHz. To get the divisors,
2931 * it is necessary to divide one by another, so we
2932 * convert the virtual clock precision to KHz here for higher
2935 u32 iclk_virtual_root_freq = 172800 * 1000;
2936 u32 iclk_pi_range = 64;
2937 u32 desired_divisor, msb_divisor_value, pi_value;
2939 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2940 msb_divisor_value = desired_divisor / iclk_pi_range;
2941 pi_value = desired_divisor % iclk_pi_range;
2944 divsel = msb_divisor_value - 2;
2945 phaseinc = pi_value;
2948 /* This should not happen with any sane values */
2949 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2950 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2951 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2952 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2954 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2961 /* Program SSCDIVINTPHASE6 */
2962 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2963 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2964 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2965 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2966 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2967 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2968 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2969 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2971 /* Program SSCAUXDIV */
2972 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2973 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2974 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2975 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2977 /* Enable modulator and associated divider */
2978 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2979 temp &= ~SBI_SSCCTL_DISABLE;
2980 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2982 /* Wait for initialization time */
2985 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2987 mutex_unlock(&dev_priv->dpio_lock);
2991 * Enable PCH resources required for PCH ports:
2993 * - FDI training & RX/TX
2994 * - update transcoder timings
2995 * - DP transcoding bits
2998 static void ironlake_pch_enable(struct drm_crtc *crtc)
3000 struct drm_device *dev = crtc->dev;
3001 struct drm_i915_private *dev_priv = dev->dev_private;
3002 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3003 int pipe = intel_crtc->pipe;
3006 assert_transcoder_disabled(dev_priv, pipe);
3008 /* Write the TU size bits before fdi link training, so that error
3009 * detection works. */
3010 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3011 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3013 /* For PCH output, training FDI link */
3014 dev_priv->display.fdi_link_train(crtc);
3016 /* XXX: pch pll's can be enabled any time before we enable the PCH
3017 * transcoder, and we actually should do this to not upset any PCH
3018 * transcoder that already use the clock when we share it.
3020 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3021 * unconditionally resets the pll - we need that to have the right LVDS
3022 * enable sequence. */
3023 ironlake_enable_pch_pll(intel_crtc);
3025 if (HAS_PCH_CPT(dev)) {
3028 temp = I915_READ(PCH_DPLL_SEL);
3032 temp |= TRANSA_DPLL_ENABLE;
3033 sel = TRANSA_DPLLB_SEL;
3036 temp |= TRANSB_DPLL_ENABLE;
3037 sel = TRANSB_DPLLB_SEL;
3040 temp |= TRANSC_DPLL_ENABLE;
3041 sel = TRANSC_DPLLB_SEL;
3044 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3048 I915_WRITE(PCH_DPLL_SEL, temp);
3051 /* set transcoder timing, panel must allow it */
3052 assert_panel_unlocked(dev_priv, pipe);
3053 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3054 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3055 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
3057 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3058 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3059 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
3060 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
3062 intel_fdi_normal_train(crtc);
3064 /* For PCH DP, enable TRANS_DP_CTL */
3065 if (HAS_PCH_CPT(dev) &&
3066 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3067 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3068 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3069 reg = TRANS_DP_CTL(pipe);
3070 temp = I915_READ(reg);
3071 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3072 TRANS_DP_SYNC_MASK |
3074 temp |= (TRANS_DP_OUTPUT_ENABLE |
3075 TRANS_DP_ENH_FRAMING);
3076 temp |= bpc << 9; /* same format but at 11:9 */
3078 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3079 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3080 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3081 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3083 switch (intel_trans_dp_port_sel(crtc)) {
3085 temp |= TRANS_DP_PORT_SEL_B;
3088 temp |= TRANS_DP_PORT_SEL_C;
3091 temp |= TRANS_DP_PORT_SEL_D;
3097 I915_WRITE(reg, temp);
3100 ironlake_enable_pch_transcoder(dev_priv, pipe);
3103 static void lpt_pch_enable(struct drm_crtc *crtc)
3105 struct drm_device *dev = crtc->dev;
3106 struct drm_i915_private *dev_priv = dev->dev_private;
3107 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3108 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3110 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
3112 lpt_program_iclkip(crtc);
3114 /* Set transcoder timing. */
3115 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3116 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3117 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
3119 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3120 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3121 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3122 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
3124 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3127 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3129 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3134 if (pll->refcount == 0) {
3135 WARN(1, "bad PCH PLL refcount\n");
3140 intel_crtc->pch_pll = NULL;
3143 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3145 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3146 struct intel_pch_pll *pll;
3149 pll = intel_crtc->pch_pll;
3151 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3152 intel_crtc->base.base.id, pll->pll_reg);
3156 if (HAS_PCH_IBX(dev_priv->dev)) {
3157 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3158 i = intel_crtc->pipe;
3159 pll = &dev_priv->pch_plls[i];
3161 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3162 intel_crtc->base.base.id, pll->pll_reg);
3167 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3168 pll = &dev_priv->pch_plls[i];
3170 /* Only want to check enabled timings first */
3171 if (pll->refcount == 0)
3174 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3175 fp == I915_READ(pll->fp0_reg)) {
3176 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3177 intel_crtc->base.base.id,
3178 pll->pll_reg, pll->refcount, pll->active);
3184 /* Ok no matching timings, maybe there's a free one? */
3185 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3186 pll = &dev_priv->pch_plls[i];
3187 if (pll->refcount == 0) {
3188 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3189 intel_crtc->base.base.id, pll->pll_reg);
3197 intel_crtc->pch_pll = pll;
3199 DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
3200 prepare: /* separate function? */
3201 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3203 /* Wait for the clocks to stabilize before rewriting the regs */
3204 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3205 POSTING_READ(pll->pll_reg);
3208 I915_WRITE(pll->fp0_reg, fp);
3209 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3214 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3216 struct drm_i915_private *dev_priv = dev->dev_private;
3217 int dslreg = PIPEDSL(pipe);
3220 temp = I915_READ(dslreg);
3222 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3223 if (wait_for(I915_READ(dslreg) != temp, 5))
3224 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3228 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3230 struct drm_device *dev = crtc->base.dev;
3231 struct drm_i915_private *dev_priv = dev->dev_private;
3232 int pipe = crtc->pipe;
3234 if (crtc->config.pch_pfit.size &&
3235 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) {
3236 /* Force use of hard-coded filter coefficients
3237 * as some pre-programmed values are broken,
3240 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3241 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3242 PF_PIPE_SEL_IVB(pipe));
3244 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3245 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3246 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3250 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3252 struct drm_device *dev = crtc->dev;
3253 struct drm_i915_private *dev_priv = dev->dev_private;
3254 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3255 struct intel_encoder *encoder;
3256 int pipe = intel_crtc->pipe;
3257 int plane = intel_crtc->plane;
3260 WARN_ON(!crtc->enabled);
3262 if (intel_crtc->active)
3265 intel_crtc->active = true;
3267 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3268 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3270 intel_update_watermarks(dev);
3272 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3273 temp = I915_READ(PCH_LVDS);
3274 if ((temp & LVDS_PORT_EN) == 0)
3275 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3279 if (intel_crtc->config.has_pch_encoder) {
3280 /* Note: FDI PLL enabling _must_ be done before we enable the
3281 * cpu pipes, hence this is separate from all the other fdi/pch
3283 ironlake_fdi_pll_enable(intel_crtc);
3285 assert_fdi_tx_disabled(dev_priv, pipe);
3286 assert_fdi_rx_disabled(dev_priv, pipe);
3289 for_each_encoder_on_crtc(dev, crtc, encoder)
3290 if (encoder->pre_enable)
3291 encoder->pre_enable(encoder);
3293 /* Enable panel fitting for LVDS */
3294 ironlake_pfit_enable(intel_crtc);
3297 * On ILK+ LUT must be loaded before the pipe is running but with
3300 intel_crtc_load_lut(crtc);
3302 intel_enable_pipe(dev_priv, pipe,
3303 intel_crtc->config.has_pch_encoder);
3304 intel_enable_plane(dev_priv, plane, pipe);
3306 if (intel_crtc->config.has_pch_encoder)
3307 ironlake_pch_enable(crtc);
3309 mutex_lock(&dev->struct_mutex);
3310 intel_update_fbc(dev);
3311 mutex_unlock(&dev->struct_mutex);
3313 intel_crtc_update_cursor(crtc, true);
3315 for_each_encoder_on_crtc(dev, crtc, encoder)
3316 encoder->enable(encoder);
3318 if (HAS_PCH_CPT(dev))
3319 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3322 * There seems to be a race in PCH platform hw (at least on some
3323 * outputs) where an enabled pipe still completes any pageflip right
3324 * away (as if the pipe is off) instead of waiting for vblank. As soon
3325 * as the first vblank happend, everything works as expected. Hence just
3326 * wait for one vblank before returning to avoid strange things
3329 intel_wait_for_vblank(dev, intel_crtc->pipe);
3332 static void haswell_crtc_enable(struct drm_crtc *crtc)
3334 struct drm_device *dev = crtc->dev;
3335 struct drm_i915_private *dev_priv = dev->dev_private;
3336 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3337 struct intel_encoder *encoder;
3338 int pipe = intel_crtc->pipe;
3339 int plane = intel_crtc->plane;
3341 WARN_ON(!crtc->enabled);
3343 if (intel_crtc->active)
3346 intel_crtc->active = true;
3348 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3349 if (intel_crtc->config.has_pch_encoder)
3350 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3352 intel_update_watermarks(dev);
3354 if (intel_crtc->config.has_pch_encoder)
3355 dev_priv->display.fdi_link_train(crtc);
3357 for_each_encoder_on_crtc(dev, crtc, encoder)
3358 if (encoder->pre_enable)
3359 encoder->pre_enable(encoder);
3361 intel_ddi_enable_pipe_clock(intel_crtc);
3363 /* Enable panel fitting for eDP */
3364 ironlake_pfit_enable(intel_crtc);
3367 * On ILK+ LUT must be loaded before the pipe is running but with
3370 intel_crtc_load_lut(crtc);
3372 intel_ddi_set_pipe_settings(crtc);
3373 intel_ddi_enable_transcoder_func(crtc);
3375 intel_enable_pipe(dev_priv, pipe,
3376 intel_crtc->config.has_pch_encoder);
3377 intel_enable_plane(dev_priv, plane, pipe);
3379 if (intel_crtc->config.has_pch_encoder)
3380 lpt_pch_enable(crtc);
3382 mutex_lock(&dev->struct_mutex);
3383 intel_update_fbc(dev);
3384 mutex_unlock(&dev->struct_mutex);
3386 intel_crtc_update_cursor(crtc, true);
3388 for_each_encoder_on_crtc(dev, crtc, encoder)
3389 encoder->enable(encoder);
3392 * There seems to be a race in PCH platform hw (at least on some
3393 * outputs) where an enabled pipe still completes any pageflip right
3394 * away (as if the pipe is off) instead of waiting for vblank. As soon
3395 * as the first vblank happend, everything works as expected. Hence just
3396 * wait for one vblank before returning to avoid strange things
3399 intel_wait_for_vblank(dev, intel_crtc->pipe);
3402 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3404 struct drm_device *dev = crtc->dev;
3405 struct drm_i915_private *dev_priv = dev->dev_private;
3406 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3407 struct intel_encoder *encoder;
3408 int pipe = intel_crtc->pipe;
3409 int plane = intel_crtc->plane;
3413 if (!intel_crtc->active)
3416 for_each_encoder_on_crtc(dev, crtc, encoder)
3417 encoder->disable(encoder);
3419 intel_crtc_wait_for_pending_flips(crtc);
3420 drm_vblank_off(dev, pipe);
3421 intel_crtc_update_cursor(crtc, false);
3423 intel_disable_plane(dev_priv, plane, pipe);
3425 if (dev_priv->cfb_plane == plane)
3426 intel_disable_fbc(dev);
3428 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3429 intel_disable_pipe(dev_priv, pipe);
3432 I915_WRITE(PF_CTL(pipe), 0);
3433 I915_WRITE(PF_WIN_SZ(pipe), 0);
3435 for_each_encoder_on_crtc(dev, crtc, encoder)
3436 if (encoder->post_disable)
3437 encoder->post_disable(encoder);
3439 ironlake_fdi_disable(crtc);
3441 ironlake_disable_pch_transcoder(dev_priv, pipe);
3442 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3444 if (HAS_PCH_CPT(dev)) {
3445 /* disable TRANS_DP_CTL */
3446 reg = TRANS_DP_CTL(pipe);
3447 temp = I915_READ(reg);
3448 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3449 temp |= TRANS_DP_PORT_SEL_NONE;
3450 I915_WRITE(reg, temp);
3452 /* disable DPLL_SEL */
3453 temp = I915_READ(PCH_DPLL_SEL);
3456 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3459 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3462 /* C shares PLL A or B */
3463 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3468 I915_WRITE(PCH_DPLL_SEL, temp);
3471 /* disable PCH DPLL */
3472 intel_disable_pch_pll(intel_crtc);
3474 ironlake_fdi_pll_disable(intel_crtc);
3476 intel_crtc->active = false;
3477 intel_update_watermarks(dev);
3479 mutex_lock(&dev->struct_mutex);
3480 intel_update_fbc(dev);
3481 mutex_unlock(&dev->struct_mutex);
3484 static void haswell_crtc_disable(struct drm_crtc *crtc)
3486 struct drm_device *dev = crtc->dev;
3487 struct drm_i915_private *dev_priv = dev->dev_private;
3488 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3489 struct intel_encoder *encoder;
3490 int pipe = intel_crtc->pipe;
3491 int plane = intel_crtc->plane;
3492 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3494 if (!intel_crtc->active)
3497 for_each_encoder_on_crtc(dev, crtc, encoder)
3498 encoder->disable(encoder);
3500 intel_crtc_wait_for_pending_flips(crtc);
3501 drm_vblank_off(dev, pipe);
3502 intel_crtc_update_cursor(crtc, false);
3504 intel_disable_plane(dev_priv, plane, pipe);
3506 if (dev_priv->cfb_plane == plane)
3507 intel_disable_fbc(dev);
3509 if (intel_crtc->config.has_pch_encoder)
3510 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3511 intel_disable_pipe(dev_priv, pipe);
3513 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3515 /* XXX: Once we have proper panel fitter state tracking implemented with
3516 * hardware state read/check support we should switch to only disable
3517 * the panel fitter when we know it's used. */
3518 if (intel_using_power_well(dev)) {
3519 I915_WRITE(PF_CTL(pipe), 0);
3520 I915_WRITE(PF_WIN_SZ(pipe), 0);
3523 intel_ddi_disable_pipe_clock(intel_crtc);
3525 for_each_encoder_on_crtc(dev, crtc, encoder)
3526 if (encoder->post_disable)
3527 encoder->post_disable(encoder);
3529 if (intel_crtc->config.has_pch_encoder) {
3530 lpt_disable_pch_transcoder(dev_priv);
3531 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3532 intel_ddi_fdi_disable(crtc);
3535 intel_crtc->active = false;
3536 intel_update_watermarks(dev);
3538 mutex_lock(&dev->struct_mutex);
3539 intel_update_fbc(dev);
3540 mutex_unlock(&dev->struct_mutex);
3543 static void ironlake_crtc_off(struct drm_crtc *crtc)
3545 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3546 intel_put_pch_pll(intel_crtc);
3549 static void haswell_crtc_off(struct drm_crtc *crtc)
3551 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3553 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3554 * start using it. */
3555 intel_crtc->config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
3557 intel_ddi_put_crtc_pll(crtc);
3560 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3562 if (!enable && intel_crtc->overlay) {
3563 struct drm_device *dev = intel_crtc->base.dev;
3564 struct drm_i915_private *dev_priv = dev->dev_private;
3566 mutex_lock(&dev->struct_mutex);
3567 dev_priv->mm.interruptible = false;
3568 (void) intel_overlay_switch_off(intel_crtc->overlay);
3569 dev_priv->mm.interruptible = true;
3570 mutex_unlock(&dev->struct_mutex);
3573 /* Let userspace switch the overlay on again. In most cases userspace
3574 * has to recompute where to put it anyway.
3579 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3580 * cursor plane briefly if not already running after enabling the display
3582 * This workaround avoids occasional blank screens when self refresh is
3586 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3588 u32 cntl = I915_READ(CURCNTR(pipe));
3590 if ((cntl & CURSOR_MODE) == 0) {
3591 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3593 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3594 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3595 intel_wait_for_vblank(dev_priv->dev, pipe);
3596 I915_WRITE(CURCNTR(pipe), cntl);
3597 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3598 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3602 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3604 struct drm_device *dev = crtc->base.dev;
3605 struct drm_i915_private *dev_priv = dev->dev_private;
3606 struct intel_crtc_config *pipe_config = &crtc->config;
3608 if (!(intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
3609 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)))
3612 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3613 assert_pipe_disabled(dev_priv, crtc->pipe);
3616 * Enable automatic panel scaling so that non-native modes
3617 * fill the screen. The panel fitter should only be
3618 * adjusted whilst the pipe is disabled, according to
3619 * register description and PRM.
3621 DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n",
3622 pipe_config->gmch_pfit.control,
3623 pipe_config->gmch_pfit.pgm_ratios);
3625 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3626 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3629 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3631 struct drm_device *dev = crtc->dev;
3632 struct drm_i915_private *dev_priv = dev->dev_private;
3633 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3634 struct intel_encoder *encoder;
3635 int pipe = intel_crtc->pipe;
3636 int plane = intel_crtc->plane;
3638 WARN_ON(!crtc->enabled);
3640 if (intel_crtc->active)
3643 intel_crtc->active = true;
3644 intel_update_watermarks(dev);
3646 mutex_lock(&dev_priv->dpio_lock);
3648 for_each_encoder_on_crtc(dev, crtc, encoder)
3649 if (encoder->pre_pll_enable)
3650 encoder->pre_pll_enable(encoder);
3652 intel_enable_pll(dev_priv, pipe);
3654 for_each_encoder_on_crtc(dev, crtc, encoder)
3655 if (encoder->pre_enable)
3656 encoder->pre_enable(encoder);
3658 /* VLV wants encoder enabling _before_ the pipe is up. */
3659 for_each_encoder_on_crtc(dev, crtc, encoder)
3660 encoder->enable(encoder);
3662 /* Enable panel fitting for eDP */
3663 i9xx_pfit_enable(intel_crtc);
3665 intel_enable_pipe(dev_priv, pipe, false);
3666 intel_enable_plane(dev_priv, plane, pipe);
3668 intel_crtc_load_lut(crtc);
3669 intel_update_fbc(dev);
3671 /* Give the overlay scaler a chance to enable if it's on this pipe */
3672 intel_crtc_dpms_overlay(intel_crtc, true);
3673 intel_crtc_update_cursor(crtc, true);
3675 mutex_unlock(&dev_priv->dpio_lock);
3678 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3680 struct drm_device *dev = crtc->dev;
3681 struct drm_i915_private *dev_priv = dev->dev_private;
3682 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3683 struct intel_encoder *encoder;
3684 int pipe = intel_crtc->pipe;
3685 int plane = intel_crtc->plane;
3687 WARN_ON(!crtc->enabled);
3689 if (intel_crtc->active)
3692 intel_crtc->active = true;
3693 intel_update_watermarks(dev);
3695 intel_enable_pll(dev_priv, pipe);
3697 for_each_encoder_on_crtc(dev, crtc, encoder)
3698 if (encoder->pre_enable)
3699 encoder->pre_enable(encoder);
3701 /* Enable panel fitting for LVDS */
3702 i9xx_pfit_enable(intel_crtc);
3704 intel_enable_pipe(dev_priv, pipe, false);
3705 intel_enable_plane(dev_priv, plane, pipe);
3707 g4x_fixup_plane(dev_priv, pipe);
3709 intel_crtc_load_lut(crtc);
3710 intel_update_fbc(dev);
3712 /* Give the overlay scaler a chance to enable if it's on this pipe */
3713 intel_crtc_dpms_overlay(intel_crtc, true);
3714 intel_crtc_update_cursor(crtc, true);
3716 for_each_encoder_on_crtc(dev, crtc, encoder)
3717 encoder->enable(encoder);
3720 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3722 struct drm_device *dev = crtc->base.dev;
3723 struct drm_i915_private *dev_priv = dev->dev_private;
3725 uint32_t pctl = I915_READ(PFIT_CONTROL);
3727 assert_pipe_disabled(dev_priv, crtc->pipe);
3729 if (INTEL_INFO(dev)->gen >= 4)
3730 pipe = (pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT;
3734 if (pipe == crtc->pipe) {
3735 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", pctl);
3736 I915_WRITE(PFIT_CONTROL, 0);
3740 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3742 struct drm_device *dev = crtc->dev;
3743 struct drm_i915_private *dev_priv = dev->dev_private;
3744 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3745 struct intel_encoder *encoder;
3746 int pipe = intel_crtc->pipe;
3747 int plane = intel_crtc->plane;
3749 if (!intel_crtc->active)
3752 for_each_encoder_on_crtc(dev, crtc, encoder)
3753 encoder->disable(encoder);
3755 /* Give the overlay scaler a chance to disable if it's on this pipe */
3756 intel_crtc_wait_for_pending_flips(crtc);
3757 drm_vblank_off(dev, pipe);
3758 intel_crtc_dpms_overlay(intel_crtc, false);
3759 intel_crtc_update_cursor(crtc, false);
3761 if (dev_priv->cfb_plane == plane)
3762 intel_disable_fbc(dev);
3764 intel_disable_plane(dev_priv, plane, pipe);
3765 intel_disable_pipe(dev_priv, pipe);
3767 i9xx_pfit_disable(intel_crtc);
3769 for_each_encoder_on_crtc(dev, crtc, encoder)
3770 if (encoder->post_disable)
3771 encoder->post_disable(encoder);
3773 intel_disable_pll(dev_priv, pipe);
3775 intel_crtc->active = false;
3776 intel_update_fbc(dev);
3777 intel_update_watermarks(dev);
3780 static void i9xx_crtc_off(struct drm_crtc *crtc)
3784 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3787 struct drm_device *dev = crtc->dev;
3788 struct drm_i915_master_private *master_priv;
3789 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3790 int pipe = intel_crtc->pipe;
3792 if (!dev->primary->master)
3795 master_priv = dev->primary->master->driver_priv;
3796 if (!master_priv->sarea_priv)
3801 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3802 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3805 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3806 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3809 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3815 * Sets the power management mode of the pipe and plane.
3817 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3819 struct drm_device *dev = crtc->dev;
3820 struct drm_i915_private *dev_priv = dev->dev_private;
3821 struct intel_encoder *intel_encoder;
3822 bool enable = false;
3824 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3825 enable |= intel_encoder->connectors_active;
3828 dev_priv->display.crtc_enable(crtc);
3830 dev_priv->display.crtc_disable(crtc);
3832 intel_crtc_update_sarea(crtc, enable);
3835 static void intel_crtc_disable(struct drm_crtc *crtc)
3837 struct drm_device *dev = crtc->dev;
3838 struct drm_connector *connector;
3839 struct drm_i915_private *dev_priv = dev->dev_private;
3840 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3842 /* crtc should still be enabled when we disable it. */
3843 WARN_ON(!crtc->enabled);
3845 intel_crtc->eld_vld = false;
3846 dev_priv->display.crtc_disable(crtc);
3847 intel_crtc_update_sarea(crtc, false);
3848 dev_priv->display.off(crtc);
3850 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3851 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3854 mutex_lock(&dev->struct_mutex);
3855 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3856 mutex_unlock(&dev->struct_mutex);
3860 /* Update computed state. */
3861 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3862 if (!connector->encoder || !connector->encoder->crtc)
3865 if (connector->encoder->crtc != crtc)
3868 connector->dpms = DRM_MODE_DPMS_OFF;
3869 to_intel_encoder(connector->encoder)->connectors_active = false;
3873 void intel_modeset_disable(struct drm_device *dev)
3875 struct drm_crtc *crtc;
3877 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3879 intel_crtc_disable(crtc);
3883 void intel_encoder_destroy(struct drm_encoder *encoder)
3885 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3887 drm_encoder_cleanup(encoder);
3888 kfree(intel_encoder);
3891 /* Simple dpms helper for encodres with just one connector, no cloning and only
3892 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3893 * state of the entire output pipe. */
3894 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3896 if (mode == DRM_MODE_DPMS_ON) {
3897 encoder->connectors_active = true;
3899 intel_crtc_update_dpms(encoder->base.crtc);
3901 encoder->connectors_active = false;
3903 intel_crtc_update_dpms(encoder->base.crtc);
3907 /* Cross check the actual hw state with our own modeset state tracking (and it's
3908 * internal consistency). */
3909 static void intel_connector_check_state(struct intel_connector *connector)
3911 if (connector->get_hw_state(connector)) {
3912 struct intel_encoder *encoder = connector->encoder;
3913 struct drm_crtc *crtc;
3914 bool encoder_enabled;
3917 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3918 connector->base.base.id,
3919 drm_get_connector_name(&connector->base));
3921 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3922 "wrong connector dpms state\n");
3923 WARN(connector->base.encoder != &encoder->base,
3924 "active connector not linked to encoder\n");
3925 WARN(!encoder->connectors_active,
3926 "encoder->connectors_active not set\n");
3928 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3929 WARN(!encoder_enabled, "encoder not enabled\n");
3930 if (WARN_ON(!encoder->base.crtc))
3933 crtc = encoder->base.crtc;
3935 WARN(!crtc->enabled, "crtc not enabled\n");
3936 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3937 WARN(pipe != to_intel_crtc(crtc)->pipe,
3938 "encoder active on the wrong pipe\n");
3942 /* Even simpler default implementation, if there's really no special case to
3944 void intel_connector_dpms(struct drm_connector *connector, int mode)
3946 struct intel_encoder *encoder = intel_attached_encoder(connector);
3948 /* All the simple cases only support two dpms states. */
3949 if (mode != DRM_MODE_DPMS_ON)
3950 mode = DRM_MODE_DPMS_OFF;
3952 if (mode == connector->dpms)
3955 connector->dpms = mode;
3957 /* Only need to change hw state when actually enabled */
3958 if (encoder->base.crtc)
3959 intel_encoder_dpms(encoder, mode);
3961 WARN_ON(encoder->connectors_active != false);
3963 intel_modeset_check_state(connector->dev);
3966 /* Simple connector->get_hw_state implementation for encoders that support only
3967 * one connector and no cloning and hence the encoder state determines the state
3968 * of the connector. */
3969 bool intel_connector_get_hw_state(struct intel_connector *connector)
3972 struct intel_encoder *encoder = connector->encoder;
3974 return encoder->get_hw_state(encoder, &pipe);
3977 static void ironlake_fdi_compute_config(struct drm_device *dev,
3978 struct intel_crtc_config *pipe_config)
3980 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
3981 int target_clock, lane, link_bw;
3983 /* FDI is a binary signal running at ~2.7GHz, encoding
3984 * each output octet as 10 bits. The actual frequency
3985 * is stored as a divider into a 100MHz clock, and the
3986 * mode pixel clock is stored in units of 1KHz.
3987 * Hence the bw of each lane in terms of the mode signal
3990 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
3992 if (pipe_config->pixel_target_clock)
3993 target_clock = pipe_config->pixel_target_clock;
3995 target_clock = adjusted_mode->clock;
3997 lane = ironlake_get_lanes_required(target_clock, link_bw,
3998 pipe_config->pipe_bpp);
4000 pipe_config->fdi_lanes = lane;
4002 if (pipe_config->pixel_multiplier > 1)
4003 link_bw *= pipe_config->pixel_multiplier;
4004 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, target_clock,
4005 link_bw, &pipe_config->fdi_m_n);
4008 static bool intel_crtc_compute_config(struct drm_crtc *crtc,
4009 struct intel_crtc_config *pipe_config)
4011 struct drm_device *dev = crtc->dev;
4012 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4014 if (HAS_PCH_SPLIT(dev)) {
4015 /* FDI link clock is fixed at 2.7G */
4016 if (pipe_config->requested_mode.clock * 3
4017 > IRONLAKE_FDI_FREQ * 4)
4021 /* All interlaced capable intel hw wants timings in frames. Note though
4022 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4023 * timings, so we need to be careful not to clobber these.*/
4024 if (!pipe_config->timings_set)
4025 drm_mode_set_crtcinfo(adjusted_mode, 0);
4027 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
4028 * with a hsync front porch of 0.
4030 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4031 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4034 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4035 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4036 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4037 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4039 pipe_config->pipe_bpp = 8*3;
4042 if (pipe_config->has_pch_encoder)
4043 ironlake_fdi_compute_config(dev, pipe_config);
4048 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4050 return 400000; /* FIXME */
4053 static int i945_get_display_clock_speed(struct drm_device *dev)
4058 static int i915_get_display_clock_speed(struct drm_device *dev)
4063 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4068 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4072 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4074 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4077 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4078 case GC_DISPLAY_CLOCK_333_MHZ:
4081 case GC_DISPLAY_CLOCK_190_200_MHZ:
4087 static int i865_get_display_clock_speed(struct drm_device *dev)
4092 static int i855_get_display_clock_speed(struct drm_device *dev)
4095 /* Assume that the hardware is in the high speed state. This
4096 * should be the default.
4098 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4099 case GC_CLOCK_133_200:
4100 case GC_CLOCK_100_200:
4102 case GC_CLOCK_166_250:
4104 case GC_CLOCK_100_133:
4108 /* Shouldn't happen */
4112 static int i830_get_display_clock_speed(struct drm_device *dev)
4118 intel_reduce_ratio(uint32_t *num, uint32_t *den)
4120 while (*num > 0xffffff || *den > 0xffffff) {
4127 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4128 int pixel_clock, int link_clock,
4129 struct intel_link_m_n *m_n)
4132 m_n->gmch_m = bits_per_pixel * pixel_clock;
4133 m_n->gmch_n = link_clock * nlanes * 8;
4134 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4135 m_n->link_m = pixel_clock;
4136 m_n->link_n = link_clock;
4137 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
4140 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4142 if (i915_panel_use_ssc >= 0)
4143 return i915_panel_use_ssc != 0;
4144 return dev_priv->lvds_use_ssc
4145 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4148 static int vlv_get_refclk(struct drm_crtc *crtc)
4150 struct drm_device *dev = crtc->dev;
4151 struct drm_i915_private *dev_priv = dev->dev_private;
4152 int refclk = 27000; /* for DP & HDMI */
4154 return 100000; /* only one validated so far */
4156 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4158 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4159 if (intel_panel_use_ssc(dev_priv))
4163 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4170 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4172 struct drm_device *dev = crtc->dev;
4173 struct drm_i915_private *dev_priv = dev->dev_private;
4176 if (IS_VALLEYVIEW(dev)) {
4177 refclk = vlv_get_refclk(crtc);
4178 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4179 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4180 refclk = dev_priv->lvds_ssc_freq * 1000;
4181 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4183 } else if (!IS_GEN2(dev)) {
4192 static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc *crtc)
4194 unsigned dotclock = crtc->config.adjusted_mode.clock;
4195 struct dpll *clock = &crtc->config.dpll;
4197 /* SDVO TV has fixed PLL values depend on its clock range,
4198 this mirrors vbios setting. */
4199 if (dotclock >= 100000 && dotclock < 140500) {
4205 } else if (dotclock >= 140500 && dotclock <= 200000) {
4213 crtc->config.clock_set = true;
4216 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4218 return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2;
4221 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4223 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4226 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4227 intel_clock_t *reduced_clock)
4229 struct drm_device *dev = crtc->base.dev;
4230 struct drm_i915_private *dev_priv = dev->dev_private;
4231 int pipe = crtc->pipe;
4234 if (IS_PINEVIEW(dev)) {
4235 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4237 fp2 = pnv_dpll_compute_fp(reduced_clock);
4239 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4241 fp2 = i9xx_dpll_compute_fp(reduced_clock);
4244 I915_WRITE(FP0(pipe), fp);
4246 crtc->lowfreq_avail = false;
4247 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4248 reduced_clock && i915_powersave) {
4249 I915_WRITE(FP1(pipe), fp2);
4250 crtc->lowfreq_avail = true;
4252 I915_WRITE(FP1(pipe), fp);
4256 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4261 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4262 * and set it to a reasonable value instead.
4264 reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4265 reg_val &= 0xffffff00;
4266 reg_val |= 0x00000030;
4267 intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4269 reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4270 reg_val &= 0x8cffffff;
4271 reg_val = 0x8c000000;
4272 intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4274 reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4275 reg_val &= 0xffffff00;
4276 intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4278 reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4279 reg_val &= 0x00ffffff;
4280 reg_val |= 0xb0000000;
4281 intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4284 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4286 if (crtc->config.has_pch_encoder)
4287 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4289 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4292 static void vlv_update_pll(struct intel_crtc *crtc)
4294 struct drm_device *dev = crtc->base.dev;
4295 struct drm_i915_private *dev_priv = dev->dev_private;
4296 struct drm_display_mode *adjusted_mode =
4297 &crtc->config.adjusted_mode;
4298 struct intel_encoder *encoder;
4299 int pipe = crtc->pipe;
4301 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4303 u32 coreclk, reg_val, dpll_md;
4305 mutex_lock(&dev_priv->dpio_lock);
4307 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4309 bestn = crtc->config.dpll.n;
4310 bestm1 = crtc->config.dpll.m1;
4311 bestm2 = crtc->config.dpll.m2;
4312 bestp1 = crtc->config.dpll.p1;
4313 bestp2 = crtc->config.dpll.p2;
4315 /* See eDP HDMI DPIO driver vbios notes doc */
4317 /* PLL B needs special handling */
4319 vlv_pllb_recal_opamp(dev_priv);
4321 /* Set up Tx target for periodic Rcomp update */
4322 intel_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4324 /* Disable target IRef on PLL */
4325 reg_val = intel_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4326 reg_val &= 0x00ffffff;
4327 intel_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4329 /* Disable fast lock */
4330 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4332 /* Set idtafcrecal before PLL is enabled */
4333 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4334 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4335 mdiv |= ((bestn << DPIO_N_SHIFT));
4336 mdiv |= (1 << DPIO_K_SHIFT);
4337 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI) ||
4338 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4339 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4340 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4341 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4343 mdiv |= DPIO_ENABLE_CALIBRATION;
4344 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4346 /* Set HBR and RBR LPF coefficients */
4347 if (adjusted_mode->clock == 162000 ||
4348 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4349 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4352 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4355 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4356 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4357 /* Use SSC source */
4359 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4362 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4364 } else { /* HDMI or VGA */
4365 /* Use bend source */
4367 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4370 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4374 coreclk = intel_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4375 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4376 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4377 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4378 coreclk |= 0x01000000;
4379 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4381 intel_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4383 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4384 if (encoder->pre_pll_enable)
4385 encoder->pre_pll_enable(encoder);
4387 /* Enable DPIO clock input */
4388 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4389 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4391 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4393 dpll |= DPLL_VCO_ENABLE;
4394 I915_WRITE(DPLL(pipe), dpll);
4395 POSTING_READ(DPLL(pipe));
4398 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4399 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4402 if (crtc->config.pixel_multiplier > 1) {
4403 dpll_md = (crtc->config.pixel_multiplier - 1)
4404 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4406 I915_WRITE(DPLL_MD(pipe), dpll_md);
4407 POSTING_READ(DPLL_MD(pipe));
4409 if (crtc->config.has_dp_encoder)
4410 intel_dp_set_m_n(crtc);
4412 mutex_unlock(&dev_priv->dpio_lock);
4415 static void i9xx_update_pll(struct intel_crtc *crtc,
4416 intel_clock_t *reduced_clock,
4419 struct drm_device *dev = crtc->base.dev;
4420 struct drm_i915_private *dev_priv = dev->dev_private;
4421 struct intel_encoder *encoder;
4422 int pipe = crtc->pipe;
4425 struct dpll *clock = &crtc->config.dpll;
4427 i9xx_update_pll_dividers(crtc, reduced_clock);
4429 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4430 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4432 dpll = DPLL_VGA_MODE_DIS;
4434 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4435 dpll |= DPLLB_MODE_LVDS;
4437 dpll |= DPLLB_MODE_DAC_SERIAL;
4439 if ((crtc->config.pixel_multiplier > 1) &&
4440 (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
4441 dpll |= (crtc->config.pixel_multiplier - 1)
4442 << SDVO_MULTIPLIER_SHIFT_HIRES;
4446 dpll |= DPLL_DVO_HIGH_SPEED;
4448 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4449 dpll |= DPLL_DVO_HIGH_SPEED;
4451 /* compute bitmask from p1 value */
4452 if (IS_PINEVIEW(dev))
4453 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4455 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4456 if (IS_G4X(dev) && reduced_clock)
4457 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4459 switch (clock->p2) {
4461 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4464 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4467 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4470 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4473 if (INTEL_INFO(dev)->gen >= 4)
4474 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4476 if (is_sdvo && intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
4477 dpll |= PLL_REF_INPUT_TVCLKINBC;
4478 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
4479 /* XXX: just matching BIOS for now */
4480 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4482 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4483 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4484 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4486 dpll |= PLL_REF_INPUT_DREFCLK;
4488 dpll |= DPLL_VCO_ENABLE;
4489 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4490 POSTING_READ(DPLL(pipe));
4493 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4494 if (encoder->pre_pll_enable)
4495 encoder->pre_pll_enable(encoder);
4497 if (crtc->config.has_dp_encoder)
4498 intel_dp_set_m_n(crtc);
4500 I915_WRITE(DPLL(pipe), dpll);
4502 /* Wait for the clocks to stabilize. */
4503 POSTING_READ(DPLL(pipe));
4506 if (INTEL_INFO(dev)->gen >= 4) {
4508 if (crtc->config.pixel_multiplier > 1) {
4509 dpll_md = (crtc->config.pixel_multiplier - 1)
4510 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4512 I915_WRITE(DPLL_MD(pipe), dpll_md);
4514 /* The pixel multiplier can only be updated once the
4515 * DPLL is enabled and the clocks are stable.
4517 * So write it again.
4519 I915_WRITE(DPLL(pipe), dpll);
4523 static void i8xx_update_pll(struct intel_crtc *crtc,
4524 struct drm_display_mode *adjusted_mode,
4525 intel_clock_t *reduced_clock,
4528 struct drm_device *dev = crtc->base.dev;
4529 struct drm_i915_private *dev_priv = dev->dev_private;
4530 struct intel_encoder *encoder;
4531 int pipe = crtc->pipe;
4533 struct dpll *clock = &crtc->config.dpll;
4535 i9xx_update_pll_dividers(crtc, reduced_clock);
4537 dpll = DPLL_VGA_MODE_DIS;
4539 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4540 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4543 dpll |= PLL_P1_DIVIDE_BY_TWO;
4545 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4547 dpll |= PLL_P2_DIVIDE_BY_4;
4550 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4551 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4552 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4554 dpll |= PLL_REF_INPUT_DREFCLK;
4556 dpll |= DPLL_VCO_ENABLE;
4557 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4558 POSTING_READ(DPLL(pipe));
4561 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4562 if (encoder->pre_pll_enable)
4563 encoder->pre_pll_enable(encoder);
4565 I915_WRITE(DPLL(pipe), dpll);
4567 /* Wait for the clocks to stabilize. */
4568 POSTING_READ(DPLL(pipe));
4571 /* The pixel multiplier can only be updated once the
4572 * DPLL is enabled and the clocks are stable.
4574 * So write it again.
4576 I915_WRITE(DPLL(pipe), dpll);
4579 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4580 struct drm_display_mode *mode,
4581 struct drm_display_mode *adjusted_mode)
4583 struct drm_device *dev = intel_crtc->base.dev;
4584 struct drm_i915_private *dev_priv = dev->dev_private;
4585 enum pipe pipe = intel_crtc->pipe;
4586 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4587 uint32_t vsyncshift;
4589 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4590 /* the chip adds 2 halflines automatically */
4591 adjusted_mode->crtc_vtotal -= 1;
4592 adjusted_mode->crtc_vblank_end -= 1;
4593 vsyncshift = adjusted_mode->crtc_hsync_start
4594 - adjusted_mode->crtc_htotal / 2;
4599 if (INTEL_INFO(dev)->gen > 3)
4600 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4602 I915_WRITE(HTOTAL(cpu_transcoder),
4603 (adjusted_mode->crtc_hdisplay - 1) |
4604 ((adjusted_mode->crtc_htotal - 1) << 16));
4605 I915_WRITE(HBLANK(cpu_transcoder),
4606 (adjusted_mode->crtc_hblank_start - 1) |
4607 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4608 I915_WRITE(HSYNC(cpu_transcoder),
4609 (adjusted_mode->crtc_hsync_start - 1) |
4610 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4612 I915_WRITE(VTOTAL(cpu_transcoder),
4613 (adjusted_mode->crtc_vdisplay - 1) |
4614 ((adjusted_mode->crtc_vtotal - 1) << 16));
4615 I915_WRITE(VBLANK(cpu_transcoder),
4616 (adjusted_mode->crtc_vblank_start - 1) |
4617 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4618 I915_WRITE(VSYNC(cpu_transcoder),
4619 (adjusted_mode->crtc_vsync_start - 1) |
4620 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4622 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4623 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4624 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4626 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4627 (pipe == PIPE_B || pipe == PIPE_C))
4628 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4630 /* pipesrc controls the size that is scaled from, which should
4631 * always be the user's requested size.
4633 I915_WRITE(PIPESRC(pipe),
4634 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4637 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4639 struct drm_device *dev = intel_crtc->base.dev;
4640 struct drm_i915_private *dev_priv = dev->dev_private;
4643 pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4645 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4646 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4649 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4652 if (intel_crtc->config.requested_mode.clock >
4653 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4654 pipeconf |= PIPECONF_DOUBLE_WIDE;
4656 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4659 /* only g4x and later have fancy bpc/dither controls */
4660 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4661 pipeconf &= ~(PIPECONF_BPC_MASK |
4662 PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4664 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4665 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4666 pipeconf |= PIPECONF_DITHER_EN |
4667 PIPECONF_DITHER_TYPE_SP;
4669 switch (intel_crtc->config.pipe_bpp) {
4671 pipeconf |= PIPECONF_6BPC;
4674 pipeconf |= PIPECONF_8BPC;
4677 pipeconf |= PIPECONF_10BPC;
4680 /* Case prevented by intel_choose_pipe_bpp_dither. */
4685 if (HAS_PIPE_CXSR(dev)) {
4686 if (intel_crtc->lowfreq_avail) {
4687 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4688 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4690 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4691 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4695 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4696 if (!IS_GEN2(dev) &&
4697 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4698 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4700 pipeconf |= PIPECONF_PROGRESSIVE;
4702 if (IS_VALLEYVIEW(dev)) {
4703 if (intel_crtc->config.limited_color_range)
4704 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4706 pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4709 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4710 POSTING_READ(PIPECONF(intel_crtc->pipe));
4713 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4715 struct drm_framebuffer *fb)
4717 struct drm_device *dev = crtc->dev;
4718 struct drm_i915_private *dev_priv = dev->dev_private;
4719 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4720 struct drm_display_mode *adjusted_mode =
4721 &intel_crtc->config.adjusted_mode;
4722 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4723 int pipe = intel_crtc->pipe;
4724 int plane = intel_crtc->plane;
4725 int refclk, num_connectors = 0;
4726 intel_clock_t clock, reduced_clock;
4728 bool ok, has_reduced_clock = false, is_sdvo = false;
4729 bool is_lvds = false, is_tv = false;
4730 struct intel_encoder *encoder;
4731 const intel_limit_t *limit;
4734 for_each_encoder_on_crtc(dev, crtc, encoder) {
4735 switch (encoder->type) {
4736 case INTEL_OUTPUT_LVDS:
4739 case INTEL_OUTPUT_SDVO:
4740 case INTEL_OUTPUT_HDMI:
4742 if (encoder->needs_tv_clock)
4745 case INTEL_OUTPUT_TVOUT:
4753 refclk = i9xx_get_refclk(crtc, num_connectors);
4756 * Returns a set of divisors for the desired target clock with the given
4757 * refclk, or FALSE. The returned values represent the clock equation:
4758 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4760 limit = intel_limit(crtc, refclk);
4761 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4764 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4768 /* Ensure that the cursor is valid for the new mode before changing... */
4769 intel_crtc_update_cursor(crtc, true);
4771 if (is_lvds && dev_priv->lvds_downclock_avail) {
4773 * Ensure we match the reduced clock's P to the target clock.
4774 * If the clocks don't match, we can't switch the display clock
4775 * by using the FP0/FP1. In such case we will disable the LVDS
4776 * downclock feature.
4778 has_reduced_clock = limit->find_pll(limit, crtc,
4779 dev_priv->lvds_downclock,
4784 /* Compat-code for transition, will disappear. */
4785 if (!intel_crtc->config.clock_set) {
4786 intel_crtc->config.dpll.n = clock.n;
4787 intel_crtc->config.dpll.m1 = clock.m1;
4788 intel_crtc->config.dpll.m2 = clock.m2;
4789 intel_crtc->config.dpll.p1 = clock.p1;
4790 intel_crtc->config.dpll.p2 = clock.p2;
4793 if (is_sdvo && is_tv)
4794 i9xx_adjust_sdvo_tv_clock(intel_crtc);
4797 i8xx_update_pll(intel_crtc, adjusted_mode,
4798 has_reduced_clock ? &reduced_clock : NULL,
4800 else if (IS_VALLEYVIEW(dev))
4801 vlv_update_pll(intel_crtc);
4803 i9xx_update_pll(intel_crtc,
4804 has_reduced_clock ? &reduced_clock : NULL,
4807 /* Set up the display plane register */
4808 dspcntr = DISPPLANE_GAMMA_ENABLE;
4810 if (!IS_VALLEYVIEW(dev)) {
4812 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4814 dspcntr |= DISPPLANE_SEL_PIPE_B;
4817 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
4818 drm_mode_debug_printmodeline(mode);
4820 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4822 /* pipesrc and dspsize control the size that is scaled from,
4823 * which should always be the user's requested size.
4825 I915_WRITE(DSPSIZE(plane),
4826 ((mode->vdisplay - 1) << 16) |
4827 (mode->hdisplay - 1));
4828 I915_WRITE(DSPPOS(plane), 0);
4830 i9xx_set_pipeconf(intel_crtc);
4832 I915_WRITE(DSPCNTR(plane), dspcntr);
4833 POSTING_READ(DSPCNTR(plane));
4835 ret = intel_pipe_set_base(crtc, x, y, fb);
4837 intel_update_watermarks(dev);
4842 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4843 struct intel_crtc_config *pipe_config)
4845 struct drm_device *dev = crtc->base.dev;
4846 struct drm_i915_private *dev_priv = dev->dev_private;
4849 tmp = I915_READ(PIPECONF(crtc->pipe));
4850 if (!(tmp & PIPECONF_ENABLE))
4856 static void ironlake_init_pch_refclk(struct drm_device *dev)
4858 struct drm_i915_private *dev_priv = dev->dev_private;
4859 struct drm_mode_config *mode_config = &dev->mode_config;
4860 struct intel_encoder *encoder;
4862 bool has_lvds = false;
4863 bool has_cpu_edp = false;
4864 bool has_pch_edp = false;
4865 bool has_panel = false;
4866 bool has_ck505 = false;
4867 bool can_ssc = false;
4869 /* We need to take the global config into account */
4870 list_for_each_entry(encoder, &mode_config->encoder_list,
4872 switch (encoder->type) {
4873 case INTEL_OUTPUT_LVDS:
4877 case INTEL_OUTPUT_EDP:
4879 if (intel_encoder_is_pch_edp(&encoder->base))
4887 if (HAS_PCH_IBX(dev)) {
4888 has_ck505 = dev_priv->display_clock_mode;
4889 can_ssc = has_ck505;
4895 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4896 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4899 /* Ironlake: try to setup display ref clock before DPLL
4900 * enabling. This is only under driver's control after
4901 * PCH B stepping, previous chipset stepping should be
4902 * ignoring this setting.
4904 val = I915_READ(PCH_DREF_CONTROL);
4906 /* As we must carefully and slowly disable/enable each source in turn,
4907 * compute the final state we want first and check if we need to
4908 * make any changes at all.
4911 final &= ~DREF_NONSPREAD_SOURCE_MASK;
4913 final |= DREF_NONSPREAD_CK505_ENABLE;
4915 final |= DREF_NONSPREAD_SOURCE_ENABLE;
4917 final &= ~DREF_SSC_SOURCE_MASK;
4918 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4919 final &= ~DREF_SSC1_ENABLE;
4922 final |= DREF_SSC_SOURCE_ENABLE;
4924 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4925 final |= DREF_SSC1_ENABLE;
4928 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4929 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4931 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4933 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4935 final |= DREF_SSC_SOURCE_DISABLE;
4936 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4942 /* Always enable nonspread source */
4943 val &= ~DREF_NONSPREAD_SOURCE_MASK;
4946 val |= DREF_NONSPREAD_CK505_ENABLE;
4948 val |= DREF_NONSPREAD_SOURCE_ENABLE;
4951 val &= ~DREF_SSC_SOURCE_MASK;
4952 val |= DREF_SSC_SOURCE_ENABLE;
4954 /* SSC must be turned on before enabling the CPU output */
4955 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4956 DRM_DEBUG_KMS("Using SSC on panel\n");
4957 val |= DREF_SSC1_ENABLE;
4959 val &= ~DREF_SSC1_ENABLE;
4961 /* Get SSC going before enabling the outputs */
4962 I915_WRITE(PCH_DREF_CONTROL, val);
4963 POSTING_READ(PCH_DREF_CONTROL);
4966 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4968 /* Enable CPU source on CPU attached eDP */
4970 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4971 DRM_DEBUG_KMS("Using SSC on eDP\n");
4972 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4975 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4977 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4979 I915_WRITE(PCH_DREF_CONTROL, val);
4980 POSTING_READ(PCH_DREF_CONTROL);
4983 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4985 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4987 /* Turn off CPU output */
4988 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4990 I915_WRITE(PCH_DREF_CONTROL, val);
4991 POSTING_READ(PCH_DREF_CONTROL);
4994 /* Turn off the SSC source */
4995 val &= ~DREF_SSC_SOURCE_MASK;
4996 val |= DREF_SSC_SOURCE_DISABLE;
4999 val &= ~DREF_SSC1_ENABLE;
5001 I915_WRITE(PCH_DREF_CONTROL, val);
5002 POSTING_READ(PCH_DREF_CONTROL);
5006 BUG_ON(val != final);
5009 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5010 static void lpt_init_pch_refclk(struct drm_device *dev)
5012 struct drm_i915_private *dev_priv = dev->dev_private;
5013 struct drm_mode_config *mode_config = &dev->mode_config;
5014 struct intel_encoder *encoder;
5015 bool has_vga = false;
5016 bool is_sdv = false;
5019 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5020 switch (encoder->type) {
5021 case INTEL_OUTPUT_ANALOG:
5030 mutex_lock(&dev_priv->dpio_lock);
5032 /* XXX: Rip out SDV support once Haswell ships for real. */
5033 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5036 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5037 tmp &= ~SBI_SSCCTL_DISABLE;
5038 tmp |= SBI_SSCCTL_PATHALT;
5039 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5043 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5044 tmp &= ~SBI_SSCCTL_PATHALT;
5045 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5048 tmp = I915_READ(SOUTH_CHICKEN2);
5049 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5050 I915_WRITE(SOUTH_CHICKEN2, tmp);
5052 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5053 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5054 DRM_ERROR("FDI mPHY reset assert timeout\n");
5056 tmp = I915_READ(SOUTH_CHICKEN2);
5057 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5058 I915_WRITE(SOUTH_CHICKEN2, tmp);
5060 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5061 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5063 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5066 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5067 tmp &= ~(0xFF << 24);
5068 tmp |= (0x12 << 24);
5069 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5072 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5074 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5077 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5079 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5081 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5083 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5086 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5087 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5088 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5090 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5091 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5092 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5094 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5096 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5098 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5100 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5103 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5104 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5105 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5107 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5108 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5109 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5112 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5115 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5117 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5120 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5123 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5126 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5128 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5131 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5133 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5134 tmp &= ~(0xFF << 16);
5135 tmp |= (0x1C << 16);
5136 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5138 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5139 tmp &= ~(0xFF << 16);
5140 tmp |= (0x1C << 16);
5141 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5144 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5146 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5148 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5150 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5152 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5153 tmp &= ~(0xF << 28);
5155 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5157 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5158 tmp &= ~(0xF << 28);
5160 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5163 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5164 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5165 tmp |= SBI_DBUFF0_ENABLE;
5166 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5168 mutex_unlock(&dev_priv->dpio_lock);
5172 * Initialize reference clocks when the driver loads
5174 void intel_init_pch_refclk(struct drm_device *dev)
5176 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5177 ironlake_init_pch_refclk(dev);
5178 else if (HAS_PCH_LPT(dev))
5179 lpt_init_pch_refclk(dev);
5182 static int ironlake_get_refclk(struct drm_crtc *crtc)
5184 struct drm_device *dev = crtc->dev;
5185 struct drm_i915_private *dev_priv = dev->dev_private;
5186 struct intel_encoder *encoder;
5187 struct intel_encoder *edp_encoder = NULL;
5188 int num_connectors = 0;
5189 bool is_lvds = false;
5191 for_each_encoder_on_crtc(dev, crtc, encoder) {
5192 switch (encoder->type) {
5193 case INTEL_OUTPUT_LVDS:
5196 case INTEL_OUTPUT_EDP:
5197 edp_encoder = encoder;
5203 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5204 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5205 dev_priv->lvds_ssc_freq);
5206 return dev_priv->lvds_ssc_freq * 1000;
5212 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5214 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5215 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5216 int pipe = intel_crtc->pipe;
5219 val = I915_READ(PIPECONF(pipe));
5221 val &= ~PIPECONF_BPC_MASK;
5222 switch (intel_crtc->config.pipe_bpp) {
5224 val |= PIPECONF_6BPC;
5227 val |= PIPECONF_8BPC;
5230 val |= PIPECONF_10BPC;
5233 val |= PIPECONF_12BPC;
5236 /* Case prevented by intel_choose_pipe_bpp_dither. */
5240 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5241 if (intel_crtc->config.dither)
5242 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5244 val &= ~PIPECONF_INTERLACE_MASK;
5245 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5246 val |= PIPECONF_INTERLACED_ILK;
5248 val |= PIPECONF_PROGRESSIVE;
5250 if (intel_crtc->config.limited_color_range)
5251 val |= PIPECONF_COLOR_RANGE_SELECT;
5253 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5255 I915_WRITE(PIPECONF(pipe), val);
5256 POSTING_READ(PIPECONF(pipe));
5260 * Set up the pipe CSC unit.
5262 * Currently only full range RGB to limited range RGB conversion
5263 * is supported, but eventually this should handle various
5264 * RGB<->YCbCr scenarios as well.
5266 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5268 struct drm_device *dev = crtc->dev;
5269 struct drm_i915_private *dev_priv = dev->dev_private;
5270 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5271 int pipe = intel_crtc->pipe;
5272 uint16_t coeff = 0x7800; /* 1.0 */
5275 * TODO: Check what kind of values actually come out of the pipe
5276 * with these coeff/postoff values and adjust to get the best
5277 * accuracy. Perhaps we even need to take the bpc value into
5281 if (intel_crtc->config.limited_color_range)
5282 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5285 * GY/GU and RY/RU should be the other way around according
5286 * to BSpec, but reality doesn't agree. Just set them up in
5287 * a way that results in the correct picture.
5289 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5290 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5292 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5293 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5295 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5296 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5298 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5299 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5300 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5302 if (INTEL_INFO(dev)->gen > 6) {
5303 uint16_t postoff = 0;
5305 if (intel_crtc->config.limited_color_range)
5306 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5308 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5309 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5310 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5312 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5314 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5316 if (intel_crtc->config.limited_color_range)
5317 mode |= CSC_BLACK_SCREEN_OFFSET;
5319 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5323 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5325 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5326 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5327 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5330 val = I915_READ(PIPECONF(cpu_transcoder));
5332 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5333 if (intel_crtc->config.dither)
5334 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5336 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5337 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5338 val |= PIPECONF_INTERLACED_ILK;
5340 val |= PIPECONF_PROGRESSIVE;
5342 I915_WRITE(PIPECONF(cpu_transcoder), val);
5343 POSTING_READ(PIPECONF(cpu_transcoder));
5346 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5347 struct drm_display_mode *adjusted_mode,
5348 intel_clock_t *clock,
5349 bool *has_reduced_clock,
5350 intel_clock_t *reduced_clock)
5352 struct drm_device *dev = crtc->dev;
5353 struct drm_i915_private *dev_priv = dev->dev_private;
5354 struct intel_encoder *intel_encoder;
5356 const intel_limit_t *limit;
5357 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5359 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5360 switch (intel_encoder->type) {
5361 case INTEL_OUTPUT_LVDS:
5364 case INTEL_OUTPUT_SDVO:
5365 case INTEL_OUTPUT_HDMI:
5367 if (intel_encoder->needs_tv_clock)
5370 case INTEL_OUTPUT_TVOUT:
5376 refclk = ironlake_get_refclk(crtc);
5379 * Returns a set of divisors for the desired target clock with the given
5380 * refclk, or FALSE. The returned values represent the clock equation:
5381 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5383 limit = intel_limit(crtc, refclk);
5384 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5389 if (is_lvds && dev_priv->lvds_downclock_avail) {
5391 * Ensure we match the reduced clock's P to the target clock.
5392 * If the clocks don't match, we can't switch the display clock
5393 * by using the FP0/FP1. In such case we will disable the LVDS
5394 * downclock feature.
5396 *has_reduced_clock = limit->find_pll(limit, crtc,
5397 dev_priv->lvds_downclock,
5403 if (is_sdvo && is_tv)
5404 i9xx_adjust_sdvo_tv_clock(to_intel_crtc(crtc));
5409 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5411 struct drm_i915_private *dev_priv = dev->dev_private;
5414 temp = I915_READ(SOUTH_CHICKEN1);
5415 if (temp & FDI_BC_BIFURCATION_SELECT)
5418 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5419 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5421 temp |= FDI_BC_BIFURCATION_SELECT;
5422 DRM_DEBUG_KMS("enabling fdi C rx\n");
5423 I915_WRITE(SOUTH_CHICKEN1, temp);
5424 POSTING_READ(SOUTH_CHICKEN1);
5427 static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5429 struct drm_device *dev = intel_crtc->base.dev;
5430 struct drm_i915_private *dev_priv = dev->dev_private;
5431 struct intel_crtc *pipe_B_crtc =
5432 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5434 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5435 pipe_name(intel_crtc->pipe), intel_crtc->config.fdi_lanes);
5436 if (intel_crtc->config.fdi_lanes > 4) {
5437 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5438 pipe_name(intel_crtc->pipe), intel_crtc->config.fdi_lanes);
5439 /* Clamp lanes to avoid programming the hw with bogus values. */
5440 intel_crtc->config.fdi_lanes = 4;
5445 if (INTEL_INFO(dev)->num_pipes == 2)
5448 switch (intel_crtc->pipe) {
5452 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5453 intel_crtc->config.fdi_lanes > 2) {
5454 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5455 pipe_name(intel_crtc->pipe), intel_crtc->config.fdi_lanes);
5456 /* Clamp lanes to avoid programming the hw with bogus values. */
5457 intel_crtc->config.fdi_lanes = 2;
5464 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->config.fdi_lanes <= 2) {
5465 if (intel_crtc->config.fdi_lanes > 2) {
5466 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5467 pipe_name(intel_crtc->pipe), intel_crtc->config.fdi_lanes);
5468 /* Clamp lanes to avoid programming the hw with bogus values. */
5469 intel_crtc->config.fdi_lanes = 2;
5474 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5484 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5486 struct drm_device *dev = intel_crtc->base.dev;
5487 struct drm_i915_private *dev_priv = dev->dev_private;
5489 switch (intel_crtc->pipe) {
5493 if (intel_crtc->config.fdi_lanes > 2)
5494 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5496 cpt_enable_fdi_bc_bifurcation(dev);
5500 cpt_enable_fdi_bc_bifurcation(dev);
5508 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5511 * Account for spread spectrum to avoid
5512 * oversubscribing the link. Max center spread
5513 * is 2.5%; use 5% for safety's sake.
5515 u32 bps = target_clock * bpp * 21 / 20;
5516 return bps / (link_bw * 8) + 1;
5519 void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5520 struct intel_link_m_n *m_n)
5522 struct drm_device *dev = crtc->base.dev;
5523 struct drm_i915_private *dev_priv = dev->dev_private;
5524 int pipe = crtc->pipe;
5526 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5527 I915_WRITE(TRANSDATA_N1(pipe), m_n->gmch_n);
5528 I915_WRITE(TRANSDPLINK_M1(pipe), m_n->link_m);
5529 I915_WRITE(TRANSDPLINK_N1(pipe), m_n->link_n);
5532 void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5533 struct intel_link_m_n *m_n)
5535 struct drm_device *dev = crtc->base.dev;
5536 struct drm_i915_private *dev_priv = dev->dev_private;
5537 int pipe = crtc->pipe;
5538 enum transcoder transcoder = crtc->config.cpu_transcoder;
5540 if (INTEL_INFO(dev)->gen >= 5) {
5541 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5542 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5543 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5544 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5546 I915_WRITE(PIPE_GMCH_DATA_M(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5547 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n->gmch_n);
5548 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n->link_m);
5549 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n->link_n);
5553 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5555 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5558 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5560 intel_clock_t *reduced_clock, u32 *fp2)
5562 struct drm_crtc *crtc = &intel_crtc->base;
5563 struct drm_device *dev = crtc->dev;
5564 struct drm_i915_private *dev_priv = dev->dev_private;
5565 struct intel_encoder *intel_encoder;
5567 int factor, num_connectors = 0;
5568 bool is_lvds = false, is_sdvo = false, is_tv = false;
5570 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5571 switch (intel_encoder->type) {
5572 case INTEL_OUTPUT_LVDS:
5575 case INTEL_OUTPUT_SDVO:
5576 case INTEL_OUTPUT_HDMI:
5578 if (intel_encoder->needs_tv_clock)
5581 case INTEL_OUTPUT_TVOUT:
5589 /* Enable autotuning of the PLL clock (if permissible) */
5592 if ((intel_panel_use_ssc(dev_priv) &&
5593 dev_priv->lvds_ssc_freq == 100) ||
5594 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5596 } else if (is_sdvo && is_tv)
5599 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5602 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5608 dpll |= DPLLB_MODE_LVDS;
5610 dpll |= DPLLB_MODE_DAC_SERIAL;
5612 if (intel_crtc->config.pixel_multiplier > 1) {
5613 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5614 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5618 dpll |= DPLL_DVO_HIGH_SPEED;
5619 if (intel_crtc->config.has_dp_encoder)
5620 dpll |= DPLL_DVO_HIGH_SPEED;
5622 /* compute bitmask from p1 value */
5623 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5625 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5627 switch (intel_crtc->config.dpll.p2) {
5629 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5632 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5635 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5638 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5642 if (is_sdvo && is_tv)
5643 dpll |= PLL_REF_INPUT_TVCLKINBC;
5645 /* XXX: just matching BIOS for now */
5646 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5648 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5649 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5651 dpll |= PLL_REF_INPUT_DREFCLK;
5656 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5658 struct drm_framebuffer *fb)
5660 struct drm_device *dev = crtc->dev;
5661 struct drm_i915_private *dev_priv = dev->dev_private;
5662 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5663 struct drm_display_mode *adjusted_mode =
5664 &intel_crtc->config.adjusted_mode;
5665 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5666 int pipe = intel_crtc->pipe;
5667 int plane = intel_crtc->plane;
5668 int num_connectors = 0;
5669 intel_clock_t clock, reduced_clock;
5670 u32 dpll = 0, fp = 0, fp2 = 0;
5671 bool ok, has_reduced_clock = false;
5672 bool is_lvds = false;
5673 struct intel_encoder *encoder;
5677 for_each_encoder_on_crtc(dev, crtc, encoder) {
5678 switch (encoder->type) {
5679 case INTEL_OUTPUT_LVDS:
5687 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5688 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5690 intel_crtc->config.cpu_transcoder = pipe;
5692 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5693 &has_reduced_clock, &reduced_clock);
5695 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5698 /* Compat-code for transition, will disappear. */
5699 if (!intel_crtc->config.clock_set) {
5700 intel_crtc->config.dpll.n = clock.n;
5701 intel_crtc->config.dpll.m1 = clock.m1;
5702 intel_crtc->config.dpll.m2 = clock.m2;
5703 intel_crtc->config.dpll.p1 = clock.p1;
5704 intel_crtc->config.dpll.p2 = clock.p2;
5707 /* Ensure that the cursor is valid for the new mode before changing... */
5708 intel_crtc_update_cursor(crtc, true);
5710 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
5711 drm_mode_debug_printmodeline(mode);
5713 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5714 if (intel_crtc->config.has_pch_encoder) {
5715 struct intel_pch_pll *pll;
5717 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5718 if (has_reduced_clock)
5719 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5721 dpll = ironlake_compute_dpll(intel_crtc,
5722 &fp, &reduced_clock,
5723 has_reduced_clock ? &fp2 : NULL);
5725 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5727 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5732 intel_put_pch_pll(intel_crtc);
5734 if (intel_crtc->config.has_dp_encoder)
5735 intel_dp_set_m_n(intel_crtc);
5737 for_each_encoder_on_crtc(dev, crtc, encoder)
5738 if (encoder->pre_pll_enable)
5739 encoder->pre_pll_enable(encoder);
5741 if (intel_crtc->pch_pll) {
5742 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5744 /* Wait for the clocks to stabilize. */
5745 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5748 /* The pixel multiplier can only be updated once the
5749 * DPLL is enabled and the clocks are stable.
5751 * So write it again.
5753 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5756 intel_crtc->lowfreq_avail = false;
5757 if (intel_crtc->pch_pll) {
5758 if (is_lvds && has_reduced_clock && i915_powersave) {
5759 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5760 intel_crtc->lowfreq_avail = true;
5762 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5766 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5768 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5769 * ironlake_check_fdi_lanes. */
5770 if (intel_crtc->config.has_pch_encoder) {
5771 intel_cpu_transcoder_set_m_n(intel_crtc,
5772 &intel_crtc->config.fdi_m_n);
5775 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5776 if (IS_IVYBRIDGE(dev))
5777 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5779 ironlake_set_pipeconf(crtc);
5781 /* Set up the display plane register */
5782 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5783 POSTING_READ(DSPCNTR(plane));
5785 ret = intel_pipe_set_base(crtc, x, y, fb);
5787 intel_update_watermarks(dev);
5789 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5791 return fdi_config_ok ? ret : -EINVAL;
5794 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5795 struct intel_crtc_config *pipe_config)
5797 struct drm_device *dev = crtc->base.dev;
5798 struct drm_i915_private *dev_priv = dev->dev_private;
5801 tmp = I915_READ(PIPECONF(crtc->pipe));
5802 if (!(tmp & PIPECONF_ENABLE))
5805 if (I915_READ(TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5806 pipe_config->has_pch_encoder = true;
5808 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5809 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5810 FDI_DP_PORT_WIDTH_SHIFT) + 1;
5816 static void haswell_modeset_global_resources(struct drm_device *dev)
5818 struct drm_i915_private *dev_priv = dev->dev_private;
5819 bool enable = false;
5820 struct intel_crtc *crtc;
5821 struct intel_encoder *encoder;
5823 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5824 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5826 /* XXX: Should check for edp transcoder here, but thanks to init
5827 * sequence that's not yet available. Just in case desktop eDP
5828 * on PORT D is possible on haswell, too. */
5829 /* Even the eDP panel fitter is outside the always-on well. */
5830 if (I915_READ(PF_WIN_SZ(crtc->pipe)))
5834 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5836 if (encoder->type != INTEL_OUTPUT_EDP &&
5837 encoder->connectors_active)
5841 intel_set_power_well(dev, enable);
5844 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5846 struct drm_framebuffer *fb)
5848 struct drm_device *dev = crtc->dev;
5849 struct drm_i915_private *dev_priv = dev->dev_private;
5850 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5851 struct drm_display_mode *adjusted_mode =
5852 &intel_crtc->config.adjusted_mode;
5853 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5854 int pipe = intel_crtc->pipe;
5855 int plane = intel_crtc->plane;
5856 int num_connectors = 0;
5857 bool is_cpu_edp = false;
5858 struct intel_encoder *encoder;
5861 for_each_encoder_on_crtc(dev, crtc, encoder) {
5862 switch (encoder->type) {
5863 case INTEL_OUTPUT_EDP:
5864 if (!intel_encoder_is_pch_edp(&encoder->base))
5873 intel_crtc->config.cpu_transcoder = TRANSCODER_EDP;
5875 intel_crtc->config.cpu_transcoder = pipe;
5877 /* We are not sure yet this won't happen. */
5878 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5879 INTEL_PCH_TYPE(dev));
5881 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5882 num_connectors, pipe_name(pipe));
5884 WARN_ON(I915_READ(PIPECONF(intel_crtc->config.cpu_transcoder)) &
5885 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5887 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5889 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5892 /* Ensure that the cursor is valid for the new mode before changing... */
5893 intel_crtc_update_cursor(crtc, true);
5895 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
5896 drm_mode_debug_printmodeline(mode);
5898 if (intel_crtc->config.has_dp_encoder)
5899 intel_dp_set_m_n(intel_crtc);
5901 intel_crtc->lowfreq_avail = false;
5903 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5905 if (intel_crtc->config.has_pch_encoder) {
5906 intel_cpu_transcoder_set_m_n(intel_crtc,
5907 &intel_crtc->config.fdi_m_n);
5910 haswell_set_pipeconf(crtc);
5912 intel_set_pipe_csc(crtc);
5914 /* Set up the display plane register */
5915 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
5916 POSTING_READ(DSPCNTR(plane));
5918 ret = intel_pipe_set_base(crtc, x, y, fb);
5920 intel_update_watermarks(dev);
5922 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5927 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5928 struct intel_crtc_config *pipe_config)
5930 struct drm_device *dev = crtc->base.dev;
5931 struct drm_i915_private *dev_priv = dev->dev_private;
5932 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
5935 if (!intel_using_power_well(dev_priv->dev) &&
5936 cpu_transcoder != TRANSCODER_EDP)
5939 tmp = I915_READ(PIPECONF(cpu_transcoder));
5940 if (!(tmp & PIPECONF_ENABLE))
5944 * Haswell has only FDI/PCH transcoder A. It is which is connected to
5945 * DDI E. So just check whether this pipe is wired to DDI E and whether
5946 * the PCH transcoder is on.
5948 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
5949 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
5950 I915_READ(TRANSCONF(PIPE_A)) & TRANS_ENABLE) {
5951 pipe_config->has_pch_encoder = true;
5953 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
5954 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5955 FDI_DP_PORT_WIDTH_SHIFT) + 1;
5961 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5963 struct drm_framebuffer *fb)
5965 struct drm_device *dev = crtc->dev;
5966 struct drm_i915_private *dev_priv = dev->dev_private;
5967 struct drm_encoder_helper_funcs *encoder_funcs;
5968 struct intel_encoder *encoder;
5969 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5970 struct drm_display_mode *adjusted_mode =
5971 &intel_crtc->config.adjusted_mode;
5972 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5973 int pipe = intel_crtc->pipe;
5976 drm_vblank_pre_modeset(dev, pipe);
5978 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
5980 drm_vblank_post_modeset(dev, pipe);
5985 for_each_encoder_on_crtc(dev, crtc, encoder) {
5986 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5987 encoder->base.base.id,
5988 drm_get_encoder_name(&encoder->base),
5989 mode->base.id, mode->name);
5990 if (encoder->mode_set) {
5991 encoder->mode_set(encoder);
5993 encoder_funcs = encoder->base.helper_private;
5994 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6001 static bool intel_eld_uptodate(struct drm_connector *connector,
6002 int reg_eldv, uint32_t bits_eldv,
6003 int reg_elda, uint32_t bits_elda,
6006 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6007 uint8_t *eld = connector->eld;
6010 i = I915_READ(reg_eldv);
6019 i = I915_READ(reg_elda);
6021 I915_WRITE(reg_elda, i);
6023 for (i = 0; i < eld[2]; i++)
6024 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6030 static void g4x_write_eld(struct drm_connector *connector,
6031 struct drm_crtc *crtc)
6033 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6034 uint8_t *eld = connector->eld;
6039 i = I915_READ(G4X_AUD_VID_DID);
6041 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6042 eldv = G4X_ELDV_DEVCL_DEVBLC;
6044 eldv = G4X_ELDV_DEVCTG;
6046 if (intel_eld_uptodate(connector,
6047 G4X_AUD_CNTL_ST, eldv,
6048 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6049 G4X_HDMIW_HDMIEDID))
6052 i = I915_READ(G4X_AUD_CNTL_ST);
6053 i &= ~(eldv | G4X_ELD_ADDR);
6054 len = (i >> 9) & 0x1f; /* ELD buffer size */
6055 I915_WRITE(G4X_AUD_CNTL_ST, i);
6060 len = min_t(uint8_t, eld[2], len);
6061 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6062 for (i = 0; i < len; i++)
6063 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6065 i = I915_READ(G4X_AUD_CNTL_ST);
6067 I915_WRITE(G4X_AUD_CNTL_ST, i);
6070 static void haswell_write_eld(struct drm_connector *connector,
6071 struct drm_crtc *crtc)
6073 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6074 uint8_t *eld = connector->eld;
6075 struct drm_device *dev = crtc->dev;
6076 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6080 int pipe = to_intel_crtc(crtc)->pipe;
6083 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6084 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6085 int aud_config = HSW_AUD_CFG(pipe);
6086 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6089 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6091 /* Audio output enable */
6092 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6093 tmp = I915_READ(aud_cntrl_st2);
6094 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6095 I915_WRITE(aud_cntrl_st2, tmp);
6097 /* Wait for 1 vertical blank */
6098 intel_wait_for_vblank(dev, pipe);
6100 /* Set ELD valid state */
6101 tmp = I915_READ(aud_cntrl_st2);
6102 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6103 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6104 I915_WRITE(aud_cntrl_st2, tmp);
6105 tmp = I915_READ(aud_cntrl_st2);
6106 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6108 /* Enable HDMI mode */
6109 tmp = I915_READ(aud_config);
6110 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6111 /* clear N_programing_enable and N_value_index */
6112 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6113 I915_WRITE(aud_config, tmp);
6115 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6117 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6118 intel_crtc->eld_vld = true;
6120 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6121 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6122 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6123 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6125 I915_WRITE(aud_config, 0);
6127 if (intel_eld_uptodate(connector,
6128 aud_cntrl_st2, eldv,
6129 aud_cntl_st, IBX_ELD_ADDRESS,
6133 i = I915_READ(aud_cntrl_st2);
6135 I915_WRITE(aud_cntrl_st2, i);
6140 i = I915_READ(aud_cntl_st);
6141 i &= ~IBX_ELD_ADDRESS;
6142 I915_WRITE(aud_cntl_st, i);
6143 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6144 DRM_DEBUG_DRIVER("port num:%d\n", i);
6146 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6147 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6148 for (i = 0; i < len; i++)
6149 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6151 i = I915_READ(aud_cntrl_st2);
6153 I915_WRITE(aud_cntrl_st2, i);
6157 static void ironlake_write_eld(struct drm_connector *connector,
6158 struct drm_crtc *crtc)
6160 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6161 uint8_t *eld = connector->eld;
6169 int pipe = to_intel_crtc(crtc)->pipe;
6171 if (HAS_PCH_IBX(connector->dev)) {
6172 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6173 aud_config = IBX_AUD_CFG(pipe);
6174 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6175 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6177 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6178 aud_config = CPT_AUD_CFG(pipe);
6179 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6180 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6183 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6185 i = I915_READ(aud_cntl_st);
6186 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6188 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6189 /* operate blindly on all ports */
6190 eldv = IBX_ELD_VALIDB;
6191 eldv |= IBX_ELD_VALIDB << 4;
6192 eldv |= IBX_ELD_VALIDB << 8;
6194 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6195 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6198 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6199 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6200 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6201 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6203 I915_WRITE(aud_config, 0);
6205 if (intel_eld_uptodate(connector,
6206 aud_cntrl_st2, eldv,
6207 aud_cntl_st, IBX_ELD_ADDRESS,
6211 i = I915_READ(aud_cntrl_st2);
6213 I915_WRITE(aud_cntrl_st2, i);
6218 i = I915_READ(aud_cntl_st);
6219 i &= ~IBX_ELD_ADDRESS;
6220 I915_WRITE(aud_cntl_st, i);
6222 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6223 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6224 for (i = 0; i < len; i++)
6225 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6227 i = I915_READ(aud_cntrl_st2);
6229 I915_WRITE(aud_cntrl_st2, i);
6232 void intel_write_eld(struct drm_encoder *encoder,
6233 struct drm_display_mode *mode)
6235 struct drm_crtc *crtc = encoder->crtc;
6236 struct drm_connector *connector;
6237 struct drm_device *dev = encoder->dev;
6238 struct drm_i915_private *dev_priv = dev->dev_private;
6240 connector = drm_select_eld(encoder, mode);
6244 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6246 drm_get_connector_name(connector),
6247 connector->encoder->base.id,
6248 drm_get_encoder_name(connector->encoder));
6250 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6252 if (dev_priv->display.write_eld)
6253 dev_priv->display.write_eld(connector, crtc);
6256 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6257 void intel_crtc_load_lut(struct drm_crtc *crtc)
6259 struct drm_device *dev = crtc->dev;
6260 struct drm_i915_private *dev_priv = dev->dev_private;
6261 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6262 int palreg = PALETTE(intel_crtc->pipe);
6265 /* The clocks have to be on to load the palette. */
6266 if (!crtc->enabled || !intel_crtc->active)
6269 /* use legacy palette for Ironlake */
6270 if (HAS_PCH_SPLIT(dev))
6271 palreg = LGC_PALETTE(intel_crtc->pipe);
6273 for (i = 0; i < 256; i++) {
6274 I915_WRITE(palreg + 4 * i,
6275 (intel_crtc->lut_r[i] << 16) |
6276 (intel_crtc->lut_g[i] << 8) |
6277 intel_crtc->lut_b[i]);
6281 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6283 struct drm_device *dev = crtc->dev;
6284 struct drm_i915_private *dev_priv = dev->dev_private;
6285 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6286 bool visible = base != 0;
6289 if (intel_crtc->cursor_visible == visible)
6292 cntl = I915_READ(_CURACNTR);
6294 /* On these chipsets we can only modify the base whilst
6295 * the cursor is disabled.
6297 I915_WRITE(_CURABASE, base);
6299 cntl &= ~(CURSOR_FORMAT_MASK);
6300 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6301 cntl |= CURSOR_ENABLE |
6302 CURSOR_GAMMA_ENABLE |
6305 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6306 I915_WRITE(_CURACNTR, cntl);
6308 intel_crtc->cursor_visible = visible;
6311 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6313 struct drm_device *dev = crtc->dev;
6314 struct drm_i915_private *dev_priv = dev->dev_private;
6315 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6316 int pipe = intel_crtc->pipe;
6317 bool visible = base != 0;
6319 if (intel_crtc->cursor_visible != visible) {
6320 uint32_t cntl = I915_READ(CURCNTR(pipe));
6322 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6323 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6324 cntl |= pipe << 28; /* Connect to correct pipe */
6326 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6327 cntl |= CURSOR_MODE_DISABLE;
6329 I915_WRITE(CURCNTR(pipe), cntl);
6331 intel_crtc->cursor_visible = visible;
6333 /* and commit changes on next vblank */
6334 I915_WRITE(CURBASE(pipe), base);
6337 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6339 struct drm_device *dev = crtc->dev;
6340 struct drm_i915_private *dev_priv = dev->dev_private;
6341 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6342 int pipe = intel_crtc->pipe;
6343 bool visible = base != 0;
6345 if (intel_crtc->cursor_visible != visible) {
6346 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6348 cntl &= ~CURSOR_MODE;
6349 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6351 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6352 cntl |= CURSOR_MODE_DISABLE;
6354 if (IS_HASWELL(dev))
6355 cntl |= CURSOR_PIPE_CSC_ENABLE;
6356 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6358 intel_crtc->cursor_visible = visible;
6360 /* and commit changes on next vblank */
6361 I915_WRITE(CURBASE_IVB(pipe), base);
6364 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6365 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6368 struct drm_device *dev = crtc->dev;
6369 struct drm_i915_private *dev_priv = dev->dev_private;
6370 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6371 int pipe = intel_crtc->pipe;
6372 int x = intel_crtc->cursor_x;
6373 int y = intel_crtc->cursor_y;
6379 if (on && crtc->enabled && crtc->fb) {
6380 base = intel_crtc->cursor_addr;
6381 if (x > (int) crtc->fb->width)
6384 if (y > (int) crtc->fb->height)
6390 if (x + intel_crtc->cursor_width < 0)
6393 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6396 pos |= x << CURSOR_X_SHIFT;
6399 if (y + intel_crtc->cursor_height < 0)
6402 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6405 pos |= y << CURSOR_Y_SHIFT;
6407 visible = base != 0;
6408 if (!visible && !intel_crtc->cursor_visible)
6411 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6412 I915_WRITE(CURPOS_IVB(pipe), pos);
6413 ivb_update_cursor(crtc, base);
6415 I915_WRITE(CURPOS(pipe), pos);
6416 if (IS_845G(dev) || IS_I865G(dev))
6417 i845_update_cursor(crtc, base);
6419 i9xx_update_cursor(crtc, base);
6423 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6424 struct drm_file *file,
6426 uint32_t width, uint32_t height)
6428 struct drm_device *dev = crtc->dev;
6429 struct drm_i915_private *dev_priv = dev->dev_private;
6430 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6431 struct drm_i915_gem_object *obj;
6435 /* if we want to turn off the cursor ignore width and height */
6437 DRM_DEBUG_KMS("cursor off\n");
6440 mutex_lock(&dev->struct_mutex);
6444 /* Currently we only support 64x64 cursors */
6445 if (width != 64 || height != 64) {
6446 DRM_ERROR("we currently only support 64x64 cursors\n");
6450 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6451 if (&obj->base == NULL)
6454 if (obj->base.size < width * height * 4) {
6455 DRM_ERROR("buffer is to small\n");
6460 /* we only need to pin inside GTT if cursor is non-phy */
6461 mutex_lock(&dev->struct_mutex);
6462 if (!dev_priv->info->cursor_needs_physical) {
6465 if (obj->tiling_mode) {
6466 DRM_ERROR("cursor cannot be tiled\n");
6471 /* Note that the w/a also requires 2 PTE of padding following
6472 * the bo. We currently fill all unused PTE with the shadow
6473 * page and so we should always have valid PTE following the
6474 * cursor preventing the VT-d warning.
6477 if (need_vtd_wa(dev))
6478 alignment = 64*1024;
6480 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6482 DRM_ERROR("failed to move cursor bo into the GTT\n");
6486 ret = i915_gem_object_put_fence(obj);
6488 DRM_ERROR("failed to release fence for cursor");
6492 addr = obj->gtt_offset;
6494 int align = IS_I830(dev) ? 16 * 1024 : 256;
6495 ret = i915_gem_attach_phys_object(dev, obj,
6496 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6499 DRM_ERROR("failed to attach phys object\n");
6502 addr = obj->phys_obj->handle->busaddr;
6506 I915_WRITE(CURSIZE, (height << 12) | width);
6509 if (intel_crtc->cursor_bo) {
6510 if (dev_priv->info->cursor_needs_physical) {
6511 if (intel_crtc->cursor_bo != obj)
6512 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6514 i915_gem_object_unpin(intel_crtc->cursor_bo);
6515 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6518 mutex_unlock(&dev->struct_mutex);
6520 intel_crtc->cursor_addr = addr;
6521 intel_crtc->cursor_bo = obj;
6522 intel_crtc->cursor_width = width;
6523 intel_crtc->cursor_height = height;
6525 intel_crtc_update_cursor(crtc, true);
6529 i915_gem_object_unpin(obj);
6531 mutex_unlock(&dev->struct_mutex);
6533 drm_gem_object_unreference_unlocked(&obj->base);
6537 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6539 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6541 intel_crtc->cursor_x = x;
6542 intel_crtc->cursor_y = y;
6544 intel_crtc_update_cursor(crtc, true);
6549 /** Sets the color ramps on behalf of RandR */
6550 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6551 u16 blue, int regno)
6553 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6555 intel_crtc->lut_r[regno] = red >> 8;
6556 intel_crtc->lut_g[regno] = green >> 8;
6557 intel_crtc->lut_b[regno] = blue >> 8;
6560 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6561 u16 *blue, int regno)
6563 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6565 *red = intel_crtc->lut_r[regno] << 8;
6566 *green = intel_crtc->lut_g[regno] << 8;
6567 *blue = intel_crtc->lut_b[regno] << 8;
6570 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6571 u16 *blue, uint32_t start, uint32_t size)
6573 int end = (start + size > 256) ? 256 : start + size, i;
6574 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6576 for (i = start; i < end; i++) {
6577 intel_crtc->lut_r[i] = red[i] >> 8;
6578 intel_crtc->lut_g[i] = green[i] >> 8;
6579 intel_crtc->lut_b[i] = blue[i] >> 8;
6582 intel_crtc_load_lut(crtc);
6585 /* VESA 640x480x72Hz mode to set on the pipe */
6586 static struct drm_display_mode load_detect_mode = {
6587 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6588 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6591 static struct drm_framebuffer *
6592 intel_framebuffer_create(struct drm_device *dev,
6593 struct drm_mode_fb_cmd2 *mode_cmd,
6594 struct drm_i915_gem_object *obj)
6596 struct intel_framebuffer *intel_fb;
6599 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6601 drm_gem_object_unreference_unlocked(&obj->base);
6602 return ERR_PTR(-ENOMEM);
6605 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6607 drm_gem_object_unreference_unlocked(&obj->base);
6609 return ERR_PTR(ret);
6612 return &intel_fb->base;
6616 intel_framebuffer_pitch_for_width(int width, int bpp)
6618 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6619 return ALIGN(pitch, 64);
6623 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6625 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6626 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6629 static struct drm_framebuffer *
6630 intel_framebuffer_create_for_mode(struct drm_device *dev,
6631 struct drm_display_mode *mode,
6634 struct drm_i915_gem_object *obj;
6635 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6637 obj = i915_gem_alloc_object(dev,
6638 intel_framebuffer_size_for_mode(mode, bpp));
6640 return ERR_PTR(-ENOMEM);
6642 mode_cmd.width = mode->hdisplay;
6643 mode_cmd.height = mode->vdisplay;
6644 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6646 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6648 return intel_framebuffer_create(dev, &mode_cmd, obj);
6651 static struct drm_framebuffer *
6652 mode_fits_in_fbdev(struct drm_device *dev,
6653 struct drm_display_mode *mode)
6655 struct drm_i915_private *dev_priv = dev->dev_private;
6656 struct drm_i915_gem_object *obj;
6657 struct drm_framebuffer *fb;
6659 if (dev_priv->fbdev == NULL)
6662 obj = dev_priv->fbdev->ifb.obj;
6666 fb = &dev_priv->fbdev->ifb.base;
6667 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6668 fb->bits_per_pixel))
6671 if (obj->base.size < mode->vdisplay * fb->pitches[0])
6677 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6678 struct drm_display_mode *mode,
6679 struct intel_load_detect_pipe *old)
6681 struct intel_crtc *intel_crtc;
6682 struct intel_encoder *intel_encoder =
6683 intel_attached_encoder(connector);
6684 struct drm_crtc *possible_crtc;
6685 struct drm_encoder *encoder = &intel_encoder->base;
6686 struct drm_crtc *crtc = NULL;
6687 struct drm_device *dev = encoder->dev;
6688 struct drm_framebuffer *fb;
6691 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6692 connector->base.id, drm_get_connector_name(connector),
6693 encoder->base.id, drm_get_encoder_name(encoder));
6696 * Algorithm gets a little messy:
6698 * - if the connector already has an assigned crtc, use it (but make
6699 * sure it's on first)
6701 * - try to find the first unused crtc that can drive this connector,
6702 * and use that if we find one
6705 /* See if we already have a CRTC for this connector */
6706 if (encoder->crtc) {
6707 crtc = encoder->crtc;
6709 mutex_lock(&crtc->mutex);
6711 old->dpms_mode = connector->dpms;
6712 old->load_detect_temp = false;
6714 /* Make sure the crtc and connector are running */
6715 if (connector->dpms != DRM_MODE_DPMS_ON)
6716 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6721 /* Find an unused one (if possible) */
6722 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6724 if (!(encoder->possible_crtcs & (1 << i)))
6726 if (!possible_crtc->enabled) {
6727 crtc = possible_crtc;
6733 * If we didn't find an unused CRTC, don't use any.
6736 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6740 mutex_lock(&crtc->mutex);
6741 intel_encoder->new_crtc = to_intel_crtc(crtc);
6742 to_intel_connector(connector)->new_encoder = intel_encoder;
6744 intel_crtc = to_intel_crtc(crtc);
6745 old->dpms_mode = connector->dpms;
6746 old->load_detect_temp = true;
6747 old->release_fb = NULL;
6750 mode = &load_detect_mode;
6752 /* We need a framebuffer large enough to accommodate all accesses
6753 * that the plane may generate whilst we perform load detection.
6754 * We can not rely on the fbcon either being present (we get called
6755 * during its initialisation to detect all boot displays, or it may
6756 * not even exist) or that it is large enough to satisfy the
6759 fb = mode_fits_in_fbdev(dev, mode);
6761 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6762 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6763 old->release_fb = fb;
6765 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6767 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6768 mutex_unlock(&crtc->mutex);
6772 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6773 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6774 if (old->release_fb)
6775 old->release_fb->funcs->destroy(old->release_fb);
6776 mutex_unlock(&crtc->mutex);
6780 /* let the connector get through one full cycle before testing */
6781 intel_wait_for_vblank(dev, intel_crtc->pipe);
6785 void intel_release_load_detect_pipe(struct drm_connector *connector,
6786 struct intel_load_detect_pipe *old)
6788 struct intel_encoder *intel_encoder =
6789 intel_attached_encoder(connector);
6790 struct drm_encoder *encoder = &intel_encoder->base;
6791 struct drm_crtc *crtc = encoder->crtc;
6793 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6794 connector->base.id, drm_get_connector_name(connector),
6795 encoder->base.id, drm_get_encoder_name(encoder));
6797 if (old->load_detect_temp) {
6798 to_intel_connector(connector)->new_encoder = NULL;
6799 intel_encoder->new_crtc = NULL;
6800 intel_set_mode(crtc, NULL, 0, 0, NULL);
6802 if (old->release_fb) {
6803 drm_framebuffer_unregister_private(old->release_fb);
6804 drm_framebuffer_unreference(old->release_fb);
6807 mutex_unlock(&crtc->mutex);
6811 /* Switch crtc and encoder back off if necessary */
6812 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6813 connector->funcs->dpms(connector, old->dpms_mode);
6815 mutex_unlock(&crtc->mutex);
6818 /* Returns the clock of the currently programmed mode of the given pipe. */
6819 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6821 struct drm_i915_private *dev_priv = dev->dev_private;
6822 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6823 int pipe = intel_crtc->pipe;
6824 u32 dpll = I915_READ(DPLL(pipe));
6826 intel_clock_t clock;
6828 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6829 fp = I915_READ(FP0(pipe));
6831 fp = I915_READ(FP1(pipe));
6833 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6834 if (IS_PINEVIEW(dev)) {
6835 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6836 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6838 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6839 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6842 if (!IS_GEN2(dev)) {
6843 if (IS_PINEVIEW(dev))
6844 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6845 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6847 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6848 DPLL_FPA01_P1_POST_DIV_SHIFT);
6850 switch (dpll & DPLL_MODE_MASK) {
6851 case DPLLB_MODE_DAC_SERIAL:
6852 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6855 case DPLLB_MODE_LVDS:
6856 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6860 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6861 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6865 /* XXX: Handle the 100Mhz refclk */
6866 intel_clock(dev, 96000, &clock);
6868 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6871 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6872 DPLL_FPA01_P1_POST_DIV_SHIFT);
6875 if ((dpll & PLL_REF_INPUT_MASK) ==
6876 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6877 /* XXX: might not be 66MHz */
6878 intel_clock(dev, 66000, &clock);
6880 intel_clock(dev, 48000, &clock);
6882 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6885 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6886 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6888 if (dpll & PLL_P2_DIVIDE_BY_4)
6893 intel_clock(dev, 48000, &clock);
6897 /* XXX: It would be nice to validate the clocks, but we can't reuse
6898 * i830PllIsValid() because it relies on the xf86_config connector
6899 * configuration being accurate, which it isn't necessarily.
6905 /** Returns the currently programmed mode of the given pipe. */
6906 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6907 struct drm_crtc *crtc)
6909 struct drm_i915_private *dev_priv = dev->dev_private;
6910 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6911 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6912 struct drm_display_mode *mode;
6913 int htot = I915_READ(HTOTAL(cpu_transcoder));
6914 int hsync = I915_READ(HSYNC(cpu_transcoder));
6915 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6916 int vsync = I915_READ(VSYNC(cpu_transcoder));
6918 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6922 mode->clock = intel_crtc_clock_get(dev, crtc);
6923 mode->hdisplay = (htot & 0xffff) + 1;
6924 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6925 mode->hsync_start = (hsync & 0xffff) + 1;
6926 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6927 mode->vdisplay = (vtot & 0xffff) + 1;
6928 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6929 mode->vsync_start = (vsync & 0xffff) + 1;
6930 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6932 drm_mode_set_name(mode);
6937 static void intel_increase_pllclock(struct drm_crtc *crtc)
6939 struct drm_device *dev = crtc->dev;
6940 drm_i915_private_t *dev_priv = dev->dev_private;
6941 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6942 int pipe = intel_crtc->pipe;
6943 int dpll_reg = DPLL(pipe);
6946 if (HAS_PCH_SPLIT(dev))
6949 if (!dev_priv->lvds_downclock_avail)
6952 dpll = I915_READ(dpll_reg);
6953 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6954 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6956 assert_panel_unlocked(dev_priv, pipe);
6958 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6959 I915_WRITE(dpll_reg, dpll);
6960 intel_wait_for_vblank(dev, pipe);
6962 dpll = I915_READ(dpll_reg);
6963 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6964 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6968 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6970 struct drm_device *dev = crtc->dev;
6971 drm_i915_private_t *dev_priv = dev->dev_private;
6972 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6974 if (HAS_PCH_SPLIT(dev))
6977 if (!dev_priv->lvds_downclock_avail)
6981 * Since this is called by a timer, we should never get here in
6984 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6985 int pipe = intel_crtc->pipe;
6986 int dpll_reg = DPLL(pipe);
6989 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6991 assert_panel_unlocked(dev_priv, pipe);
6993 dpll = I915_READ(dpll_reg);
6994 dpll |= DISPLAY_RATE_SELECT_FPA1;
6995 I915_WRITE(dpll_reg, dpll);
6996 intel_wait_for_vblank(dev, pipe);
6997 dpll = I915_READ(dpll_reg);
6998 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6999 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7004 void intel_mark_busy(struct drm_device *dev)
7006 i915_update_gfx_val(dev->dev_private);
7009 void intel_mark_idle(struct drm_device *dev)
7011 struct drm_crtc *crtc;
7013 if (!i915_powersave)
7016 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7020 intel_decrease_pllclock(crtc);
7024 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
7026 struct drm_device *dev = obj->base.dev;
7027 struct drm_crtc *crtc;
7029 if (!i915_powersave)
7032 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7036 if (to_intel_framebuffer(crtc->fb)->obj == obj)
7037 intel_increase_pllclock(crtc);
7041 static void intel_crtc_destroy(struct drm_crtc *crtc)
7043 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7044 struct drm_device *dev = crtc->dev;
7045 struct intel_unpin_work *work;
7046 unsigned long flags;
7048 spin_lock_irqsave(&dev->event_lock, flags);
7049 work = intel_crtc->unpin_work;
7050 intel_crtc->unpin_work = NULL;
7051 spin_unlock_irqrestore(&dev->event_lock, flags);
7054 cancel_work_sync(&work->work);
7058 drm_crtc_cleanup(crtc);
7063 static void intel_unpin_work_fn(struct work_struct *__work)
7065 struct intel_unpin_work *work =
7066 container_of(__work, struct intel_unpin_work, work);
7067 struct drm_device *dev = work->crtc->dev;
7069 mutex_lock(&dev->struct_mutex);
7070 intel_unpin_fb_obj(work->old_fb_obj);
7071 drm_gem_object_unreference(&work->pending_flip_obj->base);
7072 drm_gem_object_unreference(&work->old_fb_obj->base);
7074 intel_update_fbc(dev);
7075 mutex_unlock(&dev->struct_mutex);
7077 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7078 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7083 static void do_intel_finish_page_flip(struct drm_device *dev,
7084 struct drm_crtc *crtc)
7086 drm_i915_private_t *dev_priv = dev->dev_private;
7087 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7088 struct intel_unpin_work *work;
7089 unsigned long flags;
7091 /* Ignore early vblank irqs */
7092 if (intel_crtc == NULL)
7095 spin_lock_irqsave(&dev->event_lock, flags);
7096 work = intel_crtc->unpin_work;
7098 /* Ensure we don't miss a work->pending update ... */
7101 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7102 spin_unlock_irqrestore(&dev->event_lock, flags);
7106 /* and that the unpin work is consistent wrt ->pending. */
7109 intel_crtc->unpin_work = NULL;
7112 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7114 drm_vblank_put(dev, intel_crtc->pipe);
7116 spin_unlock_irqrestore(&dev->event_lock, flags);
7118 wake_up_all(&dev_priv->pending_flip_queue);
7120 queue_work(dev_priv->wq, &work->work);
7122 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7125 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7127 drm_i915_private_t *dev_priv = dev->dev_private;
7128 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7130 do_intel_finish_page_flip(dev, crtc);
7133 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7135 drm_i915_private_t *dev_priv = dev->dev_private;
7136 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7138 do_intel_finish_page_flip(dev, crtc);
7141 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7143 drm_i915_private_t *dev_priv = dev->dev_private;
7144 struct intel_crtc *intel_crtc =
7145 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7146 unsigned long flags;
7148 /* NB: An MMIO update of the plane base pointer will also
7149 * generate a page-flip completion irq, i.e. every modeset
7150 * is also accompanied by a spurious intel_prepare_page_flip().
7152 spin_lock_irqsave(&dev->event_lock, flags);
7153 if (intel_crtc->unpin_work)
7154 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7155 spin_unlock_irqrestore(&dev->event_lock, flags);
7158 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7160 /* Ensure that the work item is consistent when activating it ... */
7162 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7163 /* and that it is marked active as soon as the irq could fire. */
7167 static int intel_gen2_queue_flip(struct drm_device *dev,
7168 struct drm_crtc *crtc,
7169 struct drm_framebuffer *fb,
7170 struct drm_i915_gem_object *obj)
7172 struct drm_i915_private *dev_priv = dev->dev_private;
7173 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7175 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7178 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7182 ret = intel_ring_begin(ring, 6);
7186 /* Can't queue multiple flips, so wait for the previous
7187 * one to finish before executing the next.
7189 if (intel_crtc->plane)
7190 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7192 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7193 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7194 intel_ring_emit(ring, MI_NOOP);
7195 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7196 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7197 intel_ring_emit(ring, fb->pitches[0]);
7198 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7199 intel_ring_emit(ring, 0); /* aux display base address, unused */
7201 intel_mark_page_flip_active(intel_crtc);
7202 intel_ring_advance(ring);
7206 intel_unpin_fb_obj(obj);
7211 static int intel_gen3_queue_flip(struct drm_device *dev,
7212 struct drm_crtc *crtc,
7213 struct drm_framebuffer *fb,
7214 struct drm_i915_gem_object *obj)
7216 struct drm_i915_private *dev_priv = dev->dev_private;
7217 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7219 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7222 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7226 ret = intel_ring_begin(ring, 6);
7230 if (intel_crtc->plane)
7231 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7233 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7234 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7235 intel_ring_emit(ring, MI_NOOP);
7236 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7237 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7238 intel_ring_emit(ring, fb->pitches[0]);
7239 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7240 intel_ring_emit(ring, MI_NOOP);
7242 intel_mark_page_flip_active(intel_crtc);
7243 intel_ring_advance(ring);
7247 intel_unpin_fb_obj(obj);
7252 static int intel_gen4_queue_flip(struct drm_device *dev,
7253 struct drm_crtc *crtc,
7254 struct drm_framebuffer *fb,
7255 struct drm_i915_gem_object *obj)
7257 struct drm_i915_private *dev_priv = dev->dev_private;
7258 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7259 uint32_t pf, pipesrc;
7260 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7263 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7267 ret = intel_ring_begin(ring, 4);
7271 /* i965+ uses the linear or tiled offsets from the
7272 * Display Registers (which do not change across a page-flip)
7273 * so we need only reprogram the base address.
7275 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7276 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7277 intel_ring_emit(ring, fb->pitches[0]);
7278 intel_ring_emit(ring,
7279 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7282 /* XXX Enabling the panel-fitter across page-flip is so far
7283 * untested on non-native modes, so ignore it for now.
7284 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7287 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7288 intel_ring_emit(ring, pf | pipesrc);
7290 intel_mark_page_flip_active(intel_crtc);
7291 intel_ring_advance(ring);
7295 intel_unpin_fb_obj(obj);
7300 static int intel_gen6_queue_flip(struct drm_device *dev,
7301 struct drm_crtc *crtc,
7302 struct drm_framebuffer *fb,
7303 struct drm_i915_gem_object *obj)
7305 struct drm_i915_private *dev_priv = dev->dev_private;
7306 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7307 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7308 uint32_t pf, pipesrc;
7311 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7315 ret = intel_ring_begin(ring, 4);
7319 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7320 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7321 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7322 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7324 /* Contrary to the suggestions in the documentation,
7325 * "Enable Panel Fitter" does not seem to be required when page
7326 * flipping with a non-native mode, and worse causes a normal
7328 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7331 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7332 intel_ring_emit(ring, pf | pipesrc);
7334 intel_mark_page_flip_active(intel_crtc);
7335 intel_ring_advance(ring);
7339 intel_unpin_fb_obj(obj);
7345 * On gen7 we currently use the blit ring because (in early silicon at least)
7346 * the render ring doesn't give us interrpts for page flip completion, which
7347 * means clients will hang after the first flip is queued. Fortunately the
7348 * blit ring generates interrupts properly, so use it instead.
7350 static int intel_gen7_queue_flip(struct drm_device *dev,
7351 struct drm_crtc *crtc,
7352 struct drm_framebuffer *fb,
7353 struct drm_i915_gem_object *obj)
7355 struct drm_i915_private *dev_priv = dev->dev_private;
7356 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7357 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7358 uint32_t plane_bit = 0;
7361 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7365 switch(intel_crtc->plane) {
7367 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7370 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7373 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7376 WARN_ONCE(1, "unknown plane in flip command\n");
7381 ret = intel_ring_begin(ring, 4);
7385 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7386 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7387 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7388 intel_ring_emit(ring, (MI_NOOP));
7390 intel_mark_page_flip_active(intel_crtc);
7391 intel_ring_advance(ring);
7395 intel_unpin_fb_obj(obj);
7400 static int intel_default_queue_flip(struct drm_device *dev,
7401 struct drm_crtc *crtc,
7402 struct drm_framebuffer *fb,
7403 struct drm_i915_gem_object *obj)
7408 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7409 struct drm_framebuffer *fb,
7410 struct drm_pending_vblank_event *event)
7412 struct drm_device *dev = crtc->dev;
7413 struct drm_i915_private *dev_priv = dev->dev_private;
7414 struct drm_framebuffer *old_fb = crtc->fb;
7415 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7416 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7417 struct intel_unpin_work *work;
7418 unsigned long flags;
7421 /* Can't change pixel format via MI display flips. */
7422 if (fb->pixel_format != crtc->fb->pixel_format)
7426 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7427 * Note that pitch changes could also affect these register.
7429 if (INTEL_INFO(dev)->gen > 3 &&
7430 (fb->offsets[0] != crtc->fb->offsets[0] ||
7431 fb->pitches[0] != crtc->fb->pitches[0]))
7434 work = kzalloc(sizeof *work, GFP_KERNEL);
7438 work->event = event;
7440 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7441 INIT_WORK(&work->work, intel_unpin_work_fn);
7443 ret = drm_vblank_get(dev, intel_crtc->pipe);
7447 /* We borrow the event spin lock for protecting unpin_work */
7448 spin_lock_irqsave(&dev->event_lock, flags);
7449 if (intel_crtc->unpin_work) {
7450 spin_unlock_irqrestore(&dev->event_lock, flags);
7452 drm_vblank_put(dev, intel_crtc->pipe);
7454 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7457 intel_crtc->unpin_work = work;
7458 spin_unlock_irqrestore(&dev->event_lock, flags);
7460 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7461 flush_workqueue(dev_priv->wq);
7463 ret = i915_mutex_lock_interruptible(dev);
7467 /* Reference the objects for the scheduled work. */
7468 drm_gem_object_reference(&work->old_fb_obj->base);
7469 drm_gem_object_reference(&obj->base);
7473 work->pending_flip_obj = obj;
7475 work->enable_stall_check = true;
7477 atomic_inc(&intel_crtc->unpin_work_count);
7478 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7480 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7482 goto cleanup_pending;
7484 intel_disable_fbc(dev);
7485 intel_mark_fb_busy(obj);
7486 mutex_unlock(&dev->struct_mutex);
7488 trace_i915_flip_request(intel_crtc->plane, obj);
7493 atomic_dec(&intel_crtc->unpin_work_count);
7495 drm_gem_object_unreference(&work->old_fb_obj->base);
7496 drm_gem_object_unreference(&obj->base);
7497 mutex_unlock(&dev->struct_mutex);
7500 spin_lock_irqsave(&dev->event_lock, flags);
7501 intel_crtc->unpin_work = NULL;
7502 spin_unlock_irqrestore(&dev->event_lock, flags);
7504 drm_vblank_put(dev, intel_crtc->pipe);
7511 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7512 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7513 .load_lut = intel_crtc_load_lut,
7516 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7518 struct intel_encoder *other_encoder;
7519 struct drm_crtc *crtc = &encoder->new_crtc->base;
7524 list_for_each_entry(other_encoder,
7525 &crtc->dev->mode_config.encoder_list,
7528 if (&other_encoder->new_crtc->base != crtc ||
7529 encoder == other_encoder)
7538 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7539 struct drm_crtc *crtc)
7541 struct drm_device *dev;
7542 struct drm_crtc *tmp;
7545 WARN(!crtc, "checking null crtc?\n");
7549 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7555 if (encoder->possible_crtcs & crtc_mask)
7561 * intel_modeset_update_staged_output_state
7563 * Updates the staged output configuration state, e.g. after we've read out the
7566 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7568 struct intel_encoder *encoder;
7569 struct intel_connector *connector;
7571 list_for_each_entry(connector, &dev->mode_config.connector_list,
7573 connector->new_encoder =
7574 to_intel_encoder(connector->base.encoder);
7577 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7580 to_intel_crtc(encoder->base.crtc);
7585 * intel_modeset_commit_output_state
7587 * This function copies the stage display pipe configuration to the real one.
7589 static void intel_modeset_commit_output_state(struct drm_device *dev)
7591 struct intel_encoder *encoder;
7592 struct intel_connector *connector;
7594 list_for_each_entry(connector, &dev->mode_config.connector_list,
7596 connector->base.encoder = &connector->new_encoder->base;
7599 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7601 encoder->base.crtc = &encoder->new_crtc->base;
7606 pipe_config_set_bpp(struct drm_crtc *crtc,
7607 struct drm_framebuffer *fb,
7608 struct intel_crtc_config *pipe_config)
7610 struct drm_device *dev = crtc->dev;
7611 struct drm_connector *connector;
7614 switch (fb->pixel_format) {
7616 bpp = 8*3; /* since we go through a colormap */
7618 case DRM_FORMAT_XRGB1555:
7619 case DRM_FORMAT_ARGB1555:
7620 /* checked in intel_framebuffer_init already */
7621 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7623 case DRM_FORMAT_RGB565:
7624 bpp = 6*3; /* min is 18bpp */
7626 case DRM_FORMAT_XBGR8888:
7627 case DRM_FORMAT_ABGR8888:
7628 /* checked in intel_framebuffer_init already */
7629 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7631 case DRM_FORMAT_XRGB8888:
7632 case DRM_FORMAT_ARGB8888:
7635 case DRM_FORMAT_XRGB2101010:
7636 case DRM_FORMAT_ARGB2101010:
7637 case DRM_FORMAT_XBGR2101010:
7638 case DRM_FORMAT_ABGR2101010:
7639 /* checked in intel_framebuffer_init already */
7640 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7644 /* TODO: gen4+ supports 16 bpc floating point, too. */
7646 DRM_DEBUG_KMS("unsupported depth\n");
7650 pipe_config->pipe_bpp = bpp;
7652 /* Clamp display bpp to EDID value */
7653 list_for_each_entry(connector, &dev->mode_config.connector_list,
7655 if (connector->encoder && connector->encoder->crtc != crtc)
7658 /* Don't use an invalid EDID bpc value */
7659 if (connector->display_info.bpc &&
7660 connector->display_info.bpc * 3 < bpp) {
7661 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7662 bpp, connector->display_info.bpc*3);
7663 pipe_config->pipe_bpp = connector->display_info.bpc*3;
7666 /* Clamp bpp to 8 on screens without EDID 1.4 */
7667 if (connector->display_info.bpc == 0 && bpp > 24) {
7668 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7670 pipe_config->pipe_bpp = 24;
7677 static struct intel_crtc_config *
7678 intel_modeset_pipe_config(struct drm_crtc *crtc,
7679 struct drm_framebuffer *fb,
7680 struct drm_display_mode *mode)
7682 struct drm_device *dev = crtc->dev;
7683 struct drm_encoder_helper_funcs *encoder_funcs;
7684 struct intel_encoder *encoder;
7685 struct intel_crtc_config *pipe_config;
7688 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7690 return ERR_PTR(-ENOMEM);
7692 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7693 drm_mode_copy(&pipe_config->requested_mode, mode);
7695 plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
7699 /* Pass our mode to the connectors and the CRTC to give them a chance to
7700 * adjust it according to limitations or connector properties, and also
7701 * a chance to reject the mode entirely.
7703 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7706 if (&encoder->new_crtc->base != crtc)
7709 if (encoder->compute_config) {
7710 if (!(encoder->compute_config(encoder, pipe_config))) {
7711 DRM_DEBUG_KMS("Encoder config failure\n");
7718 encoder_funcs = encoder->base.helper_private;
7719 if (!(encoder_funcs->mode_fixup(&encoder->base,
7720 &pipe_config->requested_mode,
7721 &pipe_config->adjusted_mode))) {
7722 DRM_DEBUG_KMS("Encoder fixup failed\n");
7727 if (!(intel_crtc_compute_config(crtc, pipe_config))) {
7728 DRM_DEBUG_KMS("CRTC fixup failed\n");
7731 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7733 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7734 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7735 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7740 return ERR_PTR(-EINVAL);
7743 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7744 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7746 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7747 unsigned *prepare_pipes, unsigned *disable_pipes)
7749 struct intel_crtc *intel_crtc;
7750 struct drm_device *dev = crtc->dev;
7751 struct intel_encoder *encoder;
7752 struct intel_connector *connector;
7753 struct drm_crtc *tmp_crtc;
7755 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7757 /* Check which crtcs have changed outputs connected to them, these need
7758 * to be part of the prepare_pipes mask. We don't (yet) support global
7759 * modeset across multiple crtcs, so modeset_pipes will only have one
7760 * bit set at most. */
7761 list_for_each_entry(connector, &dev->mode_config.connector_list,
7763 if (connector->base.encoder == &connector->new_encoder->base)
7766 if (connector->base.encoder) {
7767 tmp_crtc = connector->base.encoder->crtc;
7769 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7772 if (connector->new_encoder)
7774 1 << connector->new_encoder->new_crtc->pipe;
7777 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7779 if (encoder->base.crtc == &encoder->new_crtc->base)
7782 if (encoder->base.crtc) {
7783 tmp_crtc = encoder->base.crtc;
7785 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7788 if (encoder->new_crtc)
7789 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7792 /* Check for any pipes that will be fully disabled ... */
7793 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7797 /* Don't try to disable disabled crtcs. */
7798 if (!intel_crtc->base.enabled)
7801 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7803 if (encoder->new_crtc == intel_crtc)
7808 *disable_pipes |= 1 << intel_crtc->pipe;
7812 /* set_mode is also used to update properties on life display pipes. */
7813 intel_crtc = to_intel_crtc(crtc);
7815 *prepare_pipes |= 1 << intel_crtc->pipe;
7818 * For simplicity do a full modeset on any pipe where the output routing
7819 * changed. We could be more clever, but that would require us to be
7820 * more careful with calling the relevant encoder->mode_set functions.
7823 *modeset_pipes = *prepare_pipes;
7825 /* ... and mask these out. */
7826 *modeset_pipes &= ~(*disable_pipes);
7827 *prepare_pipes &= ~(*disable_pipes);
7830 * HACK: We don't (yet) fully support global modesets. intel_set_config
7831 * obies this rule, but the modeset restore mode of
7832 * intel_modeset_setup_hw_state does not.
7834 *modeset_pipes &= 1 << intel_crtc->pipe;
7835 *prepare_pipes &= 1 << intel_crtc->pipe;
7837 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7838 *modeset_pipes, *prepare_pipes, *disable_pipes);
7841 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7843 struct drm_encoder *encoder;
7844 struct drm_device *dev = crtc->dev;
7846 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7847 if (encoder->crtc == crtc)
7854 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7856 struct intel_encoder *intel_encoder;
7857 struct intel_crtc *intel_crtc;
7858 struct drm_connector *connector;
7860 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7862 if (!intel_encoder->base.crtc)
7865 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7867 if (prepare_pipes & (1 << intel_crtc->pipe))
7868 intel_encoder->connectors_active = false;
7871 intel_modeset_commit_output_state(dev);
7873 /* Update computed state. */
7874 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7876 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7879 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7880 if (!connector->encoder || !connector->encoder->crtc)
7883 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7885 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7886 struct drm_property *dpms_property =
7887 dev->mode_config.dpms_property;
7889 connector->dpms = DRM_MODE_DPMS_ON;
7890 drm_object_property_set_value(&connector->base,
7894 intel_encoder = to_intel_encoder(connector->encoder);
7895 intel_encoder->connectors_active = true;
7901 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7902 list_for_each_entry((intel_crtc), \
7903 &(dev)->mode_config.crtc_list, \
7905 if (mask & (1 <<(intel_crtc)->pipe)) \
7908 intel_pipe_config_compare(struct intel_crtc_config *current_config,
7909 struct intel_crtc_config *pipe_config)
7911 if (current_config->has_pch_encoder != pipe_config->has_pch_encoder) {
7912 DRM_ERROR("mismatch in has_pch_encoder "
7913 "(expected %i, found %i)\n",
7914 current_config->has_pch_encoder,
7915 pipe_config->has_pch_encoder);
7919 if (current_config->fdi_lanes != pipe_config->fdi_lanes) {
7920 DRM_ERROR("mismatch in fdi_lanes "
7921 "(expected %i, found %i)\n",
7922 current_config->fdi_lanes,
7923 pipe_config->fdi_lanes);
7931 intel_modeset_check_state(struct drm_device *dev)
7933 drm_i915_private_t *dev_priv = dev->dev_private;
7934 struct intel_crtc *crtc;
7935 struct intel_encoder *encoder;
7936 struct intel_connector *connector;
7937 struct intel_crtc_config pipe_config;
7939 list_for_each_entry(connector, &dev->mode_config.connector_list,
7941 /* This also checks the encoder/connector hw state with the
7942 * ->get_hw_state callbacks. */
7943 intel_connector_check_state(connector);
7945 WARN(&connector->new_encoder->base != connector->base.encoder,
7946 "connector's staged encoder doesn't match current encoder\n");
7949 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7951 bool enabled = false;
7952 bool active = false;
7953 enum pipe pipe, tracked_pipe;
7955 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7956 encoder->base.base.id,
7957 drm_get_encoder_name(&encoder->base));
7959 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7960 "encoder's stage crtc doesn't match current crtc\n");
7961 WARN(encoder->connectors_active && !encoder->base.crtc,
7962 "encoder's active_connectors set, but no crtc\n");
7964 list_for_each_entry(connector, &dev->mode_config.connector_list,
7966 if (connector->base.encoder != &encoder->base)
7969 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7972 WARN(!!encoder->base.crtc != enabled,
7973 "encoder's enabled state mismatch "
7974 "(expected %i, found %i)\n",
7975 !!encoder->base.crtc, enabled);
7976 WARN(active && !encoder->base.crtc,
7977 "active encoder with no crtc\n");
7979 WARN(encoder->connectors_active != active,
7980 "encoder's computed active state doesn't match tracked active state "
7981 "(expected %i, found %i)\n", active, encoder->connectors_active);
7983 active = encoder->get_hw_state(encoder, &pipe);
7984 WARN(active != encoder->connectors_active,
7985 "encoder's hw state doesn't match sw tracking "
7986 "(expected %i, found %i)\n",
7987 encoder->connectors_active, active);
7989 if (!encoder->base.crtc)
7992 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7993 WARN(active && pipe != tracked_pipe,
7994 "active encoder's pipe doesn't match"
7995 "(expected %i, found %i)\n",
7996 tracked_pipe, pipe);
8000 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8002 bool enabled = false;
8003 bool active = false;
8005 DRM_DEBUG_KMS("[CRTC:%d]\n",
8006 crtc->base.base.id);
8008 WARN(crtc->active && !crtc->base.enabled,
8009 "active crtc, but not enabled in sw tracking\n");
8011 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8013 if (encoder->base.crtc != &crtc->base)
8016 if (encoder->connectors_active)
8019 WARN(active != crtc->active,
8020 "crtc's computed active state doesn't match tracked active state "
8021 "(expected %i, found %i)\n", active, crtc->active);
8022 WARN(enabled != crtc->base.enabled,
8023 "crtc's computed enabled state doesn't match tracked enabled state "
8024 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8026 memset(&pipe_config, 0, sizeof(pipe_config));
8027 pipe_config.cpu_transcoder = crtc->config.cpu_transcoder;
8028 active = dev_priv->display.get_pipe_config(crtc,
8030 WARN(crtc->active != active,
8031 "crtc active state doesn't match with hw state "
8032 "(expected %i, found %i)\n", crtc->active, active);
8035 !intel_pipe_config_compare(&crtc->config, &pipe_config),
8036 "pipe state doesn't match!\n");
8040 static int __intel_set_mode(struct drm_crtc *crtc,
8041 struct drm_display_mode *mode,
8042 int x, int y, struct drm_framebuffer *fb)
8044 struct drm_device *dev = crtc->dev;
8045 drm_i915_private_t *dev_priv = dev->dev_private;
8046 struct drm_display_mode *saved_mode, *saved_hwmode;
8047 struct intel_crtc_config *pipe_config = NULL;
8048 struct intel_crtc *intel_crtc;
8049 unsigned disable_pipes, prepare_pipes, modeset_pipes;
8052 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
8055 saved_hwmode = saved_mode + 1;
8057 intel_modeset_affected_pipes(crtc, &modeset_pipes,
8058 &prepare_pipes, &disable_pipes);
8060 *saved_hwmode = crtc->hwmode;
8061 *saved_mode = crtc->mode;
8063 /* Hack: Because we don't (yet) support global modeset on multiple
8064 * crtcs, we don't keep track of the new mode for more than one crtc.
8065 * Hence simply check whether any bit is set in modeset_pipes in all the
8066 * pieces of code that are not yet converted to deal with mutliple crtcs
8067 * changing their mode at the same time. */
8068 if (modeset_pipes) {
8069 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8070 if (IS_ERR(pipe_config)) {
8071 ret = PTR_ERR(pipe_config);
8078 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8079 intel_crtc_disable(&intel_crtc->base);
8081 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8082 if (intel_crtc->base.enabled)
8083 dev_priv->display.crtc_disable(&intel_crtc->base);
8086 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8087 * to set it here already despite that we pass it down the callchain.
8089 if (modeset_pipes) {
8090 enum transcoder tmp = to_intel_crtc(crtc)->config.cpu_transcoder;
8092 /* mode_set/enable/disable functions rely on a correct pipe
8094 to_intel_crtc(crtc)->config = *pipe_config;
8095 to_intel_crtc(crtc)->config.cpu_transcoder = tmp;
8098 /* Only after disabling all output pipelines that will be changed can we
8099 * update the the output configuration. */
8100 intel_modeset_update_state(dev, prepare_pipes);
8102 if (dev_priv->display.modeset_global_resources)
8103 dev_priv->display.modeset_global_resources(dev);
8105 /* Set up the DPLL and any encoders state that needs to adjust or depend
8108 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8109 ret = intel_crtc_mode_set(&intel_crtc->base,
8115 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8116 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8117 dev_priv->display.crtc_enable(&intel_crtc->base);
8119 if (modeset_pipes) {
8120 /* Store real post-adjustment hardware mode. */
8121 crtc->hwmode = pipe_config->adjusted_mode;
8123 /* Calculate and store various constants which
8124 * are later needed by vblank and swap-completion
8125 * timestamping. They are derived from true hwmode.
8127 drm_calc_timestamping_constants(crtc);
8130 /* FIXME: add subpixel order */
8132 if (ret && crtc->enabled) {
8133 crtc->hwmode = *saved_hwmode;
8134 crtc->mode = *saved_mode;
8143 int intel_set_mode(struct drm_crtc *crtc,
8144 struct drm_display_mode *mode,
8145 int x, int y, struct drm_framebuffer *fb)
8149 ret = __intel_set_mode(crtc, mode, x, y, fb);
8152 intel_modeset_check_state(crtc->dev);
8157 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8159 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8162 #undef for_each_intel_crtc_masked
8164 static void intel_set_config_free(struct intel_set_config *config)
8169 kfree(config->save_connector_encoders);
8170 kfree(config->save_encoder_crtcs);
8174 static int intel_set_config_save_state(struct drm_device *dev,
8175 struct intel_set_config *config)
8177 struct drm_encoder *encoder;
8178 struct drm_connector *connector;
8181 config->save_encoder_crtcs =
8182 kcalloc(dev->mode_config.num_encoder,
8183 sizeof(struct drm_crtc *), GFP_KERNEL);
8184 if (!config->save_encoder_crtcs)
8187 config->save_connector_encoders =
8188 kcalloc(dev->mode_config.num_connector,
8189 sizeof(struct drm_encoder *), GFP_KERNEL);
8190 if (!config->save_connector_encoders)
8193 /* Copy data. Note that driver private data is not affected.
8194 * Should anything bad happen only the expected state is
8195 * restored, not the drivers personal bookkeeping.
8198 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8199 config->save_encoder_crtcs[count++] = encoder->crtc;
8203 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8204 config->save_connector_encoders[count++] = connector->encoder;
8210 static void intel_set_config_restore_state(struct drm_device *dev,
8211 struct intel_set_config *config)
8213 struct intel_encoder *encoder;
8214 struct intel_connector *connector;
8218 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8220 to_intel_crtc(config->save_encoder_crtcs[count++]);
8224 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8225 connector->new_encoder =
8226 to_intel_encoder(config->save_connector_encoders[count++]);
8231 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8232 struct intel_set_config *config)
8235 /* We should be able to check here if the fb has the same properties
8236 * and then just flip_or_move it */
8237 if (set->crtc->fb != set->fb) {
8238 /* If we have no fb then treat it as a full mode set */
8239 if (set->crtc->fb == NULL) {
8240 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8241 config->mode_changed = true;
8242 } else if (set->fb == NULL) {
8243 config->mode_changed = true;
8244 } else if (set->fb->pixel_format !=
8245 set->crtc->fb->pixel_format) {
8246 config->mode_changed = true;
8248 config->fb_changed = true;
8251 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8252 config->fb_changed = true;
8254 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8255 DRM_DEBUG_KMS("modes are different, full mode set\n");
8256 drm_mode_debug_printmodeline(&set->crtc->mode);
8257 drm_mode_debug_printmodeline(set->mode);
8258 config->mode_changed = true;
8263 intel_modeset_stage_output_state(struct drm_device *dev,
8264 struct drm_mode_set *set,
8265 struct intel_set_config *config)
8267 struct drm_crtc *new_crtc;
8268 struct intel_connector *connector;
8269 struct intel_encoder *encoder;
8272 /* The upper layers ensure that we either disable a crtc or have a list
8273 * of connectors. For paranoia, double-check this. */
8274 WARN_ON(!set->fb && (set->num_connectors != 0));
8275 WARN_ON(set->fb && (set->num_connectors == 0));
8278 list_for_each_entry(connector, &dev->mode_config.connector_list,
8280 /* Otherwise traverse passed in connector list and get encoders
8282 for (ro = 0; ro < set->num_connectors; ro++) {
8283 if (set->connectors[ro] == &connector->base) {
8284 connector->new_encoder = connector->encoder;
8289 /* If we disable the crtc, disable all its connectors. Also, if
8290 * the connector is on the changing crtc but not on the new
8291 * connector list, disable it. */
8292 if ((!set->fb || ro == set->num_connectors) &&
8293 connector->base.encoder &&
8294 connector->base.encoder->crtc == set->crtc) {
8295 connector->new_encoder = NULL;
8297 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8298 connector->base.base.id,
8299 drm_get_connector_name(&connector->base));
8303 if (&connector->new_encoder->base != connector->base.encoder) {
8304 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8305 config->mode_changed = true;
8308 /* connector->new_encoder is now updated for all connectors. */
8310 /* Update crtc of enabled connectors. */
8312 list_for_each_entry(connector, &dev->mode_config.connector_list,
8314 if (!connector->new_encoder)
8317 new_crtc = connector->new_encoder->base.crtc;
8319 for (ro = 0; ro < set->num_connectors; ro++) {
8320 if (set->connectors[ro] == &connector->base)
8321 new_crtc = set->crtc;
8324 /* Make sure the new CRTC will work with the encoder */
8325 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8329 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8331 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8332 connector->base.base.id,
8333 drm_get_connector_name(&connector->base),
8337 /* Check for any encoders that needs to be disabled. */
8338 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8340 list_for_each_entry(connector,
8341 &dev->mode_config.connector_list,
8343 if (connector->new_encoder == encoder) {
8344 WARN_ON(!connector->new_encoder->new_crtc);
8349 encoder->new_crtc = NULL;
8351 /* Only now check for crtc changes so we don't miss encoders
8352 * that will be disabled. */
8353 if (&encoder->new_crtc->base != encoder->base.crtc) {
8354 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8355 config->mode_changed = true;
8358 /* Now we've also updated encoder->new_crtc for all encoders. */
8363 static int intel_crtc_set_config(struct drm_mode_set *set)
8365 struct drm_device *dev;
8366 struct drm_mode_set save_set;
8367 struct intel_set_config *config;
8372 BUG_ON(!set->crtc->helper_private);
8374 /* Enforce sane interface api - has been abused by the fb helper. */
8375 BUG_ON(!set->mode && set->fb);
8376 BUG_ON(set->fb && set->num_connectors == 0);
8379 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8380 set->crtc->base.id, set->fb->base.id,
8381 (int)set->num_connectors, set->x, set->y);
8383 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8386 dev = set->crtc->dev;
8389 config = kzalloc(sizeof(*config), GFP_KERNEL);
8393 ret = intel_set_config_save_state(dev, config);
8397 save_set.crtc = set->crtc;
8398 save_set.mode = &set->crtc->mode;
8399 save_set.x = set->crtc->x;
8400 save_set.y = set->crtc->y;
8401 save_set.fb = set->crtc->fb;
8403 /* Compute whether we need a full modeset, only an fb base update or no
8404 * change at all. In the future we might also check whether only the
8405 * mode changed, e.g. for LVDS where we only change the panel fitter in
8407 intel_set_config_compute_mode_changes(set, config);
8409 ret = intel_modeset_stage_output_state(dev, set, config);
8413 if (config->mode_changed) {
8415 DRM_DEBUG_KMS("attempting to set mode from"
8417 drm_mode_debug_printmodeline(set->mode);
8420 ret = intel_set_mode(set->crtc, set->mode,
8421 set->x, set->y, set->fb);
8423 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8424 set->crtc->base.id, ret);
8427 } else if (config->fb_changed) {
8428 intel_crtc_wait_for_pending_flips(set->crtc);
8430 ret = intel_pipe_set_base(set->crtc,
8431 set->x, set->y, set->fb);
8434 intel_set_config_free(config);
8439 intel_set_config_restore_state(dev, config);
8441 /* Try to restore the config */
8442 if (config->mode_changed &&
8443 intel_set_mode(save_set.crtc, save_set.mode,
8444 save_set.x, save_set.y, save_set.fb))
8445 DRM_ERROR("failed to restore config after modeset failure\n");
8448 intel_set_config_free(config);
8452 static const struct drm_crtc_funcs intel_crtc_funcs = {
8453 .cursor_set = intel_crtc_cursor_set,
8454 .cursor_move = intel_crtc_cursor_move,
8455 .gamma_set = intel_crtc_gamma_set,
8456 .set_config = intel_crtc_set_config,
8457 .destroy = intel_crtc_destroy,
8458 .page_flip = intel_crtc_page_flip,
8461 static void intel_cpu_pll_init(struct drm_device *dev)
8464 intel_ddi_pll_init(dev);
8467 static void intel_pch_pll_init(struct drm_device *dev)
8469 drm_i915_private_t *dev_priv = dev->dev_private;
8472 if (dev_priv->num_pch_pll == 0) {
8473 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8477 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8478 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8479 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8480 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8484 static void intel_crtc_init(struct drm_device *dev, int pipe)
8486 drm_i915_private_t *dev_priv = dev->dev_private;
8487 struct intel_crtc *intel_crtc;
8490 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8491 if (intel_crtc == NULL)
8494 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8496 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8497 for (i = 0; i < 256; i++) {
8498 intel_crtc->lut_r[i] = i;
8499 intel_crtc->lut_g[i] = i;
8500 intel_crtc->lut_b[i] = i;
8503 /* Swap pipes & planes for FBC on pre-965 */
8504 intel_crtc->pipe = pipe;
8505 intel_crtc->plane = pipe;
8506 intel_crtc->config.cpu_transcoder = pipe;
8507 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8508 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8509 intel_crtc->plane = !pipe;
8512 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8513 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8514 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8515 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8517 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8520 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8521 struct drm_file *file)
8523 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8524 struct drm_mode_object *drmmode_obj;
8525 struct intel_crtc *crtc;
8527 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8530 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8531 DRM_MODE_OBJECT_CRTC);
8534 DRM_ERROR("no such CRTC id\n");
8538 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8539 pipe_from_crtc_id->pipe = crtc->pipe;
8544 static int intel_encoder_clones(struct intel_encoder *encoder)
8546 struct drm_device *dev = encoder->base.dev;
8547 struct intel_encoder *source_encoder;
8551 list_for_each_entry(source_encoder,
8552 &dev->mode_config.encoder_list, base.head) {
8554 if (encoder == source_encoder)
8555 index_mask |= (1 << entry);
8557 /* Intel hw has only one MUX where enocoders could be cloned. */
8558 if (encoder->cloneable && source_encoder->cloneable)
8559 index_mask |= (1 << entry);
8567 static bool has_edp_a(struct drm_device *dev)
8569 struct drm_i915_private *dev_priv = dev->dev_private;
8571 if (!IS_MOBILE(dev))
8574 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8578 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8584 static void intel_setup_outputs(struct drm_device *dev)
8586 struct drm_i915_private *dev_priv = dev->dev_private;
8587 struct intel_encoder *encoder;
8588 bool dpd_is_edp = false;
8591 has_lvds = intel_lvds_init(dev);
8592 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8593 /* disable the panel fitter on everything but LVDS */
8594 I915_WRITE(PFIT_CONTROL, 0);
8598 intel_crt_init(dev);
8603 /* Haswell uses DDI functions to detect digital outputs */
8604 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8605 /* DDI A only supports eDP */
8607 intel_ddi_init(dev, PORT_A);
8609 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8611 found = I915_READ(SFUSE_STRAP);
8613 if (found & SFUSE_STRAP_DDIB_DETECTED)
8614 intel_ddi_init(dev, PORT_B);
8615 if (found & SFUSE_STRAP_DDIC_DETECTED)
8616 intel_ddi_init(dev, PORT_C);
8617 if (found & SFUSE_STRAP_DDID_DETECTED)
8618 intel_ddi_init(dev, PORT_D);
8619 } else if (HAS_PCH_SPLIT(dev)) {
8621 dpd_is_edp = intel_dpd_is_edp(dev);
8624 intel_dp_init(dev, DP_A, PORT_A);
8626 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
8627 /* PCH SDVOB multiplex with HDMIB */
8628 found = intel_sdvo_init(dev, PCH_SDVOB, true);
8630 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
8631 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8632 intel_dp_init(dev, PCH_DP_B, PORT_B);
8635 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
8636 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
8638 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
8639 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
8641 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8642 intel_dp_init(dev, PCH_DP_C, PORT_C);
8644 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8645 intel_dp_init(dev, PCH_DP_D, PORT_D);
8646 } else if (IS_VALLEYVIEW(dev)) {
8647 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8648 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8649 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
8651 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
8652 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8654 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8655 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
8657 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8660 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8661 DRM_DEBUG_KMS("probing SDVOB\n");
8662 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
8663 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8664 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8665 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
8668 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8669 DRM_DEBUG_KMS("probing DP_B\n");
8670 intel_dp_init(dev, DP_B, PORT_B);
8674 /* Before G4X SDVOC doesn't have its own detect register */
8676 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8677 DRM_DEBUG_KMS("probing SDVOC\n");
8678 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
8681 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
8683 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8684 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8685 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
8687 if (SUPPORTS_INTEGRATED_DP(dev)) {
8688 DRM_DEBUG_KMS("probing DP_C\n");
8689 intel_dp_init(dev, DP_C, PORT_C);
8693 if (SUPPORTS_INTEGRATED_DP(dev) &&
8694 (I915_READ(DP_D) & DP_DETECTED)) {
8695 DRM_DEBUG_KMS("probing DP_D\n");
8696 intel_dp_init(dev, DP_D, PORT_D);
8698 } else if (IS_GEN2(dev))
8699 intel_dvo_init(dev);
8701 if (SUPPORTS_TV(dev))
8704 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8705 encoder->base.possible_crtcs = encoder->crtc_mask;
8706 encoder->base.possible_clones =
8707 intel_encoder_clones(encoder);
8710 intel_init_pch_refclk(dev);
8712 drm_helper_move_panel_connectors_to_head(dev);
8715 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8717 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8719 drm_framebuffer_cleanup(fb);
8720 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8725 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8726 struct drm_file *file,
8727 unsigned int *handle)
8729 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8730 struct drm_i915_gem_object *obj = intel_fb->obj;
8732 return drm_gem_handle_create(file, &obj->base, handle);
8735 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8736 .destroy = intel_user_framebuffer_destroy,
8737 .create_handle = intel_user_framebuffer_create_handle,
8740 int intel_framebuffer_init(struct drm_device *dev,
8741 struct intel_framebuffer *intel_fb,
8742 struct drm_mode_fb_cmd2 *mode_cmd,
8743 struct drm_i915_gem_object *obj)
8747 if (obj->tiling_mode == I915_TILING_Y) {
8748 DRM_DEBUG("hardware does not support tiling Y\n");
8752 if (mode_cmd->pitches[0] & 63) {
8753 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8754 mode_cmd->pitches[0]);
8758 /* FIXME <= Gen4 stride limits are bit unclear */
8759 if (mode_cmd->pitches[0] > 32768) {
8760 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8761 mode_cmd->pitches[0]);
8765 if (obj->tiling_mode != I915_TILING_NONE &&
8766 mode_cmd->pitches[0] != obj->stride) {
8767 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8768 mode_cmd->pitches[0], obj->stride);
8772 /* Reject formats not supported by any plane early. */
8773 switch (mode_cmd->pixel_format) {
8775 case DRM_FORMAT_RGB565:
8776 case DRM_FORMAT_XRGB8888:
8777 case DRM_FORMAT_ARGB8888:
8779 case DRM_FORMAT_XRGB1555:
8780 case DRM_FORMAT_ARGB1555:
8781 if (INTEL_INFO(dev)->gen > 3) {
8782 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8786 case DRM_FORMAT_XBGR8888:
8787 case DRM_FORMAT_ABGR8888:
8788 case DRM_FORMAT_XRGB2101010:
8789 case DRM_FORMAT_ARGB2101010:
8790 case DRM_FORMAT_XBGR2101010:
8791 case DRM_FORMAT_ABGR2101010:
8792 if (INTEL_INFO(dev)->gen < 4) {
8793 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8797 case DRM_FORMAT_YUYV:
8798 case DRM_FORMAT_UYVY:
8799 case DRM_FORMAT_YVYU:
8800 case DRM_FORMAT_VYUY:
8801 if (INTEL_INFO(dev)->gen < 5) {
8802 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8807 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8811 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8812 if (mode_cmd->offsets[0] != 0)
8815 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8816 intel_fb->obj = obj;
8818 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8820 DRM_ERROR("framebuffer init failed %d\n", ret);
8827 static struct drm_framebuffer *
8828 intel_user_framebuffer_create(struct drm_device *dev,
8829 struct drm_file *filp,
8830 struct drm_mode_fb_cmd2 *mode_cmd)
8832 struct drm_i915_gem_object *obj;
8834 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8835 mode_cmd->handles[0]));
8836 if (&obj->base == NULL)
8837 return ERR_PTR(-ENOENT);
8839 return intel_framebuffer_create(dev, mode_cmd, obj);
8842 static const struct drm_mode_config_funcs intel_mode_funcs = {
8843 .fb_create = intel_user_framebuffer_create,
8844 .output_poll_changed = intel_fb_output_poll_changed,
8847 /* Set up chip specific display functions */
8848 static void intel_init_display(struct drm_device *dev)
8850 struct drm_i915_private *dev_priv = dev->dev_private;
8853 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
8854 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8855 dev_priv->display.crtc_enable = haswell_crtc_enable;
8856 dev_priv->display.crtc_disable = haswell_crtc_disable;
8857 dev_priv->display.off = haswell_crtc_off;
8858 dev_priv->display.update_plane = ironlake_update_plane;
8859 } else if (HAS_PCH_SPLIT(dev)) {
8860 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
8861 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8862 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8863 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8864 dev_priv->display.off = ironlake_crtc_off;
8865 dev_priv->display.update_plane = ironlake_update_plane;
8866 } else if (IS_VALLEYVIEW(dev)) {
8867 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
8868 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8869 dev_priv->display.crtc_enable = valleyview_crtc_enable;
8870 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8871 dev_priv->display.off = i9xx_crtc_off;
8872 dev_priv->display.update_plane = i9xx_update_plane;
8874 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
8875 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8876 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8877 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8878 dev_priv->display.off = i9xx_crtc_off;
8879 dev_priv->display.update_plane = i9xx_update_plane;
8882 /* Returns the core display clock speed */
8883 if (IS_VALLEYVIEW(dev))
8884 dev_priv->display.get_display_clock_speed =
8885 valleyview_get_display_clock_speed;
8886 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8887 dev_priv->display.get_display_clock_speed =
8888 i945_get_display_clock_speed;
8889 else if (IS_I915G(dev))
8890 dev_priv->display.get_display_clock_speed =
8891 i915_get_display_clock_speed;
8892 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8893 dev_priv->display.get_display_clock_speed =
8894 i9xx_misc_get_display_clock_speed;
8895 else if (IS_I915GM(dev))
8896 dev_priv->display.get_display_clock_speed =
8897 i915gm_get_display_clock_speed;
8898 else if (IS_I865G(dev))
8899 dev_priv->display.get_display_clock_speed =
8900 i865_get_display_clock_speed;
8901 else if (IS_I85X(dev))
8902 dev_priv->display.get_display_clock_speed =
8903 i855_get_display_clock_speed;
8905 dev_priv->display.get_display_clock_speed =
8906 i830_get_display_clock_speed;
8908 if (HAS_PCH_SPLIT(dev)) {
8910 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8911 dev_priv->display.write_eld = ironlake_write_eld;
8912 } else if (IS_GEN6(dev)) {
8913 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8914 dev_priv->display.write_eld = ironlake_write_eld;
8915 } else if (IS_IVYBRIDGE(dev)) {
8916 /* FIXME: detect B0+ stepping and use auto training */
8917 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8918 dev_priv->display.write_eld = ironlake_write_eld;
8919 dev_priv->display.modeset_global_resources =
8920 ivb_modeset_global_resources;
8921 } else if (IS_HASWELL(dev)) {
8922 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8923 dev_priv->display.write_eld = haswell_write_eld;
8924 dev_priv->display.modeset_global_resources =
8925 haswell_modeset_global_resources;
8927 } else if (IS_G4X(dev)) {
8928 dev_priv->display.write_eld = g4x_write_eld;
8931 /* Default just returns -ENODEV to indicate unsupported */
8932 dev_priv->display.queue_flip = intel_default_queue_flip;
8934 switch (INTEL_INFO(dev)->gen) {
8936 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8940 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8945 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8949 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8952 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8958 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8959 * resume, or other times. This quirk makes sure that's the case for
8962 static void quirk_pipea_force(struct drm_device *dev)
8964 struct drm_i915_private *dev_priv = dev->dev_private;
8966 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8967 DRM_INFO("applying pipe a force quirk\n");
8971 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8973 static void quirk_ssc_force_disable(struct drm_device *dev)
8975 struct drm_i915_private *dev_priv = dev->dev_private;
8976 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8977 DRM_INFO("applying lvds SSC disable quirk\n");
8981 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8984 static void quirk_invert_brightness(struct drm_device *dev)
8986 struct drm_i915_private *dev_priv = dev->dev_private;
8987 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8988 DRM_INFO("applying inverted panel brightness quirk\n");
8991 struct intel_quirk {
8993 int subsystem_vendor;
8994 int subsystem_device;
8995 void (*hook)(struct drm_device *dev);
8998 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8999 struct intel_dmi_quirk {
9000 void (*hook)(struct drm_device *dev);
9001 const struct dmi_system_id (*dmi_id_list)[];
9004 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9006 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9010 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9012 .dmi_id_list = &(const struct dmi_system_id[]) {
9014 .callback = intel_dmi_reverse_brightness,
9015 .ident = "NCR Corporation",
9016 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9017 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9020 { } /* terminating entry */
9022 .hook = quirk_invert_brightness,
9026 static struct intel_quirk intel_quirks[] = {
9027 /* HP Mini needs pipe A force quirk (LP: #322104) */
9028 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9030 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9031 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9033 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9034 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9036 /* 830/845 need to leave pipe A & dpll A up */
9037 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9038 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9040 /* Lenovo U160 cannot use SSC on LVDS */
9041 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9043 /* Sony Vaio Y cannot use SSC on LVDS */
9044 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9046 /* Acer Aspire 5734Z must invert backlight brightness */
9047 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9049 /* Acer/eMachines G725 */
9050 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
9052 /* Acer/eMachines e725 */
9053 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
9055 /* Acer/Packard Bell NCL20 */
9056 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
9058 /* Acer Aspire 4736Z */
9059 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
9062 static void intel_init_quirks(struct drm_device *dev)
9064 struct pci_dev *d = dev->pdev;
9067 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9068 struct intel_quirk *q = &intel_quirks[i];
9070 if (d->device == q->device &&
9071 (d->subsystem_vendor == q->subsystem_vendor ||
9072 q->subsystem_vendor == PCI_ANY_ID) &&
9073 (d->subsystem_device == q->subsystem_device ||
9074 q->subsystem_device == PCI_ANY_ID))
9077 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9078 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9079 intel_dmi_quirks[i].hook(dev);
9083 /* Disable the VGA plane that we never use */
9084 static void i915_disable_vga(struct drm_device *dev)
9086 struct drm_i915_private *dev_priv = dev->dev_private;
9088 u32 vga_reg = i915_vgacntrl_reg(dev);
9090 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9091 outb(SR01, VGA_SR_INDEX);
9092 sr1 = inb(VGA_SR_DATA);
9093 outb(sr1 | 1<<5, VGA_SR_DATA);
9094 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9097 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9098 POSTING_READ(vga_reg);
9101 void intel_modeset_init_hw(struct drm_device *dev)
9103 intel_init_power_well(dev);
9105 intel_prepare_ddi(dev);
9107 intel_init_clock_gating(dev);
9109 mutex_lock(&dev->struct_mutex);
9110 intel_enable_gt_powersave(dev);
9111 mutex_unlock(&dev->struct_mutex);
9114 void intel_modeset_init(struct drm_device *dev)
9116 struct drm_i915_private *dev_priv = dev->dev_private;
9119 drm_mode_config_init(dev);
9121 dev->mode_config.min_width = 0;
9122 dev->mode_config.min_height = 0;
9124 dev->mode_config.preferred_depth = 24;
9125 dev->mode_config.prefer_shadow = 1;
9127 dev->mode_config.funcs = &intel_mode_funcs;
9129 intel_init_quirks(dev);
9133 if (INTEL_INFO(dev)->num_pipes == 0)
9136 intel_init_display(dev);
9139 dev->mode_config.max_width = 2048;
9140 dev->mode_config.max_height = 2048;
9141 } else if (IS_GEN3(dev)) {
9142 dev->mode_config.max_width = 4096;
9143 dev->mode_config.max_height = 4096;
9145 dev->mode_config.max_width = 8192;
9146 dev->mode_config.max_height = 8192;
9148 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
9150 DRM_DEBUG_KMS("%d display pipe%s available.\n",
9151 INTEL_INFO(dev)->num_pipes,
9152 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
9154 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
9155 intel_crtc_init(dev, i);
9156 for (j = 0; j < dev_priv->num_plane; j++) {
9157 ret = intel_plane_init(dev, i, j);
9159 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9160 pipe_name(i), sprite_name(i, j), ret);
9164 intel_cpu_pll_init(dev);
9165 intel_pch_pll_init(dev);
9167 /* Just disable it once at startup */
9168 i915_disable_vga(dev);
9169 intel_setup_outputs(dev);
9171 /* Just in case the BIOS is doing something questionable. */
9172 intel_disable_fbc(dev);
9176 intel_connector_break_all_links(struct intel_connector *connector)
9178 connector->base.dpms = DRM_MODE_DPMS_OFF;
9179 connector->base.encoder = NULL;
9180 connector->encoder->connectors_active = false;
9181 connector->encoder->base.crtc = NULL;
9184 static void intel_enable_pipe_a(struct drm_device *dev)
9186 struct intel_connector *connector;
9187 struct drm_connector *crt = NULL;
9188 struct intel_load_detect_pipe load_detect_temp;
9190 /* We can't just switch on the pipe A, we need to set things up with a
9191 * proper mode and output configuration. As a gross hack, enable pipe A
9192 * by enabling the load detect pipe once. */
9193 list_for_each_entry(connector,
9194 &dev->mode_config.connector_list,
9196 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9197 crt = &connector->base;
9205 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9206 intel_release_load_detect_pipe(crt, &load_detect_temp);
9212 intel_check_plane_mapping(struct intel_crtc *crtc)
9214 struct drm_device *dev = crtc->base.dev;
9215 struct drm_i915_private *dev_priv = dev->dev_private;
9218 if (INTEL_INFO(dev)->num_pipes == 1)
9221 reg = DSPCNTR(!crtc->plane);
9222 val = I915_READ(reg);
9224 if ((val & DISPLAY_PLANE_ENABLE) &&
9225 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9231 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9233 struct drm_device *dev = crtc->base.dev;
9234 struct drm_i915_private *dev_priv = dev->dev_private;
9237 /* Clear any frame start delays used for debugging left by the BIOS */
9238 reg = PIPECONF(crtc->config.cpu_transcoder);
9239 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9241 /* We need to sanitize the plane -> pipe mapping first because this will
9242 * disable the crtc (and hence change the state) if it is wrong. Note
9243 * that gen4+ has a fixed plane -> pipe mapping. */
9244 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9245 struct intel_connector *connector;
9248 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9249 crtc->base.base.id);
9251 /* Pipe has the wrong plane attached and the plane is active.
9252 * Temporarily change the plane mapping and disable everything
9254 plane = crtc->plane;
9255 crtc->plane = !plane;
9256 dev_priv->display.crtc_disable(&crtc->base);
9257 crtc->plane = plane;
9259 /* ... and break all links. */
9260 list_for_each_entry(connector, &dev->mode_config.connector_list,
9262 if (connector->encoder->base.crtc != &crtc->base)
9265 intel_connector_break_all_links(connector);
9268 WARN_ON(crtc->active);
9269 crtc->base.enabled = false;
9272 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9273 crtc->pipe == PIPE_A && !crtc->active) {
9274 /* BIOS forgot to enable pipe A, this mostly happens after
9275 * resume. Force-enable the pipe to fix this, the update_dpms
9276 * call below we restore the pipe to the right state, but leave
9277 * the required bits on. */
9278 intel_enable_pipe_a(dev);
9281 /* Adjust the state of the output pipe according to whether we
9282 * have active connectors/encoders. */
9283 intel_crtc_update_dpms(&crtc->base);
9285 if (crtc->active != crtc->base.enabled) {
9286 struct intel_encoder *encoder;
9288 /* This can happen either due to bugs in the get_hw_state
9289 * functions or because the pipe is force-enabled due to the
9291 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9293 crtc->base.enabled ? "enabled" : "disabled",
9294 crtc->active ? "enabled" : "disabled");
9296 crtc->base.enabled = crtc->active;
9298 /* Because we only establish the connector -> encoder ->
9299 * crtc links if something is active, this means the
9300 * crtc is now deactivated. Break the links. connector
9301 * -> encoder links are only establish when things are
9302 * actually up, hence no need to break them. */
9303 WARN_ON(crtc->active);
9305 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9306 WARN_ON(encoder->connectors_active);
9307 encoder->base.crtc = NULL;
9312 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9314 struct intel_connector *connector;
9315 struct drm_device *dev = encoder->base.dev;
9317 /* We need to check both for a crtc link (meaning that the
9318 * encoder is active and trying to read from a pipe) and the
9319 * pipe itself being active. */
9320 bool has_active_crtc = encoder->base.crtc &&
9321 to_intel_crtc(encoder->base.crtc)->active;
9323 if (encoder->connectors_active && !has_active_crtc) {
9324 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9325 encoder->base.base.id,
9326 drm_get_encoder_name(&encoder->base));
9328 /* Connector is active, but has no active pipe. This is
9329 * fallout from our resume register restoring. Disable
9330 * the encoder manually again. */
9331 if (encoder->base.crtc) {
9332 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9333 encoder->base.base.id,
9334 drm_get_encoder_name(&encoder->base));
9335 encoder->disable(encoder);
9338 /* Inconsistent output/port/pipe state happens presumably due to
9339 * a bug in one of the get_hw_state functions. Or someplace else
9340 * in our code, like the register restore mess on resume. Clamp
9341 * things to off as a safer default. */
9342 list_for_each_entry(connector,
9343 &dev->mode_config.connector_list,
9345 if (connector->encoder != encoder)
9348 intel_connector_break_all_links(connector);
9351 /* Enabled encoders without active connectors will be fixed in
9352 * the crtc fixup. */
9355 void i915_redisable_vga(struct drm_device *dev)
9357 struct drm_i915_private *dev_priv = dev->dev_private;
9358 u32 vga_reg = i915_vgacntrl_reg(dev);
9360 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9361 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9362 i915_disable_vga(dev);
9366 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9367 * and i915 state tracking structures. */
9368 void intel_modeset_setup_hw_state(struct drm_device *dev,
9371 struct drm_i915_private *dev_priv = dev->dev_private;
9374 struct drm_plane *plane;
9375 struct intel_crtc *crtc;
9376 struct intel_encoder *encoder;
9377 struct intel_connector *connector;
9380 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9382 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9383 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9384 case TRANS_DDI_EDP_INPUT_A_ON:
9385 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9388 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9391 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9395 /* A bogus value has been programmed, disable
9397 WARN(1, "Bogus eDP source %08x\n", tmp);
9398 intel_ddi_disable_transcoder_func(dev_priv,
9403 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9404 crtc->config.cpu_transcoder = TRANSCODER_EDP;
9406 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9412 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9414 enum transcoder tmp = crtc->config.cpu_transcoder;
9415 memset(&crtc->config, 0, sizeof(crtc->config));
9416 crtc->config.cpu_transcoder = tmp;
9418 crtc->active = dev_priv->display.get_pipe_config(crtc,
9421 crtc->base.enabled = crtc->active;
9423 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9425 crtc->active ? "enabled" : "disabled");
9429 intel_ddi_setup_hw_pll_state(dev);
9431 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9435 if (encoder->get_hw_state(encoder, &pipe)) {
9436 encoder->base.crtc =
9437 dev_priv->pipe_to_crtc_mapping[pipe];
9439 encoder->base.crtc = NULL;
9442 encoder->connectors_active = false;
9443 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9444 encoder->base.base.id,
9445 drm_get_encoder_name(&encoder->base),
9446 encoder->base.crtc ? "enabled" : "disabled",
9450 list_for_each_entry(connector, &dev->mode_config.connector_list,
9452 if (connector->get_hw_state(connector)) {
9453 connector->base.dpms = DRM_MODE_DPMS_ON;
9454 connector->encoder->connectors_active = true;
9455 connector->base.encoder = &connector->encoder->base;
9457 connector->base.dpms = DRM_MODE_DPMS_OFF;
9458 connector->base.encoder = NULL;
9460 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9461 connector->base.base.id,
9462 drm_get_connector_name(&connector->base),
9463 connector->base.encoder ? "enabled" : "disabled");
9466 /* HW state is read out, now we need to sanitize this mess. */
9467 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9469 intel_sanitize_encoder(encoder);
9472 for_each_pipe(pipe) {
9473 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9474 intel_sanitize_crtc(crtc);
9477 if (force_restore) {
9479 * We need to use raw interfaces for restoring state to avoid
9480 * checking (bogus) intermediate states.
9482 for_each_pipe(pipe) {
9483 struct drm_crtc *crtc =
9484 dev_priv->pipe_to_crtc_mapping[pipe];
9486 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9489 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9490 intel_plane_restore(plane);
9492 i915_redisable_vga(dev);
9494 intel_modeset_update_staged_output_state(dev);
9497 intel_modeset_check_state(dev);
9499 drm_mode_config_reset(dev);
9502 void intel_modeset_gem_init(struct drm_device *dev)
9504 intel_modeset_init_hw(dev);
9506 intel_setup_overlay(dev);
9508 intel_modeset_setup_hw_state(dev, false);
9511 void intel_modeset_cleanup(struct drm_device *dev)
9513 struct drm_i915_private *dev_priv = dev->dev_private;
9514 struct drm_crtc *crtc;
9515 struct intel_crtc *intel_crtc;
9518 * Interrupts and polling as the first thing to avoid creating havoc.
9519 * Too much stuff here (turning of rps, connectors, ...) would
9520 * experience fancy races otherwise.
9522 drm_irq_uninstall(dev);
9523 cancel_work_sync(&dev_priv->hotplug_work);
9525 * Due to the hpd irq storm handling the hotplug work can re-arm the
9526 * poll handlers. Hence disable polling after hpd handling is shut down.
9528 drm_kms_helper_poll_fini(dev);
9530 mutex_lock(&dev->struct_mutex);
9532 intel_unregister_dsm_handler();
9534 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9535 /* Skip inactive CRTCs */
9539 intel_crtc = to_intel_crtc(crtc);
9540 intel_increase_pllclock(crtc);
9543 intel_disable_fbc(dev);
9545 intel_disable_gt_powersave(dev);
9547 ironlake_teardown_rc6(dev);
9549 mutex_unlock(&dev->struct_mutex);
9551 /* flush any delayed tasks or pending work */
9552 flush_scheduled_work();
9554 /* destroy backlight, if any, before the connectors */
9555 intel_panel_destroy_backlight(dev);
9557 drm_mode_config_cleanup(dev);
9559 intel_cleanup_overlay(dev);
9563 * Return which encoder is currently attached for connector.
9565 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9567 return &intel_attached_encoder(connector)->base;
9570 void intel_connector_attach_encoder(struct intel_connector *connector,
9571 struct intel_encoder *encoder)
9573 connector->encoder = encoder;
9574 drm_mode_connector_attach_encoder(&connector->base,
9579 * set vga decode state - true == enable VGA decode
9581 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9583 struct drm_i915_private *dev_priv = dev->dev_private;
9586 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9588 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9590 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9591 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9595 #ifdef CONFIG_DEBUG_FS
9596 #include <linux/seq_file.h>
9598 struct intel_display_error_state {
9599 struct intel_cursor_error_state {
9604 } cursor[I915_MAX_PIPES];
9606 struct intel_pipe_error_state {
9616 } pipe[I915_MAX_PIPES];
9618 struct intel_plane_error_state {
9626 } plane[I915_MAX_PIPES];
9629 struct intel_display_error_state *
9630 intel_display_capture_error_state(struct drm_device *dev)
9632 drm_i915_private_t *dev_priv = dev->dev_private;
9633 struct intel_display_error_state *error;
9634 enum transcoder cpu_transcoder;
9637 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9642 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9644 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9645 error->cursor[i].control = I915_READ(CURCNTR(i));
9646 error->cursor[i].position = I915_READ(CURPOS(i));
9647 error->cursor[i].base = I915_READ(CURBASE(i));
9649 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9650 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9651 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9654 error->plane[i].control = I915_READ(DSPCNTR(i));
9655 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9656 if (INTEL_INFO(dev)->gen <= 3) {
9657 error->plane[i].size = I915_READ(DSPSIZE(i));
9658 error->plane[i].pos = I915_READ(DSPPOS(i));
9660 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9661 error->plane[i].addr = I915_READ(DSPADDR(i));
9662 if (INTEL_INFO(dev)->gen >= 4) {
9663 error->plane[i].surface = I915_READ(DSPSURF(i));
9664 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9667 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9668 error->pipe[i].source = I915_READ(PIPESRC(i));
9669 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9670 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9671 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9672 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9673 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9674 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9681 intel_display_print_error_state(struct seq_file *m,
9682 struct drm_device *dev,
9683 struct intel_display_error_state *error)
9687 seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
9689 seq_printf(m, "Pipe [%d]:\n", i);
9690 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9691 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9692 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9693 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9694 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9695 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9696 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9697 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9699 seq_printf(m, "Plane [%d]:\n", i);
9700 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9701 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9702 if (INTEL_INFO(dev)->gen <= 3) {
9703 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9704 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9706 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9707 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9708 if (INTEL_INFO(dev)->gen >= 4) {
9709 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9710 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9713 seq_printf(m, "Cursor [%d]:\n", i);
9714 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9715 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9716 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);