drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_edid.h>
  35 #include "intel_drv.h"
  36 #include <drm/i915_drm.h>
  37 #include "i915_drv.h"
  38
  39 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  40
  41 struct dp_link_dpll {
  42         int link_bw;
  43         struct dpll dpll;
  44 };
  45
  46 static const struct dp_link_dpll gen4_dpll[] = {
  47         { DP_LINK_BW_1_62,
  48                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  49         { DP_LINK_BW_2_7,
  50                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  51 };
  52
  53 static const struct dp_link_dpll pch_dpll[] = {
  54         { DP_LINK_BW_1_62,
  55                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  56         { DP_LINK_BW_2_7,
  57                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  58 };
  59
  60 static const struct dp_link_dpll vlv_dpll[] = {
  61         { DP_LINK_BW_1_62,
  62                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  63         { DP_LINK_BW_2_7,
  64                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  65 };
  66
  67 /**
  68  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  69  * @intel_dp: DP struct
  70  *
  71  * If a CPU or PCH DP output is attached to an eDP panel, this function
  72  * will return true, and false otherwise.
  73  */
  74 static bool is_edp(struct intel_dp *intel_dp)
  75 {
  76         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  77
  78         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
  79 }
  80
  81 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
  82 {
  83         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  84
  85         return intel_dig_port->base.base.dev;
  86 }
  87
  88 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
  89 {
  90         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
  91 }
  92
  93 static void intel_dp_link_down(struct intel_dp *intel_dp);
  94 static void edp_panel_vdd_on(struct intel_dp *intel_dp);
  95 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
  96
  97 static int
  98 intel_dp_max_link_bw(struct intel_dp *intel_dp)
  99 {
 100         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 101
 102         switch (max_link_bw) {
 103         case DP_LINK_BW_1_62:
 104         case DP_LINK_BW_2_7:
 105                 break;
 106         case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
 107                 max_link_bw = DP_LINK_BW_2_7;
 108                 break;
 109         default:
 110                 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
 111                      max_link_bw);
 112                 max_link_bw = DP_LINK_BW_1_62;
 113                 break;
 114         }
 115         return max_link_bw;
 116 }
 117
 118 /*
 119  * The units on the numbers in the next two are... bizarre.  Examples will
 120  * make it clearer; this one parallels an example in the eDP spec.
 121  *
 122  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 123  *
 124  *     270000 * 1 * 8 / 10 == 216000
 125  *
 126  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 127  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 128  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 129  * 119000.  At 18bpp that's 2142000 kilobits per second.
 130  *
 131  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 132  * get the result in decakilobits instead of kilobits.
 133  */
 134
 135 static int
 136 intel_dp_link_required(int pixel_clock, int bpp)
 137 {
 138         return (pixel_clock * bpp + 9) / 10;
 139 }
 140
 141 static int
 142 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 143 {
 144         return (max_link_clock * max_lanes * 8) / 10;
 145 }
 146
 147 static enum drm_mode_status
 148 intel_dp_mode_valid(struct drm_connector *connector,
 149                     struct drm_display_mode *mode)
 150 {
 151         struct intel_dp *intel_dp = intel_attached_dp(connector);
 152         struct intel_connector *intel_connector = to_intel_connector(connector);
 153         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 154         int target_clock = mode->clock;
 155         int max_rate, mode_rate, max_lanes, max_link_clock;
 156
 157         if (is_edp(intel_dp) && fixed_mode) {
 158                 if (mode->hdisplay > fixed_mode->hdisplay)
 159                         return MODE_PANEL;
 160
 161                 if (mode->vdisplay > fixed_mode->vdisplay)
 162                         return MODE_PANEL;
 163
 164                 target_clock = fixed_mode->clock;
 165         }
 166
 167         max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
 168         max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
 169
 170         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 171         mode_rate = intel_dp_link_required(target_clock, 18);
 172
 173         if (mode_rate > max_rate)
 174                 return MODE_CLOCK_HIGH;
 175
 176         if (mode->clock < 10000)
 177                 return MODE_CLOCK_LOW;
 178
 179         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 180                 return MODE_H_ILLEGAL;
 181
 182         return MODE_OK;
 183 }
 184
 185 static uint32_t
 186 pack_aux(uint8_t *src, int src_bytes)
 187 {
 188         int     i;
 189         uint32_t v = 0;
 190
 191         if (src_bytes > 4)
 192                 src_bytes = 4;
 193         for (i = 0; i < src_bytes; i++)
 194                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 195         return v;
 196 }
 197
 198 static void
 199 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 200 {
 201         int i;
 202         if (dst_bytes > 4)
 203                 dst_bytes = 4;
 204         for (i = 0; i < dst_bytes; i++)
 205                 dst[i] = src >> ((3-i) * 8);
 206 }
 207
 208 /* hrawclock is 1/4 the FSB frequency */
 209 static int
 210 intel_hrawclk(struct drm_device *dev)
 211 {
 212         struct drm_i915_private *dev_priv = dev->dev_private;
 213         uint32_t clkcfg;
 214
 215         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 216         if (IS_VALLEYVIEW(dev))
 217                 return 200;
 218
 219         clkcfg = I915_READ(CLKCFG);
 220         switch (clkcfg & CLKCFG_FSB_MASK) {
 221         case CLKCFG_FSB_400:
 222                 return 100;
 223         case CLKCFG_FSB_533:
 224                 return 133;
 225         case CLKCFG_FSB_667:
 226                 return 166;
 227         case CLKCFG_FSB_800:
 228                 return 200;
 229         case CLKCFG_FSB_1067:
 230                 return 266;
 231         case CLKCFG_FSB_1333:
 232                 return 333;
 233         /* these two are just a guess; one of them might be right */
 234         case CLKCFG_FSB_1600:
 235         case CLKCFG_FSB_1600_ALT:
 236                 return 400;
 237         default:
 238                 return 133;
 239         }
 240 }
 241
 242 static void
 243 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 244                                     struct intel_dp *intel_dp,
 245                                     struct edp_power_seq *out);
 246 static void
 247 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 248                                               struct intel_dp *intel_dp,
 249                                               struct edp_power_seq *out);
 250
 251 static enum pipe
 252 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 253 {
 254         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 255         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
 256         struct drm_device *dev = intel_dig_port->base.base.dev;
 257         struct drm_i915_private *dev_priv = dev->dev_private;
 258         enum port port = intel_dig_port->port;
 259         enum pipe pipe;
 260
 261         /* modeset should have pipe */
 262         if (crtc)
 263                 return to_intel_crtc(crtc)->pipe;
 264
 265         /* init time, try to find a pipe with this port selected */
 266         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 267                 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
 268                         PANEL_PORT_SELECT_MASK;
 269                 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
 270                         return pipe;
 271                 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
 272                         return pipe;
 273         }
 274
 275         /* shrug */
 276         return PIPE_A;
 277 }
 278
 279 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
 280 {
 281         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 282
 283         if (HAS_PCH_SPLIT(dev))
 284                 return PCH_PP_CONTROL;
 285         else
 286                 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
 287 }
 288
 289 static u32 _pp_stat_reg(struct intel_dp *intel_dp)
 290 {
 291         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 292
 293         if (HAS_PCH_SPLIT(dev))
 294                 return PCH_PP_STATUS;
 295         else
 296                 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
 297 }
 298
 299 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 300 {
 301         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 302         struct drm_i915_private *dev_priv = dev->dev_private;
 303
 304         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 305 }
 306
 307 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 308 {
 309         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 310         struct drm_i915_private *dev_priv = dev->dev_private;
 311
 312         return (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
 313 }
 314
 315 static void
 316 intel_dp_check_edp(struct intel_dp *intel_dp)
 317 {
 318         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 319         struct drm_i915_private *dev_priv = dev->dev_private;
 320
 321         if (!is_edp(intel_dp))
 322                 return;
 323
 324         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 325                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 326                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 327                               I915_READ(_pp_stat_reg(intel_dp)),
 328                               I915_READ(_pp_ctrl_reg(intel_dp)));
 329         }
 330 }
 331
 332 static uint32_t
 333 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 334 {
 335         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 336         struct drm_device *dev = intel_dig_port->base.base.dev;
 337         struct drm_i915_private *dev_priv = dev->dev_private;
 338         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 339         uint32_t status;
 340         bool done;
 341
 342 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 343         if (has_aux_irq)
 344                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 345                                           msecs_to_jiffies_timeout(10));
 346         else
 347                 done = wait_for_atomic(C, 10) == 0;
 348         if (!done)
 349                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 350                           has_aux_irq);
 351 #undef C
 352
 353         return status;
 354 }
 355
 356 static uint32_t get_aux_clock_divider(struct intel_dp *intel_dp,
 357                                       int index)
 358 {
 359         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 360         struct drm_device *dev = intel_dig_port->base.base.dev;
 361         struct drm_i915_private *dev_priv = dev->dev_private;
 362
 363         /* The clock divider is based off the hrawclk,
 364          * and would like to run at 2MHz. So, take the
 365          * hrawclk value and divide by 2 and use that
 366          *
 367          * Note that PCH attached eDP panels should use a 125MHz input
 368          * clock divider.
 369          */
 370         if (IS_VALLEYVIEW(dev)) {
 371                 return index ? 0 : 100;
 372         } else if (intel_dig_port->port == PORT_A) {
 373                 if (index)
 374                         return 0;
 375                 if (HAS_DDI(dev))
 376                         return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
 377                 else if (IS_GEN6(dev) || IS_GEN7(dev))
 378                         return 200; /* SNB & IVB eDP input clock at 400Mhz */
 379                 else
 380                         return 225; /* eDP input clock at 450Mhz */
 381         } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 382                 /* Workaround for non-ULT HSW */
 383                 switch (index) {
 384                 case 0: return 63;
 385                 case 1: return 72;
 386                 default: return 0;
 387                 }
 388         } else if (HAS_PCH_SPLIT(dev)) {
 389                 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 390         } else {
 391                 return index ? 0 :intel_hrawclk(dev) / 2;
 392         }
 393 }
 394
 395 static int
 396 intel_dp_aux_ch(struct intel_dp *intel_dp,
 397                 uint8_t *send, int send_bytes,
 398                 uint8_t *recv, int recv_size)
 399 {
 400         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 401         struct drm_device *dev = intel_dig_port->base.base.dev;
 402         struct drm_i915_private *dev_priv = dev->dev_private;
 403         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 404         uint32_t ch_data = ch_ctl + 4;
 405         uint32_t aux_clock_divider;
 406         int i, ret, recv_bytes;
 407         uint32_t status;
 408         int try, precharge, clock = 0;
 409         bool has_aux_irq = true;
 410         uint32_t timeout;
 411
 412         /* dp aux is extremely sensitive to irq latency, hence request the
 413          * lowest possible wakeup latency and so prevent the cpu from going into
 414          * deep sleep states.
 415          */
 416         pm_qos_update_request(&dev_priv->pm_qos, 0);
 417
 418         intel_dp_check_edp(intel_dp);
 419
 420         if (IS_GEN6(dev))
 421                 precharge = 3;
 422         else
 423                 precharge = 5;
 424
 425         if (IS_BROADWELL(dev) && ch_ctl == DPA_AUX_CH_CTL)
 426                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
 427         else
 428                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
 429
 430         intel_aux_display_runtime_get(dev_priv);
 431
 432         /* Try to wait for any previous AUX channel activity */
 433         for (try = 0; try < 3; try++) {
 434                 status = I915_READ_NOTRACE(ch_ctl);
 435                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 436                         break;
 437                 msleep(1);
 438         }
 439
 440         if (try == 3) {
 441                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 442                      I915_READ(ch_ctl));
 443                 ret = -EBUSY;
 444                 goto out;
 445         }
 446
 447         /* Only 5 data registers! */
 448         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
 449                 ret = -E2BIG;
 450                 goto out;
 451         }
 452
 453         while ((aux_clock_divider = get_aux_clock_divider(intel_dp, clock++))) {
 454                 /* Must try at least 3 times according to DP spec */
 455                 for (try = 0; try < 5; try++) {
 456                         /* Load the send data into the aux channel data registers */
 457                         for (i = 0; i < send_bytes; i += 4)
 458                                 I915_WRITE(ch_data + i,
 459                                            pack_aux(send + i, send_bytes - i));
 460
 461                         /* Send the command and wait for it to complete */
 462                         I915_WRITE(ch_ctl,
 463                                    DP_AUX_CH_CTL_SEND_BUSY |
 464                                    (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 465                                    timeout |
 466                                    (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 467                                    (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 468                                    (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 469                                    DP_AUX_CH_CTL_DONE |
 470                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
 471                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
 472
 473                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
 474
 475                         /* Clear done status and any errors */
 476                         I915_WRITE(ch_ctl,
 477                                    status |
 478                                    DP_AUX_CH_CTL_DONE |
 479                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
 480                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
 481
 482                         if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
 483                                       DP_AUX_CH_CTL_RECEIVE_ERROR))
 484                                 continue;
 485                         if (status & DP_AUX_CH_CTL_DONE)
 486                                 break;
 487                 }
 488                 if (status & DP_AUX_CH_CTL_DONE)
 489                         break;
 490         }
 491
 492         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 493                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 494                 ret = -EBUSY;
 495                 goto out;
 496         }
 497
 498         /* Check for timeout or receive error.
 499          * Timeouts occur when the sink is not connected
 500          */
 501         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 502                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 503                 ret = -EIO;
 504                 goto out;
 505         }
 506
 507         /* Timeouts occur when the device isn't connected, so they're
 508          * "normal" -- don't fill the kernel log with these */
 509         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 510                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 511                 ret = -ETIMEDOUT;
 512                 goto out;
 513         }
 514
 515         /* Unload any bytes sent back from the other side */
 516         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 517                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 518         if (recv_bytes > recv_size)
 519                 recv_bytes = recv_size;
 520
 521         for (i = 0; i < recv_bytes; i += 4)
 522                 unpack_aux(I915_READ(ch_data + i),
 523                            recv + i, recv_bytes - i);
 524
 525         ret = recv_bytes;
 526 out:
 527         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 528         intel_aux_display_runtime_put(dev_priv);
 529
 530         return ret;
 531 }
 532
 533 /* Write data to the aux channel in native mode */
 534 static int
 535 intel_dp_aux_native_write(struct intel_dp *intel_dp,
 536                           uint16_t address, uint8_t *send, int send_bytes)
 537 {
 538         int ret;
 539         uint8_t msg[20];
 540         int msg_bytes;
 541         uint8_t ack;
 542
 543         if (WARN_ON(send_bytes > 16))
 544                 return -E2BIG;
 545
 546         intel_dp_check_edp(intel_dp);
 547         msg[0] = DP_AUX_NATIVE_WRITE << 4;
 548         msg[1] = address >> 8;
 549         msg[2] = address & 0xff;
 550         msg[3] = send_bytes - 1;
 551         memcpy(&msg[4], send, send_bytes);
 552         msg_bytes = send_bytes + 4;
 553         for (;;) {
 554                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 555                 if (ret < 0)
 556                         return ret;
 557                 ack >>= 4;
 558                 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK)
 559                         break;
 560                 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
 561                         udelay(100);
 562                 else
 563                         return -EIO;
 564         }
 565         return send_bytes;
 566 }
 567
 568 /* Write a single byte to the aux channel in native mode */
 569 static int
 570 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 571                             uint16_t address, uint8_t byte)
 572 {
 573         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 574 }
 575
 576 /* read bytes from a native aux channel */
 577 static int
 578 intel_dp_aux_native_read(struct intel_dp *intel_dp,
 579                          uint16_t address, uint8_t *recv, int recv_bytes)
 580 {
 581         uint8_t msg[4];
 582         int msg_bytes;
 583         uint8_t reply[20];
 584         int reply_bytes;
 585         uint8_t ack;
 586         int ret;
 587
 588         if (WARN_ON(recv_bytes > 19))
 589                 return -E2BIG;
 590
 591         intel_dp_check_edp(intel_dp);
 592         msg[0] = DP_AUX_NATIVE_READ << 4;
 593         msg[1] = address >> 8;
 594         msg[2] = address & 0xff;
 595         msg[3] = recv_bytes - 1;
 596
 597         msg_bytes = 4;
 598         reply_bytes = recv_bytes + 1;
 599
 600         for (;;) {
 601                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 602                                       reply, reply_bytes);
 603                 if (ret == 0)
 604                         return -EPROTO;
 605                 if (ret < 0)
 606                         return ret;
 607                 ack = reply[0] >> 4;
 608                 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) {
 609                         memcpy(recv, reply + 1, ret - 1);
 610                         return ret - 1;
 611                 }
 612                 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
 613                         udelay(100);
 614                 else
 615                         return -EIO;
 616         }
 617 }
 618
 619 static int
 620 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 621                     uint8_t write_byte, uint8_t *read_byte)
 622 {
 623         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 624         struct intel_dp *intel_dp = container_of(adapter,
 625                                                 struct intel_dp,
 626                                                 adapter);
 627         uint16_t address = algo_data->address;
 628         uint8_t msg[5];
 629         uint8_t reply[2];
 630         unsigned retry;
 631         int msg_bytes;
 632         int reply_bytes;
 633         int ret;
 634
 635         edp_panel_vdd_on(intel_dp);
 636         intel_dp_check_edp(intel_dp);
 637         /* Set up the command byte */
 638         if (mode & MODE_I2C_READ)
 639                 msg[0] = DP_AUX_I2C_READ << 4;
 640         else
 641                 msg[0] = DP_AUX_I2C_WRITE << 4;
 642
 643         if (!(mode & MODE_I2C_STOP))
 644                 msg[0] |= DP_AUX_I2C_MOT << 4;
 645
 646         msg[1] = address >> 8;
 647         msg[2] = address;
 648
 649         switch (mode) {
 650         case MODE_I2C_WRITE:
 651                 msg[3] = 0;
 652                 msg[4] = write_byte;
 653                 msg_bytes = 5;
 654                 reply_bytes = 1;
 655                 break;
 656         case MODE_I2C_READ:
 657                 msg[3] = 0;
 658                 msg_bytes = 4;
 659                 reply_bytes = 2;
 660                 break;
 661         default:
 662                 msg_bytes = 3;
 663                 reply_bytes = 1;
 664                 break;
 665         }
 666
 667         /*
 668          * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is
 669          * required to retry at least seven times upon receiving AUX_DEFER
 670          * before giving up the AUX transaction.
 671          */
 672         for (retry = 0; retry < 7; retry++) {
 673                 ret = intel_dp_aux_ch(intel_dp,
 674                                       msg, msg_bytes,
 675                                       reply, reply_bytes);
 676                 if (ret < 0) {
 677                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 678                         goto out;
 679                 }
 680
 681                 switch ((reply[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK) {
 682                 case DP_AUX_NATIVE_REPLY_ACK:
 683                         /* I2C-over-AUX Reply field is only valid
 684                          * when paired with AUX ACK.
 685                          */
 686                         break;
 687                 case DP_AUX_NATIVE_REPLY_NACK:
 688                         DRM_DEBUG_KMS("aux_ch native nack\n");
 689                         ret = -EREMOTEIO;
 690                         goto out;
 691                 case DP_AUX_NATIVE_REPLY_DEFER:
 692                         /*
 693                          * For now, just give more slack to branch devices. We
 694                          * could check the DPCD for I2C bit rate capabilities,
 695                          * and if available, adjust the interval. We could also
 696                          * be more careful with DP-to-Legacy adapters where a
 697                          * long legacy cable may force very low I2C bit rates.
 698                          */
 699                         if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
 700                             DP_DWN_STRM_PORT_PRESENT)
 701                                 usleep_range(500, 600);
 702                         else
 703                                 usleep_range(300, 400);
 704                         continue;
 705                 default:
 706                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
 707                                   reply[0]);
 708                         ret = -EREMOTEIO;
 709                         goto out;
 710                 }
 711
 712                 switch ((reply[0] >> 4) & DP_AUX_I2C_REPLY_MASK) {
 713                 case DP_AUX_I2C_REPLY_ACK:
 714                         if (mode == MODE_I2C_READ) {
 715                                 *read_byte = reply[1];
 716                         }
 717                         ret = reply_bytes - 1;
 718                         goto out;
 719                 case DP_AUX_I2C_REPLY_NACK:
 720                         DRM_DEBUG_KMS("aux_i2c nack\n");
 721                         ret = -EREMOTEIO;
 722                         goto out;
 723                 case DP_AUX_I2C_REPLY_DEFER:
 724                         DRM_DEBUG_KMS("aux_i2c defer\n");
 725                         udelay(100);
 726                         break;
 727                 default:
 728                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
 729                         ret = -EREMOTEIO;
 730                         goto out;
 731                 }
 732         }
 733
 734         DRM_ERROR("too many retries, giving up\n");
 735         ret = -EREMOTEIO;
 736
 737 out:
 738         edp_panel_vdd_off(intel_dp, false);
 739         return ret;
 740 }
 741
 742 static int
 743 intel_dp_i2c_init(struct intel_dp *intel_dp,
 744                   struct intel_connector *intel_connector, const char *name)
 745 {
 746         int     ret;
 747
 748         DRM_DEBUG_KMS("i2c_init %s\n", name);
 749         intel_dp->algo.running = false;
 750         intel_dp->algo.address = 0;
 751         intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
 752
 753         memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
 754         intel_dp->adapter.owner = THIS_MODULE;
 755         intel_dp->adapter.class = I2C_CLASS_DDC;
 756         strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
 757         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
 758         intel_dp->adapter.algo_data = &intel_dp->algo;
 759         intel_dp->adapter.dev.parent = intel_connector->base.kdev;
 760
 761         ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
 762         return ret;
 763 }
 764
 765 static void
 766 intel_dp_set_clock(struct intel_encoder *encoder,
 767                    struct intel_crtc_config *pipe_config, int link_bw)
 768 {
 769         struct drm_device *dev = encoder->base.dev;
 770         const struct dp_link_dpll *divisor = NULL;
 771         int i, count = 0;
 772
 773         if (IS_G4X(dev)) {
 774                 divisor = gen4_dpll;
 775                 count = ARRAY_SIZE(gen4_dpll);
 776         } else if (IS_HASWELL(dev)) {
 777                 /* Haswell has special-purpose DP DDI clocks. */
 778         } else if (HAS_PCH_SPLIT(dev)) {
 779                 divisor = pch_dpll;
 780                 count = ARRAY_SIZE(pch_dpll);
 781         } else if (IS_VALLEYVIEW(dev)) {
 782                 divisor = vlv_dpll;
 783                 count = ARRAY_SIZE(vlv_dpll);
 784         }
 785
 786         if (divisor && count) {
 787                 for (i = 0; i < count; i++) {
 788                         if (link_bw == divisor[i].link_bw) {
 789                                 pipe_config->dpll = divisor[i].dpll;
 790                                 pipe_config->clock_set = true;
 791                                 break;
 792                         }
 793                 }
 794         }
 795 }
 796
 797 bool
 798 intel_dp_compute_config(struct intel_encoder *encoder,
 799                         struct intel_crtc_config *pipe_config)
 800 {
 801         struct drm_device *dev = encoder->base.dev;
 802         struct drm_i915_private *dev_priv = dev->dev_private;
 803         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
 804         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 805         enum port port = dp_to_dig_port(intel_dp)->port;
 806         struct intel_crtc *intel_crtc = encoder->new_crtc;
 807         struct intel_connector *intel_connector = intel_dp->attached_connector;
 808         int lane_count, clock;
 809         int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
 810         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
 811         int bpp, mode_rate;
 812         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 813         int link_avail, link_clock;
 814
 815         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
 816                 pipe_config->has_pch_encoder = true;
 817
 818         pipe_config->has_dp_encoder = true;
 819
 820         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
 821                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
 822                                        adjusted_mode);
 823                 if (!HAS_PCH_SPLIT(dev))
 824                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
 825                                                  intel_connector->panel.fitting_mode);
 826                 else
 827                         intel_pch_panel_fitting(intel_crtc, pipe_config,
 828                                                 intel_connector->panel.fitting_mode);
 829         }
 830
 831         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 832                 return false;
 833
 834         DRM_DEBUG_KMS("DP link computation with max lane count %i "
 835                       "max bw %02x pixel clock %iKHz\n",
 836                       max_lane_count, bws[max_clock],
 837                       adjusted_mode->crtc_clock);
 838
 839         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
 840          * bpc in between. */
 841         bpp = pipe_config->pipe_bpp;
 842         if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
 843             dev_priv->vbt.edp_bpp < bpp) {
 844                 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
 845                               dev_priv->vbt.edp_bpp);
 846                 bpp = dev_priv->vbt.edp_bpp;
 847         }
 848
 849         for (; bpp >= 6*3; bpp -= 2*3) {
 850                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
 851                                                    bpp);
 852
 853                 for (clock = 0; clock <= max_clock; clock++) {
 854                         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 855                                 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
 856                                 link_avail = intel_dp_max_data_rate(link_clock,
 857                                                                     lane_count);
 858
 859                                 if (mode_rate <= link_avail) {
 860                                         goto found;
 861                                 }
 862                         }
 863                 }
 864         }
 865
 866         return false;
 867
 868 found:
 869         if (intel_dp->color_range_auto) {
 870                 /*
 871                  * See:
 872                  * CEA-861-E - 5.1 Default Encoding Parameters
 873                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
 874                  */
 875                 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
 876                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
 877                 else
 878                         intel_dp->color_range = 0;
 879         }
 880
 881         if (intel_dp->color_range)
 882                 pipe_config->limited_color_range = true;
 883
 884         intel_dp->link_bw = bws[clock];
 885         intel_dp->lane_count = lane_count;
 886         pipe_config->pipe_bpp = bpp;
 887         pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
 888
 889         DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
 890                       intel_dp->link_bw, intel_dp->lane_count,
 891                       pipe_config->port_clock, bpp);
 892         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
 893                       mode_rate, link_avail);
 894
 895         intel_link_compute_m_n(bpp, lane_count,
 896                                adjusted_mode->crtc_clock,
 897                                pipe_config->port_clock,
 898                                &pipe_config->dp_m_n);
 899
 900         intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
 901
 902         return true;
 903 }
 904
 905 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
 906 {
 907         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 908         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
 909         struct drm_device *dev = crtc->base.dev;
 910         struct drm_i915_private *dev_priv = dev->dev_private;
 911         u32 dpa_ctl;
 912
 913         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
 914         dpa_ctl = I915_READ(DP_A);
 915         dpa_ctl &= ~DP_PLL_FREQ_MASK;
 916
 917         if (crtc->config.port_clock == 162000) {
 918                 /* For a long time we've carried around a ILK-DevA w/a for the
 919                  * 160MHz clock. If we're really unlucky, it's still required.
 920                  */
 921                 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
 922                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
 923                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 924         } else {
 925                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
 926                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 927         }
 928
 929         I915_WRITE(DP_A, dpa_ctl);
 930
 931         POSTING_READ(DP_A);
 932         udelay(500);
 933 }
 934
 935 static void intel_dp_mode_set(struct intel_encoder *encoder)
 936 {
 937         struct drm_device *dev = encoder->base.dev;
 938         struct drm_i915_private *dev_priv = dev->dev_private;
 939         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 940         enum port port = dp_to_dig_port(intel_dp)->port;
 941         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 942         struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
 943
 944         /*
 945          * There are four kinds of DP registers:
 946          *
 947          *      IBX PCH
 948          *      SNB CPU
 949          *      IVB CPU
 950          *      CPT PCH
 951          *
 952          * IBX PCH and CPU are the same for almost everything,
 953          * except that the CPU DP PLL is configured in this
 954          * register
 955          *
 956          * CPT PCH is quite different, having many bits moved
 957          * to the TRANS_DP_CTL register instead. That
 958          * configuration happens (oddly) in ironlake_pch_enable
 959          */
 960
 961         /* Preserve the BIOS-computed detected bit. This is
 962          * supposed to be read-only.
 963          */
 964         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 965
 966         /* Handle DP bits in common between all three register formats */
 967         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 968         intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
 969
 970         if (intel_dp->has_audio) {
 971                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
 972                                  pipe_name(crtc->pipe));
 973                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 974                 intel_write_eld(&encoder->base, adjusted_mode);
 975         }
 976
 977         /* Split out the IBX/CPU vs CPT settings */
 978
 979         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
 980                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 981                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 982                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 983                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 984                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 985
 986                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
 987                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 988
 989                 intel_dp->DP |= crtc->pipe << 29;
 990         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
 991                 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
 992                         intel_dp->DP |= intel_dp->color_range;
 993
 994                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 995                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 996                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 997                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 998                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 999
1000                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1001                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1002
1003                 if (crtc->pipe == 1)
1004                         intel_dp->DP |= DP_PIPEB_SELECT;
1005         } else {
1006                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1007         }
1008
1009         if (port == PORT_A && !IS_VALLEYVIEW(dev))
1010                 ironlake_set_pll_cpu_edp(intel_dp);
1011 }
1012
1013 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1014 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1015
1016 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
1017 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
1018
1019 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1020 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1021
1022 static void wait_panel_status(struct intel_dp *intel_dp,
1023                                        u32 mask,
1024                                        u32 value)
1025 {
1026         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1027         struct drm_i915_private *dev_priv = dev->dev_private;
1028         u32 pp_stat_reg, pp_ctrl_reg;
1029
1030         pp_stat_reg = _pp_stat_reg(intel_dp);
1031         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1032
1033         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1034                         mask, value,
1035                         I915_READ(pp_stat_reg),
1036                         I915_READ(pp_ctrl_reg));
1037
1038         if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1039                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1040                                 I915_READ(pp_stat_reg),
1041                                 I915_READ(pp_ctrl_reg));
1042         }
1043
1044         DRM_DEBUG_KMS("Wait complete\n");
1045 }
1046
1047 static void wait_panel_on(struct intel_dp *intel_dp)
1048 {
1049         DRM_DEBUG_KMS("Wait for panel power on\n");
1050         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1051 }
1052
1053 static void wait_panel_off(struct intel_dp *intel_dp)
1054 {
1055         DRM_DEBUG_KMS("Wait for panel power off time\n");
1056         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1057 }
1058
1059 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1060 {
1061         DRM_DEBUG_KMS("Wait for panel power cycle\n");
1062
1063         /* When we disable the VDD override bit last we have to do the manual
1064          * wait. */
1065         wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1066                                        intel_dp->panel_power_cycle_delay);
1067
1068         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1069 }
1070
1071 static void wait_backlight_on(struct intel_dp *intel_dp)
1072 {
1073         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1074                                        intel_dp->backlight_on_delay);
1075 }
1076
1077 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1078 {
1079         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1080                                        intel_dp->backlight_off_delay);
1081 }
1082
1083 /* Read the current pp_control value, unlocking the register if it
1084  * is locked
1085  */
1086
1087 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1088 {
1089         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1090         struct drm_i915_private *dev_priv = dev->dev_private;
1091         u32 control;
1092
1093         control = I915_READ(_pp_ctrl_reg(intel_dp));
1094         control &= ~PANEL_UNLOCK_MASK;
1095         control |= PANEL_UNLOCK_REGS;
1096         return control;
1097 }
1098
1099 static void edp_panel_vdd_on(struct intel_dp *intel_dp)
1100 {
1101         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1102         struct drm_i915_private *dev_priv = dev->dev_private;
1103         u32 pp;
1104         u32 pp_stat_reg, pp_ctrl_reg;
1105
1106         if (!is_edp(intel_dp))
1107                 return;
1108
1109         WARN(intel_dp->want_panel_vdd,
1110              "eDP VDD already requested on\n");
1111
1112         intel_dp->want_panel_vdd = true;
1113
1114         if (edp_have_panel_vdd(intel_dp))
1115                 return;
1116
1117         intel_runtime_pm_get(dev_priv);
1118
1119         DRM_DEBUG_KMS("Turning eDP VDD on\n");
1120
1121         if (!edp_have_panel_power(intel_dp))
1122                 wait_panel_power_cycle(intel_dp);
1123
1124         pp = ironlake_get_pp_control(intel_dp);
1125         pp |= EDP_FORCE_VDD;
1126
1127         pp_stat_reg = _pp_stat_reg(intel_dp);
1128         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1129
1130         I915_WRITE(pp_ctrl_reg, pp);
1131         POSTING_READ(pp_ctrl_reg);
1132         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1133                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1134         /*
1135          * If the panel wasn't on, delay before accessing aux channel
1136          */
1137         if (!edp_have_panel_power(intel_dp)) {
1138                 DRM_DEBUG_KMS("eDP was not running\n");
1139                 msleep(intel_dp->panel_power_up_delay);
1140         }
1141 }
1142
1143 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1144 {
1145         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1146         struct drm_i915_private *dev_priv = dev->dev_private;
1147         u32 pp;
1148         u32 pp_stat_reg, pp_ctrl_reg;
1149
1150         WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1151
1152         if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
1153                 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1154
1155                 pp = ironlake_get_pp_control(intel_dp);
1156                 pp &= ~EDP_FORCE_VDD;
1157
1158                 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1159                 pp_stat_reg = _pp_stat_reg(intel_dp);
1160
1161                 I915_WRITE(pp_ctrl_reg, pp);
1162                 POSTING_READ(pp_ctrl_reg);
1163
1164                 /* Make sure sequencer is idle before allowing subsequent activity */
1165                 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1166                 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1167
1168                 if ((pp & POWER_TARGET_ON) == 0)
1169                         intel_dp->last_power_cycle = jiffies;
1170
1171                 intel_runtime_pm_put(dev_priv);
1172         }
1173 }
1174
1175 static void edp_panel_vdd_work(struct work_struct *__work)
1176 {
1177         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1178                                                  struct intel_dp, panel_vdd_work);
1179         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1180
1181         mutex_lock(&dev->mode_config.mutex);
1182         edp_panel_vdd_off_sync(intel_dp);
1183         mutex_unlock(&dev->mode_config.mutex);
1184 }
1185
1186 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1187 {
1188         if (!is_edp(intel_dp))
1189                 return;
1190
1191         WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1192
1193         intel_dp->want_panel_vdd = false;
1194
1195         if (sync) {
1196                 edp_panel_vdd_off_sync(intel_dp);
1197         } else {
1198                 /*
1199                  * Queue the timer to fire a long
1200                  * time from now (relative to the power down delay)
1201                  * to keep the panel power up across a sequence of operations
1202                  */
1203                 schedule_delayed_work(&intel_dp->panel_vdd_work,
1204                                       msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1205         }
1206 }
1207
1208 void intel_edp_panel_on(struct intel_dp *intel_dp)
1209 {
1210         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1211         struct drm_i915_private *dev_priv = dev->dev_private;
1212         u32 pp;
1213         u32 pp_ctrl_reg;
1214
1215         if (!is_edp(intel_dp))
1216                 return;
1217
1218         DRM_DEBUG_KMS("Turn eDP power on\n");
1219
1220         if (edp_have_panel_power(intel_dp)) {
1221                 DRM_DEBUG_KMS("eDP power already on\n");
1222                 return;
1223         }
1224
1225         wait_panel_power_cycle(intel_dp);
1226
1227         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1228         pp = ironlake_get_pp_control(intel_dp);
1229         if (IS_GEN5(dev)) {
1230                 /* ILK workaround: disable reset around power sequence */
1231                 pp &= ~PANEL_POWER_RESET;
1232                 I915_WRITE(pp_ctrl_reg, pp);
1233                 POSTING_READ(pp_ctrl_reg);
1234         }
1235
1236         pp |= POWER_TARGET_ON;
1237         if (!IS_GEN5(dev))
1238                 pp |= PANEL_POWER_RESET;
1239
1240         I915_WRITE(pp_ctrl_reg, pp);
1241         POSTING_READ(pp_ctrl_reg);
1242
1243         wait_panel_on(intel_dp);
1244         intel_dp->last_power_on = jiffies;
1245
1246         if (IS_GEN5(dev)) {
1247                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1248                 I915_WRITE(pp_ctrl_reg, pp);
1249                 POSTING_READ(pp_ctrl_reg);
1250         }
1251 }
1252
1253 void intel_edp_panel_off(struct intel_dp *intel_dp)
1254 {
1255         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1256         struct drm_i915_private *dev_priv = dev->dev_private;
1257         u32 pp;
1258         u32 pp_ctrl_reg;
1259
1260         if (!is_edp(intel_dp))
1261                 return;
1262
1263         DRM_DEBUG_KMS("Turn eDP power off\n");
1264
1265         edp_wait_backlight_off(intel_dp);
1266
1267         pp = ironlake_get_pp_control(intel_dp);
1268         /* We need to switch off panel power _and_ force vdd, for otherwise some
1269          * panels get very unhappy and cease to work. */
1270         pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1271
1272         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1273
1274         I915_WRITE(pp_ctrl_reg, pp);
1275         POSTING_READ(pp_ctrl_reg);
1276
1277         intel_dp->last_power_cycle = jiffies;
1278         wait_panel_off(intel_dp);
1279 }
1280
1281 void intel_edp_backlight_on(struct intel_dp *intel_dp)
1282 {
1283         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1284         struct drm_device *dev = intel_dig_port->base.base.dev;
1285         struct drm_i915_private *dev_priv = dev->dev_private;
1286         u32 pp;
1287         u32 pp_ctrl_reg;
1288
1289         if (!is_edp(intel_dp))
1290                 return;
1291
1292         DRM_DEBUG_KMS("\n");
1293         /*
1294          * If we enable the backlight right away following a panel power
1295          * on, we may see slight flicker as the panel syncs with the eDP
1296          * link.  So delay a bit to make sure the image is solid before
1297          * allowing it to appear.
1298          */
1299         wait_backlight_on(intel_dp);
1300         pp = ironlake_get_pp_control(intel_dp);
1301         pp |= EDP_BLC_ENABLE;
1302
1303         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1304
1305         I915_WRITE(pp_ctrl_reg, pp);
1306         POSTING_READ(pp_ctrl_reg);
1307
1308         intel_panel_enable_backlight(intel_dp->attached_connector);
1309 }
1310
1311 void intel_edp_backlight_off(struct intel_dp *intel_dp)
1312 {
1313         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1314         struct drm_i915_private *dev_priv = dev->dev_private;
1315         u32 pp;
1316         u32 pp_ctrl_reg;
1317
1318         if (!is_edp(intel_dp))
1319                 return;
1320
1321         intel_panel_disable_backlight(intel_dp->attached_connector);
1322
1323         DRM_DEBUG_KMS("\n");
1324         pp = ironlake_get_pp_control(intel_dp);
1325         pp &= ~EDP_BLC_ENABLE;
1326
1327         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1328
1329         I915_WRITE(pp_ctrl_reg, pp);
1330         POSTING_READ(pp_ctrl_reg);
1331         intel_dp->last_backlight_off = jiffies;
1332 }
1333
1334 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1335 {
1336         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1337         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1338         struct drm_device *dev = crtc->dev;
1339         struct drm_i915_private *dev_priv = dev->dev_private;
1340         u32 dpa_ctl;
1341
1342         assert_pipe_disabled(dev_priv,
1343                              to_intel_crtc(crtc)->pipe);
1344
1345         DRM_DEBUG_KMS("\n");
1346         dpa_ctl = I915_READ(DP_A);
1347         WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1348         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1349
1350         /* We don't adjust intel_dp->DP while tearing down the link, to
1351          * facilitate link retraining (e.g. after hotplug). Hence clear all
1352          * enable bits here to ensure that we don't enable too much. */
1353         intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1354         intel_dp->DP |= DP_PLL_ENABLE;
1355         I915_WRITE(DP_A, intel_dp->DP);
1356         POSTING_READ(DP_A);
1357         udelay(200);
1358 }
1359
1360 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1361 {
1362         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1363         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1364         struct drm_device *dev = crtc->dev;
1365         struct drm_i915_private *dev_priv = dev->dev_private;
1366         u32 dpa_ctl;
1367
1368         assert_pipe_disabled(dev_priv,
1369                              to_intel_crtc(crtc)->pipe);
1370
1371         dpa_ctl = I915_READ(DP_A);
1372         WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1373              "dp pll off, should be on\n");
1374         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1375
1376         /* We can't rely on the value tracked for the DP register in
1377          * intel_dp->DP because link_down must not change that (otherwise link
1378          * re-training will fail. */
1379         dpa_ctl &= ~DP_PLL_ENABLE;
1380         I915_WRITE(DP_A, dpa_ctl);
1381         POSTING_READ(DP_A);
1382         udelay(200);
1383 }
1384
1385 /* If the sink supports it, try to set the power state appropriately */
1386 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1387 {
1388         int ret, i;
1389
1390         /* Should have a valid DPCD by this point */
1391         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1392                 return;
1393
1394         if (mode != DRM_MODE_DPMS_ON) {
1395                 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1396                                                   DP_SET_POWER_D3);
1397                 if (ret != 1)
1398                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
1399         } else {
1400                 /*
1401                  * When turning on, we need to retry for 1ms to give the sink
1402                  * time to wake up.
1403                  */
1404                 for (i = 0; i < 3; i++) {
1405                         ret = intel_dp_aux_native_write_1(intel_dp,
1406                                                           DP_SET_POWER,
1407                                                           DP_SET_POWER_D0);
1408                         if (ret == 1)
1409                                 break;
1410                         msleep(1);
1411                 }
1412         }
1413 }
1414
1415 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1416                                   enum pipe *pipe)
1417 {
1418         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1419         enum port port = dp_to_dig_port(intel_dp)->port;
1420         struct drm_device *dev = encoder->base.dev;
1421         struct drm_i915_private *dev_priv = dev->dev_private;
1422         u32 tmp = I915_READ(intel_dp->output_reg);
1423
1424         if (!(tmp & DP_PORT_EN))
1425                 return false;
1426
1427         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1428                 *pipe = PORT_TO_PIPE_CPT(tmp);
1429         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1430                 *pipe = PORT_TO_PIPE(tmp);
1431         } else {
1432                 u32 trans_sel;
1433                 u32 trans_dp;
1434                 int i;
1435
1436                 switch (intel_dp->output_reg) {
1437                 case PCH_DP_B:
1438                         trans_sel = TRANS_DP_PORT_SEL_B;
1439                         break;
1440                 case PCH_DP_C:
1441                         trans_sel = TRANS_DP_PORT_SEL_C;
1442                         break;
1443                 case PCH_DP_D:
1444                         trans_sel = TRANS_DP_PORT_SEL_D;
1445                         break;
1446                 default:
1447                         return true;
1448                 }
1449
1450                 for_each_pipe(i) {
1451                         trans_dp = I915_READ(TRANS_DP_CTL(i));
1452                         if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1453                                 *pipe = i;
1454                                 return true;
1455                         }
1456                 }
1457
1458                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1459                               intel_dp->output_reg);
1460         }
1461
1462         return true;
1463 }
1464
1465 static void intel_dp_get_config(struct intel_encoder *encoder,
1466                                 struct intel_crtc_config *pipe_config)
1467 {
1468         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1469         u32 tmp, flags = 0;
1470         struct drm_device *dev = encoder->base.dev;
1471         struct drm_i915_private *dev_priv = dev->dev_private;
1472         enum port port = dp_to_dig_port(intel_dp)->port;
1473         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1474         int dotclock;
1475
1476         if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1477                 tmp = I915_READ(intel_dp->output_reg);
1478                 if (tmp & DP_SYNC_HS_HIGH)
1479                         flags |= DRM_MODE_FLAG_PHSYNC;
1480                 else
1481                         flags |= DRM_MODE_FLAG_NHSYNC;
1482
1483                 if (tmp & DP_SYNC_VS_HIGH)
1484                         flags |= DRM_MODE_FLAG_PVSYNC;
1485                 else
1486                         flags |= DRM_MODE_FLAG_NVSYNC;
1487         } else {
1488                 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1489                 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1490                         flags |= DRM_MODE_FLAG_PHSYNC;
1491                 else
1492                         flags |= DRM_MODE_FLAG_NHSYNC;
1493
1494                 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1495                         flags |= DRM_MODE_FLAG_PVSYNC;
1496                 else
1497                         flags |= DRM_MODE_FLAG_NVSYNC;
1498         }
1499
1500         pipe_config->adjusted_mode.flags |= flags;
1501
1502         pipe_config->has_dp_encoder = true;
1503
1504         intel_dp_get_m_n(crtc, pipe_config);
1505
1506         if (port == PORT_A) {
1507                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1508                         pipe_config->port_clock = 162000;
1509                 else
1510                         pipe_config->port_clock = 270000;
1511         }
1512
1513         dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1514                                             &pipe_config->dp_m_n);
1515
1516         if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1517                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1518
1519         pipe_config->adjusted_mode.crtc_clock = dotclock;
1520
1521         if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1522             pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1523                 /*
1524                  * This is a big fat ugly hack.
1525                  *
1526                  * Some machines in UEFI boot mode provide us a VBT that has 18
1527                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1528                  * unknown we fail to light up. Yet the same BIOS boots up with
1529                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1530                  * max, not what it tells us to use.
1531                  *
1532                  * Note: This will still be broken if the eDP panel is not lit
1533                  * up by the BIOS, and thus we can't get the mode at module
1534                  * load.
1535                  */
1536                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1537                               pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1538                 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1539         }
1540 }
1541
1542 static bool is_edp_psr(struct drm_device *dev)
1543 {
1544         struct drm_i915_private *dev_priv = dev->dev_private;
1545
1546         return dev_priv->psr.sink_support;
1547 }
1548
1549 static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1550 {
1551         struct drm_i915_private *dev_priv = dev->dev_private;
1552
1553         if (!HAS_PSR(dev))
1554                 return false;
1555
1556         return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1557 }
1558
1559 static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1560                                     struct edp_vsc_psr *vsc_psr)
1561 {
1562         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1563         struct drm_device *dev = dig_port->base.base.dev;
1564         struct drm_i915_private *dev_priv = dev->dev_private;
1565         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1566         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1567         u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1568         uint32_t *data = (uint32_t *) vsc_psr;
1569         unsigned int i;
1570
1571         /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1572            the video DIP being updated before program video DIP data buffer
1573            registers for DIP being updated. */
1574         I915_WRITE(ctl_reg, 0);
1575         POSTING_READ(ctl_reg);
1576
1577         for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1578                 if (i < sizeof(struct edp_vsc_psr))
1579                         I915_WRITE(data_reg + i, *data++);
1580                 else
1581                         I915_WRITE(data_reg + i, 0);
1582         }
1583
1584         I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1585         POSTING_READ(ctl_reg);
1586 }
1587
1588 static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1589 {
1590         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1591         struct drm_i915_private *dev_priv = dev->dev_private;
1592         struct edp_vsc_psr psr_vsc;
1593
1594         if (intel_dp->psr_setup_done)
1595                 return;
1596
1597         /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1598         memset(&psr_vsc, 0, sizeof(psr_vsc));
1599         psr_vsc.sdp_header.HB0 = 0;
1600         psr_vsc.sdp_header.HB1 = 0x7;
1601         psr_vsc.sdp_header.HB2 = 0x2;
1602         psr_vsc.sdp_header.HB3 = 0x8;
1603         intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1604
1605         /* Avoid continuous PSR exit by masking memup and hpd */
1606         I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
1607                    EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
1608
1609         intel_dp->psr_setup_done = true;
1610 }
1611
1612 static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1613 {
1614         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1615         struct drm_i915_private *dev_priv = dev->dev_private;
1616         uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp, 0);
1617         int precharge = 0x3;
1618         int msg_size = 5;       /* Header(4) + Message(1) */
1619
1620         /* Enable PSR in sink */
1621         if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1622                 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1623                                             DP_PSR_ENABLE &
1624                                             ~DP_PSR_MAIN_LINK_ACTIVE);
1625         else
1626                 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1627                                             DP_PSR_ENABLE |
1628                                             DP_PSR_MAIN_LINK_ACTIVE);
1629
1630         /* Setup AUX registers */
1631         I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1632         I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1633         I915_WRITE(EDP_PSR_AUX_CTL(dev),
1634                    DP_AUX_CH_CTL_TIME_OUT_400us |
1635                    (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1636                    (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1637                    (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1638 }
1639
1640 static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1641 {
1642         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1643         struct drm_i915_private *dev_priv = dev->dev_private;
1644         uint32_t max_sleep_time = 0x1f;
1645         uint32_t idle_frames = 1;
1646         uint32_t val = 0x0;
1647         const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
1648
1649         if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1650                 val |= EDP_PSR_LINK_STANDBY;
1651                 val |= EDP_PSR_TP2_TP3_TIME_0us;
1652                 val |= EDP_PSR_TP1_TIME_0us;
1653                 val |= EDP_PSR_SKIP_AUX_EXIT;
1654         } else
1655                 val |= EDP_PSR_LINK_DISABLE;
1656
1657         I915_WRITE(EDP_PSR_CTL(dev), val |
1658                    IS_BROADWELL(dev) ? 0 : link_entry_time |
1659                    max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1660                    idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1661                    EDP_PSR_ENABLE);
1662 }
1663
1664 static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1665 {
1666         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1667         struct drm_device *dev = dig_port->base.base.dev;
1668         struct drm_i915_private *dev_priv = dev->dev_private;
1669         struct drm_crtc *crtc = dig_port->base.base.crtc;
1670         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1671         struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
1672         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1673
1674         dev_priv->psr.source_ok = false;
1675
1676         if (!HAS_PSR(dev)) {
1677                 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1678                 return false;
1679         }
1680
1681         if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1682             (dig_port->port != PORT_A)) {
1683                 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1684                 return false;
1685         }
1686
1687         if (!i915_enable_psr) {
1688                 DRM_DEBUG_KMS("PSR disable by flag\n");
1689                 return false;
1690         }
1691
1692         crtc = dig_port->base.base.crtc;
1693         if (crtc == NULL) {
1694                 DRM_DEBUG_KMS("crtc not active for PSR\n");
1695                 return false;
1696         }
1697
1698         intel_crtc = to_intel_crtc(crtc);
1699         if (!intel_crtc_active(crtc)) {
1700                 DRM_DEBUG_KMS("crtc not active for PSR\n");
1701                 return false;
1702         }
1703
1704         obj = to_intel_framebuffer(crtc->fb)->obj;
1705         if (obj->tiling_mode != I915_TILING_X ||
1706             obj->fence_reg == I915_FENCE_REG_NONE) {
1707                 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
1708                 return false;
1709         }
1710
1711         if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1712                 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
1713                 return false;
1714         }
1715
1716         if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1717             S3D_ENABLE) {
1718                 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1719                 return false;
1720         }
1721
1722         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
1723                 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1724                 return false;
1725         }
1726
1727         dev_priv->psr.source_ok = true;
1728         return true;
1729 }
1730
1731 static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
1732 {
1733         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1734
1735         if (!intel_edp_psr_match_conditions(intel_dp) ||
1736             intel_edp_is_psr_enabled(dev))
1737                 return;
1738
1739         /* Setup PSR once */
1740         intel_edp_psr_setup(intel_dp);
1741
1742         /* Enable PSR on the panel */
1743         intel_edp_psr_enable_sink(intel_dp);
1744
1745         /* Enable PSR on the host */
1746         intel_edp_psr_enable_source(intel_dp);
1747 }
1748
1749 void intel_edp_psr_enable(struct intel_dp *intel_dp)
1750 {
1751         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1752
1753         if (intel_edp_psr_match_conditions(intel_dp) &&
1754             !intel_edp_is_psr_enabled(dev))
1755                 intel_edp_psr_do_enable(intel_dp);
1756 }
1757
1758 void intel_edp_psr_disable(struct intel_dp *intel_dp)
1759 {
1760         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1761         struct drm_i915_private *dev_priv = dev->dev_private;
1762
1763         if (!intel_edp_is_psr_enabled(dev))
1764                 return;
1765
1766         I915_WRITE(EDP_PSR_CTL(dev),
1767                    I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
1768
1769         /* Wait till PSR is idle */
1770         if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
1771                        EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1772                 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1773 }
1774
1775 void intel_edp_psr_update(struct drm_device *dev)
1776 {
1777         struct intel_encoder *encoder;
1778         struct intel_dp *intel_dp = NULL;
1779
1780         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1781                 if (encoder->type == INTEL_OUTPUT_EDP) {
1782                         intel_dp = enc_to_intel_dp(&encoder->base);
1783
1784                         if (!is_edp_psr(dev))
1785                                 return;
1786
1787                         if (!intel_edp_psr_match_conditions(intel_dp))
1788                                 intel_edp_psr_disable(intel_dp);
1789                         else
1790                                 if (!intel_edp_is_psr_enabled(dev))
1791                                         intel_edp_psr_do_enable(intel_dp);
1792                 }
1793 }
1794
1795 static void intel_disable_dp(struct intel_encoder *encoder)
1796 {
1797         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1798         enum port port = dp_to_dig_port(intel_dp)->port;
1799         struct drm_device *dev = encoder->base.dev;
1800
1801         /* Make sure the panel is off before trying to change the mode. But also
1802          * ensure that we have vdd while we switch off the panel. */
1803         intel_edp_backlight_off(intel_dp);
1804         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1805         intel_edp_panel_off(intel_dp);
1806
1807         /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1808         if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
1809                 intel_dp_link_down(intel_dp);
1810 }
1811
1812 static void intel_post_disable_dp(struct intel_encoder *encoder)
1813 {
1814         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1815         enum port port = dp_to_dig_port(intel_dp)->port;
1816         struct drm_device *dev = encoder->base.dev;
1817
1818         if (port == PORT_A || IS_VALLEYVIEW(dev)) {
1819                 intel_dp_link_down(intel_dp);
1820                 if (!IS_VALLEYVIEW(dev))
1821                         ironlake_edp_pll_off(intel_dp);
1822         }
1823 }
1824
1825 static void intel_enable_dp(struct intel_encoder *encoder)
1826 {
1827         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1828         struct drm_device *dev = encoder->base.dev;
1829         struct drm_i915_private *dev_priv = dev->dev_private;
1830         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1831
1832         if (WARN_ON(dp_reg & DP_PORT_EN))
1833                 return;
1834
1835         edp_panel_vdd_on(intel_dp);
1836         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1837         intel_dp_start_link_train(intel_dp);
1838         intel_edp_panel_on(intel_dp);
1839         edp_panel_vdd_off(intel_dp, true);
1840         intel_dp_complete_link_train(intel_dp);
1841         intel_dp_stop_link_train(intel_dp);
1842 }
1843
1844 static void g4x_enable_dp(struct intel_encoder *encoder)
1845 {
1846         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1847
1848         intel_enable_dp(encoder);
1849         intel_edp_backlight_on(intel_dp);
1850 }
1851
1852 static void vlv_enable_dp(struct intel_encoder *encoder)
1853 {
1854         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1855
1856         intel_edp_backlight_on(intel_dp);
1857 }
1858
1859 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
1860 {
1861         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1862         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1863
1864         if (dport->port == PORT_A)
1865                 ironlake_edp_pll_on(intel_dp);
1866 }
1867
1868 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
1869 {
1870         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1871         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1872         struct drm_device *dev = encoder->base.dev;
1873         struct drm_i915_private *dev_priv = dev->dev_private;
1874         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1875         enum dpio_channel port = vlv_dport_to_channel(dport);
1876         int pipe = intel_crtc->pipe;
1877         struct edp_power_seq power_seq;
1878         u32 val;
1879
1880         mutex_lock(&dev_priv->dpio_lock);
1881
1882         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1883         val = 0;
1884         if (pipe)
1885                 val |= (1<<21);
1886         else
1887                 val &= ~(1<<21);
1888         val |= 0x001000c4;
1889         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1890         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1891         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1892
1893         mutex_unlock(&dev_priv->dpio_lock);
1894
1895         /* init power sequencer on this pipe and port */
1896         intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1897         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1898                                                       &power_seq);
1899
1900         intel_enable_dp(encoder);
1901
1902         vlv_wait_port_ready(dev_priv, dport);
1903 }
1904
1905 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
1906 {
1907         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1908         struct drm_device *dev = encoder->base.dev;
1909         struct drm_i915_private *dev_priv = dev->dev_private;
1910         struct intel_crtc *intel_crtc =
1911                 to_intel_crtc(encoder->base.crtc);
1912         enum dpio_channel port = vlv_dport_to_channel(dport);
1913         int pipe = intel_crtc->pipe;
1914
1915         /* Program Tx lane resets to default */
1916         mutex_lock(&dev_priv->dpio_lock);
1917         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1918                          DPIO_PCS_TX_LANE2_RESET |
1919                          DPIO_PCS_TX_LANE1_RESET);
1920         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1921                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1922                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1923                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1924                                  DPIO_PCS_CLK_SOFT_RESET);
1925
1926         /* Fix up inter-pair skew failure */
1927         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1928         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1929         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1930         mutex_unlock(&dev_priv->dpio_lock);
1931 }
1932
1933 /*
1934  * Native read with retry for link status and receiver capability reads for
1935  * cases where the sink may still be asleep.
1936  */
1937 static bool
1938 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1939                                uint8_t *recv, int recv_bytes)
1940 {
1941         int ret, i;
1942
1943         /*
1944          * Sinks are *supposed* to come up within 1ms from an off state,
1945          * but we're also supposed to retry 3 times per the spec.
1946          */
1947         for (i = 0; i < 3; i++) {
1948                 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1949                                                recv_bytes);
1950                 if (ret == recv_bytes)
1951                         return true;
1952                 msleep(1);
1953         }
1954
1955         return false;
1956 }
1957
1958 /*
1959  * Fetch AUX CH registers 0x202 - 0x207 which contain
1960  * link status information
1961  */
1962 static bool
1963 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1964 {
1965         return intel_dp_aux_native_read_retry(intel_dp,
1966                                               DP_LANE0_1_STATUS,
1967                                               link_status,
1968                                               DP_LINK_STATUS_SIZE);
1969 }
1970
1971 /*
1972  * These are source-specific values; current Intel hardware supports
1973  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1974  */
1975
1976 static uint8_t
1977 intel_dp_voltage_max(struct intel_dp *intel_dp)
1978 {
1979         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1980         enum port port = dp_to_dig_port(intel_dp)->port;
1981
1982         if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
1983                 return DP_TRAIN_VOLTAGE_SWING_1200;
1984         else if (IS_GEN7(dev) && port == PORT_A)
1985                 return DP_TRAIN_VOLTAGE_SWING_800;
1986         else if (HAS_PCH_CPT(dev) && port != PORT_A)
1987                 return DP_TRAIN_VOLTAGE_SWING_1200;
1988         else
1989                 return DP_TRAIN_VOLTAGE_SWING_800;
1990 }
1991
1992 static uint8_t
1993 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1994 {
1995         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1996         enum port port = dp_to_dig_port(intel_dp)->port;
1997
1998         if (IS_BROADWELL(dev)) {
1999                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2000                 case DP_TRAIN_VOLTAGE_SWING_400:
2001                 case DP_TRAIN_VOLTAGE_SWING_600:
2002                         return DP_TRAIN_PRE_EMPHASIS_6;
2003                 case DP_TRAIN_VOLTAGE_SWING_800:
2004                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2005                 case DP_TRAIN_VOLTAGE_SWING_1200:
2006                 default:
2007                         return DP_TRAIN_PRE_EMPHASIS_0;
2008                 }
2009         } else if (IS_HASWELL(dev)) {
2010                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2011                 case DP_TRAIN_VOLTAGE_SWING_400:
2012                         return DP_TRAIN_PRE_EMPHASIS_9_5;
2013                 case DP_TRAIN_VOLTAGE_SWING_600:
2014                         return DP_TRAIN_PRE_EMPHASIS_6;
2015                 case DP_TRAIN_VOLTAGE_SWING_800:
2016                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2017                 case DP_TRAIN_VOLTAGE_SWING_1200:
2018                 default:
2019                         return DP_TRAIN_PRE_EMPHASIS_0;
2020                 }
2021         } else if (IS_VALLEYVIEW(dev)) {
2022                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2023                 case DP_TRAIN_VOLTAGE_SWING_400:
2024                         return DP_TRAIN_PRE_EMPHASIS_9_5;
2025                 case DP_TRAIN_VOLTAGE_SWING_600:
2026                         return DP_TRAIN_PRE_EMPHASIS_6;
2027                 case DP_TRAIN_VOLTAGE_SWING_800:
2028                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2029                 case DP_TRAIN_VOLTAGE_SWING_1200:
2030                 default:
2031                         return DP_TRAIN_PRE_EMPHASIS_0;
2032                 }
2033         } else if (IS_GEN7(dev) && port == PORT_A) {
2034                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2035                 case DP_TRAIN_VOLTAGE_SWING_400:
2036                         return DP_TRAIN_PRE_EMPHASIS_6;
2037                 case DP_TRAIN_VOLTAGE_SWING_600:
2038                 case DP_TRAIN_VOLTAGE_SWING_800:
2039                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2040                 default:
2041                         return DP_TRAIN_PRE_EMPHASIS_0;
2042                 }
2043         } else {
2044                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2045                 case DP_TRAIN_VOLTAGE_SWING_400:
2046                         return DP_TRAIN_PRE_EMPHASIS_6;
2047                 case DP_TRAIN_VOLTAGE_SWING_600:
2048                         return DP_TRAIN_PRE_EMPHASIS_6;
2049                 case DP_TRAIN_VOLTAGE_SWING_800:
2050                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2051                 case DP_TRAIN_VOLTAGE_SWING_1200:
2052                 default:
2053                         return DP_TRAIN_PRE_EMPHASIS_0;
2054                 }
2055         }
2056 }
2057
2058 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2059 {
2060         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2061         struct drm_i915_private *dev_priv = dev->dev_private;
2062         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2063         struct intel_crtc *intel_crtc =
2064                 to_intel_crtc(dport->base.base.crtc);
2065         unsigned long demph_reg_value, preemph_reg_value,
2066                 uniqtranscale_reg_value;
2067         uint8_t train_set = intel_dp->train_set[0];
2068         enum dpio_channel port = vlv_dport_to_channel(dport);
2069         int pipe = intel_crtc->pipe;
2070
2071         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2072         case DP_TRAIN_PRE_EMPHASIS_0:
2073                 preemph_reg_value = 0x0004000;
2074                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2075                 case DP_TRAIN_VOLTAGE_SWING_400:
2076                         demph_reg_value = 0x2B405555;
2077                         uniqtranscale_reg_value = 0x552AB83A;
2078                         break;
2079                 case DP_TRAIN_VOLTAGE_SWING_600:
2080                         demph_reg_value = 0x2B404040;
2081                         uniqtranscale_reg_value = 0x5548B83A;
2082                         break;
2083                 case DP_TRAIN_VOLTAGE_SWING_800:
2084                         demph_reg_value = 0x2B245555;
2085                         uniqtranscale_reg_value = 0x5560B83A;
2086                         break;
2087                 case DP_TRAIN_VOLTAGE_SWING_1200:
2088                         demph_reg_value = 0x2B405555;
2089                         uniqtranscale_reg_value = 0x5598DA3A;
2090                         break;
2091                 default:
2092                         return 0;
2093                 }
2094                 break;
2095         case DP_TRAIN_PRE_EMPHASIS_3_5:
2096                 preemph_reg_value = 0x0002000;
2097                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2098                 case DP_TRAIN_VOLTAGE_SWING_400:
2099                         demph_reg_value = 0x2B404040;
2100                         uniqtranscale_reg_value = 0x5552B83A;
2101                         break;
2102                 case DP_TRAIN_VOLTAGE_SWING_600:
2103                         demph_reg_value = 0x2B404848;
2104                         uniqtranscale_reg_value = 0x5580B83A;
2105                         break;
2106                 case DP_TRAIN_VOLTAGE_SWING_800:
2107                         demph_reg_value = 0x2B404040;
2108                         uniqtranscale_reg_value = 0x55ADDA3A;
2109                         break;
2110                 default:
2111                         return 0;
2112                 }
2113                 break;
2114         case DP_TRAIN_PRE_EMPHASIS_6:
2115                 preemph_reg_value = 0x0000000;
2116                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2117                 case DP_TRAIN_VOLTAGE_SWING_400:
2118                         demph_reg_value = 0x2B305555;
2119                         uniqtranscale_reg_value = 0x5570B83A;
2120                         break;
2121                 case DP_TRAIN_VOLTAGE_SWING_600:
2122                         demph_reg_value = 0x2B2B4040;
2123                         uniqtranscale_reg_value = 0x55ADDA3A;
2124                         break;
2125                 default:
2126                         return 0;
2127                 }
2128                 break;
2129         case DP_TRAIN_PRE_EMPHASIS_9_5:
2130                 preemph_reg_value = 0x0006000;
2131                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2132                 case DP_TRAIN_VOLTAGE_SWING_400:
2133                         demph_reg_value = 0x1B405555;
2134                         uniqtranscale_reg_value = 0x55ADDA3A;
2135                         break;
2136                 default:
2137                         return 0;
2138                 }
2139                 break;
2140         default:
2141                 return 0;
2142         }
2143
2144         mutex_lock(&dev_priv->dpio_lock);
2145         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2146         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2147         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
2148                          uniqtranscale_reg_value);
2149         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2150         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2151         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2152         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
2153         mutex_unlock(&dev_priv->dpio_lock);
2154
2155         return 0;
2156 }
2157
2158 static void
2159 intel_get_adjust_train(struct intel_dp *intel_dp,
2160                        const uint8_t link_status[DP_LINK_STATUS_SIZE])
2161 {
2162         uint8_t v = 0;
2163         uint8_t p = 0;
2164         int lane;
2165         uint8_t voltage_max;
2166         uint8_t preemph_max;
2167
2168         for (lane = 0; lane < intel_dp->lane_count; lane++) {
2169                 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2170                 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
2171
2172                 if (this_v > v)
2173                         v = this_v;
2174                 if (this_p > p)
2175                         p = this_p;
2176         }
2177
2178         voltage_max = intel_dp_voltage_max(intel_dp);
2179         if (v >= voltage_max)
2180                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
2181
2182         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2183         if (p >= preemph_max)
2184                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2185
2186         for (lane = 0; lane < 4; lane++)
2187                 intel_dp->train_set[lane] = v | p;
2188 }
2189
2190 static uint32_t
2191 intel_gen4_signal_levels(uint8_t train_set)
2192 {
2193         uint32_t        signal_levels = 0;
2194
2195         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2196         case DP_TRAIN_VOLTAGE_SWING_400:
2197         default:
2198                 signal_levels |= DP_VOLTAGE_0_4;
2199                 break;
2200         case DP_TRAIN_VOLTAGE_SWING_600:
2201                 signal_levels |= DP_VOLTAGE_0_6;
2202                 break;
2203         case DP_TRAIN_VOLTAGE_SWING_800:
2204                 signal_levels |= DP_VOLTAGE_0_8;
2205                 break;
2206         case DP_TRAIN_VOLTAGE_SWING_1200:
2207                 signal_levels |= DP_VOLTAGE_1_2;
2208                 break;
2209         }
2210         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2211         case DP_TRAIN_PRE_EMPHASIS_0:
2212         default:
2213                 signal_levels |= DP_PRE_EMPHASIS_0;
2214                 break;
2215         case DP_TRAIN_PRE_EMPHASIS_3_5:
2216                 signal_levels |= DP_PRE_EMPHASIS_3_5;
2217                 break;
2218         case DP_TRAIN_PRE_EMPHASIS_6:
2219                 signal_levels |= DP_PRE_EMPHASIS_6;
2220                 break;
2221         case DP_TRAIN_PRE_EMPHASIS_9_5:
2222                 signal_levels |= DP_PRE_EMPHASIS_9_5;
2223                 break;
2224         }
2225         return signal_levels;
2226 }
2227
2228 /* Gen6's DP voltage swing and pre-emphasis control */
2229 static uint32_t
2230 intel_gen6_edp_signal_levels(uint8_t train_set)
2231 {
2232         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2233                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2234         switch (signal_levels) {
2235         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2236         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2237                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2238         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2239                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
2240         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2241         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2242                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
2243         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2244         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2245                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
2246         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2247         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2248                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
2249         default:
2250                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2251                               "0x%x\n", signal_levels);
2252                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2253         }
2254 }
2255
2256 /* Gen7's DP voltage swing and pre-emphasis control */
2257 static uint32_t
2258 intel_gen7_edp_signal_levels(uint8_t train_set)
2259 {
2260         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2261                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2262         switch (signal_levels) {
2263         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2264                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2265         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2266                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2267         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2268                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2269
2270         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2271                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2272         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2273                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2274
2275         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2276                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2277         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2278                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2279
2280         default:
2281                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2282                               "0x%x\n", signal_levels);
2283                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2284         }
2285 }
2286
2287 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2288 static uint32_t
2289 intel_hsw_signal_levels(uint8_t train_set)
2290 {
2291         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2292                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2293         switch (signal_levels) {
2294         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2295                 return DDI_BUF_EMP_400MV_0DB_HSW;
2296         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2297                 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2298         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2299                 return DDI_BUF_EMP_400MV_6DB_HSW;
2300         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2301                 return DDI_BUF_EMP_400MV_9_5DB_HSW;
2302
2303         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2304                 return DDI_BUF_EMP_600MV_0DB_HSW;
2305         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2306                 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2307         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2308                 return DDI_BUF_EMP_600MV_6DB_HSW;
2309
2310         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2311                 return DDI_BUF_EMP_800MV_0DB_HSW;
2312         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2313                 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2314         default:
2315                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2316                               "0x%x\n", signal_levels);
2317                 return DDI_BUF_EMP_400MV_0DB_HSW;
2318         }
2319 }
2320
2321 static uint32_t
2322 intel_bdw_signal_levels(uint8_t train_set)
2323 {
2324         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2325                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2326         switch (signal_levels) {
2327         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2328                 return DDI_BUF_EMP_400MV_0DB_BDW;       /* Sel0 */
2329         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2330                 return DDI_BUF_EMP_400MV_3_5DB_BDW;     /* Sel1 */
2331         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2332                 return DDI_BUF_EMP_400MV_6DB_BDW;       /* Sel2 */
2333
2334         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2335                 return DDI_BUF_EMP_600MV_0DB_BDW;       /* Sel3 */
2336         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2337                 return DDI_BUF_EMP_600MV_3_5DB_BDW;     /* Sel4 */
2338         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2339                 return DDI_BUF_EMP_600MV_6DB_BDW;       /* Sel5 */
2340
2341         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2342                 return DDI_BUF_EMP_800MV_0DB_BDW;       /* Sel6 */
2343         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2344                 return DDI_BUF_EMP_800MV_3_5DB_BDW;     /* Sel7 */
2345
2346         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2347                 return DDI_BUF_EMP_1200MV_0DB_BDW;      /* Sel8 */
2348
2349         default:
2350                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2351                               "0x%x\n", signal_levels);
2352                 return DDI_BUF_EMP_400MV_0DB_BDW;       /* Sel0 */
2353         }
2354 }
2355
2356 /* Properly updates "DP" with the correct signal levels. */
2357 static void
2358 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2359 {
2360         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2361         enum port port = intel_dig_port->port;
2362         struct drm_device *dev = intel_dig_port->base.base.dev;
2363         uint32_t signal_levels, mask;
2364         uint8_t train_set = intel_dp->train_set[0];
2365
2366         if (IS_BROADWELL(dev)) {
2367                 signal_levels = intel_bdw_signal_levels(train_set);
2368                 mask = DDI_BUF_EMP_MASK;
2369         } else if (IS_HASWELL(dev)) {
2370                 signal_levels = intel_hsw_signal_levels(train_set);
2371                 mask = DDI_BUF_EMP_MASK;
2372         } else if (IS_VALLEYVIEW(dev)) {
2373                 signal_levels = intel_vlv_signal_levels(intel_dp);
2374                 mask = 0;
2375         } else if (IS_GEN7(dev) && port == PORT_A) {
2376                 signal_levels = intel_gen7_edp_signal_levels(train_set);
2377                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
2378         } else if (IS_GEN6(dev) && port == PORT_A) {
2379                 signal_levels = intel_gen6_edp_signal_levels(train_set);
2380                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2381         } else {
2382                 signal_levels = intel_gen4_signal_levels(train_set);
2383                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2384         }
2385
2386         DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2387
2388         *DP = (*DP & ~mask) | signal_levels;
2389 }
2390
2391 static bool
2392 intel_dp_set_link_train(struct intel_dp *intel_dp,
2393                         uint32_t *DP,
2394                         uint8_t dp_train_pat)
2395 {
2396         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2397         struct drm_device *dev = intel_dig_port->base.base.dev;
2398         struct drm_i915_private *dev_priv = dev->dev_private;
2399         enum port port = intel_dig_port->port;
2400         uint8_t buf[sizeof(intel_dp->train_set) + 1];
2401         int ret, len;
2402
2403         if (HAS_DDI(dev)) {
2404                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2405
2406                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2407                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2408                 else
2409                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2410
2411                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2412                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2413                 case DP_TRAINING_PATTERN_DISABLE:
2414                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2415
2416                         break;
2417                 case DP_TRAINING_PATTERN_1:
2418                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2419                         break;
2420                 case DP_TRAINING_PATTERN_2:
2421                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2422                         break;
2423                 case DP_TRAINING_PATTERN_3:
2424                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2425                         break;
2426                 }
2427                 I915_WRITE(DP_TP_CTL(port), temp);
2428
2429         } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2430                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2431
2432                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2433                 case DP_TRAINING_PATTERN_DISABLE:
2434                         *DP |= DP_LINK_TRAIN_OFF_CPT;
2435                         break;
2436                 case DP_TRAINING_PATTERN_1:
2437                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2438                         break;
2439                 case DP_TRAINING_PATTERN_2:
2440                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2441                         break;
2442                 case DP_TRAINING_PATTERN_3:
2443                         DRM_ERROR("DP training pattern 3 not supported\n");
2444                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2445                         break;
2446                 }
2447
2448         } else {
2449                 *DP &= ~DP_LINK_TRAIN_MASK;
2450
2451                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2452                 case DP_TRAINING_PATTERN_DISABLE:
2453                         *DP |= DP_LINK_TRAIN_OFF;
2454                         break;
2455                 case DP_TRAINING_PATTERN_1:
2456                         *DP |= DP_LINK_TRAIN_PAT_1;
2457                         break;
2458                 case DP_TRAINING_PATTERN_2:
2459                         *DP |= DP_LINK_TRAIN_PAT_2;
2460                         break;
2461                 case DP_TRAINING_PATTERN_3:
2462                         DRM_ERROR("DP training pattern 3 not supported\n");
2463                         *DP |= DP_LINK_TRAIN_PAT_2;
2464                         break;
2465                 }
2466         }
2467
2468         I915_WRITE(intel_dp->output_reg, *DP);
2469         POSTING_READ(intel_dp->output_reg);
2470
2471         buf[0] = dp_train_pat;
2472         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
2473             DP_TRAINING_PATTERN_DISABLE) {
2474                 /* don't write DP_TRAINING_LANEx_SET on disable */
2475                 len = 1;
2476         } else {
2477                 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2478                 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2479                 len = intel_dp->lane_count + 1;
2480         }
2481
2482         ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_PATTERN_SET,
2483                                         buf, len);
2484
2485         return ret == len;
2486 }
2487
2488 static bool
2489 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2490                         uint8_t dp_train_pat)
2491 {
2492         memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
2493         intel_dp_set_signal_levels(intel_dp, DP);
2494         return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2495 }
2496
2497 static bool
2498 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2499                            const uint8_t link_status[DP_LINK_STATUS_SIZE])
2500 {
2501         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2502         struct drm_device *dev = intel_dig_port->base.base.dev;
2503         struct drm_i915_private *dev_priv = dev->dev_private;
2504         int ret;
2505
2506         intel_get_adjust_train(intel_dp, link_status);
2507         intel_dp_set_signal_levels(intel_dp, DP);
2508
2509         I915_WRITE(intel_dp->output_reg, *DP);
2510         POSTING_READ(intel_dp->output_reg);
2511
2512         ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_LANE0_SET,
2513                                         intel_dp->train_set,
2514                                         intel_dp->lane_count);
2515
2516         return ret == intel_dp->lane_count;
2517 }
2518
2519 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2520 {
2521         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2522         struct drm_device *dev = intel_dig_port->base.base.dev;
2523         struct drm_i915_private *dev_priv = dev->dev_private;
2524         enum port port = intel_dig_port->port;
2525         uint32_t val;
2526
2527         if (!HAS_DDI(dev))
2528                 return;
2529
2530         val = I915_READ(DP_TP_CTL(port));
2531         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2532         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2533         I915_WRITE(DP_TP_CTL(port), val);
2534
2535         /*
2536          * On PORT_A we can have only eDP in SST mode. There the only reason
2537          * we need to set idle transmission mode is to work around a HW issue
2538          * where we enable the pipe while not in idle link-training mode.
2539          * In this case there is requirement to wait for a minimum number of
2540          * idle patterns to be sent.
2541          */
2542         if (port == PORT_A)
2543                 return;
2544
2545         if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2546                      1))
2547                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2548 }
2549
2550 /* Enable corresponding port and start training pattern 1 */
2551 void
2552 intel_dp_start_link_train(struct intel_dp *intel_dp)
2553 {
2554         struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2555         struct drm_device *dev = encoder->dev;
2556         int i;
2557         uint8_t voltage;
2558         int voltage_tries, loop_tries;
2559         uint32_t DP = intel_dp->DP;
2560         uint8_t link_config[2];
2561
2562         if (HAS_DDI(dev))
2563                 intel_ddi_prepare_link_retrain(encoder);
2564
2565         /* Write the link configuration data */
2566         link_config[0] = intel_dp->link_bw;
2567         link_config[1] = intel_dp->lane_count;
2568         if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2569                 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
2570         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, link_config, 2);
2571
2572         link_config[0] = 0;
2573         link_config[1] = DP_SET_ANSI_8B10B;
2574         intel_dp_aux_native_write(intel_dp, DP_DOWNSPREAD_CTRL, link_config, 2);
2575
2576         DP |= DP_PORT_EN;
2577
2578         /* clock recovery */
2579         if (!intel_dp_reset_link_train(intel_dp, &DP,
2580                                        DP_TRAINING_PATTERN_1 |
2581                                        DP_LINK_SCRAMBLING_DISABLE)) {
2582                 DRM_ERROR("failed to enable link training\n");
2583                 return;
2584         }
2585
2586         voltage = 0xff;
2587         voltage_tries = 0;
2588         loop_tries = 0;
2589         for (;;) {
2590                 uint8_t link_status[DP_LINK_STATUS_SIZE];
2591
2592                 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2593                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2594                         DRM_ERROR("failed to get link status\n");
2595                         break;
2596                 }
2597
2598                 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2599                         DRM_DEBUG_KMS("clock recovery OK\n");
2600                         break;
2601                 }
2602
2603                 /* Check to see if we've tried the max voltage */
2604                 for (i = 0; i < intel_dp->lane_count; i++)
2605                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2606                                 break;
2607                 if (i == intel_dp->lane_count) {
2608                         ++loop_tries;
2609                         if (loop_tries == 5) {
2610                                 DRM_ERROR("too many full retries, give up\n");
2611                                 break;
2612                         }
2613                         intel_dp_reset_link_train(intel_dp, &DP,
2614                                                   DP_TRAINING_PATTERN_1 |
2615                                                   DP_LINK_SCRAMBLING_DISABLE);
2616                         voltage_tries = 0;
2617                         continue;
2618                 }
2619
2620                 /* Check to see if we've tried the same voltage 5 times */
2621                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2622                         ++voltage_tries;
2623                         if (voltage_tries == 5) {
2624                                 DRM_ERROR("too many voltage retries, give up\n");
2625                                 break;
2626                         }
2627                 } else
2628                         voltage_tries = 0;
2629                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
2630
2631                 /* Update training set as requested by target */
2632                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2633                         DRM_ERROR("failed to update link training\n");
2634                         break;
2635                 }
2636         }
2637
2638         intel_dp->DP = DP;
2639 }
2640
2641 void
2642 intel_dp_complete_link_train(struct intel_dp *intel_dp)
2643 {
2644         bool channel_eq = false;
2645         int tries, cr_tries;
2646         uint32_t DP = intel_dp->DP;
2647
2648         /* channel equalization */
2649         if (!intel_dp_set_link_train(intel_dp, &DP,
2650                                      DP_TRAINING_PATTERN_2 |
2651                                      DP_LINK_SCRAMBLING_DISABLE)) {
2652                 DRM_ERROR("failed to start channel equalization\n");
2653                 return;
2654         }
2655
2656         tries = 0;
2657         cr_tries = 0;
2658         channel_eq = false;
2659         for (;;) {
2660                 uint8_t link_status[DP_LINK_STATUS_SIZE];
2661
2662                 if (cr_tries > 5) {
2663                         DRM_ERROR("failed to train DP, aborting\n");
2664                         break;
2665                 }
2666
2667                 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
2668                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2669                         DRM_ERROR("failed to get link status\n");
2670                         break;
2671                 }
2672
2673                 /* Make sure clock is still ok */
2674                 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2675                         intel_dp_start_link_train(intel_dp);
2676                         intel_dp_set_link_train(intel_dp, &DP,
2677                                                 DP_TRAINING_PATTERN_2 |
2678                                                 DP_LINK_SCRAMBLING_DISABLE);
2679                         cr_tries++;
2680                         continue;
2681                 }
2682
2683                 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2684                         channel_eq = true;
2685                         break;
2686                 }
2687
2688                 /* Try 5 times, then try clock recovery if that fails */
2689                 if (tries > 5) {
2690                         intel_dp_link_down(intel_dp);
2691                         intel_dp_start_link_train(intel_dp);
2692                         intel_dp_set_link_train(intel_dp, &DP,
2693                                                 DP_TRAINING_PATTERN_2 |
2694                                                 DP_LINK_SCRAMBLING_DISABLE);
2695                         tries = 0;
2696                         cr_tries++;
2697                         continue;
2698                 }
2699
2700                 /* Update training set as requested by target */
2701                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2702                         DRM_ERROR("failed to update link training\n");
2703                         break;
2704                 }
2705                 ++tries;
2706         }
2707
2708         intel_dp_set_idle_link_train(intel_dp);
2709
2710         intel_dp->DP = DP;
2711
2712         if (channel_eq)
2713                 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2714
2715 }
2716
2717 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2718 {
2719         intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2720                                 DP_TRAINING_PATTERN_DISABLE);
2721 }
2722
2723 static void
2724 intel_dp_link_down(struct intel_dp *intel_dp)
2725 {
2726         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2727         enum port port = intel_dig_port->port;
2728         struct drm_device *dev = intel_dig_port->base.base.dev;
2729         struct drm_i915_private *dev_priv = dev->dev_private;
2730         struct intel_crtc *intel_crtc =
2731                 to_intel_crtc(intel_dig_port->base.base.crtc);
2732         uint32_t DP = intel_dp->DP;
2733
2734         /*
2735          * DDI code has a strict mode set sequence and we should try to respect
2736          * it, otherwise we might hang the machine in many different ways. So we
2737          * really should be disabling the port only on a complete crtc_disable
2738          * sequence. This function is just called under two conditions on DDI
2739          * code:
2740          * - Link train failed while doing crtc_enable, and on this case we
2741          *   really should respect the mode set sequence and wait for a
2742          *   crtc_disable.
2743          * - Someone turned the monitor off and intel_dp_check_link_status
2744          *   called us. We don't need to disable the whole port on this case, so
2745          *   when someone turns the monitor on again,
2746          *   intel_ddi_prepare_link_retrain will take care of redoing the link
2747          *   train.
2748          */
2749         if (HAS_DDI(dev))
2750                 return;
2751
2752         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2753                 return;
2754
2755         DRM_DEBUG_KMS("\n");
2756
2757         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2758                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2759                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2760         } else {
2761                 DP &= ~DP_LINK_TRAIN_MASK;
2762                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2763         }
2764         POSTING_READ(intel_dp->output_reg);
2765
2766         /* We don't really know why we're doing this */
2767         intel_wait_for_vblank(dev, intel_crtc->pipe);
2768
2769         if (HAS_PCH_IBX(dev) &&
2770             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2771                 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2772
2773                 /* Hardware workaround: leaving our transcoder select
2774                  * set to transcoder B while it's off will prevent the
2775                  * corresponding HDMI output on transcoder A.
2776                  *
2777                  * Combine this with another hardware workaround:
2778                  * transcoder select bit can only be cleared while the
2779                  * port is enabled.
2780                  */
2781                 DP &= ~DP_PIPEB_SELECT;
2782                 I915_WRITE(intel_dp->output_reg, DP);
2783
2784                 /* Changes to enable or select take place the vblank
2785                  * after being written.
2786                  */
2787                 if (WARN_ON(crtc == NULL)) {
2788                         /* We should never try to disable a port without a crtc
2789                          * attached. For paranoia keep the code around for a
2790                          * bit. */
2791                         POSTING_READ(intel_dp->output_reg);
2792                         msleep(50);
2793                 } else
2794                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2795         }
2796
2797         DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2798         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2799         POSTING_READ(intel_dp->output_reg);
2800         msleep(intel_dp->panel_power_down_delay);
2801 }
2802
2803 static bool
2804 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2805 {
2806         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2807         struct drm_device *dev = dig_port->base.base.dev;
2808         struct drm_i915_private *dev_priv = dev->dev_private;
2809
2810         char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2811
2812         if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2813                                            sizeof(intel_dp->dpcd)) == 0)
2814                 return false; /* aux transfer failed */
2815
2816         hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2817                            32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2818         DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2819
2820         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2821                 return false; /* DPCD not present */
2822
2823         /* Check if the panel supports PSR */
2824         memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
2825         if (is_edp(intel_dp)) {
2826                 intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,
2827                                                intel_dp->psr_dpcd,
2828                                                sizeof(intel_dp->psr_dpcd));
2829                 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
2830                         dev_priv->psr.sink_support = true;
2831                         DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
2832                 }
2833         }
2834
2835         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2836               DP_DWN_STRM_PORT_PRESENT))
2837                 return true; /* native DP sink */
2838
2839         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2840                 return true; /* no per-port downstream info */
2841
2842         if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2843                                            intel_dp->downstream_ports,
2844                                            DP_MAX_DOWNSTREAM_PORTS) == 0)
2845                 return false; /* downstream port status fetch failed */
2846
2847         return true;
2848 }
2849
2850 static void
2851 intel_dp_probe_oui(struct intel_dp *intel_dp)
2852 {
2853         u8 buf[3];
2854
2855         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2856                 return;
2857
2858         edp_panel_vdd_on(intel_dp);
2859
2860         if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2861                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2862                               buf[0], buf[1], buf[2]);
2863
2864         if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2865                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2866                               buf[0], buf[1], buf[2]);
2867
2868         edp_panel_vdd_off(intel_dp, false);
2869 }
2870
2871 static bool
2872 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2873 {
2874         int ret;
2875
2876         ret = intel_dp_aux_native_read_retry(intel_dp,
2877                                              DP_DEVICE_SERVICE_IRQ_VECTOR,
2878                                              sink_irq_vector, 1);
2879         if (!ret)
2880                 return false;
2881
2882         return true;
2883 }
2884
2885 static void
2886 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2887 {
2888         /* NAK by default */
2889         intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2890 }
2891
2892 /*
2893  * According to DP spec
2894  * 5.1.2:
2895  *  1. Read DPCD
2896  *  2. Configure link according to Receiver Capabilities
2897  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
2898  *  4. Check link status on receipt of hot-plug interrupt
2899  */
2900
2901 void
2902 intel_dp_check_link_status(struct intel_dp *intel_dp)
2903 {
2904         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2905         u8 sink_irq_vector;
2906         u8 link_status[DP_LINK_STATUS_SIZE];
2907
2908         if (!intel_encoder->connectors_active)
2909                 return;
2910
2911         if (WARN_ON(!intel_encoder->base.crtc))
2912                 return;
2913
2914         /* Try to read receiver status if the link appears to be up */
2915         if (!intel_dp_get_link_status(intel_dp, link_status)) {
2916                 return;
2917         }
2918
2919         /* Now read the DPCD to see if it's actually running */
2920         if (!intel_dp_get_dpcd(intel_dp)) {
2921                 return;
2922         }
2923
2924         /* Try to read the source of the interrupt */
2925         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2926             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2927                 /* Clear interrupt source */
2928                 intel_dp_aux_native_write_1(intel_dp,
2929                                             DP_DEVICE_SERVICE_IRQ_VECTOR,
2930                                             sink_irq_vector);
2931
2932                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2933                         intel_dp_handle_test_request(intel_dp);
2934                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2935                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2936         }
2937
2938         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2939                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2940                               drm_get_encoder_name(&intel_encoder->base));
2941                 intel_dp_start_link_train(intel_dp);
2942                 intel_dp_complete_link_train(intel_dp);
2943                 intel_dp_stop_link_train(intel_dp);
2944         }
2945 }
2946
2947 /* XXX this is probably wrong for multiple downstream ports */
2948 static enum drm_connector_status
2949 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2950 {
2951         uint8_t *dpcd = intel_dp->dpcd;
2952         uint8_t type;
2953
2954         if (!intel_dp_get_dpcd(intel_dp))
2955                 return connector_status_disconnected;
2956
2957         /* if there's no downstream port, we're done */
2958         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2959                 return connector_status_connected;
2960
2961         /* If we're HPD-aware, SINK_COUNT changes dynamically */
2962         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2963             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
2964                 uint8_t reg;
2965                 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2966                                                     &reg, 1))
2967                         return connector_status_unknown;
2968                 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2969                                               : connector_status_disconnected;
2970         }
2971
2972         /* If no HPD, poke DDC gently */
2973         if (drm_probe_ddc(&intel_dp->adapter))
2974                 return connector_status_connected;
2975
2976         /* Well we tried, say unknown for unreliable port types */
2977         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
2978                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2979                 if (type == DP_DS_PORT_TYPE_VGA ||
2980                     type == DP_DS_PORT_TYPE_NON_EDID)
2981                         return connector_status_unknown;
2982         } else {
2983                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2984                         DP_DWN_STRM_PORT_TYPE_MASK;
2985                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
2986                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
2987                         return connector_status_unknown;
2988         }
2989
2990         /* Anything else is out of spec, warn and ignore */
2991         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2992         return connector_status_disconnected;
2993 }
2994
2995 static enum drm_connector_status
2996 ironlake_dp_detect(struct intel_dp *intel_dp)
2997 {
2998         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2999         struct drm_i915_private *dev_priv = dev->dev_private;
3000         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3001         enum drm_connector_status status;
3002
3003         /* Can't disconnect eDP, but you can close the lid... */
3004         if (is_edp(intel_dp)) {
3005                 status = intel_panel_detect(dev);
3006                 if (status == connector_status_unknown)
3007                         status = connector_status_connected;
3008                 return status;
3009         }
3010
3011         if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3012                 return connector_status_disconnected;
3013
3014         return intel_dp_detect_dpcd(intel_dp);
3015 }
3016
3017 static enum drm_connector_status
3018 g4x_dp_detect(struct intel_dp *intel_dp)
3019 {
3020         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3021         struct drm_i915_private *dev_priv = dev->dev_private;
3022         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3023         uint32_t bit;
3024
3025         /* Can't disconnect eDP, but you can close the lid... */
3026         if (is_edp(intel_dp)) {
3027                 enum drm_connector_status status;
3028
3029                 status = intel_panel_detect(dev);
3030                 if (status == connector_status_unknown)
3031                         status = connector_status_connected;
3032                 return status;
3033         }
3034
3035         if (IS_VALLEYVIEW(dev)) {
3036                 switch (intel_dig_port->port) {
3037                 case PORT_B:
3038                         bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3039                         break;
3040                 case PORT_C:
3041                         bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3042                         break;
3043                 case PORT_D:
3044                         bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3045                         break;
3046                 default:
3047                         return connector_status_unknown;
3048                 }
3049         } else {
3050                 switch (intel_dig_port->port) {
3051                 case PORT_B:
3052                         bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3053                         break;
3054                 case PORT_C:
3055                         bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3056                         break;
3057                 case PORT_D:
3058                         bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3059                         break;
3060                 default:
3061                         return connector_status_unknown;
3062                 }
3063         }
3064
3065         if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
3066                 return connector_status_disconnected;
3067
3068         return intel_dp_detect_dpcd(intel_dp);
3069 }
3070
3071 static struct edid *
3072 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3073 {
3074         struct intel_connector *intel_connector = to_intel_connector(connector);
3075
3076         /* use cached edid if we have one */
3077         if (intel_connector->edid) {
3078                 /* invalid edid */
3079                 if (IS_ERR(intel_connector->edid))
3080                         return NULL;
3081
3082                 return drm_edid_duplicate(intel_connector->edid);
3083         }
3084
3085         return drm_get_edid(connector, adapter);
3086 }
3087
3088 static int
3089 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3090 {
3091         struct intel_connector *intel_connector = to_intel_connector(connector);
3092
3093         /* use cached edid if we have one */
3094         if (intel_connector->edid) {
3095                 /* invalid edid */
3096                 if (IS_ERR(intel_connector->edid))
3097                         return 0;
3098
3099                 return intel_connector_update_modes(connector,
3100                                                     intel_connector->edid);
3101         }
3102
3103         return intel_ddc_get_modes(connector, adapter);
3104 }
3105
3106 static enum drm_connector_status
3107 intel_dp_detect(struct drm_connector *connector, bool force)
3108 {
3109         struct intel_dp *intel_dp = intel_attached_dp(connector);
3110         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3111         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3112         struct drm_device *dev = connector->dev;
3113         struct drm_i915_private *dev_priv = dev->dev_private;
3114         enum drm_connector_status status;
3115         struct edid *edid = NULL;
3116
3117         intel_runtime_pm_get(dev_priv);
3118
3119         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3120                       connector->base.id, drm_get_connector_name(connector));
3121
3122         intel_dp->has_audio = false;
3123
3124         if (HAS_PCH_SPLIT(dev))
3125                 status = ironlake_dp_detect(intel_dp);
3126         else
3127                 status = g4x_dp_detect(intel_dp);
3128
3129         if (status != connector_status_connected)
3130                 goto out;
3131
3132         intel_dp_probe_oui(intel_dp);
3133
3134         if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3135                 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
3136         } else {
3137                 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
3138                 if (edid) {
3139                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
3140                         kfree(edid);
3141                 }
3142         }
3143
3144         if (intel_encoder->type != INTEL_OUTPUT_EDP)
3145                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3146         status = connector_status_connected;
3147
3148 out:
3149         intel_runtime_pm_put(dev_priv);
3150         return status;
3151 }
3152
3153 static int intel_dp_get_modes(struct drm_connector *connector)
3154 {
3155         struct intel_dp *intel_dp = intel_attached_dp(connector);
3156         struct intel_connector *intel_connector = to_intel_connector(connector);
3157         struct drm_device *dev = connector->dev;
3158         int ret;
3159
3160         /* We should parse the EDID data and find out if it has an audio sink
3161          */
3162
3163         ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
3164         if (ret)
3165                 return ret;
3166
3167         /* if eDP has no EDID, fall back to fixed mode */
3168         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
3169                 struct drm_display_mode *mode;
3170                 mode = drm_mode_duplicate(dev,
3171                                           intel_connector->panel.fixed_mode);
3172                 if (mode) {
3173                         drm_mode_probed_add(connector, mode);
3174                         return 1;
3175                 }
3176         }
3177         return 0;
3178 }
3179
3180 static bool
3181 intel_dp_detect_audio(struct drm_connector *connector)
3182 {
3183         struct intel_dp *intel_dp = intel_attached_dp(connector);
3184         struct edid *edid;
3185         bool has_audio = false;
3186
3187         edid = intel_dp_get_edid(connector, &intel_dp->adapter);
3188         if (edid) {
3189                 has_audio = drm_detect_monitor_audio(edid);
3190                 kfree(edid);
3191         }
3192
3193         return has_audio;
3194 }
3195
3196 static int
3197 intel_dp_set_property(struct drm_connector *connector,
3198                       struct drm_property *property,
3199                       uint64_t val)
3200 {
3201         struct drm_i915_private *dev_priv = connector->dev->dev_private;
3202         struct intel_connector *intel_connector = to_intel_connector(connector);
3203         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3204         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3205         int ret;
3206
3207         ret = drm_object_property_set_value(&connector->base, property, val);
3208         if (ret)
3209                 return ret;
3210
3211         if (property == dev_priv->force_audio_property) {
3212                 int i = val;
3213                 bool has_audio;
3214
3215                 if (i == intel_dp->force_audio)
3216                         return 0;
3217
3218                 intel_dp->force_audio = i;
3219
3220                 if (i == HDMI_AUDIO_AUTO)
3221                         has_audio = intel_dp_detect_audio(connector);
3222                 else
3223                         has_audio = (i == HDMI_AUDIO_ON);
3224
3225                 if (has_audio == intel_dp->has_audio)
3226                         return 0;
3227
3228                 intel_dp->has_audio = has_audio;
3229                 goto done;
3230         }
3231
3232         if (property == dev_priv->broadcast_rgb_property) {
3233                 bool old_auto = intel_dp->color_range_auto;
3234                 uint32_t old_range = intel_dp->color_range;
3235
3236                 switch (val) {
3237                 case INTEL_BROADCAST_RGB_AUTO:
3238                         intel_dp->color_range_auto = true;
3239                         break;
3240                 case INTEL_BROADCAST_RGB_FULL:
3241                         intel_dp->color_range_auto = false;
3242                         intel_dp->color_range = 0;
3243                         break;
3244                 case INTEL_BROADCAST_RGB_LIMITED:
3245                         intel_dp->color_range_auto = false;
3246                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
3247                         break;
3248                 default:
3249                         return -EINVAL;
3250                 }
3251
3252                 if (old_auto == intel_dp->color_range_auto &&
3253                     old_range == intel_dp->color_range)
3254                         return 0;
3255
3256                 goto done;
3257         }
3258
3259         if (is_edp(intel_dp) &&
3260             property == connector->dev->mode_config.scaling_mode_property) {
3261                 if (val == DRM_MODE_SCALE_NONE) {
3262                         DRM_DEBUG_KMS("no scaling not supported\n");
3263                         return -EINVAL;
3264                 }
3265
3266                 if (intel_connector->panel.fitting_mode == val) {
3267                         /* the eDP scaling property is not changed */
3268                         return 0;
3269                 }
3270                 intel_connector->panel.fitting_mode = val;
3271
3272                 goto done;
3273         }
3274
3275         return -EINVAL;
3276
3277 done:
3278         if (intel_encoder->base.crtc)
3279                 intel_crtc_restore_mode(intel_encoder->base.crtc);
3280
3281         return 0;
3282 }
3283
3284 static void
3285 intel_dp_connector_destroy(struct drm_connector *connector)
3286 {
3287         struct intel_connector *intel_connector = to_intel_connector(connector);
3288
3289         if (!IS_ERR_OR_NULL(intel_connector->edid))
3290                 kfree(intel_connector->edid);
3291
3292         /* Can't call is_edp() since the encoder may have been destroyed
3293          * already. */
3294         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3295                 intel_panel_fini(&intel_connector->panel);
3296
3297         drm_connector_cleanup(connector);
3298         kfree(connector);
3299 }
3300
3301 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
3302 {
3303         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3304         struct intel_dp *intel_dp = &intel_dig_port->dp;
3305         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3306
3307         i2c_del_adapter(&intel_dp->adapter);
3308         drm_encoder_cleanup(encoder);
3309         if (is_edp(intel_dp)) {
3310                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3311                 mutex_lock(&dev->mode_config.mutex);
3312                 edp_panel_vdd_off_sync(intel_dp);
3313                 mutex_unlock(&dev->mode_config.mutex);
3314         }
3315         kfree(intel_dig_port);
3316 }
3317
3318 static const struct drm_connector_funcs intel_dp_connector_funcs = {
3319         .dpms = intel_connector_dpms,
3320         .detect = intel_dp_detect,
3321         .fill_modes = drm_helper_probe_single_connector_modes,
3322         .set_property = intel_dp_set_property,
3323         .destroy = intel_dp_connector_destroy,
3324 };
3325
3326 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3327         .get_modes = intel_dp_get_modes,
3328         .mode_valid = intel_dp_mode_valid,
3329         .best_encoder = intel_best_encoder,
3330 };
3331
3332 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
3333         .destroy = intel_dp_encoder_destroy,
3334 };
3335
3336 static void
3337 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
3338 {
3339         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3340
3341         intel_dp_check_link_status(intel_dp);
3342 }
3343
3344 /* Return which DP Port should be selected for Transcoder DP control */
3345 int
3346 intel_trans_dp_port_sel(struct drm_crtc *crtc)
3347 {
3348         struct drm_device *dev = crtc->dev;
3349         struct intel_encoder *intel_encoder;
3350         struct intel_dp *intel_dp;
3351
3352         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3353                 intel_dp = enc_to_intel_dp(&intel_encoder->base);
3354
3355                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3356                     intel_encoder->type == INTEL_OUTPUT_EDP)
3357                         return intel_dp->output_reg;
3358         }
3359
3360         return -1;
3361 }
3362
3363 /* check the VBT to see whether the eDP is on DP-D port */
3364 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
3365 {
3366         struct drm_i915_private *dev_priv = dev->dev_private;
3367         union child_device_config *p_child;
3368         int i;
3369         static const short port_mapping[] = {
3370                 [PORT_B] = PORT_IDPB,
3371                 [PORT_C] = PORT_IDPC,
3372                 [PORT_D] = PORT_IDPD,
3373         };
3374
3375         if (port == PORT_A)
3376                 return true;
3377
3378         if (!dev_priv->vbt.child_dev_num)
3379                 return false;
3380
3381         for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3382                 p_child = dev_priv->vbt.child_dev + i;
3383
3384                 if (p_child->common.dvo_port == port_mapping[port] &&
3385                     (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3386                     (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
3387                         return true;
3388         }
3389         return false;
3390 }
3391
3392 static void
3393 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3394 {
3395         struct intel_connector *intel_connector = to_intel_connector(connector);
3396
3397         intel_attach_force_audio_property(connector);
3398         intel_attach_broadcast_rgb_property(connector);
3399         intel_dp->color_range_auto = true;
3400
3401         if (is_edp(intel_dp)) {
3402                 drm_mode_create_scaling_mode_property(connector->dev);
3403                 drm_object_attach_property(
3404                         &connector->base,
3405                         connector->dev->mode_config.scaling_mode_property,
3406                         DRM_MODE_SCALE_ASPECT);
3407                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
3408         }
3409 }
3410
3411 static void
3412 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
3413                                     struct intel_dp *intel_dp,
3414                                     struct edp_power_seq *out)
3415 {
3416         struct drm_i915_private *dev_priv = dev->dev_private;
3417         struct edp_power_seq cur, vbt, spec, final;
3418         u32 pp_on, pp_off, pp_div, pp;
3419         int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
3420
3421         if (HAS_PCH_SPLIT(dev)) {
3422                 pp_ctrl_reg = PCH_PP_CONTROL;
3423                 pp_on_reg = PCH_PP_ON_DELAYS;
3424                 pp_off_reg = PCH_PP_OFF_DELAYS;
3425                 pp_div_reg = PCH_PP_DIVISOR;
3426         } else {
3427                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3428
3429                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3430                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3431                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3432                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3433         }
3434
3435         /* Workaround: Need to write PP_CONTROL with the unlock key as
3436          * the very first thing. */
3437         pp = ironlake_get_pp_control(intel_dp);
3438         I915_WRITE(pp_ctrl_reg, pp);
3439
3440         pp_on = I915_READ(pp_on_reg);
3441         pp_off = I915_READ(pp_off_reg);
3442         pp_div = I915_READ(pp_div_reg);
3443
3444         /* Pull timing values out of registers */
3445         cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3446                 PANEL_POWER_UP_DELAY_SHIFT;
3447
3448         cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3449                 PANEL_LIGHT_ON_DELAY_SHIFT;
3450
3451         cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3452                 PANEL_LIGHT_OFF_DELAY_SHIFT;
3453
3454         cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3455                 PANEL_POWER_DOWN_DELAY_SHIFT;
3456
3457         cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3458                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3459
3460         DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3461                       cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3462
3463         vbt = dev_priv->vbt.edp_pps;
3464
3465         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3466          * our hw here, which are all in 100usec. */
3467         spec.t1_t3 = 210 * 10;
3468         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3469         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3470         spec.t10 = 500 * 10;
3471         /* This one is special and actually in units of 100ms, but zero
3472          * based in the hw (so we need to add 100 ms). But the sw vbt
3473          * table multiplies it with 1000 to make it in units of 100usec,
3474          * too. */
3475         spec.t11_t12 = (510 + 100) * 10;
3476
3477         DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3478                       vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3479
3480         /* Use the max of the register settings and vbt. If both are
3481          * unset, fall back to the spec limits. */
3482 #define assign_final(field)     final.field = (max(cur.field, vbt.field) == 0 ? \
3483                                        spec.field : \
3484                                        max(cur.field, vbt.field))
3485         assign_final(t1_t3);
3486         assign_final(t8);
3487         assign_final(t9);
3488         assign_final(t10);
3489         assign_final(t11_t12);
3490 #undef assign_final
3491
3492 #define get_delay(field)        (DIV_ROUND_UP(final.field, 10))
3493         intel_dp->panel_power_up_delay = get_delay(t1_t3);
3494         intel_dp->backlight_on_delay = get_delay(t8);
3495         intel_dp->backlight_off_delay = get_delay(t9);
3496         intel_dp->panel_power_down_delay = get_delay(t10);
3497         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3498 #undef get_delay
3499
3500         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3501                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3502                       intel_dp->panel_power_cycle_delay);
3503
3504         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3505                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3506
3507         if (out)
3508                 *out = final;
3509 }
3510
3511 static void
3512 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3513                                               struct intel_dp *intel_dp,
3514                                               struct edp_power_seq *seq)
3515 {
3516         struct drm_i915_private *dev_priv = dev->dev_private;
3517         u32 pp_on, pp_off, pp_div, port_sel = 0;
3518         int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3519         int pp_on_reg, pp_off_reg, pp_div_reg;
3520
3521         if (HAS_PCH_SPLIT(dev)) {
3522                 pp_on_reg = PCH_PP_ON_DELAYS;
3523                 pp_off_reg = PCH_PP_OFF_DELAYS;
3524                 pp_div_reg = PCH_PP_DIVISOR;
3525         } else {
3526                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3527
3528                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3529                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3530                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3531         }
3532
3533         /* And finally store the new values in the power sequencer. */
3534         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
3535                 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
3536         pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
3537                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
3538         /* Compute the divisor for the pp clock, simply match the Bspec
3539          * formula. */
3540         pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
3541         pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
3542                         << PANEL_POWER_CYCLE_DELAY_SHIFT);
3543
3544         /* Haswell doesn't have any port selection bits for the panel
3545          * power sequencer any more. */
3546         if (IS_VALLEYVIEW(dev)) {
3547                 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3548                         port_sel = PANEL_PORT_SELECT_DPB_VLV;
3549                 else
3550                         port_sel = PANEL_PORT_SELECT_DPC_VLV;
3551         } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3552                 if (dp_to_dig_port(intel_dp)->port == PORT_A)
3553                         port_sel = PANEL_PORT_SELECT_DPA;
3554                 else
3555                         port_sel = PANEL_PORT_SELECT_DPD;
3556         }
3557
3558         pp_on |= port_sel;
3559
3560         I915_WRITE(pp_on_reg, pp_on);
3561         I915_WRITE(pp_off_reg, pp_off);
3562         I915_WRITE(pp_div_reg, pp_div);
3563
3564         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
3565                       I915_READ(pp_on_reg),
3566                       I915_READ(pp_off_reg),
3567                       I915_READ(pp_div_reg));
3568 }
3569
3570 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
3571                                      struct intel_connector *intel_connector,
3572                                      struct edp_power_seq *power_seq)
3573 {
3574         struct drm_connector *connector = &intel_connector->base;
3575         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3576         struct drm_device *dev = intel_dig_port->base.base.dev;
3577         struct drm_i915_private *dev_priv = dev->dev_private;
3578         struct drm_display_mode *fixed_mode = NULL;
3579         bool has_dpcd;
3580         struct drm_display_mode *scan;
3581         struct edid *edid;
3582
3583         if (!is_edp(intel_dp))
3584                 return true;
3585
3586         /* Cache DPCD and EDID for edp. */
3587         edp_panel_vdd_on(intel_dp);
3588         has_dpcd = intel_dp_get_dpcd(intel_dp);
3589         edp_panel_vdd_off(intel_dp, false);
3590
3591         if (has_dpcd) {
3592                 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3593                         dev_priv->no_aux_handshake =
3594                                 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3595                                 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3596         } else {
3597                 /* if this fails, presume the device is a ghost */
3598                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3599                 return false;
3600         }
3601
3602         /* We now know it's not a ghost, init power sequence regs. */
3603         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
3604
3605         edid = drm_get_edid(connector, &intel_dp->adapter);
3606         if (edid) {
3607                 if (drm_add_edid_modes(connector, edid)) {
3608                         drm_mode_connector_update_edid_property(connector,
3609                                                                 edid);
3610                         drm_edid_to_eld(connector, edid);
3611                 } else {
3612                         kfree(edid);
3613                         edid = ERR_PTR(-EINVAL);
3614                 }
3615         } else {
3616                 edid = ERR_PTR(-ENOENT);
3617         }
3618         intel_connector->edid = edid;
3619
3620         /* prefer fixed mode from EDID if available */
3621         list_for_each_entry(scan, &connector->probed_modes, head) {
3622                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3623                         fixed_mode = drm_mode_duplicate(dev, scan);
3624                         break;
3625                 }
3626         }
3627
3628         /* fallback to VBT if available for eDP */
3629         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3630                 fixed_mode = drm_mode_duplicate(dev,
3631                                         dev_priv->vbt.lfp_lvds_vbt_mode);
3632                 if (fixed_mode)
3633                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3634         }
3635
3636         intel_panel_init(&intel_connector->panel, fixed_mode);
3637         intel_panel_setup_backlight(connector);
3638
3639         return true;
3640 }
3641
3642 bool
3643 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3644                         struct intel_connector *intel_connector)
3645 {
3646         struct drm_connector *connector = &intel_connector->base;
3647         struct intel_dp *intel_dp = &intel_dig_port->dp;
3648         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3649         struct drm_device *dev = intel_encoder->base.dev;
3650         struct drm_i915_private *dev_priv = dev->dev_private;
3651         enum port port = intel_dig_port->port;
3652         struct edp_power_seq power_seq = { 0 };
3653         const char *name = NULL;
3654         int type, error;
3655
3656         /* Preserve the current hw state. */
3657         intel_dp->DP = I915_READ(intel_dp->output_reg);
3658         intel_dp->attached_connector = intel_connector;
3659
3660         if (intel_dp_is_edp(dev, port))
3661                 type = DRM_MODE_CONNECTOR_eDP;
3662         else
3663                 type = DRM_MODE_CONNECTOR_DisplayPort;
3664
3665         /*
3666          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3667          * for DP the encoder type can be set by the caller to
3668          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3669          */
3670         if (type == DRM_MODE_CONNECTOR_eDP)
3671                 intel_encoder->type = INTEL_OUTPUT_EDP;
3672
3673         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3674                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3675                         port_name(port));
3676
3677         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
3678         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3679
3680         connector->interlace_allowed = true;
3681         connector->doublescan_allowed = 0;
3682
3683         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3684                           edp_panel_vdd_work);
3685
3686         intel_connector_attach_encoder(intel_connector, intel_encoder);
3687         drm_sysfs_connector_add(connector);
3688
3689         if (HAS_DDI(dev))
3690                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3691         else
3692                 intel_connector->get_hw_state = intel_connector_get_hw_state;
3693
3694         intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3695         if (HAS_DDI(dev)) {
3696                 switch (intel_dig_port->port) {
3697                 case PORT_A:
3698                         intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3699                         break;
3700                 case PORT_B:
3701                         intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3702                         break;
3703                 case PORT_C:
3704                         intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3705                         break;
3706                 case PORT_D:
3707                         intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3708                         break;
3709                 default:
3710                         BUG();
3711                 }
3712         }
3713
3714         /* Set up the DDC bus. */
3715         switch (port) {
3716         case PORT_A:
3717                 intel_encoder->hpd_pin = HPD_PORT_A;
3718                 name = "DPDDC-A";
3719                 break;
3720         case PORT_B:
3721                 intel_encoder->hpd_pin = HPD_PORT_B;
3722                 name = "DPDDC-B";
3723                 break;
3724         case PORT_C:
3725                 intel_encoder->hpd_pin = HPD_PORT_C;
3726                 name = "DPDDC-C";
3727                 break;
3728         case PORT_D:
3729                 intel_encoder->hpd_pin = HPD_PORT_D;
3730                 name = "DPDDC-D";
3731                 break;
3732         default:
3733                 BUG();
3734         }
3735
3736         if (is_edp(intel_dp))
3737                 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3738
3739         error = intel_dp_i2c_init(intel_dp, intel_connector, name);
3740         WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
3741              error, port_name(port));
3742
3743         intel_dp->psr_setup_done = false;
3744
3745         if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
3746                 i2c_del_adapter(&intel_dp->adapter);
3747                 if (is_edp(intel_dp)) {
3748                         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3749                         mutex_lock(&dev->mode_config.mutex);
3750                         edp_panel_vdd_off_sync(intel_dp);
3751                         mutex_unlock(&dev->mode_config.mutex);
3752                 }
3753                 drm_sysfs_connector_remove(connector);
3754                 drm_connector_cleanup(connector);
3755                 return false;
3756         }
3757
3758         intel_dp_add_properties(intel_dp, connector);
3759
3760         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3761          * 0xd.  Failure to do so will result in spurious interrupts being
3762          * generated on the port when a cable is not attached.
3763          */
3764         if (IS_G4X(dev) && !IS_GM45(dev)) {
3765                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3766                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3767         }
3768
3769         return true;
3770 }
3771
3772 void
3773 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3774 {
3775         struct intel_digital_port *intel_dig_port;
3776         struct intel_encoder *intel_encoder;
3777         struct drm_encoder *encoder;
3778         struct intel_connector *intel_connector;
3779
3780         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3781         if (!intel_dig_port)
3782                 return;
3783
3784         intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
3785         if (!intel_connector) {
3786                 kfree(intel_dig_port);
3787                 return;
3788         }
3789
3790         intel_encoder = &intel_dig_port->base;
3791         encoder = &intel_encoder->base;
3792
3793         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3794                          DRM_MODE_ENCODER_TMDS);
3795
3796         intel_encoder->compute_config = intel_dp_compute_config;
3797         intel_encoder->mode_set = intel_dp_mode_set;
3798         intel_encoder->disable = intel_disable_dp;
3799         intel_encoder->post_disable = intel_post_disable_dp;
3800         intel_encoder->get_hw_state = intel_dp_get_hw_state;
3801         intel_encoder->get_config = intel_dp_get_config;
3802         if (IS_VALLEYVIEW(dev)) {
3803                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
3804                 intel_encoder->pre_enable = vlv_pre_enable_dp;
3805                 intel_encoder->enable = vlv_enable_dp;
3806         } else {
3807                 intel_encoder->pre_enable = g4x_pre_enable_dp;
3808                 intel_encoder->enable = g4x_enable_dp;
3809         }
3810
3811         intel_dig_port->port = port;
3812         intel_dig_port->dp.output_reg = output_reg;
3813
3814         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3815         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3816         intel_encoder->cloneable = false;
3817         intel_encoder->hot_plug = intel_dp_hot_plug;
3818
3819         if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3820                 drm_encoder_cleanup(encoder);
3821                 kfree(intel_dig_port);
3822                 kfree(intel_connector);
3823         }
3824 }