drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_edid.h>
  35 #include "intel_drv.h"
  36 #include <drm/i915_drm.h>
  37 #include "i915_drv.h"
  38
  39 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  40
  41 struct dp_link_dpll {
  42         int link_bw;
  43         struct dpll dpll;
  44 };
  45
  46 static const struct dp_link_dpll gen4_dpll[] = {
  47         { DP_LINK_BW_1_62,
  48                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  49         { DP_LINK_BW_2_7,
  50                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  51 };
  52
  53 static const struct dp_link_dpll pch_dpll[] = {
  54         { DP_LINK_BW_1_62,
  55                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  56         { DP_LINK_BW_2_7,
  57                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  58 };
  59
  60 static const struct dp_link_dpll vlv_dpll[] = {
  61         { DP_LINK_BW_1_62,
  62                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  63         { DP_LINK_BW_2_7,
  64                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  65 };
  66
  67 /*
  68  * CHV supports eDP 1.4 that have  more link rates.
  69  * Below only provides the fixed rate but exclude variable rate.
  70  */
  71 static const struct dp_link_dpll chv_dpll[] = {
  72         /*
  73          * CHV requires to program fractional division for m2.
  74          * m2 is stored in fixed point format using formula below
  75          * (m2_int << 22) | m2_fraction
  76          */
  77         { DP_LINK_BW_1_62,      /* m2_int = 32, m2_fraction = 1677722 */
  78                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
  79         { DP_LINK_BW_2_7,       /* m2_int = 27, m2_fraction = 0 */
  80                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
  81         { DP_LINK_BW_5_4,       /* m2_int = 27, m2_fraction = 0 */
  82                 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
  83 };
  84
  85 /**
  86  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  87  * @intel_dp: DP struct
  88  *
  89  * If a CPU or PCH DP output is attached to an eDP panel, this function
  90  * will return true, and false otherwise.
  91  */
  92 static bool is_edp(struct intel_dp *intel_dp)
  93 {
  94         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  95
  96         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
  97 }
  98
  99 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
 100 {
 101         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 102
 103         return intel_dig_port->base.base.dev;
 104 }
 105
 106 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 107 {
 108         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 109 }
 110
 111 static void intel_dp_link_down(struct intel_dp *intel_dp);
 112 static bool _edp_panel_vdd_on(struct intel_dp *intel_dp);
 113 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 114
 115 static int
 116 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 117 {
 118         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 119         struct drm_device *dev = intel_dp->attached_connector->base.dev;
 120
 121         switch (max_link_bw) {
 122         case DP_LINK_BW_1_62:
 123         case DP_LINK_BW_2_7:
 124                 break;
 125         case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
 126                 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
 127                      INTEL_INFO(dev)->gen >= 8) &&
 128                     intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
 129                         max_link_bw = DP_LINK_BW_5_4;
 130                 else
 131                         max_link_bw = DP_LINK_BW_2_7;
 132                 break;
 133         default:
 134                 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
 135                      max_link_bw);
 136                 max_link_bw = DP_LINK_BW_1_62;
 137                 break;
 138         }
 139         return max_link_bw;
 140 }
 141
 142 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 143 {
 144         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 145         struct drm_device *dev = intel_dig_port->base.base.dev;
 146         u8 source_max, sink_max;
 147
 148         source_max = 4;
 149         if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
 150             (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
 151                 source_max = 2;
 152
 153         sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 154
 155         return min(source_max, sink_max);
 156 }
 157
 158 /*
 159  * The units on the numbers in the next two are... bizarre.  Examples will
 160  * make it clearer; this one parallels an example in the eDP spec.
 161  *
 162  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 163  *
 164  *     270000 * 1 * 8 / 10 == 216000
 165  *
 166  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 167  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 168  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 169  * 119000.  At 18bpp that's 2142000 kilobits per second.
 170  *
 171  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 172  * get the result in decakilobits instead of kilobits.
 173  */
 174
 175 static int
 176 intel_dp_link_required(int pixel_clock, int bpp)
 177 {
 178         return (pixel_clock * bpp + 9) / 10;
 179 }
 180
 181 static int
 182 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 183 {
 184         return (max_link_clock * max_lanes * 8) / 10;
 185 }
 186
 187 static enum drm_mode_status
 188 intel_dp_mode_valid(struct drm_connector *connector,
 189                     struct drm_display_mode *mode)
 190 {
 191         struct intel_dp *intel_dp = intel_attached_dp(connector);
 192         struct intel_connector *intel_connector = to_intel_connector(connector);
 193         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 194         int target_clock = mode->clock;
 195         int max_rate, mode_rate, max_lanes, max_link_clock;
 196
 197         if (is_edp(intel_dp) && fixed_mode) {
 198                 if (mode->hdisplay > fixed_mode->hdisplay)
 199                         return MODE_PANEL;
 200
 201                 if (mode->vdisplay > fixed_mode->vdisplay)
 202                         return MODE_PANEL;
 203
 204                 target_clock = fixed_mode->clock;
 205         }
 206
 207         max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
 208         max_lanes = intel_dp_max_lane_count(intel_dp);
 209
 210         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 211         mode_rate = intel_dp_link_required(target_clock, 18);
 212
 213         if (mode_rate > max_rate)
 214                 return MODE_CLOCK_HIGH;
 215
 216         if (mode->clock < 10000)
 217                 return MODE_CLOCK_LOW;
 218
 219         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 220                 return MODE_H_ILLEGAL;
 221
 222         return MODE_OK;
 223 }
 224
 225 static uint32_t
 226 pack_aux(uint8_t *src, int src_bytes)
 227 {
 228         int     i;
 229         uint32_t v = 0;
 230
 231         if (src_bytes > 4)
 232                 src_bytes = 4;
 233         for (i = 0; i < src_bytes; i++)
 234                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 235         return v;
 236 }
 237
 238 static void
 239 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 240 {
 241         int i;
 242         if (dst_bytes > 4)
 243                 dst_bytes = 4;
 244         for (i = 0; i < dst_bytes; i++)
 245                 dst[i] = src >> ((3-i) * 8);
 246 }
 247
 248 /* hrawclock is 1/4 the FSB frequency */
 249 static int
 250 intel_hrawclk(struct drm_device *dev)
 251 {
 252         struct drm_i915_private *dev_priv = dev->dev_private;
 253         uint32_t clkcfg;
 254
 255         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 256         if (IS_VALLEYVIEW(dev))
 257                 return 200;
 258
 259         clkcfg = I915_READ(CLKCFG);
 260         switch (clkcfg & CLKCFG_FSB_MASK) {
 261         case CLKCFG_FSB_400:
 262                 return 100;
 263         case CLKCFG_FSB_533:
 264                 return 133;
 265         case CLKCFG_FSB_667:
 266                 return 166;
 267         case CLKCFG_FSB_800:
 268                 return 200;
 269         case CLKCFG_FSB_1067:
 270                 return 266;
 271         case CLKCFG_FSB_1333:
 272                 return 333;
 273         /* these two are just a guess; one of them might be right */
 274         case CLKCFG_FSB_1600:
 275         case CLKCFG_FSB_1600_ALT:
 276                 return 400;
 277         default:
 278                 return 133;
 279         }
 280 }
 281
 282 static void
 283 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 284                                     struct intel_dp *intel_dp,
 285                                     struct edp_power_seq *out);
 286 static void
 287 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 288                                               struct intel_dp *intel_dp,
 289                                               struct edp_power_seq *out);
 290
 291 static enum pipe
 292 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 293 {
 294         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 295         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
 296         struct drm_device *dev = intel_dig_port->base.base.dev;
 297         struct drm_i915_private *dev_priv = dev->dev_private;
 298         enum port port = intel_dig_port->port;
 299         enum pipe pipe;
 300
 301         /* modeset should have pipe */
 302         if (crtc)
 303                 return to_intel_crtc(crtc)->pipe;
 304
 305         /* init time, try to find a pipe with this port selected */
 306         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 307                 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
 308                         PANEL_PORT_SELECT_MASK;
 309                 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
 310                         return pipe;
 311                 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
 312                         return pipe;
 313         }
 314
 315         /* shrug */
 316         return PIPE_A;
 317 }
 318
 319 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
 320 {
 321         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 322
 323         if (HAS_PCH_SPLIT(dev))
 324                 return PCH_PP_CONTROL;
 325         else
 326                 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
 327 }
 328
 329 static u32 _pp_stat_reg(struct intel_dp *intel_dp)
 330 {
 331         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 332
 333         if (HAS_PCH_SPLIT(dev))
 334                 return PCH_PP_STATUS;
 335         else
 336                 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
 337 }
 338
 339 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 340 {
 341         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 342         struct drm_i915_private *dev_priv = dev->dev_private;
 343
 344         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 345 }
 346
 347 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 348 {
 349         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 350         struct drm_i915_private *dev_priv = dev->dev_private;
 351         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 352         struct intel_encoder *intel_encoder = &intel_dig_port->base;
 353         enum intel_display_power_domain power_domain;
 354
 355         power_domain = intel_display_port_power_domain(intel_encoder);
 356         return intel_display_power_enabled(dev_priv, power_domain) &&
 357                (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
 358 }
 359
 360 static void
 361 intel_dp_check_edp(struct intel_dp *intel_dp)
 362 {
 363         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 364         struct drm_i915_private *dev_priv = dev->dev_private;
 365
 366         if (!is_edp(intel_dp))
 367                 return;
 368
 369         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 370                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 371                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 372                               I915_READ(_pp_stat_reg(intel_dp)),
 373                               I915_READ(_pp_ctrl_reg(intel_dp)));
 374         }
 375 }
 376
 377 static uint32_t
 378 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 379 {
 380         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 381         struct drm_device *dev = intel_dig_port->base.base.dev;
 382         struct drm_i915_private *dev_priv = dev->dev_private;
 383         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 384         uint32_t status;
 385         bool done;
 386
 387 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 388         if (has_aux_irq)
 389                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 390                                           msecs_to_jiffies_timeout(10));
 391         else
 392                 done = wait_for_atomic(C, 10) == 0;
 393         if (!done)
 394                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 395                           has_aux_irq);
 396 #undef C
 397
 398         return status;
 399 }
 400
 401 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 402 {
 403         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 404         struct drm_device *dev = intel_dig_port->base.base.dev;
 405
 406         /*
 407          * The clock divider is based off the hrawclk, and would like to run at
 408          * 2MHz.  So, take the hrawclk value and divide by 2 and use that
 409          */
 410         return index ? 0 : intel_hrawclk(dev) / 2;
 411 }
 412
 413 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 414 {
 415         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 416         struct drm_device *dev = intel_dig_port->base.base.dev;
 417
 418         if (index)
 419                 return 0;
 420
 421         if (intel_dig_port->port == PORT_A) {
 422                 if (IS_GEN6(dev) || IS_GEN7(dev))
 423                         return 200; /* SNB & IVB eDP input clock at 400Mhz */
 424                 else
 425                         return 225; /* eDP input clock at 450Mhz */
 426         } else {
 427                 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 428         }
 429 }
 430
 431 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 432 {
 433         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 434         struct drm_device *dev = intel_dig_port->base.base.dev;
 435         struct drm_i915_private *dev_priv = dev->dev_private;
 436
 437         if (intel_dig_port->port == PORT_A) {
 438                 if (index)
 439                         return 0;
 440                 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
 441         } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 442                 /* Workaround for non-ULT HSW */
 443                 switch (index) {
 444                 case 0: return 63;
 445                 case 1: return 72;
 446                 default: return 0;
 447                 }
 448         } else  {
 449                 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 450         }
 451 }
 452
 453 static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 454 {
 455         return index ? 0 : 100;
 456 }
 457
 458 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
 459                                       bool has_aux_irq,
 460                                       int send_bytes,
 461                                       uint32_t aux_clock_divider)
 462 {
 463         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 464         struct drm_device *dev = intel_dig_port->base.base.dev;
 465         uint32_t precharge, timeout;
 466
 467         if (IS_GEN6(dev))
 468                 precharge = 3;
 469         else
 470                 precharge = 5;
 471
 472         if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
 473                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
 474         else
 475                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
 476
 477         return DP_AUX_CH_CTL_SEND_BUSY |
 478                DP_AUX_CH_CTL_DONE |
 479                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 480                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 481                timeout |
 482                DP_AUX_CH_CTL_RECEIVE_ERROR |
 483                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 484                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 485                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
 486 }
 487
 488 static int
 489 intel_dp_aux_ch(struct intel_dp *intel_dp,
 490                 uint8_t *send, int send_bytes,
 491                 uint8_t *recv, int recv_size)
 492 {
 493         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 494         struct drm_device *dev = intel_dig_port->base.base.dev;
 495         struct drm_i915_private *dev_priv = dev->dev_private;
 496         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 497         uint32_t ch_data = ch_ctl + 4;
 498         uint32_t aux_clock_divider;
 499         int i, ret, recv_bytes;
 500         uint32_t status;
 501         int try, clock = 0;
 502         bool has_aux_irq = HAS_AUX_IRQ(dev);
 503         bool vdd;
 504
 505         vdd = _edp_panel_vdd_on(intel_dp);
 506
 507         /* dp aux is extremely sensitive to irq latency, hence request the
 508          * lowest possible wakeup latency and so prevent the cpu from going into
 509          * deep sleep states.
 510          */
 511         pm_qos_update_request(&dev_priv->pm_qos, 0);
 512
 513         intel_dp_check_edp(intel_dp);
 514
 515         intel_aux_display_runtime_get(dev_priv);
 516
 517         /* Try to wait for any previous AUX channel activity */
 518         for (try = 0; try < 3; try++) {
 519                 status = I915_READ_NOTRACE(ch_ctl);
 520                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 521                         break;
 522                 msleep(1);
 523         }
 524
 525         if (try == 3) {
 526                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 527                      I915_READ(ch_ctl));
 528                 ret = -EBUSY;
 529                 goto out;
 530         }
 531
 532         /* Only 5 data registers! */
 533         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
 534                 ret = -E2BIG;
 535                 goto out;
 536         }
 537
 538         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
 539                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
 540                                                           has_aux_irq,
 541                                                           send_bytes,
 542                                                           aux_clock_divider);
 543
 544                 /* Must try at least 3 times according to DP spec */
 545                 for (try = 0; try < 5; try++) {
 546                         /* Load the send data into the aux channel data registers */
 547                         for (i = 0; i < send_bytes; i += 4)
 548                                 I915_WRITE(ch_data + i,
 549                                            pack_aux(send + i, send_bytes - i));
 550
 551                         /* Send the command and wait for it to complete */
 552                         I915_WRITE(ch_ctl, send_ctl);
 553
 554                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
 555
 556                         /* Clear done status and any errors */
 557                         I915_WRITE(ch_ctl,
 558                                    status |
 559                                    DP_AUX_CH_CTL_DONE |
 560                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
 561                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
 562
 563                         if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
 564                                       DP_AUX_CH_CTL_RECEIVE_ERROR))
 565                                 continue;
 566                         if (status & DP_AUX_CH_CTL_DONE)
 567                                 break;
 568                 }
 569                 if (status & DP_AUX_CH_CTL_DONE)
 570                         break;
 571         }
 572
 573         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 574                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 575                 ret = -EBUSY;
 576                 goto out;
 577         }
 578
 579         /* Check for timeout or receive error.
 580          * Timeouts occur when the sink is not connected
 581          */
 582         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 583                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 584                 ret = -EIO;
 585                 goto out;
 586         }
 587
 588         /* Timeouts occur when the device isn't connected, so they're
 589          * "normal" -- don't fill the kernel log with these */
 590         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 591                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 592                 ret = -ETIMEDOUT;
 593                 goto out;
 594         }
 595
 596         /* Unload any bytes sent back from the other side */
 597         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 598                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 599         if (recv_bytes > recv_size)
 600                 recv_bytes = recv_size;
 601
 602         for (i = 0; i < recv_bytes; i += 4)
 603                 unpack_aux(I915_READ(ch_data + i),
 604                            recv + i, recv_bytes - i);
 605
 606         ret = recv_bytes;
 607 out:
 608         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 609         intel_aux_display_runtime_put(dev_priv);
 610
 611         if (vdd)
 612                 edp_panel_vdd_off(intel_dp, false);
 613
 614         return ret;
 615 }
 616
 617 #define BARE_ADDRESS_SIZE       3
 618 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
 619 static ssize_t
 620 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
 621 {
 622         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
 623         uint8_t txbuf[20], rxbuf[20];
 624         size_t txsize, rxsize;
 625         int ret;
 626
 627         txbuf[0] = msg->request << 4;
 628         txbuf[1] = msg->address >> 8;
 629         txbuf[2] = msg->address & 0xff;
 630         txbuf[3] = msg->size - 1;
 631
 632         switch (msg->request & ~DP_AUX_I2C_MOT) {
 633         case DP_AUX_NATIVE_WRITE:
 634         case DP_AUX_I2C_WRITE:
 635                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
 636                 rxsize = 1;
 637
 638                 if (WARN_ON(txsize > 20))
 639                         return -E2BIG;
 640
 641                 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
 642
 643                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
 644                 if (ret > 0) {
 645                         msg->reply = rxbuf[0] >> 4;
 646
 647                         /* Return payload size. */
 648                         ret = msg->size;
 649                 }
 650                 break;
 651
 652         case DP_AUX_NATIVE_READ:
 653         case DP_AUX_I2C_READ:
 654                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
 655                 rxsize = msg->size + 1;
 656
 657                 if (WARN_ON(rxsize > 20))
 658                         return -E2BIG;
 659
 660                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
 661                 if (ret > 0) {
 662                         msg->reply = rxbuf[0] >> 4;
 663                         /*
 664                          * Assume happy day, and copy the data. The caller is
 665                          * expected to check msg->reply before touching it.
 666                          *
 667                          * Return payload size.
 668                          */
 669                         ret--;
 670                         memcpy(msg->buffer, rxbuf + 1, ret);
 671                 }
 672                 break;
 673
 674         default:
 675                 ret = -EINVAL;
 676                 break;
 677         }
 678
 679         return ret;
 680 }
 681
 682 static void
 683 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
 684 {
 685         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 686         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 687         enum port port = intel_dig_port->port;
 688         const char *name = NULL;
 689         int ret;
 690
 691         switch (port) {
 692         case PORT_A:
 693                 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
 694                 name = "DPDDC-A";
 695                 break;
 696         case PORT_B:
 697                 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
 698                 name = "DPDDC-B";
 699                 break;
 700         case PORT_C:
 701                 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
 702                 name = "DPDDC-C";
 703                 break;
 704         case PORT_D:
 705                 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
 706                 name = "DPDDC-D";
 707                 break;
 708         default:
 709                 BUG();
 710         }
 711
 712         if (!HAS_DDI(dev))
 713                 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
 714
 715         intel_dp->aux.name = name;
 716         intel_dp->aux.dev = dev->dev;
 717         intel_dp->aux.transfer = intel_dp_aux_transfer;
 718
 719         DRM_DEBUG_KMS("registering %s bus for %s\n", name,
 720                       connector->base.kdev->kobj.name);
 721
 722         ret = drm_dp_aux_register(&intel_dp->aux);
 723         if (ret < 0) {
 724                 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
 725                           name, ret);
 726                 return;
 727         }
 728
 729         ret = sysfs_create_link(&connector->base.kdev->kobj,
 730                                 &intel_dp->aux.ddc.dev.kobj,
 731                                 intel_dp->aux.ddc.dev.kobj.name);
 732         if (ret < 0) {
 733                 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
 734                 drm_dp_aux_unregister(&intel_dp->aux);
 735         }
 736 }
 737
 738 static void
 739 intel_dp_connector_unregister(struct intel_connector *intel_connector)
 740 {
 741         struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
 742
 743         sysfs_remove_link(&intel_connector->base.kdev->kobj,
 744                           intel_dp->aux.ddc.dev.kobj.name);
 745         intel_connector_unregister(intel_connector);
 746 }
 747
 748 static void
 749 hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
 750 {
 751         switch (link_bw) {
 752         case DP_LINK_BW_1_62:
 753                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
 754                 break;
 755         case DP_LINK_BW_2_7:
 756                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
 757                 break;
 758         case DP_LINK_BW_5_4:
 759                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
 760                 break;
 761         }
 762 }
 763
 764 static void
 765 intel_dp_set_clock(struct intel_encoder *encoder,
 766                    struct intel_crtc_config *pipe_config, int link_bw)
 767 {
 768         struct drm_device *dev = encoder->base.dev;
 769         const struct dp_link_dpll *divisor = NULL;
 770         int i, count = 0;
 771
 772         if (IS_G4X(dev)) {
 773                 divisor = gen4_dpll;
 774                 count = ARRAY_SIZE(gen4_dpll);
 775         } else if (HAS_PCH_SPLIT(dev)) {
 776                 divisor = pch_dpll;
 777                 count = ARRAY_SIZE(pch_dpll);
 778         } else if (IS_CHERRYVIEW(dev)) {
 779                 divisor = chv_dpll;
 780                 count = ARRAY_SIZE(chv_dpll);
 781         } else if (IS_VALLEYVIEW(dev)) {
 782                 divisor = vlv_dpll;
 783                 count = ARRAY_SIZE(vlv_dpll);
 784         }
 785
 786         if (divisor && count) {
 787                 for (i = 0; i < count; i++) {
 788                         if (link_bw == divisor[i].link_bw) {
 789                                 pipe_config->dpll = divisor[i].dpll;
 790                                 pipe_config->clock_set = true;
 791                                 break;
 792                         }
 793                 }
 794         }
 795 }
 796
 797 static void
 798 intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
 799 {
 800         struct drm_device *dev = crtc->base.dev;
 801         struct drm_i915_private *dev_priv = dev->dev_private;
 802         enum transcoder transcoder = crtc->config.cpu_transcoder;
 803
 804         I915_WRITE(PIPE_DATA_M2(transcoder),
 805                 TU_SIZE(m_n->tu) | m_n->gmch_m);
 806         I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
 807         I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
 808         I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
 809 }
 810
 811 bool
 812 intel_dp_compute_config(struct intel_encoder *encoder,
 813                         struct intel_crtc_config *pipe_config)
 814 {
 815         struct drm_device *dev = encoder->base.dev;
 816         struct drm_i915_private *dev_priv = dev->dev_private;
 817         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
 818         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 819         enum port port = dp_to_dig_port(intel_dp)->port;
 820         struct intel_crtc *intel_crtc = encoder->new_crtc;
 821         struct intel_connector *intel_connector = intel_dp->attached_connector;
 822         int lane_count, clock;
 823         int min_lane_count = 1;
 824         int max_lane_count = intel_dp_max_lane_count(intel_dp);
 825         /* Conveniently, the link BW constants become indices with a shift...*/
 826         int min_clock = 0;
 827         int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
 828         int bpp, mode_rate;
 829         static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
 830         int link_avail, link_clock;
 831
 832         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
 833                 pipe_config->has_pch_encoder = true;
 834
 835         pipe_config->has_dp_encoder = true;
 836         pipe_config->has_audio = intel_dp->has_audio;
 837
 838         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
 839                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
 840                                        adjusted_mode);
 841                 if (!HAS_PCH_SPLIT(dev))
 842                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
 843                                                  intel_connector->panel.fitting_mode);
 844                 else
 845                         intel_pch_panel_fitting(intel_crtc, pipe_config,
 846                                                 intel_connector->panel.fitting_mode);
 847         }
 848
 849         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 850                 return false;
 851
 852         DRM_DEBUG_KMS("DP link computation with max lane count %i "
 853                       "max bw %02x pixel clock %iKHz\n",
 854                       max_lane_count, bws[max_clock],
 855                       adjusted_mode->crtc_clock);
 856
 857         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
 858          * bpc in between. */
 859         bpp = pipe_config->pipe_bpp;
 860         if (is_edp(intel_dp)) {
 861                 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
 862                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
 863                                       dev_priv->vbt.edp_bpp);
 864                         bpp = dev_priv->vbt.edp_bpp;
 865                 }
 866
 867                 if (IS_BROADWELL(dev)) {
 868                         /* Yes, it's an ugly hack. */
 869                         min_lane_count = max_lane_count;
 870                         DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
 871                                       min_lane_count);
 872                 } else if (dev_priv->vbt.edp_lanes) {
 873                         min_lane_count = min(dev_priv->vbt.edp_lanes,
 874                                              max_lane_count);
 875                         DRM_DEBUG_KMS("using min %u lanes per VBT\n",
 876                                       min_lane_count);
 877                 }
 878
 879                 if (dev_priv->vbt.edp_rate) {
 880                         min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock);
 881                         DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
 882                                       bws[min_clock]);
 883                 }
 884         }
 885
 886         for (; bpp >= 6*3; bpp -= 2*3) {
 887                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
 888                                                    bpp);
 889
 890                 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
 891                         for (clock = min_clock; clock <= max_clock; clock++) {
 892                                 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
 893                                 link_avail = intel_dp_max_data_rate(link_clock,
 894                                                                     lane_count);
 895
 896                                 if (mode_rate <= link_avail) {
 897                                         goto found;
 898                                 }
 899                         }
 900                 }
 901         }
 902
 903         return false;
 904
 905 found:
 906         if (intel_dp->color_range_auto) {
 907                 /*
 908                  * See:
 909                  * CEA-861-E - 5.1 Default Encoding Parameters
 910                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
 911                  */
 912                 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
 913                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
 914                 else
 915                         intel_dp->color_range = 0;
 916         }
 917
 918         if (intel_dp->color_range)
 919                 pipe_config->limited_color_range = true;
 920
 921         intel_dp->link_bw = bws[clock];
 922         intel_dp->lane_count = lane_count;
 923         pipe_config->pipe_bpp = bpp;
 924         pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
 925
 926         DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
 927                       intel_dp->link_bw, intel_dp->lane_count,
 928                       pipe_config->port_clock, bpp);
 929         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
 930                       mode_rate, link_avail);
 931
 932         intel_link_compute_m_n(bpp, lane_count,
 933                                adjusted_mode->crtc_clock,
 934                                pipe_config->port_clock,
 935                                &pipe_config->dp_m_n);
 936
 937         if (intel_connector->panel.downclock_mode != NULL &&
 938                 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
 939                         intel_link_compute_m_n(bpp, lane_count,
 940                                 intel_connector->panel.downclock_mode->clock,
 941                                 pipe_config->port_clock,
 942                                 &pipe_config->dp_m2_n2);
 943         }
 944
 945         if (HAS_DDI(dev))
 946                 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
 947         else
 948                 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
 949
 950         return true;
 951 }
 952
 953 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
 954 {
 955         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 956         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
 957         struct drm_device *dev = crtc->base.dev;
 958         struct drm_i915_private *dev_priv = dev->dev_private;
 959         u32 dpa_ctl;
 960
 961         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
 962         dpa_ctl = I915_READ(DP_A);
 963         dpa_ctl &= ~DP_PLL_FREQ_MASK;
 964
 965         if (crtc->config.port_clock == 162000) {
 966                 /* For a long time we've carried around a ILK-DevA w/a for the
 967                  * 160MHz clock. If we're really unlucky, it's still required.
 968                  */
 969                 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
 970                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
 971                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 972         } else {
 973                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
 974                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 975         }
 976
 977         I915_WRITE(DP_A, dpa_ctl);
 978
 979         POSTING_READ(DP_A);
 980         udelay(500);
 981 }
 982
 983 static void intel_dp_prepare(struct intel_encoder *encoder)
 984 {
 985         struct drm_device *dev = encoder->base.dev;
 986         struct drm_i915_private *dev_priv = dev->dev_private;
 987         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 988         enum port port = dp_to_dig_port(intel_dp)->port;
 989         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 990         struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
 991
 992         /*
 993          * There are four kinds of DP registers:
 994          *
 995          *      IBX PCH
 996          *      SNB CPU
 997          *      IVB CPU
 998          *      CPT PCH
 999          *
1000          * IBX PCH and CPU are the same for almost everything,
1001          * except that the CPU DP PLL is configured in this
1002          * register
1003          *
1004          * CPT PCH is quite different, having many bits moved
1005          * to the TRANS_DP_CTL register instead. That
1006          * configuration happens (oddly) in ironlake_pch_enable
1007          */
1008
1009         /* Preserve the BIOS-computed detected bit. This is
1010          * supposed to be read-only.
1011          */
1012         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1013
1014         /* Handle DP bits in common between all three register formats */
1015         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1016         intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
1017
1018         if (crtc->config.has_audio) {
1019                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
1020                                  pipe_name(crtc->pipe));
1021                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
1022                 intel_write_eld(&encoder->base, adjusted_mode);
1023         }
1024
1025         /* Split out the IBX/CPU vs CPT settings */
1026
1027         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1028                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1029                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1030                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1031                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1032                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1033
1034                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1035                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1036
1037                 intel_dp->DP |= crtc->pipe << 29;
1038         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1039                 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
1040                         intel_dp->DP |= intel_dp->color_range;
1041
1042                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1043                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1044                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1045                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1046                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1047
1048                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1049                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1050
1051                 if (!IS_CHERRYVIEW(dev)) {
1052                         if (crtc->pipe == 1)
1053                                 intel_dp->DP |= DP_PIPEB_SELECT;
1054                 } else {
1055                         intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1056                 }
1057         } else {
1058                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1059         }
1060 }
1061
1062 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1063 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1064
1065 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
1066 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
1067
1068 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1069 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1070
1071 static void wait_panel_status(struct intel_dp *intel_dp,
1072                                        u32 mask,
1073                                        u32 value)
1074 {
1075         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1076         struct drm_i915_private *dev_priv = dev->dev_private;
1077         u32 pp_stat_reg, pp_ctrl_reg;
1078
1079         pp_stat_reg = _pp_stat_reg(intel_dp);
1080         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1081
1082         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1083                         mask, value,
1084                         I915_READ(pp_stat_reg),
1085                         I915_READ(pp_ctrl_reg));
1086
1087         if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1088                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1089                                 I915_READ(pp_stat_reg),
1090                                 I915_READ(pp_ctrl_reg));
1091         }
1092
1093         DRM_DEBUG_KMS("Wait complete\n");
1094 }
1095
1096 static void wait_panel_on(struct intel_dp *intel_dp)
1097 {
1098         DRM_DEBUG_KMS("Wait for panel power on\n");
1099         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1100 }
1101
1102 static void wait_panel_off(struct intel_dp *intel_dp)
1103 {
1104         DRM_DEBUG_KMS("Wait for panel power off time\n");
1105         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1106 }
1107
1108 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1109 {
1110         DRM_DEBUG_KMS("Wait for panel power cycle\n");
1111
1112         /* When we disable the VDD override bit last we have to do the manual
1113          * wait. */
1114         wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1115                                        intel_dp->panel_power_cycle_delay);
1116
1117         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1118 }
1119
1120 static void wait_backlight_on(struct intel_dp *intel_dp)
1121 {
1122         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1123                                        intel_dp->backlight_on_delay);
1124 }
1125
1126 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1127 {
1128         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1129                                        intel_dp->backlight_off_delay);
1130 }
1131
1132 /* Read the current pp_control value, unlocking the register if it
1133  * is locked
1134  */
1135
1136 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1137 {
1138         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1139         struct drm_i915_private *dev_priv = dev->dev_private;
1140         u32 control;
1141
1142         control = I915_READ(_pp_ctrl_reg(intel_dp));
1143         control &= ~PANEL_UNLOCK_MASK;
1144         control |= PANEL_UNLOCK_REGS;
1145         return control;
1146 }
1147
1148 static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
1149 {
1150         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1151         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1152         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1153         struct drm_i915_private *dev_priv = dev->dev_private;
1154         enum intel_display_power_domain power_domain;
1155         u32 pp;
1156         u32 pp_stat_reg, pp_ctrl_reg;
1157         bool need_to_disable = !intel_dp->want_panel_vdd;
1158
1159         if (!is_edp(intel_dp))
1160                 return false;
1161
1162         intel_dp->want_panel_vdd = true;
1163
1164         if (edp_have_panel_vdd(intel_dp))
1165                 return need_to_disable;
1166
1167         power_domain = intel_display_port_power_domain(intel_encoder);
1168         intel_display_power_get(dev_priv, power_domain);
1169
1170         DRM_DEBUG_KMS("Turning eDP VDD on\n");
1171
1172         if (!edp_have_panel_power(intel_dp))
1173                 wait_panel_power_cycle(intel_dp);
1174
1175         pp = ironlake_get_pp_control(intel_dp);
1176         pp |= EDP_FORCE_VDD;
1177
1178         pp_stat_reg = _pp_stat_reg(intel_dp);
1179         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1180
1181         I915_WRITE(pp_ctrl_reg, pp);
1182         POSTING_READ(pp_ctrl_reg);
1183         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1184                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1185         /*
1186          * If the panel wasn't on, delay before accessing aux channel
1187          */
1188         if (!edp_have_panel_power(intel_dp)) {
1189                 DRM_DEBUG_KMS("eDP was not running\n");
1190                 msleep(intel_dp->panel_power_up_delay);
1191         }
1192
1193         return need_to_disable;
1194 }
1195
1196 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1197 {
1198         if (is_edp(intel_dp)) {
1199                 bool vdd = _edp_panel_vdd_on(intel_dp);
1200
1201                 WARN(!vdd, "eDP VDD already requested on\n");
1202         }
1203 }
1204
1205 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1206 {
1207         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1208         struct drm_i915_private *dev_priv = dev->dev_private;
1209         u32 pp;
1210         u32 pp_stat_reg, pp_ctrl_reg;
1211
1212         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
1213
1214         if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
1215                 struct intel_digital_port *intel_dig_port =
1216                                                 dp_to_dig_port(intel_dp);
1217                 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1218                 enum intel_display_power_domain power_domain;
1219
1220                 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1221
1222                 pp = ironlake_get_pp_control(intel_dp);
1223                 pp &= ~EDP_FORCE_VDD;
1224
1225                 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1226                 pp_stat_reg = _pp_stat_reg(intel_dp);
1227
1228                 I915_WRITE(pp_ctrl_reg, pp);
1229                 POSTING_READ(pp_ctrl_reg);
1230
1231                 /* Make sure sequencer is idle before allowing subsequent activity */
1232                 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1233                 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1234
1235                 if ((pp & POWER_TARGET_ON) == 0)
1236                         intel_dp->last_power_cycle = jiffies;
1237
1238                 power_domain = intel_display_port_power_domain(intel_encoder);
1239                 intel_display_power_put(dev_priv, power_domain);
1240         }
1241 }
1242
1243 static void edp_panel_vdd_work(struct work_struct *__work)
1244 {
1245         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1246                                                  struct intel_dp, panel_vdd_work);
1247         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1248
1249         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1250         edp_panel_vdd_off_sync(intel_dp);
1251         drm_modeset_unlock(&dev->mode_config.connection_mutex);
1252 }
1253
1254 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1255 {
1256         if (!is_edp(intel_dp))
1257                 return;
1258
1259         WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1260
1261         intel_dp->want_panel_vdd = false;
1262
1263         if (sync) {
1264                 edp_panel_vdd_off_sync(intel_dp);
1265         } else {
1266                 /*
1267                  * Queue the timer to fire a long
1268                  * time from now (relative to the power down delay)
1269                  * to keep the panel power up across a sequence of operations
1270                  */
1271                 schedule_delayed_work(&intel_dp->panel_vdd_work,
1272                                       msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1273         }
1274 }
1275
1276 void intel_edp_panel_on(struct intel_dp *intel_dp)
1277 {
1278         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1279         struct drm_i915_private *dev_priv = dev->dev_private;
1280         u32 pp;
1281         u32 pp_ctrl_reg;
1282
1283         if (!is_edp(intel_dp))
1284                 return;
1285
1286         DRM_DEBUG_KMS("Turn eDP power on\n");
1287
1288         if (edp_have_panel_power(intel_dp)) {
1289                 DRM_DEBUG_KMS("eDP power already on\n");
1290                 return;
1291         }
1292
1293         wait_panel_power_cycle(intel_dp);
1294
1295         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1296         pp = ironlake_get_pp_control(intel_dp);
1297         if (IS_GEN5(dev)) {
1298                 /* ILK workaround: disable reset around power sequence */
1299                 pp &= ~PANEL_POWER_RESET;
1300                 I915_WRITE(pp_ctrl_reg, pp);
1301                 POSTING_READ(pp_ctrl_reg);
1302         }
1303
1304         pp |= POWER_TARGET_ON;
1305         if (!IS_GEN5(dev))
1306                 pp |= PANEL_POWER_RESET;
1307
1308         I915_WRITE(pp_ctrl_reg, pp);
1309         POSTING_READ(pp_ctrl_reg);
1310
1311         wait_panel_on(intel_dp);
1312         intel_dp->last_power_on = jiffies;
1313
1314         if (IS_GEN5(dev)) {
1315                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1316                 I915_WRITE(pp_ctrl_reg, pp);
1317                 POSTING_READ(pp_ctrl_reg);
1318         }
1319 }
1320
1321 void intel_edp_panel_off(struct intel_dp *intel_dp)
1322 {
1323         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1324         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1325         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1326         struct drm_i915_private *dev_priv = dev->dev_private;
1327         enum intel_display_power_domain power_domain;
1328         u32 pp;
1329         u32 pp_ctrl_reg;
1330
1331         if (!is_edp(intel_dp))
1332                 return;
1333
1334         DRM_DEBUG_KMS("Turn eDP power off\n");
1335
1336         WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1337
1338         pp = ironlake_get_pp_control(intel_dp);
1339         /* We need to switch off panel power _and_ force vdd, for otherwise some
1340          * panels get very unhappy and cease to work. */
1341         pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1342                 EDP_BLC_ENABLE);
1343
1344         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1345
1346         intel_dp->want_panel_vdd = false;
1347
1348         I915_WRITE(pp_ctrl_reg, pp);
1349         POSTING_READ(pp_ctrl_reg);
1350
1351         intel_dp->last_power_cycle = jiffies;
1352         wait_panel_off(intel_dp);
1353
1354         /* We got a reference when we enabled the VDD. */
1355         power_domain = intel_display_port_power_domain(intel_encoder);
1356         intel_display_power_put(dev_priv, power_domain);
1357 }
1358
1359 void intel_edp_backlight_on(struct intel_dp *intel_dp)
1360 {
1361         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1362         struct drm_device *dev = intel_dig_port->base.base.dev;
1363         struct drm_i915_private *dev_priv = dev->dev_private;
1364         u32 pp;
1365         u32 pp_ctrl_reg;
1366
1367         if (!is_edp(intel_dp))
1368                 return;
1369
1370         DRM_DEBUG_KMS("\n");
1371
1372         intel_panel_enable_backlight(intel_dp->attached_connector);
1373
1374         /*
1375          * If we enable the backlight right away following a panel power
1376          * on, we may see slight flicker as the panel syncs with the eDP
1377          * link.  So delay a bit to make sure the image is solid before
1378          * allowing it to appear.
1379          */
1380         wait_backlight_on(intel_dp);
1381         pp = ironlake_get_pp_control(intel_dp);
1382         pp |= EDP_BLC_ENABLE;
1383
1384         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1385
1386         I915_WRITE(pp_ctrl_reg, pp);
1387         POSTING_READ(pp_ctrl_reg);
1388 }
1389
1390 void intel_edp_backlight_off(struct intel_dp *intel_dp)
1391 {
1392         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1393         struct drm_i915_private *dev_priv = dev->dev_private;
1394         u32 pp;
1395         u32 pp_ctrl_reg;
1396
1397         if (!is_edp(intel_dp))
1398                 return;
1399
1400         DRM_DEBUG_KMS("\n");
1401         pp = ironlake_get_pp_control(intel_dp);
1402         pp &= ~EDP_BLC_ENABLE;
1403
1404         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1405
1406         I915_WRITE(pp_ctrl_reg, pp);
1407         POSTING_READ(pp_ctrl_reg);
1408         intel_dp->last_backlight_off = jiffies;
1409
1410         edp_wait_backlight_off(intel_dp);
1411
1412         intel_panel_disable_backlight(intel_dp->attached_connector);
1413 }
1414
1415 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1416 {
1417         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1418         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1419         struct drm_device *dev = crtc->dev;
1420         struct drm_i915_private *dev_priv = dev->dev_private;
1421         u32 dpa_ctl;
1422
1423         assert_pipe_disabled(dev_priv,
1424                              to_intel_crtc(crtc)->pipe);
1425
1426         DRM_DEBUG_KMS("\n");
1427         dpa_ctl = I915_READ(DP_A);
1428         WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1429         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1430
1431         /* We don't adjust intel_dp->DP while tearing down the link, to
1432          * facilitate link retraining (e.g. after hotplug). Hence clear all
1433          * enable bits here to ensure that we don't enable too much. */
1434         intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1435         intel_dp->DP |= DP_PLL_ENABLE;
1436         I915_WRITE(DP_A, intel_dp->DP);
1437         POSTING_READ(DP_A);
1438         udelay(200);
1439 }
1440
1441 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1442 {
1443         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1444         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1445         struct drm_device *dev = crtc->dev;
1446         struct drm_i915_private *dev_priv = dev->dev_private;
1447         u32 dpa_ctl;
1448
1449         assert_pipe_disabled(dev_priv,
1450                              to_intel_crtc(crtc)->pipe);
1451
1452         dpa_ctl = I915_READ(DP_A);
1453         WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1454              "dp pll off, should be on\n");
1455         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1456
1457         /* We can't rely on the value tracked for the DP register in
1458          * intel_dp->DP because link_down must not change that (otherwise link
1459          * re-training will fail. */
1460         dpa_ctl &= ~DP_PLL_ENABLE;
1461         I915_WRITE(DP_A, dpa_ctl);
1462         POSTING_READ(DP_A);
1463         udelay(200);
1464 }
1465
1466 /* If the sink supports it, try to set the power state appropriately */
1467 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1468 {
1469         int ret, i;
1470
1471         /* Should have a valid DPCD by this point */
1472         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1473                 return;
1474
1475         if (mode != DRM_MODE_DPMS_ON) {
1476                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1477                                          DP_SET_POWER_D3);
1478                 if (ret != 1)
1479                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
1480         } else {
1481                 /*
1482                  * When turning on, we need to retry for 1ms to give the sink
1483                  * time to wake up.
1484                  */
1485                 for (i = 0; i < 3; i++) {
1486                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1487                                                  DP_SET_POWER_D0);
1488                         if (ret == 1)
1489                                 break;
1490                         msleep(1);
1491                 }
1492         }
1493 }
1494
1495 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1496                                   enum pipe *pipe)
1497 {
1498         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1499         enum port port = dp_to_dig_port(intel_dp)->port;
1500         struct drm_device *dev = encoder->base.dev;
1501         struct drm_i915_private *dev_priv = dev->dev_private;
1502         enum intel_display_power_domain power_domain;
1503         u32 tmp;
1504
1505         power_domain = intel_display_port_power_domain(encoder);
1506         if (!intel_display_power_enabled(dev_priv, power_domain))
1507                 return false;
1508
1509         tmp = I915_READ(intel_dp->output_reg);
1510
1511         if (!(tmp & DP_PORT_EN))
1512                 return false;
1513
1514         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1515                 *pipe = PORT_TO_PIPE_CPT(tmp);
1516         } else if (IS_CHERRYVIEW(dev)) {
1517                 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
1518         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1519                 *pipe = PORT_TO_PIPE(tmp);
1520         } else {
1521                 u32 trans_sel;
1522                 u32 trans_dp;
1523                 int i;
1524
1525                 switch (intel_dp->output_reg) {
1526                 case PCH_DP_B:
1527                         trans_sel = TRANS_DP_PORT_SEL_B;
1528                         break;
1529                 case PCH_DP_C:
1530                         trans_sel = TRANS_DP_PORT_SEL_C;
1531                         break;
1532                 case PCH_DP_D:
1533                         trans_sel = TRANS_DP_PORT_SEL_D;
1534                         break;
1535                 default:
1536                         return true;
1537                 }
1538
1539                 for_each_pipe(i) {
1540                         trans_dp = I915_READ(TRANS_DP_CTL(i));
1541                         if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1542                                 *pipe = i;
1543                                 return true;
1544                         }
1545                 }
1546
1547                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1548                               intel_dp->output_reg);
1549         }
1550
1551         return true;
1552 }
1553
1554 static void intel_dp_get_config(struct intel_encoder *encoder,
1555                                 struct intel_crtc_config *pipe_config)
1556 {
1557         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1558         u32 tmp, flags = 0;
1559         struct drm_device *dev = encoder->base.dev;
1560         struct drm_i915_private *dev_priv = dev->dev_private;
1561         enum port port = dp_to_dig_port(intel_dp)->port;
1562         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1563         int dotclock;
1564
1565         tmp = I915_READ(intel_dp->output_reg);
1566         if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1567                 pipe_config->has_audio = true;
1568
1569         if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1570                 if (tmp & DP_SYNC_HS_HIGH)
1571                         flags |= DRM_MODE_FLAG_PHSYNC;
1572                 else
1573                         flags |= DRM_MODE_FLAG_NHSYNC;
1574
1575                 if (tmp & DP_SYNC_VS_HIGH)
1576                         flags |= DRM_MODE_FLAG_PVSYNC;
1577                 else
1578                         flags |= DRM_MODE_FLAG_NVSYNC;
1579         } else {
1580                 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1581                 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1582                         flags |= DRM_MODE_FLAG_PHSYNC;
1583                 else
1584                         flags |= DRM_MODE_FLAG_NHSYNC;
1585
1586                 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1587                         flags |= DRM_MODE_FLAG_PVSYNC;
1588                 else
1589                         flags |= DRM_MODE_FLAG_NVSYNC;
1590         }
1591
1592         pipe_config->adjusted_mode.flags |= flags;
1593
1594         pipe_config->has_dp_encoder = true;
1595
1596         intel_dp_get_m_n(crtc, pipe_config);
1597
1598         if (port == PORT_A) {
1599                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1600                         pipe_config->port_clock = 162000;
1601                 else
1602                         pipe_config->port_clock = 270000;
1603         }
1604
1605         dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1606                                             &pipe_config->dp_m_n);
1607
1608         if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1609                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1610
1611         pipe_config->adjusted_mode.crtc_clock = dotclock;
1612
1613         if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1614             pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1615                 /*
1616                  * This is a big fat ugly hack.
1617                  *
1618                  * Some machines in UEFI boot mode provide us a VBT that has 18
1619                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1620                  * unknown we fail to light up. Yet the same BIOS boots up with
1621                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1622                  * max, not what it tells us to use.
1623                  *
1624                  * Note: This will still be broken if the eDP panel is not lit
1625                  * up by the BIOS, and thus we can't get the mode at module
1626                  * load.
1627                  */
1628                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1629                               pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1630                 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1631         }
1632 }
1633
1634 static bool is_edp_psr(struct intel_dp *intel_dp)
1635 {
1636         return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
1637 }
1638
1639 static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1640 {
1641         struct drm_i915_private *dev_priv = dev->dev_private;
1642
1643         if (!HAS_PSR(dev))
1644                 return false;
1645
1646         return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1647 }
1648
1649 static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1650                                     struct edp_vsc_psr *vsc_psr)
1651 {
1652         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1653         struct drm_device *dev = dig_port->base.base.dev;
1654         struct drm_i915_private *dev_priv = dev->dev_private;
1655         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1656         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1657         u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1658         uint32_t *data = (uint32_t *) vsc_psr;
1659         unsigned int i;
1660
1661         /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1662            the video DIP being updated before program video DIP data buffer
1663            registers for DIP being updated. */
1664         I915_WRITE(ctl_reg, 0);
1665         POSTING_READ(ctl_reg);
1666
1667         for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1668                 if (i < sizeof(struct edp_vsc_psr))
1669                         I915_WRITE(data_reg + i, *data++);
1670                 else
1671                         I915_WRITE(data_reg + i, 0);
1672         }
1673
1674         I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1675         POSTING_READ(ctl_reg);
1676 }
1677
1678 static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1679 {
1680         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1681         struct drm_i915_private *dev_priv = dev->dev_private;
1682         struct edp_vsc_psr psr_vsc;
1683
1684         /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1685         memset(&psr_vsc, 0, sizeof(psr_vsc));
1686         psr_vsc.sdp_header.HB0 = 0;
1687         psr_vsc.sdp_header.HB1 = 0x7;
1688         psr_vsc.sdp_header.HB2 = 0x2;
1689         psr_vsc.sdp_header.HB3 = 0x8;
1690         intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1691
1692         /* Avoid continuous PSR exit by masking memup and hpd */
1693         I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
1694                    EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
1695 }
1696
1697 static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1698 {
1699         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1700         struct drm_device *dev = dig_port->base.base.dev;
1701         struct drm_i915_private *dev_priv = dev->dev_private;
1702         uint32_t aux_clock_divider;
1703         int precharge = 0x3;
1704         int msg_size = 5;       /* Header(4) + Message(1) */
1705         bool only_standby = false;
1706
1707         aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1708
1709         if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1710                 only_standby = true;
1711
1712         /* Enable PSR in sink */
1713         if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
1714                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1715                                    DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
1716         else
1717                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1718                                    DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
1719
1720         /* Setup AUX registers */
1721         I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1722         I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1723         I915_WRITE(EDP_PSR_AUX_CTL(dev),
1724                    DP_AUX_CH_CTL_TIME_OUT_400us |
1725                    (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1726                    (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1727                    (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1728 }
1729
1730 static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1731 {
1732         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1733         struct drm_device *dev = dig_port->base.base.dev;
1734         struct drm_i915_private *dev_priv = dev->dev_private;
1735         uint32_t max_sleep_time = 0x1f;
1736         uint32_t idle_frames = 1;
1737         uint32_t val = 0x0;
1738         const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
1739         bool only_standby = false;
1740
1741         if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1742                 only_standby = true;
1743
1744         if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
1745                 val |= EDP_PSR_LINK_STANDBY;
1746                 val |= EDP_PSR_TP2_TP3_TIME_0us;
1747                 val |= EDP_PSR_TP1_TIME_0us;
1748                 val |= EDP_PSR_SKIP_AUX_EXIT;
1749                 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
1750         } else
1751                 val |= EDP_PSR_LINK_DISABLE;
1752
1753         I915_WRITE(EDP_PSR_CTL(dev), val |
1754                    (IS_BROADWELL(dev) ? 0 : link_entry_time) |
1755                    max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1756                    idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1757                    EDP_PSR_ENABLE);
1758 }
1759
1760 static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1761 {
1762         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1763         struct drm_device *dev = dig_port->base.base.dev;
1764         struct drm_i915_private *dev_priv = dev->dev_private;
1765         struct drm_crtc *crtc = dig_port->base.base.crtc;
1766         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1767
1768         lockdep_assert_held(&dev_priv->psr.lock);
1769         lockdep_assert_held(&dev->struct_mutex);
1770         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
1771         WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
1772
1773         dev_priv->psr.source_ok = false;
1774
1775         if (!HAS_PSR(dev)) {
1776                 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1777                 return false;
1778         }
1779
1780         if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
1781                 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1782                 return false;
1783         }
1784
1785         if (!i915.enable_psr) {
1786                 DRM_DEBUG_KMS("PSR disable by flag\n");
1787                 return false;
1788         }
1789
1790         /* Below limitations aren't valid for Broadwell */
1791         if (IS_BROADWELL(dev))
1792                 goto out;
1793
1794         if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1795             S3D_ENABLE) {
1796                 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1797                 return false;
1798         }
1799
1800         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
1801                 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1802                 return false;
1803         }
1804
1805  out:
1806         dev_priv->psr.source_ok = true;
1807         return true;
1808 }
1809
1810 static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
1811 {
1812         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1813         struct drm_device *dev = intel_dig_port->base.base.dev;
1814         struct drm_i915_private *dev_priv = dev->dev_private;
1815
1816         WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
1817         WARN_ON(dev_priv->psr.active);
1818         lockdep_assert_held(&dev_priv->psr.lock);
1819
1820         /* Enable PSR on the panel */
1821         intel_edp_psr_enable_sink(intel_dp);
1822
1823         /* Enable PSR on the host */
1824         intel_edp_psr_enable_source(intel_dp);
1825
1826         dev_priv->psr.active = true;
1827 }
1828
1829 void intel_edp_psr_enable(struct intel_dp *intel_dp)
1830 {
1831         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1832         struct drm_i915_private *dev_priv = dev->dev_private;
1833
1834         if (!HAS_PSR(dev)) {
1835                 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1836                 return;
1837         }
1838
1839         if (!is_edp_psr(intel_dp)) {
1840                 DRM_DEBUG_KMS("PSR not supported by this panel\n");
1841                 return;
1842         }
1843
1844         mutex_lock(&dev_priv->psr.lock);
1845         if (dev_priv->psr.enabled) {
1846                 DRM_DEBUG_KMS("PSR already in use\n");
1847                 mutex_unlock(&dev_priv->psr.lock);
1848                 return;
1849         }
1850
1851         dev_priv->psr.busy_frontbuffer_bits = 0;
1852
1853         /* Setup PSR once */
1854         intel_edp_psr_setup(intel_dp);
1855
1856         if (intel_edp_psr_match_conditions(intel_dp))
1857                 dev_priv->psr.enabled = intel_dp;
1858         mutex_unlock(&dev_priv->psr.lock);
1859 }
1860
1861 void intel_edp_psr_disable(struct intel_dp *intel_dp)
1862 {
1863         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1864         struct drm_i915_private *dev_priv = dev->dev_private;
1865
1866         if (!HAS_PSR(dev))
1867                 return;
1868
1869         mutex_lock(&dev_priv->psr.lock);
1870         if (!dev_priv->psr.enabled) {
1871                 mutex_unlock(&dev_priv->psr.lock);
1872                 return;
1873         }
1874
1875         if (dev_priv->psr.active) {
1876                 I915_WRITE(EDP_PSR_CTL(dev),
1877                            I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
1878
1879                 /* Wait till PSR is idle */
1880                 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
1881                                EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1882                         DRM_ERROR("Timed out waiting for PSR Idle State\n");
1883
1884                 dev_priv->psr.active = false;
1885         } else {
1886                 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
1887         }
1888
1889         dev_priv->psr.enabled = NULL;
1890         mutex_unlock(&dev_priv->psr.lock);
1891
1892         cancel_delayed_work_sync(&dev_priv->psr.work);
1893 }
1894
1895 static void intel_edp_psr_work(struct work_struct *work)
1896 {
1897         struct drm_i915_private *dev_priv =
1898                 container_of(work, typeof(*dev_priv), psr.work.work);
1899         struct intel_dp *intel_dp = dev_priv->psr.enabled;
1900
1901         mutex_lock(&dev_priv->psr.lock);
1902         intel_dp = dev_priv->psr.enabled;
1903
1904         if (!intel_dp)
1905                 goto unlock;
1906
1907         /*
1908          * The delayed work can race with an invalidate hence we need to
1909          * recheck. Since psr_flush first clears this and then reschedules we
1910          * won't ever miss a flush when bailing out here.
1911          */
1912         if (dev_priv->psr.busy_frontbuffer_bits)
1913                 goto unlock;
1914
1915         intel_edp_psr_do_enable(intel_dp);
1916 unlock:
1917         mutex_unlock(&dev_priv->psr.lock);
1918 }
1919
1920 static void intel_edp_psr_do_exit(struct drm_device *dev)
1921 {
1922         struct drm_i915_private *dev_priv = dev->dev_private;
1923
1924         if (dev_priv->psr.active) {
1925                 u32 val = I915_READ(EDP_PSR_CTL(dev));
1926
1927                 WARN_ON(!(val & EDP_PSR_ENABLE));
1928
1929                 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
1930
1931                 dev_priv->psr.active = false;
1932         }
1933
1934 }
1935
1936 void intel_edp_psr_invalidate(struct drm_device *dev,
1937                               unsigned frontbuffer_bits)
1938 {
1939         struct drm_i915_private *dev_priv = dev->dev_private;
1940         struct drm_crtc *crtc;
1941         enum pipe pipe;
1942
1943         if (!HAS_PSR(dev))
1944                 return;
1945
1946         mutex_lock(&dev_priv->psr.lock);
1947         if (!dev_priv->psr.enabled) {
1948                 mutex_unlock(&dev_priv->psr.lock);
1949                 return;
1950         }
1951
1952         crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
1953         pipe = to_intel_crtc(crtc)->pipe;
1954
1955         intel_edp_psr_do_exit(dev);
1956
1957         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
1958
1959         dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
1960         mutex_unlock(&dev_priv->psr.lock);
1961 }
1962
1963 void intel_edp_psr_flush(struct drm_device *dev,
1964                          unsigned frontbuffer_bits)
1965 {
1966         struct drm_i915_private *dev_priv = dev->dev_private;
1967         struct drm_crtc *crtc;
1968         enum pipe pipe;
1969
1970         if (!HAS_PSR(dev))
1971                 return;
1972
1973         mutex_lock(&dev_priv->psr.lock);
1974         if (!dev_priv->psr.enabled) {
1975                 mutex_unlock(&dev_priv->psr.lock);
1976                 return;
1977         }
1978
1979         crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
1980         pipe = to_intel_crtc(crtc)->pipe;
1981         dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
1982
1983         /*
1984          * On Haswell sprite plane updates don't result in a psr invalidating
1985          * signal in the hardware. Which means we need to manually fake this in
1986          * software for all flushes, not just when we've seen a preceding
1987          * invalidation through frontbuffer rendering.
1988          */
1989         if (IS_HASWELL(dev) &&
1990             (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
1991                 intel_edp_psr_do_exit(dev);
1992
1993         if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
1994                 schedule_delayed_work(&dev_priv->psr.work,
1995                                       msecs_to_jiffies(100));
1996         mutex_unlock(&dev_priv->psr.lock);
1997 }
1998
1999 void intel_edp_psr_init(struct drm_device *dev)
2000 {
2001         struct drm_i915_private *dev_priv = dev->dev_private;
2002
2003         INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
2004         mutex_init(&dev_priv->psr.lock);
2005 }
2006
2007 static void intel_disable_dp(struct intel_encoder *encoder)
2008 {
2009         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2010         enum port port = dp_to_dig_port(intel_dp)->port;
2011         struct drm_device *dev = encoder->base.dev;
2012
2013         /* Make sure the panel is off before trying to change the mode. But also
2014          * ensure that we have vdd while we switch off the panel. */
2015         intel_edp_panel_vdd_on(intel_dp);
2016         intel_edp_backlight_off(intel_dp);
2017         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2018         intel_edp_panel_off(intel_dp);
2019
2020         /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
2021         if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
2022                 intel_dp_link_down(intel_dp);
2023 }
2024
2025 static void g4x_post_disable_dp(struct intel_encoder *encoder)
2026 {
2027         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2028         enum port port = dp_to_dig_port(intel_dp)->port;
2029
2030         if (port != PORT_A)
2031                 return;
2032
2033         intel_dp_link_down(intel_dp);
2034         ironlake_edp_pll_off(intel_dp);
2035 }
2036
2037 static void vlv_post_disable_dp(struct intel_encoder *encoder)
2038 {
2039         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2040
2041         intel_dp_link_down(intel_dp);
2042 }
2043
2044 static void chv_post_disable_dp(struct intel_encoder *encoder)
2045 {
2046         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2047         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2048         struct drm_device *dev = encoder->base.dev;
2049         struct drm_i915_private *dev_priv = dev->dev_private;
2050         struct intel_crtc *intel_crtc =
2051                 to_intel_crtc(encoder->base.crtc);
2052         enum dpio_channel ch = vlv_dport_to_channel(dport);
2053         enum pipe pipe = intel_crtc->pipe;
2054         u32 val;
2055
2056         intel_dp_link_down(intel_dp);
2057
2058         mutex_lock(&dev_priv->dpio_lock);
2059
2060         /* Propagate soft reset to data lane reset */
2061         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2062         val |= CHV_PCS_REQ_SOFTRESET_EN;
2063         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2064
2065         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2066         val |= CHV_PCS_REQ_SOFTRESET_EN;
2067         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2068
2069         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2070         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2071         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2072
2073         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2074         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2075         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2076
2077         mutex_unlock(&dev_priv->dpio_lock);
2078 }
2079
2080 static void intel_enable_dp(struct intel_encoder *encoder)
2081 {
2082         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2083         struct drm_device *dev = encoder->base.dev;
2084         struct drm_i915_private *dev_priv = dev->dev_private;
2085         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2086
2087         if (WARN_ON(dp_reg & DP_PORT_EN))
2088                 return;
2089
2090         intel_edp_panel_vdd_on(intel_dp);
2091         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2092         intel_dp_start_link_train(intel_dp);
2093         intel_edp_panel_on(intel_dp);
2094         edp_panel_vdd_off(intel_dp, true);
2095         intel_dp_complete_link_train(intel_dp);
2096         intel_dp_stop_link_train(intel_dp);
2097 }
2098
2099 static void g4x_enable_dp(struct intel_encoder *encoder)
2100 {
2101         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2102
2103         intel_enable_dp(encoder);
2104         intel_edp_backlight_on(intel_dp);
2105 }
2106
2107 static void vlv_enable_dp(struct intel_encoder *encoder)
2108 {
2109         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2110
2111         intel_edp_backlight_on(intel_dp);
2112 }
2113
2114 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
2115 {
2116         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2117         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2118
2119         intel_dp_prepare(encoder);
2120
2121         /* Only ilk+ has port A */
2122         if (dport->port == PORT_A) {
2123                 ironlake_set_pll_cpu_edp(intel_dp);
2124                 ironlake_edp_pll_on(intel_dp);
2125         }
2126 }
2127
2128 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
2129 {
2130         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2131         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2132         struct drm_device *dev = encoder->base.dev;
2133         struct drm_i915_private *dev_priv = dev->dev_private;
2134         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2135         enum dpio_channel port = vlv_dport_to_channel(dport);
2136         int pipe = intel_crtc->pipe;
2137         struct edp_power_seq power_seq;
2138         u32 val;
2139
2140         mutex_lock(&dev_priv->dpio_lock);
2141
2142         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
2143         val = 0;
2144         if (pipe)
2145                 val |= (1<<21);
2146         else
2147                 val &= ~(1<<21);
2148         val |= 0x001000c4;
2149         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2150         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2151         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
2152
2153         mutex_unlock(&dev_priv->dpio_lock);
2154
2155         if (is_edp(intel_dp)) {
2156                 /* init power sequencer on this pipe and port */
2157                 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2158                 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2159                                                               &power_seq);
2160         }
2161
2162         intel_enable_dp(encoder);
2163
2164         vlv_wait_port_ready(dev_priv, dport);
2165 }
2166
2167 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
2168 {
2169         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2170         struct drm_device *dev = encoder->base.dev;
2171         struct drm_i915_private *dev_priv = dev->dev_private;
2172         struct intel_crtc *intel_crtc =
2173                 to_intel_crtc(encoder->base.crtc);
2174         enum dpio_channel port = vlv_dport_to_channel(dport);
2175         int pipe = intel_crtc->pipe;
2176
2177         intel_dp_prepare(encoder);
2178
2179         /* Program Tx lane resets to default */
2180         mutex_lock(&dev_priv->dpio_lock);
2181         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
2182                          DPIO_PCS_TX_LANE2_RESET |
2183                          DPIO_PCS_TX_LANE1_RESET);
2184         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
2185                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2186                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2187                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2188                                  DPIO_PCS_CLK_SOFT_RESET);
2189
2190         /* Fix up inter-pair skew failure */
2191         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2192         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2193         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
2194         mutex_unlock(&dev_priv->dpio_lock);
2195 }
2196
2197 static void chv_pre_enable_dp(struct intel_encoder *encoder)
2198 {
2199         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2200         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2201         struct drm_device *dev = encoder->base.dev;
2202         struct drm_i915_private *dev_priv = dev->dev_private;
2203         struct edp_power_seq power_seq;
2204         struct intel_crtc *intel_crtc =
2205                 to_intel_crtc(encoder->base.crtc);
2206         enum dpio_channel ch = vlv_dport_to_channel(dport);
2207         int pipe = intel_crtc->pipe;
2208         int data, i;
2209         u32 val;
2210
2211         mutex_lock(&dev_priv->dpio_lock);
2212
2213         /* Deassert soft data lane reset*/
2214         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2215         val |= CHV_PCS_REQ_SOFTRESET_EN;
2216         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2217
2218         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2219         val |= CHV_PCS_REQ_SOFTRESET_EN;
2220         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2221
2222         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2223         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2224         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2225
2226         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2227         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2228         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2229
2230         /* Program Tx lane latency optimal setting*/
2231         for (i = 0; i < 4; i++) {
2232                 /* Set the latency optimal bit */
2233                 data = (i == 1) ? 0x0 : 0x6;
2234                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2235                                 data << DPIO_FRC_LATENCY_SHFIT);
2236
2237                 /* Set the upar bit */
2238                 data = (i == 1) ? 0x0 : 0x1;
2239                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2240                                 data << DPIO_UPAR_SHIFT);
2241         }
2242
2243         /* Data lane stagger programming */
2244         /* FIXME: Fix up value only after power analysis */
2245
2246         mutex_unlock(&dev_priv->dpio_lock);
2247
2248         if (is_edp(intel_dp)) {
2249                 /* init power sequencer on this pipe and port */
2250                 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2251                 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2252                                                               &power_seq);
2253         }
2254
2255         intel_enable_dp(encoder);
2256
2257         vlv_wait_port_ready(dev_priv, dport);
2258 }
2259
2260 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2261 {
2262         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2263         struct drm_device *dev = encoder->base.dev;
2264         struct drm_i915_private *dev_priv = dev->dev_private;
2265         struct intel_crtc *intel_crtc =
2266                 to_intel_crtc(encoder->base.crtc);
2267         enum dpio_channel ch = vlv_dport_to_channel(dport);
2268         enum pipe pipe = intel_crtc->pipe;
2269         u32 val;
2270
2271         mutex_lock(&dev_priv->dpio_lock);
2272
2273         /* program left/right clock distribution */
2274         if (pipe != PIPE_B) {
2275                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2276                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2277                 if (ch == DPIO_CH0)
2278                         val |= CHV_BUFLEFTENA1_FORCE;
2279                 if (ch == DPIO_CH1)
2280                         val |= CHV_BUFRIGHTENA1_FORCE;
2281                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2282         } else {
2283                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2284                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2285                 if (ch == DPIO_CH0)
2286                         val |= CHV_BUFLEFTENA2_FORCE;
2287                 if (ch == DPIO_CH1)
2288                         val |= CHV_BUFRIGHTENA2_FORCE;
2289                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2290         }
2291
2292         /* program clock channel usage */
2293         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2294         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2295         if (pipe != PIPE_B)
2296                 val &= ~CHV_PCS_USEDCLKCHANNEL;
2297         else
2298                 val |= CHV_PCS_USEDCLKCHANNEL;
2299         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2300
2301         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2302         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2303         if (pipe != PIPE_B)
2304                 val &= ~CHV_PCS_USEDCLKCHANNEL;
2305         else
2306                 val |= CHV_PCS_USEDCLKCHANNEL;
2307         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2308
2309         /*
2310          * This a a bit weird since generally CL
2311          * matches the pipe, but here we need to
2312          * pick the CL based on the port.
2313          */
2314         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2315         if (pipe != PIPE_B)
2316                 val &= ~CHV_CMN_USEDCLKCHANNEL;
2317         else
2318                 val |= CHV_CMN_USEDCLKCHANNEL;
2319         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2320
2321         mutex_unlock(&dev_priv->dpio_lock);
2322 }
2323
2324 /*
2325  * Native read with retry for link status and receiver capability reads for
2326  * cases where the sink may still be asleep.
2327  *
2328  * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2329  * supposed to retry 3 times per the spec.
2330  */
2331 static ssize_t
2332 intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2333                         void *buffer, size_t size)
2334 {
2335         ssize_t ret;
2336         int i;
2337
2338         for (i = 0; i < 3; i++) {
2339                 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2340                 if (ret == size)
2341                         return ret;
2342                 msleep(1);
2343         }
2344
2345         return ret;
2346 }
2347
2348 /*
2349  * Fetch AUX CH registers 0x202 - 0x207 which contain
2350  * link status information
2351  */
2352 static bool
2353 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2354 {
2355         return intel_dp_dpcd_read_wake(&intel_dp->aux,
2356                                        DP_LANE0_1_STATUS,
2357                                        link_status,
2358                                        DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
2359 }
2360
2361 /* These are source-specific values. */
2362 static uint8_t
2363 intel_dp_voltage_max(struct intel_dp *intel_dp)
2364 {
2365         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2366         enum port port = dp_to_dig_port(intel_dp)->port;
2367
2368         if (IS_VALLEYVIEW(dev))
2369                 return DP_TRAIN_VOLTAGE_SWING_1200;
2370         else if (IS_GEN7(dev) && port == PORT_A)
2371                 return DP_TRAIN_VOLTAGE_SWING_800;
2372         else if (HAS_PCH_CPT(dev) && port != PORT_A)
2373                 return DP_TRAIN_VOLTAGE_SWING_1200;
2374         else
2375                 return DP_TRAIN_VOLTAGE_SWING_800;
2376 }
2377
2378 static uint8_t
2379 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2380 {
2381         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2382         enum port port = dp_to_dig_port(intel_dp)->port;
2383
2384         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2385                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2386                 case DP_TRAIN_VOLTAGE_SWING_400:
2387                         return DP_TRAIN_PRE_EMPHASIS_9_5;
2388                 case DP_TRAIN_VOLTAGE_SWING_600:
2389                         return DP_TRAIN_PRE_EMPHASIS_6;
2390                 case DP_TRAIN_VOLTAGE_SWING_800:
2391                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2392                 case DP_TRAIN_VOLTAGE_SWING_1200:
2393                 default:
2394                         return DP_TRAIN_PRE_EMPHASIS_0;
2395                 }
2396         } else if (IS_VALLEYVIEW(dev)) {
2397                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2398                 case DP_TRAIN_VOLTAGE_SWING_400:
2399                         return DP_TRAIN_PRE_EMPHASIS_9_5;
2400                 case DP_TRAIN_VOLTAGE_SWING_600:
2401                         return DP_TRAIN_PRE_EMPHASIS_6;
2402                 case DP_TRAIN_VOLTAGE_SWING_800:
2403                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2404                 case DP_TRAIN_VOLTAGE_SWING_1200:
2405                 default:
2406                         return DP_TRAIN_PRE_EMPHASIS_0;
2407                 }
2408         } else if (IS_GEN7(dev) && port == PORT_A) {
2409                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2410                 case DP_TRAIN_VOLTAGE_SWING_400:
2411                         return DP_TRAIN_PRE_EMPHASIS_6;
2412                 case DP_TRAIN_VOLTAGE_SWING_600:
2413                 case DP_TRAIN_VOLTAGE_SWING_800:
2414                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2415                 default:
2416                         return DP_TRAIN_PRE_EMPHASIS_0;
2417                 }
2418         } else {
2419                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2420                 case DP_TRAIN_VOLTAGE_SWING_400:
2421                         return DP_TRAIN_PRE_EMPHASIS_6;
2422                 case DP_TRAIN_VOLTAGE_SWING_600:
2423                         return DP_TRAIN_PRE_EMPHASIS_6;
2424                 case DP_TRAIN_VOLTAGE_SWING_800:
2425                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2426                 case DP_TRAIN_VOLTAGE_SWING_1200:
2427                 default:
2428                         return DP_TRAIN_PRE_EMPHASIS_0;
2429                 }
2430         }
2431 }
2432
2433 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2434 {
2435         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2436         struct drm_i915_private *dev_priv = dev->dev_private;
2437         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2438         struct intel_crtc *intel_crtc =
2439                 to_intel_crtc(dport->base.base.crtc);
2440         unsigned long demph_reg_value, preemph_reg_value,
2441                 uniqtranscale_reg_value;
2442         uint8_t train_set = intel_dp->train_set[0];
2443         enum dpio_channel port = vlv_dport_to_channel(dport);
2444         int pipe = intel_crtc->pipe;
2445
2446         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2447         case DP_TRAIN_PRE_EMPHASIS_0:
2448                 preemph_reg_value = 0x0004000;
2449                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2450                 case DP_TRAIN_VOLTAGE_SWING_400:
2451                         demph_reg_value = 0x2B405555;
2452                         uniqtranscale_reg_value = 0x552AB83A;
2453                         break;
2454                 case DP_TRAIN_VOLTAGE_SWING_600:
2455                         demph_reg_value = 0x2B404040;
2456                         uniqtranscale_reg_value = 0x5548B83A;
2457                         break;
2458                 case DP_TRAIN_VOLTAGE_SWING_800:
2459                         demph_reg_value = 0x2B245555;
2460                         uniqtranscale_reg_value = 0x5560B83A;
2461                         break;
2462                 case DP_TRAIN_VOLTAGE_SWING_1200:
2463                         demph_reg_value = 0x2B405555;
2464                         uniqtranscale_reg_value = 0x5598DA3A;
2465                         break;
2466                 default:
2467                         return 0;
2468                 }
2469                 break;
2470         case DP_TRAIN_PRE_EMPHASIS_3_5:
2471                 preemph_reg_value = 0x0002000;
2472                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2473                 case DP_TRAIN_VOLTAGE_SWING_400:
2474                         demph_reg_value = 0x2B404040;
2475                         uniqtranscale_reg_value = 0x5552B83A;
2476                         break;
2477                 case DP_TRAIN_VOLTAGE_SWING_600:
2478                         demph_reg_value = 0x2B404848;
2479                         uniqtranscale_reg_value = 0x5580B83A;
2480                         break;
2481                 case DP_TRAIN_VOLTAGE_SWING_800:
2482                         demph_reg_value = 0x2B404040;
2483                         uniqtranscale_reg_value = 0x55ADDA3A;
2484                         break;
2485                 default:
2486                         return 0;
2487                 }
2488                 break;
2489         case DP_TRAIN_PRE_EMPHASIS_6:
2490                 preemph_reg_value = 0x0000000;
2491                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2492                 case DP_TRAIN_VOLTAGE_SWING_400:
2493                         demph_reg_value = 0x2B305555;
2494                         uniqtranscale_reg_value = 0x5570B83A;
2495                         break;
2496                 case DP_TRAIN_VOLTAGE_SWING_600:
2497                         demph_reg_value = 0x2B2B4040;
2498                         uniqtranscale_reg_value = 0x55ADDA3A;
2499                         break;
2500                 default:
2501                         return 0;
2502                 }
2503                 break;
2504         case DP_TRAIN_PRE_EMPHASIS_9_5:
2505                 preemph_reg_value = 0x0006000;
2506                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2507                 case DP_TRAIN_VOLTAGE_SWING_400:
2508                         demph_reg_value = 0x1B405555;
2509                         uniqtranscale_reg_value = 0x55ADDA3A;
2510                         break;
2511                 default:
2512                         return 0;
2513                 }
2514                 break;
2515         default:
2516                 return 0;
2517         }
2518
2519         mutex_lock(&dev_priv->dpio_lock);
2520         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2521         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2522         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
2523                          uniqtranscale_reg_value);
2524         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2525         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2526         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2527         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
2528         mutex_unlock(&dev_priv->dpio_lock);
2529
2530         return 0;
2531 }
2532
2533 static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2534 {
2535         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2536         struct drm_i915_private *dev_priv = dev->dev_private;
2537         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2538         struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
2539         u32 deemph_reg_value, margin_reg_value, val;
2540         uint8_t train_set = intel_dp->train_set[0];
2541         enum dpio_channel ch = vlv_dport_to_channel(dport);
2542         enum pipe pipe = intel_crtc->pipe;
2543         int i;
2544
2545         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2546         case DP_TRAIN_PRE_EMPHASIS_0:
2547                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2548                 case DP_TRAIN_VOLTAGE_SWING_400:
2549                         deemph_reg_value = 128;
2550                         margin_reg_value = 52;
2551                         break;
2552                 case DP_TRAIN_VOLTAGE_SWING_600:
2553                         deemph_reg_value = 128;
2554                         margin_reg_value = 77;
2555                         break;
2556                 case DP_TRAIN_VOLTAGE_SWING_800:
2557                         deemph_reg_value = 128;
2558                         margin_reg_value = 102;
2559                         break;
2560                 case DP_TRAIN_VOLTAGE_SWING_1200:
2561                         deemph_reg_value = 128;
2562                         margin_reg_value = 154;
2563                         /* FIXME extra to set for 1200 */
2564                         break;
2565                 default:
2566                         return 0;
2567                 }
2568                 break;
2569         case DP_TRAIN_PRE_EMPHASIS_3_5:
2570                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2571                 case DP_TRAIN_VOLTAGE_SWING_400:
2572                         deemph_reg_value = 85;
2573                         margin_reg_value = 78;
2574                         break;
2575                 case DP_TRAIN_VOLTAGE_SWING_600:
2576                         deemph_reg_value = 85;
2577                         margin_reg_value = 116;
2578                         break;
2579                 case DP_TRAIN_VOLTAGE_SWING_800:
2580                         deemph_reg_value = 85;
2581                         margin_reg_value = 154;
2582                         break;
2583                 default:
2584                         return 0;
2585                 }
2586                 break;
2587         case DP_TRAIN_PRE_EMPHASIS_6:
2588                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2589                 case DP_TRAIN_VOLTAGE_SWING_400:
2590                         deemph_reg_value = 64;
2591                         margin_reg_value = 104;
2592                         break;
2593                 case DP_TRAIN_VOLTAGE_SWING_600:
2594                         deemph_reg_value = 64;
2595                         margin_reg_value = 154;
2596                         break;
2597                 default:
2598                         return 0;
2599                 }
2600                 break;
2601         case DP_TRAIN_PRE_EMPHASIS_9_5:
2602                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2603                 case DP_TRAIN_VOLTAGE_SWING_400:
2604                         deemph_reg_value = 43;
2605                         margin_reg_value = 154;
2606                         break;
2607                 default:
2608                         return 0;
2609                 }
2610                 break;
2611         default:
2612                 return 0;
2613         }
2614
2615         mutex_lock(&dev_priv->dpio_lock);
2616
2617         /* Clear calc init */
2618         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2619         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2620         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2621
2622         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2623         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2624         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
2625
2626         /* Program swing deemph */
2627         for (i = 0; i < 4; i++) {
2628                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
2629                 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
2630                 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
2631                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
2632         }
2633
2634         /* Program swing margin */
2635         for (i = 0; i < 4; i++) {
2636                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2637                 val &= ~DPIO_SWING_MARGIN_MASK;
2638                 val |= margin_reg_value << DPIO_SWING_MARGIN_SHIFT;
2639                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2640         }
2641
2642         /* Disable unique transition scale */
2643         for (i = 0; i < 4; i++) {
2644                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2645                 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
2646                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2647         }
2648
2649         if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
2650                         == DP_TRAIN_PRE_EMPHASIS_0) &&
2651                 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
2652                         == DP_TRAIN_VOLTAGE_SWING_1200)) {
2653
2654                 /*
2655                  * The document said it needs to set bit 27 for ch0 and bit 26
2656                  * for ch1. Might be a typo in the doc.
2657                  * For now, for this unique transition scale selection, set bit
2658                  * 27 for ch0 and ch1.
2659                  */
2660                 for (i = 0; i < 4; i++) {
2661                         val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2662                         val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
2663                         vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2664                 }
2665
2666                 for (i = 0; i < 4; i++) {
2667                         val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2668                         val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2669                         val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2670                         vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2671                 }
2672         }
2673
2674         /* Start swing calculation */
2675         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2676         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2677         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2678
2679         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2680         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2681         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
2682
2683         /* LRC Bypass */
2684         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
2685         val |= DPIO_LRC_BYPASS;
2686         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
2687
2688         mutex_unlock(&dev_priv->dpio_lock);
2689
2690         return 0;
2691 }
2692
2693 static void
2694 intel_get_adjust_train(struct intel_dp *intel_dp,
2695                        const uint8_t link_status[DP_LINK_STATUS_SIZE])
2696 {
2697         uint8_t v = 0;
2698         uint8_t p = 0;
2699         int lane;
2700         uint8_t voltage_max;
2701         uint8_t preemph_max;
2702
2703         for (lane = 0; lane < intel_dp->lane_count; lane++) {
2704                 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2705                 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
2706
2707                 if (this_v > v)
2708                         v = this_v;
2709                 if (this_p > p)
2710                         p = this_p;
2711         }
2712
2713         voltage_max = intel_dp_voltage_max(intel_dp);
2714         if (v >= voltage_max)
2715                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
2716
2717         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2718         if (p >= preemph_max)
2719                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2720
2721         for (lane = 0; lane < 4; lane++)
2722                 intel_dp->train_set[lane] = v | p;
2723 }
2724
2725 static uint32_t
2726 intel_gen4_signal_levels(uint8_t train_set)
2727 {
2728         uint32_t        signal_levels = 0;
2729
2730         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2731         case DP_TRAIN_VOLTAGE_SWING_400:
2732         default:
2733                 signal_levels |= DP_VOLTAGE_0_4;
2734                 break;
2735         case DP_TRAIN_VOLTAGE_SWING_600:
2736                 signal_levels |= DP_VOLTAGE_0_6;
2737                 break;
2738         case DP_TRAIN_VOLTAGE_SWING_800:
2739                 signal_levels |= DP_VOLTAGE_0_8;
2740                 break;
2741         case DP_TRAIN_VOLTAGE_SWING_1200:
2742                 signal_levels |= DP_VOLTAGE_1_2;
2743                 break;
2744         }
2745         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2746         case DP_TRAIN_PRE_EMPHASIS_0:
2747         default:
2748                 signal_levels |= DP_PRE_EMPHASIS_0;
2749                 break;
2750         case DP_TRAIN_PRE_EMPHASIS_3_5:
2751                 signal_levels |= DP_PRE_EMPHASIS_3_5;
2752                 break;
2753         case DP_TRAIN_PRE_EMPHASIS_6:
2754                 signal_levels |= DP_PRE_EMPHASIS_6;
2755                 break;
2756         case DP_TRAIN_PRE_EMPHASIS_9_5:
2757                 signal_levels |= DP_PRE_EMPHASIS_9_5;
2758                 break;
2759         }
2760         return signal_levels;
2761 }
2762
2763 /* Gen6's DP voltage swing and pre-emphasis control */
2764 static uint32_t
2765 intel_gen6_edp_signal_levels(uint8_t train_set)
2766 {
2767         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2768                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2769         switch (signal_levels) {
2770         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2771         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2772                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2773         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2774                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
2775         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2776         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2777                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
2778         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2779         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2780                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
2781         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2782         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2783                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
2784         default:
2785                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2786                               "0x%x\n", signal_levels);
2787                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2788         }
2789 }
2790
2791 /* Gen7's DP voltage swing and pre-emphasis control */
2792 static uint32_t
2793 intel_gen7_edp_signal_levels(uint8_t train_set)
2794 {
2795         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2796                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2797         switch (signal_levels) {
2798         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2799                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2800         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2801                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2802         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2803                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2804
2805         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2806                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2807         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2808                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2809
2810         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2811                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2812         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2813                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2814
2815         default:
2816                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2817                               "0x%x\n", signal_levels);
2818                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2819         }
2820 }
2821
2822 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2823 static uint32_t
2824 intel_hsw_signal_levels(uint8_t train_set)
2825 {
2826         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2827                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2828         switch (signal_levels) {
2829         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2830                 return DDI_BUF_EMP_400MV_0DB_HSW;
2831         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2832                 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2833         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2834                 return DDI_BUF_EMP_400MV_6DB_HSW;
2835         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2836                 return DDI_BUF_EMP_400MV_9_5DB_HSW;
2837
2838         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2839                 return DDI_BUF_EMP_600MV_0DB_HSW;
2840         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2841                 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2842         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2843                 return DDI_BUF_EMP_600MV_6DB_HSW;
2844
2845         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2846                 return DDI_BUF_EMP_800MV_0DB_HSW;
2847         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2848                 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2849         default:
2850                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2851                               "0x%x\n", signal_levels);
2852                 return DDI_BUF_EMP_400MV_0DB_HSW;
2853         }
2854 }
2855
2856 /* Properly updates "DP" with the correct signal levels. */
2857 static void
2858 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2859 {
2860         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2861         enum port port = intel_dig_port->port;
2862         struct drm_device *dev = intel_dig_port->base.base.dev;
2863         uint32_t signal_levels, mask;
2864         uint8_t train_set = intel_dp->train_set[0];
2865
2866         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2867                 signal_levels = intel_hsw_signal_levels(train_set);
2868                 mask = DDI_BUF_EMP_MASK;
2869         } else if (IS_CHERRYVIEW(dev)) {
2870                 signal_levels = intel_chv_signal_levels(intel_dp);
2871                 mask = 0;
2872         } else if (IS_VALLEYVIEW(dev)) {
2873                 signal_levels = intel_vlv_signal_levels(intel_dp);
2874                 mask = 0;
2875         } else if (IS_GEN7(dev) && port == PORT_A) {
2876                 signal_levels = intel_gen7_edp_signal_levels(train_set);
2877                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
2878         } else if (IS_GEN6(dev) && port == PORT_A) {
2879                 signal_levels = intel_gen6_edp_signal_levels(train_set);
2880                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2881         } else {
2882                 signal_levels = intel_gen4_signal_levels(train_set);
2883                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2884         }
2885
2886         DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2887
2888         *DP = (*DP & ~mask) | signal_levels;
2889 }
2890
2891 static bool
2892 intel_dp_set_link_train(struct intel_dp *intel_dp,
2893                         uint32_t *DP,
2894                         uint8_t dp_train_pat)
2895 {
2896         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2897         struct drm_device *dev = intel_dig_port->base.base.dev;
2898         struct drm_i915_private *dev_priv = dev->dev_private;
2899         enum port port = intel_dig_port->port;
2900         uint8_t buf[sizeof(intel_dp->train_set) + 1];
2901         int ret, len;
2902
2903         if (HAS_DDI(dev)) {
2904                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2905
2906                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2907                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2908                 else
2909                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2910
2911                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2912                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2913                 case DP_TRAINING_PATTERN_DISABLE:
2914                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2915
2916                         break;
2917                 case DP_TRAINING_PATTERN_1:
2918                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2919                         break;
2920                 case DP_TRAINING_PATTERN_2:
2921                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2922                         break;
2923                 case DP_TRAINING_PATTERN_3:
2924                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2925                         break;
2926                 }
2927                 I915_WRITE(DP_TP_CTL(port), temp);
2928
2929         } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2930                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2931
2932                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2933                 case DP_TRAINING_PATTERN_DISABLE:
2934                         *DP |= DP_LINK_TRAIN_OFF_CPT;
2935                         break;
2936                 case DP_TRAINING_PATTERN_1:
2937                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2938                         break;
2939                 case DP_TRAINING_PATTERN_2:
2940                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2941                         break;
2942                 case DP_TRAINING_PATTERN_3:
2943                         DRM_ERROR("DP training pattern 3 not supported\n");
2944                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2945                         break;
2946                 }
2947
2948         } else {
2949                 *DP &= ~DP_LINK_TRAIN_MASK;
2950
2951                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2952                 case DP_TRAINING_PATTERN_DISABLE:
2953                         *DP |= DP_LINK_TRAIN_OFF;
2954                         break;
2955                 case DP_TRAINING_PATTERN_1:
2956                         *DP |= DP_LINK_TRAIN_PAT_1;
2957                         break;
2958                 case DP_TRAINING_PATTERN_2:
2959                         *DP |= DP_LINK_TRAIN_PAT_2;
2960                         break;
2961                 case DP_TRAINING_PATTERN_3:
2962                         DRM_ERROR("DP training pattern 3 not supported\n");
2963                         *DP |= DP_LINK_TRAIN_PAT_2;
2964                         break;
2965                 }
2966         }
2967
2968         I915_WRITE(intel_dp->output_reg, *DP);
2969         POSTING_READ(intel_dp->output_reg);
2970
2971         buf[0] = dp_train_pat;
2972         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
2973             DP_TRAINING_PATTERN_DISABLE) {
2974                 /* don't write DP_TRAINING_LANEx_SET on disable */
2975                 len = 1;
2976         } else {
2977                 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2978                 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2979                 len = intel_dp->lane_count + 1;
2980         }
2981
2982         ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
2983                                 buf, len);
2984
2985         return ret == len;
2986 }
2987
2988 static bool
2989 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2990                         uint8_t dp_train_pat)
2991 {
2992         memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
2993         intel_dp_set_signal_levels(intel_dp, DP);
2994         return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2995 }
2996
2997 static bool
2998 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2999                            const uint8_t link_status[DP_LINK_STATUS_SIZE])
3000 {
3001         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3002         struct drm_device *dev = intel_dig_port->base.base.dev;
3003         struct drm_i915_private *dev_priv = dev->dev_private;
3004         int ret;
3005
3006         intel_get_adjust_train(intel_dp, link_status);
3007         intel_dp_set_signal_levels(intel_dp, DP);
3008
3009         I915_WRITE(intel_dp->output_reg, *DP);
3010         POSTING_READ(intel_dp->output_reg);
3011
3012         ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3013                                 intel_dp->train_set, intel_dp->lane_count);
3014
3015         return ret == intel_dp->lane_count;
3016 }
3017
3018 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3019 {
3020         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3021         struct drm_device *dev = intel_dig_port->base.base.dev;
3022         struct drm_i915_private *dev_priv = dev->dev_private;
3023         enum port port = intel_dig_port->port;
3024         uint32_t val;
3025
3026         if (!HAS_DDI(dev))
3027                 return;
3028
3029         val = I915_READ(DP_TP_CTL(port));
3030         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3031         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3032         I915_WRITE(DP_TP_CTL(port), val);
3033
3034         /*
3035          * On PORT_A we can have only eDP in SST mode. There the only reason
3036          * we need to set idle transmission mode is to work around a HW issue
3037          * where we enable the pipe while not in idle link-training mode.
3038          * In this case there is requirement to wait for a minimum number of
3039          * idle patterns to be sent.
3040          */
3041         if (port == PORT_A)
3042                 return;
3043
3044         if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3045                      1))
3046                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3047 }
3048
3049 /* Enable corresponding port and start training pattern 1 */
3050 void
3051 intel_dp_start_link_train(struct intel_dp *intel_dp)
3052 {
3053         struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
3054         struct drm_device *dev = encoder->dev;
3055         int i;
3056         uint8_t voltage;
3057         int voltage_tries, loop_tries;
3058         uint32_t DP = intel_dp->DP;
3059         uint8_t link_config[2];
3060
3061         if (HAS_DDI(dev))
3062                 intel_ddi_prepare_link_retrain(encoder);
3063
3064         /* Write the link configuration data */
3065         link_config[0] = intel_dp->link_bw;
3066         link_config[1] = intel_dp->lane_count;
3067         if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3068                 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
3069         drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
3070
3071         link_config[0] = 0;
3072         link_config[1] = DP_SET_ANSI_8B10B;
3073         drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
3074
3075         DP |= DP_PORT_EN;
3076
3077         /* clock recovery */
3078         if (!intel_dp_reset_link_train(intel_dp, &DP,
3079                                        DP_TRAINING_PATTERN_1 |
3080                                        DP_LINK_SCRAMBLING_DISABLE)) {
3081                 DRM_ERROR("failed to enable link training\n");
3082                 return;
3083         }
3084
3085         voltage = 0xff;
3086         voltage_tries = 0;
3087         loop_tries = 0;
3088         for (;;) {
3089                 uint8_t link_status[DP_LINK_STATUS_SIZE];
3090
3091                 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
3092                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3093                         DRM_ERROR("failed to get link status\n");
3094                         break;
3095                 }
3096
3097                 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3098                         DRM_DEBUG_KMS("clock recovery OK\n");
3099                         break;
3100                 }
3101
3102                 /* Check to see if we've tried the max voltage */
3103                 for (i = 0; i < intel_dp->lane_count; i++)
3104                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
3105                                 break;
3106                 if (i == intel_dp->lane_count) {
3107                         ++loop_tries;
3108                         if (loop_tries == 5) {
3109                                 DRM_ERROR("too many full retries, give up\n");
3110                                 break;
3111                         }
3112                         intel_dp_reset_link_train(intel_dp, &DP,
3113                                                   DP_TRAINING_PATTERN_1 |
3114                                                   DP_LINK_SCRAMBLING_DISABLE);
3115                         voltage_tries = 0;
3116                         continue;
3117                 }
3118
3119                 /* Check to see if we've tried the same voltage 5 times */
3120                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
3121                         ++voltage_tries;
3122                         if (voltage_tries == 5) {
3123                                 DRM_ERROR("too many voltage retries, give up\n");
3124                                 break;
3125                         }
3126                 } else
3127                         voltage_tries = 0;
3128                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
3129
3130                 /* Update training set as requested by target */
3131                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3132                         DRM_ERROR("failed to update link training\n");
3133                         break;
3134                 }
3135         }
3136
3137         intel_dp->DP = DP;
3138 }
3139
3140 void
3141 intel_dp_complete_link_train(struct intel_dp *intel_dp)
3142 {
3143         bool channel_eq = false;
3144         int tries, cr_tries;
3145         uint32_t DP = intel_dp->DP;
3146         uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3147
3148         /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3149         if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3150                 training_pattern = DP_TRAINING_PATTERN_3;
3151
3152         /* channel equalization */
3153         if (!intel_dp_set_link_train(intel_dp, &DP,
3154                                      training_pattern |
3155                                      DP_LINK_SCRAMBLING_DISABLE)) {
3156                 DRM_ERROR("failed to start channel equalization\n");
3157                 return;
3158         }
3159
3160         tries = 0;
3161         cr_tries = 0;
3162         channel_eq = false;
3163         for (;;) {
3164                 uint8_t link_status[DP_LINK_STATUS_SIZE];
3165
3166                 if (cr_tries > 5) {
3167                         DRM_ERROR("failed to train DP, aborting\n");
3168                         break;
3169                 }
3170
3171                 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
3172                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3173                         DRM_ERROR("failed to get link status\n");
3174                         break;
3175                 }
3176
3177                 /* Make sure clock is still ok */
3178                 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3179                         intel_dp_start_link_train(intel_dp);
3180                         intel_dp_set_link_train(intel_dp, &DP,
3181                                                 training_pattern |
3182                                                 DP_LINK_SCRAMBLING_DISABLE);
3183                         cr_tries++;
3184                         continue;
3185                 }
3186
3187                 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3188                         channel_eq = true;
3189                         break;
3190                 }
3191
3192                 /* Try 5 times, then try clock recovery if that fails */
3193                 if (tries > 5) {
3194                         intel_dp_link_down(intel_dp);
3195                         intel_dp_start_link_train(intel_dp);
3196                         intel_dp_set_link_train(intel_dp, &DP,
3197                                                 training_pattern |
3198                                                 DP_LINK_SCRAMBLING_DISABLE);
3199                         tries = 0;
3200                         cr_tries++;
3201                         continue;
3202                 }
3203
3204                 /* Update training set as requested by target */
3205                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3206                         DRM_ERROR("failed to update link training\n");
3207                         break;
3208                 }
3209                 ++tries;
3210         }
3211
3212         intel_dp_set_idle_link_train(intel_dp);
3213
3214         intel_dp->DP = DP;
3215
3216         if (channel_eq)
3217                 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3218
3219 }
3220
3221 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3222 {
3223         intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3224                                 DP_TRAINING_PATTERN_DISABLE);
3225 }
3226
3227 static void
3228 intel_dp_link_down(struct intel_dp *intel_dp)
3229 {
3230         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3231         enum port port = intel_dig_port->port;
3232         struct drm_device *dev = intel_dig_port->base.base.dev;
3233         struct drm_i915_private *dev_priv = dev->dev_private;
3234         struct intel_crtc *intel_crtc =
3235                 to_intel_crtc(intel_dig_port->base.base.crtc);
3236         uint32_t DP = intel_dp->DP;
3237
3238         if (WARN_ON(HAS_DDI(dev)))
3239                 return;
3240
3241         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3242                 return;
3243
3244         DRM_DEBUG_KMS("\n");
3245
3246         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
3247                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3248                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
3249         } else {
3250                 DP &= ~DP_LINK_TRAIN_MASK;
3251                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
3252         }
3253         POSTING_READ(intel_dp->output_reg);
3254
3255         if (HAS_PCH_IBX(dev) &&
3256             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
3257                 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
3258
3259                 /* Hardware workaround: leaving our transcoder select
3260                  * set to transcoder B while it's off will prevent the
3261                  * corresponding HDMI output on transcoder A.
3262                  *
3263                  * Combine this with another hardware workaround:
3264                  * transcoder select bit can only be cleared while the
3265                  * port is enabled.
3266                  */
3267                 DP &= ~DP_PIPEB_SELECT;
3268                 I915_WRITE(intel_dp->output_reg, DP);
3269
3270                 /* Changes to enable or select take place the vblank
3271                  * after being written.
3272                  */
3273                 if (WARN_ON(crtc == NULL)) {
3274                         /* We should never try to disable a port without a crtc
3275                          * attached. For paranoia keep the code around for a
3276                          * bit. */
3277                         POSTING_READ(intel_dp->output_reg);
3278                         msleep(50);
3279                 } else
3280                         intel_wait_for_vblank(dev, intel_crtc->pipe);
3281         }
3282
3283         DP &= ~DP_AUDIO_OUTPUT_ENABLE;
3284         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3285         POSTING_READ(intel_dp->output_reg);
3286         msleep(intel_dp->panel_power_down_delay);
3287 }
3288
3289 static bool
3290 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3291 {
3292         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3293         struct drm_device *dev = dig_port->base.base.dev;
3294         struct drm_i915_private *dev_priv = dev->dev_private;
3295
3296         char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
3297
3298         if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3299                                     sizeof(intel_dp->dpcd)) < 0)
3300                 return false; /* aux transfer failed */
3301
3302         hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
3303                            32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
3304         DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
3305
3306         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3307                 return false; /* DPCD not present */
3308
3309         /* Check if the panel supports PSR */
3310         memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
3311         if (is_edp(intel_dp)) {
3312                 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3313                                         intel_dp->psr_dpcd,
3314                                         sizeof(intel_dp->psr_dpcd));
3315                 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3316                         dev_priv->psr.sink_support = true;
3317                         DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3318                 }
3319         }
3320
3321         /* Training Pattern 3 support */
3322         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3323             intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3324                 intel_dp->use_tps3 = true;
3325                 DRM_DEBUG_KMS("Displayport TPS3 supported");
3326         } else
3327                 intel_dp->use_tps3 = false;
3328
3329         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3330               DP_DWN_STRM_PORT_PRESENT))
3331                 return true; /* native DP sink */
3332
3333         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3334                 return true; /* no per-port downstream info */
3335
3336         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3337                                     intel_dp->downstream_ports,
3338                                     DP_MAX_DOWNSTREAM_PORTS) < 0)
3339                 return false; /* downstream port status fetch failed */
3340
3341         return true;
3342 }
3343
3344 static void
3345 intel_dp_probe_oui(struct intel_dp *intel_dp)
3346 {
3347         u8 buf[3];
3348
3349         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3350                 return;
3351
3352         intel_edp_panel_vdd_on(intel_dp);
3353
3354         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
3355                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3356                               buf[0], buf[1], buf[2]);
3357
3358         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
3359                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3360                               buf[0], buf[1], buf[2]);
3361
3362         edp_panel_vdd_off(intel_dp, false);
3363 }
3364
3365 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3366 {
3367         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3368         struct drm_device *dev = intel_dig_port->base.base.dev;
3369         struct intel_crtc *intel_crtc =
3370                 to_intel_crtc(intel_dig_port->base.base.crtc);
3371         u8 buf[1];
3372
3373         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
3374                 return -EAGAIN;
3375
3376         if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
3377                 return -ENOTTY;
3378
3379         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3380                                DP_TEST_SINK_START) < 0)
3381                 return -EAGAIN;
3382
3383         /* Wait 2 vblanks to be sure we will have the correct CRC value */
3384         intel_wait_for_vblank(dev, intel_crtc->pipe);
3385         intel_wait_for_vblank(dev, intel_crtc->pipe);
3386
3387         if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
3388                 return -EAGAIN;
3389
3390         drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
3391         return 0;
3392 }
3393
3394 static bool
3395 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3396 {
3397         return intel_dp_dpcd_read_wake(&intel_dp->aux,
3398                                        DP_DEVICE_SERVICE_IRQ_VECTOR,
3399                                        sink_irq_vector, 1) == 1;
3400 }
3401
3402 static void
3403 intel_dp_handle_test_request(struct intel_dp *intel_dp)
3404 {
3405         /* NAK by default */
3406         drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
3407 }
3408
3409 /*
3410  * According to DP spec
3411  * 5.1.2:
3412  *  1. Read DPCD
3413  *  2. Configure link according to Receiver Capabilities
3414  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
3415  *  4. Check link status on receipt of hot-plug interrupt
3416  */
3417
3418 void
3419 intel_dp_check_link_status(struct intel_dp *intel_dp)
3420 {
3421         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
3422         u8 sink_irq_vector;
3423         u8 link_status[DP_LINK_STATUS_SIZE];
3424
3425         /* FIXME: This access isn't protected by any locks. */
3426         if (!intel_encoder->connectors_active)
3427                 return;
3428
3429         if (WARN_ON(!intel_encoder->base.crtc))
3430                 return;
3431
3432         /* Try to read receiver status if the link appears to be up */
3433         if (!intel_dp_get_link_status(intel_dp, link_status)) {
3434                 return;
3435         }
3436
3437         /* Now read the DPCD to see if it's actually running */
3438         if (!intel_dp_get_dpcd(intel_dp)) {
3439                 return;
3440         }
3441
3442         /* Try to read the source of the interrupt */
3443         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3444             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3445                 /* Clear interrupt source */
3446                 drm_dp_dpcd_writeb(&intel_dp->aux,
3447                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
3448                                    sink_irq_vector);
3449
3450                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3451                         intel_dp_handle_test_request(intel_dp);
3452                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3453                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3454         }
3455
3456         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3457                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3458                               intel_encoder->base.name);
3459                 intel_dp_start_link_train(intel_dp);
3460                 intel_dp_complete_link_train(intel_dp);
3461                 intel_dp_stop_link_train(intel_dp);
3462         }
3463 }
3464
3465 /* XXX this is probably wrong for multiple downstream ports */
3466 static enum drm_connector_status
3467 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
3468 {
3469         uint8_t *dpcd = intel_dp->dpcd;
3470         uint8_t type;
3471
3472         if (!intel_dp_get_dpcd(intel_dp))
3473                 return connector_status_disconnected;
3474
3475         /* if there's no downstream port, we're done */
3476         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
3477                 return connector_status_connected;
3478
3479         /* If we're HPD-aware, SINK_COUNT changes dynamically */
3480         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3481             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
3482                 uint8_t reg;
3483
3484                 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3485                                             &reg, 1) < 0)
3486                         return connector_status_unknown;
3487
3488                 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3489                                               : connector_status_disconnected;
3490         }
3491
3492         /* If no HPD, poke DDC gently */
3493         if (drm_probe_ddc(&intel_dp->aux.ddc))
3494                 return connector_status_connected;
3495
3496         /* Well we tried, say unknown for unreliable port types */
3497         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3498                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3499                 if (type == DP_DS_PORT_TYPE_VGA ||
3500                     type == DP_DS_PORT_TYPE_NON_EDID)
3501                         return connector_status_unknown;
3502         } else {
3503                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3504                         DP_DWN_STRM_PORT_TYPE_MASK;
3505                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3506                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
3507                         return connector_status_unknown;
3508         }
3509
3510         /* Anything else is out of spec, warn and ignore */
3511         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
3512         return connector_status_disconnected;
3513 }
3514
3515 static enum drm_connector_status
3516 ironlake_dp_detect(struct intel_dp *intel_dp)
3517 {
3518         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3519         struct drm_i915_private *dev_priv = dev->dev_private;
3520         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3521         enum drm_connector_status status;
3522
3523         /* Can't disconnect eDP, but you can close the lid... */
3524         if (is_edp(intel_dp)) {
3525                 status = intel_panel_detect(dev);
3526                 if (status == connector_status_unknown)
3527                         status = connector_status_connected;
3528                 return status;
3529         }
3530
3531         if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3532                 return connector_status_disconnected;
3533
3534         return intel_dp_detect_dpcd(intel_dp);
3535 }
3536
3537 static enum drm_connector_status
3538 g4x_dp_detect(struct intel_dp *intel_dp)
3539 {
3540         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3541         struct drm_i915_private *dev_priv = dev->dev_private;
3542         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3543         uint32_t bit;
3544
3545         /* Can't disconnect eDP, but you can close the lid... */
3546         if (is_edp(intel_dp)) {
3547                 enum drm_connector_status status;
3548
3549                 status = intel_panel_detect(dev);
3550                 if (status == connector_status_unknown)
3551                         status = connector_status_connected;
3552                 return status;
3553         }
3554
3555         if (IS_VALLEYVIEW(dev)) {
3556                 switch (intel_dig_port->port) {
3557                 case PORT_B:
3558                         bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3559                         break;
3560                 case PORT_C:
3561                         bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3562                         break;
3563                 case PORT_D:
3564                         bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3565                         break;
3566                 default:
3567                         return connector_status_unknown;
3568                 }
3569         } else {
3570                 switch (intel_dig_port->port) {
3571                 case PORT_B:
3572                         bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3573                         break;
3574                 case PORT_C:
3575                         bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3576                         break;
3577                 case PORT_D:
3578                         bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3579                         break;
3580                 default:
3581                         return connector_status_unknown;
3582                 }
3583         }
3584
3585         if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
3586                 return connector_status_disconnected;
3587
3588         return intel_dp_detect_dpcd(intel_dp);
3589 }
3590
3591 static struct edid *
3592 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3593 {
3594         struct intel_connector *intel_connector = to_intel_connector(connector);
3595
3596         /* use cached edid if we have one */
3597         if (intel_connector->edid) {
3598                 /* invalid edid */
3599                 if (IS_ERR(intel_connector->edid))
3600                         return NULL;
3601
3602                 return drm_edid_duplicate(intel_connector->edid);
3603         }
3604
3605         return drm_get_edid(connector, adapter);
3606 }
3607
3608 static int
3609 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3610 {
3611         struct intel_connector *intel_connector = to_intel_connector(connector);
3612
3613         /* use cached edid if we have one */
3614         if (intel_connector->edid) {
3615                 /* invalid edid */
3616                 if (IS_ERR(intel_connector->edid))
3617                         return 0;
3618
3619                 return intel_connector_update_modes(connector,
3620                                                     intel_connector->edid);
3621         }
3622
3623         return intel_ddc_get_modes(connector, adapter);
3624 }
3625
3626 static enum drm_connector_status
3627 intel_dp_detect(struct drm_connector *connector, bool force)
3628 {
3629         struct intel_dp *intel_dp = intel_attached_dp(connector);
3630         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3631         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3632         struct drm_device *dev = connector->dev;
3633         struct drm_i915_private *dev_priv = dev->dev_private;
3634         enum drm_connector_status status;
3635         enum intel_display_power_domain power_domain;
3636         struct edid *edid = NULL;
3637
3638         intel_runtime_pm_get(dev_priv);
3639
3640         power_domain = intel_display_port_power_domain(intel_encoder);
3641         intel_display_power_get(dev_priv, power_domain);
3642
3643         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3644                       connector->base.id, connector->name);
3645
3646         intel_dp->has_audio = false;
3647
3648         if (HAS_PCH_SPLIT(dev))
3649                 status = ironlake_dp_detect(intel_dp);
3650         else
3651                 status = g4x_dp_detect(intel_dp);
3652
3653         if (status != connector_status_connected)
3654                 goto out;
3655
3656         intel_dp_probe_oui(intel_dp);
3657
3658         if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3659                 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
3660         } else {
3661                 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
3662                 if (edid) {
3663                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
3664                         kfree(edid);
3665                 }
3666         }
3667
3668         if (intel_encoder->type != INTEL_OUTPUT_EDP)
3669                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3670         status = connector_status_connected;
3671
3672 out:
3673         intel_display_power_put(dev_priv, power_domain);
3674
3675         intel_runtime_pm_put(dev_priv);
3676
3677         return status;
3678 }
3679
3680 static int intel_dp_get_modes(struct drm_connector *connector)
3681 {
3682         struct intel_dp *intel_dp = intel_attached_dp(connector);
3683         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3684         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3685         struct intel_connector *intel_connector = to_intel_connector(connector);
3686         struct drm_device *dev = connector->dev;
3687         struct drm_i915_private *dev_priv = dev->dev_private;
3688         enum intel_display_power_domain power_domain;
3689         int ret;
3690
3691         /* We should parse the EDID data and find out if it has an audio sink
3692          */
3693
3694         power_domain = intel_display_port_power_domain(intel_encoder);
3695         intel_display_power_get(dev_priv, power_domain);
3696
3697         ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
3698         intel_display_power_put(dev_priv, power_domain);
3699         if (ret)
3700                 return ret;
3701
3702         /* if eDP has no EDID, fall back to fixed mode */
3703         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
3704                 struct drm_display_mode *mode;
3705                 mode = drm_mode_duplicate(dev,
3706                                           intel_connector->panel.fixed_mode);
3707                 if (mode) {
3708                         drm_mode_probed_add(connector, mode);
3709                         return 1;
3710                 }
3711         }
3712         return 0;
3713 }
3714
3715 static bool
3716 intel_dp_detect_audio(struct drm_connector *connector)
3717 {
3718         struct intel_dp *intel_dp = intel_attached_dp(connector);
3719         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3720         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3721         struct drm_device *dev = connector->dev;
3722         struct drm_i915_private *dev_priv = dev->dev_private;
3723         enum intel_display_power_domain power_domain;
3724         struct edid *edid;
3725         bool has_audio = false;
3726
3727         power_domain = intel_display_port_power_domain(intel_encoder);
3728         intel_display_power_get(dev_priv, power_domain);
3729
3730         edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
3731         if (edid) {
3732                 has_audio = drm_detect_monitor_audio(edid);
3733                 kfree(edid);
3734         }
3735
3736         intel_display_power_put(dev_priv, power_domain);
3737
3738         return has_audio;
3739 }
3740
3741 static int
3742 intel_dp_set_property(struct drm_connector *connector,
3743                       struct drm_property *property,
3744                       uint64_t val)
3745 {
3746         struct drm_i915_private *dev_priv = connector->dev->dev_private;
3747         struct intel_connector *intel_connector = to_intel_connector(connector);
3748         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3749         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3750         int ret;
3751
3752         ret = drm_object_property_set_value(&connector->base, property, val);
3753         if (ret)
3754                 return ret;
3755
3756         if (property == dev_priv->force_audio_property) {
3757                 int i = val;
3758                 bool has_audio;
3759
3760                 if (i == intel_dp->force_audio)
3761                         return 0;
3762
3763                 intel_dp->force_audio = i;
3764
3765                 if (i == HDMI_AUDIO_AUTO)
3766                         has_audio = intel_dp_detect_audio(connector);
3767                 else
3768                         has_audio = (i == HDMI_AUDIO_ON);
3769
3770                 if (has_audio == intel_dp->has_audio)
3771                         return 0;
3772
3773                 intel_dp->has_audio = has_audio;
3774                 goto done;
3775         }
3776
3777         if (property == dev_priv->broadcast_rgb_property) {
3778                 bool old_auto = intel_dp->color_range_auto;
3779                 uint32_t old_range = intel_dp->color_range;
3780
3781                 switch (val) {
3782                 case INTEL_BROADCAST_RGB_AUTO:
3783                         intel_dp->color_range_auto = true;
3784                         break;
3785                 case INTEL_BROADCAST_RGB_FULL:
3786                         intel_dp->color_range_auto = false;
3787                         intel_dp->color_range = 0;
3788                         break;
3789                 case INTEL_BROADCAST_RGB_LIMITED:
3790                         intel_dp->color_range_auto = false;
3791                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
3792                         break;
3793                 default:
3794                         return -EINVAL;
3795                 }
3796
3797                 if (old_auto == intel_dp->color_range_auto &&
3798                     old_range == intel_dp->color_range)
3799                         return 0;
3800
3801                 goto done;
3802         }
3803
3804         if (is_edp(intel_dp) &&
3805             property == connector->dev->mode_config.scaling_mode_property) {
3806                 if (val == DRM_MODE_SCALE_NONE) {
3807                         DRM_DEBUG_KMS("no scaling not supported\n");
3808                         return -EINVAL;
3809                 }
3810
3811                 if (intel_connector->panel.fitting_mode == val) {
3812                         /* the eDP scaling property is not changed */
3813                         return 0;
3814                 }
3815                 intel_connector->panel.fitting_mode = val;
3816
3817                 goto done;
3818         }
3819
3820         return -EINVAL;
3821
3822 done:
3823         if (intel_encoder->base.crtc)
3824                 intel_crtc_restore_mode(intel_encoder->base.crtc);
3825
3826         return 0;
3827 }
3828
3829 static void
3830 intel_dp_connector_destroy(struct drm_connector *connector)
3831 {
3832         struct intel_connector *intel_connector = to_intel_connector(connector);
3833
3834         if (!IS_ERR_OR_NULL(intel_connector->edid))
3835                 kfree(intel_connector->edid);
3836
3837         /* Can't call is_edp() since the encoder may have been destroyed
3838          * already. */
3839         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3840                 intel_panel_fini(&intel_connector->panel);
3841
3842         drm_connector_cleanup(connector);
3843         kfree(connector);
3844 }
3845
3846 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
3847 {
3848         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3849         struct intel_dp *intel_dp = &intel_dig_port->dp;
3850         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3851
3852         drm_dp_aux_unregister(&intel_dp->aux);
3853         drm_encoder_cleanup(encoder);
3854         if (is_edp(intel_dp)) {
3855                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3856                 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
3857                 edp_panel_vdd_off_sync(intel_dp);
3858                 drm_modeset_unlock(&dev->mode_config.connection_mutex);
3859         }
3860         kfree(intel_dig_port);
3861 }
3862
3863 static const struct drm_connector_funcs intel_dp_connector_funcs = {
3864         .dpms = intel_connector_dpms,
3865         .detect = intel_dp_detect,
3866         .fill_modes = drm_helper_probe_single_connector_modes,
3867         .set_property = intel_dp_set_property,
3868         .destroy = intel_dp_connector_destroy,
3869 };
3870
3871 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3872         .get_modes = intel_dp_get_modes,
3873         .mode_valid = intel_dp_mode_valid,
3874         .best_encoder = intel_best_encoder,
3875 };
3876
3877 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
3878         .destroy = intel_dp_encoder_destroy,
3879 };
3880
3881 static void
3882 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
3883 {
3884         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3885
3886         intel_dp_check_link_status(intel_dp);
3887 }
3888
3889 bool
3890 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
3891 {
3892         struct intel_dp *intel_dp = &intel_dig_port->dp;
3893
3894         if (long_hpd)
3895                 return true;
3896
3897         /*
3898          * we'll check the link status via the normal hot plug path later -
3899          * but for short hpds we should check it now
3900          */
3901         intel_dp_check_link_status(intel_dp);
3902         return false;
3903 }
3904
3905 /* Return which DP Port should be selected for Transcoder DP control */
3906 int
3907 intel_trans_dp_port_sel(struct drm_crtc *crtc)
3908 {
3909         struct drm_device *dev = crtc->dev;
3910         struct intel_encoder *intel_encoder;
3911         struct intel_dp *intel_dp;
3912
3913         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3914                 intel_dp = enc_to_intel_dp(&intel_encoder->base);
3915
3916                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3917                     intel_encoder->type == INTEL_OUTPUT_EDP)
3918                         return intel_dp->output_reg;
3919         }
3920
3921         return -1;
3922 }
3923
3924 /* check the VBT to see whether the eDP is on DP-D port */
3925 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
3926 {
3927         struct drm_i915_private *dev_priv = dev->dev_private;
3928         union child_device_config *p_child;
3929         int i;
3930         static const short port_mapping[] = {
3931                 [PORT_B] = PORT_IDPB,
3932                 [PORT_C] = PORT_IDPC,
3933                 [PORT_D] = PORT_IDPD,
3934         };
3935
3936         if (port == PORT_A)
3937                 return true;
3938
3939         if (!dev_priv->vbt.child_dev_num)
3940                 return false;
3941
3942         for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3943                 p_child = dev_priv->vbt.child_dev + i;
3944
3945                 if (p_child->common.dvo_port == port_mapping[port] &&
3946                     (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3947                     (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
3948                         return true;
3949         }
3950         return false;
3951 }
3952
3953 static void
3954 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3955 {
3956         struct intel_connector *intel_connector = to_intel_connector(connector);
3957
3958         intel_attach_force_audio_property(connector);
3959         intel_attach_broadcast_rgb_property(connector);
3960         intel_dp->color_range_auto = true;
3961
3962         if (is_edp(intel_dp)) {
3963                 drm_mode_create_scaling_mode_property(connector->dev);
3964                 drm_object_attach_property(
3965                         &connector->base,
3966                         connector->dev->mode_config.scaling_mode_property,
3967                         DRM_MODE_SCALE_ASPECT);
3968                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
3969         }
3970 }
3971
3972 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
3973 {
3974         intel_dp->last_power_cycle = jiffies;
3975         intel_dp->last_power_on = jiffies;
3976         intel_dp->last_backlight_off = jiffies;
3977 }
3978
3979 static void
3980 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
3981                                     struct intel_dp *intel_dp,
3982                                     struct edp_power_seq *out)
3983 {
3984         struct drm_i915_private *dev_priv = dev->dev_private;
3985         struct edp_power_seq cur, vbt, spec, final;
3986         u32 pp_on, pp_off, pp_div, pp;
3987         int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
3988
3989         if (HAS_PCH_SPLIT(dev)) {
3990                 pp_ctrl_reg = PCH_PP_CONTROL;
3991                 pp_on_reg = PCH_PP_ON_DELAYS;
3992                 pp_off_reg = PCH_PP_OFF_DELAYS;
3993                 pp_div_reg = PCH_PP_DIVISOR;
3994         } else {
3995                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3996
3997                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3998                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3999                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4000                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
4001         }
4002
4003         /* Workaround: Need to write PP_CONTROL with the unlock key as
4004          * the very first thing. */
4005         pp = ironlake_get_pp_control(intel_dp);
4006         I915_WRITE(pp_ctrl_reg, pp);
4007
4008         pp_on = I915_READ(pp_on_reg);
4009         pp_off = I915_READ(pp_off_reg);
4010         pp_div = I915_READ(pp_div_reg);
4011
4012         /* Pull timing values out of registers */
4013         cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4014                 PANEL_POWER_UP_DELAY_SHIFT;
4015
4016         cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4017                 PANEL_LIGHT_ON_DELAY_SHIFT;
4018
4019         cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4020                 PANEL_LIGHT_OFF_DELAY_SHIFT;
4021
4022         cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4023                 PANEL_POWER_DOWN_DELAY_SHIFT;
4024
4025         cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4026                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4027
4028         DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4029                       cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4030
4031         vbt = dev_priv->vbt.edp_pps;
4032
4033         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4034          * our hw here, which are all in 100usec. */
4035         spec.t1_t3 = 210 * 10;
4036         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4037         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4038         spec.t10 = 500 * 10;
4039         /* This one is special and actually in units of 100ms, but zero
4040          * based in the hw (so we need to add 100 ms). But the sw vbt
4041          * table multiplies it with 1000 to make it in units of 100usec,
4042          * too. */
4043         spec.t11_t12 = (510 + 100) * 10;
4044
4045         DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4046                       vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4047
4048         /* Use the max of the register settings and vbt. If both are
4049          * unset, fall back to the spec limits. */
4050 #define assign_final(field)     final.field = (max(cur.field, vbt.field) == 0 ? \
4051                                        spec.field : \
4052                                        max(cur.field, vbt.field))
4053         assign_final(t1_t3);
4054         assign_final(t8);
4055         assign_final(t9);
4056         assign_final(t10);
4057         assign_final(t11_t12);
4058 #undef assign_final
4059
4060 #define get_delay(field)        (DIV_ROUND_UP(final.field, 10))
4061         intel_dp->panel_power_up_delay = get_delay(t1_t3);
4062         intel_dp->backlight_on_delay = get_delay(t8);
4063         intel_dp->backlight_off_delay = get_delay(t9);
4064         intel_dp->panel_power_down_delay = get_delay(t10);
4065         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4066 #undef get_delay
4067
4068         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4069                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4070                       intel_dp->panel_power_cycle_delay);
4071
4072         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4073                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4074
4075         if (out)
4076                 *out = final;
4077 }
4078
4079 static void
4080 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4081                                               struct intel_dp *intel_dp,
4082                                               struct edp_power_seq *seq)
4083 {
4084         struct drm_i915_private *dev_priv = dev->dev_private;
4085         u32 pp_on, pp_off, pp_div, port_sel = 0;
4086         int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4087         int pp_on_reg, pp_off_reg, pp_div_reg;
4088
4089         if (HAS_PCH_SPLIT(dev)) {
4090                 pp_on_reg = PCH_PP_ON_DELAYS;
4091                 pp_off_reg = PCH_PP_OFF_DELAYS;
4092                 pp_div_reg = PCH_PP_DIVISOR;
4093         } else {
4094                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4095
4096                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4097                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4098                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
4099         }
4100
4101         /*
4102          * And finally store the new values in the power sequencer. The
4103          * backlight delays are set to 1 because we do manual waits on them. For
4104          * T8, even BSpec recommends doing it. For T9, if we don't do this,
4105          * we'll end up waiting for the backlight off delay twice: once when we
4106          * do the manual sleep, and once when we disable the panel and wait for
4107          * the PP_STATUS bit to become zero.
4108          */
4109         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
4110                 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4111         pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
4112                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
4113         /* Compute the divisor for the pp clock, simply match the Bspec
4114          * formula. */
4115         pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
4116         pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
4117                         << PANEL_POWER_CYCLE_DELAY_SHIFT);
4118
4119         /* Haswell doesn't have any port selection bits for the panel
4120          * power sequencer any more. */
4121         if (IS_VALLEYVIEW(dev)) {
4122                 if (dp_to_dig_port(intel_dp)->port == PORT_B)
4123                         port_sel = PANEL_PORT_SELECT_DPB_VLV;
4124                 else
4125                         port_sel = PANEL_PORT_SELECT_DPC_VLV;
4126         } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
4127                 if (dp_to_dig_port(intel_dp)->port == PORT_A)
4128                         port_sel = PANEL_PORT_SELECT_DPA;
4129                 else
4130                         port_sel = PANEL_PORT_SELECT_DPD;
4131         }
4132
4133         pp_on |= port_sel;
4134
4135         I915_WRITE(pp_on_reg, pp_on);
4136         I915_WRITE(pp_off_reg, pp_off);
4137         I915_WRITE(pp_div_reg, pp_div);
4138
4139         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
4140                       I915_READ(pp_on_reg),
4141                       I915_READ(pp_off_reg),
4142                       I915_READ(pp_div_reg));
4143 }
4144
4145 void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4146 {
4147         struct drm_i915_private *dev_priv = dev->dev_private;
4148         struct intel_encoder *encoder;
4149         struct intel_dp *intel_dp = NULL;
4150         struct intel_crtc_config *config = NULL;
4151         struct intel_crtc *intel_crtc = NULL;
4152         struct intel_connector *intel_connector = dev_priv->drrs.connector;
4153         u32 reg, val;
4154         enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4155
4156         if (refresh_rate <= 0) {
4157                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4158                 return;
4159         }
4160
4161         if (intel_connector == NULL) {
4162                 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4163                 return;
4164         }
4165
4166         /*
4167          * FIXME: This needs proper synchronization with psr state. But really
4168          * hard to tell without seeing the user of this function of this code.
4169          * Check locking and ordering once that lands.
4170          */
4171         if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
4172                 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4173                 return;
4174         }
4175
4176         encoder = intel_attached_encoder(&intel_connector->base);
4177         intel_dp = enc_to_intel_dp(&encoder->base);
4178         intel_crtc = encoder->new_crtc;
4179
4180         if (!intel_crtc) {
4181                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4182                 return;
4183         }
4184
4185         config = &intel_crtc->config;
4186
4187         if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4188                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4189                 return;
4190         }
4191
4192         if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
4193                 index = DRRS_LOW_RR;
4194
4195         if (index == intel_dp->drrs_state.refresh_rate_type) {
4196                 DRM_DEBUG_KMS(
4197                         "DRRS requested for previously set RR...ignoring\n");
4198                 return;
4199         }
4200
4201         if (!intel_crtc->active) {
4202                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4203                 return;
4204         }
4205
4206         if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4207                 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4208                 val = I915_READ(reg);
4209                 if (index > DRRS_HIGH_RR) {
4210                         val |= PIPECONF_EDP_RR_MODE_SWITCH;
4211                         intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2);
4212                 } else {
4213                         val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4214                 }
4215                 I915_WRITE(reg, val);
4216         }
4217
4218         /*
4219          * mutex taken to ensure that there is no race between differnt
4220          * drrs calls trying to update refresh rate. This scenario may occur
4221          * in future when idleness detection based DRRS in kernel and
4222          * possible calls from user space to set differnt RR are made.
4223          */
4224
4225         mutex_lock(&intel_dp->drrs_state.mutex);
4226
4227         intel_dp->drrs_state.refresh_rate_type = index;
4228
4229         mutex_unlock(&intel_dp->drrs_state.mutex);
4230
4231         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4232 }
4233
4234 static struct drm_display_mode *
4235 intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4236                         struct intel_connector *intel_connector,
4237                         struct drm_display_mode *fixed_mode)
4238 {
4239         struct drm_connector *connector = &intel_connector->base;
4240         struct intel_dp *intel_dp = &intel_dig_port->dp;
4241         struct drm_device *dev = intel_dig_port->base.base.dev;
4242         struct drm_i915_private *dev_priv = dev->dev_private;
4243         struct drm_display_mode *downclock_mode = NULL;
4244
4245         if (INTEL_INFO(dev)->gen <= 6) {
4246                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4247                 return NULL;
4248         }
4249
4250         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4251                 DRM_INFO("VBT doesn't support DRRS\n");
4252                 return NULL;
4253         }
4254
4255         downclock_mode = intel_find_panel_downclock
4256                                         (dev, fixed_mode, connector);
4257
4258         if (!downclock_mode) {
4259                 DRM_INFO("DRRS not supported\n");
4260                 return NULL;
4261         }
4262
4263         dev_priv->drrs.connector = intel_connector;
4264
4265         mutex_init(&intel_dp->drrs_state.mutex);
4266
4267         intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4268
4269         intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4270         DRM_INFO("seamless DRRS supported for eDP panel.\n");
4271         return downclock_mode;
4272 }
4273
4274 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
4275                                      struct intel_connector *intel_connector,
4276                                      struct edp_power_seq *power_seq)
4277 {
4278         struct drm_connector *connector = &intel_connector->base;
4279         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4280         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4281         struct drm_device *dev = intel_encoder->base.dev;
4282         struct drm_i915_private *dev_priv = dev->dev_private;
4283         struct drm_display_mode *fixed_mode = NULL;
4284         struct drm_display_mode *downclock_mode = NULL;
4285         bool has_dpcd;
4286         struct drm_display_mode *scan;
4287         struct edid *edid;
4288
4289         intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
4290
4291         if (!is_edp(intel_dp))
4292                 return true;
4293
4294         /* The VDD bit needs a power domain reference, so if the bit is already
4295          * enabled when we boot, grab this reference. */
4296         if (edp_have_panel_vdd(intel_dp)) {
4297                 enum intel_display_power_domain power_domain;
4298                 power_domain = intel_display_port_power_domain(intel_encoder);
4299                 intel_display_power_get(dev_priv, power_domain);
4300         }
4301
4302         /* Cache DPCD and EDID for edp. */
4303         intel_edp_panel_vdd_on(intel_dp);
4304         has_dpcd = intel_dp_get_dpcd(intel_dp);
4305         edp_panel_vdd_off(intel_dp, false);
4306
4307         if (has_dpcd) {
4308                 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4309                         dev_priv->no_aux_handshake =
4310                                 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4311                                 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4312         } else {
4313                 /* if this fails, presume the device is a ghost */
4314                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
4315                 return false;
4316         }
4317
4318         /* We now know it's not a ghost, init power sequence regs. */
4319         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
4320
4321         mutex_lock(&dev->mode_config.mutex);
4322         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
4323         if (edid) {
4324                 if (drm_add_edid_modes(connector, edid)) {
4325                         drm_mode_connector_update_edid_property(connector,
4326                                                                 edid);
4327                         drm_edid_to_eld(connector, edid);
4328                 } else {
4329                         kfree(edid);
4330                         edid = ERR_PTR(-EINVAL);
4331                 }
4332         } else {
4333                 edid = ERR_PTR(-ENOENT);
4334         }
4335         intel_connector->edid = edid;
4336
4337         /* prefer fixed mode from EDID if available */
4338         list_for_each_entry(scan, &connector->probed_modes, head) {
4339                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
4340                         fixed_mode = drm_mode_duplicate(dev, scan);
4341                         downclock_mode = intel_dp_drrs_init(
4342                                                 intel_dig_port,
4343                                                 intel_connector, fixed_mode);
4344                         break;
4345                 }
4346         }
4347
4348         /* fallback to VBT if available for eDP */
4349         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
4350                 fixed_mode = drm_mode_duplicate(dev,
4351                                         dev_priv->vbt.lfp_lvds_vbt_mode);
4352                 if (fixed_mode)
4353                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
4354         }
4355         mutex_unlock(&dev->mode_config.mutex);
4356
4357         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
4358         intel_panel_setup_backlight(connector);
4359
4360         return true;
4361 }
4362
4363 bool
4364 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
4365                         struct intel_connector *intel_connector)
4366 {
4367         struct drm_connector *connector = &intel_connector->base;
4368         struct intel_dp *intel_dp = &intel_dig_port->dp;
4369         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4370         struct drm_device *dev = intel_encoder->base.dev;
4371         struct drm_i915_private *dev_priv = dev->dev_private;
4372         enum port port = intel_dig_port->port;
4373         struct edp_power_seq power_seq = { 0 };
4374         int type;
4375
4376         /* intel_dp vfuncs */
4377         if (IS_VALLEYVIEW(dev))
4378                 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
4379         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4380                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
4381         else if (HAS_PCH_SPLIT(dev))
4382                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
4383         else
4384                 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
4385
4386         intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
4387
4388         /* Preserve the current hw state. */
4389         intel_dp->DP = I915_READ(intel_dp->output_reg);
4390         intel_dp->attached_connector = intel_connector;
4391
4392         if (intel_dp_is_edp(dev, port))
4393                 type = DRM_MODE_CONNECTOR_eDP;
4394         else
4395                 type = DRM_MODE_CONNECTOR_DisplayPort;
4396
4397         /*
4398          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
4399          * for DP the encoder type can be set by the caller to
4400          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
4401          */
4402         if (type == DRM_MODE_CONNECTOR_eDP)
4403                 intel_encoder->type = INTEL_OUTPUT_EDP;
4404
4405         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
4406                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
4407                         port_name(port));
4408
4409         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
4410         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
4411
4412         connector->interlace_allowed = true;
4413         connector->doublescan_allowed = 0;
4414
4415         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4416                           edp_panel_vdd_work);
4417
4418         intel_connector_attach_encoder(intel_connector, intel_encoder);
4419         drm_sysfs_connector_add(connector);
4420
4421         if (HAS_DDI(dev))
4422                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
4423         else
4424                 intel_connector->get_hw_state = intel_connector_get_hw_state;
4425         intel_connector->unregister = intel_dp_connector_unregister;
4426
4427         /* Set up the hotplug pin. */
4428         switch (port) {
4429         case PORT_A:
4430                 intel_encoder->hpd_pin = HPD_PORT_A;
4431                 break;
4432         case PORT_B:
4433                 intel_encoder->hpd_pin = HPD_PORT_B;
4434                 break;
4435         case PORT_C:
4436                 intel_encoder->hpd_pin = HPD_PORT_C;
4437                 break;
4438         case PORT_D:
4439                 intel_encoder->hpd_pin = HPD_PORT_D;
4440                 break;
4441         default:
4442                 BUG();
4443         }
4444
4445         if (is_edp(intel_dp)) {
4446                 intel_dp_init_panel_power_timestamps(intel_dp);
4447                 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
4448         }
4449
4450         intel_dp_aux_init(intel_dp, intel_connector);
4451
4452         if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
4453                 drm_dp_aux_unregister(&intel_dp->aux);
4454                 if (is_edp(intel_dp)) {
4455                         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4456                         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4457                         edp_panel_vdd_off_sync(intel_dp);
4458                         drm_modeset_unlock(&dev->mode_config.connection_mutex);
4459                 }
4460                 drm_sysfs_connector_remove(connector);
4461                 drm_connector_cleanup(connector);
4462                 return false;
4463         }
4464
4465         intel_dp_add_properties(intel_dp, connector);
4466
4467         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
4468          * 0xd.  Failure to do so will result in spurious interrupts being
4469          * generated on the port when a cable is not attached.
4470          */
4471         if (IS_G4X(dev) && !IS_GM45(dev)) {
4472                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
4473                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
4474         }
4475
4476         return true;
4477 }
4478
4479 void
4480 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
4481 {
4482         struct drm_i915_private *dev_priv = dev->dev_private;
4483         struct intel_digital_port *intel_dig_port;
4484         struct intel_encoder *intel_encoder;
4485         struct drm_encoder *encoder;
4486         struct intel_connector *intel_connector;
4487
4488         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
4489         if (!intel_dig_port)
4490                 return;
4491
4492         intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
4493         if (!intel_connector) {
4494                 kfree(intel_dig_port);
4495                 return;
4496         }
4497
4498         intel_encoder = &intel_dig_port->base;
4499         encoder = &intel_encoder->base;
4500
4501         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
4502                          DRM_MODE_ENCODER_TMDS);
4503
4504         intel_encoder->compute_config = intel_dp_compute_config;
4505         intel_encoder->disable = intel_disable_dp;
4506         intel_encoder->get_hw_state = intel_dp_get_hw_state;
4507         intel_encoder->get_config = intel_dp_get_config;
4508         if (IS_CHERRYVIEW(dev)) {
4509                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
4510                 intel_encoder->pre_enable = chv_pre_enable_dp;
4511                 intel_encoder->enable = vlv_enable_dp;
4512                 intel_encoder->post_disable = chv_post_disable_dp;
4513         } else if (IS_VALLEYVIEW(dev)) {
4514                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
4515                 intel_encoder->pre_enable = vlv_pre_enable_dp;
4516                 intel_encoder->enable = vlv_enable_dp;
4517                 intel_encoder->post_disable = vlv_post_disable_dp;
4518         } else {
4519                 intel_encoder->pre_enable = g4x_pre_enable_dp;
4520                 intel_encoder->enable = g4x_enable_dp;
4521                 intel_encoder->post_disable = g4x_post_disable_dp;
4522         }
4523
4524         intel_dig_port->port = port;
4525         intel_dig_port->dp.output_reg = output_reg;
4526
4527         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4528         if (IS_CHERRYVIEW(dev)) {
4529                 if (port == PORT_D)
4530                         intel_encoder->crtc_mask = 1 << 2;
4531                 else
4532                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
4533         } else {
4534                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
4535         }
4536         intel_encoder->cloneable = 0;
4537         intel_encoder->hot_plug = intel_dp_hot_plug;
4538
4539         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
4540         dev_priv->hpd_irq_port[port] = intel_dig_port;
4541
4542         if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
4543                 drm_encoder_cleanup(encoder);
4544                 kfree(intel_dig_port);
4545                 kfree(intel_connector);
4546         }
4547 }