drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <linux/notifier.h>
  32 #include <linux/reboot.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_crtc_helper.h>
  36 #include <drm/drm_edid.h>
  37 #include "intel_drv.h"
  38 #include <drm/i915_drm.h>
  39 #include "i915_drv.h"
  40
  41 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  42
  43 struct dp_link_dpll {
  44         int link_bw;
  45         struct dpll dpll;
  46 };
  47
  48 static const struct dp_link_dpll gen4_dpll[] = {
  49         { DP_LINK_BW_1_62,
  50                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  51         { DP_LINK_BW_2_7,
  52                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  53 };
  54
  55 static const struct dp_link_dpll pch_dpll[] = {
  56         { DP_LINK_BW_1_62,
  57                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  58         { DP_LINK_BW_2_7,
  59                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  60 };
  61
  62 static const struct dp_link_dpll vlv_dpll[] = {
  63         { DP_LINK_BW_1_62,
  64                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  65         { DP_LINK_BW_2_7,
  66                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  67 };
  68
  69 /*
  70  * CHV supports eDP 1.4 that have  more link rates.
  71  * Below only provides the fixed rate but exclude variable rate.
  72  */
  73 static const struct dp_link_dpll chv_dpll[] = {
  74         /*
  75          * CHV requires to program fractional division for m2.
  76          * m2 is stored in fixed point format using formula below
  77          * (m2_int << 22) | m2_fraction
  78          */
  79         { DP_LINK_BW_1_62,      /* m2_int = 32, m2_fraction = 1677722 */
  80                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
  81         { DP_LINK_BW_2_7,       /* m2_int = 27, m2_fraction = 0 */
  82                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
  83         { DP_LINK_BW_5_4,       /* m2_int = 27, m2_fraction = 0 */
  84                 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
  85 };
  86
  87 /**
  88  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  89  * @intel_dp: DP struct
  90  *
  91  * If a CPU or PCH DP output is attached to an eDP panel, this function
  92  * will return true, and false otherwise.
  93  */
  94 static bool is_edp(struct intel_dp *intel_dp)
  95 {
  96         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  97
  98         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
  99 }
 100
 101 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
 102 {
 103         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 104
 105         return intel_dig_port->base.base.dev;
 106 }
 107
 108 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 109 {
 110         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 111 }
 112
 113 static void intel_dp_link_down(struct intel_dp *intel_dp);
 114 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 115 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 116 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
 117 static void vlv_steal_power_sequencer(struct drm_device *dev,
 118                                       enum pipe pipe);
 119
 120 int
 121 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 122 {
 123         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 124         struct drm_device *dev = intel_dp->attached_connector->base.dev;
 125
 126         switch (max_link_bw) {
 127         case DP_LINK_BW_1_62:
 128         case DP_LINK_BW_2_7:
 129                 break;
 130         case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
 131                 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
 132                      INTEL_INFO(dev)->gen >= 8) &&
 133                     intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
 134                         max_link_bw = DP_LINK_BW_5_4;
 135                 else
 136                         max_link_bw = DP_LINK_BW_2_7;
 137                 break;
 138         default:
 139                 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
 140                      max_link_bw);
 141                 max_link_bw = DP_LINK_BW_1_62;
 142                 break;
 143         }
 144         return max_link_bw;
 145 }
 146
 147 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 148 {
 149         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 150         struct drm_device *dev = intel_dig_port->base.base.dev;
 151         u8 source_max, sink_max;
 152
 153         source_max = 4;
 154         if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
 155             (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
 156                 source_max = 2;
 157
 158         sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 159
 160         return min(source_max, sink_max);
 161 }
 162
 163 /*
 164  * The units on the numbers in the next two are... bizarre.  Examples will
 165  * make it clearer; this one parallels an example in the eDP spec.
 166  *
 167  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 168  *
 169  *     270000 * 1 * 8 / 10 == 216000
 170  *
 171  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 172  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 173  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 174  * 119000.  At 18bpp that's 2142000 kilobits per second.
 175  *
 176  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 177  * get the result in decakilobits instead of kilobits.
 178  */
 179
 180 static int
 181 intel_dp_link_required(int pixel_clock, int bpp)
 182 {
 183         return (pixel_clock * bpp + 9) / 10;
 184 }
 185
 186 static int
 187 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 188 {
 189         return (max_link_clock * max_lanes * 8) / 10;
 190 }
 191
 192 static enum drm_mode_status
 193 intel_dp_mode_valid(struct drm_connector *connector,
 194                     struct drm_display_mode *mode)
 195 {
 196         struct intel_dp *intel_dp = intel_attached_dp(connector);
 197         struct intel_connector *intel_connector = to_intel_connector(connector);
 198         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 199         int target_clock = mode->clock;
 200         int max_rate, mode_rate, max_lanes, max_link_clock;
 201
 202         if (is_edp(intel_dp) && fixed_mode) {
 203                 if (mode->hdisplay > fixed_mode->hdisplay)
 204                         return MODE_PANEL;
 205
 206                 if (mode->vdisplay > fixed_mode->vdisplay)
 207                         return MODE_PANEL;
 208
 209                 target_clock = fixed_mode->clock;
 210         }
 211
 212         max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
 213         max_lanes = intel_dp_max_lane_count(intel_dp);
 214
 215         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 216         mode_rate = intel_dp_link_required(target_clock, 18);
 217
 218         if (mode_rate > max_rate)
 219                 return MODE_CLOCK_HIGH;
 220
 221         if (mode->clock < 10000)
 222                 return MODE_CLOCK_LOW;
 223
 224         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 225                 return MODE_H_ILLEGAL;
 226
 227         return MODE_OK;
 228 }
 229
 230 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
 231 {
 232         int     i;
 233         uint32_t v = 0;
 234
 235         if (src_bytes > 4)
 236                 src_bytes = 4;
 237         for (i = 0; i < src_bytes; i++)
 238                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 239         return v;
 240 }
 241
 242 void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 243 {
 244         int i;
 245         if (dst_bytes > 4)
 246                 dst_bytes = 4;
 247         for (i = 0; i < dst_bytes; i++)
 248                 dst[i] = src >> ((3-i) * 8);
 249 }
 250
 251 /* hrawclock is 1/4 the FSB frequency */
 252 static int
 253 intel_hrawclk(struct drm_device *dev)
 254 {
 255         struct drm_i915_private *dev_priv = dev->dev_private;
 256         uint32_t clkcfg;
 257
 258         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 259         if (IS_VALLEYVIEW(dev))
 260                 return 200;
 261
 262         clkcfg = I915_READ(CLKCFG);
 263         switch (clkcfg & CLKCFG_FSB_MASK) {
 264         case CLKCFG_FSB_400:
 265                 return 100;
 266         case CLKCFG_FSB_533:
 267                 return 133;
 268         case CLKCFG_FSB_667:
 269                 return 166;
 270         case CLKCFG_FSB_800:
 271                 return 200;
 272         case CLKCFG_FSB_1067:
 273                 return 266;
 274         case CLKCFG_FSB_1333:
 275                 return 333;
 276         /* these two are just a guess; one of them might be right */
 277         case CLKCFG_FSB_1600:
 278         case CLKCFG_FSB_1600_ALT:
 279                 return 400;
 280         default:
 281                 return 133;
 282         }
 283 }
 284
 285 static void
 286 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 287                                     struct intel_dp *intel_dp);
 288 static void
 289 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 290                                               struct intel_dp *intel_dp);
 291
 292 static void pps_lock(struct intel_dp *intel_dp)
 293 {
 294         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 295         struct intel_encoder *encoder = &intel_dig_port->base;
 296         struct drm_device *dev = encoder->base.dev;
 297         struct drm_i915_private *dev_priv = dev->dev_private;
 298         enum intel_display_power_domain power_domain;
 299
 300         /*
 301          * See vlv_power_sequencer_reset() why we need
 302          * a power domain reference here.
 303          */
 304         power_domain = intel_display_port_power_domain(encoder);
 305         intel_display_power_get(dev_priv, power_domain);
 306
 307         mutex_lock(&dev_priv->pps_mutex);
 308 }
 309
 310 static void pps_unlock(struct intel_dp *intel_dp)
 311 {
 312         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 313         struct intel_encoder *encoder = &intel_dig_port->base;
 314         struct drm_device *dev = encoder->base.dev;
 315         struct drm_i915_private *dev_priv = dev->dev_private;
 316         enum intel_display_power_domain power_domain;
 317
 318         mutex_unlock(&dev_priv->pps_mutex);
 319
 320         power_domain = intel_display_port_power_domain(encoder);
 321         intel_display_power_put(dev_priv, power_domain);
 322 }
 323
 324 static void
 325 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 326 {
 327         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 328         struct drm_device *dev = intel_dig_port->base.base.dev;
 329         struct drm_i915_private *dev_priv = dev->dev_private;
 330         enum pipe pipe = intel_dp->pps_pipe;
 331         bool pll_enabled;
 332         uint32_t DP;
 333
 334         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
 335                  "skipping pipe %c power seqeuncer kick due to port %c being active\n",
 336                  pipe_name(pipe), port_name(intel_dig_port->port)))
 337                 return;
 338
 339         DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
 340                       pipe_name(pipe), port_name(intel_dig_port->port));
 341
 342         /* Preserve the BIOS-computed detected bit. This is
 343          * supposed to be read-only.
 344          */
 345         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 346         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 347         DP |= DP_PORT_WIDTH(1);
 348         DP |= DP_LINK_TRAIN_PAT_1;
 349
 350         if (IS_CHERRYVIEW(dev))
 351                 DP |= DP_PIPE_SELECT_CHV(pipe);
 352         else if (pipe == PIPE_B)
 353                 DP |= DP_PIPEB_SELECT;
 354
 355         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
 356
 357         /*
 358          * The DPLL for the pipe must be enabled for this to work.
 359          * So enable temporarily it if it's not already enabled.
 360          */
 361         if (!pll_enabled)
 362                 vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
 363                                  &chv_dpll[0].dpll : &vlv_dpll[0].dpll);
 364
 365         /*
 366          * Similar magic as in intel_dp_enable_port().
 367          * We _must_ do this port enable + disable trick
 368          * to make this power seqeuencer lock onto the port.
 369          * Otherwise even VDD force bit won't work.
 370          */
 371         I915_WRITE(intel_dp->output_reg, DP);
 372         POSTING_READ(intel_dp->output_reg);
 373
 374         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
 375         POSTING_READ(intel_dp->output_reg);
 376
 377         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
 378         POSTING_READ(intel_dp->output_reg);
 379
 380         if (!pll_enabled)
 381                 vlv_force_pll_off(dev, pipe);
 382 }
 383
 384 static enum pipe
 385 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 386 {
 387         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 388         struct drm_device *dev = intel_dig_port->base.base.dev;
 389         struct drm_i915_private *dev_priv = dev->dev_private;
 390         struct intel_encoder *encoder;
 391         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 392         enum pipe pipe;
 393
 394         lockdep_assert_held(&dev_priv->pps_mutex);
 395
 396         /* We should never land here with regular DP ports */
 397         WARN_ON(!is_edp(intel_dp));
 398
 399         if (intel_dp->pps_pipe != INVALID_PIPE)
 400                 return intel_dp->pps_pipe;
 401
 402         /*
 403          * We don't have power sequencer currently.
 404          * Pick one that's not used by other ports.
 405          */
 406         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
 407                             base.head) {
 408                 struct intel_dp *tmp;
 409
 410                 if (encoder->type != INTEL_OUTPUT_EDP)
 411                         continue;
 412
 413                 tmp = enc_to_intel_dp(&encoder->base);
 414
 415                 if (tmp->pps_pipe != INVALID_PIPE)
 416                         pipes &= ~(1 << tmp->pps_pipe);
 417         }
 418
 419         /*
 420          * Didn't find one. This should not happen since there
 421          * are two power sequencers and up to two eDP ports.
 422          */
 423         if (WARN_ON(pipes == 0))
 424                 pipe = PIPE_A;
 425         else
 426                 pipe = ffs(pipes) - 1;
 427
 428         vlv_steal_power_sequencer(dev, pipe);
 429         intel_dp->pps_pipe = pipe;
 430
 431         DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
 432                       pipe_name(intel_dp->pps_pipe),
 433                       port_name(intel_dig_port->port));
 434
 435         /* init power sequencer on this pipe and port */
 436         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 437         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
 438
 439         /*
 440          * Even vdd force doesn't work until we've made
 441          * the power sequencer lock in on the port.
 442          */
 443         vlv_power_sequencer_kick(intel_dp);
 444
 445         return intel_dp->pps_pipe;
 446 }
 447
 448 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 449                                enum pipe pipe);
 450
 451 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 452                                enum pipe pipe)
 453 {
 454         return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
 455 }
 456
 457 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 458                                 enum pipe pipe)
 459 {
 460         return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 461 }
 462
 463 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 464                          enum pipe pipe)
 465 {
 466         return true;
 467 }
 468
 469 static enum pipe
 470 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 471                      enum port port,
 472                      vlv_pipe_check pipe_check)
 473 {
 474         enum pipe pipe;
 475
 476         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 477                 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
 478                         PANEL_PORT_SELECT_MASK;
 479
 480                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 481                         continue;
 482
 483                 if (!pipe_check(dev_priv, pipe))
 484                         continue;
 485
 486                 return pipe;
 487         }
 488
 489         return INVALID_PIPE;
 490 }
 491
 492 static void
 493 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 494 {
 495         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 496         struct drm_device *dev = intel_dig_port->base.base.dev;
 497         struct drm_i915_private *dev_priv = dev->dev_private;
 498         enum port port = intel_dig_port->port;
 499
 500         lockdep_assert_held(&dev_priv->pps_mutex);
 501
 502         /* try to find a pipe with this port selected */
 503         /* first pick one where the panel is on */
 504         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 505                                                   vlv_pipe_has_pp_on);
 506         /* didn't find one? pick one where vdd is on */
 507         if (intel_dp->pps_pipe == INVALID_PIPE)
 508                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 509                                                           vlv_pipe_has_vdd_on);
 510         /* didn't find one? pick one with just the correct port */
 511         if (intel_dp->pps_pipe == INVALID_PIPE)
 512                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 513                                                           vlv_pipe_any);
 514
 515         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 516         if (intel_dp->pps_pipe == INVALID_PIPE) {
 517                 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
 518                               port_name(port));
 519                 return;
 520         }
 521
 522         DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
 523                       port_name(port), pipe_name(intel_dp->pps_pipe));
 524
 525         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 526         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
 527 }
 528
 529 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
 530 {
 531         struct drm_device *dev = dev_priv->dev;
 532         struct intel_encoder *encoder;
 533
 534         if (WARN_ON(!IS_VALLEYVIEW(dev)))
 535                 return;
 536
 537         /*
 538          * We can't grab pps_mutex here due to deadlock with power_domain
 539          * mutex when power_domain functions are called while holding pps_mutex.
 540          * That also means that in order to use pps_pipe the code needs to
 541          * hold both a power domain reference and pps_mutex, and the power domain
 542          * reference get/put must be done while _not_ holding pps_mutex.
 543          * pps_{lock,unlock}() do these steps in the correct order, so one
 544          * should use them always.
 545          */
 546
 547         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
 548                 struct intel_dp *intel_dp;
 549
 550                 if (encoder->type != INTEL_OUTPUT_EDP)
 551                         continue;
 552
 553                 intel_dp = enc_to_intel_dp(&encoder->base);
 554                 intel_dp->pps_pipe = INVALID_PIPE;
 555         }
 556 }
 557
 558 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
 559 {
 560         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 561
 562         if (HAS_PCH_SPLIT(dev))
 563                 return PCH_PP_CONTROL;
 564         else
 565                 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
 566 }
 567
 568 static u32 _pp_stat_reg(struct intel_dp *intel_dp)
 569 {
 570         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 571
 572         if (HAS_PCH_SPLIT(dev))
 573                 return PCH_PP_STATUS;
 574         else
 575                 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
 576 }
 577
 578 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
 579    This function only applicable when panel PM state is not to be tracked */
 580 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 581                               void *unused)
 582 {
 583         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
 584                                                  edp_notifier);
 585         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 586         struct drm_i915_private *dev_priv = dev->dev_private;
 587         u32 pp_div;
 588         u32 pp_ctrl_reg, pp_div_reg;
 589
 590         if (!is_edp(intel_dp) || code != SYS_RESTART)
 591                 return 0;
 592
 593         pps_lock(intel_dp);
 594
 595         if (IS_VALLEYVIEW(dev)) {
 596                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 597
 598                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
 599                 pp_div_reg  = VLV_PIPE_PP_DIVISOR(pipe);
 600                 pp_div = I915_READ(pp_div_reg);
 601                 pp_div &= PP_REFERENCE_DIVIDER_MASK;
 602
 603                 /* 0x1F write to PP_DIV_REG sets max cycle delay */
 604                 I915_WRITE(pp_div_reg, pp_div | 0x1F);
 605                 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
 606                 msleep(intel_dp->panel_power_cycle_delay);
 607         }
 608
 609         pps_unlock(intel_dp);
 610
 611         return 0;
 612 }
 613
 614 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 615 {
 616         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 617         struct drm_i915_private *dev_priv = dev->dev_private;
 618
 619         lockdep_assert_held(&dev_priv->pps_mutex);
 620
 621         if (IS_VALLEYVIEW(dev) &&
 622             intel_dp->pps_pipe == INVALID_PIPE)
 623                 return false;
 624
 625         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 626 }
 627
 628 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 629 {
 630         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 631         struct drm_i915_private *dev_priv = dev->dev_private;
 632
 633         lockdep_assert_held(&dev_priv->pps_mutex);
 634
 635         if (IS_VALLEYVIEW(dev) &&
 636             intel_dp->pps_pipe == INVALID_PIPE)
 637                 return false;
 638
 639         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
 640 }
 641
 642 static void
 643 intel_dp_check_edp(struct intel_dp *intel_dp)
 644 {
 645         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 646         struct drm_i915_private *dev_priv = dev->dev_private;
 647
 648         if (!is_edp(intel_dp))
 649                 return;
 650
 651         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 652                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 653                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 654                               I915_READ(_pp_stat_reg(intel_dp)),
 655                               I915_READ(_pp_ctrl_reg(intel_dp)));
 656         }
 657 }
 658
 659 static uint32_t
 660 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 661 {
 662         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 663         struct drm_device *dev = intel_dig_port->base.base.dev;
 664         struct drm_i915_private *dev_priv = dev->dev_private;
 665         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 666         uint32_t status;
 667         bool done;
 668
 669 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 670         if (has_aux_irq)
 671                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 672                                           msecs_to_jiffies_timeout(10));
 673         else
 674                 done = wait_for_atomic(C, 10) == 0;
 675         if (!done)
 676                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 677                           has_aux_irq);
 678 #undef C
 679
 680         return status;
 681 }
 682
 683 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 684 {
 685         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 686         struct drm_device *dev = intel_dig_port->base.base.dev;
 687
 688         /*
 689          * The clock divider is based off the hrawclk, and would like to run at
 690          * 2MHz.  So, take the hrawclk value and divide by 2 and use that
 691          */
 692         return index ? 0 : intel_hrawclk(dev) / 2;
 693 }
 694
 695 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 696 {
 697         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 698         struct drm_device *dev = intel_dig_port->base.base.dev;
 699
 700         if (index)
 701                 return 0;
 702
 703         if (intel_dig_port->port == PORT_A) {
 704                 if (IS_GEN6(dev) || IS_GEN7(dev))
 705                         return 200; /* SNB & IVB eDP input clock at 400Mhz */
 706                 else
 707                         return 225; /* eDP input clock at 450Mhz */
 708         } else {
 709                 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 710         }
 711 }
 712
 713 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 714 {
 715         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 716         struct drm_device *dev = intel_dig_port->base.base.dev;
 717         struct drm_i915_private *dev_priv = dev->dev_private;
 718
 719         if (intel_dig_port->port == PORT_A) {
 720                 if (index)
 721                         return 0;
 722                 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
 723         } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 724                 /* Workaround for non-ULT HSW */
 725                 switch (index) {
 726                 case 0: return 63;
 727                 case 1: return 72;
 728                 default: return 0;
 729                 }
 730         } else  {
 731                 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 732         }
 733 }
 734
 735 static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 736 {
 737         return index ? 0 : 100;
 738 }
 739
 740 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 741 {
 742         /*
 743          * SKL doesn't need us to program the AUX clock divider (Hardware will
 744          * derive the clock from CDCLK automatically). We still implement the
 745          * get_aux_clock_divider vfunc to plug-in into the existing code.
 746          */
 747         return index ? 0 : 1;
 748 }
 749
 750 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
 751                                       bool has_aux_irq,
 752                                       int send_bytes,
 753                                       uint32_t aux_clock_divider)
 754 {
 755         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 756         struct drm_device *dev = intel_dig_port->base.base.dev;
 757         uint32_t precharge, timeout;
 758
 759         if (IS_GEN6(dev))
 760                 precharge = 3;
 761         else
 762                 precharge = 5;
 763
 764         if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
 765                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
 766         else
 767                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
 768
 769         return DP_AUX_CH_CTL_SEND_BUSY |
 770                DP_AUX_CH_CTL_DONE |
 771                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 772                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 773                timeout |
 774                DP_AUX_CH_CTL_RECEIVE_ERROR |
 775                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 776                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 777                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
 778 }
 779
 780 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
 781                                       bool has_aux_irq,
 782                                       int send_bytes,
 783                                       uint32_t unused)
 784 {
 785         return DP_AUX_CH_CTL_SEND_BUSY |
 786                DP_AUX_CH_CTL_DONE |
 787                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 788                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 789                DP_AUX_CH_CTL_TIME_OUT_1600us |
 790                DP_AUX_CH_CTL_RECEIVE_ERROR |
 791                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 792                DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
 793 }
 794
 795 static int
 796 intel_dp_aux_ch(struct intel_dp *intel_dp,
 797                 const uint8_t *send, int send_bytes,
 798                 uint8_t *recv, int recv_size)
 799 {
 800         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 801         struct drm_device *dev = intel_dig_port->base.base.dev;
 802         struct drm_i915_private *dev_priv = dev->dev_private;
 803         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 804         uint32_t ch_data = ch_ctl + 4;
 805         uint32_t aux_clock_divider;
 806         int i, ret, recv_bytes;
 807         uint32_t status;
 808         int try, clock = 0;
 809         bool has_aux_irq = HAS_AUX_IRQ(dev);
 810         bool vdd;
 811
 812         pps_lock(intel_dp);
 813
 814         /*
 815          * We will be called with VDD already enabled for dpcd/edid/oui reads.
 816          * In such cases we want to leave VDD enabled and it's up to upper layers
 817          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
 818          * ourselves.
 819          */
 820         vdd = edp_panel_vdd_on(intel_dp);
 821
 822         /* dp aux is extremely sensitive to irq latency, hence request the
 823          * lowest possible wakeup latency and so prevent the cpu from going into
 824          * deep sleep states.
 825          */
 826         pm_qos_update_request(&dev_priv->pm_qos, 0);
 827
 828         intel_dp_check_edp(intel_dp);
 829
 830         intel_aux_display_runtime_get(dev_priv);
 831
 832         /* Try to wait for any previous AUX channel activity */
 833         for (try = 0; try < 3; try++) {
 834                 status = I915_READ_NOTRACE(ch_ctl);
 835                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 836                         break;
 837                 msleep(1);
 838         }
 839
 840         if (try == 3) {
 841                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 842                      I915_READ(ch_ctl));
 843                 ret = -EBUSY;
 844                 goto out;
 845         }
 846
 847         /* Only 5 data registers! */
 848         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
 849                 ret = -E2BIG;
 850                 goto out;
 851         }
 852
 853         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
 854                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
 855                                                           has_aux_irq,
 856                                                           send_bytes,
 857                                                           aux_clock_divider);
 858
 859                 /* Must try at least 3 times according to DP spec */
 860                 for (try = 0; try < 5; try++) {
 861                         /* Load the send data into the aux channel data registers */
 862                         for (i = 0; i < send_bytes; i += 4)
 863                                 I915_WRITE(ch_data + i,
 864                                            intel_dp_pack_aux(send + i,
 865                                                              send_bytes - i));
 866
 867                         /* Send the command and wait for it to complete */
 868                         I915_WRITE(ch_ctl, send_ctl);
 869
 870                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
 871
 872                         /* Clear done status and any errors */
 873                         I915_WRITE(ch_ctl,
 874                                    status |
 875                                    DP_AUX_CH_CTL_DONE |
 876                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
 877                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
 878
 879                         if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
 880                                       DP_AUX_CH_CTL_RECEIVE_ERROR))
 881                                 continue;
 882                         if (status & DP_AUX_CH_CTL_DONE)
 883                                 break;
 884                 }
 885                 if (status & DP_AUX_CH_CTL_DONE)
 886                         break;
 887         }
 888
 889         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 890                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 891                 ret = -EBUSY;
 892                 goto out;
 893         }
 894
 895         /* Check for timeout or receive error.
 896          * Timeouts occur when the sink is not connected
 897          */
 898         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 899                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 900                 ret = -EIO;
 901                 goto out;
 902         }
 903
 904         /* Timeouts occur when the device isn't connected, so they're
 905          * "normal" -- don't fill the kernel log with these */
 906         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 907                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 908                 ret = -ETIMEDOUT;
 909                 goto out;
 910         }
 911
 912         /* Unload any bytes sent back from the other side */
 913         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 914                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 915         if (recv_bytes > recv_size)
 916                 recv_bytes = recv_size;
 917
 918         for (i = 0; i < recv_bytes; i += 4)
 919                 intel_dp_unpack_aux(I915_READ(ch_data + i),
 920                                     recv + i, recv_bytes - i);
 921
 922         ret = recv_bytes;
 923 out:
 924         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 925         intel_aux_display_runtime_put(dev_priv);
 926
 927         if (vdd)
 928                 edp_panel_vdd_off(intel_dp, false);
 929
 930         pps_unlock(intel_dp);
 931
 932         return ret;
 933 }
 934
 935 #define BARE_ADDRESS_SIZE       3
 936 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
 937 static ssize_t
 938 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
 939 {
 940         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
 941         uint8_t txbuf[20], rxbuf[20];
 942         size_t txsize, rxsize;
 943         int ret;
 944
 945         txbuf[0] = msg->request << 4;
 946         txbuf[1] = msg->address >> 8;
 947         txbuf[2] = msg->address & 0xff;
 948         txbuf[3] = msg->size - 1;
 949
 950         switch (msg->request & ~DP_AUX_I2C_MOT) {
 951         case DP_AUX_NATIVE_WRITE:
 952         case DP_AUX_I2C_WRITE:
 953                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
 954                 rxsize = 1;
 955
 956                 if (WARN_ON(txsize > 20))
 957                         return -E2BIG;
 958
 959                 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
 960
 961                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
 962                 if (ret > 0) {
 963                         msg->reply = rxbuf[0] >> 4;
 964
 965                         /* Return payload size. */
 966                         ret = msg->size;
 967                 }
 968                 break;
 969
 970         case DP_AUX_NATIVE_READ:
 971         case DP_AUX_I2C_READ:
 972                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
 973                 rxsize = msg->size + 1;
 974
 975                 if (WARN_ON(rxsize > 20))
 976                         return -E2BIG;
 977
 978                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
 979                 if (ret > 0) {
 980                         msg->reply = rxbuf[0] >> 4;
 981                         /*
 982                          * Assume happy day, and copy the data. The caller is
 983                          * expected to check msg->reply before touching it.
 984                          *
 985                          * Return payload size.
 986                          */
 987                         ret--;
 988                         memcpy(msg->buffer, rxbuf + 1, ret);
 989                 }
 990                 break;
 991
 992         default:
 993                 ret = -EINVAL;
 994                 break;
 995         }
 996
 997         return ret;
 998 }
 999
1000 static void
1001 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
1002 {
1003         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1004         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1005         enum port port = intel_dig_port->port;
1006         const char *name = NULL;
1007         int ret;
1008
1009         switch (port) {
1010         case PORT_A:
1011                 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
1012                 name = "DPDDC-A";
1013                 break;
1014         case PORT_B:
1015                 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
1016                 name = "DPDDC-B";
1017                 break;
1018         case PORT_C:
1019                 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
1020                 name = "DPDDC-C";
1021                 break;
1022         case PORT_D:
1023                 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
1024                 name = "DPDDC-D";
1025                 break;
1026         default:
1027                 BUG();
1028         }
1029
1030         /*
1031          * The AUX_CTL register is usually DP_CTL + 0x10.
1032          *
1033          * On Haswell and Broadwell though:
1034          *   - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
1035          *   - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
1036          *
1037          * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
1038          */
1039         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1040                 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
1041
1042         intel_dp->aux.name = name;
1043         intel_dp->aux.dev = dev->dev;
1044         intel_dp->aux.transfer = intel_dp_aux_transfer;
1045
1046         DRM_DEBUG_KMS("registering %s bus for %s\n", name,
1047                       connector->base.kdev->kobj.name);
1048
1049         ret = drm_dp_aux_register(&intel_dp->aux);
1050         if (ret < 0) {
1051                 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
1052                           name, ret);
1053                 return;
1054         }
1055
1056         ret = sysfs_create_link(&connector->base.kdev->kobj,
1057                                 &intel_dp->aux.ddc.dev.kobj,
1058                                 intel_dp->aux.ddc.dev.kobj.name);
1059         if (ret < 0) {
1060                 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
1061                 drm_dp_aux_unregister(&intel_dp->aux);
1062         }
1063 }
1064
1065 static void
1066 intel_dp_connector_unregister(struct intel_connector *intel_connector)
1067 {
1068         struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
1069
1070         if (!intel_connector->mst_port)
1071                 sysfs_remove_link(&intel_connector->base.kdev->kobj,
1072                                   intel_dp->aux.ddc.dev.kobj.name);
1073         intel_connector_unregister(intel_connector);
1074 }
1075
1076 static void
1077 skl_edp_set_pll_config(struct intel_crtc_config *pipe_config, int link_bw)
1078 {
1079         u32 ctrl1;
1080
1081         pipe_config->ddi_pll_sel = SKL_DPLL0;
1082         pipe_config->dpll_hw_state.cfgcr1 = 0;
1083         pipe_config->dpll_hw_state.cfgcr2 = 0;
1084
1085         ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
1086         switch (link_bw) {
1087         case DP_LINK_BW_1_62:
1088                 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_810,
1089                                               SKL_DPLL0);
1090                 break;
1091         case DP_LINK_BW_2_7:
1092                 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1350,
1093                                               SKL_DPLL0);
1094                 break;
1095         case DP_LINK_BW_5_4:
1096                 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2700,
1097                                               SKL_DPLL0);
1098                 break;
1099         }
1100         pipe_config->dpll_hw_state.ctrl1 = ctrl1;
1101 }
1102
1103 static void
1104 hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
1105 {
1106         switch (link_bw) {
1107         case DP_LINK_BW_1_62:
1108                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
1109                 break;
1110         case DP_LINK_BW_2_7:
1111                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
1112                 break;
1113         case DP_LINK_BW_5_4:
1114                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
1115                 break;
1116         }
1117 }
1118
1119 static void
1120 intel_dp_set_clock(struct intel_encoder *encoder,
1121                    struct intel_crtc_config *pipe_config, int link_bw)
1122 {
1123         struct drm_device *dev = encoder->base.dev;
1124         const struct dp_link_dpll *divisor = NULL;
1125         int i, count = 0;
1126
1127         if (IS_G4X(dev)) {
1128                 divisor = gen4_dpll;
1129                 count = ARRAY_SIZE(gen4_dpll);
1130         } else if (HAS_PCH_SPLIT(dev)) {
1131                 divisor = pch_dpll;
1132                 count = ARRAY_SIZE(pch_dpll);
1133         } else if (IS_CHERRYVIEW(dev)) {
1134                 divisor = chv_dpll;
1135                 count = ARRAY_SIZE(chv_dpll);
1136         } else if (IS_VALLEYVIEW(dev)) {
1137                 divisor = vlv_dpll;
1138                 count = ARRAY_SIZE(vlv_dpll);
1139         }
1140
1141         if (divisor && count) {
1142                 for (i = 0; i < count; i++) {
1143                         if (link_bw == divisor[i].link_bw) {
1144                                 pipe_config->dpll = divisor[i].dpll;
1145                                 pipe_config->clock_set = true;
1146                                 break;
1147                         }
1148                 }
1149         }
1150 }
1151
1152 bool
1153 intel_dp_compute_config(struct intel_encoder *encoder,
1154                         struct intel_crtc_config *pipe_config)
1155 {
1156         struct drm_device *dev = encoder->base.dev;
1157         struct drm_i915_private *dev_priv = dev->dev_private;
1158         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
1159         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1160         enum port port = dp_to_dig_port(intel_dp)->port;
1161         struct intel_crtc *intel_crtc = encoder->new_crtc;
1162         struct intel_connector *intel_connector = intel_dp->attached_connector;
1163         int lane_count, clock;
1164         int min_lane_count = 1;
1165         int max_lane_count = intel_dp_max_lane_count(intel_dp);
1166         /* Conveniently, the link BW constants become indices with a shift...*/
1167         int min_clock = 0;
1168         int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
1169         int bpp, mode_rate;
1170         static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
1171         int link_avail, link_clock;
1172
1173         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
1174                 pipe_config->has_pch_encoder = true;
1175
1176         pipe_config->has_dp_encoder = true;
1177         pipe_config->has_drrs = false;
1178         pipe_config->has_audio = intel_dp->has_audio;
1179
1180         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1181                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1182                                        adjusted_mode);
1183                 if (!HAS_PCH_SPLIT(dev))
1184                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
1185                                                  intel_connector->panel.fitting_mode);
1186                 else
1187                         intel_pch_panel_fitting(intel_crtc, pipe_config,
1188                                                 intel_connector->panel.fitting_mode);
1189         }
1190
1191         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1192                 return false;
1193
1194         DRM_DEBUG_KMS("DP link computation with max lane count %i "
1195                       "max bw %02x pixel clock %iKHz\n",
1196                       max_lane_count, bws[max_clock],
1197                       adjusted_mode->crtc_clock);
1198
1199         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1200          * bpc in between. */
1201         bpp = pipe_config->pipe_bpp;
1202         if (is_edp(intel_dp)) {
1203                 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
1204                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1205                                       dev_priv->vbt.edp_bpp);
1206                         bpp = dev_priv->vbt.edp_bpp;
1207                 }
1208
1209                 /*
1210                  * Use the maximum clock and number of lanes the eDP panel
1211                  * advertizes being capable of. The panels are generally
1212                  * designed to support only a single clock and lane
1213                  * configuration, and typically these values correspond to the
1214                  * native resolution of the panel.
1215                  */
1216                 min_lane_count = max_lane_count;
1217                 min_clock = max_clock;
1218         }
1219
1220         for (; bpp >= 6*3; bpp -= 2*3) {
1221                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1222                                                    bpp);
1223
1224                 for (clock = min_clock; clock <= max_clock; clock++) {
1225                         for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
1226                                 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
1227                                 link_avail = intel_dp_max_data_rate(link_clock,
1228                                                                     lane_count);
1229
1230                                 if (mode_rate <= link_avail) {
1231                                         goto found;
1232                                 }
1233                         }
1234                 }
1235         }
1236
1237         return false;
1238
1239 found:
1240         if (intel_dp->color_range_auto) {
1241                 /*
1242                  * See:
1243                  * CEA-861-E - 5.1 Default Encoding Parameters
1244                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1245                  */
1246                 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
1247                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
1248                 else
1249                         intel_dp->color_range = 0;
1250         }
1251
1252         if (intel_dp->color_range)
1253                 pipe_config->limited_color_range = true;
1254
1255         intel_dp->link_bw = bws[clock];
1256         intel_dp->lane_count = lane_count;
1257         pipe_config->pipe_bpp = bpp;
1258         pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
1259
1260         DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1261                       intel_dp->link_bw, intel_dp->lane_count,
1262                       pipe_config->port_clock, bpp);
1263         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1264                       mode_rate, link_avail);
1265
1266         intel_link_compute_m_n(bpp, lane_count,
1267                                adjusted_mode->crtc_clock,
1268                                pipe_config->port_clock,
1269                                &pipe_config->dp_m_n);
1270
1271         if (intel_connector->panel.downclock_mode != NULL &&
1272                 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
1273                         pipe_config->has_drrs = true;
1274                         intel_link_compute_m_n(bpp, lane_count,
1275                                 intel_connector->panel.downclock_mode->clock,
1276                                 pipe_config->port_clock,
1277                                 &pipe_config->dp_m2_n2);
1278         }
1279
1280         if (IS_SKYLAKE(dev) && is_edp(intel_dp))
1281                 skl_edp_set_pll_config(pipe_config, intel_dp->link_bw);
1282         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1283                 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
1284         else
1285                 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
1286
1287         return true;
1288 }
1289
1290 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
1291 {
1292         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1293         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1294         struct drm_device *dev = crtc->base.dev;
1295         struct drm_i915_private *dev_priv = dev->dev_private;
1296         u32 dpa_ctl;
1297
1298         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
1299         dpa_ctl = I915_READ(DP_A);
1300         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1301
1302         if (crtc->config.port_clock == 162000) {
1303                 /* For a long time we've carried around a ILK-DevA w/a for the
1304                  * 160MHz clock. If we're really unlucky, it's still required.
1305                  */
1306                 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
1307                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1308                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
1309         } else {
1310                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1311                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
1312         }
1313
1314         I915_WRITE(DP_A, dpa_ctl);
1315
1316         POSTING_READ(DP_A);
1317         udelay(500);
1318 }
1319
1320 static void intel_dp_prepare(struct intel_encoder *encoder)
1321 {
1322         struct drm_device *dev = encoder->base.dev;
1323         struct drm_i915_private *dev_priv = dev->dev_private;
1324         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1325         enum port port = dp_to_dig_port(intel_dp)->port;
1326         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1327         struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
1328
1329         /*
1330          * There are four kinds of DP registers:
1331          *
1332          *      IBX PCH
1333          *      SNB CPU
1334          *      IVB CPU
1335          *      CPT PCH
1336          *
1337          * IBX PCH and CPU are the same for almost everything,
1338          * except that the CPU DP PLL is configured in this
1339          * register
1340          *
1341          * CPT PCH is quite different, having many bits moved
1342          * to the TRANS_DP_CTL register instead. That
1343          * configuration happens (oddly) in ironlake_pch_enable
1344          */
1345
1346         /* Preserve the BIOS-computed detected bit. This is
1347          * supposed to be read-only.
1348          */
1349         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1350
1351         /* Handle DP bits in common between all three register formats */
1352         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1353         intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
1354
1355         if (crtc->config.has_audio)
1356                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
1357
1358         /* Split out the IBX/CPU vs CPT settings */
1359
1360         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1361                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1362                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1363                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1364                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1365                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1366
1367                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1368                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1369
1370                 intel_dp->DP |= crtc->pipe << 29;
1371         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1372                 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
1373                         intel_dp->DP |= intel_dp->color_range;
1374
1375                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1376                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1377                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1378                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1379                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1380
1381                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1382                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1383
1384                 if (!IS_CHERRYVIEW(dev)) {
1385                         if (crtc->pipe == 1)
1386                                 intel_dp->DP |= DP_PIPEB_SELECT;
1387                 } else {
1388                         intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1389                 }
1390         } else {
1391                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1392         }
1393 }
1394
1395 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1396 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1397
1398 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
1399 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
1400
1401 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1402 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1403
1404 static void wait_panel_status(struct intel_dp *intel_dp,
1405                                        u32 mask,
1406                                        u32 value)
1407 {
1408         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1409         struct drm_i915_private *dev_priv = dev->dev_private;
1410         u32 pp_stat_reg, pp_ctrl_reg;
1411
1412         lockdep_assert_held(&dev_priv->pps_mutex);
1413
1414         pp_stat_reg = _pp_stat_reg(intel_dp);
1415         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1416
1417         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1418                         mask, value,
1419                         I915_READ(pp_stat_reg),
1420                         I915_READ(pp_ctrl_reg));
1421
1422         if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1423                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1424                                 I915_READ(pp_stat_reg),
1425                                 I915_READ(pp_ctrl_reg));
1426         }
1427
1428         DRM_DEBUG_KMS("Wait complete\n");
1429 }
1430
1431 static void wait_panel_on(struct intel_dp *intel_dp)
1432 {
1433         DRM_DEBUG_KMS("Wait for panel power on\n");
1434         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1435 }
1436
1437 static void wait_panel_off(struct intel_dp *intel_dp)
1438 {
1439         DRM_DEBUG_KMS("Wait for panel power off time\n");
1440         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1441 }
1442
1443 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1444 {
1445         DRM_DEBUG_KMS("Wait for panel power cycle\n");
1446
1447         /* When we disable the VDD override bit last we have to do the manual
1448          * wait. */
1449         wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1450                                        intel_dp->panel_power_cycle_delay);
1451
1452         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1453 }
1454
1455 static void wait_backlight_on(struct intel_dp *intel_dp)
1456 {
1457         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1458                                        intel_dp->backlight_on_delay);
1459 }
1460
1461 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1462 {
1463         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1464                                        intel_dp->backlight_off_delay);
1465 }
1466
1467 /* Read the current pp_control value, unlocking the register if it
1468  * is locked
1469  */
1470
1471 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1472 {
1473         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1474         struct drm_i915_private *dev_priv = dev->dev_private;
1475         u32 control;
1476
1477         lockdep_assert_held(&dev_priv->pps_mutex);
1478
1479         control = I915_READ(_pp_ctrl_reg(intel_dp));
1480         control &= ~PANEL_UNLOCK_MASK;
1481         control |= PANEL_UNLOCK_REGS;
1482         return control;
1483 }
1484
1485 /*
1486  * Must be paired with edp_panel_vdd_off().
1487  * Must hold pps_mutex around the whole on/off sequence.
1488  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1489  */
1490 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
1491 {
1492         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1493         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1494         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1495         struct drm_i915_private *dev_priv = dev->dev_private;
1496         enum intel_display_power_domain power_domain;
1497         u32 pp;
1498         u32 pp_stat_reg, pp_ctrl_reg;
1499         bool need_to_disable = !intel_dp->want_panel_vdd;
1500
1501         lockdep_assert_held(&dev_priv->pps_mutex);
1502
1503         if (!is_edp(intel_dp))
1504                 return false;
1505
1506         intel_dp->want_panel_vdd = true;
1507
1508         if (edp_have_panel_vdd(intel_dp))
1509                 return need_to_disable;
1510
1511         power_domain = intel_display_port_power_domain(intel_encoder);
1512         intel_display_power_get(dev_priv, power_domain);
1513
1514         DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1515                       port_name(intel_dig_port->port));
1516
1517         if (!edp_have_panel_power(intel_dp))
1518                 wait_panel_power_cycle(intel_dp);
1519
1520         pp = ironlake_get_pp_control(intel_dp);
1521         pp |= EDP_FORCE_VDD;
1522
1523         pp_stat_reg = _pp_stat_reg(intel_dp);
1524         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1525
1526         I915_WRITE(pp_ctrl_reg, pp);
1527         POSTING_READ(pp_ctrl_reg);
1528         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1529                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1530         /*
1531          * If the panel wasn't on, delay before accessing aux channel
1532          */
1533         if (!edp_have_panel_power(intel_dp)) {
1534                 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1535                               port_name(intel_dig_port->port));
1536                 msleep(intel_dp->panel_power_up_delay);
1537         }
1538
1539         return need_to_disable;
1540 }
1541
1542 /*
1543  * Must be paired with intel_edp_panel_vdd_off() or
1544  * intel_edp_panel_off().
1545  * Nested calls to these functions are not allowed since
1546  * we drop the lock. Caller must use some higher level
1547  * locking to prevent nested calls from other threads.
1548  */
1549 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1550 {
1551         bool vdd;
1552
1553         if (!is_edp(intel_dp))
1554                 return;
1555
1556         pps_lock(intel_dp);
1557         vdd = edp_panel_vdd_on(intel_dp);
1558         pps_unlock(intel_dp);
1559
1560         WARN(!vdd, "eDP port %c VDD already requested on\n",
1561              port_name(dp_to_dig_port(intel_dp)->port));
1562 }
1563
1564 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1565 {
1566         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1567         struct drm_i915_private *dev_priv = dev->dev_private;
1568         struct intel_digital_port *intel_dig_port =
1569                 dp_to_dig_port(intel_dp);
1570         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1571         enum intel_display_power_domain power_domain;
1572         u32 pp;
1573         u32 pp_stat_reg, pp_ctrl_reg;
1574
1575         lockdep_assert_held(&dev_priv->pps_mutex);
1576
1577         WARN_ON(intel_dp->want_panel_vdd);
1578
1579         if (!edp_have_panel_vdd(intel_dp))
1580                 return;
1581
1582         DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1583                       port_name(intel_dig_port->port));
1584
1585         pp = ironlake_get_pp_control(intel_dp);
1586         pp &= ~EDP_FORCE_VDD;
1587
1588         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1589         pp_stat_reg = _pp_stat_reg(intel_dp);
1590
1591         I915_WRITE(pp_ctrl_reg, pp);
1592         POSTING_READ(pp_ctrl_reg);
1593
1594         /* Make sure sequencer is idle before allowing subsequent activity */
1595         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1596         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1597
1598         if ((pp & POWER_TARGET_ON) == 0)
1599                 intel_dp->last_power_cycle = jiffies;
1600
1601         power_domain = intel_display_port_power_domain(intel_encoder);
1602         intel_display_power_put(dev_priv, power_domain);
1603 }
1604
1605 static void edp_panel_vdd_work(struct work_struct *__work)
1606 {
1607         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1608                                                  struct intel_dp, panel_vdd_work);
1609
1610         pps_lock(intel_dp);
1611         if (!intel_dp->want_panel_vdd)
1612                 edp_panel_vdd_off_sync(intel_dp);
1613         pps_unlock(intel_dp);
1614 }
1615
1616 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1617 {
1618         unsigned long delay;
1619
1620         /*
1621          * Queue the timer to fire a long time from now (relative to the power
1622          * down delay) to keep the panel power up across a sequence of
1623          * operations.
1624          */
1625         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1626         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1627 }
1628
1629 /*
1630  * Must be paired with edp_panel_vdd_on().
1631  * Must hold pps_mutex around the whole on/off sequence.
1632  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1633  */
1634 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1635 {
1636         struct drm_i915_private *dev_priv =
1637                 intel_dp_to_dev(intel_dp)->dev_private;
1638
1639         lockdep_assert_held(&dev_priv->pps_mutex);
1640
1641         if (!is_edp(intel_dp))
1642                 return;
1643
1644         WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
1645              port_name(dp_to_dig_port(intel_dp)->port));
1646
1647         intel_dp->want_panel_vdd = false;
1648
1649         if (sync)
1650                 edp_panel_vdd_off_sync(intel_dp);
1651         else
1652                 edp_panel_vdd_schedule_off(intel_dp);
1653 }
1654
1655 static void edp_panel_on(struct intel_dp *intel_dp)
1656 {
1657         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1658         struct drm_i915_private *dev_priv = dev->dev_private;
1659         u32 pp;
1660         u32 pp_ctrl_reg;
1661
1662         lockdep_assert_held(&dev_priv->pps_mutex);
1663
1664         if (!is_edp(intel_dp))
1665                 return;
1666
1667         DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
1668                       port_name(dp_to_dig_port(intel_dp)->port));
1669
1670         if (WARN(edp_have_panel_power(intel_dp),
1671                  "eDP port %c panel power already on\n",
1672                  port_name(dp_to_dig_port(intel_dp)->port)))
1673                 return;
1674
1675         wait_panel_power_cycle(intel_dp);
1676
1677         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1678         pp = ironlake_get_pp_control(intel_dp);
1679         if (IS_GEN5(dev)) {
1680                 /* ILK workaround: disable reset around power sequence */
1681                 pp &= ~PANEL_POWER_RESET;
1682                 I915_WRITE(pp_ctrl_reg, pp);
1683                 POSTING_READ(pp_ctrl_reg);
1684         }
1685
1686         pp |= POWER_TARGET_ON;
1687         if (!IS_GEN5(dev))
1688                 pp |= PANEL_POWER_RESET;
1689
1690         I915_WRITE(pp_ctrl_reg, pp);
1691         POSTING_READ(pp_ctrl_reg);
1692
1693         wait_panel_on(intel_dp);
1694         intel_dp->last_power_on = jiffies;
1695
1696         if (IS_GEN5(dev)) {
1697                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1698                 I915_WRITE(pp_ctrl_reg, pp);
1699                 POSTING_READ(pp_ctrl_reg);
1700         }
1701 }
1702
1703 void intel_edp_panel_on(struct intel_dp *intel_dp)
1704 {
1705         if (!is_edp(intel_dp))
1706                 return;
1707
1708         pps_lock(intel_dp);
1709         edp_panel_on(intel_dp);
1710         pps_unlock(intel_dp);
1711 }
1712
1713
1714 static void edp_panel_off(struct intel_dp *intel_dp)
1715 {
1716         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1717         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1718         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1719         struct drm_i915_private *dev_priv = dev->dev_private;
1720         enum intel_display_power_domain power_domain;
1721         u32 pp;
1722         u32 pp_ctrl_reg;
1723
1724         lockdep_assert_held(&dev_priv->pps_mutex);
1725
1726         if (!is_edp(intel_dp))
1727                 return;
1728
1729         DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
1730                       port_name(dp_to_dig_port(intel_dp)->port));
1731
1732         WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
1733              port_name(dp_to_dig_port(intel_dp)->port));
1734
1735         pp = ironlake_get_pp_control(intel_dp);
1736         /* We need to switch off panel power _and_ force vdd, for otherwise some
1737          * panels get very unhappy and cease to work. */
1738         pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1739                 EDP_BLC_ENABLE);
1740
1741         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1742
1743         intel_dp->want_panel_vdd = false;
1744
1745         I915_WRITE(pp_ctrl_reg, pp);
1746         POSTING_READ(pp_ctrl_reg);
1747
1748         intel_dp->last_power_cycle = jiffies;
1749         wait_panel_off(intel_dp);
1750
1751         /* We got a reference when we enabled the VDD. */
1752         power_domain = intel_display_port_power_domain(intel_encoder);
1753         intel_display_power_put(dev_priv, power_domain);
1754 }
1755
1756 void intel_edp_panel_off(struct intel_dp *intel_dp)
1757 {
1758         if (!is_edp(intel_dp))
1759                 return;
1760
1761         pps_lock(intel_dp);
1762         edp_panel_off(intel_dp);
1763         pps_unlock(intel_dp);
1764 }
1765
1766 /* Enable backlight in the panel power control. */
1767 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
1768 {
1769         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1770         struct drm_device *dev = intel_dig_port->base.base.dev;
1771         struct drm_i915_private *dev_priv = dev->dev_private;
1772         u32 pp;
1773         u32 pp_ctrl_reg;
1774
1775         /*
1776          * If we enable the backlight right away following a panel power
1777          * on, we may see slight flicker as the panel syncs with the eDP
1778          * link.  So delay a bit to make sure the image is solid before
1779          * allowing it to appear.
1780          */
1781         wait_backlight_on(intel_dp);
1782
1783         pps_lock(intel_dp);
1784
1785         pp = ironlake_get_pp_control(intel_dp);
1786         pp |= EDP_BLC_ENABLE;
1787
1788         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1789
1790         I915_WRITE(pp_ctrl_reg, pp);
1791         POSTING_READ(pp_ctrl_reg);
1792
1793         pps_unlock(intel_dp);
1794 }
1795
1796 /* Enable backlight PWM and backlight PP control. */
1797 void intel_edp_backlight_on(struct intel_dp *intel_dp)
1798 {
1799         if (!is_edp(intel_dp))
1800                 return;
1801
1802         DRM_DEBUG_KMS("\n");
1803
1804         intel_panel_enable_backlight(intel_dp->attached_connector);
1805         _intel_edp_backlight_on(intel_dp);
1806 }
1807
1808 /* Disable backlight in the panel power control. */
1809 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
1810 {
1811         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1812         struct drm_i915_private *dev_priv = dev->dev_private;
1813         u32 pp;
1814         u32 pp_ctrl_reg;
1815
1816         if (!is_edp(intel_dp))
1817                 return;
1818
1819         pps_lock(intel_dp);
1820
1821         pp = ironlake_get_pp_control(intel_dp);
1822         pp &= ~EDP_BLC_ENABLE;
1823
1824         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1825
1826         I915_WRITE(pp_ctrl_reg, pp);
1827         POSTING_READ(pp_ctrl_reg);
1828
1829         pps_unlock(intel_dp);
1830
1831         intel_dp->last_backlight_off = jiffies;
1832         edp_wait_backlight_off(intel_dp);
1833 }
1834
1835 /* Disable backlight PP control and backlight PWM. */
1836 void intel_edp_backlight_off(struct intel_dp *intel_dp)
1837 {
1838         if (!is_edp(intel_dp))
1839                 return;
1840
1841         DRM_DEBUG_KMS("\n");
1842
1843         _intel_edp_backlight_off(intel_dp);
1844         intel_panel_disable_backlight(intel_dp->attached_connector);
1845 }
1846
1847 /*
1848  * Hook for controlling the panel power control backlight through the bl_power
1849  * sysfs attribute. Take care to handle multiple calls.
1850  */
1851 static void intel_edp_backlight_power(struct intel_connector *connector,
1852                                       bool enable)
1853 {
1854         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
1855         bool is_enabled;
1856
1857         pps_lock(intel_dp);
1858         is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
1859         pps_unlock(intel_dp);
1860
1861         if (is_enabled == enable)
1862                 return;
1863
1864         DRM_DEBUG_KMS("panel power control backlight %s\n",
1865                       enable ? "enable" : "disable");
1866
1867         if (enable)
1868                 _intel_edp_backlight_on(intel_dp);
1869         else
1870                 _intel_edp_backlight_off(intel_dp);
1871 }
1872
1873 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1874 {
1875         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1876         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1877         struct drm_device *dev = crtc->dev;
1878         struct drm_i915_private *dev_priv = dev->dev_private;
1879         u32 dpa_ctl;
1880
1881         assert_pipe_disabled(dev_priv,
1882                              to_intel_crtc(crtc)->pipe);
1883
1884         DRM_DEBUG_KMS("\n");
1885         dpa_ctl = I915_READ(DP_A);
1886         WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1887         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1888
1889         /* We don't adjust intel_dp->DP while tearing down the link, to
1890          * facilitate link retraining (e.g. after hotplug). Hence clear all
1891          * enable bits here to ensure that we don't enable too much. */
1892         intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1893         intel_dp->DP |= DP_PLL_ENABLE;
1894         I915_WRITE(DP_A, intel_dp->DP);
1895         POSTING_READ(DP_A);
1896         udelay(200);
1897 }
1898
1899 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1900 {
1901         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1902         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1903         struct drm_device *dev = crtc->dev;
1904         struct drm_i915_private *dev_priv = dev->dev_private;
1905         u32 dpa_ctl;
1906
1907         assert_pipe_disabled(dev_priv,
1908                              to_intel_crtc(crtc)->pipe);
1909
1910         dpa_ctl = I915_READ(DP_A);
1911         WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1912              "dp pll off, should be on\n");
1913         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1914
1915         /* We can't rely on the value tracked for the DP register in
1916          * intel_dp->DP because link_down must not change that (otherwise link
1917          * re-training will fail. */
1918         dpa_ctl &= ~DP_PLL_ENABLE;
1919         I915_WRITE(DP_A, dpa_ctl);
1920         POSTING_READ(DP_A);
1921         udelay(200);
1922 }
1923
1924 /* If the sink supports it, try to set the power state appropriately */
1925 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1926 {
1927         int ret, i;
1928
1929         /* Should have a valid DPCD by this point */
1930         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1931                 return;
1932
1933         if (mode != DRM_MODE_DPMS_ON) {
1934                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1935                                          DP_SET_POWER_D3);
1936         } else {
1937                 /*
1938                  * When turning on, we need to retry for 1ms to give the sink
1939                  * time to wake up.
1940                  */
1941                 for (i = 0; i < 3; i++) {
1942                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1943                                                  DP_SET_POWER_D0);
1944                         if (ret == 1)
1945                                 break;
1946                         msleep(1);
1947                 }
1948         }
1949
1950         if (ret != 1)
1951                 DRM_DEBUG_KMS("failed to %s sink power state\n",
1952                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
1953 }
1954
1955 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1956                                   enum pipe *pipe)
1957 {
1958         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1959         enum port port = dp_to_dig_port(intel_dp)->port;
1960         struct drm_device *dev = encoder->base.dev;
1961         struct drm_i915_private *dev_priv = dev->dev_private;
1962         enum intel_display_power_domain power_domain;
1963         u32 tmp;
1964
1965         power_domain = intel_display_port_power_domain(encoder);
1966         if (!intel_display_power_is_enabled(dev_priv, power_domain))
1967                 return false;
1968
1969         tmp = I915_READ(intel_dp->output_reg);
1970
1971         if (!(tmp & DP_PORT_EN))
1972                 return false;
1973
1974         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1975                 *pipe = PORT_TO_PIPE_CPT(tmp);
1976         } else if (IS_CHERRYVIEW(dev)) {
1977                 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
1978         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1979                 *pipe = PORT_TO_PIPE(tmp);
1980         } else {
1981                 u32 trans_sel;
1982                 u32 trans_dp;
1983                 int i;
1984
1985                 switch (intel_dp->output_reg) {
1986                 case PCH_DP_B:
1987                         trans_sel = TRANS_DP_PORT_SEL_B;
1988                         break;
1989                 case PCH_DP_C:
1990                         trans_sel = TRANS_DP_PORT_SEL_C;
1991                         break;
1992                 case PCH_DP_D:
1993                         trans_sel = TRANS_DP_PORT_SEL_D;
1994                         break;
1995                 default:
1996                         return true;
1997                 }
1998
1999                 for_each_pipe(dev_priv, i) {
2000                         trans_dp = I915_READ(TRANS_DP_CTL(i));
2001                         if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
2002                                 *pipe = i;
2003                                 return true;
2004                         }
2005                 }
2006
2007                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2008                               intel_dp->output_reg);
2009         }
2010
2011         return true;
2012 }
2013
2014 static void intel_dp_get_config(struct intel_encoder *encoder,
2015                                 struct intel_crtc_config *pipe_config)
2016 {
2017         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2018         u32 tmp, flags = 0;
2019         struct drm_device *dev = encoder->base.dev;
2020         struct drm_i915_private *dev_priv = dev->dev_private;
2021         enum port port = dp_to_dig_port(intel_dp)->port;
2022         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2023         int dotclock;
2024
2025         tmp = I915_READ(intel_dp->output_reg);
2026         if (tmp & DP_AUDIO_OUTPUT_ENABLE)
2027                 pipe_config->has_audio = true;
2028
2029         if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
2030                 if (tmp & DP_SYNC_HS_HIGH)
2031                         flags |= DRM_MODE_FLAG_PHSYNC;
2032                 else
2033                         flags |= DRM_MODE_FLAG_NHSYNC;
2034
2035                 if (tmp & DP_SYNC_VS_HIGH)
2036                         flags |= DRM_MODE_FLAG_PVSYNC;
2037                 else
2038                         flags |= DRM_MODE_FLAG_NVSYNC;
2039         } else {
2040                 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2041                 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2042                         flags |= DRM_MODE_FLAG_PHSYNC;
2043                 else
2044                         flags |= DRM_MODE_FLAG_NHSYNC;
2045
2046                 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2047                         flags |= DRM_MODE_FLAG_PVSYNC;
2048                 else
2049                         flags |= DRM_MODE_FLAG_NVSYNC;
2050         }
2051
2052         pipe_config->adjusted_mode.flags |= flags;
2053
2054         if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
2055             tmp & DP_COLOR_RANGE_16_235)
2056                 pipe_config->limited_color_range = true;
2057
2058         pipe_config->has_dp_encoder = true;
2059
2060         intel_dp_get_m_n(crtc, pipe_config);
2061
2062         if (port == PORT_A) {
2063                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
2064                         pipe_config->port_clock = 162000;
2065                 else
2066                         pipe_config->port_clock = 270000;
2067         }
2068
2069         dotclock = intel_dotclock_calculate(pipe_config->port_clock,
2070                                             &pipe_config->dp_m_n);
2071
2072         if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
2073                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
2074
2075         pipe_config->adjusted_mode.crtc_clock = dotclock;
2076
2077         if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
2078             pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2079                 /*
2080                  * This is a big fat ugly hack.
2081                  *
2082                  * Some machines in UEFI boot mode provide us a VBT that has 18
2083                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2084                  * unknown we fail to light up. Yet the same BIOS boots up with
2085                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2086                  * max, not what it tells us to use.
2087                  *
2088                  * Note: This will still be broken if the eDP panel is not lit
2089                  * up by the BIOS, and thus we can't get the mode at module
2090                  * load.
2091                  */
2092                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2093                               pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2094                 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2095         }
2096 }
2097
2098 static void intel_disable_dp(struct intel_encoder *encoder)
2099 {
2100         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2101         struct drm_device *dev = encoder->base.dev;
2102         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2103
2104         if (crtc->config.has_audio)
2105                 intel_audio_codec_disable(encoder);
2106
2107         /* Make sure the panel is off before trying to change the mode. But also
2108          * ensure that we have vdd while we switch off the panel. */
2109         intel_edp_panel_vdd_on(intel_dp);
2110         intel_edp_backlight_off(intel_dp);
2111         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2112         intel_edp_panel_off(intel_dp);
2113
2114         /* disable the port before the pipe on g4x */
2115         if (INTEL_INFO(dev)->gen < 5)
2116                 intel_dp_link_down(intel_dp);
2117 }
2118
2119 static void ilk_post_disable_dp(struct intel_encoder *encoder)
2120 {
2121         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2122         enum port port = dp_to_dig_port(intel_dp)->port;
2123
2124         intel_dp_link_down(intel_dp);
2125         if (port == PORT_A)
2126                 ironlake_edp_pll_off(intel_dp);
2127 }
2128
2129 static void vlv_post_disable_dp(struct intel_encoder *encoder)
2130 {
2131         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2132
2133         intel_dp_link_down(intel_dp);
2134 }
2135
2136 static void chv_post_disable_dp(struct intel_encoder *encoder)
2137 {
2138         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2139         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2140         struct drm_device *dev = encoder->base.dev;
2141         struct drm_i915_private *dev_priv = dev->dev_private;
2142         struct intel_crtc *intel_crtc =
2143                 to_intel_crtc(encoder->base.crtc);
2144         enum dpio_channel ch = vlv_dport_to_channel(dport);
2145         enum pipe pipe = intel_crtc->pipe;
2146         u32 val;
2147
2148         intel_dp_link_down(intel_dp);
2149
2150         mutex_lock(&dev_priv->dpio_lock);
2151
2152         /* Propagate soft reset to data lane reset */
2153         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2154         val |= CHV_PCS_REQ_SOFTRESET_EN;
2155         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2156
2157         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2158         val |= CHV_PCS_REQ_SOFTRESET_EN;
2159         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2160
2161         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2162         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2163         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2164
2165         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2166         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2167         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2168
2169         mutex_unlock(&dev_priv->dpio_lock);
2170 }
2171
2172 static void
2173 _intel_dp_set_link_train(struct intel_dp *intel_dp,
2174                          uint32_t *DP,
2175                          uint8_t dp_train_pat)
2176 {
2177         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2178         struct drm_device *dev = intel_dig_port->base.base.dev;
2179         struct drm_i915_private *dev_priv = dev->dev_private;
2180         enum port port = intel_dig_port->port;
2181
2182         if (HAS_DDI(dev)) {
2183                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2184
2185                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2186                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2187                 else
2188                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2189
2190                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2191                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2192                 case DP_TRAINING_PATTERN_DISABLE:
2193                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2194
2195                         break;
2196                 case DP_TRAINING_PATTERN_1:
2197                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2198                         break;
2199                 case DP_TRAINING_PATTERN_2:
2200                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2201                         break;
2202                 case DP_TRAINING_PATTERN_3:
2203                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2204                         break;
2205                 }
2206                 I915_WRITE(DP_TP_CTL(port), temp);
2207
2208         } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2209                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2210
2211                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2212                 case DP_TRAINING_PATTERN_DISABLE:
2213                         *DP |= DP_LINK_TRAIN_OFF_CPT;
2214                         break;
2215                 case DP_TRAINING_PATTERN_1:
2216                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2217                         break;
2218                 case DP_TRAINING_PATTERN_2:
2219                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2220                         break;
2221                 case DP_TRAINING_PATTERN_3:
2222                         DRM_ERROR("DP training pattern 3 not supported\n");
2223                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2224                         break;
2225                 }
2226
2227         } else {
2228                 if (IS_CHERRYVIEW(dev))
2229                         *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2230                 else
2231                         *DP &= ~DP_LINK_TRAIN_MASK;
2232
2233                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2234                 case DP_TRAINING_PATTERN_DISABLE:
2235                         *DP |= DP_LINK_TRAIN_OFF;
2236                         break;
2237                 case DP_TRAINING_PATTERN_1:
2238                         *DP |= DP_LINK_TRAIN_PAT_1;
2239                         break;
2240                 case DP_TRAINING_PATTERN_2:
2241                         *DP |= DP_LINK_TRAIN_PAT_2;
2242                         break;
2243                 case DP_TRAINING_PATTERN_3:
2244                         if (IS_CHERRYVIEW(dev)) {
2245                                 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2246                         } else {
2247                                 DRM_ERROR("DP training pattern 3 not supported\n");
2248                                 *DP |= DP_LINK_TRAIN_PAT_2;
2249                         }
2250                         break;
2251                 }
2252         }
2253 }
2254
2255 static void intel_dp_enable_port(struct intel_dp *intel_dp)
2256 {
2257         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2258         struct drm_i915_private *dev_priv = dev->dev_private;
2259
2260         /* enable with pattern 1 (as per spec) */
2261         _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2262                                  DP_TRAINING_PATTERN_1);
2263
2264         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2265         POSTING_READ(intel_dp->output_reg);
2266
2267         /*
2268          * Magic for VLV/CHV. We _must_ first set up the register
2269          * without actually enabling the port, and then do another
2270          * write to enable the port. Otherwise link training will
2271          * fail when the power sequencer is freshly used for this port.
2272          */
2273         intel_dp->DP |= DP_PORT_EN;
2274
2275         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2276         POSTING_READ(intel_dp->output_reg);
2277 }
2278
2279 static void intel_enable_dp(struct intel_encoder *encoder)
2280 {
2281         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2282         struct drm_device *dev = encoder->base.dev;
2283         struct drm_i915_private *dev_priv = dev->dev_private;
2284         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2285         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2286
2287         if (WARN_ON(dp_reg & DP_PORT_EN))
2288                 return;
2289
2290         pps_lock(intel_dp);
2291
2292         if (IS_VALLEYVIEW(dev))
2293                 vlv_init_panel_power_sequencer(intel_dp);
2294
2295         intel_dp_enable_port(intel_dp);
2296
2297         edp_panel_vdd_on(intel_dp);
2298         edp_panel_on(intel_dp);
2299         edp_panel_vdd_off(intel_dp, true);
2300
2301         pps_unlock(intel_dp);
2302
2303         if (IS_VALLEYVIEW(dev))
2304                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp));
2305
2306         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2307         intel_dp_start_link_train(intel_dp);
2308         intel_dp_complete_link_train(intel_dp);
2309         intel_dp_stop_link_train(intel_dp);
2310
2311         if (crtc->config.has_audio) {
2312                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2313                                  pipe_name(crtc->pipe));
2314                 intel_audio_codec_enable(encoder);
2315         }
2316 }
2317
2318 static void g4x_enable_dp(struct intel_encoder *encoder)
2319 {
2320         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2321
2322         intel_enable_dp(encoder);
2323         intel_edp_backlight_on(intel_dp);
2324 }
2325
2326 static void vlv_enable_dp(struct intel_encoder *encoder)
2327 {
2328         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2329
2330         intel_edp_backlight_on(intel_dp);
2331 }
2332
2333 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
2334 {
2335         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2336         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2337
2338         intel_dp_prepare(encoder);
2339
2340         /* Only ilk+ has port A */
2341         if (dport->port == PORT_A) {
2342                 ironlake_set_pll_cpu_edp(intel_dp);
2343                 ironlake_edp_pll_on(intel_dp);
2344         }
2345 }
2346
2347 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2348 {
2349         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2350         struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
2351         enum pipe pipe = intel_dp->pps_pipe;
2352         int pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
2353
2354         edp_panel_vdd_off_sync(intel_dp);
2355
2356         /*
2357          * VLV seems to get confused when multiple power seqeuencers
2358          * have the same port selected (even if only one has power/vdd
2359          * enabled). The failure manifests as vlv_wait_port_ready() failing
2360          * CHV on the other hand doesn't seem to mind having the same port
2361          * selected in multiple power seqeuencers, but let's clear the
2362          * port select always when logically disconnecting a power sequencer
2363          * from a port.
2364          */
2365         DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2366                       pipe_name(pipe), port_name(intel_dig_port->port));
2367         I915_WRITE(pp_on_reg, 0);
2368         POSTING_READ(pp_on_reg);
2369
2370         intel_dp->pps_pipe = INVALID_PIPE;
2371 }
2372
2373 static void vlv_steal_power_sequencer(struct drm_device *dev,
2374                                       enum pipe pipe)
2375 {
2376         struct drm_i915_private *dev_priv = dev->dev_private;
2377         struct intel_encoder *encoder;
2378
2379         lockdep_assert_held(&dev_priv->pps_mutex);
2380
2381         if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2382                 return;
2383
2384         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2385                             base.head) {
2386                 struct intel_dp *intel_dp;
2387                 enum port port;
2388
2389                 if (encoder->type != INTEL_OUTPUT_EDP)
2390                         continue;
2391
2392                 intel_dp = enc_to_intel_dp(&encoder->base);
2393                 port = dp_to_dig_port(intel_dp)->port;
2394
2395                 if (intel_dp->pps_pipe != pipe)
2396                         continue;
2397
2398                 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2399                               pipe_name(pipe), port_name(port));
2400
2401                 WARN(encoder->connectors_active,
2402                      "stealing pipe %c power sequencer from active eDP port %c\n",
2403                      pipe_name(pipe), port_name(port));
2404
2405                 /* make sure vdd is off before we steal it */
2406                 vlv_detach_power_sequencer(intel_dp);
2407         }
2408 }
2409
2410 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2411 {
2412         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2413         struct intel_encoder *encoder = &intel_dig_port->base;
2414         struct drm_device *dev = encoder->base.dev;
2415         struct drm_i915_private *dev_priv = dev->dev_private;
2416         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2417
2418         lockdep_assert_held(&dev_priv->pps_mutex);
2419
2420         if (!is_edp(intel_dp))
2421                 return;
2422
2423         if (intel_dp->pps_pipe == crtc->pipe)
2424                 return;
2425
2426         /*
2427          * If another power sequencer was being used on this
2428          * port previously make sure to turn off vdd there while
2429          * we still have control of it.
2430          */
2431         if (intel_dp->pps_pipe != INVALID_PIPE)
2432                 vlv_detach_power_sequencer(intel_dp);
2433
2434         /*
2435          * We may be stealing the power
2436          * sequencer from another port.
2437          */
2438         vlv_steal_power_sequencer(dev, crtc->pipe);
2439
2440         /* now it's all ours */
2441         intel_dp->pps_pipe = crtc->pipe;
2442
2443         DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2444                       pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2445
2446         /* init power sequencer on this pipe and port */
2447         intel_dp_init_panel_power_sequencer(dev, intel_dp);
2448         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
2449 }
2450
2451 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
2452 {
2453         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2454         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2455         struct drm_device *dev = encoder->base.dev;
2456         struct drm_i915_private *dev_priv = dev->dev_private;
2457         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2458         enum dpio_channel port = vlv_dport_to_channel(dport);
2459         int pipe = intel_crtc->pipe;
2460         u32 val;
2461
2462         mutex_lock(&dev_priv->dpio_lock);
2463
2464         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
2465         val = 0;
2466         if (pipe)
2467                 val |= (1<<21);
2468         else
2469                 val &= ~(1<<21);
2470         val |= 0x001000c4;
2471         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2472         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2473         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
2474
2475         mutex_unlock(&dev_priv->dpio_lock);
2476
2477         intel_enable_dp(encoder);
2478 }
2479
2480 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
2481 {
2482         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2483         struct drm_device *dev = encoder->base.dev;
2484         struct drm_i915_private *dev_priv = dev->dev_private;
2485         struct intel_crtc *intel_crtc =
2486                 to_intel_crtc(encoder->base.crtc);
2487         enum dpio_channel port = vlv_dport_to_channel(dport);
2488         int pipe = intel_crtc->pipe;
2489
2490         intel_dp_prepare(encoder);
2491
2492         /* Program Tx lane resets to default */
2493         mutex_lock(&dev_priv->dpio_lock);
2494         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
2495                          DPIO_PCS_TX_LANE2_RESET |
2496                          DPIO_PCS_TX_LANE1_RESET);
2497         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
2498                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2499                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2500                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2501                                  DPIO_PCS_CLK_SOFT_RESET);
2502
2503         /* Fix up inter-pair skew failure */
2504         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2505         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2506         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
2507         mutex_unlock(&dev_priv->dpio_lock);
2508 }
2509
2510 static void chv_pre_enable_dp(struct intel_encoder *encoder)
2511 {
2512         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2513         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2514         struct drm_device *dev = encoder->base.dev;
2515         struct drm_i915_private *dev_priv = dev->dev_private;
2516         struct intel_crtc *intel_crtc =
2517                 to_intel_crtc(encoder->base.crtc);
2518         enum dpio_channel ch = vlv_dport_to_channel(dport);
2519         int pipe = intel_crtc->pipe;
2520         int data, i;
2521         u32 val;
2522
2523         mutex_lock(&dev_priv->dpio_lock);
2524
2525         /* allow hardware to manage TX FIFO reset source */
2526         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2527         val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2528         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2529
2530         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2531         val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2532         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2533
2534         /* Deassert soft data lane reset*/
2535         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2536         val |= CHV_PCS_REQ_SOFTRESET_EN;
2537         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2538
2539         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2540         val |= CHV_PCS_REQ_SOFTRESET_EN;
2541         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2542
2543         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2544         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2545         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2546
2547         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2548         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2549         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2550
2551         /* Program Tx lane latency optimal setting*/
2552         for (i = 0; i < 4; i++) {
2553                 /* Set the latency optimal bit */
2554                 data = (i == 1) ? 0x0 : 0x6;
2555                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2556                                 data << DPIO_FRC_LATENCY_SHFIT);
2557
2558                 /* Set the upar bit */
2559                 data = (i == 1) ? 0x0 : 0x1;
2560                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2561                                 data << DPIO_UPAR_SHIFT);
2562         }
2563
2564         /* Data lane stagger programming */
2565         /* FIXME: Fix up value only after power analysis */
2566
2567         mutex_unlock(&dev_priv->dpio_lock);
2568
2569         intel_enable_dp(encoder);
2570 }
2571
2572 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2573 {
2574         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2575         struct drm_device *dev = encoder->base.dev;
2576         struct drm_i915_private *dev_priv = dev->dev_private;
2577         struct intel_crtc *intel_crtc =
2578                 to_intel_crtc(encoder->base.crtc);
2579         enum dpio_channel ch = vlv_dport_to_channel(dport);
2580         enum pipe pipe = intel_crtc->pipe;
2581         u32 val;
2582
2583         intel_dp_prepare(encoder);
2584
2585         mutex_lock(&dev_priv->dpio_lock);
2586
2587         /* program left/right clock distribution */
2588         if (pipe != PIPE_B) {
2589                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2590                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2591                 if (ch == DPIO_CH0)
2592                         val |= CHV_BUFLEFTENA1_FORCE;
2593                 if (ch == DPIO_CH1)
2594                         val |= CHV_BUFRIGHTENA1_FORCE;
2595                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2596         } else {
2597                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2598                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2599                 if (ch == DPIO_CH0)
2600                         val |= CHV_BUFLEFTENA2_FORCE;
2601                 if (ch == DPIO_CH1)
2602                         val |= CHV_BUFRIGHTENA2_FORCE;
2603                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2604         }
2605
2606         /* program clock channel usage */
2607         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2608         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2609         if (pipe != PIPE_B)
2610                 val &= ~CHV_PCS_USEDCLKCHANNEL;
2611         else
2612                 val |= CHV_PCS_USEDCLKCHANNEL;
2613         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2614
2615         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2616         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2617         if (pipe != PIPE_B)
2618                 val &= ~CHV_PCS_USEDCLKCHANNEL;
2619         else
2620                 val |= CHV_PCS_USEDCLKCHANNEL;
2621         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2622
2623         /*
2624          * This a a bit weird since generally CL
2625          * matches the pipe, but here we need to
2626          * pick the CL based on the port.
2627          */
2628         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2629         if (pipe != PIPE_B)
2630                 val &= ~CHV_CMN_USEDCLKCHANNEL;
2631         else
2632                 val |= CHV_CMN_USEDCLKCHANNEL;
2633         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2634
2635         mutex_unlock(&dev_priv->dpio_lock);
2636 }
2637
2638 /*
2639  * Native read with retry for link status and receiver capability reads for
2640  * cases where the sink may still be asleep.
2641  *
2642  * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2643  * supposed to retry 3 times per the spec.
2644  */
2645 static ssize_t
2646 intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2647                         void *buffer, size_t size)
2648 {
2649         ssize_t ret;
2650         int i;
2651
2652         for (i = 0; i < 3; i++) {
2653                 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2654                 if (ret == size)
2655                         return ret;
2656                 msleep(1);
2657         }
2658
2659         return ret;
2660 }
2661
2662 /*
2663  * Fetch AUX CH registers 0x202 - 0x207 which contain
2664  * link status information
2665  */
2666 static bool
2667 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2668 {
2669         return intel_dp_dpcd_read_wake(&intel_dp->aux,
2670                                        DP_LANE0_1_STATUS,
2671                                        link_status,
2672                                        DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
2673 }
2674
2675 /* These are source-specific values. */
2676 static uint8_t
2677 intel_dp_voltage_max(struct intel_dp *intel_dp)
2678 {
2679         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2680         enum port port = dp_to_dig_port(intel_dp)->port;
2681
2682         if (INTEL_INFO(dev)->gen >= 9)
2683                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2684         else if (IS_VALLEYVIEW(dev))
2685                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2686         else if (IS_GEN7(dev) && port == PORT_A)
2687                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2688         else if (HAS_PCH_CPT(dev) && port != PORT_A)
2689                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2690         else
2691                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2692 }
2693
2694 static uint8_t
2695 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2696 {
2697         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2698         enum port port = dp_to_dig_port(intel_dp)->port;
2699
2700         if (INTEL_INFO(dev)->gen >= 9) {
2701                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2702                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2703                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
2704                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2705                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2706                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2707                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
2708                 default:
2709                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2710                 }
2711         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2712                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2713                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2714                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
2715                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2716                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2717                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2718                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
2719                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2720                 default:
2721                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2722                 }
2723         } else if (IS_VALLEYVIEW(dev)) {
2724                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2725                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2726                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
2727                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2728                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2729                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2730                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
2731                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2732                 default:
2733                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2734                 }
2735         } else if (IS_GEN7(dev) && port == PORT_A) {
2736                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2737                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2738                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2739                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2740                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2741                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
2742                 default:
2743                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2744                 }
2745         } else {
2746                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2747                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2748                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2749                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2750                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2751                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2752                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
2753                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2754                 default:
2755                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2756                 }
2757         }
2758 }
2759
2760 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2761 {
2762         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2763         struct drm_i915_private *dev_priv = dev->dev_private;
2764         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2765         struct intel_crtc *intel_crtc =
2766                 to_intel_crtc(dport->base.base.crtc);
2767         unsigned long demph_reg_value, preemph_reg_value,
2768                 uniqtranscale_reg_value;
2769         uint8_t train_set = intel_dp->train_set[0];
2770         enum dpio_channel port = vlv_dport_to_channel(dport);
2771         int pipe = intel_crtc->pipe;
2772
2773         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2774         case DP_TRAIN_PRE_EMPH_LEVEL_0:
2775                 preemph_reg_value = 0x0004000;
2776                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2777                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2778                         demph_reg_value = 0x2B405555;
2779                         uniqtranscale_reg_value = 0x552AB83A;
2780                         break;
2781                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2782                         demph_reg_value = 0x2B404040;
2783                         uniqtranscale_reg_value = 0x5548B83A;
2784                         break;
2785                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2786                         demph_reg_value = 0x2B245555;
2787                         uniqtranscale_reg_value = 0x5560B83A;
2788                         break;
2789                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2790                         demph_reg_value = 0x2B405555;
2791                         uniqtranscale_reg_value = 0x5598DA3A;
2792                         break;
2793                 default:
2794                         return 0;
2795                 }
2796                 break;
2797         case DP_TRAIN_PRE_EMPH_LEVEL_1:
2798                 preemph_reg_value = 0x0002000;
2799                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2800                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2801                         demph_reg_value = 0x2B404040;
2802                         uniqtranscale_reg_value = 0x5552B83A;
2803                         break;
2804                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2805                         demph_reg_value = 0x2B404848;
2806                         uniqtranscale_reg_value = 0x5580B83A;
2807                         break;
2808                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2809                         demph_reg_value = 0x2B404040;
2810                         uniqtranscale_reg_value = 0x55ADDA3A;
2811                         break;
2812                 default:
2813                         return 0;
2814                 }
2815                 break;
2816         case DP_TRAIN_PRE_EMPH_LEVEL_2:
2817                 preemph_reg_value = 0x0000000;
2818                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2819                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2820                         demph_reg_value = 0x2B305555;
2821                         uniqtranscale_reg_value = 0x5570B83A;
2822                         break;
2823                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2824                         demph_reg_value = 0x2B2B4040;
2825                         uniqtranscale_reg_value = 0x55ADDA3A;
2826                         break;
2827                 default:
2828                         return 0;
2829                 }
2830                 break;
2831         case DP_TRAIN_PRE_EMPH_LEVEL_3:
2832                 preemph_reg_value = 0x0006000;
2833                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2834                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2835                         demph_reg_value = 0x1B405555;
2836                         uniqtranscale_reg_value = 0x55ADDA3A;
2837                         break;
2838                 default:
2839                         return 0;
2840                 }
2841                 break;
2842         default:
2843                 return 0;
2844         }
2845
2846         mutex_lock(&dev_priv->dpio_lock);
2847         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2848         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2849         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
2850                          uniqtranscale_reg_value);
2851         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2852         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2853         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2854         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
2855         mutex_unlock(&dev_priv->dpio_lock);
2856
2857         return 0;
2858 }
2859
2860 static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2861 {
2862         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2863         struct drm_i915_private *dev_priv = dev->dev_private;
2864         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2865         struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
2866         u32 deemph_reg_value, margin_reg_value, val;
2867         uint8_t train_set = intel_dp->train_set[0];
2868         enum dpio_channel ch = vlv_dport_to_channel(dport);
2869         enum pipe pipe = intel_crtc->pipe;
2870         int i;
2871
2872         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2873         case DP_TRAIN_PRE_EMPH_LEVEL_0:
2874                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2875                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2876                         deemph_reg_value = 128;
2877                         margin_reg_value = 52;
2878                         break;
2879                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2880                         deemph_reg_value = 128;
2881                         margin_reg_value = 77;
2882                         break;
2883                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2884                         deemph_reg_value = 128;
2885                         margin_reg_value = 102;
2886                         break;
2887                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2888                         deemph_reg_value = 128;
2889                         margin_reg_value = 154;
2890                         /* FIXME extra to set for 1200 */
2891                         break;
2892                 default:
2893                         return 0;
2894                 }
2895                 break;
2896         case DP_TRAIN_PRE_EMPH_LEVEL_1:
2897                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2898                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2899                         deemph_reg_value = 85;
2900                         margin_reg_value = 78;
2901                         break;
2902                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2903                         deemph_reg_value = 85;
2904                         margin_reg_value = 116;
2905                         break;
2906                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2907                         deemph_reg_value = 85;
2908                         margin_reg_value = 154;
2909                         break;
2910                 default:
2911                         return 0;
2912                 }
2913                 break;
2914         case DP_TRAIN_PRE_EMPH_LEVEL_2:
2915                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2916                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2917                         deemph_reg_value = 64;
2918                         margin_reg_value = 104;
2919                         break;
2920                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2921                         deemph_reg_value = 64;
2922                         margin_reg_value = 154;
2923                         break;
2924                 default:
2925                         return 0;
2926                 }
2927                 break;
2928         case DP_TRAIN_PRE_EMPH_LEVEL_3:
2929                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2930                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2931                         deemph_reg_value = 43;
2932                         margin_reg_value = 154;
2933                         break;
2934                 default:
2935                         return 0;
2936                 }
2937                 break;
2938         default:
2939                 return 0;
2940         }
2941
2942         mutex_lock(&dev_priv->dpio_lock);
2943
2944         /* Clear calc init */
2945         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2946         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2947         val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
2948         val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
2949         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2950
2951         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2952         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2953         val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
2954         val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
2955         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
2956
2957         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
2958         val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
2959         val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
2960         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
2961
2962         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
2963         val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
2964         val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
2965         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
2966
2967         /* Program swing deemph */
2968         for (i = 0; i < 4; i++) {
2969                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
2970                 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
2971                 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
2972                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
2973         }
2974
2975         /* Program swing margin */
2976         for (i = 0; i < 4; i++) {
2977                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2978                 val &= ~DPIO_SWING_MARGIN000_MASK;
2979                 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
2980                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2981         }
2982
2983         /* Disable unique transition scale */
2984         for (i = 0; i < 4; i++) {
2985                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2986                 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
2987                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2988         }
2989
2990         if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
2991                         == DP_TRAIN_PRE_EMPH_LEVEL_0) &&
2992                 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
2993                         == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
2994
2995                 /*
2996                  * The document said it needs to set bit 27 for ch0 and bit 26
2997                  * for ch1. Might be a typo in the doc.
2998                  * For now, for this unique transition scale selection, set bit
2999                  * 27 for ch0 and ch1.
3000                  */
3001                 for (i = 0; i < 4; i++) {
3002                         val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3003                         val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3004                         vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3005                 }
3006
3007                 for (i = 0; i < 4; i++) {
3008                         val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3009                         val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3010                         val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3011                         vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3012                 }
3013         }
3014
3015         /* Start swing calculation */
3016         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3017         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3018         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3019
3020         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3021         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3022         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
3023
3024         /* LRC Bypass */
3025         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
3026         val |= DPIO_LRC_BYPASS;
3027         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
3028
3029         mutex_unlock(&dev_priv->dpio_lock);
3030
3031         return 0;
3032 }
3033
3034 static void
3035 intel_get_adjust_train(struct intel_dp *intel_dp,
3036                        const uint8_t link_status[DP_LINK_STATUS_SIZE])
3037 {
3038         uint8_t v = 0;
3039         uint8_t p = 0;
3040         int lane;
3041         uint8_t voltage_max;
3042         uint8_t preemph_max;
3043
3044         for (lane = 0; lane < intel_dp->lane_count; lane++) {
3045                 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
3046                 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
3047
3048                 if (this_v > v)
3049                         v = this_v;
3050                 if (this_p > p)
3051                         p = this_p;
3052         }
3053
3054         voltage_max = intel_dp_voltage_max(intel_dp);
3055         if (v >= voltage_max)
3056                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
3057
3058         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
3059         if (p >= preemph_max)
3060                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
3061
3062         for (lane = 0; lane < 4; lane++)
3063                 intel_dp->train_set[lane] = v | p;
3064 }
3065
3066 static uint32_t
3067 intel_gen4_signal_levels(uint8_t train_set)
3068 {
3069         uint32_t        signal_levels = 0;
3070
3071         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3072         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3073         default:
3074                 signal_levels |= DP_VOLTAGE_0_4;
3075                 break;
3076         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3077                 signal_levels |= DP_VOLTAGE_0_6;
3078                 break;
3079         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3080                 signal_levels |= DP_VOLTAGE_0_8;
3081                 break;
3082         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3083                 signal_levels |= DP_VOLTAGE_1_2;
3084                 break;
3085         }
3086         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3087         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3088         default:
3089                 signal_levels |= DP_PRE_EMPHASIS_0;
3090                 break;
3091         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3092                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3093                 break;
3094         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3095                 signal_levels |= DP_PRE_EMPHASIS_6;
3096                 break;
3097         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3098                 signal_levels |= DP_PRE_EMPHASIS_9_5;
3099                 break;
3100         }
3101         return signal_levels;
3102 }
3103
3104 /* Gen6's DP voltage swing and pre-emphasis control */
3105 static uint32_t
3106 intel_gen6_edp_signal_levels(uint8_t train_set)
3107 {
3108         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3109                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3110         switch (signal_levels) {
3111         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3112         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3113                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3114         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3115                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3116         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3117         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3118                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3119         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3120         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3121                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3122         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3123         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3124                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3125         default:
3126                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3127                               "0x%x\n", signal_levels);
3128                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3129         }
3130 }
3131
3132 /* Gen7's DP voltage swing and pre-emphasis control */
3133 static uint32_t
3134 intel_gen7_edp_signal_levels(uint8_t train_set)
3135 {
3136         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3137                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3138         switch (signal_levels) {
3139         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3140                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3141         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3142                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3143         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3144                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3145
3146         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3147                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3148         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3149                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3150
3151         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3152                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3153         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3154                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3155
3156         default:
3157                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3158                               "0x%x\n", signal_levels);
3159                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3160         }
3161 }
3162
3163 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3164 static uint32_t
3165 intel_hsw_signal_levels(uint8_t train_set)
3166 {
3167         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3168                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3169         switch (signal_levels) {
3170         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3171                 return DDI_BUF_TRANS_SELECT(0);
3172         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3173                 return DDI_BUF_TRANS_SELECT(1);
3174         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3175                 return DDI_BUF_TRANS_SELECT(2);
3176         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
3177                 return DDI_BUF_TRANS_SELECT(3);
3178
3179         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3180                 return DDI_BUF_TRANS_SELECT(4);
3181         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3182                 return DDI_BUF_TRANS_SELECT(5);
3183         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3184                 return DDI_BUF_TRANS_SELECT(6);
3185
3186         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3187                 return DDI_BUF_TRANS_SELECT(7);
3188         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3189                 return DDI_BUF_TRANS_SELECT(8);
3190         default:
3191                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3192                               "0x%x\n", signal_levels);
3193                 return DDI_BUF_TRANS_SELECT(0);
3194         }
3195 }
3196
3197 /* Properly updates "DP" with the correct signal levels. */
3198 static void
3199 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
3200 {
3201         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3202         enum port port = intel_dig_port->port;
3203         struct drm_device *dev = intel_dig_port->base.base.dev;
3204         uint32_t signal_levels, mask;
3205         uint8_t train_set = intel_dp->train_set[0];
3206
3207         if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
3208                 signal_levels = intel_hsw_signal_levels(train_set);
3209                 mask = DDI_BUF_EMP_MASK;
3210         } else if (IS_CHERRYVIEW(dev)) {
3211                 signal_levels = intel_chv_signal_levels(intel_dp);
3212                 mask = 0;
3213         } else if (IS_VALLEYVIEW(dev)) {
3214                 signal_levels = intel_vlv_signal_levels(intel_dp);
3215                 mask = 0;
3216         } else if (IS_GEN7(dev) && port == PORT_A) {
3217                 signal_levels = intel_gen7_edp_signal_levels(train_set);
3218                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3219         } else if (IS_GEN6(dev) && port == PORT_A) {
3220                 signal_levels = intel_gen6_edp_signal_levels(train_set);
3221                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3222         } else {
3223                 signal_levels = intel_gen4_signal_levels(train_set);
3224                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3225         }
3226
3227         DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3228
3229         *DP = (*DP & ~mask) | signal_levels;
3230 }
3231
3232 static bool
3233 intel_dp_set_link_train(struct intel_dp *intel_dp,
3234                         uint32_t *DP,
3235                         uint8_t dp_train_pat)
3236 {
3237         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3238         struct drm_device *dev = intel_dig_port->base.base.dev;
3239         struct drm_i915_private *dev_priv = dev->dev_private;
3240         uint8_t buf[sizeof(intel_dp->train_set) + 1];
3241         int ret, len;
3242
3243         _intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3244
3245         I915_WRITE(intel_dp->output_reg, *DP);
3246         POSTING_READ(intel_dp->output_reg);
3247
3248         buf[0] = dp_train_pat;
3249         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
3250             DP_TRAINING_PATTERN_DISABLE) {
3251                 /* don't write DP_TRAINING_LANEx_SET on disable */
3252                 len = 1;
3253         } else {
3254                 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3255                 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3256                 len = intel_dp->lane_count + 1;
3257         }
3258
3259         ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3260                                 buf, len);
3261
3262         return ret == len;
3263 }
3264
3265 static bool
3266 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3267                         uint8_t dp_train_pat)
3268 {
3269         memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
3270         intel_dp_set_signal_levels(intel_dp, DP);
3271         return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3272 }
3273
3274 static bool
3275 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3276                            const uint8_t link_status[DP_LINK_STATUS_SIZE])
3277 {
3278         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3279         struct drm_device *dev = intel_dig_port->base.base.dev;
3280         struct drm_i915_private *dev_priv = dev->dev_private;
3281         int ret;
3282
3283         intel_get_adjust_train(intel_dp, link_status);
3284         intel_dp_set_signal_levels(intel_dp, DP);
3285
3286         I915_WRITE(intel_dp->output_reg, *DP);
3287         POSTING_READ(intel_dp->output_reg);
3288
3289         ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3290                                 intel_dp->train_set, intel_dp->lane_count);
3291
3292         return ret == intel_dp->lane_count;
3293 }
3294
3295 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3296 {
3297         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3298         struct drm_device *dev = intel_dig_port->base.base.dev;
3299         struct drm_i915_private *dev_priv = dev->dev_private;
3300         enum port port = intel_dig_port->port;
3301         uint32_t val;
3302
3303         if (!HAS_DDI(dev))
3304                 return;
3305
3306         val = I915_READ(DP_TP_CTL(port));
3307         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3308         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3309         I915_WRITE(DP_TP_CTL(port), val);
3310
3311         /*
3312          * On PORT_A we can have only eDP in SST mode. There the only reason
3313          * we need to set idle transmission mode is to work around a HW issue
3314          * where we enable the pipe while not in idle link-training mode.
3315          * In this case there is requirement to wait for a minimum number of
3316          * idle patterns to be sent.
3317          */
3318         if (port == PORT_A)
3319                 return;
3320
3321         if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3322                      1))
3323                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3324 }
3325
3326 /* Enable corresponding port and start training pattern 1 */
3327 void
3328 intel_dp_start_link_train(struct intel_dp *intel_dp)
3329 {
3330         struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
3331         struct drm_device *dev = encoder->dev;
3332         int i;
3333         uint8_t voltage;
3334         int voltage_tries, loop_tries;
3335         uint32_t DP = intel_dp->DP;
3336         uint8_t link_config[2];
3337
3338         if (HAS_DDI(dev))
3339                 intel_ddi_prepare_link_retrain(encoder);
3340
3341         /* Write the link configuration data */
3342         link_config[0] = intel_dp->link_bw;
3343         link_config[1] = intel_dp->lane_count;
3344         if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3345                 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
3346         drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
3347
3348         link_config[0] = 0;
3349         link_config[1] = DP_SET_ANSI_8B10B;
3350         drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
3351
3352         DP |= DP_PORT_EN;
3353
3354         /* clock recovery */
3355         if (!intel_dp_reset_link_train(intel_dp, &DP,
3356                                        DP_TRAINING_PATTERN_1 |
3357                                        DP_LINK_SCRAMBLING_DISABLE)) {
3358                 DRM_ERROR("failed to enable link training\n");
3359                 return;
3360         }
3361
3362         voltage = 0xff;
3363         voltage_tries = 0;
3364         loop_tries = 0;
3365         for (;;) {
3366                 uint8_t link_status[DP_LINK_STATUS_SIZE];
3367
3368                 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
3369                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3370                         DRM_ERROR("failed to get link status\n");
3371                         break;
3372                 }
3373
3374                 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3375                         DRM_DEBUG_KMS("clock recovery OK\n");
3376                         break;
3377                 }
3378
3379                 /* Check to see if we've tried the max voltage */
3380                 for (i = 0; i < intel_dp->lane_count; i++)
3381                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
3382                                 break;
3383                 if (i == intel_dp->lane_count) {
3384                         ++loop_tries;
3385                         if (loop_tries == 5) {
3386                                 DRM_ERROR("too many full retries, give up\n");
3387                                 break;
3388                         }
3389                         intel_dp_reset_link_train(intel_dp, &DP,
3390                                                   DP_TRAINING_PATTERN_1 |
3391                                                   DP_LINK_SCRAMBLING_DISABLE);
3392                         voltage_tries = 0;
3393                         continue;
3394                 }
3395
3396                 /* Check to see if we've tried the same voltage 5 times */
3397                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
3398                         ++voltage_tries;
3399                         if (voltage_tries == 5) {
3400                                 DRM_ERROR("too many voltage retries, give up\n");
3401                                 break;
3402                         }
3403                 } else
3404                         voltage_tries = 0;
3405                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
3406
3407                 /* Update training set as requested by target */
3408                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3409                         DRM_ERROR("failed to update link training\n");
3410                         break;
3411                 }
3412         }
3413
3414         intel_dp->DP = DP;
3415 }
3416
3417 void
3418 intel_dp_complete_link_train(struct intel_dp *intel_dp)
3419 {
3420         bool channel_eq = false;
3421         int tries, cr_tries;
3422         uint32_t DP = intel_dp->DP;
3423         uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3424
3425         /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3426         if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3427                 training_pattern = DP_TRAINING_PATTERN_3;
3428
3429         /* channel equalization */
3430         if (!intel_dp_set_link_train(intel_dp, &DP,
3431                                      training_pattern |
3432                                      DP_LINK_SCRAMBLING_DISABLE)) {
3433                 DRM_ERROR("failed to start channel equalization\n");
3434                 return;
3435         }
3436
3437         tries = 0;
3438         cr_tries = 0;
3439         channel_eq = false;
3440         for (;;) {
3441                 uint8_t link_status[DP_LINK_STATUS_SIZE];
3442
3443                 if (cr_tries > 5) {
3444                         DRM_ERROR("failed to train DP, aborting\n");
3445                         break;
3446                 }
3447
3448                 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
3449                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3450                         DRM_ERROR("failed to get link status\n");
3451                         break;
3452                 }
3453
3454                 /* Make sure clock is still ok */
3455                 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3456                         intel_dp_start_link_train(intel_dp);
3457                         intel_dp_set_link_train(intel_dp, &DP,
3458                                                 training_pattern |
3459                                                 DP_LINK_SCRAMBLING_DISABLE);
3460                         cr_tries++;
3461                         continue;
3462                 }
3463
3464                 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3465                         channel_eq = true;
3466                         break;
3467                 }
3468
3469                 /* Try 5 times, then try clock recovery if that fails */
3470                 if (tries > 5) {
3471                         intel_dp_start_link_train(intel_dp);
3472                         intel_dp_set_link_train(intel_dp, &DP,
3473                                                 training_pattern |
3474                                                 DP_LINK_SCRAMBLING_DISABLE);
3475                         tries = 0;
3476                         cr_tries++;
3477                         continue;
3478                 }
3479
3480                 /* Update training set as requested by target */
3481                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3482                         DRM_ERROR("failed to update link training\n");
3483                         break;
3484                 }
3485                 ++tries;
3486         }
3487
3488         intel_dp_set_idle_link_train(intel_dp);
3489
3490         intel_dp->DP = DP;
3491
3492         if (channel_eq)
3493                 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3494
3495 }
3496
3497 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3498 {
3499         intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3500                                 DP_TRAINING_PATTERN_DISABLE);
3501 }
3502
3503 static void
3504 intel_dp_link_down(struct intel_dp *intel_dp)
3505 {
3506         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3507         enum port port = intel_dig_port->port;
3508         struct drm_device *dev = intel_dig_port->base.base.dev;
3509         struct drm_i915_private *dev_priv = dev->dev_private;
3510         struct intel_crtc *intel_crtc =
3511                 to_intel_crtc(intel_dig_port->base.base.crtc);
3512         uint32_t DP = intel_dp->DP;
3513
3514         if (WARN_ON(HAS_DDI(dev)))
3515                 return;
3516
3517         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3518                 return;
3519
3520         DRM_DEBUG_KMS("\n");
3521
3522         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
3523                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3524                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
3525         } else {
3526                 if (IS_CHERRYVIEW(dev))
3527                         DP &= ~DP_LINK_TRAIN_MASK_CHV;
3528                 else
3529                         DP &= ~DP_LINK_TRAIN_MASK;
3530                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
3531         }
3532         POSTING_READ(intel_dp->output_reg);
3533
3534         if (HAS_PCH_IBX(dev) &&
3535             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
3536                 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
3537
3538                 /* Hardware workaround: leaving our transcoder select
3539                  * set to transcoder B while it's off will prevent the
3540                  * corresponding HDMI output on transcoder A.
3541                  *
3542                  * Combine this with another hardware workaround:
3543                  * transcoder select bit can only be cleared while the
3544                  * port is enabled.
3545                  */
3546                 DP &= ~DP_PIPEB_SELECT;
3547                 I915_WRITE(intel_dp->output_reg, DP);
3548
3549                 /* Changes to enable or select take place the vblank
3550                  * after being written.
3551                  */
3552                 if (WARN_ON(crtc == NULL)) {
3553                         /* We should never try to disable a port without a crtc
3554                          * attached. For paranoia keep the code around for a
3555                          * bit. */
3556                         POSTING_READ(intel_dp->output_reg);
3557                         msleep(50);
3558                 } else
3559                         intel_wait_for_vblank(dev, intel_crtc->pipe);
3560         }
3561
3562         DP &= ~DP_AUDIO_OUTPUT_ENABLE;
3563         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3564         POSTING_READ(intel_dp->output_reg);
3565         msleep(intel_dp->panel_power_down_delay);
3566 }
3567
3568 static bool
3569 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3570 {
3571         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3572         struct drm_device *dev = dig_port->base.base.dev;
3573         struct drm_i915_private *dev_priv = dev->dev_private;
3574
3575         if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3576                                     sizeof(intel_dp->dpcd)) < 0)
3577                 return false; /* aux transfer failed */
3578
3579         DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3580
3581         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3582                 return false; /* DPCD not present */
3583
3584         /* Check if the panel supports PSR */
3585         memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
3586         if (is_edp(intel_dp)) {
3587                 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3588                                         intel_dp->psr_dpcd,
3589                                         sizeof(intel_dp->psr_dpcd));
3590                 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3591                         dev_priv->psr.sink_support = true;
3592                         DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3593                 }
3594         }
3595
3596         /* Training Pattern 3 support */
3597         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3598             intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3599                 intel_dp->use_tps3 = true;
3600                 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
3601         } else
3602                 intel_dp->use_tps3 = false;
3603
3604         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3605               DP_DWN_STRM_PORT_PRESENT))
3606                 return true; /* native DP sink */
3607
3608         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3609                 return true; /* no per-port downstream info */
3610
3611         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3612                                     intel_dp->downstream_ports,
3613                                     DP_MAX_DOWNSTREAM_PORTS) < 0)
3614                 return false; /* downstream port status fetch failed */
3615
3616         return true;
3617 }
3618
3619 static void
3620 intel_dp_probe_oui(struct intel_dp *intel_dp)
3621 {
3622         u8 buf[3];
3623
3624         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3625                 return;
3626
3627         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
3628                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3629                               buf[0], buf[1], buf[2]);
3630
3631         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
3632                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3633                               buf[0], buf[1], buf[2]);
3634 }
3635
3636 static bool
3637 intel_dp_probe_mst(struct intel_dp *intel_dp)
3638 {
3639         u8 buf[1];
3640
3641         if (!intel_dp->can_mst)
3642                 return false;
3643
3644         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3645                 return false;
3646
3647         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3648                 if (buf[0] & DP_MST_CAP) {
3649                         DRM_DEBUG_KMS("Sink is MST capable\n");
3650                         intel_dp->is_mst = true;
3651                 } else {
3652                         DRM_DEBUG_KMS("Sink is not MST capable\n");
3653                         intel_dp->is_mst = false;
3654                 }
3655         }
3656
3657         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3658         return intel_dp->is_mst;
3659 }
3660
3661 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3662 {
3663         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3664         struct drm_device *dev = intel_dig_port->base.base.dev;
3665         struct intel_crtc *intel_crtc =
3666                 to_intel_crtc(intel_dig_port->base.base.crtc);
3667         u8 buf;
3668         int test_crc_count;
3669         int attempts = 6;
3670
3671         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3672                 return -EIO;
3673
3674         if (!(buf & DP_TEST_CRC_SUPPORTED))
3675                 return -ENOTTY;
3676
3677         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3678                 return -EIO;
3679
3680         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3681                                 buf | DP_TEST_SINK_START) < 0)
3682                 return -EIO;
3683
3684         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3685                 return -EIO;
3686         test_crc_count = buf & DP_TEST_COUNT_MASK;
3687
3688         do {
3689                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3690                                       DP_TEST_SINK_MISC, &buf) < 0)
3691                         return -EIO;
3692                 intel_wait_for_vblank(dev, intel_crtc->pipe);
3693         } while (--attempts && (buf & DP_TEST_COUNT_MASK) == test_crc_count);
3694
3695         if (attempts == 0) {
3696                 DRM_DEBUG_KMS("Panel is unable to calculate CRC after 6 vblanks\n");
3697                 return -ETIMEDOUT;
3698         }
3699
3700         if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
3701                 return -EIO;
3702
3703         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3704                 return -EIO;
3705         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3706                                buf & ~DP_TEST_SINK_START) < 0)
3707                 return -EIO;
3708
3709         return 0;
3710 }
3711
3712 static bool
3713 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3714 {
3715         return intel_dp_dpcd_read_wake(&intel_dp->aux,
3716                                        DP_DEVICE_SERVICE_IRQ_VECTOR,
3717                                        sink_irq_vector, 1) == 1;
3718 }
3719
3720 static bool
3721 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3722 {
3723         int ret;
3724
3725         ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
3726                                              DP_SINK_COUNT_ESI,
3727                                              sink_irq_vector, 14);
3728         if (ret != 14)
3729                 return false;
3730
3731         return true;
3732 }
3733
3734 static void
3735 intel_dp_handle_test_request(struct intel_dp *intel_dp)
3736 {
3737         /* NAK by default */
3738         drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
3739 }
3740
3741 static int
3742 intel_dp_check_mst_status(struct intel_dp *intel_dp)
3743 {
3744         bool bret;
3745
3746         if (intel_dp->is_mst) {
3747                 u8 esi[16] = { 0 };
3748                 int ret = 0;
3749                 int retry;
3750                 bool handled;
3751                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3752 go_again:
3753                 if (bret == true) {
3754
3755                         /* check link status - esi[10] = 0x200c */
3756                         if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3757                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3758                                 intel_dp_start_link_train(intel_dp);
3759                                 intel_dp_complete_link_train(intel_dp);
3760                                 intel_dp_stop_link_train(intel_dp);
3761                         }
3762
3763                         DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3764                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3765
3766                         if (handled) {
3767                                 for (retry = 0; retry < 3; retry++) {
3768                                         int wret;
3769                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
3770                                                                  DP_SINK_COUNT_ESI+1,
3771                                                                  &esi[1], 3);
3772                                         if (wret == 3) {
3773                                                 break;
3774                                         }
3775                                 }
3776
3777                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3778                                 if (bret == true) {
3779                                         DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3780                                         goto go_again;
3781                                 }
3782                         } else
3783                                 ret = 0;
3784
3785                         return ret;
3786                 } else {
3787                         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3788                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3789                         intel_dp->is_mst = false;
3790                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3791                         /* send a hotplug event */
3792                         drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3793                 }
3794         }
3795         return -EINVAL;
3796 }
3797
3798 /*
3799  * According to DP spec
3800  * 5.1.2:
3801  *  1. Read DPCD
3802  *  2. Configure link according to Receiver Capabilities
3803  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
3804  *  4. Check link status on receipt of hot-plug interrupt
3805  */
3806 void
3807 intel_dp_check_link_status(struct intel_dp *intel_dp)
3808 {
3809         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3810         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
3811         u8 sink_irq_vector;
3812         u8 link_status[DP_LINK_STATUS_SIZE];
3813
3814         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3815
3816         if (!intel_encoder->connectors_active)
3817                 return;
3818
3819         if (WARN_ON(!intel_encoder->base.crtc))
3820                 return;
3821
3822         if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3823                 return;
3824
3825         /* Try to read receiver status if the link appears to be up */
3826         if (!intel_dp_get_link_status(intel_dp, link_status)) {
3827                 return;
3828         }
3829
3830         /* Now read the DPCD to see if it's actually running */
3831         if (!intel_dp_get_dpcd(intel_dp)) {
3832                 return;
3833         }
3834
3835         /* Try to read the source of the interrupt */
3836         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3837             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3838                 /* Clear interrupt source */
3839                 drm_dp_dpcd_writeb(&intel_dp->aux,
3840                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
3841                                    sink_irq_vector);
3842
3843                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3844                         intel_dp_handle_test_request(intel_dp);
3845                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3846                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3847         }
3848
3849         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3850                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3851                               intel_encoder->base.name);
3852                 intel_dp_start_link_train(intel_dp);
3853                 intel_dp_complete_link_train(intel_dp);
3854                 intel_dp_stop_link_train(intel_dp);
3855         }
3856 }
3857
3858 /* XXX this is probably wrong for multiple downstream ports */
3859 static enum drm_connector_status
3860 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
3861 {
3862         uint8_t *dpcd = intel_dp->dpcd;
3863         uint8_t type;
3864
3865         if (!intel_dp_get_dpcd(intel_dp))
3866                 return connector_status_disconnected;
3867
3868         /* if there's no downstream port, we're done */
3869         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
3870                 return connector_status_connected;
3871
3872         /* If we're HPD-aware, SINK_COUNT changes dynamically */
3873         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3874             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
3875                 uint8_t reg;
3876
3877                 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3878                                             &reg, 1) < 0)
3879                         return connector_status_unknown;
3880
3881                 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3882                                               : connector_status_disconnected;
3883         }
3884
3885         /* If no HPD, poke DDC gently */
3886         if (drm_probe_ddc(&intel_dp->aux.ddc))
3887                 return connector_status_connected;
3888
3889         /* Well we tried, say unknown for unreliable port types */
3890         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3891                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3892                 if (type == DP_DS_PORT_TYPE_VGA ||
3893                     type == DP_DS_PORT_TYPE_NON_EDID)
3894                         return connector_status_unknown;
3895         } else {
3896                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3897                         DP_DWN_STRM_PORT_TYPE_MASK;
3898                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3899                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
3900                         return connector_status_unknown;
3901         }
3902
3903         /* Anything else is out of spec, warn and ignore */
3904         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
3905         return connector_status_disconnected;
3906 }
3907
3908 static enum drm_connector_status
3909 edp_detect(struct intel_dp *intel_dp)
3910 {
3911         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3912         enum drm_connector_status status;
3913
3914         status = intel_panel_detect(dev);
3915         if (status == connector_status_unknown)
3916                 status = connector_status_connected;
3917
3918         return status;
3919 }
3920
3921 static enum drm_connector_status
3922 ironlake_dp_detect(struct intel_dp *intel_dp)
3923 {
3924         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3925         struct drm_i915_private *dev_priv = dev->dev_private;
3926         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3927
3928         if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3929                 return connector_status_disconnected;
3930
3931         return intel_dp_detect_dpcd(intel_dp);
3932 }
3933
3934 static int g4x_digital_port_connected(struct drm_device *dev,
3935                                        struct intel_digital_port *intel_dig_port)
3936 {
3937         struct drm_i915_private *dev_priv = dev->dev_private;
3938         uint32_t bit;
3939
3940         if (IS_VALLEYVIEW(dev)) {
3941                 switch (intel_dig_port->port) {
3942                 case PORT_B:
3943                         bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3944                         break;
3945                 case PORT_C:
3946                         bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3947                         break;
3948                 case PORT_D:
3949                         bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3950                         break;
3951                 default:
3952                         return -EINVAL;
3953                 }
3954         } else {
3955                 switch (intel_dig_port->port) {
3956                 case PORT_B:
3957                         bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3958                         break;
3959                 case PORT_C:
3960                         bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3961                         break;
3962                 case PORT_D:
3963                         bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3964                         break;
3965                 default:
3966                         return -EINVAL;
3967                 }
3968         }
3969
3970         if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
3971                 return 0;
3972         return 1;
3973 }
3974
3975 static enum drm_connector_status
3976 g4x_dp_detect(struct intel_dp *intel_dp)
3977 {
3978         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3979         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3980         int ret;
3981
3982         /* Can't disconnect eDP, but you can close the lid... */
3983         if (is_edp(intel_dp)) {
3984                 enum drm_connector_status status;
3985
3986                 status = intel_panel_detect(dev);
3987                 if (status == connector_status_unknown)
3988                         status = connector_status_connected;
3989                 return status;
3990         }
3991
3992         ret = g4x_digital_port_connected(dev, intel_dig_port);
3993         if (ret == -EINVAL)
3994                 return connector_status_unknown;
3995         else if (ret == 0)
3996                 return connector_status_disconnected;
3997
3998         return intel_dp_detect_dpcd(intel_dp);
3999 }
4000
4001 static struct edid *
4002 intel_dp_get_edid(struct intel_dp *intel_dp)
4003 {
4004         struct intel_connector *intel_connector = intel_dp->attached_connector;
4005
4006         /* use cached edid if we have one */
4007         if (intel_connector->edid) {
4008                 /* invalid edid */
4009                 if (IS_ERR(intel_connector->edid))
4010                         return NULL;
4011
4012                 return drm_edid_duplicate(intel_connector->edid);
4013         } else
4014                 return drm_get_edid(&intel_connector->base,
4015                                     &intel_dp->aux.ddc);
4016 }
4017
4018 static void
4019 intel_dp_set_edid(struct intel_dp *intel_dp)
4020 {
4021         struct intel_connector *intel_connector = intel_dp->attached_connector;
4022         struct edid *edid;
4023
4024         edid = intel_dp_get_edid(intel_dp);
4025         intel_connector->detect_edid = edid;
4026
4027         if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4028                 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4029         else
4030                 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4031 }
4032
4033 static void
4034 intel_dp_unset_edid(struct intel_dp *intel_dp)
4035 {
4036         struct intel_connector *intel_connector = intel_dp->attached_connector;
4037
4038         kfree(intel_connector->detect_edid);
4039         intel_connector->detect_edid = NULL;
4040
4041         intel_dp->has_audio = false;
4042 }
4043
4044 static enum intel_display_power_domain
4045 intel_dp_power_get(struct intel_dp *dp)
4046 {
4047         struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4048         enum intel_display_power_domain power_domain;
4049
4050         power_domain = intel_display_port_power_domain(encoder);
4051         intel_display_power_get(to_i915(encoder->base.dev), power_domain);
4052
4053         return power_domain;
4054 }
4055
4056 static void
4057 intel_dp_power_put(struct intel_dp *dp,
4058                    enum intel_display_power_domain power_domain)
4059 {
4060         struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4061         intel_display_power_put(to_i915(encoder->base.dev), power_domain);
4062 }
4063
4064 static enum drm_connector_status
4065 intel_dp_detect(struct drm_connector *connector, bool force)
4066 {
4067         struct intel_dp *intel_dp = intel_attached_dp(connector);
4068         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4069         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4070         struct drm_device *dev = connector->dev;
4071         enum drm_connector_status status;
4072         enum intel_display_power_domain power_domain;
4073         bool ret;
4074
4075         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4076                       connector->base.id, connector->name);
4077         intel_dp_unset_edid(intel_dp);
4078
4079         if (intel_dp->is_mst) {
4080                 /* MST devices are disconnected from a monitor POV */
4081                 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4082                         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4083                 return connector_status_disconnected;
4084         }
4085
4086         power_domain = intel_dp_power_get(intel_dp);
4087
4088         /* Can't disconnect eDP, but you can close the lid... */
4089         if (is_edp(intel_dp))
4090                 status = edp_detect(intel_dp);
4091         else if (HAS_PCH_SPLIT(dev))
4092                 status = ironlake_dp_detect(intel_dp);
4093         else
4094                 status = g4x_dp_detect(intel_dp);
4095         if (status != connector_status_connected)
4096                 goto out;
4097
4098         intel_dp_probe_oui(intel_dp);
4099
4100         ret = intel_dp_probe_mst(intel_dp);
4101         if (ret) {
4102                 /* if we are in MST mode then this connector
4103                    won't appear connected or have anything with EDID on it */
4104                 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4105                         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4106                 status = connector_status_disconnected;
4107                 goto out;
4108         }
4109
4110         intel_dp_set_edid(intel_dp);
4111
4112         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4113                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4114         status = connector_status_connected;
4115
4116 out:
4117         intel_dp_power_put(intel_dp, power_domain);
4118         return status;
4119 }
4120
4121 static void
4122 intel_dp_force(struct drm_connector *connector)
4123 {
4124         struct intel_dp *intel_dp = intel_attached_dp(connector);
4125         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4126         enum intel_display_power_domain power_domain;
4127
4128         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4129                       connector->base.id, connector->name);
4130         intel_dp_unset_edid(intel_dp);
4131
4132         if (connector->status != connector_status_connected)
4133                 return;
4134
4135         power_domain = intel_dp_power_get(intel_dp);
4136
4137         intel_dp_set_edid(intel_dp);
4138
4139         intel_dp_power_put(intel_dp, power_domain);
4140
4141         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4142                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4143 }
4144
4145 static int intel_dp_get_modes(struct drm_connector *connector)
4146 {
4147         struct intel_connector *intel_connector = to_intel_connector(connector);
4148         struct edid *edid;
4149
4150         edid = intel_connector->detect_edid;
4151         if (edid) {
4152                 int ret = intel_connector_update_modes(connector, edid);
4153                 if (ret)
4154                         return ret;
4155         }
4156
4157         /* if eDP has no EDID, fall back to fixed mode */
4158         if (is_edp(intel_attached_dp(connector)) &&
4159             intel_connector->panel.fixed_mode) {
4160                 struct drm_display_mode *mode;
4161
4162                 mode = drm_mode_duplicate(connector->dev,
4163                                           intel_connector->panel.fixed_mode);
4164                 if (mode) {
4165                         drm_mode_probed_add(connector, mode);
4166                         return 1;
4167                 }
4168         }
4169
4170         return 0;
4171 }
4172
4173 static bool
4174 intel_dp_detect_audio(struct drm_connector *connector)
4175 {
4176         bool has_audio = false;
4177         struct edid *edid;
4178
4179         edid = to_intel_connector(connector)->detect_edid;
4180         if (edid)
4181                 has_audio = drm_detect_monitor_audio(edid);
4182
4183         return has_audio;
4184 }
4185
4186 static int
4187 intel_dp_set_property(struct drm_connector *connector,
4188                       struct drm_property *property,
4189                       uint64_t val)
4190 {
4191         struct drm_i915_private *dev_priv = connector->dev->dev_private;
4192         struct intel_connector *intel_connector = to_intel_connector(connector);
4193         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4194         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4195         int ret;
4196
4197         ret = drm_object_property_set_value(&connector->base, property, val);
4198         if (ret)
4199                 return ret;
4200
4201         if (property == dev_priv->force_audio_property) {
4202                 int i = val;
4203                 bool has_audio;
4204
4205                 if (i == intel_dp->force_audio)
4206                         return 0;
4207
4208                 intel_dp->force_audio = i;
4209
4210                 if (i == HDMI_AUDIO_AUTO)
4211                         has_audio = intel_dp_detect_audio(connector);
4212                 else
4213                         has_audio = (i == HDMI_AUDIO_ON);
4214
4215                 if (has_audio == intel_dp->has_audio)
4216                         return 0;
4217
4218                 intel_dp->has_audio = has_audio;
4219                 goto done;
4220         }
4221
4222         if (property == dev_priv->broadcast_rgb_property) {
4223                 bool old_auto = intel_dp->color_range_auto;
4224                 uint32_t old_range = intel_dp->color_range;
4225
4226                 switch (val) {
4227                 case INTEL_BROADCAST_RGB_AUTO:
4228                         intel_dp->color_range_auto = true;
4229                         break;
4230                 case INTEL_BROADCAST_RGB_FULL:
4231                         intel_dp->color_range_auto = false;
4232                         intel_dp->color_range = 0;
4233                         break;
4234                 case INTEL_BROADCAST_RGB_LIMITED:
4235                         intel_dp->color_range_auto = false;
4236                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
4237                         break;
4238                 default:
4239                         return -EINVAL;
4240                 }
4241
4242                 if (old_auto == intel_dp->color_range_auto &&
4243                     old_range == intel_dp->color_range)
4244                         return 0;
4245
4246                 goto done;
4247         }
4248
4249         if (is_edp(intel_dp) &&
4250             property == connector->dev->mode_config.scaling_mode_property) {
4251                 if (val == DRM_MODE_SCALE_NONE) {
4252                         DRM_DEBUG_KMS("no scaling not supported\n");
4253                         return -EINVAL;
4254                 }
4255
4256                 if (intel_connector->panel.fitting_mode == val) {
4257                         /* the eDP scaling property is not changed */
4258                         return 0;
4259                 }
4260                 intel_connector->panel.fitting_mode = val;
4261
4262                 goto done;
4263         }
4264
4265         return -EINVAL;
4266
4267 done:
4268         if (intel_encoder->base.crtc)
4269                 intel_crtc_restore_mode(intel_encoder->base.crtc);
4270
4271         return 0;
4272 }
4273
4274 static void
4275 intel_dp_connector_destroy(struct drm_connector *connector)
4276 {
4277         struct intel_connector *intel_connector = to_intel_connector(connector);
4278
4279         kfree(intel_connector->detect_edid);
4280
4281         if (!IS_ERR_OR_NULL(intel_connector->edid))
4282                 kfree(intel_connector->edid);
4283
4284         /* Can't call is_edp() since the encoder may have been destroyed
4285          * already. */
4286         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4287                 intel_panel_fini(&intel_connector->panel);
4288
4289         drm_connector_cleanup(connector);
4290         kfree(connector);
4291 }
4292
4293 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4294 {
4295         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4296         struct intel_dp *intel_dp = &intel_dig_port->dp;
4297
4298         drm_dp_aux_unregister(&intel_dp->aux);
4299         intel_dp_mst_encoder_cleanup(intel_dig_port);
4300         drm_encoder_cleanup(encoder);
4301         if (is_edp(intel_dp)) {
4302                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4303                 /*
4304                  * vdd might still be enabled do to the delayed vdd off.
4305                  * Make sure vdd is actually turned off here.
4306                  */
4307                 pps_lock(intel_dp);
4308                 edp_panel_vdd_off_sync(intel_dp);
4309                 pps_unlock(intel_dp);
4310
4311                 if (intel_dp->edp_notifier.notifier_call) {
4312                         unregister_reboot_notifier(&intel_dp->edp_notifier);
4313                         intel_dp->edp_notifier.notifier_call = NULL;
4314                 }
4315         }
4316         kfree(intel_dig_port);
4317 }
4318
4319 static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4320 {
4321         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4322
4323         if (!is_edp(intel_dp))
4324                 return;
4325
4326         /*
4327          * vdd might still be enabled do to the delayed vdd off.
4328          * Make sure vdd is actually turned off here.
4329          */
4330         pps_lock(intel_dp);
4331         edp_panel_vdd_off_sync(intel_dp);
4332         pps_unlock(intel_dp);
4333 }
4334
4335 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4336 {
4337         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4338         struct drm_device *dev = intel_dig_port->base.base.dev;
4339         struct drm_i915_private *dev_priv = dev->dev_private;
4340         enum intel_display_power_domain power_domain;
4341
4342         lockdep_assert_held(&dev_priv->pps_mutex);
4343
4344         if (!edp_have_panel_vdd(intel_dp))
4345                 return;
4346
4347         /*
4348          * The VDD bit needs a power domain reference, so if the bit is
4349          * already enabled when we boot or resume, grab this reference and
4350          * schedule a vdd off, so we don't hold on to the reference
4351          * indefinitely.
4352          */
4353         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4354         power_domain = intel_display_port_power_domain(&intel_dig_port->base);
4355         intel_display_power_get(dev_priv, power_domain);
4356
4357         edp_panel_vdd_schedule_off(intel_dp);
4358 }
4359
4360 static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4361 {
4362         struct intel_dp *intel_dp;
4363
4364         if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4365                 return;
4366
4367         intel_dp = enc_to_intel_dp(encoder);
4368
4369         pps_lock(intel_dp);
4370
4371         /*
4372          * Read out the current power sequencer assignment,
4373          * in case the BIOS did something with it.
4374          */
4375         if (IS_VALLEYVIEW(encoder->dev))
4376                 vlv_initial_power_sequencer_setup(intel_dp);
4377
4378         intel_edp_panel_vdd_sanitize(intel_dp);
4379
4380         pps_unlock(intel_dp);
4381 }
4382
4383 static const struct drm_connector_funcs intel_dp_connector_funcs = {
4384         .dpms = intel_connector_dpms,
4385         .detect = intel_dp_detect,
4386         .force = intel_dp_force,
4387         .fill_modes = drm_helper_probe_single_connector_modes,
4388         .set_property = intel_dp_set_property,
4389         .destroy = intel_dp_connector_destroy,
4390 };
4391
4392 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4393         .get_modes = intel_dp_get_modes,
4394         .mode_valid = intel_dp_mode_valid,
4395         .best_encoder = intel_best_encoder,
4396 };
4397
4398 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
4399         .reset = intel_dp_encoder_reset,
4400         .destroy = intel_dp_encoder_destroy,
4401 };
4402
4403 void
4404 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
4405 {
4406         return;
4407 }
4408
4409 bool
4410 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4411 {
4412         struct intel_dp *intel_dp = &intel_dig_port->dp;
4413         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4414         struct drm_device *dev = intel_dig_port->base.base.dev;
4415         struct drm_i915_private *dev_priv = dev->dev_private;
4416         enum intel_display_power_domain power_domain;
4417         bool ret = true;
4418
4419         if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4420                 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
4421
4422         DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4423                       port_name(intel_dig_port->port),
4424                       long_hpd ? "long" : "short");
4425
4426         power_domain = intel_display_port_power_domain(intel_encoder);
4427         intel_display_power_get(dev_priv, power_domain);
4428
4429         if (long_hpd) {
4430
4431                 if (HAS_PCH_SPLIT(dev)) {
4432                         if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4433                                 goto mst_fail;
4434                 } else {
4435                         if (g4x_digital_port_connected(dev, intel_dig_port) != 1)
4436                                 goto mst_fail;
4437                 }
4438
4439                 if (!intel_dp_get_dpcd(intel_dp)) {
4440                         goto mst_fail;
4441                 }
4442
4443                 intel_dp_probe_oui(intel_dp);
4444
4445                 if (!intel_dp_probe_mst(intel_dp))
4446                         goto mst_fail;
4447
4448         } else {
4449                 if (intel_dp->is_mst) {
4450                         if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
4451                                 goto mst_fail;
4452                 }
4453
4454                 if (!intel_dp->is_mst) {
4455                         /*
4456                          * we'll check the link status via the normal hot plug path later -
4457                          * but for short hpds we should check it now
4458                          */
4459                         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4460                         intel_dp_check_link_status(intel_dp);
4461                         drm_modeset_unlock(&dev->mode_config.connection_mutex);
4462                 }
4463         }
4464         ret = false;
4465         goto put_power;
4466 mst_fail:
4467         /* if we were in MST mode, and device is not there get out of MST mode */
4468         if (intel_dp->is_mst) {
4469                 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4470                 intel_dp->is_mst = false;
4471                 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4472         }
4473 put_power:
4474         intel_display_power_put(dev_priv, power_domain);
4475
4476         return ret;
4477 }
4478
4479 /* Return which DP Port should be selected for Transcoder DP control */
4480 int
4481 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4482 {
4483         struct drm_device *dev = crtc->dev;
4484         struct intel_encoder *intel_encoder;
4485         struct intel_dp *intel_dp;
4486
4487         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4488                 intel_dp = enc_to_intel_dp(&intel_encoder->base);
4489
4490                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4491                     intel_encoder->type == INTEL_OUTPUT_EDP)
4492                         return intel_dp->output_reg;
4493         }
4494
4495         return -1;
4496 }
4497
4498 /* check the VBT to see whether the eDP is on DP-D port */
4499 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
4500 {
4501         struct drm_i915_private *dev_priv = dev->dev_private;
4502         union child_device_config *p_child;
4503         int i;
4504         static const short port_mapping[] = {
4505                 [PORT_B] = PORT_IDPB,
4506                 [PORT_C] = PORT_IDPC,
4507                 [PORT_D] = PORT_IDPD,
4508         };
4509
4510         if (port == PORT_A)
4511                 return true;
4512
4513         if (!dev_priv->vbt.child_dev_num)
4514                 return false;
4515
4516         for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4517                 p_child = dev_priv->vbt.child_dev + i;
4518
4519                 if (p_child->common.dvo_port == port_mapping[port] &&
4520                     (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4521                     (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
4522                         return true;
4523         }
4524         return false;
4525 }
4526
4527 void
4528 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4529 {
4530         struct intel_connector *intel_connector = to_intel_connector(connector);
4531
4532         intel_attach_force_audio_property(connector);
4533         intel_attach_broadcast_rgb_property(connector);
4534         intel_dp->color_range_auto = true;
4535
4536         if (is_edp(intel_dp)) {
4537                 drm_mode_create_scaling_mode_property(connector->dev);
4538                 drm_object_attach_property(
4539                         &connector->base,
4540                         connector->dev->mode_config.scaling_mode_property,
4541                         DRM_MODE_SCALE_ASPECT);
4542                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
4543         }
4544 }
4545
4546 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4547 {
4548         intel_dp->last_power_cycle = jiffies;
4549         intel_dp->last_power_on = jiffies;
4550         intel_dp->last_backlight_off = jiffies;
4551 }
4552
4553 static void
4554 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
4555                                     struct intel_dp *intel_dp)
4556 {
4557         struct drm_i915_private *dev_priv = dev->dev_private;
4558         struct edp_power_seq cur, vbt, spec,
4559                 *final = &intel_dp->pps_delays;
4560         u32 pp_on, pp_off, pp_div, pp;
4561         int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
4562
4563         lockdep_assert_held(&dev_priv->pps_mutex);
4564
4565         /* already initialized? */
4566         if (final->t11_t12 != 0)
4567                 return;
4568
4569         if (HAS_PCH_SPLIT(dev)) {
4570                 pp_ctrl_reg = PCH_PP_CONTROL;
4571                 pp_on_reg = PCH_PP_ON_DELAYS;
4572                 pp_off_reg = PCH_PP_OFF_DELAYS;
4573                 pp_div_reg = PCH_PP_DIVISOR;
4574         } else {
4575                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4576
4577                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4578                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4579                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4580                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
4581         }
4582
4583         /* Workaround: Need to write PP_CONTROL with the unlock key as
4584          * the very first thing. */
4585         pp = ironlake_get_pp_control(intel_dp);
4586         I915_WRITE(pp_ctrl_reg, pp);
4587
4588         pp_on = I915_READ(pp_on_reg);
4589         pp_off = I915_READ(pp_off_reg);
4590         pp_div = I915_READ(pp_div_reg);
4591
4592         /* Pull timing values out of registers */
4593         cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4594                 PANEL_POWER_UP_DELAY_SHIFT;
4595
4596         cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4597                 PANEL_LIGHT_ON_DELAY_SHIFT;
4598
4599         cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4600                 PANEL_LIGHT_OFF_DELAY_SHIFT;
4601
4602         cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4603                 PANEL_POWER_DOWN_DELAY_SHIFT;
4604
4605         cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4606                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4607
4608         DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4609                       cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4610
4611         vbt = dev_priv->vbt.edp_pps;
4612
4613         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4614          * our hw here, which are all in 100usec. */
4615         spec.t1_t3 = 210 * 10;
4616         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4617         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4618         spec.t10 = 500 * 10;
4619         /* This one is special and actually in units of 100ms, but zero
4620          * based in the hw (so we need to add 100 ms). But the sw vbt
4621          * table multiplies it with 1000 to make it in units of 100usec,
4622          * too. */
4623         spec.t11_t12 = (510 + 100) * 10;
4624
4625         DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4626                       vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4627
4628         /* Use the max of the register settings and vbt. If both are
4629          * unset, fall back to the spec limits. */
4630 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
4631                                        spec.field : \
4632                                        max(cur.field, vbt.field))
4633         assign_final(t1_t3);
4634         assign_final(t8);
4635         assign_final(t9);
4636         assign_final(t10);
4637         assign_final(t11_t12);
4638 #undef assign_final
4639
4640 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
4641         intel_dp->panel_power_up_delay = get_delay(t1_t3);
4642         intel_dp->backlight_on_delay = get_delay(t8);
4643         intel_dp->backlight_off_delay = get_delay(t9);
4644         intel_dp->panel_power_down_delay = get_delay(t10);
4645         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4646 #undef get_delay
4647
4648         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4649                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4650                       intel_dp->panel_power_cycle_delay);
4651
4652         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4653                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4654 }
4655
4656 static void
4657 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4658                                               struct intel_dp *intel_dp)
4659 {
4660         struct drm_i915_private *dev_priv = dev->dev_private;
4661         u32 pp_on, pp_off, pp_div, port_sel = 0;
4662         int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4663         int pp_on_reg, pp_off_reg, pp_div_reg;
4664         enum port port = dp_to_dig_port(intel_dp)->port;
4665         const struct edp_power_seq *seq = &intel_dp->pps_delays;
4666
4667         lockdep_assert_held(&dev_priv->pps_mutex);
4668
4669         if (HAS_PCH_SPLIT(dev)) {
4670                 pp_on_reg = PCH_PP_ON_DELAYS;
4671                 pp_off_reg = PCH_PP_OFF_DELAYS;
4672                 pp_div_reg = PCH_PP_DIVISOR;
4673         } else {
4674                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4675
4676                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4677                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4678                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
4679         }
4680
4681         /*
4682          * And finally store the new values in the power sequencer. The
4683          * backlight delays are set to 1 because we do manual waits on them. For
4684          * T8, even BSpec recommends doing it. For T9, if we don't do this,
4685          * we'll end up waiting for the backlight off delay twice: once when we
4686          * do the manual sleep, and once when we disable the panel and wait for
4687          * the PP_STATUS bit to become zero.
4688          */
4689         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
4690                 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4691         pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
4692                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
4693         /* Compute the divisor for the pp clock, simply match the Bspec
4694          * formula. */
4695         pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
4696         pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
4697                         << PANEL_POWER_CYCLE_DELAY_SHIFT);
4698
4699         /* Haswell doesn't have any port selection bits for the panel
4700          * power sequencer any more. */
4701         if (IS_VALLEYVIEW(dev)) {
4702                 port_sel = PANEL_PORT_SELECT_VLV(port);
4703         } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
4704                 if (port == PORT_A)
4705                         port_sel = PANEL_PORT_SELECT_DPA;
4706                 else
4707                         port_sel = PANEL_PORT_SELECT_DPD;
4708         }
4709
4710         pp_on |= port_sel;
4711
4712         I915_WRITE(pp_on_reg, pp_on);
4713         I915_WRITE(pp_off_reg, pp_off);
4714         I915_WRITE(pp_div_reg, pp_div);
4715
4716         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
4717                       I915_READ(pp_on_reg),
4718                       I915_READ(pp_off_reg),
4719                       I915_READ(pp_div_reg));
4720 }
4721
4722 void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4723 {
4724         struct drm_i915_private *dev_priv = dev->dev_private;
4725         struct intel_encoder *encoder;
4726         struct intel_dp *intel_dp = NULL;
4727         struct intel_crtc_config *config = NULL;
4728         struct intel_crtc *intel_crtc = NULL;
4729         struct intel_connector *intel_connector = dev_priv->drrs.connector;
4730         u32 reg, val;
4731         enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4732
4733         if (refresh_rate <= 0) {
4734                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4735                 return;
4736         }
4737
4738         if (intel_connector == NULL) {
4739                 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4740                 return;
4741         }
4742
4743         /*
4744          * FIXME: This needs proper synchronization with psr state. But really
4745          * hard to tell without seeing the user of this function of this code.
4746          * Check locking and ordering once that lands.
4747          */
4748         if (INTEL_INFO(dev)->gen < 8 && intel_psr_is_enabled(dev)) {
4749                 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4750                 return;
4751         }
4752
4753         encoder = intel_attached_encoder(&intel_connector->base);
4754         intel_dp = enc_to_intel_dp(&encoder->base);
4755         intel_crtc = encoder->new_crtc;
4756
4757         if (!intel_crtc) {
4758                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4759                 return;
4760         }
4761
4762         config = &intel_crtc->config;
4763
4764         if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4765                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4766                 return;
4767         }
4768
4769         if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
4770                 index = DRRS_LOW_RR;
4771
4772         if (index == intel_dp->drrs_state.refresh_rate_type) {
4773                 DRM_DEBUG_KMS(
4774                         "DRRS requested for previously set RR...ignoring\n");
4775                 return;
4776         }
4777
4778         if (!intel_crtc->active) {
4779                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4780                 return;
4781         }
4782
4783         if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4784                 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4785                 val = I915_READ(reg);
4786                 if (index > DRRS_HIGH_RR) {
4787                         val |= PIPECONF_EDP_RR_MODE_SWITCH;
4788                         intel_dp_set_m_n(intel_crtc);
4789                 } else {
4790                         val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4791                 }
4792                 I915_WRITE(reg, val);
4793         }
4794
4795         /*
4796          * mutex taken to ensure that there is no race between differnt
4797          * drrs calls trying to update refresh rate. This scenario may occur
4798          * in future when idleness detection based DRRS in kernel and
4799          * possible calls from user space to set differnt RR are made.
4800          */
4801
4802         mutex_lock(&intel_dp->drrs_state.mutex);
4803
4804         intel_dp->drrs_state.refresh_rate_type = index;
4805
4806         mutex_unlock(&intel_dp->drrs_state.mutex);
4807
4808         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4809 }
4810
4811 static struct drm_display_mode *
4812 intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4813                         struct intel_connector *intel_connector,
4814                         struct drm_display_mode *fixed_mode)
4815 {
4816         struct drm_connector *connector = &intel_connector->base;
4817         struct intel_dp *intel_dp = &intel_dig_port->dp;
4818         struct drm_device *dev = intel_dig_port->base.base.dev;
4819         struct drm_i915_private *dev_priv = dev->dev_private;
4820         struct drm_display_mode *downclock_mode = NULL;
4821
4822         if (INTEL_INFO(dev)->gen <= 6) {
4823                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4824                 return NULL;
4825         }
4826
4827         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4828                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4829                 return NULL;
4830         }
4831
4832         downclock_mode = intel_find_panel_downclock
4833                                         (dev, fixed_mode, connector);
4834
4835         if (!downclock_mode) {
4836                 DRM_DEBUG_KMS("DRRS not supported\n");
4837                 return NULL;
4838         }
4839
4840         dev_priv->drrs.connector = intel_connector;
4841
4842         mutex_init(&intel_dp->drrs_state.mutex);
4843
4844         intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4845
4846         intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4847         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4848         return downclock_mode;
4849 }
4850
4851 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
4852                                      struct intel_connector *intel_connector)
4853 {
4854         struct drm_connector *connector = &intel_connector->base;
4855         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4856         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4857         struct drm_device *dev = intel_encoder->base.dev;
4858         struct drm_i915_private *dev_priv = dev->dev_private;
4859         struct drm_display_mode *fixed_mode = NULL;
4860         struct drm_display_mode *downclock_mode = NULL;
4861         bool has_dpcd;
4862         struct drm_display_mode *scan;
4863         struct edid *edid;
4864         enum pipe pipe = INVALID_PIPE;
4865
4866         intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
4867
4868         if (!is_edp(intel_dp))
4869                 return true;
4870
4871         pps_lock(intel_dp);
4872         intel_edp_panel_vdd_sanitize(intel_dp);
4873         pps_unlock(intel_dp);
4874
4875         /* Cache DPCD and EDID for edp. */
4876         has_dpcd = intel_dp_get_dpcd(intel_dp);
4877
4878         if (has_dpcd) {
4879                 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4880                         dev_priv->no_aux_handshake =
4881                                 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4882                                 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4883         } else {
4884                 /* if this fails, presume the device is a ghost */
4885                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
4886                 return false;
4887         }
4888
4889         /* We now know it's not a ghost, init power sequence regs. */
4890         pps_lock(intel_dp);
4891         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
4892         pps_unlock(intel_dp);
4893
4894         mutex_lock(&dev->mode_config.mutex);
4895         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
4896         if (edid) {
4897                 if (drm_add_edid_modes(connector, edid)) {
4898                         drm_mode_connector_update_edid_property(connector,
4899                                                                 edid);
4900                         drm_edid_to_eld(connector, edid);
4901                 } else {
4902                         kfree(edid);
4903                         edid = ERR_PTR(-EINVAL);
4904                 }
4905         } else {
4906                 edid = ERR_PTR(-ENOENT);
4907         }
4908         intel_connector->edid = edid;
4909
4910         /* prefer fixed mode from EDID if available */
4911         list_for_each_entry(scan, &connector->probed_modes, head) {
4912                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
4913                         fixed_mode = drm_mode_duplicate(dev, scan);
4914                         downclock_mode = intel_dp_drrs_init(
4915                                                 intel_dig_port,
4916                                                 intel_connector, fixed_mode);
4917                         break;
4918                 }
4919         }
4920
4921         /* fallback to VBT if available for eDP */
4922         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
4923                 fixed_mode = drm_mode_duplicate(dev,
4924                                         dev_priv->vbt.lfp_lvds_vbt_mode);
4925                 if (fixed_mode)
4926                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
4927         }
4928         mutex_unlock(&dev->mode_config.mutex);
4929
4930         if (IS_VALLEYVIEW(dev)) {
4931                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
4932                 register_reboot_notifier(&intel_dp->edp_notifier);
4933
4934                 /*
4935                  * Figure out the current pipe for the initial backlight setup.
4936                  * If the current pipe isn't valid, try the PPS pipe, and if that
4937                  * fails just assume pipe A.
4938                  */
4939                 if (IS_CHERRYVIEW(dev))
4940                         pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
4941                 else
4942                         pipe = PORT_TO_PIPE(intel_dp->DP);
4943
4944                 if (pipe != PIPE_A && pipe != PIPE_B)
4945                         pipe = intel_dp->pps_pipe;
4946
4947                 if (pipe != PIPE_A && pipe != PIPE_B)
4948                         pipe = PIPE_A;
4949
4950                 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
4951                               pipe_name(pipe));
4952         }
4953
4954         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
4955         intel_connector->panel.backlight_power = intel_edp_backlight_power;
4956         intel_panel_setup_backlight(connector, pipe);
4957
4958         return true;
4959 }
4960
4961 bool
4962 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
4963                         struct intel_connector *intel_connector)
4964 {
4965         struct drm_connector *connector = &intel_connector->base;
4966         struct intel_dp *intel_dp = &intel_dig_port->dp;
4967         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4968         struct drm_device *dev = intel_encoder->base.dev;
4969         struct drm_i915_private *dev_priv = dev->dev_private;
4970         enum port port = intel_dig_port->port;
4971         int type;
4972
4973         intel_dp->pps_pipe = INVALID_PIPE;
4974
4975         /* intel_dp vfuncs */
4976         if (INTEL_INFO(dev)->gen >= 9)
4977                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
4978         else if (IS_VALLEYVIEW(dev))
4979                 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
4980         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4981                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
4982         else if (HAS_PCH_SPLIT(dev))
4983                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
4984         else
4985                 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
4986
4987         if (INTEL_INFO(dev)->gen >= 9)
4988                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
4989         else
4990                 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
4991
4992         /* Preserve the current hw state. */
4993         intel_dp->DP = I915_READ(intel_dp->output_reg);
4994         intel_dp->attached_connector = intel_connector;
4995
4996         if (intel_dp_is_edp(dev, port))
4997                 type = DRM_MODE_CONNECTOR_eDP;
4998         else
4999                 type = DRM_MODE_CONNECTOR_DisplayPort;
5000
5001         /*
5002          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5003          * for DP the encoder type can be set by the caller to
5004          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5005          */
5006         if (type == DRM_MODE_CONNECTOR_eDP)
5007                 intel_encoder->type = INTEL_OUTPUT_EDP;
5008
5009         /* eDP only on port B and/or C on vlv/chv */
5010         if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) &&
5011                     port != PORT_B && port != PORT_C))
5012                 return false;
5013
5014         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5015                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5016                         port_name(port));
5017
5018         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5019         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5020
5021         connector->interlace_allowed = true;
5022         connector->doublescan_allowed = 0;
5023
5024         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
5025                           edp_panel_vdd_work);
5026
5027         intel_connector_attach_encoder(intel_connector, intel_encoder);
5028         drm_connector_register(connector);
5029
5030         if (HAS_DDI(dev))
5031                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5032         else
5033                 intel_connector->get_hw_state = intel_connector_get_hw_state;
5034         intel_connector->unregister = intel_dp_connector_unregister;
5035
5036         /* Set up the hotplug pin. */
5037         switch (port) {
5038         case PORT_A:
5039                 intel_encoder->hpd_pin = HPD_PORT_A;
5040                 break;
5041         case PORT_B:
5042                 intel_encoder->hpd_pin = HPD_PORT_B;
5043                 break;
5044         case PORT_C:
5045                 intel_encoder->hpd_pin = HPD_PORT_C;
5046                 break;
5047         case PORT_D:
5048                 intel_encoder->hpd_pin = HPD_PORT_D;
5049                 break;
5050         default:
5051                 BUG();
5052         }
5053
5054         if (is_edp(intel_dp)) {
5055                 pps_lock(intel_dp);
5056                 intel_dp_init_panel_power_timestamps(intel_dp);
5057                 if (IS_VALLEYVIEW(dev))
5058                         vlv_initial_power_sequencer_setup(intel_dp);
5059                 else
5060                         intel_dp_init_panel_power_sequencer(dev, intel_dp);
5061                 pps_unlock(intel_dp);
5062         }
5063
5064         intel_dp_aux_init(intel_dp, intel_connector);
5065
5066         /* init MST on ports that can support it */
5067         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5068                 if (port == PORT_B || port == PORT_C || port == PORT_D) {
5069                         intel_dp_mst_encoder_init(intel_dig_port,
5070                                                   intel_connector->base.base.id);
5071                 }
5072         }
5073
5074         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
5075                 drm_dp_aux_unregister(&intel_dp->aux);
5076                 if (is_edp(intel_dp)) {
5077                         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5078                         /*
5079                          * vdd might still be enabled do to the delayed vdd off.
5080                          * Make sure vdd is actually turned off here.
5081                          */
5082                         pps_lock(intel_dp);
5083                         edp_panel_vdd_off_sync(intel_dp);
5084                         pps_unlock(intel_dp);
5085                 }
5086                 drm_connector_unregister(connector);
5087                 drm_connector_cleanup(connector);
5088                 return false;
5089         }
5090
5091         intel_dp_add_properties(intel_dp, connector);
5092
5093         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5094          * 0xd.  Failure to do so will result in spurious interrupts being
5095          * generated on the port when a cable is not attached.
5096          */
5097         if (IS_G4X(dev) && !IS_GM45(dev)) {
5098                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5099                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5100         }
5101
5102         return true;
5103 }
5104
5105 void
5106 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
5107 {
5108         struct drm_i915_private *dev_priv = dev->dev_private;
5109         struct intel_digital_port *intel_dig_port;
5110         struct intel_encoder *intel_encoder;
5111         struct drm_encoder *encoder;
5112         struct intel_connector *intel_connector;
5113
5114         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
5115         if (!intel_dig_port)
5116                 return;
5117
5118         intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
5119         if (!intel_connector) {
5120                 kfree(intel_dig_port);
5121                 return;
5122         }
5123
5124         intel_encoder = &intel_dig_port->base;
5125         encoder = &intel_encoder->base;
5126
5127         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5128                          DRM_MODE_ENCODER_TMDS);
5129
5130         intel_encoder->compute_config = intel_dp_compute_config;
5131         intel_encoder->disable = intel_disable_dp;
5132         intel_encoder->get_hw_state = intel_dp_get_hw_state;
5133         intel_encoder->get_config = intel_dp_get_config;
5134         intel_encoder->suspend = intel_dp_encoder_suspend;
5135         if (IS_CHERRYVIEW(dev)) {
5136                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
5137                 intel_encoder->pre_enable = chv_pre_enable_dp;
5138                 intel_encoder->enable = vlv_enable_dp;
5139                 intel_encoder->post_disable = chv_post_disable_dp;
5140         } else if (IS_VALLEYVIEW(dev)) {
5141                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
5142                 intel_encoder->pre_enable = vlv_pre_enable_dp;
5143                 intel_encoder->enable = vlv_enable_dp;
5144                 intel_encoder->post_disable = vlv_post_disable_dp;
5145         } else {
5146                 intel_encoder->pre_enable = g4x_pre_enable_dp;
5147                 intel_encoder->enable = g4x_enable_dp;
5148                 if (INTEL_INFO(dev)->gen >= 5)
5149                         intel_encoder->post_disable = ilk_post_disable_dp;
5150         }
5151
5152         intel_dig_port->port = port;
5153         intel_dig_port->dp.output_reg = output_reg;
5154
5155         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
5156         if (IS_CHERRYVIEW(dev)) {
5157                 if (port == PORT_D)
5158                         intel_encoder->crtc_mask = 1 << 2;
5159                 else
5160                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5161         } else {
5162                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5163         }
5164         intel_encoder->cloneable = 0;
5165         intel_encoder->hot_plug = intel_dp_hot_plug;
5166
5167         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5168         dev_priv->hpd_irq_port[port] = intel_dig_port;
5169
5170         if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
5171                 drm_encoder_cleanup(encoder);
5172                 kfree(intel_dig_port);
5173                 kfree(intel_connector);
5174         }
5175 }
5176
5177 void intel_dp_mst_suspend(struct drm_device *dev)
5178 {
5179         struct drm_i915_private *dev_priv = dev->dev_private;
5180         int i;
5181
5182         /* disable MST */
5183         for (i = 0; i < I915_MAX_PORTS; i++) {
5184                 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5185                 if (!intel_dig_port)
5186                         continue;
5187
5188                 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5189                         if (!intel_dig_port->dp.can_mst)
5190                                 continue;
5191                         if (intel_dig_port->dp.is_mst)
5192                                 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5193                 }
5194         }
5195 }
5196
5197 void intel_dp_mst_resume(struct drm_device *dev)
5198 {
5199         struct drm_i915_private *dev_priv = dev->dev_private;
5200         int i;
5201
5202         for (i = 0; i < I915_MAX_PORTS; i++) {
5203                 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5204                 if (!intel_dig_port)
5205                         continue;
5206                 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5207                         int ret;
5208
5209                         if (!intel_dig_port->dp.can_mst)
5210                                 continue;
5211
5212                         ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5213                         if (ret != 0) {
5214                                 intel_dp_check_mst_status(&intel_dig_port->dp);
5215                         }
5216                 }
5217         }
5218 }