2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
39 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
46 static const struct dp_link_dpll gen4_dpll[] = {
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
53 static const struct dp_link_dpll pch_dpll[] = {
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
60 static const struct dp_link_dpll vlv_dpll[] = {
62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
68 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
69 * @intel_dp: DP struct
71 * If a CPU or PCH DP output is attached to an eDP panel, this function
72 * will return true, and false otherwise.
74 static bool is_edp(struct intel_dp *intel_dp)
76 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
78 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
81 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
83 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
85 return intel_dig_port->base.base.dev;
88 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
90 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
93 static void intel_dp_link_down(struct intel_dp *intel_dp);
94 static bool _edp_panel_vdd_on(struct intel_dp *intel_dp);
95 static void edp_panel_vdd_on(struct intel_dp *intel_dp);
96 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
99 intel_dp_max_link_bw(struct intel_dp *intel_dp)
101 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
102 struct drm_device *dev = intel_dp->attached_connector->base.dev;
104 switch (max_link_bw) {
105 case DP_LINK_BW_1_62:
108 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
109 if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) &&
110 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
111 max_link_bw = DP_LINK_BW_5_4;
113 max_link_bw = DP_LINK_BW_2_7;
116 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
118 max_link_bw = DP_LINK_BW_1_62;
125 * The units on the numbers in the next two are... bizarre. Examples will
126 * make it clearer; this one parallels an example in the eDP spec.
128 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
130 * 270000 * 1 * 8 / 10 == 216000
132 * The actual data capacity of that configuration is 2.16Gbit/s, so the
133 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
134 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
135 * 119000. At 18bpp that's 2142000 kilobits per second.
137 * Thus the strange-looking division by 10 in intel_dp_link_required, to
138 * get the result in decakilobits instead of kilobits.
142 intel_dp_link_required(int pixel_clock, int bpp)
144 return (pixel_clock * bpp + 9) / 10;
148 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
150 return (max_link_clock * max_lanes * 8) / 10;
153 static enum drm_mode_status
154 intel_dp_mode_valid(struct drm_connector *connector,
155 struct drm_display_mode *mode)
157 struct intel_dp *intel_dp = intel_attached_dp(connector);
158 struct intel_connector *intel_connector = to_intel_connector(connector);
159 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
160 int target_clock = mode->clock;
161 int max_rate, mode_rate, max_lanes, max_link_clock;
163 if (is_edp(intel_dp) && fixed_mode) {
164 if (mode->hdisplay > fixed_mode->hdisplay)
167 if (mode->vdisplay > fixed_mode->vdisplay)
170 target_clock = fixed_mode->clock;
173 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
174 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
176 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
177 mode_rate = intel_dp_link_required(target_clock, 18);
179 if (mode_rate > max_rate)
180 return MODE_CLOCK_HIGH;
182 if (mode->clock < 10000)
183 return MODE_CLOCK_LOW;
185 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
186 return MODE_H_ILLEGAL;
192 pack_aux(uint8_t *src, int src_bytes)
199 for (i = 0; i < src_bytes; i++)
200 v |= ((uint32_t) src[i]) << ((3-i) * 8);
205 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
210 for (i = 0; i < dst_bytes; i++)
211 dst[i] = src >> ((3-i) * 8);
214 /* hrawclock is 1/4 the FSB frequency */
216 intel_hrawclk(struct drm_device *dev)
218 struct drm_i915_private *dev_priv = dev->dev_private;
221 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
222 if (IS_VALLEYVIEW(dev))
225 clkcfg = I915_READ(CLKCFG);
226 switch (clkcfg & CLKCFG_FSB_MASK) {
235 case CLKCFG_FSB_1067:
237 case CLKCFG_FSB_1333:
239 /* these two are just a guess; one of them might be right */
240 case CLKCFG_FSB_1600:
241 case CLKCFG_FSB_1600_ALT:
249 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
250 struct intel_dp *intel_dp,
251 struct edp_power_seq *out);
253 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
254 struct intel_dp *intel_dp,
255 struct edp_power_seq *out);
258 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
260 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
261 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
262 struct drm_device *dev = intel_dig_port->base.base.dev;
263 struct drm_i915_private *dev_priv = dev->dev_private;
264 enum port port = intel_dig_port->port;
267 /* modeset should have pipe */
269 return to_intel_crtc(crtc)->pipe;
271 /* init time, try to find a pipe with this port selected */
272 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
273 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
274 PANEL_PORT_SELECT_MASK;
275 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
277 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
285 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
287 struct drm_device *dev = intel_dp_to_dev(intel_dp);
289 if (HAS_PCH_SPLIT(dev))
290 return PCH_PP_CONTROL;
292 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
295 static u32 _pp_stat_reg(struct intel_dp *intel_dp)
297 struct drm_device *dev = intel_dp_to_dev(intel_dp);
299 if (HAS_PCH_SPLIT(dev))
300 return PCH_PP_STATUS;
302 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
305 static bool edp_have_panel_power(struct intel_dp *intel_dp)
307 struct drm_device *dev = intel_dp_to_dev(intel_dp);
308 struct drm_i915_private *dev_priv = dev->dev_private;
310 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
313 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
315 struct drm_device *dev = intel_dp_to_dev(intel_dp);
316 struct drm_i915_private *dev_priv = dev->dev_private;
318 return (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
322 intel_dp_check_edp(struct intel_dp *intel_dp)
324 struct drm_device *dev = intel_dp_to_dev(intel_dp);
325 struct drm_i915_private *dev_priv = dev->dev_private;
327 if (!is_edp(intel_dp))
330 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
331 WARN(1, "eDP powered off while attempting aux channel communication.\n");
332 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
333 I915_READ(_pp_stat_reg(intel_dp)),
334 I915_READ(_pp_ctrl_reg(intel_dp)));
339 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
341 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
342 struct drm_device *dev = intel_dig_port->base.base.dev;
343 struct drm_i915_private *dev_priv = dev->dev_private;
344 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
348 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
350 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
351 msecs_to_jiffies_timeout(10));
353 done = wait_for_atomic(C, 10) == 0;
355 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
362 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
364 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
365 struct drm_device *dev = intel_dig_port->base.base.dev;
368 * The clock divider is based off the hrawclk, and would like to run at
369 * 2MHz. So, take the hrawclk value and divide by 2 and use that
371 return index ? 0 : intel_hrawclk(dev) / 2;
374 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
376 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
377 struct drm_device *dev = intel_dig_port->base.base.dev;
382 if (intel_dig_port->port == PORT_A) {
383 if (IS_GEN6(dev) || IS_GEN7(dev))
384 return 200; /* SNB & IVB eDP input clock at 400Mhz */
386 return 225; /* eDP input clock at 450Mhz */
388 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
392 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
394 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
395 struct drm_device *dev = intel_dig_port->base.base.dev;
396 struct drm_i915_private *dev_priv = dev->dev_private;
398 if (intel_dig_port->port == PORT_A) {
401 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
402 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
403 /* Workaround for non-ULT HSW */
410 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
414 static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
416 return index ? 0 : 100;
419 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
422 uint32_t aux_clock_divider)
424 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
425 struct drm_device *dev = intel_dig_port->base.base.dev;
426 uint32_t precharge, timeout;
433 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
434 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
436 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
438 return DP_AUX_CH_CTL_SEND_BUSY |
440 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
441 DP_AUX_CH_CTL_TIME_OUT_ERROR |
443 DP_AUX_CH_CTL_RECEIVE_ERROR |
444 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
445 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
446 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
450 intel_dp_aux_ch(struct intel_dp *intel_dp,
451 uint8_t *send, int send_bytes,
452 uint8_t *recv, int recv_size)
454 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
455 struct drm_device *dev = intel_dig_port->base.base.dev;
456 struct drm_i915_private *dev_priv = dev->dev_private;
457 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
458 uint32_t ch_data = ch_ctl + 4;
459 uint32_t aux_clock_divider;
460 int i, ret, recv_bytes;
463 bool has_aux_irq = HAS_AUX_IRQ(dev);
466 vdd = _edp_panel_vdd_on(intel_dp);
468 /* dp aux is extremely sensitive to irq latency, hence request the
469 * lowest possible wakeup latency and so prevent the cpu from going into
472 pm_qos_update_request(&dev_priv->pm_qos, 0);
474 intel_dp_check_edp(intel_dp);
476 intel_aux_display_runtime_get(dev_priv);
478 /* Try to wait for any previous AUX channel activity */
479 for (try = 0; try < 3; try++) {
480 status = I915_READ_NOTRACE(ch_ctl);
481 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
487 WARN(1, "dp_aux_ch not started status 0x%08x\n",
493 /* Only 5 data registers! */
494 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
499 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
500 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
505 /* Must try at least 3 times according to DP spec */
506 for (try = 0; try < 5; try++) {
507 /* Load the send data into the aux channel data registers */
508 for (i = 0; i < send_bytes; i += 4)
509 I915_WRITE(ch_data + i,
510 pack_aux(send + i, send_bytes - i));
512 /* Send the command and wait for it to complete */
513 I915_WRITE(ch_ctl, send_ctl);
515 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
517 /* Clear done status and any errors */
521 DP_AUX_CH_CTL_TIME_OUT_ERROR |
522 DP_AUX_CH_CTL_RECEIVE_ERROR);
524 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
525 DP_AUX_CH_CTL_RECEIVE_ERROR))
527 if (status & DP_AUX_CH_CTL_DONE)
530 if (status & DP_AUX_CH_CTL_DONE)
534 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
535 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
540 /* Check for timeout or receive error.
541 * Timeouts occur when the sink is not connected
543 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
544 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
549 /* Timeouts occur when the device isn't connected, so they're
550 * "normal" -- don't fill the kernel log with these */
551 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
552 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
557 /* Unload any bytes sent back from the other side */
558 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
559 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
560 if (recv_bytes > recv_size)
561 recv_bytes = recv_size;
563 for (i = 0; i < recv_bytes; i += 4)
564 unpack_aux(I915_READ(ch_data + i),
565 recv + i, recv_bytes - i);
569 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
570 intel_aux_display_runtime_put(dev_priv);
573 edp_panel_vdd_off(intel_dp, false);
578 #define HEADER_SIZE 4
580 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
582 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
583 uint8_t txbuf[20], rxbuf[20];
584 size_t txsize, rxsize;
587 txbuf[0] = msg->request << 4;
588 txbuf[1] = msg->address >> 8;
589 txbuf[2] = msg->address & 0xff;
590 txbuf[3] = msg->size - 1;
592 switch (msg->request & ~DP_AUX_I2C_MOT) {
593 case DP_AUX_NATIVE_WRITE:
594 case DP_AUX_I2C_WRITE:
595 txsize = HEADER_SIZE + msg->size;
598 if (WARN_ON(txsize > 20))
601 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
603 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
605 msg->reply = rxbuf[0] >> 4;
607 /* Return payload size. */
612 case DP_AUX_NATIVE_READ:
613 case DP_AUX_I2C_READ:
614 txsize = HEADER_SIZE;
615 rxsize = msg->size + 1;
617 if (WARN_ON(rxsize > 20))
620 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
622 msg->reply = rxbuf[0] >> 4;
624 * Assume happy day, and copy the data. The caller is
625 * expected to check msg->reply before touching it.
627 * Return payload size.
630 memcpy(msg->buffer, rxbuf + 1, ret);
643 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
645 struct drm_device *dev = intel_dp_to_dev(intel_dp);
647 intel_dp->aux.dev = dev->dev;
648 intel_dp->aux.transfer = intel_dp_aux_transfer;
652 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
653 uint8_t write_byte, uint8_t *read_byte)
655 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
656 struct intel_dp *intel_dp = container_of(adapter,
659 uint16_t address = algo_data->address;
667 /* Set up the command byte */
668 if (mode & MODE_I2C_READ)
669 msg[0] = DP_AUX_I2C_READ << 4;
671 msg[0] = DP_AUX_I2C_WRITE << 4;
673 if (!(mode & MODE_I2C_STOP))
674 msg[0] |= DP_AUX_I2C_MOT << 4;
676 msg[1] = address >> 8;
698 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is
699 * required to retry at least seven times upon receiving AUX_DEFER
700 * before giving up the AUX transaction.
702 for (retry = 0; retry < 7; retry++) {
703 ret = intel_dp_aux_ch(intel_dp,
707 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
711 switch ((reply[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK) {
712 case DP_AUX_NATIVE_REPLY_ACK:
713 /* I2C-over-AUX Reply field is only valid
714 * when paired with AUX ACK.
717 case DP_AUX_NATIVE_REPLY_NACK:
718 DRM_DEBUG_KMS("aux_ch native nack\n");
721 case DP_AUX_NATIVE_REPLY_DEFER:
723 * For now, just give more slack to branch devices. We
724 * could check the DPCD for I2C bit rate capabilities,
725 * and if available, adjust the interval. We could also
726 * be more careful with DP-to-Legacy adapters where a
727 * long legacy cable may force very low I2C bit rates.
729 if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
730 DP_DWN_STRM_PORT_PRESENT)
731 usleep_range(500, 600);
733 usleep_range(300, 400);
736 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
742 switch ((reply[0] >> 4) & DP_AUX_I2C_REPLY_MASK) {
743 case DP_AUX_I2C_REPLY_ACK:
744 if (mode == MODE_I2C_READ) {
745 *read_byte = reply[1];
747 ret = reply_bytes - 1;
749 case DP_AUX_I2C_REPLY_NACK:
750 DRM_DEBUG_KMS("aux_i2c nack\n");
753 case DP_AUX_I2C_REPLY_DEFER:
754 DRM_DEBUG_KMS("aux_i2c defer\n");
758 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
764 DRM_ERROR("too many retries, giving up\n");
772 intel_dp_connector_unregister(struct intel_connector *intel_connector)
774 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
776 sysfs_remove_link(&intel_connector->base.kdev->kobj,
777 intel_dp->adapter.dev.kobj.name);
778 intel_connector_unregister(intel_connector);
782 intel_dp_i2c_init(struct intel_dp *intel_dp,
783 struct intel_connector *intel_connector, const char *name)
787 DRM_DEBUG_KMS("i2c_init %s\n", name);
788 intel_dp->algo.running = false;
789 intel_dp->algo.address = 0;
790 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
792 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
793 intel_dp->adapter.owner = THIS_MODULE;
794 intel_dp->adapter.class = I2C_CLASS_DDC;
795 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
796 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
797 intel_dp->adapter.algo_data = &intel_dp->algo;
798 intel_dp->adapter.dev.parent = intel_connector->base.dev->dev;
800 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
804 ret = sysfs_create_link(&intel_connector->base.kdev->kobj,
805 &intel_dp->adapter.dev.kobj,
806 intel_dp->adapter.dev.kobj.name);
809 i2c_del_adapter(&intel_dp->adapter);
815 intel_dp_set_clock(struct intel_encoder *encoder,
816 struct intel_crtc_config *pipe_config, int link_bw)
818 struct drm_device *dev = encoder->base.dev;
819 const struct dp_link_dpll *divisor = NULL;
824 count = ARRAY_SIZE(gen4_dpll);
825 } else if (IS_HASWELL(dev)) {
826 /* Haswell has special-purpose DP DDI clocks. */
827 } else if (HAS_PCH_SPLIT(dev)) {
829 count = ARRAY_SIZE(pch_dpll);
830 } else if (IS_VALLEYVIEW(dev)) {
832 count = ARRAY_SIZE(vlv_dpll);
835 if (divisor && count) {
836 for (i = 0; i < count; i++) {
837 if (link_bw == divisor[i].link_bw) {
838 pipe_config->dpll = divisor[i].dpll;
839 pipe_config->clock_set = true;
847 intel_dp_compute_config(struct intel_encoder *encoder,
848 struct intel_crtc_config *pipe_config)
850 struct drm_device *dev = encoder->base.dev;
851 struct drm_i915_private *dev_priv = dev->dev_private;
852 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
853 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
854 enum port port = dp_to_dig_port(intel_dp)->port;
855 struct intel_crtc *intel_crtc = encoder->new_crtc;
856 struct intel_connector *intel_connector = intel_dp->attached_connector;
857 int lane_count, clock;
858 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
859 /* Conveniently, the link BW constants become indices with a shift...*/
860 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
862 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
863 int link_avail, link_clock;
865 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
866 pipe_config->has_pch_encoder = true;
868 pipe_config->has_dp_encoder = true;
870 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
871 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
873 if (!HAS_PCH_SPLIT(dev))
874 intel_gmch_panel_fitting(intel_crtc, pipe_config,
875 intel_connector->panel.fitting_mode);
877 intel_pch_panel_fitting(intel_crtc, pipe_config,
878 intel_connector->panel.fitting_mode);
881 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
884 DRM_DEBUG_KMS("DP link computation with max lane count %i "
885 "max bw %02x pixel clock %iKHz\n",
886 max_lane_count, bws[max_clock],
887 adjusted_mode->crtc_clock);
889 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
891 bpp = pipe_config->pipe_bpp;
892 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
893 dev_priv->vbt.edp_bpp < bpp) {
894 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
895 dev_priv->vbt.edp_bpp);
896 bpp = dev_priv->vbt.edp_bpp;
899 for (; bpp >= 6*3; bpp -= 2*3) {
900 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
903 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
904 for (clock = 0; clock <= max_clock; clock++) {
905 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
906 link_avail = intel_dp_max_data_rate(link_clock,
909 if (mode_rate <= link_avail) {
919 if (intel_dp->color_range_auto) {
922 * CEA-861-E - 5.1 Default Encoding Parameters
923 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
925 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
926 intel_dp->color_range = DP_COLOR_RANGE_16_235;
928 intel_dp->color_range = 0;
931 if (intel_dp->color_range)
932 pipe_config->limited_color_range = true;
934 intel_dp->link_bw = bws[clock];
935 intel_dp->lane_count = lane_count;
936 pipe_config->pipe_bpp = bpp;
937 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
939 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
940 intel_dp->link_bw, intel_dp->lane_count,
941 pipe_config->port_clock, bpp);
942 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
943 mode_rate, link_avail);
945 intel_link_compute_m_n(bpp, lane_count,
946 adjusted_mode->crtc_clock,
947 pipe_config->port_clock,
948 &pipe_config->dp_m_n);
950 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
955 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
957 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
958 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
959 struct drm_device *dev = crtc->base.dev;
960 struct drm_i915_private *dev_priv = dev->dev_private;
963 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
964 dpa_ctl = I915_READ(DP_A);
965 dpa_ctl &= ~DP_PLL_FREQ_MASK;
967 if (crtc->config.port_clock == 162000) {
968 /* For a long time we've carried around a ILK-DevA w/a for the
969 * 160MHz clock. If we're really unlucky, it's still required.
971 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
972 dpa_ctl |= DP_PLL_FREQ_160MHZ;
973 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
975 dpa_ctl |= DP_PLL_FREQ_270MHZ;
976 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
979 I915_WRITE(DP_A, dpa_ctl);
985 static void intel_dp_mode_set(struct intel_encoder *encoder)
987 struct drm_device *dev = encoder->base.dev;
988 struct drm_i915_private *dev_priv = dev->dev_private;
989 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
990 enum port port = dp_to_dig_port(intel_dp)->port;
991 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
992 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
995 * There are four kinds of DP registers:
1002 * IBX PCH and CPU are the same for almost everything,
1003 * except that the CPU DP PLL is configured in this
1006 * CPT PCH is quite different, having many bits moved
1007 * to the TRANS_DP_CTL register instead. That
1008 * configuration happens (oddly) in ironlake_pch_enable
1011 /* Preserve the BIOS-computed detected bit. This is
1012 * supposed to be read-only.
1014 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1016 /* Handle DP bits in common between all three register formats */
1017 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1018 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
1020 if (intel_dp->has_audio) {
1021 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
1022 pipe_name(crtc->pipe));
1023 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
1024 intel_write_eld(&encoder->base, adjusted_mode);
1027 /* Split out the IBX/CPU vs CPT settings */
1029 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1030 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1031 intel_dp->DP |= DP_SYNC_HS_HIGH;
1032 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1033 intel_dp->DP |= DP_SYNC_VS_HIGH;
1034 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1036 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1037 intel_dp->DP |= DP_ENHANCED_FRAMING;
1039 intel_dp->DP |= crtc->pipe << 29;
1040 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1041 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
1042 intel_dp->DP |= intel_dp->color_range;
1044 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1045 intel_dp->DP |= DP_SYNC_HS_HIGH;
1046 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1047 intel_dp->DP |= DP_SYNC_VS_HIGH;
1048 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1050 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1051 intel_dp->DP |= DP_ENHANCED_FRAMING;
1053 if (crtc->pipe == 1)
1054 intel_dp->DP |= DP_PIPEB_SELECT;
1056 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1059 if (port == PORT_A && !IS_VALLEYVIEW(dev))
1060 ironlake_set_pll_cpu_edp(intel_dp);
1063 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1064 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1066 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1067 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1069 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1070 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1072 static void wait_panel_status(struct intel_dp *intel_dp,
1076 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1077 struct drm_i915_private *dev_priv = dev->dev_private;
1078 u32 pp_stat_reg, pp_ctrl_reg;
1080 pp_stat_reg = _pp_stat_reg(intel_dp);
1081 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1083 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1085 I915_READ(pp_stat_reg),
1086 I915_READ(pp_ctrl_reg));
1088 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1089 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1090 I915_READ(pp_stat_reg),
1091 I915_READ(pp_ctrl_reg));
1094 DRM_DEBUG_KMS("Wait complete\n");
1097 static void wait_panel_on(struct intel_dp *intel_dp)
1099 DRM_DEBUG_KMS("Wait for panel power on\n");
1100 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1103 static void wait_panel_off(struct intel_dp *intel_dp)
1105 DRM_DEBUG_KMS("Wait for panel power off time\n");
1106 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1109 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1111 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1113 /* When we disable the VDD override bit last we have to do the manual
1115 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1116 intel_dp->panel_power_cycle_delay);
1118 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1121 static void wait_backlight_on(struct intel_dp *intel_dp)
1123 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1124 intel_dp->backlight_on_delay);
1127 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1129 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1130 intel_dp->backlight_off_delay);
1133 /* Read the current pp_control value, unlocking the register if it
1137 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1139 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1140 struct drm_i915_private *dev_priv = dev->dev_private;
1143 control = I915_READ(_pp_ctrl_reg(intel_dp));
1144 control &= ~PANEL_UNLOCK_MASK;
1145 control |= PANEL_UNLOCK_REGS;
1149 static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
1151 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1152 struct drm_i915_private *dev_priv = dev->dev_private;
1154 u32 pp_stat_reg, pp_ctrl_reg;
1155 bool need_to_disable = !intel_dp->want_panel_vdd;
1157 if (!is_edp(intel_dp))
1160 intel_dp->want_panel_vdd = true;
1162 if (edp_have_panel_vdd(intel_dp))
1163 return need_to_disable;
1165 intel_runtime_pm_get(dev_priv);
1167 DRM_DEBUG_KMS("Turning eDP VDD on\n");
1169 if (!edp_have_panel_power(intel_dp))
1170 wait_panel_power_cycle(intel_dp);
1172 pp = ironlake_get_pp_control(intel_dp);
1173 pp |= EDP_FORCE_VDD;
1175 pp_stat_reg = _pp_stat_reg(intel_dp);
1176 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1178 I915_WRITE(pp_ctrl_reg, pp);
1179 POSTING_READ(pp_ctrl_reg);
1180 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1181 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1183 * If the panel wasn't on, delay before accessing aux channel
1185 if (!edp_have_panel_power(intel_dp)) {
1186 DRM_DEBUG_KMS("eDP was not running\n");
1187 msleep(intel_dp->panel_power_up_delay);
1190 return need_to_disable;
1193 static void edp_panel_vdd_on(struct intel_dp *intel_dp)
1195 if (is_edp(intel_dp)) {
1196 bool vdd = _edp_panel_vdd_on(intel_dp);
1198 WARN(!vdd, "eDP VDD already requested on\n");
1202 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1204 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1205 struct drm_i915_private *dev_priv = dev->dev_private;
1207 u32 pp_stat_reg, pp_ctrl_reg;
1209 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1211 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
1212 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1214 pp = ironlake_get_pp_control(intel_dp);
1215 pp &= ~EDP_FORCE_VDD;
1217 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1218 pp_stat_reg = _pp_stat_reg(intel_dp);
1220 I915_WRITE(pp_ctrl_reg, pp);
1221 POSTING_READ(pp_ctrl_reg);
1223 /* Make sure sequencer is idle before allowing subsequent activity */
1224 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1225 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1227 if ((pp & POWER_TARGET_ON) == 0)
1228 intel_dp->last_power_cycle = jiffies;
1230 intel_runtime_pm_put(dev_priv);
1234 static void edp_panel_vdd_work(struct work_struct *__work)
1236 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1237 struct intel_dp, panel_vdd_work);
1238 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1240 mutex_lock(&dev->mode_config.mutex);
1241 edp_panel_vdd_off_sync(intel_dp);
1242 mutex_unlock(&dev->mode_config.mutex);
1245 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1247 if (!is_edp(intel_dp))
1250 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1252 intel_dp->want_panel_vdd = false;
1255 edp_panel_vdd_off_sync(intel_dp);
1258 * Queue the timer to fire a long
1259 * time from now (relative to the power down delay)
1260 * to keep the panel power up across a sequence of operations
1262 schedule_delayed_work(&intel_dp->panel_vdd_work,
1263 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1267 void intel_edp_panel_on(struct intel_dp *intel_dp)
1269 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1270 struct drm_i915_private *dev_priv = dev->dev_private;
1274 if (!is_edp(intel_dp))
1277 DRM_DEBUG_KMS("Turn eDP power on\n");
1279 if (edp_have_panel_power(intel_dp)) {
1280 DRM_DEBUG_KMS("eDP power already on\n");
1284 wait_panel_power_cycle(intel_dp);
1286 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1287 pp = ironlake_get_pp_control(intel_dp);
1289 /* ILK workaround: disable reset around power sequence */
1290 pp &= ~PANEL_POWER_RESET;
1291 I915_WRITE(pp_ctrl_reg, pp);
1292 POSTING_READ(pp_ctrl_reg);
1295 pp |= POWER_TARGET_ON;
1297 pp |= PANEL_POWER_RESET;
1299 I915_WRITE(pp_ctrl_reg, pp);
1300 POSTING_READ(pp_ctrl_reg);
1302 wait_panel_on(intel_dp);
1303 intel_dp->last_power_on = jiffies;
1306 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1307 I915_WRITE(pp_ctrl_reg, pp);
1308 POSTING_READ(pp_ctrl_reg);
1312 void intel_edp_panel_off(struct intel_dp *intel_dp)
1314 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1315 struct drm_i915_private *dev_priv = dev->dev_private;
1319 if (!is_edp(intel_dp))
1322 DRM_DEBUG_KMS("Turn eDP power off\n");
1324 edp_wait_backlight_off(intel_dp);
1326 pp = ironlake_get_pp_control(intel_dp);
1327 /* We need to switch off panel power _and_ force vdd, for otherwise some
1328 * panels get very unhappy and cease to work. */
1329 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1332 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1334 I915_WRITE(pp_ctrl_reg, pp);
1335 POSTING_READ(pp_ctrl_reg);
1337 intel_dp->last_power_cycle = jiffies;
1338 wait_panel_off(intel_dp);
1341 void intel_edp_backlight_on(struct intel_dp *intel_dp)
1343 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1344 struct drm_device *dev = intel_dig_port->base.base.dev;
1345 struct drm_i915_private *dev_priv = dev->dev_private;
1349 if (!is_edp(intel_dp))
1352 DRM_DEBUG_KMS("\n");
1354 * If we enable the backlight right away following a panel power
1355 * on, we may see slight flicker as the panel syncs with the eDP
1356 * link. So delay a bit to make sure the image is solid before
1357 * allowing it to appear.
1359 wait_backlight_on(intel_dp);
1360 pp = ironlake_get_pp_control(intel_dp);
1361 pp |= EDP_BLC_ENABLE;
1363 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1365 I915_WRITE(pp_ctrl_reg, pp);
1366 POSTING_READ(pp_ctrl_reg);
1368 intel_panel_enable_backlight(intel_dp->attached_connector);
1371 void intel_edp_backlight_off(struct intel_dp *intel_dp)
1373 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1374 struct drm_i915_private *dev_priv = dev->dev_private;
1378 if (!is_edp(intel_dp))
1381 intel_panel_disable_backlight(intel_dp->attached_connector);
1383 DRM_DEBUG_KMS("\n");
1384 pp = ironlake_get_pp_control(intel_dp);
1385 pp &= ~EDP_BLC_ENABLE;
1387 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1389 I915_WRITE(pp_ctrl_reg, pp);
1390 POSTING_READ(pp_ctrl_reg);
1391 intel_dp->last_backlight_off = jiffies;
1394 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1396 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1397 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1398 struct drm_device *dev = crtc->dev;
1399 struct drm_i915_private *dev_priv = dev->dev_private;
1402 assert_pipe_disabled(dev_priv,
1403 to_intel_crtc(crtc)->pipe);
1405 DRM_DEBUG_KMS("\n");
1406 dpa_ctl = I915_READ(DP_A);
1407 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1408 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1410 /* We don't adjust intel_dp->DP while tearing down the link, to
1411 * facilitate link retraining (e.g. after hotplug). Hence clear all
1412 * enable bits here to ensure that we don't enable too much. */
1413 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1414 intel_dp->DP |= DP_PLL_ENABLE;
1415 I915_WRITE(DP_A, intel_dp->DP);
1420 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1422 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1423 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1424 struct drm_device *dev = crtc->dev;
1425 struct drm_i915_private *dev_priv = dev->dev_private;
1428 assert_pipe_disabled(dev_priv,
1429 to_intel_crtc(crtc)->pipe);
1431 dpa_ctl = I915_READ(DP_A);
1432 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1433 "dp pll off, should be on\n");
1434 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1436 /* We can't rely on the value tracked for the DP register in
1437 * intel_dp->DP because link_down must not change that (otherwise link
1438 * re-training will fail. */
1439 dpa_ctl &= ~DP_PLL_ENABLE;
1440 I915_WRITE(DP_A, dpa_ctl);
1445 /* If the sink supports it, try to set the power state appropriately */
1446 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1450 /* Should have a valid DPCD by this point */
1451 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1454 if (mode != DRM_MODE_DPMS_ON) {
1455 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1458 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1461 * When turning on, we need to retry for 1ms to give the sink
1464 for (i = 0; i < 3; i++) {
1465 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1474 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1477 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1478 enum port port = dp_to_dig_port(intel_dp)->port;
1479 struct drm_device *dev = encoder->base.dev;
1480 struct drm_i915_private *dev_priv = dev->dev_private;
1481 enum intel_display_power_domain power_domain;
1484 power_domain = intel_display_port_power_domain(encoder);
1485 if (!intel_display_power_enabled(dev_priv, power_domain))
1488 tmp = I915_READ(intel_dp->output_reg);
1490 if (!(tmp & DP_PORT_EN))
1493 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1494 *pipe = PORT_TO_PIPE_CPT(tmp);
1495 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1496 *pipe = PORT_TO_PIPE(tmp);
1502 switch (intel_dp->output_reg) {
1504 trans_sel = TRANS_DP_PORT_SEL_B;
1507 trans_sel = TRANS_DP_PORT_SEL_C;
1510 trans_sel = TRANS_DP_PORT_SEL_D;
1517 trans_dp = I915_READ(TRANS_DP_CTL(i));
1518 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1524 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1525 intel_dp->output_reg);
1531 static void intel_dp_get_config(struct intel_encoder *encoder,
1532 struct intel_crtc_config *pipe_config)
1534 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1536 struct drm_device *dev = encoder->base.dev;
1537 struct drm_i915_private *dev_priv = dev->dev_private;
1538 enum port port = dp_to_dig_port(intel_dp)->port;
1539 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1542 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1543 tmp = I915_READ(intel_dp->output_reg);
1544 if (tmp & DP_SYNC_HS_HIGH)
1545 flags |= DRM_MODE_FLAG_PHSYNC;
1547 flags |= DRM_MODE_FLAG_NHSYNC;
1549 if (tmp & DP_SYNC_VS_HIGH)
1550 flags |= DRM_MODE_FLAG_PVSYNC;
1552 flags |= DRM_MODE_FLAG_NVSYNC;
1554 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1555 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1556 flags |= DRM_MODE_FLAG_PHSYNC;
1558 flags |= DRM_MODE_FLAG_NHSYNC;
1560 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1561 flags |= DRM_MODE_FLAG_PVSYNC;
1563 flags |= DRM_MODE_FLAG_NVSYNC;
1566 pipe_config->adjusted_mode.flags |= flags;
1568 pipe_config->has_dp_encoder = true;
1570 intel_dp_get_m_n(crtc, pipe_config);
1572 if (port == PORT_A) {
1573 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1574 pipe_config->port_clock = 162000;
1576 pipe_config->port_clock = 270000;
1579 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1580 &pipe_config->dp_m_n);
1582 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1583 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1585 pipe_config->adjusted_mode.crtc_clock = dotclock;
1587 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1588 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1590 * This is a big fat ugly hack.
1592 * Some machines in UEFI boot mode provide us a VBT that has 18
1593 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1594 * unknown we fail to light up. Yet the same BIOS boots up with
1595 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1596 * max, not what it tells us to use.
1598 * Note: This will still be broken if the eDP panel is not lit
1599 * up by the BIOS, and thus we can't get the mode at module
1602 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1603 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1604 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1608 static bool is_edp_psr(struct drm_device *dev)
1610 struct drm_i915_private *dev_priv = dev->dev_private;
1612 return dev_priv->psr.sink_support;
1615 static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1617 struct drm_i915_private *dev_priv = dev->dev_private;
1622 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1625 static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1626 struct edp_vsc_psr *vsc_psr)
1628 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1629 struct drm_device *dev = dig_port->base.base.dev;
1630 struct drm_i915_private *dev_priv = dev->dev_private;
1631 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1632 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1633 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1634 uint32_t *data = (uint32_t *) vsc_psr;
1637 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1638 the video DIP being updated before program video DIP data buffer
1639 registers for DIP being updated. */
1640 I915_WRITE(ctl_reg, 0);
1641 POSTING_READ(ctl_reg);
1643 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1644 if (i < sizeof(struct edp_vsc_psr))
1645 I915_WRITE(data_reg + i, *data++);
1647 I915_WRITE(data_reg + i, 0);
1650 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1651 POSTING_READ(ctl_reg);
1654 static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1656 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1657 struct drm_i915_private *dev_priv = dev->dev_private;
1658 struct edp_vsc_psr psr_vsc;
1660 if (intel_dp->psr_setup_done)
1663 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1664 memset(&psr_vsc, 0, sizeof(psr_vsc));
1665 psr_vsc.sdp_header.HB0 = 0;
1666 psr_vsc.sdp_header.HB1 = 0x7;
1667 psr_vsc.sdp_header.HB2 = 0x2;
1668 psr_vsc.sdp_header.HB3 = 0x8;
1669 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1671 /* Avoid continuous PSR exit by masking memup and hpd */
1672 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
1673 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
1675 intel_dp->psr_setup_done = true;
1678 static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1680 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1681 struct drm_i915_private *dev_priv = dev->dev_private;
1682 uint32_t aux_clock_divider;
1683 int precharge = 0x3;
1684 int msg_size = 5; /* Header(4) + Message(1) */
1686 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1688 /* Enable PSR in sink */
1689 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1690 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1691 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
1693 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1694 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
1696 /* Setup AUX registers */
1697 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1698 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1699 I915_WRITE(EDP_PSR_AUX_CTL(dev),
1700 DP_AUX_CH_CTL_TIME_OUT_400us |
1701 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1702 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1703 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1706 static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1708 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1709 struct drm_i915_private *dev_priv = dev->dev_private;
1710 uint32_t max_sleep_time = 0x1f;
1711 uint32_t idle_frames = 1;
1713 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
1715 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1716 val |= EDP_PSR_LINK_STANDBY;
1717 val |= EDP_PSR_TP2_TP3_TIME_0us;
1718 val |= EDP_PSR_TP1_TIME_0us;
1719 val |= EDP_PSR_SKIP_AUX_EXIT;
1721 val |= EDP_PSR_LINK_DISABLE;
1723 I915_WRITE(EDP_PSR_CTL(dev), val |
1724 IS_BROADWELL(dev) ? 0 : link_entry_time |
1725 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1726 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1730 static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1732 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1733 struct drm_device *dev = dig_port->base.base.dev;
1734 struct drm_i915_private *dev_priv = dev->dev_private;
1735 struct drm_crtc *crtc = dig_port->base.base.crtc;
1736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1737 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
1738 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1740 dev_priv->psr.source_ok = false;
1742 if (!HAS_PSR(dev)) {
1743 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1747 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1748 (dig_port->port != PORT_A)) {
1749 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1753 if (!i915.enable_psr) {
1754 DRM_DEBUG_KMS("PSR disable by flag\n");
1758 crtc = dig_port->base.base.crtc;
1760 DRM_DEBUG_KMS("crtc not active for PSR\n");
1764 intel_crtc = to_intel_crtc(crtc);
1765 if (!intel_crtc_active(crtc)) {
1766 DRM_DEBUG_KMS("crtc not active for PSR\n");
1770 obj = to_intel_framebuffer(crtc->fb)->obj;
1771 if (obj->tiling_mode != I915_TILING_X ||
1772 obj->fence_reg == I915_FENCE_REG_NONE) {
1773 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
1777 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1778 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
1782 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1784 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1788 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
1789 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1793 dev_priv->psr.source_ok = true;
1797 static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
1799 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1801 if (!intel_edp_psr_match_conditions(intel_dp) ||
1802 intel_edp_is_psr_enabled(dev))
1805 /* Setup PSR once */
1806 intel_edp_psr_setup(intel_dp);
1808 /* Enable PSR on the panel */
1809 intel_edp_psr_enable_sink(intel_dp);
1811 /* Enable PSR on the host */
1812 intel_edp_psr_enable_source(intel_dp);
1815 void intel_edp_psr_enable(struct intel_dp *intel_dp)
1817 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1819 if (intel_edp_psr_match_conditions(intel_dp) &&
1820 !intel_edp_is_psr_enabled(dev))
1821 intel_edp_psr_do_enable(intel_dp);
1824 void intel_edp_psr_disable(struct intel_dp *intel_dp)
1826 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1827 struct drm_i915_private *dev_priv = dev->dev_private;
1829 if (!intel_edp_is_psr_enabled(dev))
1832 I915_WRITE(EDP_PSR_CTL(dev),
1833 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
1835 /* Wait till PSR is idle */
1836 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
1837 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1838 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1841 void intel_edp_psr_update(struct drm_device *dev)
1843 struct intel_encoder *encoder;
1844 struct intel_dp *intel_dp = NULL;
1846 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1847 if (encoder->type == INTEL_OUTPUT_EDP) {
1848 intel_dp = enc_to_intel_dp(&encoder->base);
1850 if (!is_edp_psr(dev))
1853 if (!intel_edp_psr_match_conditions(intel_dp))
1854 intel_edp_psr_disable(intel_dp);
1856 if (!intel_edp_is_psr_enabled(dev))
1857 intel_edp_psr_do_enable(intel_dp);
1861 static void intel_disable_dp(struct intel_encoder *encoder)
1863 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1864 enum port port = dp_to_dig_port(intel_dp)->port;
1865 struct drm_device *dev = encoder->base.dev;
1867 /* Make sure the panel is off before trying to change the mode. But also
1868 * ensure that we have vdd while we switch off the panel. */
1869 edp_panel_vdd_on(intel_dp);
1870 intel_edp_backlight_off(intel_dp);
1871 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1872 intel_edp_panel_off(intel_dp);
1873 edp_panel_vdd_off(intel_dp, true);
1875 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1876 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
1877 intel_dp_link_down(intel_dp);
1880 static void intel_post_disable_dp(struct intel_encoder *encoder)
1882 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1883 enum port port = dp_to_dig_port(intel_dp)->port;
1884 struct drm_device *dev = encoder->base.dev;
1886 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
1887 intel_dp_link_down(intel_dp);
1888 if (!IS_VALLEYVIEW(dev))
1889 ironlake_edp_pll_off(intel_dp);
1893 static void intel_enable_dp(struct intel_encoder *encoder)
1895 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1896 struct drm_device *dev = encoder->base.dev;
1897 struct drm_i915_private *dev_priv = dev->dev_private;
1898 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1900 if (WARN_ON(dp_reg & DP_PORT_EN))
1903 edp_panel_vdd_on(intel_dp);
1904 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1905 intel_dp_start_link_train(intel_dp);
1906 intel_edp_panel_on(intel_dp);
1907 edp_panel_vdd_off(intel_dp, true);
1908 intel_dp_complete_link_train(intel_dp);
1909 intel_dp_stop_link_train(intel_dp);
1912 static void g4x_enable_dp(struct intel_encoder *encoder)
1914 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1916 intel_enable_dp(encoder);
1917 intel_edp_backlight_on(intel_dp);
1920 static void vlv_enable_dp(struct intel_encoder *encoder)
1922 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1924 intel_edp_backlight_on(intel_dp);
1927 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
1929 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1930 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1932 if (dport->port == PORT_A)
1933 ironlake_edp_pll_on(intel_dp);
1936 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
1938 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1939 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1940 struct drm_device *dev = encoder->base.dev;
1941 struct drm_i915_private *dev_priv = dev->dev_private;
1942 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1943 enum dpio_channel port = vlv_dport_to_channel(dport);
1944 int pipe = intel_crtc->pipe;
1945 struct edp_power_seq power_seq;
1948 mutex_lock(&dev_priv->dpio_lock);
1950 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1957 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1958 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1959 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1961 mutex_unlock(&dev_priv->dpio_lock);
1963 if (is_edp(intel_dp)) {
1964 /* init power sequencer on this pipe and port */
1965 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1966 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1970 intel_enable_dp(encoder);
1972 vlv_wait_port_ready(dev_priv, dport);
1975 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
1977 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1978 struct drm_device *dev = encoder->base.dev;
1979 struct drm_i915_private *dev_priv = dev->dev_private;
1980 struct intel_crtc *intel_crtc =
1981 to_intel_crtc(encoder->base.crtc);
1982 enum dpio_channel port = vlv_dport_to_channel(dport);
1983 int pipe = intel_crtc->pipe;
1985 /* Program Tx lane resets to default */
1986 mutex_lock(&dev_priv->dpio_lock);
1987 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1988 DPIO_PCS_TX_LANE2_RESET |
1989 DPIO_PCS_TX_LANE1_RESET);
1990 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1991 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1992 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1993 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1994 DPIO_PCS_CLK_SOFT_RESET);
1996 /* Fix up inter-pair skew failure */
1997 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1998 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1999 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
2000 mutex_unlock(&dev_priv->dpio_lock);
2004 * Native read with retry for link status and receiver capability reads for
2005 * cases where the sink may still be asleep.
2007 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2008 * supposed to retry 3 times per the spec.
2011 intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2012 void *buffer, size_t size)
2017 for (i = 0; i < 3; i++) {
2018 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2028 * Fetch AUX CH registers 0x202 - 0x207 which contain
2029 * link status information
2032 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2034 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2037 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
2041 * These are source-specific values; current Intel hardware supports
2042 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
2046 intel_dp_voltage_max(struct intel_dp *intel_dp)
2048 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2049 enum port port = dp_to_dig_port(intel_dp)->port;
2051 if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
2052 return DP_TRAIN_VOLTAGE_SWING_1200;
2053 else if (IS_GEN7(dev) && port == PORT_A)
2054 return DP_TRAIN_VOLTAGE_SWING_800;
2055 else if (HAS_PCH_CPT(dev) && port != PORT_A)
2056 return DP_TRAIN_VOLTAGE_SWING_1200;
2058 return DP_TRAIN_VOLTAGE_SWING_800;
2062 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2064 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2065 enum port port = dp_to_dig_port(intel_dp)->port;
2067 if (IS_BROADWELL(dev)) {
2068 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2069 case DP_TRAIN_VOLTAGE_SWING_400:
2070 case DP_TRAIN_VOLTAGE_SWING_600:
2071 return DP_TRAIN_PRE_EMPHASIS_6;
2072 case DP_TRAIN_VOLTAGE_SWING_800:
2073 return DP_TRAIN_PRE_EMPHASIS_3_5;
2074 case DP_TRAIN_VOLTAGE_SWING_1200:
2076 return DP_TRAIN_PRE_EMPHASIS_0;
2078 } else if (IS_HASWELL(dev)) {
2079 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2080 case DP_TRAIN_VOLTAGE_SWING_400:
2081 return DP_TRAIN_PRE_EMPHASIS_9_5;
2082 case DP_TRAIN_VOLTAGE_SWING_600:
2083 return DP_TRAIN_PRE_EMPHASIS_6;
2084 case DP_TRAIN_VOLTAGE_SWING_800:
2085 return DP_TRAIN_PRE_EMPHASIS_3_5;
2086 case DP_TRAIN_VOLTAGE_SWING_1200:
2088 return DP_TRAIN_PRE_EMPHASIS_0;
2090 } else if (IS_VALLEYVIEW(dev)) {
2091 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2092 case DP_TRAIN_VOLTAGE_SWING_400:
2093 return DP_TRAIN_PRE_EMPHASIS_9_5;
2094 case DP_TRAIN_VOLTAGE_SWING_600:
2095 return DP_TRAIN_PRE_EMPHASIS_6;
2096 case DP_TRAIN_VOLTAGE_SWING_800:
2097 return DP_TRAIN_PRE_EMPHASIS_3_5;
2098 case DP_TRAIN_VOLTAGE_SWING_1200:
2100 return DP_TRAIN_PRE_EMPHASIS_0;
2102 } else if (IS_GEN7(dev) && port == PORT_A) {
2103 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2104 case DP_TRAIN_VOLTAGE_SWING_400:
2105 return DP_TRAIN_PRE_EMPHASIS_6;
2106 case DP_TRAIN_VOLTAGE_SWING_600:
2107 case DP_TRAIN_VOLTAGE_SWING_800:
2108 return DP_TRAIN_PRE_EMPHASIS_3_5;
2110 return DP_TRAIN_PRE_EMPHASIS_0;
2113 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2114 case DP_TRAIN_VOLTAGE_SWING_400:
2115 return DP_TRAIN_PRE_EMPHASIS_6;
2116 case DP_TRAIN_VOLTAGE_SWING_600:
2117 return DP_TRAIN_PRE_EMPHASIS_6;
2118 case DP_TRAIN_VOLTAGE_SWING_800:
2119 return DP_TRAIN_PRE_EMPHASIS_3_5;
2120 case DP_TRAIN_VOLTAGE_SWING_1200:
2122 return DP_TRAIN_PRE_EMPHASIS_0;
2127 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2129 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2130 struct drm_i915_private *dev_priv = dev->dev_private;
2131 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2132 struct intel_crtc *intel_crtc =
2133 to_intel_crtc(dport->base.base.crtc);
2134 unsigned long demph_reg_value, preemph_reg_value,
2135 uniqtranscale_reg_value;
2136 uint8_t train_set = intel_dp->train_set[0];
2137 enum dpio_channel port = vlv_dport_to_channel(dport);
2138 int pipe = intel_crtc->pipe;
2140 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2141 case DP_TRAIN_PRE_EMPHASIS_0:
2142 preemph_reg_value = 0x0004000;
2143 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2144 case DP_TRAIN_VOLTAGE_SWING_400:
2145 demph_reg_value = 0x2B405555;
2146 uniqtranscale_reg_value = 0x552AB83A;
2148 case DP_TRAIN_VOLTAGE_SWING_600:
2149 demph_reg_value = 0x2B404040;
2150 uniqtranscale_reg_value = 0x5548B83A;
2152 case DP_TRAIN_VOLTAGE_SWING_800:
2153 demph_reg_value = 0x2B245555;
2154 uniqtranscale_reg_value = 0x5560B83A;
2156 case DP_TRAIN_VOLTAGE_SWING_1200:
2157 demph_reg_value = 0x2B405555;
2158 uniqtranscale_reg_value = 0x5598DA3A;
2164 case DP_TRAIN_PRE_EMPHASIS_3_5:
2165 preemph_reg_value = 0x0002000;
2166 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2167 case DP_TRAIN_VOLTAGE_SWING_400:
2168 demph_reg_value = 0x2B404040;
2169 uniqtranscale_reg_value = 0x5552B83A;
2171 case DP_TRAIN_VOLTAGE_SWING_600:
2172 demph_reg_value = 0x2B404848;
2173 uniqtranscale_reg_value = 0x5580B83A;
2175 case DP_TRAIN_VOLTAGE_SWING_800:
2176 demph_reg_value = 0x2B404040;
2177 uniqtranscale_reg_value = 0x55ADDA3A;
2183 case DP_TRAIN_PRE_EMPHASIS_6:
2184 preemph_reg_value = 0x0000000;
2185 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2186 case DP_TRAIN_VOLTAGE_SWING_400:
2187 demph_reg_value = 0x2B305555;
2188 uniqtranscale_reg_value = 0x5570B83A;
2190 case DP_TRAIN_VOLTAGE_SWING_600:
2191 demph_reg_value = 0x2B2B4040;
2192 uniqtranscale_reg_value = 0x55ADDA3A;
2198 case DP_TRAIN_PRE_EMPHASIS_9_5:
2199 preemph_reg_value = 0x0006000;
2200 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2201 case DP_TRAIN_VOLTAGE_SWING_400:
2202 demph_reg_value = 0x1B405555;
2203 uniqtranscale_reg_value = 0x55ADDA3A;
2213 mutex_lock(&dev_priv->dpio_lock);
2214 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2215 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2216 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
2217 uniqtranscale_reg_value);
2218 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2219 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2220 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2221 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
2222 mutex_unlock(&dev_priv->dpio_lock);
2228 intel_get_adjust_train(struct intel_dp *intel_dp,
2229 const uint8_t link_status[DP_LINK_STATUS_SIZE])
2234 uint8_t voltage_max;
2235 uint8_t preemph_max;
2237 for (lane = 0; lane < intel_dp->lane_count; lane++) {
2238 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2239 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
2247 voltage_max = intel_dp_voltage_max(intel_dp);
2248 if (v >= voltage_max)
2249 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
2251 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2252 if (p >= preemph_max)
2253 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2255 for (lane = 0; lane < 4; lane++)
2256 intel_dp->train_set[lane] = v | p;
2260 intel_gen4_signal_levels(uint8_t train_set)
2262 uint32_t signal_levels = 0;
2264 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2265 case DP_TRAIN_VOLTAGE_SWING_400:
2267 signal_levels |= DP_VOLTAGE_0_4;
2269 case DP_TRAIN_VOLTAGE_SWING_600:
2270 signal_levels |= DP_VOLTAGE_0_6;
2272 case DP_TRAIN_VOLTAGE_SWING_800:
2273 signal_levels |= DP_VOLTAGE_0_8;
2275 case DP_TRAIN_VOLTAGE_SWING_1200:
2276 signal_levels |= DP_VOLTAGE_1_2;
2279 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2280 case DP_TRAIN_PRE_EMPHASIS_0:
2282 signal_levels |= DP_PRE_EMPHASIS_0;
2284 case DP_TRAIN_PRE_EMPHASIS_3_5:
2285 signal_levels |= DP_PRE_EMPHASIS_3_5;
2287 case DP_TRAIN_PRE_EMPHASIS_6:
2288 signal_levels |= DP_PRE_EMPHASIS_6;
2290 case DP_TRAIN_PRE_EMPHASIS_9_5:
2291 signal_levels |= DP_PRE_EMPHASIS_9_5;
2294 return signal_levels;
2297 /* Gen6's DP voltage swing and pre-emphasis control */
2299 intel_gen6_edp_signal_levels(uint8_t train_set)
2301 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2302 DP_TRAIN_PRE_EMPHASIS_MASK);
2303 switch (signal_levels) {
2304 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2305 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2306 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2307 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2308 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
2309 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2310 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2311 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
2312 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2313 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2314 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
2315 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2316 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2317 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
2319 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2320 "0x%x\n", signal_levels);
2321 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2325 /* Gen7's DP voltage swing and pre-emphasis control */
2327 intel_gen7_edp_signal_levels(uint8_t train_set)
2329 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2330 DP_TRAIN_PRE_EMPHASIS_MASK);
2331 switch (signal_levels) {
2332 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2333 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2334 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2335 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2336 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2337 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2339 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2340 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2341 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2342 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2344 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2345 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2346 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2347 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2350 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2351 "0x%x\n", signal_levels);
2352 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2356 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2358 intel_hsw_signal_levels(uint8_t train_set)
2360 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2361 DP_TRAIN_PRE_EMPHASIS_MASK);
2362 switch (signal_levels) {
2363 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2364 return DDI_BUF_EMP_400MV_0DB_HSW;
2365 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2366 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2367 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2368 return DDI_BUF_EMP_400MV_6DB_HSW;
2369 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2370 return DDI_BUF_EMP_400MV_9_5DB_HSW;
2372 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2373 return DDI_BUF_EMP_600MV_0DB_HSW;
2374 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2375 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2376 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2377 return DDI_BUF_EMP_600MV_6DB_HSW;
2379 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2380 return DDI_BUF_EMP_800MV_0DB_HSW;
2381 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2382 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2384 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2385 "0x%x\n", signal_levels);
2386 return DDI_BUF_EMP_400MV_0DB_HSW;
2391 intel_bdw_signal_levels(uint8_t train_set)
2393 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2394 DP_TRAIN_PRE_EMPHASIS_MASK);
2395 switch (signal_levels) {
2396 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2397 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2398 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2399 return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */
2400 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2401 return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */
2403 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2404 return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */
2405 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2406 return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */
2407 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2408 return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */
2410 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2411 return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */
2412 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2413 return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */
2415 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2416 return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */
2419 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2420 "0x%x\n", signal_levels);
2421 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2425 /* Properly updates "DP" with the correct signal levels. */
2427 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2429 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2430 enum port port = intel_dig_port->port;
2431 struct drm_device *dev = intel_dig_port->base.base.dev;
2432 uint32_t signal_levels, mask;
2433 uint8_t train_set = intel_dp->train_set[0];
2435 if (IS_BROADWELL(dev)) {
2436 signal_levels = intel_bdw_signal_levels(train_set);
2437 mask = DDI_BUF_EMP_MASK;
2438 } else if (IS_HASWELL(dev)) {
2439 signal_levels = intel_hsw_signal_levels(train_set);
2440 mask = DDI_BUF_EMP_MASK;
2441 } else if (IS_VALLEYVIEW(dev)) {
2442 signal_levels = intel_vlv_signal_levels(intel_dp);
2444 } else if (IS_GEN7(dev) && port == PORT_A) {
2445 signal_levels = intel_gen7_edp_signal_levels(train_set);
2446 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
2447 } else if (IS_GEN6(dev) && port == PORT_A) {
2448 signal_levels = intel_gen6_edp_signal_levels(train_set);
2449 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2451 signal_levels = intel_gen4_signal_levels(train_set);
2452 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2455 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2457 *DP = (*DP & ~mask) | signal_levels;
2461 intel_dp_set_link_train(struct intel_dp *intel_dp,
2463 uint8_t dp_train_pat)
2465 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2466 struct drm_device *dev = intel_dig_port->base.base.dev;
2467 struct drm_i915_private *dev_priv = dev->dev_private;
2468 enum port port = intel_dig_port->port;
2469 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2473 uint32_t temp = I915_READ(DP_TP_CTL(port));
2475 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2476 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2478 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2480 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2481 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2482 case DP_TRAINING_PATTERN_DISABLE:
2483 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2486 case DP_TRAINING_PATTERN_1:
2487 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2489 case DP_TRAINING_PATTERN_2:
2490 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2492 case DP_TRAINING_PATTERN_3:
2493 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2496 I915_WRITE(DP_TP_CTL(port), temp);
2498 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2499 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2501 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2502 case DP_TRAINING_PATTERN_DISABLE:
2503 *DP |= DP_LINK_TRAIN_OFF_CPT;
2505 case DP_TRAINING_PATTERN_1:
2506 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2508 case DP_TRAINING_PATTERN_2:
2509 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2511 case DP_TRAINING_PATTERN_3:
2512 DRM_ERROR("DP training pattern 3 not supported\n");
2513 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2518 *DP &= ~DP_LINK_TRAIN_MASK;
2520 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2521 case DP_TRAINING_PATTERN_DISABLE:
2522 *DP |= DP_LINK_TRAIN_OFF;
2524 case DP_TRAINING_PATTERN_1:
2525 *DP |= DP_LINK_TRAIN_PAT_1;
2527 case DP_TRAINING_PATTERN_2:
2528 *DP |= DP_LINK_TRAIN_PAT_2;
2530 case DP_TRAINING_PATTERN_3:
2531 DRM_ERROR("DP training pattern 3 not supported\n");
2532 *DP |= DP_LINK_TRAIN_PAT_2;
2537 I915_WRITE(intel_dp->output_reg, *DP);
2538 POSTING_READ(intel_dp->output_reg);
2540 buf[0] = dp_train_pat;
2541 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
2542 DP_TRAINING_PATTERN_DISABLE) {
2543 /* don't write DP_TRAINING_LANEx_SET on disable */
2546 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2547 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2548 len = intel_dp->lane_count + 1;
2551 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
2558 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2559 uint8_t dp_train_pat)
2561 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
2562 intel_dp_set_signal_levels(intel_dp, DP);
2563 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2567 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2568 const uint8_t link_status[DP_LINK_STATUS_SIZE])
2570 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2571 struct drm_device *dev = intel_dig_port->base.base.dev;
2572 struct drm_i915_private *dev_priv = dev->dev_private;
2575 intel_get_adjust_train(intel_dp, link_status);
2576 intel_dp_set_signal_levels(intel_dp, DP);
2578 I915_WRITE(intel_dp->output_reg, *DP);
2579 POSTING_READ(intel_dp->output_reg);
2581 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
2582 intel_dp->train_set, intel_dp->lane_count);
2584 return ret == intel_dp->lane_count;
2587 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2589 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2590 struct drm_device *dev = intel_dig_port->base.base.dev;
2591 struct drm_i915_private *dev_priv = dev->dev_private;
2592 enum port port = intel_dig_port->port;
2598 val = I915_READ(DP_TP_CTL(port));
2599 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2600 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2601 I915_WRITE(DP_TP_CTL(port), val);
2604 * On PORT_A we can have only eDP in SST mode. There the only reason
2605 * we need to set idle transmission mode is to work around a HW issue
2606 * where we enable the pipe while not in idle link-training mode.
2607 * In this case there is requirement to wait for a minimum number of
2608 * idle patterns to be sent.
2613 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2615 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2618 /* Enable corresponding port and start training pattern 1 */
2620 intel_dp_start_link_train(struct intel_dp *intel_dp)
2622 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2623 struct drm_device *dev = encoder->dev;
2626 int voltage_tries, loop_tries;
2627 uint32_t DP = intel_dp->DP;
2628 uint8_t link_config[2];
2631 intel_ddi_prepare_link_retrain(encoder);
2633 /* Write the link configuration data */
2634 link_config[0] = intel_dp->link_bw;
2635 link_config[1] = intel_dp->lane_count;
2636 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2637 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
2638 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
2641 link_config[1] = DP_SET_ANSI_8B10B;
2642 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
2646 /* clock recovery */
2647 if (!intel_dp_reset_link_train(intel_dp, &DP,
2648 DP_TRAINING_PATTERN_1 |
2649 DP_LINK_SCRAMBLING_DISABLE)) {
2650 DRM_ERROR("failed to enable link training\n");
2658 uint8_t link_status[DP_LINK_STATUS_SIZE];
2660 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2661 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2662 DRM_ERROR("failed to get link status\n");
2666 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2667 DRM_DEBUG_KMS("clock recovery OK\n");
2671 /* Check to see if we've tried the max voltage */
2672 for (i = 0; i < intel_dp->lane_count; i++)
2673 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2675 if (i == intel_dp->lane_count) {
2677 if (loop_tries == 5) {
2678 DRM_ERROR("too many full retries, give up\n");
2681 intel_dp_reset_link_train(intel_dp, &DP,
2682 DP_TRAINING_PATTERN_1 |
2683 DP_LINK_SCRAMBLING_DISABLE);
2688 /* Check to see if we've tried the same voltage 5 times */
2689 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2691 if (voltage_tries == 5) {
2692 DRM_ERROR("too many voltage retries, give up\n");
2697 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
2699 /* Update training set as requested by target */
2700 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2701 DRM_ERROR("failed to update link training\n");
2710 intel_dp_complete_link_train(struct intel_dp *intel_dp)
2712 bool channel_eq = false;
2713 int tries, cr_tries;
2714 uint32_t DP = intel_dp->DP;
2715 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
2717 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
2718 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
2719 training_pattern = DP_TRAINING_PATTERN_3;
2721 /* channel equalization */
2722 if (!intel_dp_set_link_train(intel_dp, &DP,
2724 DP_LINK_SCRAMBLING_DISABLE)) {
2725 DRM_ERROR("failed to start channel equalization\n");
2733 uint8_t link_status[DP_LINK_STATUS_SIZE];
2736 DRM_ERROR("failed to train DP, aborting\n");
2740 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
2741 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2742 DRM_ERROR("failed to get link status\n");
2746 /* Make sure clock is still ok */
2747 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2748 intel_dp_start_link_train(intel_dp);
2749 intel_dp_set_link_train(intel_dp, &DP,
2751 DP_LINK_SCRAMBLING_DISABLE);
2756 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2761 /* Try 5 times, then try clock recovery if that fails */
2763 intel_dp_link_down(intel_dp);
2764 intel_dp_start_link_train(intel_dp);
2765 intel_dp_set_link_train(intel_dp, &DP,
2767 DP_LINK_SCRAMBLING_DISABLE);
2773 /* Update training set as requested by target */
2774 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2775 DRM_ERROR("failed to update link training\n");
2781 intel_dp_set_idle_link_train(intel_dp);
2786 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2790 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2792 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2793 DP_TRAINING_PATTERN_DISABLE);
2797 intel_dp_link_down(struct intel_dp *intel_dp)
2799 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2800 enum port port = intel_dig_port->port;
2801 struct drm_device *dev = intel_dig_port->base.base.dev;
2802 struct drm_i915_private *dev_priv = dev->dev_private;
2803 struct intel_crtc *intel_crtc =
2804 to_intel_crtc(intel_dig_port->base.base.crtc);
2805 uint32_t DP = intel_dp->DP;
2808 * DDI code has a strict mode set sequence and we should try to respect
2809 * it, otherwise we might hang the machine in many different ways. So we
2810 * really should be disabling the port only on a complete crtc_disable
2811 * sequence. This function is just called under two conditions on DDI
2813 * - Link train failed while doing crtc_enable, and on this case we
2814 * really should respect the mode set sequence and wait for a
2816 * - Someone turned the monitor off and intel_dp_check_link_status
2817 * called us. We don't need to disable the whole port on this case, so
2818 * when someone turns the monitor on again,
2819 * intel_ddi_prepare_link_retrain will take care of redoing the link
2825 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2828 DRM_DEBUG_KMS("\n");
2830 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2831 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2832 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2834 DP &= ~DP_LINK_TRAIN_MASK;
2835 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2837 POSTING_READ(intel_dp->output_reg);
2839 /* We don't really know why we're doing this */
2840 intel_wait_for_vblank(dev, intel_crtc->pipe);
2842 if (HAS_PCH_IBX(dev) &&
2843 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2844 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2846 /* Hardware workaround: leaving our transcoder select
2847 * set to transcoder B while it's off will prevent the
2848 * corresponding HDMI output on transcoder A.
2850 * Combine this with another hardware workaround:
2851 * transcoder select bit can only be cleared while the
2854 DP &= ~DP_PIPEB_SELECT;
2855 I915_WRITE(intel_dp->output_reg, DP);
2857 /* Changes to enable or select take place the vblank
2858 * after being written.
2860 if (WARN_ON(crtc == NULL)) {
2861 /* We should never try to disable a port without a crtc
2862 * attached. For paranoia keep the code around for a
2864 POSTING_READ(intel_dp->output_reg);
2867 intel_wait_for_vblank(dev, intel_crtc->pipe);
2870 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2871 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2872 POSTING_READ(intel_dp->output_reg);
2873 msleep(intel_dp->panel_power_down_delay);
2877 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2879 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2880 struct drm_device *dev = dig_port->base.base.dev;
2881 struct drm_i915_private *dev_priv = dev->dev_private;
2883 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2885 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
2886 sizeof(intel_dp->dpcd)) < 0)
2887 return false; /* aux transfer failed */
2889 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2890 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2891 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2893 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2894 return false; /* DPCD not present */
2896 /* Check if the panel supports PSR */
2897 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
2898 if (is_edp(intel_dp)) {
2899 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
2901 sizeof(intel_dp->psr_dpcd));
2902 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
2903 dev_priv->psr.sink_support = true;
2904 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
2908 /* Training Pattern 3 support */
2909 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
2910 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
2911 intel_dp->use_tps3 = true;
2912 DRM_DEBUG_KMS("Displayport TPS3 supported");
2914 intel_dp->use_tps3 = false;
2916 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2917 DP_DWN_STRM_PORT_PRESENT))
2918 return true; /* native DP sink */
2920 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2921 return true; /* no per-port downstream info */
2923 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
2924 intel_dp->downstream_ports,
2925 DP_MAX_DOWNSTREAM_PORTS) < 0)
2926 return false; /* downstream port status fetch failed */
2932 intel_dp_probe_oui(struct intel_dp *intel_dp)
2936 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2939 edp_panel_vdd_on(intel_dp);
2941 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
2942 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2943 buf[0], buf[1], buf[2]);
2945 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
2946 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2947 buf[0], buf[1], buf[2]);
2949 edp_panel_vdd_off(intel_dp, false);
2952 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
2954 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2955 struct drm_device *dev = intel_dig_port->base.base.dev;
2956 struct intel_crtc *intel_crtc =
2957 to_intel_crtc(intel_dig_port->base.base.crtc);
2960 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
2963 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
2966 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
2967 DP_TEST_SINK_START) < 0)
2970 /* Wait 2 vblanks to be sure we will have the correct CRC value */
2971 intel_wait_for_vblank(dev, intel_crtc->pipe);
2972 intel_wait_for_vblank(dev, intel_crtc->pipe);
2974 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
2977 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
2982 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2984 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2985 DP_DEVICE_SERVICE_IRQ_VECTOR,
2986 sink_irq_vector, 1) == 1;
2990 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2992 /* NAK by default */
2993 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
2997 * According to DP spec
3000 * 2. Configure link according to Receiver Capabilities
3001 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3002 * 4. Check link status on receipt of hot-plug interrupt
3006 intel_dp_check_link_status(struct intel_dp *intel_dp)
3008 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
3010 u8 link_status[DP_LINK_STATUS_SIZE];
3012 if (!intel_encoder->connectors_active)
3015 if (WARN_ON(!intel_encoder->base.crtc))
3018 /* Try to read receiver status if the link appears to be up */
3019 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3023 /* Now read the DPCD to see if it's actually running */
3024 if (!intel_dp_get_dpcd(intel_dp)) {
3028 /* Try to read the source of the interrupt */
3029 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3030 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3031 /* Clear interrupt source */
3032 drm_dp_dpcd_writeb(&intel_dp->aux,
3033 DP_DEVICE_SERVICE_IRQ_VECTOR,
3036 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3037 intel_dp_handle_test_request(intel_dp);
3038 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3039 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3042 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3043 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3044 drm_get_encoder_name(&intel_encoder->base));
3045 intel_dp_start_link_train(intel_dp);
3046 intel_dp_complete_link_train(intel_dp);
3047 intel_dp_stop_link_train(intel_dp);
3051 /* XXX this is probably wrong for multiple downstream ports */
3052 static enum drm_connector_status
3053 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
3055 uint8_t *dpcd = intel_dp->dpcd;
3058 if (!intel_dp_get_dpcd(intel_dp))
3059 return connector_status_disconnected;
3061 /* if there's no downstream port, we're done */
3062 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
3063 return connector_status_connected;
3065 /* If we're HPD-aware, SINK_COUNT changes dynamically */
3066 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3067 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
3070 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3072 return connector_status_unknown;
3074 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3075 : connector_status_disconnected;
3078 /* If no HPD, poke DDC gently */
3079 if (drm_probe_ddc(&intel_dp->adapter))
3080 return connector_status_connected;
3082 /* Well we tried, say unknown for unreliable port types */
3083 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3084 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3085 if (type == DP_DS_PORT_TYPE_VGA ||
3086 type == DP_DS_PORT_TYPE_NON_EDID)
3087 return connector_status_unknown;
3089 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3090 DP_DWN_STRM_PORT_TYPE_MASK;
3091 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3092 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3093 return connector_status_unknown;
3096 /* Anything else is out of spec, warn and ignore */
3097 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
3098 return connector_status_disconnected;
3101 static enum drm_connector_status
3102 ironlake_dp_detect(struct intel_dp *intel_dp)
3104 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3105 struct drm_i915_private *dev_priv = dev->dev_private;
3106 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3107 enum drm_connector_status status;
3109 /* Can't disconnect eDP, but you can close the lid... */
3110 if (is_edp(intel_dp)) {
3111 status = intel_panel_detect(dev);
3112 if (status == connector_status_unknown)
3113 status = connector_status_connected;
3117 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3118 return connector_status_disconnected;
3120 return intel_dp_detect_dpcd(intel_dp);
3123 static enum drm_connector_status
3124 g4x_dp_detect(struct intel_dp *intel_dp)
3126 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3127 struct drm_i915_private *dev_priv = dev->dev_private;
3128 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3131 /* Can't disconnect eDP, but you can close the lid... */
3132 if (is_edp(intel_dp)) {
3133 enum drm_connector_status status;
3135 status = intel_panel_detect(dev);
3136 if (status == connector_status_unknown)
3137 status = connector_status_connected;
3141 if (IS_VALLEYVIEW(dev)) {
3142 switch (intel_dig_port->port) {
3144 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3147 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3150 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3153 return connector_status_unknown;
3156 switch (intel_dig_port->port) {
3158 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3161 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3164 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3167 return connector_status_unknown;
3171 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
3172 return connector_status_disconnected;
3174 return intel_dp_detect_dpcd(intel_dp);
3177 static struct edid *
3178 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3180 struct intel_connector *intel_connector = to_intel_connector(connector);
3182 /* use cached edid if we have one */
3183 if (intel_connector->edid) {
3185 if (IS_ERR(intel_connector->edid))
3188 return drm_edid_duplicate(intel_connector->edid);
3191 return drm_get_edid(connector, adapter);
3195 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3197 struct intel_connector *intel_connector = to_intel_connector(connector);
3199 /* use cached edid if we have one */
3200 if (intel_connector->edid) {
3202 if (IS_ERR(intel_connector->edid))
3205 return intel_connector_update_modes(connector,
3206 intel_connector->edid);
3209 return intel_ddc_get_modes(connector, adapter);
3212 static enum drm_connector_status
3213 intel_dp_detect(struct drm_connector *connector, bool force)
3215 struct intel_dp *intel_dp = intel_attached_dp(connector);
3216 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3217 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3218 struct drm_device *dev = connector->dev;
3219 struct drm_i915_private *dev_priv = dev->dev_private;
3220 enum drm_connector_status status;
3221 enum intel_display_power_domain power_domain;
3222 struct edid *edid = NULL;
3224 intel_runtime_pm_get(dev_priv);
3226 power_domain = intel_display_port_power_domain(intel_encoder);
3227 intel_display_power_get(dev_priv, power_domain);
3229 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3230 connector->base.id, drm_get_connector_name(connector));
3232 intel_dp->has_audio = false;
3234 if (HAS_PCH_SPLIT(dev))
3235 status = ironlake_dp_detect(intel_dp);
3237 status = g4x_dp_detect(intel_dp);
3239 if (status != connector_status_connected)
3242 intel_dp_probe_oui(intel_dp);
3244 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3245 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
3247 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
3249 intel_dp->has_audio = drm_detect_monitor_audio(edid);
3254 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3255 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3256 status = connector_status_connected;
3259 intel_display_power_put(dev_priv, power_domain);
3261 intel_runtime_pm_put(dev_priv);
3266 static int intel_dp_get_modes(struct drm_connector *connector)
3268 struct intel_dp *intel_dp = intel_attached_dp(connector);
3269 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3270 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3271 struct intel_connector *intel_connector = to_intel_connector(connector);
3272 struct drm_device *dev = connector->dev;
3273 struct drm_i915_private *dev_priv = dev->dev_private;
3274 enum intel_display_power_domain power_domain;
3277 /* We should parse the EDID data and find out if it has an audio sink
3280 power_domain = intel_display_port_power_domain(intel_encoder);
3281 intel_display_power_get(dev_priv, power_domain);
3283 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
3284 intel_display_power_put(dev_priv, power_domain);
3288 /* if eDP has no EDID, fall back to fixed mode */
3289 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
3290 struct drm_display_mode *mode;
3291 mode = drm_mode_duplicate(dev,
3292 intel_connector->panel.fixed_mode);
3294 drm_mode_probed_add(connector, mode);
3302 intel_dp_detect_audio(struct drm_connector *connector)
3304 struct intel_dp *intel_dp = intel_attached_dp(connector);
3305 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3306 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3307 struct drm_device *dev = connector->dev;
3308 struct drm_i915_private *dev_priv = dev->dev_private;
3309 enum intel_display_power_domain power_domain;
3311 bool has_audio = false;
3313 power_domain = intel_display_port_power_domain(intel_encoder);
3314 intel_display_power_get(dev_priv, power_domain);
3316 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
3318 has_audio = drm_detect_monitor_audio(edid);
3322 intel_display_power_put(dev_priv, power_domain);
3328 intel_dp_set_property(struct drm_connector *connector,
3329 struct drm_property *property,
3332 struct drm_i915_private *dev_priv = connector->dev->dev_private;
3333 struct intel_connector *intel_connector = to_intel_connector(connector);
3334 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3335 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3338 ret = drm_object_property_set_value(&connector->base, property, val);
3342 if (property == dev_priv->force_audio_property) {
3346 if (i == intel_dp->force_audio)
3349 intel_dp->force_audio = i;
3351 if (i == HDMI_AUDIO_AUTO)
3352 has_audio = intel_dp_detect_audio(connector);
3354 has_audio = (i == HDMI_AUDIO_ON);
3356 if (has_audio == intel_dp->has_audio)
3359 intel_dp->has_audio = has_audio;
3363 if (property == dev_priv->broadcast_rgb_property) {
3364 bool old_auto = intel_dp->color_range_auto;
3365 uint32_t old_range = intel_dp->color_range;
3368 case INTEL_BROADCAST_RGB_AUTO:
3369 intel_dp->color_range_auto = true;
3371 case INTEL_BROADCAST_RGB_FULL:
3372 intel_dp->color_range_auto = false;
3373 intel_dp->color_range = 0;
3375 case INTEL_BROADCAST_RGB_LIMITED:
3376 intel_dp->color_range_auto = false;
3377 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3383 if (old_auto == intel_dp->color_range_auto &&
3384 old_range == intel_dp->color_range)
3390 if (is_edp(intel_dp) &&
3391 property == connector->dev->mode_config.scaling_mode_property) {
3392 if (val == DRM_MODE_SCALE_NONE) {
3393 DRM_DEBUG_KMS("no scaling not supported\n");
3397 if (intel_connector->panel.fitting_mode == val) {
3398 /* the eDP scaling property is not changed */
3401 intel_connector->panel.fitting_mode = val;
3409 if (intel_encoder->base.crtc)
3410 intel_crtc_restore_mode(intel_encoder->base.crtc);
3416 intel_dp_connector_destroy(struct drm_connector *connector)
3418 struct intel_connector *intel_connector = to_intel_connector(connector);
3420 if (!IS_ERR_OR_NULL(intel_connector->edid))
3421 kfree(intel_connector->edid);
3423 /* Can't call is_edp() since the encoder may have been destroyed
3425 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3426 intel_panel_fini(&intel_connector->panel);
3428 drm_connector_cleanup(connector);
3432 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
3434 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3435 struct intel_dp *intel_dp = &intel_dig_port->dp;
3436 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3438 i2c_del_adapter(&intel_dp->adapter);
3439 drm_encoder_cleanup(encoder);
3440 if (is_edp(intel_dp)) {
3441 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3442 mutex_lock(&dev->mode_config.mutex);
3443 edp_panel_vdd_off_sync(intel_dp);
3444 mutex_unlock(&dev->mode_config.mutex);
3446 kfree(intel_dig_port);
3449 static const struct drm_connector_funcs intel_dp_connector_funcs = {
3450 .dpms = intel_connector_dpms,
3451 .detect = intel_dp_detect,
3452 .fill_modes = drm_helper_probe_single_connector_modes,
3453 .set_property = intel_dp_set_property,
3454 .destroy = intel_dp_connector_destroy,
3457 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3458 .get_modes = intel_dp_get_modes,
3459 .mode_valid = intel_dp_mode_valid,
3460 .best_encoder = intel_best_encoder,
3463 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
3464 .destroy = intel_dp_encoder_destroy,
3468 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
3470 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3472 intel_dp_check_link_status(intel_dp);
3475 /* Return which DP Port should be selected for Transcoder DP control */
3477 intel_trans_dp_port_sel(struct drm_crtc *crtc)
3479 struct drm_device *dev = crtc->dev;
3480 struct intel_encoder *intel_encoder;
3481 struct intel_dp *intel_dp;
3483 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3484 intel_dp = enc_to_intel_dp(&intel_encoder->base);
3486 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3487 intel_encoder->type == INTEL_OUTPUT_EDP)
3488 return intel_dp->output_reg;
3494 /* check the VBT to see whether the eDP is on DP-D port */
3495 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
3497 struct drm_i915_private *dev_priv = dev->dev_private;
3498 union child_device_config *p_child;
3500 static const short port_mapping[] = {
3501 [PORT_B] = PORT_IDPB,
3502 [PORT_C] = PORT_IDPC,
3503 [PORT_D] = PORT_IDPD,
3509 if (!dev_priv->vbt.child_dev_num)
3512 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3513 p_child = dev_priv->vbt.child_dev + i;
3515 if (p_child->common.dvo_port == port_mapping[port] &&
3516 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3517 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
3524 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3526 struct intel_connector *intel_connector = to_intel_connector(connector);
3528 intel_attach_force_audio_property(connector);
3529 intel_attach_broadcast_rgb_property(connector);
3530 intel_dp->color_range_auto = true;
3532 if (is_edp(intel_dp)) {
3533 drm_mode_create_scaling_mode_property(connector->dev);
3534 drm_object_attach_property(
3536 connector->dev->mode_config.scaling_mode_property,
3537 DRM_MODE_SCALE_ASPECT);
3538 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
3542 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
3544 intel_dp->last_power_cycle = jiffies;
3545 intel_dp->last_power_on = jiffies;
3546 intel_dp->last_backlight_off = jiffies;
3550 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
3551 struct intel_dp *intel_dp,
3552 struct edp_power_seq *out)
3554 struct drm_i915_private *dev_priv = dev->dev_private;
3555 struct edp_power_seq cur, vbt, spec, final;
3556 u32 pp_on, pp_off, pp_div, pp;
3557 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
3559 if (HAS_PCH_SPLIT(dev)) {
3560 pp_ctrl_reg = PCH_PP_CONTROL;
3561 pp_on_reg = PCH_PP_ON_DELAYS;
3562 pp_off_reg = PCH_PP_OFF_DELAYS;
3563 pp_div_reg = PCH_PP_DIVISOR;
3565 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3567 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3568 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3569 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3570 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3573 /* Workaround: Need to write PP_CONTROL with the unlock key as
3574 * the very first thing. */
3575 pp = ironlake_get_pp_control(intel_dp);
3576 I915_WRITE(pp_ctrl_reg, pp);
3578 pp_on = I915_READ(pp_on_reg);
3579 pp_off = I915_READ(pp_off_reg);
3580 pp_div = I915_READ(pp_div_reg);
3582 /* Pull timing values out of registers */
3583 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3584 PANEL_POWER_UP_DELAY_SHIFT;
3586 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3587 PANEL_LIGHT_ON_DELAY_SHIFT;
3589 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3590 PANEL_LIGHT_OFF_DELAY_SHIFT;
3592 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3593 PANEL_POWER_DOWN_DELAY_SHIFT;
3595 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3596 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3598 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3599 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3601 vbt = dev_priv->vbt.edp_pps;
3603 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3604 * our hw here, which are all in 100usec. */
3605 spec.t1_t3 = 210 * 10;
3606 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3607 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3608 spec.t10 = 500 * 10;
3609 /* This one is special and actually in units of 100ms, but zero
3610 * based in the hw (so we need to add 100 ms). But the sw vbt
3611 * table multiplies it with 1000 to make it in units of 100usec,
3613 spec.t11_t12 = (510 + 100) * 10;
3615 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3616 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3618 /* Use the max of the register settings and vbt. If both are
3619 * unset, fall back to the spec limits. */
3620 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3622 max(cur.field, vbt.field))
3623 assign_final(t1_t3);
3627 assign_final(t11_t12);
3630 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3631 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3632 intel_dp->backlight_on_delay = get_delay(t8);
3633 intel_dp->backlight_off_delay = get_delay(t9);
3634 intel_dp->panel_power_down_delay = get_delay(t10);
3635 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3638 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3639 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3640 intel_dp->panel_power_cycle_delay);
3642 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3643 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3650 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3651 struct intel_dp *intel_dp,
3652 struct edp_power_seq *seq)
3654 struct drm_i915_private *dev_priv = dev->dev_private;
3655 u32 pp_on, pp_off, pp_div, port_sel = 0;
3656 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3657 int pp_on_reg, pp_off_reg, pp_div_reg;
3659 if (HAS_PCH_SPLIT(dev)) {
3660 pp_on_reg = PCH_PP_ON_DELAYS;
3661 pp_off_reg = PCH_PP_OFF_DELAYS;
3662 pp_div_reg = PCH_PP_DIVISOR;
3664 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3666 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3667 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3668 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3672 * And finally store the new values in the power sequencer. The
3673 * backlight delays are set to 1 because we do manual waits on them. For
3674 * T8, even BSpec recommends doing it. For T9, if we don't do this,
3675 * we'll end up waiting for the backlight off delay twice: once when we
3676 * do the manual sleep, and once when we disable the panel and wait for
3677 * the PP_STATUS bit to become zero.
3679 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
3680 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
3681 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
3682 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
3683 /* Compute the divisor for the pp clock, simply match the Bspec
3685 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
3686 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
3687 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3689 /* Haswell doesn't have any port selection bits for the panel
3690 * power sequencer any more. */
3691 if (IS_VALLEYVIEW(dev)) {
3692 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3693 port_sel = PANEL_PORT_SELECT_DPB_VLV;
3695 port_sel = PANEL_PORT_SELECT_DPC_VLV;
3696 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3697 if (dp_to_dig_port(intel_dp)->port == PORT_A)
3698 port_sel = PANEL_PORT_SELECT_DPA;
3700 port_sel = PANEL_PORT_SELECT_DPD;
3705 I915_WRITE(pp_on_reg, pp_on);
3706 I915_WRITE(pp_off_reg, pp_off);
3707 I915_WRITE(pp_div_reg, pp_div);
3709 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
3710 I915_READ(pp_on_reg),
3711 I915_READ(pp_off_reg),
3712 I915_READ(pp_div_reg));
3715 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
3716 struct intel_connector *intel_connector,
3717 struct edp_power_seq *power_seq)
3719 struct drm_connector *connector = &intel_connector->base;
3720 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3721 struct drm_device *dev = intel_dig_port->base.base.dev;
3722 struct drm_i915_private *dev_priv = dev->dev_private;
3723 struct drm_display_mode *fixed_mode = NULL;
3725 struct drm_display_mode *scan;
3728 if (!is_edp(intel_dp))
3731 /* Cache DPCD and EDID for edp. */
3732 edp_panel_vdd_on(intel_dp);
3733 has_dpcd = intel_dp_get_dpcd(intel_dp);
3734 edp_panel_vdd_off(intel_dp, false);
3737 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3738 dev_priv->no_aux_handshake =
3739 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3740 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3742 /* if this fails, presume the device is a ghost */
3743 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3747 /* We now know it's not a ghost, init power sequence regs. */
3748 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
3750 edid = drm_get_edid(connector, &intel_dp->adapter);
3752 if (drm_add_edid_modes(connector, edid)) {
3753 drm_mode_connector_update_edid_property(connector,
3755 drm_edid_to_eld(connector, edid);
3758 edid = ERR_PTR(-EINVAL);
3761 edid = ERR_PTR(-ENOENT);
3763 intel_connector->edid = edid;
3765 /* prefer fixed mode from EDID if available */
3766 list_for_each_entry(scan, &connector->probed_modes, head) {
3767 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3768 fixed_mode = drm_mode_duplicate(dev, scan);
3773 /* fallback to VBT if available for eDP */
3774 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3775 fixed_mode = drm_mode_duplicate(dev,
3776 dev_priv->vbt.lfp_lvds_vbt_mode);
3778 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3781 intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
3782 intel_panel_setup_backlight(connector);
3788 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3789 struct intel_connector *intel_connector)
3791 struct drm_connector *connector = &intel_connector->base;
3792 struct intel_dp *intel_dp = &intel_dig_port->dp;
3793 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3794 struct drm_device *dev = intel_encoder->base.dev;
3795 struct drm_i915_private *dev_priv = dev->dev_private;
3796 enum port port = intel_dig_port->port;
3797 struct edp_power_seq power_seq = { 0 };
3798 const char *name = NULL;
3801 /* intel_dp vfuncs */
3802 if (IS_VALLEYVIEW(dev))
3803 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
3804 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3805 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
3806 else if (HAS_PCH_SPLIT(dev))
3807 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
3809 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
3811 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
3813 /* Preserve the current hw state. */
3814 intel_dp->DP = I915_READ(intel_dp->output_reg);
3815 intel_dp->attached_connector = intel_connector;
3817 if (intel_dp_is_edp(dev, port))
3818 type = DRM_MODE_CONNECTOR_eDP;
3820 type = DRM_MODE_CONNECTOR_DisplayPort;
3823 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3824 * for DP the encoder type can be set by the caller to
3825 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3827 if (type == DRM_MODE_CONNECTOR_eDP)
3828 intel_encoder->type = INTEL_OUTPUT_EDP;
3830 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3831 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3834 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
3835 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3837 connector->interlace_allowed = true;
3838 connector->doublescan_allowed = 0;
3840 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3841 edp_panel_vdd_work);
3843 intel_connector_attach_encoder(intel_connector, intel_encoder);
3844 drm_sysfs_connector_add(connector);
3847 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3849 intel_connector->get_hw_state = intel_connector_get_hw_state;
3850 intel_connector->unregister = intel_dp_connector_unregister;
3852 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3854 switch (intel_dig_port->port) {
3856 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3859 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3862 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3865 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3872 /* Set up the DDC bus. */
3875 intel_encoder->hpd_pin = HPD_PORT_A;
3879 intel_encoder->hpd_pin = HPD_PORT_B;
3883 intel_encoder->hpd_pin = HPD_PORT_C;
3887 intel_encoder->hpd_pin = HPD_PORT_D;
3894 if (is_edp(intel_dp)) {
3895 intel_dp_init_panel_power_timestamps(intel_dp);
3896 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3899 intel_dp_aux_init(intel_dp, intel_connector);
3901 error = intel_dp_i2c_init(intel_dp, intel_connector, name);
3902 WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
3903 error, port_name(port));
3905 intel_dp->psr_setup_done = false;
3907 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
3908 i2c_del_adapter(&intel_dp->adapter);
3909 if (is_edp(intel_dp)) {
3910 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3911 mutex_lock(&dev->mode_config.mutex);
3912 edp_panel_vdd_off_sync(intel_dp);
3913 mutex_unlock(&dev->mode_config.mutex);
3915 drm_sysfs_connector_remove(connector);
3916 drm_connector_cleanup(connector);
3920 intel_dp_add_properties(intel_dp, connector);
3922 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3923 * 0xd. Failure to do so will result in spurious interrupts being
3924 * generated on the port when a cable is not attached.
3926 if (IS_G4X(dev) && !IS_GM45(dev)) {
3927 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3928 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3935 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3937 struct intel_digital_port *intel_dig_port;
3938 struct intel_encoder *intel_encoder;
3939 struct drm_encoder *encoder;
3940 struct intel_connector *intel_connector;
3942 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3943 if (!intel_dig_port)
3946 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
3947 if (!intel_connector) {
3948 kfree(intel_dig_port);
3952 intel_encoder = &intel_dig_port->base;
3953 encoder = &intel_encoder->base;
3955 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3956 DRM_MODE_ENCODER_TMDS);
3958 intel_encoder->compute_config = intel_dp_compute_config;
3959 intel_encoder->mode_set = intel_dp_mode_set;
3960 intel_encoder->disable = intel_disable_dp;
3961 intel_encoder->post_disable = intel_post_disable_dp;
3962 intel_encoder->get_hw_state = intel_dp_get_hw_state;
3963 intel_encoder->get_config = intel_dp_get_config;
3964 if (IS_VALLEYVIEW(dev)) {
3965 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
3966 intel_encoder->pre_enable = vlv_pre_enable_dp;
3967 intel_encoder->enable = vlv_enable_dp;
3969 intel_encoder->pre_enable = g4x_pre_enable_dp;
3970 intel_encoder->enable = g4x_enable_dp;
3973 intel_dig_port->port = port;
3974 intel_dig_port->dp.output_reg = output_reg;
3976 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3977 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3978 intel_encoder->cloneable = false;
3979 intel_encoder->hot_plug = intel_dp_hot_plug;
3981 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3982 drm_encoder_cleanup(encoder);
3983 kfree(intel_dig_port);
3984 kfree(intel_connector);