drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_edid.h>
  35 #include "intel_drv.h"
  36 #include <drm/i915_drm.h>
  37 #include "i915_drv.h"
  38
  39 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  40
  41 struct dp_link_dpll {
  42         int link_bw;
  43         struct dpll dpll;
  44 };
  45
  46 static const struct dp_link_dpll gen4_dpll[] = {
  47         { DP_LINK_BW_1_62,
  48                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  49         { DP_LINK_BW_2_7,
  50                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  51 };
  52
  53 static const struct dp_link_dpll pch_dpll[] = {
  54         { DP_LINK_BW_1_62,
  55                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  56         { DP_LINK_BW_2_7,
  57                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  58 };
  59
  60 static const struct dp_link_dpll vlv_dpll[] = {
  61         { DP_LINK_BW_1_62,
  62                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  63         { DP_LINK_BW_2_7,
  64                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  65 };
  66
  67 /*
  68  * CHV supports eDP 1.4 that have  more link rates.
  69  * Below only provides the fixed rate but exclude variable rate.
  70  */
  71 static const struct dp_link_dpll chv_dpll[] = {
  72         /*
  73          * CHV requires to program fractional division for m2.
  74          * m2 is stored in fixed point format using formula below
  75          * (m2_int << 22) | m2_fraction
  76          */
  77         { DP_LINK_BW_1_62,      /* m2_int = 32, m2_fraction = 1677722 */
  78                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
  79         { DP_LINK_BW_2_7,       /* m2_int = 27, m2_fraction = 0 */
  80                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
  81         { DP_LINK_BW_5_4,       /* m2_int = 27, m2_fraction = 0 */
  82                 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
  83 };
  84
  85 /**
  86  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  87  * @intel_dp: DP struct
  88  *
  89  * If a CPU or PCH DP output is attached to an eDP panel, this function
  90  * will return true, and false otherwise.
  91  */
  92 static bool is_edp(struct intel_dp *intel_dp)
  93 {
  94         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  95
  96         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
  97 }
  98
  99 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
 100 {
 101         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 102
 103         return intel_dig_port->base.base.dev;
 104 }
 105
 106 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 107 {
 108         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 109 }
 110
 111 static void intel_dp_link_down(struct intel_dp *intel_dp);
 112 static bool _edp_panel_vdd_on(struct intel_dp *intel_dp);
 113 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 114
 115 static int
 116 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 117 {
 118         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 119         struct drm_device *dev = intel_dp->attached_connector->base.dev;
 120
 121         switch (max_link_bw) {
 122         case DP_LINK_BW_1_62:
 123         case DP_LINK_BW_2_7:
 124                 break;
 125         case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
 126                 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
 127                      INTEL_INFO(dev)->gen >= 8) &&
 128                     intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
 129                         max_link_bw = DP_LINK_BW_5_4;
 130                 else
 131                         max_link_bw = DP_LINK_BW_2_7;
 132                 break;
 133         default:
 134                 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
 135                      max_link_bw);
 136                 max_link_bw = DP_LINK_BW_1_62;
 137                 break;
 138         }
 139         return max_link_bw;
 140 }
 141
 142 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 143 {
 144         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 145         struct drm_device *dev = intel_dig_port->base.base.dev;
 146         u8 source_max, sink_max;
 147
 148         source_max = 4;
 149         if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
 150             (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
 151                 source_max = 2;
 152
 153         sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 154
 155         return min(source_max, sink_max);
 156 }
 157
 158 /*
 159  * The units on the numbers in the next two are... bizarre.  Examples will
 160  * make it clearer; this one parallels an example in the eDP spec.
 161  *
 162  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 163  *
 164  *     270000 * 1 * 8 / 10 == 216000
 165  *
 166  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 167  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 168  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 169  * 119000.  At 18bpp that's 2142000 kilobits per second.
 170  *
 171  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 172  * get the result in decakilobits instead of kilobits.
 173  */
 174
 175 static int
 176 intel_dp_link_required(int pixel_clock, int bpp)
 177 {
 178         return (pixel_clock * bpp + 9) / 10;
 179 }
 180
 181 static int
 182 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 183 {
 184         return (max_link_clock * max_lanes * 8) / 10;
 185 }
 186
 187 static enum drm_mode_status
 188 intel_dp_mode_valid(struct drm_connector *connector,
 189                     struct drm_display_mode *mode)
 190 {
 191         struct intel_dp *intel_dp = intel_attached_dp(connector);
 192         struct intel_connector *intel_connector = to_intel_connector(connector);
 193         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 194         int target_clock = mode->clock;
 195         int max_rate, mode_rate, max_lanes, max_link_clock;
 196
 197         if (is_edp(intel_dp) && fixed_mode) {
 198                 if (mode->hdisplay > fixed_mode->hdisplay)
 199                         return MODE_PANEL;
 200
 201                 if (mode->vdisplay > fixed_mode->vdisplay)
 202                         return MODE_PANEL;
 203
 204                 target_clock = fixed_mode->clock;
 205         }
 206
 207         max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
 208         max_lanes = intel_dp_max_lane_count(intel_dp);
 209
 210         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 211         mode_rate = intel_dp_link_required(target_clock, 18);
 212
 213         if (mode_rate > max_rate)
 214                 return MODE_CLOCK_HIGH;
 215
 216         if (mode->clock < 10000)
 217                 return MODE_CLOCK_LOW;
 218
 219         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 220                 return MODE_H_ILLEGAL;
 221
 222         return MODE_OK;
 223 }
 224
 225 static uint32_t
 226 pack_aux(uint8_t *src, int src_bytes)
 227 {
 228         int     i;
 229         uint32_t v = 0;
 230
 231         if (src_bytes > 4)
 232                 src_bytes = 4;
 233         for (i = 0; i < src_bytes; i++)
 234                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 235         return v;
 236 }
 237
 238 static void
 239 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 240 {
 241         int i;
 242         if (dst_bytes > 4)
 243                 dst_bytes = 4;
 244         for (i = 0; i < dst_bytes; i++)
 245                 dst[i] = src >> ((3-i) * 8);
 246 }
 247
 248 /* hrawclock is 1/4 the FSB frequency */
 249 static int
 250 intel_hrawclk(struct drm_device *dev)
 251 {
 252         struct drm_i915_private *dev_priv = dev->dev_private;
 253         uint32_t clkcfg;
 254
 255         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 256         if (IS_VALLEYVIEW(dev))
 257                 return 200;
 258
 259         clkcfg = I915_READ(CLKCFG);
 260         switch (clkcfg & CLKCFG_FSB_MASK) {
 261         case CLKCFG_FSB_400:
 262                 return 100;
 263         case CLKCFG_FSB_533:
 264                 return 133;
 265         case CLKCFG_FSB_667:
 266                 return 166;
 267         case CLKCFG_FSB_800:
 268                 return 200;
 269         case CLKCFG_FSB_1067:
 270                 return 266;
 271         case CLKCFG_FSB_1333:
 272                 return 333;
 273         /* these two are just a guess; one of them might be right */
 274         case CLKCFG_FSB_1600:
 275         case CLKCFG_FSB_1600_ALT:
 276                 return 400;
 277         default:
 278                 return 133;
 279         }
 280 }
 281
 282 static void
 283 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 284                                     struct intel_dp *intel_dp,
 285                                     struct edp_power_seq *out);
 286 static void
 287 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 288                                               struct intel_dp *intel_dp,
 289                                               struct edp_power_seq *out);
 290
 291 static enum pipe
 292 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 293 {
 294         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 295         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
 296         struct drm_device *dev = intel_dig_port->base.base.dev;
 297         struct drm_i915_private *dev_priv = dev->dev_private;
 298         enum port port = intel_dig_port->port;
 299         enum pipe pipe;
 300
 301         /* modeset should have pipe */
 302         if (crtc)
 303                 return to_intel_crtc(crtc)->pipe;
 304
 305         /* init time, try to find a pipe with this port selected */
 306         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 307                 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
 308                         PANEL_PORT_SELECT_MASK;
 309                 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
 310                         return pipe;
 311                 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
 312                         return pipe;
 313         }
 314
 315         /* shrug */
 316         return PIPE_A;
 317 }
 318
 319 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
 320 {
 321         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 322
 323         if (HAS_PCH_SPLIT(dev))
 324                 return PCH_PP_CONTROL;
 325         else
 326                 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
 327 }
 328
 329 static u32 _pp_stat_reg(struct intel_dp *intel_dp)
 330 {
 331         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 332
 333         if (HAS_PCH_SPLIT(dev))
 334                 return PCH_PP_STATUS;
 335         else
 336                 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
 337 }
 338
 339 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 340 {
 341         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 342         struct drm_i915_private *dev_priv = dev->dev_private;
 343
 344         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 345 }
 346
 347 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 348 {
 349         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 350         struct drm_i915_private *dev_priv = dev->dev_private;
 351         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 352         struct intel_encoder *intel_encoder = &intel_dig_port->base;
 353         enum intel_display_power_domain power_domain;
 354
 355         power_domain = intel_display_port_power_domain(intel_encoder);
 356         return intel_display_power_enabled(dev_priv, power_domain) &&
 357                (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
 358 }
 359
 360 static void
 361 intel_dp_check_edp(struct intel_dp *intel_dp)
 362 {
 363         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 364         struct drm_i915_private *dev_priv = dev->dev_private;
 365
 366         if (!is_edp(intel_dp))
 367                 return;
 368
 369         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 370                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 371                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 372                               I915_READ(_pp_stat_reg(intel_dp)),
 373                               I915_READ(_pp_ctrl_reg(intel_dp)));
 374         }
 375 }
 376
 377 static uint32_t
 378 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 379 {
 380         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 381         struct drm_device *dev = intel_dig_port->base.base.dev;
 382         struct drm_i915_private *dev_priv = dev->dev_private;
 383         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 384         uint32_t status;
 385         bool done;
 386
 387 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 388         if (has_aux_irq)
 389                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 390                                           msecs_to_jiffies_timeout(10));
 391         else
 392                 done = wait_for_atomic(C, 10) == 0;
 393         if (!done)
 394                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 395                           has_aux_irq);
 396 #undef C
 397
 398         return status;
 399 }
 400
 401 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 402 {
 403         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 404         struct drm_device *dev = intel_dig_port->base.base.dev;
 405
 406         /*
 407          * The clock divider is based off the hrawclk, and would like to run at
 408          * 2MHz.  So, take the hrawclk value and divide by 2 and use that
 409          */
 410         return index ? 0 : intel_hrawclk(dev) / 2;
 411 }
 412
 413 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 414 {
 415         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 416         struct drm_device *dev = intel_dig_port->base.base.dev;
 417
 418         if (index)
 419                 return 0;
 420
 421         if (intel_dig_port->port == PORT_A) {
 422                 if (IS_GEN6(dev) || IS_GEN7(dev))
 423                         return 200; /* SNB & IVB eDP input clock at 400Mhz */
 424                 else
 425                         return 225; /* eDP input clock at 450Mhz */
 426         } else {
 427                 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 428         }
 429 }
 430
 431 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 432 {
 433         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 434         struct drm_device *dev = intel_dig_port->base.base.dev;
 435         struct drm_i915_private *dev_priv = dev->dev_private;
 436
 437         if (intel_dig_port->port == PORT_A) {
 438                 if (index)
 439                         return 0;
 440                 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
 441         } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 442                 /* Workaround for non-ULT HSW */
 443                 switch (index) {
 444                 case 0: return 63;
 445                 case 1: return 72;
 446                 default: return 0;
 447                 }
 448         } else  {
 449                 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 450         }
 451 }
 452
 453 static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 454 {
 455         return index ? 0 : 100;
 456 }
 457
 458 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
 459                                       bool has_aux_irq,
 460                                       int send_bytes,
 461                                       uint32_t aux_clock_divider)
 462 {
 463         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 464         struct drm_device *dev = intel_dig_port->base.base.dev;
 465         uint32_t precharge, timeout;
 466
 467         if (IS_GEN6(dev))
 468                 precharge = 3;
 469         else
 470                 precharge = 5;
 471
 472         if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
 473                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
 474         else
 475                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
 476
 477         return DP_AUX_CH_CTL_SEND_BUSY |
 478                DP_AUX_CH_CTL_DONE |
 479                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 480                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 481                timeout |
 482                DP_AUX_CH_CTL_RECEIVE_ERROR |
 483                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 484                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 485                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
 486 }
 487
 488 static int
 489 intel_dp_aux_ch(struct intel_dp *intel_dp,
 490                 uint8_t *send, int send_bytes,
 491                 uint8_t *recv, int recv_size)
 492 {
 493         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 494         struct drm_device *dev = intel_dig_port->base.base.dev;
 495         struct drm_i915_private *dev_priv = dev->dev_private;
 496         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 497         uint32_t ch_data = ch_ctl + 4;
 498         uint32_t aux_clock_divider;
 499         int i, ret, recv_bytes;
 500         uint32_t status;
 501         int try, clock = 0;
 502         bool has_aux_irq = HAS_AUX_IRQ(dev);
 503         bool vdd;
 504
 505         vdd = _edp_panel_vdd_on(intel_dp);
 506
 507         /* dp aux is extremely sensitive to irq latency, hence request the
 508          * lowest possible wakeup latency and so prevent the cpu from going into
 509          * deep sleep states.
 510          */
 511         pm_qos_update_request(&dev_priv->pm_qos, 0);
 512
 513         intel_dp_check_edp(intel_dp);
 514
 515         intel_aux_display_runtime_get(dev_priv);
 516
 517         /* Try to wait for any previous AUX channel activity */
 518         for (try = 0; try < 3; try++) {
 519                 status = I915_READ_NOTRACE(ch_ctl);
 520                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 521                         break;
 522                 msleep(1);
 523         }
 524
 525         if (try == 3) {
 526                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 527                      I915_READ(ch_ctl));
 528                 ret = -EBUSY;
 529                 goto out;
 530         }
 531
 532         /* Only 5 data registers! */
 533         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
 534                 ret = -E2BIG;
 535                 goto out;
 536         }
 537
 538         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
 539                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
 540                                                           has_aux_irq,
 541                                                           send_bytes,
 542                                                           aux_clock_divider);
 543
 544                 /* Must try at least 3 times according to DP spec */
 545                 for (try = 0; try < 5; try++) {
 546                         /* Load the send data into the aux channel data registers */
 547                         for (i = 0; i < send_bytes; i += 4)
 548                                 I915_WRITE(ch_data + i,
 549                                            pack_aux(send + i, send_bytes - i));
 550
 551                         /* Send the command and wait for it to complete */
 552                         I915_WRITE(ch_ctl, send_ctl);
 553
 554                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
 555
 556                         /* Clear done status and any errors */
 557                         I915_WRITE(ch_ctl,
 558                                    status |
 559                                    DP_AUX_CH_CTL_DONE |
 560                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
 561                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
 562
 563                         if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
 564                                       DP_AUX_CH_CTL_RECEIVE_ERROR))
 565                                 continue;
 566                         if (status & DP_AUX_CH_CTL_DONE)
 567                                 break;
 568                 }
 569                 if (status & DP_AUX_CH_CTL_DONE)
 570                         break;
 571         }
 572
 573         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 574                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 575                 ret = -EBUSY;
 576                 goto out;
 577         }
 578
 579         /* Check for timeout or receive error.
 580          * Timeouts occur when the sink is not connected
 581          */
 582         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 583                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 584                 ret = -EIO;
 585                 goto out;
 586         }
 587
 588         /* Timeouts occur when the device isn't connected, so they're
 589          * "normal" -- don't fill the kernel log with these */
 590         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 591                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 592                 ret = -ETIMEDOUT;
 593                 goto out;
 594         }
 595
 596         /* Unload any bytes sent back from the other side */
 597         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 598                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 599         if (recv_bytes > recv_size)
 600                 recv_bytes = recv_size;
 601
 602         for (i = 0; i < recv_bytes; i += 4)
 603                 unpack_aux(I915_READ(ch_data + i),
 604                            recv + i, recv_bytes - i);
 605
 606         ret = recv_bytes;
 607 out:
 608         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 609         intel_aux_display_runtime_put(dev_priv);
 610
 611         if (vdd)
 612                 edp_panel_vdd_off(intel_dp, false);
 613
 614         return ret;
 615 }
 616
 617 #define BARE_ADDRESS_SIZE       3
 618 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
 619 static ssize_t
 620 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
 621 {
 622         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
 623         uint8_t txbuf[20], rxbuf[20];
 624         size_t txsize, rxsize;
 625         int ret;
 626
 627         txbuf[0] = msg->request << 4;
 628         txbuf[1] = msg->address >> 8;
 629         txbuf[2] = msg->address & 0xff;
 630         txbuf[3] = msg->size - 1;
 631
 632         switch (msg->request & ~DP_AUX_I2C_MOT) {
 633         case DP_AUX_NATIVE_WRITE:
 634         case DP_AUX_I2C_WRITE:
 635                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
 636                 rxsize = 1;
 637
 638                 if (WARN_ON(txsize > 20))
 639                         return -E2BIG;
 640
 641                 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
 642
 643                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
 644                 if (ret > 0) {
 645                         msg->reply = rxbuf[0] >> 4;
 646
 647                         /* Return payload size. */
 648                         ret = msg->size;
 649                 }
 650                 break;
 651
 652         case DP_AUX_NATIVE_READ:
 653         case DP_AUX_I2C_READ:
 654                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
 655                 rxsize = msg->size + 1;
 656
 657                 if (WARN_ON(rxsize > 20))
 658                         return -E2BIG;
 659
 660                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
 661                 if (ret > 0) {
 662                         msg->reply = rxbuf[0] >> 4;
 663                         /*
 664                          * Assume happy day, and copy the data. The caller is
 665                          * expected to check msg->reply before touching it.
 666                          *
 667                          * Return payload size.
 668                          */
 669                         ret--;
 670                         memcpy(msg->buffer, rxbuf + 1, ret);
 671                 }
 672                 break;
 673
 674         default:
 675                 ret = -EINVAL;
 676                 break;
 677         }
 678
 679         return ret;
 680 }
 681
 682 static void
 683 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
 684 {
 685         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 686         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 687         enum port port = intel_dig_port->port;
 688         const char *name = NULL;
 689         int ret;
 690
 691         switch (port) {
 692         case PORT_A:
 693                 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
 694                 name = "DPDDC-A";
 695                 break;
 696         case PORT_B:
 697                 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
 698                 name = "DPDDC-B";
 699                 break;
 700         case PORT_C:
 701                 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
 702                 name = "DPDDC-C";
 703                 break;
 704         case PORT_D:
 705                 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
 706                 name = "DPDDC-D";
 707                 break;
 708         default:
 709                 BUG();
 710         }
 711
 712         if (!HAS_DDI(dev))
 713                 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
 714
 715         intel_dp->aux.name = name;
 716         intel_dp->aux.dev = dev->dev;
 717         intel_dp->aux.transfer = intel_dp_aux_transfer;
 718
 719         DRM_DEBUG_KMS("registering %s bus for %s\n", name,
 720                       connector->base.kdev->kobj.name);
 721
 722         ret = drm_dp_aux_register(&intel_dp->aux);
 723         if (ret < 0) {
 724                 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
 725                           name, ret);
 726                 return;
 727         }
 728
 729         ret = sysfs_create_link(&connector->base.kdev->kobj,
 730                                 &intel_dp->aux.ddc.dev.kobj,
 731                                 intel_dp->aux.ddc.dev.kobj.name);
 732         if (ret < 0) {
 733                 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
 734                 drm_dp_aux_unregister(&intel_dp->aux);
 735         }
 736 }
 737
 738 static void
 739 intel_dp_connector_unregister(struct intel_connector *intel_connector)
 740 {
 741         struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
 742
 743         sysfs_remove_link(&intel_connector->base.kdev->kobj,
 744                           intel_dp->aux.ddc.dev.kobj.name);
 745         intel_connector_unregister(intel_connector);
 746 }
 747
 748 static void
 749 intel_dp_set_clock(struct intel_encoder *encoder,
 750                    struct intel_crtc_config *pipe_config, int link_bw)
 751 {
 752         struct drm_device *dev = encoder->base.dev;
 753         const struct dp_link_dpll *divisor = NULL;
 754         int i, count = 0;
 755
 756         if (IS_G4X(dev)) {
 757                 divisor = gen4_dpll;
 758                 count = ARRAY_SIZE(gen4_dpll);
 759         } else if (IS_HASWELL(dev)) {
 760                 /* Haswell has special-purpose DP DDI clocks. */
 761         } else if (HAS_PCH_SPLIT(dev)) {
 762                 divisor = pch_dpll;
 763                 count = ARRAY_SIZE(pch_dpll);
 764         } else if (IS_CHERRYVIEW(dev)) {
 765                 divisor = chv_dpll;
 766                 count = ARRAY_SIZE(chv_dpll);
 767         } else if (IS_VALLEYVIEW(dev)) {
 768                 divisor = vlv_dpll;
 769                 count = ARRAY_SIZE(vlv_dpll);
 770         }
 771
 772         if (divisor && count) {
 773                 for (i = 0; i < count; i++) {
 774                         if (link_bw == divisor[i].link_bw) {
 775                                 pipe_config->dpll = divisor[i].dpll;
 776                                 pipe_config->clock_set = true;
 777                                 break;
 778                         }
 779                 }
 780         }
 781 }
 782
 783 static void
 784 intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
 785 {
 786         struct drm_device *dev = crtc->base.dev;
 787         struct drm_i915_private *dev_priv = dev->dev_private;
 788         enum transcoder transcoder = crtc->config.cpu_transcoder;
 789
 790         I915_WRITE(PIPE_DATA_M2(transcoder),
 791                 TU_SIZE(m_n->tu) | m_n->gmch_m);
 792         I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
 793         I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
 794         I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
 795 }
 796
 797 bool
 798 intel_dp_compute_config(struct intel_encoder *encoder,
 799                         struct intel_crtc_config *pipe_config)
 800 {
 801         struct drm_device *dev = encoder->base.dev;
 802         struct drm_i915_private *dev_priv = dev->dev_private;
 803         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
 804         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 805         enum port port = dp_to_dig_port(intel_dp)->port;
 806         struct intel_crtc *intel_crtc = encoder->new_crtc;
 807         struct intel_connector *intel_connector = intel_dp->attached_connector;
 808         int lane_count, clock;
 809         int min_lane_count = 1;
 810         int max_lane_count = intel_dp_max_lane_count(intel_dp);
 811         /* Conveniently, the link BW constants become indices with a shift...*/
 812         int min_clock = 0;
 813         int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
 814         int bpp, mode_rate;
 815         static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
 816         int link_avail, link_clock;
 817
 818         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
 819                 pipe_config->has_pch_encoder = true;
 820
 821         pipe_config->has_dp_encoder = true;
 822         pipe_config->has_audio = intel_dp->has_audio;
 823
 824         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
 825                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
 826                                        adjusted_mode);
 827                 if (!HAS_PCH_SPLIT(dev))
 828                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
 829                                                  intel_connector->panel.fitting_mode);
 830                 else
 831                         intel_pch_panel_fitting(intel_crtc, pipe_config,
 832                                                 intel_connector->panel.fitting_mode);
 833         }
 834
 835         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 836                 return false;
 837
 838         DRM_DEBUG_KMS("DP link computation with max lane count %i "
 839                       "max bw %02x pixel clock %iKHz\n",
 840                       max_lane_count, bws[max_clock],
 841                       adjusted_mode->crtc_clock);
 842
 843         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
 844          * bpc in between. */
 845         bpp = pipe_config->pipe_bpp;
 846         if (is_edp(intel_dp)) {
 847                 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
 848                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
 849                                       dev_priv->vbt.edp_bpp);
 850                         bpp = dev_priv->vbt.edp_bpp;
 851                 }
 852
 853                 if (IS_BROADWELL(dev)) {
 854                         /* Yes, it's an ugly hack. */
 855                         min_lane_count = max_lane_count;
 856                         DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
 857                                       min_lane_count);
 858                 } else if (dev_priv->vbt.edp_lanes) {
 859                         min_lane_count = min(dev_priv->vbt.edp_lanes,
 860                                              max_lane_count);
 861                         DRM_DEBUG_KMS("using min %u lanes per VBT\n",
 862                                       min_lane_count);
 863                 }
 864
 865                 if (dev_priv->vbt.edp_rate) {
 866                         min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock);
 867                         DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
 868                                       bws[min_clock]);
 869                 }
 870         }
 871
 872         for (; bpp >= 6*3; bpp -= 2*3) {
 873                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
 874                                                    bpp);
 875
 876                 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
 877                         for (clock = min_clock; clock <= max_clock; clock++) {
 878                                 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
 879                                 link_avail = intel_dp_max_data_rate(link_clock,
 880                                                                     lane_count);
 881
 882                                 if (mode_rate <= link_avail) {
 883                                         goto found;
 884                                 }
 885                         }
 886                 }
 887         }
 888
 889         return false;
 890
 891 found:
 892         if (intel_dp->color_range_auto) {
 893                 /*
 894                  * See:
 895                  * CEA-861-E - 5.1 Default Encoding Parameters
 896                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
 897                  */
 898                 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
 899                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
 900                 else
 901                         intel_dp->color_range = 0;
 902         }
 903
 904         if (intel_dp->color_range)
 905                 pipe_config->limited_color_range = true;
 906
 907         intel_dp->link_bw = bws[clock];
 908         intel_dp->lane_count = lane_count;
 909         pipe_config->pipe_bpp = bpp;
 910         pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
 911
 912         DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
 913                       intel_dp->link_bw, intel_dp->lane_count,
 914                       pipe_config->port_clock, bpp);
 915         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
 916                       mode_rate, link_avail);
 917
 918         intel_link_compute_m_n(bpp, lane_count,
 919                                adjusted_mode->crtc_clock,
 920                                pipe_config->port_clock,
 921                                &pipe_config->dp_m_n);
 922
 923         if (intel_connector->panel.downclock_mode != NULL &&
 924                 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
 925                         intel_link_compute_m_n(bpp, lane_count,
 926                                 intel_connector->panel.downclock_mode->clock,
 927                                 pipe_config->port_clock,
 928                                 &pipe_config->dp_m2_n2);
 929         }
 930
 931         intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
 932
 933         return true;
 934 }
 935
 936 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
 937 {
 938         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 939         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
 940         struct drm_device *dev = crtc->base.dev;
 941         struct drm_i915_private *dev_priv = dev->dev_private;
 942         u32 dpa_ctl;
 943
 944         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
 945         dpa_ctl = I915_READ(DP_A);
 946         dpa_ctl &= ~DP_PLL_FREQ_MASK;
 947
 948         if (crtc->config.port_clock == 162000) {
 949                 /* For a long time we've carried around a ILK-DevA w/a for the
 950                  * 160MHz clock. If we're really unlucky, it's still required.
 951                  */
 952                 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
 953                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
 954                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 955         } else {
 956                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
 957                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 958         }
 959
 960         I915_WRITE(DP_A, dpa_ctl);
 961
 962         POSTING_READ(DP_A);
 963         udelay(500);
 964 }
 965
 966 static void intel_dp_prepare(struct intel_encoder *encoder)
 967 {
 968         struct drm_device *dev = encoder->base.dev;
 969         struct drm_i915_private *dev_priv = dev->dev_private;
 970         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 971         enum port port = dp_to_dig_port(intel_dp)->port;
 972         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 973         struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
 974
 975         /*
 976          * There are four kinds of DP registers:
 977          *
 978          *      IBX PCH
 979          *      SNB CPU
 980          *      IVB CPU
 981          *      CPT PCH
 982          *
 983          * IBX PCH and CPU are the same for almost everything,
 984          * except that the CPU DP PLL is configured in this
 985          * register
 986          *
 987          * CPT PCH is quite different, having many bits moved
 988          * to the TRANS_DP_CTL register instead. That
 989          * configuration happens (oddly) in ironlake_pch_enable
 990          */
 991
 992         /* Preserve the BIOS-computed detected bit. This is
 993          * supposed to be read-only.
 994          */
 995         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 996
 997         /* Handle DP bits in common between all three register formats */
 998         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 999         intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
1000
1001         if (crtc->config.has_audio) {
1002                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
1003                                  pipe_name(crtc->pipe));
1004                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
1005                 intel_write_eld(&encoder->base, adjusted_mode);
1006         }
1007
1008         /* Split out the IBX/CPU vs CPT settings */
1009
1010         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1011                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1012                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1013                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1014                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1015                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1016
1017                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1018                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1019
1020                 intel_dp->DP |= crtc->pipe << 29;
1021         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1022                 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
1023                         intel_dp->DP |= intel_dp->color_range;
1024
1025                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1026                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1027                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1028                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1029                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1030
1031                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1032                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1033
1034                 if (!IS_CHERRYVIEW(dev)) {
1035                         if (crtc->pipe == 1)
1036                                 intel_dp->DP |= DP_PIPEB_SELECT;
1037                 } else {
1038                         intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1039                 }
1040         } else {
1041                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1042         }
1043 }
1044
1045 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1046 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1047
1048 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
1049 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
1050
1051 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1052 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1053
1054 static void wait_panel_status(struct intel_dp *intel_dp,
1055                                        u32 mask,
1056                                        u32 value)
1057 {
1058         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1059         struct drm_i915_private *dev_priv = dev->dev_private;
1060         u32 pp_stat_reg, pp_ctrl_reg;
1061
1062         pp_stat_reg = _pp_stat_reg(intel_dp);
1063         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1064
1065         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1066                         mask, value,
1067                         I915_READ(pp_stat_reg),
1068                         I915_READ(pp_ctrl_reg));
1069
1070         if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1071                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1072                                 I915_READ(pp_stat_reg),
1073                                 I915_READ(pp_ctrl_reg));
1074         }
1075
1076         DRM_DEBUG_KMS("Wait complete\n");
1077 }
1078
1079 static void wait_panel_on(struct intel_dp *intel_dp)
1080 {
1081         DRM_DEBUG_KMS("Wait for panel power on\n");
1082         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1083 }
1084
1085 static void wait_panel_off(struct intel_dp *intel_dp)
1086 {
1087         DRM_DEBUG_KMS("Wait for panel power off time\n");
1088         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1089 }
1090
1091 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1092 {
1093         DRM_DEBUG_KMS("Wait for panel power cycle\n");
1094
1095         /* When we disable the VDD override bit last we have to do the manual
1096          * wait. */
1097         wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1098                                        intel_dp->panel_power_cycle_delay);
1099
1100         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1101 }
1102
1103 static void wait_backlight_on(struct intel_dp *intel_dp)
1104 {
1105         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1106                                        intel_dp->backlight_on_delay);
1107 }
1108
1109 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1110 {
1111         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1112                                        intel_dp->backlight_off_delay);
1113 }
1114
1115 /* Read the current pp_control value, unlocking the register if it
1116  * is locked
1117  */
1118
1119 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1120 {
1121         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1122         struct drm_i915_private *dev_priv = dev->dev_private;
1123         u32 control;
1124
1125         control = I915_READ(_pp_ctrl_reg(intel_dp));
1126         control &= ~PANEL_UNLOCK_MASK;
1127         control |= PANEL_UNLOCK_REGS;
1128         return control;
1129 }
1130
1131 static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
1132 {
1133         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1134         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1135         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1136         struct drm_i915_private *dev_priv = dev->dev_private;
1137         enum intel_display_power_domain power_domain;
1138         u32 pp;
1139         u32 pp_stat_reg, pp_ctrl_reg;
1140         bool need_to_disable = !intel_dp->want_panel_vdd;
1141
1142         if (!is_edp(intel_dp))
1143                 return false;
1144
1145         intel_dp->want_panel_vdd = true;
1146
1147         if (edp_have_panel_vdd(intel_dp))
1148                 return need_to_disable;
1149
1150         power_domain = intel_display_port_power_domain(intel_encoder);
1151         intel_display_power_get(dev_priv, power_domain);
1152
1153         DRM_DEBUG_KMS("Turning eDP VDD on\n");
1154
1155         if (!edp_have_panel_power(intel_dp))
1156                 wait_panel_power_cycle(intel_dp);
1157
1158         pp = ironlake_get_pp_control(intel_dp);
1159         pp |= EDP_FORCE_VDD;
1160
1161         pp_stat_reg = _pp_stat_reg(intel_dp);
1162         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1163
1164         I915_WRITE(pp_ctrl_reg, pp);
1165         POSTING_READ(pp_ctrl_reg);
1166         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1167                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1168         /*
1169          * If the panel wasn't on, delay before accessing aux channel
1170          */
1171         if (!edp_have_panel_power(intel_dp)) {
1172                 DRM_DEBUG_KMS("eDP was not running\n");
1173                 msleep(intel_dp->panel_power_up_delay);
1174         }
1175
1176         return need_to_disable;
1177 }
1178
1179 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1180 {
1181         if (is_edp(intel_dp)) {
1182                 bool vdd = _edp_panel_vdd_on(intel_dp);
1183
1184                 WARN(!vdd, "eDP VDD already requested on\n");
1185         }
1186 }
1187
1188 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1189 {
1190         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1191         struct drm_i915_private *dev_priv = dev->dev_private;
1192         u32 pp;
1193         u32 pp_stat_reg, pp_ctrl_reg;
1194
1195         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
1196
1197         if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
1198                 struct intel_digital_port *intel_dig_port =
1199                                                 dp_to_dig_port(intel_dp);
1200                 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1201                 enum intel_display_power_domain power_domain;
1202
1203                 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1204
1205                 pp = ironlake_get_pp_control(intel_dp);
1206                 pp &= ~EDP_FORCE_VDD;
1207
1208                 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1209                 pp_stat_reg = _pp_stat_reg(intel_dp);
1210
1211                 I915_WRITE(pp_ctrl_reg, pp);
1212                 POSTING_READ(pp_ctrl_reg);
1213
1214                 /* Make sure sequencer is idle before allowing subsequent activity */
1215                 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1216                 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1217
1218                 if ((pp & POWER_TARGET_ON) == 0)
1219                         intel_dp->last_power_cycle = jiffies;
1220
1221                 power_domain = intel_display_port_power_domain(intel_encoder);
1222                 intel_display_power_put(dev_priv, power_domain);
1223         }
1224 }
1225
1226 static void edp_panel_vdd_work(struct work_struct *__work)
1227 {
1228         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1229                                                  struct intel_dp, panel_vdd_work);
1230         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1231
1232         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1233         edp_panel_vdd_off_sync(intel_dp);
1234         drm_modeset_unlock(&dev->mode_config.connection_mutex);
1235 }
1236
1237 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1238 {
1239         if (!is_edp(intel_dp))
1240                 return;
1241
1242         WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1243
1244         intel_dp->want_panel_vdd = false;
1245
1246         if (sync) {
1247                 edp_panel_vdd_off_sync(intel_dp);
1248         } else {
1249                 /*
1250                  * Queue the timer to fire a long
1251                  * time from now (relative to the power down delay)
1252                  * to keep the panel power up across a sequence of operations
1253                  */
1254                 schedule_delayed_work(&intel_dp->panel_vdd_work,
1255                                       msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1256         }
1257 }
1258
1259 void intel_edp_panel_on(struct intel_dp *intel_dp)
1260 {
1261         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1262         struct drm_i915_private *dev_priv = dev->dev_private;
1263         u32 pp;
1264         u32 pp_ctrl_reg;
1265
1266         if (!is_edp(intel_dp))
1267                 return;
1268
1269         DRM_DEBUG_KMS("Turn eDP power on\n");
1270
1271         if (edp_have_panel_power(intel_dp)) {
1272                 DRM_DEBUG_KMS("eDP power already on\n");
1273                 return;
1274         }
1275
1276         wait_panel_power_cycle(intel_dp);
1277
1278         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1279         pp = ironlake_get_pp_control(intel_dp);
1280         if (IS_GEN5(dev)) {
1281                 /* ILK workaround: disable reset around power sequence */
1282                 pp &= ~PANEL_POWER_RESET;
1283                 I915_WRITE(pp_ctrl_reg, pp);
1284                 POSTING_READ(pp_ctrl_reg);
1285         }
1286
1287         pp |= POWER_TARGET_ON;
1288         if (!IS_GEN5(dev))
1289                 pp |= PANEL_POWER_RESET;
1290
1291         I915_WRITE(pp_ctrl_reg, pp);
1292         POSTING_READ(pp_ctrl_reg);
1293
1294         wait_panel_on(intel_dp);
1295         intel_dp->last_power_on = jiffies;
1296
1297         if (IS_GEN5(dev)) {
1298                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1299                 I915_WRITE(pp_ctrl_reg, pp);
1300                 POSTING_READ(pp_ctrl_reg);
1301         }
1302 }
1303
1304 void intel_edp_panel_off(struct intel_dp *intel_dp)
1305 {
1306         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1307         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1308         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1309         struct drm_i915_private *dev_priv = dev->dev_private;
1310         enum intel_display_power_domain power_domain;
1311         u32 pp;
1312         u32 pp_ctrl_reg;
1313
1314         if (!is_edp(intel_dp))
1315                 return;
1316
1317         DRM_DEBUG_KMS("Turn eDP power off\n");
1318
1319         edp_wait_backlight_off(intel_dp);
1320
1321         WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1322
1323         pp = ironlake_get_pp_control(intel_dp);
1324         /* We need to switch off panel power _and_ force vdd, for otherwise some
1325          * panels get very unhappy and cease to work. */
1326         pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1327                 EDP_BLC_ENABLE);
1328
1329         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1330
1331         intel_dp->want_panel_vdd = false;
1332
1333         I915_WRITE(pp_ctrl_reg, pp);
1334         POSTING_READ(pp_ctrl_reg);
1335
1336         intel_dp->last_power_cycle = jiffies;
1337         wait_panel_off(intel_dp);
1338
1339         /* We got a reference when we enabled the VDD. */
1340         power_domain = intel_display_port_power_domain(intel_encoder);
1341         intel_display_power_put(dev_priv, power_domain);
1342 }
1343
1344 void intel_edp_backlight_on(struct intel_dp *intel_dp)
1345 {
1346         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1347         struct drm_device *dev = intel_dig_port->base.base.dev;
1348         struct drm_i915_private *dev_priv = dev->dev_private;
1349         u32 pp;
1350         u32 pp_ctrl_reg;
1351
1352         if (!is_edp(intel_dp))
1353                 return;
1354
1355         DRM_DEBUG_KMS("\n");
1356         /*
1357          * If we enable the backlight right away following a panel power
1358          * on, we may see slight flicker as the panel syncs with the eDP
1359          * link.  So delay a bit to make sure the image is solid before
1360          * allowing it to appear.
1361          */
1362         wait_backlight_on(intel_dp);
1363         pp = ironlake_get_pp_control(intel_dp);
1364         pp |= EDP_BLC_ENABLE;
1365
1366         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1367
1368         I915_WRITE(pp_ctrl_reg, pp);
1369         POSTING_READ(pp_ctrl_reg);
1370
1371         intel_panel_enable_backlight(intel_dp->attached_connector);
1372 }
1373
1374 void intel_edp_backlight_off(struct intel_dp *intel_dp)
1375 {
1376         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1377         struct drm_i915_private *dev_priv = dev->dev_private;
1378         u32 pp;
1379         u32 pp_ctrl_reg;
1380
1381         if (!is_edp(intel_dp))
1382                 return;
1383
1384         intel_panel_disable_backlight(intel_dp->attached_connector);
1385
1386         DRM_DEBUG_KMS("\n");
1387         pp = ironlake_get_pp_control(intel_dp);
1388         pp &= ~EDP_BLC_ENABLE;
1389
1390         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1391
1392         I915_WRITE(pp_ctrl_reg, pp);
1393         POSTING_READ(pp_ctrl_reg);
1394         intel_dp->last_backlight_off = jiffies;
1395 }
1396
1397 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1398 {
1399         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1400         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1401         struct drm_device *dev = crtc->dev;
1402         struct drm_i915_private *dev_priv = dev->dev_private;
1403         u32 dpa_ctl;
1404
1405         assert_pipe_disabled(dev_priv,
1406                              to_intel_crtc(crtc)->pipe);
1407
1408         DRM_DEBUG_KMS("\n");
1409         dpa_ctl = I915_READ(DP_A);
1410         WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1411         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1412
1413         /* We don't adjust intel_dp->DP while tearing down the link, to
1414          * facilitate link retraining (e.g. after hotplug). Hence clear all
1415          * enable bits here to ensure that we don't enable too much. */
1416         intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1417         intel_dp->DP |= DP_PLL_ENABLE;
1418         I915_WRITE(DP_A, intel_dp->DP);
1419         POSTING_READ(DP_A);
1420         udelay(200);
1421 }
1422
1423 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1424 {
1425         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1426         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1427         struct drm_device *dev = crtc->dev;
1428         struct drm_i915_private *dev_priv = dev->dev_private;
1429         u32 dpa_ctl;
1430
1431         assert_pipe_disabled(dev_priv,
1432                              to_intel_crtc(crtc)->pipe);
1433
1434         dpa_ctl = I915_READ(DP_A);
1435         WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1436              "dp pll off, should be on\n");
1437         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1438
1439         /* We can't rely on the value tracked for the DP register in
1440          * intel_dp->DP because link_down must not change that (otherwise link
1441          * re-training will fail. */
1442         dpa_ctl &= ~DP_PLL_ENABLE;
1443         I915_WRITE(DP_A, dpa_ctl);
1444         POSTING_READ(DP_A);
1445         udelay(200);
1446 }
1447
1448 /* If the sink supports it, try to set the power state appropriately */
1449 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1450 {
1451         int ret, i;
1452
1453         /* Should have a valid DPCD by this point */
1454         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1455                 return;
1456
1457         if (mode != DRM_MODE_DPMS_ON) {
1458                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1459                                          DP_SET_POWER_D3);
1460                 if (ret != 1)
1461                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
1462         } else {
1463                 /*
1464                  * When turning on, we need to retry for 1ms to give the sink
1465                  * time to wake up.
1466                  */
1467                 for (i = 0; i < 3; i++) {
1468                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1469                                                  DP_SET_POWER_D0);
1470                         if (ret == 1)
1471                                 break;
1472                         msleep(1);
1473                 }
1474         }
1475 }
1476
1477 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1478                                   enum pipe *pipe)
1479 {
1480         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1481         enum port port = dp_to_dig_port(intel_dp)->port;
1482         struct drm_device *dev = encoder->base.dev;
1483         struct drm_i915_private *dev_priv = dev->dev_private;
1484         enum intel_display_power_domain power_domain;
1485         u32 tmp;
1486
1487         power_domain = intel_display_port_power_domain(encoder);
1488         if (!intel_display_power_enabled(dev_priv, power_domain))
1489                 return false;
1490
1491         tmp = I915_READ(intel_dp->output_reg);
1492
1493         if (!(tmp & DP_PORT_EN))
1494                 return false;
1495
1496         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1497                 *pipe = PORT_TO_PIPE_CPT(tmp);
1498         } else if (IS_CHERRYVIEW(dev)) {
1499                 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
1500         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1501                 *pipe = PORT_TO_PIPE(tmp);
1502         } else {
1503                 u32 trans_sel;
1504                 u32 trans_dp;
1505                 int i;
1506
1507                 switch (intel_dp->output_reg) {
1508                 case PCH_DP_B:
1509                         trans_sel = TRANS_DP_PORT_SEL_B;
1510                         break;
1511                 case PCH_DP_C:
1512                         trans_sel = TRANS_DP_PORT_SEL_C;
1513                         break;
1514                 case PCH_DP_D:
1515                         trans_sel = TRANS_DP_PORT_SEL_D;
1516                         break;
1517                 default:
1518                         return true;
1519                 }
1520
1521                 for_each_pipe(i) {
1522                         trans_dp = I915_READ(TRANS_DP_CTL(i));
1523                         if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1524                                 *pipe = i;
1525                                 return true;
1526                         }
1527                 }
1528
1529                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1530                               intel_dp->output_reg);
1531         }
1532
1533         return true;
1534 }
1535
1536 static void intel_dp_get_config(struct intel_encoder *encoder,
1537                                 struct intel_crtc_config *pipe_config)
1538 {
1539         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1540         u32 tmp, flags = 0;
1541         struct drm_device *dev = encoder->base.dev;
1542         struct drm_i915_private *dev_priv = dev->dev_private;
1543         enum port port = dp_to_dig_port(intel_dp)->port;
1544         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1545         int dotclock;
1546
1547         tmp = I915_READ(intel_dp->output_reg);
1548         if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1549                 pipe_config->has_audio = true;
1550
1551         if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1552                 if (tmp & DP_SYNC_HS_HIGH)
1553                         flags |= DRM_MODE_FLAG_PHSYNC;
1554                 else
1555                         flags |= DRM_MODE_FLAG_NHSYNC;
1556
1557                 if (tmp & DP_SYNC_VS_HIGH)
1558                         flags |= DRM_MODE_FLAG_PVSYNC;
1559                 else
1560                         flags |= DRM_MODE_FLAG_NVSYNC;
1561         } else {
1562                 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1563                 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1564                         flags |= DRM_MODE_FLAG_PHSYNC;
1565                 else
1566                         flags |= DRM_MODE_FLAG_NHSYNC;
1567
1568                 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1569                         flags |= DRM_MODE_FLAG_PVSYNC;
1570                 else
1571                         flags |= DRM_MODE_FLAG_NVSYNC;
1572         }
1573
1574         pipe_config->adjusted_mode.flags |= flags;
1575
1576         pipe_config->has_dp_encoder = true;
1577
1578         intel_dp_get_m_n(crtc, pipe_config);
1579
1580         if (port == PORT_A) {
1581                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1582                         pipe_config->port_clock = 162000;
1583                 else
1584                         pipe_config->port_clock = 270000;
1585         }
1586
1587         dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1588                                             &pipe_config->dp_m_n);
1589
1590         if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1591                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1592
1593         pipe_config->adjusted_mode.crtc_clock = dotclock;
1594
1595         if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1596             pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1597                 /*
1598                  * This is a big fat ugly hack.
1599                  *
1600                  * Some machines in UEFI boot mode provide us a VBT that has 18
1601                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1602                  * unknown we fail to light up. Yet the same BIOS boots up with
1603                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1604                  * max, not what it tells us to use.
1605                  *
1606                  * Note: This will still be broken if the eDP panel is not lit
1607                  * up by the BIOS, and thus we can't get the mode at module
1608                  * load.
1609                  */
1610                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1611                               pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1612                 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1613         }
1614 }
1615
1616 static bool is_edp_psr(struct intel_dp *intel_dp)
1617 {
1618         return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
1619 }
1620
1621 static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1622 {
1623         struct drm_i915_private *dev_priv = dev->dev_private;
1624
1625         if (!HAS_PSR(dev))
1626                 return false;
1627
1628         return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1629 }
1630
1631 static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1632                                     struct edp_vsc_psr *vsc_psr)
1633 {
1634         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1635         struct drm_device *dev = dig_port->base.base.dev;
1636         struct drm_i915_private *dev_priv = dev->dev_private;
1637         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1638         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1639         u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1640         uint32_t *data = (uint32_t *) vsc_psr;
1641         unsigned int i;
1642
1643         /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1644            the video DIP being updated before program video DIP data buffer
1645            registers for DIP being updated. */
1646         I915_WRITE(ctl_reg, 0);
1647         POSTING_READ(ctl_reg);
1648
1649         for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1650                 if (i < sizeof(struct edp_vsc_psr))
1651                         I915_WRITE(data_reg + i, *data++);
1652                 else
1653                         I915_WRITE(data_reg + i, 0);
1654         }
1655
1656         I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1657         POSTING_READ(ctl_reg);
1658 }
1659
1660 static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1661 {
1662         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1663         struct drm_i915_private *dev_priv = dev->dev_private;
1664         struct edp_vsc_psr psr_vsc;
1665
1666         if (dev_priv->psr.setup_done)
1667                 return;
1668
1669         /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1670         memset(&psr_vsc, 0, sizeof(psr_vsc));
1671         psr_vsc.sdp_header.HB0 = 0;
1672         psr_vsc.sdp_header.HB1 = 0x7;
1673         psr_vsc.sdp_header.HB2 = 0x2;
1674         psr_vsc.sdp_header.HB3 = 0x8;
1675         intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1676
1677         /* Avoid continuous PSR exit by masking memup and hpd */
1678         I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
1679                    EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
1680
1681         dev_priv->psr.setup_done = true;
1682 }
1683
1684 static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1685 {
1686         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1687         struct drm_device *dev = dig_port->base.base.dev;
1688         struct drm_i915_private *dev_priv = dev->dev_private;
1689         uint32_t aux_clock_divider;
1690         int precharge = 0x3;
1691         int msg_size = 5;       /* Header(4) + Message(1) */
1692         bool only_standby = false;
1693
1694         aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1695
1696         if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1697                 only_standby = true;
1698
1699         /* Enable PSR in sink */
1700         if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
1701                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1702                                    DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
1703         else
1704                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1705                                    DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
1706
1707         /* Setup AUX registers */
1708         I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1709         I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1710         I915_WRITE(EDP_PSR_AUX_CTL(dev),
1711                    DP_AUX_CH_CTL_TIME_OUT_400us |
1712                    (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1713                    (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1714                    (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1715 }
1716
1717 static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1718 {
1719         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1720         struct drm_device *dev = dig_port->base.base.dev;
1721         struct drm_i915_private *dev_priv = dev->dev_private;
1722         uint32_t max_sleep_time = 0x1f;
1723         uint32_t idle_frames = 1;
1724         uint32_t val = 0x0;
1725         const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
1726         bool only_standby = false;
1727
1728         if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1729                 only_standby = true;
1730
1731         if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
1732                 val |= EDP_PSR_LINK_STANDBY;
1733                 val |= EDP_PSR_TP2_TP3_TIME_0us;
1734                 val |= EDP_PSR_TP1_TIME_0us;
1735                 val |= EDP_PSR_SKIP_AUX_EXIT;
1736                 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
1737         } else
1738                 val |= EDP_PSR_LINK_DISABLE;
1739
1740         I915_WRITE(EDP_PSR_CTL(dev), val |
1741                    (IS_BROADWELL(dev) ? 0 : link_entry_time) |
1742                    max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1743                    idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1744                    EDP_PSR_ENABLE);
1745 }
1746
1747 static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1748 {
1749         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1750         struct drm_device *dev = dig_port->base.base.dev;
1751         struct drm_i915_private *dev_priv = dev->dev_private;
1752         struct drm_crtc *crtc = dig_port->base.base.crtc;
1753         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1754         struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->primary->fb)->obj;
1755         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1756
1757         dev_priv->psr.source_ok = false;
1758
1759         if (!HAS_PSR(dev)) {
1760                 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1761                 return false;
1762         }
1763
1764         if (IS_HASWELL(dev) && (intel_encoder->type != INTEL_OUTPUT_EDP ||
1765                                 dig_port->port != PORT_A)) {
1766                 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1767                 return false;
1768         }
1769
1770         if (!i915.enable_psr) {
1771                 DRM_DEBUG_KMS("PSR disable by flag\n");
1772                 return false;
1773         }
1774
1775         crtc = dig_port->base.base.crtc;
1776         if (crtc == NULL) {
1777                 DRM_DEBUG_KMS("crtc not active for PSR\n");
1778                 return false;
1779         }
1780
1781         intel_crtc = to_intel_crtc(crtc);
1782         if (!intel_crtc_active(crtc)) {
1783                 DRM_DEBUG_KMS("crtc not active for PSR\n");
1784                 return false;
1785         }
1786
1787         obj = to_intel_framebuffer(crtc->primary->fb)->obj;
1788         if (obj->tiling_mode != I915_TILING_X ||
1789             obj->fence_reg == I915_FENCE_REG_NONE) {
1790                 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
1791                 return false;
1792         }
1793
1794         /* Below limitations aren't valid for Broadwell */
1795         if (IS_BROADWELL(dev))
1796                 goto out;
1797
1798         if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1799                 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
1800                 return false;
1801         }
1802
1803         if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1804             S3D_ENABLE) {
1805                 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1806                 return false;
1807         }
1808
1809         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
1810                 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1811                 return false;
1812         }
1813
1814  out:
1815         dev_priv->psr.source_ok = true;
1816         return true;
1817 }
1818
1819 static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
1820 {
1821         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1822         struct drm_device *dev = intel_dig_port->base.base.dev;
1823         struct drm_i915_private *dev_priv = dev->dev_private;
1824
1825         if (intel_edp_is_psr_enabled(dev))
1826                 return;
1827
1828         /* Enable PSR on the panel */
1829         intel_edp_psr_enable_sink(intel_dp);
1830
1831         /* Enable PSR on the host */
1832         intel_edp_psr_enable_source(intel_dp);
1833
1834         dev_priv->psr.enabled = true;
1835         dev_priv->psr.active = true;
1836 }
1837
1838 void intel_edp_psr_enable(struct intel_dp *intel_dp)
1839 {
1840         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1841
1842         if (!HAS_PSR(dev)) {
1843                 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1844                 return;
1845         }
1846
1847         if (!is_edp_psr(intel_dp)) {
1848                 DRM_DEBUG_KMS("PSR not supported by this panel\n");
1849                 return;
1850         }
1851
1852         /* Setup PSR once */
1853         intel_edp_psr_setup(intel_dp);
1854
1855         if (intel_edp_psr_match_conditions(intel_dp))
1856                 intel_edp_psr_do_enable(intel_dp);
1857 }
1858
1859 void intel_edp_psr_disable(struct intel_dp *intel_dp)
1860 {
1861         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1862         struct drm_i915_private *dev_priv = dev->dev_private;
1863
1864         if (!dev_priv->psr.enabled)
1865                 return;
1866
1867         I915_WRITE(EDP_PSR_CTL(dev),
1868                    I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
1869
1870         /* Wait till PSR is idle */
1871         if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
1872                        EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1873                 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1874
1875         dev_priv->psr.enabled = false;
1876 }
1877
1878 static void intel_edp_psr_work(struct work_struct *work)
1879 {
1880         struct drm_i915_private *dev_priv =
1881                 container_of(work, typeof(*dev_priv), psr.work.work);
1882         struct drm_device *dev = dev_priv->dev;
1883         struct intel_encoder *encoder;
1884         struct intel_dp *intel_dp = NULL;
1885
1886         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1887                 if (encoder->type == INTEL_OUTPUT_EDP) {
1888                         intel_dp = enc_to_intel_dp(&encoder->base);
1889
1890                         if (!intel_edp_psr_match_conditions(intel_dp))
1891                                 intel_edp_psr_disable(intel_dp);
1892                         else
1893                                 intel_edp_psr_do_enable(intel_dp);
1894                 }
1895 }
1896
1897 static void intel_edp_psr_inactivate(struct drm_device *dev)
1898 {
1899         struct drm_i915_private *dev_priv = dev->dev_private;
1900
1901         dev_priv->psr.active = false;
1902
1903         I915_WRITE(EDP_PSR_CTL(dev), I915_READ(EDP_PSR_CTL(dev))
1904                    & ~EDP_PSR_ENABLE);
1905 }
1906
1907 void intel_edp_psr_exit(struct drm_device *dev, bool schedule_back)
1908 {
1909         struct drm_i915_private *dev_priv = dev->dev_private;
1910
1911         if (!HAS_PSR(dev))
1912                 return;
1913
1914         if (!dev_priv->psr.setup_done)
1915                 return;
1916
1917         cancel_delayed_work_sync(&dev_priv->psr.work);
1918
1919         if (dev_priv->psr.active)
1920                 intel_edp_psr_inactivate(dev);
1921
1922         if (schedule_back)
1923                 schedule_delayed_work(&dev_priv->psr.work,
1924                                       msecs_to_jiffies(100));
1925 }
1926
1927 void intel_edp_psr_init(struct drm_device *dev)
1928 {
1929         struct drm_i915_private *dev_priv = dev->dev_private;
1930
1931         if (!HAS_PSR(dev))
1932                 return;
1933
1934         INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
1935 }
1936
1937 static void intel_disable_dp(struct intel_encoder *encoder)
1938 {
1939         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1940         enum port port = dp_to_dig_port(intel_dp)->port;
1941         struct drm_device *dev = encoder->base.dev;
1942
1943         /* Make sure the panel is off before trying to change the mode. But also
1944          * ensure that we have vdd while we switch off the panel. */
1945         intel_edp_panel_vdd_on(intel_dp);
1946         intel_edp_backlight_off(intel_dp);
1947         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1948         intel_edp_panel_off(intel_dp);
1949
1950         /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1951         if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
1952                 intel_dp_link_down(intel_dp);
1953 }
1954
1955 static void g4x_post_disable_dp(struct intel_encoder *encoder)
1956 {
1957         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1958         enum port port = dp_to_dig_port(intel_dp)->port;
1959
1960         if (port != PORT_A)
1961                 return;
1962
1963         intel_dp_link_down(intel_dp);
1964         ironlake_edp_pll_off(intel_dp);
1965 }
1966
1967 static void vlv_post_disable_dp(struct intel_encoder *encoder)
1968 {
1969         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1970
1971         intel_dp_link_down(intel_dp);
1972 }
1973
1974 static void chv_post_disable_dp(struct intel_encoder *encoder)
1975 {
1976         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1977         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1978         struct drm_device *dev = encoder->base.dev;
1979         struct drm_i915_private *dev_priv = dev->dev_private;
1980         struct intel_crtc *intel_crtc =
1981                 to_intel_crtc(encoder->base.crtc);
1982         enum dpio_channel ch = vlv_dport_to_channel(dport);
1983         enum pipe pipe = intel_crtc->pipe;
1984         u32 val;
1985
1986         intel_dp_link_down(intel_dp);
1987
1988         mutex_lock(&dev_priv->dpio_lock);
1989
1990         /* Propagate soft reset to data lane reset */
1991         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
1992         val |= CHV_PCS_REQ_SOFTRESET_EN;
1993         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
1994
1995         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1996         val |= CHV_PCS_REQ_SOFTRESET_EN;
1997         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1998
1999         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2000         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2001         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2002
2003         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2004         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2005         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2006
2007         mutex_unlock(&dev_priv->dpio_lock);
2008 }
2009
2010 static void intel_enable_dp(struct intel_encoder *encoder)
2011 {
2012         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2013         struct drm_device *dev = encoder->base.dev;
2014         struct drm_i915_private *dev_priv = dev->dev_private;
2015         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2016
2017         if (WARN_ON(dp_reg & DP_PORT_EN))
2018                 return;
2019
2020         intel_edp_panel_vdd_on(intel_dp);
2021         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2022         intel_dp_start_link_train(intel_dp);
2023         intel_edp_panel_on(intel_dp);
2024         edp_panel_vdd_off(intel_dp, true);
2025         intel_dp_complete_link_train(intel_dp);
2026         intel_dp_stop_link_train(intel_dp);
2027 }
2028
2029 static void g4x_enable_dp(struct intel_encoder *encoder)
2030 {
2031         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2032
2033         intel_enable_dp(encoder);
2034         intel_edp_backlight_on(intel_dp);
2035 }
2036
2037 static void vlv_enable_dp(struct intel_encoder *encoder)
2038 {
2039         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2040
2041         intel_edp_backlight_on(intel_dp);
2042 }
2043
2044 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
2045 {
2046         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2047         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2048
2049         intel_dp_prepare(encoder);
2050
2051         /* Only ilk+ has port A */
2052         if (dport->port == PORT_A) {
2053                 ironlake_set_pll_cpu_edp(intel_dp);
2054                 ironlake_edp_pll_on(intel_dp);
2055         }
2056 }
2057
2058 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
2059 {
2060         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2061         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2062         struct drm_device *dev = encoder->base.dev;
2063         struct drm_i915_private *dev_priv = dev->dev_private;
2064         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2065         enum dpio_channel port = vlv_dport_to_channel(dport);
2066         int pipe = intel_crtc->pipe;
2067         struct edp_power_seq power_seq;
2068         u32 val;
2069
2070         mutex_lock(&dev_priv->dpio_lock);
2071
2072         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
2073         val = 0;
2074         if (pipe)
2075                 val |= (1<<21);
2076         else
2077                 val &= ~(1<<21);
2078         val |= 0x001000c4;
2079         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2080         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2081         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
2082
2083         mutex_unlock(&dev_priv->dpio_lock);
2084
2085         if (is_edp(intel_dp)) {
2086                 /* init power sequencer on this pipe and port */
2087                 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2088                 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2089                                                               &power_seq);
2090         }
2091
2092         intel_enable_dp(encoder);
2093
2094         vlv_wait_port_ready(dev_priv, dport);
2095 }
2096
2097 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
2098 {
2099         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2100         struct drm_device *dev = encoder->base.dev;
2101         struct drm_i915_private *dev_priv = dev->dev_private;
2102         struct intel_crtc *intel_crtc =
2103                 to_intel_crtc(encoder->base.crtc);
2104         enum dpio_channel port = vlv_dport_to_channel(dport);
2105         int pipe = intel_crtc->pipe;
2106
2107         intel_dp_prepare(encoder);
2108
2109         /* Program Tx lane resets to default */
2110         mutex_lock(&dev_priv->dpio_lock);
2111         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
2112                          DPIO_PCS_TX_LANE2_RESET |
2113                          DPIO_PCS_TX_LANE1_RESET);
2114         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
2115                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2116                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2117                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2118                                  DPIO_PCS_CLK_SOFT_RESET);
2119
2120         /* Fix up inter-pair skew failure */
2121         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2122         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2123         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
2124         mutex_unlock(&dev_priv->dpio_lock);
2125 }
2126
2127 static void chv_pre_enable_dp(struct intel_encoder *encoder)
2128 {
2129         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2130         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2131         struct drm_device *dev = encoder->base.dev;
2132         struct drm_i915_private *dev_priv = dev->dev_private;
2133         struct edp_power_seq power_seq;
2134         struct intel_crtc *intel_crtc =
2135                 to_intel_crtc(encoder->base.crtc);
2136         enum dpio_channel ch = vlv_dport_to_channel(dport);
2137         int pipe = intel_crtc->pipe;
2138         int data, i;
2139         u32 val;
2140
2141         mutex_lock(&dev_priv->dpio_lock);
2142
2143         /* Deassert soft data lane reset*/
2144         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2145         val |= CHV_PCS_REQ_SOFTRESET_EN;
2146         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2147
2148         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2149         val |= CHV_PCS_REQ_SOFTRESET_EN;
2150         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2151
2152         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2153         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2154         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2155
2156         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2157         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2158         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2159
2160         /* Program Tx lane latency optimal setting*/
2161         for (i = 0; i < 4; i++) {
2162                 /* Set the latency optimal bit */
2163                 data = (i == 1) ? 0x0 : 0x6;
2164                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2165                                 data << DPIO_FRC_LATENCY_SHFIT);
2166
2167                 /* Set the upar bit */
2168                 data = (i == 1) ? 0x0 : 0x1;
2169                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2170                                 data << DPIO_UPAR_SHIFT);
2171         }
2172
2173         /* Data lane stagger programming */
2174         /* FIXME: Fix up value only after power analysis */
2175
2176         mutex_unlock(&dev_priv->dpio_lock);
2177
2178         if (is_edp(intel_dp)) {
2179                 /* init power sequencer on this pipe and port */
2180                 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2181                 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2182                                                               &power_seq);
2183         }
2184
2185         intel_enable_dp(encoder);
2186
2187         vlv_wait_port_ready(dev_priv, dport);
2188 }
2189
2190 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2191 {
2192         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2193         struct drm_device *dev = encoder->base.dev;
2194         struct drm_i915_private *dev_priv = dev->dev_private;
2195         struct intel_crtc *intel_crtc =
2196                 to_intel_crtc(encoder->base.crtc);
2197         enum dpio_channel ch = vlv_dport_to_channel(dport);
2198         enum pipe pipe = intel_crtc->pipe;
2199         u32 val;
2200
2201         mutex_lock(&dev_priv->dpio_lock);
2202
2203         /* program left/right clock distribution */
2204         if (pipe != PIPE_B) {
2205                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2206                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2207                 if (ch == DPIO_CH0)
2208                         val |= CHV_BUFLEFTENA1_FORCE;
2209                 if (ch == DPIO_CH1)
2210                         val |= CHV_BUFRIGHTENA1_FORCE;
2211                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2212         } else {
2213                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2214                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2215                 if (ch == DPIO_CH0)
2216                         val |= CHV_BUFLEFTENA2_FORCE;
2217                 if (ch == DPIO_CH1)
2218                         val |= CHV_BUFRIGHTENA2_FORCE;
2219                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2220         }
2221
2222         /* program clock channel usage */
2223         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2224         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2225         if (pipe != PIPE_B)
2226                 val &= ~CHV_PCS_USEDCLKCHANNEL;
2227         else
2228                 val |= CHV_PCS_USEDCLKCHANNEL;
2229         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2230
2231         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2232         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2233         if (pipe != PIPE_B)
2234                 val &= ~CHV_PCS_USEDCLKCHANNEL;
2235         else
2236                 val |= CHV_PCS_USEDCLKCHANNEL;
2237         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2238
2239         /*
2240          * This a a bit weird since generally CL
2241          * matches the pipe, but here we need to
2242          * pick the CL based on the port.
2243          */
2244         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2245         if (pipe != PIPE_B)
2246                 val &= ~CHV_CMN_USEDCLKCHANNEL;
2247         else
2248                 val |= CHV_CMN_USEDCLKCHANNEL;
2249         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2250
2251         mutex_unlock(&dev_priv->dpio_lock);
2252 }
2253
2254 /*
2255  * Native read with retry for link status and receiver capability reads for
2256  * cases where the sink may still be asleep.
2257  *
2258  * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2259  * supposed to retry 3 times per the spec.
2260  */
2261 static ssize_t
2262 intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2263                         void *buffer, size_t size)
2264 {
2265         ssize_t ret;
2266         int i;
2267
2268         for (i = 0; i < 3; i++) {
2269                 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2270                 if (ret == size)
2271                         return ret;
2272                 msleep(1);
2273         }
2274
2275         return ret;
2276 }
2277
2278 /*
2279  * Fetch AUX CH registers 0x202 - 0x207 which contain
2280  * link status information
2281  */
2282 static bool
2283 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2284 {
2285         return intel_dp_dpcd_read_wake(&intel_dp->aux,
2286                                        DP_LANE0_1_STATUS,
2287                                        link_status,
2288                                        DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
2289 }
2290
2291 /* These are source-specific values. */
2292 static uint8_t
2293 intel_dp_voltage_max(struct intel_dp *intel_dp)
2294 {
2295         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2296         enum port port = dp_to_dig_port(intel_dp)->port;
2297
2298         if (IS_VALLEYVIEW(dev))
2299                 return DP_TRAIN_VOLTAGE_SWING_1200;
2300         else if (IS_GEN7(dev) && port == PORT_A)
2301                 return DP_TRAIN_VOLTAGE_SWING_800;
2302         else if (HAS_PCH_CPT(dev) && port != PORT_A)
2303                 return DP_TRAIN_VOLTAGE_SWING_1200;
2304         else
2305                 return DP_TRAIN_VOLTAGE_SWING_800;
2306 }
2307
2308 static uint8_t
2309 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2310 {
2311         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2312         enum port port = dp_to_dig_port(intel_dp)->port;
2313
2314         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2315                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2316                 case DP_TRAIN_VOLTAGE_SWING_400:
2317                         return DP_TRAIN_PRE_EMPHASIS_9_5;
2318                 case DP_TRAIN_VOLTAGE_SWING_600:
2319                         return DP_TRAIN_PRE_EMPHASIS_6;
2320                 case DP_TRAIN_VOLTAGE_SWING_800:
2321                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2322                 case DP_TRAIN_VOLTAGE_SWING_1200:
2323                 default:
2324                         return DP_TRAIN_PRE_EMPHASIS_0;
2325                 }
2326         } else if (IS_VALLEYVIEW(dev)) {
2327                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2328                 case DP_TRAIN_VOLTAGE_SWING_400:
2329                         return DP_TRAIN_PRE_EMPHASIS_9_5;
2330                 case DP_TRAIN_VOLTAGE_SWING_600:
2331                         return DP_TRAIN_PRE_EMPHASIS_6;
2332                 case DP_TRAIN_VOLTAGE_SWING_800:
2333                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2334                 case DP_TRAIN_VOLTAGE_SWING_1200:
2335                 default:
2336                         return DP_TRAIN_PRE_EMPHASIS_0;
2337                 }
2338         } else if (IS_GEN7(dev) && port == PORT_A) {
2339                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2340                 case DP_TRAIN_VOLTAGE_SWING_400:
2341                         return DP_TRAIN_PRE_EMPHASIS_6;
2342                 case DP_TRAIN_VOLTAGE_SWING_600:
2343                 case DP_TRAIN_VOLTAGE_SWING_800:
2344                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2345                 default:
2346                         return DP_TRAIN_PRE_EMPHASIS_0;
2347                 }
2348         } else {
2349                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2350                 case DP_TRAIN_VOLTAGE_SWING_400:
2351                         return DP_TRAIN_PRE_EMPHASIS_6;
2352                 case DP_TRAIN_VOLTAGE_SWING_600:
2353                         return DP_TRAIN_PRE_EMPHASIS_6;
2354                 case DP_TRAIN_VOLTAGE_SWING_800:
2355                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2356                 case DP_TRAIN_VOLTAGE_SWING_1200:
2357                 default:
2358                         return DP_TRAIN_PRE_EMPHASIS_0;
2359                 }
2360         }
2361 }
2362
2363 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2364 {
2365         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2366         struct drm_i915_private *dev_priv = dev->dev_private;
2367         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2368         struct intel_crtc *intel_crtc =
2369                 to_intel_crtc(dport->base.base.crtc);
2370         unsigned long demph_reg_value, preemph_reg_value,
2371                 uniqtranscale_reg_value;
2372         uint8_t train_set = intel_dp->train_set[0];
2373         enum dpio_channel port = vlv_dport_to_channel(dport);
2374         int pipe = intel_crtc->pipe;
2375
2376         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2377         case DP_TRAIN_PRE_EMPHASIS_0:
2378                 preemph_reg_value = 0x0004000;
2379                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2380                 case DP_TRAIN_VOLTAGE_SWING_400:
2381                         demph_reg_value = 0x2B405555;
2382                         uniqtranscale_reg_value = 0x552AB83A;
2383                         break;
2384                 case DP_TRAIN_VOLTAGE_SWING_600:
2385                         demph_reg_value = 0x2B404040;
2386                         uniqtranscale_reg_value = 0x5548B83A;
2387                         break;
2388                 case DP_TRAIN_VOLTAGE_SWING_800:
2389                         demph_reg_value = 0x2B245555;
2390                         uniqtranscale_reg_value = 0x5560B83A;
2391                         break;
2392                 case DP_TRAIN_VOLTAGE_SWING_1200:
2393                         demph_reg_value = 0x2B405555;
2394                         uniqtranscale_reg_value = 0x5598DA3A;
2395                         break;
2396                 default:
2397                         return 0;
2398                 }
2399                 break;
2400         case DP_TRAIN_PRE_EMPHASIS_3_5:
2401                 preemph_reg_value = 0x0002000;
2402                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2403                 case DP_TRAIN_VOLTAGE_SWING_400:
2404                         demph_reg_value = 0x2B404040;
2405                         uniqtranscale_reg_value = 0x5552B83A;
2406                         break;
2407                 case DP_TRAIN_VOLTAGE_SWING_600:
2408                         demph_reg_value = 0x2B404848;
2409                         uniqtranscale_reg_value = 0x5580B83A;
2410                         break;
2411                 case DP_TRAIN_VOLTAGE_SWING_800:
2412                         demph_reg_value = 0x2B404040;
2413                         uniqtranscale_reg_value = 0x55ADDA3A;
2414                         break;
2415                 default:
2416                         return 0;
2417                 }
2418                 break;
2419         case DP_TRAIN_PRE_EMPHASIS_6:
2420                 preemph_reg_value = 0x0000000;
2421                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2422                 case DP_TRAIN_VOLTAGE_SWING_400:
2423                         demph_reg_value = 0x2B305555;
2424                         uniqtranscale_reg_value = 0x5570B83A;
2425                         break;
2426                 case DP_TRAIN_VOLTAGE_SWING_600:
2427                         demph_reg_value = 0x2B2B4040;
2428                         uniqtranscale_reg_value = 0x55ADDA3A;
2429                         break;
2430                 default:
2431                         return 0;
2432                 }
2433                 break;
2434         case DP_TRAIN_PRE_EMPHASIS_9_5:
2435                 preemph_reg_value = 0x0006000;
2436                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2437                 case DP_TRAIN_VOLTAGE_SWING_400:
2438                         demph_reg_value = 0x1B405555;
2439                         uniqtranscale_reg_value = 0x55ADDA3A;
2440                         break;
2441                 default:
2442                         return 0;
2443                 }
2444                 break;
2445         default:
2446                 return 0;
2447         }
2448
2449         mutex_lock(&dev_priv->dpio_lock);
2450         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2451         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2452         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
2453                          uniqtranscale_reg_value);
2454         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2455         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2456         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2457         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
2458         mutex_unlock(&dev_priv->dpio_lock);
2459
2460         return 0;
2461 }
2462
2463 static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2464 {
2465         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2466         struct drm_i915_private *dev_priv = dev->dev_private;
2467         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2468         struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
2469         u32 deemph_reg_value, margin_reg_value, val;
2470         uint8_t train_set = intel_dp->train_set[0];
2471         enum dpio_channel ch = vlv_dport_to_channel(dport);
2472         enum pipe pipe = intel_crtc->pipe;
2473         int i;
2474
2475         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2476         case DP_TRAIN_PRE_EMPHASIS_0:
2477                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2478                 case DP_TRAIN_VOLTAGE_SWING_400:
2479                         deemph_reg_value = 128;
2480                         margin_reg_value = 52;
2481                         break;
2482                 case DP_TRAIN_VOLTAGE_SWING_600:
2483                         deemph_reg_value = 128;
2484                         margin_reg_value = 77;
2485                         break;
2486                 case DP_TRAIN_VOLTAGE_SWING_800:
2487                         deemph_reg_value = 128;
2488                         margin_reg_value = 102;
2489                         break;
2490                 case DP_TRAIN_VOLTAGE_SWING_1200:
2491                         deemph_reg_value = 128;
2492                         margin_reg_value = 154;
2493                         /* FIXME extra to set for 1200 */
2494                         break;
2495                 default:
2496                         return 0;
2497                 }
2498                 break;
2499         case DP_TRAIN_PRE_EMPHASIS_3_5:
2500                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2501                 case DP_TRAIN_VOLTAGE_SWING_400:
2502                         deemph_reg_value = 85;
2503                         margin_reg_value = 78;
2504                         break;
2505                 case DP_TRAIN_VOLTAGE_SWING_600:
2506                         deemph_reg_value = 85;
2507                         margin_reg_value = 116;
2508                         break;
2509                 case DP_TRAIN_VOLTAGE_SWING_800:
2510                         deemph_reg_value = 85;
2511                         margin_reg_value = 154;
2512                         break;
2513                 default:
2514                         return 0;
2515                 }
2516                 break;
2517         case DP_TRAIN_PRE_EMPHASIS_6:
2518                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2519                 case DP_TRAIN_VOLTAGE_SWING_400:
2520                         deemph_reg_value = 64;
2521                         margin_reg_value = 104;
2522                         break;
2523                 case DP_TRAIN_VOLTAGE_SWING_600:
2524                         deemph_reg_value = 64;
2525                         margin_reg_value = 154;
2526                         break;
2527                 default:
2528                         return 0;
2529                 }
2530                 break;
2531         case DP_TRAIN_PRE_EMPHASIS_9_5:
2532                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2533                 case DP_TRAIN_VOLTAGE_SWING_400:
2534                         deemph_reg_value = 43;
2535                         margin_reg_value = 154;
2536                         break;
2537                 default:
2538                         return 0;
2539                 }
2540                 break;
2541         default:
2542                 return 0;
2543         }
2544
2545         mutex_lock(&dev_priv->dpio_lock);
2546
2547         /* Clear calc init */
2548         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2549         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2550         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2551
2552         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2553         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2554         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
2555
2556         /* Program swing deemph */
2557         for (i = 0; i < 4; i++) {
2558                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
2559                 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
2560                 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
2561                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
2562         }
2563
2564         /* Program swing margin */
2565         for (i = 0; i < 4; i++) {
2566                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2567                 val &= ~DPIO_SWING_MARGIN_MASK;
2568                 val |= margin_reg_value << DPIO_SWING_MARGIN_SHIFT;
2569                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2570         }
2571
2572         /* Disable unique transition scale */
2573         for (i = 0; i < 4; i++) {
2574                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2575                 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
2576                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2577         }
2578
2579         if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
2580                         == DP_TRAIN_PRE_EMPHASIS_0) &&
2581                 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
2582                         == DP_TRAIN_VOLTAGE_SWING_1200)) {
2583
2584                 /*
2585                  * The document said it needs to set bit 27 for ch0 and bit 26
2586                  * for ch1. Might be a typo in the doc.
2587                  * For now, for this unique transition scale selection, set bit
2588                  * 27 for ch0 and ch1.
2589                  */
2590                 for (i = 0; i < 4; i++) {
2591                         val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2592                         val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
2593                         vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2594                 }
2595
2596                 for (i = 0; i < 4; i++) {
2597                         val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2598                         val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2599                         val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2600                         vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2601                 }
2602         }
2603
2604         /* Start swing calculation */
2605         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2606         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2607         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2608
2609         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2610         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2611         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
2612
2613         /* LRC Bypass */
2614         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
2615         val |= DPIO_LRC_BYPASS;
2616         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
2617
2618         mutex_unlock(&dev_priv->dpio_lock);
2619
2620         return 0;
2621 }
2622
2623 static void
2624 intel_get_adjust_train(struct intel_dp *intel_dp,
2625                        const uint8_t link_status[DP_LINK_STATUS_SIZE])
2626 {
2627         uint8_t v = 0;
2628         uint8_t p = 0;
2629         int lane;
2630         uint8_t voltage_max;
2631         uint8_t preemph_max;
2632
2633         for (lane = 0; lane < intel_dp->lane_count; lane++) {
2634                 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2635                 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
2636
2637                 if (this_v > v)
2638                         v = this_v;
2639                 if (this_p > p)
2640                         p = this_p;
2641         }
2642
2643         voltage_max = intel_dp_voltage_max(intel_dp);
2644         if (v >= voltage_max)
2645                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
2646
2647         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2648         if (p >= preemph_max)
2649                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2650
2651         for (lane = 0; lane < 4; lane++)
2652                 intel_dp->train_set[lane] = v | p;
2653 }
2654
2655 static uint32_t
2656 intel_gen4_signal_levels(uint8_t train_set)
2657 {
2658         uint32_t        signal_levels = 0;
2659
2660         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2661         case DP_TRAIN_VOLTAGE_SWING_400:
2662         default:
2663                 signal_levels |= DP_VOLTAGE_0_4;
2664                 break;
2665         case DP_TRAIN_VOLTAGE_SWING_600:
2666                 signal_levels |= DP_VOLTAGE_0_6;
2667                 break;
2668         case DP_TRAIN_VOLTAGE_SWING_800:
2669                 signal_levels |= DP_VOLTAGE_0_8;
2670                 break;
2671         case DP_TRAIN_VOLTAGE_SWING_1200:
2672                 signal_levels |= DP_VOLTAGE_1_2;
2673                 break;
2674         }
2675         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2676         case DP_TRAIN_PRE_EMPHASIS_0:
2677         default:
2678                 signal_levels |= DP_PRE_EMPHASIS_0;
2679                 break;
2680         case DP_TRAIN_PRE_EMPHASIS_3_5:
2681                 signal_levels |= DP_PRE_EMPHASIS_3_5;
2682                 break;
2683         case DP_TRAIN_PRE_EMPHASIS_6:
2684                 signal_levels |= DP_PRE_EMPHASIS_6;
2685                 break;
2686         case DP_TRAIN_PRE_EMPHASIS_9_5:
2687                 signal_levels |= DP_PRE_EMPHASIS_9_5;
2688                 break;
2689         }
2690         return signal_levels;
2691 }
2692
2693 /* Gen6's DP voltage swing and pre-emphasis control */
2694 static uint32_t
2695 intel_gen6_edp_signal_levels(uint8_t train_set)
2696 {
2697         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2698                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2699         switch (signal_levels) {
2700         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2701         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2702                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2703         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2704                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
2705         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2706         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2707                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
2708         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2709         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2710                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
2711         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2712         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2713                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
2714         default:
2715                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2716                               "0x%x\n", signal_levels);
2717                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2718         }
2719 }
2720
2721 /* Gen7's DP voltage swing and pre-emphasis control */
2722 static uint32_t
2723 intel_gen7_edp_signal_levels(uint8_t train_set)
2724 {
2725         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2726                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2727         switch (signal_levels) {
2728         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2729                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2730         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2731                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2732         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2733                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2734
2735         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2736                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2737         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2738                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2739
2740         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2741                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2742         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2743                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2744
2745         default:
2746                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2747                               "0x%x\n", signal_levels);
2748                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2749         }
2750 }
2751
2752 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2753 static uint32_t
2754 intel_hsw_signal_levels(uint8_t train_set)
2755 {
2756         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2757                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2758         switch (signal_levels) {
2759         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2760                 return DDI_BUF_EMP_400MV_0DB_HSW;
2761         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2762                 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2763         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2764                 return DDI_BUF_EMP_400MV_6DB_HSW;
2765         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2766                 return DDI_BUF_EMP_400MV_9_5DB_HSW;
2767
2768         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2769                 return DDI_BUF_EMP_600MV_0DB_HSW;
2770         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2771                 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2772         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2773                 return DDI_BUF_EMP_600MV_6DB_HSW;
2774
2775         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2776                 return DDI_BUF_EMP_800MV_0DB_HSW;
2777         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2778                 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2779         default:
2780                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2781                               "0x%x\n", signal_levels);
2782                 return DDI_BUF_EMP_400MV_0DB_HSW;
2783         }
2784 }
2785
2786 /* Properly updates "DP" with the correct signal levels. */
2787 static void
2788 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2789 {
2790         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2791         enum port port = intel_dig_port->port;
2792         struct drm_device *dev = intel_dig_port->base.base.dev;
2793         uint32_t signal_levels, mask;
2794         uint8_t train_set = intel_dp->train_set[0];
2795
2796         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2797                 signal_levels = intel_hsw_signal_levels(train_set);
2798                 mask = DDI_BUF_EMP_MASK;
2799         } else if (IS_CHERRYVIEW(dev)) {
2800                 signal_levels = intel_chv_signal_levels(intel_dp);
2801                 mask = 0;
2802         } else if (IS_VALLEYVIEW(dev)) {
2803                 signal_levels = intel_vlv_signal_levels(intel_dp);
2804                 mask = 0;
2805         } else if (IS_GEN7(dev) && port == PORT_A) {
2806                 signal_levels = intel_gen7_edp_signal_levels(train_set);
2807                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
2808         } else if (IS_GEN6(dev) && port == PORT_A) {
2809                 signal_levels = intel_gen6_edp_signal_levels(train_set);
2810                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2811         } else {
2812                 signal_levels = intel_gen4_signal_levels(train_set);
2813                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2814         }
2815
2816         DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2817
2818         *DP = (*DP & ~mask) | signal_levels;
2819 }
2820
2821 static bool
2822 intel_dp_set_link_train(struct intel_dp *intel_dp,
2823                         uint32_t *DP,
2824                         uint8_t dp_train_pat)
2825 {
2826         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2827         struct drm_device *dev = intel_dig_port->base.base.dev;
2828         struct drm_i915_private *dev_priv = dev->dev_private;
2829         enum port port = intel_dig_port->port;
2830         uint8_t buf[sizeof(intel_dp->train_set) + 1];
2831         int ret, len;
2832
2833         if (HAS_DDI(dev)) {
2834                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2835
2836                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2837                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2838                 else
2839                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2840
2841                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2842                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2843                 case DP_TRAINING_PATTERN_DISABLE:
2844                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2845
2846                         break;
2847                 case DP_TRAINING_PATTERN_1:
2848                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2849                         break;
2850                 case DP_TRAINING_PATTERN_2:
2851                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2852                         break;
2853                 case DP_TRAINING_PATTERN_3:
2854                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2855                         break;
2856                 }
2857                 I915_WRITE(DP_TP_CTL(port), temp);
2858
2859         } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2860                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2861
2862                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2863                 case DP_TRAINING_PATTERN_DISABLE:
2864                         *DP |= DP_LINK_TRAIN_OFF_CPT;
2865                         break;
2866                 case DP_TRAINING_PATTERN_1:
2867                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2868                         break;
2869                 case DP_TRAINING_PATTERN_2:
2870                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2871                         break;
2872                 case DP_TRAINING_PATTERN_3:
2873                         DRM_ERROR("DP training pattern 3 not supported\n");
2874                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2875                         break;
2876                 }
2877
2878         } else {
2879                 *DP &= ~DP_LINK_TRAIN_MASK;
2880
2881                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2882                 case DP_TRAINING_PATTERN_DISABLE:
2883                         *DP |= DP_LINK_TRAIN_OFF;
2884                         break;
2885                 case DP_TRAINING_PATTERN_1:
2886                         *DP |= DP_LINK_TRAIN_PAT_1;
2887                         break;
2888                 case DP_TRAINING_PATTERN_2:
2889                         *DP |= DP_LINK_TRAIN_PAT_2;
2890                         break;
2891                 case DP_TRAINING_PATTERN_3:
2892                         DRM_ERROR("DP training pattern 3 not supported\n");
2893                         *DP |= DP_LINK_TRAIN_PAT_2;
2894                         break;
2895                 }
2896         }
2897
2898         I915_WRITE(intel_dp->output_reg, *DP);
2899         POSTING_READ(intel_dp->output_reg);
2900
2901         buf[0] = dp_train_pat;
2902         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
2903             DP_TRAINING_PATTERN_DISABLE) {
2904                 /* don't write DP_TRAINING_LANEx_SET on disable */
2905                 len = 1;
2906         } else {
2907                 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2908                 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2909                 len = intel_dp->lane_count + 1;
2910         }
2911
2912         ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
2913                                 buf, len);
2914
2915         return ret == len;
2916 }
2917
2918 static bool
2919 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2920                         uint8_t dp_train_pat)
2921 {
2922         memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
2923         intel_dp_set_signal_levels(intel_dp, DP);
2924         return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2925 }
2926
2927 static bool
2928 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2929                            const uint8_t link_status[DP_LINK_STATUS_SIZE])
2930 {
2931         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2932         struct drm_device *dev = intel_dig_port->base.base.dev;
2933         struct drm_i915_private *dev_priv = dev->dev_private;
2934         int ret;
2935
2936         intel_get_adjust_train(intel_dp, link_status);
2937         intel_dp_set_signal_levels(intel_dp, DP);
2938
2939         I915_WRITE(intel_dp->output_reg, *DP);
2940         POSTING_READ(intel_dp->output_reg);
2941
2942         ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
2943                                 intel_dp->train_set, intel_dp->lane_count);
2944
2945         return ret == intel_dp->lane_count;
2946 }
2947
2948 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2949 {
2950         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2951         struct drm_device *dev = intel_dig_port->base.base.dev;
2952         struct drm_i915_private *dev_priv = dev->dev_private;
2953         enum port port = intel_dig_port->port;
2954         uint32_t val;
2955
2956         if (!HAS_DDI(dev))
2957                 return;
2958
2959         val = I915_READ(DP_TP_CTL(port));
2960         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2961         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2962         I915_WRITE(DP_TP_CTL(port), val);
2963
2964         /*
2965          * On PORT_A we can have only eDP in SST mode. There the only reason
2966          * we need to set idle transmission mode is to work around a HW issue
2967          * where we enable the pipe while not in idle link-training mode.
2968          * In this case there is requirement to wait for a minimum number of
2969          * idle patterns to be sent.
2970          */
2971         if (port == PORT_A)
2972                 return;
2973
2974         if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2975                      1))
2976                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2977 }
2978
2979 /* Enable corresponding port and start training pattern 1 */
2980 void
2981 intel_dp_start_link_train(struct intel_dp *intel_dp)
2982 {
2983         struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2984         struct drm_device *dev = encoder->dev;
2985         int i;
2986         uint8_t voltage;
2987         int voltage_tries, loop_tries;
2988         uint32_t DP = intel_dp->DP;
2989         uint8_t link_config[2];
2990
2991         if (HAS_DDI(dev))
2992                 intel_ddi_prepare_link_retrain(encoder);
2993
2994         /* Write the link configuration data */
2995         link_config[0] = intel_dp->link_bw;
2996         link_config[1] = intel_dp->lane_count;
2997         if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2998                 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
2999         drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
3000
3001         link_config[0] = 0;
3002         link_config[1] = DP_SET_ANSI_8B10B;
3003         drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
3004
3005         DP |= DP_PORT_EN;
3006
3007         /* clock recovery */
3008         if (!intel_dp_reset_link_train(intel_dp, &DP,
3009                                        DP_TRAINING_PATTERN_1 |
3010                                        DP_LINK_SCRAMBLING_DISABLE)) {
3011                 DRM_ERROR("failed to enable link training\n");
3012                 return;
3013         }
3014
3015         voltage = 0xff;
3016         voltage_tries = 0;
3017         loop_tries = 0;
3018         for (;;) {
3019                 uint8_t link_status[DP_LINK_STATUS_SIZE];
3020
3021                 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
3022                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3023                         DRM_ERROR("failed to get link status\n");
3024                         break;
3025                 }
3026
3027                 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3028                         DRM_DEBUG_KMS("clock recovery OK\n");
3029                         break;
3030                 }
3031
3032                 /* Check to see if we've tried the max voltage */
3033                 for (i = 0; i < intel_dp->lane_count; i++)
3034                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
3035                                 break;
3036                 if (i == intel_dp->lane_count) {
3037                         ++loop_tries;
3038                         if (loop_tries == 5) {
3039                                 DRM_ERROR("too many full retries, give up\n");
3040                                 break;
3041                         }
3042                         intel_dp_reset_link_train(intel_dp, &DP,
3043                                                   DP_TRAINING_PATTERN_1 |
3044                                                   DP_LINK_SCRAMBLING_DISABLE);
3045                         voltage_tries = 0;
3046                         continue;
3047                 }
3048
3049                 /* Check to see if we've tried the same voltage 5 times */
3050                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
3051                         ++voltage_tries;
3052                         if (voltage_tries == 5) {
3053                                 DRM_ERROR("too many voltage retries, give up\n");
3054                                 break;
3055                         }
3056                 } else
3057                         voltage_tries = 0;
3058                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
3059
3060                 /* Update training set as requested by target */
3061                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3062                         DRM_ERROR("failed to update link training\n");
3063                         break;
3064                 }
3065         }
3066
3067         intel_dp->DP = DP;
3068 }
3069
3070 void
3071 intel_dp_complete_link_train(struct intel_dp *intel_dp)
3072 {
3073         bool channel_eq = false;
3074         int tries, cr_tries;
3075         uint32_t DP = intel_dp->DP;
3076         uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3077
3078         /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3079         if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3080                 training_pattern = DP_TRAINING_PATTERN_3;
3081
3082         /* channel equalization */
3083         if (!intel_dp_set_link_train(intel_dp, &DP,
3084                                      training_pattern |
3085                                      DP_LINK_SCRAMBLING_DISABLE)) {
3086                 DRM_ERROR("failed to start channel equalization\n");
3087                 return;
3088         }
3089
3090         tries = 0;
3091         cr_tries = 0;
3092         channel_eq = false;
3093         for (;;) {
3094                 uint8_t link_status[DP_LINK_STATUS_SIZE];
3095
3096                 if (cr_tries > 5) {
3097                         DRM_ERROR("failed to train DP, aborting\n");
3098                         break;
3099                 }
3100
3101                 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
3102                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3103                         DRM_ERROR("failed to get link status\n");
3104                         break;
3105                 }
3106
3107                 /* Make sure clock is still ok */
3108                 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3109                         intel_dp_start_link_train(intel_dp);
3110                         intel_dp_set_link_train(intel_dp, &DP,
3111                                                 training_pattern |
3112                                                 DP_LINK_SCRAMBLING_DISABLE);
3113                         cr_tries++;
3114                         continue;
3115                 }
3116
3117                 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3118                         channel_eq = true;
3119                         break;
3120                 }
3121
3122                 /* Try 5 times, then try clock recovery if that fails */
3123                 if (tries > 5) {
3124                         intel_dp_link_down(intel_dp);
3125                         intel_dp_start_link_train(intel_dp);
3126                         intel_dp_set_link_train(intel_dp, &DP,
3127                                                 training_pattern |
3128                                                 DP_LINK_SCRAMBLING_DISABLE);
3129                         tries = 0;
3130                         cr_tries++;
3131                         continue;
3132                 }
3133
3134                 /* Update training set as requested by target */
3135                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3136                         DRM_ERROR("failed to update link training\n");
3137                         break;
3138                 }
3139                 ++tries;
3140         }
3141
3142         intel_dp_set_idle_link_train(intel_dp);
3143
3144         intel_dp->DP = DP;
3145
3146         if (channel_eq)
3147                 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3148
3149 }
3150
3151 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3152 {
3153         intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3154                                 DP_TRAINING_PATTERN_DISABLE);
3155 }
3156
3157 static void
3158 intel_dp_link_down(struct intel_dp *intel_dp)
3159 {
3160         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3161         enum port port = intel_dig_port->port;
3162         struct drm_device *dev = intel_dig_port->base.base.dev;
3163         struct drm_i915_private *dev_priv = dev->dev_private;
3164         struct intel_crtc *intel_crtc =
3165                 to_intel_crtc(intel_dig_port->base.base.crtc);
3166         uint32_t DP = intel_dp->DP;
3167
3168         if (WARN_ON(HAS_DDI(dev)))
3169                 return;
3170
3171         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3172                 return;
3173
3174         DRM_DEBUG_KMS("\n");
3175
3176         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
3177                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3178                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
3179         } else {
3180                 DP &= ~DP_LINK_TRAIN_MASK;
3181                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
3182         }
3183         POSTING_READ(intel_dp->output_reg);
3184
3185         if (HAS_PCH_IBX(dev) &&
3186             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
3187                 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
3188
3189                 /* Hardware workaround: leaving our transcoder select
3190                  * set to transcoder B while it's off will prevent the
3191                  * corresponding HDMI output on transcoder A.
3192                  *
3193                  * Combine this with another hardware workaround:
3194                  * transcoder select bit can only be cleared while the
3195                  * port is enabled.
3196                  */
3197                 DP &= ~DP_PIPEB_SELECT;
3198                 I915_WRITE(intel_dp->output_reg, DP);
3199
3200                 /* Changes to enable or select take place the vblank
3201                  * after being written.
3202                  */
3203                 if (WARN_ON(crtc == NULL)) {
3204                         /* We should never try to disable a port without a crtc
3205                          * attached. For paranoia keep the code around for a
3206                          * bit. */
3207                         POSTING_READ(intel_dp->output_reg);
3208                         msleep(50);
3209                 } else
3210                         intel_wait_for_vblank(dev, intel_crtc->pipe);
3211         }
3212
3213         DP &= ~DP_AUDIO_OUTPUT_ENABLE;
3214         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3215         POSTING_READ(intel_dp->output_reg);
3216         msleep(intel_dp->panel_power_down_delay);
3217 }
3218
3219 static bool
3220 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3221 {
3222         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3223         struct drm_device *dev = dig_port->base.base.dev;
3224         struct drm_i915_private *dev_priv = dev->dev_private;
3225
3226         char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
3227
3228         if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3229                                     sizeof(intel_dp->dpcd)) < 0)
3230                 return false; /* aux transfer failed */
3231
3232         hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
3233                            32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
3234         DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
3235
3236         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3237                 return false; /* DPCD not present */
3238
3239         /* Check if the panel supports PSR */
3240         memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
3241         if (is_edp(intel_dp)) {
3242                 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3243                                         intel_dp->psr_dpcd,
3244                                         sizeof(intel_dp->psr_dpcd));
3245                 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3246                         dev_priv->psr.sink_support = true;
3247                         DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3248                 }
3249         }
3250
3251         /* Training Pattern 3 support */
3252         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3253             intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3254                 intel_dp->use_tps3 = true;
3255                 DRM_DEBUG_KMS("Displayport TPS3 supported");
3256         } else
3257                 intel_dp->use_tps3 = false;
3258
3259         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3260               DP_DWN_STRM_PORT_PRESENT))
3261                 return true; /* native DP sink */
3262
3263         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3264                 return true; /* no per-port downstream info */
3265
3266         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3267                                     intel_dp->downstream_ports,
3268                                     DP_MAX_DOWNSTREAM_PORTS) < 0)
3269                 return false; /* downstream port status fetch failed */
3270
3271         return true;
3272 }
3273
3274 static void
3275 intel_dp_probe_oui(struct intel_dp *intel_dp)
3276 {
3277         u8 buf[3];
3278
3279         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3280                 return;
3281
3282         intel_edp_panel_vdd_on(intel_dp);
3283
3284         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
3285                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3286                               buf[0], buf[1], buf[2]);
3287
3288         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
3289                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3290                               buf[0], buf[1], buf[2]);
3291
3292         edp_panel_vdd_off(intel_dp, false);
3293 }
3294
3295 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3296 {
3297         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3298         struct drm_device *dev = intel_dig_port->base.base.dev;
3299         struct intel_crtc *intel_crtc =
3300                 to_intel_crtc(intel_dig_port->base.base.crtc);
3301         u8 buf[1];
3302
3303         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
3304                 return -EAGAIN;
3305
3306         if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
3307                 return -ENOTTY;
3308
3309         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3310                                DP_TEST_SINK_START) < 0)
3311                 return -EAGAIN;
3312
3313         /* Wait 2 vblanks to be sure we will have the correct CRC value */
3314         intel_wait_for_vblank(dev, intel_crtc->pipe);
3315         intel_wait_for_vblank(dev, intel_crtc->pipe);
3316
3317         if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
3318                 return -EAGAIN;
3319
3320         drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
3321         return 0;
3322 }
3323
3324 static bool
3325 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3326 {
3327         return intel_dp_dpcd_read_wake(&intel_dp->aux,
3328                                        DP_DEVICE_SERVICE_IRQ_VECTOR,
3329                                        sink_irq_vector, 1) == 1;
3330 }
3331
3332 static void
3333 intel_dp_handle_test_request(struct intel_dp *intel_dp)
3334 {
3335         /* NAK by default */
3336         drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
3337 }
3338
3339 /*
3340  * According to DP spec
3341  * 5.1.2:
3342  *  1. Read DPCD
3343  *  2. Configure link according to Receiver Capabilities
3344  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
3345  *  4. Check link status on receipt of hot-plug interrupt
3346  */
3347
3348 void
3349 intel_dp_check_link_status(struct intel_dp *intel_dp)
3350 {
3351         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
3352         u8 sink_irq_vector;
3353         u8 link_status[DP_LINK_STATUS_SIZE];
3354
3355         /* FIXME: This access isn't protected by any locks. */
3356         if (!intel_encoder->connectors_active)
3357                 return;
3358
3359         if (WARN_ON(!intel_encoder->base.crtc))
3360                 return;
3361
3362         /* Try to read receiver status if the link appears to be up */
3363         if (!intel_dp_get_link_status(intel_dp, link_status)) {
3364                 return;
3365         }
3366
3367         /* Now read the DPCD to see if it's actually running */
3368         if (!intel_dp_get_dpcd(intel_dp)) {
3369                 return;
3370         }
3371
3372         /* Try to read the source of the interrupt */
3373         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3374             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3375                 /* Clear interrupt source */
3376                 drm_dp_dpcd_writeb(&intel_dp->aux,
3377                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
3378                                    sink_irq_vector);
3379
3380                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3381                         intel_dp_handle_test_request(intel_dp);
3382                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3383                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3384         }
3385
3386         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3387                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3388                               intel_encoder->base.name);
3389                 intel_dp_start_link_train(intel_dp);
3390                 intel_dp_complete_link_train(intel_dp);
3391                 intel_dp_stop_link_train(intel_dp);
3392         }
3393 }
3394
3395 /* XXX this is probably wrong for multiple downstream ports */
3396 static enum drm_connector_status
3397 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
3398 {
3399         uint8_t *dpcd = intel_dp->dpcd;
3400         uint8_t type;
3401
3402         if (!intel_dp_get_dpcd(intel_dp))
3403                 return connector_status_disconnected;
3404
3405         /* if there's no downstream port, we're done */
3406         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
3407                 return connector_status_connected;
3408
3409         /* If we're HPD-aware, SINK_COUNT changes dynamically */
3410         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3411             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
3412                 uint8_t reg;
3413
3414                 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3415                                             &reg, 1) < 0)
3416                         return connector_status_unknown;
3417
3418                 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3419                                               : connector_status_disconnected;
3420         }
3421
3422         /* If no HPD, poke DDC gently */
3423         if (drm_probe_ddc(&intel_dp->aux.ddc))
3424                 return connector_status_connected;
3425
3426         /* Well we tried, say unknown for unreliable port types */
3427         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3428                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3429                 if (type == DP_DS_PORT_TYPE_VGA ||
3430                     type == DP_DS_PORT_TYPE_NON_EDID)
3431                         return connector_status_unknown;
3432         } else {
3433                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3434                         DP_DWN_STRM_PORT_TYPE_MASK;
3435                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3436                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
3437                         return connector_status_unknown;
3438         }
3439
3440         /* Anything else is out of spec, warn and ignore */
3441         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
3442         return connector_status_disconnected;
3443 }
3444
3445 static enum drm_connector_status
3446 ironlake_dp_detect(struct intel_dp *intel_dp)
3447 {
3448         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3449         struct drm_i915_private *dev_priv = dev->dev_private;
3450         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3451         enum drm_connector_status status;
3452
3453         /* Can't disconnect eDP, but you can close the lid... */
3454         if (is_edp(intel_dp)) {
3455                 status = intel_panel_detect(dev);
3456                 if (status == connector_status_unknown)
3457                         status = connector_status_connected;
3458                 return status;
3459         }
3460
3461         if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3462                 return connector_status_disconnected;
3463
3464         return intel_dp_detect_dpcd(intel_dp);
3465 }
3466
3467 static enum drm_connector_status
3468 g4x_dp_detect(struct intel_dp *intel_dp)
3469 {
3470         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3471         struct drm_i915_private *dev_priv = dev->dev_private;
3472         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3473         uint32_t bit;
3474
3475         /* Can't disconnect eDP, but you can close the lid... */
3476         if (is_edp(intel_dp)) {
3477                 enum drm_connector_status status;
3478
3479                 status = intel_panel_detect(dev);
3480                 if (status == connector_status_unknown)
3481                         status = connector_status_connected;
3482                 return status;
3483         }
3484
3485         if (IS_VALLEYVIEW(dev)) {
3486                 switch (intel_dig_port->port) {
3487                 case PORT_B:
3488                         bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3489                         break;
3490                 case PORT_C:
3491                         bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3492                         break;
3493                 case PORT_D:
3494                         bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3495                         break;
3496                 default:
3497                         return connector_status_unknown;
3498                 }
3499         } else {
3500                 switch (intel_dig_port->port) {
3501                 case PORT_B:
3502                         bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3503                         break;
3504                 case PORT_C:
3505                         bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3506                         break;
3507                 case PORT_D:
3508                         bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3509                         break;
3510                 default:
3511                         return connector_status_unknown;
3512                 }
3513         }
3514
3515         if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
3516                 return connector_status_disconnected;
3517
3518         return intel_dp_detect_dpcd(intel_dp);
3519 }
3520
3521 static struct edid *
3522 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3523 {
3524         struct intel_connector *intel_connector = to_intel_connector(connector);
3525
3526         /* use cached edid if we have one */
3527         if (intel_connector->edid) {
3528                 /* invalid edid */
3529                 if (IS_ERR(intel_connector->edid))
3530                         return NULL;
3531
3532                 return drm_edid_duplicate(intel_connector->edid);
3533         }
3534
3535         return drm_get_edid(connector, adapter);
3536 }
3537
3538 static int
3539 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3540 {
3541         struct intel_connector *intel_connector = to_intel_connector(connector);
3542
3543         /* use cached edid if we have one */
3544         if (intel_connector->edid) {
3545                 /* invalid edid */
3546                 if (IS_ERR(intel_connector->edid))
3547                         return 0;
3548
3549                 return intel_connector_update_modes(connector,
3550                                                     intel_connector->edid);
3551         }
3552
3553         return intel_ddc_get_modes(connector, adapter);
3554 }
3555
3556 static enum drm_connector_status
3557 intel_dp_detect(struct drm_connector *connector, bool force)
3558 {
3559         struct intel_dp *intel_dp = intel_attached_dp(connector);
3560         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3561         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3562         struct drm_device *dev = connector->dev;
3563         struct drm_i915_private *dev_priv = dev->dev_private;
3564         enum drm_connector_status status;
3565         enum intel_display_power_domain power_domain;
3566         struct edid *edid = NULL;
3567
3568         intel_runtime_pm_get(dev_priv);
3569
3570         power_domain = intel_display_port_power_domain(intel_encoder);
3571         intel_display_power_get(dev_priv, power_domain);
3572
3573         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3574                       connector->base.id, connector->name);
3575
3576         intel_dp->has_audio = false;
3577
3578         if (HAS_PCH_SPLIT(dev))
3579                 status = ironlake_dp_detect(intel_dp);
3580         else
3581                 status = g4x_dp_detect(intel_dp);
3582
3583         if (status != connector_status_connected)
3584                 goto out;
3585
3586         intel_dp_probe_oui(intel_dp);
3587
3588         if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3589                 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
3590         } else {
3591                 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
3592                 if (edid) {
3593                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
3594                         kfree(edid);
3595                 }
3596         }
3597
3598         if (intel_encoder->type != INTEL_OUTPUT_EDP)
3599                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3600         status = connector_status_connected;
3601
3602 out:
3603         intel_display_power_put(dev_priv, power_domain);
3604
3605         intel_runtime_pm_put(dev_priv);
3606
3607         return status;
3608 }
3609
3610 static int intel_dp_get_modes(struct drm_connector *connector)
3611 {
3612         struct intel_dp *intel_dp = intel_attached_dp(connector);
3613         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3614         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3615         struct intel_connector *intel_connector = to_intel_connector(connector);
3616         struct drm_device *dev = connector->dev;
3617         struct drm_i915_private *dev_priv = dev->dev_private;
3618         enum intel_display_power_domain power_domain;
3619         int ret;
3620
3621         /* We should parse the EDID data and find out if it has an audio sink
3622          */
3623
3624         power_domain = intel_display_port_power_domain(intel_encoder);
3625         intel_display_power_get(dev_priv, power_domain);
3626
3627         ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
3628         intel_display_power_put(dev_priv, power_domain);
3629         if (ret)
3630                 return ret;
3631
3632         /* if eDP has no EDID, fall back to fixed mode */
3633         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
3634                 struct drm_display_mode *mode;
3635                 mode = drm_mode_duplicate(dev,
3636                                           intel_connector->panel.fixed_mode);
3637                 if (mode) {
3638                         drm_mode_probed_add(connector, mode);
3639                         return 1;
3640                 }
3641         }
3642         return 0;
3643 }
3644
3645 static bool
3646 intel_dp_detect_audio(struct drm_connector *connector)
3647 {
3648         struct intel_dp *intel_dp = intel_attached_dp(connector);
3649         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3650         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3651         struct drm_device *dev = connector->dev;
3652         struct drm_i915_private *dev_priv = dev->dev_private;
3653         enum intel_display_power_domain power_domain;
3654         struct edid *edid;
3655         bool has_audio = false;
3656
3657         power_domain = intel_display_port_power_domain(intel_encoder);
3658         intel_display_power_get(dev_priv, power_domain);
3659
3660         edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
3661         if (edid) {
3662                 has_audio = drm_detect_monitor_audio(edid);
3663                 kfree(edid);
3664         }
3665
3666         intel_display_power_put(dev_priv, power_domain);
3667
3668         return has_audio;
3669 }
3670
3671 static int
3672 intel_dp_set_property(struct drm_connector *connector,
3673                       struct drm_property *property,
3674                       uint64_t val)
3675 {
3676         struct drm_i915_private *dev_priv = connector->dev->dev_private;
3677         struct intel_connector *intel_connector = to_intel_connector(connector);
3678         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3679         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3680         int ret;
3681
3682         ret = drm_object_property_set_value(&connector->base, property, val);
3683         if (ret)
3684                 return ret;
3685
3686         if (property == dev_priv->force_audio_property) {
3687                 int i = val;
3688                 bool has_audio;
3689
3690                 if (i == intel_dp->force_audio)
3691                         return 0;
3692
3693                 intel_dp->force_audio = i;
3694
3695                 if (i == HDMI_AUDIO_AUTO)
3696                         has_audio = intel_dp_detect_audio(connector);
3697                 else
3698                         has_audio = (i == HDMI_AUDIO_ON);
3699
3700                 if (has_audio == intel_dp->has_audio)
3701                         return 0;
3702
3703                 intel_dp->has_audio = has_audio;
3704                 goto done;
3705         }
3706
3707         if (property == dev_priv->broadcast_rgb_property) {
3708                 bool old_auto = intel_dp->color_range_auto;
3709                 uint32_t old_range = intel_dp->color_range;
3710
3711                 switch (val) {
3712                 case INTEL_BROADCAST_RGB_AUTO:
3713                         intel_dp->color_range_auto = true;
3714                         break;
3715                 case INTEL_BROADCAST_RGB_FULL:
3716                         intel_dp->color_range_auto = false;
3717                         intel_dp->color_range = 0;
3718                         break;
3719                 case INTEL_BROADCAST_RGB_LIMITED:
3720                         intel_dp->color_range_auto = false;
3721                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
3722                         break;
3723                 default:
3724                         return -EINVAL;
3725                 }
3726
3727                 if (old_auto == intel_dp->color_range_auto &&
3728                     old_range == intel_dp->color_range)
3729                         return 0;
3730
3731                 goto done;
3732         }
3733
3734         if (is_edp(intel_dp) &&
3735             property == connector->dev->mode_config.scaling_mode_property) {
3736                 if (val == DRM_MODE_SCALE_NONE) {
3737                         DRM_DEBUG_KMS("no scaling not supported\n");
3738                         return -EINVAL;
3739                 }
3740
3741                 if (intel_connector->panel.fitting_mode == val) {
3742                         /* the eDP scaling property is not changed */
3743                         return 0;
3744                 }
3745                 intel_connector->panel.fitting_mode = val;
3746
3747                 goto done;
3748         }
3749
3750         return -EINVAL;
3751
3752 done:
3753         if (intel_encoder->base.crtc)
3754                 intel_crtc_restore_mode(intel_encoder->base.crtc);
3755
3756         return 0;
3757 }
3758
3759 static void
3760 intel_dp_connector_destroy(struct drm_connector *connector)
3761 {
3762         struct intel_connector *intel_connector = to_intel_connector(connector);
3763
3764         if (!IS_ERR_OR_NULL(intel_connector->edid))
3765                 kfree(intel_connector->edid);
3766
3767         /* Can't call is_edp() since the encoder may have been destroyed
3768          * already. */
3769         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3770                 intel_panel_fini(&intel_connector->panel);
3771
3772         drm_connector_cleanup(connector);
3773         kfree(connector);
3774 }
3775
3776 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
3777 {
3778         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3779         struct intel_dp *intel_dp = &intel_dig_port->dp;
3780         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3781
3782         drm_dp_aux_unregister(&intel_dp->aux);
3783         drm_encoder_cleanup(encoder);
3784         if (is_edp(intel_dp)) {
3785                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3786                 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
3787                 edp_panel_vdd_off_sync(intel_dp);
3788                 drm_modeset_unlock(&dev->mode_config.connection_mutex);
3789         }
3790         kfree(intel_dig_port);
3791 }
3792
3793 static const struct drm_connector_funcs intel_dp_connector_funcs = {
3794         .dpms = intel_connector_dpms,
3795         .detect = intel_dp_detect,
3796         .fill_modes = drm_helper_probe_single_connector_modes,
3797         .set_property = intel_dp_set_property,
3798         .destroy = intel_dp_connector_destroy,
3799 };
3800
3801 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3802         .get_modes = intel_dp_get_modes,
3803         .mode_valid = intel_dp_mode_valid,
3804         .best_encoder = intel_best_encoder,
3805 };
3806
3807 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
3808         .destroy = intel_dp_encoder_destroy,
3809 };
3810
3811 static void
3812 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
3813 {
3814         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3815
3816         intel_dp_check_link_status(intel_dp);
3817 }
3818
3819 /* Return which DP Port should be selected for Transcoder DP control */
3820 int
3821 intel_trans_dp_port_sel(struct drm_crtc *crtc)
3822 {
3823         struct drm_device *dev = crtc->dev;
3824         struct intel_encoder *intel_encoder;
3825         struct intel_dp *intel_dp;
3826
3827         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3828                 intel_dp = enc_to_intel_dp(&intel_encoder->base);
3829
3830                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3831                     intel_encoder->type == INTEL_OUTPUT_EDP)
3832                         return intel_dp->output_reg;
3833         }
3834
3835         return -1;
3836 }
3837
3838 /* check the VBT to see whether the eDP is on DP-D port */
3839 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
3840 {
3841         struct drm_i915_private *dev_priv = dev->dev_private;
3842         union child_device_config *p_child;
3843         int i;
3844         static const short port_mapping[] = {
3845                 [PORT_B] = PORT_IDPB,
3846                 [PORT_C] = PORT_IDPC,
3847                 [PORT_D] = PORT_IDPD,
3848         };
3849
3850         if (port == PORT_A)
3851                 return true;
3852
3853         if (!dev_priv->vbt.child_dev_num)
3854                 return false;
3855
3856         for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3857                 p_child = dev_priv->vbt.child_dev + i;
3858
3859                 if (p_child->common.dvo_port == port_mapping[port] &&
3860                     (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3861                     (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
3862                         return true;
3863         }
3864         return false;
3865 }
3866
3867 static void
3868 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3869 {
3870         struct intel_connector *intel_connector = to_intel_connector(connector);
3871
3872         intel_attach_force_audio_property(connector);
3873         intel_attach_broadcast_rgb_property(connector);
3874         intel_dp->color_range_auto = true;
3875
3876         if (is_edp(intel_dp)) {
3877                 drm_mode_create_scaling_mode_property(connector->dev);
3878                 drm_object_attach_property(
3879                         &connector->base,
3880                         connector->dev->mode_config.scaling_mode_property,
3881                         DRM_MODE_SCALE_ASPECT);
3882                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
3883         }
3884 }
3885
3886 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
3887 {
3888         intel_dp->last_power_cycle = jiffies;
3889         intel_dp->last_power_on = jiffies;
3890         intel_dp->last_backlight_off = jiffies;
3891 }
3892
3893 static void
3894 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
3895                                     struct intel_dp *intel_dp,
3896                                     struct edp_power_seq *out)
3897 {
3898         struct drm_i915_private *dev_priv = dev->dev_private;
3899         struct edp_power_seq cur, vbt, spec, final;
3900         u32 pp_on, pp_off, pp_div, pp;
3901         int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
3902
3903         if (HAS_PCH_SPLIT(dev)) {
3904                 pp_ctrl_reg = PCH_PP_CONTROL;
3905                 pp_on_reg = PCH_PP_ON_DELAYS;
3906                 pp_off_reg = PCH_PP_OFF_DELAYS;
3907                 pp_div_reg = PCH_PP_DIVISOR;
3908         } else {
3909                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3910
3911                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3912                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3913                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3914                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3915         }
3916
3917         /* Workaround: Need to write PP_CONTROL with the unlock key as
3918          * the very first thing. */
3919         pp = ironlake_get_pp_control(intel_dp);
3920         I915_WRITE(pp_ctrl_reg, pp);
3921
3922         pp_on = I915_READ(pp_on_reg);
3923         pp_off = I915_READ(pp_off_reg);
3924         pp_div = I915_READ(pp_div_reg);
3925
3926         /* Pull timing values out of registers */
3927         cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3928                 PANEL_POWER_UP_DELAY_SHIFT;
3929
3930         cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3931                 PANEL_LIGHT_ON_DELAY_SHIFT;
3932
3933         cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3934                 PANEL_LIGHT_OFF_DELAY_SHIFT;
3935
3936         cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3937                 PANEL_POWER_DOWN_DELAY_SHIFT;
3938
3939         cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3940                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3941
3942         DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3943                       cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3944
3945         vbt = dev_priv->vbt.edp_pps;
3946
3947         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3948          * our hw here, which are all in 100usec. */
3949         spec.t1_t3 = 210 * 10;
3950         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3951         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3952         spec.t10 = 500 * 10;
3953         /* This one is special and actually in units of 100ms, but zero
3954          * based in the hw (so we need to add 100 ms). But the sw vbt
3955          * table multiplies it with 1000 to make it in units of 100usec,
3956          * too. */
3957         spec.t11_t12 = (510 + 100) * 10;
3958
3959         DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3960                       vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3961
3962         /* Use the max of the register settings and vbt. If both are
3963          * unset, fall back to the spec limits. */
3964 #define assign_final(field)     final.field = (max(cur.field, vbt.field) == 0 ? \
3965                                        spec.field : \
3966                                        max(cur.field, vbt.field))
3967         assign_final(t1_t3);
3968         assign_final(t8);
3969         assign_final(t9);
3970         assign_final(t10);
3971         assign_final(t11_t12);
3972 #undef assign_final
3973
3974 #define get_delay(field)        (DIV_ROUND_UP(final.field, 10))
3975         intel_dp->panel_power_up_delay = get_delay(t1_t3);
3976         intel_dp->backlight_on_delay = get_delay(t8);
3977         intel_dp->backlight_off_delay = get_delay(t9);
3978         intel_dp->panel_power_down_delay = get_delay(t10);
3979         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3980 #undef get_delay
3981
3982         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3983                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3984                       intel_dp->panel_power_cycle_delay);
3985
3986         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3987                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3988
3989         if (out)
3990                 *out = final;
3991 }
3992
3993 static void
3994 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3995                                               struct intel_dp *intel_dp,
3996                                               struct edp_power_seq *seq)
3997 {
3998         struct drm_i915_private *dev_priv = dev->dev_private;
3999         u32 pp_on, pp_off, pp_div, port_sel = 0;
4000         int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4001         int pp_on_reg, pp_off_reg, pp_div_reg;
4002
4003         if (HAS_PCH_SPLIT(dev)) {
4004                 pp_on_reg = PCH_PP_ON_DELAYS;
4005                 pp_off_reg = PCH_PP_OFF_DELAYS;
4006                 pp_div_reg = PCH_PP_DIVISOR;
4007         } else {
4008                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4009
4010                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4011                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4012                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
4013         }
4014
4015         /*
4016          * And finally store the new values in the power sequencer. The
4017          * backlight delays are set to 1 because we do manual waits on them. For
4018          * T8, even BSpec recommends doing it. For T9, if we don't do this,
4019          * we'll end up waiting for the backlight off delay twice: once when we
4020          * do the manual sleep, and once when we disable the panel and wait for
4021          * the PP_STATUS bit to become zero.
4022          */
4023         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
4024                 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4025         pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
4026                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
4027         /* Compute the divisor for the pp clock, simply match the Bspec
4028          * formula. */
4029         pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
4030         pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
4031                         << PANEL_POWER_CYCLE_DELAY_SHIFT);
4032
4033         /* Haswell doesn't have any port selection bits for the panel
4034          * power sequencer any more. */
4035         if (IS_VALLEYVIEW(dev)) {
4036                 if (dp_to_dig_port(intel_dp)->port == PORT_B)
4037                         port_sel = PANEL_PORT_SELECT_DPB_VLV;
4038                 else
4039                         port_sel = PANEL_PORT_SELECT_DPC_VLV;
4040         } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
4041                 if (dp_to_dig_port(intel_dp)->port == PORT_A)
4042                         port_sel = PANEL_PORT_SELECT_DPA;
4043                 else
4044                         port_sel = PANEL_PORT_SELECT_DPD;
4045         }
4046
4047         pp_on |= port_sel;
4048
4049         I915_WRITE(pp_on_reg, pp_on);
4050         I915_WRITE(pp_off_reg, pp_off);
4051         I915_WRITE(pp_div_reg, pp_div);
4052
4053         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
4054                       I915_READ(pp_on_reg),
4055                       I915_READ(pp_off_reg),
4056                       I915_READ(pp_div_reg));
4057 }
4058
4059 void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4060 {
4061         struct drm_i915_private *dev_priv = dev->dev_private;
4062         struct intel_encoder *encoder;
4063         struct intel_dp *intel_dp = NULL;
4064         struct intel_crtc_config *config = NULL;
4065         struct intel_crtc *intel_crtc = NULL;
4066         struct intel_connector *intel_connector = dev_priv->drrs.connector;
4067         u32 reg, val;
4068         enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4069
4070         if (refresh_rate <= 0) {
4071                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4072                 return;
4073         }
4074
4075         if (intel_connector == NULL) {
4076                 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4077                 return;
4078         }
4079
4080         if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
4081                 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4082                 return;
4083         }
4084
4085         encoder = intel_attached_encoder(&intel_connector->base);
4086         intel_dp = enc_to_intel_dp(&encoder->base);
4087         intel_crtc = encoder->new_crtc;
4088
4089         if (!intel_crtc) {
4090                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4091                 return;
4092         }
4093
4094         config = &intel_crtc->config;
4095
4096         if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4097                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4098                 return;
4099         }
4100
4101         if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
4102                 index = DRRS_LOW_RR;
4103
4104         if (index == intel_dp->drrs_state.refresh_rate_type) {
4105                 DRM_DEBUG_KMS(
4106                         "DRRS requested for previously set RR...ignoring\n");
4107                 return;
4108         }
4109
4110         if (!intel_crtc->active) {
4111                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4112                 return;
4113         }
4114
4115         if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4116                 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4117                 val = I915_READ(reg);
4118                 if (index > DRRS_HIGH_RR) {
4119                         val |= PIPECONF_EDP_RR_MODE_SWITCH;
4120                         intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2);
4121                 } else {
4122                         val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4123                 }
4124                 I915_WRITE(reg, val);
4125         }
4126
4127         /*
4128          * mutex taken to ensure that there is no race between differnt
4129          * drrs calls trying to update refresh rate. This scenario may occur
4130          * in future when idleness detection based DRRS in kernel and
4131          * possible calls from user space to set differnt RR are made.
4132          */
4133
4134         mutex_lock(&intel_dp->drrs_state.mutex);
4135
4136         intel_dp->drrs_state.refresh_rate_type = index;
4137
4138         mutex_unlock(&intel_dp->drrs_state.mutex);
4139
4140         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4141 }
4142
4143 static struct drm_display_mode *
4144 intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4145                         struct intel_connector *intel_connector,
4146                         struct drm_display_mode *fixed_mode)
4147 {
4148         struct drm_connector *connector = &intel_connector->base;
4149         struct intel_dp *intel_dp = &intel_dig_port->dp;
4150         struct drm_device *dev = intel_dig_port->base.base.dev;
4151         struct drm_i915_private *dev_priv = dev->dev_private;
4152         struct drm_display_mode *downclock_mode = NULL;
4153
4154         if (INTEL_INFO(dev)->gen <= 6) {
4155                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4156                 return NULL;
4157         }
4158
4159         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4160                 DRM_INFO("VBT doesn't support DRRS\n");
4161                 return NULL;
4162         }
4163
4164         downclock_mode = intel_find_panel_downclock
4165                                         (dev, fixed_mode, connector);
4166
4167         if (!downclock_mode) {
4168                 DRM_INFO("DRRS not supported\n");
4169                 return NULL;
4170         }
4171
4172         dev_priv->drrs.connector = intel_connector;
4173
4174         mutex_init(&intel_dp->drrs_state.mutex);
4175
4176         intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4177
4178         intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4179         DRM_INFO("seamless DRRS supported for eDP panel.\n");
4180         return downclock_mode;
4181 }
4182
4183 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
4184                                      struct intel_connector *intel_connector,
4185                                      struct edp_power_seq *power_seq)
4186 {
4187         struct drm_connector *connector = &intel_connector->base;
4188         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4189         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4190         struct drm_device *dev = intel_encoder->base.dev;
4191         struct drm_i915_private *dev_priv = dev->dev_private;
4192         struct drm_display_mode *fixed_mode = NULL;
4193         struct drm_display_mode *downclock_mode = NULL;
4194         bool has_dpcd;
4195         struct drm_display_mode *scan;
4196         struct edid *edid;
4197
4198         intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
4199
4200         if (!is_edp(intel_dp))
4201                 return true;
4202
4203         /* The VDD bit needs a power domain reference, so if the bit is already
4204          * enabled when we boot, grab this reference. */
4205         if (edp_have_panel_vdd(intel_dp)) {
4206                 enum intel_display_power_domain power_domain;
4207                 power_domain = intel_display_port_power_domain(intel_encoder);
4208                 intel_display_power_get(dev_priv, power_domain);
4209         }
4210
4211         /* Cache DPCD and EDID for edp. */
4212         intel_edp_panel_vdd_on(intel_dp);
4213         has_dpcd = intel_dp_get_dpcd(intel_dp);
4214         edp_panel_vdd_off(intel_dp, false);
4215
4216         if (has_dpcd) {
4217                 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4218                         dev_priv->no_aux_handshake =
4219                                 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4220                                 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4221         } else {
4222                 /* if this fails, presume the device is a ghost */
4223                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
4224                 return false;
4225         }
4226
4227         /* We now know it's not a ghost, init power sequence regs. */
4228         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
4229
4230         mutex_lock(&dev->mode_config.mutex);
4231         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
4232         if (edid) {
4233                 if (drm_add_edid_modes(connector, edid)) {
4234                         drm_mode_connector_update_edid_property(connector,
4235                                                                 edid);
4236                         drm_edid_to_eld(connector, edid);
4237                 } else {
4238                         kfree(edid);
4239                         edid = ERR_PTR(-EINVAL);
4240                 }
4241         } else {
4242                 edid = ERR_PTR(-ENOENT);
4243         }
4244         intel_connector->edid = edid;
4245
4246         /* prefer fixed mode from EDID if available */
4247         list_for_each_entry(scan, &connector->probed_modes, head) {
4248                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
4249                         fixed_mode = drm_mode_duplicate(dev, scan);
4250                         downclock_mode = intel_dp_drrs_init(
4251                                                 intel_dig_port,
4252                                                 intel_connector, fixed_mode);
4253                         break;
4254                 }
4255         }
4256
4257         /* fallback to VBT if available for eDP */
4258         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
4259                 fixed_mode = drm_mode_duplicate(dev,
4260                                         dev_priv->vbt.lfp_lvds_vbt_mode);
4261                 if (fixed_mode)
4262                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
4263         }
4264         mutex_unlock(&dev->mode_config.mutex);
4265
4266         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
4267         intel_panel_setup_backlight(connector);
4268
4269         return true;
4270 }
4271
4272 bool
4273 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
4274                         struct intel_connector *intel_connector)
4275 {
4276         struct drm_connector *connector = &intel_connector->base;
4277         struct intel_dp *intel_dp = &intel_dig_port->dp;
4278         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4279         struct drm_device *dev = intel_encoder->base.dev;
4280         struct drm_i915_private *dev_priv = dev->dev_private;
4281         enum port port = intel_dig_port->port;
4282         struct edp_power_seq power_seq = { 0 };
4283         int type;
4284
4285         /* intel_dp vfuncs */
4286         if (IS_VALLEYVIEW(dev))
4287                 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
4288         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4289                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
4290         else if (HAS_PCH_SPLIT(dev))
4291                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
4292         else
4293                 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
4294
4295         intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
4296
4297         /* Preserve the current hw state. */
4298         intel_dp->DP = I915_READ(intel_dp->output_reg);
4299         intel_dp->attached_connector = intel_connector;
4300
4301         if (intel_dp_is_edp(dev, port))
4302                 type = DRM_MODE_CONNECTOR_eDP;
4303         else
4304                 type = DRM_MODE_CONNECTOR_DisplayPort;
4305
4306         /*
4307          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
4308          * for DP the encoder type can be set by the caller to
4309          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
4310          */
4311         if (type == DRM_MODE_CONNECTOR_eDP)
4312                 intel_encoder->type = INTEL_OUTPUT_EDP;
4313
4314         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
4315                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
4316                         port_name(port));
4317
4318         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
4319         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
4320
4321         connector->interlace_allowed = true;
4322         connector->doublescan_allowed = 0;
4323
4324         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4325                           edp_panel_vdd_work);
4326
4327         intel_connector_attach_encoder(intel_connector, intel_encoder);
4328         drm_sysfs_connector_add(connector);
4329
4330         if (HAS_DDI(dev))
4331                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
4332         else
4333                 intel_connector->get_hw_state = intel_connector_get_hw_state;
4334         intel_connector->unregister = intel_dp_connector_unregister;
4335
4336         /* Set up the hotplug pin. */
4337         switch (port) {
4338         case PORT_A:
4339                 intel_encoder->hpd_pin = HPD_PORT_A;
4340                 break;
4341         case PORT_B:
4342                 intel_encoder->hpd_pin = HPD_PORT_B;
4343                 break;
4344         case PORT_C:
4345                 intel_encoder->hpd_pin = HPD_PORT_C;
4346                 break;
4347         case PORT_D:
4348                 intel_encoder->hpd_pin = HPD_PORT_D;
4349                 break;
4350         default:
4351                 BUG();
4352         }
4353
4354         if (is_edp(intel_dp)) {
4355                 intel_dp_init_panel_power_timestamps(intel_dp);
4356                 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
4357         }
4358
4359         intel_dp_aux_init(intel_dp, intel_connector);
4360
4361         if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
4362                 drm_dp_aux_unregister(&intel_dp->aux);
4363                 if (is_edp(intel_dp)) {
4364                         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4365                         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4366                         edp_panel_vdd_off_sync(intel_dp);
4367                         drm_modeset_unlock(&dev->mode_config.connection_mutex);
4368                 }
4369                 drm_sysfs_connector_remove(connector);
4370                 drm_connector_cleanup(connector);
4371                 return false;
4372         }
4373
4374         intel_dp_add_properties(intel_dp, connector);
4375
4376         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
4377          * 0xd.  Failure to do so will result in spurious interrupts being
4378          * generated on the port when a cable is not attached.
4379          */
4380         if (IS_G4X(dev) && !IS_GM45(dev)) {
4381                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
4382                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
4383         }
4384
4385         return true;
4386 }
4387
4388 void
4389 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
4390 {
4391         struct intel_digital_port *intel_dig_port;
4392         struct intel_encoder *intel_encoder;
4393         struct drm_encoder *encoder;
4394         struct intel_connector *intel_connector;
4395
4396         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
4397         if (!intel_dig_port)
4398                 return;
4399
4400         intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
4401         if (!intel_connector) {
4402                 kfree(intel_dig_port);
4403                 return;
4404         }
4405
4406         intel_encoder = &intel_dig_port->base;
4407         encoder = &intel_encoder->base;
4408
4409         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
4410                          DRM_MODE_ENCODER_TMDS);
4411
4412         intel_encoder->compute_config = intel_dp_compute_config;
4413         intel_encoder->disable = intel_disable_dp;
4414         intel_encoder->get_hw_state = intel_dp_get_hw_state;
4415         intel_encoder->get_config = intel_dp_get_config;
4416         if (IS_CHERRYVIEW(dev)) {
4417                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
4418                 intel_encoder->pre_enable = chv_pre_enable_dp;
4419                 intel_encoder->enable = vlv_enable_dp;
4420                 intel_encoder->post_disable = chv_post_disable_dp;
4421         } else if (IS_VALLEYVIEW(dev)) {
4422                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
4423                 intel_encoder->pre_enable = vlv_pre_enable_dp;
4424                 intel_encoder->enable = vlv_enable_dp;
4425                 intel_encoder->post_disable = vlv_post_disable_dp;
4426         } else {
4427                 intel_encoder->pre_enable = g4x_pre_enable_dp;
4428                 intel_encoder->enable = g4x_enable_dp;
4429                 intel_encoder->post_disable = g4x_post_disable_dp;
4430         }
4431
4432         intel_dig_port->port = port;
4433         intel_dig_port->dp.output_reg = output_reg;
4434
4435         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4436         if (IS_CHERRYVIEW(dev)) {
4437                 if (port == PORT_D)
4438                         intel_encoder->crtc_mask = 1 << 2;
4439                 else
4440                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
4441         } else {
4442                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
4443         }
4444         intel_encoder->cloneable = 0;
4445         intel_encoder->hot_plug = intel_dp_hot_plug;
4446
4447         if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
4448                 drm_encoder_cleanup(encoder);
4449                 kfree(intel_dig_port);
4450                 kfree(intel_connector);
4451         }
4452 }