drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_edid.h>
  35 #include "intel_drv.h"
  36 #include <drm/i915_drm.h>
  37 #include "i915_drv.h"
  38
  39 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  40
  41 struct dp_link_dpll {
  42         int link_bw;
  43         struct dpll dpll;
  44 };
  45
  46 static const struct dp_link_dpll gen4_dpll[] = {
  47         { DP_LINK_BW_1_62,
  48                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  49         { DP_LINK_BW_2_7,
  50                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  51 };
  52
  53 static const struct dp_link_dpll pch_dpll[] = {
  54         { DP_LINK_BW_1_62,
  55                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  56         { DP_LINK_BW_2_7,
  57                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  58 };
  59
  60 static const struct dp_link_dpll vlv_dpll[] = {
  61         { DP_LINK_BW_1_62,
  62                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  63         { DP_LINK_BW_2_7,
  64                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  65 };
  66
  67 /*
  68  * CHV supports eDP 1.4 that have  more link rates.
  69  * Below only provides the fixed rate but exclude variable rate.
  70  */
  71 static const struct dp_link_dpll chv_dpll[] = {
  72         /*
  73          * CHV requires to program fractional division for m2.
  74          * m2 is stored in fixed point format using formula below
  75          * (m2_int << 22) | m2_fraction
  76          */
  77         { DP_LINK_BW_1_62,      /* m2_int = 32, m2_fraction = 1677722 */
  78                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
  79         { DP_LINK_BW_2_7,       /* m2_int = 27, m2_fraction = 0 */
  80                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
  81         { DP_LINK_BW_5_4,       /* m2_int = 27, m2_fraction = 0 */
  82                 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
  83 };
  84
  85 /**
  86  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  87  * @intel_dp: DP struct
  88  *
  89  * If a CPU or PCH DP output is attached to an eDP panel, this function
  90  * will return true, and false otherwise.
  91  */
  92 static bool is_edp(struct intel_dp *intel_dp)
  93 {
  94         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  95
  96         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
  97 }
  98
  99 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
 100 {
 101         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 102
 103         return intel_dig_port->base.base.dev;
 104 }
 105
 106 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 107 {
 108         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 109 }
 110
 111 static void intel_dp_link_down(struct intel_dp *intel_dp);
 112 static bool _edp_panel_vdd_on(struct intel_dp *intel_dp);
 113 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 114
 115 static int
 116 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 117 {
 118         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 119         struct drm_device *dev = intel_dp->attached_connector->base.dev;
 120
 121         switch (max_link_bw) {
 122         case DP_LINK_BW_1_62:
 123         case DP_LINK_BW_2_7:
 124                 break;
 125         case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
 126                 if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) &&
 127                     intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
 128                         max_link_bw = DP_LINK_BW_5_4;
 129                 else
 130                         max_link_bw = DP_LINK_BW_2_7;
 131                 break;
 132         default:
 133                 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
 134                      max_link_bw);
 135                 max_link_bw = DP_LINK_BW_1_62;
 136                 break;
 137         }
 138         return max_link_bw;
 139 }
 140
 141 /*
 142  * The units on the numbers in the next two are... bizarre.  Examples will
 143  * make it clearer; this one parallels an example in the eDP spec.
 144  *
 145  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 146  *
 147  *     270000 * 1 * 8 / 10 == 216000
 148  *
 149  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 150  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 151  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 152  * 119000.  At 18bpp that's 2142000 kilobits per second.
 153  *
 154  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 155  * get the result in decakilobits instead of kilobits.
 156  */
 157
 158 static int
 159 intel_dp_link_required(int pixel_clock, int bpp)
 160 {
 161         return (pixel_clock * bpp + 9) / 10;
 162 }
 163
 164 static int
 165 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 166 {
 167         return (max_link_clock * max_lanes * 8) / 10;
 168 }
 169
 170 static enum drm_mode_status
 171 intel_dp_mode_valid(struct drm_connector *connector,
 172                     struct drm_display_mode *mode)
 173 {
 174         struct intel_dp *intel_dp = intel_attached_dp(connector);
 175         struct intel_connector *intel_connector = to_intel_connector(connector);
 176         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 177         int target_clock = mode->clock;
 178         int max_rate, mode_rate, max_lanes, max_link_clock;
 179
 180         if (is_edp(intel_dp) && fixed_mode) {
 181                 if (mode->hdisplay > fixed_mode->hdisplay)
 182                         return MODE_PANEL;
 183
 184                 if (mode->vdisplay > fixed_mode->vdisplay)
 185                         return MODE_PANEL;
 186
 187                 target_clock = fixed_mode->clock;
 188         }
 189
 190         max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
 191         max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
 192
 193         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 194         mode_rate = intel_dp_link_required(target_clock, 18);
 195
 196         if (mode_rate > max_rate)
 197                 return MODE_CLOCK_HIGH;
 198
 199         if (mode->clock < 10000)
 200                 return MODE_CLOCK_LOW;
 201
 202         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 203                 return MODE_H_ILLEGAL;
 204
 205         return MODE_OK;
 206 }
 207
 208 static uint32_t
 209 pack_aux(uint8_t *src, int src_bytes)
 210 {
 211         int     i;
 212         uint32_t v = 0;
 213
 214         if (src_bytes > 4)
 215                 src_bytes = 4;
 216         for (i = 0; i < src_bytes; i++)
 217                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 218         return v;
 219 }
 220
 221 static void
 222 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 223 {
 224         int i;
 225         if (dst_bytes > 4)
 226                 dst_bytes = 4;
 227         for (i = 0; i < dst_bytes; i++)
 228                 dst[i] = src >> ((3-i) * 8);
 229 }
 230
 231 /* hrawclock is 1/4 the FSB frequency */
 232 static int
 233 intel_hrawclk(struct drm_device *dev)
 234 {
 235         struct drm_i915_private *dev_priv = dev->dev_private;
 236         uint32_t clkcfg;
 237
 238         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 239         if (IS_VALLEYVIEW(dev))
 240                 return 200;
 241
 242         clkcfg = I915_READ(CLKCFG);
 243         switch (clkcfg & CLKCFG_FSB_MASK) {
 244         case CLKCFG_FSB_400:
 245                 return 100;
 246         case CLKCFG_FSB_533:
 247                 return 133;
 248         case CLKCFG_FSB_667:
 249                 return 166;
 250         case CLKCFG_FSB_800:
 251                 return 200;
 252         case CLKCFG_FSB_1067:
 253                 return 266;
 254         case CLKCFG_FSB_1333:
 255                 return 333;
 256         /* these two are just a guess; one of them might be right */
 257         case CLKCFG_FSB_1600:
 258         case CLKCFG_FSB_1600_ALT:
 259                 return 400;
 260         default:
 261                 return 133;
 262         }
 263 }
 264
 265 static void
 266 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 267                                     struct intel_dp *intel_dp,
 268                                     struct edp_power_seq *out);
 269 static void
 270 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 271                                               struct intel_dp *intel_dp,
 272                                               struct edp_power_seq *out);
 273
 274 static enum pipe
 275 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 276 {
 277         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 278         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
 279         struct drm_device *dev = intel_dig_port->base.base.dev;
 280         struct drm_i915_private *dev_priv = dev->dev_private;
 281         enum port port = intel_dig_port->port;
 282         enum pipe pipe;
 283
 284         /* modeset should have pipe */
 285         if (crtc)
 286                 return to_intel_crtc(crtc)->pipe;
 287
 288         /* init time, try to find a pipe with this port selected */
 289         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 290                 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
 291                         PANEL_PORT_SELECT_MASK;
 292                 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
 293                         return pipe;
 294                 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
 295                         return pipe;
 296         }
 297
 298         /* shrug */
 299         return PIPE_A;
 300 }
 301
 302 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
 303 {
 304         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 305
 306         if (HAS_PCH_SPLIT(dev))
 307                 return PCH_PP_CONTROL;
 308         else
 309                 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
 310 }
 311
 312 static u32 _pp_stat_reg(struct intel_dp *intel_dp)
 313 {
 314         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 315
 316         if (HAS_PCH_SPLIT(dev))
 317                 return PCH_PP_STATUS;
 318         else
 319                 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
 320 }
 321
 322 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 323 {
 324         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 325         struct drm_i915_private *dev_priv = dev->dev_private;
 326
 327         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 328 }
 329
 330 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 331 {
 332         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 333         struct drm_i915_private *dev_priv = dev->dev_private;
 334         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 335         struct intel_encoder *intel_encoder = &intel_dig_port->base;
 336         enum intel_display_power_domain power_domain;
 337
 338         power_domain = intel_display_port_power_domain(intel_encoder);
 339         return intel_display_power_enabled(dev_priv, power_domain) &&
 340                (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
 341 }
 342
 343 static void
 344 intel_dp_check_edp(struct intel_dp *intel_dp)
 345 {
 346         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 347         struct drm_i915_private *dev_priv = dev->dev_private;
 348
 349         if (!is_edp(intel_dp))
 350                 return;
 351
 352         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 353                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 354                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 355                               I915_READ(_pp_stat_reg(intel_dp)),
 356                               I915_READ(_pp_ctrl_reg(intel_dp)));
 357         }
 358 }
 359
 360 static uint32_t
 361 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 362 {
 363         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 364         struct drm_device *dev = intel_dig_port->base.base.dev;
 365         struct drm_i915_private *dev_priv = dev->dev_private;
 366         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 367         uint32_t status;
 368         bool done;
 369
 370 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 371         if (has_aux_irq)
 372                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 373                                           msecs_to_jiffies_timeout(10));
 374         else
 375                 done = wait_for_atomic(C, 10) == 0;
 376         if (!done)
 377                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 378                           has_aux_irq);
 379 #undef C
 380
 381         return status;
 382 }
 383
 384 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 385 {
 386         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 387         struct drm_device *dev = intel_dig_port->base.base.dev;
 388
 389         /*
 390          * The clock divider is based off the hrawclk, and would like to run at
 391          * 2MHz.  So, take the hrawclk value and divide by 2 and use that
 392          */
 393         return index ? 0 : intel_hrawclk(dev) / 2;
 394 }
 395
 396 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 397 {
 398         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 399         struct drm_device *dev = intel_dig_port->base.base.dev;
 400
 401         if (index)
 402                 return 0;
 403
 404         if (intel_dig_port->port == PORT_A) {
 405                 if (IS_GEN6(dev) || IS_GEN7(dev))
 406                         return 200; /* SNB & IVB eDP input clock at 400Mhz */
 407                 else
 408                         return 225; /* eDP input clock at 450Mhz */
 409         } else {
 410                 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 411         }
 412 }
 413
 414 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 415 {
 416         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 417         struct drm_device *dev = intel_dig_port->base.base.dev;
 418         struct drm_i915_private *dev_priv = dev->dev_private;
 419
 420         if (intel_dig_port->port == PORT_A) {
 421                 if (index)
 422                         return 0;
 423                 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
 424         } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 425                 /* Workaround for non-ULT HSW */
 426                 switch (index) {
 427                 case 0: return 63;
 428                 case 1: return 72;
 429                 default: return 0;
 430                 }
 431         } else  {
 432                 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 433         }
 434 }
 435
 436 static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 437 {
 438         return index ? 0 : 100;
 439 }
 440
 441 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
 442                                       bool has_aux_irq,
 443                                       int send_bytes,
 444                                       uint32_t aux_clock_divider)
 445 {
 446         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 447         struct drm_device *dev = intel_dig_port->base.base.dev;
 448         uint32_t precharge, timeout;
 449
 450         if (IS_GEN6(dev))
 451                 precharge = 3;
 452         else
 453                 precharge = 5;
 454
 455         if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
 456                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
 457         else
 458                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
 459
 460         return DP_AUX_CH_CTL_SEND_BUSY |
 461                DP_AUX_CH_CTL_DONE |
 462                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 463                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 464                timeout |
 465                DP_AUX_CH_CTL_RECEIVE_ERROR |
 466                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 467                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 468                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
 469 }
 470
 471 static int
 472 intel_dp_aux_ch(struct intel_dp *intel_dp,
 473                 uint8_t *send, int send_bytes,
 474                 uint8_t *recv, int recv_size)
 475 {
 476         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 477         struct drm_device *dev = intel_dig_port->base.base.dev;
 478         struct drm_i915_private *dev_priv = dev->dev_private;
 479         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 480         uint32_t ch_data = ch_ctl + 4;
 481         uint32_t aux_clock_divider;
 482         int i, ret, recv_bytes;
 483         uint32_t status;
 484         int try, clock = 0;
 485         bool has_aux_irq = HAS_AUX_IRQ(dev);
 486         bool vdd;
 487
 488         vdd = _edp_panel_vdd_on(intel_dp);
 489
 490         /* dp aux is extremely sensitive to irq latency, hence request the
 491          * lowest possible wakeup latency and so prevent the cpu from going into
 492          * deep sleep states.
 493          */
 494         pm_qos_update_request(&dev_priv->pm_qos, 0);
 495
 496         intel_dp_check_edp(intel_dp);
 497
 498         intel_aux_display_runtime_get(dev_priv);
 499
 500         /* Try to wait for any previous AUX channel activity */
 501         for (try = 0; try < 3; try++) {
 502                 status = I915_READ_NOTRACE(ch_ctl);
 503                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 504                         break;
 505                 msleep(1);
 506         }
 507
 508         if (try == 3) {
 509                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 510                      I915_READ(ch_ctl));
 511                 ret = -EBUSY;
 512                 goto out;
 513         }
 514
 515         /* Only 5 data registers! */
 516         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
 517                 ret = -E2BIG;
 518                 goto out;
 519         }
 520
 521         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
 522                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
 523                                                           has_aux_irq,
 524                                                           send_bytes,
 525                                                           aux_clock_divider);
 526
 527                 /* Must try at least 3 times according to DP spec */
 528                 for (try = 0; try < 5; try++) {
 529                         /* Load the send data into the aux channel data registers */
 530                         for (i = 0; i < send_bytes; i += 4)
 531                                 I915_WRITE(ch_data + i,
 532                                            pack_aux(send + i, send_bytes - i));
 533
 534                         /* Send the command and wait for it to complete */
 535                         I915_WRITE(ch_ctl, send_ctl);
 536
 537                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
 538
 539                         /* Clear done status and any errors */
 540                         I915_WRITE(ch_ctl,
 541                                    status |
 542                                    DP_AUX_CH_CTL_DONE |
 543                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
 544                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
 545
 546                         if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
 547                                       DP_AUX_CH_CTL_RECEIVE_ERROR))
 548                                 continue;
 549                         if (status & DP_AUX_CH_CTL_DONE)
 550                                 break;
 551                 }
 552                 if (status & DP_AUX_CH_CTL_DONE)
 553                         break;
 554         }
 555
 556         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 557                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 558                 ret = -EBUSY;
 559                 goto out;
 560         }
 561
 562         /* Check for timeout or receive error.
 563          * Timeouts occur when the sink is not connected
 564          */
 565         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 566                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 567                 ret = -EIO;
 568                 goto out;
 569         }
 570
 571         /* Timeouts occur when the device isn't connected, so they're
 572          * "normal" -- don't fill the kernel log with these */
 573         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 574                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 575                 ret = -ETIMEDOUT;
 576                 goto out;
 577         }
 578
 579         /* Unload any bytes sent back from the other side */
 580         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 581                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 582         if (recv_bytes > recv_size)
 583                 recv_bytes = recv_size;
 584
 585         for (i = 0; i < recv_bytes; i += 4)
 586                 unpack_aux(I915_READ(ch_data + i),
 587                            recv + i, recv_bytes - i);
 588
 589         ret = recv_bytes;
 590 out:
 591         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 592         intel_aux_display_runtime_put(dev_priv);
 593
 594         if (vdd)
 595                 edp_panel_vdd_off(intel_dp, false);
 596
 597         return ret;
 598 }
 599
 600 #define BARE_ADDRESS_SIZE       3
 601 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
 602 static ssize_t
 603 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
 604 {
 605         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
 606         uint8_t txbuf[20], rxbuf[20];
 607         size_t txsize, rxsize;
 608         int ret;
 609
 610         txbuf[0] = msg->request << 4;
 611         txbuf[1] = msg->address >> 8;
 612         txbuf[2] = msg->address & 0xff;
 613         txbuf[3] = msg->size - 1;
 614
 615         switch (msg->request & ~DP_AUX_I2C_MOT) {
 616         case DP_AUX_NATIVE_WRITE:
 617         case DP_AUX_I2C_WRITE:
 618                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
 619                 rxsize = 1;
 620
 621                 if (WARN_ON(txsize > 20))
 622                         return -E2BIG;
 623
 624                 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
 625
 626                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
 627                 if (ret > 0) {
 628                         msg->reply = rxbuf[0] >> 4;
 629
 630                         /* Return payload size. */
 631                         ret = msg->size;
 632                 }
 633                 break;
 634
 635         case DP_AUX_NATIVE_READ:
 636         case DP_AUX_I2C_READ:
 637                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
 638                 rxsize = msg->size + 1;
 639
 640                 if (WARN_ON(rxsize > 20))
 641                         return -E2BIG;
 642
 643                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
 644                 if (ret > 0) {
 645                         msg->reply = rxbuf[0] >> 4;
 646                         /*
 647                          * Assume happy day, and copy the data. The caller is
 648                          * expected to check msg->reply before touching it.
 649                          *
 650                          * Return payload size.
 651                          */
 652                         ret--;
 653                         memcpy(msg->buffer, rxbuf + 1, ret);
 654                 }
 655                 break;
 656
 657         default:
 658                 ret = -EINVAL;
 659                 break;
 660         }
 661
 662         return ret;
 663 }
 664
 665 static void
 666 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
 667 {
 668         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 669         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 670         enum port port = intel_dig_port->port;
 671         const char *name = NULL;
 672         int ret;
 673
 674         switch (port) {
 675         case PORT_A:
 676                 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
 677                 name = "DPDDC-A";
 678                 break;
 679         case PORT_B:
 680                 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
 681                 name = "DPDDC-B";
 682                 break;
 683         case PORT_C:
 684                 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
 685                 name = "DPDDC-C";
 686                 break;
 687         case PORT_D:
 688                 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
 689                 name = "DPDDC-D";
 690                 break;
 691         default:
 692                 BUG();
 693         }
 694
 695         if (!HAS_DDI(dev))
 696                 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
 697
 698         intel_dp->aux.name = name;
 699         intel_dp->aux.dev = dev->dev;
 700         intel_dp->aux.transfer = intel_dp_aux_transfer;
 701
 702         DRM_DEBUG_KMS("registering %s bus for %s\n", name,
 703                       connector->base.kdev->kobj.name);
 704
 705         ret = drm_dp_aux_register_i2c_bus(&intel_dp->aux);
 706         if (ret < 0) {
 707                 DRM_ERROR("drm_dp_aux_register_i2c_bus() for %s failed (%d)\n",
 708                           name, ret);
 709                 return;
 710         }
 711
 712         ret = sysfs_create_link(&connector->base.kdev->kobj,
 713                                 &intel_dp->aux.ddc.dev.kobj,
 714                                 intel_dp->aux.ddc.dev.kobj.name);
 715         if (ret < 0) {
 716                 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
 717                 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
 718         }
 719 }
 720
 721 static void
 722 intel_dp_connector_unregister(struct intel_connector *intel_connector)
 723 {
 724         struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
 725
 726         sysfs_remove_link(&intel_connector->base.kdev->kobj,
 727                           intel_dp->aux.ddc.dev.kobj.name);
 728         intel_connector_unregister(intel_connector);
 729 }
 730
 731 static void
 732 intel_dp_set_clock(struct intel_encoder *encoder,
 733                    struct intel_crtc_config *pipe_config, int link_bw)
 734 {
 735         struct drm_device *dev = encoder->base.dev;
 736         const struct dp_link_dpll *divisor = NULL;
 737         int i, count = 0;
 738
 739         if (IS_G4X(dev)) {
 740                 divisor = gen4_dpll;
 741                 count = ARRAY_SIZE(gen4_dpll);
 742         } else if (IS_HASWELL(dev)) {
 743                 /* Haswell has special-purpose DP DDI clocks. */
 744         } else if (HAS_PCH_SPLIT(dev)) {
 745                 divisor = pch_dpll;
 746                 count = ARRAY_SIZE(pch_dpll);
 747         } else if (IS_CHERRYVIEW(dev)) {
 748                 divisor = chv_dpll;
 749                 count = ARRAY_SIZE(chv_dpll);
 750         } else if (IS_VALLEYVIEW(dev)) {
 751                 divisor = vlv_dpll;
 752                 count = ARRAY_SIZE(vlv_dpll);
 753         }
 754
 755         if (divisor && count) {
 756                 for (i = 0; i < count; i++) {
 757                         if (link_bw == divisor[i].link_bw) {
 758                                 pipe_config->dpll = divisor[i].dpll;
 759                                 pipe_config->clock_set = true;
 760                                 break;
 761                         }
 762                 }
 763         }
 764 }
 765
 766 static void
 767 intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
 768 {
 769         struct drm_device *dev = crtc->base.dev;
 770         struct drm_i915_private *dev_priv = dev->dev_private;
 771         enum transcoder transcoder = crtc->config.cpu_transcoder;
 772
 773         I915_WRITE(PIPE_DATA_M2(transcoder),
 774                 TU_SIZE(m_n->tu) | m_n->gmch_m);
 775         I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
 776         I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
 777         I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
 778 }
 779
 780 bool
 781 intel_dp_compute_config(struct intel_encoder *encoder,
 782                         struct intel_crtc_config *pipe_config)
 783 {
 784         struct drm_device *dev = encoder->base.dev;
 785         struct drm_i915_private *dev_priv = dev->dev_private;
 786         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
 787         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 788         enum port port = dp_to_dig_port(intel_dp)->port;
 789         struct intel_crtc *intel_crtc = encoder->new_crtc;
 790         struct intel_connector *intel_connector = intel_dp->attached_connector;
 791         int lane_count, clock;
 792         int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
 793         /* Conveniently, the link BW constants become indices with a shift...*/
 794         int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
 795         int bpp, mode_rate;
 796         static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
 797         int link_avail, link_clock;
 798
 799         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
 800                 pipe_config->has_pch_encoder = true;
 801
 802         pipe_config->has_dp_encoder = true;
 803         pipe_config->has_audio = intel_dp->has_audio;
 804
 805         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
 806                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
 807                                        adjusted_mode);
 808                 if (!HAS_PCH_SPLIT(dev))
 809                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
 810                                                  intel_connector->panel.fitting_mode);
 811                 else
 812                         intel_pch_panel_fitting(intel_crtc, pipe_config,
 813                                                 intel_connector->panel.fitting_mode);
 814         }
 815
 816         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 817                 return false;
 818
 819         DRM_DEBUG_KMS("DP link computation with max lane count %i "
 820                       "max bw %02x pixel clock %iKHz\n",
 821                       max_lane_count, bws[max_clock],
 822                       adjusted_mode->crtc_clock);
 823
 824         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
 825          * bpc in between. */
 826         bpp = pipe_config->pipe_bpp;
 827         if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
 828             dev_priv->vbt.edp_bpp < bpp) {
 829                 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
 830                               dev_priv->vbt.edp_bpp);
 831                 bpp = dev_priv->vbt.edp_bpp;
 832         }
 833
 834         for (; bpp >= 6*3; bpp -= 2*3) {
 835                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
 836                                                    bpp);
 837
 838                 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 839                         for (clock = 0; clock <= max_clock; clock++) {
 840                                 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
 841                                 link_avail = intel_dp_max_data_rate(link_clock,
 842                                                                     lane_count);
 843
 844                                 if (mode_rate <= link_avail) {
 845                                         goto found;
 846                                 }
 847                         }
 848                 }
 849         }
 850
 851         return false;
 852
 853 found:
 854         if (intel_dp->color_range_auto) {
 855                 /*
 856                  * See:
 857                  * CEA-861-E - 5.1 Default Encoding Parameters
 858                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
 859                  */
 860                 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
 861                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
 862                 else
 863                         intel_dp->color_range = 0;
 864         }
 865
 866         if (intel_dp->color_range)
 867                 pipe_config->limited_color_range = true;
 868
 869         intel_dp->link_bw = bws[clock];
 870         intel_dp->lane_count = lane_count;
 871         pipe_config->pipe_bpp = bpp;
 872         pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
 873
 874         DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
 875                       intel_dp->link_bw, intel_dp->lane_count,
 876                       pipe_config->port_clock, bpp);
 877         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
 878                       mode_rate, link_avail);
 879
 880         intel_link_compute_m_n(bpp, lane_count,
 881                                adjusted_mode->crtc_clock,
 882                                pipe_config->port_clock,
 883                                &pipe_config->dp_m_n);
 884
 885         if (intel_connector->panel.downclock_mode != NULL &&
 886                 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
 887                         intel_link_compute_m_n(bpp, lane_count,
 888                                 intel_connector->panel.downclock_mode->clock,
 889                                 pipe_config->port_clock,
 890                                 &pipe_config->dp_m2_n2);
 891         }
 892
 893         intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
 894
 895         return true;
 896 }
 897
 898 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
 899 {
 900         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 901         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
 902         struct drm_device *dev = crtc->base.dev;
 903         struct drm_i915_private *dev_priv = dev->dev_private;
 904         u32 dpa_ctl;
 905
 906         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
 907         dpa_ctl = I915_READ(DP_A);
 908         dpa_ctl &= ~DP_PLL_FREQ_MASK;
 909
 910         if (crtc->config.port_clock == 162000) {
 911                 /* For a long time we've carried around a ILK-DevA w/a for the
 912                  * 160MHz clock. If we're really unlucky, it's still required.
 913                  */
 914                 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
 915                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
 916                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 917         } else {
 918                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
 919                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 920         }
 921
 922         I915_WRITE(DP_A, dpa_ctl);
 923
 924         POSTING_READ(DP_A);
 925         udelay(500);
 926 }
 927
 928 static void intel_dp_prepare(struct intel_encoder *encoder)
 929 {
 930         struct drm_device *dev = encoder->base.dev;
 931         struct drm_i915_private *dev_priv = dev->dev_private;
 932         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 933         enum port port = dp_to_dig_port(intel_dp)->port;
 934         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 935         struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
 936
 937         /*
 938          * There are four kinds of DP registers:
 939          *
 940          *      IBX PCH
 941          *      SNB CPU
 942          *      IVB CPU
 943          *      CPT PCH
 944          *
 945          * IBX PCH and CPU are the same for almost everything,
 946          * except that the CPU DP PLL is configured in this
 947          * register
 948          *
 949          * CPT PCH is quite different, having many bits moved
 950          * to the TRANS_DP_CTL register instead. That
 951          * configuration happens (oddly) in ironlake_pch_enable
 952          */
 953
 954         /* Preserve the BIOS-computed detected bit. This is
 955          * supposed to be read-only.
 956          */
 957         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 958
 959         /* Handle DP bits in common between all three register formats */
 960         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 961         intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
 962
 963         if (crtc->config.has_audio) {
 964                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
 965                                  pipe_name(crtc->pipe));
 966                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 967                 intel_write_eld(&encoder->base, adjusted_mode);
 968         }
 969
 970         /* Split out the IBX/CPU vs CPT settings */
 971
 972         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
 973                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 974                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 975                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 976                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 977                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 978
 979                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
 980                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 981
 982                 intel_dp->DP |= crtc->pipe << 29;
 983         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
 984                 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
 985                         intel_dp->DP |= intel_dp->color_range;
 986
 987                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 988                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 989                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 990                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 991                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 992
 993                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
 994                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 995
 996                 if (!IS_CHERRYVIEW(dev)) {
 997                         if (crtc->pipe == 1)
 998                                 intel_dp->DP |= DP_PIPEB_SELECT;
 999                 } else {
1000                         intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1001                 }
1002         } else {
1003                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1004         }
1005 }
1006
1007 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1008 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1009
1010 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
1011 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
1012
1013 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1014 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1015
1016 static void wait_panel_status(struct intel_dp *intel_dp,
1017                                        u32 mask,
1018                                        u32 value)
1019 {
1020         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1021         struct drm_i915_private *dev_priv = dev->dev_private;
1022         u32 pp_stat_reg, pp_ctrl_reg;
1023
1024         pp_stat_reg = _pp_stat_reg(intel_dp);
1025         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1026
1027         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1028                         mask, value,
1029                         I915_READ(pp_stat_reg),
1030                         I915_READ(pp_ctrl_reg));
1031
1032         if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1033                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1034                                 I915_READ(pp_stat_reg),
1035                                 I915_READ(pp_ctrl_reg));
1036         }
1037
1038         DRM_DEBUG_KMS("Wait complete\n");
1039 }
1040
1041 static void wait_panel_on(struct intel_dp *intel_dp)
1042 {
1043         DRM_DEBUG_KMS("Wait for panel power on\n");
1044         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1045 }
1046
1047 static void wait_panel_off(struct intel_dp *intel_dp)
1048 {
1049         DRM_DEBUG_KMS("Wait for panel power off time\n");
1050         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1051 }
1052
1053 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1054 {
1055         DRM_DEBUG_KMS("Wait for panel power cycle\n");
1056
1057         /* When we disable the VDD override bit last we have to do the manual
1058          * wait. */
1059         wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1060                                        intel_dp->panel_power_cycle_delay);
1061
1062         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1063 }
1064
1065 static void wait_backlight_on(struct intel_dp *intel_dp)
1066 {
1067         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1068                                        intel_dp->backlight_on_delay);
1069 }
1070
1071 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1072 {
1073         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1074                                        intel_dp->backlight_off_delay);
1075 }
1076
1077 /* Read the current pp_control value, unlocking the register if it
1078  * is locked
1079  */
1080
1081 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1082 {
1083         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1084         struct drm_i915_private *dev_priv = dev->dev_private;
1085         u32 control;
1086
1087         control = I915_READ(_pp_ctrl_reg(intel_dp));
1088         control &= ~PANEL_UNLOCK_MASK;
1089         control |= PANEL_UNLOCK_REGS;
1090         return control;
1091 }
1092
1093 static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
1094 {
1095         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1096         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1097         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1098         struct drm_i915_private *dev_priv = dev->dev_private;
1099         enum intel_display_power_domain power_domain;
1100         u32 pp;
1101         u32 pp_stat_reg, pp_ctrl_reg;
1102         bool need_to_disable = !intel_dp->want_panel_vdd;
1103
1104         if (!is_edp(intel_dp))
1105                 return false;
1106
1107         intel_dp->want_panel_vdd = true;
1108
1109         if (edp_have_panel_vdd(intel_dp))
1110                 return need_to_disable;
1111
1112         power_domain = intel_display_port_power_domain(intel_encoder);
1113         intel_display_power_get(dev_priv, power_domain);
1114
1115         DRM_DEBUG_KMS("Turning eDP VDD on\n");
1116
1117         if (!edp_have_panel_power(intel_dp))
1118                 wait_panel_power_cycle(intel_dp);
1119
1120         pp = ironlake_get_pp_control(intel_dp);
1121         pp |= EDP_FORCE_VDD;
1122
1123         pp_stat_reg = _pp_stat_reg(intel_dp);
1124         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1125
1126         I915_WRITE(pp_ctrl_reg, pp);
1127         POSTING_READ(pp_ctrl_reg);
1128         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1129                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1130         /*
1131          * If the panel wasn't on, delay before accessing aux channel
1132          */
1133         if (!edp_have_panel_power(intel_dp)) {
1134                 DRM_DEBUG_KMS("eDP was not running\n");
1135                 msleep(intel_dp->panel_power_up_delay);
1136         }
1137
1138         return need_to_disable;
1139 }
1140
1141 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1142 {
1143         if (is_edp(intel_dp)) {
1144                 bool vdd = _edp_panel_vdd_on(intel_dp);
1145
1146                 WARN(!vdd, "eDP VDD already requested on\n");
1147         }
1148 }
1149
1150 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1151 {
1152         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1153         struct drm_i915_private *dev_priv = dev->dev_private;
1154         u32 pp;
1155         u32 pp_stat_reg, pp_ctrl_reg;
1156
1157         WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1158
1159         if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
1160                 struct intel_digital_port *intel_dig_port =
1161                                                 dp_to_dig_port(intel_dp);
1162                 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1163                 enum intel_display_power_domain power_domain;
1164
1165                 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1166
1167                 pp = ironlake_get_pp_control(intel_dp);
1168                 pp &= ~EDP_FORCE_VDD;
1169
1170                 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1171                 pp_stat_reg = _pp_stat_reg(intel_dp);
1172
1173                 I915_WRITE(pp_ctrl_reg, pp);
1174                 POSTING_READ(pp_ctrl_reg);
1175
1176                 /* Make sure sequencer is idle before allowing subsequent activity */
1177                 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1178                 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1179
1180                 if ((pp & POWER_TARGET_ON) == 0)
1181                         intel_dp->last_power_cycle = jiffies;
1182
1183                 power_domain = intel_display_port_power_domain(intel_encoder);
1184                 intel_display_power_put(dev_priv, power_domain);
1185         }
1186 }
1187
1188 static void edp_panel_vdd_work(struct work_struct *__work)
1189 {
1190         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1191                                                  struct intel_dp, panel_vdd_work);
1192         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1193
1194         mutex_lock(&dev->mode_config.mutex);
1195         edp_panel_vdd_off_sync(intel_dp);
1196         mutex_unlock(&dev->mode_config.mutex);
1197 }
1198
1199 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1200 {
1201         if (!is_edp(intel_dp))
1202                 return;
1203
1204         WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1205
1206         intel_dp->want_panel_vdd = false;
1207
1208         if (sync) {
1209                 edp_panel_vdd_off_sync(intel_dp);
1210         } else {
1211                 /*
1212                  * Queue the timer to fire a long
1213                  * time from now (relative to the power down delay)
1214                  * to keep the panel power up across a sequence of operations
1215                  */
1216                 schedule_delayed_work(&intel_dp->panel_vdd_work,
1217                                       msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1218         }
1219 }
1220
1221 void intel_edp_panel_on(struct intel_dp *intel_dp)
1222 {
1223         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1224         struct drm_i915_private *dev_priv = dev->dev_private;
1225         u32 pp;
1226         u32 pp_ctrl_reg;
1227
1228         if (!is_edp(intel_dp))
1229                 return;
1230
1231         DRM_DEBUG_KMS("Turn eDP power on\n");
1232
1233         if (edp_have_panel_power(intel_dp)) {
1234                 DRM_DEBUG_KMS("eDP power already on\n");
1235                 return;
1236         }
1237
1238         wait_panel_power_cycle(intel_dp);
1239
1240         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1241         pp = ironlake_get_pp_control(intel_dp);
1242         if (IS_GEN5(dev)) {
1243                 /* ILK workaround: disable reset around power sequence */
1244                 pp &= ~PANEL_POWER_RESET;
1245                 I915_WRITE(pp_ctrl_reg, pp);
1246                 POSTING_READ(pp_ctrl_reg);
1247         }
1248
1249         pp |= POWER_TARGET_ON;
1250         if (!IS_GEN5(dev))
1251                 pp |= PANEL_POWER_RESET;
1252
1253         I915_WRITE(pp_ctrl_reg, pp);
1254         POSTING_READ(pp_ctrl_reg);
1255
1256         wait_panel_on(intel_dp);
1257         intel_dp->last_power_on = jiffies;
1258
1259         if (IS_GEN5(dev)) {
1260                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1261                 I915_WRITE(pp_ctrl_reg, pp);
1262                 POSTING_READ(pp_ctrl_reg);
1263         }
1264 }
1265
1266 void intel_edp_panel_off(struct intel_dp *intel_dp)
1267 {
1268         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1269         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1270         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1271         struct drm_i915_private *dev_priv = dev->dev_private;
1272         enum intel_display_power_domain power_domain;
1273         u32 pp;
1274         u32 pp_ctrl_reg;
1275
1276         if (!is_edp(intel_dp))
1277                 return;
1278
1279         DRM_DEBUG_KMS("Turn eDP power off\n");
1280
1281         edp_wait_backlight_off(intel_dp);
1282
1283         WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1284
1285         pp = ironlake_get_pp_control(intel_dp);
1286         /* We need to switch off panel power _and_ force vdd, for otherwise some
1287          * panels get very unhappy and cease to work. */
1288         pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1289                 EDP_BLC_ENABLE);
1290
1291         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1292
1293         intel_dp->want_panel_vdd = false;
1294
1295         I915_WRITE(pp_ctrl_reg, pp);
1296         POSTING_READ(pp_ctrl_reg);
1297
1298         intel_dp->last_power_cycle = jiffies;
1299         wait_panel_off(intel_dp);
1300
1301         /* We got a reference when we enabled the VDD. */
1302         power_domain = intel_display_port_power_domain(intel_encoder);
1303         intel_display_power_put(dev_priv, power_domain);
1304 }
1305
1306 void intel_edp_backlight_on(struct intel_dp *intel_dp)
1307 {
1308         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1309         struct drm_device *dev = intel_dig_port->base.base.dev;
1310         struct drm_i915_private *dev_priv = dev->dev_private;
1311         u32 pp;
1312         u32 pp_ctrl_reg;
1313
1314         if (!is_edp(intel_dp))
1315                 return;
1316
1317         DRM_DEBUG_KMS("\n");
1318         /*
1319          * If we enable the backlight right away following a panel power
1320          * on, we may see slight flicker as the panel syncs with the eDP
1321          * link.  So delay a bit to make sure the image is solid before
1322          * allowing it to appear.
1323          */
1324         wait_backlight_on(intel_dp);
1325         pp = ironlake_get_pp_control(intel_dp);
1326         pp |= EDP_BLC_ENABLE;
1327
1328         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1329
1330         I915_WRITE(pp_ctrl_reg, pp);
1331         POSTING_READ(pp_ctrl_reg);
1332
1333         intel_panel_enable_backlight(intel_dp->attached_connector);
1334 }
1335
1336 void intel_edp_backlight_off(struct intel_dp *intel_dp)
1337 {
1338         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1339         struct drm_i915_private *dev_priv = dev->dev_private;
1340         u32 pp;
1341         u32 pp_ctrl_reg;
1342
1343         if (!is_edp(intel_dp))
1344                 return;
1345
1346         intel_panel_disable_backlight(intel_dp->attached_connector);
1347
1348         DRM_DEBUG_KMS("\n");
1349         pp = ironlake_get_pp_control(intel_dp);
1350         pp &= ~EDP_BLC_ENABLE;
1351
1352         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1353
1354         I915_WRITE(pp_ctrl_reg, pp);
1355         POSTING_READ(pp_ctrl_reg);
1356         intel_dp->last_backlight_off = jiffies;
1357 }
1358
1359 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1360 {
1361         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1362         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1363         struct drm_device *dev = crtc->dev;
1364         struct drm_i915_private *dev_priv = dev->dev_private;
1365         u32 dpa_ctl;
1366
1367         assert_pipe_disabled(dev_priv,
1368                              to_intel_crtc(crtc)->pipe);
1369
1370         DRM_DEBUG_KMS("\n");
1371         dpa_ctl = I915_READ(DP_A);
1372         WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1373         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1374
1375         /* We don't adjust intel_dp->DP while tearing down the link, to
1376          * facilitate link retraining (e.g. after hotplug). Hence clear all
1377          * enable bits here to ensure that we don't enable too much. */
1378         intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1379         intel_dp->DP |= DP_PLL_ENABLE;
1380         I915_WRITE(DP_A, intel_dp->DP);
1381         POSTING_READ(DP_A);
1382         udelay(200);
1383 }
1384
1385 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1386 {
1387         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1388         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1389         struct drm_device *dev = crtc->dev;
1390         struct drm_i915_private *dev_priv = dev->dev_private;
1391         u32 dpa_ctl;
1392
1393         assert_pipe_disabled(dev_priv,
1394                              to_intel_crtc(crtc)->pipe);
1395
1396         dpa_ctl = I915_READ(DP_A);
1397         WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1398              "dp pll off, should be on\n");
1399         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1400
1401         /* We can't rely on the value tracked for the DP register in
1402          * intel_dp->DP because link_down must not change that (otherwise link
1403          * re-training will fail. */
1404         dpa_ctl &= ~DP_PLL_ENABLE;
1405         I915_WRITE(DP_A, dpa_ctl);
1406         POSTING_READ(DP_A);
1407         udelay(200);
1408 }
1409
1410 /* If the sink supports it, try to set the power state appropriately */
1411 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1412 {
1413         int ret, i;
1414
1415         /* Should have a valid DPCD by this point */
1416         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1417                 return;
1418
1419         if (mode != DRM_MODE_DPMS_ON) {
1420                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1421                                          DP_SET_POWER_D3);
1422                 if (ret != 1)
1423                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
1424         } else {
1425                 /*
1426                  * When turning on, we need to retry for 1ms to give the sink
1427                  * time to wake up.
1428                  */
1429                 for (i = 0; i < 3; i++) {
1430                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1431                                                  DP_SET_POWER_D0);
1432                         if (ret == 1)
1433                                 break;
1434                         msleep(1);
1435                 }
1436         }
1437 }
1438
1439 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1440                                   enum pipe *pipe)
1441 {
1442         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1443         enum port port = dp_to_dig_port(intel_dp)->port;
1444         struct drm_device *dev = encoder->base.dev;
1445         struct drm_i915_private *dev_priv = dev->dev_private;
1446         enum intel_display_power_domain power_domain;
1447         u32 tmp;
1448
1449         power_domain = intel_display_port_power_domain(encoder);
1450         if (!intel_display_power_enabled(dev_priv, power_domain))
1451                 return false;
1452
1453         tmp = I915_READ(intel_dp->output_reg);
1454
1455         if (!(tmp & DP_PORT_EN))
1456                 return false;
1457
1458         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1459                 *pipe = PORT_TO_PIPE_CPT(tmp);
1460         } else if (IS_CHERRYVIEW(dev)) {
1461                 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
1462         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1463                 *pipe = PORT_TO_PIPE(tmp);
1464         } else {
1465                 u32 trans_sel;
1466                 u32 trans_dp;
1467                 int i;
1468
1469                 switch (intel_dp->output_reg) {
1470                 case PCH_DP_B:
1471                         trans_sel = TRANS_DP_PORT_SEL_B;
1472                         break;
1473                 case PCH_DP_C:
1474                         trans_sel = TRANS_DP_PORT_SEL_C;
1475                         break;
1476                 case PCH_DP_D:
1477                         trans_sel = TRANS_DP_PORT_SEL_D;
1478                         break;
1479                 default:
1480                         return true;
1481                 }
1482
1483                 for_each_pipe(i) {
1484                         trans_dp = I915_READ(TRANS_DP_CTL(i));
1485                         if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1486                                 *pipe = i;
1487                                 return true;
1488                         }
1489                 }
1490
1491                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1492                               intel_dp->output_reg);
1493         }
1494
1495         return true;
1496 }
1497
1498 static void intel_dp_get_config(struct intel_encoder *encoder,
1499                                 struct intel_crtc_config *pipe_config)
1500 {
1501         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1502         u32 tmp, flags = 0;
1503         struct drm_device *dev = encoder->base.dev;
1504         struct drm_i915_private *dev_priv = dev->dev_private;
1505         enum port port = dp_to_dig_port(intel_dp)->port;
1506         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1507         int dotclock;
1508
1509         tmp = I915_READ(intel_dp->output_reg);
1510         if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1511                 pipe_config->has_audio = true;
1512
1513         if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1514                 if (tmp & DP_SYNC_HS_HIGH)
1515                         flags |= DRM_MODE_FLAG_PHSYNC;
1516                 else
1517                         flags |= DRM_MODE_FLAG_NHSYNC;
1518
1519                 if (tmp & DP_SYNC_VS_HIGH)
1520                         flags |= DRM_MODE_FLAG_PVSYNC;
1521                 else
1522                         flags |= DRM_MODE_FLAG_NVSYNC;
1523         } else {
1524                 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1525                 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1526                         flags |= DRM_MODE_FLAG_PHSYNC;
1527                 else
1528                         flags |= DRM_MODE_FLAG_NHSYNC;
1529
1530                 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1531                         flags |= DRM_MODE_FLAG_PVSYNC;
1532                 else
1533                         flags |= DRM_MODE_FLAG_NVSYNC;
1534         }
1535
1536         pipe_config->adjusted_mode.flags |= flags;
1537
1538         pipe_config->has_dp_encoder = true;
1539
1540         intel_dp_get_m_n(crtc, pipe_config);
1541
1542         if (port == PORT_A) {
1543                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1544                         pipe_config->port_clock = 162000;
1545                 else
1546                         pipe_config->port_clock = 270000;
1547         }
1548
1549         dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1550                                             &pipe_config->dp_m_n);
1551
1552         if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1553                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1554
1555         pipe_config->adjusted_mode.crtc_clock = dotclock;
1556
1557         if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1558             pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1559                 /*
1560                  * This is a big fat ugly hack.
1561                  *
1562                  * Some machines in UEFI boot mode provide us a VBT that has 18
1563                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1564                  * unknown we fail to light up. Yet the same BIOS boots up with
1565                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1566                  * max, not what it tells us to use.
1567                  *
1568                  * Note: This will still be broken if the eDP panel is not lit
1569                  * up by the BIOS, and thus we can't get the mode at module
1570                  * load.
1571                  */
1572                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1573                               pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1574                 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1575         }
1576 }
1577
1578 static bool is_edp_psr(struct drm_device *dev)
1579 {
1580         struct drm_i915_private *dev_priv = dev->dev_private;
1581
1582         return dev_priv->psr.sink_support;
1583 }
1584
1585 static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1586 {
1587         struct drm_i915_private *dev_priv = dev->dev_private;
1588
1589         if (!HAS_PSR(dev))
1590                 return false;
1591
1592         return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1593 }
1594
1595 static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1596                                     struct edp_vsc_psr *vsc_psr)
1597 {
1598         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1599         struct drm_device *dev = dig_port->base.base.dev;
1600         struct drm_i915_private *dev_priv = dev->dev_private;
1601         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1602         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1603         u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1604         uint32_t *data = (uint32_t *) vsc_psr;
1605         unsigned int i;
1606
1607         /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1608            the video DIP being updated before program video DIP data buffer
1609            registers for DIP being updated. */
1610         I915_WRITE(ctl_reg, 0);
1611         POSTING_READ(ctl_reg);
1612
1613         for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1614                 if (i < sizeof(struct edp_vsc_psr))
1615                         I915_WRITE(data_reg + i, *data++);
1616                 else
1617                         I915_WRITE(data_reg + i, 0);
1618         }
1619
1620         I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1621         POSTING_READ(ctl_reg);
1622 }
1623
1624 static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1625 {
1626         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1627         struct drm_i915_private *dev_priv = dev->dev_private;
1628         struct edp_vsc_psr psr_vsc;
1629
1630         if (intel_dp->psr_setup_done)
1631                 return;
1632
1633         /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1634         memset(&psr_vsc, 0, sizeof(psr_vsc));
1635         psr_vsc.sdp_header.HB0 = 0;
1636         psr_vsc.sdp_header.HB1 = 0x7;
1637         psr_vsc.sdp_header.HB2 = 0x2;
1638         psr_vsc.sdp_header.HB3 = 0x8;
1639         intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1640
1641         /* Avoid continuous PSR exit by masking memup and hpd */
1642         I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
1643                    EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
1644
1645         intel_dp->psr_setup_done = true;
1646 }
1647
1648 static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1649 {
1650         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1651         struct drm_i915_private *dev_priv = dev->dev_private;
1652         uint32_t aux_clock_divider;
1653         int precharge = 0x3;
1654         int msg_size = 5;       /* Header(4) + Message(1) */
1655
1656         aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1657
1658         /* Enable PSR in sink */
1659         if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1660                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1661                                    DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
1662         else
1663                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1664                                    DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
1665
1666         /* Setup AUX registers */
1667         I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1668         I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1669         I915_WRITE(EDP_PSR_AUX_CTL(dev),
1670                    DP_AUX_CH_CTL_TIME_OUT_400us |
1671                    (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1672                    (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1673                    (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1674 }
1675
1676 static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1677 {
1678         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1679         struct drm_i915_private *dev_priv = dev->dev_private;
1680         uint32_t max_sleep_time = 0x1f;
1681         uint32_t idle_frames = 1;
1682         uint32_t val = 0x0;
1683         const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
1684
1685         if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1686                 val |= EDP_PSR_LINK_STANDBY;
1687                 val |= EDP_PSR_TP2_TP3_TIME_0us;
1688                 val |= EDP_PSR_TP1_TIME_0us;
1689                 val |= EDP_PSR_SKIP_AUX_EXIT;
1690         } else
1691                 val |= EDP_PSR_LINK_DISABLE;
1692
1693         I915_WRITE(EDP_PSR_CTL(dev), val |
1694                    (IS_BROADWELL(dev) ? 0 : link_entry_time) |
1695                    max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1696                    idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1697                    EDP_PSR_ENABLE);
1698 }
1699
1700 static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1701 {
1702         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1703         struct drm_device *dev = dig_port->base.base.dev;
1704         struct drm_i915_private *dev_priv = dev->dev_private;
1705         struct drm_crtc *crtc = dig_port->base.base.crtc;
1706         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1707         struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->primary->fb)->obj;
1708         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1709
1710         dev_priv->psr.source_ok = false;
1711
1712         if (!HAS_PSR(dev)) {
1713                 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1714                 return false;
1715         }
1716
1717         if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1718             (dig_port->port != PORT_A)) {
1719                 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1720                 return false;
1721         }
1722
1723         if (!i915.enable_psr) {
1724                 DRM_DEBUG_KMS("PSR disable by flag\n");
1725                 return false;
1726         }
1727
1728         crtc = dig_port->base.base.crtc;
1729         if (crtc == NULL) {
1730                 DRM_DEBUG_KMS("crtc not active for PSR\n");
1731                 return false;
1732         }
1733
1734         intel_crtc = to_intel_crtc(crtc);
1735         if (!intel_crtc_active(crtc)) {
1736                 DRM_DEBUG_KMS("crtc not active for PSR\n");
1737                 return false;
1738         }
1739
1740         obj = to_intel_framebuffer(crtc->primary->fb)->obj;
1741         if (obj->tiling_mode != I915_TILING_X ||
1742             obj->fence_reg == I915_FENCE_REG_NONE) {
1743                 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
1744                 return false;
1745         }
1746
1747         if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1748                 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
1749                 return false;
1750         }
1751
1752         if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1753             S3D_ENABLE) {
1754                 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1755                 return false;
1756         }
1757
1758         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
1759                 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1760                 return false;
1761         }
1762
1763         dev_priv->psr.source_ok = true;
1764         return true;
1765 }
1766
1767 static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
1768 {
1769         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1770
1771         if (!intel_edp_psr_match_conditions(intel_dp) ||
1772             intel_edp_is_psr_enabled(dev))
1773                 return;
1774
1775         /* Setup PSR once */
1776         intel_edp_psr_setup(intel_dp);
1777
1778         /* Enable PSR on the panel */
1779         intel_edp_psr_enable_sink(intel_dp);
1780
1781         /* Enable PSR on the host */
1782         intel_edp_psr_enable_source(intel_dp);
1783 }
1784
1785 void intel_edp_psr_enable(struct intel_dp *intel_dp)
1786 {
1787         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1788
1789         if (intel_edp_psr_match_conditions(intel_dp) &&
1790             !intel_edp_is_psr_enabled(dev))
1791                 intel_edp_psr_do_enable(intel_dp);
1792 }
1793
1794 void intel_edp_psr_disable(struct intel_dp *intel_dp)
1795 {
1796         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1797         struct drm_i915_private *dev_priv = dev->dev_private;
1798
1799         if (!intel_edp_is_psr_enabled(dev))
1800                 return;
1801
1802         I915_WRITE(EDP_PSR_CTL(dev),
1803                    I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
1804
1805         /* Wait till PSR is idle */
1806         if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
1807                        EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1808                 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1809 }
1810
1811 void intel_edp_psr_update(struct drm_device *dev)
1812 {
1813         struct intel_encoder *encoder;
1814         struct intel_dp *intel_dp = NULL;
1815
1816         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1817                 if (encoder->type == INTEL_OUTPUT_EDP) {
1818                         intel_dp = enc_to_intel_dp(&encoder->base);
1819
1820                         if (!is_edp_psr(dev))
1821                                 return;
1822
1823                         if (!intel_edp_psr_match_conditions(intel_dp))
1824                                 intel_edp_psr_disable(intel_dp);
1825                         else
1826                                 if (!intel_edp_is_psr_enabled(dev))
1827                                         intel_edp_psr_do_enable(intel_dp);
1828                 }
1829 }
1830
1831 static void intel_disable_dp(struct intel_encoder *encoder)
1832 {
1833         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1834         enum port port = dp_to_dig_port(intel_dp)->port;
1835         struct drm_device *dev = encoder->base.dev;
1836
1837         /* Make sure the panel is off before trying to change the mode. But also
1838          * ensure that we have vdd while we switch off the panel. */
1839         intel_edp_panel_vdd_on(intel_dp);
1840         intel_edp_backlight_off(intel_dp);
1841         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1842         intel_edp_panel_off(intel_dp);
1843
1844         /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1845         if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
1846                 intel_dp_link_down(intel_dp);
1847 }
1848
1849 static void g4x_post_disable_dp(struct intel_encoder *encoder)
1850 {
1851         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1852         enum port port = dp_to_dig_port(intel_dp)->port;
1853
1854         if (port != PORT_A)
1855                 return;
1856
1857         intel_dp_link_down(intel_dp);
1858         ironlake_edp_pll_off(intel_dp);
1859 }
1860
1861 static void vlv_post_disable_dp(struct intel_encoder *encoder)
1862 {
1863         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1864
1865         intel_dp_link_down(intel_dp);
1866 }
1867
1868 static void chv_post_disable_dp(struct intel_encoder *encoder)
1869 {
1870         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1871         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1872         struct drm_device *dev = encoder->base.dev;
1873         struct drm_i915_private *dev_priv = dev->dev_private;
1874         struct intel_crtc *intel_crtc =
1875                 to_intel_crtc(encoder->base.crtc);
1876         enum dpio_channel ch = vlv_dport_to_channel(dport);
1877         enum pipe pipe = intel_crtc->pipe;
1878         u32 val;
1879
1880         intel_dp_link_down(intel_dp);
1881
1882         mutex_lock(&dev_priv->dpio_lock);
1883
1884         /* Propagate soft reset to data lane reset */
1885         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
1886         val |= CHV_PCS_REQ_SOFTRESET_EN;
1887         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
1888
1889         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1890         val |= CHV_PCS_REQ_SOFTRESET_EN;
1891         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1892
1893         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
1894         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1895         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
1896
1897         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
1898         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1899         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
1900
1901         mutex_unlock(&dev_priv->dpio_lock);
1902 }
1903
1904 static void intel_enable_dp(struct intel_encoder *encoder)
1905 {
1906         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1907         struct drm_device *dev = encoder->base.dev;
1908         struct drm_i915_private *dev_priv = dev->dev_private;
1909         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1910
1911         if (WARN_ON(dp_reg & DP_PORT_EN))
1912                 return;
1913
1914         intel_edp_panel_vdd_on(intel_dp);
1915         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1916         intel_dp_start_link_train(intel_dp);
1917         intel_edp_panel_on(intel_dp);
1918         edp_panel_vdd_off(intel_dp, true);
1919         intel_dp_complete_link_train(intel_dp);
1920         intel_dp_stop_link_train(intel_dp);
1921 }
1922
1923 static void g4x_enable_dp(struct intel_encoder *encoder)
1924 {
1925         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1926
1927         intel_enable_dp(encoder);
1928         intel_edp_backlight_on(intel_dp);
1929 }
1930
1931 static void vlv_enable_dp(struct intel_encoder *encoder)
1932 {
1933         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1934
1935         intel_edp_backlight_on(intel_dp);
1936 }
1937
1938 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
1939 {
1940         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1941         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1942
1943         intel_dp_prepare(encoder);
1944
1945         /* Only ilk+ has port A */
1946         if (dport->port == PORT_A) {
1947                 ironlake_set_pll_cpu_edp(intel_dp);
1948                 ironlake_edp_pll_on(intel_dp);
1949         }
1950 }
1951
1952 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
1953 {
1954         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1955         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1956         struct drm_device *dev = encoder->base.dev;
1957         struct drm_i915_private *dev_priv = dev->dev_private;
1958         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1959         enum dpio_channel port = vlv_dport_to_channel(dport);
1960         int pipe = intel_crtc->pipe;
1961         struct edp_power_seq power_seq;
1962         u32 val;
1963
1964         mutex_lock(&dev_priv->dpio_lock);
1965
1966         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1967         val = 0;
1968         if (pipe)
1969                 val |= (1<<21);
1970         else
1971                 val &= ~(1<<21);
1972         val |= 0x001000c4;
1973         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1974         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1975         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1976
1977         mutex_unlock(&dev_priv->dpio_lock);
1978
1979         if (is_edp(intel_dp)) {
1980                 /* init power sequencer on this pipe and port */
1981                 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1982                 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1983                                                               &power_seq);
1984         }
1985
1986         intel_enable_dp(encoder);
1987
1988         vlv_wait_port_ready(dev_priv, dport);
1989 }
1990
1991 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
1992 {
1993         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1994         struct drm_device *dev = encoder->base.dev;
1995         struct drm_i915_private *dev_priv = dev->dev_private;
1996         struct intel_crtc *intel_crtc =
1997                 to_intel_crtc(encoder->base.crtc);
1998         enum dpio_channel port = vlv_dport_to_channel(dport);
1999         int pipe = intel_crtc->pipe;
2000
2001         intel_dp_prepare(encoder);
2002
2003         /* Program Tx lane resets to default */
2004         mutex_lock(&dev_priv->dpio_lock);
2005         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
2006                          DPIO_PCS_TX_LANE2_RESET |
2007                          DPIO_PCS_TX_LANE1_RESET);
2008         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
2009                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2010                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2011                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2012                                  DPIO_PCS_CLK_SOFT_RESET);
2013
2014         /* Fix up inter-pair skew failure */
2015         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2016         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2017         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
2018         mutex_unlock(&dev_priv->dpio_lock);
2019 }
2020
2021 static void chv_pre_enable_dp(struct intel_encoder *encoder)
2022 {
2023         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2024         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2025         struct drm_device *dev = encoder->base.dev;
2026         struct drm_i915_private *dev_priv = dev->dev_private;
2027         struct edp_power_seq power_seq;
2028         struct intel_crtc *intel_crtc =
2029                 to_intel_crtc(encoder->base.crtc);
2030         enum dpio_channel ch = vlv_dport_to_channel(dport);
2031         int pipe = intel_crtc->pipe;
2032         int data, i;
2033         u32 val;
2034
2035         mutex_lock(&dev_priv->dpio_lock);
2036
2037         /* Deassert soft data lane reset*/
2038         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2039         val |= CHV_PCS_REQ_SOFTRESET_EN;
2040         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2041
2042         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2043         val |= CHV_PCS_REQ_SOFTRESET_EN;
2044         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2045
2046         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2047         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2048         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2049
2050         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2051         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2052         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2053
2054         /* Program Tx lane latency optimal setting*/
2055         for (i = 0; i < 4; i++) {
2056                 /* Set the latency optimal bit */
2057                 data = (i == 1) ? 0x0 : 0x6;
2058                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2059                                 data << DPIO_FRC_LATENCY_SHFIT);
2060
2061                 /* Set the upar bit */
2062                 data = (i == 1) ? 0x0 : 0x1;
2063                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2064                                 data << DPIO_UPAR_SHIFT);
2065         }
2066
2067         /* Data lane stagger programming */
2068         /* FIXME: Fix up value only after power analysis */
2069
2070         mutex_unlock(&dev_priv->dpio_lock);
2071
2072         if (is_edp(intel_dp)) {
2073                 /* init power sequencer on this pipe and port */
2074                 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2075                 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2076                                                               &power_seq);
2077         }
2078
2079         intel_enable_dp(encoder);
2080
2081         vlv_wait_port_ready(dev_priv, dport);
2082 }
2083
2084 /*
2085  * Native read with retry for link status and receiver capability reads for
2086  * cases where the sink may still be asleep.
2087  *
2088  * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2089  * supposed to retry 3 times per the spec.
2090  */
2091 static ssize_t
2092 intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2093                         void *buffer, size_t size)
2094 {
2095         ssize_t ret;
2096         int i;
2097
2098         for (i = 0; i < 3; i++) {
2099                 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2100                 if (ret == size)
2101                         return ret;
2102                 msleep(1);
2103         }
2104
2105         return ret;
2106 }
2107
2108 /*
2109  * Fetch AUX CH registers 0x202 - 0x207 which contain
2110  * link status information
2111  */
2112 static bool
2113 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2114 {
2115         return intel_dp_dpcd_read_wake(&intel_dp->aux,
2116                                        DP_LANE0_1_STATUS,
2117                                        link_status,
2118                                        DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
2119 }
2120
2121 /*
2122  * These are source-specific values; current Intel hardware supports
2123  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
2124  */
2125
2126 static uint8_t
2127 intel_dp_voltage_max(struct intel_dp *intel_dp)
2128 {
2129         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2130         enum port port = dp_to_dig_port(intel_dp)->port;
2131
2132         if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
2133                 return DP_TRAIN_VOLTAGE_SWING_1200;
2134         else if (IS_GEN7(dev) && port == PORT_A)
2135                 return DP_TRAIN_VOLTAGE_SWING_800;
2136         else if (HAS_PCH_CPT(dev) && port != PORT_A)
2137                 return DP_TRAIN_VOLTAGE_SWING_1200;
2138         else
2139                 return DP_TRAIN_VOLTAGE_SWING_800;
2140 }
2141
2142 static uint8_t
2143 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2144 {
2145         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2146         enum port port = dp_to_dig_port(intel_dp)->port;
2147
2148         if (IS_BROADWELL(dev)) {
2149                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2150                 case DP_TRAIN_VOLTAGE_SWING_400:
2151                 case DP_TRAIN_VOLTAGE_SWING_600:
2152                         return DP_TRAIN_PRE_EMPHASIS_6;
2153                 case DP_TRAIN_VOLTAGE_SWING_800:
2154                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2155                 case DP_TRAIN_VOLTAGE_SWING_1200:
2156                 default:
2157                         return DP_TRAIN_PRE_EMPHASIS_0;
2158                 }
2159         } else if (IS_HASWELL(dev)) {
2160                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2161                 case DP_TRAIN_VOLTAGE_SWING_400:
2162                         return DP_TRAIN_PRE_EMPHASIS_9_5;
2163                 case DP_TRAIN_VOLTAGE_SWING_600:
2164                         return DP_TRAIN_PRE_EMPHASIS_6;
2165                 case DP_TRAIN_VOLTAGE_SWING_800:
2166                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2167                 case DP_TRAIN_VOLTAGE_SWING_1200:
2168                 default:
2169                         return DP_TRAIN_PRE_EMPHASIS_0;
2170                 }
2171         } else if (IS_VALLEYVIEW(dev)) {
2172                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2173                 case DP_TRAIN_VOLTAGE_SWING_400:
2174                         return DP_TRAIN_PRE_EMPHASIS_9_5;
2175                 case DP_TRAIN_VOLTAGE_SWING_600:
2176                         return DP_TRAIN_PRE_EMPHASIS_6;
2177                 case DP_TRAIN_VOLTAGE_SWING_800:
2178                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2179                 case DP_TRAIN_VOLTAGE_SWING_1200:
2180                 default:
2181                         return DP_TRAIN_PRE_EMPHASIS_0;
2182                 }
2183         } else if (IS_GEN7(dev) && port == PORT_A) {
2184                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2185                 case DP_TRAIN_VOLTAGE_SWING_400:
2186                         return DP_TRAIN_PRE_EMPHASIS_6;
2187                 case DP_TRAIN_VOLTAGE_SWING_600:
2188                 case DP_TRAIN_VOLTAGE_SWING_800:
2189                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2190                 default:
2191                         return DP_TRAIN_PRE_EMPHASIS_0;
2192                 }
2193         } else {
2194                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2195                 case DP_TRAIN_VOLTAGE_SWING_400:
2196                         return DP_TRAIN_PRE_EMPHASIS_6;
2197                 case DP_TRAIN_VOLTAGE_SWING_600:
2198                         return DP_TRAIN_PRE_EMPHASIS_6;
2199                 case DP_TRAIN_VOLTAGE_SWING_800:
2200                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2201                 case DP_TRAIN_VOLTAGE_SWING_1200:
2202                 default:
2203                         return DP_TRAIN_PRE_EMPHASIS_0;
2204                 }
2205         }
2206 }
2207
2208 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2209 {
2210         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2211         struct drm_i915_private *dev_priv = dev->dev_private;
2212         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2213         struct intel_crtc *intel_crtc =
2214                 to_intel_crtc(dport->base.base.crtc);
2215         unsigned long demph_reg_value, preemph_reg_value,
2216                 uniqtranscale_reg_value;
2217         uint8_t train_set = intel_dp->train_set[0];
2218         enum dpio_channel port = vlv_dport_to_channel(dport);
2219         int pipe = intel_crtc->pipe;
2220
2221         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2222         case DP_TRAIN_PRE_EMPHASIS_0:
2223                 preemph_reg_value = 0x0004000;
2224                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2225                 case DP_TRAIN_VOLTAGE_SWING_400:
2226                         demph_reg_value = 0x2B405555;
2227                         uniqtranscale_reg_value = 0x552AB83A;
2228                         break;
2229                 case DP_TRAIN_VOLTAGE_SWING_600:
2230                         demph_reg_value = 0x2B404040;
2231                         uniqtranscale_reg_value = 0x5548B83A;
2232                         break;
2233                 case DP_TRAIN_VOLTAGE_SWING_800:
2234                         demph_reg_value = 0x2B245555;
2235                         uniqtranscale_reg_value = 0x5560B83A;
2236                         break;
2237                 case DP_TRAIN_VOLTAGE_SWING_1200:
2238                         demph_reg_value = 0x2B405555;
2239                         uniqtranscale_reg_value = 0x5598DA3A;
2240                         break;
2241                 default:
2242                         return 0;
2243                 }
2244                 break;
2245         case DP_TRAIN_PRE_EMPHASIS_3_5:
2246                 preemph_reg_value = 0x0002000;
2247                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2248                 case DP_TRAIN_VOLTAGE_SWING_400:
2249                         demph_reg_value = 0x2B404040;
2250                         uniqtranscale_reg_value = 0x5552B83A;
2251                         break;
2252                 case DP_TRAIN_VOLTAGE_SWING_600:
2253                         demph_reg_value = 0x2B404848;
2254                         uniqtranscale_reg_value = 0x5580B83A;
2255                         break;
2256                 case DP_TRAIN_VOLTAGE_SWING_800:
2257                         demph_reg_value = 0x2B404040;
2258                         uniqtranscale_reg_value = 0x55ADDA3A;
2259                         break;
2260                 default:
2261                         return 0;
2262                 }
2263                 break;
2264         case DP_TRAIN_PRE_EMPHASIS_6:
2265                 preemph_reg_value = 0x0000000;
2266                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2267                 case DP_TRAIN_VOLTAGE_SWING_400:
2268                         demph_reg_value = 0x2B305555;
2269                         uniqtranscale_reg_value = 0x5570B83A;
2270                         break;
2271                 case DP_TRAIN_VOLTAGE_SWING_600:
2272                         demph_reg_value = 0x2B2B4040;
2273                         uniqtranscale_reg_value = 0x55ADDA3A;
2274                         break;
2275                 default:
2276                         return 0;
2277                 }
2278                 break;
2279         case DP_TRAIN_PRE_EMPHASIS_9_5:
2280                 preemph_reg_value = 0x0006000;
2281                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2282                 case DP_TRAIN_VOLTAGE_SWING_400:
2283                         demph_reg_value = 0x1B405555;
2284                         uniqtranscale_reg_value = 0x55ADDA3A;
2285                         break;
2286                 default:
2287                         return 0;
2288                 }
2289                 break;
2290         default:
2291                 return 0;
2292         }
2293
2294         mutex_lock(&dev_priv->dpio_lock);
2295         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2296         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2297         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
2298                          uniqtranscale_reg_value);
2299         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2300         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2301         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2302         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
2303         mutex_unlock(&dev_priv->dpio_lock);
2304
2305         return 0;
2306 }
2307
2308 static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2309 {
2310         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2311         struct drm_i915_private *dev_priv = dev->dev_private;
2312         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2313         struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
2314         u32 deemph_reg_value, margin_reg_value, val, tx_dw2;
2315         uint8_t train_set = intel_dp->train_set[0];
2316         enum dpio_channel ch = vlv_dport_to_channel(dport);
2317         int pipe = intel_crtc->pipe;
2318
2319         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2320         case DP_TRAIN_PRE_EMPHASIS_0:
2321                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2322                 case DP_TRAIN_VOLTAGE_SWING_400:
2323                         deemph_reg_value = 128;
2324                         margin_reg_value = 52;
2325                         break;
2326                 case DP_TRAIN_VOLTAGE_SWING_600:
2327                         deemph_reg_value = 128;
2328                         margin_reg_value = 77;
2329                         break;
2330                 case DP_TRAIN_VOLTAGE_SWING_800:
2331                         deemph_reg_value = 128;
2332                         margin_reg_value = 102;
2333                         break;
2334                 case DP_TRAIN_VOLTAGE_SWING_1200:
2335                         deemph_reg_value = 128;
2336                         margin_reg_value = 154;
2337                         /* FIXME extra to set for 1200 */
2338                         break;
2339                 default:
2340                         return 0;
2341                 }
2342                 break;
2343         case DP_TRAIN_PRE_EMPHASIS_3_5:
2344                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2345                 case DP_TRAIN_VOLTAGE_SWING_400:
2346                         deemph_reg_value = 85;
2347                         margin_reg_value = 78;
2348                         break;
2349                 case DP_TRAIN_VOLTAGE_SWING_600:
2350                         deemph_reg_value = 85;
2351                         margin_reg_value = 116;
2352                         break;
2353                 case DP_TRAIN_VOLTAGE_SWING_800:
2354                         deemph_reg_value = 85;
2355                         margin_reg_value = 154;
2356                         break;
2357                 default:
2358                         return 0;
2359                 }
2360                 break;
2361         case DP_TRAIN_PRE_EMPHASIS_6:
2362                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2363                 case DP_TRAIN_VOLTAGE_SWING_400:
2364                         deemph_reg_value = 64;
2365                         margin_reg_value = 104;
2366                         break;
2367                 case DP_TRAIN_VOLTAGE_SWING_600:
2368                         deemph_reg_value = 64;
2369                         margin_reg_value = 154;
2370                         break;
2371                 default:
2372                         return 0;
2373                 }
2374                 break;
2375         case DP_TRAIN_PRE_EMPHASIS_9_5:
2376                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2377                 case DP_TRAIN_VOLTAGE_SWING_400:
2378                         deemph_reg_value = 43;
2379                         margin_reg_value = 154;
2380                         break;
2381                 default:
2382                         return 0;
2383                 }
2384                 break;
2385         default:
2386                 return 0;
2387         }
2388
2389         mutex_lock(&dev_priv->dpio_lock);
2390
2391         /* Clear calc init */
2392         vlv_dpio_write(dev_priv, pipe, CHV_PCS_DW10(ch), 0);
2393
2394         /* Program swing deemph */
2395         val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW4(ch));
2396         val &= ~DPIO_SWING_DEEMPH9P5_MASK;
2397         val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
2398         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(ch), val);
2399
2400         /* Program swing margin */
2401         tx_dw2 = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch));
2402         tx_dw2 &= ~DPIO_SWING_MARGIN_MASK;
2403         tx_dw2 |= margin_reg_value << DPIO_SWING_MARGIN_SHIFT;
2404         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch), tx_dw2);
2405
2406         /* Disable unique transition scale */
2407         val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch));
2408         val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
2409         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val);
2410
2411         if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
2412                         == DP_TRAIN_PRE_EMPHASIS_0) &&
2413                 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
2414                         == DP_TRAIN_VOLTAGE_SWING_1200)) {
2415
2416                 /*
2417                  * The document said it needs to set bit 27 for ch0 and bit 26
2418                  * for ch1. Might be a typo in the doc.
2419                  * For now, for this unique transition scale selection, set bit
2420                  * 27 for ch0 and ch1.
2421                  */
2422                 val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch));
2423                 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
2424                 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val);
2425
2426                 tx_dw2 |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2427                 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch), tx_dw2);
2428         }
2429
2430         /* Start swing calculation */
2431         vlv_dpio_write(dev_priv, pipe, CHV_PCS_DW10(ch),
2432                 (DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3));
2433
2434         /* LRC Bypass */
2435         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
2436         val |= DPIO_LRC_BYPASS;
2437         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
2438
2439         mutex_unlock(&dev_priv->dpio_lock);
2440
2441         return 0;
2442 }
2443
2444 static void
2445 intel_get_adjust_train(struct intel_dp *intel_dp,
2446                        const uint8_t link_status[DP_LINK_STATUS_SIZE])
2447 {
2448         uint8_t v = 0;
2449         uint8_t p = 0;
2450         int lane;
2451         uint8_t voltage_max;
2452         uint8_t preemph_max;
2453
2454         for (lane = 0; lane < intel_dp->lane_count; lane++) {
2455                 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2456                 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
2457
2458                 if (this_v > v)
2459                         v = this_v;
2460                 if (this_p > p)
2461                         p = this_p;
2462         }
2463
2464         voltage_max = intel_dp_voltage_max(intel_dp);
2465         if (v >= voltage_max)
2466                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
2467
2468         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2469         if (p >= preemph_max)
2470                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2471
2472         for (lane = 0; lane < 4; lane++)
2473                 intel_dp->train_set[lane] = v | p;
2474 }
2475
2476 static uint32_t
2477 intel_gen4_signal_levels(uint8_t train_set)
2478 {
2479         uint32_t        signal_levels = 0;
2480
2481         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2482         case DP_TRAIN_VOLTAGE_SWING_400:
2483         default:
2484                 signal_levels |= DP_VOLTAGE_0_4;
2485                 break;
2486         case DP_TRAIN_VOLTAGE_SWING_600:
2487                 signal_levels |= DP_VOLTAGE_0_6;
2488                 break;
2489         case DP_TRAIN_VOLTAGE_SWING_800:
2490                 signal_levels |= DP_VOLTAGE_0_8;
2491                 break;
2492         case DP_TRAIN_VOLTAGE_SWING_1200:
2493                 signal_levels |= DP_VOLTAGE_1_2;
2494                 break;
2495         }
2496         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2497         case DP_TRAIN_PRE_EMPHASIS_0:
2498         default:
2499                 signal_levels |= DP_PRE_EMPHASIS_0;
2500                 break;
2501         case DP_TRAIN_PRE_EMPHASIS_3_5:
2502                 signal_levels |= DP_PRE_EMPHASIS_3_5;
2503                 break;
2504         case DP_TRAIN_PRE_EMPHASIS_6:
2505                 signal_levels |= DP_PRE_EMPHASIS_6;
2506                 break;
2507         case DP_TRAIN_PRE_EMPHASIS_9_5:
2508                 signal_levels |= DP_PRE_EMPHASIS_9_5;
2509                 break;
2510         }
2511         return signal_levels;
2512 }
2513
2514 /* Gen6's DP voltage swing and pre-emphasis control */
2515 static uint32_t
2516 intel_gen6_edp_signal_levels(uint8_t train_set)
2517 {
2518         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2519                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2520         switch (signal_levels) {
2521         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2522         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2523                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2524         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2525                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
2526         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2527         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2528                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
2529         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2530         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2531                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
2532         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2533         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2534                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
2535         default:
2536                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2537                               "0x%x\n", signal_levels);
2538                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2539         }
2540 }
2541
2542 /* Gen7's DP voltage swing and pre-emphasis control */
2543 static uint32_t
2544 intel_gen7_edp_signal_levels(uint8_t train_set)
2545 {
2546         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2547                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2548         switch (signal_levels) {
2549         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2550                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2551         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2552                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2553         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2554                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2555
2556         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2557                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2558         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2559                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2560
2561         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2562                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2563         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2564                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2565
2566         default:
2567                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2568                               "0x%x\n", signal_levels);
2569                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2570         }
2571 }
2572
2573 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2574 static uint32_t
2575 intel_hsw_signal_levels(uint8_t train_set)
2576 {
2577         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2578                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2579         switch (signal_levels) {
2580         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2581                 return DDI_BUF_EMP_400MV_0DB_HSW;
2582         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2583                 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2584         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2585                 return DDI_BUF_EMP_400MV_6DB_HSW;
2586         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2587                 return DDI_BUF_EMP_400MV_9_5DB_HSW;
2588
2589         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2590                 return DDI_BUF_EMP_600MV_0DB_HSW;
2591         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2592                 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2593         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2594                 return DDI_BUF_EMP_600MV_6DB_HSW;
2595
2596         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2597                 return DDI_BUF_EMP_800MV_0DB_HSW;
2598         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2599                 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2600         default:
2601                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2602                               "0x%x\n", signal_levels);
2603                 return DDI_BUF_EMP_400MV_0DB_HSW;
2604         }
2605 }
2606
2607 static uint32_t
2608 intel_bdw_signal_levels(uint8_t train_set)
2609 {
2610         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2611                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2612         switch (signal_levels) {
2613         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2614                 return DDI_BUF_EMP_400MV_0DB_BDW;       /* Sel0 */
2615         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2616                 return DDI_BUF_EMP_400MV_3_5DB_BDW;     /* Sel1 */
2617         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2618                 return DDI_BUF_EMP_400MV_6DB_BDW;       /* Sel2 */
2619
2620         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2621                 return DDI_BUF_EMP_600MV_0DB_BDW;       /* Sel3 */
2622         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2623                 return DDI_BUF_EMP_600MV_3_5DB_BDW;     /* Sel4 */
2624         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2625                 return DDI_BUF_EMP_600MV_6DB_BDW;       /* Sel5 */
2626
2627         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2628                 return DDI_BUF_EMP_800MV_0DB_BDW;       /* Sel6 */
2629         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2630                 return DDI_BUF_EMP_800MV_3_5DB_BDW;     /* Sel7 */
2631
2632         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2633                 return DDI_BUF_EMP_1200MV_0DB_BDW;      /* Sel8 */
2634
2635         default:
2636                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2637                               "0x%x\n", signal_levels);
2638                 return DDI_BUF_EMP_400MV_0DB_BDW;       /* Sel0 */
2639         }
2640 }
2641
2642 /* Properly updates "DP" with the correct signal levels. */
2643 static void
2644 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2645 {
2646         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2647         enum port port = intel_dig_port->port;
2648         struct drm_device *dev = intel_dig_port->base.base.dev;
2649         uint32_t signal_levels, mask;
2650         uint8_t train_set = intel_dp->train_set[0];
2651
2652         if (IS_BROADWELL(dev)) {
2653                 signal_levels = intel_bdw_signal_levels(train_set);
2654                 mask = DDI_BUF_EMP_MASK;
2655         } else if (IS_HASWELL(dev)) {
2656                 signal_levels = intel_hsw_signal_levels(train_set);
2657                 mask = DDI_BUF_EMP_MASK;
2658         } else if (IS_CHERRYVIEW(dev)) {
2659                 signal_levels = intel_chv_signal_levels(intel_dp);
2660                 mask = 0;
2661         } else if (IS_VALLEYVIEW(dev)) {
2662                 signal_levels = intel_vlv_signal_levels(intel_dp);
2663                 mask = 0;
2664         } else if (IS_GEN7(dev) && port == PORT_A) {
2665                 signal_levels = intel_gen7_edp_signal_levels(train_set);
2666                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
2667         } else if (IS_GEN6(dev) && port == PORT_A) {
2668                 signal_levels = intel_gen6_edp_signal_levels(train_set);
2669                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2670         } else {
2671                 signal_levels = intel_gen4_signal_levels(train_set);
2672                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2673         }
2674
2675         DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2676
2677         *DP = (*DP & ~mask) | signal_levels;
2678 }
2679
2680 static bool
2681 intel_dp_set_link_train(struct intel_dp *intel_dp,
2682                         uint32_t *DP,
2683                         uint8_t dp_train_pat)
2684 {
2685         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2686         struct drm_device *dev = intel_dig_port->base.base.dev;
2687         struct drm_i915_private *dev_priv = dev->dev_private;
2688         enum port port = intel_dig_port->port;
2689         uint8_t buf[sizeof(intel_dp->train_set) + 1];
2690         int ret, len;
2691
2692         if (HAS_DDI(dev)) {
2693                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2694
2695                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2696                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2697                 else
2698                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2699
2700                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2701                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2702                 case DP_TRAINING_PATTERN_DISABLE:
2703                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2704
2705                         break;
2706                 case DP_TRAINING_PATTERN_1:
2707                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2708                         break;
2709                 case DP_TRAINING_PATTERN_2:
2710                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2711                         break;
2712                 case DP_TRAINING_PATTERN_3:
2713                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2714                         break;
2715                 }
2716                 I915_WRITE(DP_TP_CTL(port), temp);
2717
2718         } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2719                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2720
2721                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2722                 case DP_TRAINING_PATTERN_DISABLE:
2723                         *DP |= DP_LINK_TRAIN_OFF_CPT;
2724                         break;
2725                 case DP_TRAINING_PATTERN_1:
2726                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2727                         break;
2728                 case DP_TRAINING_PATTERN_2:
2729                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2730                         break;
2731                 case DP_TRAINING_PATTERN_3:
2732                         DRM_ERROR("DP training pattern 3 not supported\n");
2733                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2734                         break;
2735                 }
2736
2737         } else {
2738                 *DP &= ~DP_LINK_TRAIN_MASK;
2739
2740                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2741                 case DP_TRAINING_PATTERN_DISABLE:
2742                         *DP |= DP_LINK_TRAIN_OFF;
2743                         break;
2744                 case DP_TRAINING_PATTERN_1:
2745                         *DP |= DP_LINK_TRAIN_PAT_1;
2746                         break;
2747                 case DP_TRAINING_PATTERN_2:
2748                         *DP |= DP_LINK_TRAIN_PAT_2;
2749                         break;
2750                 case DP_TRAINING_PATTERN_3:
2751                         DRM_ERROR("DP training pattern 3 not supported\n");
2752                         *DP |= DP_LINK_TRAIN_PAT_2;
2753                         break;
2754                 }
2755         }
2756
2757         I915_WRITE(intel_dp->output_reg, *DP);
2758         POSTING_READ(intel_dp->output_reg);
2759
2760         buf[0] = dp_train_pat;
2761         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
2762             DP_TRAINING_PATTERN_DISABLE) {
2763                 /* don't write DP_TRAINING_LANEx_SET on disable */
2764                 len = 1;
2765         } else {
2766                 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2767                 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2768                 len = intel_dp->lane_count + 1;
2769         }
2770
2771         ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
2772                                 buf, len);
2773
2774         return ret == len;
2775 }
2776
2777 static bool
2778 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2779                         uint8_t dp_train_pat)
2780 {
2781         memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
2782         intel_dp_set_signal_levels(intel_dp, DP);
2783         return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2784 }
2785
2786 static bool
2787 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2788                            const uint8_t link_status[DP_LINK_STATUS_SIZE])
2789 {
2790         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2791         struct drm_device *dev = intel_dig_port->base.base.dev;
2792         struct drm_i915_private *dev_priv = dev->dev_private;
2793         int ret;
2794
2795         intel_get_adjust_train(intel_dp, link_status);
2796         intel_dp_set_signal_levels(intel_dp, DP);
2797
2798         I915_WRITE(intel_dp->output_reg, *DP);
2799         POSTING_READ(intel_dp->output_reg);
2800
2801         ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
2802                                 intel_dp->train_set, intel_dp->lane_count);
2803
2804         return ret == intel_dp->lane_count;
2805 }
2806
2807 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2808 {
2809         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2810         struct drm_device *dev = intel_dig_port->base.base.dev;
2811         struct drm_i915_private *dev_priv = dev->dev_private;
2812         enum port port = intel_dig_port->port;
2813         uint32_t val;
2814
2815         if (!HAS_DDI(dev))
2816                 return;
2817
2818         val = I915_READ(DP_TP_CTL(port));
2819         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2820         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2821         I915_WRITE(DP_TP_CTL(port), val);
2822
2823         /*
2824          * On PORT_A we can have only eDP in SST mode. There the only reason
2825          * we need to set idle transmission mode is to work around a HW issue
2826          * where we enable the pipe while not in idle link-training mode.
2827          * In this case there is requirement to wait for a minimum number of
2828          * idle patterns to be sent.
2829          */
2830         if (port == PORT_A)
2831                 return;
2832
2833         if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2834                      1))
2835                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2836 }
2837
2838 /* Enable corresponding port and start training pattern 1 */
2839 void
2840 intel_dp_start_link_train(struct intel_dp *intel_dp)
2841 {
2842         struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2843         struct drm_device *dev = encoder->dev;
2844         int i;
2845         uint8_t voltage;
2846         int voltage_tries, loop_tries;
2847         uint32_t DP = intel_dp->DP;
2848         uint8_t link_config[2];
2849
2850         if (HAS_DDI(dev))
2851                 intel_ddi_prepare_link_retrain(encoder);
2852
2853         /* Write the link configuration data */
2854         link_config[0] = intel_dp->link_bw;
2855         link_config[1] = intel_dp->lane_count;
2856         if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2857                 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
2858         drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
2859
2860         link_config[0] = 0;
2861         link_config[1] = DP_SET_ANSI_8B10B;
2862         drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
2863
2864         DP |= DP_PORT_EN;
2865
2866         /* clock recovery */
2867         if (!intel_dp_reset_link_train(intel_dp, &DP,
2868                                        DP_TRAINING_PATTERN_1 |
2869                                        DP_LINK_SCRAMBLING_DISABLE)) {
2870                 DRM_ERROR("failed to enable link training\n");
2871                 return;
2872         }
2873
2874         voltage = 0xff;
2875         voltage_tries = 0;
2876         loop_tries = 0;
2877         for (;;) {
2878                 uint8_t link_status[DP_LINK_STATUS_SIZE];
2879
2880                 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2881                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2882                         DRM_ERROR("failed to get link status\n");
2883                         break;
2884                 }
2885
2886                 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2887                         DRM_DEBUG_KMS("clock recovery OK\n");
2888                         break;
2889                 }
2890
2891                 /* Check to see if we've tried the max voltage */
2892                 for (i = 0; i < intel_dp->lane_count; i++)
2893                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2894                                 break;
2895                 if (i == intel_dp->lane_count) {
2896                         ++loop_tries;
2897                         if (loop_tries == 5) {
2898                                 DRM_ERROR("too many full retries, give up\n");
2899                                 break;
2900                         }
2901                         intel_dp_reset_link_train(intel_dp, &DP,
2902                                                   DP_TRAINING_PATTERN_1 |
2903                                                   DP_LINK_SCRAMBLING_DISABLE);
2904                         voltage_tries = 0;
2905                         continue;
2906                 }
2907
2908                 /* Check to see if we've tried the same voltage 5 times */
2909                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2910                         ++voltage_tries;
2911                         if (voltage_tries == 5) {
2912                                 DRM_ERROR("too many voltage retries, give up\n");
2913                                 break;
2914                         }
2915                 } else
2916                         voltage_tries = 0;
2917                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
2918
2919                 /* Update training set as requested by target */
2920                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2921                         DRM_ERROR("failed to update link training\n");
2922                         break;
2923                 }
2924         }
2925
2926         intel_dp->DP = DP;
2927 }
2928
2929 void
2930 intel_dp_complete_link_train(struct intel_dp *intel_dp)
2931 {
2932         bool channel_eq = false;
2933         int tries, cr_tries;
2934         uint32_t DP = intel_dp->DP;
2935         uint32_t training_pattern = DP_TRAINING_PATTERN_2;
2936
2937         /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
2938         if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
2939                 training_pattern = DP_TRAINING_PATTERN_3;
2940
2941         /* channel equalization */
2942         if (!intel_dp_set_link_train(intel_dp, &DP,
2943                                      training_pattern |
2944                                      DP_LINK_SCRAMBLING_DISABLE)) {
2945                 DRM_ERROR("failed to start channel equalization\n");
2946                 return;
2947         }
2948
2949         tries = 0;
2950         cr_tries = 0;
2951         channel_eq = false;
2952         for (;;) {
2953                 uint8_t link_status[DP_LINK_STATUS_SIZE];
2954
2955                 if (cr_tries > 5) {
2956                         DRM_ERROR("failed to train DP, aborting\n");
2957                         break;
2958                 }
2959
2960                 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
2961                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2962                         DRM_ERROR("failed to get link status\n");
2963                         break;
2964                 }
2965
2966                 /* Make sure clock is still ok */
2967                 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2968                         intel_dp_start_link_train(intel_dp);
2969                         intel_dp_set_link_train(intel_dp, &DP,
2970                                                 training_pattern |
2971                                                 DP_LINK_SCRAMBLING_DISABLE);
2972                         cr_tries++;
2973                         continue;
2974                 }
2975
2976                 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2977                         channel_eq = true;
2978                         break;
2979                 }
2980
2981                 /* Try 5 times, then try clock recovery if that fails */
2982                 if (tries > 5) {
2983                         intel_dp_link_down(intel_dp);
2984                         intel_dp_start_link_train(intel_dp);
2985                         intel_dp_set_link_train(intel_dp, &DP,
2986                                                 training_pattern |
2987                                                 DP_LINK_SCRAMBLING_DISABLE);
2988                         tries = 0;
2989                         cr_tries++;
2990                         continue;
2991                 }
2992
2993                 /* Update training set as requested by target */
2994                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2995                         DRM_ERROR("failed to update link training\n");
2996                         break;
2997                 }
2998                 ++tries;
2999         }
3000
3001         intel_dp_set_idle_link_train(intel_dp);
3002
3003         intel_dp->DP = DP;
3004
3005         if (channel_eq)
3006                 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3007
3008 }
3009
3010 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3011 {
3012         intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3013                                 DP_TRAINING_PATTERN_DISABLE);
3014 }
3015
3016 static void
3017 intel_dp_link_down(struct intel_dp *intel_dp)
3018 {
3019         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3020         enum port port = intel_dig_port->port;
3021         struct drm_device *dev = intel_dig_port->base.base.dev;
3022         struct drm_i915_private *dev_priv = dev->dev_private;
3023         struct intel_crtc *intel_crtc =
3024                 to_intel_crtc(intel_dig_port->base.base.crtc);
3025         uint32_t DP = intel_dp->DP;
3026
3027         /*
3028          * DDI code has a strict mode set sequence and we should try to respect
3029          * it, otherwise we might hang the machine in many different ways. So we
3030          * really should be disabling the port only on a complete crtc_disable
3031          * sequence. This function is just called under two conditions on DDI
3032          * code:
3033          * - Link train failed while doing crtc_enable, and on this case we
3034          *   really should respect the mode set sequence and wait for a
3035          *   crtc_disable.
3036          * - Someone turned the monitor off and intel_dp_check_link_status
3037          *   called us. We don't need to disable the whole port on this case, so
3038          *   when someone turns the monitor on again,
3039          *   intel_ddi_prepare_link_retrain will take care of redoing the link
3040          *   train.
3041          */
3042         if (HAS_DDI(dev))
3043                 return;
3044
3045         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3046                 return;
3047
3048         DRM_DEBUG_KMS("\n");
3049
3050         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
3051                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3052                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
3053         } else {
3054                 DP &= ~DP_LINK_TRAIN_MASK;
3055                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
3056         }
3057         POSTING_READ(intel_dp->output_reg);
3058
3059         if (HAS_PCH_IBX(dev) &&
3060             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
3061                 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
3062
3063                 /* Hardware workaround: leaving our transcoder select
3064                  * set to transcoder B while it's off will prevent the
3065                  * corresponding HDMI output on transcoder A.
3066                  *
3067                  * Combine this with another hardware workaround:
3068                  * transcoder select bit can only be cleared while the
3069                  * port is enabled.
3070                  */
3071                 DP &= ~DP_PIPEB_SELECT;
3072                 I915_WRITE(intel_dp->output_reg, DP);
3073
3074                 /* Changes to enable or select take place the vblank
3075                  * after being written.
3076                  */
3077                 if (WARN_ON(crtc == NULL)) {
3078                         /* We should never try to disable a port without a crtc
3079                          * attached. For paranoia keep the code around for a
3080                          * bit. */
3081                         POSTING_READ(intel_dp->output_reg);
3082                         msleep(50);
3083                 } else
3084                         intel_wait_for_vblank(dev, intel_crtc->pipe);
3085         }
3086
3087         DP &= ~DP_AUDIO_OUTPUT_ENABLE;
3088         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3089         POSTING_READ(intel_dp->output_reg);
3090         msleep(intel_dp->panel_power_down_delay);
3091 }
3092
3093 static bool
3094 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3095 {
3096         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3097         struct drm_device *dev = dig_port->base.base.dev;
3098         struct drm_i915_private *dev_priv = dev->dev_private;
3099
3100         char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
3101
3102         if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3103                                     sizeof(intel_dp->dpcd)) < 0)
3104                 return false; /* aux transfer failed */
3105
3106         hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
3107                            32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
3108         DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
3109
3110         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3111                 return false; /* DPCD not present */
3112
3113         /* Check if the panel supports PSR */
3114         memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
3115         if (is_edp(intel_dp)) {
3116                 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3117                                         intel_dp->psr_dpcd,
3118                                         sizeof(intel_dp->psr_dpcd));
3119                 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3120                         dev_priv->psr.sink_support = true;
3121                         DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3122                 }
3123         }
3124
3125         /* Training Pattern 3 support */
3126         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3127             intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3128                 intel_dp->use_tps3 = true;
3129                 DRM_DEBUG_KMS("Displayport TPS3 supported");
3130         } else
3131                 intel_dp->use_tps3 = false;
3132
3133         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3134               DP_DWN_STRM_PORT_PRESENT))
3135                 return true; /* native DP sink */
3136
3137         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3138                 return true; /* no per-port downstream info */
3139
3140         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3141                                     intel_dp->downstream_ports,
3142                                     DP_MAX_DOWNSTREAM_PORTS) < 0)
3143                 return false; /* downstream port status fetch failed */
3144
3145         return true;
3146 }
3147
3148 static void
3149 intel_dp_probe_oui(struct intel_dp *intel_dp)
3150 {
3151         u8 buf[3];
3152
3153         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3154                 return;
3155
3156         intel_edp_panel_vdd_on(intel_dp);
3157
3158         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
3159                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3160                               buf[0], buf[1], buf[2]);
3161
3162         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
3163                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3164                               buf[0], buf[1], buf[2]);
3165
3166         edp_panel_vdd_off(intel_dp, false);
3167 }
3168
3169 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3170 {
3171         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3172         struct drm_device *dev = intel_dig_port->base.base.dev;
3173         struct intel_crtc *intel_crtc =
3174                 to_intel_crtc(intel_dig_port->base.base.crtc);
3175         u8 buf[1];
3176
3177         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
3178                 return -EAGAIN;
3179
3180         if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
3181                 return -ENOTTY;
3182
3183         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3184                                DP_TEST_SINK_START) < 0)
3185                 return -EAGAIN;
3186
3187         /* Wait 2 vblanks to be sure we will have the correct CRC value */
3188         intel_wait_for_vblank(dev, intel_crtc->pipe);
3189         intel_wait_for_vblank(dev, intel_crtc->pipe);
3190
3191         if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
3192                 return -EAGAIN;
3193
3194         drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
3195         return 0;
3196 }
3197
3198 static bool
3199 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3200 {
3201         return intel_dp_dpcd_read_wake(&intel_dp->aux,
3202                                        DP_DEVICE_SERVICE_IRQ_VECTOR,
3203                                        sink_irq_vector, 1) == 1;
3204 }
3205
3206 static void
3207 intel_dp_handle_test_request(struct intel_dp *intel_dp)
3208 {
3209         /* NAK by default */
3210         drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
3211 }
3212
3213 /*
3214  * According to DP spec
3215  * 5.1.2:
3216  *  1. Read DPCD
3217  *  2. Configure link according to Receiver Capabilities
3218  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
3219  *  4. Check link status on receipt of hot-plug interrupt
3220  */
3221
3222 void
3223 intel_dp_check_link_status(struct intel_dp *intel_dp)
3224 {
3225         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
3226         u8 sink_irq_vector;
3227         u8 link_status[DP_LINK_STATUS_SIZE];
3228
3229         if (!intel_encoder->connectors_active)
3230                 return;
3231
3232         if (WARN_ON(!intel_encoder->base.crtc))
3233                 return;
3234
3235         /* Try to read receiver status if the link appears to be up */
3236         if (!intel_dp_get_link_status(intel_dp, link_status)) {
3237                 return;
3238         }
3239
3240         /* Now read the DPCD to see if it's actually running */
3241         if (!intel_dp_get_dpcd(intel_dp)) {
3242                 return;
3243         }
3244
3245         /* Try to read the source of the interrupt */
3246         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3247             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3248                 /* Clear interrupt source */
3249                 drm_dp_dpcd_writeb(&intel_dp->aux,
3250                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
3251                                    sink_irq_vector);
3252
3253                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3254                         intel_dp_handle_test_request(intel_dp);
3255                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3256                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3257         }
3258
3259         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3260                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3261                               drm_get_encoder_name(&intel_encoder->base));
3262                 intel_dp_start_link_train(intel_dp);
3263                 intel_dp_complete_link_train(intel_dp);
3264                 intel_dp_stop_link_train(intel_dp);
3265         }
3266 }
3267
3268 /* XXX this is probably wrong for multiple downstream ports */
3269 static enum drm_connector_status
3270 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
3271 {
3272         uint8_t *dpcd = intel_dp->dpcd;
3273         uint8_t type;
3274
3275         if (!intel_dp_get_dpcd(intel_dp))
3276                 return connector_status_disconnected;
3277
3278         /* if there's no downstream port, we're done */
3279         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
3280                 return connector_status_connected;
3281
3282         /* If we're HPD-aware, SINK_COUNT changes dynamically */
3283         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3284             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
3285                 uint8_t reg;
3286
3287                 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3288                                             &reg, 1) < 0)
3289                         return connector_status_unknown;
3290
3291                 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3292                                               : connector_status_disconnected;
3293         }
3294
3295         /* If no HPD, poke DDC gently */
3296         if (drm_probe_ddc(&intel_dp->aux.ddc))
3297                 return connector_status_connected;
3298
3299         /* Well we tried, say unknown for unreliable port types */
3300         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3301                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3302                 if (type == DP_DS_PORT_TYPE_VGA ||
3303                     type == DP_DS_PORT_TYPE_NON_EDID)
3304                         return connector_status_unknown;
3305         } else {
3306                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3307                         DP_DWN_STRM_PORT_TYPE_MASK;
3308                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3309                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
3310                         return connector_status_unknown;
3311         }
3312
3313         /* Anything else is out of spec, warn and ignore */
3314         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
3315         return connector_status_disconnected;
3316 }
3317
3318 static enum drm_connector_status
3319 ironlake_dp_detect(struct intel_dp *intel_dp)
3320 {
3321         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3322         struct drm_i915_private *dev_priv = dev->dev_private;
3323         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3324         enum drm_connector_status status;
3325
3326         /* Can't disconnect eDP, but you can close the lid... */
3327         if (is_edp(intel_dp)) {
3328                 status = intel_panel_detect(dev);
3329                 if (status == connector_status_unknown)
3330                         status = connector_status_connected;
3331                 return status;
3332         }
3333
3334         if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3335                 return connector_status_disconnected;
3336
3337         return intel_dp_detect_dpcd(intel_dp);
3338 }
3339
3340 static enum drm_connector_status
3341 g4x_dp_detect(struct intel_dp *intel_dp)
3342 {
3343         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3344         struct drm_i915_private *dev_priv = dev->dev_private;
3345         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3346         uint32_t bit;
3347
3348         /* Can't disconnect eDP, but you can close the lid... */
3349         if (is_edp(intel_dp)) {
3350                 enum drm_connector_status status;
3351
3352                 status = intel_panel_detect(dev);
3353                 if (status == connector_status_unknown)
3354                         status = connector_status_connected;
3355                 return status;
3356         }
3357
3358         if (IS_VALLEYVIEW(dev)) {
3359                 switch (intel_dig_port->port) {
3360                 case PORT_B:
3361                         bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3362                         break;
3363                 case PORT_C:
3364                         bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3365                         break;
3366                 case PORT_D:
3367                         bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3368                         break;
3369                 default:
3370                         return connector_status_unknown;
3371                 }
3372         } else {
3373                 switch (intel_dig_port->port) {
3374                 case PORT_B:
3375                         bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3376                         break;
3377                 case PORT_C:
3378                         bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3379                         break;
3380                 case PORT_D:
3381                         bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3382                         break;
3383                 default:
3384                         return connector_status_unknown;
3385                 }
3386         }
3387
3388         if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
3389                 return connector_status_disconnected;
3390
3391         return intel_dp_detect_dpcd(intel_dp);
3392 }
3393
3394 static struct edid *
3395 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3396 {
3397         struct intel_connector *intel_connector = to_intel_connector(connector);
3398
3399         /* use cached edid if we have one */
3400         if (intel_connector->edid) {
3401                 /* invalid edid */
3402                 if (IS_ERR(intel_connector->edid))
3403                         return NULL;
3404
3405                 return drm_edid_duplicate(intel_connector->edid);
3406         }
3407
3408         return drm_get_edid(connector, adapter);
3409 }
3410
3411 static int
3412 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3413 {
3414         struct intel_connector *intel_connector = to_intel_connector(connector);
3415
3416         /* use cached edid if we have one */
3417         if (intel_connector->edid) {
3418                 /* invalid edid */
3419                 if (IS_ERR(intel_connector->edid))
3420                         return 0;
3421
3422                 return intel_connector_update_modes(connector,
3423                                                     intel_connector->edid);
3424         }
3425
3426         return intel_ddc_get_modes(connector, adapter);
3427 }
3428
3429 static enum drm_connector_status
3430 intel_dp_detect(struct drm_connector *connector, bool force)
3431 {
3432         struct intel_dp *intel_dp = intel_attached_dp(connector);
3433         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3434         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3435         struct drm_device *dev = connector->dev;
3436         struct drm_i915_private *dev_priv = dev->dev_private;
3437         enum drm_connector_status status;
3438         enum intel_display_power_domain power_domain;
3439         struct edid *edid = NULL;
3440
3441         intel_runtime_pm_get(dev_priv);
3442
3443         power_domain = intel_display_port_power_domain(intel_encoder);
3444         intel_display_power_get(dev_priv, power_domain);
3445
3446         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3447                       connector->base.id, drm_get_connector_name(connector));
3448
3449         intel_dp->has_audio = false;
3450
3451         if (HAS_PCH_SPLIT(dev))
3452                 status = ironlake_dp_detect(intel_dp);
3453         else
3454                 status = g4x_dp_detect(intel_dp);
3455
3456         if (status != connector_status_connected)
3457                 goto out;
3458
3459         intel_dp_probe_oui(intel_dp);
3460
3461         if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3462                 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
3463         } else {
3464                 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
3465                 if (edid) {
3466                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
3467                         kfree(edid);
3468                 }
3469         }
3470
3471         if (intel_encoder->type != INTEL_OUTPUT_EDP)
3472                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3473         status = connector_status_connected;
3474
3475 out:
3476         intel_display_power_put(dev_priv, power_domain);
3477
3478         intel_runtime_pm_put(dev_priv);
3479
3480         return status;
3481 }
3482
3483 static int intel_dp_get_modes(struct drm_connector *connector)
3484 {
3485         struct intel_dp *intel_dp = intel_attached_dp(connector);
3486         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3487         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3488         struct intel_connector *intel_connector = to_intel_connector(connector);
3489         struct drm_device *dev = connector->dev;
3490         struct drm_i915_private *dev_priv = dev->dev_private;
3491         enum intel_display_power_domain power_domain;
3492         int ret;
3493
3494         /* We should parse the EDID data and find out if it has an audio sink
3495          */
3496
3497         power_domain = intel_display_port_power_domain(intel_encoder);
3498         intel_display_power_get(dev_priv, power_domain);
3499
3500         ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
3501         intel_display_power_put(dev_priv, power_domain);
3502         if (ret)
3503                 return ret;
3504
3505         /* if eDP has no EDID, fall back to fixed mode */
3506         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
3507                 struct drm_display_mode *mode;
3508                 mode = drm_mode_duplicate(dev,
3509                                           intel_connector->panel.fixed_mode);
3510                 if (mode) {
3511                         drm_mode_probed_add(connector, mode);
3512                         return 1;
3513                 }
3514         }
3515         return 0;
3516 }
3517
3518 static bool
3519 intel_dp_detect_audio(struct drm_connector *connector)
3520 {
3521         struct intel_dp *intel_dp = intel_attached_dp(connector);
3522         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3523         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3524         struct drm_device *dev = connector->dev;
3525         struct drm_i915_private *dev_priv = dev->dev_private;
3526         enum intel_display_power_domain power_domain;
3527         struct edid *edid;
3528         bool has_audio = false;
3529
3530         power_domain = intel_display_port_power_domain(intel_encoder);
3531         intel_display_power_get(dev_priv, power_domain);
3532
3533         edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
3534         if (edid) {
3535                 has_audio = drm_detect_monitor_audio(edid);
3536                 kfree(edid);
3537         }
3538
3539         intel_display_power_put(dev_priv, power_domain);
3540
3541         return has_audio;
3542 }
3543
3544 static int
3545 intel_dp_set_property(struct drm_connector *connector,
3546                       struct drm_property *property,
3547                       uint64_t val)
3548 {
3549         struct drm_i915_private *dev_priv = connector->dev->dev_private;
3550         struct intel_connector *intel_connector = to_intel_connector(connector);
3551         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3552         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3553         int ret;
3554
3555         ret = drm_object_property_set_value(&connector->base, property, val);
3556         if (ret)
3557                 return ret;
3558
3559         if (property == dev_priv->force_audio_property) {
3560                 int i = val;
3561                 bool has_audio;
3562
3563                 if (i == intel_dp->force_audio)
3564                         return 0;
3565
3566                 intel_dp->force_audio = i;
3567
3568                 if (i == HDMI_AUDIO_AUTO)
3569                         has_audio = intel_dp_detect_audio(connector);
3570                 else
3571                         has_audio = (i == HDMI_AUDIO_ON);
3572
3573                 if (has_audio == intel_dp->has_audio)
3574                         return 0;
3575
3576                 intel_dp->has_audio = has_audio;
3577                 goto done;
3578         }
3579
3580         if (property == dev_priv->broadcast_rgb_property) {
3581                 bool old_auto = intel_dp->color_range_auto;
3582                 uint32_t old_range = intel_dp->color_range;
3583
3584                 switch (val) {
3585                 case INTEL_BROADCAST_RGB_AUTO:
3586                         intel_dp->color_range_auto = true;
3587                         break;
3588                 case INTEL_BROADCAST_RGB_FULL:
3589                         intel_dp->color_range_auto = false;
3590                         intel_dp->color_range = 0;
3591                         break;
3592                 case INTEL_BROADCAST_RGB_LIMITED:
3593                         intel_dp->color_range_auto = false;
3594                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
3595                         break;
3596                 default:
3597                         return -EINVAL;
3598                 }
3599
3600                 if (old_auto == intel_dp->color_range_auto &&
3601                     old_range == intel_dp->color_range)
3602                         return 0;
3603
3604                 goto done;
3605         }
3606
3607         if (is_edp(intel_dp) &&
3608             property == connector->dev->mode_config.scaling_mode_property) {
3609                 if (val == DRM_MODE_SCALE_NONE) {
3610                         DRM_DEBUG_KMS("no scaling not supported\n");
3611                         return -EINVAL;
3612                 }
3613
3614                 if (intel_connector->panel.fitting_mode == val) {
3615                         /* the eDP scaling property is not changed */
3616                         return 0;
3617                 }
3618                 intel_connector->panel.fitting_mode = val;
3619
3620                 goto done;
3621         }
3622
3623         return -EINVAL;
3624
3625 done:
3626         if (intel_encoder->base.crtc)
3627                 intel_crtc_restore_mode(intel_encoder->base.crtc);
3628
3629         return 0;
3630 }
3631
3632 static void
3633 intel_dp_connector_destroy(struct drm_connector *connector)
3634 {
3635         struct intel_connector *intel_connector = to_intel_connector(connector);
3636
3637         if (!IS_ERR_OR_NULL(intel_connector->edid))
3638                 kfree(intel_connector->edid);
3639
3640         /* Can't call is_edp() since the encoder may have been destroyed
3641          * already. */
3642         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3643                 intel_panel_fini(&intel_connector->panel);
3644
3645         drm_connector_cleanup(connector);
3646         kfree(connector);
3647 }
3648
3649 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
3650 {
3651         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3652         struct intel_dp *intel_dp = &intel_dig_port->dp;
3653         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3654
3655         drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
3656         drm_encoder_cleanup(encoder);
3657         if (is_edp(intel_dp)) {
3658                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3659                 mutex_lock(&dev->mode_config.mutex);
3660                 edp_panel_vdd_off_sync(intel_dp);
3661                 mutex_unlock(&dev->mode_config.mutex);
3662         }
3663         kfree(intel_dig_port);
3664 }
3665
3666 static const struct drm_connector_funcs intel_dp_connector_funcs = {
3667         .dpms = intel_connector_dpms,
3668         .detect = intel_dp_detect,
3669         .fill_modes = drm_helper_probe_single_connector_modes,
3670         .set_property = intel_dp_set_property,
3671         .destroy = intel_dp_connector_destroy,
3672 };
3673
3674 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3675         .get_modes = intel_dp_get_modes,
3676         .mode_valid = intel_dp_mode_valid,
3677         .best_encoder = intel_best_encoder,
3678 };
3679
3680 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
3681         .destroy = intel_dp_encoder_destroy,
3682 };
3683
3684 static void
3685 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
3686 {
3687         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3688
3689         intel_dp_check_link_status(intel_dp);
3690 }
3691
3692 /* Return which DP Port should be selected for Transcoder DP control */
3693 int
3694 intel_trans_dp_port_sel(struct drm_crtc *crtc)
3695 {
3696         struct drm_device *dev = crtc->dev;
3697         struct intel_encoder *intel_encoder;
3698         struct intel_dp *intel_dp;
3699
3700         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3701                 intel_dp = enc_to_intel_dp(&intel_encoder->base);
3702
3703                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3704                     intel_encoder->type == INTEL_OUTPUT_EDP)
3705                         return intel_dp->output_reg;
3706         }
3707
3708         return -1;
3709 }
3710
3711 /* check the VBT to see whether the eDP is on DP-D port */
3712 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
3713 {
3714         struct drm_i915_private *dev_priv = dev->dev_private;
3715         union child_device_config *p_child;
3716         int i;
3717         static const short port_mapping[] = {
3718                 [PORT_B] = PORT_IDPB,
3719                 [PORT_C] = PORT_IDPC,
3720                 [PORT_D] = PORT_IDPD,
3721         };
3722
3723         if (port == PORT_A)
3724                 return true;
3725
3726         if (!dev_priv->vbt.child_dev_num)
3727                 return false;
3728
3729         for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3730                 p_child = dev_priv->vbt.child_dev + i;
3731
3732                 if (p_child->common.dvo_port == port_mapping[port] &&
3733                     (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3734                     (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
3735                         return true;
3736         }
3737         return false;
3738 }
3739
3740 static void
3741 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3742 {
3743         struct intel_connector *intel_connector = to_intel_connector(connector);
3744
3745         intel_attach_force_audio_property(connector);
3746         intel_attach_broadcast_rgb_property(connector);
3747         intel_dp->color_range_auto = true;
3748
3749         if (is_edp(intel_dp)) {
3750                 drm_mode_create_scaling_mode_property(connector->dev);
3751                 drm_object_attach_property(
3752                         &connector->base,
3753                         connector->dev->mode_config.scaling_mode_property,
3754                         DRM_MODE_SCALE_ASPECT);
3755                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
3756         }
3757 }
3758
3759 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
3760 {
3761         intel_dp->last_power_cycle = jiffies;
3762         intel_dp->last_power_on = jiffies;
3763         intel_dp->last_backlight_off = jiffies;
3764 }
3765
3766 static void
3767 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
3768                                     struct intel_dp *intel_dp,
3769                                     struct edp_power_seq *out)
3770 {
3771         struct drm_i915_private *dev_priv = dev->dev_private;
3772         struct edp_power_seq cur, vbt, spec, final;
3773         u32 pp_on, pp_off, pp_div, pp;
3774         int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
3775
3776         if (HAS_PCH_SPLIT(dev)) {
3777                 pp_ctrl_reg = PCH_PP_CONTROL;
3778                 pp_on_reg = PCH_PP_ON_DELAYS;
3779                 pp_off_reg = PCH_PP_OFF_DELAYS;
3780                 pp_div_reg = PCH_PP_DIVISOR;
3781         } else {
3782                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3783
3784                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3785                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3786                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3787                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3788         }
3789
3790         /* Workaround: Need to write PP_CONTROL with the unlock key as
3791          * the very first thing. */
3792         pp = ironlake_get_pp_control(intel_dp);
3793         I915_WRITE(pp_ctrl_reg, pp);
3794
3795         pp_on = I915_READ(pp_on_reg);
3796         pp_off = I915_READ(pp_off_reg);
3797         pp_div = I915_READ(pp_div_reg);
3798
3799         /* Pull timing values out of registers */
3800         cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3801                 PANEL_POWER_UP_DELAY_SHIFT;
3802
3803         cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3804                 PANEL_LIGHT_ON_DELAY_SHIFT;
3805
3806         cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3807                 PANEL_LIGHT_OFF_DELAY_SHIFT;
3808
3809         cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3810                 PANEL_POWER_DOWN_DELAY_SHIFT;
3811
3812         cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3813                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3814
3815         DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3816                       cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3817
3818         vbt = dev_priv->vbt.edp_pps;
3819
3820         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3821          * our hw here, which are all in 100usec. */
3822         spec.t1_t3 = 210 * 10;
3823         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3824         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3825         spec.t10 = 500 * 10;
3826         /* This one is special and actually in units of 100ms, but zero
3827          * based in the hw (so we need to add 100 ms). But the sw vbt
3828          * table multiplies it with 1000 to make it in units of 100usec,
3829          * too. */
3830         spec.t11_t12 = (510 + 100) * 10;
3831
3832         DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3833                       vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3834
3835         /* Use the max of the register settings and vbt. If both are
3836          * unset, fall back to the spec limits. */
3837 #define assign_final(field)     final.field = (max(cur.field, vbt.field) == 0 ? \
3838                                        spec.field : \
3839                                        max(cur.field, vbt.field))
3840         assign_final(t1_t3);
3841         assign_final(t8);
3842         assign_final(t9);
3843         assign_final(t10);
3844         assign_final(t11_t12);
3845 #undef assign_final
3846
3847 #define get_delay(field)        (DIV_ROUND_UP(final.field, 10))
3848         intel_dp->panel_power_up_delay = get_delay(t1_t3);
3849         intel_dp->backlight_on_delay = get_delay(t8);
3850         intel_dp->backlight_off_delay = get_delay(t9);
3851         intel_dp->panel_power_down_delay = get_delay(t10);
3852         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3853 #undef get_delay
3854
3855         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3856                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3857                       intel_dp->panel_power_cycle_delay);
3858
3859         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3860                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3861
3862         if (out)
3863                 *out = final;
3864 }
3865
3866 static void
3867 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3868                                               struct intel_dp *intel_dp,
3869                                               struct edp_power_seq *seq)
3870 {
3871         struct drm_i915_private *dev_priv = dev->dev_private;
3872         u32 pp_on, pp_off, pp_div, port_sel = 0;
3873         int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3874         int pp_on_reg, pp_off_reg, pp_div_reg;
3875
3876         if (HAS_PCH_SPLIT(dev)) {
3877                 pp_on_reg = PCH_PP_ON_DELAYS;
3878                 pp_off_reg = PCH_PP_OFF_DELAYS;
3879                 pp_div_reg = PCH_PP_DIVISOR;
3880         } else {
3881                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3882
3883                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3884                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3885                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3886         }
3887
3888         /*
3889          * And finally store the new values in the power sequencer. The
3890          * backlight delays are set to 1 because we do manual waits on them. For
3891          * T8, even BSpec recommends doing it. For T9, if we don't do this,
3892          * we'll end up waiting for the backlight off delay twice: once when we
3893          * do the manual sleep, and once when we disable the panel and wait for
3894          * the PP_STATUS bit to become zero.
3895          */
3896         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
3897                 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
3898         pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
3899                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
3900         /* Compute the divisor for the pp clock, simply match the Bspec
3901          * formula. */
3902         pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
3903         pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
3904                         << PANEL_POWER_CYCLE_DELAY_SHIFT);
3905
3906         /* Haswell doesn't have any port selection bits for the panel
3907          * power sequencer any more. */
3908         if (IS_VALLEYVIEW(dev)) {
3909                 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3910                         port_sel = PANEL_PORT_SELECT_DPB_VLV;
3911                 else
3912                         port_sel = PANEL_PORT_SELECT_DPC_VLV;
3913         } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3914                 if (dp_to_dig_port(intel_dp)->port == PORT_A)
3915                         port_sel = PANEL_PORT_SELECT_DPA;
3916                 else
3917                         port_sel = PANEL_PORT_SELECT_DPD;
3918         }
3919
3920         pp_on |= port_sel;
3921
3922         I915_WRITE(pp_on_reg, pp_on);
3923         I915_WRITE(pp_off_reg, pp_off);
3924         I915_WRITE(pp_div_reg, pp_div);
3925
3926         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
3927                       I915_READ(pp_on_reg),
3928                       I915_READ(pp_off_reg),
3929                       I915_READ(pp_div_reg));
3930 }
3931
3932 void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
3933 {
3934         struct drm_i915_private *dev_priv = dev->dev_private;
3935         struct intel_encoder *encoder;
3936         struct intel_dp *intel_dp = NULL;
3937         struct intel_crtc_config *config = NULL;
3938         struct intel_crtc *intel_crtc = NULL;
3939         struct intel_connector *intel_connector = dev_priv->drrs.connector;
3940         u32 reg, val;
3941         enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
3942
3943         if (refresh_rate <= 0) {
3944                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
3945                 return;
3946         }
3947
3948         if (intel_connector == NULL) {
3949                 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
3950                 return;
3951         }
3952
3953         if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
3954                 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
3955                 return;
3956         }
3957
3958         encoder = intel_attached_encoder(&intel_connector->base);
3959         intel_dp = enc_to_intel_dp(&encoder->base);
3960         intel_crtc = encoder->new_crtc;
3961
3962         if (!intel_crtc) {
3963                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
3964                 return;
3965         }
3966
3967         config = &intel_crtc->config;
3968
3969         if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
3970                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
3971                 return;
3972         }
3973
3974         if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
3975                 index = DRRS_LOW_RR;
3976
3977         if (index == intel_dp->drrs_state.refresh_rate_type) {
3978                 DRM_DEBUG_KMS(
3979                         "DRRS requested for previously set RR...ignoring\n");
3980                 return;
3981         }
3982
3983         if (!intel_crtc->active) {
3984                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
3985                 return;
3986         }
3987
3988         if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
3989                 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
3990                 val = I915_READ(reg);
3991                 if (index > DRRS_HIGH_RR) {
3992                         val |= PIPECONF_EDP_RR_MODE_SWITCH;
3993                         intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2);
3994                 } else {
3995                         val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
3996                 }
3997                 I915_WRITE(reg, val);
3998         }
3999
4000         /*
4001          * mutex taken to ensure that there is no race between differnt
4002          * drrs calls trying to update refresh rate. This scenario may occur
4003          * in future when idleness detection based DRRS in kernel and
4004          * possible calls from user space to set differnt RR are made.
4005          */
4006
4007         mutex_lock(&intel_dp->drrs_state.mutex);
4008
4009         intel_dp->drrs_state.refresh_rate_type = index;
4010
4011         mutex_unlock(&intel_dp->drrs_state.mutex);
4012
4013         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4014 }
4015
4016 static struct drm_display_mode *
4017 intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4018                         struct intel_connector *intel_connector,
4019                         struct drm_display_mode *fixed_mode)
4020 {
4021         struct drm_connector *connector = &intel_connector->base;
4022         struct intel_dp *intel_dp = &intel_dig_port->dp;
4023         struct drm_device *dev = intel_dig_port->base.base.dev;
4024         struct drm_i915_private *dev_priv = dev->dev_private;
4025         struct drm_display_mode *downclock_mode = NULL;
4026
4027         if (INTEL_INFO(dev)->gen <= 6) {
4028                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4029                 return NULL;
4030         }
4031
4032         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4033                 DRM_INFO("VBT doesn't support DRRS\n");
4034                 return NULL;
4035         }
4036
4037         downclock_mode = intel_find_panel_downclock
4038                                         (dev, fixed_mode, connector);
4039
4040         if (!downclock_mode) {
4041                 DRM_INFO("DRRS not supported\n");
4042                 return NULL;
4043         }
4044
4045         dev_priv->drrs.connector = intel_connector;
4046
4047         mutex_init(&intel_dp->drrs_state.mutex);
4048
4049         intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4050
4051         intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4052         DRM_INFO("seamless DRRS supported for eDP panel.\n");
4053         return downclock_mode;
4054 }
4055
4056 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
4057                                      struct intel_connector *intel_connector,
4058                                      struct edp_power_seq *power_seq)
4059 {
4060         struct drm_connector *connector = &intel_connector->base;
4061         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4062         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4063         struct drm_device *dev = intel_encoder->base.dev;
4064         struct drm_i915_private *dev_priv = dev->dev_private;
4065         struct drm_display_mode *fixed_mode = NULL;
4066         struct drm_display_mode *downclock_mode = NULL;
4067         bool has_dpcd;
4068         struct drm_display_mode *scan;
4069         struct edid *edid;
4070
4071         intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
4072
4073         if (!is_edp(intel_dp))
4074                 return true;
4075
4076         /* The VDD bit needs a power domain reference, so if the bit is already
4077          * enabled when we boot, grab this reference. */
4078         if (edp_have_panel_vdd(intel_dp)) {
4079                 enum intel_display_power_domain power_domain;
4080                 power_domain = intel_display_port_power_domain(intel_encoder);
4081                 intel_display_power_get(dev_priv, power_domain);
4082         }
4083
4084         /* Cache DPCD and EDID for edp. */
4085         intel_edp_panel_vdd_on(intel_dp);
4086         has_dpcd = intel_dp_get_dpcd(intel_dp);
4087         edp_panel_vdd_off(intel_dp, false);
4088
4089         if (has_dpcd) {
4090                 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4091                         dev_priv->no_aux_handshake =
4092                                 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4093                                 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4094         } else {
4095                 /* if this fails, presume the device is a ghost */
4096                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
4097                 return false;
4098         }
4099
4100         /* We now know it's not a ghost, init power sequence regs. */
4101         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
4102
4103         mutex_lock(&dev->mode_config.mutex);
4104         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
4105         if (edid) {
4106                 if (drm_add_edid_modes(connector, edid)) {
4107                         drm_mode_connector_update_edid_property(connector,
4108                                                                 edid);
4109                         drm_edid_to_eld(connector, edid);
4110                 } else {
4111                         kfree(edid);
4112                         edid = ERR_PTR(-EINVAL);
4113                 }
4114         } else {
4115                 edid = ERR_PTR(-ENOENT);
4116         }
4117         intel_connector->edid = edid;
4118
4119         /* prefer fixed mode from EDID if available */
4120         list_for_each_entry(scan, &connector->probed_modes, head) {
4121                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
4122                         fixed_mode = drm_mode_duplicate(dev, scan);
4123                         downclock_mode = intel_dp_drrs_init(
4124                                                 intel_dig_port,
4125                                                 intel_connector, fixed_mode);
4126                         break;
4127                 }
4128         }
4129
4130         /* fallback to VBT if available for eDP */
4131         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
4132                 fixed_mode = drm_mode_duplicate(dev,
4133                                         dev_priv->vbt.lfp_lvds_vbt_mode);
4134                 if (fixed_mode)
4135                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
4136         }
4137         mutex_unlock(&dev->mode_config.mutex);
4138
4139         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
4140         intel_panel_setup_backlight(connector);
4141
4142         return true;
4143 }
4144
4145 bool
4146 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
4147                         struct intel_connector *intel_connector)
4148 {
4149         struct drm_connector *connector = &intel_connector->base;
4150         struct intel_dp *intel_dp = &intel_dig_port->dp;
4151         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4152         struct drm_device *dev = intel_encoder->base.dev;
4153         struct drm_i915_private *dev_priv = dev->dev_private;
4154         enum port port = intel_dig_port->port;
4155         struct edp_power_seq power_seq = { 0 };
4156         int type;
4157
4158         /* intel_dp vfuncs */
4159         if (IS_VALLEYVIEW(dev))
4160                 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
4161         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4162                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
4163         else if (HAS_PCH_SPLIT(dev))
4164                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
4165         else
4166                 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
4167
4168         intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
4169
4170         /* Preserve the current hw state. */
4171         intel_dp->DP = I915_READ(intel_dp->output_reg);
4172         intel_dp->attached_connector = intel_connector;
4173
4174         if (intel_dp_is_edp(dev, port))
4175                 type = DRM_MODE_CONNECTOR_eDP;
4176         else
4177                 type = DRM_MODE_CONNECTOR_DisplayPort;
4178
4179         /*
4180          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
4181          * for DP the encoder type can be set by the caller to
4182          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
4183          */
4184         if (type == DRM_MODE_CONNECTOR_eDP)
4185                 intel_encoder->type = INTEL_OUTPUT_EDP;
4186
4187         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
4188                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
4189                         port_name(port));
4190
4191         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
4192         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
4193
4194         connector->interlace_allowed = true;
4195         connector->doublescan_allowed = 0;
4196
4197         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4198                           edp_panel_vdd_work);
4199
4200         intel_connector_attach_encoder(intel_connector, intel_encoder);
4201         drm_sysfs_connector_add(connector);
4202
4203         if (HAS_DDI(dev))
4204                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
4205         else
4206                 intel_connector->get_hw_state = intel_connector_get_hw_state;
4207         intel_connector->unregister = intel_dp_connector_unregister;
4208
4209         /* Set up the hotplug pin. */
4210         switch (port) {
4211         case PORT_A:
4212                 intel_encoder->hpd_pin = HPD_PORT_A;
4213                 break;
4214         case PORT_B:
4215                 intel_encoder->hpd_pin = HPD_PORT_B;
4216                 break;
4217         case PORT_C:
4218                 intel_encoder->hpd_pin = HPD_PORT_C;
4219                 break;
4220         case PORT_D:
4221                 intel_encoder->hpd_pin = HPD_PORT_D;
4222                 break;
4223         default:
4224                 BUG();
4225         }
4226
4227         if (is_edp(intel_dp)) {
4228                 intel_dp_init_panel_power_timestamps(intel_dp);
4229                 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
4230         }
4231
4232         intel_dp_aux_init(intel_dp, intel_connector);
4233
4234         intel_dp->psr_setup_done = false;
4235
4236         if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
4237                 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
4238                 if (is_edp(intel_dp)) {
4239                         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4240                         mutex_lock(&dev->mode_config.mutex);
4241                         edp_panel_vdd_off_sync(intel_dp);
4242                         mutex_unlock(&dev->mode_config.mutex);
4243                 }
4244                 drm_sysfs_connector_remove(connector);
4245                 drm_connector_cleanup(connector);
4246                 return false;
4247         }
4248
4249         intel_dp_add_properties(intel_dp, connector);
4250
4251         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
4252          * 0xd.  Failure to do so will result in spurious interrupts being
4253          * generated on the port when a cable is not attached.
4254          */
4255         if (IS_G4X(dev) && !IS_GM45(dev)) {
4256                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
4257                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
4258         }
4259
4260         return true;
4261 }
4262
4263 void
4264 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
4265 {
4266         struct intel_digital_port *intel_dig_port;
4267         struct intel_encoder *intel_encoder;
4268         struct drm_encoder *encoder;
4269         struct intel_connector *intel_connector;
4270
4271         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
4272         if (!intel_dig_port)
4273                 return;
4274
4275         intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
4276         if (!intel_connector) {
4277                 kfree(intel_dig_port);
4278                 return;
4279         }
4280
4281         intel_encoder = &intel_dig_port->base;
4282         encoder = &intel_encoder->base;
4283
4284         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
4285                          DRM_MODE_ENCODER_TMDS);
4286
4287         intel_encoder->compute_config = intel_dp_compute_config;
4288         intel_encoder->disable = intel_disable_dp;
4289         intel_encoder->get_hw_state = intel_dp_get_hw_state;
4290         intel_encoder->get_config = intel_dp_get_config;
4291         if (IS_CHERRYVIEW(dev)) {
4292                 intel_encoder->pre_enable = chv_pre_enable_dp;
4293                 intel_encoder->enable = vlv_enable_dp;
4294                 intel_encoder->post_disable = chv_post_disable_dp;
4295         } else if (IS_VALLEYVIEW(dev)) {
4296                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
4297                 intel_encoder->pre_enable = vlv_pre_enable_dp;
4298                 intel_encoder->enable = vlv_enable_dp;
4299                 intel_encoder->post_disable = vlv_post_disable_dp;
4300         } else {
4301                 intel_encoder->pre_enable = g4x_pre_enable_dp;
4302                 intel_encoder->enable = g4x_enable_dp;
4303                 intel_encoder->post_disable = g4x_post_disable_dp;
4304         }
4305
4306         intel_dig_port->port = port;
4307         intel_dig_port->dp.output_reg = output_reg;
4308
4309         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4310         if (IS_CHERRYVIEW(dev)) {
4311                 if (port == PORT_D)
4312                         intel_encoder->crtc_mask = 1 << 2;
4313                 else
4314                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
4315         } else {
4316                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
4317         }
4318         intel_encoder->cloneable = 0;
4319         intel_encoder->hot_plug = intel_dp_hot_plug;
4320
4321         if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
4322                 drm_encoder_cleanup(encoder);
4323                 kfree(intel_dig_port);
4324                 kfree(intel_connector);
4325         }
4326 }