2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/notifier.h>
32 #include <linux/reboot.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_crtc_helper.h>
36 #include <drm/drm_edid.h>
37 #include "intel_drv.h"
38 #include <drm/i915_drm.h>
41 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
48 static const struct dp_link_dpll gen4_dpll[] = {
50 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
52 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
55 static const struct dp_link_dpll pch_dpll[] = {
57 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
59 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
62 static const struct dp_link_dpll vlv_dpll[] = {
64 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
66 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
73 static const struct dp_link_dpll chv_dpll[] = {
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
79 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
81 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
83 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
84 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
94 static bool is_edp(struct intel_dp *intel_dp)
96 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
98 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
101 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
103 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
105 return intel_dig_port->base.base.dev;
108 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
110 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
113 static void intel_dp_link_down(struct intel_dp *intel_dp);
114 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
115 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
118 intel_dp_max_link_bw(struct intel_dp *intel_dp)
120 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
121 struct drm_device *dev = intel_dp->attached_connector->base.dev;
123 switch (max_link_bw) {
124 case DP_LINK_BW_1_62:
127 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
128 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
129 INTEL_INFO(dev)->gen >= 8) &&
130 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
131 max_link_bw = DP_LINK_BW_5_4;
133 max_link_bw = DP_LINK_BW_2_7;
136 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
138 max_link_bw = DP_LINK_BW_1_62;
144 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
146 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
147 struct drm_device *dev = intel_dig_port->base.base.dev;
148 u8 source_max, sink_max;
151 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
152 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
155 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
157 return min(source_max, sink_max);
161 * The units on the numbers in the next two are... bizarre. Examples will
162 * make it clearer; this one parallels an example in the eDP spec.
164 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
166 * 270000 * 1 * 8 / 10 == 216000
168 * The actual data capacity of that configuration is 2.16Gbit/s, so the
169 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
170 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
171 * 119000. At 18bpp that's 2142000 kilobits per second.
173 * Thus the strange-looking division by 10 in intel_dp_link_required, to
174 * get the result in decakilobits instead of kilobits.
178 intel_dp_link_required(int pixel_clock, int bpp)
180 return (pixel_clock * bpp + 9) / 10;
184 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
186 return (max_link_clock * max_lanes * 8) / 10;
189 static enum drm_mode_status
190 intel_dp_mode_valid(struct drm_connector *connector,
191 struct drm_display_mode *mode)
193 struct intel_dp *intel_dp = intel_attached_dp(connector);
194 struct intel_connector *intel_connector = to_intel_connector(connector);
195 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
196 int target_clock = mode->clock;
197 int max_rate, mode_rate, max_lanes, max_link_clock;
199 if (is_edp(intel_dp) && fixed_mode) {
200 if (mode->hdisplay > fixed_mode->hdisplay)
203 if (mode->vdisplay > fixed_mode->vdisplay)
206 target_clock = fixed_mode->clock;
209 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
210 max_lanes = intel_dp_max_lane_count(intel_dp);
212 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
213 mode_rate = intel_dp_link_required(target_clock, 18);
215 if (mode_rate > max_rate)
216 return MODE_CLOCK_HIGH;
218 if (mode->clock < 10000)
219 return MODE_CLOCK_LOW;
221 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
222 return MODE_H_ILLEGAL;
228 pack_aux(uint8_t *src, int src_bytes)
235 for (i = 0; i < src_bytes; i++)
236 v |= ((uint32_t) src[i]) << ((3-i) * 8);
241 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
246 for (i = 0; i < dst_bytes; i++)
247 dst[i] = src >> ((3-i) * 8);
250 /* hrawclock is 1/4 the FSB frequency */
252 intel_hrawclk(struct drm_device *dev)
254 struct drm_i915_private *dev_priv = dev->dev_private;
257 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
258 if (IS_VALLEYVIEW(dev))
261 clkcfg = I915_READ(CLKCFG);
262 switch (clkcfg & CLKCFG_FSB_MASK) {
271 case CLKCFG_FSB_1067:
273 case CLKCFG_FSB_1333:
275 /* these two are just a guess; one of them might be right */
276 case CLKCFG_FSB_1600:
277 case CLKCFG_FSB_1600_ALT:
285 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
286 struct intel_dp *intel_dp,
287 struct edp_power_seq *out);
289 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
290 struct intel_dp *intel_dp,
291 struct edp_power_seq *out);
293 static void pps_lock(struct intel_dp *intel_dp)
295 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
296 struct intel_encoder *encoder = &intel_dig_port->base;
297 struct drm_device *dev = encoder->base.dev;
298 struct drm_i915_private *dev_priv = dev->dev_private;
299 enum intel_display_power_domain power_domain;
302 * See vlv_power_sequencer_reset() why we need
303 * a power domain reference here.
305 power_domain = intel_display_port_power_domain(encoder);
306 intel_display_power_get(dev_priv, power_domain);
308 mutex_lock(&dev_priv->pps_mutex);
311 static void pps_unlock(struct intel_dp *intel_dp)
313 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
314 struct intel_encoder *encoder = &intel_dig_port->base;
315 struct drm_device *dev = encoder->base.dev;
316 struct drm_i915_private *dev_priv = dev->dev_private;
317 enum intel_display_power_domain power_domain;
319 mutex_unlock(&dev_priv->pps_mutex);
321 power_domain = intel_display_port_power_domain(encoder);
322 intel_display_power_put(dev_priv, power_domain);
326 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
328 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
329 struct drm_device *dev = intel_dig_port->base.base.dev;
330 struct drm_i915_private *dev_priv = dev->dev_private;
331 struct intel_encoder *encoder;
332 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
333 struct edp_power_seq power_seq;
335 lockdep_assert_held(&dev_priv->pps_mutex);
337 if (intel_dp->pps_pipe != INVALID_PIPE)
338 return intel_dp->pps_pipe;
341 * We don't have power sequencer currently.
342 * Pick one that's not used by other ports.
344 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
346 struct intel_dp *tmp;
348 if (encoder->type != INTEL_OUTPUT_EDP)
351 tmp = enc_to_intel_dp(&encoder->base);
353 if (tmp->pps_pipe != INVALID_PIPE)
354 pipes &= ~(1 << tmp->pps_pipe);
358 * Didn't find one. This should not happen since there
359 * are two power sequencers and up to two eDP ports.
361 if (WARN_ON(pipes == 0))
364 intel_dp->pps_pipe = ffs(pipes) - 1;
366 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
367 pipe_name(intel_dp->pps_pipe),
368 port_name(intel_dig_port->port));
370 /* init power sequencer on this pipe and port */
371 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
372 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
375 return intel_dp->pps_pipe;
378 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
381 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
384 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
387 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
390 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
393 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
400 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
402 vlv_pipe_check pipe_check)
406 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
407 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
408 PANEL_PORT_SELECT_MASK;
410 if (port_sel != PANEL_PORT_SELECT_VLV(port))
413 if (!pipe_check(dev_priv, pipe))
423 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
425 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
426 struct drm_device *dev = intel_dig_port->base.base.dev;
427 struct drm_i915_private *dev_priv = dev->dev_private;
428 struct edp_power_seq power_seq;
429 enum port port = intel_dig_port->port;
431 lockdep_assert_held(&dev_priv->pps_mutex);
433 /* try to find a pipe with this port selected */
434 /* first pick one where the panel is on */
435 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
437 /* didn't find one? pick one where vdd is on */
438 if (intel_dp->pps_pipe == INVALID_PIPE)
439 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
440 vlv_pipe_has_vdd_on);
441 /* didn't find one? pick one with just the correct port */
442 if (intel_dp->pps_pipe == INVALID_PIPE)
443 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
446 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
447 if (intel_dp->pps_pipe == INVALID_PIPE) {
448 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
453 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
454 port_name(port), pipe_name(intel_dp->pps_pipe));
456 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
457 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
461 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
463 struct drm_device *dev = dev_priv->dev;
464 struct intel_encoder *encoder;
466 if (WARN_ON(!IS_VALLEYVIEW(dev)))
470 * We can't grab pps_mutex here due to deadlock with power_domain
471 * mutex when power_domain functions are called while holding pps_mutex.
472 * That also means that in order to use pps_pipe the code needs to
473 * hold both a power domain reference and pps_mutex, and the power domain
474 * reference get/put must be done while _not_ holding pps_mutex.
475 * pps_{lock,unlock}() do these steps in the correct order, so one
476 * should use them always.
479 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
480 struct intel_dp *intel_dp;
482 if (encoder->type != INTEL_OUTPUT_EDP)
485 intel_dp = enc_to_intel_dp(&encoder->base);
486 intel_dp->pps_pipe = INVALID_PIPE;
490 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
492 struct drm_device *dev = intel_dp_to_dev(intel_dp);
494 if (HAS_PCH_SPLIT(dev))
495 return PCH_PP_CONTROL;
497 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
500 static u32 _pp_stat_reg(struct intel_dp *intel_dp)
502 struct drm_device *dev = intel_dp_to_dev(intel_dp);
504 if (HAS_PCH_SPLIT(dev))
505 return PCH_PP_STATUS;
507 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
510 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
511 This function only applicable when panel PM state is not to be tracked */
512 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
515 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
517 struct drm_device *dev = intel_dp_to_dev(intel_dp);
518 struct drm_i915_private *dev_priv = dev->dev_private;
520 u32 pp_ctrl_reg, pp_div_reg;
522 if (!is_edp(intel_dp) || code != SYS_RESTART)
527 if (IS_VALLEYVIEW(dev)) {
528 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
530 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
531 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
532 pp_div = I915_READ(pp_div_reg);
533 pp_div &= PP_REFERENCE_DIVIDER_MASK;
535 /* 0x1F write to PP_DIV_REG sets max cycle delay */
536 I915_WRITE(pp_div_reg, pp_div | 0x1F);
537 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
538 msleep(intel_dp->panel_power_cycle_delay);
541 pps_unlock(intel_dp);
546 static bool edp_have_panel_power(struct intel_dp *intel_dp)
548 struct drm_device *dev = intel_dp_to_dev(intel_dp);
549 struct drm_i915_private *dev_priv = dev->dev_private;
551 lockdep_assert_held(&dev_priv->pps_mutex);
553 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
556 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
558 struct drm_device *dev = intel_dp_to_dev(intel_dp);
559 struct drm_i915_private *dev_priv = dev->dev_private;
561 lockdep_assert_held(&dev_priv->pps_mutex);
563 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
567 intel_dp_check_edp(struct intel_dp *intel_dp)
569 struct drm_device *dev = intel_dp_to_dev(intel_dp);
570 struct drm_i915_private *dev_priv = dev->dev_private;
572 if (!is_edp(intel_dp))
575 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
576 WARN(1, "eDP powered off while attempting aux channel communication.\n");
577 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
578 I915_READ(_pp_stat_reg(intel_dp)),
579 I915_READ(_pp_ctrl_reg(intel_dp)));
584 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
586 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
587 struct drm_device *dev = intel_dig_port->base.base.dev;
588 struct drm_i915_private *dev_priv = dev->dev_private;
589 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
593 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
595 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
596 msecs_to_jiffies_timeout(10));
598 done = wait_for_atomic(C, 10) == 0;
600 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
607 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
609 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
610 struct drm_device *dev = intel_dig_port->base.base.dev;
613 * The clock divider is based off the hrawclk, and would like to run at
614 * 2MHz. So, take the hrawclk value and divide by 2 and use that
616 return index ? 0 : intel_hrawclk(dev) / 2;
619 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
621 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
622 struct drm_device *dev = intel_dig_port->base.base.dev;
627 if (intel_dig_port->port == PORT_A) {
628 if (IS_GEN6(dev) || IS_GEN7(dev))
629 return 200; /* SNB & IVB eDP input clock at 400Mhz */
631 return 225; /* eDP input clock at 450Mhz */
633 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
637 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
639 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
640 struct drm_device *dev = intel_dig_port->base.base.dev;
641 struct drm_i915_private *dev_priv = dev->dev_private;
643 if (intel_dig_port->port == PORT_A) {
646 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
647 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
648 /* Workaround for non-ULT HSW */
655 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
659 static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
661 return index ? 0 : 100;
664 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
667 uint32_t aux_clock_divider)
669 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
670 struct drm_device *dev = intel_dig_port->base.base.dev;
671 uint32_t precharge, timeout;
678 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
679 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
681 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
683 return DP_AUX_CH_CTL_SEND_BUSY |
685 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
686 DP_AUX_CH_CTL_TIME_OUT_ERROR |
688 DP_AUX_CH_CTL_RECEIVE_ERROR |
689 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
690 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
691 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
695 intel_dp_aux_ch(struct intel_dp *intel_dp,
696 uint8_t *send, int send_bytes,
697 uint8_t *recv, int recv_size)
699 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
700 struct drm_device *dev = intel_dig_port->base.base.dev;
701 struct drm_i915_private *dev_priv = dev->dev_private;
702 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
703 uint32_t ch_data = ch_ctl + 4;
704 uint32_t aux_clock_divider;
705 int i, ret, recv_bytes;
708 bool has_aux_irq = HAS_AUX_IRQ(dev);
714 * We will be called with VDD already enabled for dpcd/edid/oui reads.
715 * In such cases we want to leave VDD enabled and it's up to upper layers
716 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
719 vdd = edp_panel_vdd_on(intel_dp);
721 /* dp aux is extremely sensitive to irq latency, hence request the
722 * lowest possible wakeup latency and so prevent the cpu from going into
725 pm_qos_update_request(&dev_priv->pm_qos, 0);
727 intel_dp_check_edp(intel_dp);
729 intel_aux_display_runtime_get(dev_priv);
731 /* Try to wait for any previous AUX channel activity */
732 for (try = 0; try < 3; try++) {
733 status = I915_READ_NOTRACE(ch_ctl);
734 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
740 WARN(1, "dp_aux_ch not started status 0x%08x\n",
746 /* Only 5 data registers! */
747 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
752 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
753 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
758 /* Must try at least 3 times according to DP spec */
759 for (try = 0; try < 5; try++) {
760 /* Load the send data into the aux channel data registers */
761 for (i = 0; i < send_bytes; i += 4)
762 I915_WRITE(ch_data + i,
763 pack_aux(send + i, send_bytes - i));
765 /* Send the command and wait for it to complete */
766 I915_WRITE(ch_ctl, send_ctl);
768 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
770 /* Clear done status and any errors */
774 DP_AUX_CH_CTL_TIME_OUT_ERROR |
775 DP_AUX_CH_CTL_RECEIVE_ERROR);
777 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
778 DP_AUX_CH_CTL_RECEIVE_ERROR))
780 if (status & DP_AUX_CH_CTL_DONE)
783 if (status & DP_AUX_CH_CTL_DONE)
787 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
788 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
793 /* Check for timeout or receive error.
794 * Timeouts occur when the sink is not connected
796 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
797 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
802 /* Timeouts occur when the device isn't connected, so they're
803 * "normal" -- don't fill the kernel log with these */
804 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
805 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
810 /* Unload any bytes sent back from the other side */
811 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
812 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
813 if (recv_bytes > recv_size)
814 recv_bytes = recv_size;
816 for (i = 0; i < recv_bytes; i += 4)
817 unpack_aux(I915_READ(ch_data + i),
818 recv + i, recv_bytes - i);
822 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
823 intel_aux_display_runtime_put(dev_priv);
826 edp_panel_vdd_off(intel_dp, false);
828 pps_unlock(intel_dp);
833 #define BARE_ADDRESS_SIZE 3
834 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
836 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
838 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
839 uint8_t txbuf[20], rxbuf[20];
840 size_t txsize, rxsize;
843 txbuf[0] = msg->request << 4;
844 txbuf[1] = msg->address >> 8;
845 txbuf[2] = msg->address & 0xff;
846 txbuf[3] = msg->size - 1;
848 switch (msg->request & ~DP_AUX_I2C_MOT) {
849 case DP_AUX_NATIVE_WRITE:
850 case DP_AUX_I2C_WRITE:
851 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
854 if (WARN_ON(txsize > 20))
857 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
859 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
861 msg->reply = rxbuf[0] >> 4;
863 /* Return payload size. */
868 case DP_AUX_NATIVE_READ:
869 case DP_AUX_I2C_READ:
870 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
871 rxsize = msg->size + 1;
873 if (WARN_ON(rxsize > 20))
876 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
878 msg->reply = rxbuf[0] >> 4;
880 * Assume happy day, and copy the data. The caller is
881 * expected to check msg->reply before touching it.
883 * Return payload size.
886 memcpy(msg->buffer, rxbuf + 1, ret);
899 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
901 struct drm_device *dev = intel_dp_to_dev(intel_dp);
902 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
903 enum port port = intel_dig_port->port;
904 const char *name = NULL;
909 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
913 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
917 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
921 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
929 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
931 intel_dp->aux.name = name;
932 intel_dp->aux.dev = dev->dev;
933 intel_dp->aux.transfer = intel_dp_aux_transfer;
935 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
936 connector->base.kdev->kobj.name);
938 ret = drm_dp_aux_register(&intel_dp->aux);
940 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
945 ret = sysfs_create_link(&connector->base.kdev->kobj,
946 &intel_dp->aux.ddc.dev.kobj,
947 intel_dp->aux.ddc.dev.kobj.name);
949 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
950 drm_dp_aux_unregister(&intel_dp->aux);
955 intel_dp_connector_unregister(struct intel_connector *intel_connector)
957 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
959 if (!intel_connector->mst_port)
960 sysfs_remove_link(&intel_connector->base.kdev->kobj,
961 intel_dp->aux.ddc.dev.kobj.name);
962 intel_connector_unregister(intel_connector);
966 hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
969 case DP_LINK_BW_1_62:
970 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
973 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
976 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
982 intel_dp_set_clock(struct intel_encoder *encoder,
983 struct intel_crtc_config *pipe_config, int link_bw)
985 struct drm_device *dev = encoder->base.dev;
986 const struct dp_link_dpll *divisor = NULL;
991 count = ARRAY_SIZE(gen4_dpll);
992 } else if (HAS_PCH_SPLIT(dev)) {
994 count = ARRAY_SIZE(pch_dpll);
995 } else if (IS_CHERRYVIEW(dev)) {
997 count = ARRAY_SIZE(chv_dpll);
998 } else if (IS_VALLEYVIEW(dev)) {
1000 count = ARRAY_SIZE(vlv_dpll);
1003 if (divisor && count) {
1004 for (i = 0; i < count; i++) {
1005 if (link_bw == divisor[i].link_bw) {
1006 pipe_config->dpll = divisor[i].dpll;
1007 pipe_config->clock_set = true;
1015 intel_dp_compute_config(struct intel_encoder *encoder,
1016 struct intel_crtc_config *pipe_config)
1018 struct drm_device *dev = encoder->base.dev;
1019 struct drm_i915_private *dev_priv = dev->dev_private;
1020 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
1021 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1022 enum port port = dp_to_dig_port(intel_dp)->port;
1023 struct intel_crtc *intel_crtc = encoder->new_crtc;
1024 struct intel_connector *intel_connector = intel_dp->attached_connector;
1025 int lane_count, clock;
1026 int min_lane_count = 1;
1027 int max_lane_count = intel_dp_max_lane_count(intel_dp);
1028 /* Conveniently, the link BW constants become indices with a shift...*/
1030 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
1032 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
1033 int link_avail, link_clock;
1035 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
1036 pipe_config->has_pch_encoder = true;
1038 pipe_config->has_dp_encoder = true;
1039 pipe_config->has_drrs = false;
1040 pipe_config->has_audio = intel_dp->has_audio;
1042 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1043 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1045 if (!HAS_PCH_SPLIT(dev))
1046 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1047 intel_connector->panel.fitting_mode);
1049 intel_pch_panel_fitting(intel_crtc, pipe_config,
1050 intel_connector->panel.fitting_mode);
1053 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1056 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1057 "max bw %02x pixel clock %iKHz\n",
1058 max_lane_count, bws[max_clock],
1059 adjusted_mode->crtc_clock);
1061 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1062 * bpc in between. */
1063 bpp = pipe_config->pipe_bpp;
1064 if (is_edp(intel_dp)) {
1065 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
1066 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1067 dev_priv->vbt.edp_bpp);
1068 bpp = dev_priv->vbt.edp_bpp;
1072 * Use the maximum clock and number of lanes the eDP panel
1073 * advertizes being capable of. The panels are generally
1074 * designed to support only a single clock and lane
1075 * configuration, and typically these values correspond to the
1076 * native resolution of the panel.
1078 min_lane_count = max_lane_count;
1079 min_clock = max_clock;
1082 for (; bpp >= 6*3; bpp -= 2*3) {
1083 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1086 for (clock = min_clock; clock <= max_clock; clock++) {
1087 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
1088 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
1089 link_avail = intel_dp_max_data_rate(link_clock,
1092 if (mode_rate <= link_avail) {
1102 if (intel_dp->color_range_auto) {
1105 * CEA-861-E - 5.1 Default Encoding Parameters
1106 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1108 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
1109 intel_dp->color_range = DP_COLOR_RANGE_16_235;
1111 intel_dp->color_range = 0;
1114 if (intel_dp->color_range)
1115 pipe_config->limited_color_range = true;
1117 intel_dp->link_bw = bws[clock];
1118 intel_dp->lane_count = lane_count;
1119 pipe_config->pipe_bpp = bpp;
1120 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
1122 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1123 intel_dp->link_bw, intel_dp->lane_count,
1124 pipe_config->port_clock, bpp);
1125 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1126 mode_rate, link_avail);
1128 intel_link_compute_m_n(bpp, lane_count,
1129 adjusted_mode->crtc_clock,
1130 pipe_config->port_clock,
1131 &pipe_config->dp_m_n);
1133 if (intel_connector->panel.downclock_mode != NULL &&
1134 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
1135 pipe_config->has_drrs = true;
1136 intel_link_compute_m_n(bpp, lane_count,
1137 intel_connector->panel.downclock_mode->clock,
1138 pipe_config->port_clock,
1139 &pipe_config->dp_m2_n2);
1142 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1143 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
1145 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
1150 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
1152 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1153 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1154 struct drm_device *dev = crtc->base.dev;
1155 struct drm_i915_private *dev_priv = dev->dev_private;
1158 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
1159 dpa_ctl = I915_READ(DP_A);
1160 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1162 if (crtc->config.port_clock == 162000) {
1163 /* For a long time we've carried around a ILK-DevA w/a for the
1164 * 160MHz clock. If we're really unlucky, it's still required.
1166 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
1167 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1168 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
1170 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1171 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
1174 I915_WRITE(DP_A, dpa_ctl);
1180 static void intel_dp_prepare(struct intel_encoder *encoder)
1182 struct drm_device *dev = encoder->base.dev;
1183 struct drm_i915_private *dev_priv = dev->dev_private;
1184 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1185 enum port port = dp_to_dig_port(intel_dp)->port;
1186 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1187 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
1190 * There are four kinds of DP registers:
1197 * IBX PCH and CPU are the same for almost everything,
1198 * except that the CPU DP PLL is configured in this
1201 * CPT PCH is quite different, having many bits moved
1202 * to the TRANS_DP_CTL register instead. That
1203 * configuration happens (oddly) in ironlake_pch_enable
1206 /* Preserve the BIOS-computed detected bit. This is
1207 * supposed to be read-only.
1209 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1211 /* Handle DP bits in common between all three register formats */
1212 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1213 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
1215 if (crtc->config.has_audio) {
1216 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
1217 pipe_name(crtc->pipe));
1218 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
1219 intel_write_eld(&encoder->base, adjusted_mode);
1222 /* Split out the IBX/CPU vs CPT settings */
1224 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1225 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1226 intel_dp->DP |= DP_SYNC_HS_HIGH;
1227 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1228 intel_dp->DP |= DP_SYNC_VS_HIGH;
1229 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1231 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1232 intel_dp->DP |= DP_ENHANCED_FRAMING;
1234 intel_dp->DP |= crtc->pipe << 29;
1235 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1236 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
1237 intel_dp->DP |= intel_dp->color_range;
1239 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1240 intel_dp->DP |= DP_SYNC_HS_HIGH;
1241 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1242 intel_dp->DP |= DP_SYNC_VS_HIGH;
1243 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1245 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1246 intel_dp->DP |= DP_ENHANCED_FRAMING;
1248 if (!IS_CHERRYVIEW(dev)) {
1249 if (crtc->pipe == 1)
1250 intel_dp->DP |= DP_PIPEB_SELECT;
1252 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1255 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1259 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1260 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1262 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1263 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1265 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1266 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1268 static void wait_panel_status(struct intel_dp *intel_dp,
1272 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1273 struct drm_i915_private *dev_priv = dev->dev_private;
1274 u32 pp_stat_reg, pp_ctrl_reg;
1276 lockdep_assert_held(&dev_priv->pps_mutex);
1278 pp_stat_reg = _pp_stat_reg(intel_dp);
1279 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1281 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1283 I915_READ(pp_stat_reg),
1284 I915_READ(pp_ctrl_reg));
1286 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1287 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1288 I915_READ(pp_stat_reg),
1289 I915_READ(pp_ctrl_reg));
1292 DRM_DEBUG_KMS("Wait complete\n");
1295 static void wait_panel_on(struct intel_dp *intel_dp)
1297 DRM_DEBUG_KMS("Wait for panel power on\n");
1298 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1301 static void wait_panel_off(struct intel_dp *intel_dp)
1303 DRM_DEBUG_KMS("Wait for panel power off time\n");
1304 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1307 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1309 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1311 /* When we disable the VDD override bit last we have to do the manual
1313 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1314 intel_dp->panel_power_cycle_delay);
1316 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1319 static void wait_backlight_on(struct intel_dp *intel_dp)
1321 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1322 intel_dp->backlight_on_delay);
1325 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1327 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1328 intel_dp->backlight_off_delay);
1331 /* Read the current pp_control value, unlocking the register if it
1335 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1337 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1338 struct drm_i915_private *dev_priv = dev->dev_private;
1341 lockdep_assert_held(&dev_priv->pps_mutex);
1343 control = I915_READ(_pp_ctrl_reg(intel_dp));
1344 control &= ~PANEL_UNLOCK_MASK;
1345 control |= PANEL_UNLOCK_REGS;
1350 * Must be paired with edp_panel_vdd_off().
1351 * Must hold pps_mutex around the whole on/off sequence.
1352 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1354 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
1356 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1357 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1358 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1359 struct drm_i915_private *dev_priv = dev->dev_private;
1360 enum intel_display_power_domain power_domain;
1362 u32 pp_stat_reg, pp_ctrl_reg;
1363 bool need_to_disable = !intel_dp->want_panel_vdd;
1365 lockdep_assert_held(&dev_priv->pps_mutex);
1367 if (!is_edp(intel_dp))
1370 intel_dp->want_panel_vdd = true;
1372 if (edp_have_panel_vdd(intel_dp))
1373 return need_to_disable;
1375 power_domain = intel_display_port_power_domain(intel_encoder);
1376 intel_display_power_get(dev_priv, power_domain);
1378 DRM_DEBUG_KMS("Turning eDP VDD on\n");
1380 if (!edp_have_panel_power(intel_dp))
1381 wait_panel_power_cycle(intel_dp);
1383 pp = ironlake_get_pp_control(intel_dp);
1384 pp |= EDP_FORCE_VDD;
1386 pp_stat_reg = _pp_stat_reg(intel_dp);
1387 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1389 I915_WRITE(pp_ctrl_reg, pp);
1390 POSTING_READ(pp_ctrl_reg);
1391 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1392 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1394 * If the panel wasn't on, delay before accessing aux channel
1396 if (!edp_have_panel_power(intel_dp)) {
1397 DRM_DEBUG_KMS("eDP was not running\n");
1398 msleep(intel_dp->panel_power_up_delay);
1401 return need_to_disable;
1405 * Must be paired with intel_edp_panel_vdd_off() or
1406 * intel_edp_panel_off().
1407 * Nested calls to these functions are not allowed since
1408 * we drop the lock. Caller must use some higher level
1409 * locking to prevent nested calls from other threads.
1411 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1415 if (!is_edp(intel_dp))
1419 vdd = edp_panel_vdd_on(intel_dp);
1420 pps_unlock(intel_dp);
1422 WARN(!vdd, "eDP VDD already requested on\n");
1425 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1427 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1428 struct drm_i915_private *dev_priv = dev->dev_private;
1429 struct intel_digital_port *intel_dig_port =
1430 dp_to_dig_port(intel_dp);
1431 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1432 enum intel_display_power_domain power_domain;
1434 u32 pp_stat_reg, pp_ctrl_reg;
1436 lockdep_assert_held(&dev_priv->pps_mutex);
1438 WARN_ON(intel_dp->want_panel_vdd);
1440 if (!edp_have_panel_vdd(intel_dp))
1443 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1445 pp = ironlake_get_pp_control(intel_dp);
1446 pp &= ~EDP_FORCE_VDD;
1448 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1449 pp_stat_reg = _pp_stat_reg(intel_dp);
1451 I915_WRITE(pp_ctrl_reg, pp);
1452 POSTING_READ(pp_ctrl_reg);
1454 /* Make sure sequencer is idle before allowing subsequent activity */
1455 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1456 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1458 if ((pp & POWER_TARGET_ON) == 0)
1459 intel_dp->last_power_cycle = jiffies;
1461 power_domain = intel_display_port_power_domain(intel_encoder);
1462 intel_display_power_put(dev_priv, power_domain);
1465 static void edp_panel_vdd_work(struct work_struct *__work)
1467 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1468 struct intel_dp, panel_vdd_work);
1471 if (!intel_dp->want_panel_vdd)
1472 edp_panel_vdd_off_sync(intel_dp);
1473 pps_unlock(intel_dp);
1476 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1478 unsigned long delay;
1481 * Queue the timer to fire a long time from now (relative to the power
1482 * down delay) to keep the panel power up across a sequence of
1485 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1486 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1490 * Must be paired with edp_panel_vdd_on().
1491 * Must hold pps_mutex around the whole on/off sequence.
1492 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1494 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1496 struct drm_i915_private *dev_priv =
1497 intel_dp_to_dev(intel_dp)->dev_private;
1499 lockdep_assert_held(&dev_priv->pps_mutex);
1501 if (!is_edp(intel_dp))
1504 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1506 intel_dp->want_panel_vdd = false;
1509 edp_panel_vdd_off_sync(intel_dp);
1511 edp_panel_vdd_schedule_off(intel_dp);
1515 * Must be paired with intel_edp_panel_vdd_on().
1516 * Nested calls to these functions are not allowed since
1517 * we drop the lock. Caller must use some higher level
1518 * locking to prevent nested calls from other threads.
1520 static void intel_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1522 if (!is_edp(intel_dp))
1526 edp_panel_vdd_off(intel_dp, sync);
1527 pps_unlock(intel_dp);
1530 void intel_edp_panel_on(struct intel_dp *intel_dp)
1532 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1533 struct drm_i915_private *dev_priv = dev->dev_private;
1537 if (!is_edp(intel_dp))
1540 DRM_DEBUG_KMS("Turn eDP power on\n");
1544 if (edp_have_panel_power(intel_dp)) {
1545 DRM_DEBUG_KMS("eDP power already on\n");
1549 wait_panel_power_cycle(intel_dp);
1551 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1552 pp = ironlake_get_pp_control(intel_dp);
1554 /* ILK workaround: disable reset around power sequence */
1555 pp &= ~PANEL_POWER_RESET;
1556 I915_WRITE(pp_ctrl_reg, pp);
1557 POSTING_READ(pp_ctrl_reg);
1560 pp |= POWER_TARGET_ON;
1562 pp |= PANEL_POWER_RESET;
1564 I915_WRITE(pp_ctrl_reg, pp);
1565 POSTING_READ(pp_ctrl_reg);
1567 wait_panel_on(intel_dp);
1568 intel_dp->last_power_on = jiffies;
1571 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1572 I915_WRITE(pp_ctrl_reg, pp);
1573 POSTING_READ(pp_ctrl_reg);
1577 pps_unlock(intel_dp);
1580 void intel_edp_panel_off(struct intel_dp *intel_dp)
1582 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1583 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1584 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1585 struct drm_i915_private *dev_priv = dev->dev_private;
1586 enum intel_display_power_domain power_domain;
1590 if (!is_edp(intel_dp))
1593 DRM_DEBUG_KMS("Turn eDP power off\n");
1597 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1599 pp = ironlake_get_pp_control(intel_dp);
1600 /* We need to switch off panel power _and_ force vdd, for otherwise some
1601 * panels get very unhappy and cease to work. */
1602 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1605 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1607 intel_dp->want_panel_vdd = false;
1609 I915_WRITE(pp_ctrl_reg, pp);
1610 POSTING_READ(pp_ctrl_reg);
1612 intel_dp->last_power_cycle = jiffies;
1613 wait_panel_off(intel_dp);
1615 /* We got a reference when we enabled the VDD. */
1616 power_domain = intel_display_port_power_domain(intel_encoder);
1617 intel_display_power_put(dev_priv, power_domain);
1619 pps_unlock(intel_dp);
1622 /* Enable backlight in the panel power control. */
1623 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
1625 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1626 struct drm_device *dev = intel_dig_port->base.base.dev;
1627 struct drm_i915_private *dev_priv = dev->dev_private;
1632 * If we enable the backlight right away following a panel power
1633 * on, we may see slight flicker as the panel syncs with the eDP
1634 * link. So delay a bit to make sure the image is solid before
1635 * allowing it to appear.
1637 wait_backlight_on(intel_dp);
1641 pp = ironlake_get_pp_control(intel_dp);
1642 pp |= EDP_BLC_ENABLE;
1644 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1646 I915_WRITE(pp_ctrl_reg, pp);
1647 POSTING_READ(pp_ctrl_reg);
1649 pps_unlock(intel_dp);
1652 /* Enable backlight PWM and backlight PP control. */
1653 void intel_edp_backlight_on(struct intel_dp *intel_dp)
1655 if (!is_edp(intel_dp))
1658 DRM_DEBUG_KMS("\n");
1660 intel_panel_enable_backlight(intel_dp->attached_connector);
1661 _intel_edp_backlight_on(intel_dp);
1664 /* Disable backlight in the panel power control. */
1665 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
1667 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1668 struct drm_i915_private *dev_priv = dev->dev_private;
1672 if (!is_edp(intel_dp))
1677 pp = ironlake_get_pp_control(intel_dp);
1678 pp &= ~EDP_BLC_ENABLE;
1680 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1682 I915_WRITE(pp_ctrl_reg, pp);
1683 POSTING_READ(pp_ctrl_reg);
1685 pps_unlock(intel_dp);
1687 intel_dp->last_backlight_off = jiffies;
1688 edp_wait_backlight_off(intel_dp);
1691 /* Disable backlight PP control and backlight PWM. */
1692 void intel_edp_backlight_off(struct intel_dp *intel_dp)
1694 if (!is_edp(intel_dp))
1697 DRM_DEBUG_KMS("\n");
1699 _intel_edp_backlight_off(intel_dp);
1700 intel_panel_disable_backlight(intel_dp->attached_connector);
1704 * Hook for controlling the panel power control backlight through the bl_power
1705 * sysfs attribute. Take care to handle multiple calls.
1707 static void intel_edp_backlight_power(struct intel_connector *connector,
1710 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
1714 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
1715 pps_unlock(intel_dp);
1717 if (is_enabled == enable)
1720 DRM_DEBUG_KMS("panel power control backlight %s\n",
1721 enable ? "enable" : "disable");
1724 _intel_edp_backlight_on(intel_dp);
1726 _intel_edp_backlight_off(intel_dp);
1729 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1731 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1732 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1733 struct drm_device *dev = crtc->dev;
1734 struct drm_i915_private *dev_priv = dev->dev_private;
1737 assert_pipe_disabled(dev_priv,
1738 to_intel_crtc(crtc)->pipe);
1740 DRM_DEBUG_KMS("\n");
1741 dpa_ctl = I915_READ(DP_A);
1742 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1743 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1745 /* We don't adjust intel_dp->DP while tearing down the link, to
1746 * facilitate link retraining (e.g. after hotplug). Hence clear all
1747 * enable bits here to ensure that we don't enable too much. */
1748 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1749 intel_dp->DP |= DP_PLL_ENABLE;
1750 I915_WRITE(DP_A, intel_dp->DP);
1755 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1757 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1758 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1759 struct drm_device *dev = crtc->dev;
1760 struct drm_i915_private *dev_priv = dev->dev_private;
1763 assert_pipe_disabled(dev_priv,
1764 to_intel_crtc(crtc)->pipe);
1766 dpa_ctl = I915_READ(DP_A);
1767 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1768 "dp pll off, should be on\n");
1769 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1771 /* We can't rely on the value tracked for the DP register in
1772 * intel_dp->DP because link_down must not change that (otherwise link
1773 * re-training will fail. */
1774 dpa_ctl &= ~DP_PLL_ENABLE;
1775 I915_WRITE(DP_A, dpa_ctl);
1780 /* If the sink supports it, try to set the power state appropriately */
1781 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1785 /* Should have a valid DPCD by this point */
1786 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1789 if (mode != DRM_MODE_DPMS_ON) {
1790 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1794 * When turning on, we need to retry for 1ms to give the sink
1797 for (i = 0; i < 3; i++) {
1798 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1807 DRM_DEBUG_KMS("failed to %s sink power state\n",
1808 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
1811 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1814 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1815 enum port port = dp_to_dig_port(intel_dp)->port;
1816 struct drm_device *dev = encoder->base.dev;
1817 struct drm_i915_private *dev_priv = dev->dev_private;
1818 enum intel_display_power_domain power_domain;
1821 power_domain = intel_display_port_power_domain(encoder);
1822 if (!intel_display_power_enabled(dev_priv, power_domain))
1825 tmp = I915_READ(intel_dp->output_reg);
1827 if (!(tmp & DP_PORT_EN))
1830 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1831 *pipe = PORT_TO_PIPE_CPT(tmp);
1832 } else if (IS_CHERRYVIEW(dev)) {
1833 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
1834 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1835 *pipe = PORT_TO_PIPE(tmp);
1841 switch (intel_dp->output_reg) {
1843 trans_sel = TRANS_DP_PORT_SEL_B;
1846 trans_sel = TRANS_DP_PORT_SEL_C;
1849 trans_sel = TRANS_DP_PORT_SEL_D;
1855 for_each_pipe(dev_priv, i) {
1856 trans_dp = I915_READ(TRANS_DP_CTL(i));
1857 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1863 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1864 intel_dp->output_reg);
1870 static void intel_dp_get_config(struct intel_encoder *encoder,
1871 struct intel_crtc_config *pipe_config)
1873 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1875 struct drm_device *dev = encoder->base.dev;
1876 struct drm_i915_private *dev_priv = dev->dev_private;
1877 enum port port = dp_to_dig_port(intel_dp)->port;
1878 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1881 tmp = I915_READ(intel_dp->output_reg);
1882 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1883 pipe_config->has_audio = true;
1885 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1886 if (tmp & DP_SYNC_HS_HIGH)
1887 flags |= DRM_MODE_FLAG_PHSYNC;
1889 flags |= DRM_MODE_FLAG_NHSYNC;
1891 if (tmp & DP_SYNC_VS_HIGH)
1892 flags |= DRM_MODE_FLAG_PVSYNC;
1894 flags |= DRM_MODE_FLAG_NVSYNC;
1896 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1897 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1898 flags |= DRM_MODE_FLAG_PHSYNC;
1900 flags |= DRM_MODE_FLAG_NHSYNC;
1902 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1903 flags |= DRM_MODE_FLAG_PVSYNC;
1905 flags |= DRM_MODE_FLAG_NVSYNC;
1908 pipe_config->adjusted_mode.flags |= flags;
1910 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
1911 tmp & DP_COLOR_RANGE_16_235)
1912 pipe_config->limited_color_range = true;
1914 pipe_config->has_dp_encoder = true;
1916 intel_dp_get_m_n(crtc, pipe_config);
1918 if (port == PORT_A) {
1919 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1920 pipe_config->port_clock = 162000;
1922 pipe_config->port_clock = 270000;
1925 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1926 &pipe_config->dp_m_n);
1928 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1929 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1931 pipe_config->adjusted_mode.crtc_clock = dotclock;
1933 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1934 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1936 * This is a big fat ugly hack.
1938 * Some machines in UEFI boot mode provide us a VBT that has 18
1939 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1940 * unknown we fail to light up. Yet the same BIOS boots up with
1941 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1942 * max, not what it tells us to use.
1944 * Note: This will still be broken if the eDP panel is not lit
1945 * up by the BIOS, and thus we can't get the mode at module
1948 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1949 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1950 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1954 static bool is_edp_psr(struct intel_dp *intel_dp)
1956 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
1959 static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1961 struct drm_i915_private *dev_priv = dev->dev_private;
1966 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1969 static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1970 struct edp_vsc_psr *vsc_psr)
1972 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1973 struct drm_device *dev = dig_port->base.base.dev;
1974 struct drm_i915_private *dev_priv = dev->dev_private;
1975 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1976 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1977 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1978 uint32_t *data = (uint32_t *) vsc_psr;
1981 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1982 the video DIP being updated before program video DIP data buffer
1983 registers for DIP being updated. */
1984 I915_WRITE(ctl_reg, 0);
1985 POSTING_READ(ctl_reg);
1987 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1988 if (i < sizeof(struct edp_vsc_psr))
1989 I915_WRITE(data_reg + i, *data++);
1991 I915_WRITE(data_reg + i, 0);
1994 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1995 POSTING_READ(ctl_reg);
1998 static void intel_edp_psr_setup(struct intel_dp *intel_dp)
2000 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2001 struct drm_i915_private *dev_priv = dev->dev_private;
2002 struct edp_vsc_psr psr_vsc;
2004 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
2005 memset(&psr_vsc, 0, sizeof(psr_vsc));
2006 psr_vsc.sdp_header.HB0 = 0;
2007 psr_vsc.sdp_header.HB1 = 0x7;
2008 psr_vsc.sdp_header.HB2 = 0x2;
2009 psr_vsc.sdp_header.HB3 = 0x8;
2010 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
2012 /* Avoid continuous PSR exit by masking memup and hpd */
2013 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
2014 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2017 static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
2019 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2020 struct drm_device *dev = dig_port->base.base.dev;
2021 struct drm_i915_private *dev_priv = dev->dev_private;
2022 uint32_t aux_clock_divider;
2023 int precharge = 0x3;
2024 int msg_size = 5; /* Header(4) + Message(1) */
2025 bool only_standby = false;
2027 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
2029 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
2030 only_standby = true;
2032 /* Enable PSR in sink */
2033 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
2034 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
2035 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2037 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
2038 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2040 /* Setup AUX registers */
2041 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
2042 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
2043 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2044 DP_AUX_CH_CTL_TIME_OUT_400us |
2045 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
2046 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
2047 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
2050 static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
2052 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2053 struct drm_device *dev = dig_port->base.base.dev;
2054 struct drm_i915_private *dev_priv = dev->dev_private;
2055 uint32_t max_sleep_time = 0x1f;
2056 uint32_t idle_frames = 1;
2058 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
2059 bool only_standby = false;
2061 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
2062 only_standby = true;
2064 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
2065 val |= EDP_PSR_LINK_STANDBY;
2066 val |= EDP_PSR_TP2_TP3_TIME_0us;
2067 val |= EDP_PSR_TP1_TIME_0us;
2068 val |= EDP_PSR_SKIP_AUX_EXIT;
2069 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
2071 val |= EDP_PSR_LINK_DISABLE;
2073 I915_WRITE(EDP_PSR_CTL(dev), val |
2074 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2075 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
2076 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
2080 static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
2082 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2083 struct drm_device *dev = dig_port->base.base.dev;
2084 struct drm_i915_private *dev_priv = dev->dev_private;
2085 struct drm_crtc *crtc = dig_port->base.base.crtc;
2086 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2088 lockdep_assert_held(&dev_priv->psr.lock);
2089 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
2090 WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
2092 dev_priv->psr.source_ok = false;
2094 if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
2095 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
2099 if (!i915.enable_psr) {
2100 DRM_DEBUG_KMS("PSR disable by flag\n");
2104 /* Below limitations aren't valid for Broadwell */
2105 if (IS_BROADWELL(dev))
2108 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
2110 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
2114 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
2115 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
2120 dev_priv->psr.source_ok = true;
2124 static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2126 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2127 struct drm_device *dev = intel_dig_port->base.base.dev;
2128 struct drm_i915_private *dev_priv = dev->dev_private;
2130 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2131 WARN_ON(dev_priv->psr.active);
2132 lockdep_assert_held(&dev_priv->psr.lock);
2134 /* Enable PSR on the panel */
2135 intel_edp_psr_enable_sink(intel_dp);
2137 /* Enable PSR on the host */
2138 intel_edp_psr_enable_source(intel_dp);
2140 dev_priv->psr.active = true;
2143 void intel_edp_psr_enable(struct intel_dp *intel_dp)
2145 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2146 struct drm_i915_private *dev_priv = dev->dev_private;
2148 if (!HAS_PSR(dev)) {
2149 DRM_DEBUG_KMS("PSR not supported on this platform\n");
2153 if (!is_edp_psr(intel_dp)) {
2154 DRM_DEBUG_KMS("PSR not supported by this panel\n");
2158 mutex_lock(&dev_priv->psr.lock);
2159 if (dev_priv->psr.enabled) {
2160 DRM_DEBUG_KMS("PSR already in use\n");
2161 mutex_unlock(&dev_priv->psr.lock);
2165 dev_priv->psr.busy_frontbuffer_bits = 0;
2167 /* Setup PSR once */
2168 intel_edp_psr_setup(intel_dp);
2170 if (intel_edp_psr_match_conditions(intel_dp))
2171 dev_priv->psr.enabled = intel_dp;
2172 mutex_unlock(&dev_priv->psr.lock);
2175 void intel_edp_psr_disable(struct intel_dp *intel_dp)
2177 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2178 struct drm_i915_private *dev_priv = dev->dev_private;
2180 mutex_lock(&dev_priv->psr.lock);
2181 if (!dev_priv->psr.enabled) {
2182 mutex_unlock(&dev_priv->psr.lock);
2186 if (dev_priv->psr.active) {
2187 I915_WRITE(EDP_PSR_CTL(dev),
2188 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2190 /* Wait till PSR is idle */
2191 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2192 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
2193 DRM_ERROR("Timed out waiting for PSR Idle State\n");
2195 dev_priv->psr.active = false;
2197 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2200 dev_priv->psr.enabled = NULL;
2201 mutex_unlock(&dev_priv->psr.lock);
2203 cancel_delayed_work_sync(&dev_priv->psr.work);
2206 static void intel_edp_psr_work(struct work_struct *work)
2208 struct drm_i915_private *dev_priv =
2209 container_of(work, typeof(*dev_priv), psr.work.work);
2210 struct intel_dp *intel_dp = dev_priv->psr.enabled;
2212 mutex_lock(&dev_priv->psr.lock);
2213 intel_dp = dev_priv->psr.enabled;
2219 * The delayed work can race with an invalidate hence we need to
2220 * recheck. Since psr_flush first clears this and then reschedules we
2221 * won't ever miss a flush when bailing out here.
2223 if (dev_priv->psr.busy_frontbuffer_bits)
2226 intel_edp_psr_do_enable(intel_dp);
2228 mutex_unlock(&dev_priv->psr.lock);
2231 static void intel_edp_psr_do_exit(struct drm_device *dev)
2233 struct drm_i915_private *dev_priv = dev->dev_private;
2235 if (dev_priv->psr.active) {
2236 u32 val = I915_READ(EDP_PSR_CTL(dev));
2238 WARN_ON(!(val & EDP_PSR_ENABLE));
2240 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
2242 dev_priv->psr.active = false;
2247 void intel_edp_psr_invalidate(struct drm_device *dev,
2248 unsigned frontbuffer_bits)
2250 struct drm_i915_private *dev_priv = dev->dev_private;
2251 struct drm_crtc *crtc;
2254 mutex_lock(&dev_priv->psr.lock);
2255 if (!dev_priv->psr.enabled) {
2256 mutex_unlock(&dev_priv->psr.lock);
2260 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2261 pipe = to_intel_crtc(crtc)->pipe;
2263 intel_edp_psr_do_exit(dev);
2265 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
2267 dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
2268 mutex_unlock(&dev_priv->psr.lock);
2271 void intel_edp_psr_flush(struct drm_device *dev,
2272 unsigned frontbuffer_bits)
2274 struct drm_i915_private *dev_priv = dev->dev_private;
2275 struct drm_crtc *crtc;
2278 mutex_lock(&dev_priv->psr.lock);
2279 if (!dev_priv->psr.enabled) {
2280 mutex_unlock(&dev_priv->psr.lock);
2284 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2285 pipe = to_intel_crtc(crtc)->pipe;
2286 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
2289 * On Haswell sprite plane updates don't result in a psr invalidating
2290 * signal in the hardware. Which means we need to manually fake this in
2291 * software for all flushes, not just when we've seen a preceding
2292 * invalidation through frontbuffer rendering.
2294 if (IS_HASWELL(dev) &&
2295 (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
2296 intel_edp_psr_do_exit(dev);
2298 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
2299 schedule_delayed_work(&dev_priv->psr.work,
2300 msecs_to_jiffies(100));
2301 mutex_unlock(&dev_priv->psr.lock);
2304 void intel_edp_psr_init(struct drm_device *dev)
2306 struct drm_i915_private *dev_priv = dev->dev_private;
2308 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
2309 mutex_init(&dev_priv->psr.lock);
2312 static void intel_disable_dp(struct intel_encoder *encoder)
2314 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2315 struct drm_device *dev = encoder->base.dev;
2317 /* Make sure the panel is off before trying to change the mode. But also
2318 * ensure that we have vdd while we switch off the panel. */
2319 intel_edp_panel_vdd_on(intel_dp);
2320 intel_edp_backlight_off(intel_dp);
2321 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2322 intel_edp_panel_off(intel_dp);
2324 /* disable the port before the pipe on g4x */
2325 if (INTEL_INFO(dev)->gen < 5)
2326 intel_dp_link_down(intel_dp);
2329 static void ilk_post_disable_dp(struct intel_encoder *encoder)
2331 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2332 enum port port = dp_to_dig_port(intel_dp)->port;
2334 intel_dp_link_down(intel_dp);
2336 ironlake_edp_pll_off(intel_dp);
2339 static void vlv_post_disable_dp(struct intel_encoder *encoder)
2341 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2343 intel_dp_link_down(intel_dp);
2346 static void chv_post_disable_dp(struct intel_encoder *encoder)
2348 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2349 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2350 struct drm_device *dev = encoder->base.dev;
2351 struct drm_i915_private *dev_priv = dev->dev_private;
2352 struct intel_crtc *intel_crtc =
2353 to_intel_crtc(encoder->base.crtc);
2354 enum dpio_channel ch = vlv_dport_to_channel(dport);
2355 enum pipe pipe = intel_crtc->pipe;
2358 intel_dp_link_down(intel_dp);
2360 mutex_lock(&dev_priv->dpio_lock);
2362 /* Propagate soft reset to data lane reset */
2363 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2364 val |= CHV_PCS_REQ_SOFTRESET_EN;
2365 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2367 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2368 val |= CHV_PCS_REQ_SOFTRESET_EN;
2369 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2371 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2372 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2373 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2375 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2376 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2377 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2379 mutex_unlock(&dev_priv->dpio_lock);
2383 _intel_dp_set_link_train(struct intel_dp *intel_dp,
2385 uint8_t dp_train_pat)
2387 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2388 struct drm_device *dev = intel_dig_port->base.base.dev;
2389 struct drm_i915_private *dev_priv = dev->dev_private;
2390 enum port port = intel_dig_port->port;
2393 uint32_t temp = I915_READ(DP_TP_CTL(port));
2395 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2396 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2398 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2400 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2401 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2402 case DP_TRAINING_PATTERN_DISABLE:
2403 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2406 case DP_TRAINING_PATTERN_1:
2407 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2409 case DP_TRAINING_PATTERN_2:
2410 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2412 case DP_TRAINING_PATTERN_3:
2413 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2416 I915_WRITE(DP_TP_CTL(port), temp);
2418 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2419 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2421 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2422 case DP_TRAINING_PATTERN_DISABLE:
2423 *DP |= DP_LINK_TRAIN_OFF_CPT;
2425 case DP_TRAINING_PATTERN_1:
2426 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2428 case DP_TRAINING_PATTERN_2:
2429 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2431 case DP_TRAINING_PATTERN_3:
2432 DRM_ERROR("DP training pattern 3 not supported\n");
2433 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2438 if (IS_CHERRYVIEW(dev))
2439 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2441 *DP &= ~DP_LINK_TRAIN_MASK;
2443 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2444 case DP_TRAINING_PATTERN_DISABLE:
2445 *DP |= DP_LINK_TRAIN_OFF;
2447 case DP_TRAINING_PATTERN_1:
2448 *DP |= DP_LINK_TRAIN_PAT_1;
2450 case DP_TRAINING_PATTERN_2:
2451 *DP |= DP_LINK_TRAIN_PAT_2;
2453 case DP_TRAINING_PATTERN_3:
2454 if (IS_CHERRYVIEW(dev)) {
2455 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2457 DRM_ERROR("DP training pattern 3 not supported\n");
2458 *DP |= DP_LINK_TRAIN_PAT_2;
2465 static void intel_dp_enable_port(struct intel_dp *intel_dp)
2467 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2468 struct drm_i915_private *dev_priv = dev->dev_private;
2470 intel_dp->DP |= DP_PORT_EN;
2472 /* enable with pattern 1 (as per spec) */
2473 _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2474 DP_TRAINING_PATTERN_1);
2476 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2477 POSTING_READ(intel_dp->output_reg);
2480 static void intel_enable_dp(struct intel_encoder *encoder)
2482 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2483 struct drm_device *dev = encoder->base.dev;
2484 struct drm_i915_private *dev_priv = dev->dev_private;
2485 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2487 if (WARN_ON(dp_reg & DP_PORT_EN))
2490 intel_dp_enable_port(intel_dp);
2491 intel_edp_panel_vdd_on(intel_dp);
2492 intel_edp_panel_on(intel_dp);
2493 intel_edp_panel_vdd_off(intel_dp, true);
2494 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2495 intel_dp_start_link_train(intel_dp);
2496 intel_dp_complete_link_train(intel_dp);
2497 intel_dp_stop_link_train(intel_dp);
2500 static void g4x_enable_dp(struct intel_encoder *encoder)
2502 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2504 intel_enable_dp(encoder);
2505 intel_edp_backlight_on(intel_dp);
2508 static void vlv_enable_dp(struct intel_encoder *encoder)
2510 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2512 intel_edp_backlight_on(intel_dp);
2515 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
2517 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2518 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2520 intel_dp_prepare(encoder);
2522 /* Only ilk+ has port A */
2523 if (dport->port == PORT_A) {
2524 ironlake_set_pll_cpu_edp(intel_dp);
2525 ironlake_edp_pll_on(intel_dp);
2529 static void vlv_steal_power_sequencer(struct drm_device *dev,
2532 struct drm_i915_private *dev_priv = dev->dev_private;
2533 struct intel_encoder *encoder;
2535 lockdep_assert_held(&dev_priv->pps_mutex);
2537 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2539 struct intel_dp *intel_dp;
2542 if (encoder->type != INTEL_OUTPUT_EDP)
2545 intel_dp = enc_to_intel_dp(&encoder->base);
2546 port = dp_to_dig_port(intel_dp)->port;
2548 if (intel_dp->pps_pipe != pipe)
2551 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2552 pipe_name(pipe), port_name(port));
2554 /* make sure vdd is off before we steal it */
2555 edp_panel_vdd_off_sync(intel_dp);
2557 intel_dp->pps_pipe = INVALID_PIPE;
2561 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2563 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2564 struct intel_encoder *encoder = &intel_dig_port->base;
2565 struct drm_device *dev = encoder->base.dev;
2566 struct drm_i915_private *dev_priv = dev->dev_private;
2567 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2568 struct edp_power_seq power_seq;
2570 lockdep_assert_held(&dev_priv->pps_mutex);
2572 if (intel_dp->pps_pipe == crtc->pipe)
2576 * If another power sequencer was being used on this
2577 * port previously make sure to turn off vdd there while
2578 * we still have control of it.
2580 if (intel_dp->pps_pipe != INVALID_PIPE)
2581 edp_panel_vdd_off_sync(intel_dp);
2584 * We may be stealing the power
2585 * sequencer from another port.
2587 vlv_steal_power_sequencer(dev, crtc->pipe);
2589 /* now it's all ours */
2590 intel_dp->pps_pipe = crtc->pipe;
2592 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2593 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2595 /* init power sequencer on this pipe and port */
2596 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2597 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2601 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
2603 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2604 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2605 struct drm_device *dev = encoder->base.dev;
2606 struct drm_i915_private *dev_priv = dev->dev_private;
2607 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2608 enum dpio_channel port = vlv_dport_to_channel(dport);
2609 int pipe = intel_crtc->pipe;
2612 mutex_lock(&dev_priv->dpio_lock);
2614 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
2621 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2622 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2623 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
2625 mutex_unlock(&dev_priv->dpio_lock);
2627 if (is_edp(intel_dp)) {
2629 vlv_init_panel_power_sequencer(intel_dp);
2630 pps_unlock(intel_dp);
2633 intel_enable_dp(encoder);
2635 vlv_wait_port_ready(dev_priv, dport);
2638 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
2640 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2641 struct drm_device *dev = encoder->base.dev;
2642 struct drm_i915_private *dev_priv = dev->dev_private;
2643 struct intel_crtc *intel_crtc =
2644 to_intel_crtc(encoder->base.crtc);
2645 enum dpio_channel port = vlv_dport_to_channel(dport);
2646 int pipe = intel_crtc->pipe;
2648 intel_dp_prepare(encoder);
2650 /* Program Tx lane resets to default */
2651 mutex_lock(&dev_priv->dpio_lock);
2652 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
2653 DPIO_PCS_TX_LANE2_RESET |
2654 DPIO_PCS_TX_LANE1_RESET);
2655 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
2656 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2657 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2658 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2659 DPIO_PCS_CLK_SOFT_RESET);
2661 /* Fix up inter-pair skew failure */
2662 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2663 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2664 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
2665 mutex_unlock(&dev_priv->dpio_lock);
2668 static void chv_pre_enable_dp(struct intel_encoder *encoder)
2670 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2671 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2672 struct drm_device *dev = encoder->base.dev;
2673 struct drm_i915_private *dev_priv = dev->dev_private;
2674 struct intel_crtc *intel_crtc =
2675 to_intel_crtc(encoder->base.crtc);
2676 enum dpio_channel ch = vlv_dport_to_channel(dport);
2677 int pipe = intel_crtc->pipe;
2681 mutex_lock(&dev_priv->dpio_lock);
2683 /* Deassert soft data lane reset*/
2684 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2685 val |= CHV_PCS_REQ_SOFTRESET_EN;
2686 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2688 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2689 val |= CHV_PCS_REQ_SOFTRESET_EN;
2690 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2692 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2693 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2694 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2696 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2697 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2698 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2700 /* Program Tx lane latency optimal setting*/
2701 for (i = 0; i < 4; i++) {
2702 /* Set the latency optimal bit */
2703 data = (i == 1) ? 0x0 : 0x6;
2704 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2705 data << DPIO_FRC_LATENCY_SHFIT);
2707 /* Set the upar bit */
2708 data = (i == 1) ? 0x0 : 0x1;
2709 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2710 data << DPIO_UPAR_SHIFT);
2713 /* Data lane stagger programming */
2714 /* FIXME: Fix up value only after power analysis */
2716 mutex_unlock(&dev_priv->dpio_lock);
2718 if (is_edp(intel_dp)) {
2720 vlv_init_panel_power_sequencer(intel_dp);
2721 pps_unlock(intel_dp);
2724 intel_enable_dp(encoder);
2726 vlv_wait_port_ready(dev_priv, dport);
2729 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2731 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2732 struct drm_device *dev = encoder->base.dev;
2733 struct drm_i915_private *dev_priv = dev->dev_private;
2734 struct intel_crtc *intel_crtc =
2735 to_intel_crtc(encoder->base.crtc);
2736 enum dpio_channel ch = vlv_dport_to_channel(dport);
2737 enum pipe pipe = intel_crtc->pipe;
2740 intel_dp_prepare(encoder);
2742 mutex_lock(&dev_priv->dpio_lock);
2744 /* program left/right clock distribution */
2745 if (pipe != PIPE_B) {
2746 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2747 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2749 val |= CHV_BUFLEFTENA1_FORCE;
2751 val |= CHV_BUFRIGHTENA1_FORCE;
2752 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2754 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2755 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2757 val |= CHV_BUFLEFTENA2_FORCE;
2759 val |= CHV_BUFRIGHTENA2_FORCE;
2760 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2763 /* program clock channel usage */
2764 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2765 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2767 val &= ~CHV_PCS_USEDCLKCHANNEL;
2769 val |= CHV_PCS_USEDCLKCHANNEL;
2770 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2772 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2773 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2775 val &= ~CHV_PCS_USEDCLKCHANNEL;
2777 val |= CHV_PCS_USEDCLKCHANNEL;
2778 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2781 * This a a bit weird since generally CL
2782 * matches the pipe, but here we need to
2783 * pick the CL based on the port.
2785 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2787 val &= ~CHV_CMN_USEDCLKCHANNEL;
2789 val |= CHV_CMN_USEDCLKCHANNEL;
2790 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2792 mutex_unlock(&dev_priv->dpio_lock);
2796 * Native read with retry for link status and receiver capability reads for
2797 * cases where the sink may still be asleep.
2799 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2800 * supposed to retry 3 times per the spec.
2803 intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2804 void *buffer, size_t size)
2810 * Sometime we just get the same incorrect byte repeated
2811 * over the entire buffer. Doing just one throw away read
2812 * initially seems to "solve" it.
2814 drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1);
2816 for (i = 0; i < 3; i++) {
2817 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2827 * Fetch AUX CH registers 0x202 - 0x207 which contain
2828 * link status information
2831 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2833 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2836 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
2839 /* These are source-specific values. */
2841 intel_dp_voltage_max(struct intel_dp *intel_dp)
2843 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2844 enum port port = dp_to_dig_port(intel_dp)->port;
2846 if (IS_VALLEYVIEW(dev))
2847 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2848 else if (IS_GEN7(dev) && port == PORT_A)
2849 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2850 else if (HAS_PCH_CPT(dev) && port != PORT_A)
2851 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2853 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2857 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2859 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2860 enum port port = dp_to_dig_port(intel_dp)->port;
2862 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2863 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2864 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2865 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2866 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2867 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2868 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2869 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2870 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2872 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2874 } else if (IS_VALLEYVIEW(dev)) {
2875 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2876 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2877 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2878 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2879 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2880 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2881 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2882 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2884 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2886 } else if (IS_GEN7(dev) && port == PORT_A) {
2887 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2888 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2889 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2890 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2891 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2892 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2894 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2897 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2898 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2899 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2900 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2901 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2902 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2903 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2904 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2906 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2911 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2913 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2914 struct drm_i915_private *dev_priv = dev->dev_private;
2915 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2916 struct intel_crtc *intel_crtc =
2917 to_intel_crtc(dport->base.base.crtc);
2918 unsigned long demph_reg_value, preemph_reg_value,
2919 uniqtranscale_reg_value;
2920 uint8_t train_set = intel_dp->train_set[0];
2921 enum dpio_channel port = vlv_dport_to_channel(dport);
2922 int pipe = intel_crtc->pipe;
2924 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2925 case DP_TRAIN_PRE_EMPH_LEVEL_0:
2926 preemph_reg_value = 0x0004000;
2927 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2928 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2929 demph_reg_value = 0x2B405555;
2930 uniqtranscale_reg_value = 0x552AB83A;
2932 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2933 demph_reg_value = 0x2B404040;
2934 uniqtranscale_reg_value = 0x5548B83A;
2936 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2937 demph_reg_value = 0x2B245555;
2938 uniqtranscale_reg_value = 0x5560B83A;
2940 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2941 demph_reg_value = 0x2B405555;
2942 uniqtranscale_reg_value = 0x5598DA3A;
2948 case DP_TRAIN_PRE_EMPH_LEVEL_1:
2949 preemph_reg_value = 0x0002000;
2950 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2951 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2952 demph_reg_value = 0x2B404040;
2953 uniqtranscale_reg_value = 0x5552B83A;
2955 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2956 demph_reg_value = 0x2B404848;
2957 uniqtranscale_reg_value = 0x5580B83A;
2959 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2960 demph_reg_value = 0x2B404040;
2961 uniqtranscale_reg_value = 0x55ADDA3A;
2967 case DP_TRAIN_PRE_EMPH_LEVEL_2:
2968 preemph_reg_value = 0x0000000;
2969 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2970 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2971 demph_reg_value = 0x2B305555;
2972 uniqtranscale_reg_value = 0x5570B83A;
2974 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2975 demph_reg_value = 0x2B2B4040;
2976 uniqtranscale_reg_value = 0x55ADDA3A;
2982 case DP_TRAIN_PRE_EMPH_LEVEL_3:
2983 preemph_reg_value = 0x0006000;
2984 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2985 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2986 demph_reg_value = 0x1B405555;
2987 uniqtranscale_reg_value = 0x55ADDA3A;
2997 mutex_lock(&dev_priv->dpio_lock);
2998 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2999 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
3000 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
3001 uniqtranscale_reg_value);
3002 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
3003 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
3004 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
3005 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
3006 mutex_unlock(&dev_priv->dpio_lock);
3011 static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
3013 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3014 struct drm_i915_private *dev_priv = dev->dev_private;
3015 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3016 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
3017 u32 deemph_reg_value, margin_reg_value, val;
3018 uint8_t train_set = intel_dp->train_set[0];
3019 enum dpio_channel ch = vlv_dport_to_channel(dport);
3020 enum pipe pipe = intel_crtc->pipe;
3023 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3024 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3025 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3026 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3027 deemph_reg_value = 128;
3028 margin_reg_value = 52;
3030 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3031 deemph_reg_value = 128;
3032 margin_reg_value = 77;
3034 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3035 deemph_reg_value = 128;
3036 margin_reg_value = 102;
3038 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3039 deemph_reg_value = 128;
3040 margin_reg_value = 154;
3041 /* FIXME extra to set for 1200 */
3047 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3048 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3049 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3050 deemph_reg_value = 85;
3051 margin_reg_value = 78;
3053 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3054 deemph_reg_value = 85;
3055 margin_reg_value = 116;
3057 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3058 deemph_reg_value = 85;
3059 margin_reg_value = 154;
3065 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3066 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3067 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3068 deemph_reg_value = 64;
3069 margin_reg_value = 104;
3071 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3072 deemph_reg_value = 64;
3073 margin_reg_value = 154;
3079 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3080 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3081 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3082 deemph_reg_value = 43;
3083 margin_reg_value = 154;
3093 mutex_lock(&dev_priv->dpio_lock);
3095 /* Clear calc init */
3096 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3097 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3098 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3100 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3101 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3102 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
3104 /* Program swing deemph */
3105 for (i = 0; i < 4; i++) {
3106 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
3107 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
3108 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
3109 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
3112 /* Program swing margin */
3113 for (i = 0; i < 4; i++) {
3114 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3115 val &= ~DPIO_SWING_MARGIN000_MASK;
3116 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
3117 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3120 /* Disable unique transition scale */
3121 for (i = 0; i < 4; i++) {
3122 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3123 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3124 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3127 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
3128 == DP_TRAIN_PRE_EMPH_LEVEL_0) &&
3129 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
3130 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
3133 * The document said it needs to set bit 27 for ch0 and bit 26
3134 * for ch1. Might be a typo in the doc.
3135 * For now, for this unique transition scale selection, set bit
3136 * 27 for ch0 and ch1.
3138 for (i = 0; i < 4; i++) {
3139 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3140 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3141 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3144 for (i = 0; i < 4; i++) {
3145 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3146 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3147 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3148 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3152 /* Start swing calculation */
3153 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3154 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3155 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3157 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3158 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3159 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
3162 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
3163 val |= DPIO_LRC_BYPASS;
3164 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
3166 mutex_unlock(&dev_priv->dpio_lock);
3172 intel_get_adjust_train(struct intel_dp *intel_dp,
3173 const uint8_t link_status[DP_LINK_STATUS_SIZE])
3178 uint8_t voltage_max;
3179 uint8_t preemph_max;
3181 for (lane = 0; lane < intel_dp->lane_count; lane++) {
3182 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
3183 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
3191 voltage_max = intel_dp_voltage_max(intel_dp);
3192 if (v >= voltage_max)
3193 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
3195 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
3196 if (p >= preemph_max)
3197 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
3199 for (lane = 0; lane < 4; lane++)
3200 intel_dp->train_set[lane] = v | p;
3204 intel_gen4_signal_levels(uint8_t train_set)
3206 uint32_t signal_levels = 0;
3208 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3209 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3211 signal_levels |= DP_VOLTAGE_0_4;
3213 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3214 signal_levels |= DP_VOLTAGE_0_6;
3216 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3217 signal_levels |= DP_VOLTAGE_0_8;
3219 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3220 signal_levels |= DP_VOLTAGE_1_2;
3223 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3224 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3226 signal_levels |= DP_PRE_EMPHASIS_0;
3228 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3229 signal_levels |= DP_PRE_EMPHASIS_3_5;
3231 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3232 signal_levels |= DP_PRE_EMPHASIS_6;
3234 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3235 signal_levels |= DP_PRE_EMPHASIS_9_5;
3238 return signal_levels;
3241 /* Gen6's DP voltage swing and pre-emphasis control */
3243 intel_gen6_edp_signal_levels(uint8_t train_set)
3245 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3246 DP_TRAIN_PRE_EMPHASIS_MASK);
3247 switch (signal_levels) {
3248 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3249 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3250 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3251 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3252 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3253 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3254 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3255 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3256 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3257 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3258 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3259 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3260 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3261 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3263 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3264 "0x%x\n", signal_levels);
3265 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3269 /* Gen7's DP voltage swing and pre-emphasis control */
3271 intel_gen7_edp_signal_levels(uint8_t train_set)
3273 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3274 DP_TRAIN_PRE_EMPHASIS_MASK);
3275 switch (signal_levels) {
3276 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3277 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3278 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3279 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3280 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3281 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3283 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3284 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3285 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3286 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3288 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3289 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3290 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3291 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3294 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3295 "0x%x\n", signal_levels);
3296 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3300 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3302 intel_hsw_signal_levels(uint8_t train_set)
3304 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3305 DP_TRAIN_PRE_EMPHASIS_MASK);
3306 switch (signal_levels) {
3307 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3308 return DDI_BUF_TRANS_SELECT(0);
3309 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3310 return DDI_BUF_TRANS_SELECT(1);
3311 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3312 return DDI_BUF_TRANS_SELECT(2);
3313 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
3314 return DDI_BUF_TRANS_SELECT(3);
3316 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3317 return DDI_BUF_TRANS_SELECT(4);
3318 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3319 return DDI_BUF_TRANS_SELECT(5);
3320 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3321 return DDI_BUF_TRANS_SELECT(6);
3323 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3324 return DDI_BUF_TRANS_SELECT(7);
3325 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3326 return DDI_BUF_TRANS_SELECT(8);
3328 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3329 "0x%x\n", signal_levels);
3330 return DDI_BUF_TRANS_SELECT(0);
3334 /* Properly updates "DP" with the correct signal levels. */
3336 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
3338 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3339 enum port port = intel_dig_port->port;
3340 struct drm_device *dev = intel_dig_port->base.base.dev;
3341 uint32_t signal_levels, mask;
3342 uint8_t train_set = intel_dp->train_set[0];
3344 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3345 signal_levels = intel_hsw_signal_levels(train_set);
3346 mask = DDI_BUF_EMP_MASK;
3347 } else if (IS_CHERRYVIEW(dev)) {
3348 signal_levels = intel_chv_signal_levels(intel_dp);
3350 } else if (IS_VALLEYVIEW(dev)) {
3351 signal_levels = intel_vlv_signal_levels(intel_dp);
3353 } else if (IS_GEN7(dev) && port == PORT_A) {
3354 signal_levels = intel_gen7_edp_signal_levels(train_set);
3355 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3356 } else if (IS_GEN6(dev) && port == PORT_A) {
3357 signal_levels = intel_gen6_edp_signal_levels(train_set);
3358 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3360 signal_levels = intel_gen4_signal_levels(train_set);
3361 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3364 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3366 *DP = (*DP & ~mask) | signal_levels;
3370 intel_dp_set_link_train(struct intel_dp *intel_dp,
3372 uint8_t dp_train_pat)
3374 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3375 struct drm_device *dev = intel_dig_port->base.base.dev;
3376 struct drm_i915_private *dev_priv = dev->dev_private;
3377 uint8_t buf[sizeof(intel_dp->train_set) + 1];
3380 _intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3382 I915_WRITE(intel_dp->output_reg, *DP);
3383 POSTING_READ(intel_dp->output_reg);
3385 buf[0] = dp_train_pat;
3386 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
3387 DP_TRAINING_PATTERN_DISABLE) {
3388 /* don't write DP_TRAINING_LANEx_SET on disable */
3391 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3392 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3393 len = intel_dp->lane_count + 1;
3396 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3403 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3404 uint8_t dp_train_pat)
3406 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
3407 intel_dp_set_signal_levels(intel_dp, DP);
3408 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3412 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3413 const uint8_t link_status[DP_LINK_STATUS_SIZE])
3415 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3416 struct drm_device *dev = intel_dig_port->base.base.dev;
3417 struct drm_i915_private *dev_priv = dev->dev_private;
3420 intel_get_adjust_train(intel_dp, link_status);
3421 intel_dp_set_signal_levels(intel_dp, DP);
3423 I915_WRITE(intel_dp->output_reg, *DP);
3424 POSTING_READ(intel_dp->output_reg);
3426 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3427 intel_dp->train_set, intel_dp->lane_count);
3429 return ret == intel_dp->lane_count;
3432 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3434 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3435 struct drm_device *dev = intel_dig_port->base.base.dev;
3436 struct drm_i915_private *dev_priv = dev->dev_private;
3437 enum port port = intel_dig_port->port;
3443 val = I915_READ(DP_TP_CTL(port));
3444 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3445 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3446 I915_WRITE(DP_TP_CTL(port), val);
3449 * On PORT_A we can have only eDP in SST mode. There the only reason
3450 * we need to set idle transmission mode is to work around a HW issue
3451 * where we enable the pipe while not in idle link-training mode.
3452 * In this case there is requirement to wait for a minimum number of
3453 * idle patterns to be sent.
3458 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3460 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3463 /* Enable corresponding port and start training pattern 1 */
3465 intel_dp_start_link_train(struct intel_dp *intel_dp)
3467 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
3468 struct drm_device *dev = encoder->dev;
3471 int voltage_tries, loop_tries;
3472 uint32_t DP = intel_dp->DP;
3473 uint8_t link_config[2];
3476 intel_ddi_prepare_link_retrain(encoder);
3478 /* Write the link configuration data */
3479 link_config[0] = intel_dp->link_bw;
3480 link_config[1] = intel_dp->lane_count;
3481 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3482 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
3483 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
3486 link_config[1] = DP_SET_ANSI_8B10B;
3487 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
3491 /* clock recovery */
3492 if (!intel_dp_reset_link_train(intel_dp, &DP,
3493 DP_TRAINING_PATTERN_1 |
3494 DP_LINK_SCRAMBLING_DISABLE)) {
3495 DRM_ERROR("failed to enable link training\n");
3503 uint8_t link_status[DP_LINK_STATUS_SIZE];
3505 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
3506 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3507 DRM_ERROR("failed to get link status\n");
3511 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3512 DRM_DEBUG_KMS("clock recovery OK\n");
3516 /* Check to see if we've tried the max voltage */
3517 for (i = 0; i < intel_dp->lane_count; i++)
3518 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
3520 if (i == intel_dp->lane_count) {
3522 if (loop_tries == 5) {
3523 DRM_ERROR("too many full retries, give up\n");
3526 intel_dp_reset_link_train(intel_dp, &DP,
3527 DP_TRAINING_PATTERN_1 |
3528 DP_LINK_SCRAMBLING_DISABLE);
3533 /* Check to see if we've tried the same voltage 5 times */
3534 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
3536 if (voltage_tries == 5) {
3537 DRM_ERROR("too many voltage retries, give up\n");
3542 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
3544 /* Update training set as requested by target */
3545 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3546 DRM_ERROR("failed to update link training\n");
3555 intel_dp_complete_link_train(struct intel_dp *intel_dp)
3557 bool channel_eq = false;
3558 int tries, cr_tries;
3559 uint32_t DP = intel_dp->DP;
3560 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3562 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3563 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3564 training_pattern = DP_TRAINING_PATTERN_3;
3566 /* channel equalization */
3567 if (!intel_dp_set_link_train(intel_dp, &DP,
3569 DP_LINK_SCRAMBLING_DISABLE)) {
3570 DRM_ERROR("failed to start channel equalization\n");
3578 uint8_t link_status[DP_LINK_STATUS_SIZE];
3581 DRM_ERROR("failed to train DP, aborting\n");
3585 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
3586 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3587 DRM_ERROR("failed to get link status\n");
3591 /* Make sure clock is still ok */
3592 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3593 intel_dp_start_link_train(intel_dp);
3594 intel_dp_set_link_train(intel_dp, &DP,
3596 DP_LINK_SCRAMBLING_DISABLE);
3601 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3606 /* Try 5 times, then try clock recovery if that fails */
3608 intel_dp_link_down(intel_dp);
3609 intel_dp_start_link_train(intel_dp);
3610 intel_dp_set_link_train(intel_dp, &DP,
3612 DP_LINK_SCRAMBLING_DISABLE);
3618 /* Update training set as requested by target */
3619 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3620 DRM_ERROR("failed to update link training\n");
3626 intel_dp_set_idle_link_train(intel_dp);
3631 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3635 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3637 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3638 DP_TRAINING_PATTERN_DISABLE);
3642 intel_dp_link_down(struct intel_dp *intel_dp)
3644 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3645 enum port port = intel_dig_port->port;
3646 struct drm_device *dev = intel_dig_port->base.base.dev;
3647 struct drm_i915_private *dev_priv = dev->dev_private;
3648 struct intel_crtc *intel_crtc =
3649 to_intel_crtc(intel_dig_port->base.base.crtc);
3650 uint32_t DP = intel_dp->DP;
3652 if (WARN_ON(HAS_DDI(dev)))
3655 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3658 DRM_DEBUG_KMS("\n");
3660 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
3661 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3662 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
3664 if (IS_CHERRYVIEW(dev))
3665 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3667 DP &= ~DP_LINK_TRAIN_MASK;
3668 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
3670 POSTING_READ(intel_dp->output_reg);
3672 if (HAS_PCH_IBX(dev) &&
3673 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
3674 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
3676 /* Hardware workaround: leaving our transcoder select
3677 * set to transcoder B while it's off will prevent the
3678 * corresponding HDMI output on transcoder A.
3680 * Combine this with another hardware workaround:
3681 * transcoder select bit can only be cleared while the
3684 DP &= ~DP_PIPEB_SELECT;
3685 I915_WRITE(intel_dp->output_reg, DP);
3687 /* Changes to enable or select take place the vblank
3688 * after being written.
3690 if (WARN_ON(crtc == NULL)) {
3691 /* We should never try to disable a port without a crtc
3692 * attached. For paranoia keep the code around for a
3694 POSTING_READ(intel_dp->output_reg);
3697 intel_wait_for_vblank(dev, intel_crtc->pipe);
3700 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
3701 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3702 POSTING_READ(intel_dp->output_reg);
3703 msleep(intel_dp->panel_power_down_delay);
3707 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3709 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3710 struct drm_device *dev = dig_port->base.base.dev;
3711 struct drm_i915_private *dev_priv = dev->dev_private;
3713 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3714 sizeof(intel_dp->dpcd)) < 0)
3715 return false; /* aux transfer failed */
3717 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3719 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3720 return false; /* DPCD not present */
3722 /* Check if the panel supports PSR */
3723 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
3724 if (is_edp(intel_dp)) {
3725 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3727 sizeof(intel_dp->psr_dpcd));
3728 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3729 dev_priv->psr.sink_support = true;
3730 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3734 /* Training Pattern 3 support, both source and sink */
3735 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3736 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED &&
3737 (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)) {
3738 intel_dp->use_tps3 = true;
3739 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
3741 intel_dp->use_tps3 = false;
3743 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3744 DP_DWN_STRM_PORT_PRESENT))
3745 return true; /* native DP sink */
3747 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3748 return true; /* no per-port downstream info */
3750 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3751 intel_dp->downstream_ports,
3752 DP_MAX_DOWNSTREAM_PORTS) < 0)
3753 return false; /* downstream port status fetch failed */
3759 intel_dp_probe_oui(struct intel_dp *intel_dp)
3763 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3766 intel_edp_panel_vdd_on(intel_dp);
3768 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
3769 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3770 buf[0], buf[1], buf[2]);
3772 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
3773 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3774 buf[0], buf[1], buf[2]);
3776 intel_edp_panel_vdd_off(intel_dp, false);
3780 intel_dp_probe_mst(struct intel_dp *intel_dp)
3784 if (!intel_dp->can_mst)
3787 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3790 intel_edp_panel_vdd_on(intel_dp);
3791 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3792 if (buf[0] & DP_MST_CAP) {
3793 DRM_DEBUG_KMS("Sink is MST capable\n");
3794 intel_dp->is_mst = true;
3796 DRM_DEBUG_KMS("Sink is not MST capable\n");
3797 intel_dp->is_mst = false;
3800 intel_edp_panel_vdd_off(intel_dp, false);
3802 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3803 return intel_dp->is_mst;
3806 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3808 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3809 struct drm_device *dev = intel_dig_port->base.base.dev;
3810 struct intel_crtc *intel_crtc =
3811 to_intel_crtc(intel_dig_port->base.base.crtc);
3814 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
3817 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
3820 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3821 DP_TEST_SINK_START) < 0)
3824 /* Wait 2 vblanks to be sure we will have the correct CRC value */
3825 intel_wait_for_vblank(dev, intel_crtc->pipe);
3826 intel_wait_for_vblank(dev, intel_crtc->pipe);
3828 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
3831 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
3836 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3838 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3839 DP_DEVICE_SERVICE_IRQ_VECTOR,
3840 sink_irq_vector, 1) == 1;
3844 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3848 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
3850 sink_irq_vector, 14);
3858 intel_dp_handle_test_request(struct intel_dp *intel_dp)
3860 /* NAK by default */
3861 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
3865 intel_dp_check_mst_status(struct intel_dp *intel_dp)
3869 if (intel_dp->is_mst) {
3874 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3878 /* check link status - esi[10] = 0x200c */
3879 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3880 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3881 intel_dp_start_link_train(intel_dp);
3882 intel_dp_complete_link_train(intel_dp);
3883 intel_dp_stop_link_train(intel_dp);
3886 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3887 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3890 for (retry = 0; retry < 3; retry++) {
3892 wret = drm_dp_dpcd_write(&intel_dp->aux,
3893 DP_SINK_COUNT_ESI+1,
3900 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3902 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3910 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3911 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3912 intel_dp->is_mst = false;
3913 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3914 /* send a hotplug event */
3915 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3922 * According to DP spec
3925 * 2. Configure link according to Receiver Capabilities
3926 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3927 * 4. Check link status on receipt of hot-plug interrupt
3930 intel_dp_check_link_status(struct intel_dp *intel_dp)
3932 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3933 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
3935 u8 link_status[DP_LINK_STATUS_SIZE];
3937 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3939 if (!intel_encoder->connectors_active)
3942 if (WARN_ON(!intel_encoder->base.crtc))
3945 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3948 /* Try to read receiver status if the link appears to be up */
3949 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3953 /* Now read the DPCD to see if it's actually running */
3954 if (!intel_dp_get_dpcd(intel_dp)) {
3958 /* Try to read the source of the interrupt */
3959 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3960 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3961 /* Clear interrupt source */
3962 drm_dp_dpcd_writeb(&intel_dp->aux,
3963 DP_DEVICE_SERVICE_IRQ_VECTOR,
3966 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3967 intel_dp_handle_test_request(intel_dp);
3968 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3969 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3972 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3973 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3974 intel_encoder->base.name);
3975 intel_dp_start_link_train(intel_dp);
3976 intel_dp_complete_link_train(intel_dp);
3977 intel_dp_stop_link_train(intel_dp);
3981 /* XXX this is probably wrong for multiple downstream ports */
3982 static enum drm_connector_status
3983 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
3985 uint8_t *dpcd = intel_dp->dpcd;
3988 if (!intel_dp_get_dpcd(intel_dp))
3989 return connector_status_disconnected;
3991 /* if there's no downstream port, we're done */
3992 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
3993 return connector_status_connected;
3995 /* If we're HPD-aware, SINK_COUNT changes dynamically */
3996 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3997 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4000 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
4002 return connector_status_unknown;
4004 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
4005 : connector_status_disconnected;
4008 /* If no HPD, poke DDC gently */
4009 if (drm_probe_ddc(&intel_dp->aux.ddc))
4010 return connector_status_connected;
4012 /* Well we tried, say unknown for unreliable port types */
4013 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4014 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4015 if (type == DP_DS_PORT_TYPE_VGA ||
4016 type == DP_DS_PORT_TYPE_NON_EDID)
4017 return connector_status_unknown;
4019 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4020 DP_DWN_STRM_PORT_TYPE_MASK;
4021 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4022 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4023 return connector_status_unknown;
4026 /* Anything else is out of spec, warn and ignore */
4027 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4028 return connector_status_disconnected;
4031 static enum drm_connector_status
4032 edp_detect(struct intel_dp *intel_dp)
4034 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4035 enum drm_connector_status status;
4037 status = intel_panel_detect(dev);
4038 if (status == connector_status_unknown)
4039 status = connector_status_connected;
4044 static enum drm_connector_status
4045 ironlake_dp_detect(struct intel_dp *intel_dp)
4047 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4048 struct drm_i915_private *dev_priv = dev->dev_private;
4049 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4051 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4052 return connector_status_disconnected;
4054 return intel_dp_detect_dpcd(intel_dp);
4057 static int g4x_digital_port_connected(struct drm_device *dev,
4058 struct intel_digital_port *intel_dig_port)
4060 struct drm_i915_private *dev_priv = dev->dev_private;
4063 if (IS_VALLEYVIEW(dev)) {
4064 switch (intel_dig_port->port) {
4066 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
4069 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
4072 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
4078 switch (intel_dig_port->port) {
4080 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4083 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4086 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4093 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
4098 static enum drm_connector_status
4099 g4x_dp_detect(struct intel_dp *intel_dp)
4101 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4102 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4105 /* Can't disconnect eDP, but you can close the lid... */
4106 if (is_edp(intel_dp)) {
4107 enum drm_connector_status status;
4109 status = intel_panel_detect(dev);
4110 if (status == connector_status_unknown)
4111 status = connector_status_connected;
4115 ret = g4x_digital_port_connected(dev, intel_dig_port);
4117 return connector_status_unknown;
4119 return connector_status_disconnected;
4121 return intel_dp_detect_dpcd(intel_dp);
4124 static struct edid *
4125 intel_dp_get_edid(struct intel_dp *intel_dp)
4127 struct intel_connector *intel_connector = intel_dp->attached_connector;
4129 /* use cached edid if we have one */
4130 if (intel_connector->edid) {
4132 if (IS_ERR(intel_connector->edid))
4135 return drm_edid_duplicate(intel_connector->edid);
4137 return drm_get_edid(&intel_connector->base,
4138 &intel_dp->aux.ddc);
4142 intel_dp_set_edid(struct intel_dp *intel_dp)
4144 struct intel_connector *intel_connector = intel_dp->attached_connector;
4147 edid = intel_dp_get_edid(intel_dp);
4148 intel_connector->detect_edid = edid;
4150 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4151 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4153 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4157 intel_dp_unset_edid(struct intel_dp *intel_dp)
4159 struct intel_connector *intel_connector = intel_dp->attached_connector;
4161 kfree(intel_connector->detect_edid);
4162 intel_connector->detect_edid = NULL;
4164 intel_dp->has_audio = false;
4167 static enum intel_display_power_domain
4168 intel_dp_power_get(struct intel_dp *dp)
4170 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4171 enum intel_display_power_domain power_domain;
4173 power_domain = intel_display_port_power_domain(encoder);
4174 intel_display_power_get(to_i915(encoder->base.dev), power_domain);
4176 return power_domain;
4180 intel_dp_power_put(struct intel_dp *dp,
4181 enum intel_display_power_domain power_domain)
4183 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4184 intel_display_power_put(to_i915(encoder->base.dev), power_domain);
4187 static enum drm_connector_status
4188 intel_dp_detect(struct drm_connector *connector, bool force)
4190 struct intel_dp *intel_dp = intel_attached_dp(connector);
4191 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4192 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4193 struct drm_device *dev = connector->dev;
4194 enum drm_connector_status status;
4195 enum intel_display_power_domain power_domain;
4198 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4199 connector->base.id, connector->name);
4200 intel_dp_unset_edid(intel_dp);
4202 if (intel_dp->is_mst) {
4203 /* MST devices are disconnected from a monitor POV */
4204 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4205 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4206 return connector_status_disconnected;
4209 power_domain = intel_dp_power_get(intel_dp);
4211 /* Can't disconnect eDP, but you can close the lid... */
4212 if (is_edp(intel_dp))
4213 status = edp_detect(intel_dp);
4214 else if (HAS_PCH_SPLIT(dev))
4215 status = ironlake_dp_detect(intel_dp);
4217 status = g4x_dp_detect(intel_dp);
4218 if (status != connector_status_connected)
4221 intel_dp_probe_oui(intel_dp);
4223 ret = intel_dp_probe_mst(intel_dp);
4225 /* if we are in MST mode then this connector
4226 won't appear connected or have anything with EDID on it */
4227 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4228 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4229 status = connector_status_disconnected;
4233 intel_dp_set_edid(intel_dp);
4235 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4236 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4237 status = connector_status_connected;
4240 intel_dp_power_put(intel_dp, power_domain);
4245 intel_dp_force(struct drm_connector *connector)
4247 struct intel_dp *intel_dp = intel_attached_dp(connector);
4248 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4249 enum intel_display_power_domain power_domain;
4251 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4252 connector->base.id, connector->name);
4253 intel_dp_unset_edid(intel_dp);
4255 if (connector->status != connector_status_connected)
4258 power_domain = intel_dp_power_get(intel_dp);
4260 intel_dp_set_edid(intel_dp);
4262 intel_dp_power_put(intel_dp, power_domain);
4264 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4265 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4268 static int intel_dp_get_modes(struct drm_connector *connector)
4270 struct intel_connector *intel_connector = to_intel_connector(connector);
4273 edid = intel_connector->detect_edid;
4275 int ret = intel_connector_update_modes(connector, edid);
4280 /* if eDP has no EDID, fall back to fixed mode */
4281 if (is_edp(intel_attached_dp(connector)) &&
4282 intel_connector->panel.fixed_mode) {
4283 struct drm_display_mode *mode;
4285 mode = drm_mode_duplicate(connector->dev,
4286 intel_connector->panel.fixed_mode);
4288 drm_mode_probed_add(connector, mode);
4297 intel_dp_detect_audio(struct drm_connector *connector)
4299 bool has_audio = false;
4302 edid = to_intel_connector(connector)->detect_edid;
4304 has_audio = drm_detect_monitor_audio(edid);
4310 intel_dp_set_property(struct drm_connector *connector,
4311 struct drm_property *property,
4314 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4315 struct intel_connector *intel_connector = to_intel_connector(connector);
4316 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4317 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4320 ret = drm_object_property_set_value(&connector->base, property, val);
4324 if (property == dev_priv->force_audio_property) {
4328 if (i == intel_dp->force_audio)
4331 intel_dp->force_audio = i;
4333 if (i == HDMI_AUDIO_AUTO)
4334 has_audio = intel_dp_detect_audio(connector);
4336 has_audio = (i == HDMI_AUDIO_ON);
4338 if (has_audio == intel_dp->has_audio)
4341 intel_dp->has_audio = has_audio;
4345 if (property == dev_priv->broadcast_rgb_property) {
4346 bool old_auto = intel_dp->color_range_auto;
4347 uint32_t old_range = intel_dp->color_range;
4350 case INTEL_BROADCAST_RGB_AUTO:
4351 intel_dp->color_range_auto = true;
4353 case INTEL_BROADCAST_RGB_FULL:
4354 intel_dp->color_range_auto = false;
4355 intel_dp->color_range = 0;
4357 case INTEL_BROADCAST_RGB_LIMITED:
4358 intel_dp->color_range_auto = false;
4359 intel_dp->color_range = DP_COLOR_RANGE_16_235;
4365 if (old_auto == intel_dp->color_range_auto &&
4366 old_range == intel_dp->color_range)
4372 if (is_edp(intel_dp) &&
4373 property == connector->dev->mode_config.scaling_mode_property) {
4374 if (val == DRM_MODE_SCALE_NONE) {
4375 DRM_DEBUG_KMS("no scaling not supported\n");
4379 if (intel_connector->panel.fitting_mode == val) {
4380 /* the eDP scaling property is not changed */
4383 intel_connector->panel.fitting_mode = val;
4391 if (intel_encoder->base.crtc)
4392 intel_crtc_restore_mode(intel_encoder->base.crtc);
4398 intel_dp_connector_destroy(struct drm_connector *connector)
4400 struct intel_connector *intel_connector = to_intel_connector(connector);
4402 kfree(intel_connector->detect_edid);
4404 if (!IS_ERR_OR_NULL(intel_connector->edid))
4405 kfree(intel_connector->edid);
4407 /* Can't call is_edp() since the encoder may have been destroyed
4409 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4410 intel_panel_fini(&intel_connector->panel);
4412 drm_connector_cleanup(connector);
4416 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4418 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4419 struct intel_dp *intel_dp = &intel_dig_port->dp;
4421 drm_dp_aux_unregister(&intel_dp->aux);
4422 intel_dp_mst_encoder_cleanup(intel_dig_port);
4423 drm_encoder_cleanup(encoder);
4424 if (is_edp(intel_dp)) {
4425 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4427 * vdd might still be enabled do to the delayed vdd off.
4428 * Make sure vdd is actually turned off here.
4431 edp_panel_vdd_off_sync(intel_dp);
4432 pps_unlock(intel_dp);
4434 if (intel_dp->edp_notifier.notifier_call) {
4435 unregister_reboot_notifier(&intel_dp->edp_notifier);
4436 intel_dp->edp_notifier.notifier_call = NULL;
4439 kfree(intel_dig_port);
4442 static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4444 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4446 if (!is_edp(intel_dp))
4450 * vdd might still be enabled do to the delayed vdd off.
4451 * Make sure vdd is actually turned off here.
4454 edp_panel_vdd_off_sync(intel_dp);
4455 pps_unlock(intel_dp);
4458 static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4460 intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder));
4463 static const struct drm_connector_funcs intel_dp_connector_funcs = {
4464 .dpms = intel_connector_dpms,
4465 .detect = intel_dp_detect,
4466 .force = intel_dp_force,
4467 .fill_modes = drm_helper_probe_single_connector_modes,
4468 .set_property = intel_dp_set_property,
4469 .destroy = intel_dp_connector_destroy,
4472 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4473 .get_modes = intel_dp_get_modes,
4474 .mode_valid = intel_dp_mode_valid,
4475 .best_encoder = intel_best_encoder,
4478 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
4479 .reset = intel_dp_encoder_reset,
4480 .destroy = intel_dp_encoder_destroy,
4484 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
4490 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4492 struct intel_dp *intel_dp = &intel_dig_port->dp;
4493 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4494 struct drm_device *dev = intel_dig_port->base.base.dev;
4495 struct drm_i915_private *dev_priv = dev->dev_private;
4496 enum intel_display_power_domain power_domain;
4499 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4500 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
4502 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4504 * vdd off can generate a long pulse on eDP which
4505 * would require vdd on to handle it, and thus we
4506 * would end up in an endless cycle of
4507 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4509 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4510 port_name(intel_dig_port->port));
4514 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4515 port_name(intel_dig_port->port),
4516 long_hpd ? "long" : "short");
4518 power_domain = intel_display_port_power_domain(intel_encoder);
4519 intel_display_power_get(dev_priv, power_domain);
4523 if (HAS_PCH_SPLIT(dev)) {
4524 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4527 if (g4x_digital_port_connected(dev, intel_dig_port) != 1)
4531 if (!intel_dp_get_dpcd(intel_dp)) {
4535 intel_dp_probe_oui(intel_dp);
4537 if (!intel_dp_probe_mst(intel_dp))
4541 if (intel_dp->is_mst) {
4542 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
4546 if (!intel_dp->is_mst) {
4548 * we'll check the link status via the normal hot plug path later -
4549 * but for short hpds we should check it now
4551 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4552 intel_dp_check_link_status(intel_dp);
4553 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4559 /* if we were in MST mode, and device is not there get out of MST mode */
4560 if (intel_dp->is_mst) {
4561 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4562 intel_dp->is_mst = false;
4563 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4566 intel_display_power_put(dev_priv, power_domain);
4571 /* Return which DP Port should be selected for Transcoder DP control */
4573 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4575 struct drm_device *dev = crtc->dev;
4576 struct intel_encoder *intel_encoder;
4577 struct intel_dp *intel_dp;
4579 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4580 intel_dp = enc_to_intel_dp(&intel_encoder->base);
4582 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4583 intel_encoder->type == INTEL_OUTPUT_EDP)
4584 return intel_dp->output_reg;
4590 /* check the VBT to see whether the eDP is on DP-D port */
4591 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
4593 struct drm_i915_private *dev_priv = dev->dev_private;
4594 union child_device_config *p_child;
4596 static const short port_mapping[] = {
4597 [PORT_B] = PORT_IDPB,
4598 [PORT_C] = PORT_IDPC,
4599 [PORT_D] = PORT_IDPD,
4605 if (!dev_priv->vbt.child_dev_num)
4608 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4609 p_child = dev_priv->vbt.child_dev + i;
4611 if (p_child->common.dvo_port == port_mapping[port] &&
4612 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4613 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
4620 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4622 struct intel_connector *intel_connector = to_intel_connector(connector);
4624 intel_attach_force_audio_property(connector);
4625 intel_attach_broadcast_rgb_property(connector);
4626 intel_dp->color_range_auto = true;
4628 if (is_edp(intel_dp)) {
4629 drm_mode_create_scaling_mode_property(connector->dev);
4630 drm_object_attach_property(
4632 connector->dev->mode_config.scaling_mode_property,
4633 DRM_MODE_SCALE_ASPECT);
4634 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
4638 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4640 intel_dp->last_power_cycle = jiffies;
4641 intel_dp->last_power_on = jiffies;
4642 intel_dp->last_backlight_off = jiffies;
4646 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
4647 struct intel_dp *intel_dp,
4648 struct edp_power_seq *out)
4650 struct drm_i915_private *dev_priv = dev->dev_private;
4651 struct edp_power_seq cur, vbt, spec, final;
4652 u32 pp_on, pp_off, pp_div, pp;
4653 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
4655 lockdep_assert_held(&dev_priv->pps_mutex);
4657 if (HAS_PCH_SPLIT(dev)) {
4658 pp_ctrl_reg = PCH_PP_CONTROL;
4659 pp_on_reg = PCH_PP_ON_DELAYS;
4660 pp_off_reg = PCH_PP_OFF_DELAYS;
4661 pp_div_reg = PCH_PP_DIVISOR;
4663 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4665 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4666 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4667 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4668 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
4671 /* Workaround: Need to write PP_CONTROL with the unlock key as
4672 * the very first thing. */
4673 pp = ironlake_get_pp_control(intel_dp);
4674 I915_WRITE(pp_ctrl_reg, pp);
4676 pp_on = I915_READ(pp_on_reg);
4677 pp_off = I915_READ(pp_off_reg);
4678 pp_div = I915_READ(pp_div_reg);
4680 /* Pull timing values out of registers */
4681 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4682 PANEL_POWER_UP_DELAY_SHIFT;
4684 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4685 PANEL_LIGHT_ON_DELAY_SHIFT;
4687 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4688 PANEL_LIGHT_OFF_DELAY_SHIFT;
4690 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4691 PANEL_POWER_DOWN_DELAY_SHIFT;
4693 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4694 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4696 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4697 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4699 vbt = dev_priv->vbt.edp_pps;
4701 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4702 * our hw here, which are all in 100usec. */
4703 spec.t1_t3 = 210 * 10;
4704 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4705 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4706 spec.t10 = 500 * 10;
4707 /* This one is special and actually in units of 100ms, but zero
4708 * based in the hw (so we need to add 100 ms). But the sw vbt
4709 * table multiplies it with 1000 to make it in units of 100usec,
4711 spec.t11_t12 = (510 + 100) * 10;
4713 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4714 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4716 /* Use the max of the register settings and vbt. If both are
4717 * unset, fall back to the spec limits. */
4718 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
4720 max(cur.field, vbt.field))
4721 assign_final(t1_t3);
4725 assign_final(t11_t12);
4728 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
4729 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4730 intel_dp->backlight_on_delay = get_delay(t8);
4731 intel_dp->backlight_off_delay = get_delay(t9);
4732 intel_dp->panel_power_down_delay = get_delay(t10);
4733 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4736 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4737 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4738 intel_dp->panel_power_cycle_delay);
4740 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4741 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4748 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4749 struct intel_dp *intel_dp,
4750 struct edp_power_seq *seq)
4752 struct drm_i915_private *dev_priv = dev->dev_private;
4753 u32 pp_on, pp_off, pp_div, port_sel = 0;
4754 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4755 int pp_on_reg, pp_off_reg, pp_div_reg;
4756 enum port port = dp_to_dig_port(intel_dp)->port;
4758 lockdep_assert_held(&dev_priv->pps_mutex);
4760 if (HAS_PCH_SPLIT(dev)) {
4761 pp_on_reg = PCH_PP_ON_DELAYS;
4762 pp_off_reg = PCH_PP_OFF_DELAYS;
4763 pp_div_reg = PCH_PP_DIVISOR;
4765 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4767 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4768 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4769 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
4773 * And finally store the new values in the power sequencer. The
4774 * backlight delays are set to 1 because we do manual waits on them. For
4775 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4776 * we'll end up waiting for the backlight off delay twice: once when we
4777 * do the manual sleep, and once when we disable the panel and wait for
4778 * the PP_STATUS bit to become zero.
4780 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
4781 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4782 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
4783 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
4784 /* Compute the divisor for the pp clock, simply match the Bspec
4786 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
4787 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
4788 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4790 /* Haswell doesn't have any port selection bits for the panel
4791 * power sequencer any more. */
4792 if (IS_VALLEYVIEW(dev)) {
4793 port_sel = PANEL_PORT_SELECT_VLV(port);
4794 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
4796 port_sel = PANEL_PORT_SELECT_DPA;
4798 port_sel = PANEL_PORT_SELECT_DPD;
4803 I915_WRITE(pp_on_reg, pp_on);
4804 I915_WRITE(pp_off_reg, pp_off);
4805 I915_WRITE(pp_div_reg, pp_div);
4807 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
4808 I915_READ(pp_on_reg),
4809 I915_READ(pp_off_reg),
4810 I915_READ(pp_div_reg));
4813 void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4815 struct drm_i915_private *dev_priv = dev->dev_private;
4816 struct intel_encoder *encoder;
4817 struct intel_dp *intel_dp = NULL;
4818 struct intel_crtc_config *config = NULL;
4819 struct intel_crtc *intel_crtc = NULL;
4820 struct intel_connector *intel_connector = dev_priv->drrs.connector;
4822 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4824 if (refresh_rate <= 0) {
4825 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4829 if (intel_connector == NULL) {
4830 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4835 * FIXME: This needs proper synchronization with psr state. But really
4836 * hard to tell without seeing the user of this function of this code.
4837 * Check locking and ordering once that lands.
4839 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
4840 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4844 encoder = intel_attached_encoder(&intel_connector->base);
4845 intel_dp = enc_to_intel_dp(&encoder->base);
4846 intel_crtc = encoder->new_crtc;
4849 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4853 config = &intel_crtc->config;
4855 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4856 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4860 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
4861 index = DRRS_LOW_RR;
4863 if (index == intel_dp->drrs_state.refresh_rate_type) {
4865 "DRRS requested for previously set RR...ignoring\n");
4869 if (!intel_crtc->active) {
4870 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4874 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4875 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4876 val = I915_READ(reg);
4877 if (index > DRRS_HIGH_RR) {
4878 val |= PIPECONF_EDP_RR_MODE_SWITCH;
4879 intel_dp_set_m_n(intel_crtc);
4881 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4883 I915_WRITE(reg, val);
4887 * mutex taken to ensure that there is no race between differnt
4888 * drrs calls trying to update refresh rate. This scenario may occur
4889 * in future when idleness detection based DRRS in kernel and
4890 * possible calls from user space to set differnt RR are made.
4893 mutex_lock(&intel_dp->drrs_state.mutex);
4895 intel_dp->drrs_state.refresh_rate_type = index;
4897 mutex_unlock(&intel_dp->drrs_state.mutex);
4899 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4902 static struct drm_display_mode *
4903 intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4904 struct intel_connector *intel_connector,
4905 struct drm_display_mode *fixed_mode)
4907 struct drm_connector *connector = &intel_connector->base;
4908 struct intel_dp *intel_dp = &intel_dig_port->dp;
4909 struct drm_device *dev = intel_dig_port->base.base.dev;
4910 struct drm_i915_private *dev_priv = dev->dev_private;
4911 struct drm_display_mode *downclock_mode = NULL;
4913 if (INTEL_INFO(dev)->gen <= 6) {
4914 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4918 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4919 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4923 downclock_mode = intel_find_panel_downclock
4924 (dev, fixed_mode, connector);
4926 if (!downclock_mode) {
4927 DRM_DEBUG_KMS("DRRS not supported\n");
4931 dev_priv->drrs.connector = intel_connector;
4933 mutex_init(&intel_dp->drrs_state.mutex);
4935 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4937 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4938 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4939 return downclock_mode;
4942 void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder)
4944 struct drm_device *dev = intel_encoder->base.dev;
4945 struct drm_i915_private *dev_priv = dev->dev_private;
4946 struct intel_dp *intel_dp;
4947 enum intel_display_power_domain power_domain;
4949 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4952 intel_dp = enc_to_intel_dp(&intel_encoder->base);
4956 if (!edp_have_panel_vdd(intel_dp))
4959 * The VDD bit needs a power domain reference, so if the bit is
4960 * already enabled when we boot or resume, grab this reference and
4961 * schedule a vdd off, so we don't hold on to the reference
4964 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4965 power_domain = intel_display_port_power_domain(intel_encoder);
4966 intel_display_power_get(dev_priv, power_domain);
4968 edp_panel_vdd_schedule_off(intel_dp);
4970 pps_unlock(intel_dp);
4973 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
4974 struct intel_connector *intel_connector,
4975 struct edp_power_seq *power_seq)
4977 struct drm_connector *connector = &intel_connector->base;
4978 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4979 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4980 struct drm_device *dev = intel_encoder->base.dev;
4981 struct drm_i915_private *dev_priv = dev->dev_private;
4982 struct drm_display_mode *fixed_mode = NULL;
4983 struct drm_display_mode *downclock_mode = NULL;
4985 struct drm_display_mode *scan;
4988 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
4990 if (!is_edp(intel_dp))
4993 intel_edp_panel_vdd_sanitize(intel_encoder);
4995 /* Cache DPCD and EDID for edp. */
4996 intel_edp_panel_vdd_on(intel_dp);
4997 has_dpcd = intel_dp_get_dpcd(intel_dp);
4998 intel_edp_panel_vdd_off(intel_dp, false);
5001 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5002 dev_priv->no_aux_handshake =
5003 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5004 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5006 /* if this fails, presume the device is a ghost */
5007 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5011 /* We now know it's not a ghost, init power sequence regs. */
5013 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
5014 pps_unlock(intel_dp);
5016 mutex_lock(&dev->mode_config.mutex);
5017 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5019 if (drm_add_edid_modes(connector, edid)) {
5020 drm_mode_connector_update_edid_property(connector,
5022 drm_edid_to_eld(connector, edid);
5025 edid = ERR_PTR(-EINVAL);
5028 edid = ERR_PTR(-ENOENT);
5030 intel_connector->edid = edid;
5032 /* prefer fixed mode from EDID if available */
5033 list_for_each_entry(scan, &connector->probed_modes, head) {
5034 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5035 fixed_mode = drm_mode_duplicate(dev, scan);
5036 downclock_mode = intel_dp_drrs_init(
5038 intel_connector, fixed_mode);
5043 /* fallback to VBT if available for eDP */
5044 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5045 fixed_mode = drm_mode_duplicate(dev,
5046 dev_priv->vbt.lfp_lvds_vbt_mode);
5048 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5050 mutex_unlock(&dev->mode_config.mutex);
5052 if (IS_VALLEYVIEW(dev)) {
5053 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5054 register_reboot_notifier(&intel_dp->edp_notifier);
5057 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5058 intel_connector->panel.backlight_power = intel_edp_backlight_power;
5059 intel_panel_setup_backlight(connector);
5065 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5066 struct intel_connector *intel_connector)
5068 struct drm_connector *connector = &intel_connector->base;
5069 struct intel_dp *intel_dp = &intel_dig_port->dp;
5070 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5071 struct drm_device *dev = intel_encoder->base.dev;
5072 struct drm_i915_private *dev_priv = dev->dev_private;
5073 enum port port = intel_dig_port->port;
5074 struct edp_power_seq power_seq = { 0 };
5077 intel_dp->pps_pipe = INVALID_PIPE;
5079 /* intel_dp vfuncs */
5080 if (IS_VALLEYVIEW(dev))
5081 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
5082 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5083 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5084 else if (HAS_PCH_SPLIT(dev))
5085 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5087 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
5089 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
5091 /* Preserve the current hw state. */
5092 intel_dp->DP = I915_READ(intel_dp->output_reg);
5093 intel_dp->attached_connector = intel_connector;
5095 if (intel_dp_is_edp(dev, port))
5096 type = DRM_MODE_CONNECTOR_eDP;
5098 type = DRM_MODE_CONNECTOR_DisplayPort;
5101 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5102 * for DP the encoder type can be set by the caller to
5103 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5105 if (type == DRM_MODE_CONNECTOR_eDP)
5106 intel_encoder->type = INTEL_OUTPUT_EDP;
5108 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5109 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5112 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5113 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5115 connector->interlace_allowed = true;
5116 connector->doublescan_allowed = 0;
5118 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
5119 edp_panel_vdd_work);
5121 intel_connector_attach_encoder(intel_connector, intel_encoder);
5122 drm_connector_register(connector);
5125 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5127 intel_connector->get_hw_state = intel_connector_get_hw_state;
5128 intel_connector->unregister = intel_dp_connector_unregister;
5130 /* Set up the hotplug pin. */
5133 intel_encoder->hpd_pin = HPD_PORT_A;
5136 intel_encoder->hpd_pin = HPD_PORT_B;
5139 intel_encoder->hpd_pin = HPD_PORT_C;
5142 intel_encoder->hpd_pin = HPD_PORT_D;
5148 if (is_edp(intel_dp)) {
5150 if (IS_VALLEYVIEW(dev)) {
5151 vlv_initial_power_sequencer_setup(intel_dp);
5153 intel_dp_init_panel_power_timestamps(intel_dp);
5154 intel_dp_init_panel_power_sequencer(dev, intel_dp,
5157 pps_unlock(intel_dp);
5160 intel_dp_aux_init(intel_dp, intel_connector);
5162 /* init MST on ports that can support it */
5163 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5164 if (port == PORT_B || port == PORT_C || port == PORT_D) {
5165 intel_dp_mst_encoder_init(intel_dig_port,
5166 intel_connector->base.base.id);
5170 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
5171 drm_dp_aux_unregister(&intel_dp->aux);
5172 if (is_edp(intel_dp)) {
5173 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5175 * vdd might still be enabled do to the delayed vdd off.
5176 * Make sure vdd is actually turned off here.
5179 edp_panel_vdd_off_sync(intel_dp);
5180 pps_unlock(intel_dp);
5182 drm_connector_unregister(connector);
5183 drm_connector_cleanup(connector);
5187 intel_dp_add_properties(intel_dp, connector);
5189 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5190 * 0xd. Failure to do so will result in spurious interrupts being
5191 * generated on the port when a cable is not attached.
5193 if (IS_G4X(dev) && !IS_GM45(dev)) {
5194 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5195 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5202 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
5204 struct drm_i915_private *dev_priv = dev->dev_private;
5205 struct intel_digital_port *intel_dig_port;
5206 struct intel_encoder *intel_encoder;
5207 struct drm_encoder *encoder;
5208 struct intel_connector *intel_connector;
5210 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
5211 if (!intel_dig_port)
5214 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
5215 if (!intel_connector) {
5216 kfree(intel_dig_port);
5220 intel_encoder = &intel_dig_port->base;
5221 encoder = &intel_encoder->base;
5223 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5224 DRM_MODE_ENCODER_TMDS);
5226 intel_encoder->compute_config = intel_dp_compute_config;
5227 intel_encoder->disable = intel_disable_dp;
5228 intel_encoder->get_hw_state = intel_dp_get_hw_state;
5229 intel_encoder->get_config = intel_dp_get_config;
5230 intel_encoder->suspend = intel_dp_encoder_suspend;
5231 if (IS_CHERRYVIEW(dev)) {
5232 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
5233 intel_encoder->pre_enable = chv_pre_enable_dp;
5234 intel_encoder->enable = vlv_enable_dp;
5235 intel_encoder->post_disable = chv_post_disable_dp;
5236 } else if (IS_VALLEYVIEW(dev)) {
5237 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
5238 intel_encoder->pre_enable = vlv_pre_enable_dp;
5239 intel_encoder->enable = vlv_enable_dp;
5240 intel_encoder->post_disable = vlv_post_disable_dp;
5242 intel_encoder->pre_enable = g4x_pre_enable_dp;
5243 intel_encoder->enable = g4x_enable_dp;
5244 if (INTEL_INFO(dev)->gen >= 5)
5245 intel_encoder->post_disable = ilk_post_disable_dp;
5248 intel_dig_port->port = port;
5249 intel_dig_port->dp.output_reg = output_reg;
5251 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
5252 if (IS_CHERRYVIEW(dev)) {
5254 intel_encoder->crtc_mask = 1 << 2;
5256 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5258 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5260 intel_encoder->cloneable = 0;
5261 intel_encoder->hot_plug = intel_dp_hot_plug;
5263 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5264 dev_priv->hpd_irq_port[port] = intel_dig_port;
5266 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
5267 drm_encoder_cleanup(encoder);
5268 kfree(intel_dig_port);
5269 kfree(intel_connector);
5273 void intel_dp_mst_suspend(struct drm_device *dev)
5275 struct drm_i915_private *dev_priv = dev->dev_private;
5279 for (i = 0; i < I915_MAX_PORTS; i++) {
5280 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5281 if (!intel_dig_port)
5284 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5285 if (!intel_dig_port->dp.can_mst)
5287 if (intel_dig_port->dp.is_mst)
5288 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5293 void intel_dp_mst_resume(struct drm_device *dev)
5295 struct drm_i915_private *dev_priv = dev->dev_private;
5298 for (i = 0; i < I915_MAX_PORTS; i++) {
5299 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5300 if (!intel_dig_port)
5302 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5305 if (!intel_dig_port->dp.can_mst)
5308 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5310 intel_dp_check_mst_status(&intel_dig_port->dp);