2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
39 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
48 static bool is_edp(struct intel_dp *intel_dp)
50 return intel_dp->base.type == INTEL_OUTPUT_EDP;
54 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
55 * @intel_dp: DP struct
57 * Returns true if the given DP struct corresponds to a PCH DP port attached
58 * to an eDP panel, false otherwise. Helpful for determining whether we
59 * may need FDI resources for a given DP output or not.
61 static bool is_pch_edp(struct intel_dp *intel_dp)
63 return intel_dp->is_pch_edp;
67 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
68 * @intel_dp: DP struct
70 * Returns true if the given DP struct corresponds to a CPU eDP port.
72 static bool is_cpu_edp(struct intel_dp *intel_dp)
74 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
77 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
79 return container_of(intel_attached_encoder(connector),
80 struct intel_dp, base);
84 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
85 * @encoder: DRM encoder
87 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
90 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
92 struct intel_dp *intel_dp;
97 intel_dp = enc_to_intel_dp(encoder);
99 return is_pch_edp(intel_dp);
102 static void intel_dp_link_down(struct intel_dp *intel_dp);
105 intel_edp_link_config(struct intel_encoder *intel_encoder,
106 int *lane_num, int *link_bw)
108 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
110 *lane_num = intel_dp->lane_count;
111 *link_bw = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
115 intel_edp_target_clock(struct intel_encoder *intel_encoder,
116 struct drm_display_mode *mode)
118 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
119 struct intel_connector *intel_connector = intel_dp->attached_connector;
121 if (intel_connector->panel.fixed_mode)
122 return intel_connector->panel.fixed_mode->clock;
128 intel_dp_max_link_bw(struct intel_dp *intel_dp)
130 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
132 switch (max_link_bw) {
133 case DP_LINK_BW_1_62:
137 max_link_bw = DP_LINK_BW_1_62;
144 intel_dp_link_clock(uint8_t link_bw)
146 if (link_bw == DP_LINK_BW_2_7)
153 * The units on the numbers in the next two are... bizarre. Examples will
154 * make it clearer; this one parallels an example in the eDP spec.
156 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
158 * 270000 * 1 * 8 / 10 == 216000
160 * The actual data capacity of that configuration is 2.16Gbit/s, so the
161 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
162 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
163 * 119000. At 18bpp that's 2142000 kilobits per second.
165 * Thus the strange-looking division by 10 in intel_dp_link_required, to
166 * get the result in decakilobits instead of kilobits.
170 intel_dp_link_required(int pixel_clock, int bpp)
172 return (pixel_clock * bpp + 9) / 10;
176 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
178 return (max_link_clock * max_lanes * 8) / 10;
182 intel_dp_adjust_dithering(struct intel_dp *intel_dp,
183 struct drm_display_mode *mode,
186 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
187 int max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
188 int max_rate, mode_rate;
190 mode_rate = intel_dp_link_required(mode->clock, 24);
191 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
193 if (mode_rate > max_rate) {
194 mode_rate = intel_dp_link_required(mode->clock, 18);
195 if (mode_rate > max_rate)
200 |= INTEL_MODE_DP_FORCE_6BPC;
209 intel_dp_mode_valid(struct drm_connector *connector,
210 struct drm_display_mode *mode)
212 struct intel_dp *intel_dp = intel_attached_dp(connector);
213 struct intel_connector *intel_connector = to_intel_connector(connector);
214 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
216 if (is_edp(intel_dp) && fixed_mode) {
217 if (mode->hdisplay > fixed_mode->hdisplay)
220 if (mode->vdisplay > fixed_mode->vdisplay)
224 if (!intel_dp_adjust_dithering(intel_dp, mode, false))
225 return MODE_CLOCK_HIGH;
227 if (mode->clock < 10000)
228 return MODE_CLOCK_LOW;
230 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
231 return MODE_H_ILLEGAL;
237 pack_aux(uint8_t *src, int src_bytes)
244 for (i = 0; i < src_bytes; i++)
245 v |= ((uint32_t) src[i]) << ((3-i) * 8);
250 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
255 for (i = 0; i < dst_bytes; i++)
256 dst[i] = src >> ((3-i) * 8);
259 /* hrawclock is 1/4 the FSB frequency */
261 intel_hrawclk(struct drm_device *dev)
263 struct drm_i915_private *dev_priv = dev->dev_private;
266 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
267 if (IS_VALLEYVIEW(dev))
270 clkcfg = I915_READ(CLKCFG);
271 switch (clkcfg & CLKCFG_FSB_MASK) {
280 case CLKCFG_FSB_1067:
282 case CLKCFG_FSB_1333:
284 /* these two are just a guess; one of them might be right */
285 case CLKCFG_FSB_1600:
286 case CLKCFG_FSB_1600_ALT:
293 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
295 struct drm_device *dev = intel_dp->base.base.dev;
296 struct drm_i915_private *dev_priv = dev->dev_private;
298 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
301 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
303 struct drm_device *dev = intel_dp->base.base.dev;
304 struct drm_i915_private *dev_priv = dev->dev_private;
306 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
310 intel_dp_check_edp(struct intel_dp *intel_dp)
312 struct drm_device *dev = intel_dp->base.base.dev;
313 struct drm_i915_private *dev_priv = dev->dev_private;
315 if (!is_edp(intel_dp))
317 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
318 WARN(1, "eDP powered off while attempting aux channel communication.\n");
319 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
320 I915_READ(PCH_PP_STATUS),
321 I915_READ(PCH_PP_CONTROL));
326 intel_dp_aux_ch(struct intel_dp *intel_dp,
327 uint8_t *send, int send_bytes,
328 uint8_t *recv, int recv_size)
330 uint32_t output_reg = intel_dp->output_reg;
331 struct drm_device *dev = intel_dp->base.base.dev;
332 struct drm_i915_private *dev_priv = dev->dev_private;
333 uint32_t ch_ctl = output_reg + 0x10;
334 uint32_t ch_data = ch_ctl + 4;
338 uint32_t aux_clock_divider;
341 if (IS_HASWELL(dev)) {
342 switch (intel_dp->port) {
344 ch_ctl = DPA_AUX_CH_CTL;
345 ch_data = DPA_AUX_CH_DATA1;
348 ch_ctl = PCH_DPB_AUX_CH_CTL;
349 ch_data = PCH_DPB_AUX_CH_DATA1;
352 ch_ctl = PCH_DPC_AUX_CH_CTL;
353 ch_data = PCH_DPC_AUX_CH_DATA1;
356 ch_ctl = PCH_DPD_AUX_CH_CTL;
357 ch_data = PCH_DPD_AUX_CH_DATA1;
364 intel_dp_check_edp(intel_dp);
365 /* The clock divider is based off the hrawclk,
366 * and would like to run at 2MHz. So, take the
367 * hrawclk value and divide by 2 and use that
369 * Note that PCH attached eDP panels should use a 125MHz input
372 if (is_cpu_edp(intel_dp)) {
373 if (IS_VALLEYVIEW(dev))
374 aux_clock_divider = 100;
375 else if (IS_GEN6(dev) || IS_GEN7(dev))
376 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
378 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
379 } else if (HAS_PCH_SPLIT(dev))
380 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
382 aux_clock_divider = intel_hrawclk(dev) / 2;
389 /* Try to wait for any previous AUX channel activity */
390 for (try = 0; try < 3; try++) {
391 status = I915_READ(ch_ctl);
392 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
398 WARN(1, "dp_aux_ch not started status 0x%08x\n",
403 /* Must try at least 3 times according to DP spec */
404 for (try = 0; try < 5; try++) {
405 /* Load the send data into the aux channel data registers */
406 for (i = 0; i < send_bytes; i += 4)
407 I915_WRITE(ch_data + i,
408 pack_aux(send + i, send_bytes - i));
410 /* Send the command and wait for it to complete */
412 DP_AUX_CH_CTL_SEND_BUSY |
413 DP_AUX_CH_CTL_TIME_OUT_400us |
414 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
415 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
416 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
418 DP_AUX_CH_CTL_TIME_OUT_ERROR |
419 DP_AUX_CH_CTL_RECEIVE_ERROR);
421 status = I915_READ(ch_ctl);
422 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
427 /* Clear done status and any errors */
431 DP_AUX_CH_CTL_TIME_OUT_ERROR |
432 DP_AUX_CH_CTL_RECEIVE_ERROR);
434 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
435 DP_AUX_CH_CTL_RECEIVE_ERROR))
437 if (status & DP_AUX_CH_CTL_DONE)
441 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
442 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
446 /* Check for timeout or receive error.
447 * Timeouts occur when the sink is not connected
449 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
450 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
454 /* Timeouts occur when the device isn't connected, so they're
455 * "normal" -- don't fill the kernel log with these */
456 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
457 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
461 /* Unload any bytes sent back from the other side */
462 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
463 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
464 if (recv_bytes > recv_size)
465 recv_bytes = recv_size;
467 for (i = 0; i < recv_bytes; i += 4)
468 unpack_aux(I915_READ(ch_data + i),
469 recv + i, recv_bytes - i);
474 /* Write data to the aux channel in native mode */
476 intel_dp_aux_native_write(struct intel_dp *intel_dp,
477 uint16_t address, uint8_t *send, int send_bytes)
484 intel_dp_check_edp(intel_dp);
487 msg[0] = AUX_NATIVE_WRITE << 4;
488 msg[1] = address >> 8;
489 msg[2] = address & 0xff;
490 msg[3] = send_bytes - 1;
491 memcpy(&msg[4], send, send_bytes);
492 msg_bytes = send_bytes + 4;
494 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
497 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
499 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
507 /* Write a single byte to the aux channel in native mode */
509 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
510 uint16_t address, uint8_t byte)
512 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
515 /* read bytes from a native aux channel */
517 intel_dp_aux_native_read(struct intel_dp *intel_dp,
518 uint16_t address, uint8_t *recv, int recv_bytes)
527 intel_dp_check_edp(intel_dp);
528 msg[0] = AUX_NATIVE_READ << 4;
529 msg[1] = address >> 8;
530 msg[2] = address & 0xff;
531 msg[3] = recv_bytes - 1;
534 reply_bytes = recv_bytes + 1;
537 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
544 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
545 memcpy(recv, reply + 1, ret - 1);
548 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
556 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
557 uint8_t write_byte, uint8_t *read_byte)
559 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
560 struct intel_dp *intel_dp = container_of(adapter,
563 uint16_t address = algo_data->address;
571 intel_dp_check_edp(intel_dp);
572 /* Set up the command byte */
573 if (mode & MODE_I2C_READ)
574 msg[0] = AUX_I2C_READ << 4;
576 msg[0] = AUX_I2C_WRITE << 4;
578 if (!(mode & MODE_I2C_STOP))
579 msg[0] |= AUX_I2C_MOT << 4;
581 msg[1] = address >> 8;
602 for (retry = 0; retry < 5; retry++) {
603 ret = intel_dp_aux_ch(intel_dp,
607 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
611 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
612 case AUX_NATIVE_REPLY_ACK:
613 /* I2C-over-AUX Reply field is only valid
614 * when paired with AUX ACK.
617 case AUX_NATIVE_REPLY_NACK:
618 DRM_DEBUG_KMS("aux_ch native nack\n");
620 case AUX_NATIVE_REPLY_DEFER:
624 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
629 switch (reply[0] & AUX_I2C_REPLY_MASK) {
630 case AUX_I2C_REPLY_ACK:
631 if (mode == MODE_I2C_READ) {
632 *read_byte = reply[1];
634 return reply_bytes - 1;
635 case AUX_I2C_REPLY_NACK:
636 DRM_DEBUG_KMS("aux_i2c nack\n");
638 case AUX_I2C_REPLY_DEFER:
639 DRM_DEBUG_KMS("aux_i2c defer\n");
643 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
648 DRM_ERROR("too many retries, giving up\n");
652 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
653 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
656 intel_dp_i2c_init(struct intel_dp *intel_dp,
657 struct intel_connector *intel_connector, const char *name)
661 DRM_DEBUG_KMS("i2c_init %s\n", name);
662 intel_dp->algo.running = false;
663 intel_dp->algo.address = 0;
664 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
666 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
667 intel_dp->adapter.owner = THIS_MODULE;
668 intel_dp->adapter.class = I2C_CLASS_DDC;
669 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
670 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
671 intel_dp->adapter.algo_data = &intel_dp->algo;
672 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
674 ironlake_edp_panel_vdd_on(intel_dp);
675 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
676 ironlake_edp_panel_vdd_off(intel_dp, false);
681 intel_dp_mode_fixup(struct drm_encoder *encoder,
682 const struct drm_display_mode *mode,
683 struct drm_display_mode *adjusted_mode)
685 struct drm_device *dev = encoder->dev;
686 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
687 struct intel_connector *intel_connector = intel_dp->attached_connector;
688 int lane_count, clock;
689 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
690 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
692 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
694 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
695 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
697 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
698 mode, adjusted_mode);
701 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
704 DRM_DEBUG_KMS("DP link computation with max lane count %i "
705 "max bw %02x pixel clock %iKHz\n",
706 max_lane_count, bws[max_clock], adjusted_mode->clock);
708 if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true))
711 bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
712 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
714 for (clock = 0; clock <= max_clock; clock++) {
715 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
716 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
718 if (mode_rate <= link_avail) {
719 intel_dp->link_bw = bws[clock];
720 intel_dp->lane_count = lane_count;
721 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
722 DRM_DEBUG_KMS("DP link bw %02x lane "
723 "count %d clock %d bpp %d\n",
724 intel_dp->link_bw, intel_dp->lane_count,
725 adjusted_mode->clock, bpp);
726 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
727 mode_rate, link_avail);
736 struct intel_dp_m_n {
745 intel_reduce_ratio(uint32_t *num, uint32_t *den)
747 while (*num > 0xffffff || *den > 0xffffff) {
754 intel_dp_compute_m_n(int bpp,
758 struct intel_dp_m_n *m_n)
761 m_n->gmch_m = (pixel_clock * bpp) >> 3;
762 m_n->gmch_n = link_clock * nlanes;
763 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
764 m_n->link_m = pixel_clock;
765 m_n->link_n = link_clock;
766 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
770 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
771 struct drm_display_mode *adjusted_mode)
773 struct drm_device *dev = crtc->dev;
774 struct intel_encoder *encoder;
775 struct drm_i915_private *dev_priv = dev->dev_private;
776 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
778 struct intel_dp_m_n m_n;
779 int pipe = intel_crtc->pipe;
782 * Find the lane count in the intel_encoder private
784 for_each_encoder_on_crtc(dev, crtc, encoder) {
785 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
787 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
788 intel_dp->base.type == INTEL_OUTPUT_EDP)
790 lane_count = intel_dp->lane_count;
796 * Compute the GMCH and Link ratios. The '3' here is
797 * the number of bytes_per_pixel post-LUT, which we always
798 * set up for 8-bits of R/G/B, or 3 bytes total.
800 intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
801 mode->clock, adjusted_mode->clock, &m_n);
803 if (IS_HASWELL(dev)) {
804 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
805 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
806 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
807 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
808 } else if (HAS_PCH_SPLIT(dev)) {
809 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
810 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
811 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
812 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
813 } else if (IS_VALLEYVIEW(dev)) {
814 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
815 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
816 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
817 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
819 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
820 TU_SIZE(m_n.tu) | m_n.gmch_m);
821 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
822 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
823 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
827 void intel_dp_init_link_config(struct intel_dp *intel_dp)
829 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
830 intel_dp->link_configuration[0] = intel_dp->link_bw;
831 intel_dp->link_configuration[1] = intel_dp->lane_count;
832 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
834 * Check for DPCD version > 1.1 and enhanced framing support
836 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
837 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
838 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
843 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
844 struct drm_display_mode *adjusted_mode)
846 struct drm_device *dev = encoder->dev;
847 struct drm_i915_private *dev_priv = dev->dev_private;
848 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
849 struct drm_crtc *crtc = intel_dp->base.base.crtc;
850 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
853 * There are four kinds of DP registers:
860 * IBX PCH and CPU are the same for almost everything,
861 * except that the CPU DP PLL is configured in this
864 * CPT PCH is quite different, having many bits moved
865 * to the TRANS_DP_CTL register instead. That
866 * configuration happens (oddly) in ironlake_pch_enable
869 /* Preserve the BIOS-computed detected bit. This is
870 * supposed to be read-only.
872 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
874 /* Handle DP bits in common between all three register formats */
875 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
877 switch (intel_dp->lane_count) {
879 intel_dp->DP |= DP_PORT_WIDTH_1;
882 intel_dp->DP |= DP_PORT_WIDTH_2;
885 intel_dp->DP |= DP_PORT_WIDTH_4;
888 if (intel_dp->has_audio) {
889 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
890 pipe_name(intel_crtc->pipe));
891 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
892 intel_write_eld(encoder, adjusted_mode);
895 intel_dp_init_link_config(intel_dp);
897 /* Split out the IBX/CPU vs CPT settings */
899 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
900 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
901 intel_dp->DP |= DP_SYNC_HS_HIGH;
902 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
903 intel_dp->DP |= DP_SYNC_VS_HIGH;
904 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
906 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
907 intel_dp->DP |= DP_ENHANCED_FRAMING;
909 intel_dp->DP |= intel_crtc->pipe << 29;
911 /* don't miss out required setting for eDP */
912 if (adjusted_mode->clock < 200000)
913 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
915 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
916 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
917 intel_dp->DP |= intel_dp->color_range;
919 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
920 intel_dp->DP |= DP_SYNC_HS_HIGH;
921 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
922 intel_dp->DP |= DP_SYNC_VS_HIGH;
923 intel_dp->DP |= DP_LINK_TRAIN_OFF;
925 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
926 intel_dp->DP |= DP_ENHANCED_FRAMING;
928 if (intel_crtc->pipe == 1)
929 intel_dp->DP |= DP_PIPEB_SELECT;
931 if (is_cpu_edp(intel_dp)) {
932 /* don't miss out required setting for eDP */
933 if (adjusted_mode->clock < 200000)
934 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
936 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
939 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
943 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
944 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
946 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
947 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
949 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
950 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
952 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
956 struct drm_device *dev = intel_dp->base.base.dev;
957 struct drm_i915_private *dev_priv = dev->dev_private;
959 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
961 I915_READ(PCH_PP_STATUS),
962 I915_READ(PCH_PP_CONTROL));
964 if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
965 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
966 I915_READ(PCH_PP_STATUS),
967 I915_READ(PCH_PP_CONTROL));
971 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
973 DRM_DEBUG_KMS("Wait for panel power on\n");
974 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
977 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
979 DRM_DEBUG_KMS("Wait for panel power off time\n");
980 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
983 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
985 DRM_DEBUG_KMS("Wait for panel power cycle\n");
986 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
990 /* Read the current pp_control value, unlocking the register if it
994 static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
996 u32 control = I915_READ(PCH_PP_CONTROL);
998 control &= ~PANEL_UNLOCK_MASK;
999 control |= PANEL_UNLOCK_REGS;
1003 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1005 struct drm_device *dev = intel_dp->base.base.dev;
1006 struct drm_i915_private *dev_priv = dev->dev_private;
1009 if (!is_edp(intel_dp))
1011 DRM_DEBUG_KMS("Turn eDP VDD on\n");
1013 WARN(intel_dp->want_panel_vdd,
1014 "eDP VDD already requested on\n");
1016 intel_dp->want_panel_vdd = true;
1018 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1019 DRM_DEBUG_KMS("eDP VDD already on\n");
1023 if (!ironlake_edp_have_panel_power(intel_dp))
1024 ironlake_wait_panel_power_cycle(intel_dp);
1026 pp = ironlake_get_pp_control(dev_priv);
1027 pp |= EDP_FORCE_VDD;
1028 I915_WRITE(PCH_PP_CONTROL, pp);
1029 POSTING_READ(PCH_PP_CONTROL);
1030 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1031 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1034 * If the panel wasn't on, delay before accessing aux channel
1036 if (!ironlake_edp_have_panel_power(intel_dp)) {
1037 DRM_DEBUG_KMS("eDP was not running\n");
1038 msleep(intel_dp->panel_power_up_delay);
1042 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1044 struct drm_device *dev = intel_dp->base.base.dev;
1045 struct drm_i915_private *dev_priv = dev->dev_private;
1048 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1049 pp = ironlake_get_pp_control(dev_priv);
1050 pp &= ~EDP_FORCE_VDD;
1051 I915_WRITE(PCH_PP_CONTROL, pp);
1052 POSTING_READ(PCH_PP_CONTROL);
1054 /* Make sure sequencer is idle before allowing subsequent activity */
1055 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1056 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1058 msleep(intel_dp->panel_power_down_delay);
1062 static void ironlake_panel_vdd_work(struct work_struct *__work)
1064 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1065 struct intel_dp, panel_vdd_work);
1066 struct drm_device *dev = intel_dp->base.base.dev;
1068 mutex_lock(&dev->mode_config.mutex);
1069 ironlake_panel_vdd_off_sync(intel_dp);
1070 mutex_unlock(&dev->mode_config.mutex);
1073 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1075 if (!is_edp(intel_dp))
1078 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1079 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1081 intel_dp->want_panel_vdd = false;
1084 ironlake_panel_vdd_off_sync(intel_dp);
1087 * Queue the timer to fire a long
1088 * time from now (relative to the power down delay)
1089 * to keep the panel power up across a sequence of operations
1091 schedule_delayed_work(&intel_dp->panel_vdd_work,
1092 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1096 static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1098 struct drm_device *dev = intel_dp->base.base.dev;
1099 struct drm_i915_private *dev_priv = dev->dev_private;
1102 if (!is_edp(intel_dp))
1105 DRM_DEBUG_KMS("Turn eDP power on\n");
1107 if (ironlake_edp_have_panel_power(intel_dp)) {
1108 DRM_DEBUG_KMS("eDP power already on\n");
1112 ironlake_wait_panel_power_cycle(intel_dp);
1114 pp = ironlake_get_pp_control(dev_priv);
1116 /* ILK workaround: disable reset around power sequence */
1117 pp &= ~PANEL_POWER_RESET;
1118 I915_WRITE(PCH_PP_CONTROL, pp);
1119 POSTING_READ(PCH_PP_CONTROL);
1122 pp |= POWER_TARGET_ON;
1124 pp |= PANEL_POWER_RESET;
1126 I915_WRITE(PCH_PP_CONTROL, pp);
1127 POSTING_READ(PCH_PP_CONTROL);
1129 ironlake_wait_panel_on(intel_dp);
1132 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1133 I915_WRITE(PCH_PP_CONTROL, pp);
1134 POSTING_READ(PCH_PP_CONTROL);
1138 static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1140 struct drm_device *dev = intel_dp->base.base.dev;
1141 struct drm_i915_private *dev_priv = dev->dev_private;
1144 if (!is_edp(intel_dp))
1147 DRM_DEBUG_KMS("Turn eDP power off\n");
1149 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1151 pp = ironlake_get_pp_control(dev_priv);
1152 /* We need to switch off panel power _and_ force vdd, for otherwise some
1153 * panels get very unhappy and cease to work. */
1154 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1155 I915_WRITE(PCH_PP_CONTROL, pp);
1156 POSTING_READ(PCH_PP_CONTROL);
1158 intel_dp->want_panel_vdd = false;
1160 ironlake_wait_panel_off(intel_dp);
1163 static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1165 struct drm_device *dev = intel_dp->base.base.dev;
1166 struct drm_i915_private *dev_priv = dev->dev_private;
1167 int pipe = to_intel_crtc(intel_dp->base.base.crtc)->pipe;
1170 if (!is_edp(intel_dp))
1173 DRM_DEBUG_KMS("\n");
1175 * If we enable the backlight right away following a panel power
1176 * on, we may see slight flicker as the panel syncs with the eDP
1177 * link. So delay a bit to make sure the image is solid before
1178 * allowing it to appear.
1180 msleep(intel_dp->backlight_on_delay);
1181 pp = ironlake_get_pp_control(dev_priv);
1182 pp |= EDP_BLC_ENABLE;
1183 I915_WRITE(PCH_PP_CONTROL, pp);
1184 POSTING_READ(PCH_PP_CONTROL);
1186 intel_panel_enable_backlight(dev, pipe);
1189 static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1191 struct drm_device *dev = intel_dp->base.base.dev;
1192 struct drm_i915_private *dev_priv = dev->dev_private;
1195 if (!is_edp(intel_dp))
1198 intel_panel_disable_backlight(dev);
1200 DRM_DEBUG_KMS("\n");
1201 pp = ironlake_get_pp_control(dev_priv);
1202 pp &= ~EDP_BLC_ENABLE;
1203 I915_WRITE(PCH_PP_CONTROL, pp);
1204 POSTING_READ(PCH_PP_CONTROL);
1205 msleep(intel_dp->backlight_off_delay);
1208 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1210 struct drm_device *dev = intel_dp->base.base.dev;
1211 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1212 struct drm_i915_private *dev_priv = dev->dev_private;
1215 assert_pipe_disabled(dev_priv,
1216 to_intel_crtc(crtc)->pipe);
1218 DRM_DEBUG_KMS("\n");
1219 dpa_ctl = I915_READ(DP_A);
1220 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1221 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1223 /* We don't adjust intel_dp->DP while tearing down the link, to
1224 * facilitate link retraining (e.g. after hotplug). Hence clear all
1225 * enable bits here to ensure that we don't enable too much. */
1226 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1227 intel_dp->DP |= DP_PLL_ENABLE;
1228 I915_WRITE(DP_A, intel_dp->DP);
1233 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1235 struct drm_device *dev = intel_dp->base.base.dev;
1236 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1237 struct drm_i915_private *dev_priv = dev->dev_private;
1240 assert_pipe_disabled(dev_priv,
1241 to_intel_crtc(crtc)->pipe);
1243 dpa_ctl = I915_READ(DP_A);
1244 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1245 "dp pll off, should be on\n");
1246 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1248 /* We can't rely on the value tracked for the DP register in
1249 * intel_dp->DP because link_down must not change that (otherwise link
1250 * re-training will fail. */
1251 dpa_ctl &= ~DP_PLL_ENABLE;
1252 I915_WRITE(DP_A, dpa_ctl);
1257 /* If the sink supports it, try to set the power state appropriately */
1258 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1262 /* Should have a valid DPCD by this point */
1263 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1266 if (mode != DRM_MODE_DPMS_ON) {
1267 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1270 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1273 * When turning on, we need to retry for 1ms to give the sink
1276 for (i = 0; i < 3; i++) {
1277 ret = intel_dp_aux_native_write_1(intel_dp,
1287 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1290 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1291 struct drm_device *dev = encoder->base.dev;
1292 struct drm_i915_private *dev_priv = dev->dev_private;
1293 u32 tmp = I915_READ(intel_dp->output_reg);
1295 if (!(tmp & DP_PORT_EN))
1298 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
1299 *pipe = PORT_TO_PIPE_CPT(tmp);
1300 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1301 *pipe = PORT_TO_PIPE(tmp);
1307 switch (intel_dp->output_reg) {
1309 trans_sel = TRANS_DP_PORT_SEL_B;
1312 trans_sel = TRANS_DP_PORT_SEL_C;
1315 trans_sel = TRANS_DP_PORT_SEL_D;
1322 trans_dp = I915_READ(TRANS_DP_CTL(i));
1323 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1330 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", intel_dp->output_reg);
1335 static void intel_disable_dp(struct intel_encoder *encoder)
1337 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1339 /* Make sure the panel is off before trying to change the mode. But also
1340 * ensure that we have vdd while we switch off the panel. */
1341 ironlake_edp_panel_vdd_on(intel_dp);
1342 ironlake_edp_backlight_off(intel_dp);
1343 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1344 ironlake_edp_panel_off(intel_dp);
1346 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1347 if (!is_cpu_edp(intel_dp))
1348 intel_dp_link_down(intel_dp);
1351 static void intel_post_disable_dp(struct intel_encoder *encoder)
1353 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1355 if (is_cpu_edp(intel_dp)) {
1356 intel_dp_link_down(intel_dp);
1357 ironlake_edp_pll_off(intel_dp);
1361 static void intel_enable_dp(struct intel_encoder *encoder)
1363 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1364 struct drm_device *dev = encoder->base.dev;
1365 struct drm_i915_private *dev_priv = dev->dev_private;
1366 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1368 if (WARN_ON(dp_reg & DP_PORT_EN))
1371 ironlake_edp_panel_vdd_on(intel_dp);
1372 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1373 intel_dp_start_link_train(intel_dp);
1374 ironlake_edp_panel_on(intel_dp);
1375 ironlake_edp_panel_vdd_off(intel_dp, true);
1376 intel_dp_complete_link_train(intel_dp);
1377 ironlake_edp_backlight_on(intel_dp);
1380 static void intel_pre_enable_dp(struct intel_encoder *encoder)
1382 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1384 if (is_cpu_edp(intel_dp))
1385 ironlake_edp_pll_on(intel_dp);
1389 * Native read with retry for link status and receiver capability reads for
1390 * cases where the sink may still be asleep.
1393 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1394 uint8_t *recv, int recv_bytes)
1399 * Sinks are *supposed* to come up within 1ms from an off state,
1400 * but we're also supposed to retry 3 times per the spec.
1402 for (i = 0; i < 3; i++) {
1403 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1405 if (ret == recv_bytes)
1414 * Fetch AUX CH registers 0x202 - 0x207 which contain
1415 * link status information
1418 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1420 return intel_dp_aux_native_read_retry(intel_dp,
1423 DP_LINK_STATUS_SIZE);
1427 static char *voltage_names[] = {
1428 "0.4V", "0.6V", "0.8V", "1.2V"
1430 static char *pre_emph_names[] = {
1431 "0dB", "3.5dB", "6dB", "9.5dB"
1433 static char *link_train_names[] = {
1434 "pattern 1", "pattern 2", "idle", "off"
1439 * These are source-specific values; current Intel hardware supports
1440 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1444 intel_dp_voltage_max(struct intel_dp *intel_dp)
1446 struct drm_device *dev = intel_dp->base.base.dev;
1448 if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1449 return DP_TRAIN_VOLTAGE_SWING_800;
1450 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1451 return DP_TRAIN_VOLTAGE_SWING_1200;
1453 return DP_TRAIN_VOLTAGE_SWING_800;
1457 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1459 struct drm_device *dev = intel_dp->base.base.dev;
1461 if (IS_HASWELL(dev)) {
1462 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1463 case DP_TRAIN_VOLTAGE_SWING_400:
1464 return DP_TRAIN_PRE_EMPHASIS_9_5;
1465 case DP_TRAIN_VOLTAGE_SWING_600:
1466 return DP_TRAIN_PRE_EMPHASIS_6;
1467 case DP_TRAIN_VOLTAGE_SWING_800:
1468 return DP_TRAIN_PRE_EMPHASIS_3_5;
1469 case DP_TRAIN_VOLTAGE_SWING_1200:
1471 return DP_TRAIN_PRE_EMPHASIS_0;
1473 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1474 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1475 case DP_TRAIN_VOLTAGE_SWING_400:
1476 return DP_TRAIN_PRE_EMPHASIS_6;
1477 case DP_TRAIN_VOLTAGE_SWING_600:
1478 case DP_TRAIN_VOLTAGE_SWING_800:
1479 return DP_TRAIN_PRE_EMPHASIS_3_5;
1481 return DP_TRAIN_PRE_EMPHASIS_0;
1484 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1485 case DP_TRAIN_VOLTAGE_SWING_400:
1486 return DP_TRAIN_PRE_EMPHASIS_6;
1487 case DP_TRAIN_VOLTAGE_SWING_600:
1488 return DP_TRAIN_PRE_EMPHASIS_6;
1489 case DP_TRAIN_VOLTAGE_SWING_800:
1490 return DP_TRAIN_PRE_EMPHASIS_3_5;
1491 case DP_TRAIN_VOLTAGE_SWING_1200:
1493 return DP_TRAIN_PRE_EMPHASIS_0;
1499 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1504 uint8_t voltage_max;
1505 uint8_t preemph_max;
1507 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1508 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1509 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
1517 voltage_max = intel_dp_voltage_max(intel_dp);
1518 if (v >= voltage_max)
1519 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1521 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1522 if (p >= preemph_max)
1523 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1525 for (lane = 0; lane < 4; lane++)
1526 intel_dp->train_set[lane] = v | p;
1530 intel_dp_signal_levels(uint8_t train_set)
1532 uint32_t signal_levels = 0;
1534 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1535 case DP_TRAIN_VOLTAGE_SWING_400:
1537 signal_levels |= DP_VOLTAGE_0_4;
1539 case DP_TRAIN_VOLTAGE_SWING_600:
1540 signal_levels |= DP_VOLTAGE_0_6;
1542 case DP_TRAIN_VOLTAGE_SWING_800:
1543 signal_levels |= DP_VOLTAGE_0_8;
1545 case DP_TRAIN_VOLTAGE_SWING_1200:
1546 signal_levels |= DP_VOLTAGE_1_2;
1549 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1550 case DP_TRAIN_PRE_EMPHASIS_0:
1552 signal_levels |= DP_PRE_EMPHASIS_0;
1554 case DP_TRAIN_PRE_EMPHASIS_3_5:
1555 signal_levels |= DP_PRE_EMPHASIS_3_5;
1557 case DP_TRAIN_PRE_EMPHASIS_6:
1558 signal_levels |= DP_PRE_EMPHASIS_6;
1560 case DP_TRAIN_PRE_EMPHASIS_9_5:
1561 signal_levels |= DP_PRE_EMPHASIS_9_5;
1564 return signal_levels;
1567 /* Gen6's DP voltage swing and pre-emphasis control */
1569 intel_gen6_edp_signal_levels(uint8_t train_set)
1571 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1572 DP_TRAIN_PRE_EMPHASIS_MASK);
1573 switch (signal_levels) {
1574 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1575 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1576 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1577 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1578 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1579 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1580 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1581 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1582 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1583 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1584 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1585 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1586 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1587 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1589 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1590 "0x%x\n", signal_levels);
1591 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1595 /* Gen7's DP voltage swing and pre-emphasis control */
1597 intel_gen7_edp_signal_levels(uint8_t train_set)
1599 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1600 DP_TRAIN_PRE_EMPHASIS_MASK);
1601 switch (signal_levels) {
1602 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1603 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1604 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1605 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1606 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1607 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1609 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1610 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1611 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1612 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1614 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1615 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1616 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1617 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1620 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1621 "0x%x\n", signal_levels);
1622 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1626 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1628 intel_dp_signal_levels_hsw(uint8_t train_set)
1630 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1631 DP_TRAIN_PRE_EMPHASIS_MASK);
1632 switch (signal_levels) {
1633 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1634 return DDI_BUF_EMP_400MV_0DB_HSW;
1635 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1636 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1637 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1638 return DDI_BUF_EMP_400MV_6DB_HSW;
1639 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1640 return DDI_BUF_EMP_400MV_9_5DB_HSW;
1642 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1643 return DDI_BUF_EMP_600MV_0DB_HSW;
1644 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1645 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1646 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1647 return DDI_BUF_EMP_600MV_6DB_HSW;
1649 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1650 return DDI_BUF_EMP_800MV_0DB_HSW;
1651 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1652 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1654 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1655 "0x%x\n", signal_levels);
1656 return DDI_BUF_EMP_400MV_0DB_HSW;
1661 intel_dp_set_link_train(struct intel_dp *intel_dp,
1662 uint32_t dp_reg_value,
1663 uint8_t dp_train_pat)
1665 struct drm_device *dev = intel_dp->base.base.dev;
1666 struct drm_i915_private *dev_priv = dev->dev_private;
1670 if (IS_HASWELL(dev)) {
1671 temp = I915_READ(DP_TP_CTL(intel_dp->port));
1673 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1674 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1676 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1678 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1679 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1680 case DP_TRAINING_PATTERN_DISABLE:
1681 temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
1682 I915_WRITE(DP_TP_CTL(intel_dp->port), temp);
1684 if (wait_for((I915_READ(DP_TP_STATUS(intel_dp->port)) &
1685 DP_TP_STATUS_IDLE_DONE), 1))
1686 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1688 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1689 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1692 case DP_TRAINING_PATTERN_1:
1693 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1695 case DP_TRAINING_PATTERN_2:
1696 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1698 case DP_TRAINING_PATTERN_3:
1699 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1702 I915_WRITE(DP_TP_CTL(intel_dp->port), temp);
1704 } else if (HAS_PCH_CPT(dev) &&
1705 (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1706 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1708 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1709 case DP_TRAINING_PATTERN_DISABLE:
1710 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1712 case DP_TRAINING_PATTERN_1:
1713 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1715 case DP_TRAINING_PATTERN_2:
1716 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1718 case DP_TRAINING_PATTERN_3:
1719 DRM_ERROR("DP training pattern 3 not supported\n");
1720 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1725 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1727 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1728 case DP_TRAINING_PATTERN_DISABLE:
1729 dp_reg_value |= DP_LINK_TRAIN_OFF;
1731 case DP_TRAINING_PATTERN_1:
1732 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1734 case DP_TRAINING_PATTERN_2:
1735 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1737 case DP_TRAINING_PATTERN_3:
1738 DRM_ERROR("DP training pattern 3 not supported\n");
1739 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1744 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1745 POSTING_READ(intel_dp->output_reg);
1747 intel_dp_aux_native_write_1(intel_dp,
1748 DP_TRAINING_PATTERN_SET,
1751 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1752 DP_TRAINING_PATTERN_DISABLE) {
1753 ret = intel_dp_aux_native_write(intel_dp,
1754 DP_TRAINING_LANE0_SET,
1755 intel_dp->train_set,
1756 intel_dp->lane_count);
1757 if (ret != intel_dp->lane_count)
1764 /* Enable corresponding port and start training pattern 1 */
1766 intel_dp_start_link_train(struct intel_dp *intel_dp)
1768 struct drm_encoder *encoder = &intel_dp->base.base;
1769 struct drm_device *dev = encoder->dev;
1772 bool clock_recovery = false;
1773 int voltage_tries, loop_tries;
1774 uint32_t DP = intel_dp->DP;
1776 if (IS_HASWELL(dev))
1777 intel_ddi_prepare_link_retrain(encoder);
1779 /* Write the link configuration data */
1780 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1781 intel_dp->link_configuration,
1782 DP_LINK_CONFIGURATION_SIZE);
1786 memset(intel_dp->train_set, 0, 4);
1790 clock_recovery = false;
1792 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1793 uint8_t link_status[DP_LINK_STATUS_SIZE];
1794 uint32_t signal_levels;
1796 if (IS_HASWELL(dev)) {
1797 signal_levels = intel_dp_signal_levels_hsw(
1798 intel_dp->train_set[0]);
1799 DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
1800 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1801 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1802 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1803 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1804 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1805 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1807 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1808 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1810 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n",
1813 /* Set training pattern 1 */
1814 if (!intel_dp_set_link_train(intel_dp, DP,
1815 DP_TRAINING_PATTERN_1 |
1816 DP_LINK_SCRAMBLING_DISABLE))
1819 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
1820 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1821 DRM_ERROR("failed to get link status\n");
1825 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1826 DRM_DEBUG_KMS("clock recovery OK\n");
1827 clock_recovery = true;
1831 /* Check to see if we've tried the max voltage */
1832 for (i = 0; i < intel_dp->lane_count; i++)
1833 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1835 if (i == intel_dp->lane_count && voltage_tries == 5) {
1836 if (++loop_tries == 5) {
1837 DRM_DEBUG_KMS("too many full retries, give up\n");
1840 memset(intel_dp->train_set, 0, 4);
1845 /* Check to see if we've tried the same voltage 5 times */
1846 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) {
1847 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1852 /* Compute new intel_dp->train_set as requested by target */
1853 intel_get_adjust_train(intel_dp, link_status);
1860 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1862 struct drm_device *dev = intel_dp->base.base.dev;
1863 bool channel_eq = false;
1864 int tries, cr_tries;
1865 uint32_t DP = intel_dp->DP;
1867 /* channel equalization */
1872 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1873 uint32_t signal_levels;
1874 uint8_t link_status[DP_LINK_STATUS_SIZE];
1877 DRM_ERROR("failed to train DP, aborting\n");
1878 intel_dp_link_down(intel_dp);
1882 if (IS_HASWELL(dev)) {
1883 signal_levels = intel_dp_signal_levels_hsw(intel_dp->train_set[0]);
1884 DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
1885 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1886 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1887 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1888 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1889 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1890 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1892 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1893 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1896 /* channel eq pattern */
1897 if (!intel_dp_set_link_train(intel_dp, DP,
1898 DP_TRAINING_PATTERN_2 |
1899 DP_LINK_SCRAMBLING_DISABLE))
1902 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
1903 if (!intel_dp_get_link_status(intel_dp, link_status))
1906 /* Make sure clock is still ok */
1907 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1908 intel_dp_start_link_train(intel_dp);
1913 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
1918 /* Try 5 times, then try clock recovery if that fails */
1920 intel_dp_link_down(intel_dp);
1921 intel_dp_start_link_train(intel_dp);
1927 /* Compute new intel_dp->train_set as requested by target */
1928 intel_get_adjust_train(intel_dp, link_status);
1933 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
1935 intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
1939 intel_dp_link_down(struct intel_dp *intel_dp)
1941 struct drm_device *dev = intel_dp->base.base.dev;
1942 struct drm_i915_private *dev_priv = dev->dev_private;
1943 uint32_t DP = intel_dp->DP;
1946 * DDI code has a strict mode set sequence and we should try to respect
1947 * it, otherwise we might hang the machine in many different ways. So we
1948 * really should be disabling the port only on a complete crtc_disable
1949 * sequence. This function is just called under two conditions on DDI
1951 * - Link train failed while doing crtc_enable, and on this case we
1952 * really should respect the mode set sequence and wait for a
1954 * - Someone turned the monitor off and intel_dp_check_link_status
1955 * called us. We don't need to disable the whole port on this case, so
1956 * when someone turns the monitor on again,
1957 * intel_ddi_prepare_link_retrain will take care of redoing the link
1960 if (IS_HASWELL(dev))
1963 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1966 DRM_DEBUG_KMS("\n");
1968 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1969 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1970 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1972 DP &= ~DP_LINK_TRAIN_MASK;
1973 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1975 POSTING_READ(intel_dp->output_reg);
1979 if (HAS_PCH_IBX(dev) &&
1980 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
1981 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1983 /* Hardware workaround: leaving our transcoder select
1984 * set to transcoder B while it's off will prevent the
1985 * corresponding HDMI output on transcoder A.
1987 * Combine this with another hardware workaround:
1988 * transcoder select bit can only be cleared while the
1991 DP &= ~DP_PIPEB_SELECT;
1992 I915_WRITE(intel_dp->output_reg, DP);
1994 /* Changes to enable or select take place the vblank
1995 * after being written.
1998 /* We can arrive here never having been attached
1999 * to a CRTC, for instance, due to inheriting
2000 * random state from the BIOS.
2002 * If the pipe is not running, play safe and
2003 * wait for the clocks to stabilise before
2006 POSTING_READ(intel_dp->output_reg);
2009 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
2012 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2013 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2014 POSTING_READ(intel_dp->output_reg);
2015 msleep(intel_dp->panel_power_down_delay);
2019 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2021 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2022 sizeof(intel_dp->dpcd)) == 0)
2023 return false; /* aux transfer failed */
2025 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2026 return false; /* DPCD not present */
2028 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2029 DP_DWN_STRM_PORT_PRESENT))
2030 return true; /* native DP sink */
2032 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2033 return true; /* no per-port downstream info */
2035 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2036 intel_dp->downstream_ports,
2037 DP_MAX_DOWNSTREAM_PORTS) == 0)
2038 return false; /* downstream port status fetch failed */
2044 intel_dp_probe_oui(struct intel_dp *intel_dp)
2048 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2051 ironlake_edp_panel_vdd_on(intel_dp);
2053 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2054 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2055 buf[0], buf[1], buf[2]);
2057 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2058 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2059 buf[0], buf[1], buf[2]);
2061 ironlake_edp_panel_vdd_off(intel_dp, false);
2065 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2069 ret = intel_dp_aux_native_read_retry(intel_dp,
2070 DP_DEVICE_SERVICE_IRQ_VECTOR,
2071 sink_irq_vector, 1);
2079 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2081 /* NAK by default */
2082 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2086 * According to DP spec
2089 * 2. Configure link according to Receiver Capabilities
2090 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2091 * 4. Check link status on receipt of hot-plug interrupt
2095 intel_dp_check_link_status(struct intel_dp *intel_dp)
2098 u8 link_status[DP_LINK_STATUS_SIZE];
2100 if (!intel_dp->base.connectors_active)
2103 if (WARN_ON(!intel_dp->base.base.crtc))
2106 /* Try to read receiver status if the link appears to be up */
2107 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2108 intel_dp_link_down(intel_dp);
2112 /* Now read the DPCD to see if it's actually running */
2113 if (!intel_dp_get_dpcd(intel_dp)) {
2114 intel_dp_link_down(intel_dp);
2118 /* Try to read the source of the interrupt */
2119 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2120 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2121 /* Clear interrupt source */
2122 intel_dp_aux_native_write_1(intel_dp,
2123 DP_DEVICE_SERVICE_IRQ_VECTOR,
2126 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2127 intel_dp_handle_test_request(intel_dp);
2128 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2129 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2132 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2133 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2134 drm_get_encoder_name(&intel_dp->base.base));
2135 intel_dp_start_link_train(intel_dp);
2136 intel_dp_complete_link_train(intel_dp);
2140 /* XXX this is probably wrong for multiple downstream ports */
2141 static enum drm_connector_status
2142 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2144 uint8_t *dpcd = intel_dp->dpcd;
2148 if (!intel_dp_get_dpcd(intel_dp))
2149 return connector_status_disconnected;
2151 /* if there's no downstream port, we're done */
2152 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2153 return connector_status_connected;
2155 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2156 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2159 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2161 return connector_status_unknown;
2162 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2163 : connector_status_disconnected;
2166 /* If no HPD, poke DDC gently */
2167 if (drm_probe_ddc(&intel_dp->adapter))
2168 return connector_status_connected;
2170 /* Well we tried, say unknown for unreliable port types */
2171 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2172 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2173 return connector_status_unknown;
2175 /* Anything else is out of spec, warn and ignore */
2176 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2177 return connector_status_disconnected;
2180 static enum drm_connector_status
2181 ironlake_dp_detect(struct intel_dp *intel_dp)
2183 enum drm_connector_status status;
2185 /* Can't disconnect eDP, but you can close the lid... */
2186 if (is_edp(intel_dp)) {
2187 status = intel_panel_detect(intel_dp->base.base.dev);
2188 if (status == connector_status_unknown)
2189 status = connector_status_connected;
2193 return intel_dp_detect_dpcd(intel_dp);
2196 static enum drm_connector_status
2197 g4x_dp_detect(struct intel_dp *intel_dp)
2199 struct drm_device *dev = intel_dp->base.base.dev;
2200 struct drm_i915_private *dev_priv = dev->dev_private;
2203 switch (intel_dp->output_reg) {
2205 bit = DPB_HOTPLUG_LIVE_STATUS;
2208 bit = DPC_HOTPLUG_LIVE_STATUS;
2211 bit = DPD_HOTPLUG_LIVE_STATUS;
2214 return connector_status_unknown;
2217 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2218 return connector_status_disconnected;
2220 return intel_dp_detect_dpcd(intel_dp);
2223 static struct edid *
2224 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2226 struct intel_connector *intel_connector = to_intel_connector(connector);
2228 /* use cached edid if we have one */
2229 if (intel_connector->edid) {
2234 if (IS_ERR(intel_connector->edid))
2237 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
2238 edid = kmalloc(size, GFP_KERNEL);
2242 memcpy(edid, intel_connector->edid, size);
2246 return drm_get_edid(connector, adapter);
2250 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2252 struct intel_connector *intel_connector = to_intel_connector(connector);
2254 /* use cached edid if we have one */
2255 if (intel_connector->edid) {
2257 if (IS_ERR(intel_connector->edid))
2260 return intel_connector_update_modes(connector,
2261 intel_connector->edid);
2264 return intel_ddc_get_modes(connector, adapter);
2269 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2271 * \return true if DP port is connected.
2272 * \return false if DP port is disconnected.
2274 static enum drm_connector_status
2275 intel_dp_detect(struct drm_connector *connector, bool force)
2277 struct intel_dp *intel_dp = intel_attached_dp(connector);
2278 struct drm_device *dev = intel_dp->base.base.dev;
2279 enum drm_connector_status status;
2280 struct edid *edid = NULL;
2282 intel_dp->has_audio = false;
2284 if (HAS_PCH_SPLIT(dev))
2285 status = ironlake_dp_detect(intel_dp);
2287 status = g4x_dp_detect(intel_dp);
2289 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2290 intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
2291 intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
2292 intel_dp->dpcd[6], intel_dp->dpcd[7]);
2294 if (status != connector_status_connected)
2297 intel_dp_probe_oui(intel_dp);
2299 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2300 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2302 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2304 intel_dp->has_audio = drm_detect_monitor_audio(edid);
2309 return connector_status_connected;
2312 static int intel_dp_get_modes(struct drm_connector *connector)
2314 struct intel_dp *intel_dp = intel_attached_dp(connector);
2315 struct intel_connector *intel_connector = to_intel_connector(connector);
2316 struct drm_device *dev = intel_dp->base.base.dev;
2319 /* We should parse the EDID data and find out if it has an audio sink
2322 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2326 /* if eDP has no EDID, fall back to fixed mode */
2327 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2328 struct drm_display_mode *mode;
2329 mode = drm_mode_duplicate(dev,
2330 intel_connector->panel.fixed_mode);
2332 drm_mode_probed_add(connector, mode);
2340 intel_dp_detect_audio(struct drm_connector *connector)
2342 struct intel_dp *intel_dp = intel_attached_dp(connector);
2344 bool has_audio = false;
2346 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2348 has_audio = drm_detect_monitor_audio(edid);
2356 intel_dp_set_property(struct drm_connector *connector,
2357 struct drm_property *property,
2360 struct drm_i915_private *dev_priv = connector->dev->dev_private;
2361 struct intel_dp *intel_dp = intel_attached_dp(connector);
2364 ret = drm_connector_property_set_value(connector, property, val);
2368 if (property == dev_priv->force_audio_property) {
2372 if (i == intel_dp->force_audio)
2375 intel_dp->force_audio = i;
2377 if (i == HDMI_AUDIO_AUTO)
2378 has_audio = intel_dp_detect_audio(connector);
2380 has_audio = (i == HDMI_AUDIO_ON);
2382 if (has_audio == intel_dp->has_audio)
2385 intel_dp->has_audio = has_audio;
2389 if (property == dev_priv->broadcast_rgb_property) {
2390 if (val == !!intel_dp->color_range)
2393 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2400 if (intel_dp->base.base.crtc) {
2401 struct drm_crtc *crtc = intel_dp->base.base.crtc;
2402 intel_set_mode(crtc, &crtc->mode,
2403 crtc->x, crtc->y, crtc->fb);
2410 intel_dp_destroy(struct drm_connector *connector)
2412 struct drm_device *dev = connector->dev;
2413 struct intel_dp *intel_dp = intel_attached_dp(connector);
2414 struct intel_connector *intel_connector = to_intel_connector(connector);
2416 if (!IS_ERR_OR_NULL(intel_connector->edid))
2417 kfree(intel_connector->edid);
2419 if (is_edp(intel_dp)) {
2420 intel_panel_destroy_backlight(dev);
2421 intel_panel_fini(&intel_connector->panel);
2424 drm_sysfs_connector_remove(connector);
2425 drm_connector_cleanup(connector);
2429 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2431 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2433 i2c_del_adapter(&intel_dp->adapter);
2434 drm_encoder_cleanup(encoder);
2435 if (is_edp(intel_dp)) {
2436 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2437 ironlake_panel_vdd_off_sync(intel_dp);
2442 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2443 .mode_fixup = intel_dp_mode_fixup,
2444 .mode_set = intel_dp_mode_set,
2445 .disable = intel_encoder_noop,
2448 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs_hsw = {
2449 .mode_fixup = intel_dp_mode_fixup,
2450 .mode_set = intel_ddi_mode_set,
2451 .disable = intel_encoder_noop,
2454 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2455 .dpms = intel_connector_dpms,
2456 .detect = intel_dp_detect,
2457 .fill_modes = drm_helper_probe_single_connector_modes,
2458 .set_property = intel_dp_set_property,
2459 .destroy = intel_dp_destroy,
2462 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2463 .get_modes = intel_dp_get_modes,
2464 .mode_valid = intel_dp_mode_valid,
2465 .best_encoder = intel_best_encoder,
2468 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2469 .destroy = intel_dp_encoder_destroy,
2473 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2475 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
2477 intel_dp_check_link_status(intel_dp);
2480 /* Return which DP Port should be selected for Transcoder DP control */
2482 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2484 struct drm_device *dev = crtc->dev;
2485 struct intel_encoder *encoder;
2487 for_each_encoder_on_crtc(dev, crtc, encoder) {
2488 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2490 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
2491 intel_dp->base.type == INTEL_OUTPUT_EDP)
2492 return intel_dp->output_reg;
2498 /* check the VBT to see whether the eDP is on DP-D port */
2499 bool intel_dpd_is_edp(struct drm_device *dev)
2501 struct drm_i915_private *dev_priv = dev->dev_private;
2502 struct child_device_config *p_child;
2505 if (!dev_priv->child_dev_num)
2508 for (i = 0; i < dev_priv->child_dev_num; i++) {
2509 p_child = dev_priv->child_dev + i;
2511 if (p_child->dvo_port == PORT_IDPD &&
2512 p_child->device_type == DEVICE_TYPE_eDP)
2519 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2521 intel_attach_force_audio_property(connector);
2522 intel_attach_broadcast_rgb_property(connector);
2526 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
2527 struct intel_dp *intel_dp)
2529 struct drm_i915_private *dev_priv = dev->dev_private;
2530 struct edp_power_seq cur, vbt, spec, final;
2531 u32 pp_on, pp_off, pp_div, pp;
2533 /* Workaround: Need to write PP_CONTROL with the unlock key as
2534 * the very first thing. */
2535 pp = ironlake_get_pp_control(dev_priv);
2536 I915_WRITE(PCH_PP_CONTROL, pp);
2538 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2539 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2540 pp_div = I915_READ(PCH_PP_DIVISOR);
2542 /* Pull timing values out of registers */
2543 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2544 PANEL_POWER_UP_DELAY_SHIFT;
2546 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2547 PANEL_LIGHT_ON_DELAY_SHIFT;
2549 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2550 PANEL_LIGHT_OFF_DELAY_SHIFT;
2552 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2553 PANEL_POWER_DOWN_DELAY_SHIFT;
2555 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2556 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2558 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2559 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2561 vbt = dev_priv->edp.pps;
2563 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2564 * our hw here, which are all in 100usec. */
2565 spec.t1_t3 = 210 * 10;
2566 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2567 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2568 spec.t10 = 500 * 10;
2569 /* This one is special and actually in units of 100ms, but zero
2570 * based in the hw (so we need to add 100 ms). But the sw vbt
2571 * table multiplies it with 1000 to make it in units of 100usec,
2573 spec.t11_t12 = (510 + 100) * 10;
2575 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2576 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2578 /* Use the max of the register settings and vbt. If both are
2579 * unset, fall back to the spec limits. */
2580 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
2582 max(cur.field, vbt.field))
2583 assign_final(t1_t3);
2587 assign_final(t11_t12);
2590 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
2591 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2592 intel_dp->backlight_on_delay = get_delay(t8);
2593 intel_dp->backlight_off_delay = get_delay(t9);
2594 intel_dp->panel_power_down_delay = get_delay(t10);
2595 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2598 /* And finally store the new values in the power sequencer. */
2599 pp_on = (final.t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2600 (final.t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2601 pp_off = (final.t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2602 (final.t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
2603 /* Compute the divisor for the pp clock, simply match the Bspec
2605 pp_div = ((100 * intel_pch_rawclk(dev))/2 - 1)
2606 << PP_REFERENCE_DIVIDER_SHIFT;
2607 pp_div |= (DIV_ROUND_UP(final.t11_t12, 1000)
2608 << PANEL_POWER_CYCLE_DELAY_SHIFT);
2610 /* Haswell doesn't have any port selection bits for the panel
2611 * power sequencer any more. */
2612 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2613 if (is_cpu_edp(intel_dp))
2614 pp_on |= PANEL_POWER_PORT_DP_A;
2616 pp_on |= PANEL_POWER_PORT_DP_D;
2619 I915_WRITE(PCH_PP_ON_DELAYS, pp_on);
2620 I915_WRITE(PCH_PP_OFF_DELAYS, pp_off);
2621 I915_WRITE(PCH_PP_DIVISOR, pp_div);
2624 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2625 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2626 intel_dp->panel_power_cycle_delay);
2628 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2629 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2631 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2632 I915_READ(PCH_PP_ON_DELAYS),
2633 I915_READ(PCH_PP_OFF_DELAYS),
2634 I915_READ(PCH_PP_DIVISOR));
2638 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
2640 struct drm_i915_private *dev_priv = dev->dev_private;
2641 struct drm_connector *connector;
2642 struct intel_dp *intel_dp;
2643 struct intel_encoder *intel_encoder;
2644 struct intel_connector *intel_connector;
2645 struct drm_display_mode *fixed_mode = NULL;
2646 const char *name = NULL;
2649 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2653 intel_dp->output_reg = output_reg;
2654 intel_dp->port = port;
2655 /* Preserve the current hw state. */
2656 intel_dp->DP = I915_READ(intel_dp->output_reg);
2658 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2659 if (!intel_connector) {
2663 intel_encoder = &intel_dp->base;
2664 intel_dp->attached_connector = intel_connector;
2666 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
2667 if (intel_dpd_is_edp(dev))
2668 intel_dp->is_pch_edp = true;
2671 * FIXME : We need to initialize built-in panels before external panels.
2672 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2674 if (IS_VALLEYVIEW(dev) && output_reg == DP_C) {
2675 type = DRM_MODE_CONNECTOR_eDP;
2676 intel_encoder->type = INTEL_OUTPUT_EDP;
2677 } else if (output_reg == DP_A || is_pch_edp(intel_dp)) {
2678 type = DRM_MODE_CONNECTOR_eDP;
2679 intel_encoder->type = INTEL_OUTPUT_EDP;
2681 type = DRM_MODE_CONNECTOR_DisplayPort;
2682 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2685 connector = &intel_connector->base;
2686 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2687 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2689 connector->polled = DRM_CONNECTOR_POLL_HPD;
2691 intel_encoder->cloneable = false;
2693 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2694 ironlake_panel_vdd_work);
2696 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2698 connector->interlace_allowed = true;
2699 connector->doublescan_allowed = 0;
2701 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2702 DRM_MODE_ENCODER_TMDS);
2704 if (IS_HASWELL(dev))
2705 drm_encoder_helper_add(&intel_encoder->base,
2706 &intel_dp_helper_funcs_hsw);
2708 drm_encoder_helper_add(&intel_encoder->base,
2709 &intel_dp_helper_funcs);
2711 intel_connector_attach_encoder(intel_connector, intel_encoder);
2712 drm_sysfs_connector_add(connector);
2714 if (IS_HASWELL(dev)) {
2715 intel_encoder->enable = intel_enable_ddi;
2716 intel_encoder->pre_enable = intel_ddi_pre_enable;
2717 intel_encoder->disable = intel_disable_ddi;
2718 intel_encoder->post_disable = intel_ddi_post_disable;
2719 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
2721 intel_encoder->enable = intel_enable_dp;
2722 intel_encoder->pre_enable = intel_pre_enable_dp;
2723 intel_encoder->disable = intel_disable_dp;
2724 intel_encoder->post_disable = intel_post_disable_dp;
2725 intel_encoder->get_hw_state = intel_dp_get_hw_state;
2727 intel_connector->get_hw_state = intel_connector_get_hw_state;
2729 /* Set up the DDC bus. */
2735 dev_priv->hotplug_supported_mask |= DPB_HOTPLUG_INT_STATUS;
2739 dev_priv->hotplug_supported_mask |= DPC_HOTPLUG_INT_STATUS;
2743 dev_priv->hotplug_supported_mask |= DPD_HOTPLUG_INT_STATUS;
2747 WARN(1, "Invalid port %c\n", port_name(port));
2751 if (is_edp(intel_dp))
2752 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2754 intel_dp_i2c_init(intel_dp, intel_connector, name);
2756 /* Cache DPCD and EDID for edp. */
2757 if (is_edp(intel_dp)) {
2759 struct drm_display_mode *scan;
2762 ironlake_edp_panel_vdd_on(intel_dp);
2763 ret = intel_dp_get_dpcd(intel_dp);
2764 ironlake_edp_panel_vdd_off(intel_dp, false);
2767 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2768 dev_priv->no_aux_handshake =
2769 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2770 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2772 /* if this fails, presume the device is a ghost */
2773 DRM_INFO("failed to retrieve link info, disabling eDP\n");
2774 intel_dp_encoder_destroy(&intel_dp->base.base);
2775 intel_dp_destroy(&intel_connector->base);
2779 ironlake_edp_panel_vdd_on(intel_dp);
2780 edid = drm_get_edid(connector, &intel_dp->adapter);
2782 if (drm_add_edid_modes(connector, edid)) {
2783 drm_mode_connector_update_edid_property(connector, edid);
2784 drm_edid_to_eld(connector, edid);
2787 edid = ERR_PTR(-EINVAL);
2790 edid = ERR_PTR(-ENOENT);
2792 intel_connector->edid = edid;
2794 /* prefer fixed mode from EDID if available */
2795 list_for_each_entry(scan, &connector->probed_modes, head) {
2796 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
2797 fixed_mode = drm_mode_duplicate(dev, scan);
2802 /* fallback to VBT if available for eDP */
2803 if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
2804 fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2806 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
2809 ironlake_edp_panel_vdd_off(intel_dp, false);
2812 intel_encoder->hot_plug = intel_dp_hot_plug;
2814 if (is_edp(intel_dp)) {
2815 intel_panel_init(&intel_connector->panel, fixed_mode);
2816 intel_panel_setup_backlight(connector);
2819 intel_dp_add_properties(intel_dp, connector);
2821 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2822 * 0xd. Failure to do so will result in spurious interrupts being
2823 * generated on the port when a cable is not attached.
2825 if (IS_G4X(dev) && !IS_GM45(dev)) {
2826 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2827 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);