drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <linux/notifier.h>
  32 #include <linux/reboot.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_crtc.h>
  36 #include <drm/drm_crtc_helper.h>
  37 #include <drm/drm_edid.h>
  38 #include "intel_drv.h"
  39 #include <drm/i915_drm.h>
  40 #include "i915_drv.h"
  41
  42 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  43
  44 /* Compliance test status bits  */
  45 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  46 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  47 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  48 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  49
  50 struct dp_link_dpll {
  51         int link_bw;
  52         struct dpll dpll;
  53 };
  54
  55 static const struct dp_link_dpll gen4_dpll[] = {
  56         { DP_LINK_BW_1_62,
  57                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  58         { DP_LINK_BW_2_7,
  59                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  60 };
  61
  62 static const struct dp_link_dpll pch_dpll[] = {
  63         { DP_LINK_BW_1_62,
  64                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  65         { DP_LINK_BW_2_7,
  66                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  67 };
  68
  69 static const struct dp_link_dpll vlv_dpll[] = {
  70         { DP_LINK_BW_1_62,
  71                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  72         { DP_LINK_BW_2_7,
  73                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  74 };
  75
  76 /*
  77  * CHV supports eDP 1.4 that have  more link rates.
  78  * Below only provides the fixed rate but exclude variable rate.
  79  */
  80 static const struct dp_link_dpll chv_dpll[] = {
  81         /*
  82          * CHV requires to program fractional division for m2.
  83          * m2 is stored in fixed point format using formula below
  84          * (m2_int << 22) | m2_fraction
  85          */
  86         { DP_LINK_BW_1_62,      /* m2_int = 32, m2_fraction = 1677722 */
  87                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
  88         { DP_LINK_BW_2_7,       /* m2_int = 27, m2_fraction = 0 */
  89                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
  90         { DP_LINK_BW_5_4,       /* m2_int = 27, m2_fraction = 0 */
  91                 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
  92 };
  93
  94 static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
  95                                   324000, 432000, 540000 };
  96 static const int skl_rates[] = { 162000, 216000, 270000,
  97                                   324000, 432000, 540000 };
  98 static const int chv_rates[] = { 162000, 202500, 210000, 216000,
  99                                  243000, 270000, 324000, 405000,
 100                                  420000, 432000, 540000 };
 101 static const int default_rates[] = { 162000, 270000, 540000 };
 102
 103 /**
 104  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 105  * @intel_dp: DP struct
 106  *
 107  * If a CPU or PCH DP output is attached to an eDP panel, this function
 108  * will return true, and false otherwise.
 109  */
 110 static bool is_edp(struct intel_dp *intel_dp)
 111 {
 112         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 113
 114         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
 115 }
 116
 117 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
 118 {
 119         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 120
 121         return intel_dig_port->base.base.dev;
 122 }
 123
 124 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 125 {
 126         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 127 }
 128
 129 static void intel_dp_link_down(struct intel_dp *intel_dp);
 130 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 131 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 132 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
 133 static void vlv_steal_power_sequencer(struct drm_device *dev,
 134                                       enum pipe pipe);
 135
 136 static int
 137 intel_dp_max_link_bw(struct intel_dp  *intel_dp)
 138 {
 139         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 140
 141         switch (max_link_bw) {
 142         case DP_LINK_BW_1_62:
 143         case DP_LINK_BW_2_7:
 144         case DP_LINK_BW_5_4:
 145                 break;
 146         default:
 147                 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
 148                      max_link_bw);
 149                 max_link_bw = DP_LINK_BW_1_62;
 150                 break;
 151         }
 152         return max_link_bw;
 153 }
 154
 155 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 156 {
 157         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 158         struct drm_device *dev = intel_dig_port->base.base.dev;
 159         u8 source_max, sink_max;
 160
 161         source_max = 4;
 162         if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
 163             (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
 164                 source_max = 2;
 165
 166         sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 167
 168         return min(source_max, sink_max);
 169 }
 170
 171 /*
 172  * The units on the numbers in the next two are... bizarre.  Examples will
 173  * make it clearer; this one parallels an example in the eDP spec.
 174  *
 175  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 176  *
 177  *     270000 * 1 * 8 / 10 == 216000
 178  *
 179  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 180  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 181  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 182  * 119000.  At 18bpp that's 2142000 kilobits per second.
 183  *
 184  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 185  * get the result in decakilobits instead of kilobits.
 186  */
 187
 188 static int
 189 intel_dp_link_required(int pixel_clock, int bpp)
 190 {
 191         return (pixel_clock * bpp + 9) / 10;
 192 }
 193
 194 static int
 195 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 196 {
 197         return (max_link_clock * max_lanes * 8) / 10;
 198 }
 199
 200 static enum drm_mode_status
 201 intel_dp_mode_valid(struct drm_connector *connector,
 202                     struct drm_display_mode *mode)
 203 {
 204         struct intel_dp *intel_dp = intel_attached_dp(connector);
 205         struct intel_connector *intel_connector = to_intel_connector(connector);
 206         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 207         int target_clock = mode->clock;
 208         int max_rate, mode_rate, max_lanes, max_link_clock;
 209
 210         if (is_edp(intel_dp) && fixed_mode) {
 211                 if (mode->hdisplay > fixed_mode->hdisplay)
 212                         return MODE_PANEL;
 213
 214                 if (mode->vdisplay > fixed_mode->vdisplay)
 215                         return MODE_PANEL;
 216
 217                 target_clock = fixed_mode->clock;
 218         }
 219
 220         max_link_clock = intel_dp_max_link_rate(intel_dp);
 221         max_lanes = intel_dp_max_lane_count(intel_dp);
 222
 223         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 224         mode_rate = intel_dp_link_required(target_clock, 18);
 225
 226         if (mode_rate > max_rate)
 227                 return MODE_CLOCK_HIGH;
 228
 229         if (mode->clock < 10000)
 230                 return MODE_CLOCK_LOW;
 231
 232         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 233                 return MODE_H_ILLEGAL;
 234
 235         return MODE_OK;
 236 }
 237
 238 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
 239 {
 240         int     i;
 241         uint32_t v = 0;
 242
 243         if (src_bytes > 4)
 244                 src_bytes = 4;
 245         for (i = 0; i < src_bytes; i++)
 246                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 247         return v;
 248 }
 249
 250 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 251 {
 252         int i;
 253         if (dst_bytes > 4)
 254                 dst_bytes = 4;
 255         for (i = 0; i < dst_bytes; i++)
 256                 dst[i] = src >> ((3-i) * 8);
 257 }
 258
 259 /* hrawclock is 1/4 the FSB frequency */
 260 static int
 261 intel_hrawclk(struct drm_device *dev)
 262 {
 263         struct drm_i915_private *dev_priv = dev->dev_private;
 264         uint32_t clkcfg;
 265
 266         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 267         if (IS_VALLEYVIEW(dev))
 268                 return 200;
 269
 270         clkcfg = I915_READ(CLKCFG);
 271         switch (clkcfg & CLKCFG_FSB_MASK) {
 272         case CLKCFG_FSB_400:
 273                 return 100;
 274         case CLKCFG_FSB_533:
 275                 return 133;
 276         case CLKCFG_FSB_667:
 277                 return 166;
 278         case CLKCFG_FSB_800:
 279                 return 200;
 280         case CLKCFG_FSB_1067:
 281                 return 266;
 282         case CLKCFG_FSB_1333:
 283                 return 333;
 284         /* these two are just a guess; one of them might be right */
 285         case CLKCFG_FSB_1600:
 286         case CLKCFG_FSB_1600_ALT:
 287                 return 400;
 288         default:
 289                 return 133;
 290         }
 291 }
 292
 293 static void
 294 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 295                                     struct intel_dp *intel_dp);
 296 static void
 297 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 298                                               struct intel_dp *intel_dp);
 299
 300 static void pps_lock(struct intel_dp *intel_dp)
 301 {
 302         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 303         struct intel_encoder *encoder = &intel_dig_port->base;
 304         struct drm_device *dev = encoder->base.dev;
 305         struct drm_i915_private *dev_priv = dev->dev_private;
 306         enum intel_display_power_domain power_domain;
 307
 308         /*
 309          * See vlv_power_sequencer_reset() why we need
 310          * a power domain reference here.
 311          */
 312         power_domain = intel_display_port_power_domain(encoder);
 313         intel_display_power_get(dev_priv, power_domain);
 314
 315         mutex_lock(&dev_priv->pps_mutex);
 316 }
 317
 318 static void pps_unlock(struct intel_dp *intel_dp)
 319 {
 320         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 321         struct intel_encoder *encoder = &intel_dig_port->base;
 322         struct drm_device *dev = encoder->base.dev;
 323         struct drm_i915_private *dev_priv = dev->dev_private;
 324         enum intel_display_power_domain power_domain;
 325
 326         mutex_unlock(&dev_priv->pps_mutex);
 327
 328         power_domain = intel_display_port_power_domain(encoder);
 329         intel_display_power_put(dev_priv, power_domain);
 330 }
 331
 332 static void
 333 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 334 {
 335         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 336         struct drm_device *dev = intel_dig_port->base.base.dev;
 337         struct drm_i915_private *dev_priv = dev->dev_private;
 338         enum pipe pipe = intel_dp->pps_pipe;
 339         bool pll_enabled;
 340         uint32_t DP;
 341
 342         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
 343                  "skipping pipe %c power seqeuncer kick due to port %c being active\n",
 344                  pipe_name(pipe), port_name(intel_dig_port->port)))
 345                 return;
 346
 347         DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
 348                       pipe_name(pipe), port_name(intel_dig_port->port));
 349
 350         /* Preserve the BIOS-computed detected bit. This is
 351          * supposed to be read-only.
 352          */
 353         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 354         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 355         DP |= DP_PORT_WIDTH(1);
 356         DP |= DP_LINK_TRAIN_PAT_1;
 357
 358         if (IS_CHERRYVIEW(dev))
 359                 DP |= DP_PIPE_SELECT_CHV(pipe);
 360         else if (pipe == PIPE_B)
 361                 DP |= DP_PIPEB_SELECT;
 362
 363         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
 364
 365         /*
 366          * The DPLL for the pipe must be enabled for this to work.
 367          * So enable temporarily it if it's not already enabled.
 368          */
 369         if (!pll_enabled)
 370                 vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
 371                                  &chv_dpll[0].dpll : &vlv_dpll[0].dpll);
 372
 373         /*
 374          * Similar magic as in intel_dp_enable_port().
 375          * We _must_ do this port enable + disable trick
 376          * to make this power seqeuencer lock onto the port.
 377          * Otherwise even VDD force bit won't work.
 378          */
 379         I915_WRITE(intel_dp->output_reg, DP);
 380         POSTING_READ(intel_dp->output_reg);
 381
 382         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
 383         POSTING_READ(intel_dp->output_reg);
 384
 385         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
 386         POSTING_READ(intel_dp->output_reg);
 387
 388         if (!pll_enabled)
 389                 vlv_force_pll_off(dev, pipe);
 390 }
 391
 392 static enum pipe
 393 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 394 {
 395         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 396         struct drm_device *dev = intel_dig_port->base.base.dev;
 397         struct drm_i915_private *dev_priv = dev->dev_private;
 398         struct intel_encoder *encoder;
 399         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 400         enum pipe pipe;
 401
 402         lockdep_assert_held(&dev_priv->pps_mutex);
 403
 404         /* We should never land here with regular DP ports */
 405         WARN_ON(!is_edp(intel_dp));
 406
 407         if (intel_dp->pps_pipe != INVALID_PIPE)
 408                 return intel_dp->pps_pipe;
 409
 410         /*
 411          * We don't have power sequencer currently.
 412          * Pick one that's not used by other ports.
 413          */
 414         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
 415                             base.head) {
 416                 struct intel_dp *tmp;
 417
 418                 if (encoder->type != INTEL_OUTPUT_EDP)
 419                         continue;
 420
 421                 tmp = enc_to_intel_dp(&encoder->base);
 422
 423                 if (tmp->pps_pipe != INVALID_PIPE)
 424                         pipes &= ~(1 << tmp->pps_pipe);
 425         }
 426
 427         /*
 428          * Didn't find one. This should not happen since there
 429          * are two power sequencers and up to two eDP ports.
 430          */
 431         if (WARN_ON(pipes == 0))
 432                 pipe = PIPE_A;
 433         else
 434                 pipe = ffs(pipes) - 1;
 435
 436         vlv_steal_power_sequencer(dev, pipe);
 437         intel_dp->pps_pipe = pipe;
 438
 439         DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
 440                       pipe_name(intel_dp->pps_pipe),
 441                       port_name(intel_dig_port->port));
 442
 443         /* init power sequencer on this pipe and port */
 444         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 445         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
 446
 447         /*
 448          * Even vdd force doesn't work until we've made
 449          * the power sequencer lock in on the port.
 450          */
 451         vlv_power_sequencer_kick(intel_dp);
 452
 453         return intel_dp->pps_pipe;
 454 }
 455
 456 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 457                                enum pipe pipe);
 458
 459 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 460                                enum pipe pipe)
 461 {
 462         return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
 463 }
 464
 465 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 466                                 enum pipe pipe)
 467 {
 468         return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 469 }
 470
 471 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 472                          enum pipe pipe)
 473 {
 474         return true;
 475 }
 476
 477 static enum pipe
 478 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 479                      enum port port,
 480                      vlv_pipe_check pipe_check)
 481 {
 482         enum pipe pipe;
 483
 484         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 485                 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
 486                         PANEL_PORT_SELECT_MASK;
 487
 488                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 489                         continue;
 490
 491                 if (!pipe_check(dev_priv, pipe))
 492                         continue;
 493
 494                 return pipe;
 495         }
 496
 497         return INVALID_PIPE;
 498 }
 499
 500 static void
 501 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 502 {
 503         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 504         struct drm_device *dev = intel_dig_port->base.base.dev;
 505         struct drm_i915_private *dev_priv = dev->dev_private;
 506         enum port port = intel_dig_port->port;
 507
 508         lockdep_assert_held(&dev_priv->pps_mutex);
 509
 510         /* try to find a pipe with this port selected */
 511         /* first pick one where the panel is on */
 512         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 513                                                   vlv_pipe_has_pp_on);
 514         /* didn't find one? pick one where vdd is on */
 515         if (intel_dp->pps_pipe == INVALID_PIPE)
 516                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 517                                                           vlv_pipe_has_vdd_on);
 518         /* didn't find one? pick one with just the correct port */
 519         if (intel_dp->pps_pipe == INVALID_PIPE)
 520                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 521                                                           vlv_pipe_any);
 522
 523         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 524         if (intel_dp->pps_pipe == INVALID_PIPE) {
 525                 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
 526                               port_name(port));
 527                 return;
 528         }
 529
 530         DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
 531                       port_name(port), pipe_name(intel_dp->pps_pipe));
 532
 533         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 534         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
 535 }
 536
 537 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
 538 {
 539         struct drm_device *dev = dev_priv->dev;
 540         struct intel_encoder *encoder;
 541
 542         if (WARN_ON(!IS_VALLEYVIEW(dev)))
 543                 return;
 544
 545         /*
 546          * We can't grab pps_mutex here due to deadlock with power_domain
 547          * mutex when power_domain functions are called while holding pps_mutex.
 548          * That also means that in order to use pps_pipe the code needs to
 549          * hold both a power domain reference and pps_mutex, and the power domain
 550          * reference get/put must be done while _not_ holding pps_mutex.
 551          * pps_{lock,unlock}() do these steps in the correct order, so one
 552          * should use them always.
 553          */
 554
 555         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
 556                 struct intel_dp *intel_dp;
 557
 558                 if (encoder->type != INTEL_OUTPUT_EDP)
 559                         continue;
 560
 561                 intel_dp = enc_to_intel_dp(&encoder->base);
 562                 intel_dp->pps_pipe = INVALID_PIPE;
 563         }
 564 }
 565
 566 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
 567 {
 568         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 569
 570         if (IS_BROXTON(dev))
 571                 return BXT_PP_CONTROL(0);
 572         else if (HAS_PCH_SPLIT(dev))
 573                 return PCH_PP_CONTROL;
 574         else
 575                 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
 576 }
 577
 578 static u32 _pp_stat_reg(struct intel_dp *intel_dp)
 579 {
 580         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 581
 582         if (IS_BROXTON(dev))
 583                 return BXT_PP_STATUS(0);
 584         else if (HAS_PCH_SPLIT(dev))
 585                 return PCH_PP_STATUS;
 586         else
 587                 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
 588 }
 589
 590 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
 591    This function only applicable when panel PM state is not to be tracked */
 592 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 593                               void *unused)
 594 {
 595         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
 596                                                  edp_notifier);
 597         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 598         struct drm_i915_private *dev_priv = dev->dev_private;
 599         u32 pp_div;
 600         u32 pp_ctrl_reg, pp_div_reg;
 601
 602         if (!is_edp(intel_dp) || code != SYS_RESTART)
 603                 return 0;
 604
 605         pps_lock(intel_dp);
 606
 607         if (IS_VALLEYVIEW(dev)) {
 608                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 609
 610                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
 611                 pp_div_reg  = VLV_PIPE_PP_DIVISOR(pipe);
 612                 pp_div = I915_READ(pp_div_reg);
 613                 pp_div &= PP_REFERENCE_DIVIDER_MASK;
 614
 615                 /* 0x1F write to PP_DIV_REG sets max cycle delay */
 616                 I915_WRITE(pp_div_reg, pp_div | 0x1F);
 617                 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
 618                 msleep(intel_dp->panel_power_cycle_delay);
 619         }
 620
 621         pps_unlock(intel_dp);
 622
 623         return 0;
 624 }
 625
 626 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 627 {
 628         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 629         struct drm_i915_private *dev_priv = dev->dev_private;
 630
 631         lockdep_assert_held(&dev_priv->pps_mutex);
 632
 633         if (IS_VALLEYVIEW(dev) &&
 634             intel_dp->pps_pipe == INVALID_PIPE)
 635                 return false;
 636
 637         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 638 }
 639
 640 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 641 {
 642         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 643         struct drm_i915_private *dev_priv = dev->dev_private;
 644
 645         lockdep_assert_held(&dev_priv->pps_mutex);
 646
 647         if (IS_VALLEYVIEW(dev) &&
 648             intel_dp->pps_pipe == INVALID_PIPE)
 649                 return false;
 650
 651         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
 652 }
 653
 654 static void
 655 intel_dp_check_edp(struct intel_dp *intel_dp)
 656 {
 657         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 658         struct drm_i915_private *dev_priv = dev->dev_private;
 659
 660         if (!is_edp(intel_dp))
 661                 return;
 662
 663         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 664                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 665                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 666                               I915_READ(_pp_stat_reg(intel_dp)),
 667                               I915_READ(_pp_ctrl_reg(intel_dp)));
 668         }
 669 }
 670
 671 static uint32_t
 672 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 673 {
 674         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 675         struct drm_device *dev = intel_dig_port->base.base.dev;
 676         struct drm_i915_private *dev_priv = dev->dev_private;
 677         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 678         uint32_t status;
 679         bool done;
 680
 681 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 682         if (has_aux_irq)
 683                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 684                                           msecs_to_jiffies_timeout(10));
 685         else
 686                 done = wait_for_atomic(C, 10) == 0;
 687         if (!done)
 688                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 689                           has_aux_irq);
 690 #undef C
 691
 692         return status;
 693 }
 694
 695 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 696 {
 697         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 698         struct drm_device *dev = intel_dig_port->base.base.dev;
 699
 700         /*
 701          * The clock divider is based off the hrawclk, and would like to run at
 702          * 2MHz.  So, take the hrawclk value and divide by 2 and use that
 703          */
 704         return index ? 0 : intel_hrawclk(dev) / 2;
 705 }
 706
 707 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 708 {
 709         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 710         struct drm_device *dev = intel_dig_port->base.base.dev;
 711         struct drm_i915_private *dev_priv = dev->dev_private;
 712
 713         if (index)
 714                 return 0;
 715
 716         if (intel_dig_port->port == PORT_A) {
 717                 return DIV_ROUND_UP(dev_priv->cdclk_freq, 2000);
 718
 719         } else {
 720                 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 721         }
 722 }
 723
 724 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 725 {
 726         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 727         struct drm_device *dev = intel_dig_port->base.base.dev;
 728         struct drm_i915_private *dev_priv = dev->dev_private;
 729
 730         if (intel_dig_port->port == PORT_A) {
 731                 if (index)
 732                         return 0;
 733                 return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
 734         } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 735                 /* Workaround for non-ULT HSW */
 736                 switch (index) {
 737                 case 0: return 63;
 738                 case 1: return 72;
 739                 default: return 0;
 740                 }
 741         } else  {
 742                 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 743         }
 744 }
 745
 746 static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 747 {
 748         return index ? 0 : 100;
 749 }
 750
 751 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 752 {
 753         /*
 754          * SKL doesn't need us to program the AUX clock divider (Hardware will
 755          * derive the clock from CDCLK automatically). We still implement the
 756          * get_aux_clock_divider vfunc to plug-in into the existing code.
 757          */
 758         return index ? 0 : 1;
 759 }
 760
 761 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
 762                                       bool has_aux_irq,
 763                                       int send_bytes,
 764                                       uint32_t aux_clock_divider)
 765 {
 766         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 767         struct drm_device *dev = intel_dig_port->base.base.dev;
 768         uint32_t precharge, timeout;
 769
 770         if (IS_GEN6(dev))
 771                 precharge = 3;
 772         else
 773                 precharge = 5;
 774
 775         if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
 776                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
 777         else
 778                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
 779
 780         return DP_AUX_CH_CTL_SEND_BUSY |
 781                DP_AUX_CH_CTL_DONE |
 782                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 783                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 784                timeout |
 785                DP_AUX_CH_CTL_RECEIVE_ERROR |
 786                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 787                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 788                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
 789 }
 790
 791 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
 792                                       bool has_aux_irq,
 793                                       int send_bytes,
 794                                       uint32_t unused)
 795 {
 796         return DP_AUX_CH_CTL_SEND_BUSY |
 797                DP_AUX_CH_CTL_DONE |
 798                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 799                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 800                DP_AUX_CH_CTL_TIME_OUT_1600us |
 801                DP_AUX_CH_CTL_RECEIVE_ERROR |
 802                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 803                DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
 804 }
 805
 806 static int
 807 intel_dp_aux_ch(struct intel_dp *intel_dp,
 808                 const uint8_t *send, int send_bytes,
 809                 uint8_t *recv, int recv_size)
 810 {
 811         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 812         struct drm_device *dev = intel_dig_port->base.base.dev;
 813         struct drm_i915_private *dev_priv = dev->dev_private;
 814         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 815         uint32_t ch_data = ch_ctl + 4;
 816         uint32_t aux_clock_divider;
 817         int i, ret, recv_bytes;
 818         uint32_t status;
 819         int try, clock = 0;
 820         bool has_aux_irq = HAS_AUX_IRQ(dev);
 821         bool vdd;
 822
 823         pps_lock(intel_dp);
 824
 825         /*
 826          * We will be called with VDD already enabled for dpcd/edid/oui reads.
 827          * In such cases we want to leave VDD enabled and it's up to upper layers
 828          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
 829          * ourselves.
 830          */
 831         vdd = edp_panel_vdd_on(intel_dp);
 832
 833         /* dp aux is extremely sensitive to irq latency, hence request the
 834          * lowest possible wakeup latency and so prevent the cpu from going into
 835          * deep sleep states.
 836          */
 837         pm_qos_update_request(&dev_priv->pm_qos, 0);
 838
 839         intel_dp_check_edp(intel_dp);
 840
 841         intel_aux_display_runtime_get(dev_priv);
 842
 843         /* Try to wait for any previous AUX channel activity */
 844         for (try = 0; try < 3; try++) {
 845                 status = I915_READ_NOTRACE(ch_ctl);
 846                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 847                         break;
 848                 msleep(1);
 849         }
 850
 851         if (try == 3) {
 852                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 853                      I915_READ(ch_ctl));
 854                 ret = -EBUSY;
 855                 goto out;
 856         }
 857
 858         /* Only 5 data registers! */
 859         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
 860                 ret = -E2BIG;
 861                 goto out;
 862         }
 863
 864         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
 865                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
 866                                                           has_aux_irq,
 867                                                           send_bytes,
 868                                                           aux_clock_divider);
 869
 870                 /* Must try at least 3 times according to DP spec */
 871                 for (try = 0; try < 5; try++) {
 872                         /* Load the send data into the aux channel data registers */
 873                         for (i = 0; i < send_bytes; i += 4)
 874                                 I915_WRITE(ch_data + i,
 875                                            intel_dp_pack_aux(send + i,
 876                                                              send_bytes - i));
 877
 878                         /* Send the command and wait for it to complete */
 879                         I915_WRITE(ch_ctl, send_ctl);
 880
 881                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
 882
 883                         /* Clear done status and any errors */
 884                         I915_WRITE(ch_ctl,
 885                                    status |
 886                                    DP_AUX_CH_CTL_DONE |
 887                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
 888                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
 889
 890                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
 891                                 continue;
 892
 893                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
 894                          *   400us delay required for errors and timeouts
 895                          *   Timeout errors from the HW already meet this
 896                          *   requirement so skip to next iteration
 897                          */
 898                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 899                                 usleep_range(400, 500);
 900                                 continue;
 901                         }
 902                         if (status & DP_AUX_CH_CTL_DONE)
 903                                 break;
 904                 }
 905                 if (status & DP_AUX_CH_CTL_DONE)
 906                         break;
 907         }
 908
 909         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 910                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 911                 ret = -EBUSY;
 912                 goto out;
 913         }
 914
 915         /* Check for timeout or receive error.
 916          * Timeouts occur when the sink is not connected
 917          */
 918         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 919                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 920                 ret = -EIO;
 921                 goto out;
 922         }
 923
 924         /* Timeouts occur when the device isn't connected, so they're
 925          * "normal" -- don't fill the kernel log with these */
 926         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 927                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 928                 ret = -ETIMEDOUT;
 929                 goto out;
 930         }
 931
 932         /* Unload any bytes sent back from the other side */
 933         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 934                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 935         if (recv_bytes > recv_size)
 936                 recv_bytes = recv_size;
 937
 938         for (i = 0; i < recv_bytes; i += 4)
 939                 intel_dp_unpack_aux(I915_READ(ch_data + i),
 940                                     recv + i, recv_bytes - i);
 941
 942         ret = recv_bytes;
 943 out:
 944         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 945         intel_aux_display_runtime_put(dev_priv);
 946
 947         if (vdd)
 948                 edp_panel_vdd_off(intel_dp, false);
 949
 950         pps_unlock(intel_dp);
 951
 952         return ret;
 953 }
 954
 955 #define BARE_ADDRESS_SIZE       3
 956 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
 957 static ssize_t
 958 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
 959 {
 960         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
 961         uint8_t txbuf[20], rxbuf[20];
 962         size_t txsize, rxsize;
 963         int ret;
 964
 965         txbuf[0] = (msg->request << 4) |
 966                 ((msg->address >> 16) & 0xf);
 967         txbuf[1] = (msg->address >> 8) & 0xff;
 968         txbuf[2] = msg->address & 0xff;
 969         txbuf[3] = msg->size - 1;
 970
 971         switch (msg->request & ~DP_AUX_I2C_MOT) {
 972         case DP_AUX_NATIVE_WRITE:
 973         case DP_AUX_I2C_WRITE:
 974                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
 975                 rxsize = 2; /* 0 or 1 data bytes */
 976
 977                 if (WARN_ON(txsize > 20))
 978                         return -E2BIG;
 979
 980                 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
 981
 982                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
 983                 if (ret > 0) {
 984                         msg->reply = rxbuf[0] >> 4;
 985
 986                         if (ret > 1) {
 987                                 /* Number of bytes written in a short write. */
 988                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
 989                         } else {
 990                                 /* Return payload size. */
 991                                 ret = msg->size;
 992                         }
 993                 }
 994                 break;
 995
 996         case DP_AUX_NATIVE_READ:
 997         case DP_AUX_I2C_READ:
 998                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
 999                 rxsize = msg->size + 1;
1000
1001                 if (WARN_ON(rxsize > 20))
1002                         return -E2BIG;
1003
1004                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1005                 if (ret > 0) {
1006                         msg->reply = rxbuf[0] >> 4;
1007                         /*
1008                          * Assume happy day, and copy the data. The caller is
1009                          * expected to check msg->reply before touching it.
1010                          *
1011                          * Return payload size.
1012                          */
1013                         ret--;
1014                         memcpy(msg->buffer, rxbuf + 1, ret);
1015                 }
1016                 break;
1017
1018         default:
1019                 ret = -EINVAL;
1020                 break;
1021         }
1022
1023         return ret;
1024 }
1025
1026 static void
1027 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
1028 {
1029         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1030         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1031         enum port port = intel_dig_port->port;
1032         const char *name = NULL;
1033         int ret;
1034
1035         switch (port) {
1036         case PORT_A:
1037                 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
1038                 name = "DPDDC-A";
1039                 break;
1040         case PORT_B:
1041                 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
1042                 name = "DPDDC-B";
1043                 break;
1044         case PORT_C:
1045                 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
1046                 name = "DPDDC-C";
1047                 break;
1048         case PORT_D:
1049                 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
1050                 name = "DPDDC-D";
1051                 break;
1052         default:
1053                 BUG();
1054         }
1055
1056         /*
1057          * The AUX_CTL register is usually DP_CTL + 0x10.
1058          *
1059          * On Haswell and Broadwell though:
1060          *   - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
1061          *   - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
1062          *
1063          * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
1064          */
1065         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1066                 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
1067
1068         intel_dp->aux.name = name;
1069         intel_dp->aux.dev = dev->dev;
1070         intel_dp->aux.transfer = intel_dp_aux_transfer;
1071
1072         DRM_DEBUG_KMS("registering %s bus for %s\n", name,
1073                       connector->base.kdev->kobj.name);
1074
1075         ret = drm_dp_aux_register(&intel_dp->aux);
1076         if (ret < 0) {
1077                 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
1078                           name, ret);
1079                 return;
1080         }
1081
1082         ret = sysfs_create_link(&connector->base.kdev->kobj,
1083                                 &intel_dp->aux.ddc.dev.kobj,
1084                                 intel_dp->aux.ddc.dev.kobj.name);
1085         if (ret < 0) {
1086                 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
1087                 drm_dp_aux_unregister(&intel_dp->aux);
1088         }
1089 }
1090
1091 static void
1092 intel_dp_connector_unregister(struct intel_connector *intel_connector)
1093 {
1094         struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
1095
1096         if (!intel_connector->mst_port)
1097                 sysfs_remove_link(&intel_connector->base.kdev->kobj,
1098                                   intel_dp->aux.ddc.dev.kobj.name);
1099         intel_connector_unregister(intel_connector);
1100 }
1101
1102 static void
1103 skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock)
1104 {
1105         u32 ctrl1;
1106
1107         memset(&pipe_config->dpll_hw_state, 0,
1108                sizeof(pipe_config->dpll_hw_state));
1109
1110         pipe_config->ddi_pll_sel = SKL_DPLL0;
1111         pipe_config->dpll_hw_state.cfgcr1 = 0;
1112         pipe_config->dpll_hw_state.cfgcr2 = 0;
1113
1114         ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
1115         switch (link_clock / 2) {
1116         case 81000:
1117                 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
1118                                               SKL_DPLL0);
1119                 break;
1120         case 135000:
1121                 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350,
1122                                               SKL_DPLL0);
1123                 break;
1124         case 270000:
1125                 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700,
1126                                               SKL_DPLL0);
1127                 break;
1128         case 162000:
1129                 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620,
1130                                               SKL_DPLL0);
1131                 break;
1132         /* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which
1133         results in CDCLK change. Need to handle the change of CDCLK by
1134         disabling pipes and re-enabling them */
1135         case 108000:
1136                 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
1137                                               SKL_DPLL0);
1138                 break;
1139         case 216000:
1140                 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160,
1141                                               SKL_DPLL0);
1142                 break;
1143
1144         }
1145         pipe_config->dpll_hw_state.ctrl1 = ctrl1;
1146 }
1147
1148 static void
1149 hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config, int link_bw)
1150 {
1151         switch (link_bw) {
1152         case DP_LINK_BW_1_62:
1153                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
1154                 break;
1155         case DP_LINK_BW_2_7:
1156                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
1157                 break;
1158         case DP_LINK_BW_5_4:
1159                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
1160                 break;
1161         }
1162 }
1163
1164 static int
1165 intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
1166 {
1167         if (intel_dp->num_sink_rates) {
1168                 *sink_rates = intel_dp->sink_rates;
1169                 return intel_dp->num_sink_rates;
1170         }
1171
1172         *sink_rates = default_rates;
1173
1174         return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
1175 }
1176
1177 static int
1178 intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
1179 {
1180         if (IS_BROXTON(dev)) {
1181                 *source_rates = bxt_rates;
1182                 return ARRAY_SIZE(bxt_rates);
1183         } else if (IS_SKYLAKE(dev)) {
1184                 *source_rates = skl_rates;
1185                 return ARRAY_SIZE(skl_rates);
1186         } else if (IS_CHERRYVIEW(dev)) {
1187                 *source_rates = chv_rates;
1188                 return ARRAY_SIZE(chv_rates);
1189         }
1190
1191         *source_rates = default_rates;
1192
1193         if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0)
1194                 /* WaDisableHBR2:skl */
1195                 return (DP_LINK_BW_2_7 >> 3) + 1;
1196         else if (INTEL_INFO(dev)->gen >= 8 ||
1197             (IS_HASWELL(dev) && !IS_HSW_ULX(dev)))
1198                 return (DP_LINK_BW_5_4 >> 3) + 1;
1199         else
1200                 return (DP_LINK_BW_2_7 >> 3) + 1;
1201 }
1202
1203 static void
1204 intel_dp_set_clock(struct intel_encoder *encoder,
1205                    struct intel_crtc_state *pipe_config, int link_bw)
1206 {
1207         struct drm_device *dev = encoder->base.dev;
1208         const struct dp_link_dpll *divisor = NULL;
1209         int i, count = 0;
1210
1211         if (IS_G4X(dev)) {
1212                 divisor = gen4_dpll;
1213                 count = ARRAY_SIZE(gen4_dpll);
1214         } else if (HAS_PCH_SPLIT(dev)) {
1215                 divisor = pch_dpll;
1216                 count = ARRAY_SIZE(pch_dpll);
1217         } else if (IS_CHERRYVIEW(dev)) {
1218                 divisor = chv_dpll;
1219                 count = ARRAY_SIZE(chv_dpll);
1220         } else if (IS_VALLEYVIEW(dev)) {
1221                 divisor = vlv_dpll;
1222                 count = ARRAY_SIZE(vlv_dpll);
1223         }
1224
1225         if (divisor && count) {
1226                 for (i = 0; i < count; i++) {
1227                         if (link_bw == divisor[i].link_bw) {
1228                                 pipe_config->dpll = divisor[i].dpll;
1229                                 pipe_config->clock_set = true;
1230                                 break;
1231                         }
1232                 }
1233         }
1234 }
1235
1236 static int intersect_rates(const int *source_rates, int source_len,
1237                            const int *sink_rates, int sink_len,
1238                            int *common_rates)
1239 {
1240         int i = 0, j = 0, k = 0;
1241
1242         while (i < source_len && j < sink_len) {
1243                 if (source_rates[i] == sink_rates[j]) {
1244                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
1245                                 return k;
1246                         common_rates[k] = source_rates[i];
1247                         ++k;
1248                         ++i;
1249                         ++j;
1250                 } else if (source_rates[i] < sink_rates[j]) {
1251                         ++i;
1252                 } else {
1253                         ++j;
1254                 }
1255         }
1256         return k;
1257 }
1258
1259 static int intel_dp_common_rates(struct intel_dp *intel_dp,
1260                                  int *common_rates)
1261 {
1262         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1263         const int *source_rates, *sink_rates;
1264         int source_len, sink_len;
1265
1266         sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1267         source_len = intel_dp_source_rates(dev, &source_rates);
1268
1269         return intersect_rates(source_rates, source_len,
1270                                sink_rates, sink_len,
1271                                common_rates);
1272 }
1273
1274 static void snprintf_int_array(char *str, size_t len,
1275                                const int *array, int nelem)
1276 {
1277         int i;
1278
1279         str[0] = '\0';
1280
1281         for (i = 0; i < nelem; i++) {
1282                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1283                 if (r >= len)
1284                         return;
1285                 str += r;
1286                 len -= r;
1287         }
1288 }
1289
1290 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1291 {
1292         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1293         const int *source_rates, *sink_rates;
1294         int source_len, sink_len, common_len;
1295         int common_rates[DP_MAX_SUPPORTED_RATES];
1296         char str[128]; /* FIXME: too big for stack? */
1297
1298         if ((drm_debug & DRM_UT_KMS) == 0)
1299                 return;
1300
1301         source_len = intel_dp_source_rates(dev, &source_rates);
1302         snprintf_int_array(str, sizeof(str), source_rates, source_len);
1303         DRM_DEBUG_KMS("source rates: %s\n", str);
1304
1305         sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1306         snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
1307         DRM_DEBUG_KMS("sink rates: %s\n", str);
1308
1309         common_len = intel_dp_common_rates(intel_dp, common_rates);
1310         snprintf_int_array(str, sizeof(str), common_rates, common_len);
1311         DRM_DEBUG_KMS("common rates: %s\n", str);
1312 }
1313
1314 static int rate_to_index(int find, const int *rates)
1315 {
1316         int i = 0;
1317
1318         for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
1319                 if (find == rates[i])
1320                         break;
1321
1322         return i;
1323 }
1324
1325 int
1326 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1327 {
1328         int rates[DP_MAX_SUPPORTED_RATES] = {};
1329         int len;
1330
1331         len = intel_dp_common_rates(intel_dp, rates);
1332         if (WARN_ON(len <= 0))
1333                 return 162000;
1334
1335         return rates[rate_to_index(0, rates) - 1];
1336 }
1337
1338 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1339 {
1340         return rate_to_index(rate, intel_dp->sink_rates);
1341 }
1342
1343 bool
1344 intel_dp_compute_config(struct intel_encoder *encoder,
1345                         struct intel_crtc_state *pipe_config)
1346 {
1347         struct drm_device *dev = encoder->base.dev;
1348         struct drm_i915_private *dev_priv = dev->dev_private;
1349         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1350         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1351         enum port port = dp_to_dig_port(intel_dp)->port;
1352         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1353         struct intel_connector *intel_connector = intel_dp->attached_connector;
1354         int lane_count, clock;
1355         int min_lane_count = 1;
1356         int max_lane_count = intel_dp_max_lane_count(intel_dp);
1357         /* Conveniently, the link BW constants become indices with a shift...*/
1358         int min_clock = 0;
1359         int max_clock;
1360         int bpp, mode_rate;
1361         int link_avail, link_clock;
1362         int common_rates[DP_MAX_SUPPORTED_RATES] = {};
1363         int common_len;
1364
1365         common_len = intel_dp_common_rates(intel_dp, common_rates);
1366
1367         /* No common link rates between source and sink */
1368         WARN_ON(common_len <= 0);
1369
1370         max_clock = common_len - 1;
1371
1372         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
1373                 pipe_config->has_pch_encoder = true;
1374
1375         pipe_config->has_dp_encoder = true;
1376         pipe_config->has_drrs = false;
1377         pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
1378
1379         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1380                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1381                                        adjusted_mode);
1382
1383                 if (INTEL_INFO(dev)->gen >= 9) {
1384                         int ret;
1385                         ret = skl_update_scaler_crtc(pipe_config, 0);
1386                         if (ret)
1387                                 return ret;
1388                 }
1389
1390                 if (!HAS_PCH_SPLIT(dev))
1391                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
1392                                                  intel_connector->panel.fitting_mode);
1393                 else
1394                         intel_pch_panel_fitting(intel_crtc, pipe_config,
1395                                                 intel_connector->panel.fitting_mode);
1396         }
1397
1398         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1399                 return false;
1400
1401         DRM_DEBUG_KMS("DP link computation with max lane count %i "
1402                       "max bw %d pixel clock %iKHz\n",
1403                       max_lane_count, common_rates[max_clock],
1404                       adjusted_mode->crtc_clock);
1405
1406         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1407          * bpc in between. */
1408         bpp = pipe_config->pipe_bpp;
1409         if (is_edp(intel_dp)) {
1410                 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
1411                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1412                                       dev_priv->vbt.edp_bpp);
1413                         bpp = dev_priv->vbt.edp_bpp;
1414                 }
1415
1416                 /*
1417                  * Use the maximum clock and number of lanes the eDP panel
1418                  * advertizes being capable of. The panels are generally
1419                  * designed to support only a single clock and lane
1420                  * configuration, and typically these values correspond to the
1421                  * native resolution of the panel.
1422                  */
1423                 min_lane_count = max_lane_count;
1424                 min_clock = max_clock;
1425         }
1426
1427         for (; bpp >= 6*3; bpp -= 2*3) {
1428                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1429                                                    bpp);
1430
1431                 for (clock = min_clock; clock <= max_clock; clock++) {
1432                         for (lane_count = min_lane_count;
1433                                 lane_count <= max_lane_count;
1434                                 lane_count <<= 1) {
1435
1436                                 link_clock = common_rates[clock];
1437                                 link_avail = intel_dp_max_data_rate(link_clock,
1438                                                                     lane_count);
1439
1440                                 if (mode_rate <= link_avail) {
1441                                         goto found;
1442                                 }
1443                         }
1444                 }
1445         }
1446
1447         return false;
1448
1449 found:
1450         if (intel_dp->color_range_auto) {
1451                 /*
1452                  * See:
1453                  * CEA-861-E - 5.1 Default Encoding Parameters
1454                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1455                  */
1456                 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
1457                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
1458                 else
1459                         intel_dp->color_range = 0;
1460         }
1461
1462         if (intel_dp->color_range)
1463                 pipe_config->limited_color_range = true;
1464
1465         intel_dp->lane_count = lane_count;
1466
1467         if (intel_dp->num_sink_rates) {
1468                 intel_dp->link_bw = 0;
1469                 intel_dp->rate_select =
1470                         intel_dp_rate_select(intel_dp, common_rates[clock]);
1471         } else {
1472                 intel_dp->link_bw =
1473                         drm_dp_link_rate_to_bw_code(common_rates[clock]);
1474                 intel_dp->rate_select = 0;
1475         }
1476
1477         pipe_config->pipe_bpp = bpp;
1478         pipe_config->port_clock = common_rates[clock];
1479
1480         DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1481                       intel_dp->link_bw, intel_dp->lane_count,
1482                       pipe_config->port_clock, bpp);
1483         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1484                       mode_rate, link_avail);
1485
1486         intel_link_compute_m_n(bpp, lane_count,
1487                                adjusted_mode->crtc_clock,
1488                                pipe_config->port_clock,
1489                                &pipe_config->dp_m_n);
1490
1491         if (intel_connector->panel.downclock_mode != NULL &&
1492                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1493                         pipe_config->has_drrs = true;
1494                         intel_link_compute_m_n(bpp, lane_count,
1495                                 intel_connector->panel.downclock_mode->clock,
1496                                 pipe_config->port_clock,
1497                                 &pipe_config->dp_m2_n2);
1498         }
1499
1500         if (IS_SKYLAKE(dev) && is_edp(intel_dp))
1501                 skl_edp_set_pll_config(pipe_config, common_rates[clock]);
1502         else if (IS_BROXTON(dev))
1503                 /* handled in ddi */;
1504         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1505                 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
1506         else
1507                 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
1508
1509         return true;
1510 }
1511
1512 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
1513 {
1514         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1515         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1516         struct drm_device *dev = crtc->base.dev;
1517         struct drm_i915_private *dev_priv = dev->dev_private;
1518         u32 dpa_ctl;
1519
1520         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n",
1521                       crtc->config->port_clock);
1522         dpa_ctl = I915_READ(DP_A);
1523         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1524
1525         if (crtc->config->port_clock == 162000) {
1526                 /* For a long time we've carried around a ILK-DevA w/a for the
1527                  * 160MHz clock. If we're really unlucky, it's still required.
1528                  */
1529                 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
1530                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1531                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
1532         } else {
1533                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1534                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
1535         }
1536
1537         I915_WRITE(DP_A, dpa_ctl);
1538
1539         POSTING_READ(DP_A);
1540         udelay(500);
1541 }
1542
1543 static void intel_dp_prepare(struct intel_encoder *encoder)
1544 {
1545         struct drm_device *dev = encoder->base.dev;
1546         struct drm_i915_private *dev_priv = dev->dev_private;
1547         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1548         enum port port = dp_to_dig_port(intel_dp)->port;
1549         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1550         struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
1551
1552         /*
1553          * There are four kinds of DP registers:
1554          *
1555          *      IBX PCH
1556          *      SNB CPU
1557          *      IVB CPU
1558          *      CPT PCH
1559          *
1560          * IBX PCH and CPU are the same for almost everything,
1561          * except that the CPU DP PLL is configured in this
1562          * register
1563          *
1564          * CPT PCH is quite different, having many bits moved
1565          * to the TRANS_DP_CTL register instead. That
1566          * configuration happens (oddly) in ironlake_pch_enable
1567          */
1568
1569         /* Preserve the BIOS-computed detected bit. This is
1570          * supposed to be read-only.
1571          */
1572         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1573
1574         /* Handle DP bits in common between all three register formats */
1575         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1576         intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
1577
1578         if (crtc->config->has_audio)
1579                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
1580
1581         /* Split out the IBX/CPU vs CPT settings */
1582
1583         if (IS_GEN7(dev) && port == PORT_A) {
1584                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1585                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1586                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1587                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1588                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1589
1590                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1591                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1592
1593                 intel_dp->DP |= crtc->pipe << 29;
1594         } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
1595                 u32 trans_dp;
1596
1597                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1598
1599                 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1600                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1601                         trans_dp |= TRANS_DP_ENH_FRAMING;
1602                 else
1603                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
1604                 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
1605         } else {
1606                 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
1607                         intel_dp->DP |= intel_dp->color_range;
1608
1609                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1610                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1611                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1612                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1613                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1614
1615                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1616                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1617
1618                 if (IS_CHERRYVIEW(dev))
1619                         intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1620                 else if (crtc->pipe == PIPE_B)
1621                         intel_dp->DP |= DP_PIPEB_SELECT;
1622         }
1623 }
1624
1625 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1626 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1627
1628 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
1629 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
1630
1631 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1632 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1633
1634 static void wait_panel_status(struct intel_dp *intel_dp,
1635                                        u32 mask,
1636                                        u32 value)
1637 {
1638         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1639         struct drm_i915_private *dev_priv = dev->dev_private;
1640         u32 pp_stat_reg, pp_ctrl_reg;
1641
1642         lockdep_assert_held(&dev_priv->pps_mutex);
1643
1644         pp_stat_reg = _pp_stat_reg(intel_dp);
1645         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1646
1647         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1648                         mask, value,
1649                         I915_READ(pp_stat_reg),
1650                         I915_READ(pp_ctrl_reg));
1651
1652         if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1653                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1654                                 I915_READ(pp_stat_reg),
1655                                 I915_READ(pp_ctrl_reg));
1656         }
1657
1658         DRM_DEBUG_KMS("Wait complete\n");
1659 }
1660
1661 static void wait_panel_on(struct intel_dp *intel_dp)
1662 {
1663         DRM_DEBUG_KMS("Wait for panel power on\n");
1664         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1665 }
1666
1667 static void wait_panel_off(struct intel_dp *intel_dp)
1668 {
1669         DRM_DEBUG_KMS("Wait for panel power off time\n");
1670         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1671 }
1672
1673 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1674 {
1675         DRM_DEBUG_KMS("Wait for panel power cycle\n");
1676
1677         /* When we disable the VDD override bit last we have to do the manual
1678          * wait. */
1679         wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1680                                        intel_dp->panel_power_cycle_delay);
1681
1682         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1683 }
1684
1685 static void wait_backlight_on(struct intel_dp *intel_dp)
1686 {
1687         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1688                                        intel_dp->backlight_on_delay);
1689 }
1690
1691 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1692 {
1693         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1694                                        intel_dp->backlight_off_delay);
1695 }
1696
1697 /* Read the current pp_control value, unlocking the register if it
1698  * is locked
1699  */
1700
1701 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1702 {
1703         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1704         struct drm_i915_private *dev_priv = dev->dev_private;
1705         u32 control;
1706
1707         lockdep_assert_held(&dev_priv->pps_mutex);
1708
1709         control = I915_READ(_pp_ctrl_reg(intel_dp));
1710         if (!IS_BROXTON(dev)) {
1711                 control &= ~PANEL_UNLOCK_MASK;
1712                 control |= PANEL_UNLOCK_REGS;
1713         }
1714         return control;
1715 }
1716
1717 /*
1718  * Must be paired with edp_panel_vdd_off().
1719  * Must hold pps_mutex around the whole on/off sequence.
1720  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1721  */
1722 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
1723 {
1724         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1725         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1726         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1727         struct drm_i915_private *dev_priv = dev->dev_private;
1728         enum intel_display_power_domain power_domain;
1729         u32 pp;
1730         u32 pp_stat_reg, pp_ctrl_reg;
1731         bool need_to_disable = !intel_dp->want_panel_vdd;
1732
1733         lockdep_assert_held(&dev_priv->pps_mutex);
1734
1735         if (!is_edp(intel_dp))
1736                 return false;
1737
1738         cancel_delayed_work(&intel_dp->panel_vdd_work);
1739         intel_dp->want_panel_vdd = true;
1740
1741         if (edp_have_panel_vdd(intel_dp))
1742                 return need_to_disable;
1743
1744         power_domain = intel_display_port_power_domain(intel_encoder);
1745         intel_display_power_get(dev_priv, power_domain);
1746
1747         DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1748                       port_name(intel_dig_port->port));
1749
1750         if (!edp_have_panel_power(intel_dp))
1751                 wait_panel_power_cycle(intel_dp);
1752
1753         pp = ironlake_get_pp_control(intel_dp);
1754         pp |= EDP_FORCE_VDD;
1755
1756         pp_stat_reg = _pp_stat_reg(intel_dp);
1757         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1758
1759         I915_WRITE(pp_ctrl_reg, pp);
1760         POSTING_READ(pp_ctrl_reg);
1761         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1762                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1763         /*
1764          * If the panel wasn't on, delay before accessing aux channel
1765          */
1766         if (!edp_have_panel_power(intel_dp)) {
1767                 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1768                               port_name(intel_dig_port->port));
1769                 msleep(intel_dp->panel_power_up_delay);
1770         }
1771
1772         return need_to_disable;
1773 }
1774
1775 /*
1776  * Must be paired with intel_edp_panel_vdd_off() or
1777  * intel_edp_panel_off().
1778  * Nested calls to these functions are not allowed since
1779  * we drop the lock. Caller must use some higher level
1780  * locking to prevent nested calls from other threads.
1781  */
1782 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1783 {
1784         bool vdd;
1785
1786         if (!is_edp(intel_dp))
1787                 return;
1788
1789         pps_lock(intel_dp);
1790         vdd = edp_panel_vdd_on(intel_dp);
1791         pps_unlock(intel_dp);
1792
1793         I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
1794              port_name(dp_to_dig_port(intel_dp)->port));
1795 }
1796
1797 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1798 {
1799         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1800         struct drm_i915_private *dev_priv = dev->dev_private;
1801         struct intel_digital_port *intel_dig_port =
1802                 dp_to_dig_port(intel_dp);
1803         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1804         enum intel_display_power_domain power_domain;
1805         u32 pp;
1806         u32 pp_stat_reg, pp_ctrl_reg;
1807
1808         lockdep_assert_held(&dev_priv->pps_mutex);
1809
1810         WARN_ON(intel_dp->want_panel_vdd);
1811
1812         if (!edp_have_panel_vdd(intel_dp))
1813                 return;
1814
1815         DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1816                       port_name(intel_dig_port->port));
1817
1818         pp = ironlake_get_pp_control(intel_dp);
1819         pp &= ~EDP_FORCE_VDD;
1820
1821         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1822         pp_stat_reg = _pp_stat_reg(intel_dp);
1823
1824         I915_WRITE(pp_ctrl_reg, pp);
1825         POSTING_READ(pp_ctrl_reg);
1826
1827         /* Make sure sequencer is idle before allowing subsequent activity */
1828         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1829         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1830
1831         if ((pp & POWER_TARGET_ON) == 0)
1832                 intel_dp->last_power_cycle = jiffies;
1833
1834         power_domain = intel_display_port_power_domain(intel_encoder);
1835         intel_display_power_put(dev_priv, power_domain);
1836 }
1837
1838 static void edp_panel_vdd_work(struct work_struct *__work)
1839 {
1840         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1841                                                  struct intel_dp, panel_vdd_work);
1842
1843         pps_lock(intel_dp);
1844         if (!intel_dp->want_panel_vdd)
1845                 edp_panel_vdd_off_sync(intel_dp);
1846         pps_unlock(intel_dp);
1847 }
1848
1849 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1850 {
1851         unsigned long delay;
1852
1853         /*
1854          * Queue the timer to fire a long time from now (relative to the power
1855          * down delay) to keep the panel power up across a sequence of
1856          * operations.
1857          */
1858         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1859         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1860 }
1861
1862 /*
1863  * Must be paired with edp_panel_vdd_on().
1864  * Must hold pps_mutex around the whole on/off sequence.
1865  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1866  */
1867 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1868 {
1869         struct drm_i915_private *dev_priv =
1870                 intel_dp_to_dev(intel_dp)->dev_private;
1871
1872         lockdep_assert_held(&dev_priv->pps_mutex);
1873
1874         if (!is_edp(intel_dp))
1875                 return;
1876
1877         I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
1878              port_name(dp_to_dig_port(intel_dp)->port));
1879
1880         intel_dp->want_panel_vdd = false;
1881
1882         if (sync)
1883                 edp_panel_vdd_off_sync(intel_dp);
1884         else
1885                 edp_panel_vdd_schedule_off(intel_dp);
1886 }
1887
1888 static void edp_panel_on(struct intel_dp *intel_dp)
1889 {
1890         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1891         struct drm_i915_private *dev_priv = dev->dev_private;
1892         u32 pp;
1893         u32 pp_ctrl_reg;
1894
1895         lockdep_assert_held(&dev_priv->pps_mutex);
1896
1897         if (!is_edp(intel_dp))
1898                 return;
1899
1900         DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
1901                       port_name(dp_to_dig_port(intel_dp)->port));
1902
1903         if (WARN(edp_have_panel_power(intel_dp),
1904                  "eDP port %c panel power already on\n",
1905                  port_name(dp_to_dig_port(intel_dp)->port)))
1906                 return;
1907
1908         wait_panel_power_cycle(intel_dp);
1909
1910         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1911         pp = ironlake_get_pp_control(intel_dp);
1912         if (IS_GEN5(dev)) {
1913                 /* ILK workaround: disable reset around power sequence */
1914                 pp &= ~PANEL_POWER_RESET;
1915                 I915_WRITE(pp_ctrl_reg, pp);
1916                 POSTING_READ(pp_ctrl_reg);
1917         }
1918
1919         pp |= POWER_TARGET_ON;
1920         if (!IS_GEN5(dev))
1921                 pp |= PANEL_POWER_RESET;
1922
1923         I915_WRITE(pp_ctrl_reg, pp);
1924         POSTING_READ(pp_ctrl_reg);
1925
1926         wait_panel_on(intel_dp);
1927         intel_dp->last_power_on = jiffies;
1928
1929         if (IS_GEN5(dev)) {
1930                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1931                 I915_WRITE(pp_ctrl_reg, pp);
1932                 POSTING_READ(pp_ctrl_reg);
1933         }
1934 }
1935
1936 void intel_edp_panel_on(struct intel_dp *intel_dp)
1937 {
1938         if (!is_edp(intel_dp))
1939                 return;
1940
1941         pps_lock(intel_dp);
1942         edp_panel_on(intel_dp);
1943         pps_unlock(intel_dp);
1944 }
1945
1946
1947 static void edp_panel_off(struct intel_dp *intel_dp)
1948 {
1949         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1950         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1951         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1952         struct drm_i915_private *dev_priv = dev->dev_private;
1953         enum intel_display_power_domain power_domain;
1954         u32 pp;
1955         u32 pp_ctrl_reg;
1956
1957         lockdep_assert_held(&dev_priv->pps_mutex);
1958
1959         if (!is_edp(intel_dp))
1960                 return;
1961
1962         DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
1963                       port_name(dp_to_dig_port(intel_dp)->port));
1964
1965         WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
1966              port_name(dp_to_dig_port(intel_dp)->port));
1967
1968         pp = ironlake_get_pp_control(intel_dp);
1969         /* We need to switch off panel power _and_ force vdd, for otherwise some
1970          * panels get very unhappy and cease to work. */
1971         pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1972                 EDP_BLC_ENABLE);
1973
1974         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1975
1976         intel_dp->want_panel_vdd = false;
1977
1978         I915_WRITE(pp_ctrl_reg, pp);
1979         POSTING_READ(pp_ctrl_reg);
1980
1981         intel_dp->last_power_cycle = jiffies;
1982         wait_panel_off(intel_dp);
1983
1984         /* We got a reference when we enabled the VDD. */
1985         power_domain = intel_display_port_power_domain(intel_encoder);
1986         intel_display_power_put(dev_priv, power_domain);
1987 }
1988
1989 void intel_edp_panel_off(struct intel_dp *intel_dp)
1990 {
1991         if (!is_edp(intel_dp))
1992                 return;
1993
1994         pps_lock(intel_dp);
1995         edp_panel_off(intel_dp);
1996         pps_unlock(intel_dp);
1997 }
1998
1999 /* Enable backlight in the panel power control. */
2000 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2001 {
2002         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2003         struct drm_device *dev = intel_dig_port->base.base.dev;
2004         struct drm_i915_private *dev_priv = dev->dev_private;
2005         u32 pp;
2006         u32 pp_ctrl_reg;
2007
2008         /*
2009          * If we enable the backlight right away following a panel power
2010          * on, we may see slight flicker as the panel syncs with the eDP
2011          * link.  So delay a bit to make sure the image is solid before
2012          * allowing it to appear.
2013          */
2014         wait_backlight_on(intel_dp);
2015
2016         pps_lock(intel_dp);
2017
2018         pp = ironlake_get_pp_control(intel_dp);
2019         pp |= EDP_BLC_ENABLE;
2020
2021         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2022
2023         I915_WRITE(pp_ctrl_reg, pp);
2024         POSTING_READ(pp_ctrl_reg);
2025
2026         pps_unlock(intel_dp);
2027 }
2028
2029 /* Enable backlight PWM and backlight PP control. */
2030 void intel_edp_backlight_on(struct intel_dp *intel_dp)
2031 {
2032         if (!is_edp(intel_dp))
2033                 return;
2034
2035         DRM_DEBUG_KMS("\n");
2036
2037         intel_panel_enable_backlight(intel_dp->attached_connector);
2038         _intel_edp_backlight_on(intel_dp);
2039 }
2040
2041 /* Disable backlight in the panel power control. */
2042 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2043 {
2044         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2045         struct drm_i915_private *dev_priv = dev->dev_private;
2046         u32 pp;
2047         u32 pp_ctrl_reg;
2048
2049         if (!is_edp(intel_dp))
2050                 return;
2051
2052         pps_lock(intel_dp);
2053
2054         pp = ironlake_get_pp_control(intel_dp);
2055         pp &= ~EDP_BLC_ENABLE;
2056
2057         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2058
2059         I915_WRITE(pp_ctrl_reg, pp);
2060         POSTING_READ(pp_ctrl_reg);
2061
2062         pps_unlock(intel_dp);
2063
2064         intel_dp->last_backlight_off = jiffies;
2065         edp_wait_backlight_off(intel_dp);
2066 }
2067
2068 /* Disable backlight PP control and backlight PWM. */
2069 void intel_edp_backlight_off(struct intel_dp *intel_dp)
2070 {
2071         if (!is_edp(intel_dp))
2072                 return;
2073
2074         DRM_DEBUG_KMS("\n");
2075
2076         _intel_edp_backlight_off(intel_dp);
2077         intel_panel_disable_backlight(intel_dp->attached_connector);
2078 }
2079
2080 /*
2081  * Hook for controlling the panel power control backlight through the bl_power
2082  * sysfs attribute. Take care to handle multiple calls.
2083  */
2084 static void intel_edp_backlight_power(struct intel_connector *connector,
2085                                       bool enable)
2086 {
2087         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2088         bool is_enabled;
2089
2090         pps_lock(intel_dp);
2091         is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2092         pps_unlock(intel_dp);
2093
2094         if (is_enabled == enable)
2095                 return;
2096
2097         DRM_DEBUG_KMS("panel power control backlight %s\n",
2098                       enable ? "enable" : "disable");
2099
2100         if (enable)
2101                 _intel_edp_backlight_on(intel_dp);
2102         else
2103                 _intel_edp_backlight_off(intel_dp);
2104 }
2105
2106 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
2107 {
2108         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2109         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2110         struct drm_device *dev = crtc->dev;
2111         struct drm_i915_private *dev_priv = dev->dev_private;
2112         u32 dpa_ctl;
2113
2114         assert_pipe_disabled(dev_priv,
2115                              to_intel_crtc(crtc)->pipe);
2116
2117         DRM_DEBUG_KMS("\n");
2118         dpa_ctl = I915_READ(DP_A);
2119         WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
2120         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
2121
2122         /* We don't adjust intel_dp->DP while tearing down the link, to
2123          * facilitate link retraining (e.g. after hotplug). Hence clear all
2124          * enable bits here to ensure that we don't enable too much. */
2125         intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
2126         intel_dp->DP |= DP_PLL_ENABLE;
2127         I915_WRITE(DP_A, intel_dp->DP);
2128         POSTING_READ(DP_A);
2129         udelay(200);
2130 }
2131
2132 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
2133 {
2134         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2135         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2136         struct drm_device *dev = crtc->dev;
2137         struct drm_i915_private *dev_priv = dev->dev_private;
2138         u32 dpa_ctl;
2139
2140         assert_pipe_disabled(dev_priv,
2141                              to_intel_crtc(crtc)->pipe);
2142
2143         dpa_ctl = I915_READ(DP_A);
2144         WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
2145              "dp pll off, should be on\n");
2146         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
2147
2148         /* We can't rely on the value tracked for the DP register in
2149          * intel_dp->DP because link_down must not change that (otherwise link
2150          * re-training will fail. */
2151         dpa_ctl &= ~DP_PLL_ENABLE;
2152         I915_WRITE(DP_A, dpa_ctl);
2153         POSTING_READ(DP_A);
2154         udelay(200);
2155 }
2156
2157 /* If the sink supports it, try to set the power state appropriately */
2158 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2159 {
2160         int ret, i;
2161
2162         /* Should have a valid DPCD by this point */
2163         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2164                 return;
2165
2166         if (mode != DRM_MODE_DPMS_ON) {
2167                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2168                                          DP_SET_POWER_D3);
2169         } else {
2170                 /*
2171                  * When turning on, we need to retry for 1ms to give the sink
2172                  * time to wake up.
2173                  */
2174                 for (i = 0; i < 3; i++) {
2175                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2176                                                  DP_SET_POWER_D0);
2177                         if (ret == 1)
2178                                 break;
2179                         msleep(1);
2180                 }
2181         }
2182
2183         if (ret != 1)
2184                 DRM_DEBUG_KMS("failed to %s sink power state\n",
2185                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2186 }
2187
2188 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2189                                   enum pipe *pipe)
2190 {
2191         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2192         enum port port = dp_to_dig_port(intel_dp)->port;
2193         struct drm_device *dev = encoder->base.dev;
2194         struct drm_i915_private *dev_priv = dev->dev_private;
2195         enum intel_display_power_domain power_domain;
2196         u32 tmp;
2197
2198         power_domain = intel_display_port_power_domain(encoder);
2199         if (!intel_display_power_is_enabled(dev_priv, power_domain))
2200                 return false;
2201
2202         tmp = I915_READ(intel_dp->output_reg);
2203
2204         if (!(tmp & DP_PORT_EN))
2205                 return false;
2206
2207         if (IS_GEN7(dev) && port == PORT_A) {
2208                 *pipe = PORT_TO_PIPE_CPT(tmp);
2209         } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
2210                 enum pipe p;
2211
2212                 for_each_pipe(dev_priv, p) {
2213                         u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2214                         if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2215                                 *pipe = p;
2216                                 return true;
2217                         }
2218                 }
2219
2220                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2221                               intel_dp->output_reg);
2222         } else if (IS_CHERRYVIEW(dev)) {
2223                 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2224         } else {
2225                 *pipe = PORT_TO_PIPE(tmp);
2226         }
2227
2228         return true;
2229 }
2230
2231 static void intel_dp_get_config(struct intel_encoder *encoder,
2232                                 struct intel_crtc_state *pipe_config)
2233 {
2234         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2235         u32 tmp, flags = 0;
2236         struct drm_device *dev = encoder->base.dev;
2237         struct drm_i915_private *dev_priv = dev->dev_private;
2238         enum port port = dp_to_dig_port(intel_dp)->port;
2239         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2240         int dotclock;
2241
2242         tmp = I915_READ(intel_dp->output_reg);
2243
2244         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2245
2246         if (HAS_PCH_CPT(dev) && port != PORT_A) {
2247                 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2248                 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2249                         flags |= DRM_MODE_FLAG_PHSYNC;
2250                 else
2251                         flags |= DRM_MODE_FLAG_NHSYNC;
2252
2253                 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2254                         flags |= DRM_MODE_FLAG_PVSYNC;
2255                 else
2256                         flags |= DRM_MODE_FLAG_NVSYNC;
2257         } else {
2258                 if (tmp & DP_SYNC_HS_HIGH)
2259                         flags |= DRM_MODE_FLAG_PHSYNC;
2260                 else
2261                         flags |= DRM_MODE_FLAG_NHSYNC;
2262
2263                 if (tmp & DP_SYNC_VS_HIGH)
2264                         flags |= DRM_MODE_FLAG_PVSYNC;
2265                 else
2266                         flags |= DRM_MODE_FLAG_NVSYNC;
2267         }
2268
2269         pipe_config->base.adjusted_mode.flags |= flags;
2270
2271         if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
2272             tmp & DP_COLOR_RANGE_16_235)
2273                 pipe_config->limited_color_range = true;
2274
2275         pipe_config->has_dp_encoder = true;
2276
2277         intel_dp_get_m_n(crtc, pipe_config);
2278
2279         if (port == PORT_A) {
2280                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
2281                         pipe_config->port_clock = 162000;
2282                 else
2283                         pipe_config->port_clock = 270000;
2284         }
2285
2286         dotclock = intel_dotclock_calculate(pipe_config->port_clock,
2287                                             &pipe_config->dp_m_n);
2288
2289         if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
2290                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
2291
2292         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
2293
2294         if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
2295             pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2296                 /*
2297                  * This is a big fat ugly hack.
2298                  *
2299                  * Some machines in UEFI boot mode provide us a VBT that has 18
2300                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2301                  * unknown we fail to light up. Yet the same BIOS boots up with
2302                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2303                  * max, not what it tells us to use.
2304                  *
2305                  * Note: This will still be broken if the eDP panel is not lit
2306                  * up by the BIOS, and thus we can't get the mode at module
2307                  * load.
2308                  */
2309                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2310                               pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2311                 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2312         }
2313 }
2314
2315 static void intel_disable_dp(struct intel_encoder *encoder)
2316 {
2317         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2318         struct drm_device *dev = encoder->base.dev;
2319         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2320
2321         if (crtc->config->has_audio)
2322                 intel_audio_codec_disable(encoder);
2323
2324         if (HAS_PSR(dev) && !HAS_DDI(dev))
2325                 intel_psr_disable(intel_dp);
2326
2327         /* Make sure the panel is off before trying to change the mode. But also
2328          * ensure that we have vdd while we switch off the panel. */
2329         intel_edp_panel_vdd_on(intel_dp);
2330         intel_edp_backlight_off(intel_dp);
2331         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2332         intel_edp_panel_off(intel_dp);
2333
2334         /* disable the port before the pipe on g4x */
2335         if (INTEL_INFO(dev)->gen < 5)
2336                 intel_dp_link_down(intel_dp);
2337 }
2338
2339 static void ilk_post_disable_dp(struct intel_encoder *encoder)
2340 {
2341         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2342         enum port port = dp_to_dig_port(intel_dp)->port;
2343
2344         intel_dp_link_down(intel_dp);
2345         if (port == PORT_A)
2346                 ironlake_edp_pll_off(intel_dp);
2347 }
2348
2349 static void vlv_post_disable_dp(struct intel_encoder *encoder)
2350 {
2351         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2352
2353         intel_dp_link_down(intel_dp);
2354 }
2355
2356 static void chv_post_disable_dp(struct intel_encoder *encoder)
2357 {
2358         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2359         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2360         struct drm_device *dev = encoder->base.dev;
2361         struct drm_i915_private *dev_priv = dev->dev_private;
2362         struct intel_crtc *intel_crtc =
2363                 to_intel_crtc(encoder->base.crtc);
2364         enum dpio_channel ch = vlv_dport_to_channel(dport);
2365         enum pipe pipe = intel_crtc->pipe;
2366         u32 val;
2367
2368         intel_dp_link_down(intel_dp);
2369
2370         mutex_lock(&dev_priv->sb_lock);
2371
2372         /* Propagate soft reset to data lane reset */
2373         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2374         val |= CHV_PCS_REQ_SOFTRESET_EN;
2375         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2376
2377         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2378         val |= CHV_PCS_REQ_SOFTRESET_EN;
2379         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2380
2381         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2382         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2383         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2384
2385         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2386         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2387         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2388
2389         mutex_unlock(&dev_priv->sb_lock);
2390 }
2391
2392 static void
2393 _intel_dp_set_link_train(struct intel_dp *intel_dp,
2394                          uint32_t *DP,
2395                          uint8_t dp_train_pat)
2396 {
2397         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2398         struct drm_device *dev = intel_dig_port->base.base.dev;
2399         struct drm_i915_private *dev_priv = dev->dev_private;
2400         enum port port = intel_dig_port->port;
2401
2402         if (HAS_DDI(dev)) {
2403                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2404
2405                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2406                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2407                 else
2408                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2409
2410                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2411                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2412                 case DP_TRAINING_PATTERN_DISABLE:
2413                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2414
2415                         break;
2416                 case DP_TRAINING_PATTERN_1:
2417                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2418                         break;
2419                 case DP_TRAINING_PATTERN_2:
2420                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2421                         break;
2422                 case DP_TRAINING_PATTERN_3:
2423                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2424                         break;
2425                 }
2426                 I915_WRITE(DP_TP_CTL(port), temp);
2427
2428         } else if ((IS_GEN7(dev) && port == PORT_A) ||
2429                    (HAS_PCH_CPT(dev) && port != PORT_A)) {
2430                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2431
2432                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2433                 case DP_TRAINING_PATTERN_DISABLE:
2434                         *DP |= DP_LINK_TRAIN_OFF_CPT;
2435                         break;
2436                 case DP_TRAINING_PATTERN_1:
2437                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2438                         break;
2439                 case DP_TRAINING_PATTERN_2:
2440                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2441                         break;
2442                 case DP_TRAINING_PATTERN_3:
2443                         DRM_ERROR("DP training pattern 3 not supported\n");
2444                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2445                         break;
2446                 }
2447
2448         } else {
2449                 if (IS_CHERRYVIEW(dev))
2450                         *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2451                 else
2452                         *DP &= ~DP_LINK_TRAIN_MASK;
2453
2454                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2455                 case DP_TRAINING_PATTERN_DISABLE:
2456                         *DP |= DP_LINK_TRAIN_OFF;
2457                         break;
2458                 case DP_TRAINING_PATTERN_1:
2459                         *DP |= DP_LINK_TRAIN_PAT_1;
2460                         break;
2461                 case DP_TRAINING_PATTERN_2:
2462                         *DP |= DP_LINK_TRAIN_PAT_2;
2463                         break;
2464                 case DP_TRAINING_PATTERN_3:
2465                         if (IS_CHERRYVIEW(dev)) {
2466                                 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2467                         } else {
2468                                 DRM_ERROR("DP training pattern 3 not supported\n");
2469                                 *DP |= DP_LINK_TRAIN_PAT_2;
2470                         }
2471                         break;
2472                 }
2473         }
2474 }
2475
2476 static void intel_dp_enable_port(struct intel_dp *intel_dp)
2477 {
2478         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2479         struct drm_i915_private *dev_priv = dev->dev_private;
2480
2481         /* enable with pattern 1 (as per spec) */
2482         _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2483                                  DP_TRAINING_PATTERN_1);
2484
2485         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2486         POSTING_READ(intel_dp->output_reg);
2487
2488         /*
2489          * Magic for VLV/CHV. We _must_ first set up the register
2490          * without actually enabling the port, and then do another
2491          * write to enable the port. Otherwise link training will
2492          * fail when the power sequencer is freshly used for this port.
2493          */
2494         intel_dp->DP |= DP_PORT_EN;
2495
2496         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2497         POSTING_READ(intel_dp->output_reg);
2498 }
2499
2500 static void intel_enable_dp(struct intel_encoder *encoder)
2501 {
2502         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2503         struct drm_device *dev = encoder->base.dev;
2504         struct drm_i915_private *dev_priv = dev->dev_private;
2505         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2506         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2507         unsigned int lane_mask = 0x0;
2508
2509         if (WARN_ON(dp_reg & DP_PORT_EN))
2510                 return;
2511
2512         pps_lock(intel_dp);
2513
2514         if (IS_VALLEYVIEW(dev))
2515                 vlv_init_panel_power_sequencer(intel_dp);
2516
2517         intel_dp_enable_port(intel_dp);
2518
2519         edp_panel_vdd_on(intel_dp);
2520         edp_panel_on(intel_dp);
2521         edp_panel_vdd_off(intel_dp, true);
2522
2523         pps_unlock(intel_dp);
2524
2525         if (IS_VALLEYVIEW(dev))
2526                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2527                                     lane_mask);
2528
2529         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2530         intel_dp_start_link_train(intel_dp);
2531         intel_dp_complete_link_train(intel_dp);
2532         intel_dp_stop_link_train(intel_dp);
2533
2534         if (crtc->config->has_audio) {
2535                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2536                                  pipe_name(crtc->pipe));
2537                 intel_audio_codec_enable(encoder);
2538         }
2539 }
2540
2541 static void g4x_enable_dp(struct intel_encoder *encoder)
2542 {
2543         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2544
2545         intel_enable_dp(encoder);
2546         intel_edp_backlight_on(intel_dp);
2547 }
2548
2549 static void vlv_enable_dp(struct intel_encoder *encoder)
2550 {
2551         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2552
2553         intel_edp_backlight_on(intel_dp);
2554         intel_psr_enable(intel_dp);
2555 }
2556
2557 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
2558 {
2559         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2560         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2561
2562         intel_dp_prepare(encoder);
2563
2564         /* Only ilk+ has port A */
2565         if (dport->port == PORT_A) {
2566                 ironlake_set_pll_cpu_edp(intel_dp);
2567                 ironlake_edp_pll_on(intel_dp);
2568         }
2569 }
2570
2571 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2572 {
2573         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2574         struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
2575         enum pipe pipe = intel_dp->pps_pipe;
2576         int pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
2577
2578         edp_panel_vdd_off_sync(intel_dp);
2579
2580         /*
2581          * VLV seems to get confused when multiple power seqeuencers
2582          * have the same port selected (even if only one has power/vdd
2583          * enabled). The failure manifests as vlv_wait_port_ready() failing
2584          * CHV on the other hand doesn't seem to mind having the same port
2585          * selected in multiple power seqeuencers, but let's clear the
2586          * port select always when logically disconnecting a power sequencer
2587          * from a port.
2588          */
2589         DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2590                       pipe_name(pipe), port_name(intel_dig_port->port));
2591         I915_WRITE(pp_on_reg, 0);
2592         POSTING_READ(pp_on_reg);
2593
2594         intel_dp->pps_pipe = INVALID_PIPE;
2595 }
2596
2597 static void vlv_steal_power_sequencer(struct drm_device *dev,
2598                                       enum pipe pipe)
2599 {
2600         struct drm_i915_private *dev_priv = dev->dev_private;
2601         struct intel_encoder *encoder;
2602
2603         lockdep_assert_held(&dev_priv->pps_mutex);
2604
2605         if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2606                 return;
2607
2608         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2609                             base.head) {
2610                 struct intel_dp *intel_dp;
2611                 enum port port;
2612
2613                 if (encoder->type != INTEL_OUTPUT_EDP)
2614                         continue;
2615
2616                 intel_dp = enc_to_intel_dp(&encoder->base);
2617                 port = dp_to_dig_port(intel_dp)->port;
2618
2619                 if (intel_dp->pps_pipe != pipe)
2620                         continue;
2621
2622                 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2623                               pipe_name(pipe), port_name(port));
2624
2625                 WARN(encoder->connectors_active,
2626                      "stealing pipe %c power sequencer from active eDP port %c\n",
2627                      pipe_name(pipe), port_name(port));
2628
2629                 /* make sure vdd is off before we steal it */
2630                 vlv_detach_power_sequencer(intel_dp);
2631         }
2632 }
2633
2634 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2635 {
2636         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2637         struct intel_encoder *encoder = &intel_dig_port->base;
2638         struct drm_device *dev = encoder->base.dev;
2639         struct drm_i915_private *dev_priv = dev->dev_private;
2640         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2641
2642         lockdep_assert_held(&dev_priv->pps_mutex);
2643
2644         if (!is_edp(intel_dp))
2645                 return;
2646
2647         if (intel_dp->pps_pipe == crtc->pipe)
2648                 return;
2649
2650         /*
2651          * If another power sequencer was being used on this
2652          * port previously make sure to turn off vdd there while
2653          * we still have control of it.
2654          */
2655         if (intel_dp->pps_pipe != INVALID_PIPE)
2656                 vlv_detach_power_sequencer(intel_dp);
2657
2658         /*
2659          * We may be stealing the power
2660          * sequencer from another port.
2661          */
2662         vlv_steal_power_sequencer(dev, crtc->pipe);
2663
2664         /* now it's all ours */
2665         intel_dp->pps_pipe = crtc->pipe;
2666
2667         DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2668                       pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2669
2670         /* init power sequencer on this pipe and port */
2671         intel_dp_init_panel_power_sequencer(dev, intel_dp);
2672         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
2673 }
2674
2675 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
2676 {
2677         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2678         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2679         struct drm_device *dev = encoder->base.dev;
2680         struct drm_i915_private *dev_priv = dev->dev_private;
2681         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2682         enum dpio_channel port = vlv_dport_to_channel(dport);
2683         int pipe = intel_crtc->pipe;
2684         u32 val;
2685
2686         mutex_lock(&dev_priv->sb_lock);
2687
2688         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
2689         val = 0;
2690         if (pipe)
2691                 val |= (1<<21);
2692         else
2693                 val &= ~(1<<21);
2694         val |= 0x001000c4;
2695         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2696         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2697         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
2698
2699         mutex_unlock(&dev_priv->sb_lock);
2700
2701         intel_enable_dp(encoder);
2702 }
2703
2704 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
2705 {
2706         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2707         struct drm_device *dev = encoder->base.dev;
2708         struct drm_i915_private *dev_priv = dev->dev_private;
2709         struct intel_crtc *intel_crtc =
2710                 to_intel_crtc(encoder->base.crtc);
2711         enum dpio_channel port = vlv_dport_to_channel(dport);
2712         int pipe = intel_crtc->pipe;
2713
2714         intel_dp_prepare(encoder);
2715
2716         /* Program Tx lane resets to default */
2717         mutex_lock(&dev_priv->sb_lock);
2718         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
2719                          DPIO_PCS_TX_LANE2_RESET |
2720                          DPIO_PCS_TX_LANE1_RESET);
2721         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
2722                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2723                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2724                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2725                                  DPIO_PCS_CLK_SOFT_RESET);
2726
2727         /* Fix up inter-pair skew failure */
2728         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2729         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2730         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
2731         mutex_unlock(&dev_priv->sb_lock);
2732 }
2733
2734 static void chv_pre_enable_dp(struct intel_encoder *encoder)
2735 {
2736         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2737         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2738         struct drm_device *dev = encoder->base.dev;
2739         struct drm_i915_private *dev_priv = dev->dev_private;
2740         struct intel_crtc *intel_crtc =
2741                 to_intel_crtc(encoder->base.crtc);
2742         enum dpio_channel ch = vlv_dport_to_channel(dport);
2743         int pipe = intel_crtc->pipe;
2744         int data, i, stagger;
2745         u32 val;
2746
2747         mutex_lock(&dev_priv->sb_lock);
2748
2749         /* allow hardware to manage TX FIFO reset source */
2750         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2751         val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2752         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2753
2754         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2755         val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2756         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2757
2758         /* Deassert soft data lane reset*/
2759         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2760         val |= CHV_PCS_REQ_SOFTRESET_EN;
2761         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2762
2763         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2764         val |= CHV_PCS_REQ_SOFTRESET_EN;
2765         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2766
2767         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2768         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2769         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2770
2771         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2772         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2773         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2774
2775         /* Program Tx lane latency optimal setting*/
2776         for (i = 0; i < 4; i++) {
2777                 /* Set the upar bit */
2778                 data = (i == 1) ? 0x0 : 0x1;
2779                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2780                                 data << DPIO_UPAR_SHIFT);
2781         }
2782
2783         /* Data lane stagger programming */
2784         if (intel_crtc->config->port_clock > 270000)
2785                 stagger = 0x18;
2786         else if (intel_crtc->config->port_clock > 135000)
2787                 stagger = 0xd;
2788         else if (intel_crtc->config->port_clock > 67500)
2789                 stagger = 0x7;
2790         else if (intel_crtc->config->port_clock > 33750)
2791                 stagger = 0x4;
2792         else
2793                 stagger = 0x2;
2794
2795         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2796         val |= DPIO_TX2_STAGGER_MASK(0x1f);
2797         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2798
2799         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2800         val |= DPIO_TX2_STAGGER_MASK(0x1f);
2801         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2802
2803         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
2804                        DPIO_LANESTAGGER_STRAP(stagger) |
2805                        DPIO_LANESTAGGER_STRAP_OVRD |
2806                        DPIO_TX1_STAGGER_MASK(0x1f) |
2807                        DPIO_TX1_STAGGER_MULT(6) |
2808                        DPIO_TX2_STAGGER_MULT(0));
2809
2810         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
2811                        DPIO_LANESTAGGER_STRAP(stagger) |
2812                        DPIO_LANESTAGGER_STRAP_OVRD |
2813                        DPIO_TX1_STAGGER_MASK(0x1f) |
2814                        DPIO_TX1_STAGGER_MULT(7) |
2815                        DPIO_TX2_STAGGER_MULT(5));
2816
2817         mutex_unlock(&dev_priv->sb_lock);
2818
2819         intel_enable_dp(encoder);
2820 }
2821
2822 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2823 {
2824         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2825         struct drm_device *dev = encoder->base.dev;
2826         struct drm_i915_private *dev_priv = dev->dev_private;
2827         struct intel_crtc *intel_crtc =
2828                 to_intel_crtc(encoder->base.crtc);
2829         enum dpio_channel ch = vlv_dport_to_channel(dport);
2830         enum pipe pipe = intel_crtc->pipe;
2831         u32 val;
2832
2833         intel_dp_prepare(encoder);
2834
2835         mutex_lock(&dev_priv->sb_lock);
2836
2837         /* program left/right clock distribution */
2838         if (pipe != PIPE_B) {
2839                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2840                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2841                 if (ch == DPIO_CH0)
2842                         val |= CHV_BUFLEFTENA1_FORCE;
2843                 if (ch == DPIO_CH1)
2844                         val |= CHV_BUFRIGHTENA1_FORCE;
2845                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2846         } else {
2847                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2848                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2849                 if (ch == DPIO_CH0)
2850                         val |= CHV_BUFLEFTENA2_FORCE;
2851                 if (ch == DPIO_CH1)
2852                         val |= CHV_BUFRIGHTENA2_FORCE;
2853                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2854         }
2855
2856         /* program clock channel usage */
2857         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2858         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2859         if (pipe != PIPE_B)
2860                 val &= ~CHV_PCS_USEDCLKCHANNEL;
2861         else
2862                 val |= CHV_PCS_USEDCLKCHANNEL;
2863         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2864
2865         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2866         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2867         if (pipe != PIPE_B)
2868                 val &= ~CHV_PCS_USEDCLKCHANNEL;
2869         else
2870                 val |= CHV_PCS_USEDCLKCHANNEL;
2871         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2872
2873         /*
2874          * This a a bit weird since generally CL
2875          * matches the pipe, but here we need to
2876          * pick the CL based on the port.
2877          */
2878         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2879         if (pipe != PIPE_B)
2880                 val &= ~CHV_CMN_USEDCLKCHANNEL;
2881         else
2882                 val |= CHV_CMN_USEDCLKCHANNEL;
2883         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2884
2885         mutex_unlock(&dev_priv->sb_lock);
2886 }
2887
2888 /*
2889  * Native read with retry for link status and receiver capability reads for
2890  * cases where the sink may still be asleep.
2891  *
2892  * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2893  * supposed to retry 3 times per the spec.
2894  */
2895 static ssize_t
2896 intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2897                         void *buffer, size_t size)
2898 {
2899         ssize_t ret;
2900         int i;
2901
2902         /*
2903          * Sometime we just get the same incorrect byte repeated
2904          * over the entire buffer. Doing just one throw away read
2905          * initially seems to "solve" it.
2906          */
2907         drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1);
2908
2909         for (i = 0; i < 3; i++) {
2910                 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2911                 if (ret == size)
2912                         return ret;
2913                 msleep(1);
2914         }
2915
2916         return ret;
2917 }
2918
2919 /*
2920  * Fetch AUX CH registers 0x202 - 0x207 which contain
2921  * link status information
2922  */
2923 static bool
2924 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2925 {
2926         return intel_dp_dpcd_read_wake(&intel_dp->aux,
2927                                        DP_LANE0_1_STATUS,
2928                                        link_status,
2929                                        DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
2930 }
2931
2932 /* These are source-specific values. */
2933 static uint8_t
2934 intel_dp_voltage_max(struct intel_dp *intel_dp)
2935 {
2936         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2937         struct drm_i915_private *dev_priv = dev->dev_private;
2938         enum port port = dp_to_dig_port(intel_dp)->port;
2939
2940         if (IS_BROXTON(dev))
2941                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2942         else if (INTEL_INFO(dev)->gen >= 9) {
2943                 if (dev_priv->edp_low_vswing && port == PORT_A)
2944                         return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2945                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2946         } else if (IS_VALLEYVIEW(dev))
2947                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2948         else if (IS_GEN7(dev) && port == PORT_A)
2949                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2950         else if (HAS_PCH_CPT(dev) && port != PORT_A)
2951                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2952         else
2953                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2954 }
2955
2956 static uint8_t
2957 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2958 {
2959         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2960         enum port port = dp_to_dig_port(intel_dp)->port;
2961
2962         if (INTEL_INFO(dev)->gen >= 9) {
2963                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2964                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2965                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
2966                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2967                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2968                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2969                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
2970                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2971                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2972                 default:
2973                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2974                 }
2975         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2976                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2977                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2978                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
2979                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2980                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2981                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2982                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
2983                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2984                 default:
2985                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2986                 }
2987         } else if (IS_VALLEYVIEW(dev)) {
2988                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2989                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2990                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
2991                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2992                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2993                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2994                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
2995                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2996                 default:
2997                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2998                 }
2999         } else if (IS_GEN7(dev) && port == PORT_A) {
3000                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3001                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3002                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3003                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3004                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3005                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3006                 default:
3007                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3008                 }
3009         } else {
3010                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3011                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3012                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3013                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3014                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3015                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3016                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3017                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3018                 default:
3019                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3020                 }
3021         }
3022 }
3023
3024 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
3025 {
3026         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3027         struct drm_i915_private *dev_priv = dev->dev_private;
3028         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3029         struct intel_crtc *intel_crtc =
3030                 to_intel_crtc(dport->base.base.crtc);
3031         unsigned long demph_reg_value, preemph_reg_value,
3032                 uniqtranscale_reg_value;
3033         uint8_t train_set = intel_dp->train_set[0];
3034         enum dpio_channel port = vlv_dport_to_channel(dport);
3035         int pipe = intel_crtc->pipe;
3036
3037         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3038         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3039                 preemph_reg_value = 0x0004000;
3040                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3041                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3042                         demph_reg_value = 0x2B405555;
3043                         uniqtranscale_reg_value = 0x552AB83A;
3044                         break;
3045                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3046                         demph_reg_value = 0x2B404040;
3047                         uniqtranscale_reg_value = 0x5548B83A;
3048                         break;
3049                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3050                         demph_reg_value = 0x2B245555;
3051                         uniqtranscale_reg_value = 0x5560B83A;
3052                         break;
3053                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3054                         demph_reg_value = 0x2B405555;
3055                         uniqtranscale_reg_value = 0x5598DA3A;
3056                         break;
3057                 default:
3058                         return 0;
3059                 }
3060                 break;
3061         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3062                 preemph_reg_value = 0x0002000;
3063                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3064                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3065                         demph_reg_value = 0x2B404040;
3066                         uniqtranscale_reg_value = 0x5552B83A;
3067                         break;
3068                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3069                         demph_reg_value = 0x2B404848;
3070                         uniqtranscale_reg_value = 0x5580B83A;
3071                         break;
3072                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3073                         demph_reg_value = 0x2B404040;
3074                         uniqtranscale_reg_value = 0x55ADDA3A;
3075                         break;
3076                 default:
3077                         return 0;
3078                 }
3079                 break;
3080         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3081                 preemph_reg_value = 0x0000000;
3082                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3083                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3084                         demph_reg_value = 0x2B305555;
3085                         uniqtranscale_reg_value = 0x5570B83A;
3086                         break;
3087                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3088                         demph_reg_value = 0x2B2B4040;
3089                         uniqtranscale_reg_value = 0x55ADDA3A;
3090                         break;
3091                 default:
3092                         return 0;
3093                 }
3094                 break;
3095         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3096                 preemph_reg_value = 0x0006000;
3097                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3098                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3099                         demph_reg_value = 0x1B405555;
3100                         uniqtranscale_reg_value = 0x55ADDA3A;
3101                         break;
3102                 default:
3103                         return 0;
3104                 }
3105                 break;
3106         default:
3107                 return 0;
3108         }
3109
3110         mutex_lock(&dev_priv->sb_lock);
3111         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
3112         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
3113         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
3114                          uniqtranscale_reg_value);
3115         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
3116         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
3117         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
3118         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
3119         mutex_unlock(&dev_priv->sb_lock);
3120
3121         return 0;
3122 }
3123
3124 static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3125 {
3126         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3127         struct drm_i915_private *dev_priv = dev->dev_private;
3128         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3129         struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
3130         u32 deemph_reg_value, margin_reg_value, val;
3131         uint8_t train_set = intel_dp->train_set[0];
3132         enum dpio_channel ch = vlv_dport_to_channel(dport);
3133         enum pipe pipe = intel_crtc->pipe;
3134         int i;
3135
3136         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3137         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3138                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3139                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3140                         deemph_reg_value = 128;
3141                         margin_reg_value = 52;
3142                         break;
3143                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3144                         deemph_reg_value = 128;
3145                         margin_reg_value = 77;
3146                         break;
3147                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3148                         deemph_reg_value = 128;
3149                         margin_reg_value = 102;
3150                         break;
3151                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3152                         deemph_reg_value = 128;
3153                         margin_reg_value = 154;
3154                         /* FIXME extra to set for 1200 */
3155                         break;
3156                 default:
3157                         return 0;
3158                 }
3159                 break;
3160         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3161                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3162                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3163                         deemph_reg_value = 85;
3164                         margin_reg_value = 78;
3165                         break;
3166                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3167                         deemph_reg_value = 85;
3168                         margin_reg_value = 116;
3169                         break;
3170                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3171                         deemph_reg_value = 85;
3172                         margin_reg_value = 154;
3173                         break;
3174                 default:
3175                         return 0;
3176                 }
3177                 break;
3178         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3179                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3180                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3181                         deemph_reg_value = 64;
3182                         margin_reg_value = 104;
3183                         break;
3184                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3185                         deemph_reg_value = 64;
3186                         margin_reg_value = 154;
3187                         break;
3188                 default:
3189                         return 0;
3190                 }
3191                 break;
3192         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3193                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3194                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3195                         deemph_reg_value = 43;
3196                         margin_reg_value = 154;
3197                         break;
3198                 default:
3199                         return 0;
3200                 }
3201                 break;
3202         default:
3203                 return 0;
3204         }
3205
3206         mutex_lock(&dev_priv->sb_lock);
3207
3208         /* Clear calc init */
3209         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3210         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3211         val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3212         val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
3213         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3214
3215         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3216         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3217         val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3218         val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
3219         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
3220
3221         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
3222         val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3223         val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3224         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
3225
3226         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
3227         val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3228         val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3229         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
3230
3231         /* Program swing deemph */
3232         for (i = 0; i < 4; i++) {
3233                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
3234                 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
3235                 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
3236                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
3237         }
3238
3239         /* Program swing margin */
3240         for (i = 0; i < 4; i++) {
3241                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3242                 val &= ~DPIO_SWING_MARGIN000_MASK;
3243                 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
3244                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3245         }
3246
3247         /* Disable unique transition scale */
3248         for (i = 0; i < 4; i++) {
3249                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3250                 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3251                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3252         }
3253
3254         if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
3255                         == DP_TRAIN_PRE_EMPH_LEVEL_0) &&
3256                 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
3257                         == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
3258
3259                 /*
3260                  * The document said it needs to set bit 27 for ch0 and bit 26
3261                  * for ch1. Might be a typo in the doc.
3262                  * For now, for this unique transition scale selection, set bit
3263                  * 27 for ch0 and ch1.
3264                  */
3265                 for (i = 0; i < 4; i++) {
3266                         val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3267                         val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3268                         vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3269                 }
3270
3271                 for (i = 0; i < 4; i++) {
3272                         val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3273                         val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3274                         val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3275                         vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3276                 }
3277         }
3278
3279         /* Start swing calculation */
3280         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3281         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3282         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3283
3284         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3285         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3286         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
3287
3288         /* LRC Bypass */
3289         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
3290         val |= DPIO_LRC_BYPASS;
3291         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
3292
3293         mutex_unlock(&dev_priv->sb_lock);
3294
3295         return 0;
3296 }
3297
3298 static void
3299 intel_get_adjust_train(struct intel_dp *intel_dp,
3300                        const uint8_t link_status[DP_LINK_STATUS_SIZE])
3301 {
3302         uint8_t v = 0;
3303         uint8_t p = 0;
3304         int lane;
3305         uint8_t voltage_max;
3306         uint8_t preemph_max;
3307
3308         for (lane = 0; lane < intel_dp->lane_count; lane++) {
3309                 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
3310                 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
3311
3312                 if (this_v > v)
3313                         v = this_v;
3314                 if (this_p > p)
3315                         p = this_p;
3316         }
3317
3318         voltage_max = intel_dp_voltage_max(intel_dp);
3319         if (v >= voltage_max)
3320                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
3321
3322         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
3323         if (p >= preemph_max)
3324                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
3325
3326         for (lane = 0; lane < 4; lane++)
3327                 intel_dp->train_set[lane] = v | p;
3328 }
3329
3330 static uint32_t
3331 gen4_signal_levels(uint8_t train_set)
3332 {
3333         uint32_t        signal_levels = 0;
3334
3335         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3336         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3337         default:
3338                 signal_levels |= DP_VOLTAGE_0_4;
3339                 break;
3340         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3341                 signal_levels |= DP_VOLTAGE_0_6;
3342                 break;
3343         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3344                 signal_levels |= DP_VOLTAGE_0_8;
3345                 break;
3346         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3347                 signal_levels |= DP_VOLTAGE_1_2;
3348                 break;
3349         }
3350         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3351         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3352         default:
3353                 signal_levels |= DP_PRE_EMPHASIS_0;
3354                 break;
3355         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3356                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3357                 break;
3358         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3359                 signal_levels |= DP_PRE_EMPHASIS_6;
3360                 break;
3361         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3362                 signal_levels |= DP_PRE_EMPHASIS_9_5;
3363                 break;
3364         }
3365         return signal_levels;
3366 }
3367
3368 /* Gen6's DP voltage swing and pre-emphasis control */
3369 static uint32_t
3370 gen6_edp_signal_levels(uint8_t train_set)
3371 {
3372         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3373                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3374         switch (signal_levels) {
3375         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3376         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3377                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3378         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3379                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3380         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3381         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3382                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3383         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3384         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3385                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3386         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3387         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3388                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3389         default:
3390                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3391                               "0x%x\n", signal_levels);
3392                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3393         }
3394 }
3395
3396 /* Gen7's DP voltage swing and pre-emphasis control */
3397 static uint32_t
3398 gen7_edp_signal_levels(uint8_t train_set)
3399 {
3400         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3401                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3402         switch (signal_levels) {
3403         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3404                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3405         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3406                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3407         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3408                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3409
3410         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3411                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3412         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3413                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3414
3415         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3416                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3417         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3418                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3419
3420         default:
3421                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3422                               "0x%x\n", signal_levels);
3423                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3424         }
3425 }
3426
3427 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3428 static uint32_t
3429 hsw_signal_levels(uint8_t train_set)
3430 {
3431         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3432                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3433         switch (signal_levels) {
3434         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3435                 return DDI_BUF_TRANS_SELECT(0);
3436         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3437                 return DDI_BUF_TRANS_SELECT(1);
3438         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3439                 return DDI_BUF_TRANS_SELECT(2);
3440         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
3441                 return DDI_BUF_TRANS_SELECT(3);
3442
3443         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3444                 return DDI_BUF_TRANS_SELECT(4);
3445         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3446                 return DDI_BUF_TRANS_SELECT(5);
3447         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3448                 return DDI_BUF_TRANS_SELECT(6);
3449
3450         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3451                 return DDI_BUF_TRANS_SELECT(7);
3452         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3453                 return DDI_BUF_TRANS_SELECT(8);
3454
3455         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3456                 return DDI_BUF_TRANS_SELECT(9);
3457         default:
3458                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3459                               "0x%x\n", signal_levels);
3460                 return DDI_BUF_TRANS_SELECT(0);
3461         }
3462 }
3463
3464 static void bxt_signal_levels(struct intel_dp *intel_dp)
3465 {
3466         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3467         enum port port = dport->port;
3468         struct drm_device *dev = dport->base.base.dev;
3469         struct intel_encoder *encoder = &dport->base;
3470         uint8_t train_set = intel_dp->train_set[0];
3471         uint32_t level = 0;
3472
3473         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3474                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3475         switch (signal_levels) {
3476         default:
3477                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emph level\n");
3478         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3479                 level = 0;
3480                 break;
3481         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3482                 level = 1;
3483                 break;
3484         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3485                 level = 2;
3486                 break;
3487         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
3488                 level = 3;
3489                 break;
3490         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3491                 level = 4;
3492                 break;
3493         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3494                 level = 5;
3495                 break;
3496         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3497                 level = 6;
3498                 break;
3499         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3500                 level = 7;
3501                 break;
3502         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3503                 level = 8;
3504                 break;
3505         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3506                 level = 9;
3507                 break;
3508         }
3509
3510         bxt_ddi_vswing_sequence(dev, level, port, encoder->type);
3511 }
3512
3513 /* Properly updates "DP" with the correct signal levels. */
3514 static void
3515 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
3516 {
3517         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3518         enum port port = intel_dig_port->port;
3519         struct drm_device *dev = intel_dig_port->base.base.dev;
3520         uint32_t signal_levels, mask;
3521         uint8_t train_set = intel_dp->train_set[0];
3522
3523         if (IS_BROXTON(dev)) {
3524                 signal_levels = 0;
3525                 bxt_signal_levels(intel_dp);
3526                 mask = 0;
3527         } else if (HAS_DDI(dev)) {
3528                 signal_levels = hsw_signal_levels(train_set);
3529                 mask = DDI_BUF_EMP_MASK;
3530         } else if (IS_CHERRYVIEW(dev)) {
3531                 signal_levels = chv_signal_levels(intel_dp);
3532                 mask = 0;
3533         } else if (IS_VALLEYVIEW(dev)) {
3534                 signal_levels = vlv_signal_levels(intel_dp);
3535                 mask = 0;
3536         } else if (IS_GEN7(dev) && port == PORT_A) {
3537                 signal_levels = gen7_edp_signal_levels(train_set);
3538                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3539         } else if (IS_GEN6(dev) && port == PORT_A) {
3540                 signal_levels = gen6_edp_signal_levels(train_set);
3541                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3542         } else {
3543                 signal_levels = gen4_signal_levels(train_set);
3544                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3545         }
3546
3547         if (mask)
3548                 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3549
3550         DRM_DEBUG_KMS("Using vswing level %d\n",
3551                 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3552         DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3553                 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3554                         DP_TRAIN_PRE_EMPHASIS_SHIFT);
3555
3556         *DP = (*DP & ~mask) | signal_levels;
3557 }
3558
3559 static bool
3560 intel_dp_set_link_train(struct intel_dp *intel_dp,
3561                         uint32_t *DP,
3562                         uint8_t dp_train_pat)
3563 {
3564         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3565         struct drm_device *dev = intel_dig_port->base.base.dev;
3566         struct drm_i915_private *dev_priv = dev->dev_private;
3567         uint8_t buf[sizeof(intel_dp->train_set) + 1];
3568         int ret, len;
3569
3570         _intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3571
3572         I915_WRITE(intel_dp->output_reg, *DP);
3573         POSTING_READ(intel_dp->output_reg);
3574
3575         buf[0] = dp_train_pat;
3576         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
3577             DP_TRAINING_PATTERN_DISABLE) {
3578                 /* don't write DP_TRAINING_LANEx_SET on disable */
3579                 len = 1;
3580         } else {
3581                 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3582                 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3583                 len = intel_dp->lane_count + 1;
3584         }
3585
3586         ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3587                                 buf, len);
3588
3589         return ret == len;
3590 }
3591
3592 static bool
3593 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3594                         uint8_t dp_train_pat)
3595 {
3596         if (!intel_dp->train_set_valid)
3597                 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
3598         intel_dp_set_signal_levels(intel_dp, DP);
3599         return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3600 }
3601
3602 static bool
3603 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3604                            const uint8_t link_status[DP_LINK_STATUS_SIZE])
3605 {
3606         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3607         struct drm_device *dev = intel_dig_port->base.base.dev;
3608         struct drm_i915_private *dev_priv = dev->dev_private;
3609         int ret;
3610
3611         intel_get_adjust_train(intel_dp, link_status);
3612         intel_dp_set_signal_levels(intel_dp, DP);
3613
3614         I915_WRITE(intel_dp->output_reg, *DP);
3615         POSTING_READ(intel_dp->output_reg);
3616
3617         ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3618                                 intel_dp->train_set, intel_dp->lane_count);
3619
3620         return ret == intel_dp->lane_count;
3621 }
3622
3623 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3624 {
3625         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3626         struct drm_device *dev = intel_dig_port->base.base.dev;
3627         struct drm_i915_private *dev_priv = dev->dev_private;
3628         enum port port = intel_dig_port->port;
3629         uint32_t val;
3630
3631         if (!HAS_DDI(dev))
3632                 return;
3633
3634         val = I915_READ(DP_TP_CTL(port));
3635         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3636         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3637         I915_WRITE(DP_TP_CTL(port), val);
3638
3639         /*
3640          * On PORT_A we can have only eDP in SST mode. There the only reason
3641          * we need to set idle transmission mode is to work around a HW issue
3642          * where we enable the pipe while not in idle link-training mode.
3643          * In this case there is requirement to wait for a minimum number of
3644          * idle patterns to be sent.
3645          */
3646         if (port == PORT_A)
3647                 return;
3648
3649         if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3650                      1))
3651                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3652 }
3653
3654 /* Enable corresponding port and start training pattern 1 */
3655 void
3656 intel_dp_start_link_train(struct intel_dp *intel_dp)
3657 {
3658         struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
3659         struct drm_device *dev = encoder->dev;
3660         int i;
3661         uint8_t voltage;
3662         int voltage_tries, loop_tries;
3663         uint32_t DP = intel_dp->DP;
3664         uint8_t link_config[2];
3665
3666         if (HAS_DDI(dev))
3667                 intel_ddi_prepare_link_retrain(encoder);
3668
3669         /* Write the link configuration data */
3670         link_config[0] = intel_dp->link_bw;
3671         link_config[1] = intel_dp->lane_count;
3672         if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3673                 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
3674         drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
3675         if (intel_dp->num_sink_rates)
3676                 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
3677                                 &intel_dp->rate_select, 1);
3678
3679         link_config[0] = 0;
3680         link_config[1] = DP_SET_ANSI_8B10B;
3681         drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
3682
3683         DP |= DP_PORT_EN;
3684
3685         /* clock recovery */
3686         if (!intel_dp_reset_link_train(intel_dp, &DP,
3687                                        DP_TRAINING_PATTERN_1 |
3688                                        DP_LINK_SCRAMBLING_DISABLE)) {
3689                 DRM_ERROR("failed to enable link training\n");
3690                 return;
3691         }
3692
3693         voltage = 0xff;
3694         voltage_tries = 0;
3695         loop_tries = 0;
3696         for (;;) {
3697                 uint8_t link_status[DP_LINK_STATUS_SIZE];
3698
3699                 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
3700                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3701                         DRM_ERROR("failed to get link status\n");
3702                         break;
3703                 }
3704
3705                 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3706                         DRM_DEBUG_KMS("clock recovery OK\n");
3707                         break;
3708                 }
3709
3710                 /*
3711                  * if we used previously trained voltage and pre-emphasis values
3712                  * and we don't get clock recovery, reset link training values
3713                  */
3714                 if (intel_dp->train_set_valid) {
3715                         DRM_DEBUG_KMS("clock recovery not ok, reset");
3716                         /* clear the flag as we are not reusing train set */
3717                         intel_dp->train_set_valid = false;
3718                         if (!intel_dp_reset_link_train(intel_dp, &DP,
3719                                                        DP_TRAINING_PATTERN_1 |
3720                                                        DP_LINK_SCRAMBLING_DISABLE)) {
3721                                 DRM_ERROR("failed to enable link training\n");
3722                                 return;
3723                         }
3724                         continue;
3725                 }
3726
3727                 /* Check to see if we've tried the max voltage */
3728                 for (i = 0; i < intel_dp->lane_count; i++)
3729                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
3730                                 break;
3731                 if (i == intel_dp->lane_count) {
3732                         ++loop_tries;
3733                         if (loop_tries == 5) {
3734                                 DRM_ERROR("too many full retries, give up\n");
3735                                 break;
3736                         }
3737                         intel_dp_reset_link_train(intel_dp, &DP,
3738                                                   DP_TRAINING_PATTERN_1 |
3739                                                   DP_LINK_SCRAMBLING_DISABLE);
3740                         voltage_tries = 0;
3741                         continue;
3742                 }
3743
3744                 /* Check to see if we've tried the same voltage 5 times */
3745                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
3746                         ++voltage_tries;
3747                         if (voltage_tries == 5) {
3748                                 DRM_ERROR("too many voltage retries, give up\n");
3749                                 break;
3750                         }
3751                 } else
3752                         voltage_tries = 0;
3753                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
3754
3755                 /* Update training set as requested by target */
3756                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3757                         DRM_ERROR("failed to update link training\n");
3758                         break;
3759                 }
3760         }
3761
3762         intel_dp->DP = DP;
3763 }
3764
3765 void
3766 intel_dp_complete_link_train(struct intel_dp *intel_dp)
3767 {
3768         bool channel_eq = false;
3769         int tries, cr_tries;
3770         uint32_t DP = intel_dp->DP;
3771         uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3772
3773         /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3774         if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3775                 training_pattern = DP_TRAINING_PATTERN_3;
3776
3777         /* channel equalization */
3778         if (!intel_dp_set_link_train(intel_dp, &DP,
3779                                      training_pattern |
3780                                      DP_LINK_SCRAMBLING_DISABLE)) {
3781                 DRM_ERROR("failed to start channel equalization\n");
3782                 return;
3783         }
3784
3785         tries = 0;
3786         cr_tries = 0;
3787         channel_eq = false;
3788         for (;;) {
3789                 uint8_t link_status[DP_LINK_STATUS_SIZE];
3790
3791                 if (cr_tries > 5) {
3792                         DRM_ERROR("failed to train DP, aborting\n");
3793                         break;
3794                 }
3795
3796                 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
3797                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3798                         DRM_ERROR("failed to get link status\n");
3799                         break;
3800                 }
3801
3802                 /* Make sure clock is still ok */
3803                 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3804                         intel_dp->train_set_valid = false;
3805                         intel_dp_start_link_train(intel_dp);
3806                         intel_dp_set_link_train(intel_dp, &DP,
3807                                                 training_pattern |
3808                                                 DP_LINK_SCRAMBLING_DISABLE);
3809                         cr_tries++;
3810                         continue;
3811                 }
3812
3813                 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3814                         channel_eq = true;
3815                         break;
3816                 }
3817
3818                 /* Try 5 times, then try clock recovery if that fails */
3819                 if (tries > 5) {
3820                         intel_dp->train_set_valid = false;
3821                         intel_dp_start_link_train(intel_dp);
3822                         intel_dp_set_link_train(intel_dp, &DP,
3823                                                 training_pattern |
3824                                                 DP_LINK_SCRAMBLING_DISABLE);
3825                         tries = 0;
3826                         cr_tries++;
3827                         continue;
3828                 }
3829
3830                 /* Update training set as requested by target */
3831                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3832                         DRM_ERROR("failed to update link training\n");
3833                         break;
3834                 }
3835                 ++tries;
3836         }
3837
3838         intel_dp_set_idle_link_train(intel_dp);
3839
3840         intel_dp->DP = DP;
3841
3842         if (channel_eq) {
3843                 intel_dp->train_set_valid = true;
3844                 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3845         }
3846 }
3847
3848 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3849 {
3850         intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3851                                 DP_TRAINING_PATTERN_DISABLE);
3852 }
3853
3854 static void
3855 intel_dp_link_down(struct intel_dp *intel_dp)
3856 {
3857         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3858         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
3859         enum port port = intel_dig_port->port;
3860         struct drm_device *dev = intel_dig_port->base.base.dev;
3861         struct drm_i915_private *dev_priv = dev->dev_private;
3862         uint32_t DP = intel_dp->DP;
3863
3864         if (WARN_ON(HAS_DDI(dev)))
3865                 return;
3866
3867         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3868                 return;
3869
3870         DRM_DEBUG_KMS("\n");
3871
3872         if ((IS_GEN7(dev) && port == PORT_A) ||
3873             (HAS_PCH_CPT(dev) && port != PORT_A)) {
3874                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3875                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3876         } else {
3877                 if (IS_CHERRYVIEW(dev))
3878                         DP &= ~DP_LINK_TRAIN_MASK_CHV;
3879                 else
3880                         DP &= ~DP_LINK_TRAIN_MASK;
3881                 DP |= DP_LINK_TRAIN_PAT_IDLE;
3882         }
3883         I915_WRITE(intel_dp->output_reg, DP);
3884         POSTING_READ(intel_dp->output_reg);
3885
3886         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3887         I915_WRITE(intel_dp->output_reg, DP);
3888         POSTING_READ(intel_dp->output_reg);
3889
3890         /*
3891          * HW workaround for IBX, we need to move the port
3892          * to transcoder A after disabling it to allow the
3893          * matching HDMI port to be enabled on transcoder A.
3894          */
3895         if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) {
3896                 /* always enable with pattern 1 (as per spec) */
3897                 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3898                 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3899                 I915_WRITE(intel_dp->output_reg, DP);
3900                 POSTING_READ(intel_dp->output_reg);
3901
3902                 DP &= ~DP_PORT_EN;
3903                 I915_WRITE(intel_dp->output_reg, DP);
3904                 POSTING_READ(intel_dp->output_reg);
3905         }
3906
3907         msleep(intel_dp->panel_power_down_delay);
3908 }
3909
3910 static bool
3911 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3912 {
3913         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3914         struct drm_device *dev = dig_port->base.base.dev;
3915         struct drm_i915_private *dev_priv = dev->dev_private;
3916         uint8_t rev;
3917
3918         if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3919                                     sizeof(intel_dp->dpcd)) < 0)
3920                 return false; /* aux transfer failed */
3921
3922         DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3923
3924         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3925                 return false; /* DPCD not present */
3926
3927         /* Check if the panel supports PSR */
3928         memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
3929         if (is_edp(intel_dp)) {
3930                 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3931                                         intel_dp->psr_dpcd,
3932                                         sizeof(intel_dp->psr_dpcd));
3933                 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3934                         dev_priv->psr.sink_support = true;
3935                         DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3936                 }
3937
3938                 if (INTEL_INFO(dev)->gen >= 9 &&
3939                         (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3940                         uint8_t frame_sync_cap;
3941
3942                         dev_priv->psr.sink_support = true;
3943                         intel_dp_dpcd_read_wake(&intel_dp->aux,
3944                                         DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3945                                         &frame_sync_cap, 1);
3946                         dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3947                         /* PSR2 needs frame sync as well */
3948                         dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3949                         DRM_DEBUG_KMS("PSR2 %s on sink",
3950                                 dev_priv->psr.psr2_support ? "supported" : "not supported");
3951                 }
3952         }
3953
3954         /* Training Pattern 3 support, both source and sink */
3955         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3956             intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED &&
3957             (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)) {
3958                 intel_dp->use_tps3 = true;
3959                 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
3960         } else
3961                 intel_dp->use_tps3 = false;
3962
3963         /* Intermediate frequency support */
3964         if (is_edp(intel_dp) &&
3965             (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3966             (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) &&
3967             (rev >= 0x03)) { /* eDp v1.4 or higher */
3968                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3969                 int i;
3970
3971                 intel_dp_dpcd_read_wake(&intel_dp->aux,
3972                                 DP_SUPPORTED_LINK_RATES,
3973                                 sink_rates,
3974                                 sizeof(sink_rates));
3975
3976                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3977                         int val = le16_to_cpu(sink_rates[i]);
3978
3979                         if (val == 0)
3980                                 break;
3981
3982                         /* Value read is in kHz while drm clock is saved in deca-kHz */
3983                         intel_dp->sink_rates[i] = (val * 200) / 10;
3984                 }
3985                 intel_dp->num_sink_rates = i;
3986         }
3987
3988         intel_dp_print_rates(intel_dp);
3989
3990         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3991               DP_DWN_STRM_PORT_PRESENT))
3992                 return true; /* native DP sink */
3993
3994         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3995                 return true; /* no per-port downstream info */
3996
3997         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3998                                     intel_dp->downstream_ports,
3999                                     DP_MAX_DOWNSTREAM_PORTS) < 0)
4000                 return false; /* downstream port status fetch failed */
4001
4002         return true;
4003 }
4004
4005 static void
4006 intel_dp_probe_oui(struct intel_dp *intel_dp)
4007 {
4008         u8 buf[3];
4009
4010         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
4011                 return;
4012
4013         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
4014                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
4015                               buf[0], buf[1], buf[2]);
4016
4017         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
4018                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
4019                               buf[0], buf[1], buf[2]);
4020 }
4021
4022 static bool
4023 intel_dp_probe_mst(struct intel_dp *intel_dp)
4024 {
4025         u8 buf[1];
4026
4027         if (!intel_dp->can_mst)
4028                 return false;
4029
4030         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
4031                 return false;
4032
4033         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
4034                 if (buf[0] & DP_MST_CAP) {
4035                         DRM_DEBUG_KMS("Sink is MST capable\n");
4036                         intel_dp->is_mst = true;
4037                 } else {
4038                         DRM_DEBUG_KMS("Sink is not MST capable\n");
4039                         intel_dp->is_mst = false;
4040                 }
4041         }
4042
4043         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4044         return intel_dp->is_mst;
4045 }
4046
4047 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
4048 {
4049         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4050         struct drm_device *dev = intel_dig_port->base.base.dev;
4051         struct intel_crtc *intel_crtc =
4052                 to_intel_crtc(intel_dig_port->base.base.crtc);
4053         u8 buf;
4054         int test_crc_count;
4055         int attempts = 6;
4056         int ret = 0;
4057
4058         hsw_disable_ips(intel_crtc);
4059
4060         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0) {
4061                 ret = -EIO;
4062                 goto out;
4063         }
4064
4065         if (!(buf & DP_TEST_CRC_SUPPORTED)) {
4066                 ret = -ENOTTY;
4067                 goto out;
4068         }
4069
4070         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
4071                 ret = -EIO;
4072                 goto out;
4073         }
4074
4075         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
4076                                 buf | DP_TEST_SINK_START) < 0) {
4077                 ret = -EIO;
4078                 goto out;
4079         }
4080
4081         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0) {
4082                 ret = -EIO;
4083                 goto out;
4084         }
4085
4086         test_crc_count = buf & DP_TEST_COUNT_MASK;
4087
4088         do {
4089                 if (drm_dp_dpcd_readb(&intel_dp->aux,
4090                                       DP_TEST_SINK_MISC, &buf) < 0) {
4091                         ret = -EIO;
4092                         goto out;
4093                 }
4094                 intel_wait_for_vblank(dev, intel_crtc->pipe);
4095         } while (--attempts && (buf & DP_TEST_COUNT_MASK) == test_crc_count);
4096
4097         if (attempts == 0) {
4098                 DRM_DEBUG_KMS("Panel is unable to calculate CRC after 6 vblanks\n");
4099                 ret = -ETIMEDOUT;
4100                 goto out;
4101         }
4102
4103         if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
4104                 ret = -EIO;
4105                 goto out;
4106         }
4107
4108         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
4109                 ret = -EIO;
4110                 goto out;
4111         }
4112         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
4113                                buf & ~DP_TEST_SINK_START) < 0) {
4114                 ret = -EIO;
4115                 goto out;
4116         }
4117 out:
4118         hsw_enable_ips(intel_crtc);
4119         return ret;
4120 }
4121
4122 static bool
4123 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4124 {
4125         return intel_dp_dpcd_read_wake(&intel_dp->aux,
4126                                        DP_DEVICE_SERVICE_IRQ_VECTOR,
4127                                        sink_irq_vector, 1) == 1;
4128 }
4129
4130 static bool
4131 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4132 {
4133         int ret;
4134
4135         ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
4136                                              DP_SINK_COUNT_ESI,
4137                                              sink_irq_vector, 14);
4138         if (ret != 14)
4139                 return false;
4140
4141         return true;
4142 }
4143
4144 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4145 {
4146         uint8_t test_result = DP_TEST_ACK;
4147         return test_result;
4148 }
4149
4150 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4151 {
4152         uint8_t test_result = DP_TEST_NAK;
4153         return test_result;
4154 }
4155
4156 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
4157 {
4158         uint8_t test_result = DP_TEST_NAK;
4159         struct intel_connector *intel_connector = intel_dp->attached_connector;
4160         struct drm_connector *connector = &intel_connector->base;
4161
4162         if (intel_connector->detect_edid == NULL ||
4163             connector->edid_corrupt ||
4164             intel_dp->aux.i2c_defer_count > 6) {
4165                 /* Check EDID read for NACKs, DEFERs and corruption
4166                  * (DP CTS 1.2 Core r1.1)
4167                  *    4.2.2.4 : Failed EDID read, I2C_NAK
4168                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
4169                  *    4.2.2.6 : EDID corruption detected
4170                  * Use failsafe mode for all cases
4171                  */
4172                 if (intel_dp->aux.i2c_nack_count > 0 ||
4173                         intel_dp->aux.i2c_defer_count > 0)
4174                         DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4175                                       intel_dp->aux.i2c_nack_count,
4176                                       intel_dp->aux.i2c_defer_count);
4177                 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE;
4178         } else {
4179                 if (!drm_dp_dpcd_write(&intel_dp->aux,
4180                                         DP_TEST_EDID_CHECKSUM,
4181                                         &intel_connector->detect_edid->checksum,
4182                                         1))
4183                         DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4184
4185                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4186                 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD;
4187         }
4188
4189         /* Set test active flag here so userspace doesn't interrupt things */
4190         intel_dp->compliance_test_active = 1;
4191
4192         return test_result;
4193 }
4194
4195 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4196 {
4197         uint8_t test_result = DP_TEST_NAK;
4198         return test_result;
4199 }
4200
4201 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4202 {
4203         uint8_t response = DP_TEST_NAK;
4204         uint8_t rxdata = 0;
4205         int status = 0;
4206
4207         intel_dp->compliance_test_active = 0;
4208         intel_dp->compliance_test_type = 0;
4209         intel_dp->compliance_test_data = 0;
4210
4211         intel_dp->aux.i2c_nack_count = 0;
4212         intel_dp->aux.i2c_defer_count = 0;
4213
4214         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1);
4215         if (status <= 0) {
4216                 DRM_DEBUG_KMS("Could not read test request from sink\n");
4217                 goto update_status;
4218         }
4219
4220         switch (rxdata) {
4221         case DP_TEST_LINK_TRAINING:
4222                 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4223                 intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING;
4224                 response = intel_dp_autotest_link_training(intel_dp);
4225                 break;
4226         case DP_TEST_LINK_VIDEO_PATTERN:
4227                 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4228                 intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN;
4229                 response = intel_dp_autotest_video_pattern(intel_dp);
4230                 break;
4231         case DP_TEST_LINK_EDID_READ:
4232                 DRM_DEBUG_KMS("EDID test requested\n");
4233                 intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ;
4234                 response = intel_dp_autotest_edid(intel_dp);
4235                 break;
4236         case DP_TEST_LINK_PHY_TEST_PATTERN:
4237                 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4238                 intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN;
4239                 response = intel_dp_autotest_phy_pattern(intel_dp);
4240                 break;
4241         default:
4242                 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata);
4243                 break;
4244         }
4245
4246 update_status:
4247         status = drm_dp_dpcd_write(&intel_dp->aux,
4248                                    DP_TEST_RESPONSE,
4249                                    &response, 1);
4250         if (status <= 0)
4251                 DRM_DEBUG_KMS("Could not write test response to sink\n");
4252 }
4253
4254 static int
4255 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4256 {
4257         bool bret;
4258
4259         if (intel_dp->is_mst) {
4260                 u8 esi[16] = { 0 };
4261                 int ret = 0;
4262                 int retry;
4263                 bool handled;
4264                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4265 go_again:
4266                 if (bret == true) {
4267
4268                         /* check link status - esi[10] = 0x200c */
4269                         if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4270                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4271                                 intel_dp_start_link_train(intel_dp);
4272                                 intel_dp_complete_link_train(intel_dp);
4273                                 intel_dp_stop_link_train(intel_dp);
4274                         }
4275
4276                         DRM_DEBUG_KMS("got esi %3ph\n", esi);
4277                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4278
4279                         if (handled) {
4280                                 for (retry = 0; retry < 3; retry++) {
4281                                         int wret;
4282                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
4283                                                                  DP_SINK_COUNT_ESI+1,
4284                                                                  &esi[1], 3);
4285                                         if (wret == 3) {
4286                                                 break;
4287                                         }
4288                                 }
4289
4290                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4291                                 if (bret == true) {
4292                                         DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4293                                         goto go_again;
4294                                 }
4295                         } else
4296                                 ret = 0;
4297
4298                         return ret;
4299                 } else {
4300                         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4301                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4302                         intel_dp->is_mst = false;
4303                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4304                         /* send a hotplug event */
4305                         drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4306                 }
4307         }
4308         return -EINVAL;
4309 }
4310
4311 /*
4312  * According to DP spec
4313  * 5.1.2:
4314  *  1. Read DPCD
4315  *  2. Configure link according to Receiver Capabilities
4316  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
4317  *  4. Check link status on receipt of hot-plug interrupt
4318  */
4319 static void
4320 intel_dp_check_link_status(struct intel_dp *intel_dp)
4321 {
4322         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4323         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4324         u8 sink_irq_vector;
4325         u8 link_status[DP_LINK_STATUS_SIZE];
4326
4327         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4328
4329         if (!intel_encoder->connectors_active)
4330                 return;
4331
4332         if (WARN_ON(!intel_encoder->base.crtc))
4333                 return;
4334
4335         if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4336                 return;
4337
4338         /* Try to read receiver status if the link appears to be up */
4339         if (!intel_dp_get_link_status(intel_dp, link_status)) {
4340                 return;
4341         }
4342
4343         /* Now read the DPCD to see if it's actually running */
4344         if (!intel_dp_get_dpcd(intel_dp)) {
4345                 return;
4346         }
4347
4348         /* Try to read the source of the interrupt */
4349         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4350             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4351                 /* Clear interrupt source */
4352                 drm_dp_dpcd_writeb(&intel_dp->aux,
4353                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4354                                    sink_irq_vector);
4355
4356                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4357                         DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
4358                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4359                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4360         }
4361
4362         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
4363                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4364                               intel_encoder->base.name);
4365                 intel_dp_start_link_train(intel_dp);
4366                 intel_dp_complete_link_train(intel_dp);
4367                 intel_dp_stop_link_train(intel_dp);
4368         }
4369 }
4370
4371 /* XXX this is probably wrong for multiple downstream ports */
4372 static enum drm_connector_status
4373 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4374 {
4375         uint8_t *dpcd = intel_dp->dpcd;
4376         uint8_t type;
4377
4378         if (!intel_dp_get_dpcd(intel_dp))
4379                 return connector_status_disconnected;
4380
4381         /* if there's no downstream port, we're done */
4382         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
4383                 return connector_status_connected;
4384
4385         /* If we're HPD-aware, SINK_COUNT changes dynamically */
4386         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4387             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4388                 uint8_t reg;
4389
4390                 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
4391                                             &reg, 1) < 0)
4392                         return connector_status_unknown;
4393
4394                 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
4395                                               : connector_status_disconnected;
4396         }
4397
4398         /* If no HPD, poke DDC gently */
4399         if (drm_probe_ddc(&intel_dp->aux.ddc))
4400                 return connector_status_connected;
4401
4402         /* Well we tried, say unknown for unreliable port types */
4403         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4404                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4405                 if (type == DP_DS_PORT_TYPE_VGA ||
4406                     type == DP_DS_PORT_TYPE_NON_EDID)
4407                         return connector_status_unknown;
4408         } else {
4409                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4410                         DP_DWN_STRM_PORT_TYPE_MASK;
4411                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4412                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
4413                         return connector_status_unknown;
4414         }
4415
4416         /* Anything else is out of spec, warn and ignore */
4417         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4418         return connector_status_disconnected;
4419 }
4420
4421 static enum drm_connector_status
4422 edp_detect(struct intel_dp *intel_dp)
4423 {
4424         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4425         enum drm_connector_status status;
4426
4427         status = intel_panel_detect(dev);
4428         if (status == connector_status_unknown)
4429                 status = connector_status_connected;
4430
4431         return status;
4432 }
4433
4434 static enum drm_connector_status
4435 ironlake_dp_detect(struct intel_dp *intel_dp)
4436 {
4437         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4438         struct drm_i915_private *dev_priv = dev->dev_private;
4439         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4440
4441         if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4442                 return connector_status_disconnected;
4443
4444         return intel_dp_detect_dpcd(intel_dp);
4445 }
4446
4447 static int g4x_digital_port_connected(struct drm_device *dev,
4448                                        struct intel_digital_port *intel_dig_port)
4449 {
4450         struct drm_i915_private *dev_priv = dev->dev_private;
4451         uint32_t bit;
4452
4453         if (IS_VALLEYVIEW(dev)) {
4454                 switch (intel_dig_port->port) {
4455                 case PORT_B:
4456                         bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
4457                         break;
4458                 case PORT_C:
4459                         bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
4460                         break;
4461                 case PORT_D:
4462                         bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
4463                         break;
4464                 default:
4465                         return -EINVAL;
4466                 }
4467         } else {
4468                 switch (intel_dig_port->port) {
4469                 case PORT_B:
4470                         bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4471                         break;
4472                 case PORT_C:
4473                         bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4474                         break;
4475                 case PORT_D:
4476                         bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4477                         break;
4478                 default:
4479                         return -EINVAL;
4480                 }
4481         }
4482
4483         if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
4484                 return 0;
4485         return 1;
4486 }
4487
4488 static enum drm_connector_status
4489 g4x_dp_detect(struct intel_dp *intel_dp)
4490 {
4491         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4492         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4493         int ret;
4494
4495         /* Can't disconnect eDP, but you can close the lid... */
4496         if (is_edp(intel_dp)) {
4497                 enum drm_connector_status status;
4498
4499                 status = intel_panel_detect(dev);
4500                 if (status == connector_status_unknown)
4501                         status = connector_status_connected;
4502                 return status;
4503         }
4504
4505         ret = g4x_digital_port_connected(dev, intel_dig_port);
4506         if (ret == -EINVAL)
4507                 return connector_status_unknown;
4508         else if (ret == 0)
4509                 return connector_status_disconnected;
4510
4511         return intel_dp_detect_dpcd(intel_dp);
4512 }
4513
4514 static struct edid *
4515 intel_dp_get_edid(struct intel_dp *intel_dp)
4516 {
4517         struct intel_connector *intel_connector = intel_dp->attached_connector;
4518
4519         /* use cached edid if we have one */
4520         if (intel_connector->edid) {
4521                 /* invalid edid */
4522                 if (IS_ERR(intel_connector->edid))
4523                         return NULL;
4524
4525                 return drm_edid_duplicate(intel_connector->edid);
4526         } else
4527                 return drm_get_edid(&intel_connector->base,
4528                                     &intel_dp->aux.ddc);
4529 }
4530
4531 static void
4532 intel_dp_set_edid(struct intel_dp *intel_dp)
4533 {
4534         struct intel_connector *intel_connector = intel_dp->attached_connector;
4535         struct edid *edid;
4536
4537         edid = intel_dp_get_edid(intel_dp);
4538         intel_connector->detect_edid = edid;
4539
4540         if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4541                 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4542         else
4543                 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4544 }
4545
4546 static void
4547 intel_dp_unset_edid(struct intel_dp *intel_dp)
4548 {
4549         struct intel_connector *intel_connector = intel_dp->attached_connector;
4550
4551         kfree(intel_connector->detect_edid);
4552         intel_connector->detect_edid = NULL;
4553
4554         intel_dp->has_audio = false;
4555 }
4556
4557 static enum intel_display_power_domain
4558 intel_dp_power_get(struct intel_dp *dp)
4559 {
4560         struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4561         enum intel_display_power_domain power_domain;
4562
4563         power_domain = intel_display_port_power_domain(encoder);
4564         intel_display_power_get(to_i915(encoder->base.dev), power_domain);
4565
4566         return power_domain;
4567 }
4568
4569 static void
4570 intel_dp_power_put(struct intel_dp *dp,
4571                    enum intel_display_power_domain power_domain)
4572 {
4573         struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4574         intel_display_power_put(to_i915(encoder->base.dev), power_domain);
4575 }
4576
4577 static enum drm_connector_status
4578 intel_dp_detect(struct drm_connector *connector, bool force)
4579 {
4580         struct intel_dp *intel_dp = intel_attached_dp(connector);
4581         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4582         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4583         struct drm_device *dev = connector->dev;
4584         enum drm_connector_status status;
4585         enum intel_display_power_domain power_domain;
4586         bool ret;
4587         u8 sink_irq_vector;
4588
4589         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4590                       connector->base.id, connector->name);
4591         intel_dp_unset_edid(intel_dp);
4592
4593         if (intel_dp->is_mst) {
4594                 /* MST devices are disconnected from a monitor POV */
4595                 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4596                         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4597                 return connector_status_disconnected;
4598         }
4599
4600         power_domain = intel_dp_power_get(intel_dp);
4601
4602         /* Can't disconnect eDP, but you can close the lid... */
4603         if (is_edp(intel_dp))
4604                 status = edp_detect(intel_dp);
4605         else if (HAS_PCH_SPLIT(dev))
4606                 status = ironlake_dp_detect(intel_dp);
4607         else
4608                 status = g4x_dp_detect(intel_dp);
4609         if (status != connector_status_connected)
4610                 goto out;
4611
4612         intel_dp_probe_oui(intel_dp);
4613
4614         ret = intel_dp_probe_mst(intel_dp);
4615         if (ret) {
4616                 /* if we are in MST mode then this connector
4617                    won't appear connected or have anything with EDID on it */
4618                 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4619                         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4620                 status = connector_status_disconnected;
4621                 goto out;
4622         }
4623
4624         intel_dp_set_edid(intel_dp);
4625
4626         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4627                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4628         status = connector_status_connected;
4629
4630         /* Try to read the source of the interrupt */
4631         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4632             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4633                 /* Clear interrupt source */
4634                 drm_dp_dpcd_writeb(&intel_dp->aux,
4635                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4636                                    sink_irq_vector);
4637
4638                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4639                         intel_dp_handle_test_request(intel_dp);
4640                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4641                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4642         }
4643
4644 out:
4645         intel_dp_power_put(intel_dp, power_domain);
4646         return status;
4647 }
4648
4649 static void
4650 intel_dp_force(struct drm_connector *connector)
4651 {
4652         struct intel_dp *intel_dp = intel_attached_dp(connector);
4653         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4654         enum intel_display_power_domain power_domain;
4655
4656         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4657                       connector->base.id, connector->name);
4658         intel_dp_unset_edid(intel_dp);
4659
4660         if (connector->status != connector_status_connected)
4661                 return;
4662
4663         power_domain = intel_dp_power_get(intel_dp);
4664
4665         intel_dp_set_edid(intel_dp);
4666
4667         intel_dp_power_put(intel_dp, power_domain);
4668
4669         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4670                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4671 }
4672
4673 static int intel_dp_get_modes(struct drm_connector *connector)
4674 {
4675         struct intel_connector *intel_connector = to_intel_connector(connector);
4676         struct edid *edid;
4677
4678         edid = intel_connector->detect_edid;
4679         if (edid) {
4680                 int ret = intel_connector_update_modes(connector, edid);
4681                 if (ret)
4682                         return ret;
4683         }
4684
4685         /* if eDP has no EDID, fall back to fixed mode */
4686         if (is_edp(intel_attached_dp(connector)) &&
4687             intel_connector->panel.fixed_mode) {
4688                 struct drm_display_mode *mode;
4689
4690                 mode = drm_mode_duplicate(connector->dev,
4691                                           intel_connector->panel.fixed_mode);
4692                 if (mode) {
4693                         drm_mode_probed_add(connector, mode);
4694                         return 1;
4695                 }
4696         }
4697
4698         return 0;
4699 }
4700
4701 static bool
4702 intel_dp_detect_audio(struct drm_connector *connector)
4703 {
4704         bool has_audio = false;
4705         struct edid *edid;
4706
4707         edid = to_intel_connector(connector)->detect_edid;
4708         if (edid)
4709                 has_audio = drm_detect_monitor_audio(edid);
4710
4711         return has_audio;
4712 }
4713
4714 static int
4715 intel_dp_set_property(struct drm_connector *connector,
4716                       struct drm_property *property,
4717                       uint64_t val)
4718 {
4719         struct drm_i915_private *dev_priv = connector->dev->dev_private;
4720         struct intel_connector *intel_connector = to_intel_connector(connector);
4721         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4722         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4723         int ret;
4724
4725         ret = drm_object_property_set_value(&connector->base, property, val);
4726         if (ret)
4727                 return ret;
4728
4729         if (property == dev_priv->force_audio_property) {
4730                 int i = val;
4731                 bool has_audio;
4732
4733                 if (i == intel_dp->force_audio)
4734                         return 0;
4735
4736                 intel_dp->force_audio = i;
4737
4738                 if (i == HDMI_AUDIO_AUTO)
4739                         has_audio = intel_dp_detect_audio(connector);
4740                 else
4741                         has_audio = (i == HDMI_AUDIO_ON);
4742
4743                 if (has_audio == intel_dp->has_audio)
4744                         return 0;
4745
4746                 intel_dp->has_audio = has_audio;
4747                 goto done;
4748         }
4749
4750         if (property == dev_priv->broadcast_rgb_property) {
4751                 bool old_auto = intel_dp->color_range_auto;
4752                 uint32_t old_range = intel_dp->color_range;
4753
4754                 switch (val) {
4755                 case INTEL_BROADCAST_RGB_AUTO:
4756                         intel_dp->color_range_auto = true;
4757                         break;
4758                 case INTEL_BROADCAST_RGB_FULL:
4759                         intel_dp->color_range_auto = false;
4760                         intel_dp->color_range = 0;
4761                         break;
4762                 case INTEL_BROADCAST_RGB_LIMITED:
4763                         intel_dp->color_range_auto = false;
4764                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
4765                         break;
4766                 default:
4767                         return -EINVAL;
4768                 }
4769
4770                 if (old_auto == intel_dp->color_range_auto &&
4771                     old_range == intel_dp->color_range)
4772                         return 0;
4773
4774                 goto done;
4775         }
4776
4777         if (is_edp(intel_dp) &&
4778             property == connector->dev->mode_config.scaling_mode_property) {
4779                 if (val == DRM_MODE_SCALE_NONE) {
4780                         DRM_DEBUG_KMS("no scaling not supported\n");
4781                         return -EINVAL;
4782                 }
4783
4784                 if (intel_connector->panel.fitting_mode == val) {
4785                         /* the eDP scaling property is not changed */
4786                         return 0;
4787                 }
4788                 intel_connector->panel.fitting_mode = val;
4789
4790                 goto done;
4791         }
4792
4793         return -EINVAL;
4794
4795 done:
4796         if (intel_encoder->base.crtc)
4797                 intel_crtc_restore_mode(intel_encoder->base.crtc);
4798
4799         return 0;
4800 }
4801
4802 static void
4803 intel_dp_connector_destroy(struct drm_connector *connector)
4804 {
4805         struct intel_connector *intel_connector = to_intel_connector(connector);
4806
4807         kfree(intel_connector->detect_edid);
4808
4809         if (!IS_ERR_OR_NULL(intel_connector->edid))
4810                 kfree(intel_connector->edid);
4811
4812         /* Can't call is_edp() since the encoder may have been destroyed
4813          * already. */
4814         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4815                 intel_panel_fini(&intel_connector->panel);
4816
4817         drm_connector_cleanup(connector);
4818         kfree(connector);
4819 }
4820
4821 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4822 {
4823         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4824         struct intel_dp *intel_dp = &intel_dig_port->dp;
4825
4826         drm_dp_aux_unregister(&intel_dp->aux);
4827         intel_dp_mst_encoder_cleanup(intel_dig_port);
4828         if (is_edp(intel_dp)) {
4829                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4830                 /*
4831                  * vdd might still be enabled do to the delayed vdd off.
4832                  * Make sure vdd is actually turned off here.
4833                  */
4834                 pps_lock(intel_dp);
4835                 edp_panel_vdd_off_sync(intel_dp);
4836                 pps_unlock(intel_dp);
4837
4838                 if (intel_dp->edp_notifier.notifier_call) {
4839                         unregister_reboot_notifier(&intel_dp->edp_notifier);
4840                         intel_dp->edp_notifier.notifier_call = NULL;
4841                 }
4842         }
4843         drm_encoder_cleanup(encoder);
4844         kfree(intel_dig_port);
4845 }
4846
4847 static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4848 {
4849         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4850
4851         if (!is_edp(intel_dp))
4852                 return;
4853
4854         /*
4855          * vdd might still be enabled do to the delayed vdd off.
4856          * Make sure vdd is actually turned off here.
4857          */
4858         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4859         pps_lock(intel_dp);
4860         edp_panel_vdd_off_sync(intel_dp);
4861         pps_unlock(intel_dp);
4862 }
4863
4864 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4865 {
4866         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4867         struct drm_device *dev = intel_dig_port->base.base.dev;
4868         struct drm_i915_private *dev_priv = dev->dev_private;
4869         enum intel_display_power_domain power_domain;
4870
4871         lockdep_assert_held(&dev_priv->pps_mutex);
4872
4873         if (!edp_have_panel_vdd(intel_dp))
4874                 return;
4875
4876         /*
4877          * The VDD bit needs a power domain reference, so if the bit is
4878          * already enabled when we boot or resume, grab this reference and
4879          * schedule a vdd off, so we don't hold on to the reference
4880          * indefinitely.
4881          */
4882         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4883         power_domain = intel_display_port_power_domain(&intel_dig_port->base);
4884         intel_display_power_get(dev_priv, power_domain);
4885
4886         edp_panel_vdd_schedule_off(intel_dp);
4887 }
4888
4889 static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4890 {
4891         struct intel_dp *intel_dp;
4892
4893         if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4894                 return;
4895
4896         intel_dp = enc_to_intel_dp(encoder);
4897
4898         pps_lock(intel_dp);
4899
4900         /*
4901          * Read out the current power sequencer assignment,
4902          * in case the BIOS did something with it.
4903          */
4904         if (IS_VALLEYVIEW(encoder->dev))
4905                 vlv_initial_power_sequencer_setup(intel_dp);
4906
4907         intel_edp_panel_vdd_sanitize(intel_dp);
4908
4909         pps_unlock(intel_dp);
4910 }
4911
4912 static const struct drm_connector_funcs intel_dp_connector_funcs = {
4913         .dpms = intel_connector_dpms,
4914         .detect = intel_dp_detect,
4915         .force = intel_dp_force,
4916         .fill_modes = drm_helper_probe_single_connector_modes,
4917         .set_property = intel_dp_set_property,
4918         .atomic_get_property = intel_connector_atomic_get_property,
4919         .destroy = intel_dp_connector_destroy,
4920         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
4921         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
4922 };
4923
4924 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4925         .get_modes = intel_dp_get_modes,
4926         .mode_valid = intel_dp_mode_valid,
4927         .best_encoder = intel_best_encoder,
4928 };
4929
4930 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
4931         .reset = intel_dp_encoder_reset,
4932         .destroy = intel_dp_encoder_destroy,
4933 };
4934
4935 enum irqreturn
4936 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4937 {
4938         struct intel_dp *intel_dp = &intel_dig_port->dp;
4939         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4940         struct drm_device *dev = intel_dig_port->base.base.dev;
4941         struct drm_i915_private *dev_priv = dev->dev_private;
4942         enum intel_display_power_domain power_domain;
4943         enum irqreturn ret = IRQ_NONE;
4944
4945         if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4946                 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
4947
4948         if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4949                 /*
4950                  * vdd off can generate a long pulse on eDP which
4951                  * would require vdd on to handle it, and thus we
4952                  * would end up in an endless cycle of
4953                  * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4954                  */
4955                 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4956                               port_name(intel_dig_port->port));
4957                 return IRQ_HANDLED;
4958         }
4959
4960         DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4961                       port_name(intel_dig_port->port),
4962                       long_hpd ? "long" : "short");
4963
4964         power_domain = intel_display_port_power_domain(intel_encoder);
4965         intel_display_power_get(dev_priv, power_domain);
4966
4967         if (long_hpd) {
4968                 /* indicate that we need to restart link training */
4969                 intel_dp->train_set_valid = false;
4970
4971                 if (HAS_PCH_SPLIT(dev)) {
4972                         if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4973                                 goto mst_fail;
4974                 } else {
4975                         if (g4x_digital_port_connected(dev, intel_dig_port) != 1)
4976                                 goto mst_fail;
4977                 }
4978
4979                 if (!intel_dp_get_dpcd(intel_dp)) {
4980                         goto mst_fail;
4981                 }
4982
4983                 intel_dp_probe_oui(intel_dp);
4984
4985                 if (!intel_dp_probe_mst(intel_dp))
4986                         goto mst_fail;
4987
4988         } else {
4989                 if (intel_dp->is_mst) {
4990                         if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
4991                                 goto mst_fail;
4992                 }
4993
4994                 if (!intel_dp->is_mst) {
4995                         /*
4996                          * we'll check the link status via the normal hot plug path later -
4997                          * but for short hpds we should check it now
4998                          */
4999                         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
5000                         intel_dp_check_link_status(intel_dp);
5001                         drm_modeset_unlock(&dev->mode_config.connection_mutex);
5002                 }
5003         }
5004
5005         ret = IRQ_HANDLED;
5006
5007         goto put_power;
5008 mst_fail:
5009         /* if we were in MST mode, and device is not there get out of MST mode */
5010         if (intel_dp->is_mst) {
5011                 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
5012                 intel_dp->is_mst = false;
5013                 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
5014         }
5015 put_power:
5016         intel_display_power_put(dev_priv, power_domain);
5017
5018         return ret;
5019 }
5020
5021 /* Return which DP Port should be selected for Transcoder DP control */
5022 int
5023 intel_trans_dp_port_sel(struct drm_crtc *crtc)
5024 {
5025         struct drm_device *dev = crtc->dev;
5026         struct intel_encoder *intel_encoder;
5027         struct intel_dp *intel_dp;
5028
5029         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5030                 intel_dp = enc_to_intel_dp(&intel_encoder->base);
5031
5032                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
5033                     intel_encoder->type == INTEL_OUTPUT_EDP)
5034                         return intel_dp->output_reg;
5035         }
5036
5037         return -1;
5038 }
5039
5040 /* check the VBT to see whether the eDP is on DP-D port */
5041 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
5042 {
5043         struct drm_i915_private *dev_priv = dev->dev_private;
5044         union child_device_config *p_child;
5045         int i;
5046         static const short port_mapping[] = {
5047                 [PORT_B] = PORT_IDPB,
5048                 [PORT_C] = PORT_IDPC,
5049                 [PORT_D] = PORT_IDPD,
5050         };
5051
5052         if (port == PORT_A)
5053                 return true;
5054
5055         if (!dev_priv->vbt.child_dev_num)
5056                 return false;
5057
5058         for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
5059                 p_child = dev_priv->vbt.child_dev + i;
5060
5061                 if (p_child->common.dvo_port == port_mapping[port] &&
5062                     (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
5063                     (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
5064                         return true;
5065         }
5066         return false;
5067 }
5068
5069 void
5070 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5071 {
5072         struct intel_connector *intel_connector = to_intel_connector(connector);
5073
5074         intel_attach_force_audio_property(connector);
5075         intel_attach_broadcast_rgb_property(connector);
5076         intel_dp->color_range_auto = true;
5077
5078         if (is_edp(intel_dp)) {
5079                 drm_mode_create_scaling_mode_property(connector->dev);
5080                 drm_object_attach_property(
5081                         &connector->base,
5082                         connector->dev->mode_config.scaling_mode_property,
5083                         DRM_MODE_SCALE_ASPECT);
5084                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
5085         }
5086 }
5087
5088 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
5089 {
5090         intel_dp->last_power_cycle = jiffies;
5091         intel_dp->last_power_on = jiffies;
5092         intel_dp->last_backlight_off = jiffies;
5093 }
5094
5095 static void
5096 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
5097                                     struct intel_dp *intel_dp)
5098 {
5099         struct drm_i915_private *dev_priv = dev->dev_private;
5100         struct edp_power_seq cur, vbt, spec,
5101                 *final = &intel_dp->pps_delays;
5102         u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
5103         int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg = 0;
5104
5105         lockdep_assert_held(&dev_priv->pps_mutex);
5106
5107         /* already initialized? */
5108         if (final->t11_t12 != 0)
5109                 return;
5110
5111         if (IS_BROXTON(dev)) {
5112                 /*
5113                  * TODO: BXT has 2 sets of PPS registers.
5114                  * Correct Register for Broxton need to be identified
5115                  * using VBT. hardcoding for now
5116                  */
5117                 pp_ctrl_reg = BXT_PP_CONTROL(0);
5118                 pp_on_reg = BXT_PP_ON_DELAYS(0);
5119                 pp_off_reg = BXT_PP_OFF_DELAYS(0);
5120         } else if (HAS_PCH_SPLIT(dev)) {
5121                 pp_ctrl_reg = PCH_PP_CONTROL;
5122                 pp_on_reg = PCH_PP_ON_DELAYS;
5123                 pp_off_reg = PCH_PP_OFF_DELAYS;
5124                 pp_div_reg = PCH_PP_DIVISOR;
5125         } else {
5126                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
5127
5128                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
5129                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
5130                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
5131                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
5132         }
5133
5134         /* Workaround: Need to write PP_CONTROL with the unlock key as
5135          * the very first thing. */
5136         pp_ctl = ironlake_get_pp_control(intel_dp);
5137
5138         pp_on = I915_READ(pp_on_reg);
5139         pp_off = I915_READ(pp_off_reg);
5140         if (!IS_BROXTON(dev)) {
5141                 I915_WRITE(pp_ctrl_reg, pp_ctl);
5142                 pp_div = I915_READ(pp_div_reg);
5143         }
5144
5145         /* Pull timing values out of registers */
5146         cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
5147                 PANEL_POWER_UP_DELAY_SHIFT;
5148
5149         cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
5150                 PANEL_LIGHT_ON_DELAY_SHIFT;
5151
5152         cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
5153                 PANEL_LIGHT_OFF_DELAY_SHIFT;
5154
5155         cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
5156                 PANEL_POWER_DOWN_DELAY_SHIFT;
5157
5158         if (IS_BROXTON(dev)) {
5159                 u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
5160                         BXT_POWER_CYCLE_DELAY_SHIFT;
5161                 if (tmp > 0)
5162                         cur.t11_t12 = (tmp - 1) * 1000;
5163                 else
5164                         cur.t11_t12 = 0;
5165         } else {
5166                 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
5167                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
5168         }
5169
5170         DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5171                       cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
5172
5173         vbt = dev_priv->vbt.edp_pps;
5174
5175         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5176          * our hw here, which are all in 100usec. */
5177         spec.t1_t3 = 210 * 10;
5178         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5179         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5180         spec.t10 = 500 * 10;
5181         /* This one is special and actually in units of 100ms, but zero
5182          * based in the hw (so we need to add 100 ms). But the sw vbt
5183          * table multiplies it with 1000 to make it in units of 100usec,
5184          * too. */
5185         spec.t11_t12 = (510 + 100) * 10;
5186
5187         DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5188                       vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
5189
5190         /* Use the max of the register settings and vbt. If both are
5191          * unset, fall back to the spec limits. */
5192 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
5193                                        spec.field : \
5194                                        max(cur.field, vbt.field))
5195         assign_final(t1_t3);
5196         assign_final(t8);
5197         assign_final(t9);
5198         assign_final(t10);
5199         assign_final(t11_t12);
5200 #undef assign_final
5201
5202 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
5203         intel_dp->panel_power_up_delay = get_delay(t1_t3);
5204         intel_dp->backlight_on_delay = get_delay(t8);
5205         intel_dp->backlight_off_delay = get_delay(t9);
5206         intel_dp->panel_power_down_delay = get_delay(t10);
5207         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5208 #undef get_delay
5209
5210         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5211                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5212                       intel_dp->panel_power_cycle_delay);
5213
5214         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5215                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
5216 }
5217
5218 static void
5219 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
5220                                               struct intel_dp *intel_dp)
5221 {
5222         struct drm_i915_private *dev_priv = dev->dev_private;
5223         u32 pp_on, pp_off, pp_div, port_sel = 0;
5224         int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
5225         int pp_on_reg, pp_off_reg, pp_div_reg = 0, pp_ctrl_reg;
5226         enum port port = dp_to_dig_port(intel_dp)->port;
5227         const struct edp_power_seq *seq = &intel_dp->pps_delays;
5228
5229         lockdep_assert_held(&dev_priv->pps_mutex);
5230
5231         if (IS_BROXTON(dev)) {
5232                 /*
5233                  * TODO: BXT has 2 sets of PPS registers.
5234                  * Correct Register for Broxton need to be identified
5235                  * using VBT. hardcoding for now
5236                  */
5237                 pp_ctrl_reg = BXT_PP_CONTROL(0);
5238                 pp_on_reg = BXT_PP_ON_DELAYS(0);
5239                 pp_off_reg = BXT_PP_OFF_DELAYS(0);
5240
5241         } else if (HAS_PCH_SPLIT(dev)) {
5242                 pp_on_reg = PCH_PP_ON_DELAYS;
5243                 pp_off_reg = PCH_PP_OFF_DELAYS;
5244                 pp_div_reg = PCH_PP_DIVISOR;
5245         } else {
5246                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
5247
5248                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
5249                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
5250                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
5251         }
5252
5253         /*
5254          * And finally store the new values in the power sequencer. The
5255          * backlight delays are set to 1 because we do manual waits on them. For
5256          * T8, even BSpec recommends doing it. For T9, if we don't do this,
5257          * we'll end up waiting for the backlight off delay twice: once when we
5258          * do the manual sleep, and once when we disable the panel and wait for
5259          * the PP_STATUS bit to become zero.
5260          */
5261         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
5262                 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
5263         pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
5264                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
5265         /* Compute the divisor for the pp clock, simply match the Bspec
5266          * formula. */
5267         if (IS_BROXTON(dev)) {
5268                 pp_div = I915_READ(pp_ctrl_reg);
5269                 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5270                 pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
5271                                 << BXT_POWER_CYCLE_DELAY_SHIFT);
5272         } else {
5273                 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5274                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5275                                 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5276         }
5277
5278         /* Haswell doesn't have any port selection bits for the panel
5279          * power sequencer any more. */
5280         if (IS_VALLEYVIEW(dev)) {
5281                 port_sel = PANEL_PORT_SELECT_VLV(port);
5282         } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5283                 if (port == PORT_A)
5284                         port_sel = PANEL_PORT_SELECT_DPA;
5285                 else
5286                         port_sel = PANEL_PORT_SELECT_DPD;
5287         }
5288
5289         pp_on |= port_sel;
5290
5291         I915_WRITE(pp_on_reg, pp_on);
5292         I915_WRITE(pp_off_reg, pp_off);
5293         if (IS_BROXTON(dev))
5294                 I915_WRITE(pp_ctrl_reg, pp_div);
5295         else
5296                 I915_WRITE(pp_div_reg, pp_div);
5297
5298         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5299                       I915_READ(pp_on_reg),
5300                       I915_READ(pp_off_reg),
5301                       IS_BROXTON(dev) ?
5302                       (I915_READ(pp_ctrl_reg) & BXT_POWER_CYCLE_DELAY_MASK) :
5303                       I915_READ(pp_div_reg));
5304 }
5305
5306 /**
5307  * intel_dp_set_drrs_state - program registers for RR switch to take effect
5308  * @dev: DRM device
5309  * @refresh_rate: RR to be programmed
5310  *
5311  * This function gets called when refresh rate (RR) has to be changed from
5312  * one frequency to another. Switches can be between high and low RR
5313  * supported by the panel or to any other RR based on media playback (in
5314  * this case, RR value needs to be passed from user space).
5315  *
5316  * The caller of this function needs to take a lock on dev_priv->drrs.
5317  */
5318 static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
5319 {
5320         struct drm_i915_private *dev_priv = dev->dev_private;
5321         struct intel_encoder *encoder;
5322         struct intel_digital_port *dig_port = NULL;
5323         struct intel_dp *intel_dp = dev_priv->drrs.dp;
5324         struct intel_crtc_state *config = NULL;
5325         struct intel_crtc *intel_crtc = NULL;
5326         u32 reg, val;
5327         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
5328
5329         if (refresh_rate <= 0) {
5330                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5331                 return;
5332         }
5333
5334         if (intel_dp == NULL) {
5335                 DRM_DEBUG_KMS("DRRS not supported.\n");
5336                 return;
5337         }
5338
5339         /*
5340          * FIXME: This needs proper synchronization with psr state for some
5341          * platforms that cannot have PSR and DRRS enabled at the same time.
5342          */
5343
5344         dig_port = dp_to_dig_port(intel_dp);
5345         encoder = &dig_port->base;
5346         intel_crtc = to_intel_crtc(encoder->base.crtc);
5347
5348         if (!intel_crtc) {
5349                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5350                 return;
5351         }
5352
5353         config = intel_crtc->config;
5354
5355         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
5356                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5357                 return;
5358         }
5359
5360         if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5361                         refresh_rate)
5362                 index = DRRS_LOW_RR;
5363
5364         if (index == dev_priv->drrs.refresh_rate_type) {
5365                 DRM_DEBUG_KMS(
5366                         "DRRS requested for previously set RR...ignoring\n");
5367                 return;
5368         }
5369
5370         if (!intel_crtc->active) {
5371                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5372                 return;
5373         }
5374
5375         if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {
5376                 switch (index) {
5377                 case DRRS_HIGH_RR:
5378                         intel_dp_set_m_n(intel_crtc, M1_N1);
5379                         break;
5380                 case DRRS_LOW_RR:
5381                         intel_dp_set_m_n(intel_crtc, M2_N2);
5382                         break;
5383                 case DRRS_MAX_RR:
5384                 default:
5385                         DRM_ERROR("Unsupported refreshrate type\n");
5386                 }
5387         } else if (INTEL_INFO(dev)->gen > 6) {
5388                 reg = PIPECONF(intel_crtc->config->cpu_transcoder);
5389                 val = I915_READ(reg);
5390
5391                 if (index > DRRS_HIGH_RR) {
5392                         if (IS_VALLEYVIEW(dev))
5393                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5394                         else
5395                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
5396                 } else {
5397                         if (IS_VALLEYVIEW(dev))
5398                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5399                         else
5400                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5401                 }
5402                 I915_WRITE(reg, val);
5403         }
5404
5405         dev_priv->drrs.refresh_rate_type = index;
5406
5407         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5408 }
5409
5410 /**
5411  * intel_edp_drrs_enable - init drrs struct if supported
5412  * @intel_dp: DP struct
5413  *
5414  * Initializes frontbuffer_bits and drrs.dp
5415  */
5416 void intel_edp_drrs_enable(struct intel_dp *intel_dp)
5417 {
5418         struct drm_device *dev = intel_dp_to_dev(intel_dp);
5419         struct drm_i915_private *dev_priv = dev->dev_private;
5420         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5421         struct drm_crtc *crtc = dig_port->base.base.crtc;
5422         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5423
5424         if (!intel_crtc->config->has_drrs) {
5425                 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5426                 return;
5427         }
5428
5429         mutex_lock(&dev_priv->drrs.mutex);
5430         if (WARN_ON(dev_priv->drrs.dp)) {
5431                 DRM_ERROR("DRRS already enabled\n");
5432                 goto unlock;
5433         }
5434
5435         dev_priv->drrs.busy_frontbuffer_bits = 0;
5436
5437         dev_priv->drrs.dp = intel_dp;
5438
5439 unlock:
5440         mutex_unlock(&dev_priv->drrs.mutex);
5441 }
5442
5443 /**
5444  * intel_edp_drrs_disable - Disable DRRS
5445  * @intel_dp: DP struct
5446  *
5447  */
5448 void intel_edp_drrs_disable(struct intel_dp *intel_dp)
5449 {
5450         struct drm_device *dev = intel_dp_to_dev(intel_dp);
5451         struct drm_i915_private *dev_priv = dev->dev_private;
5452         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5453         struct drm_crtc *crtc = dig_port->base.base.crtc;
5454         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5455
5456         if (!intel_crtc->config->has_drrs)
5457                 return;
5458
5459         mutex_lock(&dev_priv->drrs.mutex);
5460         if (!dev_priv->drrs.dp) {
5461                 mutex_unlock(&dev_priv->drrs.mutex);
5462                 return;
5463         }
5464
5465         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5466                 intel_dp_set_drrs_state(dev_priv->dev,
5467                         intel_dp->attached_connector->panel.
5468                         fixed_mode->vrefresh);
5469
5470         dev_priv->drrs.dp = NULL;
5471         mutex_unlock(&dev_priv->drrs.mutex);
5472
5473         cancel_delayed_work_sync(&dev_priv->drrs.work);
5474 }
5475
5476 static void intel_edp_drrs_downclock_work(struct work_struct *work)
5477 {
5478         struct drm_i915_private *dev_priv =
5479                 container_of(work, typeof(*dev_priv), drrs.work.work);
5480         struct intel_dp *intel_dp;
5481
5482         mutex_lock(&dev_priv->drrs.mutex);
5483
5484         intel_dp = dev_priv->drrs.dp;
5485
5486         if (!intel_dp)
5487                 goto unlock;
5488
5489         /*
5490          * The delayed work can race with an invalidate hence we need to
5491          * recheck.
5492          */
5493
5494         if (dev_priv->drrs.busy_frontbuffer_bits)
5495                 goto unlock;
5496
5497         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR)
5498                 intel_dp_set_drrs_state(dev_priv->dev,
5499                         intel_dp->attached_connector->panel.
5500                         downclock_mode->vrefresh);
5501
5502 unlock:
5503         mutex_unlock(&dev_priv->drrs.mutex);
5504 }
5505
5506 /**
5507  * intel_edp_drrs_invalidate - Disable Idleness DRRS
5508  * @dev: DRM device
5509  * @frontbuffer_bits: frontbuffer plane tracking bits
5510  *
5511  * This function gets called everytime rendering on the given planes start.
5512  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5513  *
5514  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5515  */
5516 void intel_edp_drrs_invalidate(struct drm_device *dev,
5517                 unsigned frontbuffer_bits)
5518 {
5519         struct drm_i915_private *dev_priv = dev->dev_private;
5520         struct drm_crtc *crtc;
5521         enum pipe pipe;
5522
5523         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5524                 return;
5525
5526         cancel_delayed_work(&dev_priv->drrs.work);
5527
5528         mutex_lock(&dev_priv->drrs.mutex);
5529         if (!dev_priv->drrs.dp) {
5530                 mutex_unlock(&dev_priv->drrs.mutex);
5531                 return;
5532         }
5533
5534         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5535         pipe = to_intel_crtc(crtc)->pipe;
5536
5537         /* invalidate means busy screen hence upclock */
5538         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) {
5539                 intel_dp_set_drrs_state(dev_priv->dev,
5540                                 dev_priv->drrs.dp->attached_connector->panel.
5541                                 fixed_mode->vrefresh);
5542         }
5543
5544         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5545
5546         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5547         mutex_unlock(&dev_priv->drrs.mutex);
5548 }
5549
5550 /**
5551  * intel_edp_drrs_flush - Restart Idleness DRRS
5552  * @dev: DRM device
5553  * @frontbuffer_bits: frontbuffer plane tracking bits
5554  *
5555  * This function gets called every time rendering on the given planes has
5556  * completed or flip on a crtc is completed. So DRRS should be upclocked
5557  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5558  * if no other planes are dirty.
5559  *
5560  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5561  */
5562 void intel_edp_drrs_flush(struct drm_device *dev,
5563                 unsigned frontbuffer_bits)
5564 {
5565         struct drm_i915_private *dev_priv = dev->dev_private;
5566         struct drm_crtc *crtc;
5567         enum pipe pipe;
5568
5569         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5570                 return;
5571
5572         cancel_delayed_work(&dev_priv->drrs.work);
5573
5574         mutex_lock(&dev_priv->drrs.mutex);
5575         if (!dev_priv->drrs.dp) {
5576                 mutex_unlock(&dev_priv->drrs.mutex);
5577                 return;
5578         }
5579
5580         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5581         pipe = to_intel_crtc(crtc)->pipe;
5582         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5583
5584         /* flush means busy screen hence upclock */
5585         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5586                 intel_dp_set_drrs_state(dev_priv->dev,
5587                                 dev_priv->drrs.dp->attached_connector->panel.
5588                                 fixed_mode->vrefresh);
5589
5590         /*
5591          * flush also means no more activity hence schedule downclock, if all
5592          * other fbs are quiescent too
5593          */
5594         if (!dev_priv->drrs.busy_frontbuffer_bits)
5595                 schedule_delayed_work(&dev_priv->drrs.work,
5596                                 msecs_to_jiffies(1000));
5597         mutex_unlock(&dev_priv->drrs.mutex);
5598 }
5599
5600 /**
5601  * DOC: Display Refresh Rate Switching (DRRS)
5602  *
5603  * Display Refresh Rate Switching (DRRS) is a power conservation feature
5604  * which enables swtching between low and high refresh rates,
5605  * dynamically, based on the usage scenario. This feature is applicable
5606  * for internal panels.
5607  *
5608  * Indication that the panel supports DRRS is given by the panel EDID, which
5609  * would list multiple refresh rates for one resolution.
5610  *
5611  * DRRS is of 2 types - static and seamless.
5612  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5613  * (may appear as a blink on screen) and is used in dock-undock scenario.
5614  * Seamless DRRS involves changing RR without any visual effect to the user
5615  * and can be used during normal system usage. This is done by programming
5616  * certain registers.
5617  *
5618  * Support for static/seamless DRRS may be indicated in the VBT based on
5619  * inputs from the panel spec.
5620  *
5621  * DRRS saves power by switching to low RR based on usage scenarios.
5622  *
5623  * eDP DRRS:-
5624  *        The implementation is based on frontbuffer tracking implementation.
5625  * When there is a disturbance on the screen triggered by user activity or a
5626  * periodic system activity, DRRS is disabled (RR is changed to high RR).
5627  * When there is no movement on screen, after a timeout of 1 second, a switch
5628  * to low RR is made.
5629  *        For integration with frontbuffer tracking code,
5630  * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called.
5631  *
5632  * DRRS can be further extended to support other internal panels and also
5633  * the scenario of video playback wherein RR is set based on the rate
5634  * requested by userspace.
5635  */
5636
5637 /**
5638  * intel_dp_drrs_init - Init basic DRRS work and mutex.
5639  * @intel_connector: eDP connector
5640  * @fixed_mode: preferred mode of panel
5641  *
5642  * This function is  called only once at driver load to initialize basic
5643  * DRRS stuff.
5644  *
5645  * Returns:
5646  * Downclock mode if panel supports it, else return NULL.
5647  * DRRS support is determined by the presence of downclock mode (apart
5648  * from VBT setting).
5649  */
5650 static struct drm_display_mode *
5651 intel_dp_drrs_init(struct intel_connector *intel_connector,
5652                 struct drm_display_mode *fixed_mode)
5653 {
5654         struct drm_connector *connector = &intel_connector->base;
5655         struct drm_device *dev = connector->dev;
5656         struct drm_i915_private *dev_priv = dev->dev_private;
5657         struct drm_display_mode *downclock_mode = NULL;
5658
5659         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5660         mutex_init(&dev_priv->drrs.mutex);
5661
5662         if (INTEL_INFO(dev)->gen <= 6) {
5663                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5664                 return NULL;
5665         }
5666
5667         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5668                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5669                 return NULL;
5670         }
5671
5672         downclock_mode = intel_find_panel_downclock
5673                                         (dev, fixed_mode, connector);
5674
5675         if (!downclock_mode) {
5676                 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5677                 return NULL;
5678         }
5679
5680         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
5681
5682         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
5683         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5684         return downclock_mode;
5685 }
5686
5687 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5688                                      struct intel_connector *intel_connector)
5689 {
5690         struct drm_connector *connector = &intel_connector->base;
5691         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5692         struct intel_encoder *intel_encoder = &intel_dig_port->base;
5693         struct drm_device *dev = intel_encoder->base.dev;
5694         struct drm_i915_private *dev_priv = dev->dev_private;
5695         struct drm_display_mode *fixed_mode = NULL;
5696         struct drm_display_mode *downclock_mode = NULL;
5697         bool has_dpcd;
5698         struct drm_display_mode *scan;
5699         struct edid *edid;
5700         enum pipe pipe = INVALID_PIPE;
5701
5702         if (!is_edp(intel_dp))
5703                 return true;
5704
5705         pps_lock(intel_dp);
5706         intel_edp_panel_vdd_sanitize(intel_dp);
5707         pps_unlock(intel_dp);
5708
5709         /* Cache DPCD and EDID for edp. */
5710         has_dpcd = intel_dp_get_dpcd(intel_dp);
5711
5712         if (has_dpcd) {
5713                 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5714                         dev_priv->no_aux_handshake =
5715                                 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5716                                 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5717         } else {
5718                 /* if this fails, presume the device is a ghost */
5719                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5720                 return false;
5721         }
5722
5723         /* We now know it's not a ghost, init power sequence regs. */
5724         pps_lock(intel_dp);
5725         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
5726         pps_unlock(intel_dp);
5727
5728         mutex_lock(&dev->mode_config.mutex);
5729         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5730         if (edid) {
5731                 if (drm_add_edid_modes(connector, edid)) {
5732                         drm_mode_connector_update_edid_property(connector,
5733                                                                 edid);
5734                         drm_edid_to_eld(connector, edid);
5735                 } else {
5736                         kfree(edid);
5737                         edid = ERR_PTR(-EINVAL);
5738                 }
5739         } else {
5740                 edid = ERR_PTR(-ENOENT);
5741         }
5742         intel_connector->edid = edid;
5743
5744         /* prefer fixed mode from EDID if available */
5745         list_for_each_entry(scan, &connector->probed_modes, head) {
5746                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5747                         fixed_mode = drm_mode_duplicate(dev, scan);
5748                         downclock_mode = intel_dp_drrs_init(
5749                                                 intel_connector, fixed_mode);
5750                         break;
5751                 }
5752         }
5753
5754         /* fallback to VBT if available for eDP */
5755         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5756                 fixed_mode = drm_mode_duplicate(dev,
5757                                         dev_priv->vbt.lfp_lvds_vbt_mode);
5758                 if (fixed_mode)
5759                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5760         }
5761         mutex_unlock(&dev->mode_config.mutex);
5762
5763         if (IS_VALLEYVIEW(dev)) {
5764                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5765                 register_reboot_notifier(&intel_dp->edp_notifier);
5766
5767                 /*
5768                  * Figure out the current pipe for the initial backlight setup.
5769                  * If the current pipe isn't valid, try the PPS pipe, and if that
5770                  * fails just assume pipe A.
5771                  */
5772                 if (IS_CHERRYVIEW(dev))
5773                         pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5774                 else
5775                         pipe = PORT_TO_PIPE(intel_dp->DP);
5776
5777                 if (pipe != PIPE_A && pipe != PIPE_B)
5778                         pipe = intel_dp->pps_pipe;
5779
5780                 if (pipe != PIPE_A && pipe != PIPE_B)
5781                         pipe = PIPE_A;
5782
5783                 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5784                               pipe_name(pipe));
5785         }
5786
5787         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5788         intel_connector->panel.backlight_power = intel_edp_backlight_power;
5789         intel_panel_setup_backlight(connector, pipe);
5790
5791         return true;
5792 }
5793
5794 bool
5795 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5796                         struct intel_connector *intel_connector)
5797 {
5798         struct drm_connector *connector = &intel_connector->base;
5799         struct intel_dp *intel_dp = &intel_dig_port->dp;
5800         struct intel_encoder *intel_encoder = &intel_dig_port->base;
5801         struct drm_device *dev = intel_encoder->base.dev;
5802         struct drm_i915_private *dev_priv = dev->dev_private;
5803         enum port port = intel_dig_port->port;
5804         int type;
5805
5806         intel_dp->pps_pipe = INVALID_PIPE;
5807
5808         /* intel_dp vfuncs */
5809         if (INTEL_INFO(dev)->gen >= 9)
5810                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5811         else if (IS_VALLEYVIEW(dev))
5812                 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
5813         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5814                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5815         else if (HAS_PCH_SPLIT(dev))
5816                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5817         else
5818                 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
5819
5820         if (INTEL_INFO(dev)->gen >= 9)
5821                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5822         else
5823                 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
5824
5825         /* Preserve the current hw state. */
5826         intel_dp->DP = I915_READ(intel_dp->output_reg);
5827         intel_dp->attached_connector = intel_connector;
5828
5829         if (intel_dp_is_edp(dev, port))
5830                 type = DRM_MODE_CONNECTOR_eDP;
5831         else
5832                 type = DRM_MODE_CONNECTOR_DisplayPort;
5833
5834         /*
5835          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5836          * for DP the encoder type can be set by the caller to
5837          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5838          */
5839         if (type == DRM_MODE_CONNECTOR_eDP)
5840                 intel_encoder->type = INTEL_OUTPUT_EDP;
5841
5842         /* eDP only on port B and/or C on vlv/chv */
5843         if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) &&
5844                     port != PORT_B && port != PORT_C))
5845                 return false;
5846
5847         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5848                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5849                         port_name(port));
5850
5851         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5852         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5853
5854         connector->interlace_allowed = true;
5855         connector->doublescan_allowed = 0;
5856
5857         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
5858                           edp_panel_vdd_work);
5859
5860         intel_connector_attach_encoder(intel_connector, intel_encoder);
5861         drm_connector_register(connector);
5862
5863         if (HAS_DDI(dev))
5864                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5865         else
5866                 intel_connector->get_hw_state = intel_connector_get_hw_state;
5867         intel_connector->unregister = intel_dp_connector_unregister;
5868
5869         /* Set up the hotplug pin. */
5870         switch (port) {
5871         case PORT_A:
5872                 intel_encoder->hpd_pin = HPD_PORT_A;
5873                 break;
5874         case PORT_B:
5875                 intel_encoder->hpd_pin = HPD_PORT_B;
5876                 break;
5877         case PORT_C:
5878                 intel_encoder->hpd_pin = HPD_PORT_C;
5879                 break;
5880         case PORT_D:
5881                 intel_encoder->hpd_pin = HPD_PORT_D;
5882                 break;
5883         default:
5884                 BUG();
5885         }
5886
5887         if (is_edp(intel_dp)) {
5888                 pps_lock(intel_dp);
5889                 intel_dp_init_panel_power_timestamps(intel_dp);
5890                 if (IS_VALLEYVIEW(dev))
5891                         vlv_initial_power_sequencer_setup(intel_dp);
5892                 else
5893                         intel_dp_init_panel_power_sequencer(dev, intel_dp);
5894                 pps_unlock(intel_dp);
5895         }
5896
5897         intel_dp_aux_init(intel_dp, intel_connector);
5898
5899         /* init MST on ports that can support it */
5900         if (HAS_DP_MST(dev) &&
5901             (port == PORT_B || port == PORT_C || port == PORT_D))
5902                 intel_dp_mst_encoder_init(intel_dig_port,
5903                                           intel_connector->base.base.id);
5904
5905         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
5906                 drm_dp_aux_unregister(&intel_dp->aux);
5907                 if (is_edp(intel_dp)) {
5908                         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5909                         /*
5910                          * vdd might still be enabled do to the delayed vdd off.
5911                          * Make sure vdd is actually turned off here.
5912                          */
5913                         pps_lock(intel_dp);
5914                         edp_panel_vdd_off_sync(intel_dp);
5915                         pps_unlock(intel_dp);
5916                 }
5917                 drm_connector_unregister(connector);
5918                 drm_connector_cleanup(connector);
5919                 return false;
5920         }
5921
5922         intel_dp_add_properties(intel_dp, connector);
5923
5924         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5925          * 0xd.  Failure to do so will result in spurious interrupts being
5926          * generated on the port when a cable is not attached.
5927          */
5928         if (IS_G4X(dev) && !IS_GM45(dev)) {
5929                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5930                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5931         }
5932
5933         i915_debugfs_connector_add(connector);
5934
5935         return true;
5936 }
5937
5938 void
5939 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
5940 {
5941         struct drm_i915_private *dev_priv = dev->dev_private;
5942         struct intel_digital_port *intel_dig_port;
5943         struct intel_encoder *intel_encoder;
5944         struct drm_encoder *encoder;
5945         struct intel_connector *intel_connector;
5946
5947         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
5948         if (!intel_dig_port)
5949                 return;
5950
5951         intel_connector = intel_connector_alloc();
5952         if (!intel_connector) {
5953                 kfree(intel_dig_port);
5954                 return;
5955         }
5956
5957         intel_encoder = &intel_dig_port->base;
5958         encoder = &intel_encoder->base;
5959
5960         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5961                          DRM_MODE_ENCODER_TMDS);
5962
5963         intel_encoder->compute_config = intel_dp_compute_config;
5964         intel_encoder->disable = intel_disable_dp;
5965         intel_encoder->get_hw_state = intel_dp_get_hw_state;
5966         intel_encoder->get_config = intel_dp_get_config;
5967         intel_encoder->suspend = intel_dp_encoder_suspend;
5968         if (IS_CHERRYVIEW(dev)) {
5969                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
5970                 intel_encoder->pre_enable = chv_pre_enable_dp;
5971                 intel_encoder->enable = vlv_enable_dp;
5972                 intel_encoder->post_disable = chv_post_disable_dp;
5973         } else if (IS_VALLEYVIEW(dev)) {
5974                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
5975                 intel_encoder->pre_enable = vlv_pre_enable_dp;
5976                 intel_encoder->enable = vlv_enable_dp;
5977                 intel_encoder->post_disable = vlv_post_disable_dp;
5978         } else {
5979                 intel_encoder->pre_enable = g4x_pre_enable_dp;
5980                 intel_encoder->enable = g4x_enable_dp;
5981                 if (INTEL_INFO(dev)->gen >= 5)
5982                         intel_encoder->post_disable = ilk_post_disable_dp;
5983         }
5984
5985         intel_dig_port->port = port;
5986         intel_dig_port->dp.output_reg = output_reg;
5987
5988         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
5989         if (IS_CHERRYVIEW(dev)) {
5990                 if (port == PORT_D)
5991                         intel_encoder->crtc_mask = 1 << 2;
5992                 else
5993                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5994         } else {
5995                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5996         }
5997         intel_encoder->cloneable = 0;
5998
5999         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
6000         dev_priv->hotplug.irq_port[port] = intel_dig_port;
6001
6002         if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
6003                 drm_encoder_cleanup(encoder);
6004                 kfree(intel_dig_port);
6005                 kfree(intel_connector);
6006         }
6007 }
6008
6009 void intel_dp_mst_suspend(struct drm_device *dev)
6010 {
6011         struct drm_i915_private *dev_priv = dev->dev_private;
6012         int i;
6013
6014         /* disable MST */
6015         for (i = 0; i < I915_MAX_PORTS; i++) {
6016                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6017                 if (!intel_dig_port)
6018                         continue;
6019
6020                 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
6021                         if (!intel_dig_port->dp.can_mst)
6022                                 continue;
6023                         if (intel_dig_port->dp.is_mst)
6024                                 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
6025                 }
6026         }
6027 }
6028
6029 void intel_dp_mst_resume(struct drm_device *dev)
6030 {
6031         struct drm_i915_private *dev_priv = dev->dev_private;
6032         int i;
6033
6034         for (i = 0; i < I915_MAX_PORTS; i++) {
6035                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6036                 if (!intel_dig_port)
6037                         continue;
6038                 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
6039                         int ret;
6040
6041                         if (!intel_dig_port->dp.can_mst)
6042                                 continue;
6043
6044                         ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
6045                         if (ret != 0) {
6046                                 intel_dp_check_mst_status(&intel_dig_port->dp);
6047                         }
6048                 }
6049         }
6050 }