2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
39 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
48 static bool is_edp(struct intel_dp *intel_dp)
50 return intel_dp->base.type == INTEL_OUTPUT_EDP;
54 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
55 * @intel_dp: DP struct
57 * Returns true if the given DP struct corresponds to a PCH DP port attached
58 * to an eDP panel, false otherwise. Helpful for determining whether we
59 * may need FDI resources for a given DP output or not.
61 static bool is_pch_edp(struct intel_dp *intel_dp)
63 return intel_dp->is_pch_edp;
67 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
68 * @intel_dp: DP struct
70 * Returns true if the given DP struct corresponds to a CPU eDP port.
72 static bool is_cpu_edp(struct intel_dp *intel_dp)
74 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
77 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
79 return container_of(intel_attached_encoder(connector),
80 struct intel_dp, base);
84 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
85 * @encoder: DRM encoder
87 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
90 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
92 struct intel_dp *intel_dp;
97 intel_dp = enc_to_intel_dp(encoder);
99 return is_pch_edp(intel_dp);
102 static void intel_dp_link_down(struct intel_dp *intel_dp);
105 intel_edp_link_config(struct intel_encoder *intel_encoder,
106 int *lane_num, int *link_bw)
108 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
110 *lane_num = intel_dp->lane_count;
111 if (intel_dp->link_bw == DP_LINK_BW_1_62)
113 else if (intel_dp->link_bw == DP_LINK_BW_2_7)
118 intel_edp_target_clock(struct intel_encoder *intel_encoder,
119 struct drm_display_mode *mode)
121 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
122 struct intel_connector *intel_connector = intel_dp->attached_connector;
124 if (intel_connector->panel.fixed_mode)
125 return intel_connector->panel.fixed_mode->clock;
131 intel_dp_max_lane_count(struct intel_dp *intel_dp)
133 int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
134 switch (max_lane_count) {
135 case 1: case 2: case 4:
140 return max_lane_count;
144 intel_dp_max_link_bw(struct intel_dp *intel_dp)
146 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
148 switch (max_link_bw) {
149 case DP_LINK_BW_1_62:
153 max_link_bw = DP_LINK_BW_1_62;
160 intel_dp_link_clock(uint8_t link_bw)
162 if (link_bw == DP_LINK_BW_2_7)
169 * The units on the numbers in the next two are... bizarre. Examples will
170 * make it clearer; this one parallels an example in the eDP spec.
172 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
174 * 270000 * 1 * 8 / 10 == 216000
176 * The actual data capacity of that configuration is 2.16Gbit/s, so the
177 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
178 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
179 * 119000. At 18bpp that's 2142000 kilobits per second.
181 * Thus the strange-looking division by 10 in intel_dp_link_required, to
182 * get the result in decakilobits instead of kilobits.
186 intel_dp_link_required(int pixel_clock, int bpp)
188 return (pixel_clock * bpp + 9) / 10;
192 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
194 return (max_link_clock * max_lanes * 8) / 10;
198 intel_dp_adjust_dithering(struct intel_dp *intel_dp,
199 struct drm_display_mode *mode,
202 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
203 int max_lanes = intel_dp_max_lane_count(intel_dp);
204 int max_rate, mode_rate;
206 mode_rate = intel_dp_link_required(mode->clock, 24);
207 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
209 if (mode_rate > max_rate) {
210 mode_rate = intel_dp_link_required(mode->clock, 18);
211 if (mode_rate > max_rate)
216 |= INTEL_MODE_DP_FORCE_6BPC;
225 intel_dp_mode_valid(struct drm_connector *connector,
226 struct drm_display_mode *mode)
228 struct intel_dp *intel_dp = intel_attached_dp(connector);
229 struct intel_connector *intel_connector = to_intel_connector(connector);
230 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
232 if (is_edp(intel_dp) && fixed_mode) {
233 if (mode->hdisplay > fixed_mode->hdisplay)
236 if (mode->vdisplay > fixed_mode->vdisplay)
240 if (!intel_dp_adjust_dithering(intel_dp, mode, false))
241 return MODE_CLOCK_HIGH;
243 if (mode->clock < 10000)
244 return MODE_CLOCK_LOW;
246 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
247 return MODE_H_ILLEGAL;
253 pack_aux(uint8_t *src, int src_bytes)
260 for (i = 0; i < src_bytes; i++)
261 v |= ((uint32_t) src[i]) << ((3-i) * 8);
266 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
271 for (i = 0; i < dst_bytes; i++)
272 dst[i] = src >> ((3-i) * 8);
275 /* hrawclock is 1/4 the FSB frequency */
277 intel_hrawclk(struct drm_device *dev)
279 struct drm_i915_private *dev_priv = dev->dev_private;
282 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
283 if (IS_VALLEYVIEW(dev))
286 clkcfg = I915_READ(CLKCFG);
287 switch (clkcfg & CLKCFG_FSB_MASK) {
296 case CLKCFG_FSB_1067:
298 case CLKCFG_FSB_1333:
300 /* these two are just a guess; one of them might be right */
301 case CLKCFG_FSB_1600:
302 case CLKCFG_FSB_1600_ALT:
309 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
311 struct drm_device *dev = intel_dp->base.base.dev;
312 struct drm_i915_private *dev_priv = dev->dev_private;
314 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
317 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
319 struct drm_device *dev = intel_dp->base.base.dev;
320 struct drm_i915_private *dev_priv = dev->dev_private;
322 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
326 intel_dp_check_edp(struct intel_dp *intel_dp)
328 struct drm_device *dev = intel_dp->base.base.dev;
329 struct drm_i915_private *dev_priv = dev->dev_private;
331 if (!is_edp(intel_dp))
333 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
334 WARN(1, "eDP powered off while attempting aux channel communication.\n");
335 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
336 I915_READ(PCH_PP_STATUS),
337 I915_READ(PCH_PP_CONTROL));
342 intel_dp_aux_ch(struct intel_dp *intel_dp,
343 uint8_t *send, int send_bytes,
344 uint8_t *recv, int recv_size)
346 uint32_t output_reg = intel_dp->output_reg;
347 struct drm_device *dev = intel_dp->base.base.dev;
348 struct drm_i915_private *dev_priv = dev->dev_private;
349 uint32_t ch_ctl = output_reg + 0x10;
350 uint32_t ch_data = ch_ctl + 4;
354 uint32_t aux_clock_divider;
357 if (IS_HASWELL(dev)) {
358 switch (intel_dp->port) {
360 ch_ctl = DPA_AUX_CH_CTL;
361 ch_data = DPA_AUX_CH_DATA1;
364 ch_ctl = PCH_DPB_AUX_CH_CTL;
365 ch_data = PCH_DPB_AUX_CH_DATA1;
368 ch_ctl = PCH_DPC_AUX_CH_CTL;
369 ch_data = PCH_DPC_AUX_CH_DATA1;
372 ch_ctl = PCH_DPD_AUX_CH_CTL;
373 ch_data = PCH_DPD_AUX_CH_DATA1;
380 intel_dp_check_edp(intel_dp);
381 /* The clock divider is based off the hrawclk,
382 * and would like to run at 2MHz. So, take the
383 * hrawclk value and divide by 2 and use that
385 * Note that PCH attached eDP panels should use a 125MHz input
388 if (is_cpu_edp(intel_dp)) {
389 if (IS_VALLEYVIEW(dev))
390 aux_clock_divider = 100;
391 else if (IS_GEN6(dev) || IS_GEN7(dev))
392 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
394 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
395 } else if (HAS_PCH_SPLIT(dev))
396 aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */
398 aux_clock_divider = intel_hrawclk(dev) / 2;
405 /* Try to wait for any previous AUX channel activity */
406 for (try = 0; try < 3; try++) {
407 status = I915_READ(ch_ctl);
408 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
414 WARN(1, "dp_aux_ch not started status 0x%08x\n",
419 /* Must try at least 3 times according to DP spec */
420 for (try = 0; try < 5; try++) {
421 /* Load the send data into the aux channel data registers */
422 for (i = 0; i < send_bytes; i += 4)
423 I915_WRITE(ch_data + i,
424 pack_aux(send + i, send_bytes - i));
426 /* Send the command and wait for it to complete */
428 DP_AUX_CH_CTL_SEND_BUSY |
429 DP_AUX_CH_CTL_TIME_OUT_400us |
430 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
431 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
432 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
434 DP_AUX_CH_CTL_TIME_OUT_ERROR |
435 DP_AUX_CH_CTL_RECEIVE_ERROR);
437 status = I915_READ(ch_ctl);
438 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
443 /* Clear done status and any errors */
447 DP_AUX_CH_CTL_TIME_OUT_ERROR |
448 DP_AUX_CH_CTL_RECEIVE_ERROR);
450 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
451 DP_AUX_CH_CTL_RECEIVE_ERROR))
453 if (status & DP_AUX_CH_CTL_DONE)
457 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
458 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
462 /* Check for timeout or receive error.
463 * Timeouts occur when the sink is not connected
465 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
466 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
470 /* Timeouts occur when the device isn't connected, so they're
471 * "normal" -- don't fill the kernel log with these */
472 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
473 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
477 /* Unload any bytes sent back from the other side */
478 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
479 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
480 if (recv_bytes > recv_size)
481 recv_bytes = recv_size;
483 for (i = 0; i < recv_bytes; i += 4)
484 unpack_aux(I915_READ(ch_data + i),
485 recv + i, recv_bytes - i);
490 /* Write data to the aux channel in native mode */
492 intel_dp_aux_native_write(struct intel_dp *intel_dp,
493 uint16_t address, uint8_t *send, int send_bytes)
500 intel_dp_check_edp(intel_dp);
503 msg[0] = AUX_NATIVE_WRITE << 4;
504 msg[1] = address >> 8;
505 msg[2] = address & 0xff;
506 msg[3] = send_bytes - 1;
507 memcpy(&msg[4], send, send_bytes);
508 msg_bytes = send_bytes + 4;
510 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
513 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
515 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
523 /* Write a single byte to the aux channel in native mode */
525 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
526 uint16_t address, uint8_t byte)
528 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
531 /* read bytes from a native aux channel */
533 intel_dp_aux_native_read(struct intel_dp *intel_dp,
534 uint16_t address, uint8_t *recv, int recv_bytes)
543 intel_dp_check_edp(intel_dp);
544 msg[0] = AUX_NATIVE_READ << 4;
545 msg[1] = address >> 8;
546 msg[2] = address & 0xff;
547 msg[3] = recv_bytes - 1;
550 reply_bytes = recv_bytes + 1;
553 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
560 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
561 memcpy(recv, reply + 1, ret - 1);
564 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
572 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
573 uint8_t write_byte, uint8_t *read_byte)
575 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
576 struct intel_dp *intel_dp = container_of(adapter,
579 uint16_t address = algo_data->address;
587 intel_dp_check_edp(intel_dp);
588 /* Set up the command byte */
589 if (mode & MODE_I2C_READ)
590 msg[0] = AUX_I2C_READ << 4;
592 msg[0] = AUX_I2C_WRITE << 4;
594 if (!(mode & MODE_I2C_STOP))
595 msg[0] |= AUX_I2C_MOT << 4;
597 msg[1] = address >> 8;
618 for (retry = 0; retry < 5; retry++) {
619 ret = intel_dp_aux_ch(intel_dp,
623 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
627 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
628 case AUX_NATIVE_REPLY_ACK:
629 /* I2C-over-AUX Reply field is only valid
630 * when paired with AUX ACK.
633 case AUX_NATIVE_REPLY_NACK:
634 DRM_DEBUG_KMS("aux_ch native nack\n");
636 case AUX_NATIVE_REPLY_DEFER:
640 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
645 switch (reply[0] & AUX_I2C_REPLY_MASK) {
646 case AUX_I2C_REPLY_ACK:
647 if (mode == MODE_I2C_READ) {
648 *read_byte = reply[1];
650 return reply_bytes - 1;
651 case AUX_I2C_REPLY_NACK:
652 DRM_DEBUG_KMS("aux_i2c nack\n");
654 case AUX_I2C_REPLY_DEFER:
655 DRM_DEBUG_KMS("aux_i2c defer\n");
659 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
664 DRM_ERROR("too many retries, giving up\n");
668 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
669 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
672 intel_dp_i2c_init(struct intel_dp *intel_dp,
673 struct intel_connector *intel_connector, const char *name)
677 DRM_DEBUG_KMS("i2c_init %s\n", name);
678 intel_dp->algo.running = false;
679 intel_dp->algo.address = 0;
680 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
682 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
683 intel_dp->adapter.owner = THIS_MODULE;
684 intel_dp->adapter.class = I2C_CLASS_DDC;
685 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
686 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
687 intel_dp->adapter.algo_data = &intel_dp->algo;
688 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
690 ironlake_edp_panel_vdd_on(intel_dp);
691 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
692 ironlake_edp_panel_vdd_off(intel_dp, false);
697 intel_dp_mode_fixup(struct drm_encoder *encoder,
698 const struct drm_display_mode *mode,
699 struct drm_display_mode *adjusted_mode)
701 struct drm_device *dev = encoder->dev;
702 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
703 struct intel_connector *intel_connector = intel_dp->attached_connector;
704 int lane_count, clock;
705 int max_lane_count = intel_dp_max_lane_count(intel_dp);
706 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
708 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
710 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
711 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
713 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
714 mode, adjusted_mode);
717 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
720 DRM_DEBUG_KMS("DP link computation with max lane count %i "
721 "max bw %02x pixel clock %iKHz\n",
722 max_lane_count, bws[max_clock], adjusted_mode->clock);
724 if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true))
727 bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
728 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
730 for (clock = 0; clock <= max_clock; clock++) {
731 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
732 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
734 if (mode_rate <= link_avail) {
735 intel_dp->link_bw = bws[clock];
736 intel_dp->lane_count = lane_count;
737 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
738 DRM_DEBUG_KMS("DP link bw %02x lane "
739 "count %d clock %d bpp %d\n",
740 intel_dp->link_bw, intel_dp->lane_count,
741 adjusted_mode->clock, bpp);
742 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
743 mode_rate, link_avail);
752 struct intel_dp_m_n {
761 intel_reduce_ratio(uint32_t *num, uint32_t *den)
763 while (*num > 0xffffff || *den > 0xffffff) {
770 intel_dp_compute_m_n(int bpp,
774 struct intel_dp_m_n *m_n)
777 m_n->gmch_m = (pixel_clock * bpp) >> 3;
778 m_n->gmch_n = link_clock * nlanes;
779 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
780 m_n->link_m = pixel_clock;
781 m_n->link_n = link_clock;
782 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
786 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
787 struct drm_display_mode *adjusted_mode)
789 struct drm_device *dev = crtc->dev;
790 struct intel_encoder *encoder;
791 struct drm_i915_private *dev_priv = dev->dev_private;
792 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
794 struct intel_dp_m_n m_n;
795 int pipe = intel_crtc->pipe;
798 * Find the lane count in the intel_encoder private
800 for_each_encoder_on_crtc(dev, crtc, encoder) {
801 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
803 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
804 intel_dp->base.type == INTEL_OUTPUT_EDP)
806 lane_count = intel_dp->lane_count;
812 * Compute the GMCH and Link ratios. The '3' here is
813 * the number of bytes_per_pixel post-LUT, which we always
814 * set up for 8-bits of R/G/B, or 3 bytes total.
816 intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
817 mode->clock, adjusted_mode->clock, &m_n);
819 if (IS_HASWELL(dev)) {
820 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
821 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
822 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
823 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
824 } else if (HAS_PCH_SPLIT(dev)) {
825 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
826 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
827 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
828 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
829 } else if (IS_VALLEYVIEW(dev)) {
830 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
831 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
832 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
833 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
835 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
836 TU_SIZE(m_n.tu) | m_n.gmch_m);
837 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
838 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
839 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
843 void intel_dp_init_link_config(struct intel_dp *intel_dp)
845 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
846 intel_dp->link_configuration[0] = intel_dp->link_bw;
847 intel_dp->link_configuration[1] = intel_dp->lane_count;
848 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
850 * Check for DPCD version > 1.1 and enhanced framing support
852 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
853 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
854 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
859 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
860 struct drm_display_mode *adjusted_mode)
862 struct drm_device *dev = encoder->dev;
863 struct drm_i915_private *dev_priv = dev->dev_private;
864 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
865 struct drm_crtc *crtc = intel_dp->base.base.crtc;
866 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
869 * There are four kinds of DP registers:
876 * IBX PCH and CPU are the same for almost everything,
877 * except that the CPU DP PLL is configured in this
880 * CPT PCH is quite different, having many bits moved
881 * to the TRANS_DP_CTL register instead. That
882 * configuration happens (oddly) in ironlake_pch_enable
885 /* Preserve the BIOS-computed detected bit. This is
886 * supposed to be read-only.
888 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
890 /* Handle DP bits in common between all three register formats */
891 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
893 switch (intel_dp->lane_count) {
895 intel_dp->DP |= DP_PORT_WIDTH_1;
898 intel_dp->DP |= DP_PORT_WIDTH_2;
901 intel_dp->DP |= DP_PORT_WIDTH_4;
904 if (intel_dp->has_audio) {
905 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
906 pipe_name(intel_crtc->pipe));
907 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
908 intel_write_eld(encoder, adjusted_mode);
911 intel_dp_init_link_config(intel_dp);
913 /* Split out the IBX/CPU vs CPT settings */
915 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
916 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
917 intel_dp->DP |= DP_SYNC_HS_HIGH;
918 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
919 intel_dp->DP |= DP_SYNC_VS_HIGH;
920 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
922 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
923 intel_dp->DP |= DP_ENHANCED_FRAMING;
925 intel_dp->DP |= intel_crtc->pipe << 29;
927 /* don't miss out required setting for eDP */
928 if (adjusted_mode->clock < 200000)
929 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
931 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
932 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
933 intel_dp->DP |= intel_dp->color_range;
935 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
936 intel_dp->DP |= DP_SYNC_HS_HIGH;
937 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
938 intel_dp->DP |= DP_SYNC_VS_HIGH;
939 intel_dp->DP |= DP_LINK_TRAIN_OFF;
941 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
942 intel_dp->DP |= DP_ENHANCED_FRAMING;
944 if (intel_crtc->pipe == 1)
945 intel_dp->DP |= DP_PIPEB_SELECT;
947 if (is_cpu_edp(intel_dp)) {
948 /* don't miss out required setting for eDP */
949 if (adjusted_mode->clock < 200000)
950 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
952 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
955 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
959 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
960 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
962 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
963 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
965 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
966 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
968 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
972 struct drm_device *dev = intel_dp->base.base.dev;
973 struct drm_i915_private *dev_priv = dev->dev_private;
975 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
977 I915_READ(PCH_PP_STATUS),
978 I915_READ(PCH_PP_CONTROL));
980 if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
981 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
982 I915_READ(PCH_PP_STATUS),
983 I915_READ(PCH_PP_CONTROL));
987 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
989 DRM_DEBUG_KMS("Wait for panel power on\n");
990 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
993 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
995 DRM_DEBUG_KMS("Wait for panel power off time\n");
996 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
999 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1001 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1002 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1006 /* Read the current pp_control value, unlocking the register if it
1010 static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
1012 u32 control = I915_READ(PCH_PP_CONTROL);
1014 control &= ~PANEL_UNLOCK_MASK;
1015 control |= PANEL_UNLOCK_REGS;
1019 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1021 struct drm_device *dev = intel_dp->base.base.dev;
1022 struct drm_i915_private *dev_priv = dev->dev_private;
1025 if (!is_edp(intel_dp))
1027 DRM_DEBUG_KMS("Turn eDP VDD on\n");
1029 WARN(intel_dp->want_panel_vdd,
1030 "eDP VDD already requested on\n");
1032 intel_dp->want_panel_vdd = true;
1034 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1035 DRM_DEBUG_KMS("eDP VDD already on\n");
1039 if (!ironlake_edp_have_panel_power(intel_dp))
1040 ironlake_wait_panel_power_cycle(intel_dp);
1042 pp = ironlake_get_pp_control(dev_priv);
1043 pp |= EDP_FORCE_VDD;
1044 I915_WRITE(PCH_PP_CONTROL, pp);
1045 POSTING_READ(PCH_PP_CONTROL);
1046 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1047 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1050 * If the panel wasn't on, delay before accessing aux channel
1052 if (!ironlake_edp_have_panel_power(intel_dp)) {
1053 DRM_DEBUG_KMS("eDP was not running\n");
1054 msleep(intel_dp->panel_power_up_delay);
1058 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1060 struct drm_device *dev = intel_dp->base.base.dev;
1061 struct drm_i915_private *dev_priv = dev->dev_private;
1064 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1065 pp = ironlake_get_pp_control(dev_priv);
1066 pp &= ~EDP_FORCE_VDD;
1067 I915_WRITE(PCH_PP_CONTROL, pp);
1068 POSTING_READ(PCH_PP_CONTROL);
1070 /* Make sure sequencer is idle before allowing subsequent activity */
1071 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1072 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1074 msleep(intel_dp->panel_power_down_delay);
1078 static void ironlake_panel_vdd_work(struct work_struct *__work)
1080 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1081 struct intel_dp, panel_vdd_work);
1082 struct drm_device *dev = intel_dp->base.base.dev;
1084 mutex_lock(&dev->mode_config.mutex);
1085 ironlake_panel_vdd_off_sync(intel_dp);
1086 mutex_unlock(&dev->mode_config.mutex);
1089 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1091 if (!is_edp(intel_dp))
1094 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1095 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1097 intel_dp->want_panel_vdd = false;
1100 ironlake_panel_vdd_off_sync(intel_dp);
1103 * Queue the timer to fire a long
1104 * time from now (relative to the power down delay)
1105 * to keep the panel power up across a sequence of operations
1107 schedule_delayed_work(&intel_dp->panel_vdd_work,
1108 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1112 static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1114 struct drm_device *dev = intel_dp->base.base.dev;
1115 struct drm_i915_private *dev_priv = dev->dev_private;
1118 if (!is_edp(intel_dp))
1121 DRM_DEBUG_KMS("Turn eDP power on\n");
1123 if (ironlake_edp_have_panel_power(intel_dp)) {
1124 DRM_DEBUG_KMS("eDP power already on\n");
1128 ironlake_wait_panel_power_cycle(intel_dp);
1130 pp = ironlake_get_pp_control(dev_priv);
1132 /* ILK workaround: disable reset around power sequence */
1133 pp &= ~PANEL_POWER_RESET;
1134 I915_WRITE(PCH_PP_CONTROL, pp);
1135 POSTING_READ(PCH_PP_CONTROL);
1138 pp |= POWER_TARGET_ON;
1140 pp |= PANEL_POWER_RESET;
1142 I915_WRITE(PCH_PP_CONTROL, pp);
1143 POSTING_READ(PCH_PP_CONTROL);
1145 ironlake_wait_panel_on(intel_dp);
1148 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1149 I915_WRITE(PCH_PP_CONTROL, pp);
1150 POSTING_READ(PCH_PP_CONTROL);
1154 static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1156 struct drm_device *dev = intel_dp->base.base.dev;
1157 struct drm_i915_private *dev_priv = dev->dev_private;
1160 if (!is_edp(intel_dp))
1163 DRM_DEBUG_KMS("Turn eDP power off\n");
1165 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1167 pp = ironlake_get_pp_control(dev_priv);
1168 /* We need to switch off panel power _and_ force vdd, for otherwise some
1169 * panels get very unhappy and cease to work. */
1170 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1171 I915_WRITE(PCH_PP_CONTROL, pp);
1172 POSTING_READ(PCH_PP_CONTROL);
1174 intel_dp->want_panel_vdd = false;
1176 ironlake_wait_panel_off(intel_dp);
1179 static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1181 struct drm_device *dev = intel_dp->base.base.dev;
1182 struct drm_i915_private *dev_priv = dev->dev_private;
1185 if (!is_edp(intel_dp))
1188 DRM_DEBUG_KMS("\n");
1190 * If we enable the backlight right away following a panel power
1191 * on, we may see slight flicker as the panel syncs with the eDP
1192 * link. So delay a bit to make sure the image is solid before
1193 * allowing it to appear.
1195 msleep(intel_dp->backlight_on_delay);
1196 pp = ironlake_get_pp_control(dev_priv);
1197 pp |= EDP_BLC_ENABLE;
1198 I915_WRITE(PCH_PP_CONTROL, pp);
1199 POSTING_READ(PCH_PP_CONTROL);
1202 static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1204 struct drm_device *dev = intel_dp->base.base.dev;
1205 struct drm_i915_private *dev_priv = dev->dev_private;
1208 if (!is_edp(intel_dp))
1211 DRM_DEBUG_KMS("\n");
1212 pp = ironlake_get_pp_control(dev_priv);
1213 pp &= ~EDP_BLC_ENABLE;
1214 I915_WRITE(PCH_PP_CONTROL, pp);
1215 POSTING_READ(PCH_PP_CONTROL);
1216 msleep(intel_dp->backlight_off_delay);
1219 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1221 struct drm_device *dev = intel_dp->base.base.dev;
1222 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1223 struct drm_i915_private *dev_priv = dev->dev_private;
1226 assert_pipe_disabled(dev_priv,
1227 to_intel_crtc(crtc)->pipe);
1229 DRM_DEBUG_KMS("\n");
1230 dpa_ctl = I915_READ(DP_A);
1231 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1232 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1234 /* We don't adjust intel_dp->DP while tearing down the link, to
1235 * facilitate link retraining (e.g. after hotplug). Hence clear all
1236 * enable bits here to ensure that we don't enable too much. */
1237 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1238 intel_dp->DP |= DP_PLL_ENABLE;
1239 I915_WRITE(DP_A, intel_dp->DP);
1244 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1246 struct drm_device *dev = intel_dp->base.base.dev;
1247 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1248 struct drm_i915_private *dev_priv = dev->dev_private;
1251 assert_pipe_disabled(dev_priv,
1252 to_intel_crtc(crtc)->pipe);
1254 dpa_ctl = I915_READ(DP_A);
1255 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1256 "dp pll off, should be on\n");
1257 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1259 /* We can't rely on the value tracked for the DP register in
1260 * intel_dp->DP because link_down must not change that (otherwise link
1261 * re-training will fail. */
1262 dpa_ctl &= ~DP_PLL_ENABLE;
1263 I915_WRITE(DP_A, dpa_ctl);
1268 /* If the sink supports it, try to set the power state appropriately */
1269 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1273 /* Should have a valid DPCD by this point */
1274 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1277 if (mode != DRM_MODE_DPMS_ON) {
1278 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1281 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1284 * When turning on, we need to retry for 1ms to give the sink
1287 for (i = 0; i < 3; i++) {
1288 ret = intel_dp_aux_native_write_1(intel_dp,
1298 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1301 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1302 struct drm_device *dev = encoder->base.dev;
1303 struct drm_i915_private *dev_priv = dev->dev_private;
1304 u32 tmp = I915_READ(intel_dp->output_reg);
1306 if (!(tmp & DP_PORT_EN))
1309 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
1310 *pipe = PORT_TO_PIPE_CPT(tmp);
1311 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1312 *pipe = PORT_TO_PIPE(tmp);
1318 switch (intel_dp->output_reg) {
1320 trans_sel = TRANS_DP_PORT_SEL_B;
1323 trans_sel = TRANS_DP_PORT_SEL_C;
1326 trans_sel = TRANS_DP_PORT_SEL_D;
1333 trans_dp = I915_READ(TRANS_DP_CTL(i));
1334 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1341 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", intel_dp->output_reg);
1346 static void intel_disable_dp(struct intel_encoder *encoder)
1348 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1350 /* Make sure the panel is off before trying to change the mode. But also
1351 * ensure that we have vdd while we switch off the panel. */
1352 ironlake_edp_panel_vdd_on(intel_dp);
1353 ironlake_edp_backlight_off(intel_dp);
1354 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1355 ironlake_edp_panel_off(intel_dp);
1357 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1358 if (!is_cpu_edp(intel_dp))
1359 intel_dp_link_down(intel_dp);
1362 static void intel_post_disable_dp(struct intel_encoder *encoder)
1364 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1366 if (is_cpu_edp(intel_dp)) {
1367 intel_dp_link_down(intel_dp);
1368 ironlake_edp_pll_off(intel_dp);
1372 static void intel_enable_dp(struct intel_encoder *encoder)
1374 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1375 struct drm_device *dev = encoder->base.dev;
1376 struct drm_i915_private *dev_priv = dev->dev_private;
1377 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1379 if (WARN_ON(dp_reg & DP_PORT_EN))
1382 ironlake_edp_panel_vdd_on(intel_dp);
1383 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1384 intel_dp_start_link_train(intel_dp);
1385 ironlake_edp_panel_on(intel_dp);
1386 ironlake_edp_panel_vdd_off(intel_dp, true);
1387 intel_dp_complete_link_train(intel_dp);
1388 ironlake_edp_backlight_on(intel_dp);
1391 static void intel_pre_enable_dp(struct intel_encoder *encoder)
1393 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1395 if (is_cpu_edp(intel_dp))
1396 ironlake_edp_pll_on(intel_dp);
1400 * Native read with retry for link status and receiver capability reads for
1401 * cases where the sink may still be asleep.
1404 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1405 uint8_t *recv, int recv_bytes)
1410 * Sinks are *supposed* to come up within 1ms from an off state,
1411 * but we're also supposed to retry 3 times per the spec.
1413 for (i = 0; i < 3; i++) {
1414 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1416 if (ret == recv_bytes)
1425 * Fetch AUX CH registers 0x202 - 0x207 which contain
1426 * link status information
1429 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1431 return intel_dp_aux_native_read_retry(intel_dp,
1434 DP_LINK_STATUS_SIZE);
1438 static char *voltage_names[] = {
1439 "0.4V", "0.6V", "0.8V", "1.2V"
1441 static char *pre_emph_names[] = {
1442 "0dB", "3.5dB", "6dB", "9.5dB"
1444 static char *link_train_names[] = {
1445 "pattern 1", "pattern 2", "idle", "off"
1450 * These are source-specific values; current Intel hardware supports
1451 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1455 intel_dp_voltage_max(struct intel_dp *intel_dp)
1457 struct drm_device *dev = intel_dp->base.base.dev;
1459 if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1460 return DP_TRAIN_VOLTAGE_SWING_800;
1461 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1462 return DP_TRAIN_VOLTAGE_SWING_1200;
1464 return DP_TRAIN_VOLTAGE_SWING_800;
1468 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1470 struct drm_device *dev = intel_dp->base.base.dev;
1472 if (IS_HASWELL(dev)) {
1473 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1474 case DP_TRAIN_VOLTAGE_SWING_400:
1475 return DP_TRAIN_PRE_EMPHASIS_9_5;
1476 case DP_TRAIN_VOLTAGE_SWING_600:
1477 return DP_TRAIN_PRE_EMPHASIS_6;
1478 case DP_TRAIN_VOLTAGE_SWING_800:
1479 return DP_TRAIN_PRE_EMPHASIS_3_5;
1480 case DP_TRAIN_VOLTAGE_SWING_1200:
1482 return DP_TRAIN_PRE_EMPHASIS_0;
1484 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1485 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1486 case DP_TRAIN_VOLTAGE_SWING_400:
1487 return DP_TRAIN_PRE_EMPHASIS_6;
1488 case DP_TRAIN_VOLTAGE_SWING_600:
1489 case DP_TRAIN_VOLTAGE_SWING_800:
1490 return DP_TRAIN_PRE_EMPHASIS_3_5;
1492 return DP_TRAIN_PRE_EMPHASIS_0;
1495 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1496 case DP_TRAIN_VOLTAGE_SWING_400:
1497 return DP_TRAIN_PRE_EMPHASIS_6;
1498 case DP_TRAIN_VOLTAGE_SWING_600:
1499 return DP_TRAIN_PRE_EMPHASIS_6;
1500 case DP_TRAIN_VOLTAGE_SWING_800:
1501 return DP_TRAIN_PRE_EMPHASIS_3_5;
1502 case DP_TRAIN_VOLTAGE_SWING_1200:
1504 return DP_TRAIN_PRE_EMPHASIS_0;
1510 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1515 uint8_t voltage_max;
1516 uint8_t preemph_max;
1518 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1519 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1520 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
1528 voltage_max = intel_dp_voltage_max(intel_dp);
1529 if (v >= voltage_max)
1530 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1532 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1533 if (p >= preemph_max)
1534 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1536 for (lane = 0; lane < 4; lane++)
1537 intel_dp->train_set[lane] = v | p;
1541 intel_dp_signal_levels(uint8_t train_set)
1543 uint32_t signal_levels = 0;
1545 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1546 case DP_TRAIN_VOLTAGE_SWING_400:
1548 signal_levels |= DP_VOLTAGE_0_4;
1550 case DP_TRAIN_VOLTAGE_SWING_600:
1551 signal_levels |= DP_VOLTAGE_0_6;
1553 case DP_TRAIN_VOLTAGE_SWING_800:
1554 signal_levels |= DP_VOLTAGE_0_8;
1556 case DP_TRAIN_VOLTAGE_SWING_1200:
1557 signal_levels |= DP_VOLTAGE_1_2;
1560 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1561 case DP_TRAIN_PRE_EMPHASIS_0:
1563 signal_levels |= DP_PRE_EMPHASIS_0;
1565 case DP_TRAIN_PRE_EMPHASIS_3_5:
1566 signal_levels |= DP_PRE_EMPHASIS_3_5;
1568 case DP_TRAIN_PRE_EMPHASIS_6:
1569 signal_levels |= DP_PRE_EMPHASIS_6;
1571 case DP_TRAIN_PRE_EMPHASIS_9_5:
1572 signal_levels |= DP_PRE_EMPHASIS_9_5;
1575 return signal_levels;
1578 /* Gen6's DP voltage swing and pre-emphasis control */
1580 intel_gen6_edp_signal_levels(uint8_t train_set)
1582 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1583 DP_TRAIN_PRE_EMPHASIS_MASK);
1584 switch (signal_levels) {
1585 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1586 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1587 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1588 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1589 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1590 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1591 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1592 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1593 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1594 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1595 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1596 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1597 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1598 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1600 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1601 "0x%x\n", signal_levels);
1602 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1606 /* Gen7's DP voltage swing and pre-emphasis control */
1608 intel_gen7_edp_signal_levels(uint8_t train_set)
1610 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1611 DP_TRAIN_PRE_EMPHASIS_MASK);
1612 switch (signal_levels) {
1613 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1614 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1615 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1616 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1617 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1618 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1620 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1621 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1622 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1623 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1625 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1626 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1627 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1628 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1631 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1632 "0x%x\n", signal_levels);
1633 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1637 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1639 intel_dp_signal_levels_hsw(uint8_t train_set)
1641 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1642 DP_TRAIN_PRE_EMPHASIS_MASK);
1643 switch (signal_levels) {
1644 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1645 return DDI_BUF_EMP_400MV_0DB_HSW;
1646 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1647 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1648 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1649 return DDI_BUF_EMP_400MV_6DB_HSW;
1650 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1651 return DDI_BUF_EMP_400MV_9_5DB_HSW;
1653 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1654 return DDI_BUF_EMP_600MV_0DB_HSW;
1655 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1656 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1657 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1658 return DDI_BUF_EMP_600MV_6DB_HSW;
1660 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1661 return DDI_BUF_EMP_800MV_0DB_HSW;
1662 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1663 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1665 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1666 "0x%x\n", signal_levels);
1667 return DDI_BUF_EMP_400MV_0DB_HSW;
1672 intel_dp_set_link_train(struct intel_dp *intel_dp,
1673 uint32_t dp_reg_value,
1674 uint8_t dp_train_pat)
1676 struct drm_device *dev = intel_dp->base.base.dev;
1677 struct drm_i915_private *dev_priv = dev->dev_private;
1681 if (IS_HASWELL(dev)) {
1682 temp = I915_READ(DP_TP_CTL(intel_dp->port));
1684 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1685 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1687 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1689 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1690 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1691 case DP_TRAINING_PATTERN_DISABLE:
1692 temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
1693 I915_WRITE(DP_TP_CTL(intel_dp->port), temp);
1695 if (wait_for((I915_READ(DP_TP_STATUS(intel_dp->port)) &
1696 DP_TP_STATUS_IDLE_DONE), 1))
1697 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1699 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1700 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1703 case DP_TRAINING_PATTERN_1:
1704 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1706 case DP_TRAINING_PATTERN_2:
1707 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1709 case DP_TRAINING_PATTERN_3:
1710 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1713 I915_WRITE(DP_TP_CTL(intel_dp->port), temp);
1715 } else if (HAS_PCH_CPT(dev) &&
1716 (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1717 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1719 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1720 case DP_TRAINING_PATTERN_DISABLE:
1721 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1723 case DP_TRAINING_PATTERN_1:
1724 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1726 case DP_TRAINING_PATTERN_2:
1727 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1729 case DP_TRAINING_PATTERN_3:
1730 DRM_ERROR("DP training pattern 3 not supported\n");
1731 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1736 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1738 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1739 case DP_TRAINING_PATTERN_DISABLE:
1740 dp_reg_value |= DP_LINK_TRAIN_OFF;
1742 case DP_TRAINING_PATTERN_1:
1743 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1745 case DP_TRAINING_PATTERN_2:
1746 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1748 case DP_TRAINING_PATTERN_3:
1749 DRM_ERROR("DP training pattern 3 not supported\n");
1750 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1755 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1756 POSTING_READ(intel_dp->output_reg);
1758 intel_dp_aux_native_write_1(intel_dp,
1759 DP_TRAINING_PATTERN_SET,
1762 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1763 DP_TRAINING_PATTERN_DISABLE) {
1764 ret = intel_dp_aux_native_write(intel_dp,
1765 DP_TRAINING_LANE0_SET,
1766 intel_dp->train_set,
1767 intel_dp->lane_count);
1768 if (ret != intel_dp->lane_count)
1775 /* Enable corresponding port and start training pattern 1 */
1777 intel_dp_start_link_train(struct intel_dp *intel_dp)
1779 struct drm_encoder *encoder = &intel_dp->base.base;
1780 struct drm_device *dev = encoder->dev;
1783 bool clock_recovery = false;
1784 int voltage_tries, loop_tries;
1785 uint32_t DP = intel_dp->DP;
1787 if (IS_HASWELL(dev))
1788 intel_ddi_prepare_link_retrain(encoder);
1790 /* Write the link configuration data */
1791 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1792 intel_dp->link_configuration,
1793 DP_LINK_CONFIGURATION_SIZE);
1797 memset(intel_dp->train_set, 0, 4);
1801 clock_recovery = false;
1803 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1804 uint8_t link_status[DP_LINK_STATUS_SIZE];
1805 uint32_t signal_levels;
1807 if (IS_HASWELL(dev)) {
1808 signal_levels = intel_dp_signal_levels_hsw(
1809 intel_dp->train_set[0]);
1810 DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
1811 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1812 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1813 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1814 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1815 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1816 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1818 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1819 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1821 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n",
1824 /* Set training pattern 1 */
1825 if (!intel_dp_set_link_train(intel_dp, DP,
1826 DP_TRAINING_PATTERN_1 |
1827 DP_LINK_SCRAMBLING_DISABLE))
1830 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
1831 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1832 DRM_ERROR("failed to get link status\n");
1836 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1837 DRM_DEBUG_KMS("clock recovery OK\n");
1838 clock_recovery = true;
1842 /* Check to see if we've tried the max voltage */
1843 for (i = 0; i < intel_dp->lane_count; i++)
1844 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1846 if (i == intel_dp->lane_count && voltage_tries == 5) {
1847 if (++loop_tries == 5) {
1848 DRM_DEBUG_KMS("too many full retries, give up\n");
1851 memset(intel_dp->train_set, 0, 4);
1856 /* Check to see if we've tried the same voltage 5 times */
1857 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) {
1858 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1863 /* Compute new intel_dp->train_set as requested by target */
1864 intel_get_adjust_train(intel_dp, link_status);
1871 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1873 struct drm_device *dev = intel_dp->base.base.dev;
1874 bool channel_eq = false;
1875 int tries, cr_tries;
1876 uint32_t DP = intel_dp->DP;
1878 /* channel equalization */
1883 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1884 uint32_t signal_levels;
1885 uint8_t link_status[DP_LINK_STATUS_SIZE];
1888 DRM_ERROR("failed to train DP, aborting\n");
1889 intel_dp_link_down(intel_dp);
1893 if (IS_HASWELL(dev)) {
1894 signal_levels = intel_dp_signal_levels_hsw(intel_dp->train_set[0]);
1895 DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
1896 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1897 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1898 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1899 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1900 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1901 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1903 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1904 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1907 /* channel eq pattern */
1908 if (!intel_dp_set_link_train(intel_dp, DP,
1909 DP_TRAINING_PATTERN_2 |
1910 DP_LINK_SCRAMBLING_DISABLE))
1913 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
1914 if (!intel_dp_get_link_status(intel_dp, link_status))
1917 /* Make sure clock is still ok */
1918 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1919 intel_dp_start_link_train(intel_dp);
1924 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
1929 /* Try 5 times, then try clock recovery if that fails */
1931 intel_dp_link_down(intel_dp);
1932 intel_dp_start_link_train(intel_dp);
1938 /* Compute new intel_dp->train_set as requested by target */
1939 intel_get_adjust_train(intel_dp, link_status);
1944 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
1946 intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
1950 intel_dp_link_down(struct intel_dp *intel_dp)
1952 struct drm_device *dev = intel_dp->base.base.dev;
1953 struct drm_i915_private *dev_priv = dev->dev_private;
1954 uint32_t DP = intel_dp->DP;
1957 * DDI code has a strict mode set sequence and we should try to respect
1958 * it, otherwise we might hang the machine in many different ways. So we
1959 * really should be disabling the port only on a complete crtc_disable
1960 * sequence. This function is just called under two conditions on DDI
1962 * - Link train failed while doing crtc_enable, and on this case we
1963 * really should respect the mode set sequence and wait for a
1965 * - Someone turned the monitor off and intel_dp_check_link_status
1966 * called us. We don't need to disable the whole port on this case, so
1967 * when someone turns the monitor on again,
1968 * intel_ddi_prepare_link_retrain will take care of redoing the link
1971 if (IS_HASWELL(dev))
1974 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1977 DRM_DEBUG_KMS("\n");
1979 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1980 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1981 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1983 DP &= ~DP_LINK_TRAIN_MASK;
1984 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1986 POSTING_READ(intel_dp->output_reg);
1990 if (HAS_PCH_IBX(dev) &&
1991 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
1992 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1994 /* Hardware workaround: leaving our transcoder select
1995 * set to transcoder B while it's off will prevent the
1996 * corresponding HDMI output on transcoder A.
1998 * Combine this with another hardware workaround:
1999 * transcoder select bit can only be cleared while the
2002 DP &= ~DP_PIPEB_SELECT;
2003 I915_WRITE(intel_dp->output_reg, DP);
2005 /* Changes to enable or select take place the vblank
2006 * after being written.
2009 /* We can arrive here never having been attached
2010 * to a CRTC, for instance, due to inheriting
2011 * random state from the BIOS.
2013 * If the pipe is not running, play safe and
2014 * wait for the clocks to stabilise before
2017 POSTING_READ(intel_dp->output_reg);
2020 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
2023 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2024 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2025 POSTING_READ(intel_dp->output_reg);
2026 msleep(intel_dp->panel_power_down_delay);
2030 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2032 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2033 sizeof(intel_dp->dpcd)) == 0)
2034 return false; /* aux transfer failed */
2036 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2037 return false; /* DPCD not present */
2039 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2040 DP_DWN_STRM_PORT_PRESENT))
2041 return true; /* native DP sink */
2043 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2044 return true; /* no per-port downstream info */
2046 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2047 intel_dp->downstream_ports,
2048 DP_MAX_DOWNSTREAM_PORTS) == 0)
2049 return false; /* downstream port status fetch failed */
2055 intel_dp_probe_oui(struct intel_dp *intel_dp)
2059 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2062 ironlake_edp_panel_vdd_on(intel_dp);
2064 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2065 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2066 buf[0], buf[1], buf[2]);
2068 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2069 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2070 buf[0], buf[1], buf[2]);
2072 ironlake_edp_panel_vdd_off(intel_dp, false);
2076 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2080 ret = intel_dp_aux_native_read_retry(intel_dp,
2081 DP_DEVICE_SERVICE_IRQ_VECTOR,
2082 sink_irq_vector, 1);
2090 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2092 /* NAK by default */
2093 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK);
2097 * According to DP spec
2100 * 2. Configure link according to Receiver Capabilities
2101 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2102 * 4. Check link status on receipt of hot-plug interrupt
2106 intel_dp_check_link_status(struct intel_dp *intel_dp)
2109 u8 link_status[DP_LINK_STATUS_SIZE];
2111 if (!intel_dp->base.connectors_active)
2114 if (WARN_ON(!intel_dp->base.base.crtc))
2117 /* Try to read receiver status if the link appears to be up */
2118 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2119 intel_dp_link_down(intel_dp);
2123 /* Now read the DPCD to see if it's actually running */
2124 if (!intel_dp_get_dpcd(intel_dp)) {
2125 intel_dp_link_down(intel_dp);
2129 /* Try to read the source of the interrupt */
2130 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2131 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2132 /* Clear interrupt source */
2133 intel_dp_aux_native_write_1(intel_dp,
2134 DP_DEVICE_SERVICE_IRQ_VECTOR,
2137 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2138 intel_dp_handle_test_request(intel_dp);
2139 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2140 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2143 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2144 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2145 drm_get_encoder_name(&intel_dp->base.base));
2146 intel_dp_start_link_train(intel_dp);
2147 intel_dp_complete_link_train(intel_dp);
2151 /* XXX this is probably wrong for multiple downstream ports */
2152 static enum drm_connector_status
2153 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2155 uint8_t *dpcd = intel_dp->dpcd;
2159 if (!intel_dp_get_dpcd(intel_dp))
2160 return connector_status_disconnected;
2162 /* if there's no downstream port, we're done */
2163 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2164 return connector_status_connected;
2166 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2167 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2170 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2172 return connector_status_unknown;
2173 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2174 : connector_status_disconnected;
2177 /* If no HPD, poke DDC gently */
2178 if (drm_probe_ddc(&intel_dp->adapter))
2179 return connector_status_connected;
2181 /* Well we tried, say unknown for unreliable port types */
2182 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2183 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2184 return connector_status_unknown;
2186 /* Anything else is out of spec, warn and ignore */
2187 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2188 return connector_status_disconnected;
2191 static enum drm_connector_status
2192 ironlake_dp_detect(struct intel_dp *intel_dp)
2194 enum drm_connector_status status;
2196 /* Can't disconnect eDP, but you can close the lid... */
2197 if (is_edp(intel_dp)) {
2198 status = intel_panel_detect(intel_dp->base.base.dev);
2199 if (status == connector_status_unknown)
2200 status = connector_status_connected;
2204 return intel_dp_detect_dpcd(intel_dp);
2207 static enum drm_connector_status
2208 g4x_dp_detect(struct intel_dp *intel_dp)
2210 struct drm_device *dev = intel_dp->base.base.dev;
2211 struct drm_i915_private *dev_priv = dev->dev_private;
2214 switch (intel_dp->output_reg) {
2216 bit = DPB_HOTPLUG_LIVE_STATUS;
2219 bit = DPC_HOTPLUG_LIVE_STATUS;
2222 bit = DPD_HOTPLUG_LIVE_STATUS;
2225 return connector_status_unknown;
2228 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2229 return connector_status_disconnected;
2231 return intel_dp_detect_dpcd(intel_dp);
2234 static struct edid *
2235 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2237 struct intel_connector *intel_connector = to_intel_connector(connector);
2239 /* use cached edid if we have one */
2240 if (intel_connector->edid) {
2245 if (IS_ERR(intel_connector->edid))
2248 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
2249 edid = kmalloc(size, GFP_KERNEL);
2253 memcpy(edid, intel_connector->edid, size);
2257 return drm_get_edid(connector, adapter);
2261 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2263 struct intel_connector *intel_connector = to_intel_connector(connector);
2265 /* use cached edid if we have one */
2266 if (intel_connector->edid) {
2268 if (IS_ERR(intel_connector->edid))
2271 return intel_connector_update_modes(connector,
2272 intel_connector->edid);
2275 return intel_ddc_get_modes(connector, adapter);
2280 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2282 * \return true if DP port is connected.
2283 * \return false if DP port is disconnected.
2285 static enum drm_connector_status
2286 intel_dp_detect(struct drm_connector *connector, bool force)
2288 struct intel_dp *intel_dp = intel_attached_dp(connector);
2289 struct drm_device *dev = intel_dp->base.base.dev;
2290 enum drm_connector_status status;
2291 struct edid *edid = NULL;
2293 intel_dp->has_audio = false;
2295 if (HAS_PCH_SPLIT(dev))
2296 status = ironlake_dp_detect(intel_dp);
2298 status = g4x_dp_detect(intel_dp);
2300 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2301 intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
2302 intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
2303 intel_dp->dpcd[6], intel_dp->dpcd[7]);
2305 if (status != connector_status_connected)
2308 intel_dp_probe_oui(intel_dp);
2310 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2311 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2313 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2315 intel_dp->has_audio = drm_detect_monitor_audio(edid);
2320 return connector_status_connected;
2323 static int intel_dp_get_modes(struct drm_connector *connector)
2325 struct intel_dp *intel_dp = intel_attached_dp(connector);
2326 struct intel_connector *intel_connector = to_intel_connector(connector);
2327 struct drm_device *dev = intel_dp->base.base.dev;
2330 /* We should parse the EDID data and find out if it has an audio sink
2333 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2337 /* if eDP has no EDID, fall back to fixed mode */
2338 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2339 struct drm_display_mode *mode;
2340 mode = drm_mode_duplicate(dev,
2341 intel_connector->panel.fixed_mode);
2343 drm_mode_probed_add(connector, mode);
2351 intel_dp_detect_audio(struct drm_connector *connector)
2353 struct intel_dp *intel_dp = intel_attached_dp(connector);
2355 bool has_audio = false;
2357 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2359 has_audio = drm_detect_monitor_audio(edid);
2367 intel_dp_set_property(struct drm_connector *connector,
2368 struct drm_property *property,
2371 struct drm_i915_private *dev_priv = connector->dev->dev_private;
2372 struct intel_dp *intel_dp = intel_attached_dp(connector);
2375 ret = drm_connector_property_set_value(connector, property, val);
2379 if (property == dev_priv->force_audio_property) {
2383 if (i == intel_dp->force_audio)
2386 intel_dp->force_audio = i;
2388 if (i == HDMI_AUDIO_AUTO)
2389 has_audio = intel_dp_detect_audio(connector);
2391 has_audio = (i == HDMI_AUDIO_ON);
2393 if (has_audio == intel_dp->has_audio)
2396 intel_dp->has_audio = has_audio;
2400 if (property == dev_priv->broadcast_rgb_property) {
2401 if (val == !!intel_dp->color_range)
2404 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2411 if (intel_dp->base.base.crtc) {
2412 struct drm_crtc *crtc = intel_dp->base.base.crtc;
2413 intel_set_mode(crtc, &crtc->mode,
2414 crtc->x, crtc->y, crtc->fb);
2421 intel_dp_destroy(struct drm_connector *connector)
2423 struct drm_device *dev = connector->dev;
2424 struct intel_dp *intel_dp = intel_attached_dp(connector);
2425 struct intel_connector *intel_connector = to_intel_connector(connector);
2427 if (!IS_ERR_OR_NULL(intel_connector->edid))
2428 kfree(intel_connector->edid);
2430 if (is_edp(intel_dp)) {
2431 intel_panel_destroy_backlight(dev);
2432 intel_panel_fini(&intel_connector->panel);
2435 drm_sysfs_connector_remove(connector);
2436 drm_connector_cleanup(connector);
2440 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2442 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2444 i2c_del_adapter(&intel_dp->adapter);
2445 drm_encoder_cleanup(encoder);
2446 if (is_edp(intel_dp)) {
2447 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2448 ironlake_panel_vdd_off_sync(intel_dp);
2453 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2454 .mode_fixup = intel_dp_mode_fixup,
2455 .mode_set = intel_dp_mode_set,
2456 .disable = intel_encoder_noop,
2459 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs_hsw = {
2460 .mode_fixup = intel_dp_mode_fixup,
2461 .mode_set = intel_ddi_mode_set,
2462 .disable = intel_encoder_noop,
2465 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2466 .dpms = intel_connector_dpms,
2467 .detect = intel_dp_detect,
2468 .fill_modes = drm_helper_probe_single_connector_modes,
2469 .set_property = intel_dp_set_property,
2470 .destroy = intel_dp_destroy,
2473 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2474 .get_modes = intel_dp_get_modes,
2475 .mode_valid = intel_dp_mode_valid,
2476 .best_encoder = intel_best_encoder,
2479 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2480 .destroy = intel_dp_encoder_destroy,
2484 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2486 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
2488 intel_dp_check_link_status(intel_dp);
2491 /* Return which DP Port should be selected for Transcoder DP control */
2493 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2495 struct drm_device *dev = crtc->dev;
2496 struct intel_encoder *encoder;
2498 for_each_encoder_on_crtc(dev, crtc, encoder) {
2499 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2501 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
2502 intel_dp->base.type == INTEL_OUTPUT_EDP)
2503 return intel_dp->output_reg;
2509 /* check the VBT to see whether the eDP is on DP-D port */
2510 bool intel_dpd_is_edp(struct drm_device *dev)
2512 struct drm_i915_private *dev_priv = dev->dev_private;
2513 struct child_device_config *p_child;
2516 if (!dev_priv->child_dev_num)
2519 for (i = 0; i < dev_priv->child_dev_num; i++) {
2520 p_child = dev_priv->child_dev + i;
2522 if (p_child->dvo_port == PORT_IDPD &&
2523 p_child->device_type == DEVICE_TYPE_eDP)
2530 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2532 intel_attach_force_audio_property(connector);
2533 intel_attach_broadcast_rgb_property(connector);
2537 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
2539 struct drm_i915_private *dev_priv = dev->dev_private;
2540 struct drm_connector *connector;
2541 struct intel_dp *intel_dp;
2542 struct intel_encoder *intel_encoder;
2543 struct intel_connector *intel_connector;
2544 struct drm_display_mode *fixed_mode = NULL;
2545 const char *name = NULL;
2548 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2552 intel_dp->output_reg = output_reg;
2553 intel_dp->port = port;
2554 /* Preserve the current hw state. */
2555 intel_dp->DP = I915_READ(intel_dp->output_reg);
2557 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2558 if (!intel_connector) {
2562 intel_encoder = &intel_dp->base;
2563 intel_dp->attached_connector = intel_connector;
2565 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
2566 if (intel_dpd_is_edp(dev))
2567 intel_dp->is_pch_edp = true;
2570 * FIXME : We need to initialize built-in panels before external panels.
2571 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2573 if (IS_VALLEYVIEW(dev) && output_reg == DP_C) {
2574 type = DRM_MODE_CONNECTOR_eDP;
2575 intel_encoder->type = INTEL_OUTPUT_EDP;
2576 } else if (output_reg == DP_A || is_pch_edp(intel_dp)) {
2577 type = DRM_MODE_CONNECTOR_eDP;
2578 intel_encoder->type = INTEL_OUTPUT_EDP;
2580 type = DRM_MODE_CONNECTOR_DisplayPort;
2581 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2584 connector = &intel_connector->base;
2585 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2586 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2588 connector->polled = DRM_CONNECTOR_POLL_HPD;
2590 intel_encoder->cloneable = false;
2592 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2593 ironlake_panel_vdd_work);
2595 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2597 connector->interlace_allowed = true;
2598 connector->doublescan_allowed = 0;
2600 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2601 DRM_MODE_ENCODER_TMDS);
2603 if (IS_HASWELL(dev))
2604 drm_encoder_helper_add(&intel_encoder->base,
2605 &intel_dp_helper_funcs_hsw);
2607 drm_encoder_helper_add(&intel_encoder->base,
2608 &intel_dp_helper_funcs);
2610 intel_connector_attach_encoder(intel_connector, intel_encoder);
2611 drm_sysfs_connector_add(connector);
2613 if (IS_HASWELL(dev)) {
2614 intel_encoder->enable = intel_enable_ddi;
2615 intel_encoder->pre_enable = intel_ddi_pre_enable;
2616 intel_encoder->disable = intel_disable_ddi;
2617 intel_encoder->post_disable = intel_ddi_post_disable;
2618 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
2620 intel_encoder->enable = intel_enable_dp;
2621 intel_encoder->pre_enable = intel_pre_enable_dp;
2622 intel_encoder->disable = intel_disable_dp;
2623 intel_encoder->post_disable = intel_post_disable_dp;
2624 intel_encoder->get_hw_state = intel_dp_get_hw_state;
2626 intel_connector->get_hw_state = intel_connector_get_hw_state;
2628 /* Set up the DDC bus. */
2634 dev_priv->hotplug_supported_mask |= DPB_HOTPLUG_INT_STATUS;
2638 dev_priv->hotplug_supported_mask |= DPC_HOTPLUG_INT_STATUS;
2642 dev_priv->hotplug_supported_mask |= DPD_HOTPLUG_INT_STATUS;
2646 WARN(1, "Invalid port %c\n", port_name(port));
2650 /* Cache some DPCD data in the eDP case */
2651 if (is_edp(intel_dp)) {
2652 struct edp_power_seq cur, vbt;
2653 u32 pp_on, pp_off, pp_div;
2655 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2656 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2657 pp_div = I915_READ(PCH_PP_DIVISOR);
2659 if (!pp_on || !pp_off || !pp_div) {
2660 DRM_INFO("bad panel power sequencing delays, disabling panel\n");
2661 intel_dp_encoder_destroy(&intel_dp->base.base);
2662 intel_dp_destroy(&intel_connector->base);
2666 /* Pull timing values out of registers */
2667 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2668 PANEL_POWER_UP_DELAY_SHIFT;
2670 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2671 PANEL_LIGHT_ON_DELAY_SHIFT;
2673 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2674 PANEL_LIGHT_OFF_DELAY_SHIFT;
2676 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2677 PANEL_POWER_DOWN_DELAY_SHIFT;
2679 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2680 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2682 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2683 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2685 vbt = dev_priv->edp.pps;
2687 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2688 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2690 #define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10)
2692 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2693 intel_dp->backlight_on_delay = get_delay(t8);
2694 intel_dp->backlight_off_delay = get_delay(t9);
2695 intel_dp->panel_power_down_delay = get_delay(t10);
2696 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2698 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2699 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2700 intel_dp->panel_power_cycle_delay);
2702 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2703 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2706 intel_dp_i2c_init(intel_dp, intel_connector, name);
2708 if (is_edp(intel_dp)) {
2710 struct drm_display_mode *scan;
2713 ironlake_edp_panel_vdd_on(intel_dp);
2714 ret = intel_dp_get_dpcd(intel_dp);
2715 ironlake_edp_panel_vdd_off(intel_dp, false);
2718 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2719 dev_priv->no_aux_handshake =
2720 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2721 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2723 /* if this fails, presume the device is a ghost */
2724 DRM_INFO("failed to retrieve link info, disabling eDP\n");
2725 intel_dp_encoder_destroy(&intel_dp->base.base);
2726 intel_dp_destroy(&intel_connector->base);
2730 ironlake_edp_panel_vdd_on(intel_dp);
2731 edid = drm_get_edid(connector, &intel_dp->adapter);
2733 if (drm_add_edid_modes(connector, edid)) {
2734 drm_mode_connector_update_edid_property(connector, edid);
2735 drm_edid_to_eld(connector, edid);
2738 edid = ERR_PTR(-EINVAL);
2741 edid = ERR_PTR(-ENOENT);
2743 intel_connector->edid = edid;
2745 /* prefer fixed mode from EDID if available */
2746 list_for_each_entry(scan, &connector->probed_modes, head) {
2747 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
2748 fixed_mode = drm_mode_duplicate(dev, scan);
2753 /* fallback to VBT if available for eDP */
2754 if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
2755 fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2757 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
2760 ironlake_edp_panel_vdd_off(intel_dp, false);
2763 intel_encoder->hot_plug = intel_dp_hot_plug;
2765 if (is_edp(intel_dp)) {
2766 intel_panel_init(&intel_connector->panel, fixed_mode);
2767 intel_panel_setup_backlight(connector);
2770 intel_dp_add_properties(intel_dp, connector);
2772 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2773 * 0xd. Failure to do so will result in spurious interrupts being
2774 * generated on the port when a cable is not attached.
2776 if (IS_G4X(dev) && !IS_GM45(dev)) {
2777 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2778 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);