drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_edid.h>
  35 #include "intel_drv.h"
  36 #include <drm/i915_drm.h>
  37 #include "i915_drv.h"
  38
  39 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  40
  41 /**
  42  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  43  * @intel_dp: DP struct
  44  *
  45  * If a CPU or PCH DP output is attached to an eDP panel, this function
  46  * will return true, and false otherwise.
  47  */
  48 static bool is_edp(struct intel_dp *intel_dp)
  49 {
  50         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  51
  52         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
  53 }
  54
  55 /**
  56  * is_pch_edp - is the port on the PCH and attached to an eDP panel?
  57  * @intel_dp: DP struct
  58  *
  59  * Returns true if the given DP struct corresponds to a PCH DP port attached
  60  * to an eDP panel, false otherwise.  Helpful for determining whether we
  61  * may need FDI resources for a given DP output or not.
  62  */
  63 static bool is_pch_edp(struct intel_dp *intel_dp)
  64 {
  65         return intel_dp->is_pch_edp;
  66 }
  67
  68 /**
  69  * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
  70  * @intel_dp: DP struct
  71  *
  72  * Returns true if the given DP struct corresponds to a CPU eDP port.
  73  */
  74 static bool is_cpu_edp(struct intel_dp *intel_dp)
  75 {
  76         return is_edp(intel_dp) && !is_pch_edp(intel_dp);
  77 }
  78
  79 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
  80 {
  81         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  82
  83         return intel_dig_port->base.base.dev;
  84 }
  85
  86 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
  87 {
  88         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
  89 }
  90
  91 /**
  92  * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
  93  * @encoder: DRM encoder
  94  *
  95  * Return true if @encoder corresponds to a PCH attached eDP panel.  Needed
  96  * by intel_display.c.
  97  */
  98 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
  99 {
 100         struct intel_dp *intel_dp;
 101
 102         if (!encoder)
 103                 return false;
 104
 105         intel_dp = enc_to_intel_dp(encoder);
 106
 107         return is_pch_edp(intel_dp);
 108 }
 109
 110 static void intel_dp_link_down(struct intel_dp *intel_dp);
 111
 112 void
 113 intel_edp_link_config(struct intel_encoder *intel_encoder,
 114                        int *lane_num, int *link_bw)
 115 {
 116         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
 117
 118         *lane_num = intel_dp->lane_count;
 119         *link_bw = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
 120 }
 121
 122 int
 123 intel_edp_target_clock(struct intel_encoder *intel_encoder,
 124                        struct drm_display_mode *mode)
 125 {
 126         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
 127         struct intel_connector *intel_connector = intel_dp->attached_connector;
 128
 129         if (intel_connector->panel.fixed_mode)
 130                 return intel_connector->panel.fixed_mode->clock;
 131         else
 132                 return mode->clock;
 133 }
 134
 135 static int
 136 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 137 {
 138         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 139
 140         switch (max_link_bw) {
 141         case DP_LINK_BW_1_62:
 142         case DP_LINK_BW_2_7:
 143                 break;
 144         default:
 145                 max_link_bw = DP_LINK_BW_1_62;
 146                 break;
 147         }
 148         return max_link_bw;
 149 }
 150
 151 static int
 152 intel_dp_link_clock(uint8_t link_bw)
 153 {
 154         if (link_bw == DP_LINK_BW_2_7)
 155                 return 270000;
 156         else
 157                 return 162000;
 158 }
 159
 160 /*
 161  * The units on the numbers in the next two are... bizarre.  Examples will
 162  * make it clearer; this one parallels an example in the eDP spec.
 163  *
 164  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 165  *
 166  *     270000 * 1 * 8 / 10 == 216000
 167  *
 168  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 169  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 170  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 171  * 119000.  At 18bpp that's 2142000 kilobits per second.
 172  *
 173  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 174  * get the result in decakilobits instead of kilobits.
 175  */
 176
 177 static int
 178 intel_dp_link_required(int pixel_clock, int bpp)
 179 {
 180         return (pixel_clock * bpp + 9) / 10;
 181 }
 182
 183 static int
 184 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 185 {
 186         return (max_link_clock * max_lanes * 8) / 10;
 187 }
 188
 189 static bool
 190 intel_dp_adjust_dithering(struct intel_dp *intel_dp,
 191                           struct drm_display_mode *mode,
 192                           bool adjust_mode)
 193 {
 194         int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
 195         int max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
 196         int max_rate, mode_rate;
 197
 198         mode_rate = intel_dp_link_required(mode->clock, 24);
 199         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 200
 201         if (mode_rate > max_rate) {
 202                 mode_rate = intel_dp_link_required(mode->clock, 18);
 203                 if (mode_rate > max_rate)
 204                         return false;
 205
 206                 if (adjust_mode)
 207                         mode->private_flags
 208                                 |= INTEL_MODE_DP_FORCE_6BPC;
 209
 210                 return true;
 211         }
 212
 213         return true;
 214 }
 215
 216 static int
 217 intel_dp_mode_valid(struct drm_connector *connector,
 218                     struct drm_display_mode *mode)
 219 {
 220         struct intel_dp *intel_dp = intel_attached_dp(connector);
 221         struct intel_connector *intel_connector = to_intel_connector(connector);
 222         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 223
 224         if (is_edp(intel_dp) && fixed_mode) {
 225                 if (mode->hdisplay > fixed_mode->hdisplay)
 226                         return MODE_PANEL;
 227
 228                 if (mode->vdisplay > fixed_mode->vdisplay)
 229                         return MODE_PANEL;
 230         }
 231
 232         if (!intel_dp_adjust_dithering(intel_dp, mode, false))
 233                 return MODE_CLOCK_HIGH;
 234
 235         if (mode->clock < 10000)
 236                 return MODE_CLOCK_LOW;
 237
 238         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 239                 return MODE_H_ILLEGAL;
 240
 241         return MODE_OK;
 242 }
 243
 244 static uint32_t
 245 pack_aux(uint8_t *src, int src_bytes)
 246 {
 247         int     i;
 248         uint32_t v = 0;
 249
 250         if (src_bytes > 4)
 251                 src_bytes = 4;
 252         for (i = 0; i < src_bytes; i++)
 253                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 254         return v;
 255 }
 256
 257 static void
 258 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 259 {
 260         int i;
 261         if (dst_bytes > 4)
 262                 dst_bytes = 4;
 263         for (i = 0; i < dst_bytes; i++)
 264                 dst[i] = src >> ((3-i) * 8);
 265 }
 266
 267 /* hrawclock is 1/4 the FSB frequency */
 268 static int
 269 intel_hrawclk(struct drm_device *dev)
 270 {
 271         struct drm_i915_private *dev_priv = dev->dev_private;
 272         uint32_t clkcfg;
 273
 274         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 275         if (IS_VALLEYVIEW(dev))
 276                 return 200;
 277
 278         clkcfg = I915_READ(CLKCFG);
 279         switch (clkcfg & CLKCFG_FSB_MASK) {
 280         case CLKCFG_FSB_400:
 281                 return 100;
 282         case CLKCFG_FSB_533:
 283                 return 133;
 284         case CLKCFG_FSB_667:
 285                 return 166;
 286         case CLKCFG_FSB_800:
 287                 return 200;
 288         case CLKCFG_FSB_1067:
 289                 return 266;
 290         case CLKCFG_FSB_1333:
 291                 return 333;
 292         /* these two are just a guess; one of them might be right */
 293         case CLKCFG_FSB_1600:
 294         case CLKCFG_FSB_1600_ALT:
 295                 return 400;
 296         default:
 297                 return 133;
 298         }
 299 }
 300
 301 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
 302 {
 303         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 304         struct drm_i915_private *dev_priv = dev->dev_private;
 305
 306         return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
 307 }
 308
 309 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
 310 {
 311         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 312         struct drm_i915_private *dev_priv = dev->dev_private;
 313
 314         return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
 315 }
 316
 317 static void
 318 intel_dp_check_edp(struct intel_dp *intel_dp)
 319 {
 320         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 321         struct drm_i915_private *dev_priv = dev->dev_private;
 322
 323         if (!is_edp(intel_dp))
 324                 return;
 325         if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
 326                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 327                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 328                               I915_READ(PCH_PP_STATUS),
 329                               I915_READ(PCH_PP_CONTROL));
 330         }
 331 }
 332
 333 static int
 334 intel_dp_aux_ch(struct intel_dp *intel_dp,
 335                 uint8_t *send, int send_bytes,
 336                 uint8_t *recv, int recv_size)
 337 {
 338         uint32_t output_reg = intel_dp->output_reg;
 339         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 340         struct drm_i915_private *dev_priv = dev->dev_private;
 341         uint32_t ch_ctl = output_reg + 0x10;
 342         uint32_t ch_data = ch_ctl + 4;
 343         int i;
 344         int recv_bytes;
 345         uint32_t status;
 346         uint32_t aux_clock_divider;
 347         int try, precharge;
 348
 349         if (IS_HASWELL(dev)) {
 350                 switch (intel_dp->port) {
 351                 case PORT_A:
 352                         ch_ctl = DPA_AUX_CH_CTL;
 353                         ch_data = DPA_AUX_CH_DATA1;
 354                         break;
 355                 case PORT_B:
 356                         ch_ctl = PCH_DPB_AUX_CH_CTL;
 357                         ch_data = PCH_DPB_AUX_CH_DATA1;
 358                         break;
 359                 case PORT_C:
 360                         ch_ctl = PCH_DPC_AUX_CH_CTL;
 361                         ch_data = PCH_DPC_AUX_CH_DATA1;
 362                         break;
 363                 case PORT_D:
 364                         ch_ctl = PCH_DPD_AUX_CH_CTL;
 365                         ch_data = PCH_DPD_AUX_CH_DATA1;
 366                         break;
 367                 default:
 368                         BUG();
 369                 }
 370         }
 371
 372         intel_dp_check_edp(intel_dp);
 373         /* The clock divider is based off the hrawclk,
 374          * and would like to run at 2MHz. So, take the
 375          * hrawclk value and divide by 2 and use that
 376          *
 377          * Note that PCH attached eDP panels should use a 125MHz input
 378          * clock divider.
 379          */
 380         if (is_cpu_edp(intel_dp)) {
 381                 if (IS_HASWELL(dev))
 382                         aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
 383                 else if (IS_VALLEYVIEW(dev))
 384                         aux_clock_divider = 100;
 385                 else if (IS_GEN6(dev) || IS_GEN7(dev))
 386                         aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
 387                 else
 388                         aux_clock_divider = 225; /* eDP input clock at 450Mhz */
 389         } else if (HAS_PCH_SPLIT(dev))
 390                 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 391         else
 392                 aux_clock_divider = intel_hrawclk(dev) / 2;
 393
 394         if (IS_GEN6(dev))
 395                 precharge = 3;
 396         else
 397                 precharge = 5;
 398
 399         /* Try to wait for any previous AUX channel activity */
 400         for (try = 0; try < 3; try++) {
 401                 status = I915_READ(ch_ctl);
 402                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 403                         break;
 404                 msleep(1);
 405         }
 406
 407         if (try == 3) {
 408                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 409                      I915_READ(ch_ctl));
 410                 return -EBUSY;
 411         }
 412
 413         /* Must try at least 3 times according to DP spec */
 414         for (try = 0; try < 5; try++) {
 415                 /* Load the send data into the aux channel data registers */
 416                 for (i = 0; i < send_bytes; i += 4)
 417                         I915_WRITE(ch_data + i,
 418                                    pack_aux(send + i, send_bytes - i));
 419
 420                 /* Send the command and wait for it to complete */
 421                 I915_WRITE(ch_ctl,
 422                            DP_AUX_CH_CTL_SEND_BUSY |
 423                            DP_AUX_CH_CTL_TIME_OUT_400us |
 424                            (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 425                            (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 426                            (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 427                            DP_AUX_CH_CTL_DONE |
 428                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 429                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 430                 for (;;) {
 431                         status = I915_READ(ch_ctl);
 432                         if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 433                                 break;
 434                         udelay(100);
 435                 }
 436
 437                 /* Clear done status and any errors */
 438                 I915_WRITE(ch_ctl,
 439                            status |
 440                            DP_AUX_CH_CTL_DONE |
 441                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 442                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 443
 444                 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
 445                               DP_AUX_CH_CTL_RECEIVE_ERROR))
 446                         continue;
 447                 if (status & DP_AUX_CH_CTL_DONE)
 448                         break;
 449         }
 450
 451         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 452                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 453                 return -EBUSY;
 454         }
 455
 456         /* Check for timeout or receive error.
 457          * Timeouts occur when the sink is not connected
 458          */
 459         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 460                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 461                 return -EIO;
 462         }
 463
 464         /* Timeouts occur when the device isn't connected, so they're
 465          * "normal" -- don't fill the kernel log with these */
 466         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 467                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 468                 return -ETIMEDOUT;
 469         }
 470
 471         /* Unload any bytes sent back from the other side */
 472         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 473                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 474         if (recv_bytes > recv_size)
 475                 recv_bytes = recv_size;
 476
 477         for (i = 0; i < recv_bytes; i += 4)
 478                 unpack_aux(I915_READ(ch_data + i),
 479                            recv + i, recv_bytes - i);
 480
 481         return recv_bytes;
 482 }
 483
 484 /* Write data to the aux channel in native mode */
 485 static int
 486 intel_dp_aux_native_write(struct intel_dp *intel_dp,
 487                           uint16_t address, uint8_t *send, int send_bytes)
 488 {
 489         int ret;
 490         uint8_t msg[20];
 491         int msg_bytes;
 492         uint8_t ack;
 493
 494         intel_dp_check_edp(intel_dp);
 495         if (send_bytes > 16)
 496                 return -1;
 497         msg[0] = AUX_NATIVE_WRITE << 4;
 498         msg[1] = address >> 8;
 499         msg[2] = address & 0xff;
 500         msg[3] = send_bytes - 1;
 501         memcpy(&msg[4], send, send_bytes);
 502         msg_bytes = send_bytes + 4;
 503         for (;;) {
 504                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 505                 if (ret < 0)
 506                         return ret;
 507                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 508                         break;
 509                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 510                         udelay(100);
 511                 else
 512                         return -EIO;
 513         }
 514         return send_bytes;
 515 }
 516
 517 /* Write a single byte to the aux channel in native mode */
 518 static int
 519 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 520                             uint16_t address, uint8_t byte)
 521 {
 522         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 523 }
 524
 525 /* read bytes from a native aux channel */
 526 static int
 527 intel_dp_aux_native_read(struct intel_dp *intel_dp,
 528                          uint16_t address, uint8_t *recv, int recv_bytes)
 529 {
 530         uint8_t msg[4];
 531         int msg_bytes;
 532         uint8_t reply[20];
 533         int reply_bytes;
 534         uint8_t ack;
 535         int ret;
 536
 537         intel_dp_check_edp(intel_dp);
 538         msg[0] = AUX_NATIVE_READ << 4;
 539         msg[1] = address >> 8;
 540         msg[2] = address & 0xff;
 541         msg[3] = recv_bytes - 1;
 542
 543         msg_bytes = 4;
 544         reply_bytes = recv_bytes + 1;
 545
 546         for (;;) {
 547                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 548                                       reply, reply_bytes);
 549                 if (ret == 0)
 550                         return -EPROTO;
 551                 if (ret < 0)
 552                         return ret;
 553                 ack = reply[0];
 554                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 555                         memcpy(recv, reply + 1, ret - 1);
 556                         return ret - 1;
 557                 }
 558                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 559                         udelay(100);
 560                 else
 561                         return -EIO;
 562         }
 563 }
 564
 565 static int
 566 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 567                     uint8_t write_byte, uint8_t *read_byte)
 568 {
 569         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 570         struct intel_dp *intel_dp = container_of(adapter,
 571                                                 struct intel_dp,
 572                                                 adapter);
 573         uint16_t address = algo_data->address;
 574         uint8_t msg[5];
 575         uint8_t reply[2];
 576         unsigned retry;
 577         int msg_bytes;
 578         int reply_bytes;
 579         int ret;
 580
 581         intel_dp_check_edp(intel_dp);
 582         /* Set up the command byte */
 583         if (mode & MODE_I2C_READ)
 584                 msg[0] = AUX_I2C_READ << 4;
 585         else
 586                 msg[0] = AUX_I2C_WRITE << 4;
 587
 588         if (!(mode & MODE_I2C_STOP))
 589                 msg[0] |= AUX_I2C_MOT << 4;
 590
 591         msg[1] = address >> 8;
 592         msg[2] = address;
 593
 594         switch (mode) {
 595         case MODE_I2C_WRITE:
 596                 msg[3] = 0;
 597                 msg[4] = write_byte;
 598                 msg_bytes = 5;
 599                 reply_bytes = 1;
 600                 break;
 601         case MODE_I2C_READ:
 602                 msg[3] = 0;
 603                 msg_bytes = 4;
 604                 reply_bytes = 2;
 605                 break;
 606         default:
 607                 msg_bytes = 3;
 608                 reply_bytes = 1;
 609                 break;
 610         }
 611
 612         for (retry = 0; retry < 5; retry++) {
 613                 ret = intel_dp_aux_ch(intel_dp,
 614                                       msg, msg_bytes,
 615                                       reply, reply_bytes);
 616                 if (ret < 0) {
 617                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 618                         return ret;
 619                 }
 620
 621                 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
 622                 case AUX_NATIVE_REPLY_ACK:
 623                         /* I2C-over-AUX Reply field is only valid
 624                          * when paired with AUX ACK.
 625                          */
 626                         break;
 627                 case AUX_NATIVE_REPLY_NACK:
 628                         DRM_DEBUG_KMS("aux_ch native nack\n");
 629                         return -EREMOTEIO;
 630                 case AUX_NATIVE_REPLY_DEFER:
 631                         udelay(100);
 632                         continue;
 633                 default:
 634                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
 635                                   reply[0]);
 636                         return -EREMOTEIO;
 637                 }
 638
 639                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 640                 case AUX_I2C_REPLY_ACK:
 641                         if (mode == MODE_I2C_READ) {
 642                                 *read_byte = reply[1];
 643                         }
 644                         return reply_bytes - 1;
 645                 case AUX_I2C_REPLY_NACK:
 646                         DRM_DEBUG_KMS("aux_i2c nack\n");
 647                         return -EREMOTEIO;
 648                 case AUX_I2C_REPLY_DEFER:
 649                         DRM_DEBUG_KMS("aux_i2c defer\n");
 650                         udelay(100);
 651                         break;
 652                 default:
 653                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
 654                         return -EREMOTEIO;
 655                 }
 656         }
 657
 658         DRM_ERROR("too many retries, giving up\n");
 659         return -EREMOTEIO;
 660 }
 661
 662 static int
 663 intel_dp_i2c_init(struct intel_dp *intel_dp,
 664                   struct intel_connector *intel_connector, const char *name)
 665 {
 666         int     ret;
 667
 668         DRM_DEBUG_KMS("i2c_init %s\n", name);
 669         intel_dp->algo.running = false;
 670         intel_dp->algo.address = 0;
 671         intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
 672
 673         memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
 674         intel_dp->adapter.owner = THIS_MODULE;
 675         intel_dp->adapter.class = I2C_CLASS_DDC;
 676         strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
 677         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
 678         intel_dp->adapter.algo_data = &intel_dp->algo;
 679         intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
 680
 681         ironlake_edp_panel_vdd_on(intel_dp);
 682         ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
 683         ironlake_edp_panel_vdd_off(intel_dp, false);
 684         return ret;
 685 }
 686
 687 static bool
 688 intel_dp_mode_fixup(struct drm_encoder *encoder,
 689                     const struct drm_display_mode *mode,
 690                     struct drm_display_mode *adjusted_mode)
 691 {
 692         struct drm_device *dev = encoder->dev;
 693         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 694         struct intel_connector *intel_connector = intel_dp->attached_connector;
 695         int lane_count, clock;
 696         int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
 697         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
 698         int bpp, mode_rate;
 699         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 700
 701         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
 702                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
 703                                        adjusted_mode);
 704                 intel_pch_panel_fitting(dev,
 705                                         intel_connector->panel.fitting_mode,
 706                                         mode, adjusted_mode);
 707         }
 708
 709         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 710                 return false;
 711
 712         DRM_DEBUG_KMS("DP link computation with max lane count %i "
 713                       "max bw %02x pixel clock %iKHz\n",
 714                       max_lane_count, bws[max_clock], adjusted_mode->clock);
 715
 716         if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true))
 717                 return false;
 718
 719         bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
 720         mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
 721
 722         for (clock = 0; clock <= max_clock; clock++) {
 723                 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 724                         int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
 725
 726                         if (mode_rate <= link_avail) {
 727                                 intel_dp->link_bw = bws[clock];
 728                                 intel_dp->lane_count = lane_count;
 729                                 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
 730                                 DRM_DEBUG_KMS("DP link bw %02x lane "
 731                                                 "count %d clock %d bpp %d\n",
 732                                        intel_dp->link_bw, intel_dp->lane_count,
 733                                        adjusted_mode->clock, bpp);
 734                                 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
 735                                               mode_rate, link_avail);
 736                                 return true;
 737                         }
 738                 }
 739         }
 740
 741         return false;
 742 }
 743
 744 struct intel_dp_m_n {
 745         uint32_t        tu;
 746         uint32_t        gmch_m;
 747         uint32_t        gmch_n;
 748         uint32_t        link_m;
 749         uint32_t        link_n;
 750 };
 751
 752 static void
 753 intel_reduce_ratio(uint32_t *num, uint32_t *den)
 754 {
 755         while (*num > 0xffffff || *den > 0xffffff) {
 756                 *num >>= 1;
 757                 *den >>= 1;
 758         }
 759 }
 760
 761 static void
 762 intel_dp_compute_m_n(int bpp,
 763                      int nlanes,
 764                      int pixel_clock,
 765                      int link_clock,
 766                      struct intel_dp_m_n *m_n)
 767 {
 768         m_n->tu = 64;
 769         m_n->gmch_m = (pixel_clock * bpp) >> 3;
 770         m_n->gmch_n = link_clock * nlanes;
 771         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
 772         m_n->link_m = pixel_clock;
 773         m_n->link_n = link_clock;
 774         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
 775 }
 776
 777 void
 778 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 779                  struct drm_display_mode *adjusted_mode)
 780 {
 781         struct drm_device *dev = crtc->dev;
 782         struct intel_encoder *intel_encoder;
 783         struct intel_dp *intel_dp;
 784         struct drm_i915_private *dev_priv = dev->dev_private;
 785         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 786         int lane_count = 4;
 787         struct intel_dp_m_n m_n;
 788         int pipe = intel_crtc->pipe;
 789         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
 790
 791         /*
 792          * Find the lane count in the intel_encoder private
 793          */
 794         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
 795                 intel_dp = enc_to_intel_dp(&intel_encoder->base);
 796
 797                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
 798                     intel_encoder->type == INTEL_OUTPUT_EDP)
 799                 {
 800                         lane_count = intel_dp->lane_count;
 801                         break;
 802                 }
 803         }
 804
 805         /*
 806          * Compute the GMCH and Link ratios. The '3' here is
 807          * the number of bytes_per_pixel post-LUT, which we always
 808          * set up for 8-bits of R/G/B, or 3 bytes total.
 809          */
 810         intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
 811                              mode->clock, adjusted_mode->clock, &m_n);
 812
 813         if (IS_HASWELL(dev)) {
 814                 I915_WRITE(PIPE_DATA_M1(cpu_transcoder),
 815                            TU_SIZE(m_n.tu) | m_n.gmch_m);
 816                 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
 817                 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
 818                 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
 819         } else if (HAS_PCH_SPLIT(dev)) {
 820                 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
 821                 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
 822                 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
 823                 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
 824         } else if (IS_VALLEYVIEW(dev)) {
 825                 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
 826                 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
 827                 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
 828                 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
 829         } else {
 830                 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
 831                            TU_SIZE(m_n.tu) | m_n.gmch_m);
 832                 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
 833                 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
 834                 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
 835         }
 836 }
 837
 838 void intel_dp_init_link_config(struct intel_dp *intel_dp)
 839 {
 840         memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 841         intel_dp->link_configuration[0] = intel_dp->link_bw;
 842         intel_dp->link_configuration[1] = intel_dp->lane_count;
 843         intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
 844         /*
 845          * Check for DPCD version > 1.1 and enhanced framing support
 846          */
 847         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
 848             (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
 849                 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 850         }
 851 }
 852
 853 static void
 854 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 855                   struct drm_display_mode *adjusted_mode)
 856 {
 857         struct drm_device *dev = encoder->dev;
 858         struct drm_i915_private *dev_priv = dev->dev_private;
 859         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 860         struct drm_crtc *crtc = encoder->crtc;
 861         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 862
 863         /*
 864          * There are four kinds of DP registers:
 865          *
 866          *      IBX PCH
 867          *      SNB CPU
 868          *      IVB CPU
 869          *      CPT PCH
 870          *
 871          * IBX PCH and CPU are the same for almost everything,
 872          * except that the CPU DP PLL is configured in this
 873          * register
 874          *
 875          * CPT PCH is quite different, having many bits moved
 876          * to the TRANS_DP_CTL register instead. That
 877          * configuration happens (oddly) in ironlake_pch_enable
 878          */
 879
 880         /* Preserve the BIOS-computed detected bit. This is
 881          * supposed to be read-only.
 882          */
 883         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 884
 885         /* Handle DP bits in common between all three register formats */
 886         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 887
 888         switch (intel_dp->lane_count) {
 889         case 1:
 890                 intel_dp->DP |= DP_PORT_WIDTH_1;
 891                 break;
 892         case 2:
 893                 intel_dp->DP |= DP_PORT_WIDTH_2;
 894                 break;
 895         case 4:
 896                 intel_dp->DP |= DP_PORT_WIDTH_4;
 897                 break;
 898         }
 899         if (intel_dp->has_audio) {
 900                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
 901                                  pipe_name(intel_crtc->pipe));
 902                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 903                 intel_write_eld(encoder, adjusted_mode);
 904         }
 905
 906         intel_dp_init_link_config(intel_dp);
 907
 908         /* Split out the IBX/CPU vs CPT settings */
 909
 910         if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
 911                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 912                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 913                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 914                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 915                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 916
 917                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 918                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 919
 920                 intel_dp->DP |= intel_crtc->pipe << 29;
 921
 922                 /* don't miss out required setting for eDP */
 923                 if (adjusted_mode->clock < 200000)
 924                         intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 925                 else
 926                         intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 927         } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
 928                 intel_dp->DP |= intel_dp->color_range;
 929
 930                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 931                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 932                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 933                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 934                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 935
 936                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 937                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 938
 939                 if (intel_crtc->pipe == 1)
 940                         intel_dp->DP |= DP_PIPEB_SELECT;
 941
 942                 if (is_cpu_edp(intel_dp)) {
 943                         /* don't miss out required setting for eDP */
 944                         if (adjusted_mode->clock < 200000)
 945                                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 946                         else
 947                                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 948                 }
 949         } else {
 950                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 951         }
 952 }
 953
 954 #define IDLE_ON_MASK            (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 955 #define IDLE_ON_VALUE           (PP_ON | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
 956
 957 #define IDLE_OFF_MASK           (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 958 #define IDLE_OFF_VALUE          (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 959
 960 #define IDLE_CYCLE_MASK         (PP_ON | 0        | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
 961 #define IDLE_CYCLE_VALUE        (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 962
 963 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
 964                                        u32 mask,
 965                                        u32 value)
 966 {
 967         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 968         struct drm_i915_private *dev_priv = dev->dev_private;
 969
 970         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
 971                       mask, value,
 972                       I915_READ(PCH_PP_STATUS),
 973                       I915_READ(PCH_PP_CONTROL));
 974
 975         if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
 976                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
 977                           I915_READ(PCH_PP_STATUS),
 978                           I915_READ(PCH_PP_CONTROL));
 979         }
 980 }
 981
 982 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
 983 {
 984         DRM_DEBUG_KMS("Wait for panel power on\n");
 985         ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
 986 }
 987
 988 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
 989 {
 990         DRM_DEBUG_KMS("Wait for panel power off time\n");
 991         ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
 992 }
 993
 994 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
 995 {
 996         DRM_DEBUG_KMS("Wait for panel power cycle\n");
 997         ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
 998 }
 999
1000
1001 /* Read the current pp_control value, unlocking the register if it
1002  * is locked
1003  */
1004
1005 static  u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
1006 {
1007         u32     control = I915_READ(PCH_PP_CONTROL);
1008
1009         control &= ~PANEL_UNLOCK_MASK;
1010         control |= PANEL_UNLOCK_REGS;
1011         return control;
1012 }
1013
1014 void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1015 {
1016         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1017         struct drm_i915_private *dev_priv = dev->dev_private;
1018         u32 pp;
1019
1020         if (!is_edp(intel_dp))
1021                 return;
1022         DRM_DEBUG_KMS("Turn eDP VDD on\n");
1023
1024         WARN(intel_dp->want_panel_vdd,
1025              "eDP VDD already requested on\n");
1026
1027         intel_dp->want_panel_vdd = true;
1028
1029         if (ironlake_edp_have_panel_vdd(intel_dp)) {
1030                 DRM_DEBUG_KMS("eDP VDD already on\n");
1031                 return;
1032         }
1033
1034         if (!ironlake_edp_have_panel_power(intel_dp))
1035                 ironlake_wait_panel_power_cycle(intel_dp);
1036
1037         pp = ironlake_get_pp_control(dev_priv);
1038         pp |= EDP_FORCE_VDD;
1039         I915_WRITE(PCH_PP_CONTROL, pp);
1040         POSTING_READ(PCH_PP_CONTROL);
1041         DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1042                       I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1043
1044         /*
1045          * If the panel wasn't on, delay before accessing aux channel
1046          */
1047         if (!ironlake_edp_have_panel_power(intel_dp)) {
1048                 DRM_DEBUG_KMS("eDP was not running\n");
1049                 msleep(intel_dp->panel_power_up_delay);
1050         }
1051 }
1052
1053 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1054 {
1055         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1056         struct drm_i915_private *dev_priv = dev->dev_private;
1057         u32 pp;
1058
1059         if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1060                 pp = ironlake_get_pp_control(dev_priv);
1061                 pp &= ~EDP_FORCE_VDD;
1062                 I915_WRITE(PCH_PP_CONTROL, pp);
1063                 POSTING_READ(PCH_PP_CONTROL);
1064
1065                 /* Make sure sequencer is idle before allowing subsequent activity */
1066                 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1067                               I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1068
1069                 msleep(intel_dp->panel_power_down_delay);
1070         }
1071 }
1072
1073 static void ironlake_panel_vdd_work(struct work_struct *__work)
1074 {
1075         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1076                                                  struct intel_dp, panel_vdd_work);
1077         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1078
1079         mutex_lock(&dev->mode_config.mutex);
1080         ironlake_panel_vdd_off_sync(intel_dp);
1081         mutex_unlock(&dev->mode_config.mutex);
1082 }
1083
1084 void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1085 {
1086         if (!is_edp(intel_dp))
1087                 return;
1088
1089         DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1090         WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1091
1092         intel_dp->want_panel_vdd = false;
1093
1094         if (sync) {
1095                 ironlake_panel_vdd_off_sync(intel_dp);
1096         } else {
1097                 /*
1098                  * Queue the timer to fire a long
1099                  * time from now (relative to the power down delay)
1100                  * to keep the panel power up across a sequence of operations
1101                  */
1102                 schedule_delayed_work(&intel_dp->panel_vdd_work,
1103                                       msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1104         }
1105 }
1106
1107 void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1108 {
1109         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1110         struct drm_i915_private *dev_priv = dev->dev_private;
1111         u32 pp;
1112
1113         if (!is_edp(intel_dp))
1114                 return;
1115
1116         DRM_DEBUG_KMS("Turn eDP power on\n");
1117
1118         if (ironlake_edp_have_panel_power(intel_dp)) {
1119                 DRM_DEBUG_KMS("eDP power already on\n");
1120                 return;
1121         }
1122
1123         ironlake_wait_panel_power_cycle(intel_dp);
1124
1125         pp = ironlake_get_pp_control(dev_priv);
1126         if (IS_GEN5(dev)) {
1127                 /* ILK workaround: disable reset around power sequence */
1128                 pp &= ~PANEL_POWER_RESET;
1129                 I915_WRITE(PCH_PP_CONTROL, pp);
1130                 POSTING_READ(PCH_PP_CONTROL);
1131         }
1132
1133         pp |= POWER_TARGET_ON;
1134         if (!IS_GEN5(dev))
1135                 pp |= PANEL_POWER_RESET;
1136
1137         I915_WRITE(PCH_PP_CONTROL, pp);
1138         POSTING_READ(PCH_PP_CONTROL);
1139
1140         ironlake_wait_panel_on(intel_dp);
1141
1142         if (IS_GEN5(dev)) {
1143                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1144                 I915_WRITE(PCH_PP_CONTROL, pp);
1145                 POSTING_READ(PCH_PP_CONTROL);
1146         }
1147 }
1148
1149 void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1150 {
1151         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1152         struct drm_i915_private *dev_priv = dev->dev_private;
1153         u32 pp;
1154
1155         if (!is_edp(intel_dp))
1156                 return;
1157
1158         DRM_DEBUG_KMS("Turn eDP power off\n");
1159
1160         WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1161
1162         pp = ironlake_get_pp_control(dev_priv);
1163         /* We need to switch off panel power _and_ force vdd, for otherwise some
1164          * panels get very unhappy and cease to work. */
1165         pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1166         I915_WRITE(PCH_PP_CONTROL, pp);
1167         POSTING_READ(PCH_PP_CONTROL);
1168
1169         intel_dp->want_panel_vdd = false;
1170
1171         ironlake_wait_panel_off(intel_dp);
1172 }
1173
1174 void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1175 {
1176         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1177         struct drm_device *dev = intel_dig_port->base.base.dev;
1178         struct drm_i915_private *dev_priv = dev->dev_private;
1179         int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
1180         u32 pp;
1181
1182         if (!is_edp(intel_dp))
1183                 return;
1184
1185         DRM_DEBUG_KMS("\n");
1186         /*
1187          * If we enable the backlight right away following a panel power
1188          * on, we may see slight flicker as the panel syncs with the eDP
1189          * link.  So delay a bit to make sure the image is solid before
1190          * allowing it to appear.
1191          */
1192         msleep(intel_dp->backlight_on_delay);
1193         pp = ironlake_get_pp_control(dev_priv);
1194         pp |= EDP_BLC_ENABLE;
1195         I915_WRITE(PCH_PP_CONTROL, pp);
1196         POSTING_READ(PCH_PP_CONTROL);
1197
1198         intel_panel_enable_backlight(dev, pipe);
1199 }
1200
1201 void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1202 {
1203         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1204         struct drm_i915_private *dev_priv = dev->dev_private;
1205         u32 pp;
1206
1207         if (!is_edp(intel_dp))
1208                 return;
1209
1210         intel_panel_disable_backlight(dev);
1211
1212         DRM_DEBUG_KMS("\n");
1213         pp = ironlake_get_pp_control(dev_priv);
1214         pp &= ~EDP_BLC_ENABLE;
1215         I915_WRITE(PCH_PP_CONTROL, pp);
1216         POSTING_READ(PCH_PP_CONTROL);
1217         msleep(intel_dp->backlight_off_delay);
1218 }
1219
1220 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1221 {
1222         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1223         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1224         struct drm_device *dev = crtc->dev;
1225         struct drm_i915_private *dev_priv = dev->dev_private;
1226         u32 dpa_ctl;
1227
1228         assert_pipe_disabled(dev_priv,
1229                              to_intel_crtc(crtc)->pipe);
1230
1231         DRM_DEBUG_KMS("\n");
1232         dpa_ctl = I915_READ(DP_A);
1233         WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1234         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1235
1236         /* We don't adjust intel_dp->DP while tearing down the link, to
1237          * facilitate link retraining (e.g. after hotplug). Hence clear all
1238          * enable bits here to ensure that we don't enable too much. */
1239         intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1240         intel_dp->DP |= DP_PLL_ENABLE;
1241         I915_WRITE(DP_A, intel_dp->DP);
1242         POSTING_READ(DP_A);
1243         udelay(200);
1244 }
1245
1246 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1247 {
1248         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1249         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1250         struct drm_device *dev = crtc->dev;
1251         struct drm_i915_private *dev_priv = dev->dev_private;
1252         u32 dpa_ctl;
1253
1254         assert_pipe_disabled(dev_priv,
1255                              to_intel_crtc(crtc)->pipe);
1256
1257         dpa_ctl = I915_READ(DP_A);
1258         WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1259              "dp pll off, should be on\n");
1260         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1261
1262         /* We can't rely on the value tracked for the DP register in
1263          * intel_dp->DP because link_down must not change that (otherwise link
1264          * re-training will fail. */
1265         dpa_ctl &= ~DP_PLL_ENABLE;
1266         I915_WRITE(DP_A, dpa_ctl);
1267         POSTING_READ(DP_A);
1268         udelay(200);
1269 }
1270
1271 /* If the sink supports it, try to set the power state appropriately */
1272 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1273 {
1274         int ret, i;
1275
1276         /* Should have a valid DPCD by this point */
1277         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1278                 return;
1279
1280         if (mode != DRM_MODE_DPMS_ON) {
1281                 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1282                                                   DP_SET_POWER_D3);
1283                 if (ret != 1)
1284                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
1285         } else {
1286                 /*
1287                  * When turning on, we need to retry for 1ms to give the sink
1288                  * time to wake up.
1289                  */
1290                 for (i = 0; i < 3; i++) {
1291                         ret = intel_dp_aux_native_write_1(intel_dp,
1292                                                           DP_SET_POWER,
1293                                                           DP_SET_POWER_D0);
1294                         if (ret == 1)
1295                                 break;
1296                         msleep(1);
1297                 }
1298         }
1299 }
1300
1301 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1302                                   enum pipe *pipe)
1303 {
1304         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1305         struct drm_device *dev = encoder->base.dev;
1306         struct drm_i915_private *dev_priv = dev->dev_private;
1307         u32 tmp = I915_READ(intel_dp->output_reg);
1308
1309         if (!(tmp & DP_PORT_EN))
1310                 return false;
1311
1312         if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
1313                 *pipe = PORT_TO_PIPE_CPT(tmp);
1314         } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1315                 *pipe = PORT_TO_PIPE(tmp);
1316         } else {
1317                 u32 trans_sel;
1318                 u32 trans_dp;
1319                 int i;
1320
1321                 switch (intel_dp->output_reg) {
1322                 case PCH_DP_B:
1323                         trans_sel = TRANS_DP_PORT_SEL_B;
1324                         break;
1325                 case PCH_DP_C:
1326                         trans_sel = TRANS_DP_PORT_SEL_C;
1327                         break;
1328                 case PCH_DP_D:
1329                         trans_sel = TRANS_DP_PORT_SEL_D;
1330                         break;
1331                 default:
1332                         return true;
1333                 }
1334
1335                 for_each_pipe(i) {
1336                         trans_dp = I915_READ(TRANS_DP_CTL(i));
1337                         if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1338                                 *pipe = i;
1339                                 return true;
1340                         }
1341                 }
1342
1343                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1344                               intel_dp->output_reg);
1345         }
1346
1347         return true;
1348 }
1349
1350 static void intel_disable_dp(struct intel_encoder *encoder)
1351 {
1352         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1353
1354         /* Make sure the panel is off before trying to change the mode. But also
1355          * ensure that we have vdd while we switch off the panel. */
1356         ironlake_edp_panel_vdd_on(intel_dp);
1357         ironlake_edp_backlight_off(intel_dp);
1358         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1359         ironlake_edp_panel_off(intel_dp);
1360
1361         /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1362         if (!is_cpu_edp(intel_dp))
1363                 intel_dp_link_down(intel_dp);
1364 }
1365
1366 static void intel_post_disable_dp(struct intel_encoder *encoder)
1367 {
1368         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1369
1370         if (is_cpu_edp(intel_dp)) {
1371                 intel_dp_link_down(intel_dp);
1372                 ironlake_edp_pll_off(intel_dp);
1373         }
1374 }
1375
1376 static void intel_enable_dp(struct intel_encoder *encoder)
1377 {
1378         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1379         struct drm_device *dev = encoder->base.dev;
1380         struct drm_i915_private *dev_priv = dev->dev_private;
1381         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1382
1383         if (WARN_ON(dp_reg & DP_PORT_EN))
1384                 return;
1385
1386         ironlake_edp_panel_vdd_on(intel_dp);
1387         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1388         intel_dp_start_link_train(intel_dp);
1389         ironlake_edp_panel_on(intel_dp);
1390         ironlake_edp_panel_vdd_off(intel_dp, true);
1391         intel_dp_complete_link_train(intel_dp);
1392         ironlake_edp_backlight_on(intel_dp);
1393 }
1394
1395 static void intel_pre_enable_dp(struct intel_encoder *encoder)
1396 {
1397         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1398
1399         if (is_cpu_edp(intel_dp))
1400                 ironlake_edp_pll_on(intel_dp);
1401 }
1402
1403 /*
1404  * Native read with retry for link status and receiver capability reads for
1405  * cases where the sink may still be asleep.
1406  */
1407 static bool
1408 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1409                                uint8_t *recv, int recv_bytes)
1410 {
1411         int ret, i;
1412
1413         /*
1414          * Sinks are *supposed* to come up within 1ms from an off state,
1415          * but we're also supposed to retry 3 times per the spec.
1416          */
1417         for (i = 0; i < 3; i++) {
1418                 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1419                                                recv_bytes);
1420                 if (ret == recv_bytes)
1421                         return true;
1422                 msleep(1);
1423         }
1424
1425         return false;
1426 }
1427
1428 /*
1429  * Fetch AUX CH registers 0x202 - 0x207 which contain
1430  * link status information
1431  */
1432 static bool
1433 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1434 {
1435         return intel_dp_aux_native_read_retry(intel_dp,
1436                                               DP_LANE0_1_STATUS,
1437                                               link_status,
1438                                               DP_LINK_STATUS_SIZE);
1439 }
1440
1441 #if 0
1442 static char     *voltage_names[] = {
1443         "0.4V", "0.6V", "0.8V", "1.2V"
1444 };
1445 static char     *pre_emph_names[] = {
1446         "0dB", "3.5dB", "6dB", "9.5dB"
1447 };
1448 static char     *link_train_names[] = {
1449         "pattern 1", "pattern 2", "idle", "off"
1450 };
1451 #endif
1452
1453 /*
1454  * These are source-specific values; current Intel hardware supports
1455  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1456  */
1457
1458 static uint8_t
1459 intel_dp_voltage_max(struct intel_dp *intel_dp)
1460 {
1461         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1462
1463         if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1464                 return DP_TRAIN_VOLTAGE_SWING_800;
1465         else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1466                 return DP_TRAIN_VOLTAGE_SWING_1200;
1467         else
1468                 return DP_TRAIN_VOLTAGE_SWING_800;
1469 }
1470
1471 static uint8_t
1472 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1473 {
1474         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1475
1476         if (IS_HASWELL(dev)) {
1477                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1478                 case DP_TRAIN_VOLTAGE_SWING_400:
1479                         return DP_TRAIN_PRE_EMPHASIS_9_5;
1480                 case DP_TRAIN_VOLTAGE_SWING_600:
1481                         return DP_TRAIN_PRE_EMPHASIS_6;
1482                 case DP_TRAIN_VOLTAGE_SWING_800:
1483                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1484                 case DP_TRAIN_VOLTAGE_SWING_1200:
1485                 default:
1486                         return DP_TRAIN_PRE_EMPHASIS_0;
1487                 }
1488         } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1489                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1490                 case DP_TRAIN_VOLTAGE_SWING_400:
1491                         return DP_TRAIN_PRE_EMPHASIS_6;
1492                 case DP_TRAIN_VOLTAGE_SWING_600:
1493                 case DP_TRAIN_VOLTAGE_SWING_800:
1494                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1495                 default:
1496                         return DP_TRAIN_PRE_EMPHASIS_0;
1497                 }
1498         } else {
1499                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1500                 case DP_TRAIN_VOLTAGE_SWING_400:
1501                         return DP_TRAIN_PRE_EMPHASIS_6;
1502                 case DP_TRAIN_VOLTAGE_SWING_600:
1503                         return DP_TRAIN_PRE_EMPHASIS_6;
1504                 case DP_TRAIN_VOLTAGE_SWING_800:
1505                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1506                 case DP_TRAIN_VOLTAGE_SWING_1200:
1507                 default:
1508                         return DP_TRAIN_PRE_EMPHASIS_0;
1509                 }
1510         }
1511 }
1512
1513 static void
1514 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1515 {
1516         uint8_t v = 0;
1517         uint8_t p = 0;
1518         int lane;
1519         uint8_t voltage_max;
1520         uint8_t preemph_max;
1521
1522         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1523                 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1524                 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
1525
1526                 if (this_v > v)
1527                         v = this_v;
1528                 if (this_p > p)
1529                         p = this_p;
1530         }
1531
1532         voltage_max = intel_dp_voltage_max(intel_dp);
1533         if (v >= voltage_max)
1534                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1535
1536         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1537         if (p >= preemph_max)
1538                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1539
1540         for (lane = 0; lane < 4; lane++)
1541                 intel_dp->train_set[lane] = v | p;
1542 }
1543
1544 static uint32_t
1545 intel_dp_signal_levels(uint8_t train_set)
1546 {
1547         uint32_t        signal_levels = 0;
1548
1549         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1550         case DP_TRAIN_VOLTAGE_SWING_400:
1551         default:
1552                 signal_levels |= DP_VOLTAGE_0_4;
1553                 break;
1554         case DP_TRAIN_VOLTAGE_SWING_600:
1555                 signal_levels |= DP_VOLTAGE_0_6;
1556                 break;
1557         case DP_TRAIN_VOLTAGE_SWING_800:
1558                 signal_levels |= DP_VOLTAGE_0_8;
1559                 break;
1560         case DP_TRAIN_VOLTAGE_SWING_1200:
1561                 signal_levels |= DP_VOLTAGE_1_2;
1562                 break;
1563         }
1564         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1565         case DP_TRAIN_PRE_EMPHASIS_0:
1566         default:
1567                 signal_levels |= DP_PRE_EMPHASIS_0;
1568                 break;
1569         case DP_TRAIN_PRE_EMPHASIS_3_5:
1570                 signal_levels |= DP_PRE_EMPHASIS_3_5;
1571                 break;
1572         case DP_TRAIN_PRE_EMPHASIS_6:
1573                 signal_levels |= DP_PRE_EMPHASIS_6;
1574                 break;
1575         case DP_TRAIN_PRE_EMPHASIS_9_5:
1576                 signal_levels |= DP_PRE_EMPHASIS_9_5;
1577                 break;
1578         }
1579         return signal_levels;
1580 }
1581
1582 /* Gen6's DP voltage swing and pre-emphasis control */
1583 static uint32_t
1584 intel_gen6_edp_signal_levels(uint8_t train_set)
1585 {
1586         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1587                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1588         switch (signal_levels) {
1589         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1590         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1591                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1592         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1593                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1594         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1595         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1596                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1597         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1598         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1599                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1600         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1601         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1602                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1603         default:
1604                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1605                               "0x%x\n", signal_levels);
1606                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1607         }
1608 }
1609
1610 /* Gen7's DP voltage swing and pre-emphasis control */
1611 static uint32_t
1612 intel_gen7_edp_signal_levels(uint8_t train_set)
1613 {
1614         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1615                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1616         switch (signal_levels) {
1617         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1618                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1619         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1620                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1621         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1622                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1623
1624         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1625                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1626         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1627                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1628
1629         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1630                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1631         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1632                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1633
1634         default:
1635                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1636                               "0x%x\n", signal_levels);
1637                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1638         }
1639 }
1640
1641 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1642 static uint32_t
1643 intel_dp_signal_levels_hsw(uint8_t train_set)
1644 {
1645         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1646                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1647         switch (signal_levels) {
1648         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1649                 return DDI_BUF_EMP_400MV_0DB_HSW;
1650         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1651                 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1652         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1653                 return DDI_BUF_EMP_400MV_6DB_HSW;
1654         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1655                 return DDI_BUF_EMP_400MV_9_5DB_HSW;
1656
1657         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1658                 return DDI_BUF_EMP_600MV_0DB_HSW;
1659         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1660                 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1661         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1662                 return DDI_BUF_EMP_600MV_6DB_HSW;
1663
1664         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1665                 return DDI_BUF_EMP_800MV_0DB_HSW;
1666         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1667                 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1668         default:
1669                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1670                               "0x%x\n", signal_levels);
1671                 return DDI_BUF_EMP_400MV_0DB_HSW;
1672         }
1673 }
1674
1675 static bool
1676 intel_dp_set_link_train(struct intel_dp *intel_dp,
1677                         uint32_t dp_reg_value,
1678                         uint8_t dp_train_pat)
1679 {
1680         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1681         struct drm_i915_private *dev_priv = dev->dev_private;
1682         int ret;
1683         uint32_t temp;
1684
1685         if (IS_HASWELL(dev)) {
1686                 temp = I915_READ(DP_TP_CTL(intel_dp->port));
1687
1688                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1689                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1690                 else
1691                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1692
1693                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1694                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1695                 case DP_TRAINING_PATTERN_DISABLE:
1696                         temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
1697                         I915_WRITE(DP_TP_CTL(intel_dp->port), temp);
1698
1699                         if (wait_for((I915_READ(DP_TP_STATUS(intel_dp->port)) &
1700                                       DP_TP_STATUS_IDLE_DONE), 1))
1701                                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1702
1703                         temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1704                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1705
1706                         break;
1707                 case DP_TRAINING_PATTERN_1:
1708                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1709                         break;
1710                 case DP_TRAINING_PATTERN_2:
1711                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1712                         break;
1713                 case DP_TRAINING_PATTERN_3:
1714                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1715                         break;
1716                 }
1717                 I915_WRITE(DP_TP_CTL(intel_dp->port), temp);
1718
1719         } else if (HAS_PCH_CPT(dev) &&
1720                    (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1721                 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1722
1723                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1724                 case DP_TRAINING_PATTERN_DISABLE:
1725                         dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1726                         break;
1727                 case DP_TRAINING_PATTERN_1:
1728                         dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1729                         break;
1730                 case DP_TRAINING_PATTERN_2:
1731                         dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1732                         break;
1733                 case DP_TRAINING_PATTERN_3:
1734                         DRM_ERROR("DP training pattern 3 not supported\n");
1735                         dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1736                         break;
1737                 }
1738
1739         } else {
1740                 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1741
1742                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1743                 case DP_TRAINING_PATTERN_DISABLE:
1744                         dp_reg_value |= DP_LINK_TRAIN_OFF;
1745                         break;
1746                 case DP_TRAINING_PATTERN_1:
1747                         dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1748                         break;
1749                 case DP_TRAINING_PATTERN_2:
1750                         dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1751                         break;
1752                 case DP_TRAINING_PATTERN_3:
1753                         DRM_ERROR("DP training pattern 3 not supported\n");
1754                         dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1755                         break;
1756                 }
1757         }
1758
1759         I915_WRITE(intel_dp->output_reg, dp_reg_value);
1760         POSTING_READ(intel_dp->output_reg);
1761
1762         intel_dp_aux_native_write_1(intel_dp,
1763                                     DP_TRAINING_PATTERN_SET,
1764                                     dp_train_pat);
1765
1766         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1767             DP_TRAINING_PATTERN_DISABLE) {
1768                 ret = intel_dp_aux_native_write(intel_dp,
1769                                                 DP_TRAINING_LANE0_SET,
1770                                                 intel_dp->train_set,
1771                                                 intel_dp->lane_count);
1772                 if (ret != intel_dp->lane_count)
1773                         return false;
1774         }
1775
1776         return true;
1777 }
1778
1779 /* Enable corresponding port and start training pattern 1 */
1780 void
1781 intel_dp_start_link_train(struct intel_dp *intel_dp)
1782 {
1783         struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
1784         struct drm_device *dev = encoder->dev;
1785         int i;
1786         uint8_t voltage;
1787         bool clock_recovery = false;
1788         int voltage_tries, loop_tries;
1789         uint32_t DP = intel_dp->DP;
1790
1791         if (IS_HASWELL(dev))
1792                 intel_ddi_prepare_link_retrain(encoder);
1793
1794         /* Write the link configuration data */
1795         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1796                                   intel_dp->link_configuration,
1797                                   DP_LINK_CONFIGURATION_SIZE);
1798
1799         DP |= DP_PORT_EN;
1800
1801         memset(intel_dp->train_set, 0, 4);
1802         voltage = 0xff;
1803         voltage_tries = 0;
1804         loop_tries = 0;
1805         clock_recovery = false;
1806         for (;;) {
1807                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1808                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
1809                 uint32_t    signal_levels;
1810
1811                 if (IS_HASWELL(dev)) {
1812                         signal_levels = intel_dp_signal_levels_hsw(
1813                                                         intel_dp->train_set[0]);
1814                         DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
1815                 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1816                         signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1817                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1818                 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1819                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1820                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1821                 } else {
1822                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1823                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1824                 }
1825                 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n",
1826                               signal_levels);
1827
1828                 /* Set training pattern 1 */
1829                 if (!intel_dp_set_link_train(intel_dp, DP,
1830                                              DP_TRAINING_PATTERN_1 |
1831                                              DP_LINK_SCRAMBLING_DISABLE))
1832                         break;
1833
1834                 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
1835                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1836                         DRM_ERROR("failed to get link status\n");
1837                         break;
1838                 }
1839
1840                 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1841                         DRM_DEBUG_KMS("clock recovery OK\n");
1842                         clock_recovery = true;
1843                         break;
1844                 }
1845
1846                 /* Check to see if we've tried the max voltage */
1847                 for (i = 0; i < intel_dp->lane_count; i++)
1848                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1849                                 break;
1850                 if (i == intel_dp->lane_count && voltage_tries == 5) {
1851                         if (++loop_tries == 5) {
1852                                 DRM_DEBUG_KMS("too many full retries, give up\n");
1853                                 break;
1854                         }
1855                         memset(intel_dp->train_set, 0, 4);
1856                         voltage_tries = 0;
1857                         continue;
1858                 }
1859
1860                 /* Check to see if we've tried the same voltage 5 times */
1861                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) {
1862                         voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1863                         voltage_tries = 0;
1864                 } else
1865                         ++voltage_tries;
1866
1867                 /* Compute new intel_dp->train_set as requested by target */
1868                 intel_get_adjust_train(intel_dp, link_status);
1869         }
1870
1871         intel_dp->DP = DP;
1872 }
1873
1874 void
1875 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1876 {
1877         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1878         bool channel_eq = false;
1879         int tries, cr_tries;
1880         uint32_t DP = intel_dp->DP;
1881
1882         /* channel equalization */
1883         tries = 0;
1884         cr_tries = 0;
1885         channel_eq = false;
1886         for (;;) {
1887                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1888                 uint32_t    signal_levels;
1889                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
1890
1891                 if (cr_tries > 5) {
1892                         DRM_ERROR("failed to train DP, aborting\n");
1893                         intel_dp_link_down(intel_dp);
1894                         break;
1895                 }
1896
1897                 if (IS_HASWELL(dev)) {
1898                         signal_levels = intel_dp_signal_levels_hsw(intel_dp->train_set[0]);
1899                         DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
1900                 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1901                         signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1902                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1903                 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1904                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1905                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1906                 } else {
1907                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1908                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1909                 }
1910
1911                 /* channel eq pattern */
1912                 if (!intel_dp_set_link_train(intel_dp, DP,
1913                                              DP_TRAINING_PATTERN_2 |
1914                                              DP_LINK_SCRAMBLING_DISABLE))
1915                         break;
1916
1917                 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
1918                 if (!intel_dp_get_link_status(intel_dp, link_status))
1919                         break;
1920
1921                 /* Make sure clock is still ok */
1922                 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1923                         intel_dp_start_link_train(intel_dp);
1924                         cr_tries++;
1925                         continue;
1926                 }
1927
1928                 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
1929                         channel_eq = true;
1930                         break;
1931                 }
1932
1933                 /* Try 5 times, then try clock recovery if that fails */
1934                 if (tries > 5) {
1935                         intel_dp_link_down(intel_dp);
1936                         intel_dp_start_link_train(intel_dp);
1937                         tries = 0;
1938                         cr_tries++;
1939                         continue;
1940                 }
1941
1942                 /* Compute new intel_dp->train_set as requested by target */
1943                 intel_get_adjust_train(intel_dp, link_status);
1944                 ++tries;
1945         }
1946
1947         if (channel_eq)
1948                 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
1949
1950         intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
1951 }
1952
1953 static void
1954 intel_dp_link_down(struct intel_dp *intel_dp)
1955 {
1956         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1957         struct drm_device *dev = intel_dig_port->base.base.dev;
1958         struct drm_i915_private *dev_priv = dev->dev_private;
1959         uint32_t DP = intel_dp->DP;
1960
1961         /*
1962          * DDI code has a strict mode set sequence and we should try to respect
1963          * it, otherwise we might hang the machine in many different ways. So we
1964          * really should be disabling the port only on a complete crtc_disable
1965          * sequence. This function is just called under two conditions on DDI
1966          * code:
1967          * - Link train failed while doing crtc_enable, and on this case we
1968          *   really should respect the mode set sequence and wait for a
1969          *   crtc_disable.
1970          * - Someone turned the monitor off and intel_dp_check_link_status
1971          *   called us. We don't need to disable the whole port on this case, so
1972          *   when someone turns the monitor on again,
1973          *   intel_ddi_prepare_link_retrain will take care of redoing the link
1974          *   train.
1975          */
1976         if (IS_HASWELL(dev))
1977                 return;
1978
1979         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1980                 return;
1981
1982         DRM_DEBUG_KMS("\n");
1983
1984         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1985                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1986                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1987         } else {
1988                 DP &= ~DP_LINK_TRAIN_MASK;
1989                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1990         }
1991         POSTING_READ(intel_dp->output_reg);
1992
1993         msleep(17);
1994
1995         if (HAS_PCH_IBX(dev) &&
1996             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
1997                 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1998
1999                 /* Hardware workaround: leaving our transcoder select
2000                  * set to transcoder B while it's off will prevent the
2001                  * corresponding HDMI output on transcoder A.
2002                  *
2003                  * Combine this with another hardware workaround:
2004                  * transcoder select bit can only be cleared while the
2005                  * port is enabled.
2006                  */
2007                 DP &= ~DP_PIPEB_SELECT;
2008                 I915_WRITE(intel_dp->output_reg, DP);
2009
2010                 /* Changes to enable or select take place the vblank
2011                  * after being written.
2012                  */
2013                 if (crtc == NULL) {
2014                         /* We can arrive here never having been attached
2015                          * to a CRTC, for instance, due to inheriting
2016                          * random state from the BIOS.
2017                          *
2018                          * If the pipe is not running, play safe and
2019                          * wait for the clocks to stabilise before
2020                          * continuing.
2021                          */
2022                         POSTING_READ(intel_dp->output_reg);
2023                         msleep(50);
2024                 } else
2025                         intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
2026         }
2027
2028         DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2029         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2030         POSTING_READ(intel_dp->output_reg);
2031         msleep(intel_dp->panel_power_down_delay);
2032 }
2033
2034 static bool
2035 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2036 {
2037         if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2038                                            sizeof(intel_dp->dpcd)) == 0)
2039                 return false; /* aux transfer failed */
2040
2041         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2042                 return false; /* DPCD not present */
2043
2044         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2045               DP_DWN_STRM_PORT_PRESENT))
2046                 return true; /* native DP sink */
2047
2048         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2049                 return true; /* no per-port downstream info */
2050
2051         if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2052                                            intel_dp->downstream_ports,
2053                                            DP_MAX_DOWNSTREAM_PORTS) == 0)
2054                 return false; /* downstream port status fetch failed */
2055
2056         return true;
2057 }
2058
2059 static void
2060 intel_dp_probe_oui(struct intel_dp *intel_dp)
2061 {
2062         u8 buf[3];
2063
2064         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2065                 return;
2066
2067         ironlake_edp_panel_vdd_on(intel_dp);
2068
2069         if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2070                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2071                               buf[0], buf[1], buf[2]);
2072
2073         if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2074                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2075                               buf[0], buf[1], buf[2]);
2076
2077         ironlake_edp_panel_vdd_off(intel_dp, false);
2078 }
2079
2080 static bool
2081 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2082 {
2083         int ret;
2084
2085         ret = intel_dp_aux_native_read_retry(intel_dp,
2086                                              DP_DEVICE_SERVICE_IRQ_VECTOR,
2087                                              sink_irq_vector, 1);
2088         if (!ret)
2089                 return false;
2090
2091         return true;
2092 }
2093
2094 static void
2095 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2096 {
2097         /* NAK by default */
2098         intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2099 }
2100
2101 /*
2102  * According to DP spec
2103  * 5.1.2:
2104  *  1. Read DPCD
2105  *  2. Configure link according to Receiver Capabilities
2106  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
2107  *  4. Check link status on receipt of hot-plug interrupt
2108  */
2109
2110 static void
2111 intel_dp_check_link_status(struct intel_dp *intel_dp)
2112 {
2113         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2114         u8 sink_irq_vector;
2115         u8 link_status[DP_LINK_STATUS_SIZE];
2116
2117         if (!intel_encoder->connectors_active)
2118                 return;
2119
2120         if (WARN_ON(!intel_encoder->base.crtc))
2121                 return;
2122
2123         /* Try to read receiver status if the link appears to be up */
2124         if (!intel_dp_get_link_status(intel_dp, link_status)) {
2125                 intel_dp_link_down(intel_dp);
2126                 return;
2127         }
2128
2129         /* Now read the DPCD to see if it's actually running */
2130         if (!intel_dp_get_dpcd(intel_dp)) {
2131                 intel_dp_link_down(intel_dp);
2132                 return;
2133         }
2134
2135         /* Try to read the source of the interrupt */
2136         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2137             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2138                 /* Clear interrupt source */
2139                 intel_dp_aux_native_write_1(intel_dp,
2140                                             DP_DEVICE_SERVICE_IRQ_VECTOR,
2141                                             sink_irq_vector);
2142
2143                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2144                         intel_dp_handle_test_request(intel_dp);
2145                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2146                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2147         }
2148
2149         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2150                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2151                               drm_get_encoder_name(&intel_encoder->base));
2152                 intel_dp_start_link_train(intel_dp);
2153                 intel_dp_complete_link_train(intel_dp);
2154         }
2155 }
2156
2157 /* XXX this is probably wrong for multiple downstream ports */
2158 static enum drm_connector_status
2159 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2160 {
2161         uint8_t *dpcd = intel_dp->dpcd;
2162         bool hpd;
2163         uint8_t type;
2164
2165         if (!intel_dp_get_dpcd(intel_dp))
2166                 return connector_status_disconnected;
2167
2168         /* if there's no downstream port, we're done */
2169         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2170                 return connector_status_connected;
2171
2172         /* If we're HPD-aware, SINK_COUNT changes dynamically */
2173         hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2174         if (hpd) {
2175                 uint8_t reg;
2176                 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2177                                                     &reg, 1))
2178                         return connector_status_unknown;
2179                 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2180                                               : connector_status_disconnected;
2181         }
2182
2183         /* If no HPD, poke DDC gently */
2184         if (drm_probe_ddc(&intel_dp->adapter))
2185                 return connector_status_connected;
2186
2187         /* Well we tried, say unknown for unreliable port types */
2188         type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2189         if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2190                 return connector_status_unknown;
2191
2192         /* Anything else is out of spec, warn and ignore */
2193         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2194         return connector_status_disconnected;
2195 }
2196
2197 static enum drm_connector_status
2198 ironlake_dp_detect(struct intel_dp *intel_dp)
2199 {
2200         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2201         enum drm_connector_status status;
2202
2203         /* Can't disconnect eDP, but you can close the lid... */
2204         if (is_edp(intel_dp)) {
2205                 status = intel_panel_detect(dev);
2206                 if (status == connector_status_unknown)
2207                         status = connector_status_connected;
2208                 return status;
2209         }
2210
2211         return intel_dp_detect_dpcd(intel_dp);
2212 }
2213
2214 static enum drm_connector_status
2215 g4x_dp_detect(struct intel_dp *intel_dp)
2216 {
2217         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2218         struct drm_i915_private *dev_priv = dev->dev_private;
2219         uint32_t bit;
2220
2221         switch (intel_dp->output_reg) {
2222         case DP_B:
2223                 bit = DPB_HOTPLUG_LIVE_STATUS;
2224                 break;
2225         case DP_C:
2226                 bit = DPC_HOTPLUG_LIVE_STATUS;
2227                 break;
2228         case DP_D:
2229                 bit = DPD_HOTPLUG_LIVE_STATUS;
2230                 break;
2231         default:
2232                 return connector_status_unknown;
2233         }
2234
2235         if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2236                 return connector_status_disconnected;
2237
2238         return intel_dp_detect_dpcd(intel_dp);
2239 }
2240
2241 static struct edid *
2242 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2243 {
2244         struct intel_connector *intel_connector = to_intel_connector(connector);
2245
2246         /* use cached edid if we have one */
2247         if (intel_connector->edid) {
2248                 struct edid *edid;
2249                 int size;
2250
2251                 /* invalid edid */
2252                 if (IS_ERR(intel_connector->edid))
2253                         return NULL;
2254
2255                 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
2256                 edid = kmalloc(size, GFP_KERNEL);
2257                 if (!edid)
2258                         return NULL;
2259
2260                 memcpy(edid, intel_connector->edid, size);
2261                 return edid;
2262         }
2263
2264         return drm_get_edid(connector, adapter);
2265 }
2266
2267 static int
2268 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2269 {
2270         struct intel_connector *intel_connector = to_intel_connector(connector);
2271
2272         /* use cached edid if we have one */
2273         if (intel_connector->edid) {
2274                 /* invalid edid */
2275                 if (IS_ERR(intel_connector->edid))
2276                         return 0;
2277
2278                 return intel_connector_update_modes(connector,
2279                                                     intel_connector->edid);
2280         }
2281
2282         return intel_ddc_get_modes(connector, adapter);
2283 }
2284
2285
2286 /**
2287  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2288  *
2289  * \return true if DP port is connected.
2290  * \return false if DP port is disconnected.
2291  */
2292 static enum drm_connector_status
2293 intel_dp_detect(struct drm_connector *connector, bool force)
2294 {
2295         struct intel_dp *intel_dp = intel_attached_dp(connector);
2296         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2297         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2298         struct drm_device *dev = connector->dev;
2299         enum drm_connector_status status;
2300         struct edid *edid = NULL;
2301         char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2302
2303         intel_dp->has_audio = false;
2304
2305         if (HAS_PCH_SPLIT(dev))
2306                 status = ironlake_dp_detect(intel_dp);
2307         else
2308                 status = g4x_dp_detect(intel_dp);
2309
2310         hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2311                            32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2312         DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2313
2314         if (status != connector_status_connected)
2315                 return status;
2316
2317         intel_dp_probe_oui(intel_dp);
2318
2319         if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2320                 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2321         } else {
2322                 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2323                 if (edid) {
2324                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
2325                         kfree(edid);
2326                 }
2327         }
2328
2329         if (intel_encoder->type != INTEL_OUTPUT_EDP)
2330                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2331         return connector_status_connected;
2332 }
2333
2334 static int intel_dp_get_modes(struct drm_connector *connector)
2335 {
2336         struct intel_dp *intel_dp = intel_attached_dp(connector);
2337         struct intel_connector *intel_connector = to_intel_connector(connector);
2338         struct drm_device *dev = connector->dev;
2339         int ret;
2340
2341         /* We should parse the EDID data and find out if it has an audio sink
2342          */
2343
2344         ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2345         if (ret)
2346                 return ret;
2347
2348         /* if eDP has no EDID, fall back to fixed mode */
2349         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2350                 struct drm_display_mode *mode;
2351                 mode = drm_mode_duplicate(dev,
2352                                           intel_connector->panel.fixed_mode);
2353                 if (mode) {
2354                         drm_mode_probed_add(connector, mode);
2355                         return 1;
2356                 }
2357         }
2358         return 0;
2359 }
2360
2361 static bool
2362 intel_dp_detect_audio(struct drm_connector *connector)
2363 {
2364         struct intel_dp *intel_dp = intel_attached_dp(connector);
2365         struct edid *edid;
2366         bool has_audio = false;
2367
2368         edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2369         if (edid) {
2370                 has_audio = drm_detect_monitor_audio(edid);
2371                 kfree(edid);
2372         }
2373
2374         return has_audio;
2375 }
2376
2377 static int
2378 intel_dp_set_property(struct drm_connector *connector,
2379                       struct drm_property *property,
2380                       uint64_t val)
2381 {
2382         struct drm_i915_private *dev_priv = connector->dev->dev_private;
2383         struct intel_connector *intel_connector = to_intel_connector(connector);
2384         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2385         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2386         int ret;
2387
2388         ret = drm_connector_property_set_value(connector, property, val);
2389         if (ret)
2390                 return ret;
2391
2392         if (property == dev_priv->force_audio_property) {
2393                 int i = val;
2394                 bool has_audio;
2395
2396                 if (i == intel_dp->force_audio)
2397                         return 0;
2398
2399                 intel_dp->force_audio = i;
2400
2401                 if (i == HDMI_AUDIO_AUTO)
2402                         has_audio = intel_dp_detect_audio(connector);
2403                 else
2404                         has_audio = (i == HDMI_AUDIO_ON);
2405
2406                 if (has_audio == intel_dp->has_audio)
2407                         return 0;
2408
2409                 intel_dp->has_audio = has_audio;
2410                 goto done;
2411         }
2412
2413         if (property == dev_priv->broadcast_rgb_property) {
2414                 if (val == !!intel_dp->color_range)
2415                         return 0;
2416
2417                 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2418                 goto done;
2419         }
2420
2421         if (is_edp(intel_dp) &&
2422             property == connector->dev->mode_config.scaling_mode_property) {
2423                 if (val == DRM_MODE_SCALE_NONE) {
2424                         DRM_DEBUG_KMS("no scaling not supported\n");
2425                         return -EINVAL;
2426                 }
2427
2428                 if (intel_connector->panel.fitting_mode == val) {
2429                         /* the eDP scaling property is not changed */
2430                         return 0;
2431                 }
2432                 intel_connector->panel.fitting_mode = val;
2433
2434                 goto done;
2435         }
2436
2437         return -EINVAL;
2438
2439 done:
2440         if (intel_encoder->base.crtc) {
2441                 struct drm_crtc *crtc = intel_encoder->base.crtc;
2442                 intel_set_mode(crtc, &crtc->mode,
2443                                crtc->x, crtc->y, crtc->fb);
2444         }
2445
2446         return 0;
2447 }
2448
2449 static void
2450 intel_dp_destroy(struct drm_connector *connector)
2451 {
2452         struct drm_device *dev = connector->dev;
2453         struct intel_dp *intel_dp = intel_attached_dp(connector);
2454         struct intel_connector *intel_connector = to_intel_connector(connector);
2455
2456         if (!IS_ERR_OR_NULL(intel_connector->edid))
2457                 kfree(intel_connector->edid);
2458
2459         if (is_edp(intel_dp)) {
2460                 intel_panel_destroy_backlight(dev);
2461                 intel_panel_fini(&intel_connector->panel);
2462         }
2463
2464         drm_sysfs_connector_remove(connector);
2465         drm_connector_cleanup(connector);
2466         kfree(connector);
2467 }
2468
2469 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2470 {
2471         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2472         struct intel_dp *intel_dp = &intel_dig_port->dp;
2473
2474         i2c_del_adapter(&intel_dp->adapter);
2475         drm_encoder_cleanup(encoder);
2476         if (is_edp(intel_dp)) {
2477                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2478                 ironlake_panel_vdd_off_sync(intel_dp);
2479         }
2480         kfree(intel_dig_port);
2481 }
2482
2483 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2484         .mode_fixup = intel_dp_mode_fixup,
2485         .mode_set = intel_dp_mode_set,
2486         .disable = intel_encoder_noop,
2487 };
2488
2489 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs_hsw = {
2490         .mode_fixup = intel_dp_mode_fixup,
2491         .mode_set = intel_ddi_mode_set,
2492         .disable = intel_encoder_noop,
2493 };
2494
2495 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2496         .dpms = intel_connector_dpms,
2497         .detect = intel_dp_detect,
2498         .fill_modes = drm_helper_probe_single_connector_modes,
2499         .set_property = intel_dp_set_property,
2500         .destroy = intel_dp_destroy,
2501 };
2502
2503 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2504         .get_modes = intel_dp_get_modes,
2505         .mode_valid = intel_dp_mode_valid,
2506         .best_encoder = intel_best_encoder,
2507 };
2508
2509 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2510         .destroy = intel_dp_encoder_destroy,
2511 };
2512
2513 static void
2514 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2515 {
2516         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2517
2518         intel_dp_check_link_status(intel_dp);
2519 }
2520
2521 /* Return which DP Port should be selected for Transcoder DP control */
2522 int
2523 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2524 {
2525         struct drm_device *dev = crtc->dev;
2526         struct intel_encoder *intel_encoder;
2527         struct intel_dp *intel_dp;
2528
2529         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2530                 intel_dp = enc_to_intel_dp(&intel_encoder->base);
2531
2532                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2533                     intel_encoder->type == INTEL_OUTPUT_EDP)
2534                         return intel_dp->output_reg;
2535         }
2536
2537         return -1;
2538 }
2539
2540 /* check the VBT to see whether the eDP is on DP-D port */
2541 bool intel_dpd_is_edp(struct drm_device *dev)
2542 {
2543         struct drm_i915_private *dev_priv = dev->dev_private;
2544         struct child_device_config *p_child;
2545         int i;
2546
2547         if (!dev_priv->child_dev_num)
2548                 return false;
2549
2550         for (i = 0; i < dev_priv->child_dev_num; i++) {
2551                 p_child = dev_priv->child_dev + i;
2552
2553                 if (p_child->dvo_port == PORT_IDPD &&
2554                     p_child->device_type == DEVICE_TYPE_eDP)
2555                         return true;
2556         }
2557         return false;
2558 }
2559
2560 static void
2561 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2562 {
2563         struct intel_connector *intel_connector = to_intel_connector(connector);
2564
2565         intel_attach_force_audio_property(connector);
2566         intel_attach_broadcast_rgb_property(connector);
2567
2568         if (is_edp(intel_dp)) {
2569                 drm_mode_create_scaling_mode_property(connector->dev);
2570                 drm_connector_attach_property(
2571                         connector,
2572                         connector->dev->mode_config.scaling_mode_property,
2573                         DRM_MODE_SCALE_ASPECT);
2574                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
2575         }
2576 }
2577
2578 static void
2579 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
2580                                     struct intel_dp *intel_dp)
2581 {
2582         struct drm_i915_private *dev_priv = dev->dev_private;
2583         struct edp_power_seq cur, vbt, spec, final;
2584         u32 pp_on, pp_off, pp_div, pp;
2585
2586         /* Workaround: Need to write PP_CONTROL with the unlock key as
2587          * the very first thing. */
2588         pp = ironlake_get_pp_control(dev_priv);
2589         I915_WRITE(PCH_PP_CONTROL, pp);
2590
2591         pp_on = I915_READ(PCH_PP_ON_DELAYS);
2592         pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2593         pp_div = I915_READ(PCH_PP_DIVISOR);
2594
2595         /* Pull timing values out of registers */
2596         cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2597                 PANEL_POWER_UP_DELAY_SHIFT;
2598
2599         cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2600                 PANEL_LIGHT_ON_DELAY_SHIFT;
2601
2602         cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2603                 PANEL_LIGHT_OFF_DELAY_SHIFT;
2604
2605         cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2606                 PANEL_POWER_DOWN_DELAY_SHIFT;
2607
2608         cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2609                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2610
2611         DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2612                       cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2613
2614         vbt = dev_priv->edp.pps;
2615
2616         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2617          * our hw here, which are all in 100usec. */
2618         spec.t1_t3 = 210 * 10;
2619         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2620         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2621         spec.t10 = 500 * 10;
2622         /* This one is special and actually in units of 100ms, but zero
2623          * based in the hw (so we need to add 100 ms). But the sw vbt
2624          * table multiplies it with 1000 to make it in units of 100usec,
2625          * too. */
2626         spec.t11_t12 = (510 + 100) * 10;
2627
2628         DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2629                       vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2630
2631         /* Use the max of the register settings and vbt. If both are
2632          * unset, fall back to the spec limits. */
2633 #define assign_final(field)     final.field = (max(cur.field, vbt.field) == 0 ? \
2634                                        spec.field : \
2635                                        max(cur.field, vbt.field))
2636         assign_final(t1_t3);
2637         assign_final(t8);
2638         assign_final(t9);
2639         assign_final(t10);
2640         assign_final(t11_t12);
2641 #undef assign_final
2642
2643 #define get_delay(field)        (DIV_ROUND_UP(final.field, 10))
2644         intel_dp->panel_power_up_delay = get_delay(t1_t3);
2645         intel_dp->backlight_on_delay = get_delay(t8);
2646         intel_dp->backlight_off_delay = get_delay(t9);
2647         intel_dp->panel_power_down_delay = get_delay(t10);
2648         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2649 #undef get_delay
2650
2651         /* And finally store the new values in the power sequencer. */
2652         pp_on = (final.t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2653                 (final.t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2654         pp_off = (final.t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2655                  (final.t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
2656         /* Compute the divisor for the pp clock, simply match the Bspec
2657          * formula. */
2658         pp_div = ((100 * intel_pch_rawclk(dev))/2 - 1)
2659                         << PP_REFERENCE_DIVIDER_SHIFT;
2660         pp_div |= (DIV_ROUND_UP(final.t11_t12, 1000)
2661                         << PANEL_POWER_CYCLE_DELAY_SHIFT);
2662
2663         /* Haswell doesn't have any port selection bits for the panel
2664          * power sequencer any more. */
2665         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2666                 if (is_cpu_edp(intel_dp))
2667                         pp_on |= PANEL_POWER_PORT_DP_A;
2668                 else
2669                         pp_on |= PANEL_POWER_PORT_DP_D;
2670         }
2671
2672         I915_WRITE(PCH_PP_ON_DELAYS, pp_on);
2673         I915_WRITE(PCH_PP_OFF_DELAYS, pp_off);
2674         I915_WRITE(PCH_PP_DIVISOR, pp_div);
2675
2676
2677         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2678                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2679                       intel_dp->panel_power_cycle_delay);
2680
2681         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2682                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2683
2684         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2685                       I915_READ(PCH_PP_ON_DELAYS),
2686                       I915_READ(PCH_PP_OFF_DELAYS),
2687                       I915_READ(PCH_PP_DIVISOR));
2688 }
2689
2690 static void
2691 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
2692                         struct intel_connector *intel_connector)
2693 {
2694         struct drm_connector *connector = &intel_connector->base;
2695         struct intel_dp *intel_dp = &intel_dig_port->dp;
2696         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2697         struct drm_device *dev = intel_encoder->base.dev;
2698         struct drm_i915_private *dev_priv = dev->dev_private;
2699         struct drm_display_mode *fixed_mode = NULL;
2700         enum port port = intel_dp->port;
2701         const char *name = NULL;
2702         int type;
2703
2704         /* Preserve the current hw state. */
2705         intel_dp->DP = I915_READ(intel_dp->output_reg);
2706         intel_dp->attached_connector = intel_connector;
2707
2708         if (HAS_PCH_SPLIT(dev) && port == PORT_D)
2709                 if (intel_dpd_is_edp(dev))
2710                         intel_dp->is_pch_edp = true;
2711
2712         /*
2713          * FIXME : We need to initialize built-in panels before external panels.
2714          * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2715          */
2716         if (IS_VALLEYVIEW(dev) && port == PORT_C) {
2717                 type = DRM_MODE_CONNECTOR_eDP;
2718                 intel_encoder->type = INTEL_OUTPUT_EDP;
2719         } else if (port == PORT_A || is_pch_edp(intel_dp)) {
2720                 type = DRM_MODE_CONNECTOR_eDP;
2721                 intel_encoder->type = INTEL_OUTPUT_EDP;
2722         } else {
2723                 type = DRM_MODE_CONNECTOR_DisplayPort;
2724                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2725         }
2726
2727         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2728         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2729
2730         connector->polled = DRM_CONNECTOR_POLL_HPD;
2731         connector->interlace_allowed = true;
2732         connector->doublescan_allowed = 0;
2733
2734         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2735                           ironlake_panel_vdd_work);
2736
2737         intel_connector_attach_encoder(intel_connector, intel_encoder);
2738         drm_sysfs_connector_add(connector);
2739
2740         intel_connector->get_hw_state = intel_connector_get_hw_state;
2741
2742         /* Set up the DDC bus. */
2743         switch (port) {
2744         case PORT_A:
2745                 name = "DPDDC-A";
2746                 break;
2747         case PORT_B:
2748                 dev_priv->hotplug_supported_mask |= DPB_HOTPLUG_INT_STATUS;
2749                 name = "DPDDC-B";
2750                 break;
2751         case PORT_C:
2752                 dev_priv->hotplug_supported_mask |= DPC_HOTPLUG_INT_STATUS;
2753                 name = "DPDDC-C";
2754                 break;
2755         case PORT_D:
2756                 dev_priv->hotplug_supported_mask |= DPD_HOTPLUG_INT_STATUS;
2757                 name = "DPDDC-D";
2758                 break;
2759         default:
2760                 WARN(1, "Invalid port %c\n", port_name(port));
2761                 break;
2762         }
2763
2764         if (is_edp(intel_dp))
2765                 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2766
2767         intel_dp_i2c_init(intel_dp, intel_connector, name);
2768
2769         /* Cache DPCD and EDID for edp. */
2770         if (is_edp(intel_dp)) {
2771                 bool ret;
2772                 struct drm_display_mode *scan;
2773                 struct edid *edid;
2774
2775                 ironlake_edp_panel_vdd_on(intel_dp);
2776                 ret = intel_dp_get_dpcd(intel_dp);
2777                 ironlake_edp_panel_vdd_off(intel_dp, false);
2778
2779                 if (ret) {
2780                         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2781                                 dev_priv->no_aux_handshake =
2782                                         intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2783                                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2784                 } else {
2785                         /* if this fails, presume the device is a ghost */
2786                         DRM_INFO("failed to retrieve link info, disabling eDP\n");
2787                         intel_dp_encoder_destroy(&intel_encoder->base);
2788                         intel_dp_destroy(connector);
2789                         return;
2790                 }
2791
2792                 ironlake_edp_panel_vdd_on(intel_dp);
2793                 edid = drm_get_edid(connector, &intel_dp->adapter);
2794                 if (edid) {
2795                         if (drm_add_edid_modes(connector, edid)) {
2796                                 drm_mode_connector_update_edid_property(connector, edid);
2797                                 drm_edid_to_eld(connector, edid);
2798                         } else {
2799                                 kfree(edid);
2800                                 edid = ERR_PTR(-EINVAL);
2801                         }
2802                 } else {
2803                         edid = ERR_PTR(-ENOENT);
2804                 }
2805                 intel_connector->edid = edid;
2806
2807                 /* prefer fixed mode from EDID if available */
2808                 list_for_each_entry(scan, &connector->probed_modes, head) {
2809                         if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
2810                                 fixed_mode = drm_mode_duplicate(dev, scan);
2811                                 break;
2812                         }
2813                 }
2814
2815                 /* fallback to VBT if available for eDP */
2816                 if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
2817                         fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2818                         if (fixed_mode)
2819                                 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
2820                 }
2821
2822                 ironlake_edp_panel_vdd_off(intel_dp, false);
2823         }
2824
2825         if (is_edp(intel_dp)) {
2826                 intel_panel_init(&intel_connector->panel, fixed_mode);
2827                 intel_panel_setup_backlight(connector);
2828         }
2829
2830         intel_dp_add_properties(intel_dp, connector);
2831
2832         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2833          * 0xd.  Failure to do so will result in spurious interrupts being
2834          * generated on the port when a cable is not attached.
2835          */
2836         if (IS_G4X(dev) && !IS_GM45(dev)) {
2837                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2838                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2839         }
2840 }
2841
2842 void
2843 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
2844 {
2845         struct intel_digital_port *intel_dig_port;
2846         struct intel_encoder *intel_encoder;
2847         struct drm_encoder *encoder;
2848         struct intel_connector *intel_connector;
2849
2850         intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
2851         if (!intel_dig_port)
2852                 return;
2853
2854         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2855         if (!intel_connector) {
2856                 kfree(intel_dig_port);
2857                 return;
2858         }
2859
2860         intel_encoder = &intel_dig_port->base;
2861         encoder = &intel_encoder->base;
2862
2863         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2864                          DRM_MODE_ENCODER_TMDS);
2865
2866         if (IS_HASWELL(dev)) {
2867                 drm_encoder_helper_add(&intel_encoder->base,
2868                                        &intel_dp_helper_funcs_hsw);
2869
2870                 intel_encoder->enable = intel_enable_ddi;
2871                 intel_encoder->pre_enable = intel_ddi_pre_enable;
2872                 intel_encoder->disable = intel_disable_ddi;
2873                 intel_encoder->post_disable = intel_ddi_post_disable;
2874                 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
2875         } else {
2876                 drm_encoder_helper_add(&intel_encoder->base,
2877                                        &intel_dp_helper_funcs);
2878
2879                 intel_encoder->enable = intel_enable_dp;
2880                 intel_encoder->pre_enable = intel_pre_enable_dp;
2881                 intel_encoder->disable = intel_disable_dp;
2882                 intel_encoder->post_disable = intel_post_disable_dp;
2883                 intel_encoder->get_hw_state = intel_dp_get_hw_state;
2884         }
2885
2886         intel_dig_port->dp.port = port;
2887         intel_dig_port->dp.output_reg = output_reg;
2888
2889         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2890         intel_encoder->cloneable = false;
2891         intel_encoder->hot_plug = intel_dp_hot_plug;
2892
2893         intel_dp_init_connector(intel_dig_port, intel_connector);
2894 }