2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
39 #define DP_RECEIVER_CAP_SIZE 0xf
40 #define DP_LINK_STATUS_SIZE 6
41 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
44 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
45 * @intel_dp: DP struct
47 * If a CPU or PCH DP output is attached to an eDP panel, this function
48 * will return true, and false otherwise.
50 static bool is_edp(struct intel_dp *intel_dp)
52 return intel_dp->base.type == INTEL_OUTPUT_EDP;
56 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
57 * @intel_dp: DP struct
59 * Returns true if the given DP struct corresponds to a PCH DP port attached
60 * to an eDP panel, false otherwise. Helpful for determining whether we
61 * may need FDI resources for a given DP output or not.
63 static bool is_pch_edp(struct intel_dp *intel_dp)
65 return intel_dp->is_pch_edp;
69 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
70 * @intel_dp: DP struct
72 * Returns true if the given DP struct corresponds to a CPU eDP port.
74 static bool is_cpu_edp(struct intel_dp *intel_dp)
76 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
79 static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
81 return container_of(encoder, struct intel_dp, base.base);
84 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
86 return container_of(intel_attached_encoder(connector),
87 struct intel_dp, base);
91 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
92 * @encoder: DRM encoder
94 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
97 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
99 struct intel_dp *intel_dp;
104 intel_dp = enc_to_intel_dp(encoder);
106 return is_pch_edp(intel_dp);
109 static void intel_dp_start_link_train(struct intel_dp *intel_dp);
110 static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
111 static void intel_dp_link_down(struct intel_dp *intel_dp);
114 intel_edp_link_config(struct intel_encoder *intel_encoder,
115 int *lane_num, int *link_bw)
117 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
119 *lane_num = intel_dp->lane_count;
120 if (intel_dp->link_bw == DP_LINK_BW_1_62)
122 else if (intel_dp->link_bw == DP_LINK_BW_2_7)
127 intel_edp_target_clock(struct intel_encoder *intel_encoder,
128 struct drm_display_mode *mode)
130 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
132 if (intel_dp->panel_fixed_mode)
133 return intel_dp->panel_fixed_mode->clock;
139 intel_dp_max_lane_count(struct intel_dp *intel_dp)
141 int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
142 switch (max_lane_count) {
143 case 1: case 2: case 4:
148 return max_lane_count;
152 intel_dp_max_link_bw(struct intel_dp *intel_dp)
154 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
156 switch (max_link_bw) {
157 case DP_LINK_BW_1_62:
161 max_link_bw = DP_LINK_BW_1_62;
168 intel_dp_link_clock(uint8_t link_bw)
170 if (link_bw == DP_LINK_BW_2_7)
177 * The units on the numbers in the next two are... bizarre. Examples will
178 * make it clearer; this one parallels an example in the eDP spec.
180 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
182 * 270000 * 1 * 8 / 10 == 216000
184 * The actual data capacity of that configuration is 2.16Gbit/s, so the
185 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
186 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
187 * 119000. At 18bpp that's 2142000 kilobits per second.
189 * Thus the strange-looking division by 10 in intel_dp_link_required, to
190 * get the result in decakilobits instead of kilobits.
194 intel_dp_link_required(int pixel_clock, int bpp)
196 return (pixel_clock * bpp + 9) / 10;
200 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
202 return (max_link_clock * max_lanes * 8) / 10;
206 intel_dp_adjust_dithering(struct intel_dp *intel_dp,
207 struct drm_display_mode *mode,
210 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
211 int max_lanes = intel_dp_max_lane_count(intel_dp);
212 int max_rate, mode_rate;
214 mode_rate = intel_dp_link_required(mode->clock, 24);
215 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
217 if (mode_rate > max_rate) {
218 mode_rate = intel_dp_link_required(mode->clock, 18);
219 if (mode_rate > max_rate)
224 |= INTEL_MODE_DP_FORCE_6BPC;
233 intel_dp_mode_valid(struct drm_connector *connector,
234 struct drm_display_mode *mode)
236 struct intel_dp *intel_dp = intel_attached_dp(connector);
238 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
239 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
242 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
246 if (!intel_dp_adjust_dithering(intel_dp, mode, false))
247 return MODE_CLOCK_HIGH;
249 if (mode->clock < 10000)
250 return MODE_CLOCK_LOW;
252 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
253 return MODE_H_ILLEGAL;
259 pack_aux(uint8_t *src, int src_bytes)
266 for (i = 0; i < src_bytes; i++)
267 v |= ((uint32_t) src[i]) << ((3-i) * 8);
272 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
277 for (i = 0; i < dst_bytes; i++)
278 dst[i] = src >> ((3-i) * 8);
281 /* hrawclock is 1/4 the FSB frequency */
283 intel_hrawclk(struct drm_device *dev)
285 struct drm_i915_private *dev_priv = dev->dev_private;
288 clkcfg = I915_READ(CLKCFG);
289 switch (clkcfg & CLKCFG_FSB_MASK) {
298 case CLKCFG_FSB_1067:
300 case CLKCFG_FSB_1333:
302 /* these two are just a guess; one of them might be right */
303 case CLKCFG_FSB_1600:
304 case CLKCFG_FSB_1600_ALT:
311 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
313 struct drm_device *dev = intel_dp->base.base.dev;
314 struct drm_i915_private *dev_priv = dev->dev_private;
316 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
319 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
321 struct drm_device *dev = intel_dp->base.base.dev;
322 struct drm_i915_private *dev_priv = dev->dev_private;
324 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
328 intel_dp_check_edp(struct intel_dp *intel_dp)
330 struct drm_device *dev = intel_dp->base.base.dev;
331 struct drm_i915_private *dev_priv = dev->dev_private;
333 if (!is_edp(intel_dp))
335 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
336 WARN(1, "eDP powered off while attempting aux channel communication.\n");
337 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
338 I915_READ(PCH_PP_STATUS),
339 I915_READ(PCH_PP_CONTROL));
344 intel_dp_aux_ch(struct intel_dp *intel_dp,
345 uint8_t *send, int send_bytes,
346 uint8_t *recv, int recv_size)
348 uint32_t output_reg = intel_dp->output_reg;
349 struct drm_device *dev = intel_dp->base.base.dev;
350 struct drm_i915_private *dev_priv = dev->dev_private;
351 uint32_t ch_ctl = output_reg + 0x10;
352 uint32_t ch_data = ch_ctl + 4;
356 uint32_t aux_clock_divider;
359 intel_dp_check_edp(intel_dp);
360 /* The clock divider is based off the hrawclk,
361 * and would like to run at 2MHz. So, take the
362 * hrawclk value and divide by 2 and use that
364 * Note that PCH attached eDP panels should use a 125MHz input
367 if (is_cpu_edp(intel_dp)) {
368 if (IS_GEN6(dev) || IS_GEN7(dev))
369 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
371 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
372 } else if (HAS_PCH_SPLIT(dev))
373 aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */
375 aux_clock_divider = intel_hrawclk(dev) / 2;
382 /* Try to wait for any previous AUX channel activity */
383 for (try = 0; try < 3; try++) {
384 status = I915_READ(ch_ctl);
385 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
391 WARN(1, "dp_aux_ch not started status 0x%08x\n",
396 /* Must try at least 3 times according to DP spec */
397 for (try = 0; try < 5; try++) {
398 /* Load the send data into the aux channel data registers */
399 for (i = 0; i < send_bytes; i += 4)
400 I915_WRITE(ch_data + i,
401 pack_aux(send + i, send_bytes - i));
403 /* Send the command and wait for it to complete */
405 DP_AUX_CH_CTL_SEND_BUSY |
406 DP_AUX_CH_CTL_TIME_OUT_400us |
407 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
408 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
409 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
411 DP_AUX_CH_CTL_TIME_OUT_ERROR |
412 DP_AUX_CH_CTL_RECEIVE_ERROR);
414 status = I915_READ(ch_ctl);
415 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
420 /* Clear done status and any errors */
424 DP_AUX_CH_CTL_TIME_OUT_ERROR |
425 DP_AUX_CH_CTL_RECEIVE_ERROR);
427 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
428 DP_AUX_CH_CTL_RECEIVE_ERROR))
430 if (status & DP_AUX_CH_CTL_DONE)
434 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
435 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
439 /* Check for timeout or receive error.
440 * Timeouts occur when the sink is not connected
442 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
443 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
447 /* Timeouts occur when the device isn't connected, so they're
448 * "normal" -- don't fill the kernel log with these */
449 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
450 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
454 /* Unload any bytes sent back from the other side */
455 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
456 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
457 if (recv_bytes > recv_size)
458 recv_bytes = recv_size;
460 for (i = 0; i < recv_bytes; i += 4)
461 unpack_aux(I915_READ(ch_data + i),
462 recv + i, recv_bytes - i);
467 /* Write data to the aux channel in native mode */
469 intel_dp_aux_native_write(struct intel_dp *intel_dp,
470 uint16_t address, uint8_t *send, int send_bytes)
477 intel_dp_check_edp(intel_dp);
480 msg[0] = AUX_NATIVE_WRITE << 4;
481 msg[1] = address >> 8;
482 msg[2] = address & 0xff;
483 msg[3] = send_bytes - 1;
484 memcpy(&msg[4], send, send_bytes);
485 msg_bytes = send_bytes + 4;
487 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
490 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
492 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
500 /* Write a single byte to the aux channel in native mode */
502 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
503 uint16_t address, uint8_t byte)
505 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
508 /* read bytes from a native aux channel */
510 intel_dp_aux_native_read(struct intel_dp *intel_dp,
511 uint16_t address, uint8_t *recv, int recv_bytes)
520 intel_dp_check_edp(intel_dp);
521 msg[0] = AUX_NATIVE_READ << 4;
522 msg[1] = address >> 8;
523 msg[2] = address & 0xff;
524 msg[3] = recv_bytes - 1;
527 reply_bytes = recv_bytes + 1;
530 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
537 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
538 memcpy(recv, reply + 1, ret - 1);
541 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
549 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
550 uint8_t write_byte, uint8_t *read_byte)
552 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
553 struct intel_dp *intel_dp = container_of(adapter,
556 uint16_t address = algo_data->address;
564 intel_dp_check_edp(intel_dp);
565 /* Set up the command byte */
566 if (mode & MODE_I2C_READ)
567 msg[0] = AUX_I2C_READ << 4;
569 msg[0] = AUX_I2C_WRITE << 4;
571 if (!(mode & MODE_I2C_STOP))
572 msg[0] |= AUX_I2C_MOT << 4;
574 msg[1] = address >> 8;
595 for (retry = 0; retry < 5; retry++) {
596 ret = intel_dp_aux_ch(intel_dp,
600 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
604 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
605 case AUX_NATIVE_REPLY_ACK:
606 /* I2C-over-AUX Reply field is only valid
607 * when paired with AUX ACK.
610 case AUX_NATIVE_REPLY_NACK:
611 DRM_DEBUG_KMS("aux_ch native nack\n");
613 case AUX_NATIVE_REPLY_DEFER:
617 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
622 switch (reply[0] & AUX_I2C_REPLY_MASK) {
623 case AUX_I2C_REPLY_ACK:
624 if (mode == MODE_I2C_READ) {
625 *read_byte = reply[1];
627 return reply_bytes - 1;
628 case AUX_I2C_REPLY_NACK:
629 DRM_DEBUG_KMS("aux_i2c nack\n");
631 case AUX_I2C_REPLY_DEFER:
632 DRM_DEBUG_KMS("aux_i2c defer\n");
636 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
641 DRM_ERROR("too many retries, giving up\n");
645 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
646 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
649 intel_dp_i2c_init(struct intel_dp *intel_dp,
650 struct intel_connector *intel_connector, const char *name)
654 DRM_DEBUG_KMS("i2c_init %s\n", name);
655 intel_dp->algo.running = false;
656 intel_dp->algo.address = 0;
657 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
659 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
660 intel_dp->adapter.owner = THIS_MODULE;
661 intel_dp->adapter.class = I2C_CLASS_DDC;
662 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
663 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
664 intel_dp->adapter.algo_data = &intel_dp->algo;
665 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
667 ironlake_edp_panel_vdd_on(intel_dp);
668 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
669 ironlake_edp_panel_vdd_off(intel_dp, false);
674 intel_dp_mode_fixup(struct drm_encoder *encoder,
675 const struct drm_display_mode *mode,
676 struct drm_display_mode *adjusted_mode)
678 struct drm_device *dev = encoder->dev;
679 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
680 int lane_count, clock;
681 int max_lane_count = intel_dp_max_lane_count(intel_dp);
682 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
684 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
686 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
687 intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
688 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
689 mode, adjusted_mode);
692 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
695 DRM_DEBUG_KMS("DP link computation with max lane count %i "
696 "max bw %02x pixel clock %iKHz\n",
697 max_lane_count, bws[max_clock], adjusted_mode->clock);
699 if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true))
702 bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
703 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
705 for (clock = 0; clock <= max_clock; clock++) {
706 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
707 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
709 if (mode_rate <= link_avail) {
710 intel_dp->link_bw = bws[clock];
711 intel_dp->lane_count = lane_count;
712 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
713 DRM_DEBUG_KMS("DP link bw %02x lane "
714 "count %d clock %d bpp %d\n",
715 intel_dp->link_bw, intel_dp->lane_count,
716 adjusted_mode->clock, bpp);
717 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
718 mode_rate, link_avail);
727 struct intel_dp_m_n {
736 intel_reduce_ratio(uint32_t *num, uint32_t *den)
738 while (*num > 0xffffff || *den > 0xffffff) {
745 intel_dp_compute_m_n(int bpp,
749 struct intel_dp_m_n *m_n)
752 m_n->gmch_m = (pixel_clock * bpp) >> 3;
753 m_n->gmch_n = link_clock * nlanes;
754 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
755 m_n->link_m = pixel_clock;
756 m_n->link_n = link_clock;
757 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
761 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
762 struct drm_display_mode *adjusted_mode)
764 struct drm_device *dev = crtc->dev;
765 struct intel_encoder *encoder;
766 struct drm_i915_private *dev_priv = dev->dev_private;
767 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
769 struct intel_dp_m_n m_n;
770 int pipe = intel_crtc->pipe;
773 * Find the lane count in the intel_encoder private
775 for_each_encoder_on_crtc(dev, crtc, encoder) {
776 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
778 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
779 intel_dp->base.type == INTEL_OUTPUT_EDP)
781 lane_count = intel_dp->lane_count;
787 * Compute the GMCH and Link ratios. The '3' here is
788 * the number of bytes_per_pixel post-LUT, which we always
789 * set up for 8-bits of R/G/B, or 3 bytes total.
791 intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
792 mode->clock, adjusted_mode->clock, &m_n);
794 if (HAS_PCH_SPLIT(dev)) {
795 I915_WRITE(TRANSDATA_M1(pipe),
796 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
798 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
799 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
800 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
802 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
803 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
805 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
806 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
807 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
812 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
813 struct drm_display_mode *adjusted_mode)
815 struct drm_device *dev = encoder->dev;
816 struct drm_i915_private *dev_priv = dev->dev_private;
817 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
818 struct drm_crtc *crtc = intel_dp->base.base.crtc;
819 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
822 * There are four kinds of DP registers:
829 * IBX PCH and CPU are the same for almost everything,
830 * except that the CPU DP PLL is configured in this
833 * CPT PCH is quite different, having many bits moved
834 * to the TRANS_DP_CTL register instead. That
835 * configuration happens (oddly) in ironlake_pch_enable
838 /* Preserve the BIOS-computed detected bit. This is
839 * supposed to be read-only.
841 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
843 /* Handle DP bits in common between all three register formats */
844 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
846 switch (intel_dp->lane_count) {
848 intel_dp->DP |= DP_PORT_WIDTH_1;
851 intel_dp->DP |= DP_PORT_WIDTH_2;
854 intel_dp->DP |= DP_PORT_WIDTH_4;
857 if (intel_dp->has_audio) {
858 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
859 pipe_name(intel_crtc->pipe));
860 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
861 intel_write_eld(encoder, adjusted_mode);
863 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
864 intel_dp->link_configuration[0] = intel_dp->link_bw;
865 intel_dp->link_configuration[1] = intel_dp->lane_count;
866 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
868 * Check for DPCD version > 1.1 and enhanced framing support
870 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
871 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
872 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
875 /* Split out the IBX/CPU vs CPT settings */
877 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
878 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
879 intel_dp->DP |= DP_SYNC_HS_HIGH;
880 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
881 intel_dp->DP |= DP_SYNC_VS_HIGH;
882 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
884 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
885 intel_dp->DP |= DP_ENHANCED_FRAMING;
887 intel_dp->DP |= intel_crtc->pipe << 29;
889 /* don't miss out required setting for eDP */
890 if (adjusted_mode->clock < 200000)
891 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
893 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
894 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
895 intel_dp->DP |= intel_dp->color_range;
897 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
898 intel_dp->DP |= DP_SYNC_HS_HIGH;
899 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
900 intel_dp->DP |= DP_SYNC_VS_HIGH;
901 intel_dp->DP |= DP_LINK_TRAIN_OFF;
903 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
904 intel_dp->DP |= DP_ENHANCED_FRAMING;
906 if (intel_crtc->pipe == 1)
907 intel_dp->DP |= DP_PIPEB_SELECT;
909 if (is_cpu_edp(intel_dp)) {
910 /* don't miss out required setting for eDP */
911 if (adjusted_mode->clock < 200000)
912 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
914 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
917 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
921 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
922 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
924 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
925 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
927 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
928 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
930 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
934 struct drm_device *dev = intel_dp->base.base.dev;
935 struct drm_i915_private *dev_priv = dev->dev_private;
937 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
939 I915_READ(PCH_PP_STATUS),
940 I915_READ(PCH_PP_CONTROL));
942 if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
943 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
944 I915_READ(PCH_PP_STATUS),
945 I915_READ(PCH_PP_CONTROL));
949 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
951 DRM_DEBUG_KMS("Wait for panel power on\n");
952 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
955 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
957 DRM_DEBUG_KMS("Wait for panel power off time\n");
958 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
961 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
963 DRM_DEBUG_KMS("Wait for panel power cycle\n");
964 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
968 /* Read the current pp_control value, unlocking the register if it
972 static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
974 u32 control = I915_READ(PCH_PP_CONTROL);
976 control &= ~PANEL_UNLOCK_MASK;
977 control |= PANEL_UNLOCK_REGS;
981 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
983 struct drm_device *dev = intel_dp->base.base.dev;
984 struct drm_i915_private *dev_priv = dev->dev_private;
987 if (!is_edp(intel_dp))
989 DRM_DEBUG_KMS("Turn eDP VDD on\n");
991 WARN(intel_dp->want_panel_vdd,
992 "eDP VDD already requested on\n");
994 intel_dp->want_panel_vdd = true;
996 if (ironlake_edp_have_panel_vdd(intel_dp)) {
997 DRM_DEBUG_KMS("eDP VDD already on\n");
1001 if (!ironlake_edp_have_panel_power(intel_dp))
1002 ironlake_wait_panel_power_cycle(intel_dp);
1004 pp = ironlake_get_pp_control(dev_priv);
1005 pp |= EDP_FORCE_VDD;
1006 I915_WRITE(PCH_PP_CONTROL, pp);
1007 POSTING_READ(PCH_PP_CONTROL);
1008 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1009 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1012 * If the panel wasn't on, delay before accessing aux channel
1014 if (!ironlake_edp_have_panel_power(intel_dp)) {
1015 DRM_DEBUG_KMS("eDP was not running\n");
1016 msleep(intel_dp->panel_power_up_delay);
1020 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1022 struct drm_device *dev = intel_dp->base.base.dev;
1023 struct drm_i915_private *dev_priv = dev->dev_private;
1026 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1027 pp = ironlake_get_pp_control(dev_priv);
1028 pp &= ~EDP_FORCE_VDD;
1029 I915_WRITE(PCH_PP_CONTROL, pp);
1030 POSTING_READ(PCH_PP_CONTROL);
1032 /* Make sure sequencer is idle before allowing subsequent activity */
1033 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1034 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1036 msleep(intel_dp->panel_power_down_delay);
1040 static void ironlake_panel_vdd_work(struct work_struct *__work)
1042 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1043 struct intel_dp, panel_vdd_work);
1044 struct drm_device *dev = intel_dp->base.base.dev;
1046 mutex_lock(&dev->mode_config.mutex);
1047 ironlake_panel_vdd_off_sync(intel_dp);
1048 mutex_unlock(&dev->mode_config.mutex);
1051 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1053 if (!is_edp(intel_dp))
1056 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1057 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1059 intel_dp->want_panel_vdd = false;
1062 ironlake_panel_vdd_off_sync(intel_dp);
1065 * Queue the timer to fire a long
1066 * time from now (relative to the power down delay)
1067 * to keep the panel power up across a sequence of operations
1069 schedule_delayed_work(&intel_dp->panel_vdd_work,
1070 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1074 static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1076 struct drm_device *dev = intel_dp->base.base.dev;
1077 struct drm_i915_private *dev_priv = dev->dev_private;
1080 if (!is_edp(intel_dp))
1083 DRM_DEBUG_KMS("Turn eDP power on\n");
1085 if (ironlake_edp_have_panel_power(intel_dp)) {
1086 DRM_DEBUG_KMS("eDP power already on\n");
1090 ironlake_wait_panel_power_cycle(intel_dp);
1092 pp = ironlake_get_pp_control(dev_priv);
1094 /* ILK workaround: disable reset around power sequence */
1095 pp &= ~PANEL_POWER_RESET;
1096 I915_WRITE(PCH_PP_CONTROL, pp);
1097 POSTING_READ(PCH_PP_CONTROL);
1100 pp |= POWER_TARGET_ON;
1102 pp |= PANEL_POWER_RESET;
1104 I915_WRITE(PCH_PP_CONTROL, pp);
1105 POSTING_READ(PCH_PP_CONTROL);
1107 ironlake_wait_panel_on(intel_dp);
1110 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1111 I915_WRITE(PCH_PP_CONTROL, pp);
1112 POSTING_READ(PCH_PP_CONTROL);
1116 static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1118 struct drm_device *dev = intel_dp->base.base.dev;
1119 struct drm_i915_private *dev_priv = dev->dev_private;
1122 if (!is_edp(intel_dp))
1125 DRM_DEBUG_KMS("Turn eDP power off\n");
1127 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1129 pp = ironlake_get_pp_control(dev_priv);
1130 /* We need to switch off panel power _and_ force vdd, for otherwise some
1131 * panels get very unhappy and cease to work. */
1132 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1133 I915_WRITE(PCH_PP_CONTROL, pp);
1134 POSTING_READ(PCH_PP_CONTROL);
1136 intel_dp->want_panel_vdd = false;
1138 ironlake_wait_panel_off(intel_dp);
1141 static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1143 struct drm_device *dev = intel_dp->base.base.dev;
1144 struct drm_i915_private *dev_priv = dev->dev_private;
1147 if (!is_edp(intel_dp))
1150 DRM_DEBUG_KMS("\n");
1152 * If we enable the backlight right away following a panel power
1153 * on, we may see slight flicker as the panel syncs with the eDP
1154 * link. So delay a bit to make sure the image is solid before
1155 * allowing it to appear.
1157 msleep(intel_dp->backlight_on_delay);
1158 pp = ironlake_get_pp_control(dev_priv);
1159 pp |= EDP_BLC_ENABLE;
1160 I915_WRITE(PCH_PP_CONTROL, pp);
1161 POSTING_READ(PCH_PP_CONTROL);
1164 static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1166 struct drm_device *dev = intel_dp->base.base.dev;
1167 struct drm_i915_private *dev_priv = dev->dev_private;
1170 if (!is_edp(intel_dp))
1173 DRM_DEBUG_KMS("\n");
1174 pp = ironlake_get_pp_control(dev_priv);
1175 pp &= ~EDP_BLC_ENABLE;
1176 I915_WRITE(PCH_PP_CONTROL, pp);
1177 POSTING_READ(PCH_PP_CONTROL);
1178 msleep(intel_dp->backlight_off_delay);
1181 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1183 struct drm_device *dev = intel_dp->base.base.dev;
1184 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1185 struct drm_i915_private *dev_priv = dev->dev_private;
1188 assert_pipe_disabled(dev_priv,
1189 to_intel_crtc(crtc)->pipe);
1191 DRM_DEBUG_KMS("\n");
1192 dpa_ctl = I915_READ(DP_A);
1193 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1194 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1196 /* We don't adjust intel_dp->DP while tearing down the link, to
1197 * facilitate link retraining (e.g. after hotplug). Hence clear all
1198 * enable bits here to ensure that we don't enable too much. */
1199 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1200 intel_dp->DP |= DP_PLL_ENABLE;
1201 I915_WRITE(DP_A, intel_dp->DP);
1206 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1208 struct drm_device *dev = intel_dp->base.base.dev;
1209 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1210 struct drm_i915_private *dev_priv = dev->dev_private;
1213 assert_pipe_disabled(dev_priv,
1214 to_intel_crtc(crtc)->pipe);
1216 dpa_ctl = I915_READ(DP_A);
1217 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1218 "dp pll off, should be on\n");
1219 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1221 /* We can't rely on the value tracked for the DP register in
1222 * intel_dp->DP because link_down must not change that (otherwise link
1223 * re-training will fail. */
1224 dpa_ctl &= ~DP_PLL_ENABLE;
1225 I915_WRITE(DP_A, dpa_ctl);
1230 /* If the sink supports it, try to set the power state appropriately */
1231 static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1235 /* Should have a valid DPCD by this point */
1236 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1239 if (mode != DRM_MODE_DPMS_ON) {
1240 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1243 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1246 * When turning on, we need to retry for 1ms to give the sink
1249 for (i = 0; i < 3; i++) {
1250 ret = intel_dp_aux_native_write_1(intel_dp,
1260 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1263 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1264 struct drm_device *dev = encoder->base.dev;
1265 struct drm_i915_private *dev_priv = dev->dev_private;
1266 u32 tmp = I915_READ(intel_dp->output_reg);
1268 if (!(tmp & DP_PORT_EN))
1271 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
1272 *pipe = PORT_TO_PIPE_CPT(tmp);
1273 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1274 *pipe = PORT_TO_PIPE(tmp);
1280 switch (intel_dp->output_reg) {
1282 trans_sel = TRANS_DP_PORT_SEL_B;
1285 trans_sel = TRANS_DP_PORT_SEL_C;
1288 trans_sel = TRANS_DP_PORT_SEL_D;
1295 trans_dp = I915_READ(TRANS_DP_CTL(i));
1296 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1303 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", intel_dp->output_reg);
1308 static void intel_disable_dp(struct intel_encoder *encoder)
1310 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1312 /* Make sure the panel is off before trying to change the mode. But also
1313 * ensure that we have vdd while we switch off the panel. */
1314 ironlake_edp_panel_vdd_on(intel_dp);
1315 ironlake_edp_backlight_off(intel_dp);
1316 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1317 ironlake_edp_panel_off(intel_dp);
1319 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1320 if (!is_cpu_edp(intel_dp))
1321 intel_dp_link_down(intel_dp);
1324 static void intel_post_disable_dp(struct intel_encoder *encoder)
1326 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1328 if (is_cpu_edp(intel_dp)) {
1329 intel_dp_link_down(intel_dp);
1330 ironlake_edp_pll_off(intel_dp);
1334 static void intel_enable_dp(struct intel_encoder *encoder)
1336 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1337 struct drm_device *dev = encoder->base.dev;
1338 struct drm_i915_private *dev_priv = dev->dev_private;
1339 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1341 if (WARN_ON(dp_reg & DP_PORT_EN))
1344 ironlake_edp_panel_vdd_on(intel_dp);
1345 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1346 intel_dp_start_link_train(intel_dp);
1347 ironlake_edp_panel_on(intel_dp);
1348 ironlake_edp_panel_vdd_off(intel_dp, true);
1349 intel_dp_complete_link_train(intel_dp);
1350 ironlake_edp_backlight_on(intel_dp);
1353 static void intel_pre_enable_dp(struct intel_encoder *encoder)
1355 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1357 if (is_cpu_edp(intel_dp))
1358 ironlake_edp_pll_on(intel_dp);
1362 * Native read with retry for link status and receiver capability reads for
1363 * cases where the sink may still be asleep.
1366 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1367 uint8_t *recv, int recv_bytes)
1372 * Sinks are *supposed* to come up within 1ms from an off state,
1373 * but we're also supposed to retry 3 times per the spec.
1375 for (i = 0; i < 3; i++) {
1376 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1378 if (ret == recv_bytes)
1387 * Fetch AUX CH registers 0x202 - 0x207 which contain
1388 * link status information
1391 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1393 return intel_dp_aux_native_read_retry(intel_dp,
1396 DP_LINK_STATUS_SIZE);
1400 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1403 return link_status[r - DP_LANE0_1_STATUS];
1407 intel_get_adjust_request_voltage(uint8_t adjust_request[2],
1410 int s = ((lane & 1) ?
1411 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1412 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1413 uint8_t l = adjust_request[lane>>1];
1415 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1419 intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2],
1422 int s = ((lane & 1) ?
1423 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1424 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1425 uint8_t l = adjust_request[lane>>1];
1427 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1432 static char *voltage_names[] = {
1433 "0.4V", "0.6V", "0.8V", "1.2V"
1435 static char *pre_emph_names[] = {
1436 "0dB", "3.5dB", "6dB", "9.5dB"
1438 static char *link_train_names[] = {
1439 "pattern 1", "pattern 2", "idle", "off"
1444 * These are source-specific values; current Intel hardware supports
1445 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1449 intel_dp_voltage_max(struct intel_dp *intel_dp)
1451 struct drm_device *dev = intel_dp->base.base.dev;
1453 if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1454 return DP_TRAIN_VOLTAGE_SWING_800;
1455 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1456 return DP_TRAIN_VOLTAGE_SWING_1200;
1458 return DP_TRAIN_VOLTAGE_SWING_800;
1462 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1464 struct drm_device *dev = intel_dp->base.base.dev;
1466 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1467 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1468 case DP_TRAIN_VOLTAGE_SWING_400:
1469 return DP_TRAIN_PRE_EMPHASIS_6;
1470 case DP_TRAIN_VOLTAGE_SWING_600:
1471 case DP_TRAIN_VOLTAGE_SWING_800:
1472 return DP_TRAIN_PRE_EMPHASIS_3_5;
1474 return DP_TRAIN_PRE_EMPHASIS_0;
1477 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1478 case DP_TRAIN_VOLTAGE_SWING_400:
1479 return DP_TRAIN_PRE_EMPHASIS_6;
1480 case DP_TRAIN_VOLTAGE_SWING_600:
1481 return DP_TRAIN_PRE_EMPHASIS_6;
1482 case DP_TRAIN_VOLTAGE_SWING_800:
1483 return DP_TRAIN_PRE_EMPHASIS_3_5;
1484 case DP_TRAIN_VOLTAGE_SWING_1200:
1486 return DP_TRAIN_PRE_EMPHASIS_0;
1492 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1497 uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS);
1498 uint8_t voltage_max;
1499 uint8_t preemph_max;
1501 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1502 uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane);
1503 uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane);
1511 voltage_max = intel_dp_voltage_max(intel_dp);
1512 if (v >= voltage_max)
1513 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1515 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1516 if (p >= preemph_max)
1517 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1519 for (lane = 0; lane < 4; lane++)
1520 intel_dp->train_set[lane] = v | p;
1524 intel_dp_signal_levels(uint8_t train_set)
1526 uint32_t signal_levels = 0;
1528 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1529 case DP_TRAIN_VOLTAGE_SWING_400:
1531 signal_levels |= DP_VOLTAGE_0_4;
1533 case DP_TRAIN_VOLTAGE_SWING_600:
1534 signal_levels |= DP_VOLTAGE_0_6;
1536 case DP_TRAIN_VOLTAGE_SWING_800:
1537 signal_levels |= DP_VOLTAGE_0_8;
1539 case DP_TRAIN_VOLTAGE_SWING_1200:
1540 signal_levels |= DP_VOLTAGE_1_2;
1543 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1544 case DP_TRAIN_PRE_EMPHASIS_0:
1546 signal_levels |= DP_PRE_EMPHASIS_0;
1548 case DP_TRAIN_PRE_EMPHASIS_3_5:
1549 signal_levels |= DP_PRE_EMPHASIS_3_5;
1551 case DP_TRAIN_PRE_EMPHASIS_6:
1552 signal_levels |= DP_PRE_EMPHASIS_6;
1554 case DP_TRAIN_PRE_EMPHASIS_9_5:
1555 signal_levels |= DP_PRE_EMPHASIS_9_5;
1558 return signal_levels;
1561 /* Gen6's DP voltage swing and pre-emphasis control */
1563 intel_gen6_edp_signal_levels(uint8_t train_set)
1565 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1566 DP_TRAIN_PRE_EMPHASIS_MASK);
1567 switch (signal_levels) {
1568 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1569 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1570 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1571 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1572 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1573 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1574 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1575 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1576 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1577 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1578 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1579 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1580 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1581 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1583 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1584 "0x%x\n", signal_levels);
1585 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1589 /* Gen7's DP voltage swing and pre-emphasis control */
1591 intel_gen7_edp_signal_levels(uint8_t train_set)
1593 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1594 DP_TRAIN_PRE_EMPHASIS_MASK);
1595 switch (signal_levels) {
1596 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1597 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1598 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1599 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1600 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1601 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1603 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1604 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1605 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1606 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1608 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1609 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1610 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1611 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1614 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1615 "0x%x\n", signal_levels);
1616 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1621 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1624 int s = (lane & 1) * 4;
1625 uint8_t l = link_status[lane>>1];
1627 return (l >> s) & 0xf;
1630 /* Check for clock recovery is done on all channels */
1632 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1635 uint8_t lane_status;
1637 for (lane = 0; lane < lane_count; lane++) {
1638 lane_status = intel_get_lane_status(link_status, lane);
1639 if ((lane_status & DP_LANE_CR_DONE) == 0)
1645 /* Check to see if channel eq is done on all channels */
1646 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1647 DP_LANE_CHANNEL_EQ_DONE|\
1648 DP_LANE_SYMBOL_LOCKED)
1650 intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1653 uint8_t lane_status;
1656 lane_align = intel_dp_link_status(link_status,
1657 DP_LANE_ALIGN_STATUS_UPDATED);
1658 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1660 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1661 lane_status = intel_get_lane_status(link_status, lane);
1662 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1669 intel_dp_set_link_train(struct intel_dp *intel_dp,
1670 uint32_t dp_reg_value,
1671 uint8_t dp_train_pat)
1673 struct drm_device *dev = intel_dp->base.base.dev;
1674 struct drm_i915_private *dev_priv = dev->dev_private;
1677 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1678 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1680 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1681 case DP_TRAINING_PATTERN_DISABLE:
1682 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1684 case DP_TRAINING_PATTERN_1:
1685 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1687 case DP_TRAINING_PATTERN_2:
1688 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1690 case DP_TRAINING_PATTERN_3:
1691 DRM_ERROR("DP training pattern 3 not supported\n");
1692 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1697 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1699 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1700 case DP_TRAINING_PATTERN_DISABLE:
1701 dp_reg_value |= DP_LINK_TRAIN_OFF;
1703 case DP_TRAINING_PATTERN_1:
1704 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1706 case DP_TRAINING_PATTERN_2:
1707 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1709 case DP_TRAINING_PATTERN_3:
1710 DRM_ERROR("DP training pattern 3 not supported\n");
1711 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1716 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1717 POSTING_READ(intel_dp->output_reg);
1719 intel_dp_aux_native_write_1(intel_dp,
1720 DP_TRAINING_PATTERN_SET,
1723 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1724 DP_TRAINING_PATTERN_DISABLE) {
1725 ret = intel_dp_aux_native_write(intel_dp,
1726 DP_TRAINING_LANE0_SET,
1727 intel_dp->train_set,
1728 intel_dp->lane_count);
1729 if (ret != intel_dp->lane_count)
1736 /* Enable corresponding port and start training pattern 1 */
1738 intel_dp_start_link_train(struct intel_dp *intel_dp)
1740 struct drm_device *dev = intel_dp->base.base.dev;
1743 bool clock_recovery = false;
1744 int voltage_tries, loop_tries;
1745 uint32_t DP = intel_dp->DP;
1747 /* Write the link configuration data */
1748 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1749 intel_dp->link_configuration,
1750 DP_LINK_CONFIGURATION_SIZE);
1754 memset(intel_dp->train_set, 0, 4);
1758 clock_recovery = false;
1760 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1761 uint8_t link_status[DP_LINK_STATUS_SIZE];
1762 uint32_t signal_levels;
1765 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1766 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1767 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1768 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1769 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1770 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1772 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1773 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels);
1774 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1777 if (!intel_dp_set_link_train(intel_dp, DP,
1778 DP_TRAINING_PATTERN_1 |
1779 DP_LINK_SCRAMBLING_DISABLE))
1781 /* Set training pattern 1 */
1784 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1785 DRM_ERROR("failed to get link status\n");
1789 if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1790 DRM_DEBUG_KMS("clock recovery OK\n");
1791 clock_recovery = true;
1795 /* Check to see if we've tried the max voltage */
1796 for (i = 0; i < intel_dp->lane_count; i++)
1797 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1799 if (i == intel_dp->lane_count && voltage_tries == 5) {
1801 if (loop_tries == 5) {
1802 DRM_DEBUG_KMS("too many full retries, give up\n");
1805 memset(intel_dp->train_set, 0, 4);
1810 /* Check to see if we've tried the same voltage 5 times */
1811 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1813 if (voltage_tries == 5) {
1814 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1819 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1821 /* Compute new intel_dp->train_set as requested by target */
1822 intel_get_adjust_train(intel_dp, link_status);
1829 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1831 struct drm_device *dev = intel_dp->base.base.dev;
1832 bool channel_eq = false;
1833 int tries, cr_tries;
1834 uint32_t DP = intel_dp->DP;
1836 /* channel equalization */
1841 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1842 uint32_t signal_levels;
1843 uint8_t link_status[DP_LINK_STATUS_SIZE];
1846 DRM_ERROR("failed to train DP, aborting\n");
1847 intel_dp_link_down(intel_dp);
1851 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1852 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1853 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1854 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1855 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1856 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1858 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1859 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1862 /* channel eq pattern */
1863 if (!intel_dp_set_link_train(intel_dp, DP,
1864 DP_TRAINING_PATTERN_2 |
1865 DP_LINK_SCRAMBLING_DISABLE))
1869 if (!intel_dp_get_link_status(intel_dp, link_status))
1872 /* Make sure clock is still ok */
1873 if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1874 intel_dp_start_link_train(intel_dp);
1879 if (intel_channel_eq_ok(intel_dp, link_status)) {
1884 /* Try 5 times, then try clock recovery if that fails */
1886 intel_dp_link_down(intel_dp);
1887 intel_dp_start_link_train(intel_dp);
1893 /* Compute new intel_dp->train_set as requested by target */
1894 intel_get_adjust_train(intel_dp, link_status);
1898 intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
1902 intel_dp_link_down(struct intel_dp *intel_dp)
1904 struct drm_device *dev = intel_dp->base.base.dev;
1905 struct drm_i915_private *dev_priv = dev->dev_private;
1906 uint32_t DP = intel_dp->DP;
1908 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1911 DRM_DEBUG_KMS("\n");
1913 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1914 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1915 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1917 DP &= ~DP_LINK_TRAIN_MASK;
1918 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1920 POSTING_READ(intel_dp->output_reg);
1924 if (HAS_PCH_IBX(dev) &&
1925 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
1926 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1928 /* Hardware workaround: leaving our transcoder select
1929 * set to transcoder B while it's off will prevent the
1930 * corresponding HDMI output on transcoder A.
1932 * Combine this with another hardware workaround:
1933 * transcoder select bit can only be cleared while the
1936 DP &= ~DP_PIPEB_SELECT;
1937 I915_WRITE(intel_dp->output_reg, DP);
1939 /* Changes to enable or select take place the vblank
1940 * after being written.
1943 /* We can arrive here never having been attached
1944 * to a CRTC, for instance, due to inheriting
1945 * random state from the BIOS.
1947 * If the pipe is not running, play safe and
1948 * wait for the clocks to stabilise before
1951 POSTING_READ(intel_dp->output_reg);
1954 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
1957 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
1958 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1959 POSTING_READ(intel_dp->output_reg);
1960 msleep(intel_dp->panel_power_down_delay);
1964 intel_dp_get_dpcd(struct intel_dp *intel_dp)
1966 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
1967 sizeof(intel_dp->dpcd)) == 0)
1968 return false; /* aux transfer failed */
1970 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
1971 return false; /* DPCD not present */
1973 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
1974 DP_DWN_STRM_PORT_PRESENT))
1975 return true; /* native DP sink */
1977 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
1978 return true; /* no per-port downstream info */
1980 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
1981 intel_dp->downstream_ports,
1982 DP_MAX_DOWNSTREAM_PORTS) == 0)
1983 return false; /* downstream port status fetch failed */
1989 intel_dp_probe_oui(struct intel_dp *intel_dp)
1993 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
1996 ironlake_edp_panel_vdd_on(intel_dp);
1998 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
1999 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2000 buf[0], buf[1], buf[2]);
2002 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2003 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2004 buf[0], buf[1], buf[2]);
2006 ironlake_edp_panel_vdd_off(intel_dp, false);
2010 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2014 ret = intel_dp_aux_native_read_retry(intel_dp,
2015 DP_DEVICE_SERVICE_IRQ_VECTOR,
2016 sink_irq_vector, 1);
2024 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2026 /* NAK by default */
2027 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK);
2031 * According to DP spec
2034 * 2. Configure link according to Receiver Capabilities
2035 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2036 * 4. Check link status on receipt of hot-plug interrupt
2040 intel_dp_check_link_status(struct intel_dp *intel_dp)
2043 u8 link_status[DP_LINK_STATUS_SIZE];
2045 if (!intel_dp->base.connectors_active)
2048 if (WARN_ON(!intel_dp->base.base.crtc))
2051 /* Try to read receiver status if the link appears to be up */
2052 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2053 intel_dp_link_down(intel_dp);
2057 /* Now read the DPCD to see if it's actually running */
2058 if (!intel_dp_get_dpcd(intel_dp)) {
2059 intel_dp_link_down(intel_dp);
2063 /* Try to read the source of the interrupt */
2064 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2065 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2066 /* Clear interrupt source */
2067 intel_dp_aux_native_write_1(intel_dp,
2068 DP_DEVICE_SERVICE_IRQ_VECTOR,
2071 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2072 intel_dp_handle_test_request(intel_dp);
2073 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2074 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2077 if (!intel_channel_eq_ok(intel_dp, link_status)) {
2078 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2079 drm_get_encoder_name(&intel_dp->base.base));
2080 intel_dp_start_link_train(intel_dp);
2081 intel_dp_complete_link_train(intel_dp);
2085 /* XXX this is probably wrong for multiple downstream ports */
2086 static enum drm_connector_status
2087 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2089 uint8_t *dpcd = intel_dp->dpcd;
2093 if (!intel_dp_get_dpcd(intel_dp))
2094 return connector_status_disconnected;
2096 /* if there's no downstream port, we're done */
2097 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2098 return connector_status_connected;
2100 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2101 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2104 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2106 return connector_status_unknown;
2107 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2108 : connector_status_disconnected;
2111 /* If no HPD, poke DDC gently */
2112 if (drm_probe_ddc(&intel_dp->adapter))
2113 return connector_status_connected;
2115 /* Well we tried, say unknown for unreliable port types */
2116 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2117 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2118 return connector_status_unknown;
2120 /* Anything else is out of spec, warn and ignore */
2121 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2122 return connector_status_disconnected;
2125 static enum drm_connector_status
2126 ironlake_dp_detect(struct intel_dp *intel_dp)
2128 enum drm_connector_status status;
2130 /* Can't disconnect eDP, but you can close the lid... */
2131 if (is_edp(intel_dp)) {
2132 status = intel_panel_detect(intel_dp->base.base.dev);
2133 if (status == connector_status_unknown)
2134 status = connector_status_connected;
2138 return intel_dp_detect_dpcd(intel_dp);
2141 static enum drm_connector_status
2142 g4x_dp_detect(struct intel_dp *intel_dp)
2144 struct drm_device *dev = intel_dp->base.base.dev;
2145 struct drm_i915_private *dev_priv = dev->dev_private;
2148 switch (intel_dp->output_reg) {
2150 bit = DPB_HOTPLUG_LIVE_STATUS;
2153 bit = DPC_HOTPLUG_LIVE_STATUS;
2156 bit = DPD_HOTPLUG_LIVE_STATUS;
2159 return connector_status_unknown;
2162 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2163 return connector_status_disconnected;
2165 return intel_dp_detect_dpcd(intel_dp);
2168 static struct edid *
2169 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2171 struct intel_dp *intel_dp = intel_attached_dp(connector);
2175 if (is_edp(intel_dp)) {
2176 if (!intel_dp->edid)
2179 size = (intel_dp->edid->extensions + 1) * EDID_LENGTH;
2180 edid = kmalloc(size, GFP_KERNEL);
2184 memcpy(edid, intel_dp->edid, size);
2188 edid = drm_get_edid(connector, adapter);
2193 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2195 struct intel_dp *intel_dp = intel_attached_dp(connector);
2198 if (is_edp(intel_dp)) {
2199 drm_mode_connector_update_edid_property(connector,
2201 ret = drm_add_edid_modes(connector, intel_dp->edid);
2202 drm_edid_to_eld(connector,
2204 return intel_dp->edid_mode_count;
2207 ret = intel_ddc_get_modes(connector, adapter);
2213 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2215 * \return true if DP port is connected.
2216 * \return false if DP port is disconnected.
2218 static enum drm_connector_status
2219 intel_dp_detect(struct drm_connector *connector, bool force)
2221 struct intel_dp *intel_dp = intel_attached_dp(connector);
2222 struct drm_device *dev = intel_dp->base.base.dev;
2223 enum drm_connector_status status;
2224 struct edid *edid = NULL;
2226 intel_dp->has_audio = false;
2228 if (HAS_PCH_SPLIT(dev))
2229 status = ironlake_dp_detect(intel_dp);
2231 status = g4x_dp_detect(intel_dp);
2233 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2234 intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
2235 intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
2236 intel_dp->dpcd[6], intel_dp->dpcd[7]);
2238 if (status != connector_status_connected)
2241 intel_dp_probe_oui(intel_dp);
2243 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2244 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2246 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2248 intel_dp->has_audio = drm_detect_monitor_audio(edid);
2253 return connector_status_connected;
2256 static int intel_dp_get_modes(struct drm_connector *connector)
2258 struct intel_dp *intel_dp = intel_attached_dp(connector);
2259 struct drm_device *dev = intel_dp->base.base.dev;
2260 struct drm_i915_private *dev_priv = dev->dev_private;
2263 /* We should parse the EDID data and find out if it has an audio sink
2266 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2268 if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
2269 struct drm_display_mode *newmode;
2270 list_for_each_entry(newmode, &connector->probed_modes,
2272 if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) {
2273 intel_dp->panel_fixed_mode =
2274 drm_mode_duplicate(dev, newmode);
2282 /* if eDP has no EDID, try to use fixed panel mode from VBT */
2283 if (is_edp(intel_dp)) {
2284 /* initialize panel mode from VBT if available for eDP */
2285 if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
2286 intel_dp->panel_fixed_mode =
2287 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2288 if (intel_dp->panel_fixed_mode) {
2289 intel_dp->panel_fixed_mode->type |=
2290 DRM_MODE_TYPE_PREFERRED;
2293 if (intel_dp->panel_fixed_mode) {
2294 struct drm_display_mode *mode;
2295 mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
2296 drm_mode_probed_add(connector, mode);
2304 intel_dp_detect_audio(struct drm_connector *connector)
2306 struct intel_dp *intel_dp = intel_attached_dp(connector);
2308 bool has_audio = false;
2310 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2312 has_audio = drm_detect_monitor_audio(edid);
2320 intel_dp_set_property(struct drm_connector *connector,
2321 struct drm_property *property,
2324 struct drm_i915_private *dev_priv = connector->dev->dev_private;
2325 struct intel_dp *intel_dp = intel_attached_dp(connector);
2328 ret = drm_connector_property_set_value(connector, property, val);
2332 if (property == dev_priv->force_audio_property) {
2336 if (i == intel_dp->force_audio)
2339 intel_dp->force_audio = i;
2341 if (i == HDMI_AUDIO_AUTO)
2342 has_audio = intel_dp_detect_audio(connector);
2344 has_audio = (i == HDMI_AUDIO_ON);
2346 if (has_audio == intel_dp->has_audio)
2349 intel_dp->has_audio = has_audio;
2353 if (property == dev_priv->broadcast_rgb_property) {
2354 if (val == !!intel_dp->color_range)
2357 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2364 if (intel_dp->base.base.crtc) {
2365 struct drm_crtc *crtc = intel_dp->base.base.crtc;
2366 intel_set_mode(crtc, &crtc->mode,
2367 crtc->x, crtc->y, crtc->fb);
2374 intel_dp_destroy(struct drm_connector *connector)
2376 struct drm_device *dev = connector->dev;
2377 struct intel_dp *intel_dp = intel_attached_dp(connector);
2379 if (is_edp(intel_dp))
2380 intel_panel_destroy_backlight(dev);
2382 drm_sysfs_connector_remove(connector);
2383 drm_connector_cleanup(connector);
2387 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2389 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2391 i2c_del_adapter(&intel_dp->adapter);
2392 drm_encoder_cleanup(encoder);
2393 if (is_edp(intel_dp)) {
2394 kfree(intel_dp->edid);
2395 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2396 ironlake_panel_vdd_off_sync(intel_dp);
2401 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2402 .mode_fixup = intel_dp_mode_fixup,
2403 .mode_set = intel_dp_mode_set,
2404 .disable = intel_encoder_noop,
2407 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2408 .dpms = intel_connector_dpms,
2409 .detect = intel_dp_detect,
2410 .fill_modes = drm_helper_probe_single_connector_modes,
2411 .set_property = intel_dp_set_property,
2412 .destroy = intel_dp_destroy,
2415 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2416 .get_modes = intel_dp_get_modes,
2417 .mode_valid = intel_dp_mode_valid,
2418 .best_encoder = intel_best_encoder,
2421 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2422 .destroy = intel_dp_encoder_destroy,
2426 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2428 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
2430 intel_dp_check_link_status(intel_dp);
2433 /* Return which DP Port should be selected for Transcoder DP control */
2435 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2437 struct drm_device *dev = crtc->dev;
2438 struct intel_encoder *encoder;
2440 for_each_encoder_on_crtc(dev, crtc, encoder) {
2441 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2443 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
2444 intel_dp->base.type == INTEL_OUTPUT_EDP)
2445 return intel_dp->output_reg;
2451 /* check the VBT to see whether the eDP is on DP-D port */
2452 bool intel_dpd_is_edp(struct drm_device *dev)
2454 struct drm_i915_private *dev_priv = dev->dev_private;
2455 struct child_device_config *p_child;
2458 if (!dev_priv->child_dev_num)
2461 for (i = 0; i < dev_priv->child_dev_num; i++) {
2462 p_child = dev_priv->child_dev + i;
2464 if (p_child->dvo_port == PORT_IDPD &&
2465 p_child->device_type == DEVICE_TYPE_eDP)
2472 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2474 intel_attach_force_audio_property(connector);
2475 intel_attach_broadcast_rgb_property(connector);
2479 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
2481 struct drm_i915_private *dev_priv = dev->dev_private;
2482 struct drm_connector *connector;
2483 struct intel_dp *intel_dp;
2484 struct intel_encoder *intel_encoder;
2485 struct intel_connector *intel_connector;
2486 const char *name = NULL;
2489 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2493 intel_dp->output_reg = output_reg;
2494 intel_dp->port = port;
2495 /* Preserve the current hw state. */
2496 intel_dp->DP = I915_READ(intel_dp->output_reg);
2498 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2499 if (!intel_connector) {
2503 intel_encoder = &intel_dp->base;
2505 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
2506 if (intel_dpd_is_edp(dev))
2507 intel_dp->is_pch_edp = true;
2509 if (output_reg == DP_A || is_pch_edp(intel_dp)) {
2510 type = DRM_MODE_CONNECTOR_eDP;
2511 intel_encoder->type = INTEL_OUTPUT_EDP;
2513 type = DRM_MODE_CONNECTOR_DisplayPort;
2514 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2517 connector = &intel_connector->base;
2518 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2519 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2521 connector->polled = DRM_CONNECTOR_POLL_HPD;
2523 intel_encoder->cloneable = false;
2525 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2526 ironlake_panel_vdd_work);
2528 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2530 connector->interlace_allowed = true;
2531 connector->doublescan_allowed = 0;
2533 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2534 DRM_MODE_ENCODER_TMDS);
2535 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
2537 intel_connector_attach_encoder(intel_connector, intel_encoder);
2538 drm_sysfs_connector_add(connector);
2540 intel_encoder->enable = intel_enable_dp;
2541 intel_encoder->pre_enable = intel_pre_enable_dp;
2542 intel_encoder->disable = intel_disable_dp;
2543 intel_encoder->post_disable = intel_post_disable_dp;
2544 intel_encoder->get_hw_state = intel_dp_get_hw_state;
2545 intel_connector->get_hw_state = intel_connector_get_hw_state;
2547 /* Set up the DDC bus. */
2553 dev_priv->hotplug_supported_mask |= DPB_HOTPLUG_INT_STATUS;
2557 dev_priv->hotplug_supported_mask |= DPC_HOTPLUG_INT_STATUS;
2561 dev_priv->hotplug_supported_mask |= DPD_HOTPLUG_INT_STATUS;
2565 WARN(1, "Invalid port %c\n", port_name(port));
2569 /* Cache some DPCD data in the eDP case */
2570 if (is_edp(intel_dp)) {
2571 struct edp_power_seq cur, vbt;
2572 u32 pp_on, pp_off, pp_div;
2574 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2575 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2576 pp_div = I915_READ(PCH_PP_DIVISOR);
2578 if (!pp_on || !pp_off || !pp_div) {
2579 DRM_INFO("bad panel power sequencing delays, disabling panel\n");
2580 intel_dp_encoder_destroy(&intel_dp->base.base);
2581 intel_dp_destroy(&intel_connector->base);
2585 /* Pull timing values out of registers */
2586 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2587 PANEL_POWER_UP_DELAY_SHIFT;
2589 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2590 PANEL_LIGHT_ON_DELAY_SHIFT;
2592 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2593 PANEL_LIGHT_OFF_DELAY_SHIFT;
2595 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2596 PANEL_POWER_DOWN_DELAY_SHIFT;
2598 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2599 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2601 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2602 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2604 vbt = dev_priv->edp.pps;
2606 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2607 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2609 #define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10)
2611 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2612 intel_dp->backlight_on_delay = get_delay(t8);
2613 intel_dp->backlight_off_delay = get_delay(t9);
2614 intel_dp->panel_power_down_delay = get_delay(t10);
2615 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2617 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2618 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2619 intel_dp->panel_power_cycle_delay);
2621 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2622 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2625 intel_dp_i2c_init(intel_dp, intel_connector, name);
2627 if (is_edp(intel_dp)) {
2631 ironlake_edp_panel_vdd_on(intel_dp);
2632 ret = intel_dp_get_dpcd(intel_dp);
2633 ironlake_edp_panel_vdd_off(intel_dp, false);
2636 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2637 dev_priv->no_aux_handshake =
2638 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2639 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2641 /* if this fails, presume the device is a ghost */
2642 DRM_INFO("failed to retrieve link info, disabling eDP\n");
2643 intel_dp_encoder_destroy(&intel_dp->base.base);
2644 intel_dp_destroy(&intel_connector->base);
2648 ironlake_edp_panel_vdd_on(intel_dp);
2649 edid = drm_get_edid(connector, &intel_dp->adapter);
2651 drm_mode_connector_update_edid_property(connector,
2653 intel_dp->edid_mode_count =
2654 drm_add_edid_modes(connector, edid);
2655 drm_edid_to_eld(connector, edid);
2656 intel_dp->edid = edid;
2658 ironlake_edp_panel_vdd_off(intel_dp, false);
2661 intel_encoder->hot_plug = intel_dp_hot_plug;
2663 if (is_edp(intel_dp)) {
2664 dev_priv->int_edp_connector = connector;
2665 intel_panel_setup_backlight(dev);
2668 intel_dp_add_properties(intel_dp, connector);
2670 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2671 * 0xd. Failure to do so will result in spurious interrupts being
2672 * generated on the port when a cable is not attached.
2674 if (IS_G4X(dev) && !IS_GM45(dev)) {
2675 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2676 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);