2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <drm/i915_drm.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_fb_helper.h>
36 #include <drm/drm_dp_mst_helper.h>
37 #include <drm/drm_rect.h>
40 * _wait_for - magic (register) wait macro
42 * Does the right thing for modeset paths when run under kdgb or similar atomic
43 * contexts. Note that it's important that we check the condition again after
44 * having timed out, since the timeout could be due to preemption or similar and
45 * we've never had a chance to check the condition before the timeout.
47 #define _wait_for(COND, MS, W) ({ \
48 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
51 if (time_after(jiffies, timeout__)) { \
56 if (W && drm_can_sleep()) { \
65 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
66 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
67 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
68 DIV_ROUND_UP((US), 1000), 0)
70 #define KHz(x) (1000 * (x))
71 #define MHz(x) KHz(1000 * (x))
74 * Display related stuff
77 /* store information about an Ixxx DVO */
78 /* The i830->i865 use multiple DVOs with multiple i2cs */
79 /* the i915, i945 have a single sDVO i2c bus - which is different */
81 /* maximum connectors per crtcs in the mode set */
83 /* Maximum cursor sizes */
84 #define GEN2_CURSOR_WIDTH 64
85 #define GEN2_CURSOR_HEIGHT 64
86 #define MAX_CURSOR_WIDTH 256
87 #define MAX_CURSOR_HEIGHT 256
89 #define INTEL_I2C_BUS_DVO 1
90 #define INTEL_I2C_BUS_SDVO 2
92 /* these are outputs from the chip - integrated only
93 external chips are via DVO or SDVO output */
94 #define INTEL_OUTPUT_UNUSED 0
95 #define INTEL_OUTPUT_ANALOG 1
96 #define INTEL_OUTPUT_DVO 2
97 #define INTEL_OUTPUT_SDVO 3
98 #define INTEL_OUTPUT_LVDS 4
99 #define INTEL_OUTPUT_TVOUT 5
100 #define INTEL_OUTPUT_HDMI 6
101 #define INTEL_OUTPUT_DISPLAYPORT 7
102 #define INTEL_OUTPUT_EDP 8
103 #define INTEL_OUTPUT_DSI 9
104 #define INTEL_OUTPUT_UNKNOWN 10
105 #define INTEL_OUTPUT_DP_MST 11
107 #define INTEL_DVO_CHIP_NONE 0
108 #define INTEL_DVO_CHIP_LVDS 1
109 #define INTEL_DVO_CHIP_TMDS 2
110 #define INTEL_DVO_CHIP_TVOUT 4
112 #define INTEL_DSI_VIDEO_MODE 0
113 #define INTEL_DSI_COMMAND_MODE 1
115 struct intel_framebuffer {
116 struct drm_framebuffer base;
117 struct drm_i915_gem_object *obj;
121 struct drm_fb_helper helper;
122 struct intel_framebuffer *fb;
123 struct list_head fbdev_list;
124 struct drm_display_mode *our_mode;
128 struct intel_encoder {
129 struct drm_encoder base;
131 * The new crtc this encoder will be driven from. Only differs from
132 * base->crtc while a modeset is in progress.
134 struct intel_crtc *new_crtc;
137 unsigned int cloneable;
138 bool connectors_active;
139 void (*hot_plug)(struct intel_encoder *);
140 bool (*compute_config)(struct intel_encoder *,
141 struct intel_crtc_config *);
142 void (*pre_pll_enable)(struct intel_encoder *);
143 void (*pre_enable)(struct intel_encoder *);
144 void (*enable)(struct intel_encoder *);
145 void (*mode_set)(struct intel_encoder *intel_encoder);
146 void (*disable)(struct intel_encoder *);
147 void (*post_disable)(struct intel_encoder *);
148 /* Read out the current hw state of this connector, returning true if
149 * the encoder is active. If the encoder is enabled it also set the pipe
150 * it is connected to in the pipe parameter. */
151 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
152 /* Reconstructs the equivalent mode flags for the current hardware
153 * state. This must be called _after_ display->get_pipe_config has
154 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
155 * be set correctly before calling this function. */
156 void (*get_config)(struct intel_encoder *,
157 struct intel_crtc_config *pipe_config);
159 * Called during system suspend after all pending requests for the
160 * encoder are flushed (for example for DP AUX transactions) and
161 * device interrupts are disabled.
163 void (*suspend)(struct intel_encoder *);
165 enum hpd_pin hpd_pin;
169 struct drm_display_mode *fixed_mode;
170 struct drm_display_mode *downclock_mode;
180 bool combination_mode; /* gen 2/4 only */
182 struct backlight_device *device;
185 void (*backlight_power)(struct intel_connector *, bool enable);
188 struct intel_connector {
189 struct drm_connector base;
191 * The fixed encoder this connector is connected to.
193 struct intel_encoder *encoder;
196 * The new encoder this connector will be driven. Only differs from
197 * encoder while a modeset is in progress.
199 struct intel_encoder *new_encoder;
201 /* Reads out the current hw, returning true if the connector is enabled
202 * and active (i.e. dpms ON state). */
203 bool (*get_hw_state)(struct intel_connector *);
206 * Removes all interfaces through which the connector is accessible
207 * - like sysfs, debugfs entries -, so that no new operations can be
208 * started on the connector. Also makes sure all currently pending
209 * operations finish before returing.
211 void (*unregister)(struct intel_connector *);
213 /* Panel info for eDP and LVDS */
214 struct intel_panel panel;
216 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
218 struct edid *detect_edid;
220 /* since POLL and HPD connectors may use the same HPD line keep the native
221 state of connector->polled in case hotplug storm detection changes it */
224 void *port; /* store this opaque as its illegal to dereference it */
226 struct intel_dp *mst_port;
229 typedef struct dpll {
241 struct intel_plane_state {
242 struct drm_crtc *crtc;
243 struct drm_framebuffer *fb;
246 struct drm_rect clip;
247 struct drm_rect orig_src;
248 struct drm_rect orig_dst;
252 struct intel_plane_config {
258 struct intel_crtc_config {
260 * quirks - bitfield with hw state readout quirks
262 * For various reasons the hw state readout code might not be able to
263 * completely faithfully read out the current state. These cases are
264 * tracked with quirk flags so that fastboot and state checker can act
267 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
268 #define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1) /* mode inherited from firmware */
269 unsigned long quirks;
271 /* User requested mode, only valid as a starting point to
272 * compute adjusted_mode, except in the case of (S)DVO where
273 * it's also for the output timings of the (S)DVO chip.
274 * adjusted_mode will then correspond to the S(DVO) chip's
275 * preferred input timings. */
276 struct drm_display_mode requested_mode;
277 /* Actual pipe timings ie. what we program into the pipe timing
278 * registers. adjusted_mode.crtc_clock is the pipe pixel clock. */
279 struct drm_display_mode adjusted_mode;
281 /* Pipe source size (ie. panel fitter input size)
282 * All planes will be positioned inside this space,
283 * and get clipped at the edges. */
284 int pipe_src_w, pipe_src_h;
286 /* Whether to set up the PCH/FDI. Note that we never allow sharing
287 * between pch encoders and cpu encoders. */
288 bool has_pch_encoder;
290 /* CPU Transcoder for the pipe. Currently this can only differ from the
291 * pipe on Haswell (where we have a special eDP transcoder). */
292 enum transcoder cpu_transcoder;
295 * Use reduced/limited/broadcast rbg range, compressing from the full
296 * range fed into the crtcs.
298 bool limited_color_range;
300 /* DP has a bunch of special case unfortunately, so mark the pipe
304 /* Whether we should send NULL infoframes. Required for audio. */
307 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
308 * has_dp_encoder is set. */
312 * Enable dithering, used when the selected pipe bpp doesn't match the
317 /* Controls for the clock computation, to override various stages. */
320 /* SDVO TV has a bunch of special case. To make multifunction encoders
321 * work correctly, we need to track this at runtime.*/
325 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
326 * required. This is set in the 2nd loop of calling encoder's
327 * ->compute_config if the first pick doesn't work out.
331 /* Settings for the intel dpll used on pretty much everything but
335 /* Selected dpll when shared or DPLL_ID_PRIVATE. */
336 enum intel_dpll_id shared_dpll;
338 /* PORT_CLK_SEL for DDI ports. */
339 uint32_t ddi_pll_sel;
341 /* Actual register state of the dpll, for shared dpll cross-checking. */
342 struct intel_dpll_hw_state dpll_hw_state;
345 struct intel_link_m_n dp_m_n;
347 /* m2_n2 for eDP downclock */
348 struct intel_link_m_n dp_m2_n2;
352 * Frequence the dpll for the port should run at. Differs from the
353 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
354 * already multiplied by pixel_multiplier.
358 /* Used by SDVO (and if we ever fix it, HDMI). */
359 unsigned pixel_multiplier;
361 /* Panel fitter controls for gen2-gen4 + VLV */
365 u32 lvds_border_bits;
368 /* Panel fitter placement and size for Ironlake+ */
376 /* FDI configuration, only valid if has_pch_encoder is set. */
378 struct intel_link_m_n fdi_m_n;
384 bool dp_encoder_is_mst;
388 struct intel_pipe_wm {
389 struct intel_wm_level wm[5];
393 bool sprites_enabled;
397 struct intel_mmio_flip {
403 struct drm_crtc base;
406 u8 lut_r[256], lut_g[256], lut_b[256];
408 * Whether the crtc and the connected output pipeline is active. Implies
409 * that crtc->enabled is set, i.e. the current mode configuration has
410 * some outputs connected to this crtc.
413 unsigned long enabled_power_domains;
414 bool primary_enabled; /* is the primary plane (partially) visible? */
416 struct intel_overlay *overlay;
417 struct intel_unpin_work *unpin_work;
419 atomic_t unpin_work_count;
421 /* Display surface base address adjustement for pageflips. Note that on
422 * gen4+ this only adjusts up to a tile, offsets within a tile are
423 * handled in the hw itself (with the TILEOFF register). */
424 unsigned long dspaddr_offset;
426 struct drm_i915_gem_object *cursor_bo;
427 uint32_t cursor_addr;
428 int16_t cursor_width, cursor_height;
429 uint32_t cursor_cntl;
430 uint32_t cursor_size;
431 uint32_t cursor_base;
433 struct intel_plane_config plane_config;
434 struct intel_crtc_config config;
435 struct intel_crtc_config *new_config;
438 /* reset counter value when the last flip was submitted */
439 unsigned int reset_counter;
441 /* Access to these should be protected by dev_priv->irq_lock. */
442 bool cpu_fifo_underrun_disabled;
443 bool pch_fifo_underrun_disabled;
445 /* per-pipe watermark state */
447 /* watermarks currently being used */
448 struct intel_pipe_wm active;
452 struct intel_mmio_flip mmio_flip;
455 struct intel_plane_wm_parameters {
456 uint32_t horiz_pixels;
457 uint32_t vert_pixels;
458 uint8_t bytes_per_pixel;
464 struct drm_plane base;
467 struct drm_i915_gem_object *obj;
471 unsigned int crtc_w, crtc_h;
472 uint32_t src_x, src_y;
473 uint32_t src_w, src_h;
474 unsigned int rotation;
476 /* Since we need to change the watermarks before/after
477 * enabling/disabling the planes, we need to store the parameters here
478 * as the other pieces of the struct may not reflect the values we want
479 * for the watermark calculations. Currently only Haswell uses this.
481 struct intel_plane_wm_parameters wm;
483 void (*update_plane)(struct drm_plane *plane,
484 struct drm_crtc *crtc,
485 struct drm_framebuffer *fb,
486 struct drm_i915_gem_object *obj,
487 int crtc_x, int crtc_y,
488 unsigned int crtc_w, unsigned int crtc_h,
489 uint32_t x, uint32_t y,
490 uint32_t src_w, uint32_t src_h);
491 void (*disable_plane)(struct drm_plane *plane,
492 struct drm_crtc *crtc);
493 int (*update_colorkey)(struct drm_plane *plane,
494 struct drm_intel_sprite_colorkey *key);
495 void (*get_colorkey)(struct drm_plane *plane,
496 struct drm_intel_sprite_colorkey *key);
499 struct intel_watermark_params {
500 unsigned long fifo_size;
501 unsigned long max_wm;
502 unsigned long default_wm;
503 unsigned long guard_size;
504 unsigned long cacheline_size;
507 struct cxsr_latency {
510 unsigned long fsb_freq;
511 unsigned long mem_freq;
512 unsigned long display_sr;
513 unsigned long display_hpll_disable;
514 unsigned long cursor_sr;
515 unsigned long cursor_hpll_disable;
518 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
519 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
520 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
521 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
522 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
523 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
528 uint32_t color_range;
529 bool color_range_auto;
532 enum hdmi_force_audio force_audio;
533 bool rgb_quant_range_selectable;
534 enum hdmi_picture_aspect aspect_ratio;
535 void (*write_infoframe)(struct drm_encoder *encoder,
536 enum hdmi_infoframe_type type,
537 const void *frame, ssize_t len);
538 void (*set_infoframes)(struct drm_encoder *encoder,
540 struct drm_display_mode *adjusted_mode);
543 struct intel_dp_mst_encoder;
544 #define DP_MAX_DOWNSTREAM_PORTS 0x10
547 * HIGH_RR is the highest eDP panel refresh rate read from EDID
548 * LOW_RR is the lowest eDP panel refresh rate found from EDID
549 * parsing for same resolution.
551 enum edp_drrs_refresh_rate_type {
554 DRRS_MAX_RR, /* RR count */
559 uint32_t aux_ch_ctl_reg;
562 enum hdmi_force_audio force_audio;
563 uint32_t color_range;
564 bool color_range_auto;
567 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
568 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
569 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
570 struct drm_dp_aux aux;
571 uint8_t train_set[4];
572 int panel_power_up_delay;
573 int panel_power_down_delay;
574 int panel_power_cycle_delay;
575 int backlight_on_delay;
576 int backlight_off_delay;
577 struct delayed_work panel_vdd_work;
579 unsigned long last_power_cycle;
580 unsigned long last_power_on;
581 unsigned long last_backlight_off;
583 struct notifier_block edp_notifier;
586 * Pipe whose power sequencer is currently locked into
587 * this port. Only relevant on VLV/CHV.
592 bool can_mst; /* this port supports mst */
594 int active_mst_links;
595 /* connector directly attached - won't be use for modeset in mst world */
596 struct intel_connector *attached_connector;
598 /* mst connector list */
599 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
600 struct drm_dp_mst_topology_mgr mst_mgr;
602 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
604 * This function returns the value we have to program the AUX_CTL
605 * register with to kick off an AUX transaction.
607 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
610 uint32_t aux_clock_divider);
612 enum drrs_support_type type;
613 enum edp_drrs_refresh_rate_type refresh_rate_type;
619 struct intel_digital_port {
620 struct intel_encoder base;
624 struct intel_hdmi hdmi;
625 bool (*hpd_pulse)(struct intel_digital_port *, bool);
628 struct intel_dp_mst_encoder {
629 struct intel_encoder base;
631 struct intel_digital_port *primary;
632 void *port; /* store this opaque as its illegal to dereference it */
636 vlv_dport_to_channel(struct intel_digital_port *dport)
638 switch (dport->port) {
650 vlv_pipe_to_channel(enum pipe pipe)
663 static inline struct drm_crtc *
664 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
666 struct drm_i915_private *dev_priv = dev->dev_private;
667 return dev_priv->pipe_to_crtc_mapping[pipe];
670 static inline struct drm_crtc *
671 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
673 struct drm_i915_private *dev_priv = dev->dev_private;
674 return dev_priv->plane_to_crtc_mapping[plane];
677 struct intel_unpin_work {
678 struct work_struct work;
679 struct drm_crtc *crtc;
680 struct drm_i915_gem_object *old_fb_obj;
681 struct drm_i915_gem_object *pending_flip_obj;
682 struct drm_pending_vblank_event *event;
684 #define INTEL_FLIP_INACTIVE 0
685 #define INTEL_FLIP_PENDING 1
686 #define INTEL_FLIP_COMPLETE 2
689 struct intel_engine_cs *flip_queued_ring;
690 u32 flip_queued_seqno;
691 int flip_queued_vblank;
692 int flip_ready_vblank;
693 bool enable_stall_check;
696 struct intel_set_config {
697 struct drm_encoder **save_connector_encoders;
698 struct drm_crtc **save_encoder_crtcs;
699 bool *save_crtc_enabled;
705 struct intel_load_detect_pipe {
706 struct drm_framebuffer *release_fb;
707 bool load_detect_temp;
711 static inline struct intel_encoder *
712 intel_attached_encoder(struct drm_connector *connector)
714 return to_intel_connector(connector)->encoder;
717 static inline struct intel_digital_port *
718 enc_to_dig_port(struct drm_encoder *encoder)
720 return container_of(encoder, struct intel_digital_port, base.base);
723 static inline struct intel_dp_mst_encoder *
724 enc_to_mst(struct drm_encoder *encoder)
726 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
729 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
731 return &enc_to_dig_port(encoder)->dp;
734 static inline struct intel_digital_port *
735 dp_to_dig_port(struct intel_dp *intel_dp)
737 return container_of(intel_dp, struct intel_digital_port, dp);
740 static inline struct intel_digital_port *
741 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
743 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
748 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
749 enum pipe pipe, bool enable);
750 bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
751 enum transcoder pch_transcoder,
753 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
754 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
755 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
756 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
757 void gen8_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
758 void gen8_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
759 void intel_runtime_pm_disable_interrupts(struct drm_device *dev);
760 void intel_runtime_pm_restore_interrupts(struct drm_device *dev);
761 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
764 * We only use drm_irq_uninstall() at unload and VT switch, so
765 * this is the only thing we need to check.
767 return !dev_priv->pm._irqs_disabled;
770 int intel_get_crtc_scanline(struct intel_crtc *crtc);
771 void i9xx_check_fifo_underruns(struct drm_device *dev);
772 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv);
775 void intel_crt_init(struct drm_device *dev);
779 void intel_prepare_ddi(struct drm_device *dev);
780 void hsw_fdi_link_train(struct drm_crtc *crtc);
781 void intel_ddi_init(struct drm_device *dev, enum port port);
782 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
783 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
784 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
785 void intel_ddi_pll_init(struct drm_device *dev);
786 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
787 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
788 enum transcoder cpu_transcoder);
789 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
790 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
791 bool intel_ddi_pll_select(struct intel_crtc *crtc);
792 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
793 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
794 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
795 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
796 void intel_ddi_get_config(struct intel_encoder *encoder,
797 struct intel_crtc_config *pipe_config);
799 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
800 void intel_ddi_clock_get(struct intel_encoder *encoder,
801 struct intel_crtc_config *pipe_config);
802 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
804 /* intel_display.c */
805 const char *intel_output_name(int output);
806 bool intel_has_pending_fb_unpin(struct drm_device *dev);
807 int intel_pch_rawclk(struct drm_device *dev);
808 void intel_mark_busy(struct drm_device *dev);
809 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
810 struct intel_engine_cs *ring);
811 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
812 unsigned frontbuffer_bits);
813 void intel_frontbuffer_flip_complete(struct drm_device *dev,
814 unsigned frontbuffer_bits);
815 void intel_frontbuffer_flush(struct drm_device *dev,
816 unsigned frontbuffer_bits);
818 * intel_frontbuffer_flip - prepare frontbuffer flip
820 * @frontbuffer_bits: frontbuffer plane tracking bits
822 * This function gets called after scheduling a flip on @obj. This is for
823 * synchronous plane updates which will happen on the next vblank and which will
824 * not get delayed by pending gpu rendering.
826 * Can be called without any locks held.
829 void intel_frontbuffer_flip(struct drm_device *dev,
830 unsigned frontbuffer_bits)
832 intel_frontbuffer_flush(dev, frontbuffer_bits);
835 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire);
836 void intel_mark_idle(struct drm_device *dev);
837 void intel_crtc_restore_mode(struct drm_crtc *crtc);
838 void intel_crtc_control(struct drm_crtc *crtc, bool enable);
839 void intel_crtc_update_dpms(struct drm_crtc *crtc);
840 void intel_encoder_destroy(struct drm_encoder *encoder);
841 void intel_connector_dpms(struct drm_connector *, int mode);
842 bool intel_connector_get_hw_state(struct intel_connector *connector);
843 void intel_modeset_check_state(struct drm_device *dev);
844 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
845 struct intel_digital_port *port);
846 void intel_connector_attach_encoder(struct intel_connector *connector,
847 struct intel_encoder *encoder);
848 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
849 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
850 struct drm_crtc *crtc);
851 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
852 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
853 struct drm_file *file_priv);
854 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
857 intel_wait_for_vblank(struct drm_device *dev, int pipe)
859 drm_wait_one_vblank(dev, pipe);
861 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
862 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
863 struct intel_digital_port *dport);
864 bool intel_get_load_detect_pipe(struct drm_connector *connector,
865 struct drm_display_mode *mode,
866 struct intel_load_detect_pipe *old,
867 struct drm_modeset_acquire_ctx *ctx);
868 void intel_release_load_detect_pipe(struct drm_connector *connector,
869 struct intel_load_detect_pipe *old);
870 int intel_pin_and_fence_fb_obj(struct drm_device *dev,
871 struct drm_i915_gem_object *obj,
872 struct intel_engine_cs *pipelined);
873 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
874 struct drm_framebuffer *
875 __intel_framebuffer_create(struct drm_device *dev,
876 struct drm_mode_fb_cmd2 *mode_cmd,
877 struct drm_i915_gem_object *obj);
878 void intel_prepare_page_flip(struct drm_device *dev, int plane);
879 void intel_finish_page_flip(struct drm_device *dev, int pipe);
880 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
881 void intel_check_page_flip(struct drm_device *dev, int pipe);
883 /* shared dpll functions */
884 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
885 void assert_shared_dpll(struct drm_i915_private *dev_priv,
886 struct intel_shared_dpll *pll,
888 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
889 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
890 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc);
891 void intel_put_shared_dpll(struct intel_crtc *crtc);
893 /* modesetting asserts */
894 void assert_pll(struct drm_i915_private *dev_priv,
895 enum pipe pipe, bool state);
896 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
897 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
898 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
899 enum pipe pipe, bool state);
900 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
901 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
902 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
903 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
904 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
905 void intel_write_eld(struct drm_encoder *encoder,
906 struct drm_display_mode *mode);
907 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
908 unsigned int tiling_mode,
911 void intel_display_handle_reset(struct drm_device *dev);
912 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
913 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
914 void intel_dp_get_m_n(struct intel_crtc *crtc,
915 struct intel_crtc_config *pipe_config);
916 void intel_dp_set_m_n(struct intel_crtc *crtc);
917 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
919 ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
921 bool intel_crtc_active(struct drm_crtc *crtc);
922 void hsw_enable_ips(struct intel_crtc *crtc);
923 void hsw_disable_ips(struct intel_crtc *crtc);
924 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
925 enum intel_display_power_domain
926 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
927 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
928 struct intel_crtc_config *pipe_config);
929 int intel_format_to_fourcc(int format);
930 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
931 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
934 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
935 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
936 struct intel_connector *intel_connector);
937 void intel_dp_start_link_train(struct intel_dp *intel_dp);
938 void intel_dp_complete_link_train(struct intel_dp *intel_dp);
939 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
940 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
941 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
942 void intel_dp_check_link_status(struct intel_dp *intel_dp);
943 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
944 bool intel_dp_compute_config(struct intel_encoder *encoder,
945 struct intel_crtc_config *pipe_config);
946 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
947 bool intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
949 void intel_edp_backlight_on(struct intel_dp *intel_dp);
950 void intel_edp_backlight_off(struct intel_dp *intel_dp);
951 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
952 void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder);
953 void intel_edp_panel_on(struct intel_dp *intel_dp);
954 void intel_edp_panel_off(struct intel_dp *intel_dp);
955 void intel_edp_psr_enable(struct intel_dp *intel_dp);
956 void intel_edp_psr_disable(struct intel_dp *intel_dp);
957 void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate);
958 void intel_edp_psr_invalidate(struct drm_device *dev,
959 unsigned frontbuffer_bits);
960 void intel_edp_psr_flush(struct drm_device *dev,
961 unsigned frontbuffer_bits);
962 void intel_edp_psr_init(struct drm_device *dev);
964 int intel_dp_handle_hpd_irq(struct intel_digital_port *digport, bool long_hpd);
965 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
966 void intel_dp_mst_suspend(struct drm_device *dev);
967 void intel_dp_mst_resume(struct drm_device *dev);
968 int intel_dp_max_link_bw(struct intel_dp *intel_dp);
969 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
970 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
972 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
973 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
975 void intel_dsi_init(struct drm_device *dev);
979 void intel_dvo_init(struct drm_device *dev);
982 /* legacy fbdev emulation in intel_fbdev.c */
983 #ifdef CONFIG_DRM_I915_FBDEV
984 extern int intel_fbdev_init(struct drm_device *dev);
985 extern void intel_fbdev_initial_config(void *data, async_cookie_t cookie);
986 extern void intel_fbdev_fini(struct drm_device *dev);
987 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
988 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
989 extern void intel_fbdev_restore_mode(struct drm_device *dev);
991 static inline int intel_fbdev_init(struct drm_device *dev)
996 static inline void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
1000 static inline void intel_fbdev_fini(struct drm_device *dev)
1004 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1008 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1014 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
1015 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1016 struct intel_connector *intel_connector);
1017 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1018 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1019 struct intel_crtc_config *pipe_config);
1023 void intel_lvds_init(struct drm_device *dev);
1024 bool intel_is_dual_link_lvds(struct drm_device *dev);
1028 int intel_connector_update_modes(struct drm_connector *connector,
1030 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1031 void intel_attach_force_audio_property(struct drm_connector *connector);
1032 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1035 /* intel_overlay.c */
1036 void intel_setup_overlay(struct drm_device *dev);
1037 void intel_cleanup_overlay(struct drm_device *dev);
1038 int intel_overlay_switch_off(struct intel_overlay *overlay);
1039 int intel_overlay_put_image(struct drm_device *dev, void *data,
1040 struct drm_file *file_priv);
1041 int intel_overlay_attrs(struct drm_device *dev, void *data,
1042 struct drm_file *file_priv);
1046 int intel_panel_init(struct intel_panel *panel,
1047 struct drm_display_mode *fixed_mode,
1048 struct drm_display_mode *downclock_mode);
1049 void intel_panel_fini(struct intel_panel *panel);
1050 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1051 struct drm_display_mode *adjusted_mode);
1052 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1053 struct intel_crtc_config *pipe_config,
1055 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1056 struct intel_crtc_config *pipe_config,
1058 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1059 u32 level, u32 max);
1060 int intel_panel_setup_backlight(struct drm_connector *connector);
1061 void intel_panel_enable_backlight(struct intel_connector *connector);
1062 void intel_panel_disable_backlight(struct intel_connector *connector);
1063 void intel_panel_destroy_backlight(struct drm_connector *connector);
1064 void intel_panel_init_backlight_funcs(struct drm_device *dev);
1065 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1066 extern struct drm_display_mode *intel_find_panel_downclock(
1067 struct drm_device *dev,
1068 struct drm_display_mode *fixed_mode,
1069 struct drm_connector *connector);
1072 void intel_init_clock_gating(struct drm_device *dev);
1073 void intel_suspend_hw(struct drm_device *dev);
1074 int ilk_wm_max_level(const struct drm_device *dev);
1075 void intel_update_watermarks(struct drm_crtc *crtc);
1076 void intel_update_sprite_watermarks(struct drm_plane *plane,
1077 struct drm_crtc *crtc,
1078 uint32_t sprite_width,
1079 uint32_t sprite_height,
1081 bool enabled, bool scaled);
1082 void intel_init_pm(struct drm_device *dev);
1083 void intel_pm_setup(struct drm_device *dev);
1084 bool intel_fbc_enabled(struct drm_device *dev);
1085 void intel_update_fbc(struct drm_device *dev);
1086 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1087 void intel_gpu_ips_teardown(void);
1088 int intel_power_domains_init(struct drm_i915_private *);
1089 void intel_power_domains_remove(struct drm_i915_private *);
1090 bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
1091 enum intel_display_power_domain domain);
1092 bool intel_display_power_enabled_unlocked(struct drm_i915_private *dev_priv,
1093 enum intel_display_power_domain domain);
1094 void intel_display_power_get(struct drm_i915_private *dev_priv,
1095 enum intel_display_power_domain domain);
1096 void intel_display_power_put(struct drm_i915_private *dev_priv,
1097 enum intel_display_power_domain domain);
1098 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
1099 void intel_init_gt_powersave(struct drm_device *dev);
1100 void intel_cleanup_gt_powersave(struct drm_device *dev);
1101 void intel_enable_gt_powersave(struct drm_device *dev);
1102 void intel_disable_gt_powersave(struct drm_device *dev);
1103 void intel_suspend_gt_powersave(struct drm_device *dev);
1104 void intel_reset_gt_powersave(struct drm_device *dev);
1105 void ironlake_teardown_rc6(struct drm_device *dev);
1106 void gen6_update_ring_freq(struct drm_device *dev);
1107 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1108 void gen6_rps_boost(struct drm_i915_private *dev_priv);
1109 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
1110 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
1111 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1112 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1113 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1114 void intel_init_runtime_pm(struct drm_i915_private *dev_priv);
1115 void intel_fini_runtime_pm(struct drm_i915_private *dev_priv);
1116 void ilk_wm_get_hw_state(struct drm_device *dev);
1120 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
1123 /* intel_sprite.c */
1124 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1125 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1127 int intel_plane_set_property(struct drm_plane *plane,
1128 struct drm_property *prop,
1130 int intel_plane_restore(struct drm_plane *plane);
1131 void intel_plane_disable(struct drm_plane *plane);
1132 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1133 struct drm_file *file_priv);
1134 int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
1135 struct drm_file *file_priv);
1139 void intel_tv_init(struct drm_device *dev);
1141 #endif /* __INTEL_DRV_H__ */