2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/i2c.h>
29 #include <linux/hdmi.h>
30 #include <drm/i915_drm.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_fb_helper.h>
35 #include <drm/drm_dp_helper.h>
38 * _wait_for - magic (register) wait macro
40 * Does the right thing for modeset paths when run under kdgb or similar atomic
41 * contexts. Note that it's important that we check the condition again after
42 * having timed out, since the timeout could be due to preemption or similar and
43 * we've never had a chance to check the condition before the timeout.
45 #define _wait_for(COND, MS, W) ({ \
46 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
49 if (time_after(jiffies, timeout__)) { \
54 if (W && drm_can_sleep()) { \
63 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
64 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
65 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
66 DIV_ROUND_UP((US), 1000), 0)
68 #define KHz(x) (1000*x)
69 #define MHz(x) KHz(1000*x)
72 * Display related stuff
75 /* store information about an Ixxx DVO */
76 /* The i830->i865 use multiple DVOs with multiple i2cs */
77 /* the i915, i945 have a single sDVO i2c bus - which is different */
79 /* maximum connectors per crtcs in the mode set */
81 #define INTEL_I2C_BUS_DVO 1
82 #define INTEL_I2C_BUS_SDVO 2
84 /* these are outputs from the chip - integrated only
85 external chips are via DVO or SDVO output */
86 #define INTEL_OUTPUT_UNUSED 0
87 #define INTEL_OUTPUT_ANALOG 1
88 #define INTEL_OUTPUT_DVO 2
89 #define INTEL_OUTPUT_SDVO 3
90 #define INTEL_OUTPUT_LVDS 4
91 #define INTEL_OUTPUT_TVOUT 5
92 #define INTEL_OUTPUT_HDMI 6
93 #define INTEL_OUTPUT_DISPLAYPORT 7
94 #define INTEL_OUTPUT_EDP 8
95 #define INTEL_OUTPUT_DSI 9
96 #define INTEL_OUTPUT_UNKNOWN 10
98 #define INTEL_DVO_CHIP_NONE 0
99 #define INTEL_DVO_CHIP_LVDS 1
100 #define INTEL_DVO_CHIP_TMDS 2
101 #define INTEL_DVO_CHIP_TVOUT 4
103 #define INTEL_DSI_COMMAND_MODE 0
104 #define INTEL_DSI_VIDEO_MODE 1
106 struct intel_framebuffer {
107 struct drm_framebuffer base;
108 struct drm_i915_gem_object *obj;
112 struct drm_fb_helper helper;
113 struct intel_framebuffer ifb;
114 struct list_head fbdev_list;
115 struct drm_display_mode *our_mode;
118 struct intel_encoder {
119 struct drm_encoder base;
121 * The new crtc this encoder will be driven from. Only differs from
122 * base->crtc while a modeset is in progress.
124 struct intel_crtc *new_crtc;
128 * Intel hw has only one MUX where encoders could be clone, hence a
129 * simple flag is enough to compute the possible_clones mask.
132 bool connectors_active;
133 void (*hot_plug)(struct intel_encoder *);
134 bool (*compute_config)(struct intel_encoder *,
135 struct intel_crtc_config *);
136 void (*pre_pll_enable)(struct intel_encoder *);
137 void (*pre_enable)(struct intel_encoder *);
138 void (*enable)(struct intel_encoder *);
139 void (*mode_set)(struct intel_encoder *intel_encoder);
140 void (*disable)(struct intel_encoder *);
141 void (*post_disable)(struct intel_encoder *);
142 /* Read out the current hw state of this connector, returning true if
143 * the encoder is active. If the encoder is enabled it also set the pipe
144 * it is connected to in the pipe parameter. */
145 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
146 /* Reconstructs the equivalent mode flags for the current hardware
147 * state. This must be called _after_ display->get_pipe_config has
148 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
149 * be set correctly before calling this function. */
150 void (*get_config)(struct intel_encoder *,
151 struct intel_crtc_config *pipe_config);
153 enum hpd_pin hpd_pin;
157 struct drm_display_mode *fixed_mode;
166 struct backlight_device *device;
170 struct intel_connector {
171 struct drm_connector base;
173 * The fixed encoder this connector is connected to.
175 struct intel_encoder *encoder;
178 * The new encoder this connector will be driven. Only differs from
179 * encoder while a modeset is in progress.
181 struct intel_encoder *new_encoder;
183 /* Reads out the current hw, returning true if the connector is enabled
184 * and active (i.e. dpms ON state). */
185 bool (*get_hw_state)(struct intel_connector *);
187 /* Panel info for eDP and LVDS */
188 struct intel_panel panel;
190 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
193 /* since POLL and HPD connectors may use the same HPD line keep the native
194 state of connector->polled in case hotplug storm detection changes it */
198 typedef struct dpll {
210 struct intel_crtc_config {
212 * quirks - bitfield with hw state readout quirks
214 * For various reasons the hw state readout code might not be able to
215 * completely faithfully read out the current state. These cases are
216 * tracked with quirk flags so that fastboot and state checker can act
219 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
220 unsigned long quirks;
222 /* User requested mode, only valid as a starting point to
223 * compute adjusted_mode, except in the case of (S)DVO where
224 * it's also for the output timings of the (S)DVO chip.
225 * adjusted_mode will then correspond to the S(DVO) chip's
226 * preferred input timings. */
227 struct drm_display_mode requested_mode;
228 /* Actual pipe timings ie. what we program into the pipe timing
229 * registers. adjusted_mode.crtc_clock is the pipe pixel clock. */
230 struct drm_display_mode adjusted_mode;
232 /* Pipe source size (ie. panel fitter input size)
233 * All planes will be positioned inside this space,
234 * and get clipped at the edges. */
235 int pipe_src_w, pipe_src_h;
237 /* Whether to set up the PCH/FDI. Note that we never allow sharing
238 * between pch encoders and cpu encoders. */
239 bool has_pch_encoder;
241 /* CPU Transcoder for the pipe. Currently this can only differ from the
242 * pipe on Haswell (where we have a special eDP transcoder). */
243 enum transcoder cpu_transcoder;
246 * Use reduced/limited/broadcast rbg range, compressing from the full
247 * range fed into the crtcs.
249 bool limited_color_range;
251 /* DP has a bunch of special case unfortunately, so mark the pipe
256 * Enable dithering, used when the selected pipe bpp doesn't match the
261 /* Controls for the clock computation, to override various stages. */
264 /* SDVO TV has a bunch of special case. To make multifunction encoders
265 * work correctly, we need to track this at runtime.*/
269 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
270 * required. This is set in the 2nd loop of calling encoder's
271 * ->compute_config if the first pick doesn't work out.
275 /* Settings for the intel dpll used on pretty much everything but
279 /* Selected dpll when shared or DPLL_ID_PRIVATE. */
280 enum intel_dpll_id shared_dpll;
282 /* Actual register state of the dpll, for shared dpll cross-checking. */
283 struct intel_dpll_hw_state dpll_hw_state;
286 struct intel_link_m_n dp_m_n;
289 * Frequence the dpll for the port should run at. Differs from the
290 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
291 * already multiplied by pixel_multiplier.
295 /* Used by SDVO (and if we ever fix it, HDMI). */
296 unsigned pixel_multiplier;
298 /* Panel fitter controls for gen2-gen4 + VLV */
302 u32 lvds_border_bits;
305 /* Panel fitter placement and size for Ironlake+ */
312 /* FDI configuration, only valid if has_pch_encoder is set. */
314 struct intel_link_m_n fdi_m_n;
321 struct intel_pipe_wm {
322 struct intel_wm_level wm[5];
328 struct drm_crtc base;
331 u8 lut_r[256], lut_g[256], lut_b[256];
333 * Whether the crtc and the connected output pipeline is active. Implies
334 * that crtc->enabled is set, i.e. the current mode configuration has
335 * some outputs connected to this crtc.
338 unsigned long enabled_power_domains;
340 bool primary_enabled; /* is the primary plane (partially) visible? */
342 struct intel_overlay *overlay;
343 struct intel_unpin_work *unpin_work;
345 atomic_t unpin_work_count;
347 /* Display surface base address adjustement for pageflips. Note that on
348 * gen4+ this only adjusts up to a tile, offsets within a tile are
349 * handled in the hw itself (with the TILEOFF register). */
350 unsigned long dspaddr_offset;
352 struct drm_i915_gem_object *cursor_bo;
353 uint32_t cursor_addr;
354 int16_t cursor_x, cursor_y;
355 int16_t cursor_width, cursor_height;
358 struct intel_crtc_config config;
360 uint32_t ddi_pll_sel;
362 /* reset counter value when the last flip was submitted */
363 unsigned int reset_counter;
365 /* Access to these should be protected by dev_priv->irq_lock. */
366 bool cpu_fifo_underrun_disabled;
367 bool pch_fifo_underrun_disabled;
369 /* per-pipe watermark state */
371 /* watermarks currently being used */
372 struct intel_pipe_wm active;
376 struct intel_plane_wm_parameters {
377 uint32_t horiz_pixels;
378 uint8_t bytes_per_pixel;
384 struct drm_plane base;
387 struct drm_i915_gem_object *obj;
390 u32 lut_r[1024], lut_g[1024], lut_b[1024];
392 unsigned int crtc_w, crtc_h;
393 uint32_t src_x, src_y;
394 uint32_t src_w, src_h;
396 /* Since we need to change the watermarks before/after
397 * enabling/disabling the planes, we need to store the parameters here
398 * as the other pieces of the struct may not reflect the values we want
399 * for the watermark calculations. Currently only Haswell uses this.
401 struct intel_plane_wm_parameters wm;
403 void (*update_plane)(struct drm_plane *plane,
404 struct drm_crtc *crtc,
405 struct drm_framebuffer *fb,
406 struct drm_i915_gem_object *obj,
407 int crtc_x, int crtc_y,
408 unsigned int crtc_w, unsigned int crtc_h,
409 uint32_t x, uint32_t y,
410 uint32_t src_w, uint32_t src_h);
411 void (*disable_plane)(struct drm_plane *plane,
412 struct drm_crtc *crtc);
413 int (*update_colorkey)(struct drm_plane *plane,
414 struct drm_intel_sprite_colorkey *key);
415 void (*get_colorkey)(struct drm_plane *plane,
416 struct drm_intel_sprite_colorkey *key);
419 struct intel_watermark_params {
420 unsigned long fifo_size;
421 unsigned long max_wm;
422 unsigned long default_wm;
423 unsigned long guard_size;
424 unsigned long cacheline_size;
427 struct cxsr_latency {
430 unsigned long fsb_freq;
431 unsigned long mem_freq;
432 unsigned long display_sr;
433 unsigned long display_hpll_disable;
434 unsigned long cursor_sr;
435 unsigned long cursor_hpll_disable;
438 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
439 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
440 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
441 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
442 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
447 uint32_t color_range;
448 bool color_range_auto;
451 enum hdmi_force_audio force_audio;
452 bool rgb_quant_range_selectable;
453 void (*write_infoframe)(struct drm_encoder *encoder,
454 enum hdmi_infoframe_type type,
455 const uint8_t *frame, ssize_t len);
456 void (*set_infoframes)(struct drm_encoder *encoder,
457 struct drm_display_mode *adjusted_mode);
460 #define DP_MAX_DOWNSTREAM_PORTS 0x10
464 uint32_t aux_ch_ctl_reg;
467 enum hdmi_force_audio force_audio;
468 uint32_t color_range;
469 bool color_range_auto;
472 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
473 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
474 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
475 struct i2c_adapter adapter;
476 struct i2c_algo_dp_aux_data algo;
477 uint8_t train_set[4];
478 int panel_power_up_delay;
479 int panel_power_down_delay;
480 int panel_power_cycle_delay;
481 int backlight_on_delay;
482 int backlight_off_delay;
483 struct delayed_work panel_vdd_work;
486 struct intel_connector *attached_connector;
489 struct intel_digital_port {
490 struct intel_encoder base;
494 struct intel_hdmi hdmi;
498 vlv_dport_to_channel(struct intel_digital_port *dport)
500 switch (dport->port) {
510 static inline struct drm_crtc *
511 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
513 struct drm_i915_private *dev_priv = dev->dev_private;
514 return dev_priv->pipe_to_crtc_mapping[pipe];
517 static inline struct drm_crtc *
518 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
520 struct drm_i915_private *dev_priv = dev->dev_private;
521 return dev_priv->plane_to_crtc_mapping[plane];
524 struct intel_unpin_work {
525 struct work_struct work;
526 struct drm_crtc *crtc;
527 struct drm_i915_gem_object *old_fb_obj;
528 struct drm_i915_gem_object *pending_flip_obj;
529 struct drm_pending_vblank_event *event;
531 #define INTEL_FLIP_INACTIVE 0
532 #define INTEL_FLIP_PENDING 1
533 #define INTEL_FLIP_COMPLETE 2
534 bool enable_stall_check;
537 struct intel_set_config {
538 struct drm_encoder **save_connector_encoders;
539 struct drm_crtc **save_encoder_crtcs;
545 struct intel_load_detect_pipe {
546 struct drm_framebuffer *release_fb;
547 bool load_detect_temp;
551 static inline struct intel_encoder *
552 intel_attached_encoder(struct drm_connector *connector)
554 return to_intel_connector(connector)->encoder;
557 static inline struct intel_digital_port *
558 enc_to_dig_port(struct drm_encoder *encoder)
560 return container_of(encoder, struct intel_digital_port, base.base);
563 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
565 return &enc_to_dig_port(encoder)->dp;
568 static inline struct intel_digital_port *
569 dp_to_dig_port(struct intel_dp *intel_dp)
571 return container_of(intel_dp, struct intel_digital_port, dp);
574 static inline struct intel_digital_port *
575 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
577 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
582 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
583 enum pipe pipe, bool enable);
584 bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
585 enum transcoder pch_transcoder,
587 void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
588 void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
589 void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
590 void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
591 void hsw_pc8_disable_interrupts(struct drm_device *dev);
592 void hsw_pc8_restore_interrupts(struct drm_device *dev);
596 void intel_crt_init(struct drm_device *dev);
600 void intel_prepare_ddi(struct drm_device *dev);
601 void hsw_fdi_link_train(struct drm_crtc *crtc);
602 void intel_ddi_init(struct drm_device *dev, enum port port);
603 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
604 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
605 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
606 void intel_ddi_pll_init(struct drm_device *dev);
607 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
608 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
609 enum transcoder cpu_transcoder);
610 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
611 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
612 void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
613 bool intel_ddi_pll_mode_set(struct drm_crtc *crtc);
614 void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
615 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
616 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
617 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
618 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
619 void intel_ddi_get_config(struct intel_encoder *encoder,
620 struct intel_crtc_config *pipe_config);
623 /* intel_display.c */
624 int intel_pch_rawclk(struct drm_device *dev);
625 void intel_mark_busy(struct drm_device *dev);
626 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
627 struct intel_ring_buffer *ring);
628 void intel_mark_idle(struct drm_device *dev);
629 void intel_crtc_restore_mode(struct drm_crtc *crtc);
630 void intel_crtc_update_dpms(struct drm_crtc *crtc);
631 void intel_encoder_destroy(struct drm_encoder *encoder);
632 void intel_connector_dpms(struct drm_connector *, int mode);
633 bool intel_connector_get_hw_state(struct intel_connector *connector);
634 void intel_modeset_check_state(struct drm_device *dev);
635 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
636 struct intel_digital_port *port);
637 void intel_connector_attach_encoder(struct intel_connector *connector,
638 struct intel_encoder *encoder);
639 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
640 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
641 struct drm_crtc *crtc);
642 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
643 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
644 struct drm_file *file_priv);
645 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
647 void intel_wait_for_vblank(struct drm_device *dev, int pipe);
648 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
649 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
650 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port);
651 bool intel_get_load_detect_pipe(struct drm_connector *connector,
652 struct drm_display_mode *mode,
653 struct intel_load_detect_pipe *old);
654 void intel_release_load_detect_pipe(struct drm_connector *connector,
655 struct intel_load_detect_pipe *old);
656 int intel_pin_and_fence_fb_obj(struct drm_device *dev,
657 struct drm_i915_gem_object *obj,
658 struct intel_ring_buffer *pipelined);
659 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
660 int intel_framebuffer_init(struct drm_device *dev,
661 struct intel_framebuffer *ifb,
662 struct drm_mode_fb_cmd2 *mode_cmd,
663 struct drm_i915_gem_object *obj);
664 void intel_framebuffer_fini(struct intel_framebuffer *fb);
665 void intel_prepare_page_flip(struct drm_device *dev, int plane);
666 void intel_finish_page_flip(struct drm_device *dev, int pipe);
667 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
668 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
669 void assert_shared_dpll(struct drm_i915_private *dev_priv,
670 struct intel_shared_dpll *pll,
672 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
673 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
674 void assert_pll(struct drm_i915_private *dev_priv,
675 enum pipe pipe, bool state);
676 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
677 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
678 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
679 enum pipe pipe, bool state);
680 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
681 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
682 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
683 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
684 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
685 void intel_write_eld(struct drm_encoder *encoder,
686 struct drm_display_mode *mode);
687 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
688 unsigned int tiling_mode,
691 void intel_display_handle_reset(struct drm_device *dev);
692 void hsw_enable_pc8_work(struct work_struct *__work);
693 void hsw_enable_package_c8(struct drm_i915_private *dev_priv);
694 void hsw_disable_package_c8(struct drm_i915_private *dev_priv);
695 void intel_dp_get_m_n(struct intel_crtc *crtc,
696 struct intel_crtc_config *pipe_config);
697 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
699 ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
701 bool intel_crtc_active(struct drm_crtc *crtc);
702 void i915_disable_vga_mem(struct drm_device *dev);
703 void hsw_enable_ips(struct intel_crtc *crtc);
704 void hsw_disable_ips(struct intel_crtc *crtc);
705 void intel_display_set_init_power(struct drm_device *dev, bool enable);
709 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
710 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
711 struct intel_connector *intel_connector);
712 void intel_dp_start_link_train(struct intel_dp *intel_dp);
713 void intel_dp_complete_link_train(struct intel_dp *intel_dp);
714 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
715 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
716 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
717 void intel_dp_check_link_status(struct intel_dp *intel_dp);
718 bool intel_dp_compute_config(struct intel_encoder *encoder,
719 struct intel_crtc_config *pipe_config);
720 bool intel_dpd_is_edp(struct drm_device *dev);
721 void ironlake_edp_backlight_on(struct intel_dp *intel_dp);
722 void ironlake_edp_backlight_off(struct intel_dp *intel_dp);
723 void ironlake_edp_panel_on(struct intel_dp *intel_dp);
724 void ironlake_edp_panel_off(struct intel_dp *intel_dp);
725 void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
726 void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
727 void intel_edp_psr_enable(struct intel_dp *intel_dp);
728 void intel_edp_psr_disable(struct intel_dp *intel_dp);
729 void intel_edp_psr_update(struct drm_device *dev);
733 bool intel_dsi_init(struct drm_device *dev);
737 void intel_dvo_init(struct drm_device *dev);
740 /* legacy fbdev emulation in intel_fbdev.c */
741 #ifdef CONFIG_DRM_I915_FBDEV
742 extern int intel_fbdev_init(struct drm_device *dev);
743 extern void intel_fbdev_initial_config(struct drm_device *dev);
744 extern void intel_fbdev_fini(struct drm_device *dev);
745 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
746 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
747 extern void intel_fbdev_restore_mode(struct drm_device *dev);
749 static inline int intel_fbdev_init(struct drm_device *dev)
754 static inline void intel_fbdev_initial_config(struct drm_device *dev)
758 static inline void intel_fbdev_fini(struct drm_device *dev)
762 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state)
766 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
772 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
773 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
774 struct intel_connector *intel_connector);
775 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
776 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
777 struct intel_crtc_config *pipe_config);
781 void intel_lvds_init(struct drm_device *dev);
782 bool intel_is_dual_link_lvds(struct drm_device *dev);
786 int intel_connector_update_modes(struct drm_connector *connector,
788 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
789 void intel_attach_force_audio_property(struct drm_connector *connector);
790 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
793 /* intel_overlay.c */
794 void intel_setup_overlay(struct drm_device *dev);
795 void intel_cleanup_overlay(struct drm_device *dev);
796 int intel_overlay_switch_off(struct intel_overlay *overlay);
797 int intel_overlay_put_image(struct drm_device *dev, void *data,
798 struct drm_file *file_priv);
799 int intel_overlay_attrs(struct drm_device *dev, void *data,
800 struct drm_file *file_priv);
804 int intel_panel_init(struct intel_panel *panel,
805 struct drm_display_mode *fixed_mode);
806 void intel_panel_fini(struct intel_panel *panel);
807 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
808 struct drm_display_mode *adjusted_mode);
809 void intel_pch_panel_fitting(struct intel_crtc *crtc,
810 struct intel_crtc_config *pipe_config,
812 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
813 struct intel_crtc_config *pipe_config,
815 void intel_panel_set_backlight(struct intel_connector *connector, u32 level,
817 int intel_panel_setup_backlight(struct drm_connector *connector);
818 void intel_panel_enable_backlight(struct intel_connector *connector);
819 void intel_panel_disable_backlight(struct intel_connector *connector);
820 void intel_panel_destroy_backlight(struct drm_connector *connector);
821 void intel_panel_init_backlight_funcs(struct drm_device *dev);
822 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
826 void intel_init_clock_gating(struct drm_device *dev);
827 void intel_suspend_hw(struct drm_device *dev);
828 void intel_update_watermarks(struct drm_crtc *crtc);
829 void intel_update_sprite_watermarks(struct drm_plane *plane,
830 struct drm_crtc *crtc,
831 uint32_t sprite_width, int pixel_size,
832 bool enabled, bool scaled);
833 void intel_init_pm(struct drm_device *dev);
834 bool intel_fbc_enabled(struct drm_device *dev);
835 void intel_update_fbc(struct drm_device *dev);
836 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
837 void intel_gpu_ips_teardown(void);
838 int intel_power_domains_init(struct drm_device *dev);
839 void intel_power_domains_remove(struct drm_device *dev);
840 bool intel_display_power_enabled(struct drm_device *dev,
841 enum intel_display_power_domain domain);
842 void intel_display_power_get(struct drm_device *dev,
843 enum intel_display_power_domain domain);
844 void intel_display_power_put(struct drm_device *dev,
845 enum intel_display_power_domain domain);
846 void intel_power_domains_init_hw(struct drm_device *dev);
847 void intel_set_power_well(struct drm_device *dev, bool enable);
848 void intel_enable_gt_powersave(struct drm_device *dev);
849 void intel_disable_gt_powersave(struct drm_device *dev);
850 void ironlake_teardown_rc6(struct drm_device *dev);
851 void gen6_update_ring_freq(struct drm_device *dev);
852 void gen6_rps_idle(struct drm_i915_private *dev_priv);
853 void gen6_rps_boost(struct drm_i915_private *dev_priv);
854 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
855 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
856 void ilk_wm_get_hw_state(struct drm_device *dev);
860 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
864 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
865 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
867 void intel_plane_restore(struct drm_plane *plane);
868 void intel_plane_disable(struct drm_plane *plane);
869 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
870 struct drm_file *file_priv);
871 int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
872 struct drm_file *file_priv);
876 void intel_tv_init(struct drm_device *dev);
878 #endif /* __INTEL_DRV_H__ */