2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <drm/i915_drm.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_fb_helper.h>
36 #include <drm/drm_dp_mst_helper.h>
37 #include <drm/drm_rect.h>
38 #include <drm/drm_atomic.h>
41 * _wait_for - magic (register) wait macro
43 * Does the right thing for modeset paths when run under kdgb or similar atomic
44 * contexts. Note that it's important that we check the condition again after
45 * having timed out, since the timeout could be due to preemption or similar and
46 * we've never had a chance to check the condition before the timeout.
48 #define _wait_for(COND, MS, W) ({ \
49 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
52 if (time_after(jiffies, timeout__)) { \
57 if ((W) && drm_can_sleep()) { \
58 usleep_range((W)*1000, (W)*2000); \
66 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
67 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
68 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
69 DIV_ROUND_UP((US), 1000), 0)
71 #define KHz(x) (1000 * (x))
72 #define MHz(x) KHz(1000 * (x))
75 * Display related stuff
78 /* store information about an Ixxx DVO */
79 /* The i830->i865 use multiple DVOs with multiple i2cs */
80 /* the i915, i945 have a single sDVO i2c bus - which is different */
82 /* maximum connectors per crtcs in the mode set */
84 /* Maximum cursor sizes */
85 #define GEN2_CURSOR_WIDTH 64
86 #define GEN2_CURSOR_HEIGHT 64
87 #define MAX_CURSOR_WIDTH 256
88 #define MAX_CURSOR_HEIGHT 256
90 #define INTEL_I2C_BUS_DVO 1
91 #define INTEL_I2C_BUS_SDVO 2
93 /* these are outputs from the chip - integrated only
94 external chips are via DVO or SDVO output */
95 enum intel_output_type {
96 INTEL_OUTPUT_UNUSED = 0,
97 INTEL_OUTPUT_ANALOG = 1,
99 INTEL_OUTPUT_SDVO = 3,
100 INTEL_OUTPUT_LVDS = 4,
101 INTEL_OUTPUT_TVOUT = 5,
102 INTEL_OUTPUT_HDMI = 6,
103 INTEL_OUTPUT_DISPLAYPORT = 7,
104 INTEL_OUTPUT_EDP = 8,
105 INTEL_OUTPUT_DSI = 9,
106 INTEL_OUTPUT_UNKNOWN = 10,
107 INTEL_OUTPUT_DP_MST = 11,
110 #define INTEL_DVO_CHIP_NONE 0
111 #define INTEL_DVO_CHIP_LVDS 1
112 #define INTEL_DVO_CHIP_TMDS 2
113 #define INTEL_DVO_CHIP_TVOUT 4
115 #define INTEL_DSI_VIDEO_MODE 0
116 #define INTEL_DSI_COMMAND_MODE 1
118 struct intel_framebuffer {
119 struct drm_framebuffer base;
120 struct drm_i915_gem_object *obj;
124 struct drm_fb_helper helper;
125 struct intel_framebuffer *fb;
126 struct list_head fbdev_list;
127 struct drm_display_mode *our_mode;
131 struct intel_encoder {
132 struct drm_encoder base;
134 * The new crtc this encoder will be driven from. Only differs from
135 * base->crtc while a modeset is in progress.
137 struct intel_crtc *new_crtc;
139 enum intel_output_type type;
140 unsigned int cloneable;
141 bool connectors_active;
142 void (*hot_plug)(struct intel_encoder *);
143 bool (*compute_config)(struct intel_encoder *,
144 struct intel_crtc_state *);
145 void (*pre_pll_enable)(struct intel_encoder *);
146 void (*pre_enable)(struct intel_encoder *);
147 void (*enable)(struct intel_encoder *);
148 void (*mode_set)(struct intel_encoder *intel_encoder);
149 void (*disable)(struct intel_encoder *);
150 void (*post_disable)(struct intel_encoder *);
151 /* Read out the current hw state of this connector, returning true if
152 * the encoder is active. If the encoder is enabled it also set the pipe
153 * it is connected to in the pipe parameter. */
154 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
155 /* Reconstructs the equivalent mode flags for the current hardware
156 * state. This must be called _after_ display->get_pipe_config has
157 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
158 * be set correctly before calling this function. */
159 void (*get_config)(struct intel_encoder *,
160 struct intel_crtc_state *pipe_config);
162 * Called during system suspend after all pending requests for the
163 * encoder are flushed (for example for DP AUX transactions) and
164 * device interrupts are disabled.
166 void (*suspend)(struct intel_encoder *);
168 enum hpd_pin hpd_pin;
172 struct drm_display_mode *fixed_mode;
173 struct drm_display_mode *downclock_mode;
183 bool combination_mode; /* gen 2/4 only */
185 struct backlight_device *device;
188 void (*backlight_power)(struct intel_connector *, bool enable);
191 struct intel_connector {
192 struct drm_connector base;
194 * The fixed encoder this connector is connected to.
196 struct intel_encoder *encoder;
199 * The new encoder this connector will be driven. Only differs from
200 * encoder while a modeset is in progress.
202 struct intel_encoder *new_encoder;
204 /* Reads out the current hw, returning true if the connector is enabled
205 * and active (i.e. dpms ON state). */
206 bool (*get_hw_state)(struct intel_connector *);
209 * Removes all interfaces through which the connector is accessible
210 * - like sysfs, debugfs entries -, so that no new operations can be
211 * started on the connector. Also makes sure all currently pending
212 * operations finish before returing.
214 void (*unregister)(struct intel_connector *);
216 /* Panel info for eDP and LVDS */
217 struct intel_panel panel;
219 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
221 struct edid *detect_edid;
223 /* since POLL and HPD connectors may use the same HPD line keep the native
224 state of connector->polled in case hotplug storm detection changes it */
227 void *port; /* store this opaque as its illegal to dereference it */
229 struct intel_dp *mst_port;
232 typedef struct dpll {
244 struct intel_atomic_state {
245 struct drm_atomic_state base;
249 struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
252 struct intel_plane_state {
253 struct drm_plane_state base;
256 struct drm_rect clip;
261 * = -1 : not using a scaler
262 * >= 0 : using a scalers
264 * plane requiring a scaler:
265 * - During check_plane, its bit is set in
266 * crtc_state->scaler_state.scaler_users by calling helper function
267 * update_scaler_plane.
268 * - scaler_id indicates the scaler it got assigned.
270 * plane doesn't require a scaler:
271 * - this can happen when scaling is no more required or plane simply
273 * - During check_plane, corresponding bit is reset in
274 * crtc_state->scaler_state.scaler_users by calling helper function
275 * update_scaler_plane.
279 struct drm_intel_sprite_colorkey ckey;
282 struct intel_initial_plane_config {
283 struct intel_framebuffer *fb;
289 #define SKL_MIN_SRC_W 8
290 #define SKL_MAX_SRC_W 4096
291 #define SKL_MIN_SRC_H 8
292 #define SKL_MAX_SRC_H 4096
293 #define SKL_MIN_DST_W 8
294 #define SKL_MAX_DST_W 4096
295 #define SKL_MIN_DST_H 8
296 #define SKL_MAX_DST_H 4096
298 struct intel_scaler {
303 struct intel_crtc_scaler_state {
304 #define SKL_NUM_SCALERS 2
305 struct intel_scaler scalers[SKL_NUM_SCALERS];
308 * scaler_users: keeps track of users requesting scalers on this crtc.
310 * If a bit is set, a user is using a scaler.
311 * Here user can be a plane or crtc as defined below:
312 * bits 0-30 - plane (bit position is index from drm_plane_index)
315 * Instead of creating a new index to cover planes and crtc, using
316 * existing drm_plane_index for planes which is well less than 31
317 * planes and bit 31 for crtc. This should be fine to cover all
320 * intel_atomic_setup_scalers will setup available scalers to users
321 * requesting scalers. It will gracefully fail if request exceeds
324 #define SKL_CRTC_INDEX 31
325 unsigned scaler_users;
327 /* scaler used by crtc for panel fitting purpose */
331 struct intel_crtc_state {
332 struct drm_crtc_state base;
335 * quirks - bitfield with hw state readout quirks
337 * For various reasons the hw state readout code might not be able to
338 * completely faithfully read out the current state. These cases are
339 * tracked with quirk flags so that fastboot and state checker can act
342 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
343 #define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1) /* mode inherited from firmware */
344 #define PIPE_CONFIG_QUIRK_INITIAL_PLANES (1<<2) /* planes are in unknown state */
345 unsigned long quirks;
347 /* Pipe source size (ie. panel fitter input size)
348 * All planes will be positioned inside this space,
349 * and get clipped at the edges. */
350 int pipe_src_w, pipe_src_h;
352 /* Whether to set up the PCH/FDI. Note that we never allow sharing
353 * between pch encoders and cpu encoders. */
354 bool has_pch_encoder;
356 /* Are we sending infoframes on the attached port */
359 /* CPU Transcoder for the pipe. Currently this can only differ from the
360 * pipe on Haswell (where we have a special eDP transcoder). */
361 enum transcoder cpu_transcoder;
364 * Use reduced/limited/broadcast rbg range, compressing from the full
365 * range fed into the crtcs.
367 bool limited_color_range;
369 /* DP has a bunch of special case unfortunately, so mark the pipe
373 /* Whether we should send NULL infoframes. Required for audio. */
376 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
377 * has_dp_encoder is set. */
381 * Enable dithering, used when the selected pipe bpp doesn't match the
386 /* Controls for the clock computation, to override various stages. */
389 /* SDVO TV has a bunch of special case. To make multifunction encoders
390 * work correctly, we need to track this at runtime.*/
394 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
395 * required. This is set in the 2nd loop of calling encoder's
396 * ->compute_config if the first pick doesn't work out.
400 /* Settings for the intel dpll used on pretty much everything but
404 /* Selected dpll when shared or DPLL_ID_PRIVATE. */
405 enum intel_dpll_id shared_dpll;
408 * - PORT_CLK_SEL for DDI ports on HSW/BDW.
409 * - enum skl_dpll on SKL
411 uint32_t ddi_pll_sel;
413 /* Actual register state of the dpll, for shared dpll cross-checking. */
414 struct intel_dpll_hw_state dpll_hw_state;
417 struct intel_link_m_n dp_m_n;
419 /* m2_n2 for eDP downclock */
420 struct intel_link_m_n dp_m2_n2;
424 * Frequence the dpll for the port should run at. Differs from the
425 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
426 * already multiplied by pixel_multiplier.
430 /* Used by SDVO (and if we ever fix it, HDMI). */
431 unsigned pixel_multiplier;
433 /* Panel fitter controls for gen2-gen4 + VLV */
437 u32 lvds_border_bits;
440 /* Panel fitter placement and size for Ironlake+ */
448 /* FDI configuration, only valid if has_pch_encoder is set. */
450 struct intel_link_m_n fdi_m_n;
456 bool dp_encoder_is_mst;
459 struct intel_crtc_scaler_state scaler_state;
461 /* w/a for waiting 2 vblanks during crtc enable */
462 enum pipe hsw_workaround_pipe;
465 struct vlv_wm_state {
466 struct vlv_pipe_wm wm[3];
467 struct vlv_sr_wm sr[3];
468 uint8_t num_active_planes;
474 struct intel_pipe_wm {
475 struct intel_wm_level wm[5];
479 bool sprites_enabled;
483 struct intel_mmio_flip {
484 struct work_struct work;
485 struct drm_i915_private *i915;
486 struct drm_i915_gem_request *req;
487 struct intel_crtc *crtc;
491 struct skl_wm_level wm[8];
492 struct skl_wm_level trans_wm;
497 * Tracking of operations that need to be performed at the beginning/end of an
498 * atomic commit, outside the atomic section where interrupts are disabled.
499 * These are generally operations that grab mutexes or might otherwise sleep
500 * and thus can't be run with interrupts disabled.
502 struct intel_crtc_atomic_commit {
505 unsigned start_vbl_count;
507 /* Sleepable operations to perform before commit */
512 bool pre_disable_primary;
513 bool update_wm_pre, update_wm_post;
514 unsigned disabled_planes;
516 /* Sleepable operations to perform after commit */
520 bool post_enable_primary;
521 unsigned update_sprite_watermarks;
525 struct drm_crtc base;
528 u8 lut_r[256], lut_g[256], lut_b[256];
530 * Whether the crtc and the connected output pipeline is active. Implies
531 * that crtc->enabled is set, i.e. the current mode configuration has
532 * some outputs connected to this crtc.
535 unsigned long enabled_power_domains;
537 struct intel_overlay *overlay;
538 struct intel_unpin_work *unpin_work;
540 atomic_t unpin_work_count;
542 /* Display surface base address adjustement for pageflips. Note that on
543 * gen4+ this only adjusts up to a tile, offsets within a tile are
544 * handled in the hw itself (with the TILEOFF register). */
545 unsigned long dspaddr_offset;
547 struct drm_i915_gem_object *cursor_bo;
548 uint32_t cursor_addr;
549 uint32_t cursor_cntl;
550 uint32_t cursor_size;
551 uint32_t cursor_base;
553 struct intel_initial_plane_config plane_config;
554 struct intel_crtc_state *config;
557 /* reset counter value when the last flip was submitted */
558 unsigned int reset_counter;
560 /* Access to these should be protected by dev_priv->irq_lock. */
561 bool cpu_fifo_underrun_disabled;
562 bool pch_fifo_underrun_disabled;
564 /* per-pipe watermark state */
566 /* watermarks currently being used */
567 struct intel_pipe_wm active;
568 /* SKL wm values currently in use */
569 struct skl_pipe_wm skl_active;
570 /* allow CxSR on this pipe */
576 struct intel_crtc_atomic_commit atomic;
578 /* scalers available on this crtc */
581 struct vlv_wm_state wm_state;
584 struct intel_plane_wm_parameters {
585 uint32_t horiz_pixels;
586 uint32_t vert_pixels;
588 * For packed pixel formats:
589 * bytes_per_pixel - holds bytes per pixel
590 * For planar pixel formats:
591 * bytes_per_pixel - holds bytes per pixel for uv-plane
592 * y_bytes_per_pixel - holds bytes per pixel for y-plane
594 uint8_t bytes_per_pixel;
595 uint8_t y_bytes_per_pixel;
599 unsigned int rotation;
604 struct drm_plane base;
609 uint32_t frontbuffer_bit;
611 /* Since we need to change the watermarks before/after
612 * enabling/disabling the planes, we need to store the parameters here
613 * as the other pieces of the struct may not reflect the values we want
614 * for the watermark calculations. Currently only Haswell uses this.
616 struct intel_plane_wm_parameters wm;
619 * NOTE: Do not place new plane state fields here (e.g., when adding
620 * new plane properties). New runtime state should now be placed in
621 * the intel_plane_state structure and accessed via drm_plane->state.
624 void (*update_plane)(struct drm_plane *plane,
625 struct drm_crtc *crtc,
626 struct drm_framebuffer *fb,
627 int crtc_x, int crtc_y,
628 unsigned int crtc_w, unsigned int crtc_h,
629 uint32_t x, uint32_t y,
630 uint32_t src_w, uint32_t src_h);
631 void (*disable_plane)(struct drm_plane *plane,
632 struct drm_crtc *crtc);
633 int (*check_plane)(struct drm_plane *plane,
634 struct intel_crtc_state *crtc_state,
635 struct intel_plane_state *state);
636 void (*commit_plane)(struct drm_plane *plane,
637 struct intel_plane_state *state);
640 struct intel_watermark_params {
641 unsigned long fifo_size;
642 unsigned long max_wm;
643 unsigned long default_wm;
644 unsigned long guard_size;
645 unsigned long cacheline_size;
648 struct cxsr_latency {
651 unsigned long fsb_freq;
652 unsigned long mem_freq;
653 unsigned long display_sr;
654 unsigned long display_hpll_disable;
655 unsigned long cursor_sr;
656 unsigned long cursor_hpll_disable;
659 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
660 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
661 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
662 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
663 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
664 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
665 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
666 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
667 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
672 uint32_t color_range;
673 bool color_range_auto;
676 enum hdmi_force_audio force_audio;
677 bool rgb_quant_range_selectable;
678 enum hdmi_picture_aspect aspect_ratio;
679 void (*write_infoframe)(struct drm_encoder *encoder,
680 enum hdmi_infoframe_type type,
681 const void *frame, ssize_t len);
682 void (*set_infoframes)(struct drm_encoder *encoder,
684 struct drm_display_mode *adjusted_mode);
685 bool (*infoframe_enabled)(struct drm_encoder *encoder);
688 struct intel_dp_mst_encoder;
689 #define DP_MAX_DOWNSTREAM_PORTS 0x10
693 * When platform provides two set of M_N registers for dp, we can
694 * program them and switch between them incase of DRRS.
695 * But When only one such register is provided, we have to program the
696 * required divider value on that registers itself based on the DRRS state.
698 * M1_N1 : Program dp_m_n on M1_N1 registers
699 * dp_m2_n2 on M2_N2 registers (If supported)
701 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
702 * M2_N2 registers are not supported
706 /* Sets the m1_n1 and m2_n2 */
713 uint32_t aux_ch_ctl_reg;
716 enum hdmi_force_audio force_audio;
717 uint32_t color_range;
718 bool color_range_auto;
722 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
723 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
724 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
725 /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
726 uint8_t num_sink_rates;
727 int sink_rates[DP_MAX_SUPPORTED_RATES];
728 struct drm_dp_aux aux;
729 uint8_t train_set[4];
730 int panel_power_up_delay;
731 int panel_power_down_delay;
732 int panel_power_cycle_delay;
733 int backlight_on_delay;
734 int backlight_off_delay;
735 struct delayed_work panel_vdd_work;
737 unsigned long last_power_cycle;
738 unsigned long last_power_on;
739 unsigned long last_backlight_off;
741 struct notifier_block edp_notifier;
744 * Pipe whose power sequencer is currently locked into
745 * this port. Only relevant on VLV/CHV.
748 struct edp_power_seq pps_delays;
751 bool can_mst; /* this port supports mst */
753 int active_mst_links;
754 /* connector directly attached - won't be use for modeset in mst world */
755 struct intel_connector *attached_connector;
757 /* mst connector list */
758 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
759 struct drm_dp_mst_topology_mgr mst_mgr;
761 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
763 * This function returns the value we have to program the AUX_CTL
764 * register with to kick off an AUX transaction.
766 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
769 uint32_t aux_clock_divider);
770 bool train_set_valid;
772 /* Displayport compliance testing */
773 unsigned long compliance_test_type;
774 unsigned long compliance_test_data;
775 bool compliance_test_active;
778 struct intel_digital_port {
779 struct intel_encoder base;
783 struct intel_hdmi hdmi;
784 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
787 struct intel_dp_mst_encoder {
788 struct intel_encoder base;
790 struct intel_digital_port *primary;
791 void *port; /* store this opaque as its illegal to dereference it */
795 vlv_dport_to_channel(struct intel_digital_port *dport)
797 switch (dport->port) {
809 vlv_pipe_to_channel(enum pipe pipe)
822 static inline struct drm_crtc *
823 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
825 struct drm_i915_private *dev_priv = dev->dev_private;
826 return dev_priv->pipe_to_crtc_mapping[pipe];
829 static inline struct drm_crtc *
830 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
832 struct drm_i915_private *dev_priv = dev->dev_private;
833 return dev_priv->plane_to_crtc_mapping[plane];
836 struct intel_unpin_work {
837 struct work_struct work;
838 struct drm_crtc *crtc;
839 struct drm_framebuffer *old_fb;
840 struct drm_i915_gem_object *pending_flip_obj;
841 struct drm_pending_vblank_event *event;
843 #define INTEL_FLIP_INACTIVE 0
844 #define INTEL_FLIP_PENDING 1
845 #define INTEL_FLIP_COMPLETE 2
848 struct drm_i915_gem_request *flip_queued_req;
849 int flip_queued_vblank;
850 int flip_ready_vblank;
851 bool enable_stall_check;
854 struct intel_load_detect_pipe {
855 struct drm_framebuffer *release_fb;
856 bool load_detect_temp;
860 static inline struct intel_encoder *
861 intel_attached_encoder(struct drm_connector *connector)
863 return to_intel_connector(connector)->encoder;
866 static inline struct intel_digital_port *
867 enc_to_dig_port(struct drm_encoder *encoder)
869 return container_of(encoder, struct intel_digital_port, base.base);
872 static inline struct intel_dp_mst_encoder *
873 enc_to_mst(struct drm_encoder *encoder)
875 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
878 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
880 return &enc_to_dig_port(encoder)->dp;
883 static inline struct intel_digital_port *
884 dp_to_dig_port(struct intel_dp *intel_dp)
886 return container_of(intel_dp, struct intel_digital_port, dp);
889 static inline struct intel_digital_port *
890 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
892 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
896 * Returns the number of planes for this pipe, ie the number of sprites + 1
897 * (primary plane). This doesn't count the cursor plane then.
899 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
901 return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
904 /* intel_fifo_underrun.c */
905 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
906 enum pipe pipe, bool enable);
907 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
908 enum transcoder pch_transcoder,
910 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
912 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
913 enum transcoder pch_transcoder);
914 void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv);
917 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
918 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
919 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
920 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
921 void gen6_reset_rps_interrupts(struct drm_device *dev);
922 void gen6_enable_rps_interrupts(struct drm_device *dev);
923 void gen6_disable_rps_interrupts(struct drm_device *dev);
924 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
925 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
926 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
927 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
930 * We only use drm_irq_uninstall() at unload and VT switch, so
931 * this is the only thing we need to check.
933 return dev_priv->pm.irqs_enabled;
936 int intel_get_crtc_scanline(struct intel_crtc *crtc);
937 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
938 unsigned int pipe_mask);
941 void intel_crt_init(struct drm_device *dev);
945 void intel_prepare_ddi(struct drm_device *dev);
946 void hsw_fdi_link_train(struct drm_crtc *crtc);
947 void intel_ddi_init(struct drm_device *dev, enum port port);
948 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
949 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
950 void intel_ddi_pll_init(struct drm_device *dev);
951 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
952 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
953 enum transcoder cpu_transcoder);
954 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
955 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
956 bool intel_ddi_pll_select(struct intel_crtc *crtc,
957 struct intel_crtc_state *crtc_state);
958 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
959 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
960 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
961 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
962 void intel_ddi_get_config(struct intel_encoder *encoder,
963 struct intel_crtc_state *pipe_config);
964 struct intel_encoder *
965 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
967 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
968 void intel_ddi_clock_get(struct intel_encoder *encoder,
969 struct intel_crtc_state *pipe_config);
970 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
971 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
973 /* intel_frontbuffer.c */
974 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
975 enum fb_op_origin origin);
976 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
977 unsigned frontbuffer_bits);
978 void intel_frontbuffer_flip_complete(struct drm_device *dev,
979 unsigned frontbuffer_bits);
980 void intel_frontbuffer_flush(struct drm_device *dev,
981 unsigned frontbuffer_bits);
982 void intel_frontbuffer_flip(struct drm_device *dev,
983 unsigned frontbuffer_bits);
985 unsigned int intel_fb_align_height(struct drm_device *dev,
987 uint32_t pixel_format,
988 uint64_t fb_format_modifier);
989 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire);
991 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
992 uint32_t pixel_format);
995 void intel_init_audio(struct drm_device *dev);
996 void intel_audio_codec_enable(struct intel_encoder *encoder);
997 void intel_audio_codec_disable(struct intel_encoder *encoder);
998 void i915_audio_component_init(struct drm_i915_private *dev_priv);
999 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1001 /* intel_display.c */
1002 extern const struct drm_plane_funcs intel_plane_funcs;
1003 bool intel_has_pending_fb_unpin(struct drm_device *dev);
1004 int intel_pch_rawclk(struct drm_device *dev);
1005 void intel_mark_busy(struct drm_device *dev);
1006 void intel_mark_idle(struct drm_device *dev);
1007 void intel_crtc_restore_mode(struct drm_crtc *crtc);
1008 void intel_display_suspend(struct drm_device *dev);
1009 int intel_crtc_control(struct drm_crtc *crtc, bool enable);
1010 void intel_crtc_update_dpms(struct drm_crtc *crtc);
1011 void intel_encoder_destroy(struct drm_encoder *encoder);
1012 int intel_connector_init(struct intel_connector *);
1013 struct intel_connector *intel_connector_alloc(void);
1014 void intel_connector_dpms(struct drm_connector *, int mode);
1015 bool intel_connector_get_hw_state(struct intel_connector *connector);
1016 void intel_modeset_check_state(struct drm_device *dev);
1017 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1018 struct intel_digital_port *port);
1019 void intel_connector_attach_encoder(struct intel_connector *connector,
1020 struct intel_encoder *encoder);
1021 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
1022 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1023 struct drm_crtc *crtc);
1024 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1025 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1026 struct drm_file *file_priv);
1027 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1029 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
1031 intel_wait_for_vblank(struct drm_device *dev, int pipe)
1033 drm_wait_one_vblank(dev, pipe);
1035 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1036 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1037 struct intel_digital_port *dport,
1038 unsigned int expected_mask);
1039 bool intel_get_load_detect_pipe(struct drm_connector *connector,
1040 struct drm_display_mode *mode,
1041 struct intel_load_detect_pipe *old,
1042 struct drm_modeset_acquire_ctx *ctx);
1043 void intel_release_load_detect_pipe(struct drm_connector *connector,
1044 struct intel_load_detect_pipe *old,
1045 struct drm_modeset_acquire_ctx *ctx);
1046 int intel_pin_and_fence_fb_obj(struct drm_plane *plane,
1047 struct drm_framebuffer *fb,
1048 const struct drm_plane_state *plane_state,
1049 struct intel_engine_cs *pipelined,
1050 struct drm_i915_gem_request **pipelined_request);
1051 struct drm_framebuffer *
1052 __intel_framebuffer_create(struct drm_device *dev,
1053 struct drm_mode_fb_cmd2 *mode_cmd,
1054 struct drm_i915_gem_object *obj);
1055 void intel_prepare_page_flip(struct drm_device *dev, int plane);
1056 void intel_finish_page_flip(struct drm_device *dev, int pipe);
1057 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
1058 void intel_check_page_flip(struct drm_device *dev, int pipe);
1059 int intel_prepare_plane_fb(struct drm_plane *plane,
1060 struct drm_framebuffer *fb,
1061 const struct drm_plane_state *new_state);
1062 void intel_cleanup_plane_fb(struct drm_plane *plane,
1063 struct drm_framebuffer *fb,
1064 const struct drm_plane_state *old_state);
1065 int intel_plane_atomic_get_property(struct drm_plane *plane,
1066 const struct drm_plane_state *state,
1067 struct drm_property *property,
1069 int intel_plane_atomic_set_property(struct drm_plane *plane,
1070 struct drm_plane_state *state,
1071 struct drm_property *property,
1073 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1074 struct drm_plane_state *plane_state);
1077 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
1078 uint64_t fb_format_modifier);
1081 intel_rotation_90_or_270(unsigned int rotation)
1083 return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
1086 void intel_create_rotation_property(struct drm_device *dev,
1087 struct intel_plane *plane);
1089 /* shared dpll functions */
1090 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
1091 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1092 struct intel_shared_dpll *pll,
1094 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
1095 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
1096 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
1097 struct intel_crtc_state *state);
1099 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1100 const struct dpll *dpll);
1101 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1103 /* modesetting asserts */
1104 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1106 void assert_pll(struct drm_i915_private *dev_priv,
1107 enum pipe pipe, bool state);
1108 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1109 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1110 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1111 enum pipe pipe, bool state);
1112 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1113 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1114 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1115 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1116 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1117 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
1119 unsigned int tiling_mode,
1121 unsigned int pitch);
1122 void intel_prepare_reset(struct drm_device *dev);
1123 void intel_finish_reset(struct drm_device *dev);
1124 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1125 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1126 void broxton_init_cdclk(struct drm_device *dev);
1127 void broxton_uninit_cdclk(struct drm_device *dev);
1128 void broxton_ddi_phy_init(struct drm_device *dev);
1129 void broxton_ddi_phy_uninit(struct drm_device *dev);
1130 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1131 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1132 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1133 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1134 void intel_dp_get_m_n(struct intel_crtc *crtc,
1135 struct intel_crtc_state *pipe_config);
1136 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1137 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1139 ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
1141 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1142 intel_clock_t *best_clock);
1143 int chv_calc_dpll_params(int refclk, intel_clock_t *pll_clock);
1145 bool intel_crtc_active(struct drm_crtc *crtc);
1146 void hsw_enable_ips(struct intel_crtc *crtc);
1147 void hsw_disable_ips(struct intel_crtc *crtc);
1148 enum intel_display_power_domain
1149 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1150 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1151 struct intel_crtc_state *pipe_config);
1152 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
1153 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
1155 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state, int force_detach);
1156 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1158 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
1159 struct drm_i915_gem_object *obj);
1160 u32 skl_plane_ctl_format(uint32_t pixel_format);
1161 u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1162 u32 skl_plane_ctl_rotation(unsigned int rotation);
1165 void intel_csr_ucode_init(struct drm_device *dev);
1166 enum csr_state intel_csr_load_status_get(struct drm_i915_private *dev_priv);
1167 void intel_csr_load_status_set(struct drm_i915_private *dev_priv,
1168 enum csr_state state);
1169 void intel_csr_load_program(struct drm_device *dev);
1170 void intel_csr_ucode_fini(struct drm_device *dev);
1171 void assert_csr_loaded(struct drm_i915_private *dev_priv);
1174 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
1175 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1176 struct intel_connector *intel_connector);
1177 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1178 void intel_dp_complete_link_train(struct intel_dp *intel_dp);
1179 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1180 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1181 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1182 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1183 bool intel_dp_compute_config(struct intel_encoder *encoder,
1184 struct intel_crtc_state *pipe_config);
1185 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1186 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1188 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1189 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1190 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1191 void intel_edp_panel_on(struct intel_dp *intel_dp);
1192 void intel_edp_panel_off(struct intel_dp *intel_dp);
1193 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1194 void intel_dp_mst_suspend(struct drm_device *dev);
1195 void intel_dp_mst_resume(struct drm_device *dev);
1196 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1197 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1198 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1199 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
1200 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1201 void intel_plane_destroy(struct drm_plane *plane);
1202 void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1203 void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1204 void intel_edp_drrs_invalidate(struct drm_device *dev,
1205 unsigned frontbuffer_bits);
1206 void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
1208 /* intel_dp_mst.c */
1209 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1210 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1212 void intel_dsi_init(struct drm_device *dev);
1216 void intel_dvo_init(struct drm_device *dev);
1219 /* legacy fbdev emulation in intel_fbdev.c */
1220 #ifdef CONFIG_DRM_I915_FBDEV
1221 extern int intel_fbdev_init(struct drm_device *dev);
1222 extern void intel_fbdev_initial_config(void *data, async_cookie_t cookie);
1223 extern void intel_fbdev_fini(struct drm_device *dev);
1224 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1225 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1226 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1228 static inline int intel_fbdev_init(struct drm_device *dev)
1233 static inline void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
1237 static inline void intel_fbdev_fini(struct drm_device *dev)
1241 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1245 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1251 bool intel_fbc_enabled(struct drm_device *dev);
1252 void intel_fbc_update(struct drm_device *dev);
1253 void intel_fbc_init(struct drm_i915_private *dev_priv);
1254 void intel_fbc_disable(struct drm_device *dev);
1255 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1256 unsigned int frontbuffer_bits,
1257 enum fb_op_origin origin);
1258 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1259 unsigned int frontbuffer_bits);
1260 const char *intel_no_fbc_reason_str(enum no_fbc_reason reason);
1261 void intel_fbc_cleanup_cfb(struct drm_device *dev);
1264 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
1265 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1266 struct intel_connector *intel_connector);
1267 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1268 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1269 struct intel_crtc_state *pipe_config);
1273 void intel_lvds_init(struct drm_device *dev);
1274 bool intel_is_dual_link_lvds(struct drm_device *dev);
1278 int intel_connector_update_modes(struct drm_connector *connector,
1280 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1281 void intel_attach_force_audio_property(struct drm_connector *connector);
1282 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1285 /* intel_overlay.c */
1286 void intel_setup_overlay(struct drm_device *dev);
1287 void intel_cleanup_overlay(struct drm_device *dev);
1288 int intel_overlay_switch_off(struct intel_overlay *overlay);
1289 int intel_overlay_put_image(struct drm_device *dev, void *data,
1290 struct drm_file *file_priv);
1291 int intel_overlay_attrs(struct drm_device *dev, void *data,
1292 struct drm_file *file_priv);
1293 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1297 int intel_panel_init(struct intel_panel *panel,
1298 struct drm_display_mode *fixed_mode,
1299 struct drm_display_mode *downclock_mode);
1300 void intel_panel_fini(struct intel_panel *panel);
1301 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1302 struct drm_display_mode *adjusted_mode);
1303 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1304 struct intel_crtc_state *pipe_config,
1306 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1307 struct intel_crtc_state *pipe_config,
1309 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1310 u32 level, u32 max);
1311 int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
1312 void intel_panel_enable_backlight(struct intel_connector *connector);
1313 void intel_panel_disable_backlight(struct intel_connector *connector);
1314 void intel_panel_destroy_backlight(struct drm_connector *connector);
1315 void intel_panel_init_backlight_funcs(struct drm_device *dev);
1316 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1317 extern struct drm_display_mode *intel_find_panel_downclock(
1318 struct drm_device *dev,
1319 struct drm_display_mode *fixed_mode,
1320 struct drm_connector *connector);
1321 void intel_backlight_register(struct drm_device *dev);
1322 void intel_backlight_unregister(struct drm_device *dev);
1326 void intel_psr_enable(struct intel_dp *intel_dp);
1327 void intel_psr_disable(struct intel_dp *intel_dp);
1328 void intel_psr_invalidate(struct drm_device *dev,
1329 unsigned frontbuffer_bits);
1330 void intel_psr_flush(struct drm_device *dev,
1331 unsigned frontbuffer_bits);
1332 void intel_psr_init(struct drm_device *dev);
1333 void intel_psr_single_frame_update(struct drm_device *dev,
1334 unsigned frontbuffer_bits);
1336 /* intel_runtime_pm.c */
1337 int intel_power_domains_init(struct drm_i915_private *);
1338 void intel_power_domains_fini(struct drm_i915_private *);
1339 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
1340 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1342 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1343 enum intel_display_power_domain domain);
1344 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1345 enum intel_display_power_domain domain);
1346 void intel_display_power_get(struct drm_i915_private *dev_priv,
1347 enum intel_display_power_domain domain);
1348 void intel_display_power_put(struct drm_i915_private *dev_priv,
1349 enum intel_display_power_domain domain);
1350 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
1351 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
1352 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1353 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1354 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1356 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1359 void intel_init_clock_gating(struct drm_device *dev);
1360 void intel_suspend_hw(struct drm_device *dev);
1361 int ilk_wm_max_level(const struct drm_device *dev);
1362 void intel_update_watermarks(struct drm_crtc *crtc);
1363 void intel_update_sprite_watermarks(struct drm_plane *plane,
1364 struct drm_crtc *crtc,
1365 uint32_t sprite_width,
1366 uint32_t sprite_height,
1368 bool enabled, bool scaled);
1369 void intel_init_pm(struct drm_device *dev);
1370 void intel_pm_setup(struct drm_device *dev);
1371 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1372 void intel_gpu_ips_teardown(void);
1373 void intel_init_gt_powersave(struct drm_device *dev);
1374 void intel_cleanup_gt_powersave(struct drm_device *dev);
1375 void intel_enable_gt_powersave(struct drm_device *dev);
1376 void intel_disable_gt_powersave(struct drm_device *dev);
1377 void intel_suspend_gt_powersave(struct drm_device *dev);
1378 void intel_reset_gt_powersave(struct drm_device *dev);
1379 void gen6_update_ring_freq(struct drm_device *dev);
1380 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1381 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1382 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1383 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1384 struct intel_rps_client *rps,
1385 unsigned long submitted);
1386 void intel_queue_rps_boost_for_request(struct drm_device *dev,
1387 struct drm_i915_gem_request *req);
1388 void vlv_wm_get_hw_state(struct drm_device *dev);
1389 void ilk_wm_get_hw_state(struct drm_device *dev);
1390 void skl_wm_get_hw_state(struct drm_device *dev);
1391 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1392 struct skl_ddb_allocation *ddb /* out */);
1393 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
1396 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
1399 /* intel_sprite.c */
1400 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1401 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1402 struct drm_file *file_priv);
1403 bool intel_pipe_update_start(struct intel_crtc *crtc,
1404 uint32_t *start_vbl_count);
1405 void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count);
1408 void intel_tv_init(struct drm_device *dev);
1410 /* intel_atomic.c */
1411 int intel_atomic_check(struct drm_device *dev,
1412 struct drm_atomic_state *state);
1413 int intel_atomic_commit(struct drm_device *dev,
1414 struct drm_atomic_state *state,
1416 int intel_connector_atomic_get_property(struct drm_connector *connector,
1417 const struct drm_connector_state *state,
1418 struct drm_property *property,
1420 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1421 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1422 struct drm_crtc_state *state);
1423 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1424 void intel_atomic_state_clear(struct drm_atomic_state *);
1425 struct intel_shared_dpll_config *
1426 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
1428 static inline struct intel_crtc_state *
1429 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1430 struct intel_crtc *crtc)
1432 struct drm_crtc_state *crtc_state;
1433 crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1434 if (IS_ERR(crtc_state))
1435 return ERR_CAST(crtc_state);
1437 return to_intel_crtc_state(crtc_state);
1439 int intel_atomic_setup_scalers(struct drm_device *dev,
1440 struct intel_crtc *intel_crtc,
1441 struct intel_crtc_state *crtc_state);
1443 /* intel_atomic_plane.c */
1444 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1445 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1446 void intel_plane_destroy_state(struct drm_plane *plane,
1447 struct drm_plane_state *state);
1448 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1450 #endif /* __INTEL_DRV_H__ */