2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/i2c.h>
29 #include <linux/hdmi.h>
30 #include <drm/i915_drm.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_fb_helper.h>
35 #include <drm/drm_dp_helper.h>
38 * _wait_for - magic (register) wait macro
40 * Does the right thing for modeset paths when run under kdgb or similar atomic
41 * contexts. Note that it's important that we check the condition again after
42 * having timed out, since the timeout could be due to preemption or similar and
43 * we've never had a chance to check the condition before the timeout.
45 #define _wait_for(COND, MS, W) ({ \
46 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
49 if (time_after(jiffies, timeout__)) { \
54 if (W && drm_can_sleep()) { \
63 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
64 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
65 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
66 DIV_ROUND_UP((US), 1000), 0)
68 #define KHz(x) (1000*x)
69 #define MHz(x) KHz(1000*x)
72 * Display related stuff
75 /* store information about an Ixxx DVO */
76 /* The i830->i865 use multiple DVOs with multiple i2cs */
77 /* the i915, i945 have a single sDVO i2c bus - which is different */
79 /* maximum connectors per crtcs in the mode set */
80 #define INTELFB_CONN_LIMIT 4
82 #define INTEL_I2C_BUS_DVO 1
83 #define INTEL_I2C_BUS_SDVO 2
85 /* these are outputs from the chip - integrated only
86 external chips are via DVO or SDVO output */
87 #define INTEL_OUTPUT_UNUSED 0
88 #define INTEL_OUTPUT_ANALOG 1
89 #define INTEL_OUTPUT_DVO 2
90 #define INTEL_OUTPUT_SDVO 3
91 #define INTEL_OUTPUT_LVDS 4
92 #define INTEL_OUTPUT_TVOUT 5
93 #define INTEL_OUTPUT_HDMI 6
94 #define INTEL_OUTPUT_DISPLAYPORT 7
95 #define INTEL_OUTPUT_EDP 8
96 #define INTEL_OUTPUT_UNKNOWN 9
98 #define INTEL_DVO_CHIP_NONE 0
99 #define INTEL_DVO_CHIP_LVDS 1
100 #define INTEL_DVO_CHIP_TMDS 2
101 #define INTEL_DVO_CHIP_TVOUT 4
103 struct intel_framebuffer {
104 struct drm_framebuffer base;
105 struct drm_i915_gem_object *obj;
109 struct drm_fb_helper helper;
110 struct intel_framebuffer ifb;
111 struct list_head fbdev_list;
112 struct drm_display_mode *our_mode;
115 struct intel_encoder {
116 struct drm_encoder base;
118 * The new crtc this encoder will be driven from. Only differs from
119 * base->crtc while a modeset is in progress.
121 struct intel_crtc *new_crtc;
125 * Intel hw has only one MUX where encoders could be clone, hence a
126 * simple flag is enough to compute the possible_clones mask.
129 bool connectors_active;
130 void (*hot_plug)(struct intel_encoder *);
131 bool (*compute_config)(struct intel_encoder *,
132 struct intel_crtc_config *);
133 void (*pre_pll_enable)(struct intel_encoder *);
134 void (*pre_enable)(struct intel_encoder *);
135 void (*enable)(struct intel_encoder *);
136 void (*mode_set)(struct intel_encoder *intel_encoder);
137 void (*disable)(struct intel_encoder *);
138 void (*post_disable)(struct intel_encoder *);
139 /* Read out the current hw state of this connector, returning true if
140 * the encoder is active. If the encoder is enabled it also set the pipe
141 * it is connected to in the pipe parameter. */
142 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
143 /* Reconstructs the equivalent mode flags for the current hardware
144 * state. This must be called _after_ display->get_pipe_config has
145 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
146 * be set correctly before calling this function. */
147 void (*get_config)(struct intel_encoder *,
148 struct intel_crtc_config *pipe_config);
150 enum hpd_pin hpd_pin;
154 struct drm_display_mode *fixed_mode;
158 struct intel_connector {
159 struct drm_connector base;
161 * The fixed encoder this connector is connected to.
163 struct intel_encoder *encoder;
166 * The new encoder this connector will be driven. Only differs from
167 * encoder while a modeset is in progress.
169 struct intel_encoder *new_encoder;
171 /* Reads out the current hw, returning true if the connector is enabled
172 * and active (i.e. dpms ON state). */
173 bool (*get_hw_state)(struct intel_connector *);
175 /* Panel info for eDP and LVDS */
176 struct intel_panel panel;
178 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
181 /* since POLL and HPD connectors may use the same HPD line keep the native
182 state of connector->polled in case hotplug storm detection changes it */
186 typedef struct dpll {
198 struct intel_crtc_config {
200 * quirks - bitfield with hw state readout quirks
202 * For various reasons the hw state readout code might not be able to
203 * completely faithfully read out the current state. These cases are
204 * tracked with quirk flags so that fastboot and state checker can act
207 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
208 unsigned long quirks;
210 struct drm_display_mode requested_mode;
211 struct drm_display_mode adjusted_mode;
212 /* Whether to set up the PCH/FDI. Note that we never allow sharing
213 * between pch encoders and cpu encoders. */
214 bool has_pch_encoder;
216 /* CPU Transcoder for the pipe. Currently this can only differ from the
217 * pipe on Haswell (where we have a special eDP transcoder). */
218 enum transcoder cpu_transcoder;
221 * Use reduced/limited/broadcast rbg range, compressing from the full
222 * range fed into the crtcs.
224 bool limited_color_range;
226 /* DP has a bunch of special case unfortunately, so mark the pipe
231 * Enable dithering, used when the selected pipe bpp doesn't match the
236 /* Controls for the clock computation, to override various stages. */
239 /* SDVO TV has a bunch of special case. To make multifunction encoders
240 * work correctly, we need to track this at runtime.*/
244 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
245 * required. This is set in the 2nd loop of calling encoder's
246 * ->compute_config if the first pick doesn't work out.
250 /* Settings for the intel dpll used on pretty much everything but
254 /* Selected dpll when shared or DPLL_ID_PRIVATE. */
255 enum intel_dpll_id shared_dpll;
257 /* Actual register state of the dpll, for shared dpll cross-checking. */
258 struct intel_dpll_hw_state dpll_hw_state;
261 struct intel_link_m_n dp_m_n;
264 * Frequence the dpll for the port should run at. Differs from the
265 * adjusted dotclock e.g. for DP or 12bpc hdmi mode.
269 /* Used by SDVO (and if we ever fix it, HDMI). */
270 unsigned pixel_multiplier;
272 /* Panel fitter controls for gen2-gen4 + VLV */
276 u32 lvds_border_bits;
279 /* Panel fitter placement and size for Ironlake+ */
285 /* FDI configuration, only valid if has_pch_encoder is set. */
287 struct intel_link_m_n fdi_m_n;
293 struct drm_crtc base;
296 u8 lut_r[256], lut_g[256], lut_b[256];
298 * Whether the crtc and the connected output pipeline is active. Implies
299 * that crtc->enabled is set, i.e. the current mode configuration has
300 * some outputs connected to this crtc.
304 bool primary_disabled; /* is the crtc obscured by a plane? */
306 struct intel_overlay *overlay;
307 struct intel_unpin_work *unpin_work;
309 atomic_t unpin_work_count;
311 /* Display surface base address adjustement for pageflips. Note that on
312 * gen4+ this only adjusts up to a tile, offsets within a tile are
313 * handled in the hw itself (with the TILEOFF register). */
314 unsigned long dspaddr_offset;
316 struct drm_i915_gem_object *cursor_bo;
317 uint32_t cursor_addr;
318 int16_t cursor_x, cursor_y;
319 int16_t cursor_width, cursor_height;
322 struct intel_crtc_config config;
324 uint32_t ddi_pll_sel;
326 /* reset counter value when the last flip was submitted */
327 unsigned int reset_counter;
329 /* Access to these should be protected by dev_priv->irq_lock. */
330 bool cpu_fifo_underrun_disabled;
331 bool pch_fifo_underrun_disabled;
334 struct intel_plane_wm_parameters {
335 uint32_t horiz_pixels;
336 uint8_t bytes_per_pixel;
342 struct drm_plane base;
345 struct drm_i915_gem_object *obj;
348 u32 lut_r[1024], lut_g[1024], lut_b[1024];
350 unsigned int crtc_w, crtc_h;
351 uint32_t src_x, src_y;
352 uint32_t src_w, src_h;
354 /* Since we need to change the watermarks before/after
355 * enabling/disabling the planes, we need to store the parameters here
356 * as the other pieces of the struct may not reflect the values we want
357 * for the watermark calculations. Currently only Haswell uses this.
359 struct intel_plane_wm_parameters wm;
361 void (*update_plane)(struct drm_plane *plane,
362 struct drm_crtc *crtc,
363 struct drm_framebuffer *fb,
364 struct drm_i915_gem_object *obj,
365 int crtc_x, int crtc_y,
366 unsigned int crtc_w, unsigned int crtc_h,
367 uint32_t x, uint32_t y,
368 uint32_t src_w, uint32_t src_h);
369 void (*disable_plane)(struct drm_plane *plane,
370 struct drm_crtc *crtc);
371 int (*update_colorkey)(struct drm_plane *plane,
372 struct drm_intel_sprite_colorkey *key);
373 void (*get_colorkey)(struct drm_plane *plane,
374 struct drm_intel_sprite_colorkey *key);
377 struct intel_watermark_params {
378 unsigned long fifo_size;
379 unsigned long max_wm;
380 unsigned long default_wm;
381 unsigned long guard_size;
382 unsigned long cacheline_size;
385 struct cxsr_latency {
388 unsigned long fsb_freq;
389 unsigned long mem_freq;
390 unsigned long display_sr;
391 unsigned long display_hpll_disable;
392 unsigned long cursor_sr;
393 unsigned long cursor_hpll_disable;
396 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
397 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
398 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
399 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
400 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
405 uint32_t color_range;
406 bool color_range_auto;
409 enum hdmi_force_audio force_audio;
410 bool rgb_quant_range_selectable;
411 void (*write_infoframe)(struct drm_encoder *encoder,
412 enum hdmi_infoframe_type type,
413 const uint8_t *frame, ssize_t len);
414 void (*set_infoframes)(struct drm_encoder *encoder,
415 struct drm_display_mode *adjusted_mode);
418 #define DP_MAX_DOWNSTREAM_PORTS 0x10
419 #define DP_LINK_CONFIGURATION_SIZE 9
423 uint32_t aux_ch_ctl_reg;
425 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
427 enum hdmi_force_audio force_audio;
428 uint32_t color_range;
429 bool color_range_auto;
432 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
433 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
434 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
435 struct i2c_adapter adapter;
436 struct i2c_algo_dp_aux_data algo;
437 uint8_t train_set[4];
438 int panel_power_up_delay;
439 int panel_power_down_delay;
440 int panel_power_cycle_delay;
441 int backlight_on_delay;
442 int backlight_off_delay;
443 struct delayed_work panel_vdd_work;
446 struct intel_connector *attached_connector;
449 struct intel_digital_port {
450 struct intel_encoder base;
454 struct intel_hdmi hdmi;
458 vlv_dport_to_channel(struct intel_digital_port *dport)
460 switch (dport->port) {
470 static inline struct drm_crtc *
471 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
473 struct drm_i915_private *dev_priv = dev->dev_private;
474 return dev_priv->pipe_to_crtc_mapping[pipe];
477 static inline struct drm_crtc *
478 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
480 struct drm_i915_private *dev_priv = dev->dev_private;
481 return dev_priv->plane_to_crtc_mapping[plane];
484 struct intel_unpin_work {
485 struct work_struct work;
486 struct drm_crtc *crtc;
487 struct drm_i915_gem_object *old_fb_obj;
488 struct drm_i915_gem_object *pending_flip_obj;
489 struct drm_pending_vblank_event *event;
491 #define INTEL_FLIP_INACTIVE 0
492 #define INTEL_FLIP_PENDING 1
493 #define INTEL_FLIP_COMPLETE 2
494 bool enable_stall_check;
497 int intel_pch_rawclk(struct drm_device *dev);
499 int intel_connector_update_modes(struct drm_connector *connector,
501 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
503 extern void intel_attach_force_audio_property(struct drm_connector *connector);
504 extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
506 extern bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
507 extern void intel_crt_init(struct drm_device *dev);
508 extern void intel_hdmi_init(struct drm_device *dev,
509 int hdmi_reg, enum port port);
510 extern void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
511 struct intel_connector *intel_connector);
512 extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
513 extern bool intel_hdmi_compute_config(struct intel_encoder *encoder,
514 struct intel_crtc_config *pipe_config);
515 extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg,
517 extern void intel_dvo_init(struct drm_device *dev);
518 extern void intel_tv_init(struct drm_device *dev);
519 extern void intel_mark_busy(struct drm_device *dev);
520 extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
521 struct intel_ring_buffer *ring);
522 extern void intel_mark_idle(struct drm_device *dev);
523 extern void intel_lvds_init(struct drm_device *dev);
524 extern bool intel_is_dual_link_lvds(struct drm_device *dev);
525 extern void intel_dp_init(struct drm_device *dev, int output_reg,
527 extern bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
528 struct intel_connector *intel_connector);
529 extern void intel_dp_init_link_config(struct intel_dp *intel_dp);
530 extern void intel_dp_start_link_train(struct intel_dp *intel_dp);
531 extern void intel_dp_complete_link_train(struct intel_dp *intel_dp);
532 extern void intel_dp_stop_link_train(struct intel_dp *intel_dp);
533 extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
534 extern void intel_dp_encoder_destroy(struct drm_encoder *encoder);
535 extern void intel_dp_check_link_status(struct intel_dp *intel_dp);
536 extern bool intel_dp_compute_config(struct intel_encoder *encoder,
537 struct intel_crtc_config *pipe_config);
538 extern bool intel_dpd_is_edp(struct drm_device *dev);
539 extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp);
540 extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp);
541 extern void ironlake_edp_panel_on(struct intel_dp *intel_dp);
542 extern void ironlake_edp_panel_off(struct intel_dp *intel_dp);
543 extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
544 extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
545 extern int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
546 extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
550 extern int intel_panel_init(struct intel_panel *panel,
551 struct drm_display_mode *fixed_mode);
552 extern void intel_panel_fini(struct intel_panel *panel);
554 extern void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
555 struct drm_display_mode *adjusted_mode);
556 extern void intel_pch_panel_fitting(struct intel_crtc *crtc,
557 struct intel_crtc_config *pipe_config,
559 extern void intel_gmch_panel_fitting(struct intel_crtc *crtc,
560 struct intel_crtc_config *pipe_config,
562 extern void intel_panel_set_backlight(struct drm_device *dev,
564 extern int intel_panel_setup_backlight(struct drm_connector *connector);
565 extern void intel_panel_enable_backlight(struct drm_device *dev,
567 extern void intel_panel_disable_backlight(struct drm_device *dev);
568 extern void intel_panel_destroy_backlight(struct drm_device *dev);
569 extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
571 struct intel_set_config {
572 struct drm_encoder **save_connector_encoders;
573 struct drm_crtc **save_encoder_crtcs;
579 extern void intel_crtc_restore_mode(struct drm_crtc *crtc);
580 extern void intel_crtc_load_lut(struct drm_crtc *crtc);
581 extern void intel_crtc_update_dpms(struct drm_crtc *crtc);
582 extern void intel_encoder_destroy(struct drm_encoder *encoder);
583 extern void intel_connector_dpms(struct drm_connector *, int mode);
584 extern bool intel_connector_get_hw_state(struct intel_connector *connector);
585 extern void intel_modeset_check_state(struct drm_device *dev);
586 extern void intel_plane_restore(struct drm_plane *plane);
587 extern void intel_plane_disable(struct drm_plane *plane);
590 static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector)
592 return to_intel_connector(connector)->encoder;
595 static inline struct intel_digital_port *
596 enc_to_dig_port(struct drm_encoder *encoder)
598 return container_of(encoder, struct intel_digital_port, base.base);
601 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
603 return &enc_to_dig_port(encoder)->dp;
606 static inline struct intel_digital_port *
607 dp_to_dig_port(struct intel_dp *intel_dp)
609 return container_of(intel_dp, struct intel_digital_port, dp);
612 static inline struct intel_digital_port *
613 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
615 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
618 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
619 struct intel_digital_port *port);
621 extern void intel_connector_attach_encoder(struct intel_connector *connector,
622 struct intel_encoder *encoder);
623 extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
625 extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
626 struct drm_crtc *crtc);
627 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
628 struct drm_file *file_priv);
629 extern enum transcoder
630 intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
632 extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
633 extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
634 extern int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
635 extern void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port);
637 struct intel_load_detect_pipe {
638 struct drm_framebuffer *release_fb;
639 bool load_detect_temp;
642 extern bool intel_get_load_detect_pipe(struct drm_connector *connector,
643 struct drm_display_mode *mode,
644 struct intel_load_detect_pipe *old);
645 extern void intel_release_load_detect_pipe(struct drm_connector *connector,
646 struct intel_load_detect_pipe *old);
648 extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
649 u16 blue, int regno);
650 extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
651 u16 *blue, int regno);
653 extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
654 struct drm_i915_gem_object *obj,
655 struct intel_ring_buffer *pipelined);
656 extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
658 extern int intel_framebuffer_init(struct drm_device *dev,
659 struct intel_framebuffer *ifb,
660 struct drm_mode_fb_cmd2 *mode_cmd,
661 struct drm_i915_gem_object *obj);
662 extern void intel_framebuffer_fini(struct intel_framebuffer *fb);
663 extern int intel_fbdev_init(struct drm_device *dev);
664 extern void intel_fbdev_initial_config(struct drm_device *dev);
665 extern void intel_fbdev_fini(struct drm_device *dev);
666 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
667 extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
668 extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
669 extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
671 extern void intel_setup_overlay(struct drm_device *dev);
672 extern void intel_cleanup_overlay(struct drm_device *dev);
673 extern int intel_overlay_switch_off(struct intel_overlay *overlay);
674 extern int intel_overlay_put_image(struct drm_device *dev, void *data,
675 struct drm_file *file_priv);
676 extern int intel_overlay_attrs(struct drm_device *dev, void *data,
677 struct drm_file *file_priv);
679 extern void intel_fb_output_poll_changed(struct drm_device *dev);
680 extern void intel_fb_restore_mode(struct drm_device *dev);
682 struct intel_shared_dpll *
683 intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
685 void assert_shared_dpll(struct drm_i915_private *dev_priv,
686 struct intel_shared_dpll *pll,
688 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
689 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
690 void assert_pll(struct drm_i915_private *dev_priv,
691 enum pipe pipe, bool state);
692 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
693 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
694 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
695 enum pipe pipe, bool state);
696 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
697 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
698 extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
700 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
701 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
703 extern void intel_init_clock_gating(struct drm_device *dev);
704 extern void intel_suspend_hw(struct drm_device *dev);
705 extern void intel_write_eld(struct drm_encoder *encoder,
706 struct drm_display_mode *mode);
707 extern void intel_prepare_ddi(struct drm_device *dev);
708 extern void hsw_fdi_link_train(struct drm_crtc *crtc);
709 extern void intel_ddi_init(struct drm_device *dev, enum port port);
711 /* For use by IVB LP watermark workaround in intel_sprite.c */
712 extern void intel_update_watermarks(struct drm_device *dev);
713 extern void intel_update_sprite_watermarks(struct drm_plane *plane,
714 struct drm_crtc *crtc,
715 uint32_t sprite_width, int pixel_size,
716 bool enabled, bool scaled);
718 extern unsigned long intel_gen4_compute_page_offset(int *x, int *y,
719 unsigned int tiling_mode,
723 extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
724 struct drm_file *file_priv);
725 extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
726 struct drm_file *file_priv);
728 /* Power-related functions, located in intel_pm.c */
729 extern void intel_init_pm(struct drm_device *dev);
731 extern bool intel_fbc_enabled(struct drm_device *dev);
732 extern void intel_update_fbc(struct drm_device *dev);
734 extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
735 extern void intel_gpu_ips_teardown(void);
738 extern int i915_init_power_well(struct drm_device *dev);
739 extern void i915_remove_power_well(struct drm_device *dev);
741 extern bool intel_display_power_enabled(struct drm_device *dev,
742 enum intel_display_power_domain domain);
743 extern void intel_init_power_well(struct drm_device *dev);
744 extern void intel_set_power_well(struct drm_device *dev, bool enable);
745 extern void intel_enable_gt_powersave(struct drm_device *dev);
746 extern void intel_disable_gt_powersave(struct drm_device *dev);
747 extern void ironlake_teardown_rc6(struct drm_device *dev);
748 void gen6_update_ring_freq(struct drm_device *dev);
750 extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
752 extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
753 extern void intel_ddi_pll_init(struct drm_device *dev);
754 extern void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
755 extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
756 enum transcoder cpu_transcoder);
757 extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
758 extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
759 extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
760 extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc);
761 extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
762 extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
763 extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
765 intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
766 extern void intel_ddi_fdi_disable(struct drm_crtc *crtc);
768 extern void intel_display_handle_reset(struct drm_device *dev);
769 extern bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
772 extern bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
773 enum transcoder pch_transcoder,
776 extern void intel_edp_psr_enable(struct intel_dp *intel_dp);
777 extern void intel_edp_psr_disable(struct intel_dp *intel_dp);
778 extern void intel_edp_psr_update(struct drm_device *dev);
779 extern void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
780 bool switch_to_fclk, bool allow_power_down);
781 extern void hsw_restore_lcpll(struct drm_i915_private *dev_priv);
782 extern void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
783 extern void ilk_disable_gt_irq(struct drm_i915_private *dev_priv,
785 extern void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
786 extern void snb_disable_pm_irq(struct drm_i915_private *dev_priv,
788 extern void hsw_enable_pc8_work(struct work_struct *__work);
789 extern void hsw_enable_package_c8(struct drm_i915_private *dev_priv);
790 extern void hsw_disable_package_c8(struct drm_i915_private *dev_priv);
791 extern void hsw_pc8_disable_interrupts(struct drm_device *dev);
792 extern void hsw_pc8_restore_interrupts(struct drm_device *dev);
793 extern void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
794 extern void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
795 extern void i915_disable_vga_mem(struct drm_device *dev);
797 #endif /* __INTEL_DRV_H__ */