2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/i2c.h>
29 #include <linux/hdmi.h>
30 #include <drm/i915_drm.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_fb_helper.h>
35 #include <drm/drm_dp_helper.h>
38 * _wait_for - magic (register) wait macro
40 * Does the right thing for modeset paths when run under kdgb or similar atomic
41 * contexts. Note that it's important that we check the condition again after
42 * having timed out, since the timeout could be due to preemption or similar and
43 * we've never had a chance to check the condition before the timeout.
45 #define _wait_for(COND, MS, W) ({ \
46 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
49 if (time_after(jiffies, timeout__)) { \
54 if (W && drm_can_sleep()) { \
63 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
64 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
65 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
66 DIV_ROUND_UP((US), 1000), 0)
68 #define KHz(x) (1000*x)
69 #define MHz(x) KHz(1000*x)
72 * Display related stuff
75 /* store information about an Ixxx DVO */
76 /* The i830->i865 use multiple DVOs with multiple i2cs */
77 /* the i915, i945 have a single sDVO i2c bus - which is different */
79 /* maximum connectors per crtcs in the mode set */
80 #define INTELFB_CONN_LIMIT 4
82 #define INTEL_I2C_BUS_DVO 1
83 #define INTEL_I2C_BUS_SDVO 2
85 /* these are outputs from the chip - integrated only
86 external chips are via DVO or SDVO output */
87 #define INTEL_OUTPUT_UNUSED 0
88 #define INTEL_OUTPUT_ANALOG 1
89 #define INTEL_OUTPUT_DVO 2
90 #define INTEL_OUTPUT_SDVO 3
91 #define INTEL_OUTPUT_LVDS 4
92 #define INTEL_OUTPUT_TVOUT 5
93 #define INTEL_OUTPUT_HDMI 6
94 #define INTEL_OUTPUT_DISPLAYPORT 7
95 #define INTEL_OUTPUT_EDP 8
96 #define INTEL_OUTPUT_DSI 9
97 #define INTEL_OUTPUT_UNKNOWN 10
99 #define INTEL_DVO_CHIP_NONE 0
100 #define INTEL_DVO_CHIP_LVDS 1
101 #define INTEL_DVO_CHIP_TMDS 2
102 #define INTEL_DVO_CHIP_TVOUT 4
104 #define INTEL_DSI_COMMAND_MODE 0
105 #define INTEL_DSI_VIDEO_MODE 1
107 struct intel_framebuffer {
108 struct drm_framebuffer base;
109 struct drm_i915_gem_object *obj;
113 struct drm_fb_helper helper;
114 struct intel_framebuffer ifb;
115 struct list_head fbdev_list;
116 struct drm_display_mode *our_mode;
119 struct intel_encoder {
120 struct drm_encoder base;
122 * The new crtc this encoder will be driven from. Only differs from
123 * base->crtc while a modeset is in progress.
125 struct intel_crtc *new_crtc;
129 * Intel hw has only one MUX where encoders could be clone, hence a
130 * simple flag is enough to compute the possible_clones mask.
133 bool connectors_active;
134 void (*hot_plug)(struct intel_encoder *);
135 bool (*compute_config)(struct intel_encoder *,
136 struct intel_crtc_config *);
137 void (*pre_pll_enable)(struct intel_encoder *);
138 void (*pre_enable)(struct intel_encoder *);
139 void (*enable)(struct intel_encoder *);
140 void (*mode_set)(struct intel_encoder *intel_encoder);
141 void (*disable)(struct intel_encoder *);
142 void (*post_disable)(struct intel_encoder *);
143 /* Read out the current hw state of this connector, returning true if
144 * the encoder is active. If the encoder is enabled it also set the pipe
145 * it is connected to in the pipe parameter. */
146 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
147 /* Reconstructs the equivalent mode flags for the current hardware
148 * state. This must be called _after_ display->get_pipe_config has
149 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
150 * be set correctly before calling this function. */
151 void (*get_config)(struct intel_encoder *,
152 struct intel_crtc_config *pipe_config);
154 enum hpd_pin hpd_pin;
158 struct drm_display_mode *fixed_mode;
162 struct intel_connector {
163 struct drm_connector base;
165 * The fixed encoder this connector is connected to.
167 struct intel_encoder *encoder;
170 * The new encoder this connector will be driven. Only differs from
171 * encoder while a modeset is in progress.
173 struct intel_encoder *new_encoder;
175 /* Reads out the current hw, returning true if the connector is enabled
176 * and active (i.e. dpms ON state). */
177 bool (*get_hw_state)(struct intel_connector *);
179 /* Panel info for eDP and LVDS */
180 struct intel_panel panel;
182 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
185 /* since POLL and HPD connectors may use the same HPD line keep the native
186 state of connector->polled in case hotplug storm detection changes it */
190 typedef struct dpll {
202 struct intel_crtc_config {
204 * quirks - bitfield with hw state readout quirks
206 * For various reasons the hw state readout code might not be able to
207 * completely faithfully read out the current state. These cases are
208 * tracked with quirk flags so that fastboot and state checker can act
211 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
212 unsigned long quirks;
214 /* User requested mode, only valid as a starting point to
215 * compute adjusted_mode, except in the case of (S)DVO where
216 * it's also for the output timings of the (S)DVO chip.
217 * adjusted_mode will then correspond to the S(DVO) chip's
218 * preferred input timings. */
219 struct drm_display_mode requested_mode;
220 /* Actual pipe timings ie. what we program into the pipe timing
221 * registers. adjusted_mode.clock is the pipe pixel clock. */
222 struct drm_display_mode adjusted_mode;
224 /* Pipe source size (ie. panel fitter input size)
225 * All planes will be positioned inside this space,
226 * and get clipped at the edges. */
227 int pipe_src_w, pipe_src_h;
229 /* Whether to set up the PCH/FDI. Note that we never allow sharing
230 * between pch encoders and cpu encoders. */
231 bool has_pch_encoder;
233 /* CPU Transcoder for the pipe. Currently this can only differ from the
234 * pipe on Haswell (where we have a special eDP transcoder). */
235 enum transcoder cpu_transcoder;
238 * Use reduced/limited/broadcast rbg range, compressing from the full
239 * range fed into the crtcs.
241 bool limited_color_range;
243 /* DP has a bunch of special case unfortunately, so mark the pipe
248 * Enable dithering, used when the selected pipe bpp doesn't match the
253 /* Controls for the clock computation, to override various stages. */
256 /* SDVO TV has a bunch of special case. To make multifunction encoders
257 * work correctly, we need to track this at runtime.*/
261 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
262 * required. This is set in the 2nd loop of calling encoder's
263 * ->compute_config if the first pick doesn't work out.
267 /* Settings for the intel dpll used on pretty much everything but
271 /* Selected dpll when shared or DPLL_ID_PRIVATE. */
272 enum intel_dpll_id shared_dpll;
274 /* Actual register state of the dpll, for shared dpll cross-checking. */
275 struct intel_dpll_hw_state dpll_hw_state;
278 struct intel_link_m_n dp_m_n;
281 * Frequence the dpll for the port should run at. Differs from the
282 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
283 * already multiplied by pixel_multiplier.
287 /* Used by SDVO (and if we ever fix it, HDMI). */
288 unsigned pixel_multiplier;
290 /* Panel fitter controls for gen2-gen4 + VLV */
294 u32 lvds_border_bits;
297 /* Panel fitter placement and size for Ironlake+ */
304 /* FDI configuration, only valid if has_pch_encoder is set. */
306 struct intel_link_m_n fdi_m_n;
314 struct drm_crtc base;
317 u8 lut_r[256], lut_g[256], lut_b[256];
319 * Whether the crtc and the connected output pipeline is active. Implies
320 * that crtc->enabled is set, i.e. the current mode configuration has
321 * some outputs connected to this crtc.
325 bool primary_disabled; /* is the crtc obscured by a plane? */
327 struct intel_overlay *overlay;
328 struct intel_unpin_work *unpin_work;
330 atomic_t unpin_work_count;
332 /* Display surface base address adjustement for pageflips. Note that on
333 * gen4+ this only adjusts up to a tile, offsets within a tile are
334 * handled in the hw itself (with the TILEOFF register). */
335 unsigned long dspaddr_offset;
337 struct drm_i915_gem_object *cursor_bo;
338 uint32_t cursor_addr;
339 int16_t cursor_x, cursor_y;
340 int16_t cursor_width, cursor_height;
343 struct intel_crtc_config config;
345 uint32_t ddi_pll_sel;
347 /* reset counter value when the last flip was submitted */
348 unsigned int reset_counter;
350 /* Access to these should be protected by dev_priv->irq_lock. */
351 bool cpu_fifo_underrun_disabled;
352 bool pch_fifo_underrun_disabled;
355 struct intel_plane_wm_parameters {
356 uint32_t horiz_pixels;
357 uint8_t bytes_per_pixel;
363 struct drm_plane base;
366 struct drm_i915_gem_object *obj;
369 u32 lut_r[1024], lut_g[1024], lut_b[1024];
371 unsigned int crtc_w, crtc_h;
372 uint32_t src_x, src_y;
373 uint32_t src_w, src_h;
375 /* Since we need to change the watermarks before/after
376 * enabling/disabling the planes, we need to store the parameters here
377 * as the other pieces of the struct may not reflect the values we want
378 * for the watermark calculations. Currently only Haswell uses this.
380 struct intel_plane_wm_parameters wm;
382 void (*update_plane)(struct drm_plane *plane,
383 struct drm_crtc *crtc,
384 struct drm_framebuffer *fb,
385 struct drm_i915_gem_object *obj,
386 int crtc_x, int crtc_y,
387 unsigned int crtc_w, unsigned int crtc_h,
388 uint32_t x, uint32_t y,
389 uint32_t src_w, uint32_t src_h);
390 void (*disable_plane)(struct drm_plane *plane,
391 struct drm_crtc *crtc);
392 int (*update_colorkey)(struct drm_plane *plane,
393 struct drm_intel_sprite_colorkey *key);
394 void (*get_colorkey)(struct drm_plane *plane,
395 struct drm_intel_sprite_colorkey *key);
398 struct intel_watermark_params {
399 unsigned long fifo_size;
400 unsigned long max_wm;
401 unsigned long default_wm;
402 unsigned long guard_size;
403 unsigned long cacheline_size;
406 struct cxsr_latency {
409 unsigned long fsb_freq;
410 unsigned long mem_freq;
411 unsigned long display_sr;
412 unsigned long display_hpll_disable;
413 unsigned long cursor_sr;
414 unsigned long cursor_hpll_disable;
417 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
418 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
419 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
420 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
421 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
426 uint32_t color_range;
427 bool color_range_auto;
430 enum hdmi_force_audio force_audio;
431 bool rgb_quant_range_selectable;
432 void (*write_infoframe)(struct drm_encoder *encoder,
433 enum hdmi_infoframe_type type,
434 const uint8_t *frame, ssize_t len);
435 void (*set_infoframes)(struct drm_encoder *encoder,
436 struct drm_display_mode *adjusted_mode);
439 #define DP_MAX_DOWNSTREAM_PORTS 0x10
440 #define DP_LINK_CONFIGURATION_SIZE 9
444 uint32_t aux_ch_ctl_reg;
446 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
448 enum hdmi_force_audio force_audio;
449 uint32_t color_range;
450 bool color_range_auto;
453 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
454 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
455 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
456 struct i2c_adapter adapter;
457 struct i2c_algo_dp_aux_data algo;
458 uint8_t train_set[4];
459 int panel_power_up_delay;
460 int panel_power_down_delay;
461 int panel_power_cycle_delay;
462 int backlight_on_delay;
463 int backlight_off_delay;
464 struct delayed_work panel_vdd_work;
467 struct intel_connector *attached_connector;
470 struct intel_digital_port {
471 struct intel_encoder base;
475 struct intel_hdmi hdmi;
479 vlv_dport_to_channel(struct intel_digital_port *dport)
481 switch (dport->port) {
491 static inline struct drm_crtc *
492 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
494 struct drm_i915_private *dev_priv = dev->dev_private;
495 return dev_priv->pipe_to_crtc_mapping[pipe];
498 static inline struct drm_crtc *
499 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
501 struct drm_i915_private *dev_priv = dev->dev_private;
502 return dev_priv->plane_to_crtc_mapping[plane];
505 struct intel_unpin_work {
506 struct work_struct work;
507 struct drm_crtc *crtc;
508 struct drm_i915_gem_object *old_fb_obj;
509 struct drm_i915_gem_object *pending_flip_obj;
510 struct drm_pending_vblank_event *event;
512 #define INTEL_FLIP_INACTIVE 0
513 #define INTEL_FLIP_PENDING 1
514 #define INTEL_FLIP_COMPLETE 2
515 bool enable_stall_check;
518 int intel_pch_rawclk(struct drm_device *dev);
520 int intel_connector_update_modes(struct drm_connector *connector,
522 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
524 extern void intel_attach_force_audio_property(struct drm_connector *connector);
525 extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
527 extern bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
528 extern void intel_crt_init(struct drm_device *dev);
529 extern void intel_hdmi_init(struct drm_device *dev,
530 int hdmi_reg, enum port port);
531 extern void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
532 struct intel_connector *intel_connector);
533 extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
534 extern bool intel_hdmi_compute_config(struct intel_encoder *encoder,
535 struct intel_crtc_config *pipe_config);
536 extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg,
538 extern void intel_dvo_init(struct drm_device *dev);
539 extern void intel_tv_init(struct drm_device *dev);
540 extern void intel_mark_busy(struct drm_device *dev);
541 extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
542 struct intel_ring_buffer *ring);
543 extern void intel_mark_idle(struct drm_device *dev);
544 extern void intel_lvds_init(struct drm_device *dev);
545 extern bool intel_dsi_init(struct drm_device *dev);
546 extern bool intel_is_dual_link_lvds(struct drm_device *dev);
547 extern void intel_dp_init(struct drm_device *dev, int output_reg,
549 extern bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
550 struct intel_connector *intel_connector);
551 extern void intel_dp_init_link_config(struct intel_dp *intel_dp);
552 extern void intel_dp_start_link_train(struct intel_dp *intel_dp);
553 extern void intel_dp_complete_link_train(struct intel_dp *intel_dp);
554 extern void intel_dp_stop_link_train(struct intel_dp *intel_dp);
555 extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
556 extern void intel_dp_encoder_destroy(struct drm_encoder *encoder);
557 extern void intel_dp_check_link_status(struct intel_dp *intel_dp);
558 extern bool intel_dp_compute_config(struct intel_encoder *encoder,
559 struct intel_crtc_config *pipe_config);
560 extern bool intel_dpd_is_edp(struct drm_device *dev);
561 extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp);
562 extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp);
563 extern void ironlake_edp_panel_on(struct intel_dp *intel_dp);
564 extern void ironlake_edp_panel_off(struct intel_dp *intel_dp);
565 extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
566 extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
567 extern int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
568 extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
572 extern int intel_panel_init(struct intel_panel *panel,
573 struct drm_display_mode *fixed_mode);
574 extern void intel_panel_fini(struct intel_panel *panel);
576 extern void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
577 struct drm_display_mode *adjusted_mode);
578 extern void intel_pch_panel_fitting(struct intel_crtc *crtc,
579 struct intel_crtc_config *pipe_config,
581 extern void intel_gmch_panel_fitting(struct intel_crtc *crtc,
582 struct intel_crtc_config *pipe_config,
584 extern void intel_panel_set_backlight(struct drm_device *dev,
586 extern int intel_panel_setup_backlight(struct drm_connector *connector);
587 extern void intel_panel_enable_backlight(struct drm_device *dev,
589 extern void intel_panel_disable_backlight(struct drm_device *dev);
590 extern void intel_panel_destroy_backlight(struct drm_device *dev);
591 extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
593 struct intel_set_config {
594 struct drm_encoder **save_connector_encoders;
595 struct drm_crtc **save_encoder_crtcs;
601 extern void intel_crtc_restore_mode(struct drm_crtc *crtc);
602 extern void intel_crtc_load_lut(struct drm_crtc *crtc);
603 extern void intel_crtc_update_dpms(struct drm_crtc *crtc);
604 extern void intel_encoder_destroy(struct drm_encoder *encoder);
605 extern void intel_connector_dpms(struct drm_connector *, int mode);
606 extern bool intel_connector_get_hw_state(struct intel_connector *connector);
607 extern void intel_modeset_check_state(struct drm_device *dev);
608 extern void intel_plane_restore(struct drm_plane *plane);
609 extern void intel_plane_disable(struct drm_plane *plane);
612 static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector)
614 return to_intel_connector(connector)->encoder;
617 static inline struct intel_digital_port *
618 enc_to_dig_port(struct drm_encoder *encoder)
620 return container_of(encoder, struct intel_digital_port, base.base);
623 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
625 return &enc_to_dig_port(encoder)->dp;
628 static inline struct intel_digital_port *
629 dp_to_dig_port(struct intel_dp *intel_dp)
631 return container_of(intel_dp, struct intel_digital_port, dp);
634 static inline struct intel_digital_port *
635 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
637 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
640 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
641 struct intel_digital_port *port);
643 extern void intel_connector_attach_encoder(struct intel_connector *connector,
644 struct intel_encoder *encoder);
645 extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
647 extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
648 struct drm_crtc *crtc);
649 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
650 struct drm_file *file_priv);
651 extern enum transcoder
652 intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
654 extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
655 extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
656 extern int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
657 extern void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port);
659 struct intel_load_detect_pipe {
660 struct drm_framebuffer *release_fb;
661 bool load_detect_temp;
664 extern bool intel_get_load_detect_pipe(struct drm_connector *connector,
665 struct drm_display_mode *mode,
666 struct intel_load_detect_pipe *old);
667 extern void intel_release_load_detect_pipe(struct drm_connector *connector,
668 struct intel_load_detect_pipe *old);
670 extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
671 u16 blue, int regno);
672 extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
673 u16 *blue, int regno);
675 extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
676 struct drm_i915_gem_object *obj,
677 struct intel_ring_buffer *pipelined);
678 extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
680 extern int intel_framebuffer_init(struct drm_device *dev,
681 struct intel_framebuffer *ifb,
682 struct drm_mode_fb_cmd2 *mode_cmd,
683 struct drm_i915_gem_object *obj);
684 extern void intel_framebuffer_fini(struct intel_framebuffer *fb);
685 extern int intel_fbdev_init(struct drm_device *dev);
686 extern void intel_fbdev_initial_config(struct drm_device *dev);
687 extern void intel_fbdev_fini(struct drm_device *dev);
688 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
689 extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
690 extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
691 extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
693 extern void intel_setup_overlay(struct drm_device *dev);
694 extern void intel_cleanup_overlay(struct drm_device *dev);
695 extern int intel_overlay_switch_off(struct intel_overlay *overlay);
696 extern int intel_overlay_put_image(struct drm_device *dev, void *data,
697 struct drm_file *file_priv);
698 extern int intel_overlay_attrs(struct drm_device *dev, void *data,
699 struct drm_file *file_priv);
701 extern void intel_fb_output_poll_changed(struct drm_device *dev);
702 extern void intel_fb_restore_mode(struct drm_device *dev);
704 struct intel_shared_dpll *
705 intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
707 void assert_shared_dpll(struct drm_i915_private *dev_priv,
708 struct intel_shared_dpll *pll,
710 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
711 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
712 void assert_pll(struct drm_i915_private *dev_priv,
713 enum pipe pipe, bool state);
714 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
715 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
716 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
717 enum pipe pipe, bool state);
718 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
719 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
720 extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
722 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
723 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
725 extern void intel_init_clock_gating(struct drm_device *dev);
726 extern void intel_suspend_hw(struct drm_device *dev);
727 extern void intel_write_eld(struct drm_encoder *encoder,
728 struct drm_display_mode *mode);
729 extern void intel_prepare_ddi(struct drm_device *dev);
730 extern void hsw_fdi_link_train(struct drm_crtc *crtc);
731 extern void intel_ddi_init(struct drm_device *dev, enum port port);
732 extern enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
734 /* For use by IVB LP watermark workaround in intel_sprite.c */
735 extern void intel_update_watermarks(struct drm_crtc *crtc);
736 extern void intel_update_sprite_watermarks(struct drm_plane *plane,
737 struct drm_crtc *crtc,
738 uint32_t sprite_width, int pixel_size,
739 bool enabled, bool scaled);
741 extern unsigned long intel_gen4_compute_page_offset(int *x, int *y,
742 unsigned int tiling_mode,
746 extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
747 struct drm_file *file_priv);
748 extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
749 struct drm_file *file_priv);
751 /* Power-related functions, located in intel_pm.c */
752 extern void intel_init_pm(struct drm_device *dev);
754 extern bool intel_fbc_enabled(struct drm_device *dev);
755 extern void intel_update_fbc(struct drm_device *dev);
757 extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
758 extern void intel_gpu_ips_teardown(void);
761 extern int i915_init_power_well(struct drm_device *dev);
762 extern void i915_remove_power_well(struct drm_device *dev);
764 extern bool intel_display_power_enabled(struct drm_device *dev,
765 enum intel_display_power_domain domain);
766 extern void intel_display_power_get(struct drm_device *dev,
767 enum intel_display_power_domain domain);
768 extern void intel_display_power_put(struct drm_device *dev,
769 enum intel_display_power_domain domain);
770 extern void intel_init_power_well(struct drm_device *dev);
771 extern void intel_set_power_well(struct drm_device *dev, bool enable);
772 extern void intel_resume_power_well(struct drm_device *dev);
773 extern void intel_enable_gt_powersave(struct drm_device *dev);
774 extern void intel_disable_gt_powersave(struct drm_device *dev);
775 extern void ironlake_teardown_rc6(struct drm_device *dev);
776 void gen6_update_ring_freq(struct drm_device *dev);
778 extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
780 extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
781 extern void intel_ddi_pll_init(struct drm_device *dev);
782 extern void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
783 extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
784 enum transcoder cpu_transcoder);
785 extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
786 extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
787 extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
788 extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc);
789 extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
790 extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
791 extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
793 intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
794 extern void intel_ddi_fdi_disable(struct drm_crtc *crtc);
796 extern void intel_display_handle_reset(struct drm_device *dev);
797 extern bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
800 extern bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
801 enum transcoder pch_transcoder,
804 extern void intel_edp_psr_enable(struct intel_dp *intel_dp);
805 extern void intel_edp_psr_disable(struct intel_dp *intel_dp);
806 extern void intel_edp_psr_update(struct drm_device *dev);
807 extern void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
808 bool switch_to_fclk, bool allow_power_down);
809 extern void hsw_restore_lcpll(struct drm_i915_private *dev_priv);
810 extern void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
811 extern void ilk_disable_gt_irq(struct drm_i915_private *dev_priv,
813 extern void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
814 extern void snb_disable_pm_irq(struct drm_i915_private *dev_priv,
816 extern void hsw_enable_pc8_work(struct work_struct *__work);
817 extern void hsw_enable_package_c8(struct drm_i915_private *dev_priv);
818 extern void hsw_disable_package_c8(struct drm_i915_private *dev_priv);
819 extern void hsw_pc8_disable_interrupts(struct drm_device *dev);
820 extern void hsw_pc8_restore_interrupts(struct drm_device *dev);
821 extern void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
822 extern void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
823 extern void intel_dp_get_m_n(struct intel_crtc *crtc,
824 struct intel_crtc_config *pipe_config);
825 extern int intel_dotclock_calculate(int link_freq,
826 const struct intel_link_m_n *m_n);
827 extern void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
830 extern bool intel_crtc_active(struct drm_crtc *crtc);
831 extern void i915_disable_vga_mem(struct drm_device *dev);
833 #endif /* __INTEL_DRV_H__ */