2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/i2c.h>
29 #include <drm/i915_drm.h>
31 #include <drm/drm_crtc.h>
32 #include <drm/drm_crtc_helper.h>
33 #include <drm/drm_fb_helper.h>
34 #include <drm/drm_dp_helper.h>
36 #define _wait_for(COND, MS, W) ({ \
37 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
40 if (time_after(jiffies, timeout__)) { \
44 if (W && drm_can_sleep()) { \
53 #define wait_for_atomic_us(COND, US) ({ \
54 unsigned long timeout__ = jiffies + usecs_to_jiffies(US); \
57 if (time_after(jiffies, timeout__)) { \
66 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
67 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
69 #define KHz(x) (1000*x)
70 #define MHz(x) KHz(1000*x)
73 * Display related stuff
76 /* store information about an Ixxx DVO */
77 /* The i830->i865 use multiple DVOs with multiple i2cs */
78 /* the i915, i945 have a single sDVO i2c bus - which is different */
80 /* maximum connectors per crtcs in the mode set */
81 #define INTELFB_CONN_LIMIT 4
83 #define INTEL_I2C_BUS_DVO 1
84 #define INTEL_I2C_BUS_SDVO 2
86 /* these are outputs from the chip - integrated only
87 external chips are via DVO or SDVO output */
88 #define INTEL_OUTPUT_UNUSED 0
89 #define INTEL_OUTPUT_ANALOG 1
90 #define INTEL_OUTPUT_DVO 2
91 #define INTEL_OUTPUT_SDVO 3
92 #define INTEL_OUTPUT_LVDS 4
93 #define INTEL_OUTPUT_TVOUT 5
94 #define INTEL_OUTPUT_HDMI 6
95 #define INTEL_OUTPUT_DISPLAYPORT 7
96 #define INTEL_OUTPUT_EDP 8
98 #define INTEL_DVO_CHIP_NONE 0
99 #define INTEL_DVO_CHIP_LVDS 1
100 #define INTEL_DVO_CHIP_TMDS 2
101 #define INTEL_DVO_CHIP_TVOUT 4
103 /* drm_display_mode->private_flags */
104 #define INTEL_MODE_PIXEL_MULTIPLIER_SHIFT (0x0)
105 #define INTEL_MODE_PIXEL_MULTIPLIER_MASK (0xf << INTEL_MODE_PIXEL_MULTIPLIER_SHIFT)
106 #define INTEL_MODE_DP_FORCE_6BPC (0x10)
107 /* This flag must be set by the encoder's mode_fixup if it changes the crtc
108 * timings in the mode to prevent the crtc fixup from overwriting them.
109 * Currently only lvds needs that. */
110 #define INTEL_MODE_CRTC_TIMINGS_SET (0x20)
113 intel_mode_set_pixel_multiplier(struct drm_display_mode *mode,
116 mode->clock *= multiplier;
117 mode->private_flags |= multiplier;
121 intel_mode_get_pixel_multiplier(const struct drm_display_mode *mode)
123 return (mode->private_flags & INTEL_MODE_PIXEL_MULTIPLIER_MASK) >> INTEL_MODE_PIXEL_MULTIPLIER_SHIFT;
126 struct intel_framebuffer {
127 struct drm_framebuffer base;
128 struct drm_i915_gem_object *obj;
132 struct drm_fb_helper helper;
133 struct intel_framebuffer ifb;
134 struct list_head fbdev_list;
135 struct drm_display_mode *our_mode;
138 struct intel_encoder {
139 struct drm_encoder base;
141 * The new crtc this encoder will be driven from. Only differs from
142 * base->crtc while a modeset is in progress.
144 struct intel_crtc *new_crtc;
149 * Intel hw has only one MUX where encoders could be clone, hence a
150 * simple flag is enough to compute the possible_clones mask.
153 bool connectors_active;
154 void (*hot_plug)(struct intel_encoder *);
155 void (*pre_enable)(struct intel_encoder *);
156 void (*enable)(struct intel_encoder *);
157 void (*disable)(struct intel_encoder *);
158 void (*post_disable)(struct intel_encoder *);
159 /* Read out the current hw state of this connector, returning true if
160 * the encoder is active. If the encoder is enabled it also set the pipe
161 * it is connected to in the pipe parameter. */
162 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
167 struct drm_display_mode *fixed_mode;
171 struct intel_connector {
172 struct drm_connector base;
174 * The fixed encoder this connector is connected to.
176 struct intel_encoder *encoder;
179 * The new encoder this connector will be driven. Only differs from
180 * encoder while a modeset is in progress.
182 struct intel_encoder *new_encoder;
184 /* Reads out the current hw, returning true if the connector is enabled
185 * and active (i.e. dpms ON state). */
186 bool (*get_hw_state)(struct intel_connector *);
188 /* Panel info for eDP and LVDS */
189 struct intel_panel panel;
191 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
196 struct drm_crtc base;
199 enum transcoder cpu_transcoder;
200 u8 lut_r[256], lut_g[256], lut_b[256];
202 * Whether the crtc and the connected output pipeline is active. Implies
203 * that crtc->enabled is set, i.e. the current mode configuration has
204 * some outputs connected to this crtc.
207 bool primary_disabled; /* is the crtc obscured by a plane? */
209 struct intel_overlay *overlay;
210 struct intel_unpin_work *unpin_work;
213 /* Display surface base address adjustement for pageflips. Note that on
214 * gen4+ this only adjusts up to a tile, offsets within a tile are
215 * handled in the hw itself (with the TILEOFF register). */
216 unsigned long dspaddr_offset;
218 struct drm_i915_gem_object *cursor_bo;
219 uint32_t cursor_addr;
220 int16_t cursor_x, cursor_y;
221 int16_t cursor_width, cursor_height;
225 /* We can share PLLs across outputs if the timings match */
226 struct intel_pch_pll *pch_pll;
227 uint32_t ddi_pll_sel;
231 struct drm_plane base;
233 struct drm_i915_gem_object *obj;
236 u32 lut_r[1024], lut_g[1024], lut_b[1024];
237 void (*update_plane)(struct drm_plane *plane,
238 struct drm_framebuffer *fb,
239 struct drm_i915_gem_object *obj,
240 int crtc_x, int crtc_y,
241 unsigned int crtc_w, unsigned int crtc_h,
242 uint32_t x, uint32_t y,
243 uint32_t src_w, uint32_t src_h);
244 void (*disable_plane)(struct drm_plane *plane);
245 int (*update_colorkey)(struct drm_plane *plane,
246 struct drm_intel_sprite_colorkey *key);
247 void (*get_colorkey)(struct drm_plane *plane,
248 struct drm_intel_sprite_colorkey *key);
251 struct intel_watermark_params {
252 unsigned long fifo_size;
253 unsigned long max_wm;
254 unsigned long default_wm;
255 unsigned long guard_size;
256 unsigned long cacheline_size;
259 struct cxsr_latency {
262 unsigned long fsb_freq;
263 unsigned long mem_freq;
264 unsigned long display_sr;
265 unsigned long display_hpll_disable;
266 unsigned long cursor_sr;
267 unsigned long cursor_hpll_disable;
270 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
271 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
272 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
273 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
274 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
276 #define DIP_HEADER_SIZE 5
278 #define DIP_TYPE_AVI 0x82
279 #define DIP_VERSION_AVI 0x2
280 #define DIP_LEN_AVI 13
281 #define DIP_AVI_PR_1 0
282 #define DIP_AVI_PR_2 1
284 #define DIP_TYPE_SPD 0x83
285 #define DIP_VERSION_SPD 0x1
286 #define DIP_LEN_SPD 25
287 #define DIP_SPD_UNKNOWN 0
288 #define DIP_SPD_DSTB 0x1
289 #define DIP_SPD_DVDP 0x2
290 #define DIP_SPD_DVHS 0x3
291 #define DIP_SPD_HDDVR 0x4
292 #define DIP_SPD_DVC 0x5
293 #define DIP_SPD_DSC 0x6
294 #define DIP_SPD_VCD 0x7
295 #define DIP_SPD_GAME 0x8
296 #define DIP_SPD_PC 0x9
297 #define DIP_SPD_BD 0xa
298 #define DIP_SPD_SCD 0xb
300 struct dip_infoframe {
301 uint8_t type; /* HB0 */
302 uint8_t ver; /* HB1 */
303 uint8_t len; /* HB2 - body len, not including checksum */
304 uint8_t ecc; /* Header ECC */
305 uint8_t checksum; /* PB0 */
308 /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */
310 /* PB2 - C 7:6, M 5:4, R 3:0 */
312 /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */
316 /* PB5 - YQ 7:6, CN 5:4, PR 3:0 */
319 uint16_t top_bar_end;
320 uint16_t bottom_bar_start;
321 uint16_t left_bar_end;
322 uint16_t right_bar_start;
323 } __attribute__ ((packed)) avi;
328 } __attribute__ ((packed)) spd;
330 } __attribute__ ((packed)) body;
331 } __attribute__((packed));
336 uint32_t color_range;
339 enum hdmi_force_audio force_audio;
340 void (*write_infoframe)(struct drm_encoder *encoder,
341 struct dip_infoframe *frame);
342 void (*set_infoframes)(struct drm_encoder *encoder,
343 struct drm_display_mode *adjusted_mode);
346 #define DP_MAX_DOWNSTREAM_PORTS 0x10
347 #define DP_LINK_CONFIGURATION_SIZE 9
352 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
354 enum hdmi_force_audio force_audio;
355 uint32_t color_range;
358 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
359 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
360 struct i2c_adapter adapter;
361 struct i2c_algo_dp_aux_data algo;
363 uint8_t train_set[4];
364 int panel_power_up_delay;
365 int panel_power_down_delay;
366 int panel_power_cycle_delay;
367 int backlight_on_delay;
368 int backlight_off_delay;
369 struct delayed_work panel_vdd_work;
371 struct intel_connector *attached_connector;
374 struct intel_digital_port {
375 struct intel_encoder base;
378 struct intel_hdmi hdmi;
381 static inline struct drm_crtc *
382 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
384 struct drm_i915_private *dev_priv = dev->dev_private;
385 return dev_priv->pipe_to_crtc_mapping[pipe];
388 static inline struct drm_crtc *
389 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
391 struct drm_i915_private *dev_priv = dev->dev_private;
392 return dev_priv->plane_to_crtc_mapping[plane];
395 struct intel_unpin_work {
396 struct work_struct work;
397 struct drm_device *dev;
398 struct drm_i915_gem_object *old_fb_obj;
399 struct drm_i915_gem_object *pending_flip_obj;
400 struct drm_pending_vblank_event *event;
402 bool enable_stall_check;
405 struct intel_fbc_work {
406 struct delayed_work work;
407 struct drm_crtc *crtc;
408 struct drm_framebuffer *fb;
412 int intel_pch_rawclk(struct drm_device *dev);
414 int intel_connector_update_modes(struct drm_connector *connector,
416 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
418 extern void intel_attach_force_audio_property(struct drm_connector *connector);
419 extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
421 extern void intel_crt_init(struct drm_device *dev);
422 extern void intel_hdmi_init(struct drm_device *dev,
423 int sdvox_reg, enum port port);
424 extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
425 extern void intel_dip_infoframe_csum(struct dip_infoframe *avi_if);
426 extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg,
428 extern void intel_dvo_init(struct drm_device *dev);
429 extern void intel_tv_init(struct drm_device *dev);
430 extern void intel_mark_busy(struct drm_device *dev);
431 extern void intel_mark_idle(struct drm_device *dev);
432 extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj);
433 extern void intel_mark_fb_idle(struct drm_i915_gem_object *obj);
434 extern bool intel_lvds_init(struct drm_device *dev);
435 extern void intel_dp_init(struct drm_device *dev, int output_reg,
438 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
439 struct drm_display_mode *adjusted_mode);
440 extern void intel_dp_init_link_config(struct intel_dp *intel_dp);
441 extern void intel_dp_start_link_train(struct intel_dp *intel_dp);
442 extern void intel_dp_complete_link_train(struct intel_dp *intel_dp);
443 extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
444 extern bool intel_dpd_is_edp(struct drm_device *dev);
445 extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp);
446 extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp);
447 extern void ironlake_edp_panel_on(struct intel_dp *intel_dp);
448 extern void ironlake_edp_panel_off(struct intel_dp *intel_dp);
449 extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
450 extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
451 extern void intel_edp_link_config(struct intel_encoder *, int *, int *);
452 extern int intel_edp_target_clock(struct intel_encoder *,
453 struct drm_display_mode *mode);
454 extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder);
455 extern int intel_plane_init(struct drm_device *dev, enum pipe pipe);
456 extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
460 extern int intel_panel_init(struct intel_panel *panel,
461 struct drm_display_mode *fixed_mode);
462 extern void intel_panel_fini(struct intel_panel *panel);
464 extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
465 struct drm_display_mode *adjusted_mode);
466 extern void intel_pch_panel_fitting(struct drm_device *dev,
468 const struct drm_display_mode *mode,
469 struct drm_display_mode *adjusted_mode);
470 extern u32 intel_panel_get_max_backlight(struct drm_device *dev);
471 extern void intel_panel_set_backlight(struct drm_device *dev, u32 level);
472 extern int intel_panel_setup_backlight(struct drm_connector *connector);
473 extern void intel_panel_enable_backlight(struct drm_device *dev,
475 extern void intel_panel_disable_backlight(struct drm_device *dev);
476 extern void intel_panel_destroy_backlight(struct drm_device *dev);
477 extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
479 struct intel_set_config {
480 struct drm_encoder **save_connector_encoders;
481 struct drm_crtc **save_encoder_crtcs;
487 extern bool intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
488 int x, int y, struct drm_framebuffer *old_fb);
489 extern void intel_modeset_disable(struct drm_device *dev);
490 extern void intel_crtc_load_lut(struct drm_crtc *crtc);
491 extern void intel_crtc_update_dpms(struct drm_crtc *crtc);
492 extern void intel_encoder_noop(struct drm_encoder *encoder);
493 extern void intel_encoder_destroy(struct drm_encoder *encoder);
494 extern void intel_encoder_dpms(struct intel_encoder *encoder, int mode);
495 extern bool intel_encoder_check_is_cloned(struct intel_encoder *encoder);
496 extern void intel_connector_dpms(struct drm_connector *, int mode);
497 extern bool intel_connector_get_hw_state(struct intel_connector *connector);
498 extern void intel_modeset_check_state(struct drm_device *dev);
501 static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector)
503 return to_intel_connector(connector)->encoder;
506 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
508 struct intel_digital_port *intel_dig_port =
509 container_of(encoder, struct intel_digital_port, base.base);
510 return &intel_dig_port->dp;
513 static inline struct intel_digital_port *
514 enc_to_dig_port(struct drm_encoder *encoder)
516 return container_of(encoder, struct intel_digital_port, base.base);
519 static inline struct intel_digital_port *
520 dp_to_dig_port(struct intel_dp *intel_dp)
522 return container_of(intel_dp, struct intel_digital_port, dp);
525 static inline struct intel_digital_port *
526 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
528 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
531 extern void intel_connector_attach_encoder(struct intel_connector *connector,
532 struct intel_encoder *encoder);
533 extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
535 extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
536 struct drm_crtc *crtc);
537 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
538 struct drm_file *file_priv);
539 extern enum transcoder
540 intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
542 extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
543 extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
545 struct intel_load_detect_pipe {
546 struct drm_framebuffer *release_fb;
547 bool load_detect_temp;
550 extern bool intel_get_load_detect_pipe(struct drm_connector *connector,
551 struct drm_display_mode *mode,
552 struct intel_load_detect_pipe *old);
553 extern void intel_release_load_detect_pipe(struct drm_connector *connector,
554 struct intel_load_detect_pipe *old);
556 extern void intelfb_restore(void);
557 extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
558 u16 blue, int regno);
559 extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
560 u16 *blue, int regno);
561 extern void intel_enable_clock_gating(struct drm_device *dev);
563 extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
564 struct drm_i915_gem_object *obj,
565 struct intel_ring_buffer *pipelined);
566 extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
568 extern int intel_framebuffer_init(struct drm_device *dev,
569 struct intel_framebuffer *ifb,
570 struct drm_mode_fb_cmd2 *mode_cmd,
571 struct drm_i915_gem_object *obj);
572 extern int intel_fbdev_init(struct drm_device *dev);
573 extern void intel_fbdev_fini(struct drm_device *dev);
574 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
575 extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
576 extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
577 extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
579 extern void intel_setup_overlay(struct drm_device *dev);
580 extern void intel_cleanup_overlay(struct drm_device *dev);
581 extern int intel_overlay_switch_off(struct intel_overlay *overlay);
582 extern int intel_overlay_put_image(struct drm_device *dev, void *data,
583 struct drm_file *file_priv);
584 extern int intel_overlay_attrs(struct drm_device *dev, void *data,
585 struct drm_file *file_priv);
587 extern void intel_fb_output_poll_changed(struct drm_device *dev);
588 extern void intel_fb_restore_mode(struct drm_device *dev);
590 extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
592 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
593 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
595 extern void intel_init_clock_gating(struct drm_device *dev);
596 extern void intel_write_eld(struct drm_encoder *encoder,
597 struct drm_display_mode *mode);
598 extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
599 extern void intel_prepare_ddi(struct drm_device *dev);
600 extern void hsw_fdi_link_train(struct drm_crtc *crtc);
601 extern void intel_ddi_init(struct drm_device *dev, enum port port);
603 /* For use by IVB LP watermark workaround in intel_sprite.c */
604 extern void intel_update_watermarks(struct drm_device *dev);
605 extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
606 uint32_t sprite_width,
608 extern void intel_update_linetime_watermarks(struct drm_device *dev, int pipe,
609 struct drm_display_mode *mode);
611 extern unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
615 extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
616 struct drm_file *file_priv);
617 extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
618 struct drm_file *file_priv);
620 extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg);
622 /* Power-related functions, located in intel_pm.c */
623 extern void intel_init_pm(struct drm_device *dev);
625 extern bool intel_fbc_enabled(struct drm_device *dev);
626 extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
627 extern void intel_update_fbc(struct drm_device *dev);
629 extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
630 extern void intel_gpu_ips_teardown(void);
632 extern void intel_init_power_wells(struct drm_device *dev);
633 extern void intel_enable_gt_powersave(struct drm_device *dev);
634 extern void intel_disable_gt_powersave(struct drm_device *dev);
635 extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv);
636 extern void ironlake_teardown_rc6(struct drm_device *dev);
638 extern void intel_enable_ddi(struct intel_encoder *intel_encoder);
639 extern void intel_disable_ddi(struct intel_encoder *intel_encoder);
640 extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
642 extern void intel_ddi_mode_set(struct drm_encoder *encoder,
643 struct drm_display_mode *mode,
644 struct drm_display_mode *adjusted_mode);
645 extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
646 extern void intel_ddi_pll_init(struct drm_device *dev);
647 extern void intel_ddi_enable_pipe_func(struct drm_crtc *crtc);
648 extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
649 enum transcoder cpu_transcoder);
650 extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
651 extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
652 extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
653 extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock);
654 extern void intel_ddi_pre_enable(struct intel_encoder *intel_encoder);
655 extern void intel_ddi_post_disable(struct intel_encoder *intel_encoder);
656 extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
657 extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
658 extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
659 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
661 #endif /* __INTEL_DRV_H__ */