2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <drm/i915_drm.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_fb_helper.h>
36 #include <drm/drm_dp_mst_helper.h>
37 #include <drm/drm_rect.h>
38 #include <drm/drm_atomic.h>
41 * _wait_for - magic (register) wait macro
43 * Does the right thing for modeset paths when run under kdgb or similar atomic
44 * contexts. Note that it's important that we check the condition again after
45 * having timed out, since the timeout could be due to preemption or similar and
46 * we've never had a chance to check the condition before the timeout.
48 #define _wait_for(COND, MS, W) ({ \
49 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
52 if (time_after(jiffies, timeout__)) { \
57 if ((W) && drm_can_sleep()) { \
58 usleep_range((W)*1000, (W)*2000); \
66 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
67 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
68 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
69 DIV_ROUND_UP((US), 1000), 0)
71 #define KHz(x) (1000 * (x))
72 #define MHz(x) KHz(1000 * (x))
75 * Display related stuff
78 /* store information about an Ixxx DVO */
79 /* The i830->i865 use multiple DVOs with multiple i2cs */
80 /* the i915, i945 have a single sDVO i2c bus - which is different */
82 /* maximum connectors per crtcs in the mode set */
84 /* Maximum cursor sizes */
85 #define GEN2_CURSOR_WIDTH 64
86 #define GEN2_CURSOR_HEIGHT 64
87 #define MAX_CURSOR_WIDTH 256
88 #define MAX_CURSOR_HEIGHT 256
90 #define INTEL_I2C_BUS_DVO 1
91 #define INTEL_I2C_BUS_SDVO 2
93 /* these are outputs from the chip - integrated only
94 external chips are via DVO or SDVO output */
95 enum intel_output_type {
96 INTEL_OUTPUT_UNUSED = 0,
97 INTEL_OUTPUT_ANALOG = 1,
99 INTEL_OUTPUT_SDVO = 3,
100 INTEL_OUTPUT_LVDS = 4,
101 INTEL_OUTPUT_TVOUT = 5,
102 INTEL_OUTPUT_HDMI = 6,
103 INTEL_OUTPUT_DISPLAYPORT = 7,
104 INTEL_OUTPUT_EDP = 8,
105 INTEL_OUTPUT_DSI = 9,
106 INTEL_OUTPUT_UNKNOWN = 10,
107 INTEL_OUTPUT_DP_MST = 11,
110 #define INTEL_DVO_CHIP_NONE 0
111 #define INTEL_DVO_CHIP_LVDS 1
112 #define INTEL_DVO_CHIP_TMDS 2
113 #define INTEL_DVO_CHIP_TVOUT 4
115 #define INTEL_DSI_VIDEO_MODE 0
116 #define INTEL_DSI_COMMAND_MODE 1
118 struct intel_framebuffer {
119 struct drm_framebuffer base;
120 struct drm_i915_gem_object *obj;
124 struct drm_fb_helper helper;
125 struct intel_framebuffer *fb;
126 struct list_head fbdev_list;
127 struct drm_display_mode *our_mode;
131 struct intel_encoder {
132 struct drm_encoder base;
134 * The new crtc this encoder will be driven from. Only differs from
135 * base->crtc while a modeset is in progress.
137 struct intel_crtc *new_crtc;
139 enum intel_output_type type;
140 unsigned int cloneable;
141 bool connectors_active;
142 void (*hot_plug)(struct intel_encoder *);
143 bool (*compute_config)(struct intel_encoder *,
144 struct intel_crtc_state *);
145 void (*pre_pll_enable)(struct intel_encoder *);
146 void (*pre_enable)(struct intel_encoder *);
147 void (*enable)(struct intel_encoder *);
148 void (*mode_set)(struct intel_encoder *intel_encoder);
149 void (*disable)(struct intel_encoder *);
150 void (*post_disable)(struct intel_encoder *);
151 /* Read out the current hw state of this connector, returning true if
152 * the encoder is active. If the encoder is enabled it also set the pipe
153 * it is connected to in the pipe parameter. */
154 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
155 /* Reconstructs the equivalent mode flags for the current hardware
156 * state. This must be called _after_ display->get_pipe_config has
157 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
158 * be set correctly before calling this function. */
159 void (*get_config)(struct intel_encoder *,
160 struct intel_crtc_state *pipe_config);
162 * Called during system suspend after all pending requests for the
163 * encoder are flushed (for example for DP AUX transactions) and
164 * device interrupts are disabled.
166 void (*suspend)(struct intel_encoder *);
168 enum hpd_pin hpd_pin;
172 struct drm_display_mode *fixed_mode;
173 struct drm_display_mode *downclock_mode;
183 bool combination_mode; /* gen 2/4 only */
185 struct backlight_device *device;
188 void (*backlight_power)(struct intel_connector *, bool enable);
191 struct intel_connector {
192 struct drm_connector base;
194 * The fixed encoder this connector is connected to.
196 struct intel_encoder *encoder;
199 * The new encoder this connector will be driven. Only differs from
200 * encoder while a modeset is in progress.
202 struct intel_encoder *new_encoder;
204 /* Reads out the current hw, returning true if the connector is enabled
205 * and active (i.e. dpms ON state). */
206 bool (*get_hw_state)(struct intel_connector *);
209 * Removes all interfaces through which the connector is accessible
210 * - like sysfs, debugfs entries -, so that no new operations can be
211 * started on the connector. Also makes sure all currently pending
212 * operations finish before returing.
214 void (*unregister)(struct intel_connector *);
216 /* Panel info for eDP and LVDS */
217 struct intel_panel panel;
219 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
221 struct edid *detect_edid;
223 /* since POLL and HPD connectors may use the same HPD line keep the native
224 state of connector->polled in case hotplug storm detection changes it */
227 void *port; /* store this opaque as its illegal to dereference it */
229 struct intel_dp *mst_port;
232 typedef struct dpll {
244 struct intel_plane_state {
245 struct drm_plane_state base;
248 struct drm_rect clip;
253 * = -1 : not using a scaler
254 * >= 0 : using a scalers
256 * plane requiring a scaler:
257 * - During check_plane, its bit is set in
258 * crtc_state->scaler_state.scaler_users by calling helper function
259 * update_scaler_users.
260 * - scaler_id indicates the scaler it got assigned.
262 * plane doesn't require a scaler:
263 * - this can happen when scaling is no more required or plane simply
265 * - During check_plane, corresponding bit is reset in
266 * crtc_state->scaler_state.scaler_users by calling helper function
267 * update_scaler_users.
272 struct intel_initial_plane_config {
273 struct intel_framebuffer *fb;
279 #define SKL_MIN_SRC_W 8
280 #define SKL_MAX_SRC_W 4096
281 #define SKL_MIN_SRC_H 8
282 #define SKL_MAX_SRC_H 4096
283 #define SKL_MIN_DST_W 8
284 #define SKL_MAX_DST_W 4096
285 #define SKL_MIN_DST_H 8
286 #define SKL_MAX_DST_H 4096
288 struct intel_scaler {
294 struct intel_crtc_scaler_state {
295 #define SKL_NUM_SCALERS 2
296 struct intel_scaler scalers[SKL_NUM_SCALERS];
299 * scaler_users: keeps track of users requesting scalers on this crtc.
301 * If a bit is set, a user is using a scaler.
302 * Here user can be a plane or crtc as defined below:
303 * bits 0-30 - plane (bit position is index from drm_plane_index)
306 * Instead of creating a new index to cover planes and crtc, using
307 * existing drm_plane_index for planes which is well less than 31
308 * planes and bit 31 for crtc. This should be fine to cover all
311 * intel_atomic_setup_scalers will setup available scalers to users
312 * requesting scalers. It will gracefully fail if request exceeds
315 #define SKL_CRTC_INDEX 31
316 unsigned scaler_users;
318 /* scaler used by crtc for panel fitting purpose */
322 struct intel_crtc_state {
323 struct drm_crtc_state base;
326 * quirks - bitfield with hw state readout quirks
328 * For various reasons the hw state readout code might not be able to
329 * completely faithfully read out the current state. These cases are
330 * tracked with quirk flags so that fastboot and state checker can act
333 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
334 #define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1) /* mode inherited from firmware */
335 unsigned long quirks;
337 /* Pipe source size (ie. panel fitter input size)
338 * All planes will be positioned inside this space,
339 * and get clipped at the edges. */
340 int pipe_src_w, pipe_src_h;
342 /* Whether to set up the PCH/FDI. Note that we never allow sharing
343 * between pch encoders and cpu encoders. */
344 bool has_pch_encoder;
346 /* Are we sending infoframes on the attached port */
349 /* CPU Transcoder for the pipe. Currently this can only differ from the
350 * pipe on Haswell (where we have a special eDP transcoder). */
351 enum transcoder cpu_transcoder;
354 * Use reduced/limited/broadcast rbg range, compressing from the full
355 * range fed into the crtcs.
357 bool limited_color_range;
359 /* DP has a bunch of special case unfortunately, so mark the pipe
363 /* Whether we should send NULL infoframes. Required for audio. */
366 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
367 * has_dp_encoder is set. */
371 * Enable dithering, used when the selected pipe bpp doesn't match the
376 /* Controls for the clock computation, to override various stages. */
379 /* SDVO TV has a bunch of special case. To make multifunction encoders
380 * work correctly, we need to track this at runtime.*/
384 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
385 * required. This is set in the 2nd loop of calling encoder's
386 * ->compute_config if the first pick doesn't work out.
390 /* Settings for the intel dpll used on pretty much everything but
394 /* Selected dpll when shared or DPLL_ID_PRIVATE. */
395 enum intel_dpll_id shared_dpll;
398 * - PORT_CLK_SEL for DDI ports on HSW/BDW.
399 * - enum skl_dpll on SKL
401 uint32_t ddi_pll_sel;
403 /* Actual register state of the dpll, for shared dpll cross-checking. */
404 struct intel_dpll_hw_state dpll_hw_state;
407 struct intel_link_m_n dp_m_n;
409 /* m2_n2 for eDP downclock */
410 struct intel_link_m_n dp_m2_n2;
414 * Frequence the dpll for the port should run at. Differs from the
415 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
416 * already multiplied by pixel_multiplier.
420 /* Used by SDVO (and if we ever fix it, HDMI). */
421 unsigned pixel_multiplier;
423 /* Panel fitter controls for gen2-gen4 + VLV */
427 u32 lvds_border_bits;
430 /* Panel fitter placement and size for Ironlake+ */
438 /* FDI configuration, only valid if has_pch_encoder is set. */
440 struct intel_link_m_n fdi_m_n;
446 bool dp_encoder_is_mst;
449 struct intel_crtc_scaler_state scaler_state;
452 struct intel_pipe_wm {
453 struct intel_wm_level wm[5];
457 bool sprites_enabled;
461 struct intel_mmio_flip {
462 struct drm_i915_gem_request *req;
463 struct work_struct work;
467 struct skl_wm_level wm[8];
468 struct skl_wm_level trans_wm;
473 * Tracking of operations that need to be performed at the beginning/end of an
474 * atomic commit, outside the atomic section where interrupts are disabled.
475 * These are generally operations that grab mutexes or might otherwise sleep
476 * and thus can't be run with interrupts disabled.
478 struct intel_crtc_atomic_commit {
481 unsigned start_vbl_count;
483 /* Sleepable operations to perform before commit */
486 bool pre_disable_primary;
488 unsigned disabled_planes;
490 /* Sleepable operations to perform after commit */
494 bool post_enable_primary;
495 unsigned update_sprite_watermarks;
499 struct drm_crtc base;
502 u8 lut_r[256], lut_g[256], lut_b[256];
504 * Whether the crtc and the connected output pipeline is active. Implies
505 * that crtc->enabled is set, i.e. the current mode configuration has
506 * some outputs connected to this crtc.
509 unsigned long enabled_power_domains;
510 bool primary_enabled; /* is the primary plane (partially) visible? */
512 struct intel_overlay *overlay;
513 struct intel_unpin_work *unpin_work;
515 atomic_t unpin_work_count;
517 /* Display surface base address adjustement for pageflips. Note that on
518 * gen4+ this only adjusts up to a tile, offsets within a tile are
519 * handled in the hw itself (with the TILEOFF register). */
520 unsigned long dspaddr_offset;
522 struct drm_i915_gem_object *cursor_bo;
523 uint32_t cursor_addr;
524 uint32_t cursor_cntl;
525 uint32_t cursor_size;
526 uint32_t cursor_base;
528 struct intel_initial_plane_config plane_config;
529 struct intel_crtc_state *config;
532 /* reset counter value when the last flip was submitted */
533 unsigned int reset_counter;
535 /* Access to these should be protected by dev_priv->irq_lock. */
536 bool cpu_fifo_underrun_disabled;
537 bool pch_fifo_underrun_disabled;
539 /* per-pipe watermark state */
541 /* watermarks currently being used */
542 struct intel_pipe_wm active;
543 /* SKL wm values currently in use */
544 struct skl_pipe_wm skl_active;
548 struct intel_mmio_flip mmio_flip;
550 struct intel_crtc_atomic_commit atomic;
552 /* scalers available on this crtc */
556 struct intel_plane_wm_parameters {
557 uint32_t horiz_pixels;
558 uint32_t vert_pixels;
559 uint8_t bytes_per_pixel;
563 unsigned int rotation;
567 struct drm_plane base;
573 /* FIXME convert to properties */
574 struct drm_intel_sprite_colorkey ckey;
576 /* Since we need to change the watermarks before/after
577 * enabling/disabling the planes, we need to store the parameters here
578 * as the other pieces of the struct may not reflect the values we want
579 * for the watermark calculations. Currently only Haswell uses this.
581 struct intel_plane_wm_parameters wm;
584 * NOTE: Do not place new plane state fields here (e.g., when adding
585 * new plane properties). New runtime state should now be placed in
586 * the intel_plane_state structure and accessed via drm_plane->state.
589 void (*update_plane)(struct drm_plane *plane,
590 struct drm_crtc *crtc,
591 struct drm_framebuffer *fb,
592 int crtc_x, int crtc_y,
593 unsigned int crtc_w, unsigned int crtc_h,
594 uint32_t x, uint32_t y,
595 uint32_t src_w, uint32_t src_h);
596 void (*disable_plane)(struct drm_plane *plane,
597 struct drm_crtc *crtc);
598 int (*check_plane)(struct drm_plane *plane,
599 struct intel_plane_state *state);
600 void (*commit_plane)(struct drm_plane *plane,
601 struct intel_plane_state *state);
604 struct intel_watermark_params {
605 unsigned long fifo_size;
606 unsigned long max_wm;
607 unsigned long default_wm;
608 unsigned long guard_size;
609 unsigned long cacheline_size;
612 struct cxsr_latency {
615 unsigned long fsb_freq;
616 unsigned long mem_freq;
617 unsigned long display_sr;
618 unsigned long display_hpll_disable;
619 unsigned long cursor_sr;
620 unsigned long cursor_hpll_disable;
623 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
624 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
625 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
626 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
627 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
628 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
629 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
630 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
635 uint32_t color_range;
636 bool color_range_auto;
639 enum hdmi_force_audio force_audio;
640 bool rgb_quant_range_selectable;
641 enum hdmi_picture_aspect aspect_ratio;
642 void (*write_infoframe)(struct drm_encoder *encoder,
643 enum hdmi_infoframe_type type,
644 const void *frame, ssize_t len);
645 void (*set_infoframes)(struct drm_encoder *encoder,
647 struct drm_display_mode *adjusted_mode);
648 bool (*infoframe_enabled)(struct drm_encoder *encoder);
651 struct intel_dp_mst_encoder;
652 #define DP_MAX_DOWNSTREAM_PORTS 0x10
656 * When platform provides two set of M_N registers for dp, we can
657 * program them and switch between them incase of DRRS.
658 * But When only one such register is provided, we have to program the
659 * required divider value on that registers itself based on the DRRS state.
661 * M1_N1 : Program dp_m_n on M1_N1 registers
662 * dp_m2_n2 on M2_N2 registers (If supported)
664 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
665 * M2_N2 registers are not supported
669 /* Sets the m1_n1 and m2_n2 */
676 uint32_t aux_ch_ctl_reg;
679 enum hdmi_force_audio force_audio;
680 uint32_t color_range;
681 bool color_range_auto;
685 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
686 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
687 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
688 /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
689 uint8_t num_sink_rates;
690 int sink_rates[DP_MAX_SUPPORTED_RATES];
691 struct drm_dp_aux aux;
692 uint8_t train_set[4];
693 int panel_power_up_delay;
694 int panel_power_down_delay;
695 int panel_power_cycle_delay;
696 int backlight_on_delay;
697 int backlight_off_delay;
698 struct delayed_work panel_vdd_work;
700 unsigned long last_power_cycle;
701 unsigned long last_power_on;
702 unsigned long last_backlight_off;
704 struct notifier_block edp_notifier;
707 * Pipe whose power sequencer is currently locked into
708 * this port. Only relevant on VLV/CHV.
711 struct edp_power_seq pps_delays;
714 bool can_mst; /* this port supports mst */
716 int active_mst_links;
717 /* connector directly attached - won't be use for modeset in mst world */
718 struct intel_connector *attached_connector;
720 /* mst connector list */
721 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
722 struct drm_dp_mst_topology_mgr mst_mgr;
724 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
726 * This function returns the value we have to program the AUX_CTL
727 * register with to kick off an AUX transaction.
729 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
732 uint32_t aux_clock_divider);
733 bool train_set_valid;
735 /* Displayport compliance testing */
736 unsigned long compliance_test_type;
737 unsigned long compliance_test_data;
738 bool compliance_test_active;
741 struct intel_digital_port {
742 struct intel_encoder base;
746 struct intel_hdmi hdmi;
747 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
750 struct intel_dp_mst_encoder {
751 struct intel_encoder base;
753 struct intel_digital_port *primary;
754 void *port; /* store this opaque as its illegal to dereference it */
758 vlv_dport_to_channel(struct intel_digital_port *dport)
760 switch (dport->port) {
772 vlv_pipe_to_channel(enum pipe pipe)
785 static inline struct drm_crtc *
786 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
788 struct drm_i915_private *dev_priv = dev->dev_private;
789 return dev_priv->pipe_to_crtc_mapping[pipe];
792 static inline struct drm_crtc *
793 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
795 struct drm_i915_private *dev_priv = dev->dev_private;
796 return dev_priv->plane_to_crtc_mapping[plane];
799 struct intel_unpin_work {
800 struct work_struct work;
801 struct drm_crtc *crtc;
802 struct drm_framebuffer *old_fb;
803 struct drm_i915_gem_object *pending_flip_obj;
804 struct drm_pending_vblank_event *event;
806 #define INTEL_FLIP_INACTIVE 0
807 #define INTEL_FLIP_PENDING 1
808 #define INTEL_FLIP_COMPLETE 2
811 struct drm_i915_gem_request *flip_queued_req;
812 int flip_queued_vblank;
813 int flip_ready_vblank;
814 bool enable_stall_check;
817 struct intel_set_config {
818 struct drm_encoder **save_connector_encoders;
819 struct drm_crtc **save_encoder_crtcs;
820 bool *save_crtc_enabled;
826 struct intel_load_detect_pipe {
827 struct drm_framebuffer *release_fb;
828 bool load_detect_temp;
832 static inline struct intel_encoder *
833 intel_attached_encoder(struct drm_connector *connector)
835 return to_intel_connector(connector)->encoder;
838 static inline struct intel_digital_port *
839 enc_to_dig_port(struct drm_encoder *encoder)
841 return container_of(encoder, struct intel_digital_port, base.base);
844 static inline struct intel_dp_mst_encoder *
845 enc_to_mst(struct drm_encoder *encoder)
847 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
850 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
852 return &enc_to_dig_port(encoder)->dp;
855 static inline struct intel_digital_port *
856 dp_to_dig_port(struct intel_dp *intel_dp)
858 return container_of(intel_dp, struct intel_digital_port, dp);
861 static inline struct intel_digital_port *
862 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
864 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
868 * Returns the number of planes for this pipe, ie the number of sprites + 1
869 * (primary plane). This doesn't count the cursor plane then.
871 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
873 return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
876 /* intel_fifo_underrun.c */
877 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
878 enum pipe pipe, bool enable);
879 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
880 enum transcoder pch_transcoder,
882 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
884 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
885 enum transcoder pch_transcoder);
886 void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv);
889 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
890 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
891 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
892 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
893 void gen6_reset_rps_interrupts(struct drm_device *dev);
894 void gen6_enable_rps_interrupts(struct drm_device *dev);
895 void gen6_disable_rps_interrupts(struct drm_device *dev);
896 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
897 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
898 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
899 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
902 * We only use drm_irq_uninstall() at unload and VT switch, so
903 * this is the only thing we need to check.
905 return dev_priv->pm.irqs_enabled;
908 int intel_get_crtc_scanline(struct intel_crtc *crtc);
909 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
910 unsigned int pipe_mask);
913 void intel_crt_init(struct drm_device *dev);
917 void intel_prepare_ddi(struct drm_device *dev);
918 void hsw_fdi_link_train(struct drm_crtc *crtc);
919 void intel_ddi_init(struct drm_device *dev, enum port port);
920 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
921 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
922 void intel_ddi_pll_init(struct drm_device *dev);
923 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
924 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
925 enum transcoder cpu_transcoder);
926 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
927 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
928 bool intel_ddi_pll_select(struct intel_crtc *crtc,
929 struct intel_crtc_state *crtc_state);
930 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
931 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
932 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
933 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
934 void intel_ddi_get_config(struct intel_encoder *encoder,
935 struct intel_crtc_state *pipe_config);
936 struct intel_encoder *
937 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
939 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
940 void intel_ddi_clock_get(struct intel_encoder *encoder,
941 struct intel_crtc_state *pipe_config);
942 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
943 void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
944 enum port port, int type);
946 /* intel_frontbuffer.c */
947 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
948 struct intel_engine_cs *ring,
949 enum fb_op_origin origin);
950 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
951 unsigned frontbuffer_bits);
952 void intel_frontbuffer_flip_complete(struct drm_device *dev,
953 unsigned frontbuffer_bits);
954 void intel_frontbuffer_flush(struct drm_device *dev,
955 unsigned frontbuffer_bits);
957 * intel_frontbuffer_flip - synchronous frontbuffer flip
959 * @frontbuffer_bits: frontbuffer plane tracking bits
961 * This function gets called after scheduling a flip on @obj. This is for
962 * synchronous plane updates which will happen on the next vblank and which will
963 * not get delayed by pending gpu rendering.
965 * Can be called without any locks held.
968 void intel_frontbuffer_flip(struct drm_device *dev,
969 unsigned frontbuffer_bits)
971 intel_frontbuffer_flush(dev, frontbuffer_bits);
974 unsigned int intel_fb_align_height(struct drm_device *dev,
976 uint32_t pixel_format,
977 uint64_t fb_format_modifier);
978 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire);
980 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
981 uint32_t pixel_format);
984 void intel_init_audio(struct drm_device *dev);
985 void intel_audio_codec_enable(struct intel_encoder *encoder);
986 void intel_audio_codec_disable(struct intel_encoder *encoder);
987 void i915_audio_component_init(struct drm_i915_private *dev_priv);
988 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
990 /* intel_display.c */
991 extern const struct drm_plane_funcs intel_plane_funcs;
992 bool intel_has_pending_fb_unpin(struct drm_device *dev);
993 int intel_pch_rawclk(struct drm_device *dev);
994 void intel_mark_busy(struct drm_device *dev);
995 void intel_mark_idle(struct drm_device *dev);
996 void intel_crtc_restore_mode(struct drm_crtc *crtc);
997 void intel_crtc_control(struct drm_crtc *crtc, bool enable);
998 void intel_crtc_update_dpms(struct drm_crtc *crtc);
999 void intel_encoder_destroy(struct drm_encoder *encoder);
1000 int intel_connector_init(struct intel_connector *);
1001 struct intel_connector *intel_connector_alloc(void);
1002 void intel_connector_dpms(struct drm_connector *, int mode);
1003 bool intel_connector_get_hw_state(struct intel_connector *connector);
1004 void intel_modeset_check_state(struct drm_device *dev);
1005 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1006 struct intel_digital_port *port);
1007 void intel_connector_attach_encoder(struct intel_connector *connector,
1008 struct intel_encoder *encoder);
1009 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
1010 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1011 struct drm_crtc *crtc);
1012 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1013 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1014 struct drm_file *file_priv);
1015 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1017 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
1019 intel_wait_for_vblank(struct drm_device *dev, int pipe)
1021 drm_wait_one_vblank(dev, pipe);
1023 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1024 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1025 struct intel_digital_port *dport);
1026 bool intel_get_load_detect_pipe(struct drm_connector *connector,
1027 struct drm_display_mode *mode,
1028 struct intel_load_detect_pipe *old,
1029 struct drm_modeset_acquire_ctx *ctx);
1030 void intel_release_load_detect_pipe(struct drm_connector *connector,
1031 struct intel_load_detect_pipe *old,
1032 struct drm_modeset_acquire_ctx *ctx);
1033 int intel_pin_and_fence_fb_obj(struct drm_plane *plane,
1034 struct drm_framebuffer *fb,
1035 const struct drm_plane_state *plane_state,
1036 struct intel_engine_cs *pipelined);
1037 struct drm_framebuffer *
1038 __intel_framebuffer_create(struct drm_device *dev,
1039 struct drm_mode_fb_cmd2 *mode_cmd,
1040 struct drm_i915_gem_object *obj);
1041 void intel_prepare_page_flip(struct drm_device *dev, int plane);
1042 void intel_finish_page_flip(struct drm_device *dev, int pipe);
1043 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
1044 void intel_check_page_flip(struct drm_device *dev, int pipe);
1045 int intel_prepare_plane_fb(struct drm_plane *plane,
1046 struct drm_framebuffer *fb,
1047 const struct drm_plane_state *new_state);
1048 void intel_cleanup_plane_fb(struct drm_plane *plane,
1049 struct drm_framebuffer *fb,
1050 const struct drm_plane_state *old_state);
1051 int intel_plane_atomic_get_property(struct drm_plane *plane,
1052 const struct drm_plane_state *state,
1053 struct drm_property *property,
1055 int intel_plane_atomic_set_property(struct drm_plane *plane,
1056 struct drm_plane_state *state,
1057 struct drm_property *property,
1061 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
1062 uint64_t fb_format_modifier);
1065 intel_rotation_90_or_270(unsigned int rotation)
1067 return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
1071 intel_tile_height(struct drm_device *dev, uint32_t bits_per_pixel,
1072 uint64_t fb_modifier);
1073 void intel_create_rotation_property(struct drm_device *dev,
1074 struct intel_plane *plane);
1076 bool intel_wm_need_update(struct drm_plane *plane,
1077 struct drm_plane_state *state);
1079 /* shared dpll functions */
1080 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
1081 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1082 struct intel_shared_dpll *pll,
1084 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
1085 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
1086 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
1087 struct intel_crtc_state *state);
1088 void intel_put_shared_dpll(struct intel_crtc *crtc);
1090 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1091 const struct dpll *dpll);
1092 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1094 /* modesetting asserts */
1095 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1097 void assert_pll(struct drm_i915_private *dev_priv,
1098 enum pipe pipe, bool state);
1099 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1100 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1101 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1102 enum pipe pipe, bool state);
1103 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1104 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1105 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1106 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1107 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1108 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1109 unsigned int tiling_mode,
1111 unsigned int pitch);
1112 void intel_prepare_reset(struct drm_device *dev);
1113 void intel_finish_reset(struct drm_device *dev);
1114 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1115 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1116 void broxton_init_cdclk(struct drm_device *dev);
1117 void broxton_uninit_cdclk(struct drm_device *dev);
1118 void broxton_set_cdclk(struct drm_device *dev, int frequency);
1119 void broxton_ddi_phy_init(struct drm_device *dev);
1120 void broxton_ddi_phy_uninit(struct drm_device *dev);
1121 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1122 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1123 void intel_dp_get_m_n(struct intel_crtc *crtc,
1124 struct intel_crtc_state *pipe_config);
1125 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1126 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1128 ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
1130 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1131 intel_clock_t *best_clock);
1132 bool intel_crtc_active(struct drm_crtc *crtc);
1133 void hsw_enable_ips(struct intel_crtc *crtc);
1134 void hsw_disable_ips(struct intel_crtc *crtc);
1135 enum intel_display_power_domain
1136 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1137 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1138 struct intel_crtc_state *pipe_config);
1139 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
1140 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
1141 void skl_detach_scalers(struct intel_crtc *intel_crtc);
1142 int skl_update_scaler_users(struct intel_crtc *intel_crtc,
1143 struct intel_crtc_state *crtc_state, struct intel_plane *intel_plane,
1144 struct intel_plane_state *plane_state, int force_detach);
1145 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1147 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
1148 struct drm_i915_gem_object *obj);
1149 u32 skl_plane_ctl_format(uint32_t pixel_format);
1150 u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1151 u32 skl_plane_ctl_rotation(unsigned int rotation);
1154 void intel_csr_ucode_init(struct drm_device *dev);
1155 enum csr_state intel_csr_load_status_get(struct drm_i915_private *dev_priv);
1156 void intel_csr_load_status_set(struct drm_i915_private *dev_priv,
1157 enum csr_state state);
1158 void intel_csr_load_program(struct drm_device *dev);
1159 void intel_csr_ucode_fini(struct drm_device *dev);
1160 void assert_csr_loaded(struct drm_i915_private *dev_priv);
1163 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
1164 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1165 struct intel_connector *intel_connector);
1166 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1167 void intel_dp_complete_link_train(struct intel_dp *intel_dp);
1168 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1169 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1170 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1171 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1172 bool intel_dp_compute_config(struct intel_encoder *encoder,
1173 struct intel_crtc_state *pipe_config);
1174 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1175 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1177 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1178 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1179 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1180 void intel_edp_panel_on(struct intel_dp *intel_dp);
1181 void intel_edp_panel_off(struct intel_dp *intel_dp);
1182 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1183 void intel_dp_mst_suspend(struct drm_device *dev);
1184 void intel_dp_mst_resume(struct drm_device *dev);
1185 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1186 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1187 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1188 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
1189 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1190 void intel_plane_destroy(struct drm_plane *plane);
1191 void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1192 void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1193 void intel_edp_drrs_invalidate(struct drm_device *dev,
1194 unsigned frontbuffer_bits);
1195 void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
1197 /* intel_dp_mst.c */
1198 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1199 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1201 void intel_dsi_init(struct drm_device *dev);
1205 void intel_dvo_init(struct drm_device *dev);
1208 /* legacy fbdev emulation in intel_fbdev.c */
1209 #ifdef CONFIG_DRM_I915_FBDEV
1210 extern int intel_fbdev_init(struct drm_device *dev);
1211 extern void intel_fbdev_initial_config(void *data, async_cookie_t cookie);
1212 extern void intel_fbdev_fini(struct drm_device *dev);
1213 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1214 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1215 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1217 static inline int intel_fbdev_init(struct drm_device *dev)
1222 static inline void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
1226 static inline void intel_fbdev_fini(struct drm_device *dev)
1230 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1234 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1240 bool intel_fbc_enabled(struct drm_device *dev);
1241 void intel_fbc_update(struct drm_device *dev);
1242 void intel_fbc_init(struct drm_i915_private *dev_priv);
1243 void intel_fbc_disable(struct drm_device *dev);
1244 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1245 unsigned int frontbuffer_bits,
1246 enum fb_op_origin origin);
1247 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1248 unsigned int frontbuffer_bits);
1251 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
1252 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1253 struct intel_connector *intel_connector);
1254 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1255 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1256 struct intel_crtc_state *pipe_config);
1260 void intel_lvds_init(struct drm_device *dev);
1261 bool intel_is_dual_link_lvds(struct drm_device *dev);
1265 int intel_connector_update_modes(struct drm_connector *connector,
1267 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1268 void intel_attach_force_audio_property(struct drm_connector *connector);
1269 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1272 /* intel_overlay.c */
1273 void intel_setup_overlay(struct drm_device *dev);
1274 void intel_cleanup_overlay(struct drm_device *dev);
1275 int intel_overlay_switch_off(struct intel_overlay *overlay);
1276 int intel_overlay_put_image(struct drm_device *dev, void *data,
1277 struct drm_file *file_priv);
1278 int intel_overlay_attrs(struct drm_device *dev, void *data,
1279 struct drm_file *file_priv);
1280 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1284 int intel_panel_init(struct intel_panel *panel,
1285 struct drm_display_mode *fixed_mode,
1286 struct drm_display_mode *downclock_mode);
1287 void intel_panel_fini(struct intel_panel *panel);
1288 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1289 struct drm_display_mode *adjusted_mode);
1290 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1291 struct intel_crtc_state *pipe_config,
1293 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1294 struct intel_crtc_state *pipe_config,
1296 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1297 u32 level, u32 max);
1298 int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
1299 void intel_panel_enable_backlight(struct intel_connector *connector);
1300 void intel_panel_disable_backlight(struct intel_connector *connector);
1301 void intel_panel_destroy_backlight(struct drm_connector *connector);
1302 void intel_panel_init_backlight_funcs(struct drm_device *dev);
1303 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1304 extern struct drm_display_mode *intel_find_panel_downclock(
1305 struct drm_device *dev,
1306 struct drm_display_mode *fixed_mode,
1307 struct drm_connector *connector);
1308 void intel_backlight_register(struct drm_device *dev);
1309 void intel_backlight_unregister(struct drm_device *dev);
1313 void intel_psr_enable(struct intel_dp *intel_dp);
1314 void intel_psr_disable(struct intel_dp *intel_dp);
1315 void intel_psr_invalidate(struct drm_device *dev,
1316 unsigned frontbuffer_bits);
1317 void intel_psr_flush(struct drm_device *dev,
1318 unsigned frontbuffer_bits);
1319 void intel_psr_init(struct drm_device *dev);
1320 void intel_psr_single_frame_update(struct drm_device *dev);
1322 /* intel_runtime_pm.c */
1323 int intel_power_domains_init(struct drm_i915_private *);
1324 void intel_power_domains_fini(struct drm_i915_private *);
1325 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
1326 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1328 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1329 enum intel_display_power_domain domain);
1330 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1331 enum intel_display_power_domain domain);
1332 void intel_display_power_get(struct drm_i915_private *dev_priv,
1333 enum intel_display_power_domain domain);
1334 void intel_display_power_put(struct drm_i915_private *dev_priv,
1335 enum intel_display_power_domain domain);
1336 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
1337 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
1338 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1339 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1340 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1342 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1345 void intel_init_clock_gating(struct drm_device *dev);
1346 void intel_suspend_hw(struct drm_device *dev);
1347 int ilk_wm_max_level(const struct drm_device *dev);
1348 void intel_update_watermarks(struct drm_crtc *crtc);
1349 void intel_update_sprite_watermarks(struct drm_plane *plane,
1350 struct drm_crtc *crtc,
1351 uint32_t sprite_width,
1352 uint32_t sprite_height,
1354 bool enabled, bool scaled);
1355 void intel_init_pm(struct drm_device *dev);
1356 void intel_pm_setup(struct drm_device *dev);
1357 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1358 void intel_gpu_ips_teardown(void);
1359 void intel_init_gt_powersave(struct drm_device *dev);
1360 void intel_cleanup_gt_powersave(struct drm_device *dev);
1361 void intel_enable_gt_powersave(struct drm_device *dev);
1362 void intel_disable_gt_powersave(struct drm_device *dev);
1363 void intel_suspend_gt_powersave(struct drm_device *dev);
1364 void intel_reset_gt_powersave(struct drm_device *dev);
1365 void gen6_update_ring_freq(struct drm_device *dev);
1366 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1367 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1368 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1369 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1370 struct drm_i915_file_private *file_priv);
1371 void intel_queue_rps_boost_for_request(struct drm_device *dev,
1372 struct drm_i915_gem_request *rq);
1373 void ilk_wm_get_hw_state(struct drm_device *dev);
1374 void skl_wm_get_hw_state(struct drm_device *dev);
1375 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1376 struct skl_ddb_allocation *ddb /* out */);
1380 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
1383 /* intel_sprite.c */
1384 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1385 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1387 int intel_plane_restore(struct drm_plane *plane);
1388 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1389 struct drm_file *file_priv);
1390 bool intel_pipe_update_start(struct intel_crtc *crtc,
1391 uint32_t *start_vbl_count);
1392 void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count);
1393 void intel_post_enable_primary(struct drm_crtc *crtc);
1394 void intel_pre_disable_primary(struct drm_crtc *crtc);
1397 void intel_tv_init(struct drm_device *dev);
1399 /* intel_atomic.c */
1400 int intel_atomic_check(struct drm_device *dev,
1401 struct drm_atomic_state *state);
1402 int intel_atomic_commit(struct drm_device *dev,
1403 struct drm_atomic_state *state,
1405 int intel_connector_atomic_get_property(struct drm_connector *connector,
1406 const struct drm_connector_state *state,
1407 struct drm_property *property,
1409 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1410 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1411 struct drm_crtc_state *state);
1412 static inline struct intel_crtc_state *
1413 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1414 struct intel_crtc *crtc)
1416 struct drm_crtc_state *crtc_state;
1417 crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1418 if (IS_ERR(crtc_state))
1419 return ERR_CAST(crtc_state);
1421 return to_intel_crtc_state(crtc_state);
1423 int intel_atomic_setup_scalers(struct drm_device *dev,
1424 struct intel_crtc *intel_crtc,
1425 struct intel_crtc_state *crtc_state);
1427 /* intel_atomic_plane.c */
1428 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1429 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1430 void intel_plane_destroy_state(struct drm_plane *plane,
1431 struct drm_plane_state *state);
1432 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1434 #endif /* __INTEL_DRV_H__ */