drivers/gpu/drm/i915/intel_hdmi.c

   1 /*
   2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2009 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Jesse Barnes <jesse.barnes@intel.com>
  27  */
  28
  29 #include <linux/i2c.h>
  30 #include <linux/slab.h>
  31 #include <linux/delay.h>
  32 #include "drmP.h"
  33 #include "drm.h"
  34 #include "drm_crtc.h"
  35 #include "drm_edid.h"
  36 #include "intel_drv.h"
  37 #include "i915_drm.h"
  38 #include "i915_drv.h"
  39
  40 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  41 {
  42         return container_of(encoder, struct intel_hdmi, base.base);
  43 }
  44
  45 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  46 {
  47         return container_of(intel_attached_encoder(connector),
  48                             struct intel_hdmi, base);
  49 }
  50
  51 void intel_dip_infoframe_csum(struct dip_infoframe *frame)
  52 {
  53         uint8_t *data = (uint8_t *)frame;
  54         uint8_t sum = 0;
  55         unsigned i;
  56
  57         frame->checksum = 0;
  58         frame->ecc = 0;
  59
  60         for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++)
  61                 sum += data[i];
  62
  63         frame->checksum = 0x100 - sum;
  64 }
  65
  66 static u32 g4x_infoframe_index(struct dip_infoframe *frame)
  67 {
  68         switch (frame->type) {
  69         case DIP_TYPE_AVI:
  70                 return VIDEO_DIP_SELECT_AVI;
  71         case DIP_TYPE_SPD:
  72                 return VIDEO_DIP_SELECT_SPD;
  73         default:
  74                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
  75                 return 0;
  76         }
  77 }
  78
  79 static u32 g4x_infoframe_enable(struct dip_infoframe *frame)
  80 {
  81         switch (frame->type) {
  82         case DIP_TYPE_AVI:
  83                 return VIDEO_DIP_ENABLE_AVI;
  84         case DIP_TYPE_SPD:
  85                 return VIDEO_DIP_ENABLE_SPD;
  86         default:
  87                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
  88                 return 0;
  89         }
  90 }
  91
  92 static void g4x_write_infoframe(struct drm_encoder *encoder,
  93                                 struct dip_infoframe *frame)
  94 {
  95         uint32_t *data = (uint32_t *)frame;
  96         struct drm_device *dev = encoder->dev;
  97         struct drm_i915_private *dev_priv = dev->dev_private;
  98         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  99         u32 val = I915_READ(VIDEO_DIP_CTL);
 100         unsigned i, len = DIP_HEADER_SIZE + frame->len;
 101
 102         val &= ~VIDEO_DIP_PORT_MASK;
 103         if (intel_hdmi->sdvox_reg == SDVOB)
 104                 val |= VIDEO_DIP_PORT_B;
 105         else if (intel_hdmi->sdvox_reg == SDVOC)
 106                 val |= VIDEO_DIP_PORT_C;
 107         else
 108                 return;
 109
 110         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 111         val |= g4x_infoframe_index(frame);
 112
 113         val &= ~g4x_infoframe_enable(frame);
 114         val |= VIDEO_DIP_ENABLE;
 115
 116         I915_WRITE(VIDEO_DIP_CTL, val);
 117
 118         for (i = 0; i < len; i += 4) {
 119                 I915_WRITE(VIDEO_DIP_DATA, *data);
 120                 data++;
 121         }
 122
 123         val |= g4x_infoframe_enable(frame);
 124         val &= ~VIDEO_DIP_FREQ_MASK;
 125         val |= VIDEO_DIP_FREQ_VSYNC;
 126
 127         I915_WRITE(VIDEO_DIP_CTL, val);
 128 }
 129
 130 static void ibx_write_infoframe(struct drm_encoder *encoder,
 131                                 struct dip_infoframe *frame)
 132 {
 133         uint32_t *data = (uint32_t *)frame;
 134         struct drm_device *dev = encoder->dev;
 135         struct drm_i915_private *dev_priv = dev->dev_private;
 136         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 137         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 138         int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 139         unsigned i, len = DIP_HEADER_SIZE + frame->len;
 140         u32 val = I915_READ(reg);
 141
 142         val &= ~VIDEO_DIP_PORT_MASK;
 143         switch (intel_hdmi->sdvox_reg) {
 144         case HDMIB:
 145                 val |= VIDEO_DIP_PORT_B;
 146                 break;
 147         case HDMIC:
 148                 val |= VIDEO_DIP_PORT_C;
 149                 break;
 150         case HDMID:
 151                 val |= VIDEO_DIP_PORT_D;
 152                 break;
 153         default:
 154                 return;
 155         }
 156
 157         intel_wait_for_vblank(dev, intel_crtc->pipe);
 158
 159         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 160         val |= g4x_infoframe_index(frame);
 161
 162         val &= ~g4x_infoframe_enable(frame);
 163         val |= VIDEO_DIP_ENABLE;
 164
 165         I915_WRITE(reg, val);
 166
 167         for (i = 0; i < len; i += 4) {
 168                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 169                 data++;
 170         }
 171
 172         val |= g4x_infoframe_enable(frame);
 173         val &= ~VIDEO_DIP_FREQ_MASK;
 174         val |= VIDEO_DIP_FREQ_VSYNC;
 175
 176         I915_WRITE(reg, val);
 177 }
 178
 179 static void cpt_write_infoframe(struct drm_encoder *encoder,
 180                                 struct dip_infoframe *frame)
 181 {
 182         uint32_t *data = (uint32_t *)frame;
 183         struct drm_device *dev = encoder->dev;
 184         struct drm_i915_private *dev_priv = dev->dev_private;
 185         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 186         int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 187         unsigned i, len = DIP_HEADER_SIZE + frame->len;
 188         u32 val = I915_READ(reg);
 189
 190         intel_wait_for_vblank(dev, intel_crtc->pipe);
 191
 192         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 193         val |= g4x_infoframe_index(frame);
 194
 195         /* The DIP control register spec says that we need to update the AVI
 196          * infoframe without clearing its enable bit */
 197         if (frame->type == DIP_TYPE_AVI)
 198                 val |= VIDEO_DIP_ENABLE_AVI;
 199         else
 200                 val &= ~g4x_infoframe_enable(frame);
 201
 202         val |= VIDEO_DIP_ENABLE;
 203
 204         I915_WRITE(reg, val);
 205
 206         for (i = 0; i < len; i += 4) {
 207                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 208                 data++;
 209         }
 210
 211         val |= g4x_infoframe_enable(frame);
 212         val &= ~VIDEO_DIP_FREQ_MASK;
 213         val |= VIDEO_DIP_FREQ_VSYNC;
 214
 215         I915_WRITE(reg, val);
 216 }
 217
 218 static void vlv_write_infoframe(struct drm_encoder *encoder,
 219                                      struct dip_infoframe *frame)
 220 {
 221         uint32_t *data = (uint32_t *)frame;
 222         struct drm_device *dev = encoder->dev;
 223         struct drm_i915_private *dev_priv = dev->dev_private;
 224         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 225         int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 226         unsigned i, len = DIP_HEADER_SIZE + frame->len;
 227         u32 val = I915_READ(reg);
 228
 229         intel_wait_for_vblank(dev, intel_crtc->pipe);
 230
 231         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 232         val |= g4x_infoframe_index(frame);
 233
 234         val &= ~g4x_infoframe_enable(frame);
 235         val |= VIDEO_DIP_ENABLE;
 236
 237         I915_WRITE(reg, val);
 238
 239         for (i = 0; i < len; i += 4) {
 240                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 241                 data++;
 242         }
 243
 244         val |= g4x_infoframe_enable(frame);
 245         val &= ~VIDEO_DIP_FREQ_MASK;
 246         val |= VIDEO_DIP_FREQ_VSYNC;
 247
 248         I915_WRITE(reg, val);
 249 }
 250
 251 static void hsw_write_infoframe(struct drm_encoder *encoder,
 252                                 struct dip_infoframe *frame)
 253 {
 254         /* Not implemented yet, so avoid doing anything at all.
 255          * This is the placeholder for Paulo Zanoni's infoframe writing patch
 256          */
 257         DRM_DEBUG_DRIVER("Attempting to write infoframe on Haswell, this is not implemented yet.\n");
 258
 259         return;
 260
 261 }
 262
 263 static void intel_set_infoframe(struct drm_encoder *encoder,
 264                                 struct dip_infoframe *frame)
 265 {
 266         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 267
 268         if (!intel_hdmi->has_hdmi_sink)
 269                 return;
 270
 271         intel_dip_infoframe_csum(frame);
 272         intel_hdmi->write_infoframe(encoder, frame);
 273 }
 274
 275 void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
 276                                          struct drm_display_mode *adjusted_mode)
 277 {
 278         struct dip_infoframe avi_if = {
 279                 .type = DIP_TYPE_AVI,
 280                 .ver = DIP_VERSION_AVI,
 281                 .len = DIP_LEN_AVI,
 282         };
 283
 284         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 285                 avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2;
 286
 287         intel_set_infoframe(encoder, &avi_if);
 288 }
 289
 290 void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 291 {
 292         struct dip_infoframe spd_if;
 293
 294         memset(&spd_if, 0, sizeof(spd_if));
 295         spd_if.type = DIP_TYPE_SPD;
 296         spd_if.ver = DIP_VERSION_SPD;
 297         spd_if.len = DIP_LEN_SPD;
 298         strcpy(spd_if.body.spd.vn, "Intel");
 299         strcpy(spd_if.body.spd.pd, "Integrated gfx");
 300         spd_if.body.spd.sdi = DIP_SPD_PC;
 301
 302         intel_set_infoframe(encoder, &spd_if);
 303 }
 304
 305 static void intel_hdmi_mode_set(struct drm_encoder *encoder,
 306                                 struct drm_display_mode *mode,
 307                                 struct drm_display_mode *adjusted_mode)
 308 {
 309         struct drm_device *dev = encoder->dev;
 310         struct drm_i915_private *dev_priv = dev->dev_private;
 311         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 312         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 313         u32 sdvox;
 314
 315         sdvox = SDVO_ENCODING_HDMI | SDVO_BORDER_ENABLE;
 316         if (!HAS_PCH_SPLIT(dev))
 317                 sdvox |= intel_hdmi->color_range;
 318         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 319                 sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
 320         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 321                 sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
 322
 323         if (intel_crtc->bpp > 24)
 324                 sdvox |= COLOR_FORMAT_12bpc;
 325         else
 326                 sdvox |= COLOR_FORMAT_8bpc;
 327
 328         /* Required on CPT */
 329         if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
 330                 sdvox |= HDMI_MODE_SELECT;
 331
 332         if (intel_hdmi->has_audio) {
 333                 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
 334                                  pipe_name(intel_crtc->pipe));
 335                 sdvox |= SDVO_AUDIO_ENABLE;
 336                 sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC;
 337                 intel_write_eld(encoder, adjusted_mode);
 338         }
 339
 340         if (HAS_PCH_CPT(dev))
 341                 sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe);
 342         else if (intel_crtc->pipe == 1)
 343                 sdvox |= SDVO_PIPE_B_SELECT;
 344
 345         I915_WRITE(intel_hdmi->sdvox_reg, sdvox);
 346         POSTING_READ(intel_hdmi->sdvox_reg);
 347
 348         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 349         intel_hdmi_set_spd_infoframe(encoder);
 350 }
 351
 352 static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode)
 353 {
 354         struct drm_device *dev = encoder->dev;
 355         struct drm_i915_private *dev_priv = dev->dev_private;
 356         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 357         u32 temp;
 358         u32 enable_bits = SDVO_ENABLE;
 359
 360         if (intel_hdmi->has_audio)
 361                 enable_bits |= SDVO_AUDIO_ENABLE;
 362
 363         temp = I915_READ(intel_hdmi->sdvox_reg);
 364
 365         /* HW workaround, need to toggle enable bit off and on for 12bpc, but
 366          * we do this anyway which shows more stable in testing.
 367          */
 368         if (HAS_PCH_SPLIT(dev)) {
 369                 I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);
 370                 POSTING_READ(intel_hdmi->sdvox_reg);
 371         }
 372
 373         if (mode != DRM_MODE_DPMS_ON) {
 374                 temp &= ~enable_bits;
 375         } else {
 376                 temp |= enable_bits;
 377         }
 378
 379         I915_WRITE(intel_hdmi->sdvox_reg, temp);
 380         POSTING_READ(intel_hdmi->sdvox_reg);
 381
 382         /* HW workaround, need to write this twice for issue that may result
 383          * in first write getting masked.
 384          */
 385         if (HAS_PCH_SPLIT(dev)) {
 386                 I915_WRITE(intel_hdmi->sdvox_reg, temp);
 387                 POSTING_READ(intel_hdmi->sdvox_reg);
 388         }
 389 }
 390
 391 static int intel_hdmi_mode_valid(struct drm_connector *connector,
 392                                  struct drm_display_mode *mode)
 393 {
 394         if (mode->clock > 165000)
 395                 return MODE_CLOCK_HIGH;
 396         if (mode->clock < 20000)
 397                 return MODE_CLOCK_LOW;
 398
 399         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 400                 return MODE_NO_DBLESCAN;
 401
 402         return MODE_OK;
 403 }
 404
 405 static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
 406                                   struct drm_display_mode *mode,
 407                                   struct drm_display_mode *adjusted_mode)
 408 {
 409         return true;
 410 }
 411
 412 static enum drm_connector_status
 413 intel_hdmi_detect(struct drm_connector *connector, bool force)
 414 {
 415         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 416         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 417         struct edid *edid;
 418         enum drm_connector_status status = connector_status_disconnected;
 419
 420         intel_hdmi->has_hdmi_sink = false;
 421         intel_hdmi->has_audio = false;
 422         edid = drm_get_edid(connector,
 423                             intel_gmbus_get_adapter(dev_priv,
 424                                                     intel_hdmi->ddc_bus));
 425
 426         if (edid) {
 427                 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
 428                         status = connector_status_connected;
 429                         if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
 430                                 intel_hdmi->has_hdmi_sink =
 431                                                 drm_detect_hdmi_monitor(edid);
 432                         intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
 433                 }
 434                 connector->display_info.raw_edid = NULL;
 435                 kfree(edid);
 436         }
 437
 438         if (status == connector_status_connected) {
 439                 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
 440                         intel_hdmi->has_audio =
 441                                 (intel_hdmi->force_audio == HDMI_AUDIO_ON);
 442         }
 443
 444         return status;
 445 }
 446
 447 static int intel_hdmi_get_modes(struct drm_connector *connector)
 448 {
 449         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 450         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 451
 452         /* We should parse the EDID data and find out if it's an HDMI sink so
 453          * we can send audio to it.
 454          */
 455
 456         return intel_ddc_get_modes(connector,
 457                                    intel_gmbus_get_adapter(dev_priv,
 458                                                            intel_hdmi->ddc_bus));
 459 }
 460
 461 static bool
 462 intel_hdmi_detect_audio(struct drm_connector *connector)
 463 {
 464         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 465         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 466         struct edid *edid;
 467         bool has_audio = false;
 468
 469         edid = drm_get_edid(connector,
 470                             intel_gmbus_get_adapter(dev_priv,
 471                                                     intel_hdmi->ddc_bus));
 472         if (edid) {
 473                 if (edid->input & DRM_EDID_INPUT_DIGITAL)
 474                         has_audio = drm_detect_monitor_audio(edid);
 475
 476                 connector->display_info.raw_edid = NULL;
 477                 kfree(edid);
 478         }
 479
 480         return has_audio;
 481 }
 482
 483 static int
 484 intel_hdmi_set_property(struct drm_connector *connector,
 485                         struct drm_property *property,
 486                         uint64_t val)
 487 {
 488         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 489         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 490         int ret;
 491
 492         ret = drm_connector_property_set_value(connector, property, val);
 493         if (ret)
 494                 return ret;
 495
 496         if (property == dev_priv->force_audio_property) {
 497                 enum hdmi_force_audio i = val;
 498                 bool has_audio;
 499
 500                 if (i == intel_hdmi->force_audio)
 501                         return 0;
 502
 503                 intel_hdmi->force_audio = i;
 504
 505                 if (i == HDMI_AUDIO_AUTO)
 506                         has_audio = intel_hdmi_detect_audio(connector);
 507                 else
 508                         has_audio = (i == HDMI_AUDIO_ON);
 509
 510                 if (i == HDMI_AUDIO_OFF_DVI)
 511                         intel_hdmi->has_hdmi_sink = 0;
 512
 513                 intel_hdmi->has_audio = has_audio;
 514                 goto done;
 515         }
 516
 517         if (property == dev_priv->broadcast_rgb_property) {
 518                 if (val == !!intel_hdmi->color_range)
 519                         return 0;
 520
 521                 intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
 522                 goto done;
 523         }
 524
 525         return -EINVAL;
 526
 527 done:
 528         if (intel_hdmi->base.base.crtc) {
 529                 struct drm_crtc *crtc = intel_hdmi->base.base.crtc;
 530                 drm_crtc_helper_set_mode(crtc, &crtc->mode,
 531                                          crtc->x, crtc->y,
 532                                          crtc->fb);
 533         }
 534
 535         return 0;
 536 }
 537
 538 static void intel_hdmi_destroy(struct drm_connector *connector)
 539 {
 540         drm_sysfs_connector_remove(connector);
 541         drm_connector_cleanup(connector);
 542         kfree(connector);
 543 }
 544
 545 static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs_hsw = {
 546         .dpms = intel_ddi_dpms,
 547         .mode_fixup = intel_hdmi_mode_fixup,
 548         .prepare = intel_encoder_prepare,
 549         .mode_set = intel_ddi_mode_set,
 550         .commit = intel_encoder_commit,
 551 };
 552
 553 static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = {
 554         .dpms = intel_hdmi_dpms,
 555         .mode_fixup = intel_hdmi_mode_fixup,
 556         .prepare = intel_encoder_prepare,
 557         .mode_set = intel_hdmi_mode_set,
 558         .commit = intel_encoder_commit,
 559 };
 560
 561 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
 562         .dpms = drm_helper_connector_dpms,
 563         .detect = intel_hdmi_detect,
 564         .fill_modes = drm_helper_probe_single_connector_modes,
 565         .set_property = intel_hdmi_set_property,
 566         .destroy = intel_hdmi_destroy,
 567 };
 568
 569 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
 570         .get_modes = intel_hdmi_get_modes,
 571         .mode_valid = intel_hdmi_mode_valid,
 572         .best_encoder = intel_best_encoder,
 573 };
 574
 575 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
 576         .destroy = intel_encoder_destroy,
 577 };
 578
 579 static void
 580 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
 581 {
 582         intel_attach_force_audio_property(connector);
 583         intel_attach_broadcast_rgb_property(connector);
 584 }
 585
 586 void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
 587 {
 588         struct drm_i915_private *dev_priv = dev->dev_private;
 589         struct drm_connector *connector;
 590         struct intel_encoder *intel_encoder;
 591         struct intel_connector *intel_connector;
 592         struct intel_hdmi *intel_hdmi;
 593         int i;
 594
 595         intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL);
 596         if (!intel_hdmi)
 597                 return;
 598
 599         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
 600         if (!intel_connector) {
 601                 kfree(intel_hdmi);
 602                 return;
 603         }
 604
 605         intel_encoder = &intel_hdmi->base;
 606         drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
 607                          DRM_MODE_ENCODER_TMDS);
 608
 609         connector = &intel_connector->base;
 610         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
 611                            DRM_MODE_CONNECTOR_HDMIA);
 612         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
 613
 614         intel_encoder->type = INTEL_OUTPUT_HDMI;
 615
 616         connector->polled = DRM_CONNECTOR_POLL_HPD;
 617         connector->interlace_allowed = 1;
 618         connector->doublescan_allowed = 0;
 619         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
 620
 621         /* Set up the DDC bus. */
 622         if (sdvox_reg == SDVOB) {
 623                 intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT);
 624                 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
 625                 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
 626         } else if (sdvox_reg == SDVOC) {
 627                 intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT);
 628                 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
 629                 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
 630         } else if (sdvox_reg == HDMIB) {
 631                 intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT);
 632                 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
 633                 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
 634         } else if (sdvox_reg == HDMIC) {
 635                 intel_encoder->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT);
 636                 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
 637                 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
 638         } else if (sdvox_reg == HDMID) {
 639                 intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT);
 640                 intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
 641                 dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
 642         } else if (sdvox_reg == DDI_BUF_CTL(PORT_B)) {
 643                 DRM_DEBUG_DRIVER("LPT: detected output on DDI B\n");
 644                 intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT);
 645                 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
 646                 intel_hdmi->ddi_port = PORT_B;
 647                 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
 648         } else if (sdvox_reg == DDI_BUF_CTL(PORT_C)) {
 649                 DRM_DEBUG_DRIVER("LPT: detected output on DDI C\n");
 650                 intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT);
 651                 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
 652                 intel_hdmi->ddi_port = PORT_C;
 653                 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
 654         } else if (sdvox_reg == DDI_BUF_CTL(PORT_D)) {
 655                 DRM_DEBUG_DRIVER("LPT: detected output on DDI D\n");
 656                 intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT);
 657                 intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
 658                 intel_hdmi->ddi_port = PORT_D;
 659                 dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
 660         } else {
 661                 /* If we got an unknown sdvox_reg, things are pretty much broken
 662                  * in a way that we should let the kernel know about it */
 663                 BUG();
 664         }
 665
 666         intel_hdmi->sdvox_reg = sdvox_reg;
 667
 668         if (!HAS_PCH_SPLIT(dev)) {
 669                 intel_hdmi->write_infoframe = g4x_write_infoframe;
 670                 I915_WRITE(VIDEO_DIP_CTL, 0);
 671         } else if (IS_VALLEYVIEW(dev)) {
 672                 intel_hdmi->write_infoframe = vlv_write_infoframe;
 673                 for_each_pipe(i)
 674                         I915_WRITE(VLV_TVIDEO_DIP_CTL(i), 0);
 675         } else if (IS_HASWELL(dev)) {
 676                 /* FIXME: Haswell has a new set of DIP frame registers, but we are
 677                  * just doing the minimal required for HDMI to work at this stage.
 678                  */
 679                 intel_hdmi->write_infoframe = hsw_write_infoframe;
 680                 for_each_pipe(i)
 681                         I915_WRITE(HSW_TVIDEO_DIP_CTL(i), 0);
 682         } else if (HAS_PCH_IBX(dev)) {
 683                 intel_hdmi->write_infoframe = ibx_write_infoframe;
 684                 for_each_pipe(i)
 685                         I915_WRITE(TVIDEO_DIP_CTL(i), 0);
 686         } else {
 687                 intel_hdmi->write_infoframe = cpt_write_infoframe;
 688                 for_each_pipe(i)
 689                         I915_WRITE(TVIDEO_DIP_CTL(i), 0);
 690         }
 691
 692         if (IS_HASWELL(dev))
 693                 drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs_hsw);
 694         else
 695                 drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs);
 696
 697         intel_hdmi_add_properties(intel_hdmi, connector);
 698
 699         intel_connector_attach_encoder(intel_connector, intel_encoder);
 700         drm_sysfs_connector_add(connector);
 701
 702         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
 703          * 0xd.  Failure to do so will result in spurious interrupts being
 704          * generated on the port when a cable is not attached.
 705          */
 706         if (IS_G4X(dev) && !IS_GM45(dev)) {
 707                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
 708                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
 709         }
 710 }