2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
29 #include <linux/i2c.h>
30 #include <linux/slab.h>
31 #include <linux/delay.h>
32 #include <linux/hdmi.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
40 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
42 return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
46 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
48 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
49 struct drm_i915_private *dev_priv = dev->dev_private;
50 uint32_t enabled_bits;
52 enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
54 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
55 "HDMI port enabled, expecting disabled\n");
58 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
60 struct intel_digital_port *intel_dig_port =
61 container_of(encoder, struct intel_digital_port, base.base);
62 return &intel_dig_port->hdmi;
65 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
67 return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
70 static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
73 case HDMI_INFOFRAME_TYPE_AVI:
74 return VIDEO_DIP_SELECT_AVI;
75 case HDMI_INFOFRAME_TYPE_SPD:
76 return VIDEO_DIP_SELECT_SPD;
77 case HDMI_INFOFRAME_TYPE_VENDOR:
78 return VIDEO_DIP_SELECT_VENDOR;
80 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
85 static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
88 case HDMI_INFOFRAME_TYPE_AVI:
89 return VIDEO_DIP_ENABLE_AVI;
90 case HDMI_INFOFRAME_TYPE_SPD:
91 return VIDEO_DIP_ENABLE_SPD;
92 case HDMI_INFOFRAME_TYPE_VENDOR:
93 return VIDEO_DIP_ENABLE_VENDOR;
95 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
100 static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
103 case HDMI_INFOFRAME_TYPE_AVI:
104 return VIDEO_DIP_ENABLE_AVI_HSW;
105 case HDMI_INFOFRAME_TYPE_SPD:
106 return VIDEO_DIP_ENABLE_SPD_HSW;
107 case HDMI_INFOFRAME_TYPE_VENDOR:
108 return VIDEO_DIP_ENABLE_VS_HSW;
110 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
115 static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type,
116 enum transcoder cpu_transcoder,
117 struct drm_i915_private *dev_priv)
120 case HDMI_INFOFRAME_TYPE_AVI:
121 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder);
122 case HDMI_INFOFRAME_TYPE_SPD:
123 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder);
124 case HDMI_INFOFRAME_TYPE_VENDOR:
125 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder);
127 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
132 static void g4x_write_infoframe(struct drm_encoder *encoder,
133 enum hdmi_infoframe_type type,
134 const void *frame, ssize_t len)
136 const uint32_t *data = frame;
137 struct drm_device *dev = encoder->dev;
138 struct drm_i915_private *dev_priv = dev->dev_private;
139 u32 val = I915_READ(VIDEO_DIP_CTL);
142 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
144 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
145 val |= g4x_infoframe_index(type);
147 val &= ~g4x_infoframe_enable(type);
149 I915_WRITE(VIDEO_DIP_CTL, val);
152 for (i = 0; i < len; i += 4) {
153 I915_WRITE(VIDEO_DIP_DATA, *data);
156 /* Write every possible data byte to force correct ECC calculation. */
157 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
158 I915_WRITE(VIDEO_DIP_DATA, 0);
161 val |= g4x_infoframe_enable(type);
162 val &= ~VIDEO_DIP_FREQ_MASK;
163 val |= VIDEO_DIP_FREQ_VSYNC;
165 I915_WRITE(VIDEO_DIP_CTL, val);
166 POSTING_READ(VIDEO_DIP_CTL);
169 static void ibx_write_infoframe(struct drm_encoder *encoder,
170 enum hdmi_infoframe_type type,
171 const void *frame, ssize_t len)
173 const uint32_t *data = frame;
174 struct drm_device *dev = encoder->dev;
175 struct drm_i915_private *dev_priv = dev->dev_private;
176 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
177 int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
178 u32 val = I915_READ(reg);
180 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
182 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
183 val |= g4x_infoframe_index(type);
185 val &= ~g4x_infoframe_enable(type);
187 I915_WRITE(reg, val);
190 for (i = 0; i < len; i += 4) {
191 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
194 /* Write every possible data byte to force correct ECC calculation. */
195 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
196 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
199 val |= g4x_infoframe_enable(type);
200 val &= ~VIDEO_DIP_FREQ_MASK;
201 val |= VIDEO_DIP_FREQ_VSYNC;
203 I915_WRITE(reg, val);
207 static void cpt_write_infoframe(struct drm_encoder *encoder,
208 enum hdmi_infoframe_type type,
209 const void *frame, ssize_t len)
211 const uint32_t *data = frame;
212 struct drm_device *dev = encoder->dev;
213 struct drm_i915_private *dev_priv = dev->dev_private;
214 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
215 int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
216 u32 val = I915_READ(reg);
218 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
220 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
221 val |= g4x_infoframe_index(type);
223 /* The DIP control register spec says that we need to update the AVI
224 * infoframe without clearing its enable bit */
225 if (type != HDMI_INFOFRAME_TYPE_AVI)
226 val &= ~g4x_infoframe_enable(type);
228 I915_WRITE(reg, val);
231 for (i = 0; i < len; i += 4) {
232 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
235 /* Write every possible data byte to force correct ECC calculation. */
236 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
237 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
240 val |= g4x_infoframe_enable(type);
241 val &= ~VIDEO_DIP_FREQ_MASK;
242 val |= VIDEO_DIP_FREQ_VSYNC;
244 I915_WRITE(reg, val);
248 static void vlv_write_infoframe(struct drm_encoder *encoder,
249 enum hdmi_infoframe_type type,
250 const void *frame, ssize_t len)
252 const uint32_t *data = frame;
253 struct drm_device *dev = encoder->dev;
254 struct drm_i915_private *dev_priv = dev->dev_private;
255 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
256 int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
257 u32 val = I915_READ(reg);
259 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
261 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
262 val |= g4x_infoframe_index(type);
264 val &= ~g4x_infoframe_enable(type);
266 I915_WRITE(reg, val);
269 for (i = 0; i < len; i += 4) {
270 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
273 /* Write every possible data byte to force correct ECC calculation. */
274 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
275 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
278 val |= g4x_infoframe_enable(type);
279 val &= ~VIDEO_DIP_FREQ_MASK;
280 val |= VIDEO_DIP_FREQ_VSYNC;
282 I915_WRITE(reg, val);
286 static void hsw_write_infoframe(struct drm_encoder *encoder,
287 enum hdmi_infoframe_type type,
288 const void *frame, ssize_t len)
290 const uint32_t *data = frame;
291 struct drm_device *dev = encoder->dev;
292 struct drm_i915_private *dev_priv = dev->dev_private;
293 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
294 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
297 u32 val = I915_READ(ctl_reg);
299 data_reg = hsw_infoframe_data_reg(type,
300 intel_crtc->config.cpu_transcoder,
305 val &= ~hsw_infoframe_enable(type);
306 I915_WRITE(ctl_reg, val);
309 for (i = 0; i < len; i += 4) {
310 I915_WRITE(data_reg + i, *data);
313 /* Write every possible data byte to force correct ECC calculation. */
314 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
315 I915_WRITE(data_reg + i, 0);
318 val |= hsw_infoframe_enable(type);
319 I915_WRITE(ctl_reg, val);
320 POSTING_READ(ctl_reg);
324 * The data we write to the DIP data buffer registers is 1 byte bigger than the
325 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
326 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
327 * used for both technologies.
329 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
330 * DW1: DB3 | DB2 | DB1 | DB0
331 * DW2: DB7 | DB6 | DB5 | DB4
334 * (HB is Header Byte, DB is Data Byte)
336 * The hdmi pack() functions don't know about that hardware specific hole so we
337 * trick them by giving an offset into the buffer and moving back the header
340 static void intel_write_infoframe(struct drm_encoder *encoder,
341 union hdmi_infoframe *frame)
343 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
344 uint8_t buffer[VIDEO_DIP_DATA_SIZE];
347 /* see comment above for the reason for this offset */
348 len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
352 /* Insert the 'hole' (see big comment above) at position 3 */
353 buffer[0] = buffer[1];
354 buffer[1] = buffer[2];
355 buffer[2] = buffer[3];
359 intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);
362 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
363 struct drm_display_mode *adjusted_mode)
365 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
366 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
367 union hdmi_infoframe frame;
370 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
373 DRM_ERROR("couldn't fill AVI infoframe\n");
377 if (intel_hdmi->rgb_quant_range_selectable) {
378 if (intel_crtc->config.limited_color_range)
379 frame.avi.quantization_range =
380 HDMI_QUANTIZATION_RANGE_LIMITED;
382 frame.avi.quantization_range =
383 HDMI_QUANTIZATION_RANGE_FULL;
386 intel_write_infoframe(encoder, &frame);
389 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
391 union hdmi_infoframe frame;
394 ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
396 DRM_ERROR("couldn't fill SPD infoframe\n");
400 frame.spd.sdi = HDMI_SPD_SDI_PC;
402 intel_write_infoframe(encoder, &frame);
406 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
407 struct drm_display_mode *adjusted_mode)
409 union hdmi_infoframe frame;
412 ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
417 intel_write_infoframe(encoder, &frame);
420 static void g4x_set_infoframes(struct drm_encoder *encoder,
422 struct drm_display_mode *adjusted_mode)
424 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
425 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
426 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
427 u32 reg = VIDEO_DIP_CTL;
428 u32 val = I915_READ(reg);
429 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
431 assert_hdmi_port_disabled(intel_hdmi);
433 /* If the registers were not initialized yet, they might be zeroes,
434 * which means we're selecting the AVI DIP and we're setting its
435 * frequency to once. This seems to really confuse the HW and make
436 * things stop working (the register spec says the AVI always needs to
437 * be sent every VSync). So here we avoid writing to the register more
438 * than we need and also explicitly select the AVI DIP and explicitly
439 * set its frequency to every VSync. Avoiding to write it twice seems to
440 * be enough to solve the problem, but being defensive shouldn't hurt us
442 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
445 if (!(val & VIDEO_DIP_ENABLE))
447 val &= ~VIDEO_DIP_ENABLE;
448 I915_WRITE(reg, val);
453 if (port != (val & VIDEO_DIP_PORT_MASK)) {
454 if (val & VIDEO_DIP_ENABLE) {
455 val &= ~VIDEO_DIP_ENABLE;
456 I915_WRITE(reg, val);
459 val &= ~VIDEO_DIP_PORT_MASK;
463 val |= VIDEO_DIP_ENABLE;
464 val &= ~VIDEO_DIP_ENABLE_VENDOR;
466 I915_WRITE(reg, val);
469 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
470 intel_hdmi_set_spd_infoframe(encoder);
471 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
474 static void ibx_set_infoframes(struct drm_encoder *encoder,
476 struct drm_display_mode *adjusted_mode)
478 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
479 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
480 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
481 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
482 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
483 u32 val = I915_READ(reg);
484 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
486 assert_hdmi_port_disabled(intel_hdmi);
488 /* See the big comment in g4x_set_infoframes() */
489 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
492 if (!(val & VIDEO_DIP_ENABLE))
494 val &= ~VIDEO_DIP_ENABLE;
495 I915_WRITE(reg, val);
500 if (port != (val & VIDEO_DIP_PORT_MASK)) {
501 if (val & VIDEO_DIP_ENABLE) {
502 val &= ~VIDEO_DIP_ENABLE;
503 I915_WRITE(reg, val);
506 val &= ~VIDEO_DIP_PORT_MASK;
510 val |= VIDEO_DIP_ENABLE;
511 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
512 VIDEO_DIP_ENABLE_GCP);
514 I915_WRITE(reg, val);
517 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
518 intel_hdmi_set_spd_infoframe(encoder);
519 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
522 static void cpt_set_infoframes(struct drm_encoder *encoder,
524 struct drm_display_mode *adjusted_mode)
526 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
527 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
528 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
529 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
530 u32 val = I915_READ(reg);
532 assert_hdmi_port_disabled(intel_hdmi);
534 /* See the big comment in g4x_set_infoframes() */
535 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
538 if (!(val & VIDEO_DIP_ENABLE))
540 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI);
541 I915_WRITE(reg, val);
546 /* Set both together, unset both together: see the spec. */
547 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
548 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
549 VIDEO_DIP_ENABLE_GCP);
551 I915_WRITE(reg, val);
554 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
555 intel_hdmi_set_spd_infoframe(encoder);
556 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
559 static void vlv_set_infoframes(struct drm_encoder *encoder,
561 struct drm_display_mode *adjusted_mode)
563 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
564 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
565 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
566 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
567 u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
568 u32 val = I915_READ(reg);
569 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
571 assert_hdmi_port_disabled(intel_hdmi);
573 /* See the big comment in g4x_set_infoframes() */
574 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
577 if (!(val & VIDEO_DIP_ENABLE))
579 val &= ~VIDEO_DIP_ENABLE;
580 I915_WRITE(reg, val);
585 if (port != (val & VIDEO_DIP_PORT_MASK)) {
586 if (val & VIDEO_DIP_ENABLE) {
587 val &= ~VIDEO_DIP_ENABLE;
588 I915_WRITE(reg, val);
591 val &= ~VIDEO_DIP_PORT_MASK;
595 val |= VIDEO_DIP_ENABLE;
596 val &= ~(VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_ENABLE_VENDOR |
597 VIDEO_DIP_ENABLE_GAMUT | VIDEO_DIP_ENABLE_GCP);
599 I915_WRITE(reg, val);
602 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
603 intel_hdmi_set_spd_infoframe(encoder);
604 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
607 static void hsw_set_infoframes(struct drm_encoder *encoder,
609 struct drm_display_mode *adjusted_mode)
611 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
612 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
613 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
614 u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
615 u32 val = I915_READ(reg);
617 assert_hdmi_port_disabled(intel_hdmi);
625 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
626 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW);
628 I915_WRITE(reg, val);
631 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
632 intel_hdmi_set_spd_infoframe(encoder);
633 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
636 static void intel_hdmi_prepare(struct intel_encoder *encoder)
638 struct drm_device *dev = encoder->base.dev;
639 struct drm_i915_private *dev_priv = dev->dev_private;
640 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
641 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
642 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
645 hdmi_val = SDVO_ENCODING_HDMI;
646 if (!HAS_PCH_SPLIT(dev))
647 hdmi_val |= intel_hdmi->color_range;
648 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
649 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
650 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
651 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
653 if (crtc->config.pipe_bpp > 24)
654 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
656 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
658 if (crtc->config.has_hdmi_sink)
659 hdmi_val |= HDMI_MODE_SELECT_HDMI;
661 if (crtc->config.has_audio) {
662 WARN_ON(!crtc->config.has_hdmi_sink);
663 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
664 pipe_name(crtc->pipe));
665 hdmi_val |= SDVO_AUDIO_ENABLE;
666 intel_write_eld(&encoder->base, adjusted_mode);
669 if (HAS_PCH_CPT(dev))
670 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
671 else if (IS_CHERRYVIEW(dev))
672 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
674 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
676 I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
677 POSTING_READ(intel_hdmi->hdmi_reg);
680 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
683 struct drm_device *dev = encoder->base.dev;
684 struct drm_i915_private *dev_priv = dev->dev_private;
685 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
686 enum intel_display_power_domain power_domain;
689 power_domain = intel_display_port_power_domain(encoder);
690 if (!intel_display_power_enabled(dev_priv, power_domain))
693 tmp = I915_READ(intel_hdmi->hdmi_reg);
695 if (!(tmp & SDVO_ENABLE))
698 if (HAS_PCH_CPT(dev))
699 *pipe = PORT_TO_PIPE_CPT(tmp);
700 else if (IS_CHERRYVIEW(dev))
701 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
703 *pipe = PORT_TO_PIPE(tmp);
708 static void intel_hdmi_get_config(struct intel_encoder *encoder,
709 struct intel_crtc_config *pipe_config)
711 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
712 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
716 tmp = I915_READ(intel_hdmi->hdmi_reg);
718 if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
719 flags |= DRM_MODE_FLAG_PHSYNC;
721 flags |= DRM_MODE_FLAG_NHSYNC;
723 if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
724 flags |= DRM_MODE_FLAG_PVSYNC;
726 flags |= DRM_MODE_FLAG_NVSYNC;
728 if (tmp & HDMI_MODE_SELECT_HDMI)
729 pipe_config->has_hdmi_sink = true;
731 if (tmp & HDMI_MODE_SELECT_HDMI)
732 pipe_config->has_audio = true;
734 pipe_config->adjusted_mode.flags |= flags;
736 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
737 dotclock = pipe_config->port_clock * 2 / 3;
739 dotclock = pipe_config->port_clock;
741 if (HAS_PCH_SPLIT(dev_priv->dev))
742 ironlake_check_encoder_dotclock(pipe_config, dotclock);
744 pipe_config->adjusted_mode.crtc_clock = dotclock;
747 static void intel_enable_hdmi(struct intel_encoder *encoder)
749 struct drm_device *dev = encoder->base.dev;
750 struct drm_i915_private *dev_priv = dev->dev_private;
751 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
752 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
754 u32 enable_bits = SDVO_ENABLE;
756 if (intel_crtc->config.has_audio)
757 enable_bits |= SDVO_AUDIO_ENABLE;
759 temp = I915_READ(intel_hdmi->hdmi_reg);
761 /* HW workaround for IBX, we need to move the port to transcoder A
762 * before disabling it, so restore the transcoder select bit here. */
763 if (HAS_PCH_IBX(dev))
764 enable_bits |= SDVO_PIPE_SEL(intel_crtc->pipe);
766 /* HW workaround, need to toggle enable bit off and on for 12bpc, but
767 * we do this anyway which shows more stable in testing.
769 if (HAS_PCH_SPLIT(dev)) {
770 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
771 POSTING_READ(intel_hdmi->hdmi_reg);
776 I915_WRITE(intel_hdmi->hdmi_reg, temp);
777 POSTING_READ(intel_hdmi->hdmi_reg);
779 /* HW workaround, need to write this twice for issue that may result
780 * in first write getting masked.
782 if (HAS_PCH_SPLIT(dev)) {
783 I915_WRITE(intel_hdmi->hdmi_reg, temp);
784 POSTING_READ(intel_hdmi->hdmi_reg);
788 static void vlv_enable_hdmi(struct intel_encoder *encoder)
792 static void intel_disable_hdmi(struct intel_encoder *encoder)
794 struct drm_device *dev = encoder->base.dev;
795 struct drm_i915_private *dev_priv = dev->dev_private;
796 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
798 u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE;
800 temp = I915_READ(intel_hdmi->hdmi_reg);
802 /* HW workaround for IBX, we need to move the port to transcoder A
803 * before disabling it. */
804 if (HAS_PCH_IBX(dev)) {
805 struct drm_crtc *crtc = encoder->base.crtc;
806 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
808 if (temp & SDVO_PIPE_B_SELECT) {
809 temp &= ~SDVO_PIPE_B_SELECT;
810 I915_WRITE(intel_hdmi->hdmi_reg, temp);
811 POSTING_READ(intel_hdmi->hdmi_reg);
813 /* Again we need to write this twice. */
814 I915_WRITE(intel_hdmi->hdmi_reg, temp);
815 POSTING_READ(intel_hdmi->hdmi_reg);
817 /* Transcoder selection bits only update
818 * effectively on vblank. */
820 intel_wait_for_vblank(dev, pipe);
826 /* HW workaround, need to toggle enable bit off and on for 12bpc, but
827 * we do this anyway which shows more stable in testing.
829 if (HAS_PCH_SPLIT(dev)) {
830 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
831 POSTING_READ(intel_hdmi->hdmi_reg);
834 temp &= ~enable_bits;
836 I915_WRITE(intel_hdmi->hdmi_reg, temp);
837 POSTING_READ(intel_hdmi->hdmi_reg);
839 /* HW workaround, need to write this twice for issue that may result
840 * in first write getting masked.
842 if (HAS_PCH_SPLIT(dev)) {
843 I915_WRITE(intel_hdmi->hdmi_reg, temp);
844 POSTING_READ(intel_hdmi->hdmi_reg);
848 static int hdmi_portclock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit)
850 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
852 if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev))
854 else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8)
860 static enum drm_mode_status
861 intel_hdmi_mode_valid(struct drm_connector *connector,
862 struct drm_display_mode *mode)
864 if (mode->clock > hdmi_portclock_limit(intel_attached_hdmi(connector),
866 return MODE_CLOCK_HIGH;
867 if (mode->clock < 20000)
868 return MODE_CLOCK_LOW;
870 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
871 return MODE_NO_DBLESCAN;
876 static bool hdmi_12bpc_possible(struct intel_crtc *crtc)
878 struct drm_device *dev = crtc->base.dev;
879 struct intel_encoder *encoder;
880 int count = 0, count_hdmi = 0;
882 if (!HAS_PCH_SPLIT(dev))
885 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
886 if (encoder->new_crtc != crtc)
889 count_hdmi += encoder->type == INTEL_OUTPUT_HDMI;
894 * HDMI 12bpc affects the clocks, so it's only possible
895 * when not cloning with other encoder types.
897 return count_hdmi > 0 && count_hdmi == count;
900 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
901 struct intel_crtc_config *pipe_config)
903 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
904 struct drm_device *dev = encoder->base.dev;
905 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
906 int clock_12bpc = pipe_config->adjusted_mode.crtc_clock * 3 / 2;
907 int portclock_limit = hdmi_portclock_limit(intel_hdmi, false);
910 pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink;
912 if (intel_hdmi->color_range_auto) {
913 /* See CEA-861-E - 5.1 Default Encoding Parameters */
914 if (pipe_config->has_hdmi_sink &&
915 drm_match_cea_mode(adjusted_mode) > 1)
916 intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
918 intel_hdmi->color_range = 0;
921 if (intel_hdmi->color_range)
922 pipe_config->limited_color_range = true;
924 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
925 pipe_config->has_pch_encoder = true;
927 if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio)
928 pipe_config->has_audio = true;
931 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
932 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
933 * outputs. We also need to check that the higher clock still fits
936 if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink &&
937 clock_12bpc <= portclock_limit &&
938 hdmi_12bpc_possible(encoder->new_crtc)) {
939 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
942 /* Need to adjust the port link by 1.5x for 12bpc. */
943 pipe_config->port_clock = clock_12bpc;
945 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
949 if (!pipe_config->bw_constrained) {
950 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
951 pipe_config->pipe_bpp = desired_bpp;
954 if (adjusted_mode->crtc_clock > portclock_limit) {
955 DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n");
962 static enum drm_connector_status
963 intel_hdmi_detect(struct drm_connector *connector, bool force)
965 struct drm_device *dev = connector->dev;
966 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
967 struct intel_digital_port *intel_dig_port =
968 hdmi_to_dig_port(intel_hdmi);
969 struct intel_encoder *intel_encoder = &intel_dig_port->base;
970 struct drm_i915_private *dev_priv = dev->dev_private;
972 enum intel_display_power_domain power_domain;
973 enum drm_connector_status status = connector_status_disconnected;
975 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
976 connector->base.id, drm_get_connector_name(connector));
978 power_domain = intel_display_port_power_domain(intel_encoder);
979 intel_display_power_get(dev_priv, power_domain);
981 intel_hdmi->has_hdmi_sink = false;
982 intel_hdmi->has_audio = false;
983 intel_hdmi->rgb_quant_range_selectable = false;
984 edid = drm_get_edid(connector,
985 intel_gmbus_get_adapter(dev_priv,
986 intel_hdmi->ddc_bus));
989 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
990 status = connector_status_connected;
991 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
992 intel_hdmi->has_hdmi_sink =
993 drm_detect_hdmi_monitor(edid);
994 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
995 intel_hdmi->rgb_quant_range_selectable =
996 drm_rgb_quant_range_selectable(edid);
1001 if (status == connector_status_connected) {
1002 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
1003 intel_hdmi->has_audio =
1004 (intel_hdmi->force_audio == HDMI_AUDIO_ON);
1005 intel_encoder->type = INTEL_OUTPUT_HDMI;
1008 intel_display_power_put(dev_priv, power_domain);
1013 static int intel_hdmi_get_modes(struct drm_connector *connector)
1015 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
1016 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
1017 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1018 enum intel_display_power_domain power_domain;
1021 /* We should parse the EDID data and find out if it's an HDMI sink so
1022 * we can send audio to it.
1025 power_domain = intel_display_port_power_domain(intel_encoder);
1026 intel_display_power_get(dev_priv, power_domain);
1028 ret = intel_ddc_get_modes(connector,
1029 intel_gmbus_get_adapter(dev_priv,
1030 intel_hdmi->ddc_bus));
1032 intel_display_power_put(dev_priv, power_domain);
1038 intel_hdmi_detect_audio(struct drm_connector *connector)
1040 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
1041 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
1042 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1043 enum intel_display_power_domain power_domain;
1045 bool has_audio = false;
1047 power_domain = intel_display_port_power_domain(intel_encoder);
1048 intel_display_power_get(dev_priv, power_domain);
1050 edid = drm_get_edid(connector,
1051 intel_gmbus_get_adapter(dev_priv,
1052 intel_hdmi->ddc_bus));
1054 if (edid->input & DRM_EDID_INPUT_DIGITAL)
1055 has_audio = drm_detect_monitor_audio(edid);
1059 intel_display_power_put(dev_priv, power_domain);
1065 intel_hdmi_set_property(struct drm_connector *connector,
1066 struct drm_property *property,
1069 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1070 struct intel_digital_port *intel_dig_port =
1071 hdmi_to_dig_port(intel_hdmi);
1072 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1075 ret = drm_object_property_set_value(&connector->base, property, val);
1079 if (property == dev_priv->force_audio_property) {
1080 enum hdmi_force_audio i = val;
1083 if (i == intel_hdmi->force_audio)
1086 intel_hdmi->force_audio = i;
1088 if (i == HDMI_AUDIO_AUTO)
1089 has_audio = intel_hdmi_detect_audio(connector);
1091 has_audio = (i == HDMI_AUDIO_ON);
1093 if (i == HDMI_AUDIO_OFF_DVI)
1094 intel_hdmi->has_hdmi_sink = 0;
1096 intel_hdmi->has_audio = has_audio;
1100 if (property == dev_priv->broadcast_rgb_property) {
1101 bool old_auto = intel_hdmi->color_range_auto;
1102 uint32_t old_range = intel_hdmi->color_range;
1105 case INTEL_BROADCAST_RGB_AUTO:
1106 intel_hdmi->color_range_auto = true;
1108 case INTEL_BROADCAST_RGB_FULL:
1109 intel_hdmi->color_range_auto = false;
1110 intel_hdmi->color_range = 0;
1112 case INTEL_BROADCAST_RGB_LIMITED:
1113 intel_hdmi->color_range_auto = false;
1114 intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
1120 if (old_auto == intel_hdmi->color_range_auto &&
1121 old_range == intel_hdmi->color_range)
1130 if (intel_dig_port->base.base.crtc)
1131 intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
1136 static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
1138 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1139 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1140 struct drm_display_mode *adjusted_mode =
1141 &intel_crtc->config.adjusted_mode;
1143 intel_hdmi_prepare(encoder);
1145 intel_hdmi->set_infoframes(&encoder->base,
1146 intel_crtc->config.has_hdmi_sink,
1150 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
1152 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1153 struct intel_hdmi *intel_hdmi = &dport->hdmi;
1154 struct drm_device *dev = encoder->base.dev;
1155 struct drm_i915_private *dev_priv = dev->dev_private;
1156 struct intel_crtc *intel_crtc =
1157 to_intel_crtc(encoder->base.crtc);
1158 struct drm_display_mode *adjusted_mode =
1159 &intel_crtc->config.adjusted_mode;
1160 enum dpio_channel port = vlv_dport_to_channel(dport);
1161 int pipe = intel_crtc->pipe;
1164 /* Enable clock channels for this port */
1165 mutex_lock(&dev_priv->dpio_lock);
1166 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1173 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1176 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
1177 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
1178 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
1179 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
1180 vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
1181 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
1182 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1183 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1185 /* Program lane clock */
1186 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1187 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1188 mutex_unlock(&dev_priv->dpio_lock);
1190 intel_hdmi->set_infoframes(&encoder->base,
1191 intel_crtc->config.has_hdmi_sink,
1194 intel_enable_hdmi(encoder);
1196 vlv_wait_port_ready(dev_priv, dport);
1199 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1201 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1202 struct drm_device *dev = encoder->base.dev;
1203 struct drm_i915_private *dev_priv = dev->dev_private;
1204 struct intel_crtc *intel_crtc =
1205 to_intel_crtc(encoder->base.crtc);
1206 enum dpio_channel port = vlv_dport_to_channel(dport);
1207 int pipe = intel_crtc->pipe;
1209 intel_hdmi_prepare(encoder);
1211 /* Program Tx lane resets to default */
1212 mutex_lock(&dev_priv->dpio_lock);
1213 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1214 DPIO_PCS_TX_LANE2_RESET |
1215 DPIO_PCS_TX_LANE1_RESET);
1216 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1217 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1218 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1219 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1220 DPIO_PCS_CLK_SOFT_RESET);
1222 /* Fix up inter-pair skew failure */
1223 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1224 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1225 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1227 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1228 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1229 mutex_unlock(&dev_priv->dpio_lock);
1232 static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
1234 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1235 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1236 struct intel_crtc *intel_crtc =
1237 to_intel_crtc(encoder->base.crtc);
1238 enum dpio_channel port = vlv_dport_to_channel(dport);
1239 int pipe = intel_crtc->pipe;
1241 /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1242 mutex_lock(&dev_priv->dpio_lock);
1243 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
1244 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
1245 mutex_unlock(&dev_priv->dpio_lock);
1248 static void chv_hdmi_post_disable(struct intel_encoder *encoder)
1250 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1251 struct drm_device *dev = encoder->base.dev;
1252 struct drm_i915_private *dev_priv = dev->dev_private;
1253 struct intel_crtc *intel_crtc =
1254 to_intel_crtc(encoder->base.crtc);
1255 enum dpio_channel ch = vlv_dport_to_channel(dport);
1256 enum pipe pipe = intel_crtc->pipe;
1259 mutex_lock(&dev_priv->dpio_lock);
1261 /* Propagate soft reset to data lane reset */
1262 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
1263 val |= CHV_PCS_REQ_SOFTRESET_EN;
1264 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val);
1266 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
1267 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1268 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
1270 mutex_unlock(&dev_priv->dpio_lock);
1273 static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
1275 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1276 struct drm_device *dev = encoder->base.dev;
1277 struct drm_i915_private *dev_priv = dev->dev_private;
1278 struct intel_crtc *intel_crtc =
1279 to_intel_crtc(encoder->base.crtc);
1280 enum dpio_channel ch = vlv_dport_to_channel(dport);
1281 int pipe = intel_crtc->pipe;
1285 mutex_lock(&dev_priv->dpio_lock);
1287 /* Deassert soft data lane reset*/
1288 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
1289 val |= CHV_PCS_REQ_SOFTRESET_EN;
1290 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val);
1292 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
1293 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1294 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
1296 /* Program Tx latency optimal setting */
1297 for (i = 0; i < 4; i++) {
1298 /* Set the latency optimal bit */
1299 data = (i == 1) ? 0x0 : 0x6;
1300 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
1301 data << DPIO_FRC_LATENCY_SHFIT);
1303 /* Set the upar bit */
1304 data = (i == 1) ? 0x0 : 0x1;
1305 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
1306 data << DPIO_UPAR_SHIFT);
1309 /* Data lane stagger programming */
1310 /* FIXME: Fix up value only after power analysis */
1312 /* Clear calc init */
1313 vlv_dpio_write(dev_priv, pipe, CHV_PCS_DW10(ch), 0);
1315 /* FIXME: Program the support xxx V-dB */
1317 val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW4(ch));
1318 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
1319 val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT;
1320 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(ch), val);
1322 val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch));
1323 val &= ~DPIO_SWING_MARGIN_MASK;
1324 val |= 102 << DPIO_SWING_MARGIN_SHIFT;
1325 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch), val);
1327 /* Disable unique transition scale */
1328 val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch));
1329 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
1330 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val);
1332 /* Additional steps for 1200mV-0dB */
1334 val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch));
1336 val |= DPIO_TX_UNIQ_TRANS_SCALE_CH1;
1338 val |= DPIO_TX_UNIQ_TRANS_SCALE_CH0;
1339 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val);
1341 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch),
1342 vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch)) |
1343 (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT));
1345 /* Start swing calculation */
1346 vlv_dpio_write(dev_priv, pipe, CHV_PCS_DW10(ch),
1347 DPIO_PCS_SWING_CALC_TX0_TX2 |
1348 DPIO_PCS_SWING_CALC_TX1_TX3);
1351 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1352 val |= DPIO_LRC_BYPASS;
1353 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
1355 mutex_unlock(&dev_priv->dpio_lock);
1357 intel_enable_hdmi(encoder);
1359 vlv_wait_port_ready(dev_priv, dport);
1362 static void intel_hdmi_destroy(struct drm_connector *connector)
1364 drm_connector_cleanup(connector);
1368 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
1369 .dpms = intel_connector_dpms,
1370 .detect = intel_hdmi_detect,
1371 .fill_modes = drm_helper_probe_single_connector_modes,
1372 .set_property = intel_hdmi_set_property,
1373 .destroy = intel_hdmi_destroy,
1376 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
1377 .get_modes = intel_hdmi_get_modes,
1378 .mode_valid = intel_hdmi_mode_valid,
1379 .best_encoder = intel_best_encoder,
1382 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
1383 .destroy = intel_encoder_destroy,
1387 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
1389 intel_attach_force_audio_property(connector);
1390 intel_attach_broadcast_rgb_property(connector);
1391 intel_hdmi->color_range_auto = true;
1394 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1395 struct intel_connector *intel_connector)
1397 struct drm_connector *connector = &intel_connector->base;
1398 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
1399 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1400 struct drm_device *dev = intel_encoder->base.dev;
1401 struct drm_i915_private *dev_priv = dev->dev_private;
1402 enum port port = intel_dig_port->port;
1404 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
1405 DRM_MODE_CONNECTOR_HDMIA);
1406 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
1408 connector->interlace_allowed = 1;
1409 connector->doublescan_allowed = 0;
1410 connector->stereo_allowed = 1;
1414 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
1415 intel_encoder->hpd_pin = HPD_PORT_B;
1418 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
1419 intel_encoder->hpd_pin = HPD_PORT_C;
1422 if (IS_CHERRYVIEW(dev))
1423 intel_hdmi->ddc_bus = GMBUS_PORT_DPD_CHV;
1425 intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
1426 intel_encoder->hpd_pin = HPD_PORT_D;
1429 intel_encoder->hpd_pin = HPD_PORT_A;
1430 /* Internal port only for eDP. */
1435 if (IS_VALLEYVIEW(dev)) {
1436 intel_hdmi->write_infoframe = vlv_write_infoframe;
1437 intel_hdmi->set_infoframes = vlv_set_infoframes;
1438 } else if (!HAS_PCH_SPLIT(dev)) {
1439 intel_hdmi->write_infoframe = g4x_write_infoframe;
1440 intel_hdmi->set_infoframes = g4x_set_infoframes;
1441 } else if (HAS_DDI(dev)) {
1442 intel_hdmi->write_infoframe = hsw_write_infoframe;
1443 intel_hdmi->set_infoframes = hsw_set_infoframes;
1444 } else if (HAS_PCH_IBX(dev)) {
1445 intel_hdmi->write_infoframe = ibx_write_infoframe;
1446 intel_hdmi->set_infoframes = ibx_set_infoframes;
1448 intel_hdmi->write_infoframe = cpt_write_infoframe;
1449 intel_hdmi->set_infoframes = cpt_set_infoframes;
1453 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
1455 intel_connector->get_hw_state = intel_connector_get_hw_state;
1456 intel_connector->unregister = intel_connector_unregister;
1458 intel_hdmi_add_properties(intel_hdmi, connector);
1460 intel_connector_attach_encoder(intel_connector, intel_encoder);
1461 drm_sysfs_connector_add(connector);
1463 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1464 * 0xd. Failure to do so will result in spurious interrupts being
1465 * generated on the port when a cable is not attached.
1467 if (IS_G4X(dev) && !IS_GM45(dev)) {
1468 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1469 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1473 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
1475 struct intel_digital_port *intel_dig_port;
1476 struct intel_encoder *intel_encoder;
1477 struct intel_connector *intel_connector;
1479 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
1480 if (!intel_dig_port)
1483 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
1484 if (!intel_connector) {
1485 kfree(intel_dig_port);
1489 intel_encoder = &intel_dig_port->base;
1491 drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
1492 DRM_MODE_ENCODER_TMDS);
1494 intel_encoder->compute_config = intel_hdmi_compute_config;
1495 intel_encoder->disable = intel_disable_hdmi;
1496 intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
1497 intel_encoder->get_config = intel_hdmi_get_config;
1498 if (IS_CHERRYVIEW(dev)) {
1499 intel_encoder->pre_enable = chv_hdmi_pre_enable;
1500 intel_encoder->enable = vlv_enable_hdmi;
1501 intel_encoder->post_disable = chv_hdmi_post_disable;
1502 } else if (IS_VALLEYVIEW(dev)) {
1503 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
1504 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
1505 intel_encoder->enable = vlv_enable_hdmi;
1506 intel_encoder->post_disable = vlv_hdmi_post_disable;
1508 intel_encoder->pre_enable = intel_hdmi_pre_enable;
1509 intel_encoder->enable = intel_enable_hdmi;
1512 intel_encoder->type = INTEL_OUTPUT_HDMI;
1513 if (IS_CHERRYVIEW(dev)) {
1515 intel_encoder->crtc_mask = 1 << 2;
1517 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1519 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1521 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
1523 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
1524 * to work on real hardware. And since g4x can send infoframes to
1525 * only one port anyway, nothing is lost by allowing it.
1528 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
1530 intel_dig_port->port = port;
1531 intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
1532 intel_dig_port->dp.output_reg = 0;
1534 intel_hdmi_init_connector(intel_dig_port, intel_connector);