2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
29 #include <linux/i2c.h>
30 #include <linux/slab.h>
31 #include <linux/delay.h>
32 #include <linux/hdmi.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_edid.h>
37 #include "intel_drv.h"
38 #include <drm/i915_drm.h>
41 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
43 return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
47 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
49 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
50 struct drm_i915_private *dev_priv = dev->dev_private;
51 uint32_t enabled_bits;
53 enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
55 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
56 "HDMI port enabled, expecting disabled\n");
59 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
61 struct intel_digital_port *intel_dig_port =
62 container_of(encoder, struct intel_digital_port, base.base);
63 return &intel_dig_port->hdmi;
66 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
68 return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
71 static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
74 case HDMI_INFOFRAME_TYPE_AVI:
75 return VIDEO_DIP_SELECT_AVI;
76 case HDMI_INFOFRAME_TYPE_SPD:
77 return VIDEO_DIP_SELECT_SPD;
78 case HDMI_INFOFRAME_TYPE_VENDOR:
79 return VIDEO_DIP_SELECT_VENDOR;
81 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
86 static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
89 case HDMI_INFOFRAME_TYPE_AVI:
90 return VIDEO_DIP_ENABLE_AVI;
91 case HDMI_INFOFRAME_TYPE_SPD:
92 return VIDEO_DIP_ENABLE_SPD;
93 case HDMI_INFOFRAME_TYPE_VENDOR:
94 return VIDEO_DIP_ENABLE_VENDOR;
96 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
101 static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
104 case HDMI_INFOFRAME_TYPE_AVI:
105 return VIDEO_DIP_ENABLE_AVI_HSW;
106 case HDMI_INFOFRAME_TYPE_SPD:
107 return VIDEO_DIP_ENABLE_SPD_HSW;
108 case HDMI_INFOFRAME_TYPE_VENDOR:
109 return VIDEO_DIP_ENABLE_VS_HSW;
111 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
116 static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type,
117 enum transcoder cpu_transcoder,
118 struct drm_i915_private *dev_priv)
121 case HDMI_INFOFRAME_TYPE_AVI:
122 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder);
123 case HDMI_INFOFRAME_TYPE_SPD:
124 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder);
125 case HDMI_INFOFRAME_TYPE_VENDOR:
126 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder);
128 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
133 static void g4x_write_infoframe(struct drm_encoder *encoder,
134 enum hdmi_infoframe_type type,
135 const void *frame, ssize_t len)
137 const uint32_t *data = frame;
138 struct drm_device *dev = encoder->dev;
139 struct drm_i915_private *dev_priv = dev->dev_private;
140 u32 val = I915_READ(VIDEO_DIP_CTL);
143 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
145 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
146 val |= g4x_infoframe_index(type);
148 val &= ~g4x_infoframe_enable(type);
150 I915_WRITE(VIDEO_DIP_CTL, val);
153 for (i = 0; i < len; i += 4) {
154 I915_WRITE(VIDEO_DIP_DATA, *data);
157 /* Write every possible data byte to force correct ECC calculation. */
158 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
159 I915_WRITE(VIDEO_DIP_DATA, 0);
162 val |= g4x_infoframe_enable(type);
163 val &= ~VIDEO_DIP_FREQ_MASK;
164 val |= VIDEO_DIP_FREQ_VSYNC;
166 I915_WRITE(VIDEO_DIP_CTL, val);
167 POSTING_READ(VIDEO_DIP_CTL);
170 static bool g4x_infoframe_enabled(struct drm_encoder *encoder)
172 struct drm_device *dev = encoder->dev;
173 struct drm_i915_private *dev_priv = dev->dev_private;
174 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
175 u32 val = I915_READ(VIDEO_DIP_CTL);
177 if ((val & VIDEO_DIP_ENABLE) == 0)
180 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
183 return val & (VIDEO_DIP_ENABLE_AVI |
184 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
187 static void ibx_write_infoframe(struct drm_encoder *encoder,
188 enum hdmi_infoframe_type type,
189 const void *frame, ssize_t len)
191 const uint32_t *data = frame;
192 struct drm_device *dev = encoder->dev;
193 struct drm_i915_private *dev_priv = dev->dev_private;
194 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
195 int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
196 u32 val = I915_READ(reg);
198 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
200 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
201 val |= g4x_infoframe_index(type);
203 val &= ~g4x_infoframe_enable(type);
205 I915_WRITE(reg, val);
208 for (i = 0; i < len; i += 4) {
209 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
212 /* Write every possible data byte to force correct ECC calculation. */
213 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
214 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
217 val |= g4x_infoframe_enable(type);
218 val &= ~VIDEO_DIP_FREQ_MASK;
219 val |= VIDEO_DIP_FREQ_VSYNC;
221 I915_WRITE(reg, val);
225 static bool ibx_infoframe_enabled(struct drm_encoder *encoder)
227 struct drm_device *dev = encoder->dev;
228 struct drm_i915_private *dev_priv = dev->dev_private;
229 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
230 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
231 int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
232 u32 val = I915_READ(reg);
234 if ((val & VIDEO_DIP_ENABLE) == 0)
237 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
240 return val & (VIDEO_DIP_ENABLE_AVI |
241 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
242 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
245 static void cpt_write_infoframe(struct drm_encoder *encoder,
246 enum hdmi_infoframe_type type,
247 const void *frame, ssize_t len)
249 const uint32_t *data = frame;
250 struct drm_device *dev = encoder->dev;
251 struct drm_i915_private *dev_priv = dev->dev_private;
252 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
253 int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
254 u32 val = I915_READ(reg);
256 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
258 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
259 val |= g4x_infoframe_index(type);
261 /* The DIP control register spec says that we need to update the AVI
262 * infoframe without clearing its enable bit */
263 if (type != HDMI_INFOFRAME_TYPE_AVI)
264 val &= ~g4x_infoframe_enable(type);
266 I915_WRITE(reg, val);
269 for (i = 0; i < len; i += 4) {
270 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
273 /* Write every possible data byte to force correct ECC calculation. */
274 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
275 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
278 val |= g4x_infoframe_enable(type);
279 val &= ~VIDEO_DIP_FREQ_MASK;
280 val |= VIDEO_DIP_FREQ_VSYNC;
282 I915_WRITE(reg, val);
286 static bool cpt_infoframe_enabled(struct drm_encoder *encoder)
288 struct drm_device *dev = encoder->dev;
289 struct drm_i915_private *dev_priv = dev->dev_private;
290 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
291 int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
292 u32 val = I915_READ(reg);
294 if ((val & VIDEO_DIP_ENABLE) == 0)
297 return val & (VIDEO_DIP_ENABLE_AVI |
298 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
299 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
302 static void vlv_write_infoframe(struct drm_encoder *encoder,
303 enum hdmi_infoframe_type type,
304 const void *frame, ssize_t len)
306 const uint32_t *data = frame;
307 struct drm_device *dev = encoder->dev;
308 struct drm_i915_private *dev_priv = dev->dev_private;
309 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
310 int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
311 u32 val = I915_READ(reg);
313 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
315 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
316 val |= g4x_infoframe_index(type);
318 val &= ~g4x_infoframe_enable(type);
320 I915_WRITE(reg, val);
323 for (i = 0; i < len; i += 4) {
324 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
327 /* Write every possible data byte to force correct ECC calculation. */
328 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
329 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
332 val |= g4x_infoframe_enable(type);
333 val &= ~VIDEO_DIP_FREQ_MASK;
334 val |= VIDEO_DIP_FREQ_VSYNC;
336 I915_WRITE(reg, val);
340 static bool vlv_infoframe_enabled(struct drm_encoder *encoder)
342 struct drm_device *dev = encoder->dev;
343 struct drm_i915_private *dev_priv = dev->dev_private;
344 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
345 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
346 int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
347 u32 val = I915_READ(reg);
349 if ((val & VIDEO_DIP_ENABLE) == 0)
352 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
355 return val & (VIDEO_DIP_ENABLE_AVI |
356 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
357 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
360 static void hsw_write_infoframe(struct drm_encoder *encoder,
361 enum hdmi_infoframe_type type,
362 const void *frame, ssize_t len)
364 const uint32_t *data = frame;
365 struct drm_device *dev = encoder->dev;
366 struct drm_i915_private *dev_priv = dev->dev_private;
367 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
368 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
371 u32 val = I915_READ(ctl_reg);
373 data_reg = hsw_infoframe_data_reg(type,
374 intel_crtc->config->cpu_transcoder,
379 val &= ~hsw_infoframe_enable(type);
380 I915_WRITE(ctl_reg, val);
383 for (i = 0; i < len; i += 4) {
384 I915_WRITE(data_reg + i, *data);
387 /* Write every possible data byte to force correct ECC calculation. */
388 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
389 I915_WRITE(data_reg + i, 0);
392 val |= hsw_infoframe_enable(type);
393 I915_WRITE(ctl_reg, val);
394 POSTING_READ(ctl_reg);
397 static bool hsw_infoframe_enabled(struct drm_encoder *encoder)
399 struct drm_device *dev = encoder->dev;
400 struct drm_i915_private *dev_priv = dev->dev_private;
401 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
402 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
403 u32 val = I915_READ(ctl_reg);
405 return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
406 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
407 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
411 * The data we write to the DIP data buffer registers is 1 byte bigger than the
412 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
413 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
414 * used for both technologies.
416 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
417 * DW1: DB3 | DB2 | DB1 | DB0
418 * DW2: DB7 | DB6 | DB5 | DB4
421 * (HB is Header Byte, DB is Data Byte)
423 * The hdmi pack() functions don't know about that hardware specific hole so we
424 * trick them by giving an offset into the buffer and moving back the header
427 static void intel_write_infoframe(struct drm_encoder *encoder,
428 union hdmi_infoframe *frame)
430 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
431 uint8_t buffer[VIDEO_DIP_DATA_SIZE];
434 /* see comment above for the reason for this offset */
435 len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
439 /* Insert the 'hole' (see big comment above) at position 3 */
440 buffer[0] = buffer[1];
441 buffer[1] = buffer[2];
442 buffer[2] = buffer[3];
446 intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);
449 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
450 struct drm_display_mode *adjusted_mode)
452 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
453 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
454 union hdmi_infoframe frame;
457 /* Set user selected PAR to incoming mode's member */
458 adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio;
460 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
463 DRM_ERROR("couldn't fill AVI infoframe\n");
467 if (intel_hdmi->rgb_quant_range_selectable) {
468 if (intel_crtc->config->limited_color_range)
469 frame.avi.quantization_range =
470 HDMI_QUANTIZATION_RANGE_LIMITED;
472 frame.avi.quantization_range =
473 HDMI_QUANTIZATION_RANGE_FULL;
476 intel_write_infoframe(encoder, &frame);
479 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
481 union hdmi_infoframe frame;
484 ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
486 DRM_ERROR("couldn't fill SPD infoframe\n");
490 frame.spd.sdi = HDMI_SPD_SDI_PC;
492 intel_write_infoframe(encoder, &frame);
496 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
497 struct drm_display_mode *adjusted_mode)
499 union hdmi_infoframe frame;
502 ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
507 intel_write_infoframe(encoder, &frame);
510 static void g4x_set_infoframes(struct drm_encoder *encoder,
512 struct drm_display_mode *adjusted_mode)
514 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
515 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
516 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
517 u32 reg = VIDEO_DIP_CTL;
518 u32 val = I915_READ(reg);
519 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
521 assert_hdmi_port_disabled(intel_hdmi);
523 /* If the registers were not initialized yet, they might be zeroes,
524 * which means we're selecting the AVI DIP and we're setting its
525 * frequency to once. This seems to really confuse the HW and make
526 * things stop working (the register spec says the AVI always needs to
527 * be sent every VSync). So here we avoid writing to the register more
528 * than we need and also explicitly select the AVI DIP and explicitly
529 * set its frequency to every VSync. Avoiding to write it twice seems to
530 * be enough to solve the problem, but being defensive shouldn't hurt us
532 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
535 if (!(val & VIDEO_DIP_ENABLE))
537 if (port != (val & VIDEO_DIP_PORT_MASK)) {
538 DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
539 (val & VIDEO_DIP_PORT_MASK) >> 29);
542 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
543 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
544 I915_WRITE(reg, val);
549 if (port != (val & VIDEO_DIP_PORT_MASK)) {
550 if (val & VIDEO_DIP_ENABLE) {
551 DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
552 (val & VIDEO_DIP_PORT_MASK) >> 29);
555 val &= ~VIDEO_DIP_PORT_MASK;
559 val |= VIDEO_DIP_ENABLE;
560 val &= ~(VIDEO_DIP_ENABLE_AVI |
561 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
563 I915_WRITE(reg, val);
566 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
567 intel_hdmi_set_spd_infoframe(encoder);
568 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
571 static bool hdmi_sink_is_deep_color(struct drm_encoder *encoder)
573 struct drm_device *dev = encoder->dev;
574 struct drm_connector *connector;
576 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
579 * HDMI cloning is only supported on g4x which doesn't
580 * support deep color or GCP infoframes anyway so no
581 * need to worry about multiple HDMI sinks here.
583 list_for_each_entry(connector, &dev->mode_config.connector_list, head)
584 if (connector->encoder == encoder)
585 return connector->display_info.bpc > 8;
591 * Determine if default_phase=1 can be indicated in the GCP infoframe.
593 * From HDMI specification 1.4a:
594 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
595 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
596 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
597 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
600 static bool gcp_default_phase_possible(int pipe_bpp,
601 const struct drm_display_mode *mode)
603 unsigned int pixels_per_group;
607 /* 4 pixels in 5 clocks */
608 pixels_per_group = 4;
611 /* 2 pixels in 3 clocks */
612 pixels_per_group = 2;
615 /* 1 pixel in 2 clocks */
616 pixels_per_group = 1;
619 /* phase information not relevant for 8bpc */
623 return mode->crtc_hdisplay % pixels_per_group == 0 &&
624 mode->crtc_htotal % pixels_per_group == 0 &&
625 mode->crtc_hblank_start % pixels_per_group == 0 &&
626 mode->crtc_hblank_end % pixels_per_group == 0 &&
627 mode->crtc_hsync_start % pixels_per_group == 0 &&
628 mode->crtc_hsync_end % pixels_per_group == 0 &&
629 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
630 mode->crtc_htotal/2 % pixels_per_group == 0);
633 static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder)
635 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
636 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
639 if (HAS_DDI(dev_priv))
640 reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder);
641 else if (IS_VALLEYVIEW(dev_priv))
642 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
643 else if (HAS_PCH_SPLIT(dev_priv->dev))
644 reg = TVIDEO_DIP_GCP(crtc->pipe);
648 /* Indicate color depth whenever the sink supports deep color */
649 if (hdmi_sink_is_deep_color(encoder))
650 val |= GCP_COLOR_INDICATION;
652 /* Enable default_phase whenever the display mode is suitably aligned */
653 if (gcp_default_phase_possible(crtc->config->pipe_bpp,
654 &crtc->config->base.adjusted_mode))
655 val |= GCP_DEFAULT_PHASE_ENABLE;
657 I915_WRITE(reg, val);
662 static void ibx_set_infoframes(struct drm_encoder *encoder,
664 struct drm_display_mode *adjusted_mode)
666 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
667 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
668 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
669 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
670 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
671 u32 val = I915_READ(reg);
672 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
674 assert_hdmi_port_disabled(intel_hdmi);
676 /* See the big comment in g4x_set_infoframes() */
677 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
680 if (!(val & VIDEO_DIP_ENABLE))
682 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
683 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
684 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
685 I915_WRITE(reg, val);
690 if (port != (val & VIDEO_DIP_PORT_MASK)) {
691 WARN(val & VIDEO_DIP_ENABLE,
692 "DIP already enabled on port %c\n",
693 (val & VIDEO_DIP_PORT_MASK) >> 29);
694 val &= ~VIDEO_DIP_PORT_MASK;
698 val |= VIDEO_DIP_ENABLE;
699 val &= ~(VIDEO_DIP_ENABLE_AVI |
700 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
701 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
703 if (intel_hdmi_set_gcp_infoframe(encoder))
704 val |= VIDEO_DIP_ENABLE_GCP;
706 I915_WRITE(reg, val);
709 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
710 intel_hdmi_set_spd_infoframe(encoder);
711 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
714 static void cpt_set_infoframes(struct drm_encoder *encoder,
716 struct drm_display_mode *adjusted_mode)
718 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
719 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
720 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
721 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
722 u32 val = I915_READ(reg);
724 assert_hdmi_port_disabled(intel_hdmi);
726 /* See the big comment in g4x_set_infoframes() */
727 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
730 if (!(val & VIDEO_DIP_ENABLE))
732 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
733 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
734 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
735 I915_WRITE(reg, val);
740 /* Set both together, unset both together: see the spec. */
741 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
742 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
743 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
745 if (intel_hdmi_set_gcp_infoframe(encoder))
746 val |= VIDEO_DIP_ENABLE_GCP;
748 I915_WRITE(reg, val);
751 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
752 intel_hdmi_set_spd_infoframe(encoder);
753 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
756 static void vlv_set_infoframes(struct drm_encoder *encoder,
758 struct drm_display_mode *adjusted_mode)
760 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
761 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
762 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
763 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
764 u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
765 u32 val = I915_READ(reg);
766 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
768 assert_hdmi_port_disabled(intel_hdmi);
770 /* See the big comment in g4x_set_infoframes() */
771 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
774 if (!(val & VIDEO_DIP_ENABLE))
776 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
777 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
778 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
779 I915_WRITE(reg, val);
784 if (port != (val & VIDEO_DIP_PORT_MASK)) {
785 WARN(val & VIDEO_DIP_ENABLE,
786 "DIP already enabled on port %c\n",
787 (val & VIDEO_DIP_PORT_MASK) >> 29);
788 val &= ~VIDEO_DIP_PORT_MASK;
792 val |= VIDEO_DIP_ENABLE;
793 val &= ~(VIDEO_DIP_ENABLE_AVI |
794 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
795 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
797 if (intel_hdmi_set_gcp_infoframe(encoder))
798 val |= VIDEO_DIP_ENABLE_GCP;
800 I915_WRITE(reg, val);
803 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
804 intel_hdmi_set_spd_infoframe(encoder);
805 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
808 static void hsw_set_infoframes(struct drm_encoder *encoder,
810 struct drm_display_mode *adjusted_mode)
812 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
813 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
814 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
815 u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
816 u32 val = I915_READ(reg);
818 assert_hdmi_port_disabled(intel_hdmi);
820 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
821 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
822 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
825 I915_WRITE(reg, val);
830 if (intel_hdmi_set_gcp_infoframe(encoder))
831 val |= VIDEO_DIP_ENABLE_GCP_HSW;
833 I915_WRITE(reg, val);
836 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
837 intel_hdmi_set_spd_infoframe(encoder);
838 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
841 static void intel_hdmi_prepare(struct intel_encoder *encoder)
843 struct drm_device *dev = encoder->base.dev;
844 struct drm_i915_private *dev_priv = dev->dev_private;
845 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
846 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
847 struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
850 hdmi_val = SDVO_ENCODING_HDMI;
851 if (!HAS_PCH_SPLIT(dev))
852 hdmi_val |= intel_hdmi->color_range;
853 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
854 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
855 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
856 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
858 if (crtc->config->pipe_bpp > 24)
859 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
861 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
863 if (crtc->config->has_hdmi_sink)
864 hdmi_val |= HDMI_MODE_SELECT_HDMI;
866 if (HAS_PCH_CPT(dev))
867 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
868 else if (IS_CHERRYVIEW(dev))
869 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
871 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
873 I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
874 POSTING_READ(intel_hdmi->hdmi_reg);
877 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
880 struct drm_device *dev = encoder->base.dev;
881 struct drm_i915_private *dev_priv = dev->dev_private;
882 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
883 enum intel_display_power_domain power_domain;
886 power_domain = intel_display_port_power_domain(encoder);
887 if (!intel_display_power_is_enabled(dev_priv, power_domain))
890 tmp = I915_READ(intel_hdmi->hdmi_reg);
892 if (!(tmp & SDVO_ENABLE))
895 if (HAS_PCH_CPT(dev))
896 *pipe = PORT_TO_PIPE_CPT(tmp);
897 else if (IS_CHERRYVIEW(dev))
898 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
900 *pipe = PORT_TO_PIPE(tmp);
905 static void intel_hdmi_get_config(struct intel_encoder *encoder,
906 struct intel_crtc_state *pipe_config)
908 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
909 struct drm_device *dev = encoder->base.dev;
910 struct drm_i915_private *dev_priv = dev->dev_private;
914 tmp = I915_READ(intel_hdmi->hdmi_reg);
916 if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
917 flags |= DRM_MODE_FLAG_PHSYNC;
919 flags |= DRM_MODE_FLAG_NHSYNC;
921 if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
922 flags |= DRM_MODE_FLAG_PVSYNC;
924 flags |= DRM_MODE_FLAG_NVSYNC;
926 if (tmp & HDMI_MODE_SELECT_HDMI)
927 pipe_config->has_hdmi_sink = true;
929 if (intel_hdmi->infoframe_enabled(&encoder->base))
930 pipe_config->has_infoframe = true;
932 if (tmp & SDVO_AUDIO_ENABLE)
933 pipe_config->has_audio = true;
935 if (!HAS_PCH_SPLIT(dev) &&
936 tmp & HDMI_COLOR_RANGE_16_235)
937 pipe_config->limited_color_range = true;
939 pipe_config->base.adjusted_mode.flags |= flags;
941 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
942 dotclock = pipe_config->port_clock * 2 / 3;
944 dotclock = pipe_config->port_clock;
946 if (pipe_config->pixel_multiplier)
947 dotclock /= pipe_config->pixel_multiplier;
949 if (HAS_PCH_SPLIT(dev_priv->dev))
950 ironlake_check_encoder_dotclock(pipe_config, dotclock);
952 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
955 static void intel_enable_hdmi_audio(struct intel_encoder *encoder)
957 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
959 WARN_ON(!crtc->config->has_hdmi_sink);
960 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
961 pipe_name(crtc->pipe));
962 intel_audio_codec_enable(encoder);
965 static void g4x_enable_hdmi(struct intel_encoder *encoder)
967 struct drm_device *dev = encoder->base.dev;
968 struct drm_i915_private *dev_priv = dev->dev_private;
969 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
970 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
973 temp = I915_READ(intel_hdmi->hdmi_reg);
976 if (crtc->config->has_audio)
977 temp |= SDVO_AUDIO_ENABLE;
979 I915_WRITE(intel_hdmi->hdmi_reg, temp);
980 POSTING_READ(intel_hdmi->hdmi_reg);
982 if (crtc->config->has_audio)
983 intel_enable_hdmi_audio(encoder);
986 static void ibx_enable_hdmi(struct intel_encoder *encoder)
988 struct drm_device *dev = encoder->base.dev;
989 struct drm_i915_private *dev_priv = dev->dev_private;
990 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
991 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
994 temp = I915_READ(intel_hdmi->hdmi_reg);
997 if (crtc->config->has_audio)
998 temp |= SDVO_AUDIO_ENABLE;
1001 * HW workaround, need to write this twice for issue
1002 * that may result in first write getting masked.
1004 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1005 POSTING_READ(intel_hdmi->hdmi_reg);
1006 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1007 POSTING_READ(intel_hdmi->hdmi_reg);
1010 * HW workaround, need to toggle enable bit off and on
1011 * for 12bpc with pixel repeat.
1013 * FIXME: BSpec says this should be done at the end of
1014 * of the modeset sequence, so not sure if this isn't too soon.
1016 if (crtc->config->pipe_bpp > 24 &&
1017 crtc->config->pixel_multiplier > 1) {
1018 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1019 POSTING_READ(intel_hdmi->hdmi_reg);
1022 * HW workaround, need to write this twice for issue
1023 * that may result in first write getting masked.
1025 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1026 POSTING_READ(intel_hdmi->hdmi_reg);
1027 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1028 POSTING_READ(intel_hdmi->hdmi_reg);
1031 if (crtc->config->has_audio)
1032 intel_enable_hdmi_audio(encoder);
1035 static void cpt_enable_hdmi(struct intel_encoder *encoder)
1037 struct drm_device *dev = encoder->base.dev;
1038 struct drm_i915_private *dev_priv = dev->dev_private;
1039 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1040 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1041 enum pipe pipe = crtc->pipe;
1044 temp = I915_READ(intel_hdmi->hdmi_reg);
1046 temp |= SDVO_ENABLE;
1047 if (crtc->config->has_audio)
1048 temp |= SDVO_AUDIO_ENABLE;
1051 * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1053 * The procedure for 12bpc is as follows:
1054 * 1. disable HDMI clock gating
1055 * 2. enable HDMI with 8bpc
1056 * 3. enable HDMI with 12bpc
1057 * 4. enable HDMI clock gating
1060 if (crtc->config->pipe_bpp > 24) {
1061 I915_WRITE(TRANS_CHICKEN1(pipe),
1062 I915_READ(TRANS_CHICKEN1(pipe)) |
1063 TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1065 temp &= ~SDVO_COLOR_FORMAT_MASK;
1066 temp |= SDVO_COLOR_FORMAT_8bpc;
1069 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1070 POSTING_READ(intel_hdmi->hdmi_reg);
1072 if (crtc->config->pipe_bpp > 24) {
1073 temp &= ~SDVO_COLOR_FORMAT_MASK;
1074 temp |= HDMI_COLOR_FORMAT_12bpc;
1076 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1077 POSTING_READ(intel_hdmi->hdmi_reg);
1079 I915_WRITE(TRANS_CHICKEN1(pipe),
1080 I915_READ(TRANS_CHICKEN1(pipe)) &
1081 ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1084 if (crtc->config->has_audio)
1085 intel_enable_hdmi_audio(encoder);
1088 static void vlv_enable_hdmi(struct intel_encoder *encoder)
1092 static void intel_disable_hdmi(struct intel_encoder *encoder)
1094 struct drm_device *dev = encoder->base.dev;
1095 struct drm_i915_private *dev_priv = dev->dev_private;
1096 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1097 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1100 temp = I915_READ(intel_hdmi->hdmi_reg);
1102 temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
1103 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1104 POSTING_READ(intel_hdmi->hdmi_reg);
1107 * HW workaround for IBX, we need to move the port
1108 * to transcoder A after disabling it to allow the
1109 * matching DP port to be enabled on transcoder A.
1111 if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) {
1112 temp &= ~SDVO_PIPE_B_SELECT;
1113 temp |= SDVO_ENABLE;
1115 * HW workaround, need to write this twice for issue
1116 * that may result in first write getting masked.
1118 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1119 POSTING_READ(intel_hdmi->hdmi_reg);
1120 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1121 POSTING_READ(intel_hdmi->hdmi_reg);
1123 temp &= ~SDVO_ENABLE;
1124 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1125 POSTING_READ(intel_hdmi->hdmi_reg);
1128 intel_hdmi->set_infoframes(&encoder->base, false, NULL);
1131 static void g4x_disable_hdmi(struct intel_encoder *encoder)
1133 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1135 if (crtc->config->has_audio)
1136 intel_audio_codec_disable(encoder);
1138 intel_disable_hdmi(encoder);
1141 static void pch_disable_hdmi(struct intel_encoder *encoder)
1143 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1145 if (crtc->config->has_audio)
1146 intel_audio_codec_disable(encoder);
1149 static void pch_post_disable_hdmi(struct intel_encoder *encoder)
1151 intel_disable_hdmi(encoder);
1154 static int hdmi_portclock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit)
1156 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1158 if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev))
1160 else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8)
1166 static enum drm_mode_status
1167 intel_hdmi_mode_valid(struct drm_connector *connector,
1168 struct drm_display_mode *mode)
1170 int clock = mode->clock;
1172 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1175 if (clock > hdmi_portclock_limit(intel_attached_hdmi(connector),
1177 return MODE_CLOCK_HIGH;
1179 return MODE_CLOCK_LOW;
1181 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1182 return MODE_NO_DBLESCAN;
1187 static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)
1189 struct drm_device *dev = crtc_state->base.crtc->dev;
1190 struct drm_atomic_state *state;
1191 struct intel_encoder *encoder;
1192 struct drm_connector *connector;
1193 struct drm_connector_state *connector_state;
1194 int count = 0, count_hdmi = 0;
1197 if (HAS_GMCH_DISPLAY(dev))
1200 state = crtc_state->base.state;
1202 for_each_connector_in_state(state, connector, connector_state, i) {
1203 if (connector_state->crtc != crtc_state->base.crtc)
1206 encoder = to_intel_encoder(connector_state->best_encoder);
1208 count_hdmi += encoder->type == INTEL_OUTPUT_HDMI;
1213 * HDMI 12bpc affects the clocks, so it's only possible
1214 * when not cloning with other encoder types.
1216 return count_hdmi > 0 && count_hdmi == count;
1219 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1220 struct intel_crtc_state *pipe_config)
1222 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1223 struct drm_device *dev = encoder->base.dev;
1224 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1225 int clock_12bpc = pipe_config->base.adjusted_mode.crtc_clock * 3 / 2;
1226 int portclock_limit = hdmi_portclock_limit(intel_hdmi, false);
1229 pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink;
1231 if (pipe_config->has_hdmi_sink)
1232 pipe_config->has_infoframe = true;
1234 if (intel_hdmi->color_range_auto) {
1235 /* See CEA-861-E - 5.1 Default Encoding Parameters */
1236 if (pipe_config->has_hdmi_sink &&
1237 drm_match_cea_mode(adjusted_mode) > 1)
1238 intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
1240 intel_hdmi->color_range = 0;
1243 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
1244 pipe_config->pixel_multiplier = 2;
1248 if (intel_hdmi->color_range)
1249 pipe_config->limited_color_range = true;
1251 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
1252 pipe_config->has_pch_encoder = true;
1254 if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio)
1255 pipe_config->has_audio = true;
1258 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
1259 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
1260 * outputs. We also need to check that the higher clock still fits
1263 if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink &&
1264 clock_12bpc <= portclock_limit &&
1265 hdmi_12bpc_possible(pipe_config) &&
1266 0 /* FIXME 12bpc support totally broken */) {
1267 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
1270 /* Need to adjust the port link by 1.5x for 12bpc. */
1271 pipe_config->port_clock = clock_12bpc;
1273 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
1277 if (!pipe_config->bw_constrained) {
1278 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
1279 pipe_config->pipe_bpp = desired_bpp;
1282 if (adjusted_mode->crtc_clock > portclock_limit) {
1283 DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n");
1291 intel_hdmi_unset_edid(struct drm_connector *connector)
1293 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1295 intel_hdmi->has_hdmi_sink = false;
1296 intel_hdmi->has_audio = false;
1297 intel_hdmi->rgb_quant_range_selectable = false;
1299 kfree(to_intel_connector(connector)->detect_edid);
1300 to_intel_connector(connector)->detect_edid = NULL;
1304 intel_hdmi_set_edid(struct drm_connector *connector)
1306 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1307 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1308 struct intel_encoder *intel_encoder =
1309 &hdmi_to_dig_port(intel_hdmi)->base;
1310 enum intel_display_power_domain power_domain;
1312 bool connected = false;
1314 power_domain = intel_display_port_power_domain(intel_encoder);
1315 intel_display_power_get(dev_priv, power_domain);
1317 edid = drm_get_edid(connector,
1318 intel_gmbus_get_adapter(dev_priv,
1319 intel_hdmi->ddc_bus));
1321 intel_display_power_put(dev_priv, power_domain);
1323 to_intel_connector(connector)->detect_edid = edid;
1324 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
1325 intel_hdmi->rgb_quant_range_selectable =
1326 drm_rgb_quant_range_selectable(edid);
1328 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
1329 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
1330 intel_hdmi->has_audio =
1331 intel_hdmi->force_audio == HDMI_AUDIO_ON;
1333 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
1334 intel_hdmi->has_hdmi_sink =
1335 drm_detect_hdmi_monitor(edid);
1343 static enum drm_connector_status
1344 intel_hdmi_detect(struct drm_connector *connector, bool force)
1346 enum drm_connector_status status;
1348 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1349 connector->base.id, connector->name);
1351 intel_hdmi_unset_edid(connector);
1353 if (intel_hdmi_set_edid(connector)) {
1354 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1356 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1357 status = connector_status_connected;
1359 status = connector_status_disconnected;
1365 intel_hdmi_force(struct drm_connector *connector)
1367 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1369 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1370 connector->base.id, connector->name);
1372 intel_hdmi_unset_edid(connector);
1374 if (connector->status != connector_status_connected)
1377 intel_hdmi_set_edid(connector);
1378 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1381 static int intel_hdmi_get_modes(struct drm_connector *connector)
1385 edid = to_intel_connector(connector)->detect_edid;
1389 return intel_connector_update_modes(connector, edid);
1393 intel_hdmi_detect_audio(struct drm_connector *connector)
1395 bool has_audio = false;
1398 edid = to_intel_connector(connector)->detect_edid;
1399 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL)
1400 has_audio = drm_detect_monitor_audio(edid);
1406 intel_hdmi_set_property(struct drm_connector *connector,
1407 struct drm_property *property,
1410 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1411 struct intel_digital_port *intel_dig_port =
1412 hdmi_to_dig_port(intel_hdmi);
1413 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1416 ret = drm_object_property_set_value(&connector->base, property, val);
1420 if (property == dev_priv->force_audio_property) {
1421 enum hdmi_force_audio i = val;
1424 if (i == intel_hdmi->force_audio)
1427 intel_hdmi->force_audio = i;
1429 if (i == HDMI_AUDIO_AUTO)
1430 has_audio = intel_hdmi_detect_audio(connector);
1432 has_audio = (i == HDMI_AUDIO_ON);
1434 if (i == HDMI_AUDIO_OFF_DVI)
1435 intel_hdmi->has_hdmi_sink = 0;
1437 intel_hdmi->has_audio = has_audio;
1441 if (property == dev_priv->broadcast_rgb_property) {
1442 bool old_auto = intel_hdmi->color_range_auto;
1443 uint32_t old_range = intel_hdmi->color_range;
1446 case INTEL_BROADCAST_RGB_AUTO:
1447 intel_hdmi->color_range_auto = true;
1449 case INTEL_BROADCAST_RGB_FULL:
1450 intel_hdmi->color_range_auto = false;
1451 intel_hdmi->color_range = 0;
1453 case INTEL_BROADCAST_RGB_LIMITED:
1454 intel_hdmi->color_range_auto = false;
1455 intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
1461 if (old_auto == intel_hdmi->color_range_auto &&
1462 old_range == intel_hdmi->color_range)
1468 if (property == connector->dev->mode_config.aspect_ratio_property) {
1470 case DRM_MODE_PICTURE_ASPECT_NONE:
1471 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1473 case DRM_MODE_PICTURE_ASPECT_4_3:
1474 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3;
1476 case DRM_MODE_PICTURE_ASPECT_16_9:
1477 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
1488 if (intel_dig_port->base.base.crtc)
1489 intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
1494 static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
1496 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1497 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1498 struct drm_display_mode *adjusted_mode =
1499 &intel_crtc->config->base.adjusted_mode;
1501 intel_hdmi_prepare(encoder);
1503 intel_hdmi->set_infoframes(&encoder->base,
1504 intel_crtc->config->has_hdmi_sink,
1508 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
1510 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1511 struct intel_hdmi *intel_hdmi = &dport->hdmi;
1512 struct drm_device *dev = encoder->base.dev;
1513 struct drm_i915_private *dev_priv = dev->dev_private;
1514 struct intel_crtc *intel_crtc =
1515 to_intel_crtc(encoder->base.crtc);
1516 struct drm_display_mode *adjusted_mode =
1517 &intel_crtc->config->base.adjusted_mode;
1518 enum dpio_channel port = vlv_dport_to_channel(dport);
1519 int pipe = intel_crtc->pipe;
1522 /* Enable clock channels for this port */
1523 mutex_lock(&dev_priv->sb_lock);
1524 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1531 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1534 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
1535 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
1536 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
1537 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
1538 vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
1539 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
1540 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1541 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1543 /* Program lane clock */
1544 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1545 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1546 mutex_unlock(&dev_priv->sb_lock);
1548 intel_hdmi->set_infoframes(&encoder->base,
1549 intel_crtc->config->has_hdmi_sink,
1552 g4x_enable_hdmi(encoder);
1554 vlv_wait_port_ready(dev_priv, dport, 0x0);
1557 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1559 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1560 struct drm_device *dev = encoder->base.dev;
1561 struct drm_i915_private *dev_priv = dev->dev_private;
1562 struct intel_crtc *intel_crtc =
1563 to_intel_crtc(encoder->base.crtc);
1564 enum dpio_channel port = vlv_dport_to_channel(dport);
1565 int pipe = intel_crtc->pipe;
1567 intel_hdmi_prepare(encoder);
1569 /* Program Tx lane resets to default */
1570 mutex_lock(&dev_priv->sb_lock);
1571 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1572 DPIO_PCS_TX_LANE2_RESET |
1573 DPIO_PCS_TX_LANE1_RESET);
1574 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1575 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1576 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1577 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1578 DPIO_PCS_CLK_SOFT_RESET);
1580 /* Fix up inter-pair skew failure */
1581 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1582 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1583 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1585 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1586 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1587 mutex_unlock(&dev_priv->sb_lock);
1590 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1592 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1593 struct drm_device *dev = encoder->base.dev;
1594 struct drm_i915_private *dev_priv = dev->dev_private;
1595 struct intel_crtc *intel_crtc =
1596 to_intel_crtc(encoder->base.crtc);
1597 enum dpio_channel ch = vlv_dport_to_channel(dport);
1598 enum pipe pipe = intel_crtc->pipe;
1601 intel_hdmi_prepare(encoder);
1603 mutex_lock(&dev_priv->sb_lock);
1605 /* program left/right clock distribution */
1606 if (pipe != PIPE_B) {
1607 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1608 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1610 val |= CHV_BUFLEFTENA1_FORCE;
1612 val |= CHV_BUFRIGHTENA1_FORCE;
1613 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1615 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1616 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1618 val |= CHV_BUFLEFTENA2_FORCE;
1620 val |= CHV_BUFRIGHTENA2_FORCE;
1621 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1624 /* program clock channel usage */
1625 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
1626 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1628 val &= ~CHV_PCS_USEDCLKCHANNEL;
1630 val |= CHV_PCS_USEDCLKCHANNEL;
1631 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
1633 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
1634 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1636 val &= ~CHV_PCS_USEDCLKCHANNEL;
1638 val |= CHV_PCS_USEDCLKCHANNEL;
1639 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
1642 * This a a bit weird since generally CL
1643 * matches the pipe, but here we need to
1644 * pick the CL based on the port.
1646 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
1648 val &= ~CHV_CMN_USEDCLKCHANNEL;
1650 val |= CHV_CMN_USEDCLKCHANNEL;
1651 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
1653 mutex_unlock(&dev_priv->sb_lock);
1656 static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
1658 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1659 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1660 struct intel_crtc *intel_crtc =
1661 to_intel_crtc(encoder->base.crtc);
1662 enum dpio_channel port = vlv_dport_to_channel(dport);
1663 int pipe = intel_crtc->pipe;
1665 /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1666 mutex_lock(&dev_priv->sb_lock);
1667 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
1668 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
1669 mutex_unlock(&dev_priv->sb_lock);
1672 static void chv_hdmi_post_disable(struct intel_encoder *encoder)
1674 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1675 struct drm_device *dev = encoder->base.dev;
1676 struct drm_i915_private *dev_priv = dev->dev_private;
1677 struct intel_crtc *intel_crtc =
1678 to_intel_crtc(encoder->base.crtc);
1679 enum dpio_channel ch = vlv_dport_to_channel(dport);
1680 enum pipe pipe = intel_crtc->pipe;
1683 mutex_lock(&dev_priv->sb_lock);
1685 /* Propagate soft reset to data lane reset */
1686 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
1687 val |= CHV_PCS_REQ_SOFTRESET_EN;
1688 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
1690 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1691 val |= CHV_PCS_REQ_SOFTRESET_EN;
1692 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1694 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
1695 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1696 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
1698 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
1699 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1700 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
1702 mutex_unlock(&dev_priv->sb_lock);
1705 static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
1707 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1708 struct intel_hdmi *intel_hdmi = &dport->hdmi;
1709 struct drm_device *dev = encoder->base.dev;
1710 struct drm_i915_private *dev_priv = dev->dev_private;
1711 struct intel_crtc *intel_crtc =
1712 to_intel_crtc(encoder->base.crtc);
1713 struct drm_display_mode *adjusted_mode =
1714 &intel_crtc->config->base.adjusted_mode;
1715 enum dpio_channel ch = vlv_dport_to_channel(dport);
1716 int pipe = intel_crtc->pipe;
1717 int data, i, stagger;
1720 mutex_lock(&dev_priv->sb_lock);
1722 /* allow hardware to manage TX FIFO reset source */
1723 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
1724 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
1725 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
1727 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
1728 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
1729 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
1731 /* Deassert soft data lane reset*/
1732 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
1733 val |= CHV_PCS_REQ_SOFTRESET_EN;
1734 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
1736 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1737 val |= CHV_PCS_REQ_SOFTRESET_EN;
1738 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1740 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
1741 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1742 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
1744 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
1745 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1746 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
1748 /* Program Tx latency optimal setting */
1749 for (i = 0; i < 4; i++) {
1750 /* Set the upar bit */
1751 data = (i == 1) ? 0x0 : 0x1;
1752 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
1753 data << DPIO_UPAR_SHIFT);
1756 /* Data lane stagger programming */
1757 if (intel_crtc->config->port_clock > 270000)
1759 else if (intel_crtc->config->port_clock > 135000)
1761 else if (intel_crtc->config->port_clock > 67500)
1763 else if (intel_crtc->config->port_clock > 33750)
1768 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
1769 val |= DPIO_TX2_STAGGER_MASK(0x1f);
1770 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
1772 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
1773 val |= DPIO_TX2_STAGGER_MASK(0x1f);
1774 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
1776 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
1777 DPIO_LANESTAGGER_STRAP(stagger) |
1778 DPIO_LANESTAGGER_STRAP_OVRD |
1779 DPIO_TX1_STAGGER_MASK(0x1f) |
1780 DPIO_TX1_STAGGER_MULT(6) |
1781 DPIO_TX2_STAGGER_MULT(0));
1783 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
1784 DPIO_LANESTAGGER_STRAP(stagger) |
1785 DPIO_LANESTAGGER_STRAP_OVRD |
1786 DPIO_TX1_STAGGER_MASK(0x1f) |
1787 DPIO_TX1_STAGGER_MULT(7) |
1788 DPIO_TX2_STAGGER_MULT(5));
1790 /* Clear calc init */
1791 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1792 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
1793 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
1794 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1795 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1797 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1798 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
1799 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
1800 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1801 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1803 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
1804 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
1805 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
1806 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
1808 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
1809 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
1810 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
1811 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
1813 /* FIXME: Program the support xxx V-dB */
1815 for (i = 0; i < 4; i++) {
1816 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
1817 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
1818 val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT;
1819 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
1822 for (i = 0; i < 4; i++) {
1823 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1824 val &= ~DPIO_SWING_MARGIN000_MASK;
1825 val |= 102 << DPIO_SWING_MARGIN000_SHIFT;
1826 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
1829 /* Disable unique transition scale */
1830 for (i = 0; i < 4; i++) {
1831 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
1832 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
1833 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
1836 /* Additional steps for 1200mV-0dB */
1838 val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch));
1840 val |= DPIO_TX_UNIQ_TRANS_SCALE_CH1;
1842 val |= DPIO_TX_UNIQ_TRANS_SCALE_CH0;
1843 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val);
1845 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch),
1846 vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch)) |
1847 (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT));
1849 /* Start swing calculation */
1850 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1851 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1852 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1854 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1855 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1856 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1859 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1860 val |= DPIO_LRC_BYPASS;
1861 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
1863 mutex_unlock(&dev_priv->sb_lock);
1865 intel_hdmi->set_infoframes(&encoder->base,
1866 intel_crtc->config->has_hdmi_sink,
1869 g4x_enable_hdmi(encoder);
1871 vlv_wait_port_ready(dev_priv, dport, 0x0);
1874 static void intel_hdmi_destroy(struct drm_connector *connector)
1876 kfree(to_intel_connector(connector)->detect_edid);
1877 drm_connector_cleanup(connector);
1881 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
1882 .dpms = intel_connector_dpms,
1883 .detect = intel_hdmi_detect,
1884 .force = intel_hdmi_force,
1885 .fill_modes = drm_helper_probe_single_connector_modes,
1886 .set_property = intel_hdmi_set_property,
1887 .atomic_get_property = intel_connector_atomic_get_property,
1888 .destroy = intel_hdmi_destroy,
1889 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1890 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1893 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
1894 .get_modes = intel_hdmi_get_modes,
1895 .mode_valid = intel_hdmi_mode_valid,
1896 .best_encoder = intel_best_encoder,
1899 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
1900 .destroy = intel_encoder_destroy,
1904 intel_attach_aspect_ratio_property(struct drm_connector *connector)
1906 if (!drm_mode_create_aspect_ratio_property(connector->dev))
1907 drm_object_attach_property(&connector->base,
1908 connector->dev->mode_config.aspect_ratio_property,
1909 DRM_MODE_PICTURE_ASPECT_NONE);
1913 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
1915 intel_attach_force_audio_property(connector);
1916 intel_attach_broadcast_rgb_property(connector);
1917 intel_hdmi->color_range_auto = true;
1918 intel_attach_aspect_ratio_property(connector);
1919 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1922 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1923 struct intel_connector *intel_connector)
1925 struct drm_connector *connector = &intel_connector->base;
1926 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
1927 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1928 struct drm_device *dev = intel_encoder->base.dev;
1929 struct drm_i915_private *dev_priv = dev->dev_private;
1930 enum port port = intel_dig_port->port;
1932 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
1933 DRM_MODE_CONNECTOR_HDMIA);
1934 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
1936 connector->interlace_allowed = 1;
1937 connector->doublescan_allowed = 0;
1938 connector->stereo_allowed = 1;
1942 if (IS_BROXTON(dev_priv))
1943 intel_hdmi->ddc_bus = GMBUS_PIN_1_BXT;
1945 intel_hdmi->ddc_bus = GMBUS_PIN_DPB;
1946 intel_encoder->hpd_pin = HPD_PORT_B;
1949 if (IS_BROXTON(dev_priv))
1950 intel_hdmi->ddc_bus = GMBUS_PIN_2_BXT;
1952 intel_hdmi->ddc_bus = GMBUS_PIN_DPC;
1953 intel_encoder->hpd_pin = HPD_PORT_C;
1956 if (WARN_ON(IS_BROXTON(dev_priv)))
1957 intel_hdmi->ddc_bus = GMBUS_PIN_DISABLED;
1958 else if (IS_CHERRYVIEW(dev_priv))
1959 intel_hdmi->ddc_bus = GMBUS_PIN_DPD_CHV;
1961 intel_hdmi->ddc_bus = GMBUS_PIN_DPD;
1962 intel_encoder->hpd_pin = HPD_PORT_D;
1965 intel_encoder->hpd_pin = HPD_PORT_A;
1966 /* Internal port only for eDP. */
1971 if (IS_VALLEYVIEW(dev)) {
1972 intel_hdmi->write_infoframe = vlv_write_infoframe;
1973 intel_hdmi->set_infoframes = vlv_set_infoframes;
1974 intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
1975 } else if (IS_G4X(dev)) {
1976 intel_hdmi->write_infoframe = g4x_write_infoframe;
1977 intel_hdmi->set_infoframes = g4x_set_infoframes;
1978 intel_hdmi->infoframe_enabled = g4x_infoframe_enabled;
1979 } else if (HAS_DDI(dev)) {
1980 intel_hdmi->write_infoframe = hsw_write_infoframe;
1981 intel_hdmi->set_infoframes = hsw_set_infoframes;
1982 intel_hdmi->infoframe_enabled = hsw_infoframe_enabled;
1983 } else if (HAS_PCH_IBX(dev)) {
1984 intel_hdmi->write_infoframe = ibx_write_infoframe;
1985 intel_hdmi->set_infoframes = ibx_set_infoframes;
1986 intel_hdmi->infoframe_enabled = ibx_infoframe_enabled;
1988 intel_hdmi->write_infoframe = cpt_write_infoframe;
1989 intel_hdmi->set_infoframes = cpt_set_infoframes;
1990 intel_hdmi->infoframe_enabled = cpt_infoframe_enabled;
1994 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
1996 intel_connector->get_hw_state = intel_connector_get_hw_state;
1997 intel_connector->unregister = intel_connector_unregister;
1999 intel_hdmi_add_properties(intel_hdmi, connector);
2001 intel_connector_attach_encoder(intel_connector, intel_encoder);
2002 drm_connector_register(connector);
2004 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2005 * 0xd. Failure to do so will result in spurious interrupts being
2006 * generated on the port when a cable is not attached.
2008 if (IS_G4X(dev) && !IS_GM45(dev)) {
2009 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2010 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2014 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
2016 struct intel_digital_port *intel_dig_port;
2017 struct intel_encoder *intel_encoder;
2018 struct intel_connector *intel_connector;
2020 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2021 if (!intel_dig_port)
2024 intel_connector = intel_connector_alloc();
2025 if (!intel_connector) {
2026 kfree(intel_dig_port);
2030 intel_encoder = &intel_dig_port->base;
2032 drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
2033 DRM_MODE_ENCODER_TMDS);
2035 intel_encoder->compute_config = intel_hdmi_compute_config;
2036 if (HAS_PCH_SPLIT(dev)) {
2037 intel_encoder->disable = pch_disable_hdmi;
2038 intel_encoder->post_disable = pch_post_disable_hdmi;
2040 intel_encoder->disable = g4x_disable_hdmi;
2042 intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
2043 intel_encoder->get_config = intel_hdmi_get_config;
2044 if (IS_CHERRYVIEW(dev)) {
2045 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
2046 intel_encoder->pre_enable = chv_hdmi_pre_enable;
2047 intel_encoder->enable = vlv_enable_hdmi;
2048 intel_encoder->post_disable = chv_hdmi_post_disable;
2049 } else if (IS_VALLEYVIEW(dev)) {
2050 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
2051 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
2052 intel_encoder->enable = vlv_enable_hdmi;
2053 intel_encoder->post_disable = vlv_hdmi_post_disable;
2055 intel_encoder->pre_enable = intel_hdmi_pre_enable;
2056 if (HAS_PCH_CPT(dev))
2057 intel_encoder->enable = cpt_enable_hdmi;
2058 else if (HAS_PCH_IBX(dev))
2059 intel_encoder->enable = ibx_enable_hdmi;
2061 intel_encoder->enable = g4x_enable_hdmi;
2064 intel_encoder->type = INTEL_OUTPUT_HDMI;
2065 if (IS_CHERRYVIEW(dev)) {
2067 intel_encoder->crtc_mask = 1 << 2;
2069 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
2071 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2073 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
2075 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
2076 * to work on real hardware. And since g4x can send infoframes to
2077 * only one port anyway, nothing is lost by allowing it.
2080 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
2082 intel_dig_port->port = port;
2083 intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
2084 intel_dig_port->dp.output_reg = 0;
2086 intel_hdmi_init_connector(intel_dig_port, intel_connector);