2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
29 #include <linux/i2c.h>
30 #include <linux/slab.h>
31 #include <linux/delay.h>
32 #include <linux/hdmi.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_edid.h>
37 #include "intel_drv.h"
38 #include <drm/i915_drm.h>
41 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
43 return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
47 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
49 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
50 struct drm_i915_private *dev_priv = dev->dev_private;
51 uint32_t enabled_bits;
53 enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
55 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
56 "HDMI port enabled, expecting disabled\n");
59 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
61 struct intel_digital_port *intel_dig_port =
62 container_of(encoder, struct intel_digital_port, base.base);
63 return &intel_dig_port->hdmi;
66 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
68 return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
71 static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
74 case HDMI_INFOFRAME_TYPE_AVI:
75 return VIDEO_DIP_SELECT_AVI;
76 case HDMI_INFOFRAME_TYPE_SPD:
77 return VIDEO_DIP_SELECT_SPD;
78 case HDMI_INFOFRAME_TYPE_VENDOR:
79 return VIDEO_DIP_SELECT_VENDOR;
81 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
86 static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
89 case HDMI_INFOFRAME_TYPE_AVI:
90 return VIDEO_DIP_ENABLE_AVI;
91 case HDMI_INFOFRAME_TYPE_SPD:
92 return VIDEO_DIP_ENABLE_SPD;
93 case HDMI_INFOFRAME_TYPE_VENDOR:
94 return VIDEO_DIP_ENABLE_VENDOR;
96 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
101 static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
104 case HDMI_INFOFRAME_TYPE_AVI:
105 return VIDEO_DIP_ENABLE_AVI_HSW;
106 case HDMI_INFOFRAME_TYPE_SPD:
107 return VIDEO_DIP_ENABLE_SPD_HSW;
108 case HDMI_INFOFRAME_TYPE_VENDOR:
109 return VIDEO_DIP_ENABLE_VS_HSW;
111 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
116 static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type,
117 enum transcoder cpu_transcoder,
118 struct drm_i915_private *dev_priv)
121 case HDMI_INFOFRAME_TYPE_AVI:
122 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder);
123 case HDMI_INFOFRAME_TYPE_SPD:
124 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder);
125 case HDMI_INFOFRAME_TYPE_VENDOR:
126 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder);
128 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
133 static void g4x_write_infoframe(struct drm_encoder *encoder,
134 enum hdmi_infoframe_type type,
135 const void *frame, ssize_t len)
137 const uint32_t *data = frame;
138 struct drm_device *dev = encoder->dev;
139 struct drm_i915_private *dev_priv = dev->dev_private;
140 u32 val = I915_READ(VIDEO_DIP_CTL);
143 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
145 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
146 val |= g4x_infoframe_index(type);
148 val &= ~g4x_infoframe_enable(type);
150 I915_WRITE(VIDEO_DIP_CTL, val);
153 for (i = 0; i < len; i += 4) {
154 I915_WRITE(VIDEO_DIP_DATA, *data);
157 /* Write every possible data byte to force correct ECC calculation. */
158 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
159 I915_WRITE(VIDEO_DIP_DATA, 0);
162 val |= g4x_infoframe_enable(type);
163 val &= ~VIDEO_DIP_FREQ_MASK;
164 val |= VIDEO_DIP_FREQ_VSYNC;
166 I915_WRITE(VIDEO_DIP_CTL, val);
167 POSTING_READ(VIDEO_DIP_CTL);
170 static bool g4x_infoframe_enabled(struct drm_encoder *encoder)
172 struct drm_device *dev = encoder->dev;
173 struct drm_i915_private *dev_priv = dev->dev_private;
174 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
175 u32 val = I915_READ(VIDEO_DIP_CTL);
177 if ((val & VIDEO_DIP_ENABLE) == 0)
180 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
183 return val & (VIDEO_DIP_ENABLE_AVI |
184 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
187 static void ibx_write_infoframe(struct drm_encoder *encoder,
188 enum hdmi_infoframe_type type,
189 const void *frame, ssize_t len)
191 const uint32_t *data = frame;
192 struct drm_device *dev = encoder->dev;
193 struct drm_i915_private *dev_priv = dev->dev_private;
194 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
195 int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
196 u32 val = I915_READ(reg);
198 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
200 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
201 val |= g4x_infoframe_index(type);
203 val &= ~g4x_infoframe_enable(type);
205 I915_WRITE(reg, val);
208 for (i = 0; i < len; i += 4) {
209 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
212 /* Write every possible data byte to force correct ECC calculation. */
213 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
214 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
217 val |= g4x_infoframe_enable(type);
218 val &= ~VIDEO_DIP_FREQ_MASK;
219 val |= VIDEO_DIP_FREQ_VSYNC;
221 I915_WRITE(reg, val);
225 static bool ibx_infoframe_enabled(struct drm_encoder *encoder)
227 struct drm_device *dev = encoder->dev;
228 struct drm_i915_private *dev_priv = dev->dev_private;
229 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
230 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
231 int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
232 u32 val = I915_READ(reg);
234 if ((val & VIDEO_DIP_ENABLE) == 0)
237 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
240 return val & (VIDEO_DIP_ENABLE_AVI |
241 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
242 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
245 static void cpt_write_infoframe(struct drm_encoder *encoder,
246 enum hdmi_infoframe_type type,
247 const void *frame, ssize_t len)
249 const uint32_t *data = frame;
250 struct drm_device *dev = encoder->dev;
251 struct drm_i915_private *dev_priv = dev->dev_private;
252 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
253 int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
254 u32 val = I915_READ(reg);
256 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
258 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
259 val |= g4x_infoframe_index(type);
261 /* The DIP control register spec says that we need to update the AVI
262 * infoframe without clearing its enable bit */
263 if (type != HDMI_INFOFRAME_TYPE_AVI)
264 val &= ~g4x_infoframe_enable(type);
266 I915_WRITE(reg, val);
269 for (i = 0; i < len; i += 4) {
270 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
273 /* Write every possible data byte to force correct ECC calculation. */
274 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
275 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
278 val |= g4x_infoframe_enable(type);
279 val &= ~VIDEO_DIP_FREQ_MASK;
280 val |= VIDEO_DIP_FREQ_VSYNC;
282 I915_WRITE(reg, val);
286 static bool cpt_infoframe_enabled(struct drm_encoder *encoder)
288 struct drm_device *dev = encoder->dev;
289 struct drm_i915_private *dev_priv = dev->dev_private;
290 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
291 int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
292 u32 val = I915_READ(reg);
294 if ((val & VIDEO_DIP_ENABLE) == 0)
297 return val & (VIDEO_DIP_ENABLE_AVI |
298 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
299 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
302 static void vlv_write_infoframe(struct drm_encoder *encoder,
303 enum hdmi_infoframe_type type,
304 const void *frame, ssize_t len)
306 const uint32_t *data = frame;
307 struct drm_device *dev = encoder->dev;
308 struct drm_i915_private *dev_priv = dev->dev_private;
309 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
310 int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
311 u32 val = I915_READ(reg);
313 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
315 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
316 val |= g4x_infoframe_index(type);
318 val &= ~g4x_infoframe_enable(type);
320 I915_WRITE(reg, val);
323 for (i = 0; i < len; i += 4) {
324 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
327 /* Write every possible data byte to force correct ECC calculation. */
328 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
329 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
332 val |= g4x_infoframe_enable(type);
333 val &= ~VIDEO_DIP_FREQ_MASK;
334 val |= VIDEO_DIP_FREQ_VSYNC;
336 I915_WRITE(reg, val);
340 static bool vlv_infoframe_enabled(struct drm_encoder *encoder)
342 struct drm_device *dev = encoder->dev;
343 struct drm_i915_private *dev_priv = dev->dev_private;
344 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
345 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
346 int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
347 u32 val = I915_READ(reg);
349 if ((val & VIDEO_DIP_ENABLE) == 0)
352 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
355 return val & (VIDEO_DIP_ENABLE_AVI |
356 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
357 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
360 static void hsw_write_infoframe(struct drm_encoder *encoder,
361 enum hdmi_infoframe_type type,
362 const void *frame, ssize_t len)
364 const uint32_t *data = frame;
365 struct drm_device *dev = encoder->dev;
366 struct drm_i915_private *dev_priv = dev->dev_private;
367 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
368 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
371 u32 val = I915_READ(ctl_reg);
373 data_reg = hsw_infoframe_data_reg(type,
374 intel_crtc->config->cpu_transcoder,
379 val &= ~hsw_infoframe_enable(type);
380 I915_WRITE(ctl_reg, val);
383 for (i = 0; i < len; i += 4) {
384 I915_WRITE(data_reg + i, *data);
387 /* Write every possible data byte to force correct ECC calculation. */
388 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
389 I915_WRITE(data_reg + i, 0);
392 val |= hsw_infoframe_enable(type);
393 I915_WRITE(ctl_reg, val);
394 POSTING_READ(ctl_reg);
397 static bool hsw_infoframe_enabled(struct drm_encoder *encoder)
399 struct drm_device *dev = encoder->dev;
400 struct drm_i915_private *dev_priv = dev->dev_private;
401 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
402 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
403 u32 val = I915_READ(ctl_reg);
405 return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
406 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
407 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
411 * The data we write to the DIP data buffer registers is 1 byte bigger than the
412 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
413 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
414 * used for both technologies.
416 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
417 * DW1: DB3 | DB2 | DB1 | DB0
418 * DW2: DB7 | DB6 | DB5 | DB4
421 * (HB is Header Byte, DB is Data Byte)
423 * The hdmi pack() functions don't know about that hardware specific hole so we
424 * trick them by giving an offset into the buffer and moving back the header
427 static void intel_write_infoframe(struct drm_encoder *encoder,
428 union hdmi_infoframe *frame)
430 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
431 uint8_t buffer[VIDEO_DIP_DATA_SIZE];
434 /* see comment above for the reason for this offset */
435 len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
439 /* Insert the 'hole' (see big comment above) at position 3 */
440 buffer[0] = buffer[1];
441 buffer[1] = buffer[2];
442 buffer[2] = buffer[3];
446 intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);
449 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
450 struct drm_display_mode *adjusted_mode)
452 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
453 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
454 union hdmi_infoframe frame;
457 /* Set user selected PAR to incoming mode's member */
458 adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio;
460 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
463 DRM_ERROR("couldn't fill AVI infoframe\n");
467 if (intel_hdmi->rgb_quant_range_selectable) {
468 if (intel_crtc->config->limited_color_range)
469 frame.avi.quantization_range =
470 HDMI_QUANTIZATION_RANGE_LIMITED;
472 frame.avi.quantization_range =
473 HDMI_QUANTIZATION_RANGE_FULL;
476 intel_write_infoframe(encoder, &frame);
479 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
481 union hdmi_infoframe frame;
484 ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
486 DRM_ERROR("couldn't fill SPD infoframe\n");
490 frame.spd.sdi = HDMI_SPD_SDI_PC;
492 intel_write_infoframe(encoder, &frame);
496 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
497 struct drm_display_mode *adjusted_mode)
499 union hdmi_infoframe frame;
502 ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
507 intel_write_infoframe(encoder, &frame);
510 static void g4x_set_infoframes(struct drm_encoder *encoder,
512 struct drm_display_mode *adjusted_mode)
514 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
515 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
516 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
517 u32 reg = VIDEO_DIP_CTL;
518 u32 val = I915_READ(reg);
519 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
521 assert_hdmi_port_disabled(intel_hdmi);
523 /* If the registers were not initialized yet, they might be zeroes,
524 * which means we're selecting the AVI DIP and we're setting its
525 * frequency to once. This seems to really confuse the HW and make
526 * things stop working (the register spec says the AVI always needs to
527 * be sent every VSync). So here we avoid writing to the register more
528 * than we need and also explicitly select the AVI DIP and explicitly
529 * set its frequency to every VSync. Avoiding to write it twice seems to
530 * be enough to solve the problem, but being defensive shouldn't hurt us
532 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
535 if (!(val & VIDEO_DIP_ENABLE))
537 if (port != (val & VIDEO_DIP_PORT_MASK)) {
538 DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
539 (val & VIDEO_DIP_PORT_MASK) >> 29);
542 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
543 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
544 I915_WRITE(reg, val);
549 if (port != (val & VIDEO_DIP_PORT_MASK)) {
550 if (val & VIDEO_DIP_ENABLE) {
551 DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
552 (val & VIDEO_DIP_PORT_MASK) >> 29);
555 val &= ~VIDEO_DIP_PORT_MASK;
559 val |= VIDEO_DIP_ENABLE;
560 val &= ~(VIDEO_DIP_ENABLE_AVI |
561 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
563 I915_WRITE(reg, val);
566 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
567 intel_hdmi_set_spd_infoframe(encoder);
568 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
571 static bool hdmi_sink_is_deep_color(struct drm_encoder *encoder)
573 struct drm_device *dev = encoder->dev;
574 struct drm_connector *connector;
576 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
579 * HDMI cloning is only supported on g4x which doesn't
580 * support deep color or GCP infoframes anyway so no
581 * need to worry about multiple HDMI sinks here.
583 list_for_each_entry(connector, &dev->mode_config.connector_list, head)
584 if (connector->encoder == encoder)
585 return connector->display_info.bpc > 8;
591 * Determine if default_phase=1 can be indicated in the GCP infoframe.
593 * From HDMI specification 1.4a:
594 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
595 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
596 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
597 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
600 static bool gcp_default_phase_possible(int pipe_bpp,
601 const struct drm_display_mode *mode)
603 unsigned int pixels_per_group;
607 /* 4 pixels in 5 clocks */
608 pixels_per_group = 4;
611 /* 2 pixels in 3 clocks */
612 pixels_per_group = 2;
615 /* 1 pixel in 2 clocks */
616 pixels_per_group = 1;
619 /* phase information not relevant for 8bpc */
623 return mode->crtc_hdisplay % pixels_per_group == 0 &&
624 mode->crtc_htotal % pixels_per_group == 0 &&
625 mode->crtc_hblank_start % pixels_per_group == 0 &&
626 mode->crtc_hblank_end % pixels_per_group == 0 &&
627 mode->crtc_hsync_start % pixels_per_group == 0 &&
628 mode->crtc_hsync_end % pixels_per_group == 0 &&
629 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
630 mode->crtc_htotal/2 % pixels_per_group == 0);
633 static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder)
635 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
636 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
639 if (HAS_DDI(dev_priv))
640 reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder);
641 else if (IS_VALLEYVIEW(dev_priv))
642 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
643 else if (HAS_PCH_SPLIT(dev_priv->dev))
644 reg = TVIDEO_DIP_GCP(crtc->pipe);
648 /* Indicate color depth whenever the sink supports deep color */
649 if (hdmi_sink_is_deep_color(encoder))
650 val |= GCP_COLOR_INDICATION;
652 /* Enable default_phase whenever the display mode is suitably aligned */
653 if (gcp_default_phase_possible(crtc->config->pipe_bpp,
654 &crtc->config->base.adjusted_mode))
655 val |= GCP_DEFAULT_PHASE_ENABLE;
657 I915_WRITE(reg, val);
662 static void ibx_set_infoframes(struct drm_encoder *encoder,
664 struct drm_display_mode *adjusted_mode)
666 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
667 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
668 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
669 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
670 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
671 u32 val = I915_READ(reg);
672 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
674 assert_hdmi_port_disabled(intel_hdmi);
676 /* See the big comment in g4x_set_infoframes() */
677 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
680 if (!(val & VIDEO_DIP_ENABLE))
682 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
683 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
684 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
685 I915_WRITE(reg, val);
690 if (port != (val & VIDEO_DIP_PORT_MASK)) {
691 WARN(val & VIDEO_DIP_ENABLE,
692 "DIP already enabled on port %c\n",
693 (val & VIDEO_DIP_PORT_MASK) >> 29);
694 val &= ~VIDEO_DIP_PORT_MASK;
698 val |= VIDEO_DIP_ENABLE;
699 val &= ~(VIDEO_DIP_ENABLE_AVI |
700 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
701 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
703 if (intel_hdmi_set_gcp_infoframe(encoder))
704 val |= VIDEO_DIP_ENABLE_GCP;
706 I915_WRITE(reg, val);
709 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
710 intel_hdmi_set_spd_infoframe(encoder);
711 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
714 static void cpt_set_infoframes(struct drm_encoder *encoder,
716 struct drm_display_mode *adjusted_mode)
718 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
719 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
720 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
721 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
722 u32 val = I915_READ(reg);
724 assert_hdmi_port_disabled(intel_hdmi);
726 /* See the big comment in g4x_set_infoframes() */
727 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
730 if (!(val & VIDEO_DIP_ENABLE))
732 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
733 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
734 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
735 I915_WRITE(reg, val);
740 /* Set both together, unset both together: see the spec. */
741 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
742 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
743 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
745 if (intel_hdmi_set_gcp_infoframe(encoder))
746 val |= VIDEO_DIP_ENABLE_GCP;
748 I915_WRITE(reg, val);
751 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
752 intel_hdmi_set_spd_infoframe(encoder);
753 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
756 static void vlv_set_infoframes(struct drm_encoder *encoder,
758 struct drm_display_mode *adjusted_mode)
760 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
761 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
762 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
763 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
764 u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
765 u32 val = I915_READ(reg);
766 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
768 assert_hdmi_port_disabled(intel_hdmi);
770 /* See the big comment in g4x_set_infoframes() */
771 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
774 if (!(val & VIDEO_DIP_ENABLE))
776 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
777 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
778 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
779 I915_WRITE(reg, val);
784 if (port != (val & VIDEO_DIP_PORT_MASK)) {
785 WARN(val & VIDEO_DIP_ENABLE,
786 "DIP already enabled on port %c\n",
787 (val & VIDEO_DIP_PORT_MASK) >> 29);
788 val &= ~VIDEO_DIP_PORT_MASK;
792 val |= VIDEO_DIP_ENABLE;
793 val &= ~(VIDEO_DIP_ENABLE_AVI |
794 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
795 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
797 if (intel_hdmi_set_gcp_infoframe(encoder))
798 val |= VIDEO_DIP_ENABLE_GCP;
800 I915_WRITE(reg, val);
803 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
804 intel_hdmi_set_spd_infoframe(encoder);
805 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
808 static void hsw_set_infoframes(struct drm_encoder *encoder,
810 struct drm_display_mode *adjusted_mode)
812 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
813 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
814 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
815 u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
816 u32 val = I915_READ(reg);
818 assert_hdmi_port_disabled(intel_hdmi);
820 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
821 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
822 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
825 I915_WRITE(reg, val);
830 if (intel_hdmi_set_gcp_infoframe(encoder))
831 val |= VIDEO_DIP_ENABLE_GCP_HSW;
833 I915_WRITE(reg, val);
836 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
837 intel_hdmi_set_spd_infoframe(encoder);
838 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
841 static void intel_hdmi_prepare(struct intel_encoder *encoder)
843 struct drm_device *dev = encoder->base.dev;
844 struct drm_i915_private *dev_priv = dev->dev_private;
845 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
846 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
847 struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
850 hdmi_val = SDVO_ENCODING_HDMI;
851 if (!HAS_PCH_SPLIT(dev))
852 hdmi_val |= intel_hdmi->color_range;
853 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
854 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
855 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
856 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
858 if (crtc->config->pipe_bpp > 24)
859 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
861 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
863 if (crtc->config->has_hdmi_sink)
864 hdmi_val |= HDMI_MODE_SELECT_HDMI;
866 if (HAS_PCH_CPT(dev))
867 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
868 else if (IS_CHERRYVIEW(dev))
869 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
871 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
873 I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
874 POSTING_READ(intel_hdmi->hdmi_reg);
877 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
880 struct drm_device *dev = encoder->base.dev;
881 struct drm_i915_private *dev_priv = dev->dev_private;
882 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
883 enum intel_display_power_domain power_domain;
886 power_domain = intel_display_port_power_domain(encoder);
887 if (!intel_display_power_is_enabled(dev_priv, power_domain))
890 tmp = I915_READ(intel_hdmi->hdmi_reg);
892 if (!(tmp & SDVO_ENABLE))
895 if (HAS_PCH_CPT(dev))
896 *pipe = PORT_TO_PIPE_CPT(tmp);
897 else if (IS_CHERRYVIEW(dev))
898 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
900 *pipe = PORT_TO_PIPE(tmp);
905 static void intel_hdmi_get_config(struct intel_encoder *encoder,
906 struct intel_crtc_state *pipe_config)
908 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
909 struct drm_device *dev = encoder->base.dev;
910 struct drm_i915_private *dev_priv = dev->dev_private;
914 tmp = I915_READ(intel_hdmi->hdmi_reg);
916 if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
917 flags |= DRM_MODE_FLAG_PHSYNC;
919 flags |= DRM_MODE_FLAG_NHSYNC;
921 if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
922 flags |= DRM_MODE_FLAG_PVSYNC;
924 flags |= DRM_MODE_FLAG_NVSYNC;
926 if (tmp & HDMI_MODE_SELECT_HDMI)
927 pipe_config->has_hdmi_sink = true;
929 if (intel_hdmi->infoframe_enabled(&encoder->base))
930 pipe_config->has_infoframe = true;
932 if (tmp & SDVO_AUDIO_ENABLE)
933 pipe_config->has_audio = true;
935 if (!HAS_PCH_SPLIT(dev) &&
936 tmp & HDMI_COLOR_RANGE_16_235)
937 pipe_config->limited_color_range = true;
939 pipe_config->base.adjusted_mode.flags |= flags;
941 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
942 dotclock = pipe_config->port_clock * 2 / 3;
944 dotclock = pipe_config->port_clock;
946 if (pipe_config->pixel_multiplier)
947 dotclock /= pipe_config->pixel_multiplier;
949 if (HAS_PCH_SPLIT(dev_priv->dev))
950 ironlake_check_encoder_dotclock(pipe_config, dotclock);
952 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
955 static void intel_enable_hdmi_audio(struct intel_encoder *encoder)
957 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
959 WARN_ON(!crtc->config->has_hdmi_sink);
960 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
961 pipe_name(crtc->pipe));
962 intel_audio_codec_enable(encoder);
965 static void g4x_enable_hdmi(struct intel_encoder *encoder)
967 struct drm_device *dev = encoder->base.dev;
968 struct drm_i915_private *dev_priv = dev->dev_private;
969 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
970 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
973 temp = I915_READ(intel_hdmi->hdmi_reg);
976 if (crtc->config->has_audio)
977 temp |= SDVO_AUDIO_ENABLE;
979 I915_WRITE(intel_hdmi->hdmi_reg, temp);
980 POSTING_READ(intel_hdmi->hdmi_reg);
982 if (crtc->config->has_audio)
983 intel_enable_hdmi_audio(encoder);
986 static void ibx_enable_hdmi(struct intel_encoder *encoder)
988 struct drm_device *dev = encoder->base.dev;
989 struct drm_i915_private *dev_priv = dev->dev_private;
990 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
991 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
994 temp = I915_READ(intel_hdmi->hdmi_reg);
997 if (crtc->config->has_audio)
998 temp |= SDVO_AUDIO_ENABLE;
1001 * HW workaround, need to write this twice for issue
1002 * that may result in first write getting masked.
1004 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1005 POSTING_READ(intel_hdmi->hdmi_reg);
1006 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1007 POSTING_READ(intel_hdmi->hdmi_reg);
1010 * HW workaround, need to toggle enable bit off and on
1011 * for 12bpc with pixel repeat.
1013 * FIXME: BSpec says this should be done at the end of
1014 * of the modeset sequence, so not sure if this isn't too soon.
1016 if (crtc->config->pipe_bpp > 24 &&
1017 crtc->config->pixel_multiplier > 1) {
1018 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1019 POSTING_READ(intel_hdmi->hdmi_reg);
1022 * HW workaround, need to write this twice for issue
1023 * that may result in first write getting masked.
1025 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1026 POSTING_READ(intel_hdmi->hdmi_reg);
1027 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1028 POSTING_READ(intel_hdmi->hdmi_reg);
1031 if (crtc->config->has_audio)
1032 intel_enable_hdmi_audio(encoder);
1035 static void cpt_enable_hdmi(struct intel_encoder *encoder)
1037 struct drm_device *dev = encoder->base.dev;
1038 struct drm_i915_private *dev_priv = dev->dev_private;
1039 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1040 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1041 enum pipe pipe = crtc->pipe;
1044 temp = I915_READ(intel_hdmi->hdmi_reg);
1046 temp |= SDVO_ENABLE;
1047 if (crtc->config->has_audio)
1048 temp |= SDVO_AUDIO_ENABLE;
1051 * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1053 * The procedure for 12bpc is as follows:
1054 * 1. disable HDMI clock gating
1055 * 2. enable HDMI with 8bpc
1056 * 3. enable HDMI with 12bpc
1057 * 4. enable HDMI clock gating
1060 if (crtc->config->pipe_bpp > 24) {
1061 I915_WRITE(TRANS_CHICKEN1(pipe),
1062 I915_READ(TRANS_CHICKEN1(pipe)) |
1063 TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1065 temp &= ~SDVO_COLOR_FORMAT_MASK;
1066 temp |= SDVO_COLOR_FORMAT_8bpc;
1069 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1070 POSTING_READ(intel_hdmi->hdmi_reg);
1072 if (crtc->config->pipe_bpp > 24) {
1073 temp &= ~SDVO_COLOR_FORMAT_MASK;
1074 temp |= HDMI_COLOR_FORMAT_12bpc;
1076 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1077 POSTING_READ(intel_hdmi->hdmi_reg);
1079 I915_WRITE(TRANS_CHICKEN1(pipe),
1080 I915_READ(TRANS_CHICKEN1(pipe)) &
1081 ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1084 if (crtc->config->has_audio)
1085 intel_enable_hdmi_audio(encoder);
1088 static void vlv_enable_hdmi(struct intel_encoder *encoder)
1092 static void intel_disable_hdmi(struct intel_encoder *encoder)
1094 struct drm_device *dev = encoder->base.dev;
1095 struct drm_i915_private *dev_priv = dev->dev_private;
1096 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1097 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1100 temp = I915_READ(intel_hdmi->hdmi_reg);
1102 temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
1103 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1104 POSTING_READ(intel_hdmi->hdmi_reg);
1107 * HW workaround for IBX, we need to move the port
1108 * to transcoder A after disabling it to allow the
1109 * matching DP port to be enabled on transcoder A.
1111 if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) {
1112 temp &= ~SDVO_PIPE_B_SELECT;
1113 temp |= SDVO_ENABLE;
1115 * HW workaround, need to write this twice for issue
1116 * that may result in first write getting masked.
1118 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1119 POSTING_READ(intel_hdmi->hdmi_reg);
1120 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1121 POSTING_READ(intel_hdmi->hdmi_reg);
1123 temp &= ~SDVO_ENABLE;
1124 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1125 POSTING_READ(intel_hdmi->hdmi_reg);
1128 intel_hdmi->set_infoframes(&encoder->base, false, NULL);
1131 static void g4x_disable_hdmi(struct intel_encoder *encoder)
1133 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1135 if (crtc->config->has_audio)
1136 intel_audio_codec_disable(encoder);
1138 intel_disable_hdmi(encoder);
1141 static void pch_disable_hdmi(struct intel_encoder *encoder)
1143 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1145 if (crtc->config->has_audio)
1146 intel_audio_codec_disable(encoder);
1149 static void pch_post_disable_hdmi(struct intel_encoder *encoder)
1151 intel_disable_hdmi(encoder);
1154 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit)
1156 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1158 if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev))
1160 else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8)
1166 static enum drm_mode_status
1167 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1168 int clock, bool respect_dvi_limit)
1170 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1173 return MODE_CLOCK_LOW;
1174 if (clock > hdmi_port_clock_limit(hdmi, respect_dvi_limit))
1175 return MODE_CLOCK_HIGH;
1177 /* CHV/BXT DPLL can't generate 216-240 MHz */
1178 if ((IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) &&
1179 clock > 216000 && clock < 240000)
1180 return MODE_CLOCK_RANGE;
1185 static enum drm_mode_status
1186 intel_hdmi_mode_valid(struct drm_connector *connector,
1187 struct drm_display_mode *mode)
1189 struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1190 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1191 enum drm_mode_status status;
1194 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1195 return MODE_NO_DBLESCAN;
1197 clock = mode->clock;
1198 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1201 /* check if we can do 8bpc */
1202 status = hdmi_port_clock_valid(hdmi, clock, true);
1204 /* if we can't do 8bpc we may still be able to do 12bpc */
1205 if (!HAS_GMCH_DISPLAY(dev) && status != MODE_OK)
1206 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true);
1211 static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)
1213 struct drm_device *dev = crtc_state->base.crtc->dev;
1214 struct drm_atomic_state *state;
1215 struct intel_encoder *encoder;
1216 struct drm_connector *connector;
1217 struct drm_connector_state *connector_state;
1218 int count = 0, count_hdmi = 0;
1221 if (HAS_GMCH_DISPLAY(dev))
1224 state = crtc_state->base.state;
1226 for_each_connector_in_state(state, connector, connector_state, i) {
1227 if (connector_state->crtc != crtc_state->base.crtc)
1230 encoder = to_intel_encoder(connector_state->best_encoder);
1232 count_hdmi += encoder->type == INTEL_OUTPUT_HDMI;
1237 * HDMI 12bpc affects the clocks, so it's only possible
1238 * when not cloning with other encoder types.
1240 return count_hdmi > 0 && count_hdmi == count;
1243 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1244 struct intel_crtc_state *pipe_config)
1246 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1247 struct drm_device *dev = encoder->base.dev;
1248 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1249 int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
1250 int clock_12bpc = clock_8bpc * 3 / 2;
1253 pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink;
1255 if (pipe_config->has_hdmi_sink)
1256 pipe_config->has_infoframe = true;
1258 if (intel_hdmi->color_range_auto) {
1259 /* See CEA-861-E - 5.1 Default Encoding Parameters */
1260 if (pipe_config->has_hdmi_sink &&
1261 drm_match_cea_mode(adjusted_mode) > 1)
1262 intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
1264 intel_hdmi->color_range = 0;
1267 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
1268 pipe_config->pixel_multiplier = 2;
1273 if (intel_hdmi->color_range)
1274 pipe_config->limited_color_range = true;
1276 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
1277 pipe_config->has_pch_encoder = true;
1279 if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio)
1280 pipe_config->has_audio = true;
1283 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
1284 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
1285 * outputs. We also need to check that the higher clock still fits
1288 if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink &&
1289 hdmi_port_clock_valid(intel_hdmi, clock_12bpc, false) == MODE_OK &&
1290 hdmi_12bpc_possible(pipe_config)) {
1291 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
1294 /* Need to adjust the port link by 1.5x for 12bpc. */
1295 pipe_config->port_clock = clock_12bpc;
1297 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
1300 pipe_config->port_clock = clock_8bpc;
1303 if (!pipe_config->bw_constrained) {
1304 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
1305 pipe_config->pipe_bpp = desired_bpp;
1308 if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
1309 false) != MODE_OK) {
1310 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
1318 intel_hdmi_unset_edid(struct drm_connector *connector)
1320 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1322 intel_hdmi->has_hdmi_sink = false;
1323 intel_hdmi->has_audio = false;
1324 intel_hdmi->rgb_quant_range_selectable = false;
1326 kfree(to_intel_connector(connector)->detect_edid);
1327 to_intel_connector(connector)->detect_edid = NULL;
1331 intel_hdmi_set_edid(struct drm_connector *connector)
1333 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1334 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1335 struct intel_encoder *intel_encoder =
1336 &hdmi_to_dig_port(intel_hdmi)->base;
1337 enum intel_display_power_domain power_domain;
1339 bool connected = false;
1341 power_domain = intel_display_port_power_domain(intel_encoder);
1342 intel_display_power_get(dev_priv, power_domain);
1344 edid = drm_get_edid(connector,
1345 intel_gmbus_get_adapter(dev_priv,
1346 intel_hdmi->ddc_bus));
1348 intel_display_power_put(dev_priv, power_domain);
1350 to_intel_connector(connector)->detect_edid = edid;
1351 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
1352 intel_hdmi->rgb_quant_range_selectable =
1353 drm_rgb_quant_range_selectable(edid);
1355 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
1356 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
1357 intel_hdmi->has_audio =
1358 intel_hdmi->force_audio == HDMI_AUDIO_ON;
1360 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
1361 intel_hdmi->has_hdmi_sink =
1362 drm_detect_hdmi_monitor(edid);
1370 static enum drm_connector_status
1371 intel_hdmi_detect(struct drm_connector *connector, bool force)
1373 enum drm_connector_status status;
1375 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1376 connector->base.id, connector->name);
1378 intel_hdmi_unset_edid(connector);
1380 if (intel_hdmi_set_edid(connector)) {
1381 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1383 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1384 status = connector_status_connected;
1386 status = connector_status_disconnected;
1392 intel_hdmi_force(struct drm_connector *connector)
1394 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1396 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1397 connector->base.id, connector->name);
1399 intel_hdmi_unset_edid(connector);
1401 if (connector->status != connector_status_connected)
1404 intel_hdmi_set_edid(connector);
1405 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1408 static int intel_hdmi_get_modes(struct drm_connector *connector)
1412 edid = to_intel_connector(connector)->detect_edid;
1416 return intel_connector_update_modes(connector, edid);
1420 intel_hdmi_detect_audio(struct drm_connector *connector)
1422 bool has_audio = false;
1425 edid = to_intel_connector(connector)->detect_edid;
1426 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL)
1427 has_audio = drm_detect_monitor_audio(edid);
1433 intel_hdmi_set_property(struct drm_connector *connector,
1434 struct drm_property *property,
1437 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1438 struct intel_digital_port *intel_dig_port =
1439 hdmi_to_dig_port(intel_hdmi);
1440 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1443 ret = drm_object_property_set_value(&connector->base, property, val);
1447 if (property == dev_priv->force_audio_property) {
1448 enum hdmi_force_audio i = val;
1451 if (i == intel_hdmi->force_audio)
1454 intel_hdmi->force_audio = i;
1456 if (i == HDMI_AUDIO_AUTO)
1457 has_audio = intel_hdmi_detect_audio(connector);
1459 has_audio = (i == HDMI_AUDIO_ON);
1461 if (i == HDMI_AUDIO_OFF_DVI)
1462 intel_hdmi->has_hdmi_sink = 0;
1464 intel_hdmi->has_audio = has_audio;
1468 if (property == dev_priv->broadcast_rgb_property) {
1469 bool old_auto = intel_hdmi->color_range_auto;
1470 uint32_t old_range = intel_hdmi->color_range;
1473 case INTEL_BROADCAST_RGB_AUTO:
1474 intel_hdmi->color_range_auto = true;
1476 case INTEL_BROADCAST_RGB_FULL:
1477 intel_hdmi->color_range_auto = false;
1478 intel_hdmi->color_range = 0;
1480 case INTEL_BROADCAST_RGB_LIMITED:
1481 intel_hdmi->color_range_auto = false;
1482 intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
1488 if (old_auto == intel_hdmi->color_range_auto &&
1489 old_range == intel_hdmi->color_range)
1495 if (property == connector->dev->mode_config.aspect_ratio_property) {
1497 case DRM_MODE_PICTURE_ASPECT_NONE:
1498 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1500 case DRM_MODE_PICTURE_ASPECT_4_3:
1501 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3;
1503 case DRM_MODE_PICTURE_ASPECT_16_9:
1504 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
1515 if (intel_dig_port->base.base.crtc)
1516 intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
1521 static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
1523 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1524 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1525 struct drm_display_mode *adjusted_mode =
1526 &intel_crtc->config->base.adjusted_mode;
1528 intel_hdmi_prepare(encoder);
1530 intel_hdmi->set_infoframes(&encoder->base,
1531 intel_crtc->config->has_hdmi_sink,
1535 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
1537 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1538 struct intel_hdmi *intel_hdmi = &dport->hdmi;
1539 struct drm_device *dev = encoder->base.dev;
1540 struct drm_i915_private *dev_priv = dev->dev_private;
1541 struct intel_crtc *intel_crtc =
1542 to_intel_crtc(encoder->base.crtc);
1543 struct drm_display_mode *adjusted_mode =
1544 &intel_crtc->config->base.adjusted_mode;
1545 enum dpio_channel port = vlv_dport_to_channel(dport);
1546 int pipe = intel_crtc->pipe;
1549 /* Enable clock channels for this port */
1550 mutex_lock(&dev_priv->sb_lock);
1551 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1558 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1561 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
1562 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
1563 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
1564 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
1565 vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
1566 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
1567 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1568 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1570 /* Program lane clock */
1571 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1572 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1573 mutex_unlock(&dev_priv->sb_lock);
1575 intel_hdmi->set_infoframes(&encoder->base,
1576 intel_crtc->config->has_hdmi_sink,
1579 g4x_enable_hdmi(encoder);
1581 vlv_wait_port_ready(dev_priv, dport, 0x0);
1584 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1586 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1587 struct drm_device *dev = encoder->base.dev;
1588 struct drm_i915_private *dev_priv = dev->dev_private;
1589 struct intel_crtc *intel_crtc =
1590 to_intel_crtc(encoder->base.crtc);
1591 enum dpio_channel port = vlv_dport_to_channel(dport);
1592 int pipe = intel_crtc->pipe;
1594 intel_hdmi_prepare(encoder);
1596 /* Program Tx lane resets to default */
1597 mutex_lock(&dev_priv->sb_lock);
1598 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1599 DPIO_PCS_TX_LANE2_RESET |
1600 DPIO_PCS_TX_LANE1_RESET);
1601 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1602 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1603 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1604 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1605 DPIO_PCS_CLK_SOFT_RESET);
1607 /* Fix up inter-pair skew failure */
1608 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1609 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1610 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1612 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1613 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1614 mutex_unlock(&dev_priv->sb_lock);
1617 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1619 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1620 struct drm_device *dev = encoder->base.dev;
1621 struct drm_i915_private *dev_priv = dev->dev_private;
1622 struct intel_crtc *intel_crtc =
1623 to_intel_crtc(encoder->base.crtc);
1624 enum dpio_channel ch = vlv_dport_to_channel(dport);
1625 enum pipe pipe = intel_crtc->pipe;
1628 intel_hdmi_prepare(encoder);
1630 mutex_lock(&dev_priv->sb_lock);
1632 /* program left/right clock distribution */
1633 if (pipe != PIPE_B) {
1634 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1635 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1637 val |= CHV_BUFLEFTENA1_FORCE;
1639 val |= CHV_BUFRIGHTENA1_FORCE;
1640 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1642 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1643 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1645 val |= CHV_BUFLEFTENA2_FORCE;
1647 val |= CHV_BUFRIGHTENA2_FORCE;
1648 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1651 /* program clock channel usage */
1652 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
1653 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1655 val &= ~CHV_PCS_USEDCLKCHANNEL;
1657 val |= CHV_PCS_USEDCLKCHANNEL;
1658 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
1660 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
1661 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1663 val &= ~CHV_PCS_USEDCLKCHANNEL;
1665 val |= CHV_PCS_USEDCLKCHANNEL;
1666 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
1669 * This a a bit weird since generally CL
1670 * matches the pipe, but here we need to
1671 * pick the CL based on the port.
1673 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
1675 val &= ~CHV_CMN_USEDCLKCHANNEL;
1677 val |= CHV_CMN_USEDCLKCHANNEL;
1678 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
1680 mutex_unlock(&dev_priv->sb_lock);
1683 static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
1685 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1686 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1687 struct intel_crtc *intel_crtc =
1688 to_intel_crtc(encoder->base.crtc);
1689 enum dpio_channel port = vlv_dport_to_channel(dport);
1690 int pipe = intel_crtc->pipe;
1692 /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1693 mutex_lock(&dev_priv->sb_lock);
1694 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
1695 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
1696 mutex_unlock(&dev_priv->sb_lock);
1699 static void chv_hdmi_post_disable(struct intel_encoder *encoder)
1701 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1702 struct drm_device *dev = encoder->base.dev;
1703 struct drm_i915_private *dev_priv = dev->dev_private;
1704 struct intel_crtc *intel_crtc =
1705 to_intel_crtc(encoder->base.crtc);
1706 enum dpio_channel ch = vlv_dport_to_channel(dport);
1707 enum pipe pipe = intel_crtc->pipe;
1710 mutex_lock(&dev_priv->sb_lock);
1712 /* Propagate soft reset to data lane reset */
1713 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
1714 val |= CHV_PCS_REQ_SOFTRESET_EN;
1715 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
1717 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1718 val |= CHV_PCS_REQ_SOFTRESET_EN;
1719 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1721 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
1722 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1723 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
1725 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
1726 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1727 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
1729 mutex_unlock(&dev_priv->sb_lock);
1732 static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
1734 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1735 struct intel_hdmi *intel_hdmi = &dport->hdmi;
1736 struct drm_device *dev = encoder->base.dev;
1737 struct drm_i915_private *dev_priv = dev->dev_private;
1738 struct intel_crtc *intel_crtc =
1739 to_intel_crtc(encoder->base.crtc);
1740 struct drm_display_mode *adjusted_mode =
1741 &intel_crtc->config->base.adjusted_mode;
1742 enum dpio_channel ch = vlv_dport_to_channel(dport);
1743 int pipe = intel_crtc->pipe;
1744 int data, i, stagger;
1747 mutex_lock(&dev_priv->sb_lock);
1749 /* allow hardware to manage TX FIFO reset source */
1750 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
1751 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
1752 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
1754 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
1755 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
1756 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
1758 /* Deassert soft data lane reset*/
1759 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
1760 val |= CHV_PCS_REQ_SOFTRESET_EN;
1761 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
1763 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1764 val |= CHV_PCS_REQ_SOFTRESET_EN;
1765 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1767 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
1768 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1769 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
1771 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
1772 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1773 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
1775 /* Program Tx latency optimal setting */
1776 for (i = 0; i < 4; i++) {
1777 /* Set the upar bit */
1778 data = (i == 1) ? 0x0 : 0x1;
1779 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
1780 data << DPIO_UPAR_SHIFT);
1783 /* Data lane stagger programming */
1784 if (intel_crtc->config->port_clock > 270000)
1786 else if (intel_crtc->config->port_clock > 135000)
1788 else if (intel_crtc->config->port_clock > 67500)
1790 else if (intel_crtc->config->port_clock > 33750)
1795 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
1796 val |= DPIO_TX2_STAGGER_MASK(0x1f);
1797 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
1799 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
1800 val |= DPIO_TX2_STAGGER_MASK(0x1f);
1801 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
1803 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
1804 DPIO_LANESTAGGER_STRAP(stagger) |
1805 DPIO_LANESTAGGER_STRAP_OVRD |
1806 DPIO_TX1_STAGGER_MASK(0x1f) |
1807 DPIO_TX1_STAGGER_MULT(6) |
1808 DPIO_TX2_STAGGER_MULT(0));
1810 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
1811 DPIO_LANESTAGGER_STRAP(stagger) |
1812 DPIO_LANESTAGGER_STRAP_OVRD |
1813 DPIO_TX1_STAGGER_MASK(0x1f) |
1814 DPIO_TX1_STAGGER_MULT(7) |
1815 DPIO_TX2_STAGGER_MULT(5));
1817 /* Clear calc init */
1818 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1819 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
1820 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
1821 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1822 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1824 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1825 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
1826 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
1827 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1828 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1830 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
1831 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
1832 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
1833 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
1835 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
1836 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
1837 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
1838 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
1840 /* FIXME: Program the support xxx V-dB */
1842 for (i = 0; i < 4; i++) {
1843 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
1844 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
1845 val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT;
1846 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
1849 for (i = 0; i < 4; i++) {
1850 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1851 val &= ~DPIO_SWING_MARGIN000_MASK;
1852 val |= 102 << DPIO_SWING_MARGIN000_SHIFT;
1853 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
1856 /* Disable unique transition scale */
1857 for (i = 0; i < 4; i++) {
1858 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
1859 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
1860 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
1863 /* Additional steps for 1200mV-0dB */
1865 val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch));
1867 val |= DPIO_TX_UNIQ_TRANS_SCALE_CH1;
1869 val |= DPIO_TX_UNIQ_TRANS_SCALE_CH0;
1870 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val);
1872 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch),
1873 vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch)) |
1874 (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT));
1876 /* Start swing calculation */
1877 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1878 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1879 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1881 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1882 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1883 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1886 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1887 val |= DPIO_LRC_BYPASS;
1888 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
1890 mutex_unlock(&dev_priv->sb_lock);
1892 intel_hdmi->set_infoframes(&encoder->base,
1893 intel_crtc->config->has_hdmi_sink,
1896 g4x_enable_hdmi(encoder);
1898 vlv_wait_port_ready(dev_priv, dport, 0x0);
1901 static void intel_hdmi_destroy(struct drm_connector *connector)
1903 kfree(to_intel_connector(connector)->detect_edid);
1904 drm_connector_cleanup(connector);
1908 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
1909 .dpms = intel_connector_dpms,
1910 .detect = intel_hdmi_detect,
1911 .force = intel_hdmi_force,
1912 .fill_modes = drm_helper_probe_single_connector_modes,
1913 .set_property = intel_hdmi_set_property,
1914 .atomic_get_property = intel_connector_atomic_get_property,
1915 .destroy = intel_hdmi_destroy,
1916 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1917 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1920 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
1921 .get_modes = intel_hdmi_get_modes,
1922 .mode_valid = intel_hdmi_mode_valid,
1923 .best_encoder = intel_best_encoder,
1926 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
1927 .destroy = intel_encoder_destroy,
1931 intel_attach_aspect_ratio_property(struct drm_connector *connector)
1933 if (!drm_mode_create_aspect_ratio_property(connector->dev))
1934 drm_object_attach_property(&connector->base,
1935 connector->dev->mode_config.aspect_ratio_property,
1936 DRM_MODE_PICTURE_ASPECT_NONE);
1940 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
1942 intel_attach_force_audio_property(connector);
1943 intel_attach_broadcast_rgb_property(connector);
1944 intel_hdmi->color_range_auto = true;
1945 intel_attach_aspect_ratio_property(connector);
1946 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1949 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1950 struct intel_connector *intel_connector)
1952 struct drm_connector *connector = &intel_connector->base;
1953 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
1954 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1955 struct drm_device *dev = intel_encoder->base.dev;
1956 struct drm_i915_private *dev_priv = dev->dev_private;
1957 enum port port = intel_dig_port->port;
1959 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
1960 DRM_MODE_CONNECTOR_HDMIA);
1961 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
1963 connector->interlace_allowed = 1;
1964 connector->doublescan_allowed = 0;
1965 connector->stereo_allowed = 1;
1969 if (IS_BROXTON(dev_priv))
1970 intel_hdmi->ddc_bus = GMBUS_PIN_1_BXT;
1972 intel_hdmi->ddc_bus = GMBUS_PIN_DPB;
1973 intel_encoder->hpd_pin = HPD_PORT_B;
1976 if (IS_BROXTON(dev_priv))
1977 intel_hdmi->ddc_bus = GMBUS_PIN_2_BXT;
1979 intel_hdmi->ddc_bus = GMBUS_PIN_DPC;
1980 intel_encoder->hpd_pin = HPD_PORT_C;
1983 if (WARN_ON(IS_BROXTON(dev_priv)))
1984 intel_hdmi->ddc_bus = GMBUS_PIN_DISABLED;
1985 else if (IS_CHERRYVIEW(dev_priv))
1986 intel_hdmi->ddc_bus = GMBUS_PIN_DPD_CHV;
1988 intel_hdmi->ddc_bus = GMBUS_PIN_DPD;
1989 intel_encoder->hpd_pin = HPD_PORT_D;
1992 intel_encoder->hpd_pin = HPD_PORT_A;
1993 /* Internal port only for eDP. */
1998 if (IS_VALLEYVIEW(dev)) {
1999 intel_hdmi->write_infoframe = vlv_write_infoframe;
2000 intel_hdmi->set_infoframes = vlv_set_infoframes;
2001 intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
2002 } else if (IS_G4X(dev)) {
2003 intel_hdmi->write_infoframe = g4x_write_infoframe;
2004 intel_hdmi->set_infoframes = g4x_set_infoframes;
2005 intel_hdmi->infoframe_enabled = g4x_infoframe_enabled;
2006 } else if (HAS_DDI(dev)) {
2007 intel_hdmi->write_infoframe = hsw_write_infoframe;
2008 intel_hdmi->set_infoframes = hsw_set_infoframes;
2009 intel_hdmi->infoframe_enabled = hsw_infoframe_enabled;
2010 } else if (HAS_PCH_IBX(dev)) {
2011 intel_hdmi->write_infoframe = ibx_write_infoframe;
2012 intel_hdmi->set_infoframes = ibx_set_infoframes;
2013 intel_hdmi->infoframe_enabled = ibx_infoframe_enabled;
2015 intel_hdmi->write_infoframe = cpt_write_infoframe;
2016 intel_hdmi->set_infoframes = cpt_set_infoframes;
2017 intel_hdmi->infoframe_enabled = cpt_infoframe_enabled;
2021 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2023 intel_connector->get_hw_state = intel_connector_get_hw_state;
2024 intel_connector->unregister = intel_connector_unregister;
2026 intel_hdmi_add_properties(intel_hdmi, connector);
2028 intel_connector_attach_encoder(intel_connector, intel_encoder);
2029 drm_connector_register(connector);
2031 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2032 * 0xd. Failure to do so will result in spurious interrupts being
2033 * generated on the port when a cable is not attached.
2035 if (IS_G4X(dev) && !IS_GM45(dev)) {
2036 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2037 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2041 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
2043 struct intel_digital_port *intel_dig_port;
2044 struct intel_encoder *intel_encoder;
2045 struct intel_connector *intel_connector;
2047 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2048 if (!intel_dig_port)
2051 intel_connector = intel_connector_alloc();
2052 if (!intel_connector) {
2053 kfree(intel_dig_port);
2057 intel_encoder = &intel_dig_port->base;
2059 drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
2060 DRM_MODE_ENCODER_TMDS);
2062 intel_encoder->compute_config = intel_hdmi_compute_config;
2063 if (HAS_PCH_SPLIT(dev)) {
2064 intel_encoder->disable = pch_disable_hdmi;
2065 intel_encoder->post_disable = pch_post_disable_hdmi;
2067 intel_encoder->disable = g4x_disable_hdmi;
2069 intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
2070 intel_encoder->get_config = intel_hdmi_get_config;
2071 if (IS_CHERRYVIEW(dev)) {
2072 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
2073 intel_encoder->pre_enable = chv_hdmi_pre_enable;
2074 intel_encoder->enable = vlv_enable_hdmi;
2075 intel_encoder->post_disable = chv_hdmi_post_disable;
2076 } else if (IS_VALLEYVIEW(dev)) {
2077 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
2078 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
2079 intel_encoder->enable = vlv_enable_hdmi;
2080 intel_encoder->post_disable = vlv_hdmi_post_disable;
2082 intel_encoder->pre_enable = intel_hdmi_pre_enable;
2083 if (HAS_PCH_CPT(dev))
2084 intel_encoder->enable = cpt_enable_hdmi;
2085 else if (HAS_PCH_IBX(dev))
2086 intel_encoder->enable = ibx_enable_hdmi;
2088 intel_encoder->enable = g4x_enable_hdmi;
2091 intel_encoder->type = INTEL_OUTPUT_HDMI;
2092 if (IS_CHERRYVIEW(dev)) {
2094 intel_encoder->crtc_mask = 1 << 2;
2096 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
2098 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2100 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
2102 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
2103 * to work on real hardware. And since g4x can send infoframes to
2104 * only one port anyway, nothing is lost by allowing it.
2107 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
2109 intel_dig_port->port = port;
2110 intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
2111 intel_dig_port->dp.output_reg = 0;
2113 intel_hdmi_init_connector(intel_dig_port, intel_connector);