2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
29 #include <linux/i2c.h>
30 #include <linux/slab.h>
31 #include <linux/delay.h>
32 #include <linux/hdmi.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_edid.h>
37 #include "intel_drv.h"
38 #include <drm/i915_drm.h>
41 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
43 return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
47 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
49 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
50 struct drm_i915_private *dev_priv = dev->dev_private;
51 uint32_t enabled_bits;
53 enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
55 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
56 "HDMI port enabled, expecting disabled\n");
59 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
61 struct intel_digital_port *intel_dig_port =
62 container_of(encoder, struct intel_digital_port, base.base);
63 return &intel_dig_port->hdmi;
66 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
68 return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
71 static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
74 case HDMI_INFOFRAME_TYPE_AVI:
75 return VIDEO_DIP_SELECT_AVI;
76 case HDMI_INFOFRAME_TYPE_SPD:
77 return VIDEO_DIP_SELECT_SPD;
78 case HDMI_INFOFRAME_TYPE_VENDOR:
79 return VIDEO_DIP_SELECT_VENDOR;
81 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
86 static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
89 case HDMI_INFOFRAME_TYPE_AVI:
90 return VIDEO_DIP_ENABLE_AVI;
91 case HDMI_INFOFRAME_TYPE_SPD:
92 return VIDEO_DIP_ENABLE_SPD;
93 case HDMI_INFOFRAME_TYPE_VENDOR:
94 return VIDEO_DIP_ENABLE_VENDOR;
96 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
101 static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
104 case HDMI_INFOFRAME_TYPE_AVI:
105 return VIDEO_DIP_ENABLE_AVI_HSW;
106 case HDMI_INFOFRAME_TYPE_SPD:
107 return VIDEO_DIP_ENABLE_SPD_HSW;
108 case HDMI_INFOFRAME_TYPE_VENDOR:
109 return VIDEO_DIP_ENABLE_VS_HSW;
111 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
116 static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type,
117 enum transcoder cpu_transcoder,
118 struct drm_i915_private *dev_priv)
121 case HDMI_INFOFRAME_TYPE_AVI:
122 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder);
123 case HDMI_INFOFRAME_TYPE_SPD:
124 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder);
125 case HDMI_INFOFRAME_TYPE_VENDOR:
126 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder);
128 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
133 static void g4x_write_infoframe(struct drm_encoder *encoder,
134 enum hdmi_infoframe_type type,
135 const void *frame, ssize_t len)
137 const uint32_t *data = frame;
138 struct drm_device *dev = encoder->dev;
139 struct drm_i915_private *dev_priv = dev->dev_private;
140 u32 val = I915_READ(VIDEO_DIP_CTL);
143 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
145 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
146 val |= g4x_infoframe_index(type);
148 val &= ~g4x_infoframe_enable(type);
150 I915_WRITE(VIDEO_DIP_CTL, val);
153 for (i = 0; i < len; i += 4) {
154 I915_WRITE(VIDEO_DIP_DATA, *data);
157 /* Write every possible data byte to force correct ECC calculation. */
158 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
159 I915_WRITE(VIDEO_DIP_DATA, 0);
162 val |= g4x_infoframe_enable(type);
163 val &= ~VIDEO_DIP_FREQ_MASK;
164 val |= VIDEO_DIP_FREQ_VSYNC;
166 I915_WRITE(VIDEO_DIP_CTL, val);
167 POSTING_READ(VIDEO_DIP_CTL);
170 static bool g4x_infoframe_enabled(struct drm_encoder *encoder)
172 struct drm_device *dev = encoder->dev;
173 struct drm_i915_private *dev_priv = dev->dev_private;
174 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
175 u32 val = I915_READ(VIDEO_DIP_CTL);
177 if (VIDEO_DIP_PORT(intel_dig_port->port) == (val & VIDEO_DIP_PORT_MASK))
178 return val & VIDEO_DIP_ENABLE;
183 static void ibx_write_infoframe(struct drm_encoder *encoder,
184 enum hdmi_infoframe_type type,
185 const void *frame, ssize_t len)
187 const uint32_t *data = frame;
188 struct drm_device *dev = encoder->dev;
189 struct drm_i915_private *dev_priv = dev->dev_private;
190 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
191 int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
192 u32 val = I915_READ(reg);
194 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
196 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
197 val |= g4x_infoframe_index(type);
199 val &= ~g4x_infoframe_enable(type);
201 I915_WRITE(reg, val);
204 for (i = 0; i < len; i += 4) {
205 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
208 /* Write every possible data byte to force correct ECC calculation. */
209 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
210 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
213 val |= g4x_infoframe_enable(type);
214 val &= ~VIDEO_DIP_FREQ_MASK;
215 val |= VIDEO_DIP_FREQ_VSYNC;
217 I915_WRITE(reg, val);
221 static bool ibx_infoframe_enabled(struct drm_encoder *encoder)
223 struct drm_device *dev = encoder->dev;
224 struct drm_i915_private *dev_priv = dev->dev_private;
225 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
226 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
227 int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
228 u32 val = I915_READ(reg);
230 if (VIDEO_DIP_PORT(intel_dig_port->port) == (val & VIDEO_DIP_PORT_MASK))
231 return val & VIDEO_DIP_ENABLE;
236 static void cpt_write_infoframe(struct drm_encoder *encoder,
237 enum hdmi_infoframe_type type,
238 const void *frame, ssize_t len)
240 const uint32_t *data = frame;
241 struct drm_device *dev = encoder->dev;
242 struct drm_i915_private *dev_priv = dev->dev_private;
243 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
244 int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
245 u32 val = I915_READ(reg);
247 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
249 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
250 val |= g4x_infoframe_index(type);
252 /* The DIP control register spec says that we need to update the AVI
253 * infoframe without clearing its enable bit */
254 if (type != HDMI_INFOFRAME_TYPE_AVI)
255 val &= ~g4x_infoframe_enable(type);
257 I915_WRITE(reg, val);
260 for (i = 0; i < len; i += 4) {
261 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
264 /* Write every possible data byte to force correct ECC calculation. */
265 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
266 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
269 val |= g4x_infoframe_enable(type);
270 val &= ~VIDEO_DIP_FREQ_MASK;
271 val |= VIDEO_DIP_FREQ_VSYNC;
273 I915_WRITE(reg, val);
277 static bool cpt_infoframe_enabled(struct drm_encoder *encoder)
279 struct drm_device *dev = encoder->dev;
280 struct drm_i915_private *dev_priv = dev->dev_private;
281 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
282 int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
283 u32 val = I915_READ(reg);
285 return val & VIDEO_DIP_ENABLE;
288 static void vlv_write_infoframe(struct drm_encoder *encoder,
289 enum hdmi_infoframe_type type,
290 const void *frame, ssize_t len)
292 const uint32_t *data = frame;
293 struct drm_device *dev = encoder->dev;
294 struct drm_i915_private *dev_priv = dev->dev_private;
295 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
296 int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
297 u32 val = I915_READ(reg);
299 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
301 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
302 val |= g4x_infoframe_index(type);
304 val &= ~g4x_infoframe_enable(type);
306 I915_WRITE(reg, val);
309 for (i = 0; i < len; i += 4) {
310 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
313 /* Write every possible data byte to force correct ECC calculation. */
314 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
315 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
318 val |= g4x_infoframe_enable(type);
319 val &= ~VIDEO_DIP_FREQ_MASK;
320 val |= VIDEO_DIP_FREQ_VSYNC;
322 I915_WRITE(reg, val);
326 static bool vlv_infoframe_enabled(struct drm_encoder *encoder)
328 struct drm_device *dev = encoder->dev;
329 struct drm_i915_private *dev_priv = dev->dev_private;
330 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
331 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
332 int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
333 u32 val = I915_READ(reg);
335 if (VIDEO_DIP_PORT(intel_dig_port->port) == (val & VIDEO_DIP_PORT_MASK))
336 return val & VIDEO_DIP_ENABLE;
341 static void hsw_write_infoframe(struct drm_encoder *encoder,
342 enum hdmi_infoframe_type type,
343 const void *frame, ssize_t len)
345 const uint32_t *data = frame;
346 struct drm_device *dev = encoder->dev;
347 struct drm_i915_private *dev_priv = dev->dev_private;
348 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
349 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
352 u32 val = I915_READ(ctl_reg);
354 data_reg = hsw_infoframe_data_reg(type,
355 intel_crtc->config->cpu_transcoder,
360 val &= ~hsw_infoframe_enable(type);
361 I915_WRITE(ctl_reg, val);
364 for (i = 0; i < len; i += 4) {
365 I915_WRITE(data_reg + i, *data);
368 /* Write every possible data byte to force correct ECC calculation. */
369 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
370 I915_WRITE(data_reg + i, 0);
373 val |= hsw_infoframe_enable(type);
374 I915_WRITE(ctl_reg, val);
375 POSTING_READ(ctl_reg);
378 static bool hsw_infoframe_enabled(struct drm_encoder *encoder)
380 struct drm_device *dev = encoder->dev;
381 struct drm_i915_private *dev_priv = dev->dev_private;
382 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
383 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
384 u32 val = I915_READ(ctl_reg);
386 return val & (VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
387 VIDEO_DIP_ENABLE_VS_HSW);
391 * The data we write to the DIP data buffer registers is 1 byte bigger than the
392 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
393 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
394 * used for both technologies.
396 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
397 * DW1: DB3 | DB2 | DB1 | DB0
398 * DW2: DB7 | DB6 | DB5 | DB4
401 * (HB is Header Byte, DB is Data Byte)
403 * The hdmi pack() functions don't know about that hardware specific hole so we
404 * trick them by giving an offset into the buffer and moving back the header
407 static void intel_write_infoframe(struct drm_encoder *encoder,
408 union hdmi_infoframe *frame)
410 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
411 uint8_t buffer[VIDEO_DIP_DATA_SIZE];
414 /* see comment above for the reason for this offset */
415 len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
419 /* Insert the 'hole' (see big comment above) at position 3 */
420 buffer[0] = buffer[1];
421 buffer[1] = buffer[2];
422 buffer[2] = buffer[3];
426 intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);
429 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
430 struct drm_display_mode *adjusted_mode)
432 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
433 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
434 union hdmi_infoframe frame;
437 /* Set user selected PAR to incoming mode's member */
438 adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio;
440 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
443 DRM_ERROR("couldn't fill AVI infoframe\n");
447 if (intel_hdmi->rgb_quant_range_selectable) {
448 if (intel_crtc->config->limited_color_range)
449 frame.avi.quantization_range =
450 HDMI_QUANTIZATION_RANGE_LIMITED;
452 frame.avi.quantization_range =
453 HDMI_QUANTIZATION_RANGE_FULL;
456 intel_write_infoframe(encoder, &frame);
459 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
461 union hdmi_infoframe frame;
464 ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
466 DRM_ERROR("couldn't fill SPD infoframe\n");
470 frame.spd.sdi = HDMI_SPD_SDI_PC;
472 intel_write_infoframe(encoder, &frame);
476 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
477 struct drm_display_mode *adjusted_mode)
479 union hdmi_infoframe frame;
482 ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
487 intel_write_infoframe(encoder, &frame);
490 static void g4x_set_infoframes(struct drm_encoder *encoder,
492 struct drm_display_mode *adjusted_mode)
494 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
495 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
496 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
497 u32 reg = VIDEO_DIP_CTL;
498 u32 val = I915_READ(reg);
499 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
501 assert_hdmi_port_disabled(intel_hdmi);
503 /* If the registers were not initialized yet, they might be zeroes,
504 * which means we're selecting the AVI DIP and we're setting its
505 * frequency to once. This seems to really confuse the HW and make
506 * things stop working (the register spec says the AVI always needs to
507 * be sent every VSync). So here we avoid writing to the register more
508 * than we need and also explicitly select the AVI DIP and explicitly
509 * set its frequency to every VSync. Avoiding to write it twice seems to
510 * be enough to solve the problem, but being defensive shouldn't hurt us
512 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
515 if (!(val & VIDEO_DIP_ENABLE))
517 val &= ~VIDEO_DIP_ENABLE;
518 I915_WRITE(reg, val);
523 if (port != (val & VIDEO_DIP_PORT_MASK)) {
524 if (val & VIDEO_DIP_ENABLE) {
525 val &= ~VIDEO_DIP_ENABLE;
526 I915_WRITE(reg, val);
529 val &= ~VIDEO_DIP_PORT_MASK;
533 val |= VIDEO_DIP_ENABLE;
534 val &= ~VIDEO_DIP_ENABLE_VENDOR;
536 I915_WRITE(reg, val);
539 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
540 intel_hdmi_set_spd_infoframe(encoder);
541 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
544 static void ibx_set_infoframes(struct drm_encoder *encoder,
546 struct drm_display_mode *adjusted_mode)
548 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
549 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
550 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
551 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
552 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
553 u32 val = I915_READ(reg);
554 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
556 assert_hdmi_port_disabled(intel_hdmi);
558 /* See the big comment in g4x_set_infoframes() */
559 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
562 if (!(val & VIDEO_DIP_ENABLE))
564 val &= ~VIDEO_DIP_ENABLE;
565 I915_WRITE(reg, val);
570 if (port != (val & VIDEO_DIP_PORT_MASK)) {
571 if (val & VIDEO_DIP_ENABLE) {
572 val &= ~VIDEO_DIP_ENABLE;
573 I915_WRITE(reg, val);
576 val &= ~VIDEO_DIP_PORT_MASK;
580 val |= VIDEO_DIP_ENABLE;
581 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
582 VIDEO_DIP_ENABLE_GCP);
584 I915_WRITE(reg, val);
587 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
588 intel_hdmi_set_spd_infoframe(encoder);
589 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
592 static void cpt_set_infoframes(struct drm_encoder *encoder,
594 struct drm_display_mode *adjusted_mode)
596 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
597 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
598 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
599 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
600 u32 val = I915_READ(reg);
602 assert_hdmi_port_disabled(intel_hdmi);
604 /* See the big comment in g4x_set_infoframes() */
605 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
608 if (!(val & VIDEO_DIP_ENABLE))
610 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI);
611 I915_WRITE(reg, val);
616 /* Set both together, unset both together: see the spec. */
617 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
618 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
619 VIDEO_DIP_ENABLE_GCP);
621 I915_WRITE(reg, val);
624 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
625 intel_hdmi_set_spd_infoframe(encoder);
626 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
629 static void vlv_set_infoframes(struct drm_encoder *encoder,
631 struct drm_display_mode *adjusted_mode)
633 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
634 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
635 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
636 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
637 u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
638 u32 val = I915_READ(reg);
639 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
641 assert_hdmi_port_disabled(intel_hdmi);
643 /* See the big comment in g4x_set_infoframes() */
644 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
647 if (!(val & VIDEO_DIP_ENABLE))
649 val &= ~VIDEO_DIP_ENABLE;
650 I915_WRITE(reg, val);
655 if (port != (val & VIDEO_DIP_PORT_MASK)) {
656 if (val & VIDEO_DIP_ENABLE) {
657 val &= ~VIDEO_DIP_ENABLE;
658 I915_WRITE(reg, val);
661 val &= ~VIDEO_DIP_PORT_MASK;
665 val |= VIDEO_DIP_ENABLE;
666 val &= ~(VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_ENABLE_VENDOR |
667 VIDEO_DIP_ENABLE_GAMUT | VIDEO_DIP_ENABLE_GCP);
669 I915_WRITE(reg, val);
672 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
673 intel_hdmi_set_spd_infoframe(encoder);
674 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
677 static void hsw_set_infoframes(struct drm_encoder *encoder,
679 struct drm_display_mode *adjusted_mode)
681 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
682 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
683 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
684 u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
685 u32 val = I915_READ(reg);
687 assert_hdmi_port_disabled(intel_hdmi);
695 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
696 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW);
698 I915_WRITE(reg, val);
701 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
702 intel_hdmi_set_spd_infoframe(encoder);
703 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
706 static void intel_hdmi_prepare(struct intel_encoder *encoder)
708 struct drm_device *dev = encoder->base.dev;
709 struct drm_i915_private *dev_priv = dev->dev_private;
710 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
711 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
712 struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
715 hdmi_val = SDVO_ENCODING_HDMI;
716 if (!HAS_PCH_SPLIT(dev))
717 hdmi_val |= intel_hdmi->color_range;
718 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
719 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
720 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
721 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
723 if (crtc->config->pipe_bpp > 24)
724 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
726 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
728 if (crtc->config->has_hdmi_sink)
729 hdmi_val |= HDMI_MODE_SELECT_HDMI;
731 if (HAS_PCH_CPT(dev))
732 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
733 else if (IS_CHERRYVIEW(dev))
734 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
736 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
738 I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
739 POSTING_READ(intel_hdmi->hdmi_reg);
742 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
745 struct drm_device *dev = encoder->base.dev;
746 struct drm_i915_private *dev_priv = dev->dev_private;
747 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
748 enum intel_display_power_domain power_domain;
751 power_domain = intel_display_port_power_domain(encoder);
752 if (!intel_display_power_is_enabled(dev_priv, power_domain))
755 tmp = I915_READ(intel_hdmi->hdmi_reg);
757 if (!(tmp & SDVO_ENABLE))
760 if (HAS_PCH_CPT(dev))
761 *pipe = PORT_TO_PIPE_CPT(tmp);
762 else if (IS_CHERRYVIEW(dev))
763 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
765 *pipe = PORT_TO_PIPE(tmp);
770 static void intel_hdmi_get_config(struct intel_encoder *encoder,
771 struct intel_crtc_state *pipe_config)
773 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
774 struct drm_device *dev = encoder->base.dev;
775 struct drm_i915_private *dev_priv = dev->dev_private;
779 tmp = I915_READ(intel_hdmi->hdmi_reg);
781 if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
782 flags |= DRM_MODE_FLAG_PHSYNC;
784 flags |= DRM_MODE_FLAG_NHSYNC;
786 if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
787 flags |= DRM_MODE_FLAG_PVSYNC;
789 flags |= DRM_MODE_FLAG_NVSYNC;
791 if (tmp & HDMI_MODE_SELECT_HDMI)
792 pipe_config->has_hdmi_sink = true;
794 if (intel_hdmi->infoframe_enabled(&encoder->base))
795 pipe_config->has_infoframe = true;
797 if (tmp & SDVO_AUDIO_ENABLE)
798 pipe_config->has_audio = true;
800 if (!HAS_PCH_SPLIT(dev) &&
801 tmp & HDMI_COLOR_RANGE_16_235)
802 pipe_config->limited_color_range = true;
804 pipe_config->base.adjusted_mode.flags |= flags;
806 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
807 dotclock = pipe_config->port_clock * 2 / 3;
809 dotclock = pipe_config->port_clock;
811 if (HAS_PCH_SPLIT(dev_priv->dev))
812 ironlake_check_encoder_dotclock(pipe_config, dotclock);
814 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
817 static void intel_enable_hdmi(struct intel_encoder *encoder)
819 struct drm_device *dev = encoder->base.dev;
820 struct drm_i915_private *dev_priv = dev->dev_private;
821 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
822 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
824 u32 enable_bits = SDVO_ENABLE;
826 if (intel_crtc->config->has_audio)
827 enable_bits |= SDVO_AUDIO_ENABLE;
829 temp = I915_READ(intel_hdmi->hdmi_reg);
831 /* HW workaround for IBX, we need to move the port to transcoder A
832 * before disabling it, so restore the transcoder select bit here. */
833 if (HAS_PCH_IBX(dev))
834 enable_bits |= SDVO_PIPE_SEL(intel_crtc->pipe);
836 /* HW workaround, need to toggle enable bit off and on for 12bpc, but
837 * we do this anyway which shows more stable in testing.
839 if (HAS_PCH_SPLIT(dev)) {
840 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
841 POSTING_READ(intel_hdmi->hdmi_reg);
846 I915_WRITE(intel_hdmi->hdmi_reg, temp);
847 POSTING_READ(intel_hdmi->hdmi_reg);
849 /* HW workaround, need to write this twice for issue that may result
850 * in first write getting masked.
852 if (HAS_PCH_SPLIT(dev)) {
853 I915_WRITE(intel_hdmi->hdmi_reg, temp);
854 POSTING_READ(intel_hdmi->hdmi_reg);
857 if (intel_crtc->config->has_audio) {
858 WARN_ON(!intel_crtc->config->has_hdmi_sink);
859 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
860 pipe_name(intel_crtc->pipe));
861 intel_audio_codec_enable(encoder);
865 static void vlv_enable_hdmi(struct intel_encoder *encoder)
869 static void intel_disable_hdmi(struct intel_encoder *encoder)
871 struct drm_device *dev = encoder->base.dev;
872 struct drm_i915_private *dev_priv = dev->dev_private;
873 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
874 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
876 u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE;
878 if (crtc->config->has_audio)
879 intel_audio_codec_disable(encoder);
881 temp = I915_READ(intel_hdmi->hdmi_reg);
883 /* HW workaround for IBX, we need to move the port to transcoder A
884 * before disabling it. */
885 if (HAS_PCH_IBX(dev)) {
886 struct drm_crtc *crtc = encoder->base.crtc;
887 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
889 if (temp & SDVO_PIPE_B_SELECT) {
890 temp &= ~SDVO_PIPE_B_SELECT;
891 I915_WRITE(intel_hdmi->hdmi_reg, temp);
892 POSTING_READ(intel_hdmi->hdmi_reg);
894 /* Again we need to write this twice. */
895 I915_WRITE(intel_hdmi->hdmi_reg, temp);
896 POSTING_READ(intel_hdmi->hdmi_reg);
898 /* Transcoder selection bits only update
899 * effectively on vblank. */
901 intel_wait_for_vblank(dev, pipe);
907 /* HW workaround, need to toggle enable bit off and on for 12bpc, but
908 * we do this anyway which shows more stable in testing.
910 if (HAS_PCH_SPLIT(dev)) {
911 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
912 POSTING_READ(intel_hdmi->hdmi_reg);
915 temp &= ~enable_bits;
917 I915_WRITE(intel_hdmi->hdmi_reg, temp);
918 POSTING_READ(intel_hdmi->hdmi_reg);
920 /* HW workaround, need to write this twice for issue that may result
921 * in first write getting masked.
923 if (HAS_PCH_SPLIT(dev)) {
924 I915_WRITE(intel_hdmi->hdmi_reg, temp);
925 POSTING_READ(intel_hdmi->hdmi_reg);
929 static int hdmi_portclock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit)
931 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
933 if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev))
935 else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8)
941 static enum drm_mode_status
942 intel_hdmi_mode_valid(struct drm_connector *connector,
943 struct drm_display_mode *mode)
945 int clock = mode->clock;
947 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
950 if (clock > hdmi_portclock_limit(intel_attached_hdmi(connector),
952 return MODE_CLOCK_HIGH;
954 return MODE_CLOCK_LOW;
956 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
957 return MODE_NO_DBLESCAN;
962 static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)
964 struct drm_device *dev = crtc_state->base.crtc->dev;
965 struct drm_atomic_state *state;
966 struct intel_encoder *encoder;
967 struct drm_connector_state *connector_state;
968 int count = 0, count_hdmi = 0;
971 if (HAS_GMCH_DISPLAY(dev))
974 state = crtc_state->base.state;
976 for (i = 0; i < state->num_connector; i++) {
977 if (!state->connectors[i])
980 connector_state = state->connector_states[i];
981 if (connector_state->crtc != crtc_state->base.crtc)
984 encoder = to_intel_encoder(connector_state->best_encoder);
986 count_hdmi += encoder->type == INTEL_OUTPUT_HDMI;
991 * HDMI 12bpc affects the clocks, so it's only possible
992 * when not cloning with other encoder types.
994 return count_hdmi > 0 && count_hdmi == count;
997 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
998 struct intel_crtc_state *pipe_config)
1000 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1001 struct drm_device *dev = encoder->base.dev;
1002 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1003 int clock_12bpc = pipe_config->base.adjusted_mode.crtc_clock * 3 / 2;
1004 int portclock_limit = hdmi_portclock_limit(intel_hdmi, false);
1007 pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink;
1009 if (pipe_config->has_hdmi_sink)
1010 pipe_config->has_infoframe = true;
1012 if (intel_hdmi->color_range_auto) {
1013 /* See CEA-861-E - 5.1 Default Encoding Parameters */
1014 if (pipe_config->has_hdmi_sink &&
1015 drm_match_cea_mode(adjusted_mode) > 1)
1016 intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
1018 intel_hdmi->color_range = 0;
1021 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
1022 pipe_config->pixel_multiplier = 2;
1025 if (intel_hdmi->color_range)
1026 pipe_config->limited_color_range = true;
1028 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
1029 pipe_config->has_pch_encoder = true;
1031 if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio)
1032 pipe_config->has_audio = true;
1035 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
1036 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
1037 * outputs. We also need to check that the higher clock still fits
1040 if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink &&
1041 clock_12bpc <= portclock_limit &&
1042 hdmi_12bpc_possible(pipe_config)) {
1043 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
1046 /* Need to adjust the port link by 1.5x for 12bpc. */
1047 pipe_config->port_clock = clock_12bpc;
1049 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
1053 if (!pipe_config->bw_constrained) {
1054 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
1055 pipe_config->pipe_bpp = desired_bpp;
1058 if (adjusted_mode->crtc_clock > portclock_limit) {
1059 DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n");
1067 intel_hdmi_unset_edid(struct drm_connector *connector)
1069 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1071 intel_hdmi->has_hdmi_sink = false;
1072 intel_hdmi->has_audio = false;
1073 intel_hdmi->rgb_quant_range_selectable = false;
1075 kfree(to_intel_connector(connector)->detect_edid);
1076 to_intel_connector(connector)->detect_edid = NULL;
1080 intel_hdmi_set_edid(struct drm_connector *connector)
1082 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1083 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1084 struct intel_encoder *intel_encoder =
1085 &hdmi_to_dig_port(intel_hdmi)->base;
1086 enum intel_display_power_domain power_domain;
1088 bool connected = false;
1090 power_domain = intel_display_port_power_domain(intel_encoder);
1091 intel_display_power_get(dev_priv, power_domain);
1093 edid = drm_get_edid(connector,
1094 intel_gmbus_get_adapter(dev_priv,
1095 intel_hdmi->ddc_bus));
1097 intel_display_power_put(dev_priv, power_domain);
1099 to_intel_connector(connector)->detect_edid = edid;
1100 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
1101 intel_hdmi->rgb_quant_range_selectable =
1102 drm_rgb_quant_range_selectable(edid);
1104 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
1105 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
1106 intel_hdmi->has_audio =
1107 intel_hdmi->force_audio == HDMI_AUDIO_ON;
1109 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
1110 intel_hdmi->has_hdmi_sink =
1111 drm_detect_hdmi_monitor(edid);
1119 static enum drm_connector_status
1120 intel_hdmi_detect(struct drm_connector *connector, bool force)
1122 enum drm_connector_status status;
1124 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1125 connector->base.id, connector->name);
1127 intel_hdmi_unset_edid(connector);
1129 if (intel_hdmi_set_edid(connector)) {
1130 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1132 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1133 status = connector_status_connected;
1135 status = connector_status_disconnected;
1141 intel_hdmi_force(struct drm_connector *connector)
1143 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1145 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1146 connector->base.id, connector->name);
1148 intel_hdmi_unset_edid(connector);
1150 if (connector->status != connector_status_connected)
1153 intel_hdmi_set_edid(connector);
1154 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1157 static int intel_hdmi_get_modes(struct drm_connector *connector)
1161 edid = to_intel_connector(connector)->detect_edid;
1165 return intel_connector_update_modes(connector, edid);
1169 intel_hdmi_detect_audio(struct drm_connector *connector)
1171 bool has_audio = false;
1174 edid = to_intel_connector(connector)->detect_edid;
1175 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL)
1176 has_audio = drm_detect_monitor_audio(edid);
1182 intel_hdmi_set_property(struct drm_connector *connector,
1183 struct drm_property *property,
1186 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1187 struct intel_digital_port *intel_dig_port =
1188 hdmi_to_dig_port(intel_hdmi);
1189 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1192 ret = drm_object_property_set_value(&connector->base, property, val);
1196 if (property == dev_priv->force_audio_property) {
1197 enum hdmi_force_audio i = val;
1200 if (i == intel_hdmi->force_audio)
1203 intel_hdmi->force_audio = i;
1205 if (i == HDMI_AUDIO_AUTO)
1206 has_audio = intel_hdmi_detect_audio(connector);
1208 has_audio = (i == HDMI_AUDIO_ON);
1210 if (i == HDMI_AUDIO_OFF_DVI)
1211 intel_hdmi->has_hdmi_sink = 0;
1213 intel_hdmi->has_audio = has_audio;
1217 if (property == dev_priv->broadcast_rgb_property) {
1218 bool old_auto = intel_hdmi->color_range_auto;
1219 uint32_t old_range = intel_hdmi->color_range;
1222 case INTEL_BROADCAST_RGB_AUTO:
1223 intel_hdmi->color_range_auto = true;
1225 case INTEL_BROADCAST_RGB_FULL:
1226 intel_hdmi->color_range_auto = false;
1227 intel_hdmi->color_range = 0;
1229 case INTEL_BROADCAST_RGB_LIMITED:
1230 intel_hdmi->color_range_auto = false;
1231 intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
1237 if (old_auto == intel_hdmi->color_range_auto &&
1238 old_range == intel_hdmi->color_range)
1244 if (property == connector->dev->mode_config.aspect_ratio_property) {
1246 case DRM_MODE_PICTURE_ASPECT_NONE:
1247 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1249 case DRM_MODE_PICTURE_ASPECT_4_3:
1250 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3;
1252 case DRM_MODE_PICTURE_ASPECT_16_9:
1253 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
1264 if (intel_dig_port->base.base.crtc)
1265 intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
1270 static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
1272 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1273 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1274 struct drm_display_mode *adjusted_mode =
1275 &intel_crtc->config->base.adjusted_mode;
1277 intel_hdmi_prepare(encoder);
1279 intel_hdmi->set_infoframes(&encoder->base,
1280 intel_crtc->config->has_hdmi_sink,
1284 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
1286 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1287 struct intel_hdmi *intel_hdmi = &dport->hdmi;
1288 struct drm_device *dev = encoder->base.dev;
1289 struct drm_i915_private *dev_priv = dev->dev_private;
1290 struct intel_crtc *intel_crtc =
1291 to_intel_crtc(encoder->base.crtc);
1292 struct drm_display_mode *adjusted_mode =
1293 &intel_crtc->config->base.adjusted_mode;
1294 enum dpio_channel port = vlv_dport_to_channel(dport);
1295 int pipe = intel_crtc->pipe;
1298 /* Enable clock channels for this port */
1299 mutex_lock(&dev_priv->dpio_lock);
1300 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1307 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1310 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
1311 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
1312 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
1313 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
1314 vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
1315 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
1316 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1317 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1319 /* Program lane clock */
1320 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1321 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1322 mutex_unlock(&dev_priv->dpio_lock);
1324 intel_hdmi->set_infoframes(&encoder->base,
1325 intel_crtc->config->has_hdmi_sink,
1328 intel_enable_hdmi(encoder);
1330 vlv_wait_port_ready(dev_priv, dport);
1333 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1335 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1336 struct drm_device *dev = encoder->base.dev;
1337 struct drm_i915_private *dev_priv = dev->dev_private;
1338 struct intel_crtc *intel_crtc =
1339 to_intel_crtc(encoder->base.crtc);
1340 enum dpio_channel port = vlv_dport_to_channel(dport);
1341 int pipe = intel_crtc->pipe;
1343 intel_hdmi_prepare(encoder);
1345 /* Program Tx lane resets to default */
1346 mutex_lock(&dev_priv->dpio_lock);
1347 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1348 DPIO_PCS_TX_LANE2_RESET |
1349 DPIO_PCS_TX_LANE1_RESET);
1350 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1351 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1352 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1353 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1354 DPIO_PCS_CLK_SOFT_RESET);
1356 /* Fix up inter-pair skew failure */
1357 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1358 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1359 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1361 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1362 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1363 mutex_unlock(&dev_priv->dpio_lock);
1366 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1368 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1369 struct drm_device *dev = encoder->base.dev;
1370 struct drm_i915_private *dev_priv = dev->dev_private;
1371 struct intel_crtc *intel_crtc =
1372 to_intel_crtc(encoder->base.crtc);
1373 enum dpio_channel ch = vlv_dport_to_channel(dport);
1374 enum pipe pipe = intel_crtc->pipe;
1377 intel_hdmi_prepare(encoder);
1379 mutex_lock(&dev_priv->dpio_lock);
1381 /* program left/right clock distribution */
1382 if (pipe != PIPE_B) {
1383 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1384 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1386 val |= CHV_BUFLEFTENA1_FORCE;
1388 val |= CHV_BUFRIGHTENA1_FORCE;
1389 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1391 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1392 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1394 val |= CHV_BUFLEFTENA2_FORCE;
1396 val |= CHV_BUFRIGHTENA2_FORCE;
1397 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1400 /* program clock channel usage */
1401 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
1402 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1404 val &= ~CHV_PCS_USEDCLKCHANNEL;
1406 val |= CHV_PCS_USEDCLKCHANNEL;
1407 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
1409 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
1410 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1412 val &= ~CHV_PCS_USEDCLKCHANNEL;
1414 val |= CHV_PCS_USEDCLKCHANNEL;
1415 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
1418 * This a a bit weird since generally CL
1419 * matches the pipe, but here we need to
1420 * pick the CL based on the port.
1422 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
1424 val &= ~CHV_CMN_USEDCLKCHANNEL;
1426 val |= CHV_CMN_USEDCLKCHANNEL;
1427 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
1429 mutex_unlock(&dev_priv->dpio_lock);
1432 static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
1434 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1435 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1436 struct intel_crtc *intel_crtc =
1437 to_intel_crtc(encoder->base.crtc);
1438 enum dpio_channel port = vlv_dport_to_channel(dport);
1439 int pipe = intel_crtc->pipe;
1441 /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1442 mutex_lock(&dev_priv->dpio_lock);
1443 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
1444 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
1445 mutex_unlock(&dev_priv->dpio_lock);
1448 static void chv_hdmi_post_disable(struct intel_encoder *encoder)
1450 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1451 struct drm_device *dev = encoder->base.dev;
1452 struct drm_i915_private *dev_priv = dev->dev_private;
1453 struct intel_crtc *intel_crtc =
1454 to_intel_crtc(encoder->base.crtc);
1455 enum dpio_channel ch = vlv_dport_to_channel(dport);
1456 enum pipe pipe = intel_crtc->pipe;
1459 mutex_lock(&dev_priv->dpio_lock);
1461 /* Propagate soft reset to data lane reset */
1462 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
1463 val |= CHV_PCS_REQ_SOFTRESET_EN;
1464 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
1466 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1467 val |= CHV_PCS_REQ_SOFTRESET_EN;
1468 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1470 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
1471 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1472 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
1474 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
1475 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1476 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
1478 mutex_unlock(&dev_priv->dpio_lock);
1481 static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
1483 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1484 struct intel_hdmi *intel_hdmi = &dport->hdmi;
1485 struct drm_device *dev = encoder->base.dev;
1486 struct drm_i915_private *dev_priv = dev->dev_private;
1487 struct intel_crtc *intel_crtc =
1488 to_intel_crtc(encoder->base.crtc);
1489 struct drm_display_mode *adjusted_mode =
1490 &intel_crtc->config->base.adjusted_mode;
1491 enum dpio_channel ch = vlv_dport_to_channel(dport);
1492 int pipe = intel_crtc->pipe;
1496 mutex_lock(&dev_priv->dpio_lock);
1498 /* allow hardware to manage TX FIFO reset source */
1499 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
1500 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
1501 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
1503 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
1504 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
1505 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
1507 /* Deassert soft data lane reset*/
1508 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
1509 val |= CHV_PCS_REQ_SOFTRESET_EN;
1510 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
1512 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1513 val |= CHV_PCS_REQ_SOFTRESET_EN;
1514 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1516 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
1517 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1518 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
1520 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
1521 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1522 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
1524 /* Program Tx latency optimal setting */
1525 for (i = 0; i < 4; i++) {
1526 /* Set the upar bit */
1527 data = (i == 1) ? 0x0 : 0x1;
1528 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
1529 data << DPIO_UPAR_SHIFT);
1532 /* Data lane stagger programming */
1533 /* FIXME: Fix up value only after power analysis */
1535 /* Clear calc init */
1536 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1537 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
1538 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
1539 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1540 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1542 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1543 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
1544 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
1545 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1546 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1548 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
1549 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
1550 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
1551 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
1553 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
1554 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
1555 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
1556 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
1558 /* FIXME: Program the support xxx V-dB */
1560 for (i = 0; i < 4; i++) {
1561 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
1562 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
1563 val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT;
1564 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
1567 for (i = 0; i < 4; i++) {
1568 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1569 val &= ~DPIO_SWING_MARGIN000_MASK;
1570 val |= 102 << DPIO_SWING_MARGIN000_SHIFT;
1571 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
1574 /* Disable unique transition scale */
1575 for (i = 0; i < 4; i++) {
1576 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
1577 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
1578 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
1581 /* Additional steps for 1200mV-0dB */
1583 val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch));
1585 val |= DPIO_TX_UNIQ_TRANS_SCALE_CH1;
1587 val |= DPIO_TX_UNIQ_TRANS_SCALE_CH0;
1588 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val);
1590 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch),
1591 vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch)) |
1592 (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT));
1594 /* Start swing calculation */
1595 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1596 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1597 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1599 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1600 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1601 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1604 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1605 val |= DPIO_LRC_BYPASS;
1606 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
1608 mutex_unlock(&dev_priv->dpio_lock);
1610 intel_hdmi->set_infoframes(&encoder->base,
1611 intel_crtc->config->has_hdmi_sink,
1614 intel_enable_hdmi(encoder);
1616 vlv_wait_port_ready(dev_priv, dport);
1619 static void intel_hdmi_destroy(struct drm_connector *connector)
1621 kfree(to_intel_connector(connector)->detect_edid);
1622 drm_connector_cleanup(connector);
1626 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
1627 .dpms = intel_connector_dpms,
1628 .detect = intel_hdmi_detect,
1629 .force = intel_hdmi_force,
1630 .fill_modes = drm_helper_probe_single_connector_modes,
1631 .set_property = intel_hdmi_set_property,
1632 .atomic_get_property = intel_connector_atomic_get_property,
1633 .destroy = intel_hdmi_destroy,
1634 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1635 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1638 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
1639 .get_modes = intel_hdmi_get_modes,
1640 .mode_valid = intel_hdmi_mode_valid,
1641 .best_encoder = intel_best_encoder,
1644 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
1645 .destroy = intel_encoder_destroy,
1649 intel_attach_aspect_ratio_property(struct drm_connector *connector)
1651 if (!drm_mode_create_aspect_ratio_property(connector->dev))
1652 drm_object_attach_property(&connector->base,
1653 connector->dev->mode_config.aspect_ratio_property,
1654 DRM_MODE_PICTURE_ASPECT_NONE);
1658 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
1660 intel_attach_force_audio_property(connector);
1661 intel_attach_broadcast_rgb_property(connector);
1662 intel_hdmi->color_range_auto = true;
1663 intel_attach_aspect_ratio_property(connector);
1664 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1667 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1668 struct intel_connector *intel_connector)
1670 struct drm_connector *connector = &intel_connector->base;
1671 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
1672 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1673 struct drm_device *dev = intel_encoder->base.dev;
1674 struct drm_i915_private *dev_priv = dev->dev_private;
1675 enum port port = intel_dig_port->port;
1677 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
1678 DRM_MODE_CONNECTOR_HDMIA);
1679 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
1681 connector->interlace_allowed = 1;
1682 connector->doublescan_allowed = 0;
1683 connector->stereo_allowed = 1;
1687 if (IS_BROXTON(dev_priv))
1688 intel_hdmi->ddc_bus = GMBUS_PIN_1_BXT;
1690 intel_hdmi->ddc_bus = GMBUS_PIN_DPB;
1691 intel_encoder->hpd_pin = HPD_PORT_B;
1694 if (IS_BROXTON(dev_priv))
1695 intel_hdmi->ddc_bus = GMBUS_PIN_2_BXT;
1697 intel_hdmi->ddc_bus = GMBUS_PIN_DPC;
1698 intel_encoder->hpd_pin = HPD_PORT_C;
1701 if (WARN_ON(IS_BROXTON(dev_priv)))
1702 intel_hdmi->ddc_bus = GMBUS_PIN_DISABLED;
1703 else if (IS_CHERRYVIEW(dev_priv))
1704 intel_hdmi->ddc_bus = GMBUS_PIN_DPD_CHV;
1706 intel_hdmi->ddc_bus = GMBUS_PIN_DPD;
1707 intel_encoder->hpd_pin = HPD_PORT_D;
1710 intel_encoder->hpd_pin = HPD_PORT_A;
1711 /* Internal port only for eDP. */
1716 if (IS_VALLEYVIEW(dev)) {
1717 intel_hdmi->write_infoframe = vlv_write_infoframe;
1718 intel_hdmi->set_infoframes = vlv_set_infoframes;
1719 intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
1720 } else if (IS_G4X(dev)) {
1721 intel_hdmi->write_infoframe = g4x_write_infoframe;
1722 intel_hdmi->set_infoframes = g4x_set_infoframes;
1723 intel_hdmi->infoframe_enabled = g4x_infoframe_enabled;
1724 } else if (HAS_DDI(dev)) {
1725 intel_hdmi->write_infoframe = hsw_write_infoframe;
1726 intel_hdmi->set_infoframes = hsw_set_infoframes;
1727 intel_hdmi->infoframe_enabled = hsw_infoframe_enabled;
1728 } else if (HAS_PCH_IBX(dev)) {
1729 intel_hdmi->write_infoframe = ibx_write_infoframe;
1730 intel_hdmi->set_infoframes = ibx_set_infoframes;
1731 intel_hdmi->infoframe_enabled = ibx_infoframe_enabled;
1733 intel_hdmi->write_infoframe = cpt_write_infoframe;
1734 intel_hdmi->set_infoframes = cpt_set_infoframes;
1735 intel_hdmi->infoframe_enabled = cpt_infoframe_enabled;
1739 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
1741 intel_connector->get_hw_state = intel_connector_get_hw_state;
1742 intel_connector->unregister = intel_connector_unregister;
1744 intel_hdmi_add_properties(intel_hdmi, connector);
1746 intel_connector_attach_encoder(intel_connector, intel_encoder);
1747 drm_connector_register(connector);
1749 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1750 * 0xd. Failure to do so will result in spurious interrupts being
1751 * generated on the port when a cable is not attached.
1753 if (IS_G4X(dev) && !IS_GM45(dev)) {
1754 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1755 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1759 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
1761 struct intel_digital_port *intel_dig_port;
1762 struct intel_encoder *intel_encoder;
1763 struct intel_connector *intel_connector;
1765 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
1766 if (!intel_dig_port)
1769 intel_connector = intel_connector_alloc();
1770 if (!intel_connector) {
1771 kfree(intel_dig_port);
1775 intel_encoder = &intel_dig_port->base;
1777 drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
1778 DRM_MODE_ENCODER_TMDS);
1780 intel_encoder->compute_config = intel_hdmi_compute_config;
1781 intel_encoder->disable = intel_disable_hdmi;
1782 intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
1783 intel_encoder->get_config = intel_hdmi_get_config;
1784 if (IS_CHERRYVIEW(dev)) {
1785 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
1786 intel_encoder->pre_enable = chv_hdmi_pre_enable;
1787 intel_encoder->enable = vlv_enable_hdmi;
1788 intel_encoder->post_disable = chv_hdmi_post_disable;
1789 } else if (IS_VALLEYVIEW(dev)) {
1790 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
1791 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
1792 intel_encoder->enable = vlv_enable_hdmi;
1793 intel_encoder->post_disable = vlv_hdmi_post_disable;
1795 intel_encoder->pre_enable = intel_hdmi_pre_enable;
1796 intel_encoder->enable = intel_enable_hdmi;
1799 intel_encoder->type = INTEL_OUTPUT_HDMI;
1800 if (IS_CHERRYVIEW(dev)) {
1802 intel_encoder->crtc_mask = 1 << 2;
1804 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1806 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1808 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
1810 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
1811 * to work on real hardware. And since g4x can send infoframes to
1812 * only one port anyway, nothing is lost by allowing it.
1815 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
1817 intel_dig_port->port = port;
1818 intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
1819 intel_dig_port->dp.output_reg = 0;
1821 intel_hdmi_init_connector(intel_dig_port, intel_connector);