drivers/gpu/drm/i915/intel_hdmi.c

   1 /*
   2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2009 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Jesse Barnes <jesse.barnes@intel.com>
  27  */
  28
  29 #include <linux/i2c.h>
  30 #include <linux/slab.h>
  31 #include <linux/delay.h>
  32 #include <linux/hdmi.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_crtc.h>
  36 #include <drm/drm_edid.h>
  37 #include "intel_drv.h"
  38 #include <drm/i915_drm.h>
  39 #include "i915_drv.h"
  40
  41 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
  42 {
  43         return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
  44 }
  45
  46 static void
  47 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  48 {
  49         struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
  50         struct drm_i915_private *dev_priv = dev->dev_private;
  51         uint32_t enabled_bits;
  52
  53         enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  54
  55         WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
  56              "HDMI port enabled, expecting disabled\n");
  57 }
  58
  59 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  60 {
  61         struct intel_digital_port *intel_dig_port =
  62                 container_of(encoder, struct intel_digital_port, base.base);
  63         return &intel_dig_port->hdmi;
  64 }
  65
  66 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  67 {
  68         return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
  69 }
  70
  71 static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
  72 {
  73         switch (type) {
  74         case HDMI_INFOFRAME_TYPE_AVI:
  75                 return VIDEO_DIP_SELECT_AVI;
  76         case HDMI_INFOFRAME_TYPE_SPD:
  77                 return VIDEO_DIP_SELECT_SPD;
  78         case HDMI_INFOFRAME_TYPE_VENDOR:
  79                 return VIDEO_DIP_SELECT_VENDOR;
  80         default:
  81                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
  82                 return 0;
  83         }
  84 }
  85
  86 static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
  87 {
  88         switch (type) {
  89         case HDMI_INFOFRAME_TYPE_AVI:
  90                 return VIDEO_DIP_ENABLE_AVI;
  91         case HDMI_INFOFRAME_TYPE_SPD:
  92                 return VIDEO_DIP_ENABLE_SPD;
  93         case HDMI_INFOFRAME_TYPE_VENDOR:
  94                 return VIDEO_DIP_ENABLE_VENDOR;
  95         default:
  96                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
  97                 return 0;
  98         }
  99 }
 100
 101 static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
 102 {
 103         switch (type) {
 104         case HDMI_INFOFRAME_TYPE_AVI:
 105                 return VIDEO_DIP_ENABLE_AVI_HSW;
 106         case HDMI_INFOFRAME_TYPE_SPD:
 107                 return VIDEO_DIP_ENABLE_SPD_HSW;
 108         case HDMI_INFOFRAME_TYPE_VENDOR:
 109                 return VIDEO_DIP_ENABLE_VS_HSW;
 110         default:
 111                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
 112                 return 0;
 113         }
 114 }
 115
 116 static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type,
 117                                   enum transcoder cpu_transcoder,
 118                                   struct drm_i915_private *dev_priv)
 119 {
 120         switch (type) {
 121         case HDMI_INFOFRAME_TYPE_AVI:
 122                 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder);
 123         case HDMI_INFOFRAME_TYPE_SPD:
 124                 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder);
 125         case HDMI_INFOFRAME_TYPE_VENDOR:
 126                 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder);
 127         default:
 128                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
 129                 return 0;
 130         }
 131 }
 132
 133 static void g4x_write_infoframe(struct drm_encoder *encoder,
 134                                 enum hdmi_infoframe_type type,
 135                                 const void *frame, ssize_t len)
 136 {
 137         const uint32_t *data = frame;
 138         struct drm_device *dev = encoder->dev;
 139         struct drm_i915_private *dev_priv = dev->dev_private;
 140         u32 val = I915_READ(VIDEO_DIP_CTL);
 141         int i;
 142
 143         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 144
 145         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 146         val |= g4x_infoframe_index(type);
 147
 148         val &= ~g4x_infoframe_enable(type);
 149
 150         I915_WRITE(VIDEO_DIP_CTL, val);
 151
 152         mmiowb();
 153         for (i = 0; i < len; i += 4) {
 154                 I915_WRITE(VIDEO_DIP_DATA, *data);
 155                 data++;
 156         }
 157         /* Write every possible data byte to force correct ECC calculation. */
 158         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 159                 I915_WRITE(VIDEO_DIP_DATA, 0);
 160         mmiowb();
 161
 162         val |= g4x_infoframe_enable(type);
 163         val &= ~VIDEO_DIP_FREQ_MASK;
 164         val |= VIDEO_DIP_FREQ_VSYNC;
 165
 166         I915_WRITE(VIDEO_DIP_CTL, val);
 167         POSTING_READ(VIDEO_DIP_CTL);
 168 }
 169
 170 static bool g4x_infoframe_enabled(struct drm_encoder *encoder)
 171 {
 172         struct drm_device *dev = encoder->dev;
 173         struct drm_i915_private *dev_priv = dev->dev_private;
 174         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 175         u32 val = I915_READ(VIDEO_DIP_CTL);
 176
 177         if (VIDEO_DIP_PORT(intel_dig_port->port) == (val & VIDEO_DIP_PORT_MASK))
 178                 return val & VIDEO_DIP_ENABLE;
 179
 180         return false;
 181 }
 182
 183 static void ibx_write_infoframe(struct drm_encoder *encoder,
 184                                 enum hdmi_infoframe_type type,
 185                                 const void *frame, ssize_t len)
 186 {
 187         const uint32_t *data = frame;
 188         struct drm_device *dev = encoder->dev;
 189         struct drm_i915_private *dev_priv = dev->dev_private;
 190         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 191         int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 192         u32 val = I915_READ(reg);
 193
 194         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 195
 196         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 197         val |= g4x_infoframe_index(type);
 198
 199         val &= ~g4x_infoframe_enable(type);
 200
 201         I915_WRITE(reg, val);
 202
 203         mmiowb();
 204         for (i = 0; i < len; i += 4) {
 205                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 206                 data++;
 207         }
 208         /* Write every possible data byte to force correct ECC calculation. */
 209         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 210                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 211         mmiowb();
 212
 213         val |= g4x_infoframe_enable(type);
 214         val &= ~VIDEO_DIP_FREQ_MASK;
 215         val |= VIDEO_DIP_FREQ_VSYNC;
 216
 217         I915_WRITE(reg, val);
 218         POSTING_READ(reg);
 219 }
 220
 221 static bool ibx_infoframe_enabled(struct drm_encoder *encoder)
 222 {
 223         struct drm_device *dev = encoder->dev;
 224         struct drm_i915_private *dev_priv = dev->dev_private;
 225         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 226         int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 227         u32 val = I915_READ(reg);
 228
 229         return val & VIDEO_DIP_ENABLE;
 230 }
 231
 232 static void cpt_write_infoframe(struct drm_encoder *encoder,
 233                                 enum hdmi_infoframe_type type,
 234                                 const void *frame, ssize_t len)
 235 {
 236         const uint32_t *data = frame;
 237         struct drm_device *dev = encoder->dev;
 238         struct drm_i915_private *dev_priv = dev->dev_private;
 239         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 240         int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 241         u32 val = I915_READ(reg);
 242
 243         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 244
 245         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 246         val |= g4x_infoframe_index(type);
 247
 248         /* The DIP control register spec says that we need to update the AVI
 249          * infoframe without clearing its enable bit */
 250         if (type != HDMI_INFOFRAME_TYPE_AVI)
 251                 val &= ~g4x_infoframe_enable(type);
 252
 253         I915_WRITE(reg, val);
 254
 255         mmiowb();
 256         for (i = 0; i < len; i += 4) {
 257                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 258                 data++;
 259         }
 260         /* Write every possible data byte to force correct ECC calculation. */
 261         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 262                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 263         mmiowb();
 264
 265         val |= g4x_infoframe_enable(type);
 266         val &= ~VIDEO_DIP_FREQ_MASK;
 267         val |= VIDEO_DIP_FREQ_VSYNC;
 268
 269         I915_WRITE(reg, val);
 270         POSTING_READ(reg);
 271 }
 272
 273 static bool cpt_infoframe_enabled(struct drm_encoder *encoder)
 274 {
 275         struct drm_device *dev = encoder->dev;
 276         struct drm_i915_private *dev_priv = dev->dev_private;
 277         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 278         int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 279         u32 val = I915_READ(reg);
 280
 281         return val & VIDEO_DIP_ENABLE;
 282 }
 283
 284 static void vlv_write_infoframe(struct drm_encoder *encoder,
 285                                 enum hdmi_infoframe_type type,
 286                                 const void *frame, ssize_t len)
 287 {
 288         const uint32_t *data = frame;
 289         struct drm_device *dev = encoder->dev;
 290         struct drm_i915_private *dev_priv = dev->dev_private;
 291         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 292         int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 293         u32 val = I915_READ(reg);
 294
 295         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 296
 297         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 298         val |= g4x_infoframe_index(type);
 299
 300         val &= ~g4x_infoframe_enable(type);
 301
 302         I915_WRITE(reg, val);
 303
 304         mmiowb();
 305         for (i = 0; i < len; i += 4) {
 306                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 307                 data++;
 308         }
 309         /* Write every possible data byte to force correct ECC calculation. */
 310         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 311                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 312         mmiowb();
 313
 314         val |= g4x_infoframe_enable(type);
 315         val &= ~VIDEO_DIP_FREQ_MASK;
 316         val |= VIDEO_DIP_FREQ_VSYNC;
 317
 318         I915_WRITE(reg, val);
 319         POSTING_READ(reg);
 320 }
 321
 322 static bool vlv_infoframe_enabled(struct drm_encoder *encoder)
 323 {
 324         struct drm_device *dev = encoder->dev;
 325         struct drm_i915_private *dev_priv = dev->dev_private;
 326         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 327         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 328         int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 329         u32 val = I915_READ(reg);
 330
 331         if (VIDEO_DIP_PORT(intel_dig_port->port) == (val & VIDEO_DIP_PORT_MASK))
 332                 return val & VIDEO_DIP_ENABLE;
 333
 334         return false;
 335 }
 336
 337 static void hsw_write_infoframe(struct drm_encoder *encoder,
 338                                 enum hdmi_infoframe_type type,
 339                                 const void *frame, ssize_t len)
 340 {
 341         const uint32_t *data = frame;
 342         struct drm_device *dev = encoder->dev;
 343         struct drm_i915_private *dev_priv = dev->dev_private;
 344         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 345         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
 346         u32 data_reg;
 347         int i;
 348         u32 val = I915_READ(ctl_reg);
 349
 350         data_reg = hsw_infoframe_data_reg(type,
 351                                           intel_crtc->config->cpu_transcoder,
 352                                           dev_priv);
 353         if (data_reg == 0)
 354                 return;
 355
 356         val &= ~hsw_infoframe_enable(type);
 357         I915_WRITE(ctl_reg, val);
 358
 359         mmiowb();
 360         for (i = 0; i < len; i += 4) {
 361                 I915_WRITE(data_reg + i, *data);
 362                 data++;
 363         }
 364         /* Write every possible data byte to force correct ECC calculation. */
 365         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 366                 I915_WRITE(data_reg + i, 0);
 367         mmiowb();
 368
 369         val |= hsw_infoframe_enable(type);
 370         I915_WRITE(ctl_reg, val);
 371         POSTING_READ(ctl_reg);
 372 }
 373
 374 static bool hsw_infoframe_enabled(struct drm_encoder *encoder)
 375 {
 376         struct drm_device *dev = encoder->dev;
 377         struct drm_i915_private *dev_priv = dev->dev_private;
 378         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 379         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
 380         u32 val = I915_READ(ctl_reg);
 381
 382         return val & (VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
 383                       VIDEO_DIP_ENABLE_VS_HSW);
 384 }
 385
 386 /*
 387  * The data we write to the DIP data buffer registers is 1 byte bigger than the
 388  * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
 389  * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
 390  * used for both technologies.
 391  *
 392  * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
 393  * DW1:       DB3       | DB2 | DB1 | DB0
 394  * DW2:       DB7       | DB6 | DB5 | DB4
 395  * DW3: ...
 396  *
 397  * (HB is Header Byte, DB is Data Byte)
 398  *
 399  * The hdmi pack() functions don't know about that hardware specific hole so we
 400  * trick them by giving an offset into the buffer and moving back the header
 401  * bytes by one.
 402  */
 403 static void intel_write_infoframe(struct drm_encoder *encoder,
 404                                   union hdmi_infoframe *frame)
 405 {
 406         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 407         uint8_t buffer[VIDEO_DIP_DATA_SIZE];
 408         ssize_t len;
 409
 410         /* see comment above for the reason for this offset */
 411         len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
 412         if (len < 0)
 413                 return;
 414
 415         /* Insert the 'hole' (see big comment above) at position 3 */
 416         buffer[0] = buffer[1];
 417         buffer[1] = buffer[2];
 418         buffer[2] = buffer[3];
 419         buffer[3] = 0;
 420         len++;
 421
 422         intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);
 423 }
 424
 425 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
 426                                          struct drm_display_mode *adjusted_mode)
 427 {
 428         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 429         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 430         union hdmi_infoframe frame;
 431         int ret;
 432
 433         /* Set user selected PAR to incoming mode's member */
 434         adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio;
 435
 436         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 437                                                        adjusted_mode);
 438         if (ret < 0) {
 439                 DRM_ERROR("couldn't fill AVI infoframe\n");
 440                 return;
 441         }
 442
 443         if (intel_hdmi->rgb_quant_range_selectable) {
 444                 if (intel_crtc->config->limited_color_range)
 445                         frame.avi.quantization_range =
 446                                 HDMI_QUANTIZATION_RANGE_LIMITED;
 447                 else
 448                         frame.avi.quantization_range =
 449                                 HDMI_QUANTIZATION_RANGE_FULL;
 450         }
 451
 452         intel_write_infoframe(encoder, &frame);
 453 }
 454
 455 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 456 {
 457         union hdmi_infoframe frame;
 458         int ret;
 459
 460         ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
 461         if (ret < 0) {
 462                 DRM_ERROR("couldn't fill SPD infoframe\n");
 463                 return;
 464         }
 465
 466         frame.spd.sdi = HDMI_SPD_SDI_PC;
 467
 468         intel_write_infoframe(encoder, &frame);
 469 }
 470
 471 static void
 472 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
 473                               struct drm_display_mode *adjusted_mode)
 474 {
 475         union hdmi_infoframe frame;
 476         int ret;
 477
 478         ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
 479                                                           adjusted_mode);
 480         if (ret < 0)
 481                 return;
 482
 483         intel_write_infoframe(encoder, &frame);
 484 }
 485
 486 static void g4x_set_infoframes(struct drm_encoder *encoder,
 487                                bool enable,
 488                                struct drm_display_mode *adjusted_mode)
 489 {
 490         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 491         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 492         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 493         u32 reg = VIDEO_DIP_CTL;
 494         u32 val = I915_READ(reg);
 495         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 496
 497         assert_hdmi_port_disabled(intel_hdmi);
 498
 499         /* If the registers were not initialized yet, they might be zeroes,
 500          * which means we're selecting the AVI DIP and we're setting its
 501          * frequency to once. This seems to really confuse the HW and make
 502          * things stop working (the register spec says the AVI always needs to
 503          * be sent every VSync). So here we avoid writing to the register more
 504          * than we need and also explicitly select the AVI DIP and explicitly
 505          * set its frequency to every VSync. Avoiding to write it twice seems to
 506          * be enough to solve the problem, but being defensive shouldn't hurt us
 507          * either. */
 508         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 509
 510         if (!enable) {
 511                 if (!(val & VIDEO_DIP_ENABLE))
 512                         return;
 513                 val &= ~VIDEO_DIP_ENABLE;
 514                 I915_WRITE(reg, val);
 515                 POSTING_READ(reg);
 516                 return;
 517         }
 518
 519         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 520                 if (val & VIDEO_DIP_ENABLE) {
 521                         val &= ~VIDEO_DIP_ENABLE;
 522                         I915_WRITE(reg, val);
 523                         POSTING_READ(reg);
 524                 }
 525                 val &= ~VIDEO_DIP_PORT_MASK;
 526                 val |= port;
 527         }
 528
 529         val |= VIDEO_DIP_ENABLE;
 530         val &= ~VIDEO_DIP_ENABLE_VENDOR;
 531
 532         I915_WRITE(reg, val);
 533         POSTING_READ(reg);
 534
 535         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 536         intel_hdmi_set_spd_infoframe(encoder);
 537         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 538 }
 539
 540 static void ibx_set_infoframes(struct drm_encoder *encoder,
 541                                bool enable,
 542                                struct drm_display_mode *adjusted_mode)
 543 {
 544         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 545         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 546         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 547         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 548         u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 549         u32 val = I915_READ(reg);
 550         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 551
 552         assert_hdmi_port_disabled(intel_hdmi);
 553
 554         /* See the big comment in g4x_set_infoframes() */
 555         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 556
 557         if (!enable) {
 558                 if (!(val & VIDEO_DIP_ENABLE))
 559                         return;
 560                 val &= ~VIDEO_DIP_ENABLE;
 561                 I915_WRITE(reg, val);
 562                 POSTING_READ(reg);
 563                 return;
 564         }
 565
 566         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 567                 if (val & VIDEO_DIP_ENABLE) {
 568                         val &= ~VIDEO_DIP_ENABLE;
 569                         I915_WRITE(reg, val);
 570                         POSTING_READ(reg);
 571                 }
 572                 val &= ~VIDEO_DIP_PORT_MASK;
 573                 val |= port;
 574         }
 575
 576         val |= VIDEO_DIP_ENABLE;
 577         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 578                  VIDEO_DIP_ENABLE_GCP);
 579
 580         I915_WRITE(reg, val);
 581         POSTING_READ(reg);
 582
 583         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 584         intel_hdmi_set_spd_infoframe(encoder);
 585         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 586 }
 587
 588 static void cpt_set_infoframes(struct drm_encoder *encoder,
 589                                bool enable,
 590                                struct drm_display_mode *adjusted_mode)
 591 {
 592         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 593         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 594         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 595         u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 596         u32 val = I915_READ(reg);
 597
 598         assert_hdmi_port_disabled(intel_hdmi);
 599
 600         /* See the big comment in g4x_set_infoframes() */
 601         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 602
 603         if (!enable) {
 604                 if (!(val & VIDEO_DIP_ENABLE))
 605                         return;
 606                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI);
 607                 I915_WRITE(reg, val);
 608                 POSTING_READ(reg);
 609                 return;
 610         }
 611
 612         /* Set both together, unset both together: see the spec. */
 613         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
 614         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 615                  VIDEO_DIP_ENABLE_GCP);
 616
 617         I915_WRITE(reg, val);
 618         POSTING_READ(reg);
 619
 620         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 621         intel_hdmi_set_spd_infoframe(encoder);
 622         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 623 }
 624
 625 static void vlv_set_infoframes(struct drm_encoder *encoder,
 626                                bool enable,
 627                                struct drm_display_mode *adjusted_mode)
 628 {
 629         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 630         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 631         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 632         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 633         u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 634         u32 val = I915_READ(reg);
 635         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 636
 637         assert_hdmi_port_disabled(intel_hdmi);
 638
 639         /* See the big comment in g4x_set_infoframes() */
 640         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 641
 642         if (!enable) {
 643                 if (!(val & VIDEO_DIP_ENABLE))
 644                         return;
 645                 val &= ~VIDEO_DIP_ENABLE;
 646                 I915_WRITE(reg, val);
 647                 POSTING_READ(reg);
 648                 return;
 649         }
 650
 651         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 652                 if (val & VIDEO_DIP_ENABLE) {
 653                         val &= ~VIDEO_DIP_ENABLE;
 654                         I915_WRITE(reg, val);
 655                         POSTING_READ(reg);
 656                 }
 657                 val &= ~VIDEO_DIP_PORT_MASK;
 658                 val |= port;
 659         }
 660
 661         val |= VIDEO_DIP_ENABLE;
 662         val &= ~(VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_ENABLE_VENDOR |
 663                  VIDEO_DIP_ENABLE_GAMUT | VIDEO_DIP_ENABLE_GCP);
 664
 665         I915_WRITE(reg, val);
 666         POSTING_READ(reg);
 667
 668         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 669         intel_hdmi_set_spd_infoframe(encoder);
 670         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 671 }
 672
 673 static void hsw_set_infoframes(struct drm_encoder *encoder,
 674                                bool enable,
 675                                struct drm_display_mode *adjusted_mode)
 676 {
 677         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 678         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 679         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 680         u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
 681         u32 val = I915_READ(reg);
 682
 683         assert_hdmi_port_disabled(intel_hdmi);
 684
 685         if (!enable) {
 686                 I915_WRITE(reg, 0);
 687                 POSTING_READ(reg);
 688                 return;
 689         }
 690
 691         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
 692                  VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW);
 693
 694         I915_WRITE(reg, val);
 695         POSTING_READ(reg);
 696
 697         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 698         intel_hdmi_set_spd_infoframe(encoder);
 699         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 700 }
 701
 702 static void intel_hdmi_prepare(struct intel_encoder *encoder)
 703 {
 704         struct drm_device *dev = encoder->base.dev;
 705         struct drm_i915_private *dev_priv = dev->dev_private;
 706         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 707         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 708         struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
 709         u32 hdmi_val;
 710
 711         hdmi_val = SDVO_ENCODING_HDMI;
 712         if (!HAS_PCH_SPLIT(dev))
 713                 hdmi_val |= intel_hdmi->color_range;
 714         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 715                 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
 716         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 717                 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
 718
 719         if (crtc->config->pipe_bpp > 24)
 720                 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
 721         else
 722                 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
 723
 724         if (crtc->config->has_hdmi_sink)
 725                 hdmi_val |= HDMI_MODE_SELECT_HDMI;
 726
 727         if (HAS_PCH_CPT(dev))
 728                 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
 729         else if (IS_CHERRYVIEW(dev))
 730                 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
 731         else
 732                 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
 733
 734         I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
 735         POSTING_READ(intel_hdmi->hdmi_reg);
 736 }
 737
 738 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
 739                                     enum pipe *pipe)
 740 {
 741         struct drm_device *dev = encoder->base.dev;
 742         struct drm_i915_private *dev_priv = dev->dev_private;
 743         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 744         enum intel_display_power_domain power_domain;
 745         u32 tmp;
 746
 747         power_domain = intel_display_port_power_domain(encoder);
 748         if (!intel_display_power_is_enabled(dev_priv, power_domain))
 749                 return false;
 750
 751         tmp = I915_READ(intel_hdmi->hdmi_reg);
 752
 753         if (!(tmp & SDVO_ENABLE))
 754                 return false;
 755
 756         if (HAS_PCH_CPT(dev))
 757                 *pipe = PORT_TO_PIPE_CPT(tmp);
 758         else if (IS_CHERRYVIEW(dev))
 759                 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
 760         else
 761                 *pipe = PORT_TO_PIPE(tmp);
 762
 763         return true;
 764 }
 765
 766 static void intel_hdmi_get_config(struct intel_encoder *encoder,
 767                                   struct intel_crtc_state *pipe_config)
 768 {
 769         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 770         struct drm_device *dev = encoder->base.dev;
 771         struct drm_i915_private *dev_priv = dev->dev_private;
 772         u32 tmp, flags = 0;
 773         int dotclock;
 774
 775         tmp = I915_READ(intel_hdmi->hdmi_reg);
 776
 777         if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
 778                 flags |= DRM_MODE_FLAG_PHSYNC;
 779         else
 780                 flags |= DRM_MODE_FLAG_NHSYNC;
 781
 782         if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
 783                 flags |= DRM_MODE_FLAG_PVSYNC;
 784         else
 785                 flags |= DRM_MODE_FLAG_NVSYNC;
 786
 787         if (tmp & HDMI_MODE_SELECT_HDMI)
 788                 pipe_config->has_hdmi_sink = true;
 789
 790         if (intel_hdmi->infoframe_enabled(&encoder->base))
 791                 pipe_config->has_infoframe = true;
 792
 793         if (tmp & SDVO_AUDIO_ENABLE)
 794                 pipe_config->has_audio = true;
 795
 796         if (!HAS_PCH_SPLIT(dev) &&
 797             tmp & HDMI_COLOR_RANGE_16_235)
 798                 pipe_config->limited_color_range = true;
 799
 800         pipe_config->base.adjusted_mode.flags |= flags;
 801
 802         if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
 803                 dotclock = pipe_config->port_clock * 2 / 3;
 804         else
 805                 dotclock = pipe_config->port_clock;
 806
 807         if (HAS_PCH_SPLIT(dev_priv->dev))
 808                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
 809
 810         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
 811 }
 812
 813 static void intel_enable_hdmi(struct intel_encoder *encoder)
 814 {
 815         struct drm_device *dev = encoder->base.dev;
 816         struct drm_i915_private *dev_priv = dev->dev_private;
 817         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 818         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 819         u32 temp;
 820         u32 enable_bits = SDVO_ENABLE;
 821
 822         if (intel_crtc->config->has_audio)
 823                 enable_bits |= SDVO_AUDIO_ENABLE;
 824
 825         temp = I915_READ(intel_hdmi->hdmi_reg);
 826
 827         /* HW workaround for IBX, we need to move the port to transcoder A
 828          * before disabling it, so restore the transcoder select bit here. */
 829         if (HAS_PCH_IBX(dev))
 830                 enable_bits |= SDVO_PIPE_SEL(intel_crtc->pipe);
 831
 832         /* HW workaround, need to toggle enable bit off and on for 12bpc, but
 833          * we do this anyway which shows more stable in testing.
 834          */
 835         if (HAS_PCH_SPLIT(dev)) {
 836                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
 837                 POSTING_READ(intel_hdmi->hdmi_reg);
 838         }
 839
 840         temp |= enable_bits;
 841
 842         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 843         POSTING_READ(intel_hdmi->hdmi_reg);
 844
 845         /* HW workaround, need to write this twice for issue that may result
 846          * in first write getting masked.
 847          */
 848         if (HAS_PCH_SPLIT(dev)) {
 849                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
 850                 POSTING_READ(intel_hdmi->hdmi_reg);
 851         }
 852
 853         if (intel_crtc->config->has_audio) {
 854                 WARN_ON(!intel_crtc->config->has_hdmi_sink);
 855                 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
 856                                  pipe_name(intel_crtc->pipe));
 857                 intel_audio_codec_enable(encoder);
 858         }
 859 }
 860
 861 static void vlv_enable_hdmi(struct intel_encoder *encoder)
 862 {
 863 }
 864
 865 static void intel_disable_hdmi(struct intel_encoder *encoder)
 866 {
 867         struct drm_device *dev = encoder->base.dev;
 868         struct drm_i915_private *dev_priv = dev->dev_private;
 869         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 870         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 871         u32 temp;
 872         u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE;
 873
 874         if (crtc->config->has_audio)
 875                 intel_audio_codec_disable(encoder);
 876
 877         temp = I915_READ(intel_hdmi->hdmi_reg);
 878
 879         /* HW workaround for IBX, we need to move the port to transcoder A
 880          * before disabling it. */
 881         if (HAS_PCH_IBX(dev)) {
 882                 struct drm_crtc *crtc = encoder->base.crtc;
 883                 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
 884
 885                 if (temp & SDVO_PIPE_B_SELECT) {
 886                         temp &= ~SDVO_PIPE_B_SELECT;
 887                         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 888                         POSTING_READ(intel_hdmi->hdmi_reg);
 889
 890                         /* Again we need to write this twice. */
 891                         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 892                         POSTING_READ(intel_hdmi->hdmi_reg);
 893
 894                         /* Transcoder selection bits only update
 895                          * effectively on vblank. */
 896                         if (crtc)
 897                                 intel_wait_for_vblank(dev, pipe);
 898                         else
 899                                 msleep(50);
 900                 }
 901         }
 902
 903         /* HW workaround, need to toggle enable bit off and on for 12bpc, but
 904          * we do this anyway which shows more stable in testing.
 905          */
 906         if (HAS_PCH_SPLIT(dev)) {
 907                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
 908                 POSTING_READ(intel_hdmi->hdmi_reg);
 909         }
 910
 911         temp &= ~enable_bits;
 912
 913         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 914         POSTING_READ(intel_hdmi->hdmi_reg);
 915
 916         /* HW workaround, need to write this twice for issue that may result
 917          * in first write getting masked.
 918          */
 919         if (HAS_PCH_SPLIT(dev)) {
 920                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
 921                 POSTING_READ(intel_hdmi->hdmi_reg);
 922         }
 923 }
 924
 925 static int hdmi_portclock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit)
 926 {
 927         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
 928
 929         if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev))
 930                 return 165000;
 931         else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8)
 932                 return 300000;
 933         else
 934                 return 225000;
 935 }
 936
 937 static enum drm_mode_status
 938 intel_hdmi_mode_valid(struct drm_connector *connector,
 939                       struct drm_display_mode *mode)
 940 {
 941         int clock = mode->clock;
 942
 943         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 944                 clock *= 2;
 945
 946         if (clock > hdmi_portclock_limit(intel_attached_hdmi(connector),
 947                                          true))
 948                 return MODE_CLOCK_HIGH;
 949         if (clock < 20000)
 950                 return MODE_CLOCK_LOW;
 951
 952         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 953                 return MODE_NO_DBLESCAN;
 954
 955         return MODE_OK;
 956 }
 957
 958 static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)
 959 {
 960         struct drm_device *dev = crtc_state->base.crtc->dev;
 961         struct drm_atomic_state *state;
 962         struct intel_encoder *encoder;
 963         struct drm_connector_state *connector_state;
 964         int count = 0, count_hdmi = 0;
 965         int i;
 966
 967         if (HAS_GMCH_DISPLAY(dev))
 968                 return false;
 969
 970         state = crtc_state->base.state;
 971
 972         for (i = 0; i < state->num_connector; i++) {
 973                 if (!state->connectors[i])
 974                         continue;
 975
 976                 connector_state = state->connector_states[i];
 977                 if (connector_state->crtc != crtc_state->base.crtc)
 978                         continue;
 979
 980                 encoder = to_intel_encoder(connector_state->best_encoder);
 981
 982                 count_hdmi += encoder->type == INTEL_OUTPUT_HDMI;
 983                 count++;
 984         }
 985
 986         /*
 987          * HDMI 12bpc affects the clocks, so it's only possible
 988          * when not cloning with other encoder types.
 989          */
 990         return count_hdmi > 0 && count_hdmi == count;
 991 }
 992
 993 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
 994                                struct intel_crtc_state *pipe_config)
 995 {
 996         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 997         struct drm_device *dev = encoder->base.dev;
 998         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 999         int clock_12bpc = pipe_config->base.adjusted_mode.crtc_clock * 3 / 2;
1000         int portclock_limit = hdmi_portclock_limit(intel_hdmi, false);
1001         int desired_bpp;
1002
1003         pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink;
1004
1005         if (pipe_config->has_hdmi_sink)
1006                 pipe_config->has_infoframe = true;
1007
1008         if (intel_hdmi->color_range_auto) {
1009                 /* See CEA-861-E - 5.1 Default Encoding Parameters */
1010                 if (pipe_config->has_hdmi_sink &&
1011                     drm_match_cea_mode(adjusted_mode) > 1)
1012                         intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
1013                 else
1014                         intel_hdmi->color_range = 0;
1015         }
1016
1017         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
1018                 pipe_config->pixel_multiplier = 2;
1019         }
1020
1021         if (intel_hdmi->color_range)
1022                 pipe_config->limited_color_range = true;
1023
1024         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
1025                 pipe_config->has_pch_encoder = true;
1026
1027         if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio)
1028                 pipe_config->has_audio = true;
1029
1030         /*
1031          * HDMI is either 12 or 8, so if the display lets 10bpc sneak
1032          * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
1033          * outputs. We also need to check that the higher clock still fits
1034          * within limits.
1035          */
1036         if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink &&
1037             clock_12bpc <= portclock_limit &&
1038             hdmi_12bpc_possible(pipe_config)) {
1039                 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
1040                 desired_bpp = 12*3;
1041
1042                 /* Need to adjust the port link by 1.5x for 12bpc. */
1043                 pipe_config->port_clock = clock_12bpc;
1044         } else {
1045                 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
1046                 desired_bpp = 8*3;
1047         }
1048
1049         if (!pipe_config->bw_constrained) {
1050                 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
1051                 pipe_config->pipe_bpp = desired_bpp;
1052         }
1053
1054         if (adjusted_mode->crtc_clock > portclock_limit) {
1055                 DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n");
1056                 return false;
1057         }
1058
1059         return true;
1060 }
1061
1062 static void
1063 intel_hdmi_unset_edid(struct drm_connector *connector)
1064 {
1065         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1066
1067         intel_hdmi->has_hdmi_sink = false;
1068         intel_hdmi->has_audio = false;
1069         intel_hdmi->rgb_quant_range_selectable = false;
1070
1071         kfree(to_intel_connector(connector)->detect_edid);
1072         to_intel_connector(connector)->detect_edid = NULL;
1073 }
1074
1075 static bool
1076 intel_hdmi_set_edid(struct drm_connector *connector)
1077 {
1078         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1079         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1080         struct intel_encoder *intel_encoder =
1081                 &hdmi_to_dig_port(intel_hdmi)->base;
1082         enum intel_display_power_domain power_domain;
1083         struct edid *edid;
1084         bool connected = false;
1085
1086         power_domain = intel_display_port_power_domain(intel_encoder);
1087         intel_display_power_get(dev_priv, power_domain);
1088
1089         edid = drm_get_edid(connector,
1090                             intel_gmbus_get_adapter(dev_priv,
1091                                                     intel_hdmi->ddc_bus));
1092
1093         intel_display_power_put(dev_priv, power_domain);
1094
1095         to_intel_connector(connector)->detect_edid = edid;
1096         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
1097                 intel_hdmi->rgb_quant_range_selectable =
1098                         drm_rgb_quant_range_selectable(edid);
1099
1100                 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
1101                 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
1102                         intel_hdmi->has_audio =
1103                                 intel_hdmi->force_audio == HDMI_AUDIO_ON;
1104
1105                 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
1106                         intel_hdmi->has_hdmi_sink =
1107                                 drm_detect_hdmi_monitor(edid);
1108
1109                 connected = true;
1110         }
1111
1112         return connected;
1113 }
1114
1115 static enum drm_connector_status
1116 intel_hdmi_detect(struct drm_connector *connector, bool force)
1117 {
1118         enum drm_connector_status status;
1119
1120         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1121                       connector->base.id, connector->name);
1122
1123         intel_hdmi_unset_edid(connector);
1124
1125         if (intel_hdmi_set_edid(connector)) {
1126                 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1127
1128                 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1129                 status = connector_status_connected;
1130         } else
1131                 status = connector_status_disconnected;
1132
1133         return status;
1134 }
1135
1136 static void
1137 intel_hdmi_force(struct drm_connector *connector)
1138 {
1139         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1140
1141         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1142                       connector->base.id, connector->name);
1143
1144         intel_hdmi_unset_edid(connector);
1145
1146         if (connector->status != connector_status_connected)
1147                 return;
1148
1149         intel_hdmi_set_edid(connector);
1150         hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1151 }
1152
1153 static int intel_hdmi_get_modes(struct drm_connector *connector)
1154 {
1155         struct edid *edid;
1156
1157         edid = to_intel_connector(connector)->detect_edid;
1158         if (edid == NULL)
1159                 return 0;
1160
1161         return intel_connector_update_modes(connector, edid);
1162 }
1163
1164 static bool
1165 intel_hdmi_detect_audio(struct drm_connector *connector)
1166 {
1167         bool has_audio = false;
1168         struct edid *edid;
1169
1170         edid = to_intel_connector(connector)->detect_edid;
1171         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL)
1172                 has_audio = drm_detect_monitor_audio(edid);
1173
1174         return has_audio;
1175 }
1176
1177 static int
1178 intel_hdmi_set_property(struct drm_connector *connector,
1179                         struct drm_property *property,
1180                         uint64_t val)
1181 {
1182         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1183         struct intel_digital_port *intel_dig_port =
1184                 hdmi_to_dig_port(intel_hdmi);
1185         struct drm_i915_private *dev_priv = connector->dev->dev_private;
1186         int ret;
1187
1188         ret = drm_object_property_set_value(&connector->base, property, val);
1189         if (ret)
1190                 return ret;
1191
1192         if (property == dev_priv->force_audio_property) {
1193                 enum hdmi_force_audio i = val;
1194                 bool has_audio;
1195
1196                 if (i == intel_hdmi->force_audio)
1197                         return 0;
1198
1199                 intel_hdmi->force_audio = i;
1200
1201                 if (i == HDMI_AUDIO_AUTO)
1202                         has_audio = intel_hdmi_detect_audio(connector);
1203                 else
1204                         has_audio = (i == HDMI_AUDIO_ON);
1205
1206                 if (i == HDMI_AUDIO_OFF_DVI)
1207                         intel_hdmi->has_hdmi_sink = 0;
1208
1209                 intel_hdmi->has_audio = has_audio;
1210                 goto done;
1211         }
1212
1213         if (property == dev_priv->broadcast_rgb_property) {
1214                 bool old_auto = intel_hdmi->color_range_auto;
1215                 uint32_t old_range = intel_hdmi->color_range;
1216
1217                 switch (val) {
1218                 case INTEL_BROADCAST_RGB_AUTO:
1219                         intel_hdmi->color_range_auto = true;
1220                         break;
1221                 case INTEL_BROADCAST_RGB_FULL:
1222                         intel_hdmi->color_range_auto = false;
1223                         intel_hdmi->color_range = 0;
1224                         break;
1225                 case INTEL_BROADCAST_RGB_LIMITED:
1226                         intel_hdmi->color_range_auto = false;
1227                         intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
1228                         break;
1229                 default:
1230                         return -EINVAL;
1231                 }
1232
1233                 if (old_auto == intel_hdmi->color_range_auto &&
1234                     old_range == intel_hdmi->color_range)
1235                         return 0;
1236
1237                 goto done;
1238         }
1239
1240         if (property == connector->dev->mode_config.aspect_ratio_property) {
1241                 switch (val) {
1242                 case DRM_MODE_PICTURE_ASPECT_NONE:
1243                         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1244                         break;
1245                 case DRM_MODE_PICTURE_ASPECT_4_3:
1246                         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3;
1247                         break;
1248                 case DRM_MODE_PICTURE_ASPECT_16_9:
1249                         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
1250                         break;
1251                 default:
1252                         return -EINVAL;
1253                 }
1254                 goto done;
1255         }
1256
1257         return -EINVAL;
1258
1259 done:
1260         if (intel_dig_port->base.base.crtc)
1261                 intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
1262
1263         return 0;
1264 }
1265
1266 static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
1267 {
1268         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1269         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1270         struct drm_display_mode *adjusted_mode =
1271                 &intel_crtc->config->base.adjusted_mode;
1272
1273         intel_hdmi_prepare(encoder);
1274
1275         intel_hdmi->set_infoframes(&encoder->base,
1276                                    intel_crtc->config->has_hdmi_sink,
1277                                    adjusted_mode);
1278 }
1279
1280 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
1281 {
1282         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1283         struct intel_hdmi *intel_hdmi = &dport->hdmi;
1284         struct drm_device *dev = encoder->base.dev;
1285         struct drm_i915_private *dev_priv = dev->dev_private;
1286         struct intel_crtc *intel_crtc =
1287                 to_intel_crtc(encoder->base.crtc);
1288         struct drm_display_mode *adjusted_mode =
1289                 &intel_crtc->config->base.adjusted_mode;
1290         enum dpio_channel port = vlv_dport_to_channel(dport);
1291         int pipe = intel_crtc->pipe;
1292         u32 val;
1293
1294         /* Enable clock channels for this port */
1295         mutex_lock(&dev_priv->dpio_lock);
1296         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1297         val = 0;
1298         if (pipe)
1299                 val |= (1<<21);
1300         else
1301                 val &= ~(1<<21);
1302         val |= 0x001000c4;
1303         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1304
1305         /* HDMI 1.0V-2dB */
1306         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
1307         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
1308         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
1309         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
1310         vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
1311         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
1312         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1313         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1314
1315         /* Program lane clock */
1316         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1317         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1318         mutex_unlock(&dev_priv->dpio_lock);
1319
1320         intel_hdmi->set_infoframes(&encoder->base,
1321                                    intel_crtc->config->has_hdmi_sink,
1322                                    adjusted_mode);
1323
1324         intel_enable_hdmi(encoder);
1325
1326         vlv_wait_port_ready(dev_priv, dport);
1327 }
1328
1329 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1330 {
1331         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1332         struct drm_device *dev = encoder->base.dev;
1333         struct drm_i915_private *dev_priv = dev->dev_private;
1334         struct intel_crtc *intel_crtc =
1335                 to_intel_crtc(encoder->base.crtc);
1336         enum dpio_channel port = vlv_dport_to_channel(dport);
1337         int pipe = intel_crtc->pipe;
1338
1339         intel_hdmi_prepare(encoder);
1340
1341         /* Program Tx lane resets to default */
1342         mutex_lock(&dev_priv->dpio_lock);
1343         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1344                          DPIO_PCS_TX_LANE2_RESET |
1345                          DPIO_PCS_TX_LANE1_RESET);
1346         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1347                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1348                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1349                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1350                          DPIO_PCS_CLK_SOFT_RESET);
1351
1352         /* Fix up inter-pair skew failure */
1353         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1354         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1355         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1356
1357         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1358         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1359         mutex_unlock(&dev_priv->dpio_lock);
1360 }
1361
1362 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1363 {
1364         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1365         struct drm_device *dev = encoder->base.dev;
1366         struct drm_i915_private *dev_priv = dev->dev_private;
1367         struct intel_crtc *intel_crtc =
1368                 to_intel_crtc(encoder->base.crtc);
1369         enum dpio_channel ch = vlv_dport_to_channel(dport);
1370         enum pipe pipe = intel_crtc->pipe;
1371         u32 val;
1372
1373         intel_hdmi_prepare(encoder);
1374
1375         mutex_lock(&dev_priv->dpio_lock);
1376
1377         /* program left/right clock distribution */
1378         if (pipe != PIPE_B) {
1379                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1380                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1381                 if (ch == DPIO_CH0)
1382                         val |= CHV_BUFLEFTENA1_FORCE;
1383                 if (ch == DPIO_CH1)
1384                         val |= CHV_BUFRIGHTENA1_FORCE;
1385                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1386         } else {
1387                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1388                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1389                 if (ch == DPIO_CH0)
1390                         val |= CHV_BUFLEFTENA2_FORCE;
1391                 if (ch == DPIO_CH1)
1392                         val |= CHV_BUFRIGHTENA2_FORCE;
1393                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1394         }
1395
1396         /* program clock channel usage */
1397         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
1398         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1399         if (pipe != PIPE_B)
1400                 val &= ~CHV_PCS_USEDCLKCHANNEL;
1401         else
1402                 val |= CHV_PCS_USEDCLKCHANNEL;
1403         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
1404
1405         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
1406         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1407         if (pipe != PIPE_B)
1408                 val &= ~CHV_PCS_USEDCLKCHANNEL;
1409         else
1410                 val |= CHV_PCS_USEDCLKCHANNEL;
1411         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
1412
1413         /*
1414          * This a a bit weird since generally CL
1415          * matches the pipe, but here we need to
1416          * pick the CL based on the port.
1417          */
1418         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
1419         if (pipe != PIPE_B)
1420                 val &= ~CHV_CMN_USEDCLKCHANNEL;
1421         else
1422                 val |= CHV_CMN_USEDCLKCHANNEL;
1423         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
1424
1425         mutex_unlock(&dev_priv->dpio_lock);
1426 }
1427
1428 static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
1429 {
1430         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1431         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1432         struct intel_crtc *intel_crtc =
1433                 to_intel_crtc(encoder->base.crtc);
1434         enum dpio_channel port = vlv_dport_to_channel(dport);
1435         int pipe = intel_crtc->pipe;
1436
1437         /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1438         mutex_lock(&dev_priv->dpio_lock);
1439         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
1440         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
1441         mutex_unlock(&dev_priv->dpio_lock);
1442 }
1443
1444 static void chv_hdmi_post_disable(struct intel_encoder *encoder)
1445 {
1446         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1447         struct drm_device *dev = encoder->base.dev;
1448         struct drm_i915_private *dev_priv = dev->dev_private;
1449         struct intel_crtc *intel_crtc =
1450                 to_intel_crtc(encoder->base.crtc);
1451         enum dpio_channel ch = vlv_dport_to_channel(dport);
1452         enum pipe pipe = intel_crtc->pipe;
1453         u32 val;
1454
1455         mutex_lock(&dev_priv->dpio_lock);
1456
1457         /* Propagate soft reset to data lane reset */
1458         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
1459         val |= CHV_PCS_REQ_SOFTRESET_EN;
1460         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
1461
1462         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1463         val |= CHV_PCS_REQ_SOFTRESET_EN;
1464         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1465
1466         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
1467         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1468         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
1469
1470         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
1471         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1472         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
1473
1474         mutex_unlock(&dev_priv->dpio_lock);
1475 }
1476
1477 static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
1478 {
1479         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1480         struct intel_hdmi *intel_hdmi = &dport->hdmi;
1481         struct drm_device *dev = encoder->base.dev;
1482         struct drm_i915_private *dev_priv = dev->dev_private;
1483         struct intel_crtc *intel_crtc =
1484                 to_intel_crtc(encoder->base.crtc);
1485         struct drm_display_mode *adjusted_mode =
1486                 &intel_crtc->config->base.adjusted_mode;
1487         enum dpio_channel ch = vlv_dport_to_channel(dport);
1488         int pipe = intel_crtc->pipe;
1489         int data, i;
1490         u32 val;
1491
1492         mutex_lock(&dev_priv->dpio_lock);
1493
1494         /* allow hardware to manage TX FIFO reset source */
1495         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
1496         val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
1497         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
1498
1499         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
1500         val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
1501         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
1502
1503         /* Deassert soft data lane reset*/
1504         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
1505         val |= CHV_PCS_REQ_SOFTRESET_EN;
1506         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
1507
1508         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1509         val |= CHV_PCS_REQ_SOFTRESET_EN;
1510         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1511
1512         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
1513         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1514         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
1515
1516         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
1517         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1518         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
1519
1520         /* Program Tx latency optimal setting */
1521         for (i = 0; i < 4; i++) {
1522                 /* Set the latency optimal bit */
1523                 data = (i == 1) ? 0x0 : 0x6;
1524                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
1525                                 data << DPIO_FRC_LATENCY_SHFIT);
1526
1527                 /* Set the upar bit */
1528                 data = (i == 1) ? 0x0 : 0x1;
1529                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
1530                                 data << DPIO_UPAR_SHIFT);
1531         }
1532
1533         /* Data lane stagger programming */
1534         /* FIXME: Fix up value only after power analysis */
1535
1536         /* Clear calc init */
1537         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1538         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
1539         val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
1540         val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1541         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1542
1543         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1544         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
1545         val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
1546         val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1547         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1548
1549         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
1550         val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
1551         val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
1552         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
1553
1554         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
1555         val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
1556         val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
1557         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
1558
1559         /* FIXME: Program the support xxx V-dB */
1560         /* Use 800mV-0dB */
1561         for (i = 0; i < 4; i++) {
1562                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
1563                 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
1564                 val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT;
1565                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
1566         }
1567
1568         for (i = 0; i < 4; i++) {
1569                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1570                 val &= ~DPIO_SWING_MARGIN000_MASK;
1571                 val |= 102 << DPIO_SWING_MARGIN000_SHIFT;
1572                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
1573         }
1574
1575         /* Disable unique transition scale */
1576         for (i = 0; i < 4; i++) {
1577                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
1578                 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
1579                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
1580         }
1581
1582         /* Additional steps for 1200mV-0dB */
1583 #if 0
1584         val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch));
1585         if (ch)
1586                 val |= DPIO_TX_UNIQ_TRANS_SCALE_CH1;
1587         else
1588                 val |= DPIO_TX_UNIQ_TRANS_SCALE_CH0;
1589         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val);
1590
1591         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch),
1592                         vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch)) |
1593                                 (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT));
1594 #endif
1595         /* Start swing calculation */
1596         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1597         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1598         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1599
1600         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1601         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1602         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1603
1604         /* LRC Bypass */
1605         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1606         val |= DPIO_LRC_BYPASS;
1607         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
1608
1609         mutex_unlock(&dev_priv->dpio_lock);
1610
1611         intel_hdmi->set_infoframes(&encoder->base,
1612                                    intel_crtc->config->has_hdmi_sink,
1613                                    adjusted_mode);
1614
1615         intel_enable_hdmi(encoder);
1616
1617         vlv_wait_port_ready(dev_priv, dport);
1618 }
1619
1620 static void intel_hdmi_destroy(struct drm_connector *connector)
1621 {
1622         kfree(to_intel_connector(connector)->detect_edid);
1623         drm_connector_cleanup(connector);
1624         kfree(connector);
1625 }
1626
1627 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
1628         .dpms = intel_connector_dpms,
1629         .detect = intel_hdmi_detect,
1630         .force = intel_hdmi_force,
1631         .fill_modes = drm_helper_probe_single_connector_modes,
1632         .set_property = intel_hdmi_set_property,
1633         .atomic_get_property = intel_connector_atomic_get_property,
1634         .destroy = intel_hdmi_destroy,
1635         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1636         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1637 };
1638
1639 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
1640         .get_modes = intel_hdmi_get_modes,
1641         .mode_valid = intel_hdmi_mode_valid,
1642         .best_encoder = intel_best_encoder,
1643 };
1644
1645 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
1646         .destroy = intel_encoder_destroy,
1647 };
1648
1649 static void
1650 intel_attach_aspect_ratio_property(struct drm_connector *connector)
1651 {
1652         if (!drm_mode_create_aspect_ratio_property(connector->dev))
1653                 drm_object_attach_property(&connector->base,
1654                         connector->dev->mode_config.aspect_ratio_property,
1655                         DRM_MODE_PICTURE_ASPECT_NONE);
1656 }
1657
1658 static void
1659 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
1660 {
1661         intel_attach_force_audio_property(connector);
1662         intel_attach_broadcast_rgb_property(connector);
1663         intel_hdmi->color_range_auto = true;
1664         intel_attach_aspect_ratio_property(connector);
1665         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1666 }
1667
1668 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1669                                struct intel_connector *intel_connector)
1670 {
1671         struct drm_connector *connector = &intel_connector->base;
1672         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
1673         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1674         struct drm_device *dev = intel_encoder->base.dev;
1675         struct drm_i915_private *dev_priv = dev->dev_private;
1676         enum port port = intel_dig_port->port;
1677
1678         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
1679                            DRM_MODE_CONNECTOR_HDMIA);
1680         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
1681
1682         connector->interlace_allowed = 1;
1683         connector->doublescan_allowed = 0;
1684         connector->stereo_allowed = 1;
1685
1686         switch (port) {
1687         case PORT_B:
1688                 if (IS_BROXTON(dev_priv))
1689                         intel_hdmi->ddc_bus = GMBUS_PIN_1_BXT;
1690                 else
1691                         intel_hdmi->ddc_bus = GMBUS_PIN_DPB;
1692                 intel_encoder->hpd_pin = HPD_PORT_B;
1693                 break;
1694         case PORT_C:
1695                 if (IS_BROXTON(dev_priv))
1696                         intel_hdmi->ddc_bus = GMBUS_PIN_2_BXT;
1697                 else
1698                         intel_hdmi->ddc_bus = GMBUS_PIN_DPC;
1699                 intel_encoder->hpd_pin = HPD_PORT_C;
1700                 break;
1701         case PORT_D:
1702                 if (WARN_ON(IS_BROXTON(dev_priv)))
1703                         intel_hdmi->ddc_bus = GMBUS_PIN_DISABLED;
1704                 else if (IS_CHERRYVIEW(dev_priv))
1705                         intel_hdmi->ddc_bus = GMBUS_PIN_DPD_CHV;
1706                 else
1707                         intel_hdmi->ddc_bus = GMBUS_PIN_DPD;
1708                 intel_encoder->hpd_pin = HPD_PORT_D;
1709                 break;
1710         case PORT_A:
1711                 intel_encoder->hpd_pin = HPD_PORT_A;
1712                 /* Internal port only for eDP. */
1713         default:
1714                 BUG();
1715         }
1716
1717         if (IS_VALLEYVIEW(dev)) {
1718                 intel_hdmi->write_infoframe = vlv_write_infoframe;
1719                 intel_hdmi->set_infoframes = vlv_set_infoframes;
1720                 intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
1721         } else if (IS_G4X(dev)) {
1722                 intel_hdmi->write_infoframe = g4x_write_infoframe;
1723                 intel_hdmi->set_infoframes = g4x_set_infoframes;
1724                 intel_hdmi->infoframe_enabled = g4x_infoframe_enabled;
1725         } else if (HAS_DDI(dev)) {
1726                 intel_hdmi->write_infoframe = hsw_write_infoframe;
1727                 intel_hdmi->set_infoframes = hsw_set_infoframes;
1728                 intel_hdmi->infoframe_enabled = hsw_infoframe_enabled;
1729         } else if (HAS_PCH_IBX(dev)) {
1730                 intel_hdmi->write_infoframe = ibx_write_infoframe;
1731                 intel_hdmi->set_infoframes = ibx_set_infoframes;
1732                 intel_hdmi->infoframe_enabled = ibx_infoframe_enabled;
1733         } else {
1734                 intel_hdmi->write_infoframe = cpt_write_infoframe;
1735                 intel_hdmi->set_infoframes = cpt_set_infoframes;
1736                 intel_hdmi->infoframe_enabled = cpt_infoframe_enabled;
1737         }
1738
1739         if (HAS_DDI(dev))
1740                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
1741         else
1742                 intel_connector->get_hw_state = intel_connector_get_hw_state;
1743         intel_connector->unregister = intel_connector_unregister;
1744
1745         intel_hdmi_add_properties(intel_hdmi, connector);
1746
1747         intel_connector_attach_encoder(intel_connector, intel_encoder);
1748         drm_connector_register(connector);
1749
1750         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1751          * 0xd.  Failure to do so will result in spurious interrupts being
1752          * generated on the port when a cable is not attached.
1753          */
1754         if (IS_G4X(dev) && !IS_GM45(dev)) {
1755                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1756                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1757         }
1758 }
1759
1760 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
1761 {
1762         struct intel_digital_port *intel_dig_port;
1763         struct intel_encoder *intel_encoder;
1764         struct intel_connector *intel_connector;
1765
1766         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
1767         if (!intel_dig_port)
1768                 return;
1769
1770         intel_connector = intel_connector_alloc();
1771         if (!intel_connector) {
1772                 kfree(intel_dig_port);
1773                 return;
1774         }
1775
1776         intel_encoder = &intel_dig_port->base;
1777
1778         drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
1779                          DRM_MODE_ENCODER_TMDS);
1780
1781         intel_encoder->compute_config = intel_hdmi_compute_config;
1782         intel_encoder->disable = intel_disable_hdmi;
1783         intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
1784         intel_encoder->get_config = intel_hdmi_get_config;
1785         if (IS_CHERRYVIEW(dev)) {
1786                 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
1787                 intel_encoder->pre_enable = chv_hdmi_pre_enable;
1788                 intel_encoder->enable = vlv_enable_hdmi;
1789                 intel_encoder->post_disable = chv_hdmi_post_disable;
1790         } else if (IS_VALLEYVIEW(dev)) {
1791                 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
1792                 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
1793                 intel_encoder->enable = vlv_enable_hdmi;
1794                 intel_encoder->post_disable = vlv_hdmi_post_disable;
1795         } else {
1796                 intel_encoder->pre_enable = intel_hdmi_pre_enable;
1797                 intel_encoder->enable = intel_enable_hdmi;
1798         }
1799
1800         intel_encoder->type = INTEL_OUTPUT_HDMI;
1801         if (IS_CHERRYVIEW(dev)) {
1802                 if (port == PORT_D)
1803                         intel_encoder->crtc_mask = 1 << 2;
1804                 else
1805                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1806         } else {
1807                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1808         }
1809         intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
1810         /*
1811          * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
1812          * to work on real hardware. And since g4x can send infoframes to
1813          * only one port anyway, nothing is lost by allowing it.
1814          */
1815         if (IS_G4X(dev))
1816                 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
1817
1818         intel_dig_port->port = port;
1819         intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
1820         intel_dig_port->dp.output_reg = 0;
1821
1822         intel_hdmi_init_connector(intel_dig_port, intel_connector);
1823 }