2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2008,2010 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
26 * Eric Anholt <eric@anholt.net>
27 * Chris Wilson <chris@chris-wilson.co.uk>
29 #include <linux/i2c.h>
30 #include <linux/i2c-algo-bit.h>
31 #include <linux/export.h>
33 #include "intel_drv.h"
34 #include <drm/i915_drm.h>
42 static const struct gmbus_port gmbus_ports[] = {
51 /* Intel GPIO access functions */
53 #define I2C_RISEFALL_TIME 10
55 static inline struct intel_gmbus *
56 to_intel_gmbus(struct i2c_adapter *i2c)
58 return container_of(i2c, struct intel_gmbus, adapter);
62 intel_i2c_reset(struct drm_device *dev)
64 struct drm_i915_private *dev_priv = dev->dev_private;
65 I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0);
66 I915_WRITE(dev_priv->gpio_mmio_base + GMBUS4, 0);
69 static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
73 /* When using bit bashing for I2C, this bit needs to be set to 1 */
74 if (!IS_PINEVIEW(dev_priv->dev))
77 val = I915_READ(DSPCLK_GATE_D);
79 val |= DPCUNIT_CLOCK_GATE_DISABLE;
81 val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
82 I915_WRITE(DSPCLK_GATE_D, val);
85 static u32 get_reserved(struct intel_gmbus *bus)
87 struct drm_i915_private *dev_priv = bus->dev_priv;
88 struct drm_device *dev = dev_priv->dev;
91 /* On most chips, these bits must be preserved in software. */
92 if (!IS_I830(dev) && !IS_845G(dev))
93 reserved = I915_READ_NOTRACE(bus->gpio_reg) &
94 (GPIO_DATA_PULLUP_DISABLE |
95 GPIO_CLOCK_PULLUP_DISABLE);
100 static int get_clock(void *data)
102 struct intel_gmbus *bus = data;
103 struct drm_i915_private *dev_priv = bus->dev_priv;
104 u32 reserved = get_reserved(bus);
105 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);
106 I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
107 return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
110 static int get_data(void *data)
112 struct intel_gmbus *bus = data;
113 struct drm_i915_private *dev_priv = bus->dev_priv;
114 u32 reserved = get_reserved(bus);
115 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);
116 I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
117 return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
120 static void set_clock(void *data, int state_high)
122 struct intel_gmbus *bus = data;
123 struct drm_i915_private *dev_priv = bus->dev_priv;
124 u32 reserved = get_reserved(bus);
128 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
130 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
133 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits);
134 POSTING_READ(bus->gpio_reg);
137 static void set_data(void *data, int state_high)
139 struct intel_gmbus *bus = data;
140 struct drm_i915_private *dev_priv = bus->dev_priv;
141 u32 reserved = get_reserved(bus);
145 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
147 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
150 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits);
151 POSTING_READ(bus->gpio_reg);
155 intel_gpio_pre_xfer(struct i2c_adapter *adapter)
157 struct intel_gmbus *bus = container_of(adapter,
160 struct drm_i915_private *dev_priv = bus->dev_priv;
162 intel_i2c_reset(dev_priv->dev);
163 intel_i2c_quirk_set(dev_priv, true);
166 udelay(I2C_RISEFALL_TIME);
171 intel_gpio_post_xfer(struct i2c_adapter *adapter)
173 struct intel_gmbus *bus = container_of(adapter,
176 struct drm_i915_private *dev_priv = bus->dev_priv;
180 intel_i2c_quirk_set(dev_priv, false);
184 intel_gpio_setup(struct intel_gmbus *bus, u32 pin)
186 struct drm_i915_private *dev_priv = bus->dev_priv;
187 struct i2c_algo_bit_data *algo;
189 algo = &bus->bit_algo;
191 /* -1 to map pin pair to gmbus index */
192 bus->gpio_reg = dev_priv->gpio_mmio_base + gmbus_ports[pin - 1].reg;
194 bus->adapter.algo_data = algo;
195 algo->setsda = set_data;
196 algo->setscl = set_clock;
197 algo->getsda = get_data;
198 algo->getscl = get_clock;
199 algo->pre_xfer = intel_gpio_pre_xfer;
200 algo->post_xfer = intel_gpio_post_xfer;
201 algo->udelay = I2C_RISEFALL_TIME;
202 algo->timeout = usecs_to_jiffies(2200);
207 * gmbus on gen4 seems to be able to generate legacy interrupts even when in MSI
208 * mode. This results in spurious interrupt warnings if the legacy irq no. is
209 * shared with another device. The kernel then disables that interrupt source
210 * and so prevents the other device from working properly.
212 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
214 gmbus_wait_hw_status(struct drm_i915_private *dev_priv,
219 int reg_offset = dev_priv->gpio_mmio_base;
223 if (!HAS_GMBUS_IRQ(dev_priv->dev))
226 /* Important: The hw handles only the first bit, so set only one! Since
227 * we also need to check for NAKs besides the hw ready/idle signal, we
228 * need to wake up periodically and check that ourselves. */
229 I915_WRITE(GMBUS4 + reg_offset, gmbus4_irq_en);
231 for (i = 0; i < msecs_to_jiffies_timeout(50); i++) {
232 prepare_to_wait(&dev_priv->gmbus_wait_queue, &wait,
233 TASK_UNINTERRUPTIBLE);
235 gmbus2 = I915_READ_NOTRACE(GMBUS2 + reg_offset);
236 if (gmbus2 & (GMBUS_SATOER | gmbus2_status))
241 finish_wait(&dev_priv->gmbus_wait_queue, &wait);
243 I915_WRITE(GMBUS4 + reg_offset, 0);
245 if (gmbus2 & GMBUS_SATOER)
247 if (gmbus2 & gmbus2_status)
253 gmbus_wait_idle(struct drm_i915_private *dev_priv)
256 int reg_offset = dev_priv->gpio_mmio_base;
258 #define C ((I915_READ_NOTRACE(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0)
260 if (!HAS_GMBUS_IRQ(dev_priv->dev))
261 return wait_for(C, 10);
263 /* Important: The hw handles only the first bit, so set only one! */
264 I915_WRITE(GMBUS4 + reg_offset, GMBUS_IDLE_EN);
266 ret = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
267 msecs_to_jiffies_timeout(10));
269 I915_WRITE(GMBUS4 + reg_offset, 0);
279 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
282 int reg_offset = dev_priv->gpio_mmio_base;
286 I915_WRITE(GMBUS1 + reg_offset,
289 (len << GMBUS_BYTE_COUNT_SHIFT) |
290 (msg->addr << GMBUS_SLAVE_ADDR_SHIFT) |
291 GMBUS_SLAVE_READ | GMBUS_SW_RDY);
296 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY,
301 val = I915_READ(GMBUS3 + reg_offset);
305 } while (--len && ++loop < 4);
312 gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg)
314 int reg_offset = dev_priv->gpio_mmio_base;
320 while (len && loop < 4) {
321 val |= *buf++ << (8 * loop++);
325 I915_WRITE(GMBUS3 + reg_offset, val);
326 I915_WRITE(GMBUS1 + reg_offset,
328 (msg->len << GMBUS_BYTE_COUNT_SHIFT) |
329 (msg->addr << GMBUS_SLAVE_ADDR_SHIFT) |
330 GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
336 val |= *buf++ << (8 * loop);
337 } while (--len && ++loop < 4);
339 I915_WRITE(GMBUS3 + reg_offset, val);
341 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY,
350 * The gmbus controller can combine a 1 or 2 byte write with a read that
351 * immediately follows it by using an "INDEX" cycle.
354 gmbus_is_index_read(struct i2c_msg *msgs, int i, int num)
356 return (i + 1 < num &&
357 !(msgs[i].flags & I2C_M_RD) && msgs[i].len <= 2 &&
358 (msgs[i + 1].flags & I2C_M_RD));
362 gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
364 int reg_offset = dev_priv->gpio_mmio_base;
365 u32 gmbus1_index = 0;
369 if (msgs[0].len == 2)
370 gmbus5 = GMBUS_2BYTE_INDEX_EN |
371 msgs[0].buf[1] | (msgs[0].buf[0] << 8);
372 if (msgs[0].len == 1)
373 gmbus1_index = GMBUS_CYCLE_INDEX |
374 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
376 /* GMBUS5 holds 16-bit index */
378 I915_WRITE(GMBUS5 + reg_offset, gmbus5);
380 ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index);
382 /* Clear GMBUS5 after each index transfer */
384 I915_WRITE(GMBUS5 + reg_offset, 0);
390 gmbus_xfer(struct i2c_adapter *adapter,
391 struct i2c_msg *msgs,
394 struct intel_gmbus *bus = container_of(adapter,
397 struct drm_i915_private *dev_priv = bus->dev_priv;
401 intel_aux_display_runtime_get(dev_priv);
402 mutex_lock(&dev_priv->gmbus_mutex);
404 if (bus->force_bit) {
405 ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
409 reg_offset = dev_priv->gpio_mmio_base;
411 I915_WRITE(GMBUS0 + reg_offset, bus->reg0);
413 for (i = 0; i < num; i++) {
414 if (gmbus_is_index_read(msgs, i, num)) {
415 ret = gmbus_xfer_index_read(dev_priv, &msgs[i]);
416 i += 1; /* set i to the index of the read xfer */
417 } else if (msgs[i].flags & I2C_M_RD) {
418 ret = gmbus_xfer_read(dev_priv, &msgs[i], 0);
420 ret = gmbus_xfer_write(dev_priv, &msgs[i]);
423 if (ret == -ETIMEDOUT)
428 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_WAIT_PHASE,
436 /* Generate a STOP condition on the bus. Note that gmbus can't generata
437 * a STOP on the very first cycle. To simplify the code we
438 * unconditionally generate the STOP condition with an additional gmbus
440 I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
442 /* Mark the GMBUS interface as disabled after waiting for idle.
443 * We will re-enable it at the start of the next xfer,
444 * till then let it sleep.
446 if (gmbus_wait_idle(dev_priv)) {
447 DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n",
451 I915_WRITE(GMBUS0 + reg_offset, 0);
457 * Wait for bus to IDLE before clearing NAK.
458 * If we clear the NAK while bus is still active, then it will stay
459 * active and the next transaction may fail.
461 * If no ACK is received during the address phase of a transaction, the
462 * adapter must report -ENXIO. It is not clear what to return if no ACK
463 * is received at other times. But we have to be careful to not return
464 * spurious -ENXIO because that will prevent i2c and drm edid functions
465 * from retrying. So return -ENXIO only when gmbus properly quiescents -
466 * timing out seems to happen when there _is_ a ddc chip present, but
467 * it's slow responding and only answers on the 2nd retry.
470 if (gmbus_wait_idle(dev_priv)) {
471 DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n",
476 /* Toggle the Software Clear Interrupt bit. This has the effect
477 * of resetting the GMBUS controller and so clearing the
478 * BUS_ERROR raised by the slave's NAK.
480 I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
481 I915_WRITE(GMBUS1 + reg_offset, 0);
482 I915_WRITE(GMBUS0 + reg_offset, 0);
484 DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n",
485 adapter->name, msgs[i].addr,
486 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
491 DRM_INFO("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
492 bus->adapter.name, bus->reg0 & 0xff);
493 I915_WRITE(GMBUS0 + reg_offset, 0);
495 /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
497 ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
500 mutex_unlock(&dev_priv->gmbus_mutex);
501 intel_aux_display_runtime_put(dev_priv);
505 static u32 gmbus_func(struct i2c_adapter *adapter)
507 return i2c_bit_algo.functionality(adapter) &
508 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
509 /* I2C_FUNC_10BIT_ADDR | */
510 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
511 I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
514 static const struct i2c_algorithm gmbus_algorithm = {
515 .master_xfer = gmbus_xfer,
516 .functionality = gmbus_func
520 * intel_gmbus_setup - instantiate all Intel i2c GMBuses
523 int intel_setup_gmbus(struct drm_device *dev)
525 struct drm_i915_private *dev_priv = dev->dev_private;
528 if (HAS_PCH_NOP(dev))
530 else if (HAS_PCH_SPLIT(dev))
531 dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA;
532 else if (IS_VALLEYVIEW(dev))
533 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
535 dev_priv->gpio_mmio_base = 0;
537 mutex_init(&dev_priv->gmbus_mutex);
538 init_waitqueue_head(&dev_priv->gmbus_wait_queue);
540 for (i = 0; i < GMBUS_NUM_PORTS; i++) {
541 struct intel_gmbus *bus = &dev_priv->gmbus[i];
542 u32 port = i + 1; /* +1 to map gmbus index to pin pair */
544 bus->adapter.owner = THIS_MODULE;
545 bus->adapter.class = I2C_CLASS_DDC;
546 snprintf(bus->adapter.name,
547 sizeof(bus->adapter.name),
549 gmbus_ports[i].name);
551 bus->adapter.dev.parent = &dev->pdev->dev;
552 bus->dev_priv = dev_priv;
554 bus->adapter.algo = &gmbus_algorithm;
556 /* By default use a conservative clock rate */
557 bus->reg0 = port | GMBUS_RATE_100KHZ;
559 /* gmbus seems to be broken on i830 */
563 intel_gpio_setup(bus, port);
565 ret = i2c_add_adapter(&bus->adapter);
570 intel_i2c_reset(dev_priv->dev);
576 struct intel_gmbus *bus = &dev_priv->gmbus[i];
577 i2c_del_adapter(&bus->adapter);
582 struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
585 WARN_ON(!intel_gmbus_is_port_valid(port));
586 /* -1 to map pin pair to gmbus index */
587 return (intel_gmbus_is_port_valid(port)) ?
588 &dev_priv->gmbus[port - 1].adapter : NULL;
591 void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
593 struct intel_gmbus *bus = to_intel_gmbus(adapter);
595 bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed;
598 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
600 struct intel_gmbus *bus = to_intel_gmbus(adapter);
602 bus->force_bit += force_bit ? 1 : -1;
603 DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n",
604 force_bit ? "en" : "dis", adapter->name,
608 void intel_teardown_gmbus(struct drm_device *dev)
610 struct drm_i915_private *dev_priv = dev->dev_private;
613 for (i = 0; i < GMBUS_NUM_PORTS; i++) {
614 struct intel_gmbus *bus = &dev_priv->gmbus[i];
615 i2c_del_adapter(&bus->adapter);