2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2008,2010 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
26 * Eric Anholt <eric@anholt.net>
27 * Chris Wilson <chris@chris-wilson.co.uk>
29 #include <linux/i2c.h>
30 #include <linux/i2c-algo-bit.h>
31 #include <linux/export.h>
33 #include "intel_drv.h"
34 #include <drm/i915_drm.h>
42 /* Map gmbus pin pairs to names and registers. */
43 static const struct gmbus_pin gmbus_pins[] = {
44 [GMBUS_PIN_SSC] = { "ssc", GPIOB },
45 [GMBUS_PIN_VGADDC] = { "vga", GPIOA },
46 [GMBUS_PIN_PANEL] = { "panel", GPIOC },
47 [GMBUS_PIN_DPC] = { "dpc", GPIOD },
48 [GMBUS_PIN_DPB] = { "dpb", GPIOE },
49 [GMBUS_PIN_DPD] = { "dpd", GPIOF },
52 static const struct gmbus_pin gmbus_pins_bdw[] = {
53 [GMBUS_PIN_VGADDC] = { "vga", GPIOA },
54 [GMBUS_PIN_DPC] = { "dpc", GPIOD },
55 [GMBUS_PIN_DPB] = { "dpb", GPIOE },
56 [GMBUS_PIN_DPD] = { "dpd", GPIOF },
59 static const struct gmbus_pin gmbus_pins_skl[] = {
60 [GMBUS_PIN_DPC] = { "dpc", GPIOD },
61 [GMBUS_PIN_DPB] = { "dpb", GPIOE },
62 [GMBUS_PIN_DPD] = { "dpd", GPIOF },
65 static const struct gmbus_pin gmbus_pins_bxt[] = {
66 [GMBUS_PIN_1_BXT] = { "dpb", PCH_GPIOB },
67 [GMBUS_PIN_2_BXT] = { "dpc", PCH_GPIOC },
68 [GMBUS_PIN_3_BXT] = { "misc", PCH_GPIOD },
71 /* pin is expected to be valid */
72 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
75 if (IS_BROXTON(dev_priv))
76 return &gmbus_pins_bxt[pin];
77 else if (IS_SKYLAKE(dev_priv))
78 return &gmbus_pins_skl[pin];
79 else if (IS_BROADWELL(dev_priv))
80 return &gmbus_pins_bdw[pin];
82 return &gmbus_pins[pin];
85 bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
90 if (IS_BROXTON(dev_priv))
91 size = ARRAY_SIZE(gmbus_pins_bxt);
92 else if (IS_SKYLAKE(dev_priv))
93 size = ARRAY_SIZE(gmbus_pins_skl);
94 else if (IS_BROADWELL(dev_priv))
95 size = ARRAY_SIZE(gmbus_pins_bdw);
97 size = ARRAY_SIZE(gmbus_pins);
99 return pin < size && get_gmbus_pin(dev_priv, pin)->reg;
102 /* Intel GPIO access functions */
104 #define I2C_RISEFALL_TIME 10
106 static inline struct intel_gmbus *
107 to_intel_gmbus(struct i2c_adapter *i2c)
109 return container_of(i2c, struct intel_gmbus, adapter);
113 intel_i2c_reset(struct drm_device *dev)
115 struct drm_i915_private *dev_priv = dev->dev_private;
117 I915_WRITE(GMBUS0, 0);
118 I915_WRITE(GMBUS4, 0);
121 static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
125 /* When using bit bashing for I2C, this bit needs to be set to 1 */
126 if (!IS_PINEVIEW(dev_priv->dev))
129 val = I915_READ(DSPCLK_GATE_D);
131 val |= DPCUNIT_CLOCK_GATE_DISABLE;
133 val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
134 I915_WRITE(DSPCLK_GATE_D, val);
137 static u32 get_reserved(struct intel_gmbus *bus)
139 struct drm_i915_private *dev_priv = bus->dev_priv;
140 struct drm_device *dev = dev_priv->dev;
143 /* On most chips, these bits must be preserved in software. */
144 if (!IS_I830(dev) && !IS_845G(dev))
145 reserved = I915_READ_NOTRACE(bus->gpio_reg) &
146 (GPIO_DATA_PULLUP_DISABLE |
147 GPIO_CLOCK_PULLUP_DISABLE);
152 static int get_clock(void *data)
154 struct intel_gmbus *bus = data;
155 struct drm_i915_private *dev_priv = bus->dev_priv;
156 u32 reserved = get_reserved(bus);
157 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);
158 I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
159 return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
162 static int get_data(void *data)
164 struct intel_gmbus *bus = data;
165 struct drm_i915_private *dev_priv = bus->dev_priv;
166 u32 reserved = get_reserved(bus);
167 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);
168 I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
169 return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
172 static void set_clock(void *data, int state_high)
174 struct intel_gmbus *bus = data;
175 struct drm_i915_private *dev_priv = bus->dev_priv;
176 u32 reserved = get_reserved(bus);
180 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
182 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
185 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits);
186 POSTING_READ(bus->gpio_reg);
189 static void set_data(void *data, int state_high)
191 struct intel_gmbus *bus = data;
192 struct drm_i915_private *dev_priv = bus->dev_priv;
193 u32 reserved = get_reserved(bus);
197 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
199 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
202 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits);
203 POSTING_READ(bus->gpio_reg);
207 intel_gpio_pre_xfer(struct i2c_adapter *adapter)
209 struct intel_gmbus *bus = container_of(adapter,
212 struct drm_i915_private *dev_priv = bus->dev_priv;
214 intel_i2c_reset(dev_priv->dev);
215 intel_i2c_quirk_set(dev_priv, true);
218 udelay(I2C_RISEFALL_TIME);
223 intel_gpio_post_xfer(struct i2c_adapter *adapter)
225 struct intel_gmbus *bus = container_of(adapter,
228 struct drm_i915_private *dev_priv = bus->dev_priv;
232 intel_i2c_quirk_set(dev_priv, false);
236 intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin)
238 struct drm_i915_private *dev_priv = bus->dev_priv;
239 struct i2c_algo_bit_data *algo;
241 algo = &bus->bit_algo;
243 bus->gpio_reg = dev_priv->gpio_mmio_base +
244 get_gmbus_pin(dev_priv, pin)->reg;
246 bus->adapter.algo_data = algo;
247 algo->setsda = set_data;
248 algo->setscl = set_clock;
249 algo->getsda = get_data;
250 algo->getscl = get_clock;
251 algo->pre_xfer = intel_gpio_pre_xfer;
252 algo->post_xfer = intel_gpio_post_xfer;
253 algo->udelay = I2C_RISEFALL_TIME;
254 algo->timeout = usecs_to_jiffies(2200);
259 gmbus_wait_hw_status(struct drm_i915_private *dev_priv,
267 if (!HAS_GMBUS_IRQ(dev_priv->dev))
270 /* Important: The hw handles only the first bit, so set only one! Since
271 * we also need to check for NAKs besides the hw ready/idle signal, we
272 * need to wake up periodically and check that ourselves. */
273 I915_WRITE(GMBUS4, gmbus4_irq_en);
275 for (i = 0; i < msecs_to_jiffies_timeout(50); i++) {
276 prepare_to_wait(&dev_priv->gmbus_wait_queue, &wait,
277 TASK_UNINTERRUPTIBLE);
279 gmbus2 = I915_READ_NOTRACE(GMBUS2);
280 if (gmbus2 & (GMBUS_SATOER | gmbus2_status))
285 finish_wait(&dev_priv->gmbus_wait_queue, &wait);
287 I915_WRITE(GMBUS4, 0);
289 if (gmbus2 & GMBUS_SATOER)
291 if (gmbus2 & gmbus2_status)
297 gmbus_wait_idle(struct drm_i915_private *dev_priv)
301 #define C ((I915_READ_NOTRACE(GMBUS2) & GMBUS_ACTIVE) == 0)
303 if (!HAS_GMBUS_IRQ(dev_priv->dev))
304 return wait_for(C, 10);
306 /* Important: The hw handles only the first bit, so set only one! */
307 I915_WRITE(GMBUS4, GMBUS_IDLE_EN);
309 ret = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
310 msecs_to_jiffies_timeout(10));
312 I915_WRITE(GMBUS4, 0);
322 gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
323 unsigned short addr, u8 *buf, unsigned int len,
329 (len << GMBUS_BYTE_COUNT_SHIFT) |
330 (addr << GMBUS_SLAVE_ADDR_SHIFT) |
331 GMBUS_SLAVE_READ | GMBUS_SW_RDY);
336 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY,
341 val = I915_READ(GMBUS3);
345 } while (--len && ++loop < 4);
352 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
356 unsigned int rx_size = msg->len;
361 len = min(rx_size, GMBUS_BYTE_COUNT_MAX);
363 ret = gmbus_xfer_read_chunk(dev_priv, msg->addr,
364 buf, len, gmbus1_index);
370 } while (rx_size != 0);
376 gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,
377 unsigned short addr, u8 *buf, unsigned int len)
379 unsigned int chunk_size = len;
383 while (len && loop < 4) {
384 val |= *buf++ << (8 * loop++);
388 I915_WRITE(GMBUS3, val);
391 (chunk_size << GMBUS_BYTE_COUNT_SHIFT) |
392 (addr << GMBUS_SLAVE_ADDR_SHIFT) |
393 GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
399 val |= *buf++ << (8 * loop);
400 } while (--len && ++loop < 4);
402 I915_WRITE(GMBUS3, val);
404 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY,
414 gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg)
417 unsigned int tx_size = msg->len;
422 len = min(tx_size, GMBUS_BYTE_COUNT_MAX);
424 ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len);
430 } while (tx_size != 0);
436 * The gmbus controller can combine a 1 or 2 byte write with a read that
437 * immediately follows it by using an "INDEX" cycle.
440 gmbus_is_index_read(struct i2c_msg *msgs, int i, int num)
442 return (i + 1 < num &&
443 !(msgs[i].flags & I2C_M_RD) && msgs[i].len <= 2 &&
444 (msgs[i + 1].flags & I2C_M_RD));
448 gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
450 u32 gmbus1_index = 0;
454 if (msgs[0].len == 2)
455 gmbus5 = GMBUS_2BYTE_INDEX_EN |
456 msgs[0].buf[1] | (msgs[0].buf[0] << 8);
457 if (msgs[0].len == 1)
458 gmbus1_index = GMBUS_CYCLE_INDEX |
459 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
461 /* GMBUS5 holds 16-bit index */
463 I915_WRITE(GMBUS5, gmbus5);
465 ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index);
467 /* Clear GMBUS5 after each index transfer */
469 I915_WRITE(GMBUS5, 0);
475 gmbus_xfer(struct i2c_adapter *adapter,
476 struct i2c_msg *msgs,
479 struct intel_gmbus *bus = container_of(adapter,
482 struct drm_i915_private *dev_priv = bus->dev_priv;
483 int i = 0, inc, try = 0;
486 intel_aux_display_runtime_get(dev_priv);
487 mutex_lock(&dev_priv->gmbus_mutex);
489 if (bus->force_bit) {
490 ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
495 I915_WRITE(GMBUS0, bus->reg0);
497 for (; i < num; i += inc) {
499 if (gmbus_is_index_read(msgs, i, num)) {
500 ret = gmbus_xfer_index_read(dev_priv, &msgs[i]);
501 inc = 2; /* an index read is two msgs */
502 } else if (msgs[i].flags & I2C_M_RD) {
503 ret = gmbus_xfer_read(dev_priv, &msgs[i], 0);
505 ret = gmbus_xfer_write(dev_priv, &msgs[i]);
508 if (ret == -ETIMEDOUT)
513 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_WAIT_PHASE,
521 /* Generate a STOP condition on the bus. Note that gmbus can't generata
522 * a STOP on the very first cycle. To simplify the code we
523 * unconditionally generate the STOP condition with an additional gmbus
525 I915_WRITE(GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
527 /* Mark the GMBUS interface as disabled after waiting for idle.
528 * We will re-enable it at the start of the next xfer,
529 * till then let it sleep.
531 if (gmbus_wait_idle(dev_priv)) {
532 DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n",
536 I915_WRITE(GMBUS0, 0);
542 * Wait for bus to IDLE before clearing NAK.
543 * If we clear the NAK while bus is still active, then it will stay
544 * active and the next transaction may fail.
546 * If no ACK is received during the address phase of a transaction, the
547 * adapter must report -ENXIO. It is not clear what to return if no ACK
548 * is received at other times. But we have to be careful to not return
549 * spurious -ENXIO because that will prevent i2c and drm edid functions
550 * from retrying. So return -ENXIO only when gmbus properly quiescents -
551 * timing out seems to happen when there _is_ a ddc chip present, but
552 * it's slow responding and only answers on the 2nd retry.
555 if (gmbus_wait_idle(dev_priv)) {
556 DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n",
561 /* Toggle the Software Clear Interrupt bit. This has the effect
562 * of resetting the GMBUS controller and so clearing the
563 * BUS_ERROR raised by the slave's NAK.
565 I915_WRITE(GMBUS1, GMBUS_SW_CLR_INT);
566 I915_WRITE(GMBUS1, 0);
567 I915_WRITE(GMBUS0, 0);
569 DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n",
570 adapter->name, msgs[i].addr,
571 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
574 * Passive adapters sometimes NAK the first probe. Retry the first
575 * message once on -ENXIO for GMBUS transfers; the bit banging algorithm
576 * has retries internally. See also the retry loop in
577 * drm_do_probe_ddc_edid, which bails out on the first -ENXIO.
579 if (ret == -ENXIO && i == 0 && try++ == 0) {
580 DRM_DEBUG_KMS("GMBUS [%s] NAK on first message, retry\n",
588 DRM_INFO("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
589 bus->adapter.name, bus->reg0 & 0xff);
590 I915_WRITE(GMBUS0, 0);
592 /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
594 ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
597 mutex_unlock(&dev_priv->gmbus_mutex);
598 intel_aux_display_runtime_put(dev_priv);
602 static u32 gmbus_func(struct i2c_adapter *adapter)
604 return i2c_bit_algo.functionality(adapter) &
605 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
606 /* I2C_FUNC_10BIT_ADDR | */
607 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
608 I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
611 static const struct i2c_algorithm gmbus_algorithm = {
612 .master_xfer = gmbus_xfer,
613 .functionality = gmbus_func
617 * intel_gmbus_setup - instantiate all Intel i2c GMBuses
620 int intel_setup_gmbus(struct drm_device *dev)
622 struct drm_i915_private *dev_priv = dev->dev_private;
623 struct intel_gmbus *bus;
627 if (HAS_PCH_NOP(dev))
629 else if (HAS_PCH_SPLIT(dev))
630 dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA;
631 else if (IS_VALLEYVIEW(dev))
632 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
634 dev_priv->gpio_mmio_base = 0;
636 mutex_init(&dev_priv->gmbus_mutex);
637 init_waitqueue_head(&dev_priv->gmbus_wait_queue);
639 for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
640 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
643 bus = &dev_priv->gmbus[pin];
645 bus->adapter.owner = THIS_MODULE;
646 bus->adapter.class = I2C_CLASS_DDC;
647 snprintf(bus->adapter.name,
648 sizeof(bus->adapter.name),
650 get_gmbus_pin(dev_priv, pin)->name);
652 bus->adapter.dev.parent = &dev->pdev->dev;
653 bus->dev_priv = dev_priv;
655 bus->adapter.algo = &gmbus_algorithm;
657 /* By default use a conservative clock rate */
658 bus->reg0 = pin | GMBUS_RATE_100KHZ;
660 /* gmbus seems to be broken on i830 */
664 intel_gpio_setup(bus, pin);
666 ret = i2c_add_adapter(&bus->adapter);
671 intel_i2c_reset(dev_priv->dev);
677 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
680 bus = &dev_priv->gmbus[pin];
681 i2c_del_adapter(&bus->adapter);
686 struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
689 if (WARN_ON(!intel_gmbus_is_valid_pin(dev_priv, pin)))
692 return &dev_priv->gmbus[pin].adapter;
695 void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
697 struct intel_gmbus *bus = to_intel_gmbus(adapter);
699 bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed;
702 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
704 struct intel_gmbus *bus = to_intel_gmbus(adapter);
706 bus->force_bit += force_bit ? 1 : -1;
707 DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n",
708 force_bit ? "en" : "dis", adapter->name,
712 void intel_teardown_gmbus(struct drm_device *dev)
714 struct drm_i915_private *dev_priv = dev->dev_private;
715 struct intel_gmbus *bus;
718 for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
719 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
722 bus = &dev_priv->gmbus[pin];
723 i2c_del_adapter(&bus->adapter);