2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
135 #include <drm/drmP.h>
136 #include <drm/i915_drm.h>
137 #include "i915_drv.h"
139 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
140 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
141 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
143 #define RING_EXECLIST_QFULL (1 << 0x2)
144 #define RING_EXECLIST1_VALID (1 << 0x3)
145 #define RING_EXECLIST0_VALID (1 << 0x4)
146 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
147 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
148 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
150 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
151 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
152 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
153 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
154 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
155 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
157 #define CTX_LRI_HEADER_0 0x01
158 #define CTX_CONTEXT_CONTROL 0x02
159 #define CTX_RING_HEAD 0x04
160 #define CTX_RING_TAIL 0x06
161 #define CTX_RING_BUFFER_START 0x08
162 #define CTX_RING_BUFFER_CONTROL 0x0a
163 #define CTX_BB_HEAD_U 0x0c
164 #define CTX_BB_HEAD_L 0x0e
165 #define CTX_BB_STATE 0x10
166 #define CTX_SECOND_BB_HEAD_U 0x12
167 #define CTX_SECOND_BB_HEAD_L 0x14
168 #define CTX_SECOND_BB_STATE 0x16
169 #define CTX_BB_PER_CTX_PTR 0x18
170 #define CTX_RCS_INDIRECT_CTX 0x1a
171 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
172 #define CTX_LRI_HEADER_1 0x21
173 #define CTX_CTX_TIMESTAMP 0x22
174 #define CTX_PDP3_UDW 0x24
175 #define CTX_PDP3_LDW 0x26
176 #define CTX_PDP2_UDW 0x28
177 #define CTX_PDP2_LDW 0x2a
178 #define CTX_PDP1_UDW 0x2c
179 #define CTX_PDP1_LDW 0x2e
180 #define CTX_PDP0_UDW 0x30
181 #define CTX_PDP0_LDW 0x32
182 #define CTX_LRI_HEADER_2 0x41
183 #define CTX_R_PWR_CLK_STATE 0x42
184 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
186 #define GEN8_CTX_VALID (1<<0)
187 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
188 #define GEN8_CTX_FORCE_RESTORE (1<<2)
189 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
190 #define GEN8_CTX_PRIVILEGE (1<<8)
192 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) { \
193 const u64 _addr = test_bit(n, ppgtt->pdp.used_pdpes) ? \
194 ppgtt->pdp.page_directory[n]->daddr : \
195 ppgtt->scratch_pd->daddr; \
196 reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
197 reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
201 ADVANCED_CONTEXT = 0,
206 #define GEN8_CTX_MODE_SHIFT 3
209 FAULT_AND_HALT, /* Debug only */
211 FAULT_AND_CONTINUE /* Unsupported */
213 #define GEN8_CTX_ID_SHIFT 32
214 #define CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
216 static int intel_lr_context_pin(struct intel_engine_cs *ring,
217 struct intel_context *ctx);
220 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
222 * @enable_execlists: value of i915.enable_execlists module parameter.
224 * Only certain platforms support Execlists (the prerequisites being
225 * support for Logical Ring Contexts and Aliasing PPGTT or better).
227 * Return: 1 if Execlists is supported and has to be enabled.
229 int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists)
231 WARN_ON(i915.enable_ppgtt == -1);
233 if (INTEL_INFO(dev)->gen >= 9)
236 if (enable_execlists == 0)
239 if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) &&
240 i915.use_mmio_flip >= 0)
247 * intel_execlists_ctx_id() - get the Execlists Context ID
248 * @ctx_obj: Logical Ring Context backing object.
250 * Do not confuse with ctx->id! Unfortunately we have a name overload
251 * here: the old context ID we pass to userspace as a handler so that
252 * they can refer to a context, and the new context ID we pass to the
253 * ELSP so that the GPU can inform us of the context status via
256 * Return: 20-bits globally unique context ID.
258 u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj)
260 u32 lrca = i915_gem_obj_ggtt_offset(ctx_obj);
262 /* LRCA is required to be 4K aligned so the more significant 20 bits
263 * are globally unique */
267 static uint64_t execlists_ctx_descriptor(struct intel_engine_cs *ring,
268 struct drm_i915_gem_object *ctx_obj)
270 struct drm_device *dev = ring->dev;
272 uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj);
274 WARN_ON(lrca & 0xFFFFFFFF00000FFFULL);
276 desc = GEN8_CTX_VALID;
277 desc |= LEGACY_CONTEXT << GEN8_CTX_MODE_SHIFT;
278 if (IS_GEN8(ctx_obj->base.dev))
279 desc |= GEN8_CTX_L3LLC_COHERENT;
280 desc |= GEN8_CTX_PRIVILEGE;
282 desc |= (u64)intel_execlists_ctx_id(ctx_obj) << GEN8_CTX_ID_SHIFT;
284 /* TODO: WaDisableLiteRestore when we start using semaphore
285 * signalling between Command Streamers */
286 /* desc |= GEN8_CTX_FORCE_RESTORE; */
288 /* WaEnableForceRestoreInCtxtDescForVCS:skl */
290 INTEL_REVID(dev) <= SKL_REVID_B0 &&
291 (ring->id == BCS || ring->id == VCS ||
292 ring->id == VECS || ring->id == VCS2))
293 desc |= GEN8_CTX_FORCE_RESTORE;
298 static void execlists_elsp_write(struct intel_engine_cs *ring,
299 struct drm_i915_gem_object *ctx_obj0,
300 struct drm_i915_gem_object *ctx_obj1)
302 struct drm_device *dev = ring->dev;
303 struct drm_i915_private *dev_priv = dev->dev_private;
307 /* XXX: You must always write both descriptors in the order below. */
309 temp = execlists_ctx_descriptor(ring, ctx_obj1);
312 desc[1] = (u32)(temp >> 32);
315 temp = execlists_ctx_descriptor(ring, ctx_obj0);
316 desc[3] = (u32)(temp >> 32);
319 spin_lock(&dev_priv->uncore.lock);
320 intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL);
321 I915_WRITE_FW(RING_ELSP(ring), desc[1]);
322 I915_WRITE_FW(RING_ELSP(ring), desc[0]);
323 I915_WRITE_FW(RING_ELSP(ring), desc[3]);
325 /* The context is automatically loaded after the following */
326 I915_WRITE_FW(RING_ELSP(ring), desc[2]);
328 /* ELSP is a wo register, so use another nearby reg for posting instead */
329 POSTING_READ_FW(RING_EXECLIST_STATUS(ring));
330 intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL);
331 spin_unlock(&dev_priv->uncore.lock);
334 static int execlists_update_context(struct drm_i915_gem_object *ctx_obj,
335 struct drm_i915_gem_object *ring_obj,
336 struct i915_hw_ppgtt *ppgtt,
342 page = i915_gem_object_get_page(ctx_obj, 1);
343 reg_state = kmap_atomic(page);
345 reg_state[CTX_RING_TAIL+1] = tail;
346 reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(ring_obj);
348 /* True PPGTT with dynamic page allocation: update PDP registers and
349 * point the unallocated PDPs to the scratch page
352 ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
353 ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
354 ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
355 ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
358 kunmap_atomic(reg_state);
363 static void execlists_submit_contexts(struct intel_engine_cs *ring,
364 struct intel_context *to0, u32 tail0,
365 struct intel_context *to1, u32 tail1)
367 struct drm_i915_gem_object *ctx_obj0 = to0->engine[ring->id].state;
368 struct intel_ringbuffer *ringbuf0 = to0->engine[ring->id].ringbuf;
369 struct drm_i915_gem_object *ctx_obj1 = NULL;
370 struct intel_ringbuffer *ringbuf1 = NULL;
373 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj0));
374 WARN_ON(!i915_gem_obj_is_pinned(ringbuf0->obj));
376 execlists_update_context(ctx_obj0, ringbuf0->obj, to0->ppgtt, tail0);
379 ringbuf1 = to1->engine[ring->id].ringbuf;
380 ctx_obj1 = to1->engine[ring->id].state;
382 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj1));
383 WARN_ON(!i915_gem_obj_is_pinned(ringbuf1->obj));
385 execlists_update_context(ctx_obj1, ringbuf1->obj, to1->ppgtt, tail1);
388 execlists_elsp_write(ring, ctx_obj0, ctx_obj1);
391 static void execlists_context_unqueue(struct intel_engine_cs *ring)
393 struct drm_i915_gem_request *req0 = NULL, *req1 = NULL;
394 struct drm_i915_gem_request *cursor = NULL, *tmp = NULL;
396 assert_spin_locked(&ring->execlist_lock);
399 * If irqs are not active generate a warning as batches that finish
400 * without the irqs may get lost and a GPU Hang may occur.
402 WARN_ON(!intel_irqs_enabled(ring->dev->dev_private));
404 if (list_empty(&ring->execlist_queue))
407 /* Try to read in pairs */
408 list_for_each_entry_safe(cursor, tmp, &ring->execlist_queue,
412 } else if (req0->ctx == cursor->ctx) {
413 /* Same ctx: ignore first request, as second request
414 * will update tail past first request's workload */
415 cursor->elsp_submitted = req0->elsp_submitted;
416 list_del(&req0->execlist_link);
417 list_add_tail(&req0->execlist_link,
418 &ring->execlist_retired_req_list);
426 if (IS_GEN8(ring->dev) || IS_GEN9(ring->dev)) {
428 * WaIdleLiteRestore: make sure we never cause a lite
429 * restore with HEAD==TAIL
431 if (req0->elsp_submitted) {
433 * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL
434 * as we resubmit the request. See gen8_emit_request()
435 * for where we prepare the padding after the end of the
438 struct intel_ringbuffer *ringbuf;
440 ringbuf = req0->ctx->engine[ring->id].ringbuf;
442 req0->tail &= ringbuf->size - 1;
446 WARN_ON(req1 && req1->elsp_submitted);
448 execlists_submit_contexts(ring, req0->ctx, req0->tail,
449 req1 ? req1->ctx : NULL,
450 req1 ? req1->tail : 0);
452 req0->elsp_submitted++;
454 req1->elsp_submitted++;
457 static bool execlists_check_remove_request(struct intel_engine_cs *ring,
460 struct drm_i915_gem_request *head_req;
462 assert_spin_locked(&ring->execlist_lock);
464 head_req = list_first_entry_or_null(&ring->execlist_queue,
465 struct drm_i915_gem_request,
468 if (head_req != NULL) {
469 struct drm_i915_gem_object *ctx_obj =
470 head_req->ctx->engine[ring->id].state;
471 if (intel_execlists_ctx_id(ctx_obj) == request_id) {
472 WARN(head_req->elsp_submitted == 0,
473 "Never submitted head request\n");
475 if (--head_req->elsp_submitted <= 0) {
476 list_del(&head_req->execlist_link);
477 list_add_tail(&head_req->execlist_link,
478 &ring->execlist_retired_req_list);
488 * intel_lrc_irq_handler() - handle Context Switch interrupts
489 * @ring: Engine Command Streamer to handle.
491 * Check the unread Context Status Buffers and manage the submission of new
492 * contexts to the ELSP accordingly.
494 void intel_lrc_irq_handler(struct intel_engine_cs *ring)
496 struct drm_i915_private *dev_priv = ring->dev->dev_private;
502 u32 submit_contexts = 0;
504 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
506 read_pointer = ring->next_context_status_buffer;
507 write_pointer = status_pointer & 0x07;
508 if (read_pointer > write_pointer)
511 spin_lock(&ring->execlist_lock);
513 while (read_pointer < write_pointer) {
515 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) +
516 (read_pointer % 6) * 8);
517 status_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) +
518 (read_pointer % 6) * 8 + 4);
520 if (status & GEN8_CTX_STATUS_PREEMPTED) {
521 if (status & GEN8_CTX_STATUS_LITE_RESTORE) {
522 if (execlists_check_remove_request(ring, status_id))
523 WARN(1, "Lite Restored request removed from queue\n");
525 WARN(1, "Preemption without Lite Restore\n");
528 if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) ||
529 (status & GEN8_CTX_STATUS_ELEMENT_SWITCH)) {
530 if (execlists_check_remove_request(ring, status_id))
535 if (submit_contexts != 0)
536 execlists_context_unqueue(ring);
538 spin_unlock(&ring->execlist_lock);
540 WARN(submit_contexts > 2, "More than two context complete events?\n");
541 ring->next_context_status_buffer = write_pointer % 6;
543 I915_WRITE(RING_CONTEXT_STATUS_PTR(ring),
544 ((u32)ring->next_context_status_buffer & 0x07) << 8);
547 static int execlists_context_queue(struct intel_engine_cs *ring,
548 struct intel_context *to,
550 struct drm_i915_gem_request *request)
552 struct drm_i915_gem_request *cursor;
553 int num_elements = 0;
555 if (to != ring->default_context)
556 intel_lr_context_pin(ring, to);
560 * If there isn't a request associated with this submission,
561 * create one as a temporary holder.
563 request = kzalloc(sizeof(*request), GFP_KERNEL);
566 request->ring = ring;
568 kref_init(&request->ref);
569 i915_gem_context_reference(request->ctx);
571 i915_gem_request_reference(request);
572 WARN_ON(to != request->ctx);
574 request->tail = tail;
576 spin_lock_irq(&ring->execlist_lock);
578 list_for_each_entry(cursor, &ring->execlist_queue, execlist_link)
579 if (++num_elements > 2)
582 if (num_elements > 2) {
583 struct drm_i915_gem_request *tail_req;
585 tail_req = list_last_entry(&ring->execlist_queue,
586 struct drm_i915_gem_request,
589 if (to == tail_req->ctx) {
590 WARN(tail_req->elsp_submitted != 0,
591 "More than 2 already-submitted reqs queued\n");
592 list_del(&tail_req->execlist_link);
593 list_add_tail(&tail_req->execlist_link,
594 &ring->execlist_retired_req_list);
598 list_add_tail(&request->execlist_link, &ring->execlist_queue);
599 if (num_elements == 0)
600 execlists_context_unqueue(ring);
602 spin_unlock_irq(&ring->execlist_lock);
607 static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
609 struct intel_engine_cs *ring = req->ring;
610 uint32_t flush_domains;
614 if (ring->gpu_caches_dirty)
615 flush_domains = I915_GEM_GPU_DOMAINS;
617 ret = ring->emit_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
621 ring->gpu_caches_dirty = false;
625 static int execlists_move_to_gpu(struct drm_i915_gem_request *req,
626 struct list_head *vmas)
628 const unsigned other_rings = ~intel_ring_flag(req->ring);
629 struct i915_vma *vma;
630 uint32_t flush_domains = 0;
631 bool flush_chipset = false;
634 list_for_each_entry(vma, vmas, exec_list) {
635 struct drm_i915_gem_object *obj = vma->obj;
637 if (obj->active & other_rings) {
638 ret = i915_gem_object_sync(obj, req->ring, &req);
643 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
644 flush_chipset |= i915_gem_clflush_object(obj, false);
646 flush_domains |= obj->base.write_domain;
649 if (flush_domains & I915_GEM_DOMAIN_GTT)
652 /* Unconditionally invalidate gpu caches and ensure that we do flush
653 * any residual writes from the previous batch.
655 return logical_ring_invalidate_all_caches(req);
658 int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request)
662 if (request->ctx != request->ring->default_context) {
663 ret = intel_lr_context_pin(request->ring, request->ctx);
668 request->ringbuf = request->ctx->engine[request->ring->id].ringbuf;
673 static int logical_ring_wait_for_space(struct intel_ringbuffer *ringbuf,
674 struct intel_context *ctx,
677 struct intel_engine_cs *ring = ringbuf->ring;
678 struct drm_i915_gem_request *request;
682 /* The whole point of reserving space is to not wait! */
683 WARN_ON(ringbuf->reserved_in_use);
685 if (intel_ring_space(ringbuf) >= bytes)
688 list_for_each_entry(request, &ring->request_list, list) {
690 * The request queue is per-engine, so can contain requests
691 * from multiple ringbuffers. Here, we must ignore any that
692 * aren't from the ringbuffer we're considering.
694 if (request->ringbuf != ringbuf)
697 /* Would completion of this request free enough space? */
698 space = __intel_ring_space(request->postfix, ringbuf->tail,
704 if (WARN_ON(&request->list == &ring->request_list))
707 ret = i915_wait_request(request);
711 ringbuf->space = space;
716 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
717 * @ringbuf: Logical Ringbuffer to advance.
719 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
720 * really happens during submission is that the context and current tail will be placed
721 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
722 * point, the tail *inside* the context is updated and the ELSP written to.
725 intel_logical_ring_advance_and_submit(struct intel_ringbuffer *ringbuf,
726 struct intel_context *ctx,
727 struct drm_i915_gem_request *request)
729 struct intel_engine_cs *ring = ringbuf->ring;
731 intel_logical_ring_advance(ringbuf);
733 if (intel_ring_stopped(ring))
736 execlists_context_queue(ring, ctx, ringbuf->tail, request);
739 static int logical_ring_wrap_buffer(struct intel_ringbuffer *ringbuf,
740 struct intel_context *ctx)
742 uint32_t __iomem *virt;
743 int rem = ringbuf->size - ringbuf->tail;
745 /* Can't wrap if space has already been reserved! */
746 WARN_ON(ringbuf->reserved_in_use);
748 if (ringbuf->space < rem) {
749 int ret = logical_ring_wait_for_space(ringbuf, ctx, rem);
755 virt = ringbuf->virtual_start + ringbuf->tail;
758 iowrite32(MI_NOOP, virt++);
761 intel_ring_update_space(ringbuf);
766 static int logical_ring_prepare(struct intel_ringbuffer *ringbuf,
767 struct intel_context *ctx, int bytes)
772 * Add on the reserved size to the request to make sure that after
773 * the intended commands have been emitted, there is guaranteed to
774 * still be enough free space to send them to the hardware.
776 if (!ringbuf->reserved_in_use)
777 bytes += ringbuf->reserved_size;
779 if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
780 ret = logical_ring_wrap_buffer(ringbuf, ctx);
784 if(ringbuf->reserved_size) {
785 uint32_t size = ringbuf->reserved_size;
787 intel_ring_reserved_space_cancel(ringbuf);
788 intel_ring_reserved_space_reserve(ringbuf, size);
792 if (unlikely(ringbuf->space < bytes)) {
793 ret = logical_ring_wait_for_space(ringbuf, ctx, bytes);
802 * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands
804 * @ringbuf: Logical ringbuffer.
805 * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
807 * The ringbuffer might not be ready to accept the commands right away (maybe it needs to
808 * be wrapped, or wait a bit for the tail to be updated). This function takes care of that
809 * and also preallocates a request (every workload submission is still mediated through
810 * requests, same as it did with legacy ringbuffer submission).
812 * Return: non-zero if the ringbuffer is not ready to be written to.
814 static int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf,
815 struct intel_context *ctx, int num_dwords)
817 struct drm_i915_gem_request *req;
818 struct intel_engine_cs *ring = ringbuf->ring;
819 struct drm_device *dev = ring->dev;
820 struct drm_i915_private *dev_priv = dev->dev_private;
823 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
824 dev_priv->mm.interruptible);
828 ret = logical_ring_prepare(ringbuf, ctx, num_dwords * sizeof(uint32_t));
832 /* Preallocate the olr before touching the ring */
833 ret = i915_gem_request_alloc(ring, ctx, &req);
837 ringbuf->space -= num_dwords * sizeof(uint32_t);
842 * execlists_submission() - submit a batchbuffer for execution, Execlists style
845 * @ring: Engine Command Streamer to submit to.
846 * @ctx: Context to employ for this submission.
847 * @args: execbuffer call arguments.
848 * @vmas: list of vmas.
849 * @batch_obj: the batchbuffer to submit.
850 * @exec_start: batchbuffer start virtual address pointer.
851 * @dispatch_flags: translated execbuffer call flags.
853 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
854 * away the submission details of the execbuffer ioctl call.
856 * Return: non-zero if the submission fails.
858 int intel_execlists_submission(struct i915_execbuffer_params *params,
859 struct drm_i915_gem_execbuffer2 *args,
860 struct list_head *vmas)
862 struct drm_device *dev = params->dev;
863 struct intel_engine_cs *ring = params->ring;
864 struct drm_i915_private *dev_priv = dev->dev_private;
865 struct intel_ringbuffer *ringbuf = params->ctx->engine[ring->id].ringbuf;
871 instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
872 instp_mask = I915_EXEC_CONSTANTS_MASK;
873 switch (instp_mode) {
874 case I915_EXEC_CONSTANTS_REL_GENERAL:
875 case I915_EXEC_CONSTANTS_ABSOLUTE:
876 case I915_EXEC_CONSTANTS_REL_SURFACE:
877 if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) {
878 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
882 if (instp_mode != dev_priv->relative_constants_mode) {
883 if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
884 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
888 /* The HW changed the meaning on this bit on gen6 */
889 instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
893 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode);
897 if (args->num_cliprects != 0) {
898 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
901 if (args->DR4 == 0xffffffff) {
902 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
906 if (args->DR1 || args->DR4 || args->cliprects_ptr) {
907 DRM_DEBUG("0 cliprects but dirt in cliprects fields\n");
912 if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
913 DRM_DEBUG("sol reset is gen7 only\n");
917 ret = execlists_move_to_gpu(params->request, vmas);
921 if (ring == &dev_priv->ring[RCS] &&
922 instp_mode != dev_priv->relative_constants_mode) {
923 ret = intel_logical_ring_begin(ringbuf, params->ctx, 4);
927 intel_logical_ring_emit(ringbuf, MI_NOOP);
928 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1));
929 intel_logical_ring_emit(ringbuf, INSTPM);
930 intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode);
931 intel_logical_ring_advance(ringbuf);
933 dev_priv->relative_constants_mode = instp_mode;
936 exec_start = params->batch_obj_vm_offset +
937 args->batch_start_offset;
939 ret = ring->emit_bb_start(ringbuf, params->ctx, exec_start, params->dispatch_flags);
943 trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags);
945 i915_gem_execbuffer_move_to_active(vmas, params->request);
946 i915_gem_execbuffer_retire_commands(params);
951 void intel_execlists_retire_requests(struct intel_engine_cs *ring)
953 struct drm_i915_gem_request *req, *tmp;
954 struct list_head retired_list;
956 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
957 if (list_empty(&ring->execlist_retired_req_list))
960 INIT_LIST_HEAD(&retired_list);
961 spin_lock_irq(&ring->execlist_lock);
962 list_replace_init(&ring->execlist_retired_req_list, &retired_list);
963 spin_unlock_irq(&ring->execlist_lock);
965 list_for_each_entry_safe(req, tmp, &retired_list, execlist_link) {
966 struct intel_context *ctx = req->ctx;
967 struct drm_i915_gem_object *ctx_obj =
968 ctx->engine[ring->id].state;
970 if (ctx_obj && (ctx != ring->default_context))
971 intel_lr_context_unpin(ring, ctx);
972 list_del(&req->execlist_link);
973 i915_gem_request_unreference(req);
977 void intel_logical_ring_stop(struct intel_engine_cs *ring)
979 struct drm_i915_private *dev_priv = ring->dev->dev_private;
982 if (!intel_ring_initialized(ring))
985 ret = intel_ring_idle(ring);
986 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
987 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
990 /* TODO: Is this correct with Execlists enabled? */
991 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
992 if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
993 DRM_ERROR("%s :timed out trying to stop ring\n", ring->name);
996 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
999 int logical_ring_flush_all_caches(struct drm_i915_gem_request *req)
1001 struct intel_engine_cs *ring = req->ring;
1004 if (!ring->gpu_caches_dirty)
1007 ret = ring->emit_flush(req, 0, I915_GEM_GPU_DOMAINS);
1011 ring->gpu_caches_dirty = false;
1015 static int intel_lr_context_pin(struct intel_engine_cs *ring,
1016 struct intel_context *ctx)
1018 struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state;
1019 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
1022 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
1023 if (ctx->engine[ring->id].pin_count++ == 0) {
1024 ret = i915_gem_obj_ggtt_pin(ctx_obj,
1025 GEN8_LR_CONTEXT_ALIGN, 0);
1027 goto reset_pin_count;
1029 ret = intel_pin_and_map_ringbuffer_obj(ring->dev, ringbuf);
1037 i915_gem_object_ggtt_unpin(ctx_obj);
1039 ctx->engine[ring->id].pin_count = 0;
1044 void intel_lr_context_unpin(struct intel_engine_cs *ring,
1045 struct intel_context *ctx)
1047 struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state;
1048 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
1051 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
1052 if (--ctx->engine[ring->id].pin_count == 0) {
1053 intel_unpin_ringbuffer_obj(ringbuf);
1054 i915_gem_object_ggtt_unpin(ctx_obj);
1059 static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
1062 struct intel_engine_cs *ring = req->ring;
1063 struct intel_ringbuffer *ringbuf = req->ringbuf;
1064 struct drm_device *dev = ring->dev;
1065 struct drm_i915_private *dev_priv = dev->dev_private;
1066 struct i915_workarounds *w = &dev_priv->workarounds;
1068 if (WARN_ON_ONCE(w->count == 0))
1071 ring->gpu_caches_dirty = true;
1072 ret = logical_ring_flush_all_caches(req);
1076 ret = intel_logical_ring_begin(ringbuf, req->ctx, w->count * 2 + 2);
1080 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count));
1081 for (i = 0; i < w->count; i++) {
1082 intel_logical_ring_emit(ringbuf, w->reg[i].addr);
1083 intel_logical_ring_emit(ringbuf, w->reg[i].value);
1085 intel_logical_ring_emit(ringbuf, MI_NOOP);
1087 intel_logical_ring_advance(ringbuf);
1089 ring->gpu_caches_dirty = true;
1090 ret = logical_ring_flush_all_caches(req);
1097 #define wa_ctx_emit(batch, cmd) \
1099 if (WARN_ON(index >= (PAGE_SIZE / sizeof(uint32_t)))) { \
1102 batch[index++] = (cmd); \
1105 static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb *wa_ctx,
1107 uint32_t start_alignment)
1109 return wa_ctx->offset = ALIGN(offset, start_alignment);
1112 static inline int wa_ctx_end(struct i915_wa_ctx_bb *wa_ctx,
1114 uint32_t size_alignment)
1116 wa_ctx->size = offset - wa_ctx->offset;
1118 WARN(wa_ctx->size % size_alignment,
1119 "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n",
1120 wa_ctx->size, size_alignment);
1125 * gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA
1127 * @ring: only applicable for RCS
1128 * @wa_ctx: structure representing wa_ctx
1129 * offset: specifies start of the batch, should be cache-aligned. This is updated
1130 * with the offset value received as input.
1131 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1132 * @batch: page in which WA are loaded
1133 * @offset: This field specifies the start of the batch, it should be
1134 * cache-aligned otherwise it is adjusted accordingly.
1135 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1136 * initialized at the beginning and shared across all contexts but this field
1137 * helps us to have multiple batches at different offsets and select them based
1138 * on a criteria. At the moment this batch always start at the beginning of the page
1139 * and at this point we don't have multiple wa_ctx batch buffers.
1141 * The number of WA applied are not known at the beginning; we use this field
1142 * to return the no of DWORDS written.
1144 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1145 * so it adds NOOPs as padding to make it cacheline aligned.
1146 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1147 * makes a complete batch buffer.
1149 * Return: non-zero if we exceed the PAGE_SIZE limit.
1152 static int gen8_init_indirectctx_bb(struct intel_engine_cs *ring,
1153 struct i915_wa_ctx_bb *wa_ctx,
1154 uint32_t *const batch,
1157 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1159 /* WaDisableCtxRestoreArbitration:bdw,chv */
1160 wa_ctx_emit(batch, MI_ARB_ON_OFF | MI_ARB_DISABLE);
1162 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1163 if (IS_BROADWELL(ring->dev)) {
1164 struct drm_i915_private *dev_priv = to_i915(ring->dev);
1165 uint32_t l3sqc4_flush = (I915_READ(GEN8_L3SQCREG4) |
1166 GEN8_LQSC_FLUSH_COHERENT_LINES);
1168 wa_ctx_emit(batch, MI_LOAD_REGISTER_IMM(1));
1169 wa_ctx_emit(batch, GEN8_L3SQCREG4);
1170 wa_ctx_emit(batch, l3sqc4_flush);
1172 wa_ctx_emit(batch, GFX_OP_PIPE_CONTROL(6));
1173 wa_ctx_emit(batch, (PIPE_CONTROL_CS_STALL |
1174 PIPE_CONTROL_DC_FLUSH_ENABLE));
1175 wa_ctx_emit(batch, 0);
1176 wa_ctx_emit(batch, 0);
1177 wa_ctx_emit(batch, 0);
1178 wa_ctx_emit(batch, 0);
1180 wa_ctx_emit(batch, MI_LOAD_REGISTER_IMM(1));
1181 wa_ctx_emit(batch, GEN8_L3SQCREG4);
1182 wa_ctx_emit(batch, l3sqc4_flush & ~GEN8_LQSC_FLUSH_COHERENT_LINES);
1185 /* Pad to end of cacheline */
1186 while (index % CACHELINE_DWORDS)
1187 wa_ctx_emit(batch, MI_NOOP);
1190 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1191 * execution depends on the length specified in terms of cache lines
1192 * in the register CTX_RCS_INDIRECT_CTX
1195 return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
1199 * gen8_init_perctx_bb() - initialize per ctx batch with WA
1201 * @ring: only applicable for RCS
1202 * @wa_ctx: structure representing wa_ctx
1203 * offset: specifies start of the batch, should be cache-aligned.
1204 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1205 * @offset: This field specifies the start of this batch.
1206 * This batch is started immediately after indirect_ctx batch. Since we ensure
1207 * that indirect_ctx ends on a cacheline this batch is aligned automatically.
1209 * The number of DWORDS written are returned using this field.
1211 * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
1212 * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
1214 static int gen8_init_perctx_bb(struct intel_engine_cs *ring,
1215 struct i915_wa_ctx_bb *wa_ctx,
1216 uint32_t *const batch,
1219 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1221 /* WaDisableCtxRestoreArbitration:bdw,chv */
1222 wa_ctx_emit(batch, MI_ARB_ON_OFF | MI_ARB_ENABLE);
1224 wa_ctx_emit(batch, MI_BATCH_BUFFER_END);
1226 return wa_ctx_end(wa_ctx, *offset = index, 1);
1229 static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *ring, u32 size)
1233 ring->wa_ctx.obj = i915_gem_alloc_object(ring->dev, PAGE_ALIGN(size));
1234 if (!ring->wa_ctx.obj) {
1235 DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n");
1239 ret = i915_gem_obj_ggtt_pin(ring->wa_ctx.obj, PAGE_SIZE, 0);
1241 DRM_DEBUG_DRIVER("pin LRC WA ctx backing obj failed: %d\n",
1243 drm_gem_object_unreference(&ring->wa_ctx.obj->base);
1250 static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs *ring)
1252 if (ring->wa_ctx.obj) {
1253 i915_gem_object_ggtt_unpin(ring->wa_ctx.obj);
1254 drm_gem_object_unreference(&ring->wa_ctx.obj->base);
1255 ring->wa_ctx.obj = NULL;
1259 static int intel_init_workaround_bb(struct intel_engine_cs *ring)
1265 struct i915_ctx_workarounds *wa_ctx = &ring->wa_ctx;
1267 WARN_ON(ring->id != RCS);
1269 /* some WA perform writes to scratch page, ensure it is valid */
1270 if (ring->scratch.obj == NULL) {
1271 DRM_ERROR("scratch page not allocated for %s\n", ring->name);
1275 ret = lrc_setup_wa_ctx_obj(ring, PAGE_SIZE);
1277 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret);
1281 page = i915_gem_object_get_page(wa_ctx->obj, 0);
1282 batch = kmap_atomic(page);
1285 if (INTEL_INFO(ring->dev)->gen == 8) {
1286 ret = gen8_init_indirectctx_bb(ring,
1287 &wa_ctx->indirect_ctx,
1293 ret = gen8_init_perctx_bb(ring,
1300 WARN(INTEL_INFO(ring->dev)->gen >= 8,
1301 "WA batch buffer is not initialized for Gen%d\n",
1302 INTEL_INFO(ring->dev)->gen);
1303 lrc_destroy_wa_ctx_obj(ring);
1307 kunmap_atomic(batch);
1309 lrc_destroy_wa_ctx_obj(ring);
1314 static int gen8_init_common_ring(struct intel_engine_cs *ring)
1316 struct drm_device *dev = ring->dev;
1317 struct drm_i915_private *dev_priv = dev->dev_private;
1319 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
1320 I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff);
1322 I915_WRITE(RING_MODE_GEN7(ring),
1323 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
1324 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
1325 POSTING_READ(RING_MODE_GEN7(ring));
1326 ring->next_context_status_buffer = 0;
1327 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring->name);
1329 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
1334 static int gen8_init_render_ring(struct intel_engine_cs *ring)
1336 struct drm_device *dev = ring->dev;
1337 struct drm_i915_private *dev_priv = dev->dev_private;
1340 ret = gen8_init_common_ring(ring);
1344 /* We need to disable the AsyncFlip performance optimisations in order
1345 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1346 * programmed to '1' on all products.
1348 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1350 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1352 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1354 return init_workarounds_ring(ring);
1357 static int gen9_init_render_ring(struct intel_engine_cs *ring)
1361 ret = gen8_init_common_ring(ring);
1365 return init_workarounds_ring(ring);
1368 static int gen8_emit_bb_start(struct intel_ringbuffer *ringbuf,
1369 struct intel_context *ctx,
1370 u64 offset, unsigned dispatch_flags)
1372 bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE);
1375 ret = intel_logical_ring_begin(ringbuf, ctx, 4);
1379 /* FIXME(BDW): Address space and security selectors. */
1380 intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
1381 intel_logical_ring_emit(ringbuf, lower_32_bits(offset));
1382 intel_logical_ring_emit(ringbuf, upper_32_bits(offset));
1383 intel_logical_ring_emit(ringbuf, MI_NOOP);
1384 intel_logical_ring_advance(ringbuf);
1389 static bool gen8_logical_ring_get_irq(struct intel_engine_cs *ring)
1391 struct drm_device *dev = ring->dev;
1392 struct drm_i915_private *dev_priv = dev->dev_private;
1393 unsigned long flags;
1395 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1398 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1399 if (ring->irq_refcount++ == 0) {
1400 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
1401 POSTING_READ(RING_IMR(ring->mmio_base));
1403 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1408 static void gen8_logical_ring_put_irq(struct intel_engine_cs *ring)
1410 struct drm_device *dev = ring->dev;
1411 struct drm_i915_private *dev_priv = dev->dev_private;
1412 unsigned long flags;
1414 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1415 if (--ring->irq_refcount == 0) {
1416 I915_WRITE_IMR(ring, ~ring->irq_keep_mask);
1417 POSTING_READ(RING_IMR(ring->mmio_base));
1419 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1422 static int gen8_emit_flush(struct drm_i915_gem_request *request,
1423 u32 invalidate_domains,
1426 struct intel_ringbuffer *ringbuf = request->ringbuf;
1427 struct intel_engine_cs *ring = ringbuf->ring;
1428 struct drm_device *dev = ring->dev;
1429 struct drm_i915_private *dev_priv = dev->dev_private;
1433 ret = intel_logical_ring_begin(ringbuf, request->ctx, 4);
1437 cmd = MI_FLUSH_DW + 1;
1439 /* We always require a command barrier so that subsequent
1440 * commands, such as breadcrumb interrupts, are strictly ordered
1441 * wrt the contents of the write cache being flushed to memory
1442 * (and thus being coherent from the CPU).
1444 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1446 if (invalidate_domains & I915_GEM_GPU_DOMAINS) {
1447 cmd |= MI_INVALIDATE_TLB;
1448 if (ring == &dev_priv->ring[VCS])
1449 cmd |= MI_INVALIDATE_BSD;
1452 intel_logical_ring_emit(ringbuf, cmd);
1453 intel_logical_ring_emit(ringbuf,
1454 I915_GEM_HWS_SCRATCH_ADDR |
1455 MI_FLUSH_DW_USE_GTT);
1456 intel_logical_ring_emit(ringbuf, 0); /* upper addr */
1457 intel_logical_ring_emit(ringbuf, 0); /* value */
1458 intel_logical_ring_advance(ringbuf);
1463 static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
1464 u32 invalidate_domains,
1467 struct intel_ringbuffer *ringbuf = request->ringbuf;
1468 struct intel_engine_cs *ring = ringbuf->ring;
1469 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1474 flags |= PIPE_CONTROL_CS_STALL;
1476 if (flush_domains) {
1477 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
1478 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
1481 if (invalidate_domains) {
1482 flags |= PIPE_CONTROL_TLB_INVALIDATE;
1483 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
1484 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
1485 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
1486 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
1487 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
1488 flags |= PIPE_CONTROL_QW_WRITE;
1489 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
1493 * On GEN9+ Before VF_CACHE_INVALIDATE we need to emit a NULL pipe
1496 vf_flush_wa = INTEL_INFO(ring->dev)->gen >= 9 &&
1497 flags & PIPE_CONTROL_VF_CACHE_INVALIDATE;
1499 ret = intel_logical_ring_begin(ringbuf, request->ctx, vf_flush_wa ? 12 : 6);
1504 intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1505 intel_logical_ring_emit(ringbuf, 0);
1506 intel_logical_ring_emit(ringbuf, 0);
1507 intel_logical_ring_emit(ringbuf, 0);
1508 intel_logical_ring_emit(ringbuf, 0);
1509 intel_logical_ring_emit(ringbuf, 0);
1512 intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1513 intel_logical_ring_emit(ringbuf, flags);
1514 intel_logical_ring_emit(ringbuf, scratch_addr);
1515 intel_logical_ring_emit(ringbuf, 0);
1516 intel_logical_ring_emit(ringbuf, 0);
1517 intel_logical_ring_emit(ringbuf, 0);
1518 intel_logical_ring_advance(ringbuf);
1523 static u32 gen8_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1525 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1528 static void gen8_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1530 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1533 static int gen8_emit_request(struct drm_i915_gem_request *request)
1535 struct intel_ringbuffer *ringbuf = request->ringbuf;
1536 struct intel_engine_cs *ring = ringbuf->ring;
1541 * Reserve space for 2 NOOPs at the end of each request to be
1542 * used as a workaround for not being allowed to do lite
1543 * restore with HEAD==TAIL (WaIdleLiteRestore).
1545 ret = intel_logical_ring_begin(ringbuf, request->ctx, 8);
1549 cmd = MI_STORE_DWORD_IMM_GEN4;
1550 cmd |= MI_GLOBAL_GTT;
1552 intel_logical_ring_emit(ringbuf, cmd);
1553 intel_logical_ring_emit(ringbuf,
1554 (ring->status_page.gfx_addr +
1555 (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)));
1556 intel_logical_ring_emit(ringbuf, 0);
1557 intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request));
1558 intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
1559 intel_logical_ring_emit(ringbuf, MI_NOOP);
1560 intel_logical_ring_advance_and_submit(ringbuf, request->ctx, request);
1563 * Here we add two extra NOOPs as padding to avoid
1564 * lite restore of a context with HEAD==TAIL.
1566 intel_logical_ring_emit(ringbuf, MI_NOOP);
1567 intel_logical_ring_emit(ringbuf, MI_NOOP);
1568 intel_logical_ring_advance(ringbuf);
1573 static int intel_lr_context_render_state_init(struct drm_i915_gem_request *req)
1575 struct render_state so;
1578 ret = i915_gem_render_state_prepare(req->ring, &so);
1582 if (so.rodata == NULL)
1585 ret = req->ring->emit_bb_start(req->ringbuf,
1588 I915_DISPATCH_SECURE);
1592 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), req);
1595 i915_gem_render_state_fini(&so);
1599 static int gen8_init_rcs_context(struct drm_i915_gem_request *req)
1603 ret = intel_logical_ring_workarounds_emit(req);
1607 return intel_lr_context_render_state_init(req);
1611 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1613 * @ring: Engine Command Streamer.
1616 void intel_logical_ring_cleanup(struct intel_engine_cs *ring)
1618 struct drm_i915_private *dev_priv;
1620 if (!intel_ring_initialized(ring))
1623 dev_priv = ring->dev->dev_private;
1625 intel_logical_ring_stop(ring);
1626 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1627 i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
1630 ring->cleanup(ring);
1632 i915_cmd_parser_fini_ring(ring);
1633 i915_gem_batch_pool_fini(&ring->batch_pool);
1635 if (ring->status_page.obj) {
1636 kunmap(sg_page(ring->status_page.obj->pages->sgl));
1637 ring->status_page.obj = NULL;
1640 lrc_destroy_wa_ctx_obj(ring);
1643 static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *ring)
1647 /* Intentionally left blank. */
1648 ring->buffer = NULL;
1651 INIT_LIST_HEAD(&ring->active_list);
1652 INIT_LIST_HEAD(&ring->request_list);
1653 i915_gem_batch_pool_init(dev, &ring->batch_pool);
1654 init_waitqueue_head(&ring->irq_queue);
1656 INIT_LIST_HEAD(&ring->execlist_queue);
1657 INIT_LIST_HEAD(&ring->execlist_retired_req_list);
1658 spin_lock_init(&ring->execlist_lock);
1660 ret = i915_cmd_parser_init_ring(ring);
1664 ret = intel_lr_context_deferred_create(ring->default_context, ring);
1669 static int logical_render_ring_init(struct drm_device *dev)
1671 struct drm_i915_private *dev_priv = dev->dev_private;
1672 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
1675 ring->name = "render ring";
1677 ring->mmio_base = RENDER_RING_BASE;
1678 ring->irq_enable_mask =
1679 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
1680 ring->irq_keep_mask =
1681 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
1682 if (HAS_L3_DPF(dev))
1683 ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
1685 if (INTEL_INFO(dev)->gen >= 9)
1686 ring->init_hw = gen9_init_render_ring;
1688 ring->init_hw = gen8_init_render_ring;
1689 ring->init_context = gen8_init_rcs_context;
1690 ring->cleanup = intel_fini_pipe_control;
1691 ring->get_seqno = gen8_get_seqno;
1692 ring->set_seqno = gen8_set_seqno;
1693 ring->emit_request = gen8_emit_request;
1694 ring->emit_flush = gen8_emit_flush_render;
1695 ring->irq_get = gen8_logical_ring_get_irq;
1696 ring->irq_put = gen8_logical_ring_put_irq;
1697 ring->emit_bb_start = gen8_emit_bb_start;
1701 ret = intel_init_pipe_control(ring);
1705 ret = intel_init_workaround_bb(ring);
1708 * We continue even if we fail to initialize WA batch
1709 * because we only expect rare glitches but nothing
1710 * critical to prevent us from using GPU
1712 DRM_ERROR("WA batch buffer initialization failed: %d\n",
1716 ret = logical_ring_init(dev, ring);
1718 lrc_destroy_wa_ctx_obj(ring);
1724 static int logical_bsd_ring_init(struct drm_device *dev)
1726 struct drm_i915_private *dev_priv = dev->dev_private;
1727 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
1729 ring->name = "bsd ring";
1731 ring->mmio_base = GEN6_BSD_RING_BASE;
1732 ring->irq_enable_mask =
1733 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
1734 ring->irq_keep_mask =
1735 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
1737 ring->init_hw = gen8_init_common_ring;
1738 ring->get_seqno = gen8_get_seqno;
1739 ring->set_seqno = gen8_set_seqno;
1740 ring->emit_request = gen8_emit_request;
1741 ring->emit_flush = gen8_emit_flush;
1742 ring->irq_get = gen8_logical_ring_get_irq;
1743 ring->irq_put = gen8_logical_ring_put_irq;
1744 ring->emit_bb_start = gen8_emit_bb_start;
1746 return logical_ring_init(dev, ring);
1749 static int logical_bsd2_ring_init(struct drm_device *dev)
1751 struct drm_i915_private *dev_priv = dev->dev_private;
1752 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
1754 ring->name = "bds2 ring";
1756 ring->mmio_base = GEN8_BSD2_RING_BASE;
1757 ring->irq_enable_mask =
1758 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
1759 ring->irq_keep_mask =
1760 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
1762 ring->init_hw = gen8_init_common_ring;
1763 ring->get_seqno = gen8_get_seqno;
1764 ring->set_seqno = gen8_set_seqno;
1765 ring->emit_request = gen8_emit_request;
1766 ring->emit_flush = gen8_emit_flush;
1767 ring->irq_get = gen8_logical_ring_get_irq;
1768 ring->irq_put = gen8_logical_ring_put_irq;
1769 ring->emit_bb_start = gen8_emit_bb_start;
1771 return logical_ring_init(dev, ring);
1774 static int logical_blt_ring_init(struct drm_device *dev)
1776 struct drm_i915_private *dev_priv = dev->dev_private;
1777 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
1779 ring->name = "blitter ring";
1781 ring->mmio_base = BLT_RING_BASE;
1782 ring->irq_enable_mask =
1783 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
1784 ring->irq_keep_mask =
1785 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
1787 ring->init_hw = gen8_init_common_ring;
1788 ring->get_seqno = gen8_get_seqno;
1789 ring->set_seqno = gen8_set_seqno;
1790 ring->emit_request = gen8_emit_request;
1791 ring->emit_flush = gen8_emit_flush;
1792 ring->irq_get = gen8_logical_ring_get_irq;
1793 ring->irq_put = gen8_logical_ring_put_irq;
1794 ring->emit_bb_start = gen8_emit_bb_start;
1796 return logical_ring_init(dev, ring);
1799 static int logical_vebox_ring_init(struct drm_device *dev)
1801 struct drm_i915_private *dev_priv = dev->dev_private;
1802 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
1804 ring->name = "video enhancement ring";
1806 ring->mmio_base = VEBOX_RING_BASE;
1807 ring->irq_enable_mask =
1808 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
1809 ring->irq_keep_mask =
1810 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
1812 ring->init_hw = gen8_init_common_ring;
1813 ring->get_seqno = gen8_get_seqno;
1814 ring->set_seqno = gen8_set_seqno;
1815 ring->emit_request = gen8_emit_request;
1816 ring->emit_flush = gen8_emit_flush;
1817 ring->irq_get = gen8_logical_ring_get_irq;
1818 ring->irq_put = gen8_logical_ring_put_irq;
1819 ring->emit_bb_start = gen8_emit_bb_start;
1821 return logical_ring_init(dev, ring);
1825 * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
1828 * This function inits the engines for an Execlists submission style (the equivalent in the
1829 * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for
1830 * those engines that are present in the hardware.
1832 * Return: non-zero if the initialization failed.
1834 int intel_logical_rings_init(struct drm_device *dev)
1836 struct drm_i915_private *dev_priv = dev->dev_private;
1839 ret = logical_render_ring_init(dev);
1844 ret = logical_bsd_ring_init(dev);
1846 goto cleanup_render_ring;
1850 ret = logical_blt_ring_init(dev);
1852 goto cleanup_bsd_ring;
1855 if (HAS_VEBOX(dev)) {
1856 ret = logical_vebox_ring_init(dev);
1858 goto cleanup_blt_ring;
1861 if (HAS_BSD2(dev)) {
1862 ret = logical_bsd2_ring_init(dev);
1864 goto cleanup_vebox_ring;
1867 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
1869 goto cleanup_bsd2_ring;
1874 intel_logical_ring_cleanup(&dev_priv->ring[VCS2]);
1876 intel_logical_ring_cleanup(&dev_priv->ring[VECS]);
1878 intel_logical_ring_cleanup(&dev_priv->ring[BCS]);
1880 intel_logical_ring_cleanup(&dev_priv->ring[VCS]);
1881 cleanup_render_ring:
1882 intel_logical_ring_cleanup(&dev_priv->ring[RCS]);
1888 make_rpcs(struct drm_device *dev)
1893 * No explicit RPCS request is needed to ensure full
1894 * slice/subslice/EU enablement prior to Gen9.
1896 if (INTEL_INFO(dev)->gen < 9)
1900 * Starting in Gen9, render power gating can leave
1901 * slice/subslice/EU in a partially enabled state. We
1902 * must make an explicit request through RPCS for full
1905 if (INTEL_INFO(dev)->has_slice_pg) {
1906 rpcs |= GEN8_RPCS_S_CNT_ENABLE;
1907 rpcs |= INTEL_INFO(dev)->slice_total <<
1908 GEN8_RPCS_S_CNT_SHIFT;
1909 rpcs |= GEN8_RPCS_ENABLE;
1912 if (INTEL_INFO(dev)->has_subslice_pg) {
1913 rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
1914 rpcs |= INTEL_INFO(dev)->subslice_per_slice <<
1915 GEN8_RPCS_SS_CNT_SHIFT;
1916 rpcs |= GEN8_RPCS_ENABLE;
1919 if (INTEL_INFO(dev)->has_eu_pg) {
1920 rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
1921 GEN8_RPCS_EU_MIN_SHIFT;
1922 rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
1923 GEN8_RPCS_EU_MAX_SHIFT;
1924 rpcs |= GEN8_RPCS_ENABLE;
1931 populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj,
1932 struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf)
1934 struct drm_device *dev = ring->dev;
1935 struct drm_i915_private *dev_priv = dev->dev_private;
1936 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
1938 uint32_t *reg_state;
1942 ppgtt = dev_priv->mm.aliasing_ppgtt;
1944 ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
1946 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
1950 ret = i915_gem_object_get_pages(ctx_obj);
1952 DRM_DEBUG_DRIVER("Could not get object pages\n");
1956 i915_gem_object_pin_pages(ctx_obj);
1958 /* The second page of the context object contains some fields which must
1959 * be set up prior to the first execution. */
1960 page = i915_gem_object_get_page(ctx_obj, 1);
1961 reg_state = kmap_atomic(page);
1963 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
1964 * commands followed by (reg, value) pairs. The values we are setting here are
1965 * only for the first context restore: on a subsequent save, the GPU will
1966 * recreate this batchbuffer with new values (including all the missing
1967 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
1968 if (ring->id == RCS)
1969 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(14);
1971 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(11);
1972 reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED;
1973 reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring);
1974 reg_state[CTX_CONTEXT_CONTROL+1] =
1975 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
1976 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
1977 reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base);
1978 reg_state[CTX_RING_HEAD+1] = 0;
1979 reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base);
1980 reg_state[CTX_RING_TAIL+1] = 0;
1981 reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base);
1982 /* Ring buffer start address is not known until the buffer is pinned.
1983 * It is written to the context image in execlists_update_context()
1985 reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base);
1986 reg_state[CTX_RING_BUFFER_CONTROL+1] =
1987 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID;
1988 reg_state[CTX_BB_HEAD_U] = ring->mmio_base + 0x168;
1989 reg_state[CTX_BB_HEAD_U+1] = 0;
1990 reg_state[CTX_BB_HEAD_L] = ring->mmio_base + 0x140;
1991 reg_state[CTX_BB_HEAD_L+1] = 0;
1992 reg_state[CTX_BB_STATE] = ring->mmio_base + 0x110;
1993 reg_state[CTX_BB_STATE+1] = (1<<5);
1994 reg_state[CTX_SECOND_BB_HEAD_U] = ring->mmio_base + 0x11c;
1995 reg_state[CTX_SECOND_BB_HEAD_U+1] = 0;
1996 reg_state[CTX_SECOND_BB_HEAD_L] = ring->mmio_base + 0x114;
1997 reg_state[CTX_SECOND_BB_HEAD_L+1] = 0;
1998 reg_state[CTX_SECOND_BB_STATE] = ring->mmio_base + 0x118;
1999 reg_state[CTX_SECOND_BB_STATE+1] = 0;
2000 if (ring->id == RCS) {
2001 reg_state[CTX_BB_PER_CTX_PTR] = ring->mmio_base + 0x1c0;
2002 reg_state[CTX_BB_PER_CTX_PTR+1] = 0;
2003 reg_state[CTX_RCS_INDIRECT_CTX] = ring->mmio_base + 0x1c4;
2004 reg_state[CTX_RCS_INDIRECT_CTX+1] = 0;
2005 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET] = ring->mmio_base + 0x1c8;
2006 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = 0;
2007 if (ring->wa_ctx.obj) {
2008 struct i915_ctx_workarounds *wa_ctx = &ring->wa_ctx;
2009 uint32_t ggtt_offset = i915_gem_obj_ggtt_offset(wa_ctx->obj);
2011 reg_state[CTX_RCS_INDIRECT_CTX+1] =
2012 (ggtt_offset + wa_ctx->indirect_ctx.offset * sizeof(uint32_t)) |
2013 (wa_ctx->indirect_ctx.size / CACHELINE_DWORDS);
2015 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] =
2016 CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT << 6;
2018 reg_state[CTX_BB_PER_CTX_PTR+1] =
2019 (ggtt_offset + wa_ctx->per_ctx.offset * sizeof(uint32_t)) |
2023 reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9);
2024 reg_state[CTX_LRI_HEADER_1] |= MI_LRI_FORCE_POSTED;
2025 reg_state[CTX_CTX_TIMESTAMP] = ring->mmio_base + 0x3a8;
2026 reg_state[CTX_CTX_TIMESTAMP+1] = 0;
2027 reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3);
2028 reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3);
2029 reg_state[CTX_PDP2_UDW] = GEN8_RING_PDP_UDW(ring, 2);
2030 reg_state[CTX_PDP2_LDW] = GEN8_RING_PDP_LDW(ring, 2);
2031 reg_state[CTX_PDP1_UDW] = GEN8_RING_PDP_UDW(ring, 1);
2032 reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1);
2033 reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0);
2034 reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0);
2036 /* With dynamic page allocation, PDPs may not be allocated at this point,
2037 * Point the unallocated PDPs to the scratch page
2039 ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
2040 ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
2041 ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
2042 ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
2043 if (ring->id == RCS) {
2044 reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
2045 reg_state[CTX_R_PWR_CLK_STATE] = GEN8_R_PWR_CLK_STATE;
2046 reg_state[CTX_R_PWR_CLK_STATE+1] = make_rpcs(dev);
2049 kunmap_atomic(reg_state);
2052 set_page_dirty(page);
2053 i915_gem_object_unpin_pages(ctx_obj);
2059 * intel_lr_context_free() - free the LRC specific bits of a context
2060 * @ctx: the LR context to free.
2062 * The real context freeing is done in i915_gem_context_free: this only
2063 * takes care of the bits that are LRC related: the per-engine backing
2064 * objects and the logical ringbuffer.
2066 void intel_lr_context_free(struct intel_context *ctx)
2070 for (i = 0; i < I915_NUM_RINGS; i++) {
2071 struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state;
2074 struct intel_ringbuffer *ringbuf =
2075 ctx->engine[i].ringbuf;
2076 struct intel_engine_cs *ring = ringbuf->ring;
2078 if (ctx == ring->default_context) {
2079 intel_unpin_ringbuffer_obj(ringbuf);
2080 i915_gem_object_ggtt_unpin(ctx_obj);
2082 WARN_ON(ctx->engine[ring->id].pin_count);
2083 intel_destroy_ringbuffer_obj(ringbuf);
2085 drm_gem_object_unreference(&ctx_obj->base);
2090 static uint32_t get_lr_context_size(struct intel_engine_cs *ring)
2094 WARN_ON(INTEL_INFO(ring->dev)->gen < 8);
2098 if (INTEL_INFO(ring->dev)->gen >= 9)
2099 ret = GEN9_LR_CONTEXT_RENDER_SIZE;
2101 ret = GEN8_LR_CONTEXT_RENDER_SIZE;
2107 ret = GEN8_LR_CONTEXT_OTHER_SIZE;
2114 static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring,
2115 struct drm_i915_gem_object *default_ctx_obj)
2117 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2119 /* The status page is offset 0 from the default context object
2121 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(default_ctx_obj);
2122 ring->status_page.page_addr =
2123 kmap(sg_page(default_ctx_obj->pages->sgl));
2124 ring->status_page.obj = default_ctx_obj;
2126 I915_WRITE(RING_HWS_PGA(ring->mmio_base),
2127 (u32)ring->status_page.gfx_addr);
2128 POSTING_READ(RING_HWS_PGA(ring->mmio_base));
2132 * intel_lr_context_deferred_create() - create the LRC specific bits of a context
2133 * @ctx: LR context to create.
2134 * @ring: engine to be used with the context.
2136 * This function can be called more than once, with different engines, if we plan
2137 * to use the context with them. The context backing objects and the ringbuffers
2138 * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
2139 * the creation is a deferred call: it's better to make sure first that we need to use
2140 * a given ring with the context.
2142 * Return: non-zero on error.
2144 int intel_lr_context_deferred_create(struct intel_context *ctx,
2145 struct intel_engine_cs *ring)
2147 const bool is_global_default_ctx = (ctx == ring->default_context);
2148 struct drm_device *dev = ring->dev;
2149 struct drm_i915_gem_object *ctx_obj;
2150 uint32_t context_size;
2151 struct intel_ringbuffer *ringbuf;
2154 WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL);
2155 WARN_ON(ctx->engine[ring->id].state);
2157 context_size = round_up(get_lr_context_size(ring), 4096);
2159 ctx_obj = i915_gem_alloc_object(dev, context_size);
2161 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
2165 if (is_global_default_ctx) {
2166 ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN, 0);
2168 DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n",
2170 drm_gem_object_unreference(&ctx_obj->base);
2175 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
2177 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
2180 goto error_unpin_ctx;
2183 ringbuf->ring = ring;
2185 ringbuf->size = 32 * PAGE_SIZE;
2186 ringbuf->effective_size = ringbuf->size;
2189 ringbuf->last_retired_head = -1;
2190 intel_ring_update_space(ringbuf);
2192 if (ringbuf->obj == NULL) {
2193 ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
2196 "Failed to allocate ringbuffer obj %s: %d\n",
2198 goto error_free_rbuf;
2201 if (is_global_default_ctx) {
2202 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
2205 "Failed to pin and map ringbuffer %s: %d\n",
2207 goto error_destroy_rbuf;
2213 ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf);
2215 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
2219 ctx->engine[ring->id].ringbuf = ringbuf;
2220 ctx->engine[ring->id].state = ctx_obj;
2222 if (ctx == ring->default_context)
2223 lrc_setup_hardware_status_page(ring, ctx_obj);
2224 else if (ring->id == RCS && !ctx->rcs_initialized) {
2225 if (ring->init_context) {
2226 struct drm_i915_gem_request *req;
2228 ret = i915_gem_request_alloc(ring, ctx, &req);
2232 ret = ring->init_context(req);
2234 DRM_ERROR("ring init context: %d\n", ret);
2235 i915_gem_request_cancel(req);
2236 ctx->engine[ring->id].ringbuf = NULL;
2237 ctx->engine[ring->id].state = NULL;
2241 i915_add_request_no_flush(req);
2244 ctx->rcs_initialized = true;
2250 if (is_global_default_ctx)
2251 intel_unpin_ringbuffer_obj(ringbuf);
2253 intel_destroy_ringbuffer_obj(ringbuf);
2257 if (is_global_default_ctx)
2258 i915_gem_object_ggtt_unpin(ctx_obj);
2259 drm_gem_object_unreference(&ctx_obj->base);
2263 void intel_lr_context_reset(struct drm_device *dev,
2264 struct intel_context *ctx)
2266 struct drm_i915_private *dev_priv = dev->dev_private;
2267 struct intel_engine_cs *ring;
2270 for_each_ring(ring, dev_priv, i) {
2271 struct drm_i915_gem_object *ctx_obj =
2272 ctx->engine[ring->id].state;
2273 struct intel_ringbuffer *ringbuf =
2274 ctx->engine[ring->id].ringbuf;
2275 uint32_t *reg_state;
2281 if (i915_gem_object_get_pages(ctx_obj)) {
2282 WARN(1, "Failed get_pages for context obj\n");
2285 page = i915_gem_object_get_page(ctx_obj, 1);
2286 reg_state = kmap_atomic(page);
2288 reg_state[CTX_RING_HEAD+1] = 0;
2289 reg_state[CTX_RING_TAIL+1] = 0;
2291 kunmap_atomic(reg_state);