4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Daniel Vetter <daniel@ffwll.ch>
26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
29 #include <drm/i915_drm.h>
32 #include "intel_drv.h"
34 /* Limits for overlay size. According to intel doc, the real limits are:
35 * Y width: 4095, UV width (planar): 2047, Y height: 2047,
36 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
37 * the mininum of both. */
38 #define IMAGE_MAX_WIDTH 2048
39 #define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */
40 /* on 830 and 845 these large limits result in the card hanging */
41 #define IMAGE_MAX_WIDTH_LEGACY 1024
42 #define IMAGE_MAX_HEIGHT_LEGACY 1088
44 /* overlay register definitions */
46 #define OCMD_TILED_SURFACE (0x1<<19)
47 #define OCMD_MIRROR_MASK (0x3<<17)
48 #define OCMD_MIRROR_MODE (0x3<<17)
49 #define OCMD_MIRROR_HORIZONTAL (0x1<<17)
50 #define OCMD_MIRROR_VERTICAL (0x2<<17)
51 #define OCMD_MIRROR_BOTH (0x3<<17)
52 #define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
53 #define OCMD_UV_SWAP (0x1<<14) /* YVYU */
54 #define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */
55 #define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */
56 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
57 #define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */
58 #define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */
59 #define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */
60 #define OCMD_YUV_422_PACKED (0x8<<10)
61 #define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */
62 #define OCMD_YUV_420_PLANAR (0xc<<10)
63 #define OCMD_YUV_422_PLANAR (0xd<<10)
64 #define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */
65 #define OCMD_TVSYNCFLIP_PARITY (0x1<<9)
66 #define OCMD_TVSYNCFLIP_ENABLE (0x1<<7)
67 #define OCMD_BUF_TYPE_MASK (0x1<<5)
68 #define OCMD_BUF_TYPE_FRAME (0x0<<5)
69 #define OCMD_BUF_TYPE_FIELD (0x1<<5)
70 #define OCMD_TEST_MODE (0x1<<4)
71 #define OCMD_BUFFER_SELECT (0x3<<2)
72 #define OCMD_BUFFER0 (0x0<<2)
73 #define OCMD_BUFFER1 (0x1<<2)
74 #define OCMD_FIELD_SELECT (0x1<<2)
75 #define OCMD_FIELD0 (0x0<<1)
76 #define OCMD_FIELD1 (0x1<<1)
77 #define OCMD_ENABLE (0x1<<0)
79 /* OCONFIG register */
80 #define OCONF_PIPE_MASK (0x1<<18)
81 #define OCONF_PIPE_A (0x0<<18)
82 #define OCONF_PIPE_B (0x1<<18)
83 #define OCONF_GAMMA2_ENABLE (0x1<<16)
84 #define OCONF_CSC_MODE_BT601 (0x0<<5)
85 #define OCONF_CSC_MODE_BT709 (0x1<<5)
86 #define OCONF_CSC_BYPASS (0x1<<4)
87 #define OCONF_CC_OUT_8BIT (0x1<<3)
88 #define OCONF_TEST_MODE (0x1<<2)
89 #define OCONF_THREE_LINE_BUFFER (0x1<<0)
90 #define OCONF_TWO_LINE_BUFFER (0x0<<0)
92 /* DCLRKM (dst-key) register */
93 #define DST_KEY_ENABLE (0x1<<31)
94 #define CLK_RGB24_MASK 0x0
95 #define CLK_RGB16_MASK 0x070307
96 #define CLK_RGB15_MASK 0x070707
97 #define CLK_RGB8I_MASK 0xffffff
99 #define RGB16_TO_COLORKEY(c) \
100 (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
101 #define RGB15_TO_COLORKEY(c) \
102 (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))
104 /* overlay flip addr flag */
105 #define OFC_UPDATE 0x1
107 /* polyphase filter coefficients */
108 #define N_HORIZ_Y_TAPS 5
109 #define N_VERT_Y_TAPS 3
110 #define N_HORIZ_UV_TAPS 3
111 #define N_VERT_UV_TAPS 3
115 /* memory bufferd overlay registers */
116 struct overlay_registers {
144 u32 RESERVED1; /* 0x6C */
157 u32 FASTHSCALE; /* 0xA0 */
158 u32 UVSCALEV; /* 0xA4 */
159 u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
160 u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
161 u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
162 u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
163 u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
164 u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
165 u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
166 u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
167 u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
170 struct intel_overlay {
171 struct drm_device *dev;
172 struct intel_crtc *crtc;
173 struct drm_i915_gem_object *vid_bo;
174 struct drm_i915_gem_object *old_vid_bo;
177 u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */
179 u32 brightness, contrast, saturation;
180 u32 old_xscale, old_yscale;
181 /* register access */
183 struct drm_i915_gem_object *reg_bo;
185 struct drm_i915_gem_request *last_flip_req;
186 void (*flip_tail)(struct intel_overlay *);
189 static struct overlay_registers __iomem *
190 intel_overlay_map_regs(struct intel_overlay *overlay)
192 struct drm_i915_private *dev_priv = overlay->dev->dev_private;
193 struct overlay_registers __iomem *regs;
195 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
196 regs = (struct overlay_registers __iomem *)overlay->reg_bo->phys_handle->vaddr;
198 regs = io_mapping_map_wc(dev_priv->gtt.mappable,
199 i915_gem_obj_ggtt_offset(overlay->reg_bo));
204 static void intel_overlay_unmap_regs(struct intel_overlay *overlay,
205 struct overlay_registers __iomem *regs)
207 if (!OVERLAY_NEEDS_PHYSICAL(overlay->dev))
208 io_mapping_unmap(regs);
211 static int intel_overlay_do_wait_request(struct intel_overlay *overlay,
212 void (*tail)(struct intel_overlay *))
214 struct drm_device *dev = overlay->dev;
215 struct drm_i915_private *dev_priv = dev->dev_private;
216 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
219 WARN_ON(overlay->last_flip_req);
220 i915_gem_request_assign(&overlay->last_flip_req,
221 ring->outstanding_lazy_request);
222 ret = i915_add_request(ring);
226 overlay->flip_tail = tail;
227 ret = i915_wait_request(overlay->last_flip_req);
230 i915_gem_retire_requests(dev);
232 i915_gem_request_assign(&overlay->last_flip_req, NULL);
236 /* overlay needs to be disable in OCMD reg */
237 static int intel_overlay_on(struct intel_overlay *overlay)
239 struct drm_device *dev = overlay->dev;
240 struct drm_i915_private *dev_priv = dev->dev_private;
241 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
244 WARN_ON(overlay->active);
245 WARN_ON(IS_I830(dev) && !(dev_priv->quirks & QUIRK_PIPEA_FORCE));
247 ret = intel_ring_begin(ring, 4);
251 overlay->active = true;
253 intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_ON);
254 intel_ring_emit(ring, overlay->flip_addr | OFC_UPDATE);
255 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
256 intel_ring_emit(ring, MI_NOOP);
257 intel_ring_advance(ring);
259 return intel_overlay_do_wait_request(overlay, NULL);
262 /* overlay needs to be enabled in OCMD reg */
263 static int intel_overlay_continue(struct intel_overlay *overlay,
264 bool load_polyphase_filter)
266 struct drm_device *dev = overlay->dev;
267 struct drm_i915_private *dev_priv = dev->dev_private;
268 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
269 u32 flip_addr = overlay->flip_addr;
273 WARN_ON(!overlay->active);
275 if (load_polyphase_filter)
276 flip_addr |= OFC_UPDATE;
278 /* check for underruns */
279 tmp = I915_READ(DOVSTA);
281 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp);
283 ret = intel_ring_begin(ring, 2);
287 intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
288 intel_ring_emit(ring, flip_addr);
289 intel_ring_advance(ring);
291 WARN_ON(overlay->last_flip_req);
292 i915_gem_request_assign(&overlay->last_flip_req,
293 ring->outstanding_lazy_request);
294 return i915_add_request(ring);
297 static void intel_overlay_release_old_vid_tail(struct intel_overlay *overlay)
299 struct drm_i915_gem_object *obj = overlay->old_vid_bo;
301 i915_gem_object_ggtt_unpin(obj);
302 drm_gem_object_unreference(&obj->base);
304 overlay->old_vid_bo = NULL;
307 static void intel_overlay_off_tail(struct intel_overlay *overlay)
309 struct drm_i915_gem_object *obj = overlay->vid_bo;
311 /* never have the overlay hw on without showing a frame */
315 i915_gem_object_ggtt_unpin(obj);
316 drm_gem_object_unreference(&obj->base);
317 overlay->vid_bo = NULL;
319 overlay->crtc->overlay = NULL;
320 overlay->crtc = NULL;
321 overlay->active = false;
324 /* overlay needs to be disabled in OCMD reg */
325 static int intel_overlay_off(struct intel_overlay *overlay)
327 struct drm_device *dev = overlay->dev;
328 struct drm_i915_private *dev_priv = dev->dev_private;
329 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
330 u32 flip_addr = overlay->flip_addr;
333 WARN_ON(!overlay->active);
335 /* According to intel docs the overlay hw may hang (when switching
336 * off) without loading the filter coeffs. It is however unclear whether
337 * this applies to the disabling of the overlay or to the switching off
338 * of the hw. Do it in both cases */
339 flip_addr |= OFC_UPDATE;
341 ret = intel_ring_begin(ring, 6);
345 /* wait for overlay to go idle */
346 intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
347 intel_ring_emit(ring, flip_addr);
348 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
349 /* turn overlay off */
351 /* Workaround: Don't disable the overlay fully, since otherwise
352 * it dies on the next OVERLAY_ON cmd. */
353 intel_ring_emit(ring, MI_NOOP);
354 intel_ring_emit(ring, MI_NOOP);
355 intel_ring_emit(ring, MI_NOOP);
357 intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
358 intel_ring_emit(ring, flip_addr);
359 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
361 intel_ring_advance(ring);
363 return intel_overlay_do_wait_request(overlay, intel_overlay_off_tail);
366 /* recover from an interruption due to a signal
367 * We have to be careful not to repeat work forever an make forward progess. */
368 static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay)
372 if (overlay->last_flip_req == NULL)
375 ret = i915_wait_request(overlay->last_flip_req);
378 i915_gem_retire_requests(overlay->dev);
380 if (overlay->flip_tail)
381 overlay->flip_tail(overlay);
383 i915_gem_request_assign(&overlay->last_flip_req, NULL);
387 /* Wait for pending overlay flip and release old frame.
388 * Needs to be called before the overlay register are changed
389 * via intel_overlay_(un)map_regs
391 static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
393 struct drm_device *dev = overlay->dev;
394 struct drm_i915_private *dev_priv = dev->dev_private;
395 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
398 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
400 /* Only wait if there is actually an old frame to release to
401 * guarantee forward progress.
403 if (!overlay->old_vid_bo)
406 if (I915_READ(ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT) {
407 /* synchronous slowpath */
408 ret = intel_ring_begin(ring, 2);
412 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
413 intel_ring_emit(ring, MI_NOOP);
414 intel_ring_advance(ring);
416 ret = intel_overlay_do_wait_request(overlay,
417 intel_overlay_release_old_vid_tail);
422 intel_overlay_release_old_vid_tail(overlay);
425 i915_gem_track_fb(overlay->old_vid_bo, NULL,
426 INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe));
430 void intel_overlay_reset(struct drm_i915_private *dev_priv)
432 struct intel_overlay *overlay = dev_priv->overlay;
437 intel_overlay_release_old_vid(overlay);
439 overlay->last_flip_req = NULL;
440 overlay->old_xscale = 0;
441 overlay->old_yscale = 0;
442 overlay->crtc = NULL;
443 overlay->active = false;
446 struct put_image_params {
463 static int packed_depth_bytes(u32 format)
465 switch (format & I915_OVERLAY_DEPTH_MASK) {
466 case I915_OVERLAY_YUV422:
468 case I915_OVERLAY_YUV411:
469 /* return 6; not implemented */
475 static int packed_width_bytes(u32 format, short width)
477 switch (format & I915_OVERLAY_DEPTH_MASK) {
478 case I915_OVERLAY_YUV422:
485 static int uv_hsubsampling(u32 format)
487 switch (format & I915_OVERLAY_DEPTH_MASK) {
488 case I915_OVERLAY_YUV422:
489 case I915_OVERLAY_YUV420:
491 case I915_OVERLAY_YUV411:
492 case I915_OVERLAY_YUV410:
499 static int uv_vsubsampling(u32 format)
501 switch (format & I915_OVERLAY_DEPTH_MASK) {
502 case I915_OVERLAY_YUV420:
503 case I915_OVERLAY_YUV410:
505 case I915_OVERLAY_YUV422:
506 case I915_OVERLAY_YUV411:
513 static u32 calc_swidthsw(struct drm_device *dev, u32 offset, u32 width)
515 u32 mask, shift, ret;
523 ret = ((offset + width + mask) >> shift) - (offset >> shift);
530 static const u16 y_static_hcoeffs[N_HORIZ_Y_TAPS * N_PHASES] = {
531 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0,
532 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440,
533 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0,
534 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380,
535 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320,
536 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0,
537 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260,
538 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200,
539 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0,
540 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160,
541 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120,
542 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0,
543 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0,
544 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060,
545 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040,
546 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020,
547 0xb000, 0x3000, 0x0800, 0x3000, 0xb000
550 static const u16 uv_static_hcoeffs[N_HORIZ_UV_TAPS * N_PHASES] = {
551 0x3000, 0x1800, 0x1800, 0xb000, 0x18d0, 0x2e60,
552 0xb000, 0x1990, 0x2ce0, 0xb020, 0x1a68, 0x2b40,
553 0xb040, 0x1b20, 0x29e0, 0xb060, 0x1bd8, 0x2880,
554 0xb080, 0x1c88, 0x3e60, 0xb0a0, 0x1d28, 0x3c00,
555 0xb0c0, 0x1db8, 0x39e0, 0xb0e0, 0x1e40, 0x37e0,
556 0xb100, 0x1eb8, 0x3620, 0xb100, 0x1f18, 0x34a0,
557 0xb100, 0x1f68, 0x3360, 0xb0e0, 0x1fa8, 0x3240,
558 0xb0c0, 0x1fe0, 0x3140, 0xb060, 0x1ff0, 0x30a0,
559 0x3000, 0x0800, 0x3000
562 static void update_polyphase_filter(struct overlay_registers __iomem *regs)
564 memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs));
565 memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs,
566 sizeof(uv_static_hcoeffs));
569 static bool update_scaling_factors(struct intel_overlay *overlay,
570 struct overlay_registers __iomem *regs,
571 struct put_image_params *params)
573 /* fixed point with a 12 bit shift */
574 u32 xscale, yscale, xscale_UV, yscale_UV;
576 #define FRACT_MASK 0xfff
577 bool scale_changed = false;
578 int uv_hscale = uv_hsubsampling(params->format);
579 int uv_vscale = uv_vsubsampling(params->format);
581 if (params->dst_w > 1)
582 xscale = ((params->src_scan_w - 1) << FP_SHIFT)
585 xscale = 1 << FP_SHIFT;
587 if (params->dst_h > 1)
588 yscale = ((params->src_scan_h - 1) << FP_SHIFT)
591 yscale = 1 << FP_SHIFT;
593 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
594 xscale_UV = xscale/uv_hscale;
595 yscale_UV = yscale/uv_vscale;
596 /* make the Y scale to UV scale ratio an exact multiply */
597 xscale = xscale_UV * uv_hscale;
598 yscale = yscale_UV * uv_vscale;
604 if (xscale != overlay->old_xscale || yscale != overlay->old_yscale)
605 scale_changed = true;
606 overlay->old_xscale = xscale;
607 overlay->old_yscale = yscale;
609 iowrite32(((yscale & FRACT_MASK) << 20) |
610 ((xscale >> FP_SHIFT) << 16) |
611 ((xscale & FRACT_MASK) << 3),
614 iowrite32(((yscale_UV & FRACT_MASK) << 20) |
615 ((xscale_UV >> FP_SHIFT) << 16) |
616 ((xscale_UV & FRACT_MASK) << 3),
619 iowrite32((((yscale >> FP_SHIFT) << 16) |
620 ((yscale_UV >> FP_SHIFT) << 0)),
624 update_polyphase_filter(regs);
626 return scale_changed;
629 static void update_colorkey(struct intel_overlay *overlay,
630 struct overlay_registers __iomem *regs)
632 u32 key = overlay->color_key;
634 switch (overlay->crtc->base.primary->fb->bits_per_pixel) {
636 iowrite32(0, ®s->DCLRKV);
637 iowrite32(CLK_RGB8I_MASK | DST_KEY_ENABLE, ®s->DCLRKM);
641 if (overlay->crtc->base.primary->fb->depth == 15) {
642 iowrite32(RGB15_TO_COLORKEY(key), ®s->DCLRKV);
643 iowrite32(CLK_RGB15_MASK | DST_KEY_ENABLE,
646 iowrite32(RGB16_TO_COLORKEY(key), ®s->DCLRKV);
647 iowrite32(CLK_RGB16_MASK | DST_KEY_ENABLE,
654 iowrite32(key, ®s->DCLRKV);
655 iowrite32(CLK_RGB24_MASK | DST_KEY_ENABLE, ®s->DCLRKM);
660 static u32 overlay_cmd_reg(struct put_image_params *params)
662 u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0;
664 if (params->format & I915_OVERLAY_YUV_PLANAR) {
665 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
666 case I915_OVERLAY_YUV422:
667 cmd |= OCMD_YUV_422_PLANAR;
669 case I915_OVERLAY_YUV420:
670 cmd |= OCMD_YUV_420_PLANAR;
672 case I915_OVERLAY_YUV411:
673 case I915_OVERLAY_YUV410:
674 cmd |= OCMD_YUV_410_PLANAR;
677 } else { /* YUV packed */
678 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
679 case I915_OVERLAY_YUV422:
680 cmd |= OCMD_YUV_422_PACKED;
682 case I915_OVERLAY_YUV411:
683 cmd |= OCMD_YUV_411_PACKED;
687 switch (params->format & I915_OVERLAY_SWAP_MASK) {
688 case I915_OVERLAY_NO_SWAP:
690 case I915_OVERLAY_UV_SWAP:
693 case I915_OVERLAY_Y_SWAP:
696 case I915_OVERLAY_Y_AND_UV_SWAP:
697 cmd |= OCMD_Y_AND_UV_SWAP;
705 static int intel_overlay_do_put_image(struct intel_overlay *overlay,
706 struct drm_i915_gem_object *new_bo,
707 struct put_image_params *params)
710 struct overlay_registers __iomem *regs;
711 bool scale_changed = false;
712 struct drm_device *dev = overlay->dev;
713 u32 swidth, swidthsw, sheight, ostride;
714 enum pipe pipe = overlay->crtc->pipe;
716 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
717 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
719 ret = intel_overlay_release_old_vid(overlay);
723 ret = i915_gem_object_pin_to_display_plane(new_bo, 0, NULL,
724 &i915_ggtt_view_normal);
728 ret = i915_gem_object_put_fence(new_bo);
732 if (!overlay->active) {
734 regs = intel_overlay_map_regs(overlay);
739 oconfig = OCONF_CC_OUT_8BIT;
740 if (IS_GEN4(overlay->dev))
741 oconfig |= OCONF_CSC_MODE_BT709;
742 oconfig |= pipe == 0 ?
743 OCONF_PIPE_A : OCONF_PIPE_B;
744 iowrite32(oconfig, ®s->OCONFIG);
745 intel_overlay_unmap_regs(overlay, regs);
747 ret = intel_overlay_on(overlay);
752 regs = intel_overlay_map_regs(overlay);
758 iowrite32((params->dst_y << 16) | params->dst_x, ®s->DWINPOS);
759 iowrite32((params->dst_h << 16) | params->dst_w, ®s->DWINSZ);
761 if (params->format & I915_OVERLAY_YUV_PACKED)
762 tmp_width = packed_width_bytes(params->format, params->src_w);
764 tmp_width = params->src_w;
766 swidth = params->src_w;
767 swidthsw = calc_swidthsw(overlay->dev, params->offset_Y, tmp_width);
768 sheight = params->src_h;
769 iowrite32(i915_gem_obj_ggtt_offset(new_bo) + params->offset_Y, ®s->OBUF_0Y);
770 ostride = params->stride_Y;
772 if (params->format & I915_OVERLAY_YUV_PLANAR) {
773 int uv_hscale = uv_hsubsampling(params->format);
774 int uv_vscale = uv_vsubsampling(params->format);
776 swidth |= (params->src_w/uv_hscale) << 16;
777 tmp_U = calc_swidthsw(overlay->dev, params->offset_U,
778 params->src_w/uv_hscale);
779 tmp_V = calc_swidthsw(overlay->dev, params->offset_V,
780 params->src_w/uv_hscale);
781 swidthsw |= max_t(u32, tmp_U, tmp_V) << 16;
782 sheight |= (params->src_h/uv_vscale) << 16;
783 iowrite32(i915_gem_obj_ggtt_offset(new_bo) + params->offset_U, ®s->OBUF_0U);
784 iowrite32(i915_gem_obj_ggtt_offset(new_bo) + params->offset_V, ®s->OBUF_0V);
785 ostride |= params->stride_UV << 16;
788 iowrite32(swidth, ®s->SWIDTH);
789 iowrite32(swidthsw, ®s->SWIDTHSW);
790 iowrite32(sheight, ®s->SHEIGHT);
791 iowrite32(ostride, ®s->OSTRIDE);
793 scale_changed = update_scaling_factors(overlay, regs, params);
795 update_colorkey(overlay, regs);
797 iowrite32(overlay_cmd_reg(params), ®s->OCMD);
799 intel_overlay_unmap_regs(overlay, regs);
801 ret = intel_overlay_continue(overlay, scale_changed);
805 i915_gem_track_fb(overlay->vid_bo, new_bo,
806 INTEL_FRONTBUFFER_OVERLAY(pipe));
808 overlay->old_vid_bo = overlay->vid_bo;
809 overlay->vid_bo = new_bo;
811 intel_frontbuffer_flip(dev,
812 INTEL_FRONTBUFFER_OVERLAY(pipe));
817 i915_gem_object_ggtt_unpin(new_bo);
821 int intel_overlay_switch_off(struct intel_overlay *overlay)
823 struct overlay_registers __iomem *regs;
824 struct drm_device *dev = overlay->dev;
827 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
828 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
830 ret = intel_overlay_recover_from_interrupt(overlay);
834 if (!overlay->active)
837 ret = intel_overlay_release_old_vid(overlay);
841 regs = intel_overlay_map_regs(overlay);
842 iowrite32(0, ®s->OCMD);
843 intel_overlay_unmap_regs(overlay, regs);
845 ret = intel_overlay_off(overlay);
849 intel_overlay_off_tail(overlay);
853 static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
854 struct intel_crtc *crtc)
859 /* can't use the overlay with double wide pipe */
860 if (crtc->config->double_wide)
866 static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
868 struct drm_device *dev = overlay->dev;
869 struct drm_i915_private *dev_priv = dev->dev_private;
870 u32 pfit_control = I915_READ(PFIT_CONTROL);
873 /* XXX: This is not the same logic as in the xorg driver, but more in
874 * line with the intel documentation for the i965
876 if (INTEL_INFO(dev)->gen >= 4) {
877 /* on i965 use the PGM reg to read out the autoscaler values */
878 ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;
880 if (pfit_control & VERT_AUTO_SCALE)
881 ratio = I915_READ(PFIT_AUTO_RATIOS);
883 ratio = I915_READ(PFIT_PGM_RATIOS);
884 ratio >>= PFIT_VERT_SCALE_SHIFT;
887 overlay->pfit_vscale_ratio = ratio;
890 static int check_overlay_dst(struct intel_overlay *overlay,
891 struct drm_intel_overlay_put_image *rec)
893 struct drm_display_mode *mode = &overlay->crtc->base.mode;
895 if (rec->dst_x < mode->hdisplay &&
896 rec->dst_x + rec->dst_width <= mode->hdisplay &&
897 rec->dst_y < mode->vdisplay &&
898 rec->dst_y + rec->dst_height <= mode->vdisplay)
904 static int check_overlay_scaling(struct put_image_params *rec)
908 /* downscaling limit is 8.0 */
909 tmp = ((rec->src_scan_h << 16) / rec->dst_h) >> 16;
912 tmp = ((rec->src_scan_w << 16) / rec->dst_w) >> 16;
919 static int check_overlay_src(struct drm_device *dev,
920 struct drm_intel_overlay_put_image *rec,
921 struct drm_i915_gem_object *new_bo)
923 int uv_hscale = uv_hsubsampling(rec->flags);
924 int uv_vscale = uv_vsubsampling(rec->flags);
929 /* check src dimensions */
930 if (IS_845G(dev) || IS_I830(dev)) {
931 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY ||
932 rec->src_width > IMAGE_MAX_WIDTH_LEGACY)
935 if (rec->src_height > IMAGE_MAX_HEIGHT ||
936 rec->src_width > IMAGE_MAX_WIDTH)
940 /* better safe than sorry, use 4 as the maximal subsampling ratio */
941 if (rec->src_height < N_VERT_Y_TAPS*4 ||
942 rec->src_width < N_HORIZ_Y_TAPS*4)
945 /* check alignment constraints */
946 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
947 case I915_OVERLAY_RGB:
948 /* not implemented */
951 case I915_OVERLAY_YUV_PACKED:
955 depth = packed_depth_bytes(rec->flags);
959 /* ignore UV planes */
963 /* check pixel alignment */
964 if (rec->offset_Y % depth)
968 case I915_OVERLAY_YUV_PLANAR:
969 if (uv_vscale < 0 || uv_hscale < 0)
971 /* no offset restrictions for planar formats */
978 if (rec->src_width % uv_hscale)
981 /* stride checking */
982 if (IS_I830(dev) || IS_845G(dev))
987 if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
989 if (IS_GEN4(dev) && rec->stride_Y < 512)
992 tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
994 if (rec->stride_Y > tmp || rec->stride_UV > 2*1024)
997 /* check buffer dimensions */
998 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
999 case I915_OVERLAY_RGB:
1000 case I915_OVERLAY_YUV_PACKED:
1001 /* always 4 Y values per depth pixels */
1002 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y)
1005 tmp = rec->stride_Y*rec->src_height;
1006 if (rec->offset_Y + tmp > new_bo->base.size)
1010 case I915_OVERLAY_YUV_PLANAR:
1011 if (rec->src_width > rec->stride_Y)
1013 if (rec->src_width/uv_hscale > rec->stride_UV)
1016 tmp = rec->stride_Y * rec->src_height;
1017 if (rec->offset_Y + tmp > new_bo->base.size)
1020 tmp = rec->stride_UV * (rec->src_height / uv_vscale);
1021 if (rec->offset_U + tmp > new_bo->base.size ||
1022 rec->offset_V + tmp > new_bo->base.size)
1031 * Return the pipe currently connected to the panel fitter,
1032 * or -1 if the panel fitter is not present or not in use
1034 static int intel_panel_fitter_pipe(struct drm_device *dev)
1036 struct drm_i915_private *dev_priv = dev->dev_private;
1039 /* i830 doesn't have a panel fitter */
1040 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
1043 pfit_control = I915_READ(PFIT_CONTROL);
1045 /* See if the panel fitter is in use */
1046 if ((pfit_control & PFIT_ENABLE) == 0)
1049 /* 965 can place panel fitter on either pipe */
1051 return (pfit_control >> 29) & 0x3;
1053 /* older chips can only use pipe 1 */
1057 int intel_overlay_put_image(struct drm_device *dev, void *data,
1058 struct drm_file *file_priv)
1060 struct drm_intel_overlay_put_image *put_image_rec = data;
1061 struct drm_i915_private *dev_priv = dev->dev_private;
1062 struct intel_overlay *overlay;
1063 struct drm_crtc *drmmode_crtc;
1064 struct intel_crtc *crtc;
1065 struct drm_i915_gem_object *new_bo;
1066 struct put_image_params *params;
1069 overlay = dev_priv->overlay;
1071 DRM_DEBUG("userspace bug: no overlay\n");
1075 if (!(put_image_rec->flags & I915_OVERLAY_ENABLE)) {
1076 drm_modeset_lock_all(dev);
1077 mutex_lock(&dev->struct_mutex);
1079 ret = intel_overlay_switch_off(overlay);
1081 mutex_unlock(&dev->struct_mutex);
1082 drm_modeset_unlock_all(dev);
1087 params = kmalloc(sizeof(*params), GFP_KERNEL);
1091 drmmode_crtc = drm_crtc_find(dev, put_image_rec->crtc_id);
1092 if (!drmmode_crtc) {
1096 crtc = to_intel_crtc(drmmode_crtc);
1098 new_bo = to_intel_bo(drm_gem_object_lookup(dev, file_priv,
1099 put_image_rec->bo_handle));
1100 if (&new_bo->base == NULL) {
1105 drm_modeset_lock_all(dev);
1106 mutex_lock(&dev->struct_mutex);
1108 if (new_bo->tiling_mode) {
1109 DRM_DEBUG_KMS("buffer used for overlay image can not be tiled\n");
1114 ret = intel_overlay_recover_from_interrupt(overlay);
1118 if (overlay->crtc != crtc) {
1119 struct drm_display_mode *mode = &crtc->base.mode;
1120 ret = intel_overlay_switch_off(overlay);
1124 ret = check_overlay_possible_on_crtc(overlay, crtc);
1128 overlay->crtc = crtc;
1129 crtc->overlay = overlay;
1131 /* line too wide, i.e. one-line-mode */
1132 if (mode->hdisplay > 1024 &&
1133 intel_panel_fitter_pipe(dev) == crtc->pipe) {
1134 overlay->pfit_active = true;
1135 update_pfit_vscale_ratio(overlay);
1137 overlay->pfit_active = false;
1140 ret = check_overlay_dst(overlay, put_image_rec);
1144 if (overlay->pfit_active) {
1145 params->dst_y = ((((u32)put_image_rec->dst_y) << 12) /
1146 overlay->pfit_vscale_ratio);
1147 /* shifting right rounds downwards, so add 1 */
1148 params->dst_h = ((((u32)put_image_rec->dst_height) << 12) /
1149 overlay->pfit_vscale_ratio) + 1;
1151 params->dst_y = put_image_rec->dst_y;
1152 params->dst_h = put_image_rec->dst_height;
1154 params->dst_x = put_image_rec->dst_x;
1155 params->dst_w = put_image_rec->dst_width;
1157 params->src_w = put_image_rec->src_width;
1158 params->src_h = put_image_rec->src_height;
1159 params->src_scan_w = put_image_rec->src_scan_width;
1160 params->src_scan_h = put_image_rec->src_scan_height;
1161 if (params->src_scan_h > params->src_h ||
1162 params->src_scan_w > params->src_w) {
1167 ret = check_overlay_src(dev, put_image_rec, new_bo);
1170 params->format = put_image_rec->flags & ~I915_OVERLAY_FLAGS_MASK;
1171 params->stride_Y = put_image_rec->stride_Y;
1172 params->stride_UV = put_image_rec->stride_UV;
1173 params->offset_Y = put_image_rec->offset_Y;
1174 params->offset_U = put_image_rec->offset_U;
1175 params->offset_V = put_image_rec->offset_V;
1177 /* Check scaling after src size to prevent a divide-by-zero. */
1178 ret = check_overlay_scaling(params);
1182 ret = intel_overlay_do_put_image(overlay, new_bo, params);
1186 mutex_unlock(&dev->struct_mutex);
1187 drm_modeset_unlock_all(dev);
1194 mutex_unlock(&dev->struct_mutex);
1195 drm_modeset_unlock_all(dev);
1196 drm_gem_object_unreference_unlocked(&new_bo->base);
1203 static void update_reg_attrs(struct intel_overlay *overlay,
1204 struct overlay_registers __iomem *regs)
1206 iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff),
1208 iowrite32(overlay->saturation, ®s->OCLRC1);
1211 static bool check_gamma_bounds(u32 gamma1, u32 gamma2)
1215 if (gamma1 & 0xff000000 || gamma2 & 0xff000000)
1218 for (i = 0; i < 3; i++) {
1219 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff))
1226 static bool check_gamma5_errata(u32 gamma5)
1230 for (i = 0; i < 3; i++) {
1231 if (((gamma5 >> i*8) & 0xff) == 0x80)
1238 static int check_gamma(struct drm_intel_overlay_attrs *attrs)
1240 if (!check_gamma_bounds(0, attrs->gamma0) ||
1241 !check_gamma_bounds(attrs->gamma0, attrs->gamma1) ||
1242 !check_gamma_bounds(attrs->gamma1, attrs->gamma2) ||
1243 !check_gamma_bounds(attrs->gamma2, attrs->gamma3) ||
1244 !check_gamma_bounds(attrs->gamma3, attrs->gamma4) ||
1245 !check_gamma_bounds(attrs->gamma4, attrs->gamma5) ||
1246 !check_gamma_bounds(attrs->gamma5, 0x00ffffff))
1249 if (!check_gamma5_errata(attrs->gamma5))
1255 int intel_overlay_attrs(struct drm_device *dev, void *data,
1256 struct drm_file *file_priv)
1258 struct drm_intel_overlay_attrs *attrs = data;
1259 struct drm_i915_private *dev_priv = dev->dev_private;
1260 struct intel_overlay *overlay;
1261 struct overlay_registers __iomem *regs;
1264 overlay = dev_priv->overlay;
1266 DRM_DEBUG("userspace bug: no overlay\n");
1270 drm_modeset_lock_all(dev);
1271 mutex_lock(&dev->struct_mutex);
1274 if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) {
1275 attrs->color_key = overlay->color_key;
1276 attrs->brightness = overlay->brightness;
1277 attrs->contrast = overlay->contrast;
1278 attrs->saturation = overlay->saturation;
1280 if (!IS_GEN2(dev)) {
1281 attrs->gamma0 = I915_READ(OGAMC0);
1282 attrs->gamma1 = I915_READ(OGAMC1);
1283 attrs->gamma2 = I915_READ(OGAMC2);
1284 attrs->gamma3 = I915_READ(OGAMC3);
1285 attrs->gamma4 = I915_READ(OGAMC4);
1286 attrs->gamma5 = I915_READ(OGAMC5);
1289 if (attrs->brightness < -128 || attrs->brightness > 127)
1291 if (attrs->contrast > 255)
1293 if (attrs->saturation > 1023)
1296 overlay->color_key = attrs->color_key;
1297 overlay->brightness = attrs->brightness;
1298 overlay->contrast = attrs->contrast;
1299 overlay->saturation = attrs->saturation;
1301 regs = intel_overlay_map_regs(overlay);
1307 update_reg_attrs(overlay, regs);
1309 intel_overlay_unmap_regs(overlay, regs);
1311 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
1315 if (overlay->active) {
1320 ret = check_gamma(attrs);
1324 I915_WRITE(OGAMC0, attrs->gamma0);
1325 I915_WRITE(OGAMC1, attrs->gamma1);
1326 I915_WRITE(OGAMC2, attrs->gamma2);
1327 I915_WRITE(OGAMC3, attrs->gamma3);
1328 I915_WRITE(OGAMC4, attrs->gamma4);
1329 I915_WRITE(OGAMC5, attrs->gamma5);
1335 mutex_unlock(&dev->struct_mutex);
1336 drm_modeset_unlock_all(dev);
1341 void intel_setup_overlay(struct drm_device *dev)
1343 struct drm_i915_private *dev_priv = dev->dev_private;
1344 struct intel_overlay *overlay;
1345 struct drm_i915_gem_object *reg_bo;
1346 struct overlay_registers __iomem *regs;
1349 if (!HAS_OVERLAY(dev))
1352 overlay = kzalloc(sizeof(*overlay), GFP_KERNEL);
1356 mutex_lock(&dev->struct_mutex);
1357 if (WARN_ON(dev_priv->overlay))
1363 if (!OVERLAY_NEEDS_PHYSICAL(dev))
1364 reg_bo = i915_gem_object_create_stolen(dev, PAGE_SIZE);
1366 reg_bo = i915_gem_alloc_object(dev, PAGE_SIZE);
1369 overlay->reg_bo = reg_bo;
1371 if (OVERLAY_NEEDS_PHYSICAL(dev)) {
1372 ret = i915_gem_object_attach_phys(reg_bo, PAGE_SIZE);
1374 DRM_ERROR("failed to attach phys overlay regs\n");
1377 overlay->flip_addr = reg_bo->phys_handle->busaddr;
1379 ret = i915_gem_obj_ggtt_pin(reg_bo, PAGE_SIZE, PIN_MAPPABLE);
1381 DRM_ERROR("failed to pin overlay register bo\n");
1384 overlay->flip_addr = i915_gem_obj_ggtt_offset(reg_bo);
1386 ret = i915_gem_object_set_to_gtt_domain(reg_bo, true);
1388 DRM_ERROR("failed to move overlay register bo into the GTT\n");
1393 /* init all values */
1394 overlay->color_key = 0x0101fe;
1395 overlay->brightness = -19;
1396 overlay->contrast = 75;
1397 overlay->saturation = 146;
1399 regs = intel_overlay_map_regs(overlay);
1403 memset_io(regs, 0, sizeof(struct overlay_registers));
1404 update_polyphase_filter(regs);
1405 update_reg_attrs(overlay, regs);
1407 intel_overlay_unmap_regs(overlay, regs);
1409 dev_priv->overlay = overlay;
1410 mutex_unlock(&dev->struct_mutex);
1411 DRM_INFO("initialized overlay support\n");
1415 if (!OVERLAY_NEEDS_PHYSICAL(dev))
1416 i915_gem_object_ggtt_unpin(reg_bo);
1418 drm_gem_object_unreference(®_bo->base);
1420 mutex_unlock(&dev->struct_mutex);
1425 void intel_cleanup_overlay(struct drm_device *dev)
1427 struct drm_i915_private *dev_priv = dev->dev_private;
1429 if (!dev_priv->overlay)
1432 /* The bo's should be free'd by the generic code already.
1433 * Furthermore modesetting teardown happens beforehand so the
1434 * hardware should be off already */
1435 WARN_ON(dev_priv->overlay->active);
1437 drm_gem_object_unreference_unlocked(&dev_priv->overlay->reg_bo->base);
1438 kfree(dev_priv->overlay);
1441 struct intel_overlay_error_state {
1442 struct overlay_registers regs;
1448 static struct overlay_registers __iomem *
1449 intel_overlay_map_regs_atomic(struct intel_overlay *overlay)
1451 struct drm_i915_private *dev_priv = overlay->dev->dev_private;
1452 struct overlay_registers __iomem *regs;
1454 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
1455 /* Cast to make sparse happy, but it's wc memory anyway, so
1456 * equivalent to the wc io mapping on X86. */
1457 regs = (struct overlay_registers __iomem *)
1458 overlay->reg_bo->phys_handle->vaddr;
1460 regs = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
1461 i915_gem_obj_ggtt_offset(overlay->reg_bo));
1466 static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay,
1467 struct overlay_registers __iomem *regs)
1469 if (!OVERLAY_NEEDS_PHYSICAL(overlay->dev))
1470 io_mapping_unmap_atomic(regs);
1474 struct intel_overlay_error_state *
1475 intel_overlay_capture_error_state(struct drm_device *dev)
1477 struct drm_i915_private *dev_priv = dev->dev_private;
1478 struct intel_overlay *overlay = dev_priv->overlay;
1479 struct intel_overlay_error_state *error;
1480 struct overlay_registers __iomem *regs;
1482 if (!overlay || !overlay->active)
1485 error = kmalloc(sizeof(*error), GFP_ATOMIC);
1489 error->dovsta = I915_READ(DOVSTA);
1490 error->isr = I915_READ(ISR);
1491 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
1492 error->base = (__force long)overlay->reg_bo->phys_handle->vaddr;
1494 error->base = i915_gem_obj_ggtt_offset(overlay->reg_bo);
1496 regs = intel_overlay_map_regs_atomic(overlay);
1500 memcpy_fromio(&error->regs, regs, sizeof(struct overlay_registers));
1501 intel_overlay_unmap_regs_atomic(overlay, regs);
1511 intel_overlay_print_error_state(struct drm_i915_error_state_buf *m,
1512 struct intel_overlay_error_state *error)
1514 i915_error_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1515 error->dovsta, error->isr);
1516 i915_error_printf(m, " Register file at 0x%08lx:\n",
1519 #define P(x) i915_error_printf(m, " " #x ": 0x%08x\n", error->regs.x)