2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
28 #include <linux/cpufreq.h>
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
33 #include <linux/vgaarb.h>
34 #include <drm/i915_powerwell.h>
35 #include <linux/pm_runtime.h>
38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
54 #define INTEL_RC6_ENABLE (1<<0)
55 #define INTEL_RC6p_ENABLE (1<<1)
56 #define INTEL_RC6pp_ENABLE (1<<2)
58 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
59 * framebuffer contents in-memory, aiming at reducing the required bandwidth
60 * during in-memory transfers and, therefore, reduce the power packet.
62 * The benefits of FBC are mostly visible with solid backgrounds and
63 * variation-less patterns.
65 * FBC-related functionality can be enabled by the means of the
66 * i915.i915_enable_fbc parameter
69 static void i8xx_disable_fbc(struct drm_device *dev)
71 struct drm_i915_private *dev_priv = dev->dev_private;
74 /* Disable compression */
75 fbc_ctl = I915_READ(FBC_CONTROL);
76 if ((fbc_ctl & FBC_CTL_EN) == 0)
79 fbc_ctl &= ~FBC_CTL_EN;
80 I915_WRITE(FBC_CONTROL, fbc_ctl);
82 /* Wait for compressing bit to clear */
83 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
84 DRM_DEBUG_KMS("FBC idle timed out\n");
88 DRM_DEBUG_KMS("disabled FBC\n");
91 static void i8xx_enable_fbc(struct drm_crtc *crtc)
93 struct drm_device *dev = crtc->dev;
94 struct drm_i915_private *dev_priv = dev->dev_private;
95 struct drm_framebuffer *fb = crtc->primary->fb;
96 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
97 struct drm_i915_gem_object *obj = intel_fb->obj;
98 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
103 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
104 if (fb->pitches[0] < cfb_pitch)
105 cfb_pitch = fb->pitches[0];
107 /* FBC_CTL wants 32B or 64B units */
109 cfb_pitch = (cfb_pitch / 32) - 1;
111 cfb_pitch = (cfb_pitch / 64) - 1;
114 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
115 I915_WRITE(FBC_TAG + (i * 4), 0);
121 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
122 fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane);
123 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
124 I915_WRITE(FBC_FENCE_OFF, crtc->y);
128 fbc_ctl = I915_READ(FBC_CONTROL);
129 fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
130 fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
132 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
133 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
134 fbc_ctl |= obj->fence_reg;
135 I915_WRITE(FBC_CONTROL, fbc_ctl);
137 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
138 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
141 static bool i8xx_fbc_enabled(struct drm_device *dev)
143 struct drm_i915_private *dev_priv = dev->dev_private;
145 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
148 static void g4x_enable_fbc(struct drm_crtc *crtc)
150 struct drm_device *dev = crtc->dev;
151 struct drm_i915_private *dev_priv = dev->dev_private;
152 struct drm_framebuffer *fb = crtc->primary->fb;
153 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
154 struct drm_i915_gem_object *obj = intel_fb->obj;
155 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
158 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN;
159 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
160 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
162 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
163 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
165 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
168 I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
170 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
173 static void g4x_disable_fbc(struct drm_device *dev)
175 struct drm_i915_private *dev_priv = dev->dev_private;
178 /* Disable compression */
179 dpfc_ctl = I915_READ(DPFC_CONTROL);
180 if (dpfc_ctl & DPFC_CTL_EN) {
181 dpfc_ctl &= ~DPFC_CTL_EN;
182 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
184 DRM_DEBUG_KMS("disabled FBC\n");
188 static bool g4x_fbc_enabled(struct drm_device *dev)
190 struct drm_i915_private *dev_priv = dev->dev_private;
192 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
195 static void sandybridge_blit_fbc_update(struct drm_device *dev)
197 struct drm_i915_private *dev_priv = dev->dev_private;
200 /* Make sure blitter notifies FBC of writes */
202 /* Blitter is part of Media powerwell on VLV. No impact of
203 * his param in other platforms for now */
204 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
206 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
207 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
208 GEN6_BLITTER_LOCK_SHIFT;
209 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
210 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
211 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
212 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
213 GEN6_BLITTER_LOCK_SHIFT);
214 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
215 POSTING_READ(GEN6_BLITTER_ECOSKPD);
217 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
220 static void ironlake_enable_fbc(struct drm_crtc *crtc)
222 struct drm_device *dev = crtc->dev;
223 struct drm_i915_private *dev_priv = dev->dev_private;
224 struct drm_framebuffer *fb = crtc->primary->fb;
225 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
226 struct drm_i915_gem_object *obj = intel_fb->obj;
227 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
230 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane);
231 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
232 dev_priv->fbc.threshold++;
234 switch (dev_priv->fbc.threshold) {
237 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
240 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
243 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
246 dpfc_ctl |= DPFC_CTL_FENCE_EN;
248 dpfc_ctl |= obj->fence_reg;
250 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
251 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
253 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
256 I915_WRITE(SNB_DPFC_CTL_SA,
257 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
258 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
259 sandybridge_blit_fbc_update(dev);
262 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
265 static void ironlake_disable_fbc(struct drm_device *dev)
267 struct drm_i915_private *dev_priv = dev->dev_private;
270 /* Disable compression */
271 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
272 if (dpfc_ctl & DPFC_CTL_EN) {
273 dpfc_ctl &= ~DPFC_CTL_EN;
274 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
276 DRM_DEBUG_KMS("disabled FBC\n");
280 static bool ironlake_fbc_enabled(struct drm_device *dev)
282 struct drm_i915_private *dev_priv = dev->dev_private;
284 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
287 static void gen7_enable_fbc(struct drm_crtc *crtc)
289 struct drm_device *dev = crtc->dev;
290 struct drm_i915_private *dev_priv = dev->dev_private;
291 struct drm_framebuffer *fb = crtc->primary->fb;
292 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
293 struct drm_i915_gem_object *obj = intel_fb->obj;
294 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
297 dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane);
298 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
299 dev_priv->fbc.threshold++;
301 switch (dev_priv->fbc.threshold) {
304 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
307 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
310 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
314 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
316 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
318 if (IS_IVYBRIDGE(dev)) {
319 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
320 I915_WRITE(ILK_DISPLAY_CHICKEN1,
321 I915_READ(ILK_DISPLAY_CHICKEN1) |
324 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
325 I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe),
326 I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) |
330 I915_WRITE(SNB_DPFC_CTL_SA,
331 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
332 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
334 sandybridge_blit_fbc_update(dev);
336 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
339 bool intel_fbc_enabled(struct drm_device *dev)
341 struct drm_i915_private *dev_priv = dev->dev_private;
343 if (!dev_priv->display.fbc_enabled)
346 return dev_priv->display.fbc_enabled(dev);
349 static void intel_fbc_work_fn(struct work_struct *__work)
351 struct intel_fbc_work *work =
352 container_of(to_delayed_work(__work),
353 struct intel_fbc_work, work);
354 struct drm_device *dev = work->crtc->dev;
355 struct drm_i915_private *dev_priv = dev->dev_private;
357 mutex_lock(&dev->struct_mutex);
358 if (work == dev_priv->fbc.fbc_work) {
359 /* Double check that we haven't switched fb without cancelling
362 if (work->crtc->primary->fb == work->fb) {
363 dev_priv->display.enable_fbc(work->crtc);
365 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
366 dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id;
367 dev_priv->fbc.y = work->crtc->y;
370 dev_priv->fbc.fbc_work = NULL;
372 mutex_unlock(&dev->struct_mutex);
377 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
379 if (dev_priv->fbc.fbc_work == NULL)
382 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
384 /* Synchronisation is provided by struct_mutex and checking of
385 * dev_priv->fbc.fbc_work, so we can perform the cancellation
386 * entirely asynchronously.
388 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
389 /* tasklet was killed before being run, clean up */
390 kfree(dev_priv->fbc.fbc_work);
392 /* Mark the work as no longer wanted so that if it does
393 * wake-up (because the work was already running and waiting
394 * for our mutex), it will discover that is no longer
397 dev_priv->fbc.fbc_work = NULL;
400 static void intel_enable_fbc(struct drm_crtc *crtc)
402 struct intel_fbc_work *work;
403 struct drm_device *dev = crtc->dev;
404 struct drm_i915_private *dev_priv = dev->dev_private;
406 if (!dev_priv->display.enable_fbc)
409 intel_cancel_fbc_work(dev_priv);
411 work = kzalloc(sizeof(*work), GFP_KERNEL);
413 DRM_ERROR("Failed to allocate FBC work structure\n");
414 dev_priv->display.enable_fbc(crtc);
419 work->fb = crtc->primary->fb;
420 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
422 dev_priv->fbc.fbc_work = work;
424 /* Delay the actual enabling to let pageflipping cease and the
425 * display to settle before starting the compression. Note that
426 * this delay also serves a second purpose: it allows for a
427 * vblank to pass after disabling the FBC before we attempt
428 * to modify the control registers.
430 * A more complicated solution would involve tracking vblanks
431 * following the termination of the page-flipping sequence
432 * and indeed performing the enable as a co-routine and not
433 * waiting synchronously upon the vblank.
435 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
437 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
440 void intel_disable_fbc(struct drm_device *dev)
442 struct drm_i915_private *dev_priv = dev->dev_private;
444 intel_cancel_fbc_work(dev_priv);
446 if (!dev_priv->display.disable_fbc)
449 dev_priv->display.disable_fbc(dev);
450 dev_priv->fbc.plane = -1;
453 static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
454 enum no_fbc_reason reason)
456 if (dev_priv->fbc.no_fbc_reason == reason)
459 dev_priv->fbc.no_fbc_reason = reason;
464 * intel_update_fbc - enable/disable FBC as needed
465 * @dev: the drm_device
467 * Set up the framebuffer compression hardware at mode set time. We
468 * enable it if possible:
469 * - plane A only (on pre-965)
470 * - no pixel mulitply/line duplication
471 * - no alpha buffer discard
473 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
475 * We can't assume that any compression will take place (worst case),
476 * so the compressed buffer has to be the same size as the uncompressed
477 * one. It also must reside (along with the line length buffer) in
480 * We need to enable/disable FBC on a global basis.
482 void intel_update_fbc(struct drm_device *dev)
484 struct drm_i915_private *dev_priv = dev->dev_private;
485 struct drm_crtc *crtc = NULL, *tmp_crtc;
486 struct intel_crtc *intel_crtc;
487 struct drm_framebuffer *fb;
488 struct intel_framebuffer *intel_fb;
489 struct drm_i915_gem_object *obj;
490 const struct drm_display_mode *adjusted_mode;
491 unsigned int max_width, max_height;
494 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
498 if (!i915.powersave) {
499 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
500 DRM_DEBUG_KMS("fbc disabled per module param\n");
505 * If FBC is already on, we just have to verify that we can
506 * keep it that way...
507 * Need to disable if:
508 * - more than one pipe is active
509 * - changing FBC params (stride, fence, mode)
510 * - new fb is too large to fit in compressed buffer
511 * - going to an unsupported config (interlace, pixel multiply, etc.)
513 for_each_crtc(dev, tmp_crtc) {
514 if (intel_crtc_active(tmp_crtc) &&
515 to_intel_crtc(tmp_crtc)->primary_enabled) {
517 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
518 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
525 if (!crtc || crtc->primary->fb == NULL) {
526 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
527 DRM_DEBUG_KMS("no output, disabling\n");
531 intel_crtc = to_intel_crtc(crtc);
532 fb = crtc->primary->fb;
533 intel_fb = to_intel_framebuffer(fb);
535 adjusted_mode = &intel_crtc->config.adjusted_mode;
537 if (i915.enable_fbc < 0) {
538 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
539 DRM_DEBUG_KMS("disabled per chip default\n");
542 if (!i915.enable_fbc) {
543 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
544 DRM_DEBUG_KMS("fbc disabled per module param\n");
547 if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
548 (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
549 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
550 DRM_DEBUG_KMS("mode incompatible with compression, "
555 if (INTEL_INFO(dev)->gen >= 8 || IS_HASWELL(dev)) {
558 } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
565 if (intel_crtc->config.pipe_src_w > max_width ||
566 intel_crtc->config.pipe_src_h > max_height) {
567 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
568 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
571 if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) &&
572 intel_crtc->plane != PLANE_A) {
573 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
574 DRM_DEBUG_KMS("plane not A, disabling compression\n");
578 /* The use of a CPU fence is mandatory in order to detect writes
579 * by the CPU to the scanout and trigger updates to the FBC.
581 if (obj->tiling_mode != I915_TILING_X ||
582 obj->fence_reg == I915_FENCE_REG_NONE) {
583 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
584 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
588 /* If the kernel debugger is active, always disable compression */
592 if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size,
593 drm_format_plane_cpp(fb->pixel_format, 0))) {
594 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
595 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
599 /* If the scanout has not changed, don't modify the FBC settings.
600 * Note that we make the fundamental assumption that the fb->obj
601 * cannot be unpinned (and have its GTT offset and fence revoked)
602 * without first being decoupled from the scanout and FBC disabled.
604 if (dev_priv->fbc.plane == intel_crtc->plane &&
605 dev_priv->fbc.fb_id == fb->base.id &&
606 dev_priv->fbc.y == crtc->y)
609 if (intel_fbc_enabled(dev)) {
610 /* We update FBC along two paths, after changing fb/crtc
611 * configuration (modeswitching) and after page-flipping
612 * finishes. For the latter, we know that not only did
613 * we disable the FBC at the start of the page-flip
614 * sequence, but also more than one vblank has passed.
616 * For the former case of modeswitching, it is possible
617 * to switch between two FBC valid configurations
618 * instantaneously so we do need to disable the FBC
619 * before we can modify its control registers. We also
620 * have to wait for the next vblank for that to take
621 * effect. However, since we delay enabling FBC we can
622 * assume that a vblank has passed since disabling and
623 * that we can safely alter the registers in the deferred
626 * In the scenario that we go from a valid to invalid
627 * and then back to valid FBC configuration we have
628 * no strict enforcement that a vblank occurred since
629 * disabling the FBC. However, along all current pipe
630 * disabling paths we do need to wait for a vblank at
631 * some point. And we wait before enabling FBC anyway.
633 DRM_DEBUG_KMS("disabling active FBC for update\n");
634 intel_disable_fbc(dev);
637 intel_enable_fbc(crtc);
638 dev_priv->fbc.no_fbc_reason = FBC_OK;
642 /* Multiple disables should be harmless */
643 if (intel_fbc_enabled(dev)) {
644 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
645 intel_disable_fbc(dev);
647 i915_gem_stolen_cleanup_compression(dev);
650 static void i915_pineview_get_mem_freq(struct drm_device *dev)
652 struct drm_i915_private *dev_priv = dev->dev_private;
655 tmp = I915_READ(CLKCFG);
657 switch (tmp & CLKCFG_FSB_MASK) {
659 dev_priv->fsb_freq = 533; /* 133*4 */
662 dev_priv->fsb_freq = 800; /* 200*4 */
665 dev_priv->fsb_freq = 667; /* 167*4 */
668 dev_priv->fsb_freq = 400; /* 100*4 */
672 switch (tmp & CLKCFG_MEM_MASK) {
674 dev_priv->mem_freq = 533;
677 dev_priv->mem_freq = 667;
680 dev_priv->mem_freq = 800;
684 /* detect pineview DDR3 setting */
685 tmp = I915_READ(CSHRDDR3CTL);
686 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
689 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
691 struct drm_i915_private *dev_priv = dev->dev_private;
694 ddrpll = I915_READ16(DDRMPLL1);
695 csipll = I915_READ16(CSIPLL0);
697 switch (ddrpll & 0xff) {
699 dev_priv->mem_freq = 800;
702 dev_priv->mem_freq = 1066;
705 dev_priv->mem_freq = 1333;
708 dev_priv->mem_freq = 1600;
711 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
713 dev_priv->mem_freq = 0;
717 dev_priv->ips.r_t = dev_priv->mem_freq;
719 switch (csipll & 0x3ff) {
721 dev_priv->fsb_freq = 3200;
724 dev_priv->fsb_freq = 3733;
727 dev_priv->fsb_freq = 4266;
730 dev_priv->fsb_freq = 4800;
733 dev_priv->fsb_freq = 5333;
736 dev_priv->fsb_freq = 5866;
739 dev_priv->fsb_freq = 6400;
742 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
744 dev_priv->fsb_freq = 0;
748 if (dev_priv->fsb_freq == 3200) {
749 dev_priv->ips.c_m = 0;
750 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
751 dev_priv->ips.c_m = 1;
753 dev_priv->ips.c_m = 2;
757 static const struct cxsr_latency cxsr_latency_table[] = {
758 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
759 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
760 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
761 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
762 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
764 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
765 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
766 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
767 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
768 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
770 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
771 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
772 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
773 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
774 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
776 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
777 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
778 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
779 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
780 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
782 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
783 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
784 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
785 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
786 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
788 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
789 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
790 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
791 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
792 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
795 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
800 const struct cxsr_latency *latency;
803 if (fsb == 0 || mem == 0)
806 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
807 latency = &cxsr_latency_table[i];
808 if (is_desktop == latency->is_desktop &&
809 is_ddr3 == latency->is_ddr3 &&
810 fsb == latency->fsb_freq && mem == latency->mem_freq)
814 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
819 static void pineview_disable_cxsr(struct drm_device *dev)
821 struct drm_i915_private *dev_priv = dev->dev_private;
823 /* deactivate cxsr */
824 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
828 * Latency for FIFO fetches is dependent on several factors:
829 * - memory configuration (speed, channels)
831 * - current MCH state
832 * It can be fairly high in some situations, so here we assume a fairly
833 * pessimal value. It's a tradeoff between extra memory fetches (if we
834 * set this value too high, the FIFO will fetch frequently to stay full)
835 * and power consumption (set it too low to save power and we might see
836 * FIFO underruns and display "flicker").
838 * A value of 5us seems to be a good balance; safe for very low end
839 * platforms but not overly aggressive on lower latency configs.
841 static const int latency_ns = 5000;
843 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
845 struct drm_i915_private *dev_priv = dev->dev_private;
846 uint32_t dsparb = I915_READ(DSPARB);
849 size = dsparb & 0x7f;
851 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
853 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
854 plane ? "B" : "A", size);
859 static int i830_get_fifo_size(struct drm_device *dev, int plane)
861 struct drm_i915_private *dev_priv = dev->dev_private;
862 uint32_t dsparb = I915_READ(DSPARB);
865 size = dsparb & 0x1ff;
867 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
868 size >>= 1; /* Convert to cachelines */
870 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
871 plane ? "B" : "A", size);
876 static int i845_get_fifo_size(struct drm_device *dev, int plane)
878 struct drm_i915_private *dev_priv = dev->dev_private;
879 uint32_t dsparb = I915_READ(DSPARB);
882 size = dsparb & 0x7f;
883 size >>= 2; /* Convert to cachelines */
885 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
892 /* Pineview has different values for various configs */
893 static const struct intel_watermark_params pineview_display_wm = {
894 .fifo_size = PINEVIEW_DISPLAY_FIFO,
895 .max_wm = PINEVIEW_MAX_WM,
896 .default_wm = PINEVIEW_DFT_WM,
897 .guard_size = PINEVIEW_GUARD_WM,
898 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
900 static const struct intel_watermark_params pineview_display_hplloff_wm = {
901 .fifo_size = PINEVIEW_DISPLAY_FIFO,
902 .max_wm = PINEVIEW_MAX_WM,
903 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
904 .guard_size = PINEVIEW_GUARD_WM,
905 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
907 static const struct intel_watermark_params pineview_cursor_wm = {
908 .fifo_size = PINEVIEW_CURSOR_FIFO,
909 .max_wm = PINEVIEW_CURSOR_MAX_WM,
910 .default_wm = PINEVIEW_CURSOR_DFT_WM,
911 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
912 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
914 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
915 .fifo_size = PINEVIEW_CURSOR_FIFO,
916 .max_wm = PINEVIEW_CURSOR_MAX_WM,
917 .default_wm = PINEVIEW_CURSOR_DFT_WM,
918 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
919 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
921 static const struct intel_watermark_params g4x_wm_info = {
922 .fifo_size = G4X_FIFO_SIZE,
923 .max_wm = G4X_MAX_WM,
924 .default_wm = G4X_MAX_WM,
926 .cacheline_size = G4X_FIFO_LINE_SIZE,
928 static const struct intel_watermark_params g4x_cursor_wm_info = {
929 .fifo_size = I965_CURSOR_FIFO,
930 .max_wm = I965_CURSOR_MAX_WM,
931 .default_wm = I965_CURSOR_DFT_WM,
933 .cacheline_size = G4X_FIFO_LINE_SIZE,
935 static const struct intel_watermark_params valleyview_wm_info = {
936 .fifo_size = VALLEYVIEW_FIFO_SIZE,
937 .max_wm = VALLEYVIEW_MAX_WM,
938 .default_wm = VALLEYVIEW_MAX_WM,
940 .cacheline_size = G4X_FIFO_LINE_SIZE,
942 static const struct intel_watermark_params valleyview_cursor_wm_info = {
943 .fifo_size = I965_CURSOR_FIFO,
944 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
945 .default_wm = I965_CURSOR_DFT_WM,
947 .cacheline_size = G4X_FIFO_LINE_SIZE,
949 static const struct intel_watermark_params i965_cursor_wm_info = {
950 .fifo_size = I965_CURSOR_FIFO,
951 .max_wm = I965_CURSOR_MAX_WM,
952 .default_wm = I965_CURSOR_DFT_WM,
954 .cacheline_size = I915_FIFO_LINE_SIZE,
956 static const struct intel_watermark_params i945_wm_info = {
957 .fifo_size = I945_FIFO_SIZE,
958 .max_wm = I915_MAX_WM,
961 .cacheline_size = I915_FIFO_LINE_SIZE,
963 static const struct intel_watermark_params i915_wm_info = {
964 .fifo_size = I915_FIFO_SIZE,
965 .max_wm = I915_MAX_WM,
968 .cacheline_size = I915_FIFO_LINE_SIZE,
970 static const struct intel_watermark_params i830_wm_info = {
971 .fifo_size = I855GM_FIFO_SIZE,
972 .max_wm = I915_MAX_WM,
975 .cacheline_size = I830_FIFO_LINE_SIZE,
977 static const struct intel_watermark_params i845_wm_info = {
978 .fifo_size = I830_FIFO_SIZE,
979 .max_wm = I915_MAX_WM,
982 .cacheline_size = I830_FIFO_LINE_SIZE,
986 * intel_calculate_wm - calculate watermark level
987 * @clock_in_khz: pixel clock
988 * @wm: chip FIFO params
989 * @pixel_size: display pixel size
990 * @latency_ns: memory latency for the platform
992 * Calculate the watermark level (the level at which the display plane will
993 * start fetching from memory again). Each chip has a different display
994 * FIFO size and allocation, so the caller needs to figure that out and pass
995 * in the correct intel_watermark_params structure.
997 * As the pixel clock runs, the FIFO will be drained at a rate that depends
998 * on the pixel size. When it reaches the watermark level, it'll start
999 * fetching FIFO line sized based chunks from memory until the FIFO fills
1000 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1001 * will occur, and a display engine hang could result.
1003 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1004 const struct intel_watermark_params *wm,
1007 unsigned long latency_ns)
1009 long entries_required, wm_size;
1012 * Note: we need to make sure we don't overflow for various clock &
1014 * clocks go from a few thousand to several hundred thousand.
1015 * latency is usually a few thousand
1017 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1019 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1021 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1023 wm_size = fifo_size - (entries_required + wm->guard_size);
1025 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1027 /* Don't promote wm_size to unsigned... */
1028 if (wm_size > (long)wm->max_wm)
1029 wm_size = wm->max_wm;
1031 wm_size = wm->default_wm;
1035 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1037 struct drm_crtc *crtc, *enabled = NULL;
1039 for_each_crtc(dev, crtc) {
1040 if (intel_crtc_active(crtc)) {
1050 static void pineview_update_wm(struct drm_crtc *unused_crtc)
1052 struct drm_device *dev = unused_crtc->dev;
1053 struct drm_i915_private *dev_priv = dev->dev_private;
1054 struct drm_crtc *crtc;
1055 const struct cxsr_latency *latency;
1059 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1060 dev_priv->fsb_freq, dev_priv->mem_freq);
1062 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1063 pineview_disable_cxsr(dev);
1067 crtc = single_enabled_crtc(dev);
1069 const struct drm_display_mode *adjusted_mode;
1070 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1073 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1074 clock = adjusted_mode->crtc_clock;
1077 wm = intel_calculate_wm(clock, &pineview_display_wm,
1078 pineview_display_wm.fifo_size,
1079 pixel_size, latency->display_sr);
1080 reg = I915_READ(DSPFW1);
1081 reg &= ~DSPFW_SR_MASK;
1082 reg |= wm << DSPFW_SR_SHIFT;
1083 I915_WRITE(DSPFW1, reg);
1084 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1087 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1088 pineview_display_wm.fifo_size,
1089 pixel_size, latency->cursor_sr);
1090 reg = I915_READ(DSPFW3);
1091 reg &= ~DSPFW_CURSOR_SR_MASK;
1092 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1093 I915_WRITE(DSPFW3, reg);
1095 /* Display HPLL off SR */
1096 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1097 pineview_display_hplloff_wm.fifo_size,
1098 pixel_size, latency->display_hpll_disable);
1099 reg = I915_READ(DSPFW3);
1100 reg &= ~DSPFW_HPLL_SR_MASK;
1101 reg |= wm & DSPFW_HPLL_SR_MASK;
1102 I915_WRITE(DSPFW3, reg);
1104 /* cursor HPLL off SR */
1105 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1106 pineview_display_hplloff_wm.fifo_size,
1107 pixel_size, latency->cursor_hpll_disable);
1108 reg = I915_READ(DSPFW3);
1109 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1110 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1111 I915_WRITE(DSPFW3, reg);
1112 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1116 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1117 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1119 pineview_disable_cxsr(dev);
1120 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1124 static bool g4x_compute_wm0(struct drm_device *dev,
1126 const struct intel_watermark_params *display,
1127 int display_latency_ns,
1128 const struct intel_watermark_params *cursor,
1129 int cursor_latency_ns,
1133 struct drm_crtc *crtc;
1134 const struct drm_display_mode *adjusted_mode;
1135 int htotal, hdisplay, clock, pixel_size;
1136 int line_time_us, line_count;
1137 int entries, tlb_miss;
1139 crtc = intel_get_crtc_for_plane(dev, plane);
1140 if (!intel_crtc_active(crtc)) {
1141 *cursor_wm = cursor->guard_size;
1142 *plane_wm = display->guard_size;
1146 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1147 clock = adjusted_mode->crtc_clock;
1148 htotal = adjusted_mode->crtc_htotal;
1149 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1150 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1152 /* Use the small buffer method to calculate plane watermark */
1153 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1154 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1156 entries += tlb_miss;
1157 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1158 *plane_wm = entries + display->guard_size;
1159 if (*plane_wm > (int)display->max_wm)
1160 *plane_wm = display->max_wm;
1162 /* Use the large buffer method to calculate cursor watermark */
1163 line_time_us = max(htotal * 1000 / clock, 1);
1164 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1165 entries = line_count * to_intel_crtc(crtc)->cursor_width * pixel_size;
1166 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1168 entries += tlb_miss;
1169 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1170 *cursor_wm = entries + cursor->guard_size;
1171 if (*cursor_wm > (int)cursor->max_wm)
1172 *cursor_wm = (int)cursor->max_wm;
1178 * Check the wm result.
1180 * If any calculated watermark values is larger than the maximum value that
1181 * can be programmed into the associated watermark register, that watermark
1184 static bool g4x_check_srwm(struct drm_device *dev,
1185 int display_wm, int cursor_wm,
1186 const struct intel_watermark_params *display,
1187 const struct intel_watermark_params *cursor)
1189 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1190 display_wm, cursor_wm);
1192 if (display_wm > display->max_wm) {
1193 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1194 display_wm, display->max_wm);
1198 if (cursor_wm > cursor->max_wm) {
1199 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1200 cursor_wm, cursor->max_wm);
1204 if (!(display_wm || cursor_wm)) {
1205 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1212 static bool g4x_compute_srwm(struct drm_device *dev,
1215 const struct intel_watermark_params *display,
1216 const struct intel_watermark_params *cursor,
1217 int *display_wm, int *cursor_wm)
1219 struct drm_crtc *crtc;
1220 const struct drm_display_mode *adjusted_mode;
1221 int hdisplay, htotal, pixel_size, clock;
1222 unsigned long line_time_us;
1223 int line_count, line_size;
1228 *display_wm = *cursor_wm = 0;
1232 crtc = intel_get_crtc_for_plane(dev, plane);
1233 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1234 clock = adjusted_mode->crtc_clock;
1235 htotal = adjusted_mode->crtc_htotal;
1236 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1237 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1239 line_time_us = max(htotal * 1000 / clock, 1);
1240 line_count = (latency_ns / line_time_us + 1000) / 1000;
1241 line_size = hdisplay * pixel_size;
1243 /* Use the minimum of the small and large buffer method for primary */
1244 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1245 large = line_count * line_size;
1247 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1248 *display_wm = entries + display->guard_size;
1250 /* calculate the self-refresh watermark for display cursor */
1251 entries = line_count * pixel_size * to_intel_crtc(crtc)->cursor_width;
1252 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1253 *cursor_wm = entries + cursor->guard_size;
1255 return g4x_check_srwm(dev,
1256 *display_wm, *cursor_wm,
1260 static bool vlv_compute_drain_latency(struct drm_device *dev,
1262 int *plane_prec_mult,
1264 int *cursor_prec_mult,
1267 struct drm_crtc *crtc;
1268 int clock, pixel_size;
1271 crtc = intel_get_crtc_for_plane(dev, plane);
1272 if (!intel_crtc_active(crtc))
1275 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
1276 pixel_size = crtc->primary->fb->bits_per_pixel / 8; /* BPP */
1278 entries = (clock / 1000) * pixel_size;
1279 *plane_prec_mult = (entries > 256) ?
1280 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1281 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1284 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1285 *cursor_prec_mult = (entries > 256) ?
1286 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1287 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1293 * Update drain latency registers of memory arbiter
1295 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1296 * to be programmed. Each plane has a drain latency multiplier and a drain
1300 static void vlv_update_drain_latency(struct drm_device *dev)
1302 struct drm_i915_private *dev_priv = dev->dev_private;
1303 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1304 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1305 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1308 /* For plane A, Cursor A */
1309 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1310 &cursor_prec_mult, &cursora_dl)) {
1311 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1312 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1313 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1314 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1316 I915_WRITE(VLV_DDL1, cursora_prec |
1317 (cursora_dl << DDL_CURSORA_SHIFT) |
1318 planea_prec | planea_dl);
1321 /* For plane B, Cursor B */
1322 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1323 &cursor_prec_mult, &cursorb_dl)) {
1324 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1325 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1326 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1327 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1329 I915_WRITE(VLV_DDL2, cursorb_prec |
1330 (cursorb_dl << DDL_CURSORB_SHIFT) |
1331 planeb_prec | planeb_dl);
1335 #define single_plane_enabled(mask) is_power_of_2(mask)
1337 static void valleyview_update_wm(struct drm_crtc *crtc)
1339 struct drm_device *dev = crtc->dev;
1340 static const int sr_latency_ns = 12000;
1341 struct drm_i915_private *dev_priv = dev->dev_private;
1342 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1343 int plane_sr, cursor_sr;
1344 int ignore_plane_sr, ignore_cursor_sr;
1345 unsigned int enabled = 0;
1347 vlv_update_drain_latency(dev);
1349 if (g4x_compute_wm0(dev, PIPE_A,
1350 &valleyview_wm_info, latency_ns,
1351 &valleyview_cursor_wm_info, latency_ns,
1352 &planea_wm, &cursora_wm))
1353 enabled |= 1 << PIPE_A;
1355 if (g4x_compute_wm0(dev, PIPE_B,
1356 &valleyview_wm_info, latency_ns,
1357 &valleyview_cursor_wm_info, latency_ns,
1358 &planeb_wm, &cursorb_wm))
1359 enabled |= 1 << PIPE_B;
1361 if (single_plane_enabled(enabled) &&
1362 g4x_compute_srwm(dev, ffs(enabled) - 1,
1364 &valleyview_wm_info,
1365 &valleyview_cursor_wm_info,
1366 &plane_sr, &ignore_cursor_sr) &&
1367 g4x_compute_srwm(dev, ffs(enabled) - 1,
1369 &valleyview_wm_info,
1370 &valleyview_cursor_wm_info,
1371 &ignore_plane_sr, &cursor_sr)) {
1372 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1374 I915_WRITE(FW_BLC_SELF_VLV,
1375 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1376 plane_sr = cursor_sr = 0;
1379 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1380 planea_wm, cursora_wm,
1381 planeb_wm, cursorb_wm,
1382 plane_sr, cursor_sr);
1385 (plane_sr << DSPFW_SR_SHIFT) |
1386 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1387 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1390 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1391 (cursora_wm << DSPFW_CURSORA_SHIFT));
1393 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1394 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1397 static void g4x_update_wm(struct drm_crtc *crtc)
1399 struct drm_device *dev = crtc->dev;
1400 static const int sr_latency_ns = 12000;
1401 struct drm_i915_private *dev_priv = dev->dev_private;
1402 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1403 int plane_sr, cursor_sr;
1404 unsigned int enabled = 0;
1406 if (g4x_compute_wm0(dev, PIPE_A,
1407 &g4x_wm_info, latency_ns,
1408 &g4x_cursor_wm_info, latency_ns,
1409 &planea_wm, &cursora_wm))
1410 enabled |= 1 << PIPE_A;
1412 if (g4x_compute_wm0(dev, PIPE_B,
1413 &g4x_wm_info, latency_ns,
1414 &g4x_cursor_wm_info, latency_ns,
1415 &planeb_wm, &cursorb_wm))
1416 enabled |= 1 << PIPE_B;
1418 if (single_plane_enabled(enabled) &&
1419 g4x_compute_srwm(dev, ffs(enabled) - 1,
1422 &g4x_cursor_wm_info,
1423 &plane_sr, &cursor_sr)) {
1424 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1426 I915_WRITE(FW_BLC_SELF,
1427 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1428 plane_sr = cursor_sr = 0;
1431 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1432 planea_wm, cursora_wm,
1433 planeb_wm, cursorb_wm,
1434 plane_sr, cursor_sr);
1437 (plane_sr << DSPFW_SR_SHIFT) |
1438 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1439 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1442 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1443 (cursora_wm << DSPFW_CURSORA_SHIFT));
1444 /* HPLL off in SR has some issues on G4x... disable it */
1446 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1447 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1450 static void i965_update_wm(struct drm_crtc *unused_crtc)
1452 struct drm_device *dev = unused_crtc->dev;
1453 struct drm_i915_private *dev_priv = dev->dev_private;
1454 struct drm_crtc *crtc;
1458 /* Calc sr entries for one plane configs */
1459 crtc = single_enabled_crtc(dev);
1461 /* self-refresh has much higher latency */
1462 static const int sr_latency_ns = 12000;
1463 const struct drm_display_mode *adjusted_mode =
1464 &to_intel_crtc(crtc)->config.adjusted_mode;
1465 int clock = adjusted_mode->crtc_clock;
1466 int htotal = adjusted_mode->crtc_htotal;
1467 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1468 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1469 unsigned long line_time_us;
1472 line_time_us = max(htotal * 1000 / clock, 1);
1474 /* Use ns/us then divide to preserve precision */
1475 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1476 pixel_size * hdisplay;
1477 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1478 srwm = I965_FIFO_SIZE - entries;
1482 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1485 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1486 pixel_size * to_intel_crtc(crtc)->cursor_width;
1487 entries = DIV_ROUND_UP(entries,
1488 i965_cursor_wm_info.cacheline_size);
1489 cursor_sr = i965_cursor_wm_info.fifo_size -
1490 (entries + i965_cursor_wm_info.guard_size);
1492 if (cursor_sr > i965_cursor_wm_info.max_wm)
1493 cursor_sr = i965_cursor_wm_info.max_wm;
1495 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1496 "cursor %d\n", srwm, cursor_sr);
1498 if (IS_CRESTLINE(dev))
1499 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1501 /* Turn off self refresh if both pipes are enabled */
1502 if (IS_CRESTLINE(dev))
1503 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1507 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1510 /* 965 has limitations... */
1511 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1512 (8 << 16) | (8 << 8) | (8 << 0));
1513 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1514 /* update cursor SR watermark */
1515 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1518 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1520 struct drm_device *dev = unused_crtc->dev;
1521 struct drm_i915_private *dev_priv = dev->dev_private;
1522 const struct intel_watermark_params *wm_info;
1527 int planea_wm, planeb_wm;
1528 struct drm_crtc *crtc, *enabled = NULL;
1531 wm_info = &i945_wm_info;
1532 else if (!IS_GEN2(dev))
1533 wm_info = &i915_wm_info;
1535 wm_info = &i830_wm_info;
1537 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1538 crtc = intel_get_crtc_for_plane(dev, 0);
1539 if (intel_crtc_active(crtc)) {
1540 const struct drm_display_mode *adjusted_mode;
1541 int cpp = crtc->primary->fb->bits_per_pixel / 8;
1545 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1546 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1547 wm_info, fifo_size, cpp,
1551 planea_wm = fifo_size - wm_info->guard_size;
1553 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1554 crtc = intel_get_crtc_for_plane(dev, 1);
1555 if (intel_crtc_active(crtc)) {
1556 const struct drm_display_mode *adjusted_mode;
1557 int cpp = crtc->primary->fb->bits_per_pixel / 8;
1561 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1562 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1563 wm_info, fifo_size, cpp,
1565 if (enabled == NULL)
1570 planeb_wm = fifo_size - wm_info->guard_size;
1572 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1574 if (IS_I915GM(dev) && enabled) {
1575 struct intel_framebuffer *fb;
1577 fb = to_intel_framebuffer(enabled->primary->fb);
1579 /* self-refresh seems busted with untiled */
1580 if (fb->obj->tiling_mode == I915_TILING_NONE)
1585 * Overlay gets an aggressive default since video jitter is bad.
1589 /* Play safe and disable self-refresh before adjusting watermarks. */
1590 if (IS_I945G(dev) || IS_I945GM(dev))
1591 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1592 else if (IS_I915GM(dev))
1593 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_SELF_EN));
1595 /* Calc sr entries for one plane configs */
1596 if (HAS_FW_BLC(dev) && enabled) {
1597 /* self-refresh has much higher latency */
1598 static const int sr_latency_ns = 6000;
1599 const struct drm_display_mode *adjusted_mode =
1600 &to_intel_crtc(enabled)->config.adjusted_mode;
1601 int clock = adjusted_mode->crtc_clock;
1602 int htotal = adjusted_mode->crtc_htotal;
1603 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
1604 int pixel_size = enabled->primary->fb->bits_per_pixel / 8;
1605 unsigned long line_time_us;
1608 line_time_us = max(htotal * 1000 / clock, 1);
1610 /* Use ns/us then divide to preserve precision */
1611 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1612 pixel_size * hdisplay;
1613 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1614 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1615 srwm = wm_info->fifo_size - entries;
1619 if (IS_I945G(dev) || IS_I945GM(dev))
1620 I915_WRITE(FW_BLC_SELF,
1621 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1622 else if (IS_I915GM(dev))
1623 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1626 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1627 planea_wm, planeb_wm, cwm, srwm);
1629 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1630 fwater_hi = (cwm & 0x1f);
1632 /* Set request length to 8 cachelines per fetch */
1633 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1634 fwater_hi = fwater_hi | (1 << 8);
1636 I915_WRITE(FW_BLC, fwater_lo);
1637 I915_WRITE(FW_BLC2, fwater_hi);
1639 if (HAS_FW_BLC(dev)) {
1641 if (IS_I945G(dev) || IS_I945GM(dev))
1642 I915_WRITE(FW_BLC_SELF,
1643 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1644 else if (IS_I915GM(dev))
1645 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_SELF_EN));
1646 DRM_DEBUG_KMS("memory self refresh enabled\n");
1648 DRM_DEBUG_KMS("memory self refresh disabled\n");
1652 static void i845_update_wm(struct drm_crtc *unused_crtc)
1654 struct drm_device *dev = unused_crtc->dev;
1655 struct drm_i915_private *dev_priv = dev->dev_private;
1656 struct drm_crtc *crtc;
1657 const struct drm_display_mode *adjusted_mode;
1661 crtc = single_enabled_crtc(dev);
1665 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1666 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1668 dev_priv->display.get_fifo_size(dev, 0),
1670 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1671 fwater_lo |= (3<<8) | planea_wm;
1673 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1675 I915_WRITE(FW_BLC, fwater_lo);
1678 static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1679 struct drm_crtc *crtc)
1681 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1682 uint32_t pixel_rate;
1684 pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
1686 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1687 * adjust the pixel_rate here. */
1689 if (intel_crtc->config.pch_pfit.enabled) {
1690 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1691 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
1693 pipe_w = intel_crtc->config.pipe_src_w;
1694 pipe_h = intel_crtc->config.pipe_src_h;
1695 pfit_w = (pfit_size >> 16) & 0xFFFF;
1696 pfit_h = pfit_size & 0xFFFF;
1697 if (pipe_w < pfit_w)
1699 if (pipe_h < pfit_h)
1702 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1709 /* latency must be in 0.1us units. */
1710 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
1715 if (WARN(latency == 0, "Latency value missing\n"))
1718 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1719 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1724 /* latency must be in 0.1us units. */
1725 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1726 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1731 if (WARN(latency == 0, "Latency value missing\n"))
1734 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1735 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1736 ret = DIV_ROUND_UP(ret, 64) + 2;
1740 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1741 uint8_t bytes_per_pixel)
1743 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1746 struct ilk_pipe_wm_parameters {
1748 uint32_t pipe_htotal;
1749 uint32_t pixel_rate;
1750 struct intel_plane_wm_parameters pri;
1751 struct intel_plane_wm_parameters spr;
1752 struct intel_plane_wm_parameters cur;
1755 struct ilk_wm_maximums {
1762 /* used in computing the new watermarks state */
1763 struct intel_wm_config {
1764 unsigned int num_pipes_active;
1765 bool sprites_enabled;
1766 bool sprites_scaled;
1770 * For both WM_PIPE and WM_LP.
1771 * mem_value must be in 0.1us units.
1773 static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
1777 uint32_t method1, method2;
1779 if (!params->active || !params->pri.enabled)
1782 method1 = ilk_wm_method1(params->pixel_rate,
1783 params->pri.bytes_per_pixel,
1789 method2 = ilk_wm_method2(params->pixel_rate,
1790 params->pipe_htotal,
1791 params->pri.horiz_pixels,
1792 params->pri.bytes_per_pixel,
1795 return min(method1, method2);
1799 * For both WM_PIPE and WM_LP.
1800 * mem_value must be in 0.1us units.
1802 static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
1805 uint32_t method1, method2;
1807 if (!params->active || !params->spr.enabled)
1810 method1 = ilk_wm_method1(params->pixel_rate,
1811 params->spr.bytes_per_pixel,
1813 method2 = ilk_wm_method2(params->pixel_rate,
1814 params->pipe_htotal,
1815 params->spr.horiz_pixels,
1816 params->spr.bytes_per_pixel,
1818 return min(method1, method2);
1822 * For both WM_PIPE and WM_LP.
1823 * mem_value must be in 0.1us units.
1825 static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
1828 if (!params->active || !params->cur.enabled)
1831 return ilk_wm_method2(params->pixel_rate,
1832 params->pipe_htotal,
1833 params->cur.horiz_pixels,
1834 params->cur.bytes_per_pixel,
1838 /* Only for WM_LP. */
1839 static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1842 if (!params->active || !params->pri.enabled)
1845 return ilk_wm_fbc(pri_val,
1846 params->pri.horiz_pixels,
1847 params->pri.bytes_per_pixel);
1850 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1852 if (INTEL_INFO(dev)->gen >= 8)
1854 else if (INTEL_INFO(dev)->gen >= 7)
1860 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1861 int level, bool is_sprite)
1863 if (INTEL_INFO(dev)->gen >= 8)
1864 /* BDW primary/sprite plane watermarks */
1865 return level == 0 ? 255 : 2047;
1866 else if (INTEL_INFO(dev)->gen >= 7)
1867 /* IVB/HSW primary/sprite plane watermarks */
1868 return level == 0 ? 127 : 1023;
1869 else if (!is_sprite)
1870 /* ILK/SNB primary plane watermarks */
1871 return level == 0 ? 127 : 511;
1873 /* ILK/SNB sprite plane watermarks */
1874 return level == 0 ? 63 : 255;
1877 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1880 if (INTEL_INFO(dev)->gen >= 7)
1881 return level == 0 ? 63 : 255;
1883 return level == 0 ? 31 : 63;
1886 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1888 if (INTEL_INFO(dev)->gen >= 8)
1894 /* Calculate the maximum primary/sprite plane watermark */
1895 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1897 const struct intel_wm_config *config,
1898 enum intel_ddb_partitioning ddb_partitioning,
1901 unsigned int fifo_size = ilk_display_fifo_size(dev);
1903 /* if sprites aren't enabled, sprites get nothing */
1904 if (is_sprite && !config->sprites_enabled)
1907 /* HSW allows LP1+ watermarks even with multiple pipes */
1908 if (level == 0 || config->num_pipes_active > 1) {
1909 fifo_size /= INTEL_INFO(dev)->num_pipes;
1912 * For some reason the non self refresh
1913 * FIFO size is only half of the self
1914 * refresh FIFO size on ILK/SNB.
1916 if (INTEL_INFO(dev)->gen <= 6)
1920 if (config->sprites_enabled) {
1921 /* level 0 is always calculated with 1:1 split */
1922 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1931 /* clamp to max that the registers can hold */
1932 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1935 /* Calculate the maximum cursor plane watermark */
1936 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1938 const struct intel_wm_config *config)
1940 /* HSW LP1+ watermarks w/ multiple pipes */
1941 if (level > 0 && config->num_pipes_active > 1)
1944 /* otherwise just report max that registers can hold */
1945 return ilk_cursor_wm_reg_max(dev, level);
1948 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1950 const struct intel_wm_config *config,
1951 enum intel_ddb_partitioning ddb_partitioning,
1952 struct ilk_wm_maximums *max)
1954 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1955 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1956 max->cur = ilk_cursor_wm_max(dev, level, config);
1957 max->fbc = ilk_fbc_wm_reg_max(dev);
1960 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1962 struct ilk_wm_maximums *max)
1964 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1965 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1966 max->cur = ilk_cursor_wm_reg_max(dev, level);
1967 max->fbc = ilk_fbc_wm_reg_max(dev);
1970 static bool ilk_validate_wm_level(int level,
1971 const struct ilk_wm_maximums *max,
1972 struct intel_wm_level *result)
1976 /* already determined to be invalid? */
1977 if (!result->enable)
1980 result->enable = result->pri_val <= max->pri &&
1981 result->spr_val <= max->spr &&
1982 result->cur_val <= max->cur;
1984 ret = result->enable;
1987 * HACK until we can pre-compute everything,
1988 * and thus fail gracefully if LP0 watermarks
1991 if (level == 0 && !result->enable) {
1992 if (result->pri_val > max->pri)
1993 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1994 level, result->pri_val, max->pri);
1995 if (result->spr_val > max->spr)
1996 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1997 level, result->spr_val, max->spr);
1998 if (result->cur_val > max->cur)
1999 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2000 level, result->cur_val, max->cur);
2002 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2003 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2004 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2005 result->enable = true;
2011 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2013 const struct ilk_pipe_wm_parameters *p,
2014 struct intel_wm_level *result)
2016 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2017 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2018 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2020 /* WM1+ latency values stored in 0.5us units */
2027 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2028 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2029 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2030 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2031 result->enable = true;
2035 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2037 struct drm_i915_private *dev_priv = dev->dev_private;
2038 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2039 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
2040 u32 linetime, ips_linetime;
2042 if (!intel_crtc_active(crtc))
2045 /* The WM are computed with base on how long it takes to fill a single
2046 * row at the given clock rate, multiplied by 8.
2048 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2050 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2051 intel_ddi_get_cdclk_freq(dev_priv));
2053 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2054 PIPE_WM_LINETIME_TIME(linetime);
2057 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2059 struct drm_i915_private *dev_priv = dev->dev_private;
2061 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2062 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2064 wm[0] = (sskpd >> 56) & 0xFF;
2066 wm[0] = sskpd & 0xF;
2067 wm[1] = (sskpd >> 4) & 0xFF;
2068 wm[2] = (sskpd >> 12) & 0xFF;
2069 wm[3] = (sskpd >> 20) & 0x1FF;
2070 wm[4] = (sskpd >> 32) & 0x1FF;
2071 } else if (INTEL_INFO(dev)->gen >= 6) {
2072 uint32_t sskpd = I915_READ(MCH_SSKPD);
2074 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2075 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2076 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2077 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2078 } else if (INTEL_INFO(dev)->gen >= 5) {
2079 uint32_t mltr = I915_READ(MLTR_ILK);
2081 /* ILK primary LP0 latency is 700 ns */
2083 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2084 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2088 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2090 /* ILK sprite LP0 latency is 1300 ns */
2091 if (INTEL_INFO(dev)->gen == 5)
2095 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2097 /* ILK cursor LP0 latency is 1300 ns */
2098 if (INTEL_INFO(dev)->gen == 5)
2101 /* WaDoubleCursorLP3Latency:ivb */
2102 if (IS_IVYBRIDGE(dev))
2106 int ilk_wm_max_level(const struct drm_device *dev)
2108 /* how many WM levels are we expecting */
2109 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2111 else if (INTEL_INFO(dev)->gen >= 6)
2117 static void intel_print_wm_latency(struct drm_device *dev,
2119 const uint16_t wm[5])
2121 int level, max_level = ilk_wm_max_level(dev);
2123 for (level = 0; level <= max_level; level++) {
2124 unsigned int latency = wm[level];
2127 DRM_ERROR("%s WM%d latency not provided\n",
2132 /* WM1+ latency values in 0.5us units */
2136 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2137 name, level, wm[level],
2138 latency / 10, latency % 10);
2142 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2143 uint16_t wm[5], uint16_t min)
2145 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2150 wm[0] = max(wm[0], min);
2151 for (level = 1; level <= max_level; level++)
2152 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2157 static void snb_wm_latency_quirk(struct drm_device *dev)
2159 struct drm_i915_private *dev_priv = dev->dev_private;
2163 * The BIOS provided WM memory latency values are often
2164 * inadequate for high resolution displays. Adjust them.
2166 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2167 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2168 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2173 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2174 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2175 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2176 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2179 static void ilk_setup_wm_latency(struct drm_device *dev)
2181 struct drm_i915_private *dev_priv = dev->dev_private;
2183 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2185 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2186 sizeof(dev_priv->wm.pri_latency));
2187 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2188 sizeof(dev_priv->wm.pri_latency));
2190 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2191 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2193 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2194 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2195 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2198 snb_wm_latency_quirk(dev);
2201 static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2202 struct ilk_pipe_wm_parameters *p)
2204 struct drm_device *dev = crtc->dev;
2205 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2206 enum pipe pipe = intel_crtc->pipe;
2207 struct drm_plane *plane;
2209 if (!intel_crtc_active(crtc))
2213 p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
2214 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2215 p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8;
2216 p->cur.bytes_per_pixel = 4;
2217 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2218 p->cur.horiz_pixels = intel_crtc->cursor_width;
2219 /* TODO: for now, assume primary and cursor planes are always enabled. */
2220 p->pri.enabled = true;
2221 p->cur.enabled = true;
2223 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
2224 struct intel_plane *intel_plane = to_intel_plane(plane);
2226 if (intel_plane->pipe == pipe) {
2227 p->spr = intel_plane->wm;
2233 static void ilk_compute_wm_config(struct drm_device *dev,
2234 struct intel_wm_config *config)
2236 struct intel_crtc *intel_crtc;
2238 /* Compute the currently _active_ config */
2239 for_each_intel_crtc(dev, intel_crtc) {
2240 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
2242 if (!wm->pipe_enabled)
2245 config->sprites_enabled |= wm->sprites_enabled;
2246 config->sprites_scaled |= wm->sprites_scaled;
2247 config->num_pipes_active++;
2251 /* Compute new watermarks for the pipe */
2252 static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2253 const struct ilk_pipe_wm_parameters *params,
2254 struct intel_pipe_wm *pipe_wm)
2256 struct drm_device *dev = crtc->dev;
2257 const struct drm_i915_private *dev_priv = dev->dev_private;
2258 int level, max_level = ilk_wm_max_level(dev);
2259 /* LP0 watermark maximums depend on this pipe alone */
2260 struct intel_wm_config config = {
2261 .num_pipes_active = 1,
2262 .sprites_enabled = params->spr.enabled,
2263 .sprites_scaled = params->spr.scaled,
2265 struct ilk_wm_maximums max;
2267 pipe_wm->pipe_enabled = params->active;
2268 pipe_wm->sprites_enabled = params->spr.enabled;
2269 pipe_wm->sprites_scaled = params->spr.scaled;
2271 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2272 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2275 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2276 if (params->spr.scaled)
2279 ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
2281 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2282 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2284 /* LP0 watermarks always use 1/2 DDB partitioning */
2285 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2287 /* At least LP0 must be valid */
2288 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2291 ilk_compute_wm_reg_maximums(dev, 1, &max);
2293 for (level = 1; level <= max_level; level++) {
2294 struct intel_wm_level wm = {};
2296 ilk_compute_wm_level(dev_priv, level, params, &wm);
2299 * Disable any watermark level that exceeds the
2300 * register maximums since such watermarks are
2303 if (!ilk_validate_wm_level(level, &max, &wm))
2306 pipe_wm->wm[level] = wm;
2313 * Merge the watermarks from all active pipes for a specific level.
2315 static void ilk_merge_wm_level(struct drm_device *dev,
2317 struct intel_wm_level *ret_wm)
2319 const struct intel_crtc *intel_crtc;
2321 ret_wm->enable = true;
2323 for_each_intel_crtc(dev, intel_crtc) {
2324 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2325 const struct intel_wm_level *wm = &active->wm[level];
2327 if (!active->pipe_enabled)
2331 * The watermark values may have been used in the past,
2332 * so we must maintain them in the registers for some
2333 * time even if the level is now disabled.
2336 ret_wm->enable = false;
2338 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2339 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2340 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2341 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2346 * Merge all low power watermarks for all active pipes.
2348 static void ilk_wm_merge(struct drm_device *dev,
2349 const struct intel_wm_config *config,
2350 const struct ilk_wm_maximums *max,
2351 struct intel_pipe_wm *merged)
2353 int level, max_level = ilk_wm_max_level(dev);
2354 int last_enabled_level = max_level;
2356 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2357 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2358 config->num_pipes_active > 1)
2361 /* ILK: FBC WM must be disabled always */
2362 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2364 /* merge each WM1+ level */
2365 for (level = 1; level <= max_level; level++) {
2366 struct intel_wm_level *wm = &merged->wm[level];
2368 ilk_merge_wm_level(dev, level, wm);
2370 if (level > last_enabled_level)
2372 else if (!ilk_validate_wm_level(level, max, wm))
2373 /* make sure all following levels get disabled */
2374 last_enabled_level = level - 1;
2377 * The spec says it is preferred to disable
2378 * FBC WMs instead of disabling a WM level.
2380 if (wm->fbc_val > max->fbc) {
2382 merged->fbc_wm_enabled = false;
2387 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2389 * FIXME this is racy. FBC might get enabled later.
2390 * What we should check here is whether FBC can be
2391 * enabled sometime later.
2393 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2394 for (level = 2; level <= max_level; level++) {
2395 struct intel_wm_level *wm = &merged->wm[level];
2402 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2404 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2405 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2408 /* The value we need to program into the WM_LPx latency field */
2409 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2411 struct drm_i915_private *dev_priv = dev->dev_private;
2413 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2416 return dev_priv->wm.pri_latency[level];
2419 static void ilk_compute_wm_results(struct drm_device *dev,
2420 const struct intel_pipe_wm *merged,
2421 enum intel_ddb_partitioning partitioning,
2422 struct ilk_wm_values *results)
2424 struct intel_crtc *intel_crtc;
2427 results->enable_fbc_wm = merged->fbc_wm_enabled;
2428 results->partitioning = partitioning;
2430 /* LP1+ register values */
2431 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2432 const struct intel_wm_level *r;
2434 level = ilk_wm_lp_to_level(wm_lp, merged);
2436 r = &merged->wm[level];
2439 * Maintain the watermark values even if the level is
2440 * disabled. Doing otherwise could cause underruns.
2442 results->wm_lp[wm_lp - 1] =
2443 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2444 (r->pri_val << WM1_LP_SR_SHIFT) |
2448 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2450 if (INTEL_INFO(dev)->gen >= 8)
2451 results->wm_lp[wm_lp - 1] |=
2452 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2454 results->wm_lp[wm_lp - 1] |=
2455 r->fbc_val << WM1_LP_FBC_SHIFT;
2458 * Always set WM1S_LP_EN when spr_val != 0, even if the
2459 * level is disabled. Doing otherwise could cause underruns.
2461 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2462 WARN_ON(wm_lp != 1);
2463 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2465 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2468 /* LP0 register values */
2469 for_each_intel_crtc(dev, intel_crtc) {
2470 enum pipe pipe = intel_crtc->pipe;
2471 const struct intel_wm_level *r =
2472 &intel_crtc->wm.active.wm[0];
2474 if (WARN_ON(!r->enable))
2477 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2479 results->wm_pipe[pipe] =
2480 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2481 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2486 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2487 * case both are at the same level. Prefer r1 in case they're the same. */
2488 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2489 struct intel_pipe_wm *r1,
2490 struct intel_pipe_wm *r2)
2492 int level, max_level = ilk_wm_max_level(dev);
2493 int level1 = 0, level2 = 0;
2495 for (level = 1; level <= max_level; level++) {
2496 if (r1->wm[level].enable)
2498 if (r2->wm[level].enable)
2502 if (level1 == level2) {
2503 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2507 } else if (level1 > level2) {
2514 /* dirty bits used to track which watermarks need changes */
2515 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2516 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2517 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2518 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2519 #define WM_DIRTY_FBC (1 << 24)
2520 #define WM_DIRTY_DDB (1 << 25)
2522 static unsigned int ilk_compute_wm_dirty(struct drm_device *dev,
2523 const struct ilk_wm_values *old,
2524 const struct ilk_wm_values *new)
2526 unsigned int dirty = 0;
2530 for_each_pipe(pipe) {
2531 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2532 dirty |= WM_DIRTY_LINETIME(pipe);
2533 /* Must disable LP1+ watermarks too */
2534 dirty |= WM_DIRTY_LP_ALL;
2537 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2538 dirty |= WM_DIRTY_PIPE(pipe);
2539 /* Must disable LP1+ watermarks too */
2540 dirty |= WM_DIRTY_LP_ALL;
2544 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2545 dirty |= WM_DIRTY_FBC;
2546 /* Must disable LP1+ watermarks too */
2547 dirty |= WM_DIRTY_LP_ALL;
2550 if (old->partitioning != new->partitioning) {
2551 dirty |= WM_DIRTY_DDB;
2552 /* Must disable LP1+ watermarks too */
2553 dirty |= WM_DIRTY_LP_ALL;
2556 /* LP1+ watermarks already deemed dirty, no need to continue */
2557 if (dirty & WM_DIRTY_LP_ALL)
2560 /* Find the lowest numbered LP1+ watermark in need of an update... */
2561 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2562 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2563 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2567 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2568 for (; wm_lp <= 3; wm_lp++)
2569 dirty |= WM_DIRTY_LP(wm_lp);
2574 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2577 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2578 bool changed = false;
2580 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2581 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2582 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2585 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2586 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2587 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2590 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2591 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2592 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2597 * Don't touch WM1S_LP_EN here.
2598 * Doing so could cause underruns.
2605 * The spec says we shouldn't write when we don't need, because every write
2606 * causes WMs to be re-evaluated, expending some power.
2608 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2609 struct ilk_wm_values *results)
2611 struct drm_device *dev = dev_priv->dev;
2612 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2616 dirty = ilk_compute_wm_dirty(dev, previous, results);
2620 _ilk_disable_lp_wm(dev_priv, dirty);
2622 if (dirty & WM_DIRTY_PIPE(PIPE_A))
2623 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2624 if (dirty & WM_DIRTY_PIPE(PIPE_B))
2625 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2626 if (dirty & WM_DIRTY_PIPE(PIPE_C))
2627 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2629 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2630 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2631 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2632 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2633 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2634 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2636 if (dirty & WM_DIRTY_DDB) {
2637 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2638 val = I915_READ(WM_MISC);
2639 if (results->partitioning == INTEL_DDB_PART_1_2)
2640 val &= ~WM_MISC_DATA_PARTITION_5_6;
2642 val |= WM_MISC_DATA_PARTITION_5_6;
2643 I915_WRITE(WM_MISC, val);
2645 val = I915_READ(DISP_ARB_CTL2);
2646 if (results->partitioning == INTEL_DDB_PART_1_2)
2647 val &= ~DISP_DATA_PARTITION_5_6;
2649 val |= DISP_DATA_PARTITION_5_6;
2650 I915_WRITE(DISP_ARB_CTL2, val);
2654 if (dirty & WM_DIRTY_FBC) {
2655 val = I915_READ(DISP_ARB_CTL);
2656 if (results->enable_fbc_wm)
2657 val &= ~DISP_FBC_WM_DIS;
2659 val |= DISP_FBC_WM_DIS;
2660 I915_WRITE(DISP_ARB_CTL, val);
2663 if (dirty & WM_DIRTY_LP(1) &&
2664 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2665 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2667 if (INTEL_INFO(dev)->gen >= 7) {
2668 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2669 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2670 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2671 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2674 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2675 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2676 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2677 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2678 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2679 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2681 dev_priv->wm.hw = *results;
2684 static bool ilk_disable_lp_wm(struct drm_device *dev)
2686 struct drm_i915_private *dev_priv = dev->dev_private;
2688 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2691 static void ilk_update_wm(struct drm_crtc *crtc)
2693 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2694 struct drm_device *dev = crtc->dev;
2695 struct drm_i915_private *dev_priv = dev->dev_private;
2696 struct ilk_wm_maximums max;
2697 struct ilk_pipe_wm_parameters params = {};
2698 struct ilk_wm_values results = {};
2699 enum intel_ddb_partitioning partitioning;
2700 struct intel_pipe_wm pipe_wm = {};
2701 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
2702 struct intel_wm_config config = {};
2704 ilk_compute_wm_parameters(crtc, ¶ms);
2706 intel_compute_pipe_wm(crtc, ¶ms, &pipe_wm);
2708 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2711 intel_crtc->wm.active = pipe_wm;
2713 ilk_compute_wm_config(dev, &config);
2715 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
2716 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
2718 /* 5/6 split only in single pipe config on IVB+ */
2719 if (INTEL_INFO(dev)->gen >= 7 &&
2720 config.num_pipes_active == 1 && config.sprites_enabled) {
2721 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
2722 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
2724 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
2726 best_lp_wm = &lp_wm_1_2;
2729 partitioning = (best_lp_wm == &lp_wm_1_2) ?
2730 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
2732 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
2734 ilk_write_wm_values(dev_priv, &results);
2737 static void ilk_update_sprite_wm(struct drm_plane *plane,
2738 struct drm_crtc *crtc,
2739 uint32_t sprite_width, int pixel_size,
2740 bool enabled, bool scaled)
2742 struct drm_device *dev = plane->dev;
2743 struct intel_plane *intel_plane = to_intel_plane(plane);
2745 intel_plane->wm.enabled = enabled;
2746 intel_plane->wm.scaled = scaled;
2747 intel_plane->wm.horiz_pixels = sprite_width;
2748 intel_plane->wm.bytes_per_pixel = pixel_size;
2751 * IVB workaround: must disable low power watermarks for at least
2752 * one frame before enabling scaling. LP watermarks can be re-enabled
2753 * when scaling is disabled.
2755 * WaCxSRDisabledForSpriteScaling:ivb
2757 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
2758 intel_wait_for_vblank(dev, intel_plane->pipe);
2760 ilk_update_wm(crtc);
2763 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
2765 struct drm_device *dev = crtc->dev;
2766 struct drm_i915_private *dev_priv = dev->dev_private;
2767 struct ilk_wm_values *hw = &dev_priv->wm.hw;
2768 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2769 struct intel_pipe_wm *active = &intel_crtc->wm.active;
2770 enum pipe pipe = intel_crtc->pipe;
2771 static const unsigned int wm0_pipe_reg[] = {
2772 [PIPE_A] = WM0_PIPEA_ILK,
2773 [PIPE_B] = WM0_PIPEB_ILK,
2774 [PIPE_C] = WM0_PIPEC_IVB,
2777 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
2778 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2779 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
2781 active->pipe_enabled = intel_crtc_active(crtc);
2783 if (active->pipe_enabled) {
2784 u32 tmp = hw->wm_pipe[pipe];
2787 * For active pipes LP0 watermark is marked as
2788 * enabled, and LP1+ watermaks as disabled since
2789 * we can't really reverse compute them in case
2790 * multiple pipes are active.
2792 active->wm[0].enable = true;
2793 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
2794 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
2795 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
2796 active->linetime = hw->wm_linetime[pipe];
2798 int level, max_level = ilk_wm_max_level(dev);
2801 * For inactive pipes, all watermark levels
2802 * should be marked as enabled but zeroed,
2803 * which is what we'd compute them to.
2805 for (level = 0; level <= max_level; level++)
2806 active->wm[level].enable = true;
2810 void ilk_wm_get_hw_state(struct drm_device *dev)
2812 struct drm_i915_private *dev_priv = dev->dev_private;
2813 struct ilk_wm_values *hw = &dev_priv->wm.hw;
2814 struct drm_crtc *crtc;
2816 for_each_crtc(dev, crtc)
2817 ilk_pipe_wm_get_hw_state(crtc);
2819 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
2820 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
2821 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
2823 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
2824 if (INTEL_INFO(dev)->gen >= 7) {
2825 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2826 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2829 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2830 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
2831 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2832 else if (IS_IVYBRIDGE(dev))
2833 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
2834 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2837 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2841 * intel_update_watermarks - update FIFO watermark values based on current modes
2843 * Calculate watermark values for the various WM regs based on current mode
2844 * and plane configuration.
2846 * There are several cases to deal with here:
2847 * - normal (i.e. non-self-refresh)
2848 * - self-refresh (SR) mode
2849 * - lines are large relative to FIFO size (buffer can hold up to 2)
2850 * - lines are small relative to FIFO size (buffer can hold more than 2
2851 * lines), so need to account for TLB latency
2853 * The normal calculation is:
2854 * watermark = dotclock * bytes per pixel * latency
2855 * where latency is platform & configuration dependent (we assume pessimal
2858 * The SR calculation is:
2859 * watermark = (trunc(latency/line time)+1) * surface width *
2862 * line time = htotal / dotclock
2863 * surface width = hdisplay for normal plane and 64 for cursor
2864 * and latency is assumed to be high, as above.
2866 * The final value programmed to the register should always be rounded up,
2867 * and include an extra 2 entries to account for clock crossings.
2869 * We don't use the sprite, so we can ignore that. And on Crestline we have
2870 * to set the non-SR watermarks to 8.
2872 void intel_update_watermarks(struct drm_crtc *crtc)
2874 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
2876 if (dev_priv->display.update_wm)
2877 dev_priv->display.update_wm(crtc);
2880 void intel_update_sprite_watermarks(struct drm_plane *plane,
2881 struct drm_crtc *crtc,
2882 uint32_t sprite_width, int pixel_size,
2883 bool enabled, bool scaled)
2885 struct drm_i915_private *dev_priv = plane->dev->dev_private;
2887 if (dev_priv->display.update_sprite_wm)
2888 dev_priv->display.update_sprite_wm(plane, crtc, sprite_width,
2889 pixel_size, enabled, scaled);
2892 static struct drm_i915_gem_object *
2893 intel_alloc_context_page(struct drm_device *dev)
2895 struct drm_i915_gem_object *ctx;
2898 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2900 ctx = i915_gem_alloc_object(dev, 4096);
2902 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2906 ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0);
2908 DRM_ERROR("failed to pin power context: %d\n", ret);
2912 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2914 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2921 i915_gem_object_ggtt_unpin(ctx);
2923 drm_gem_object_unreference(&ctx->base);
2928 * Lock protecting IPS related data structures
2930 DEFINE_SPINLOCK(mchdev_lock);
2932 /* Global for IPS driver to get at the current i915 device. Protected by
2934 static struct drm_i915_private *i915_mch_dev;
2936 bool ironlake_set_drps(struct drm_device *dev, u8 val)
2938 struct drm_i915_private *dev_priv = dev->dev_private;
2941 assert_spin_locked(&mchdev_lock);
2943 rgvswctl = I915_READ16(MEMSWCTL);
2944 if (rgvswctl & MEMCTL_CMD_STS) {
2945 DRM_DEBUG("gpu busy, RCS change rejected\n");
2946 return false; /* still busy with another command */
2949 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2950 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2951 I915_WRITE16(MEMSWCTL, rgvswctl);
2952 POSTING_READ16(MEMSWCTL);
2954 rgvswctl |= MEMCTL_CMD_STS;
2955 I915_WRITE16(MEMSWCTL, rgvswctl);
2960 static void ironlake_enable_drps(struct drm_device *dev)
2962 struct drm_i915_private *dev_priv = dev->dev_private;
2963 u32 rgvmodectl = I915_READ(MEMMODECTL);
2964 u8 fmax, fmin, fstart, vstart;
2966 spin_lock_irq(&mchdev_lock);
2968 /* Enable temp reporting */
2969 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2970 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2972 /* 100ms RC evaluation intervals */
2973 I915_WRITE(RCUPEI, 100000);
2974 I915_WRITE(RCDNEI, 100000);
2976 /* Set max/min thresholds to 90ms and 80ms respectively */
2977 I915_WRITE(RCBMAXAVG, 90000);
2978 I915_WRITE(RCBMINAVG, 80000);
2980 I915_WRITE(MEMIHYST, 1);
2982 /* Set up min, max, and cur for interrupt handling */
2983 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2984 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2985 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2986 MEMMODE_FSTART_SHIFT;
2988 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2991 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2992 dev_priv->ips.fstart = fstart;
2994 dev_priv->ips.max_delay = fstart;
2995 dev_priv->ips.min_delay = fmin;
2996 dev_priv->ips.cur_delay = fstart;
2998 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2999 fmax, fmin, fstart);
3001 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3004 * Interrupts will be enabled in ironlake_irq_postinstall
3007 I915_WRITE(VIDSTART, vstart);
3008 POSTING_READ(VIDSTART);
3010 rgvmodectl |= MEMMODE_SWMODE_EN;
3011 I915_WRITE(MEMMODECTL, rgvmodectl);
3013 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
3014 DRM_ERROR("stuck trying to change perf mode\n");
3017 ironlake_set_drps(dev, fstart);
3019 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
3021 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3022 dev_priv->ips.last_count2 = I915_READ(0x112f4);
3023 getrawmonotonic(&dev_priv->ips.last_time2);
3025 spin_unlock_irq(&mchdev_lock);
3028 static void ironlake_disable_drps(struct drm_device *dev)
3030 struct drm_i915_private *dev_priv = dev->dev_private;
3033 spin_lock_irq(&mchdev_lock);
3035 rgvswctl = I915_READ16(MEMSWCTL);
3037 /* Ack interrupts, disable EFC interrupt */
3038 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3039 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3040 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3041 I915_WRITE(DEIIR, DE_PCU_EVENT);
3042 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3044 /* Go back to the starting frequency */
3045 ironlake_set_drps(dev, dev_priv->ips.fstart);
3047 rgvswctl |= MEMCTL_CMD_STS;
3048 I915_WRITE(MEMSWCTL, rgvswctl);
3051 spin_unlock_irq(&mchdev_lock);
3054 /* There's a funny hw issue where the hw returns all 0 when reading from
3055 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3056 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3057 * all limits and the gpu stuck at whatever frequency it is at atm).
3059 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
3063 /* Only set the down limit when we've reached the lowest level to avoid
3064 * getting more interrupts, otherwise leave this clear. This prevents a
3065 * race in the hw when coming out of rc6: There's a tiny window where
3066 * the hw runs at the minimal clock before selecting the desired
3067 * frequency, if the down threshold expires in that window we will not
3068 * receive a down interrupt. */
3069 limits = dev_priv->rps.max_freq_softlimit << 24;
3070 if (val <= dev_priv->rps.min_freq_softlimit)
3071 limits |= dev_priv->rps.min_freq_softlimit << 16;
3076 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3080 new_power = dev_priv->rps.power;
3081 switch (dev_priv->rps.power) {
3083 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
3084 new_power = BETWEEN;
3088 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
3089 new_power = LOW_POWER;
3090 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
3091 new_power = HIGH_POWER;
3095 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
3096 new_power = BETWEEN;
3099 /* Max/min bins are special */
3100 if (val == dev_priv->rps.min_freq_softlimit)
3101 new_power = LOW_POWER;
3102 if (val == dev_priv->rps.max_freq_softlimit)
3103 new_power = HIGH_POWER;
3104 if (new_power == dev_priv->rps.power)
3107 /* Note the units here are not exactly 1us, but 1280ns. */
3108 switch (new_power) {
3110 /* Upclock if more than 95% busy over 16ms */
3111 I915_WRITE(GEN6_RP_UP_EI, 12500);
3112 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3114 /* Downclock if less than 85% busy over 32ms */
3115 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3116 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3118 I915_WRITE(GEN6_RP_CONTROL,
3119 GEN6_RP_MEDIA_TURBO |
3120 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3121 GEN6_RP_MEDIA_IS_GFX |
3123 GEN6_RP_UP_BUSY_AVG |
3124 GEN6_RP_DOWN_IDLE_AVG);
3128 /* Upclock if more than 90% busy over 13ms */
3129 I915_WRITE(GEN6_RP_UP_EI, 10250);
3130 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3132 /* Downclock if less than 75% busy over 32ms */
3133 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3134 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3136 I915_WRITE(GEN6_RP_CONTROL,
3137 GEN6_RP_MEDIA_TURBO |
3138 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3139 GEN6_RP_MEDIA_IS_GFX |
3141 GEN6_RP_UP_BUSY_AVG |
3142 GEN6_RP_DOWN_IDLE_AVG);
3146 /* Upclock if more than 85% busy over 10ms */
3147 I915_WRITE(GEN6_RP_UP_EI, 8000);
3148 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3150 /* Downclock if less than 60% busy over 32ms */
3151 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3152 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3154 I915_WRITE(GEN6_RP_CONTROL,
3155 GEN6_RP_MEDIA_TURBO |
3156 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3157 GEN6_RP_MEDIA_IS_GFX |
3159 GEN6_RP_UP_BUSY_AVG |
3160 GEN6_RP_DOWN_IDLE_AVG);
3164 dev_priv->rps.power = new_power;
3165 dev_priv->rps.last_adj = 0;
3168 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
3172 if (val > dev_priv->rps.min_freq_softlimit)
3173 mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
3174 if (val < dev_priv->rps.max_freq_softlimit)
3175 mask |= GEN6_PM_RP_UP_THRESHOLD;
3177 /* IVB and SNB hard hangs on looping batchbuffer
3178 * if GEN6_PM_UP_EI_EXPIRED is masked.
3180 if (INTEL_INFO(dev_priv->dev)->gen <= 7 && !IS_HASWELL(dev_priv->dev))
3181 mask |= GEN6_PM_RP_UP_EI_EXPIRED;
3183 if (IS_GEN8(dev_priv->dev))
3184 mask |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;
3189 /* gen6_set_rps is called to update the frequency request, but should also be
3190 * called when the range (min_delay and max_delay) is modified so that we can
3191 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
3192 void gen6_set_rps(struct drm_device *dev, u8 val)
3194 struct drm_i915_private *dev_priv = dev->dev_private;
3196 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3197 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3198 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
3200 /* min/max delay may still have been modified so be sure to
3201 * write the limits value.
3203 if (val != dev_priv->rps.cur_freq) {
3204 gen6_set_rps_thresholds(dev_priv, val);
3206 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3207 I915_WRITE(GEN6_RPNSWREQ,
3208 HSW_FREQUENCY(val));
3210 I915_WRITE(GEN6_RPNSWREQ,
3211 GEN6_FREQUENCY(val) |
3213 GEN6_AGGRESSIVE_TURBO);
3216 /* Make sure we continue to get interrupts
3217 * until we hit the minimum or maximum frequencies.
3219 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val));
3220 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
3222 POSTING_READ(GEN6_RPNSWREQ);
3224 dev_priv->rps.cur_freq = val;
3225 trace_intel_gpu_freq_change(val * 50);
3228 /* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
3230 * * If Gfx is Idle, then
3231 * 1. Mask Turbo interrupts
3232 * 2. Bring up Gfx clock
3233 * 3. Change the freq to Rpn and wait till P-Unit updates freq
3234 * 4. Clear the Force GFX CLK ON bit so that Gfx can down
3235 * 5. Unmask Turbo interrupts
3237 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
3239 struct drm_device *dev = dev_priv->dev;
3241 /* Latest VLV doesn't need to force the gfx clock */
3242 if (dev->pdev->revision >= 0xd) {
3243 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3248 * When we are idle. Drop to min voltage state.
3251 if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit)
3254 /* Mask turbo interrupt so that they will not come in between */
3255 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3257 vlv_force_gfx_clock(dev_priv, true);
3259 dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit;
3261 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ,
3262 dev_priv->rps.min_freq_softlimit);
3264 if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
3265 & GENFREQSTATUS) == 0, 5))
3266 DRM_ERROR("timed out waiting for Punit\n");
3268 vlv_force_gfx_clock(dev_priv, false);
3270 I915_WRITE(GEN6_PMINTRMSK,
3271 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
3274 void gen6_rps_idle(struct drm_i915_private *dev_priv)
3276 struct drm_device *dev = dev_priv->dev;
3278 mutex_lock(&dev_priv->rps.hw_lock);
3279 if (dev_priv->rps.enabled) {
3280 if (IS_VALLEYVIEW(dev))
3281 vlv_set_rps_idle(dev_priv);
3283 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3284 dev_priv->rps.last_adj = 0;
3286 mutex_unlock(&dev_priv->rps.hw_lock);
3289 void gen6_rps_boost(struct drm_i915_private *dev_priv)
3291 struct drm_device *dev = dev_priv->dev;
3293 mutex_lock(&dev_priv->rps.hw_lock);
3294 if (dev_priv->rps.enabled) {
3295 if (IS_VALLEYVIEW(dev))
3296 valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
3298 gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
3299 dev_priv->rps.last_adj = 0;
3301 mutex_unlock(&dev_priv->rps.hw_lock);
3304 void valleyview_set_rps(struct drm_device *dev, u8 val)
3306 struct drm_i915_private *dev_priv = dev->dev_private;
3308 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3309 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3310 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
3312 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3313 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
3314 dev_priv->rps.cur_freq,
3315 vlv_gpu_freq(dev_priv, val), val);
3317 if (val != dev_priv->rps.cur_freq)
3318 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
3320 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
3322 dev_priv->rps.cur_freq = val;
3323 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
3326 static void gen8_disable_rps_interrupts(struct drm_device *dev)
3328 struct drm_i915_private *dev_priv = dev->dev_private;
3330 I915_WRITE(GEN6_PMINTRMSK, ~GEN8_PMINTR_REDIRECT_TO_NON_DISP);
3331 I915_WRITE(GEN8_GT_IER(2), I915_READ(GEN8_GT_IER(2)) &
3332 ~dev_priv->pm_rps_events);
3333 /* Complete PM interrupt masking here doesn't race with the rps work
3334 * item again unmasking PM interrupts because that is using a different
3335 * register (GEN8_GT_IMR(2)) to mask PM interrupts. The only risk is in
3336 * leaving stale bits in GEN8_GT_IIR(2) and GEN8_GT_IMR(2) which
3337 * gen8_enable_rps will clean up. */
3339 spin_lock_irq(&dev_priv->irq_lock);
3340 dev_priv->rps.pm_iir = 0;
3341 spin_unlock_irq(&dev_priv->irq_lock);
3343 I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3346 static void gen6_disable_rps_interrupts(struct drm_device *dev)
3348 struct drm_i915_private *dev_priv = dev->dev_private;
3350 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3351 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) &
3352 ~dev_priv->pm_rps_events);
3353 /* Complete PM interrupt masking here doesn't race with the rps work
3354 * item again unmasking PM interrupts because that is using a different
3355 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3356 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3358 spin_lock_irq(&dev_priv->irq_lock);
3359 dev_priv->rps.pm_iir = 0;
3360 spin_unlock_irq(&dev_priv->irq_lock);
3362 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
3365 static void gen6_disable_rps(struct drm_device *dev)
3367 struct drm_i915_private *dev_priv = dev->dev_private;
3369 I915_WRITE(GEN6_RC_CONTROL, 0);
3370 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
3372 if (IS_BROADWELL(dev))
3373 gen8_disable_rps_interrupts(dev);
3375 gen6_disable_rps_interrupts(dev);
3378 static void cherryview_disable_rps(struct drm_device *dev)
3380 struct drm_i915_private *dev_priv = dev->dev_private;
3382 I915_WRITE(GEN6_RC_CONTROL, 0);
3385 static void valleyview_disable_rps(struct drm_device *dev)
3387 struct drm_i915_private *dev_priv = dev->dev_private;
3389 I915_WRITE(GEN6_RC_CONTROL, 0);
3391 gen6_disable_rps_interrupts(dev);
3394 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3396 if (IS_VALLEYVIEW(dev)) {
3397 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
3398 mode = GEN6_RC_CTL_RC6_ENABLE;
3402 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3403 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3404 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3405 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3408 static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
3410 /* No RC6 before Ironlake */
3411 if (INTEL_INFO(dev)->gen < 5)
3414 /* RC6 is only on Ironlake mobile not on desktop */
3415 if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev))
3418 /* Respect the kernel parameter if it is set */
3419 if (enable_rc6 >= 0) {
3422 if (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
3423 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
3426 mask = INTEL_RC6_ENABLE;
3428 if ((enable_rc6 & mask) != enable_rc6)
3429 DRM_INFO("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
3430 enable_rc6 & mask, enable_rc6, mask);
3432 return enable_rc6 & mask;
3435 /* Disable RC6 on Ironlake */
3436 if (INTEL_INFO(dev)->gen == 5)
3439 if (IS_IVYBRIDGE(dev))
3440 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3442 return INTEL_RC6_ENABLE;
3445 int intel_enable_rc6(const struct drm_device *dev)
3447 return i915.enable_rc6;
3450 static void gen8_enable_rps_interrupts(struct drm_device *dev)
3452 struct drm_i915_private *dev_priv = dev->dev_private;
3454 spin_lock_irq(&dev_priv->irq_lock);
3455 WARN_ON(dev_priv->rps.pm_iir);
3456 bdw_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
3457 I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3458 spin_unlock_irq(&dev_priv->irq_lock);
3461 static void gen6_enable_rps_interrupts(struct drm_device *dev)
3463 struct drm_i915_private *dev_priv = dev->dev_private;
3465 spin_lock_irq(&dev_priv->irq_lock);
3466 WARN_ON(dev_priv->rps.pm_iir);
3467 snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
3468 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
3469 spin_unlock_irq(&dev_priv->irq_lock);
3472 static void parse_rp_state_cap(struct drm_i915_private *dev_priv, u32 rp_state_cap)
3474 /* All of these values are in units of 50MHz */
3475 dev_priv->rps.cur_freq = 0;
3476 /* static values from HW: RP0 < RPe < RP1 < RPn (min_freq) */
3477 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
3478 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
3479 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
3480 /* XXX: only BYT has a special efficient freq */
3481 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
3482 /* hw_max = RP0 until we check for overclocking */
3483 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
3485 /* Preserve min/max settings in case of re-init */
3486 if (dev_priv->rps.max_freq_softlimit == 0)
3487 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3489 if (dev_priv->rps.min_freq_softlimit == 0)
3490 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3493 static void gen8_enable_rps(struct drm_device *dev)
3495 struct drm_i915_private *dev_priv = dev->dev_private;
3496 struct intel_engine_cs *ring;
3497 uint32_t rc6_mask = 0, rp_state_cap;
3500 /* 1a: Software RC state - RC0 */
3501 I915_WRITE(GEN6_RC_STATE, 0);
3503 /* 1c & 1d: Get forcewake during program sequence. Although the driver
3504 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
3505 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3507 /* 2a: Disable RC states. */
3508 I915_WRITE(GEN6_RC_CONTROL, 0);
3510 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3511 parse_rp_state_cap(dev_priv, rp_state_cap);
3513 /* 2b: Program RC6 thresholds.*/
3514 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3515 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3516 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3517 for_each_ring(ring, dev_priv, unused)
3518 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3519 I915_WRITE(GEN6_RC_SLEEP, 0);
3520 if (IS_BROADWELL(dev))
3521 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
3523 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
3526 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3527 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
3528 intel_print_rc6_info(dev, rc6_mask);
3529 if (IS_BROADWELL(dev))
3530 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3531 GEN7_RC_CTL_TO_MODE |
3534 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3535 GEN6_RC_CTL_EI_MODE(1) |
3538 /* 4 Program defaults and thresholds for RPS*/
3539 I915_WRITE(GEN6_RPNSWREQ,
3540 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
3541 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3542 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
3543 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
3544 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
3546 /* Docs recommend 900MHz, and 300 MHz respectively */
3547 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3548 dev_priv->rps.max_freq_softlimit << 24 |
3549 dev_priv->rps.min_freq_softlimit << 16);
3551 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
3552 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
3553 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
3554 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
3556 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3559 I915_WRITE(GEN6_RP_CONTROL,
3560 GEN6_RP_MEDIA_TURBO |
3561 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3562 GEN6_RP_MEDIA_IS_GFX |
3564 GEN6_RP_UP_BUSY_AVG |
3565 GEN6_RP_DOWN_IDLE_AVG);
3567 /* 6: Ring frequency + overclocking (our driver does this later */
3569 gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
3571 gen8_enable_rps_interrupts(dev);
3573 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3576 static void gen6_enable_rps(struct drm_device *dev)
3578 struct drm_i915_private *dev_priv = dev->dev_private;
3579 struct intel_engine_cs *ring;
3582 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
3587 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3589 /* Here begins a magic sequence of register writes to enable
3590 * auto-downclocking.
3592 * Perhaps there might be some value in exposing these to
3595 I915_WRITE(GEN6_RC_STATE, 0);
3597 /* Clear the DBG now so we don't confuse earlier errors */
3598 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3599 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3600 I915_WRITE(GTFIFODBG, gtfifodbg);
3603 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3605 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3606 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3608 parse_rp_state_cap(dev_priv, rp_state_cap);
3610 /* disable the counters and set deterministic thresholds */
3611 I915_WRITE(GEN6_RC_CONTROL, 0);
3613 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3614 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3615 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3616 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3617 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3619 for_each_ring(ring, dev_priv, i)
3620 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3622 I915_WRITE(GEN6_RC_SLEEP, 0);
3623 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3624 if (IS_IVYBRIDGE(dev))
3625 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3627 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
3628 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
3629 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3631 /* Check if we are enabling RC6 */
3632 rc6_mode = intel_enable_rc6(dev_priv->dev);
3633 if (rc6_mode & INTEL_RC6_ENABLE)
3634 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3636 /* We don't use those on Haswell */
3637 if (!IS_HASWELL(dev)) {
3638 if (rc6_mode & INTEL_RC6p_ENABLE)
3639 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
3641 if (rc6_mode & INTEL_RC6pp_ENABLE)
3642 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3645 intel_print_rc6_info(dev, rc6_mask);
3647 I915_WRITE(GEN6_RC_CONTROL,
3649 GEN6_RC_CTL_EI_MODE(1) |
3650 GEN6_RC_CTL_HW_ENABLE);
3652 /* Power down if completely idle for over 50ms */
3653 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
3654 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3656 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
3658 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
3660 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3661 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3662 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
3663 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
3664 (pcu_mbox & 0xff) * 50);
3665 dev_priv->rps.max_freq = pcu_mbox & 0xff;
3668 dev_priv->rps.power = HIGH_POWER; /* force a reset */
3669 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3671 gen6_enable_rps_interrupts(dev);
3674 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3675 if (IS_GEN6(dev) && ret) {
3676 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3677 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3678 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3679 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3680 rc6vids &= 0xffff00;
3681 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3682 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3684 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3687 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3690 static void __gen6_update_ring_freq(struct drm_device *dev)
3692 struct drm_i915_private *dev_priv = dev->dev_private;
3694 unsigned int gpu_freq;
3695 unsigned int max_ia_freq, min_ring_freq;
3696 int scaling_factor = 180;
3697 struct cpufreq_policy *policy;
3699 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3701 policy = cpufreq_cpu_get(0);
3703 max_ia_freq = policy->cpuinfo.max_freq;
3704 cpufreq_cpu_put(policy);
3707 * Default to measured freq if none found, PCU will ensure we
3710 max_ia_freq = tsc_khz;
3713 /* Convert from kHz to MHz */
3714 max_ia_freq /= 1000;
3716 min_ring_freq = I915_READ(DCLK) & 0xf;
3717 /* convert DDR frequency from units of 266.6MHz to bandwidth */
3718 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3721 * For each potential GPU frequency, load a ring frequency we'd like
3722 * to use for memory access. We do this by specifying the IA frequency
3723 * the PCU should use as a reference to determine the ring frequency.
3725 for (gpu_freq = dev_priv->rps.max_freq_softlimit; gpu_freq >= dev_priv->rps.min_freq_softlimit;
3727 int diff = dev_priv->rps.max_freq_softlimit - gpu_freq;
3728 unsigned int ia_freq = 0, ring_freq = 0;
3730 if (INTEL_INFO(dev)->gen >= 8) {
3731 /* max(2 * GT, DDR). NB: GT is 50MHz units */
3732 ring_freq = max(min_ring_freq, gpu_freq);
3733 } else if (IS_HASWELL(dev)) {
3734 ring_freq = mult_frac(gpu_freq, 5, 4);
3735 ring_freq = max(min_ring_freq, ring_freq);
3736 /* leave ia_freq as the default, chosen by cpufreq */
3738 /* On older processors, there is no separate ring
3739 * clock domain, so in order to boost the bandwidth
3740 * of the ring, we need to upclock the CPU (ia_freq).
3742 * For GPU frequencies less than 750MHz,
3743 * just use the lowest ring freq.
3745 if (gpu_freq < min_freq)
3748 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3749 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3752 sandybridge_pcode_write(dev_priv,
3753 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3754 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3755 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3760 void gen6_update_ring_freq(struct drm_device *dev)
3762 struct drm_i915_private *dev_priv = dev->dev_private;
3764 if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))
3767 mutex_lock(&dev_priv->rps.hw_lock);
3768 __gen6_update_ring_freq(dev);
3769 mutex_unlock(&dev_priv->rps.hw_lock);
3772 int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
3776 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
3777 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
3782 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3786 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
3787 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
3792 int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
3796 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
3797 rpn = (val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) & PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK;
3801 int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3805 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
3807 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3809 rp0 = min_t(u32, rp0, 0xea);
3814 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3818 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
3819 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
3820 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
3821 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3826 int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3828 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
3831 /* Check that the pctx buffer wasn't move under us. */
3832 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
3834 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
3836 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
3837 dev_priv->vlv_pctx->stolen->start);
3841 /* Check that the pcbr address is not empty. */
3842 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
3844 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
3846 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
3849 static void cherryview_setup_pctx(struct drm_device *dev)
3851 struct drm_i915_private *dev_priv = dev->dev_private;
3852 unsigned long pctx_paddr, paddr;
3853 struct i915_gtt *gtt = &dev_priv->gtt;
3855 int pctx_size = 32*1024;
3857 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3859 pcbr = I915_READ(VLV_PCBR);
3860 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
3861 paddr = (dev_priv->mm.stolen_base +
3862 (gtt->stolen_size - pctx_size));
3864 pctx_paddr = (paddr & (~4095));
3865 I915_WRITE(VLV_PCBR, pctx_paddr);
3869 static void valleyview_setup_pctx(struct drm_device *dev)
3871 struct drm_i915_private *dev_priv = dev->dev_private;
3872 struct drm_i915_gem_object *pctx;
3873 unsigned long pctx_paddr;
3875 int pctx_size = 24*1024;
3877 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3879 pcbr = I915_READ(VLV_PCBR);
3881 /* BIOS set it up already, grab the pre-alloc'd space */
3884 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3885 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3887 I915_GTT_OFFSET_NONE,
3893 * From the Gunit register HAS:
3894 * The Gfx driver is expected to program this register and ensure
3895 * proper allocation within Gfx stolen memory. For example, this
3896 * register should be programmed such than the PCBR range does not
3897 * overlap with other ranges, such as the frame buffer, protected
3898 * memory, or any other relevant ranges.
3900 pctx = i915_gem_object_create_stolen(dev, pctx_size);
3902 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3906 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
3907 I915_WRITE(VLV_PCBR, pctx_paddr);
3910 dev_priv->vlv_pctx = pctx;
3913 static void valleyview_cleanup_pctx(struct drm_device *dev)
3915 struct drm_i915_private *dev_priv = dev->dev_private;
3917 if (WARN_ON(!dev_priv->vlv_pctx))
3920 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3921 dev_priv->vlv_pctx = NULL;
3924 static void valleyview_init_gt_powersave(struct drm_device *dev)
3926 struct drm_i915_private *dev_priv = dev->dev_private;
3928 valleyview_setup_pctx(dev);
3930 mutex_lock(&dev_priv->rps.hw_lock);
3932 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
3933 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
3934 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3935 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
3936 dev_priv->rps.max_freq);
3938 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
3939 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3940 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
3941 dev_priv->rps.efficient_freq);
3943 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
3944 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3945 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
3946 dev_priv->rps.min_freq);
3948 /* Preserve min/max settings in case of re-init */
3949 if (dev_priv->rps.max_freq_softlimit == 0)
3950 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3952 if (dev_priv->rps.min_freq_softlimit == 0)
3953 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3955 mutex_unlock(&dev_priv->rps.hw_lock);
3958 static void cherryview_init_gt_powersave(struct drm_device *dev)
3960 struct drm_i915_private *dev_priv = dev->dev_private;
3962 cherryview_setup_pctx(dev);
3964 mutex_lock(&dev_priv->rps.hw_lock);
3966 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
3967 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
3968 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3969 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
3970 dev_priv->rps.max_freq);
3972 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
3973 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3974 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
3975 dev_priv->rps.efficient_freq);
3977 dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
3978 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3979 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
3980 dev_priv->rps.min_freq);
3982 /* Preserve min/max settings in case of re-init */
3983 if (dev_priv->rps.max_freq_softlimit == 0)
3984 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3986 if (dev_priv->rps.min_freq_softlimit == 0)
3987 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3989 mutex_unlock(&dev_priv->rps.hw_lock);
3992 static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
3994 valleyview_cleanup_pctx(dev);
3997 static void cherryview_enable_rps(struct drm_device *dev)
3999 struct drm_i915_private *dev_priv = dev->dev_private;
4000 struct intel_engine_cs *ring;
4001 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
4004 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4006 gtfifodbg = I915_READ(GTFIFODBG);
4008 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4010 I915_WRITE(GTFIFODBG, gtfifodbg);
4013 cherryview_check_pctx(dev_priv);
4015 /* 1a & 1b: Get forcewake during program sequence. Although the driver
4016 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4017 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4019 /* 2a: Program RC6 thresholds.*/
4020 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4021 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4022 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4024 for_each_ring(ring, dev_priv, i)
4025 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4026 I915_WRITE(GEN6_RC_SLEEP, 0);
4028 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
4030 /* allows RC6 residency counter to work */
4031 I915_WRITE(VLV_COUNTER_CONTROL,
4032 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
4033 VLV_MEDIA_RC6_COUNT_EN |
4034 VLV_RENDER_RC6_COUNT_EN));
4036 /* For now we assume BIOS is allocating and populating the PCBR */
4037 pcbr = I915_READ(VLV_PCBR);
4039 DRM_DEBUG_DRIVER("PCBR offset : 0x%x\n", pcbr);
4042 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
4043 (pcbr >> VLV_PCBR_ADDR_SHIFT))
4044 rc6_mode = GEN6_RC_CTL_EI_MODE(1);
4046 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
4048 /* 4 Program defaults and thresholds for RPS*/
4049 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4050 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4051 I915_WRITE(GEN6_RP_UP_EI, 66000);
4052 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4054 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4056 /* WaDisablePwrmtrEvent:chv (pre-production hw) */
4057 I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff);
4058 I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00);
4061 I915_WRITE(GEN6_RP_CONTROL,
4062 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4063 GEN6_RP_MEDIA_IS_GFX | /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */
4065 GEN6_RP_UP_BUSY_AVG |
4066 GEN6_RP_DOWN_IDLE_AVG);
4068 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4070 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4071 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4073 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
4074 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4075 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
4076 dev_priv->rps.cur_freq);
4078 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4079 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4080 dev_priv->rps.efficient_freq);
4082 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
4084 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4087 static void valleyview_enable_rps(struct drm_device *dev)
4089 struct drm_i915_private *dev_priv = dev->dev_private;
4090 struct intel_engine_cs *ring;
4091 u32 gtfifodbg, val, rc6_mode = 0;
4094 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4096 valleyview_check_pctx(dev_priv);
4098 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4099 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4101 I915_WRITE(GTFIFODBG, gtfifodbg);
4104 /* If VLV, Forcewake all wells, else re-direct to regular path */
4105 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4107 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4108 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4109 I915_WRITE(GEN6_RP_UP_EI, 66000);
4110 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4112 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4114 I915_WRITE(GEN6_RP_CONTROL,
4115 GEN6_RP_MEDIA_TURBO |
4116 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4117 GEN6_RP_MEDIA_IS_GFX |
4119 GEN6_RP_UP_BUSY_AVG |
4120 GEN6_RP_DOWN_IDLE_CONT);
4122 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
4123 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4124 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4126 for_each_ring(ring, dev_priv, i)
4127 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4129 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
4131 /* allows RC6 residency counter to work */
4132 I915_WRITE(VLV_COUNTER_CONTROL,
4133 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
4134 VLV_MEDIA_RC6_COUNT_EN |
4135 VLV_RENDER_RC6_COUNT_EN));
4136 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4137 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
4139 intel_print_rc6_info(dev, rc6_mode);
4141 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
4143 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4145 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4146 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4148 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
4149 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4150 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
4151 dev_priv->rps.cur_freq);
4153 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4154 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4155 dev_priv->rps.efficient_freq);
4157 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
4159 gen6_enable_rps_interrupts(dev);
4161 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4164 void ironlake_teardown_rc6(struct drm_device *dev)
4166 struct drm_i915_private *dev_priv = dev->dev_private;
4168 if (dev_priv->ips.renderctx) {
4169 i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx);
4170 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
4171 dev_priv->ips.renderctx = NULL;
4174 if (dev_priv->ips.pwrctx) {
4175 i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx);
4176 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
4177 dev_priv->ips.pwrctx = NULL;
4181 static void ironlake_disable_rc6(struct drm_device *dev)
4183 struct drm_i915_private *dev_priv = dev->dev_private;
4185 if (I915_READ(PWRCTXA)) {
4186 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
4187 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
4188 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
4191 I915_WRITE(PWRCTXA, 0);
4192 POSTING_READ(PWRCTXA);
4194 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4195 POSTING_READ(RSTDBYCTL);
4199 static int ironlake_setup_rc6(struct drm_device *dev)
4201 struct drm_i915_private *dev_priv = dev->dev_private;
4203 if (dev_priv->ips.renderctx == NULL)
4204 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
4205 if (!dev_priv->ips.renderctx)
4208 if (dev_priv->ips.pwrctx == NULL)
4209 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
4210 if (!dev_priv->ips.pwrctx) {
4211 ironlake_teardown_rc6(dev);
4218 static void ironlake_enable_rc6(struct drm_device *dev)
4220 struct drm_i915_private *dev_priv = dev->dev_private;
4221 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
4222 bool was_interruptible;
4225 /* rc6 disabled by default due to repeated reports of hanging during
4228 if (!intel_enable_rc6(dev))
4231 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4233 ret = ironlake_setup_rc6(dev);
4237 was_interruptible = dev_priv->mm.interruptible;
4238 dev_priv->mm.interruptible = false;
4241 * GPU can automatically power down the render unit if given a page
4244 ret = intel_ring_begin(ring, 6);
4246 ironlake_teardown_rc6(dev);
4247 dev_priv->mm.interruptible = was_interruptible;
4251 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
4252 intel_ring_emit(ring, MI_SET_CONTEXT);
4253 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
4255 MI_SAVE_EXT_STATE_EN |
4256 MI_RESTORE_EXT_STATE_EN |
4257 MI_RESTORE_INHIBIT);
4258 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
4259 intel_ring_emit(ring, MI_NOOP);
4260 intel_ring_emit(ring, MI_FLUSH);
4261 intel_ring_advance(ring);
4264 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4265 * does an implicit flush, combined with MI_FLUSH above, it should be
4266 * safe to assume that renderctx is valid
4268 ret = intel_ring_idle(ring);
4269 dev_priv->mm.interruptible = was_interruptible;
4271 DRM_ERROR("failed to enable ironlake power savings\n");
4272 ironlake_teardown_rc6(dev);
4276 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
4277 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4279 intel_print_rc6_info(dev, GEN6_RC_CTL_RC6_ENABLE);
4282 static unsigned long intel_pxfreq(u32 vidfreq)
4285 int div = (vidfreq & 0x3f0000) >> 16;
4286 int post = (vidfreq & 0x3000) >> 12;
4287 int pre = (vidfreq & 0x7);
4292 freq = ((div * 133333) / ((1<<post) * pre));
4297 static const struct cparams {
4303 { 1, 1333, 301, 28664 },
4304 { 1, 1066, 294, 24460 },
4305 { 1, 800, 294, 25192 },
4306 { 0, 1333, 276, 27605 },
4307 { 0, 1066, 276, 27605 },
4308 { 0, 800, 231, 23784 },
4311 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
4313 u64 total_count, diff, ret;
4314 u32 count1, count2, count3, m = 0, c = 0;
4315 unsigned long now = jiffies_to_msecs(jiffies), diff1;
4318 assert_spin_locked(&mchdev_lock);
4320 diff1 = now - dev_priv->ips.last_time1;
4322 /* Prevent division-by-zero if we are asking too fast.
4323 * Also, we don't get interesting results if we are polling
4324 * faster than once in 10ms, so just return the saved value
4328 return dev_priv->ips.chipset_power;
4330 count1 = I915_READ(DMIEC);
4331 count2 = I915_READ(DDREC);
4332 count3 = I915_READ(CSIEC);
4334 total_count = count1 + count2 + count3;
4336 /* FIXME: handle per-counter overflow */
4337 if (total_count < dev_priv->ips.last_count1) {
4338 diff = ~0UL - dev_priv->ips.last_count1;
4339 diff += total_count;
4341 diff = total_count - dev_priv->ips.last_count1;
4344 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
4345 if (cparams[i].i == dev_priv->ips.c_m &&
4346 cparams[i].t == dev_priv->ips.r_t) {
4353 diff = div_u64(diff, diff1);
4354 ret = ((m * diff) + c);
4355 ret = div_u64(ret, 10);
4357 dev_priv->ips.last_count1 = total_count;
4358 dev_priv->ips.last_time1 = now;
4360 dev_priv->ips.chipset_power = ret;
4365 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4367 struct drm_device *dev = dev_priv->dev;
4370 if (INTEL_INFO(dev)->gen != 5)
4373 spin_lock_irq(&mchdev_lock);
4375 val = __i915_chipset_val(dev_priv);
4377 spin_unlock_irq(&mchdev_lock);
4382 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4384 unsigned long m, x, b;
4387 tsfs = I915_READ(TSFS);
4389 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4390 x = I915_READ8(TR1);
4392 b = tsfs & TSFS_INTR_MASK;
4394 return ((m * x) / 127) - b;
4397 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4399 struct drm_device *dev = dev_priv->dev;
4400 static const struct v_table {
4401 u16 vd; /* in .1 mil */
4402 u16 vm; /* in .1 mil */
4533 if (INTEL_INFO(dev)->is_mobile)
4534 return v_table[pxvid].vm;
4536 return v_table[pxvid].vd;
4539 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
4541 struct timespec now, diff1;
4543 unsigned long diffms;
4546 assert_spin_locked(&mchdev_lock);
4548 getrawmonotonic(&now);
4549 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
4551 /* Don't divide by 0 */
4552 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4556 count = I915_READ(GFXEC);
4558 if (count < dev_priv->ips.last_count2) {
4559 diff = ~0UL - dev_priv->ips.last_count2;
4562 diff = count - dev_priv->ips.last_count2;
4565 dev_priv->ips.last_count2 = count;
4566 dev_priv->ips.last_time2 = now;
4568 /* More magic constants... */
4570 diff = div_u64(diff, diffms * 10);
4571 dev_priv->ips.gfx_power = diff;
4574 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4576 struct drm_device *dev = dev_priv->dev;
4578 if (INTEL_INFO(dev)->gen != 5)
4581 spin_lock_irq(&mchdev_lock);
4583 __i915_update_gfx_val(dev_priv);
4585 spin_unlock_irq(&mchdev_lock);
4588 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
4590 unsigned long t, corr, state1, corr2, state2;
4593 assert_spin_locked(&mchdev_lock);
4595 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
4596 pxvid = (pxvid >> 24) & 0x7f;
4597 ext_v = pvid_to_extvid(dev_priv, pxvid);
4601 t = i915_mch_val(dev_priv);
4603 /* Revel in the empirically derived constants */
4605 /* Correction factor in 1/100000 units */
4607 corr = ((t * 2349) + 135940);
4609 corr = ((t * 964) + 29317);
4611 corr = ((t * 301) + 1004);
4613 corr = corr * ((150142 * state1) / 10000 - 78642);
4615 corr2 = (corr * dev_priv->ips.corr);
4617 state2 = (corr2 * state1) / 10000;
4618 state2 /= 100; /* convert to mW */
4620 __i915_update_gfx_val(dev_priv);
4622 return dev_priv->ips.gfx_power + state2;
4625 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4627 struct drm_device *dev = dev_priv->dev;
4630 if (INTEL_INFO(dev)->gen != 5)
4633 spin_lock_irq(&mchdev_lock);
4635 val = __i915_gfx_val(dev_priv);
4637 spin_unlock_irq(&mchdev_lock);
4643 * i915_read_mch_val - return value for IPS use
4645 * Calculate and return a value for the IPS driver to use when deciding whether
4646 * we have thermal and power headroom to increase CPU or GPU power budget.
4648 unsigned long i915_read_mch_val(void)
4650 struct drm_i915_private *dev_priv;
4651 unsigned long chipset_val, graphics_val, ret = 0;
4653 spin_lock_irq(&mchdev_lock);
4656 dev_priv = i915_mch_dev;
4658 chipset_val = __i915_chipset_val(dev_priv);
4659 graphics_val = __i915_gfx_val(dev_priv);
4661 ret = chipset_val + graphics_val;
4664 spin_unlock_irq(&mchdev_lock);
4668 EXPORT_SYMBOL_GPL(i915_read_mch_val);
4671 * i915_gpu_raise - raise GPU frequency limit
4673 * Raise the limit; IPS indicates we have thermal headroom.
4675 bool i915_gpu_raise(void)
4677 struct drm_i915_private *dev_priv;
4680 spin_lock_irq(&mchdev_lock);
4681 if (!i915_mch_dev) {
4685 dev_priv = i915_mch_dev;
4687 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4688 dev_priv->ips.max_delay--;
4691 spin_unlock_irq(&mchdev_lock);
4695 EXPORT_SYMBOL_GPL(i915_gpu_raise);
4698 * i915_gpu_lower - lower GPU frequency limit
4700 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4701 * frequency maximum.
4703 bool i915_gpu_lower(void)
4705 struct drm_i915_private *dev_priv;
4708 spin_lock_irq(&mchdev_lock);
4709 if (!i915_mch_dev) {
4713 dev_priv = i915_mch_dev;
4715 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4716 dev_priv->ips.max_delay++;
4719 spin_unlock_irq(&mchdev_lock);
4723 EXPORT_SYMBOL_GPL(i915_gpu_lower);
4726 * i915_gpu_busy - indicate GPU business to IPS
4728 * Tell the IPS driver whether or not the GPU is busy.
4730 bool i915_gpu_busy(void)
4732 struct drm_i915_private *dev_priv;
4733 struct intel_engine_cs *ring;
4737 spin_lock_irq(&mchdev_lock);
4740 dev_priv = i915_mch_dev;
4742 for_each_ring(ring, dev_priv, i)
4743 ret |= !list_empty(&ring->request_list);
4746 spin_unlock_irq(&mchdev_lock);
4750 EXPORT_SYMBOL_GPL(i915_gpu_busy);
4753 * i915_gpu_turbo_disable - disable graphics turbo
4755 * Disable graphics turbo by resetting the max frequency and setting the
4756 * current frequency to the default.
4758 bool i915_gpu_turbo_disable(void)
4760 struct drm_i915_private *dev_priv;
4763 spin_lock_irq(&mchdev_lock);
4764 if (!i915_mch_dev) {
4768 dev_priv = i915_mch_dev;
4770 dev_priv->ips.max_delay = dev_priv->ips.fstart;
4772 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
4776 spin_unlock_irq(&mchdev_lock);
4780 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4783 * Tells the intel_ips driver that the i915 driver is now loaded, if
4784 * IPS got loaded first.
4786 * This awkward dance is so that neither module has to depend on the
4787 * other in order for IPS to do the appropriate communication of
4788 * GPU turbo limits to i915.
4791 ips_ping_for_i915_load(void)
4795 link = symbol_get(ips_link_to_i915_driver);
4798 symbol_put(ips_link_to_i915_driver);
4802 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4804 /* We only register the i915 ips part with intel-ips once everything is
4805 * set up, to avoid intel-ips sneaking in and reading bogus values. */
4806 spin_lock_irq(&mchdev_lock);
4807 i915_mch_dev = dev_priv;
4808 spin_unlock_irq(&mchdev_lock);
4810 ips_ping_for_i915_load();
4813 void intel_gpu_ips_teardown(void)
4815 spin_lock_irq(&mchdev_lock);
4816 i915_mch_dev = NULL;
4817 spin_unlock_irq(&mchdev_lock);
4820 static void intel_init_emon(struct drm_device *dev)
4822 struct drm_i915_private *dev_priv = dev->dev_private;
4827 /* Disable to program */
4831 /* Program energy weights for various events */
4832 I915_WRITE(SDEW, 0x15040d00);
4833 I915_WRITE(CSIEW0, 0x007f0000);
4834 I915_WRITE(CSIEW1, 0x1e220004);
4835 I915_WRITE(CSIEW2, 0x04000004);
4837 for (i = 0; i < 5; i++)
4838 I915_WRITE(PEW + (i * 4), 0);
4839 for (i = 0; i < 3; i++)
4840 I915_WRITE(DEW + (i * 4), 0);
4842 /* Program P-state weights to account for frequency power adjustment */
4843 for (i = 0; i < 16; i++) {
4844 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4845 unsigned long freq = intel_pxfreq(pxvidfreq);
4846 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4851 val *= (freq / 1000);
4853 val /= (127*127*900);
4855 DRM_ERROR("bad pxval: %ld\n", val);
4858 /* Render standby states get 0 weight */
4862 for (i = 0; i < 4; i++) {
4863 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4864 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4865 I915_WRITE(PXW + (i * 4), val);
4868 /* Adjust magic regs to magic values (more experimental results) */
4869 I915_WRITE(OGW0, 0);
4870 I915_WRITE(OGW1, 0);
4871 I915_WRITE(EG0, 0x00007f00);
4872 I915_WRITE(EG1, 0x0000000e);
4873 I915_WRITE(EG2, 0x000e0000);
4874 I915_WRITE(EG3, 0x68000300);
4875 I915_WRITE(EG4, 0x42000000);
4876 I915_WRITE(EG5, 0x00140031);
4880 for (i = 0; i < 8; i++)
4881 I915_WRITE(PXWL + (i * 4), 0);
4883 /* Enable PMON + select events */
4884 I915_WRITE(ECR, 0x80000019);
4886 lcfuse = I915_READ(LCFUSE02);
4888 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
4891 void intel_init_gt_powersave(struct drm_device *dev)
4893 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
4895 if (IS_CHERRYVIEW(dev))
4896 cherryview_init_gt_powersave(dev);
4897 else if (IS_VALLEYVIEW(dev))
4898 valleyview_init_gt_powersave(dev);
4901 void intel_cleanup_gt_powersave(struct drm_device *dev)
4903 if (IS_CHERRYVIEW(dev))
4905 else if (IS_VALLEYVIEW(dev))
4906 valleyview_cleanup_gt_powersave(dev);
4910 * intel_suspend_gt_powersave - suspend PM work and helper threads
4913 * We don't want to disable RC6 or other features here, we just want
4914 * to make sure any work we've queued has finished and won't bother
4915 * us while we're suspended.
4917 void intel_suspend_gt_powersave(struct drm_device *dev)
4919 struct drm_i915_private *dev_priv = dev->dev_private;
4921 /* Interrupts should be disabled already to avoid re-arming. */
4922 WARN_ON(dev->irq_enabled && !dev_priv->pm.irqs_disabled);
4924 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4926 cancel_work_sync(&dev_priv->rps.work);
4929 void intel_disable_gt_powersave(struct drm_device *dev)
4931 struct drm_i915_private *dev_priv = dev->dev_private;
4933 /* Interrupts should be disabled already to avoid re-arming. */
4934 WARN_ON(dev->irq_enabled && !dev_priv->pm.irqs_disabled);
4936 if (IS_IRONLAKE_M(dev)) {
4937 ironlake_disable_drps(dev);
4938 ironlake_disable_rc6(dev);
4939 } else if (INTEL_INFO(dev)->gen >= 6) {
4940 intel_suspend_gt_powersave(dev);
4942 mutex_lock(&dev_priv->rps.hw_lock);
4943 if (IS_CHERRYVIEW(dev))
4944 cherryview_disable_rps(dev);
4945 else if (IS_VALLEYVIEW(dev))
4946 valleyview_disable_rps(dev);
4948 gen6_disable_rps(dev);
4949 dev_priv->rps.enabled = false;
4950 mutex_unlock(&dev_priv->rps.hw_lock);
4954 static void intel_gen6_powersave_work(struct work_struct *work)
4956 struct drm_i915_private *dev_priv =
4957 container_of(work, struct drm_i915_private,
4958 rps.delayed_resume_work.work);
4959 struct drm_device *dev = dev_priv->dev;
4961 mutex_lock(&dev_priv->rps.hw_lock);
4963 if (IS_CHERRYVIEW(dev)) {
4964 cherryview_enable_rps(dev);
4965 } else if (IS_VALLEYVIEW(dev)) {
4966 valleyview_enable_rps(dev);
4967 } else if (IS_BROADWELL(dev)) {
4968 gen8_enable_rps(dev);
4969 __gen6_update_ring_freq(dev);
4971 gen6_enable_rps(dev);
4972 __gen6_update_ring_freq(dev);
4974 dev_priv->rps.enabled = true;
4975 mutex_unlock(&dev_priv->rps.hw_lock);
4977 intel_runtime_pm_put(dev_priv);
4980 void intel_enable_gt_powersave(struct drm_device *dev)
4982 struct drm_i915_private *dev_priv = dev->dev_private;
4984 if (IS_IRONLAKE_M(dev)) {
4985 mutex_lock(&dev->struct_mutex);
4986 ironlake_enable_drps(dev);
4987 ironlake_enable_rc6(dev);
4988 intel_init_emon(dev);
4989 mutex_unlock(&dev->struct_mutex);
4990 } else if (INTEL_INFO(dev)->gen >= 6) {
4992 * PCU communication is slow and this doesn't need to be
4993 * done at any specific time, so do this out of our fast path
4994 * to make resume and init faster.
4996 * We depend on the HW RC6 power context save/restore
4997 * mechanism when entering D3 through runtime PM suspend. So
4998 * disable RPM until RPS/RC6 is properly setup. We can only
4999 * get here via the driver load/system resume/runtime resume
5000 * paths, so the _noresume version is enough (and in case of
5001 * runtime resume it's necessary).
5003 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
5004 round_jiffies_up_relative(HZ)))
5005 intel_runtime_pm_get_noresume(dev_priv);
5009 void intel_reset_gt_powersave(struct drm_device *dev)
5011 struct drm_i915_private *dev_priv = dev->dev_private;
5013 dev_priv->rps.enabled = false;
5014 intel_enable_gt_powersave(dev);
5017 static void ibx_init_clock_gating(struct drm_device *dev)
5019 struct drm_i915_private *dev_priv = dev->dev_private;
5022 * On Ibex Peak and Cougar Point, we need to disable clock
5023 * gating for the panel power sequencer or it will fail to
5024 * start up when no ports are active.
5026 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
5029 static void g4x_disable_trickle_feed(struct drm_device *dev)
5031 struct drm_i915_private *dev_priv = dev->dev_private;
5034 for_each_pipe(pipe) {
5035 I915_WRITE(DSPCNTR(pipe),
5036 I915_READ(DSPCNTR(pipe)) |
5037 DISPPLANE_TRICKLE_FEED_DISABLE);
5038 intel_flush_primary_plane(dev_priv, pipe);
5042 static void ilk_init_lp_watermarks(struct drm_device *dev)
5044 struct drm_i915_private *dev_priv = dev->dev_private;
5046 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
5047 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
5048 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
5051 * Don't touch WM1S_LP_EN here.
5052 * Doing so could cause underruns.
5056 static void ironlake_init_clock_gating(struct drm_device *dev)
5058 struct drm_i915_private *dev_priv = dev->dev_private;
5059 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
5063 * WaFbcDisableDpfcClockGating:ilk
5065 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
5066 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
5067 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
5069 I915_WRITE(PCH_3DCGDIS0,
5070 MARIUNIT_CLOCK_GATE_DISABLE |
5071 SVSMUNIT_CLOCK_GATE_DISABLE);
5072 I915_WRITE(PCH_3DCGDIS1,
5073 VFMUNIT_CLOCK_GATE_DISABLE);
5076 * According to the spec the following bits should be set in
5077 * order to enable memory self-refresh
5078 * The bit 22/21 of 0x42004
5079 * The bit 5 of 0x42020
5080 * The bit 15 of 0x45000
5082 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5083 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5084 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5085 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
5086 I915_WRITE(DISP_ARB_CTL,
5087 (I915_READ(DISP_ARB_CTL) |
5090 ilk_init_lp_watermarks(dev);
5093 * Based on the document from hardware guys the following bits
5094 * should be set unconditionally in order to enable FBC.
5095 * The bit 22 of 0x42000
5096 * The bit 22 of 0x42004
5097 * The bit 7,8,9 of 0x42020.
5099 if (IS_IRONLAKE_M(dev)) {
5100 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
5101 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5102 I915_READ(ILK_DISPLAY_CHICKEN1) |
5104 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5105 I915_READ(ILK_DISPLAY_CHICKEN2) |
5109 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5111 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5112 I915_READ(ILK_DISPLAY_CHICKEN2) |
5113 ILK_ELPIN_409_SELECT);
5114 I915_WRITE(_3D_CHICKEN2,
5115 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
5116 _3D_CHICKEN2_WM_READ_PIPELINED);
5118 /* WaDisableRenderCachePipelinedFlush:ilk */
5119 I915_WRITE(CACHE_MODE_0,
5120 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5122 /* WaDisable_RenderCache_OperationalFlush:ilk */
5123 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5125 g4x_disable_trickle_feed(dev);
5127 ibx_init_clock_gating(dev);
5130 static void cpt_init_clock_gating(struct drm_device *dev)
5132 struct drm_i915_private *dev_priv = dev->dev_private;
5137 * On Ibex Peak and Cougar Point, we need to disable clock
5138 * gating for the panel power sequencer or it will fail to
5139 * start up when no ports are active.
5141 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
5142 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
5143 PCH_CPUNIT_CLOCK_GATE_DISABLE);
5144 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
5145 DPLS_EDP_PPS_FIX_DIS);
5146 /* The below fixes the weird display corruption, a few pixels shifted
5147 * downward, on (only) LVDS of some HP laptops with IVY.
5149 for_each_pipe(pipe) {
5150 val = I915_READ(TRANS_CHICKEN2(pipe));
5151 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
5152 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
5153 if (dev_priv->vbt.fdi_rx_polarity_inverted)
5154 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
5155 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
5156 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
5157 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
5158 I915_WRITE(TRANS_CHICKEN2(pipe), val);
5160 /* WADP0ClockGatingDisable */
5161 for_each_pipe(pipe) {
5162 I915_WRITE(TRANS_CHICKEN1(pipe),
5163 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5167 static void gen6_check_mch_setup(struct drm_device *dev)
5169 struct drm_i915_private *dev_priv = dev->dev_private;
5172 tmp = I915_READ(MCH_SSKPD);
5173 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
5174 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
5175 DRM_INFO("This can cause pipe underruns and display issues.\n");
5176 DRM_INFO("Please upgrade your BIOS to fix this.\n");
5180 static void gen6_init_clock_gating(struct drm_device *dev)
5182 struct drm_i915_private *dev_priv = dev->dev_private;
5183 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
5185 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5187 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5188 I915_READ(ILK_DISPLAY_CHICKEN2) |
5189 ILK_ELPIN_409_SELECT);
5191 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
5192 I915_WRITE(_3D_CHICKEN,
5193 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
5195 /* WaSetupGtModeTdRowDispatch:snb */
5196 if (IS_SNB_GT1(dev))
5197 I915_WRITE(GEN6_GT_MODE,
5198 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
5200 /* WaDisable_RenderCache_OperationalFlush:snb */
5201 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5204 * BSpec recoomends 8x4 when MSAA is used,
5205 * however in practice 16x4 seems fastest.
5207 * Note that PS/WM thread counts depend on the WIZ hashing
5208 * disable bit, which we don't touch here, but it's good
5209 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5211 I915_WRITE(GEN6_GT_MODE,
5212 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5214 ilk_init_lp_watermarks(dev);
5216 I915_WRITE(CACHE_MODE_0,
5217 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
5219 I915_WRITE(GEN6_UCGCTL1,
5220 I915_READ(GEN6_UCGCTL1) |
5221 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
5222 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5224 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5225 * gating disable must be set. Failure to set it results in
5226 * flickering pixels due to Z write ordering failures after
5227 * some amount of runtime in the Mesa "fire" demo, and Unigine
5228 * Sanctuary and Tropics, and apparently anything else with
5229 * alpha test or pixel discard.
5231 * According to the spec, bit 11 (RCCUNIT) must also be set,
5232 * but we didn't debug actual testcases to find it out.
5234 * WaDisableRCCUnitClockGating:snb
5235 * WaDisableRCPBUnitClockGating:snb
5237 I915_WRITE(GEN6_UCGCTL2,
5238 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5239 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5241 /* WaStripsFansDisableFastClipPerformanceFix:snb */
5242 I915_WRITE(_3D_CHICKEN3,
5243 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
5247 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
5248 * 3DSTATE_SF number of SF output attributes is more than 16."
5250 I915_WRITE(_3D_CHICKEN3,
5251 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
5254 * According to the spec the following bits should be
5255 * set in order to enable memory self-refresh and fbc:
5256 * The bit21 and bit22 of 0x42000
5257 * The bit21 and bit22 of 0x42004
5258 * The bit5 and bit7 of 0x42020
5259 * The bit14 of 0x70180
5260 * The bit14 of 0x71180
5262 * WaFbcAsynchFlipDisableFbcQueue:snb
5264 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5265 I915_READ(ILK_DISPLAY_CHICKEN1) |
5266 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
5267 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5268 I915_READ(ILK_DISPLAY_CHICKEN2) |
5269 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
5270 I915_WRITE(ILK_DSPCLK_GATE_D,
5271 I915_READ(ILK_DSPCLK_GATE_D) |
5272 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
5273 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
5275 g4x_disable_trickle_feed(dev);
5277 cpt_init_clock_gating(dev);
5279 gen6_check_mch_setup(dev);
5282 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
5284 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
5287 * WaVSThreadDispatchOverride:ivb,vlv
5289 * This actually overrides the dispatch
5290 * mode for all thread types.
5292 reg &= ~GEN7_FF_SCHED_MASK;
5293 reg |= GEN7_FF_TS_SCHED_HW;
5294 reg |= GEN7_FF_VS_SCHED_HW;
5295 reg |= GEN7_FF_DS_SCHED_HW;
5297 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
5300 static void lpt_init_clock_gating(struct drm_device *dev)
5302 struct drm_i915_private *dev_priv = dev->dev_private;
5305 * TODO: this bit should only be enabled when really needed, then
5306 * disabled when not needed anymore in order to save power.
5308 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
5309 I915_WRITE(SOUTH_DSPCLK_GATE_D,
5310 I915_READ(SOUTH_DSPCLK_GATE_D) |
5311 PCH_LP_PARTITION_LEVEL_DISABLE);
5313 /* WADPOClockGatingDisable:hsw */
5314 I915_WRITE(_TRANSA_CHICKEN1,
5315 I915_READ(_TRANSA_CHICKEN1) |
5316 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5319 static void lpt_suspend_hw(struct drm_device *dev)
5321 struct drm_i915_private *dev_priv = dev->dev_private;
5323 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
5324 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
5326 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
5327 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
5331 static void gen8_init_clock_gating(struct drm_device *dev)
5333 struct drm_i915_private *dev_priv = dev->dev_private;
5336 I915_WRITE(WM3_LP_ILK, 0);
5337 I915_WRITE(WM2_LP_ILK, 0);
5338 I915_WRITE(WM1_LP_ILK, 0);
5340 /* FIXME(BDW): Check all the w/a, some might only apply to
5341 * pre-production hw. */
5343 /* WaDisablePartialInstShootdown:bdw */
5344 I915_WRITE(GEN8_ROW_CHICKEN,
5345 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
5347 /* WaDisableThreadStallDopClockGating:bdw */
5348 /* FIXME: Unclear whether we really need this on production bdw. */
5349 I915_WRITE(GEN8_ROW_CHICKEN,
5350 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
5353 * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for
5354 * pre-production hardware
5356 I915_WRITE(HALF_SLICE_CHICKEN3,
5357 _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));
5358 I915_WRITE(HALF_SLICE_CHICKEN3,
5359 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
5360 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
5362 I915_WRITE(_3D_CHICKEN3,
5363 _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2));
5365 I915_WRITE(COMMON_SLICE_CHICKEN2,
5366 _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
5368 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5369 _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
5371 /* WaDisableDopClockGating:bdw May not be needed for production */
5372 I915_WRITE(GEN7_ROW_CHICKEN2,
5373 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5375 /* WaSwitchSolVfFArbitrationPriority:bdw */
5376 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5378 /* WaPsrDPAMaskVBlankInSRD:bdw */
5379 I915_WRITE(CHICKEN_PAR1_1,
5380 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
5382 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
5383 for_each_pipe(pipe) {
5384 I915_WRITE(CHICKEN_PIPESL_1(pipe),
5385 I915_READ(CHICKEN_PIPESL_1(pipe)) |
5386 BDW_DPRS_MASK_VBLANK_SRD);
5389 /* Use Force Non-Coherent whenever executing a 3D context. This is a
5390 * workaround for for a possible hang in the unlikely event a TLB
5391 * invalidation occurs during a PSD flush.
5393 I915_WRITE(HDC_CHICKEN0,
5394 I915_READ(HDC_CHICKEN0) |
5395 _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT));
5397 /* WaVSRefCountFullforceMissDisable:bdw */
5398 /* WaDSRefCountFullforceMissDisable:bdw */
5399 I915_WRITE(GEN7_FF_THREAD_MODE,
5400 I915_READ(GEN7_FF_THREAD_MODE) &
5401 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
5404 * BSpec recommends 8x4 when MSAA is used,
5405 * however in practice 16x4 seems fastest.
5407 * Note that PS/WM thread counts depend on the WIZ hashing
5408 * disable bit, which we don't touch here, but it's good
5409 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5411 I915_WRITE(GEN7_GT_MODE,
5412 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5414 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5415 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
5417 /* WaDisableSDEUnitClockGating:bdw */
5418 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5419 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5421 /* Wa4x4STCOptimizationDisable:bdw */
5422 I915_WRITE(CACHE_MODE_1,
5423 _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
5426 static void haswell_init_clock_gating(struct drm_device *dev)
5428 struct drm_i915_private *dev_priv = dev->dev_private;
5430 ilk_init_lp_watermarks(dev);
5432 /* L3 caching of data atomics doesn't work -- disable it. */
5433 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
5434 I915_WRITE(HSW_ROW_CHICKEN3,
5435 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
5437 /* This is required by WaCatErrorRejectionIssue:hsw */
5438 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5439 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5440 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5442 /* WaVSRefCountFullforceMissDisable:hsw */
5443 I915_WRITE(GEN7_FF_THREAD_MODE,
5444 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
5446 /* WaDisable_RenderCache_OperationalFlush:hsw */
5447 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5449 /* enable HiZ Raw Stall Optimization */
5450 I915_WRITE(CACHE_MODE_0_GEN7,
5451 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5453 /* WaDisable4x2SubspanOptimization:hsw */
5454 I915_WRITE(CACHE_MODE_1,
5455 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5458 * BSpec recommends 8x4 when MSAA is used,
5459 * however in practice 16x4 seems fastest.
5461 * Note that PS/WM thread counts depend on the WIZ hashing
5462 * disable bit, which we don't touch here, but it's good
5463 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5465 I915_WRITE(GEN7_GT_MODE,
5466 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5468 /* WaSwitchSolVfFArbitrationPriority:hsw */
5469 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5471 /* WaRsPkgCStateDisplayPMReq:hsw */
5472 I915_WRITE(CHICKEN_PAR1_1,
5473 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
5475 lpt_init_clock_gating(dev);
5478 static void ivybridge_init_clock_gating(struct drm_device *dev)
5480 struct drm_i915_private *dev_priv = dev->dev_private;
5483 ilk_init_lp_watermarks(dev);
5485 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
5487 /* WaDisableEarlyCull:ivb */
5488 I915_WRITE(_3D_CHICKEN3,
5489 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5491 /* WaDisableBackToBackFlipFix:ivb */
5492 I915_WRITE(IVB_CHICKEN3,
5493 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5494 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5496 /* WaDisablePSDDualDispatchEnable:ivb */
5497 if (IS_IVB_GT1(dev))
5498 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5499 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5501 /* WaDisable_RenderCache_OperationalFlush:ivb */
5502 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5504 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
5505 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5506 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5508 /* WaApplyL3ControlAndL3ChickenMode:ivb */
5509 I915_WRITE(GEN7_L3CNTLREG1,
5510 GEN7_WA_FOR_GEN7_L3_CONTROL);
5511 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5512 GEN7_WA_L3_CHICKEN_MODE);
5513 if (IS_IVB_GT1(dev))
5514 I915_WRITE(GEN7_ROW_CHICKEN2,
5515 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5517 /* must write both registers */
5518 I915_WRITE(GEN7_ROW_CHICKEN2,
5519 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5520 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5521 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5524 /* WaForceL3Serialization:ivb */
5525 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5526 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5529 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5530 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
5532 I915_WRITE(GEN6_UCGCTL2,
5533 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5535 /* This is required by WaCatErrorRejectionIssue:ivb */
5536 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5537 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5538 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5540 g4x_disable_trickle_feed(dev);
5542 gen7_setup_fixed_func_scheduler(dev_priv);
5544 if (0) { /* causes HiZ corruption on ivb:gt1 */
5545 /* enable HiZ Raw Stall Optimization */
5546 I915_WRITE(CACHE_MODE_0_GEN7,
5547 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5550 /* WaDisable4x2SubspanOptimization:ivb */
5551 I915_WRITE(CACHE_MODE_1,
5552 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5555 * BSpec recommends 8x4 when MSAA is used,
5556 * however in practice 16x4 seems fastest.
5558 * Note that PS/WM thread counts depend on the WIZ hashing
5559 * disable bit, which we don't touch here, but it's good
5560 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5562 I915_WRITE(GEN7_GT_MODE,
5563 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5565 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5566 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5567 snpcr |= GEN6_MBC_SNPCR_MED;
5568 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5570 if (!HAS_PCH_NOP(dev))
5571 cpt_init_clock_gating(dev);
5573 gen6_check_mch_setup(dev);
5576 static void valleyview_init_clock_gating(struct drm_device *dev)
5578 struct drm_i915_private *dev_priv = dev->dev_private;
5581 mutex_lock(&dev_priv->rps.hw_lock);
5582 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5583 mutex_unlock(&dev_priv->rps.hw_lock);
5584 switch ((val >> 6) & 3) {
5587 dev_priv->mem_freq = 800;
5590 dev_priv->mem_freq = 1066;
5593 dev_priv->mem_freq = 1333;
5596 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
5598 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5600 /* WaDisableEarlyCull:vlv */
5601 I915_WRITE(_3D_CHICKEN3,
5602 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5604 /* WaDisableBackToBackFlipFix:vlv */
5605 I915_WRITE(IVB_CHICKEN3,
5606 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5607 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5609 /* WaPsdDispatchEnable:vlv */
5610 /* WaDisablePSDDualDispatchEnable:vlv */
5611 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5612 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5613 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5615 /* WaDisable_RenderCache_OperationalFlush:vlv */
5616 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5618 /* WaForceL3Serialization:vlv */
5619 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5620 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5622 /* WaDisableDopClockGating:vlv */
5623 I915_WRITE(GEN7_ROW_CHICKEN2,
5624 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5626 /* This is required by WaCatErrorRejectionIssue:vlv */
5627 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5628 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5629 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5631 gen7_setup_fixed_func_scheduler(dev_priv);
5634 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5635 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
5637 I915_WRITE(GEN6_UCGCTL2,
5638 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5640 /* WaDisableL3Bank2xClockGate:vlv
5641 * Disabling L3 clock gating- MMIO 940c[25] = 1
5642 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
5643 I915_WRITE(GEN7_UCGCTL4,
5644 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
5646 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
5649 * BSpec says this must be set, even though
5650 * WaDisable4x2SubspanOptimization isn't listed for VLV.
5652 I915_WRITE(CACHE_MODE_1,
5653 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5656 * WaIncreaseL3CreditsForVLVB0:vlv
5657 * This is the hardware default actually.
5659 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
5662 * WaDisableVLVClockGating_VBIIssue:vlv
5663 * Disable clock gating on th GCFG unit to prevent a delay
5664 * in the reporting of vblank events.
5666 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
5669 static void cherryview_init_clock_gating(struct drm_device *dev)
5671 struct drm_i915_private *dev_priv = dev->dev_private;
5673 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5675 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
5677 /* WaDisablePartialInstShootdown:chv */
5678 I915_WRITE(GEN8_ROW_CHICKEN,
5679 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
5681 /* WaDisableThreadStallDopClockGating:chv */
5682 I915_WRITE(GEN8_ROW_CHICKEN,
5683 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
5685 /* WaVSRefCountFullforceMissDisable:chv */
5686 /* WaDSRefCountFullforceMissDisable:chv */
5687 I915_WRITE(GEN7_FF_THREAD_MODE,
5688 I915_READ(GEN7_FF_THREAD_MODE) &
5689 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
5691 /* WaDisableSemaphoreAndSyncFlipWait:chv */
5692 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5693 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
5695 /* WaDisableCSUnitClockGating:chv */
5696 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
5697 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5699 /* WaDisableSDEUnitClockGating:chv */
5700 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5701 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5703 /* WaDisableSamplerPowerBypass:chv (pre-production hw) */
5704 I915_WRITE(HALF_SLICE_CHICKEN3,
5705 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
5707 /* WaDisableGunitClockGating:chv (pre-production hw) */
5708 I915_WRITE(VLV_GUNIT_CLOCK_GATE, I915_READ(VLV_GUNIT_CLOCK_GATE) |
5711 /* WaDisableFfDopClockGating:chv (pre-production hw) */
5712 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5713 _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE));
5715 /* WaDisableDopClockGating:chv (pre-production hw) */
5716 I915_WRITE(GEN7_ROW_CHICKEN2,
5717 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5718 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
5719 GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
5722 static void g4x_init_clock_gating(struct drm_device *dev)
5724 struct drm_i915_private *dev_priv = dev->dev_private;
5725 uint32_t dspclk_gate;
5727 I915_WRITE(RENCLK_GATE_D1, 0);
5728 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5729 GS_UNIT_CLOCK_GATE_DISABLE |
5730 CL_UNIT_CLOCK_GATE_DISABLE);
5731 I915_WRITE(RAMCLK_GATE_D, 0);
5732 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5733 OVRUNIT_CLOCK_GATE_DISABLE |
5734 OVCUNIT_CLOCK_GATE_DISABLE;
5736 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5737 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5739 /* WaDisableRenderCachePipelinedFlush */
5740 I915_WRITE(CACHE_MODE_0,
5741 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5743 /* WaDisable_RenderCache_OperationalFlush:g4x */
5744 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5746 g4x_disable_trickle_feed(dev);
5749 static void crestline_init_clock_gating(struct drm_device *dev)
5751 struct drm_i915_private *dev_priv = dev->dev_private;
5753 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5754 I915_WRITE(RENCLK_GATE_D2, 0);
5755 I915_WRITE(DSPCLK_GATE_D, 0);
5756 I915_WRITE(RAMCLK_GATE_D, 0);
5757 I915_WRITE16(DEUC, 0);
5758 I915_WRITE(MI_ARB_STATE,
5759 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5761 /* WaDisable_RenderCache_OperationalFlush:gen4 */
5762 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5765 static void broadwater_init_clock_gating(struct drm_device *dev)
5767 struct drm_i915_private *dev_priv = dev->dev_private;
5769 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5770 I965_RCC_CLOCK_GATE_DISABLE |
5771 I965_RCPB_CLOCK_GATE_DISABLE |
5772 I965_ISC_CLOCK_GATE_DISABLE |
5773 I965_FBC_CLOCK_GATE_DISABLE);
5774 I915_WRITE(RENCLK_GATE_D2, 0);
5775 I915_WRITE(MI_ARB_STATE,
5776 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5778 /* WaDisable_RenderCache_OperationalFlush:gen4 */
5779 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5782 static void gen3_init_clock_gating(struct drm_device *dev)
5784 struct drm_i915_private *dev_priv = dev->dev_private;
5785 u32 dstate = I915_READ(D_STATE);
5787 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5788 DSTATE_DOT_CLOCK_GATING;
5789 I915_WRITE(D_STATE, dstate);
5791 if (IS_PINEVIEW(dev))
5792 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
5794 /* IIR "flip pending" means done if this bit is set */
5795 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
5797 /* interrupts should cause a wake up from C3 */
5798 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
5800 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
5801 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
5804 static void i85x_init_clock_gating(struct drm_device *dev)
5806 struct drm_i915_private *dev_priv = dev->dev_private;
5808 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5810 /* interrupts should cause a wake up from C3 */
5811 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
5812 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
5815 static void i830_init_clock_gating(struct drm_device *dev)
5817 struct drm_i915_private *dev_priv = dev->dev_private;
5819 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5822 void intel_init_clock_gating(struct drm_device *dev)
5824 struct drm_i915_private *dev_priv = dev->dev_private;
5826 dev_priv->display.init_clock_gating(dev);
5829 void intel_suspend_hw(struct drm_device *dev)
5831 if (HAS_PCH_LPT(dev))
5832 lpt_suspend_hw(dev);
5835 #define for_each_power_well(i, power_well, domain_mask, power_domains) \
5837 i < (power_domains)->power_well_count && \
5838 ((power_well) = &(power_domains)->power_wells[i]); \
5840 if ((power_well)->domains & (domain_mask))
5842 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
5843 for (i = (power_domains)->power_well_count - 1; \
5844 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
5846 if ((power_well)->domains & (domain_mask))
5849 * We should only use the power well if we explicitly asked the hardware to
5850 * enable it, so check if it's enabled and also check if we've requested it to
5853 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
5854 struct i915_power_well *power_well)
5856 return I915_READ(HSW_PWR_WELL_DRIVER) ==
5857 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
5860 bool intel_display_power_enabled_unlocked(struct drm_i915_private *dev_priv,
5861 enum intel_display_power_domain domain)
5863 struct i915_power_domains *power_domains;
5864 struct i915_power_well *power_well;
5868 if (dev_priv->pm.suspended)
5871 power_domains = &dev_priv->power_domains;
5875 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
5876 if (power_well->always_on)
5879 if (!power_well->hw_enabled) {
5888 bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
5889 enum intel_display_power_domain domain)
5891 struct i915_power_domains *power_domains;
5894 power_domains = &dev_priv->power_domains;
5896 mutex_lock(&power_domains->lock);
5897 ret = intel_display_power_enabled_unlocked(dev_priv, domain);
5898 mutex_unlock(&power_domains->lock);
5904 * Starting with Haswell, we have a "Power Down Well" that can be turned off
5905 * when not needed anymore. We have 4 registers that can request the power well
5906 * to be enabled, and it will only be disabled if none of the registers is
5907 * requesting it to be enabled.
5909 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
5911 struct drm_device *dev = dev_priv->dev;
5912 unsigned long irqflags;
5915 * After we re-enable the power well, if we touch VGA register 0x3d5
5916 * we'll get unclaimed register interrupts. This stops after we write
5917 * anything to the VGA MSR register. The vgacon module uses this
5918 * register all the time, so if we unbind our driver and, as a
5919 * consequence, bind vgacon, we'll get stuck in an infinite loop at
5920 * console_unlock(). So make here we touch the VGA MSR register, making
5921 * sure vgacon can keep working normally without triggering interrupts
5922 * and error messages.
5924 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
5925 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
5926 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
5928 if (IS_BROADWELL(dev)) {
5929 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5930 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B),
5931 dev_priv->de_irq_mask[PIPE_B]);
5932 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B),
5933 ~dev_priv->de_irq_mask[PIPE_B] |
5935 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C),
5936 dev_priv->de_irq_mask[PIPE_C]);
5937 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C),
5938 ~dev_priv->de_irq_mask[PIPE_C] |
5940 POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C));
5941 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5945 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
5946 struct i915_power_well *power_well, bool enable)
5948 bool is_enabled, enable_requested;
5951 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
5952 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5953 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
5956 if (!enable_requested)
5957 I915_WRITE(HSW_PWR_WELL_DRIVER,
5958 HSW_PWR_WELL_ENABLE_REQUEST);
5961 DRM_DEBUG_KMS("Enabling power well\n");
5962 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
5963 HSW_PWR_WELL_STATE_ENABLED), 20))
5964 DRM_ERROR("Timeout enabling power well\n");
5967 hsw_power_well_post_enable(dev_priv);
5969 if (enable_requested) {
5970 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
5971 POSTING_READ(HSW_PWR_WELL_DRIVER);
5972 DRM_DEBUG_KMS("Requesting to disable the power well\n");
5977 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
5978 struct i915_power_well *power_well)
5980 hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
5983 * We're taking over the BIOS, so clear any requests made by it since
5984 * the driver is in charge now.
5986 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
5987 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
5990 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
5991 struct i915_power_well *power_well)
5993 hsw_set_power_well(dev_priv, power_well, true);
5996 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
5997 struct i915_power_well *power_well)
5999 hsw_set_power_well(dev_priv, power_well, false);
6002 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
6003 struct i915_power_well *power_well)
6007 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
6008 struct i915_power_well *power_well)
6013 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
6014 struct i915_power_well *power_well, bool enable)
6016 enum punit_power_well power_well_id = power_well->data;
6021 mask = PUNIT_PWRGT_MASK(power_well_id);
6022 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
6023 PUNIT_PWRGT_PWR_GATE(power_well_id);
6025 mutex_lock(&dev_priv->rps.hw_lock);
6028 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
6033 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
6036 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
6038 if (wait_for(COND, 100))
6039 DRM_ERROR("timout setting power well state %08x (%08x)\n",
6041 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
6046 mutex_unlock(&dev_priv->rps.hw_lock);
6049 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
6050 struct i915_power_well *power_well)
6052 vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
6055 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
6056 struct i915_power_well *power_well)
6058 vlv_set_power_well(dev_priv, power_well, true);
6061 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
6062 struct i915_power_well *power_well)
6064 vlv_set_power_well(dev_priv, power_well, false);
6067 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
6068 struct i915_power_well *power_well)
6070 int power_well_id = power_well->data;
6071 bool enabled = false;
6076 mask = PUNIT_PWRGT_MASK(power_well_id);
6077 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
6079 mutex_lock(&dev_priv->rps.hw_lock);
6081 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
6083 * We only ever set the power-on and power-gate states, anything
6084 * else is unexpected.
6086 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
6087 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
6092 * A transient state at this point would mean some unexpected party
6093 * is poking at the power controls too.
6095 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
6096 WARN_ON(ctrl != state);
6098 mutex_unlock(&dev_priv->rps.hw_lock);
6103 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
6104 struct i915_power_well *power_well)
6106 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
6108 vlv_set_power_well(dev_priv, power_well, true);
6110 spin_lock_irq(&dev_priv->irq_lock);
6111 valleyview_enable_display_irqs(dev_priv);
6112 spin_unlock_irq(&dev_priv->irq_lock);
6115 * During driver initialization/resume we can avoid restoring the
6116 * part of the HW/SW state that will be inited anyway explicitly.
6118 if (dev_priv->power_domains.initializing)
6121 intel_hpd_init(dev_priv->dev);
6123 i915_redisable_vga_power_on(dev_priv->dev);
6126 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
6127 struct i915_power_well *power_well)
6129 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
6131 spin_lock_irq(&dev_priv->irq_lock);
6132 valleyview_disable_display_irqs(dev_priv);
6133 spin_unlock_irq(&dev_priv->irq_lock);
6135 vlv_set_power_well(dev_priv, power_well, false);
6138 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
6139 struct i915_power_well *power_well)
6141 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
6144 * Enable the CRI clock source so we can get at the
6145 * display and the reference clock for VGA
6146 * hotplug / manual detection.
6148 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
6149 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
6150 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
6152 vlv_set_power_well(dev_priv, power_well, true);
6155 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
6156 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
6157 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
6158 * b. The other bits such as sfr settings / modesel may all
6161 * This should only be done on init and resume from S3 with
6162 * both PLLs disabled, or we risk losing DPIO and PLL
6165 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
6168 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
6169 struct i915_power_well *power_well)
6171 struct drm_device *dev = dev_priv->dev;
6174 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
6177 assert_pll_disabled(dev_priv, pipe);
6179 /* Assert common reset */
6180 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
6182 vlv_set_power_well(dev_priv, power_well, false);
6185 static void check_power_well_state(struct drm_i915_private *dev_priv,
6186 struct i915_power_well *power_well)
6188 bool enabled = power_well->ops->is_enabled(dev_priv, power_well);
6190 if (power_well->always_on || !i915.disable_power_well) {
6197 if (enabled != (power_well->count > 0))
6203 WARN(1, "state mismatch for '%s' (always_on %d hw state %d use-count %d disable_power_well %d\n",
6204 power_well->name, power_well->always_on, enabled,
6205 power_well->count, i915.disable_power_well);
6208 void intel_display_power_get(struct drm_i915_private *dev_priv,
6209 enum intel_display_power_domain domain)
6211 struct i915_power_domains *power_domains;
6212 struct i915_power_well *power_well;
6215 intel_runtime_pm_get(dev_priv);
6217 power_domains = &dev_priv->power_domains;
6219 mutex_lock(&power_domains->lock);
6221 for_each_power_well(i, power_well, BIT(domain), power_domains) {
6222 if (!power_well->count++) {
6223 DRM_DEBUG_KMS("enabling %s\n", power_well->name);
6224 power_well->ops->enable(dev_priv, power_well);
6225 power_well->hw_enabled = true;
6228 check_power_well_state(dev_priv, power_well);
6231 power_domains->domain_use_count[domain]++;
6233 mutex_unlock(&power_domains->lock);
6236 void intel_display_power_put(struct drm_i915_private *dev_priv,
6237 enum intel_display_power_domain domain)
6239 struct i915_power_domains *power_domains;
6240 struct i915_power_well *power_well;
6243 power_domains = &dev_priv->power_domains;
6245 mutex_lock(&power_domains->lock);
6247 WARN_ON(!power_domains->domain_use_count[domain]);
6248 power_domains->domain_use_count[domain]--;
6250 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
6251 WARN_ON(!power_well->count);
6253 if (!--power_well->count && i915.disable_power_well) {
6254 DRM_DEBUG_KMS("disabling %s\n", power_well->name);
6255 power_well->hw_enabled = false;
6256 power_well->ops->disable(dev_priv, power_well);
6259 check_power_well_state(dev_priv, power_well);
6262 mutex_unlock(&power_domains->lock);
6264 intel_runtime_pm_put(dev_priv);
6267 static struct i915_power_domains *hsw_pwr;
6269 /* Display audio driver power well request */
6270 int i915_request_power_well(void)
6272 struct drm_i915_private *dev_priv;
6277 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6279 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
6282 EXPORT_SYMBOL_GPL(i915_request_power_well);
6284 /* Display audio driver power well release */
6285 int i915_release_power_well(void)
6287 struct drm_i915_private *dev_priv;
6292 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6294 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
6297 EXPORT_SYMBOL_GPL(i915_release_power_well);
6300 * Private interface for the audio driver to get CDCLK in kHz.
6302 * Caller must request power well using i915_request_power_well() prior to
6305 int i915_get_cdclk_freq(void)
6307 struct drm_i915_private *dev_priv;
6312 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6315 return intel_ddi_get_cdclk_freq(dev_priv);
6317 EXPORT_SYMBOL_GPL(i915_get_cdclk_freq);
6320 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
6322 #define HSW_ALWAYS_ON_POWER_DOMAINS ( \
6323 BIT(POWER_DOMAIN_PIPE_A) | \
6324 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
6325 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
6326 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
6327 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6328 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6329 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6330 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6331 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6332 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6333 BIT(POWER_DOMAIN_PORT_CRT) | \
6334 BIT(POWER_DOMAIN_INIT))
6335 #define HSW_DISPLAY_POWER_DOMAINS ( \
6336 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \
6337 BIT(POWER_DOMAIN_INIT))
6339 #define BDW_ALWAYS_ON_POWER_DOMAINS ( \
6340 HSW_ALWAYS_ON_POWER_DOMAINS | \
6341 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
6342 #define BDW_DISPLAY_POWER_DOMAINS ( \
6343 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \
6344 BIT(POWER_DOMAIN_INIT))
6346 #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT)
6347 #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
6349 #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
6350 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6351 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6352 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6353 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6354 BIT(POWER_DOMAIN_PORT_CRT) | \
6355 BIT(POWER_DOMAIN_INIT))
6357 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
6358 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6359 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6360 BIT(POWER_DOMAIN_INIT))
6362 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
6363 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6364 BIT(POWER_DOMAIN_INIT))
6366 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
6367 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6368 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6369 BIT(POWER_DOMAIN_INIT))
6371 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
6372 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6373 BIT(POWER_DOMAIN_INIT))
6375 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
6376 .sync_hw = i9xx_always_on_power_well_noop,
6377 .enable = i9xx_always_on_power_well_noop,
6378 .disable = i9xx_always_on_power_well_noop,
6379 .is_enabled = i9xx_always_on_power_well_enabled,
6382 static struct i915_power_well i9xx_always_on_power_well[] = {
6384 .name = "always-on",
6386 .domains = POWER_DOMAIN_MASK,
6387 .ops = &i9xx_always_on_power_well_ops,
6391 static const struct i915_power_well_ops hsw_power_well_ops = {
6392 .sync_hw = hsw_power_well_sync_hw,
6393 .enable = hsw_power_well_enable,
6394 .disable = hsw_power_well_disable,
6395 .is_enabled = hsw_power_well_enabled,
6398 static struct i915_power_well hsw_power_wells[] = {
6400 .name = "always-on",
6402 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
6403 .ops = &i9xx_always_on_power_well_ops,
6407 .domains = HSW_DISPLAY_POWER_DOMAINS,
6408 .ops = &hsw_power_well_ops,
6412 static struct i915_power_well bdw_power_wells[] = {
6414 .name = "always-on",
6416 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
6417 .ops = &i9xx_always_on_power_well_ops,
6421 .domains = BDW_DISPLAY_POWER_DOMAINS,
6422 .ops = &hsw_power_well_ops,
6426 static const struct i915_power_well_ops vlv_display_power_well_ops = {
6427 .sync_hw = vlv_power_well_sync_hw,
6428 .enable = vlv_display_power_well_enable,
6429 .disable = vlv_display_power_well_disable,
6430 .is_enabled = vlv_power_well_enabled,
6433 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
6434 .sync_hw = vlv_power_well_sync_hw,
6435 .enable = vlv_dpio_cmn_power_well_enable,
6436 .disable = vlv_dpio_cmn_power_well_disable,
6437 .is_enabled = vlv_power_well_enabled,
6440 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
6441 .sync_hw = vlv_power_well_sync_hw,
6442 .enable = vlv_power_well_enable,
6443 .disable = vlv_power_well_disable,
6444 .is_enabled = vlv_power_well_enabled,
6447 static struct i915_power_well vlv_power_wells[] = {
6449 .name = "always-on",
6451 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
6452 .ops = &i9xx_always_on_power_well_ops,
6456 .domains = VLV_DISPLAY_POWER_DOMAINS,
6457 .data = PUNIT_POWER_WELL_DISP2D,
6458 .ops = &vlv_display_power_well_ops,
6461 .name = "dpio-tx-b-01",
6462 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6463 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6464 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6465 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6466 .ops = &vlv_dpio_power_well_ops,
6467 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
6470 .name = "dpio-tx-b-23",
6471 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6472 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6473 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6474 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6475 .ops = &vlv_dpio_power_well_ops,
6476 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
6479 .name = "dpio-tx-c-01",
6480 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6481 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6482 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6483 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6484 .ops = &vlv_dpio_power_well_ops,
6485 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
6488 .name = "dpio-tx-c-23",
6489 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6490 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6491 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6492 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6493 .ops = &vlv_dpio_power_well_ops,
6494 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
6497 .name = "dpio-common",
6498 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
6499 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
6500 .ops = &vlv_dpio_cmn_power_well_ops,
6504 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
6505 enum punit_power_well power_well_id)
6507 struct i915_power_domains *power_domains = &dev_priv->power_domains;
6508 struct i915_power_well *power_well;
6511 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
6512 if (power_well->data == power_well_id)
6519 #define set_power_wells(power_domains, __power_wells) ({ \
6520 (power_domains)->power_wells = (__power_wells); \
6521 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
6524 int intel_power_domains_init(struct drm_i915_private *dev_priv)
6526 struct i915_power_domains *power_domains = &dev_priv->power_domains;
6528 mutex_init(&power_domains->lock);
6531 * The enabling order will be from lower to higher indexed wells,
6532 * the disabling order is reversed.
6534 if (IS_HASWELL(dev_priv->dev)) {
6535 set_power_wells(power_domains, hsw_power_wells);
6536 hsw_pwr = power_domains;
6537 } else if (IS_BROADWELL(dev_priv->dev)) {
6538 set_power_wells(power_domains, bdw_power_wells);
6539 hsw_pwr = power_domains;
6540 } else if (IS_VALLEYVIEW(dev_priv->dev)) {
6541 set_power_wells(power_domains, vlv_power_wells);
6543 set_power_wells(power_domains, i9xx_always_on_power_well);
6549 void intel_power_domains_remove(struct drm_i915_private *dev_priv)
6554 static void intel_power_domains_resume(struct drm_i915_private *dev_priv)
6556 struct i915_power_domains *power_domains = &dev_priv->power_domains;
6557 struct i915_power_well *power_well;
6560 mutex_lock(&power_domains->lock);
6561 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
6562 power_well->ops->sync_hw(dev_priv, power_well);
6563 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
6566 mutex_unlock(&power_domains->lock);
6569 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
6571 struct i915_power_well *cmn =
6572 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
6573 struct i915_power_well *disp2d =
6574 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
6576 /* nothing to do if common lane is already off */
6577 if (!cmn->ops->is_enabled(dev_priv, cmn))
6580 /* If the display might be already active skip this */
6581 if (disp2d->ops->is_enabled(dev_priv, disp2d) &&
6582 I915_READ(DPIO_CTL) & DPIO_CMNRST)
6585 DRM_DEBUG_KMS("toggling display PHY side reset\n");
6587 /* cmnlane needs DPLL registers */
6588 disp2d->ops->enable(dev_priv, disp2d);
6591 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
6592 * Need to assert and de-assert PHY SB reset by gating the
6593 * common lane power, then un-gating it.
6594 * Simply ungating isn't enough to reset the PHY enough to get
6595 * ports and lanes running.
6597 cmn->ops->disable(dev_priv, cmn);
6600 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv)
6602 struct drm_device *dev = dev_priv->dev;
6603 struct i915_power_domains *power_domains = &dev_priv->power_domains;
6605 power_domains->initializing = true;
6607 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
6608 mutex_lock(&power_domains->lock);
6609 vlv_cmnlane_wa(dev_priv);
6610 mutex_unlock(&power_domains->lock);
6613 /* For now, we need the power well to be always enabled. */
6614 intel_display_set_init_power(dev_priv, true);
6615 intel_power_domains_resume(dev_priv);
6616 power_domains->initializing = false;
6619 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
6621 intel_runtime_pm_get(dev_priv);
6624 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
6626 intel_runtime_pm_put(dev_priv);
6629 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
6631 struct drm_device *dev = dev_priv->dev;
6632 struct device *device = &dev->pdev->dev;
6634 if (!HAS_RUNTIME_PM(dev))
6637 pm_runtime_get_sync(device);
6638 WARN(dev_priv->pm.suspended, "Device still suspended.\n");
6641 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
6643 struct drm_device *dev = dev_priv->dev;
6644 struct device *device = &dev->pdev->dev;
6646 if (!HAS_RUNTIME_PM(dev))
6649 WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n");
6650 pm_runtime_get_noresume(device);
6653 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
6655 struct drm_device *dev = dev_priv->dev;
6656 struct device *device = &dev->pdev->dev;
6658 if (!HAS_RUNTIME_PM(dev))
6661 pm_runtime_mark_last_busy(device);
6662 pm_runtime_put_autosuspend(device);
6665 void intel_init_runtime_pm(struct drm_i915_private *dev_priv)
6667 struct drm_device *dev = dev_priv->dev;
6668 struct device *device = &dev->pdev->dev;
6670 if (!HAS_RUNTIME_PM(dev))
6673 pm_runtime_set_active(device);
6676 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6679 if (!intel_enable_rc6(dev)) {
6680 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6684 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
6685 pm_runtime_mark_last_busy(device);
6686 pm_runtime_use_autosuspend(device);
6688 pm_runtime_put_autosuspend(device);
6691 void intel_fini_runtime_pm(struct drm_i915_private *dev_priv)
6693 struct drm_device *dev = dev_priv->dev;
6694 struct device *device = &dev->pdev->dev;
6696 if (!HAS_RUNTIME_PM(dev))
6699 if (!intel_enable_rc6(dev))
6702 /* Make sure we're not suspended first. */
6703 pm_runtime_get_sync(device);
6704 pm_runtime_disable(device);
6707 /* Set up chip specific power management-related functions */
6708 void intel_init_pm(struct drm_device *dev)
6710 struct drm_i915_private *dev_priv = dev->dev_private;
6713 if (INTEL_INFO(dev)->gen >= 7) {
6714 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6715 dev_priv->display.enable_fbc = gen7_enable_fbc;
6716 dev_priv->display.disable_fbc = ironlake_disable_fbc;
6717 } else if (INTEL_INFO(dev)->gen >= 5) {
6718 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6719 dev_priv->display.enable_fbc = ironlake_enable_fbc;
6720 dev_priv->display.disable_fbc = ironlake_disable_fbc;
6721 } else if (IS_GM45(dev)) {
6722 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
6723 dev_priv->display.enable_fbc = g4x_enable_fbc;
6724 dev_priv->display.disable_fbc = g4x_disable_fbc;
6726 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
6727 dev_priv->display.enable_fbc = i8xx_enable_fbc;
6728 dev_priv->display.disable_fbc = i8xx_disable_fbc;
6730 /* This value was pulled out of someone's hat */
6731 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
6736 if (IS_PINEVIEW(dev))
6737 i915_pineview_get_mem_freq(dev);
6738 else if (IS_GEN5(dev))
6739 i915_ironlake_get_mem_freq(dev);
6741 /* For FIFO watermark updates */
6742 if (HAS_PCH_SPLIT(dev)) {
6743 ilk_setup_wm_latency(dev);
6745 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
6746 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
6747 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
6748 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
6749 dev_priv->display.update_wm = ilk_update_wm;
6750 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
6752 DRM_DEBUG_KMS("Failed to read display plane latency. "
6757 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
6758 else if (IS_GEN6(dev))
6759 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
6760 else if (IS_IVYBRIDGE(dev))
6761 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6762 else if (IS_HASWELL(dev))
6763 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
6764 else if (INTEL_INFO(dev)->gen == 8)
6765 dev_priv->display.init_clock_gating = gen8_init_clock_gating;
6766 } else if (IS_CHERRYVIEW(dev)) {
6767 dev_priv->display.update_wm = valleyview_update_wm;
6768 dev_priv->display.init_clock_gating =
6769 cherryview_init_clock_gating;
6770 } else if (IS_VALLEYVIEW(dev)) {
6771 dev_priv->display.update_wm = valleyview_update_wm;
6772 dev_priv->display.init_clock_gating =
6773 valleyview_init_clock_gating;
6774 } else if (IS_PINEVIEW(dev)) {
6775 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6778 dev_priv->mem_freq)) {
6779 DRM_INFO("failed to find known CxSR latency "
6780 "(found ddr%s fsb freq %d, mem freq %d), "
6782 (dev_priv->is_ddr3 == 1) ? "3" : "2",
6783 dev_priv->fsb_freq, dev_priv->mem_freq);
6784 /* Disable CxSR and never update its watermark again */
6785 pineview_disable_cxsr(dev);
6786 dev_priv->display.update_wm = NULL;
6788 dev_priv->display.update_wm = pineview_update_wm;
6789 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6790 } else if (IS_G4X(dev)) {
6791 dev_priv->display.update_wm = g4x_update_wm;
6792 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
6793 } else if (IS_GEN4(dev)) {
6794 dev_priv->display.update_wm = i965_update_wm;
6795 if (IS_CRESTLINE(dev))
6796 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
6797 else if (IS_BROADWATER(dev))
6798 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
6799 } else if (IS_GEN3(dev)) {
6800 dev_priv->display.update_wm = i9xx_update_wm;
6801 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6802 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6803 } else if (IS_GEN2(dev)) {
6804 if (INTEL_INFO(dev)->num_pipes == 1) {
6805 dev_priv->display.update_wm = i845_update_wm;
6806 dev_priv->display.get_fifo_size = i845_get_fifo_size;
6808 dev_priv->display.update_wm = i9xx_update_wm;
6809 dev_priv->display.get_fifo_size = i830_get_fifo_size;
6812 if (IS_I85X(dev) || IS_I865G(dev))
6813 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6815 dev_priv->display.init_clock_gating = i830_init_clock_gating;
6817 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
6821 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
6823 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6825 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6826 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
6830 I915_WRITE(GEN6_PCODE_DATA, *val);
6831 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6833 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6835 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
6839 *val = I915_READ(GEN6_PCODE_DATA);
6840 I915_WRITE(GEN6_PCODE_DATA, 0);
6845 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
6847 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6849 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6850 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
6854 I915_WRITE(GEN6_PCODE_DATA, val);
6855 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6857 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6859 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
6863 I915_WRITE(GEN6_PCODE_DATA, 0);
6868 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
6873 switch (dev_priv->mem_freq) {
6887 return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
6890 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
6895 switch (dev_priv->mem_freq) {
6909 return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
6912 void intel_pm_setup(struct drm_device *dev)
6914 struct drm_i915_private *dev_priv = dev->dev_private;
6916 mutex_init(&dev_priv->rps.hw_lock);
6918 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
6919 intel_gen6_powersave_work);
6921 dev_priv->pm.suspended = false;
6922 dev_priv->pm.irqs_disabled = false;