drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "../../../platform/x86/intel_ips.h"
  32 #include <linux/module.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/i915_powerwell.h>
  35 #include <linux/pm_runtime.h>
  36
  37 /**
  38  * RC6 is a special power stage which allows the GPU to enter an very
  39  * low-voltage mode when idle, using down to 0V while at this stage.  This
  40  * stage is entered automatically when the GPU is idle when RC6 support is
  41  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  42  *
  43  * There are different RC6 modes available in Intel GPU, which differentiate
  44  * among each other with the latency required to enter and leave RC6 and
  45  * voltage consumed by the GPU in different states.
  46  *
  47  * The combination of the following flags define which states GPU is allowed
  48  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  49  * RC6pp is deepest RC6. Their support by hardware varies according to the
  50  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  51  * which brings the most power savings; deeper states save more power, but
  52  * require higher latency to switch to and wake up.
  53  */
  54 #define INTEL_RC6_ENABLE                        (1<<0)
  55 #define INTEL_RC6p_ENABLE                       (1<<1)
  56 #define INTEL_RC6pp_ENABLE                      (1<<2)
  57
  58 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
  59  * framebuffer contents in-memory, aiming at reducing the required bandwidth
  60  * during in-memory transfers and, therefore, reduce the power packet.
  61  *
  62  * The benefits of FBC are mostly visible with solid backgrounds and
  63  * variation-less patterns.
  64  *
  65  * FBC-related functionality can be enabled by the means of the
  66  * i915.i915_enable_fbc parameter
  67  */
  68
  69 static void gen9_init_clock_gating(struct drm_device *dev)
  70 {
  71         struct drm_i915_private *dev_priv = dev->dev_private;
  72
  73         /*
  74          * WaDisableSDEUnitClockGating:skl
  75          * This seems to be a pre-production w/a.
  76          */
  77         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  78                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
  79
  80         /*
  81          * WaDisableDgMirrorFixInHalfSliceChicken5:skl
  82          * This is a pre-production w/a.
  83          */
  84         I915_WRITE(GEN9_HALF_SLICE_CHICKEN5,
  85                    I915_READ(GEN9_HALF_SLICE_CHICKEN5) &
  86                    ~GEN9_DG_MIRROR_FIX_ENABLE);
  87
  88         /* Wa4x4STCOptimizationDisable:skl */
  89         I915_WRITE(CACHE_MODE_1,
  90                    _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
  91 }
  92
  93 static void i8xx_disable_fbc(struct drm_device *dev)
  94 {
  95         struct drm_i915_private *dev_priv = dev->dev_private;
  96         u32 fbc_ctl;
  97
  98         /* Disable compression */
  99         fbc_ctl = I915_READ(FBC_CONTROL);
 100         if ((fbc_ctl & FBC_CTL_EN) == 0)
 101                 return;
 102
 103         fbc_ctl &= ~FBC_CTL_EN;
 104         I915_WRITE(FBC_CONTROL, fbc_ctl);
 105
 106         /* Wait for compressing bit to clear */
 107         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
 108                 DRM_DEBUG_KMS("FBC idle timed out\n");
 109                 return;
 110         }
 111
 112         DRM_DEBUG_KMS("disabled FBC\n");
 113 }
 114
 115 static void i8xx_enable_fbc(struct drm_crtc *crtc)
 116 {
 117         struct drm_device *dev = crtc->dev;
 118         struct drm_i915_private *dev_priv = dev->dev_private;
 119         struct drm_framebuffer *fb = crtc->primary->fb;
 120         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 121         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 122         int cfb_pitch;
 123         int i;
 124         u32 fbc_ctl;
 125
 126         cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
 127         if (fb->pitches[0] < cfb_pitch)
 128                 cfb_pitch = fb->pitches[0];
 129
 130         /* FBC_CTL wants 32B or 64B units */
 131         if (IS_GEN2(dev))
 132                 cfb_pitch = (cfb_pitch / 32) - 1;
 133         else
 134                 cfb_pitch = (cfb_pitch / 64) - 1;
 135
 136         /* Clear old tags */
 137         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 138                 I915_WRITE(FBC_TAG + (i * 4), 0);
 139
 140         if (IS_GEN4(dev)) {
 141                 u32 fbc_ctl2;
 142
 143                 /* Set it up... */
 144                 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
 145                 fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane);
 146                 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 147                 I915_WRITE(FBC_FENCE_OFF, crtc->y);
 148         }
 149
 150         /* enable it... */
 151         fbc_ctl = I915_READ(FBC_CONTROL);
 152         fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
 153         fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
 154         if (IS_I945GM(dev))
 155                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 156         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 157         fbc_ctl |= obj->fence_reg;
 158         I915_WRITE(FBC_CONTROL, fbc_ctl);
 159
 160         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
 161                       cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
 162 }
 163
 164 static bool i8xx_fbc_enabled(struct drm_device *dev)
 165 {
 166         struct drm_i915_private *dev_priv = dev->dev_private;
 167
 168         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
 169 }
 170
 171 static void g4x_enable_fbc(struct drm_crtc *crtc)
 172 {
 173         struct drm_device *dev = crtc->dev;
 174         struct drm_i915_private *dev_priv = dev->dev_private;
 175         struct drm_framebuffer *fb = crtc->primary->fb;
 176         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 177         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 178         u32 dpfc_ctl;
 179
 180         dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN;
 181         if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
 182                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 183         else
 184                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 185         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
 186
 187         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
 188
 189         /* enable it... */
 190         I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 191
 192         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 193 }
 194
 195 static void g4x_disable_fbc(struct drm_device *dev)
 196 {
 197         struct drm_i915_private *dev_priv = dev->dev_private;
 198         u32 dpfc_ctl;
 199
 200         /* Disable compression */
 201         dpfc_ctl = I915_READ(DPFC_CONTROL);
 202         if (dpfc_ctl & DPFC_CTL_EN) {
 203                 dpfc_ctl &= ~DPFC_CTL_EN;
 204                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
 205
 206                 DRM_DEBUG_KMS("disabled FBC\n");
 207         }
 208 }
 209
 210 static bool g4x_fbc_enabled(struct drm_device *dev)
 211 {
 212         struct drm_i915_private *dev_priv = dev->dev_private;
 213
 214         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
 215 }
 216
 217 static void sandybridge_blit_fbc_update(struct drm_device *dev)
 218 {
 219         struct drm_i915_private *dev_priv = dev->dev_private;
 220         u32 blt_ecoskpd;
 221
 222         /* Make sure blitter notifies FBC of writes */
 223
 224         /* Blitter is part of Media powerwell on VLV. No impact of
 225          * his param in other platforms for now */
 226         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
 227
 228         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
 229         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
 230                 GEN6_BLITTER_LOCK_SHIFT;
 231         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 232         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
 233         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 234         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
 235                          GEN6_BLITTER_LOCK_SHIFT);
 236         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 237         POSTING_READ(GEN6_BLITTER_ECOSKPD);
 238
 239         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
 240 }
 241
 242 static void ironlake_enable_fbc(struct drm_crtc *crtc)
 243 {
 244         struct drm_device *dev = crtc->dev;
 245         struct drm_i915_private *dev_priv = dev->dev_private;
 246         struct drm_framebuffer *fb = crtc->primary->fb;
 247         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 248         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 249         u32 dpfc_ctl;
 250
 251         dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane);
 252         if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
 253                 dev_priv->fbc.threshold++;
 254
 255         switch (dev_priv->fbc.threshold) {
 256         case 4:
 257         case 3:
 258                 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
 259                 break;
 260         case 2:
 261                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 262                 break;
 263         case 1:
 264                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 265                 break;
 266         }
 267         dpfc_ctl |= DPFC_CTL_FENCE_EN;
 268         if (IS_GEN5(dev))
 269                 dpfc_ctl |= obj->fence_reg;
 270
 271         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
 272         I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
 273         /* enable it... */
 274         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 275
 276         if (IS_GEN6(dev)) {
 277                 I915_WRITE(SNB_DPFC_CTL_SA,
 278                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 279                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
 280                 sandybridge_blit_fbc_update(dev);
 281         }
 282
 283         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 284 }
 285
 286 static void ironlake_disable_fbc(struct drm_device *dev)
 287 {
 288         struct drm_i915_private *dev_priv = dev->dev_private;
 289         u32 dpfc_ctl;
 290
 291         /* Disable compression */
 292         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 293         if (dpfc_ctl & DPFC_CTL_EN) {
 294                 dpfc_ctl &= ~DPFC_CTL_EN;
 295                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
 296
 297                 DRM_DEBUG_KMS("disabled FBC\n");
 298         }
 299 }
 300
 301 static bool ironlake_fbc_enabled(struct drm_device *dev)
 302 {
 303         struct drm_i915_private *dev_priv = dev->dev_private;
 304
 305         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 306 }
 307
 308 static void gen7_enable_fbc(struct drm_crtc *crtc)
 309 {
 310         struct drm_device *dev = crtc->dev;
 311         struct drm_i915_private *dev_priv = dev->dev_private;
 312         struct drm_framebuffer *fb = crtc->primary->fb;
 313         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 314         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 315         u32 dpfc_ctl;
 316
 317         dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane);
 318         if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
 319                 dev_priv->fbc.threshold++;
 320
 321         switch (dev_priv->fbc.threshold) {
 322         case 4:
 323         case 3:
 324                 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
 325                 break;
 326         case 2:
 327                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 328                 break;
 329         case 1:
 330                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 331                 break;
 332         }
 333
 334         dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
 335
 336         if (dev_priv->fbc.false_color)
 337                 dpfc_ctl |= FBC_CTL_FALSE_COLOR;
 338
 339         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 340
 341         if (IS_IVYBRIDGE(dev)) {
 342                 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
 343                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
 344                            I915_READ(ILK_DISPLAY_CHICKEN1) |
 345                            ILK_FBCQ_DIS);
 346         } else {
 347                 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
 348                 I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe),
 349                            I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) |
 350                            HSW_FBCQ_DIS);
 351         }
 352
 353         I915_WRITE(SNB_DPFC_CTL_SA,
 354                    SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 355         I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
 356
 357         sandybridge_blit_fbc_update(dev);
 358
 359         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 360 }
 361
 362 bool intel_fbc_enabled(struct drm_device *dev)
 363 {
 364         struct drm_i915_private *dev_priv = dev->dev_private;
 365
 366         if (!dev_priv->display.fbc_enabled)
 367                 return false;
 368
 369         return dev_priv->display.fbc_enabled(dev);
 370 }
 371
 372 void gen8_fbc_sw_flush(struct drm_device *dev, u32 value)
 373 {
 374         struct drm_i915_private *dev_priv = dev->dev_private;
 375
 376         if (!IS_GEN8(dev))
 377                 return;
 378
 379         I915_WRITE(MSG_FBC_REND_STATE, value);
 380 }
 381
 382 static void intel_fbc_work_fn(struct work_struct *__work)
 383 {
 384         struct intel_fbc_work *work =
 385                 container_of(to_delayed_work(__work),
 386                              struct intel_fbc_work, work);
 387         struct drm_device *dev = work->crtc->dev;
 388         struct drm_i915_private *dev_priv = dev->dev_private;
 389
 390         mutex_lock(&dev->struct_mutex);
 391         if (work == dev_priv->fbc.fbc_work) {
 392                 /* Double check that we haven't switched fb without cancelling
 393                  * the prior work.
 394                  */
 395                 if (work->crtc->primary->fb == work->fb) {
 396                         dev_priv->display.enable_fbc(work->crtc);
 397
 398                         dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
 399                         dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id;
 400                         dev_priv->fbc.y = work->crtc->y;
 401                 }
 402
 403                 dev_priv->fbc.fbc_work = NULL;
 404         }
 405         mutex_unlock(&dev->struct_mutex);
 406
 407         kfree(work);
 408 }
 409
 410 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
 411 {
 412         if (dev_priv->fbc.fbc_work == NULL)
 413                 return;
 414
 415         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
 416
 417         /* Synchronisation is provided by struct_mutex and checking of
 418          * dev_priv->fbc.fbc_work, so we can perform the cancellation
 419          * entirely asynchronously.
 420          */
 421         if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
 422                 /* tasklet was killed before being run, clean up */
 423                 kfree(dev_priv->fbc.fbc_work);
 424
 425         /* Mark the work as no longer wanted so that if it does
 426          * wake-up (because the work was already running and waiting
 427          * for our mutex), it will discover that is no longer
 428          * necessary to run.
 429          */
 430         dev_priv->fbc.fbc_work = NULL;
 431 }
 432
 433 static void intel_enable_fbc(struct drm_crtc *crtc)
 434 {
 435         struct intel_fbc_work *work;
 436         struct drm_device *dev = crtc->dev;
 437         struct drm_i915_private *dev_priv = dev->dev_private;
 438
 439         if (!dev_priv->display.enable_fbc)
 440                 return;
 441
 442         intel_cancel_fbc_work(dev_priv);
 443
 444         work = kzalloc(sizeof(*work), GFP_KERNEL);
 445         if (work == NULL) {
 446                 DRM_ERROR("Failed to allocate FBC work structure\n");
 447                 dev_priv->display.enable_fbc(crtc);
 448                 return;
 449         }
 450
 451         work->crtc = crtc;
 452         work->fb = crtc->primary->fb;
 453         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
 454
 455         dev_priv->fbc.fbc_work = work;
 456
 457         /* Delay the actual enabling to let pageflipping cease and the
 458          * display to settle before starting the compression. Note that
 459          * this delay also serves a second purpose: it allows for a
 460          * vblank to pass after disabling the FBC before we attempt
 461          * to modify the control registers.
 462          *
 463          * A more complicated solution would involve tracking vblanks
 464          * following the termination of the page-flipping sequence
 465          * and indeed performing the enable as a co-routine and not
 466          * waiting synchronously upon the vblank.
 467          *
 468          * WaFbcWaitForVBlankBeforeEnable:ilk,snb
 469          */
 470         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
 471 }
 472
 473 void intel_disable_fbc(struct drm_device *dev)
 474 {
 475         struct drm_i915_private *dev_priv = dev->dev_private;
 476
 477         intel_cancel_fbc_work(dev_priv);
 478
 479         if (!dev_priv->display.disable_fbc)
 480                 return;
 481
 482         dev_priv->display.disable_fbc(dev);
 483         dev_priv->fbc.plane = -1;
 484 }
 485
 486 static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
 487                               enum no_fbc_reason reason)
 488 {
 489         if (dev_priv->fbc.no_fbc_reason == reason)
 490                 return false;
 491
 492         dev_priv->fbc.no_fbc_reason = reason;
 493         return true;
 494 }
 495
 496 /**
 497  * intel_update_fbc - enable/disable FBC as needed
 498  * @dev: the drm_device
 499  *
 500  * Set up the framebuffer compression hardware at mode set time.  We
 501  * enable it if possible:
 502  *   - plane A only (on pre-965)
 503  *   - no pixel mulitply/line duplication
 504  *   - no alpha buffer discard
 505  *   - no dual wide
 506  *   - framebuffer <= max_hdisplay in width, max_vdisplay in height
 507  *
 508  * We can't assume that any compression will take place (worst case),
 509  * so the compressed buffer has to be the same size as the uncompressed
 510  * one.  It also must reside (along with the line length buffer) in
 511  * stolen memory.
 512  *
 513  * We need to enable/disable FBC on a global basis.
 514  */
 515 void intel_update_fbc(struct drm_device *dev)
 516 {
 517         struct drm_i915_private *dev_priv = dev->dev_private;
 518         struct drm_crtc *crtc = NULL, *tmp_crtc;
 519         struct intel_crtc *intel_crtc;
 520         struct drm_framebuffer *fb;
 521         struct drm_i915_gem_object *obj;
 522         const struct drm_display_mode *adjusted_mode;
 523         unsigned int max_width, max_height;
 524
 525         if (!HAS_FBC(dev)) {
 526                 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
 527                 return;
 528         }
 529
 530         if (!i915.powersave) {
 531                 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
 532                         DRM_DEBUG_KMS("fbc disabled per module param\n");
 533                 return;
 534         }
 535
 536         /*
 537          * If FBC is already on, we just have to verify that we can
 538          * keep it that way...
 539          * Need to disable if:
 540          *   - more than one pipe is active
 541          *   - changing FBC params (stride, fence, mode)
 542          *   - new fb is too large to fit in compressed buffer
 543          *   - going to an unsupported config (interlace, pixel multiply, etc.)
 544          */
 545         for_each_crtc(dev, tmp_crtc) {
 546                 if (intel_crtc_active(tmp_crtc) &&
 547                     to_intel_crtc(tmp_crtc)->primary_enabled) {
 548                         if (crtc) {
 549                                 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
 550                                         DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
 551                                 goto out_disable;
 552                         }
 553                         crtc = tmp_crtc;
 554                 }
 555         }
 556
 557         if (!crtc || crtc->primary->fb == NULL) {
 558                 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
 559                         DRM_DEBUG_KMS("no output, disabling\n");
 560                 goto out_disable;
 561         }
 562
 563         intel_crtc = to_intel_crtc(crtc);
 564         fb = crtc->primary->fb;
 565         obj = intel_fb_obj(fb);
 566         adjusted_mode = &intel_crtc->config.adjusted_mode;
 567
 568         if (i915.enable_fbc < 0) {
 569                 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
 570                         DRM_DEBUG_KMS("disabled per chip default\n");
 571                 goto out_disable;
 572         }
 573         if (!i915.enable_fbc) {
 574                 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
 575                         DRM_DEBUG_KMS("fbc disabled per module param\n");
 576                 goto out_disable;
 577         }
 578         if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
 579             (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
 580                 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
 581                         DRM_DEBUG_KMS("mode incompatible with compression, "
 582                                       "disabling\n");
 583                 goto out_disable;
 584         }
 585
 586         if (INTEL_INFO(dev)->gen >= 8 || IS_HASWELL(dev)) {
 587                 max_width = 4096;
 588                 max_height = 4096;
 589         } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 590                 max_width = 4096;
 591                 max_height = 2048;
 592         } else {
 593                 max_width = 2048;
 594                 max_height = 1536;
 595         }
 596         if (intel_crtc->config.pipe_src_w > max_width ||
 597             intel_crtc->config.pipe_src_h > max_height) {
 598                 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
 599                         DRM_DEBUG_KMS("mode too large for compression, disabling\n");
 600                 goto out_disable;
 601         }
 602         if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) &&
 603             intel_crtc->plane != PLANE_A) {
 604                 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
 605                         DRM_DEBUG_KMS("plane not A, disabling compression\n");
 606                 goto out_disable;
 607         }
 608
 609         /* The use of a CPU fence is mandatory in order to detect writes
 610          * by the CPU to the scanout and trigger updates to the FBC.
 611          */
 612         if (obj->tiling_mode != I915_TILING_X ||
 613             obj->fence_reg == I915_FENCE_REG_NONE) {
 614                 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
 615                         DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
 616                 goto out_disable;
 617         }
 618         if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
 619             to_intel_plane(crtc->primary)->rotation != BIT(DRM_ROTATE_0)) {
 620                 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
 621                         DRM_DEBUG_KMS("Rotation unsupported, disabling\n");
 622                 goto out_disable;
 623         }
 624
 625         /* If the kernel debugger is active, always disable compression */
 626         if (in_dbg_master())
 627                 goto out_disable;
 628
 629         if (i915_gem_stolen_setup_compression(dev, obj->base.size,
 630                                               drm_format_plane_cpp(fb->pixel_format, 0))) {
 631                 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
 632                         DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
 633                 goto out_disable;
 634         }
 635
 636         /* If the scanout has not changed, don't modify the FBC settings.
 637          * Note that we make the fundamental assumption that the fb->obj
 638          * cannot be unpinned (and have its GTT offset and fence revoked)
 639          * without first being decoupled from the scanout and FBC disabled.
 640          */
 641         if (dev_priv->fbc.plane == intel_crtc->plane &&
 642             dev_priv->fbc.fb_id == fb->base.id &&
 643             dev_priv->fbc.y == crtc->y)
 644                 return;
 645
 646         if (intel_fbc_enabled(dev)) {
 647                 /* We update FBC along two paths, after changing fb/crtc
 648                  * configuration (modeswitching) and after page-flipping
 649                  * finishes. For the latter, we know that not only did
 650                  * we disable the FBC at the start of the page-flip
 651                  * sequence, but also more than one vblank has passed.
 652                  *
 653                  * For the former case of modeswitching, it is possible
 654                  * to switch between two FBC valid configurations
 655                  * instantaneously so we do need to disable the FBC
 656                  * before we can modify its control registers. We also
 657                  * have to wait for the next vblank for that to take
 658                  * effect. However, since we delay enabling FBC we can
 659                  * assume that a vblank has passed since disabling and
 660                  * that we can safely alter the registers in the deferred
 661                  * callback.
 662                  *
 663                  * In the scenario that we go from a valid to invalid
 664                  * and then back to valid FBC configuration we have
 665                  * no strict enforcement that a vblank occurred since
 666                  * disabling the FBC. However, along all current pipe
 667                  * disabling paths we do need to wait for a vblank at
 668                  * some point. And we wait before enabling FBC anyway.
 669                  */
 670                 DRM_DEBUG_KMS("disabling active FBC for update\n");
 671                 intel_disable_fbc(dev);
 672         }
 673
 674         intel_enable_fbc(crtc);
 675         dev_priv->fbc.no_fbc_reason = FBC_OK;
 676         return;
 677
 678 out_disable:
 679         /* Multiple disables should be harmless */
 680         if (intel_fbc_enabled(dev)) {
 681                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
 682                 intel_disable_fbc(dev);
 683         }
 684         i915_gem_stolen_cleanup_compression(dev);
 685 }
 686
 687 static void i915_pineview_get_mem_freq(struct drm_device *dev)
 688 {
 689         struct drm_i915_private *dev_priv = dev->dev_private;
 690         u32 tmp;
 691
 692         tmp = I915_READ(CLKCFG);
 693
 694         switch (tmp & CLKCFG_FSB_MASK) {
 695         case CLKCFG_FSB_533:
 696                 dev_priv->fsb_freq = 533; /* 133*4 */
 697                 break;
 698         case CLKCFG_FSB_800:
 699                 dev_priv->fsb_freq = 800; /* 200*4 */
 700                 break;
 701         case CLKCFG_FSB_667:
 702                 dev_priv->fsb_freq =  667; /* 167*4 */
 703                 break;
 704         case CLKCFG_FSB_400:
 705                 dev_priv->fsb_freq = 400; /* 100*4 */
 706                 break;
 707         }
 708
 709         switch (tmp & CLKCFG_MEM_MASK) {
 710         case CLKCFG_MEM_533:
 711                 dev_priv->mem_freq = 533;
 712                 break;
 713         case CLKCFG_MEM_667:
 714                 dev_priv->mem_freq = 667;
 715                 break;
 716         case CLKCFG_MEM_800:
 717                 dev_priv->mem_freq = 800;
 718                 break;
 719         }
 720
 721         /* detect pineview DDR3 setting */
 722         tmp = I915_READ(CSHRDDR3CTL);
 723         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 724 }
 725
 726 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 727 {
 728         struct drm_i915_private *dev_priv = dev->dev_private;
 729         u16 ddrpll, csipll;
 730
 731         ddrpll = I915_READ16(DDRMPLL1);
 732         csipll = I915_READ16(CSIPLL0);
 733
 734         switch (ddrpll & 0xff) {
 735         case 0xc:
 736                 dev_priv->mem_freq = 800;
 737                 break;
 738         case 0x10:
 739                 dev_priv->mem_freq = 1066;
 740                 break;
 741         case 0x14:
 742                 dev_priv->mem_freq = 1333;
 743                 break;
 744         case 0x18:
 745                 dev_priv->mem_freq = 1600;
 746                 break;
 747         default:
 748                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 749                                  ddrpll & 0xff);
 750                 dev_priv->mem_freq = 0;
 751                 break;
 752         }
 753
 754         dev_priv->ips.r_t = dev_priv->mem_freq;
 755
 756         switch (csipll & 0x3ff) {
 757         case 0x00c:
 758                 dev_priv->fsb_freq = 3200;
 759                 break;
 760         case 0x00e:
 761                 dev_priv->fsb_freq = 3733;
 762                 break;
 763         case 0x010:
 764                 dev_priv->fsb_freq = 4266;
 765                 break;
 766         case 0x012:
 767                 dev_priv->fsb_freq = 4800;
 768                 break;
 769         case 0x014:
 770                 dev_priv->fsb_freq = 5333;
 771                 break;
 772         case 0x016:
 773                 dev_priv->fsb_freq = 5866;
 774                 break;
 775         case 0x018:
 776                 dev_priv->fsb_freq = 6400;
 777                 break;
 778         default:
 779                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 780                                  csipll & 0x3ff);
 781                 dev_priv->fsb_freq = 0;
 782                 break;
 783         }
 784
 785         if (dev_priv->fsb_freq == 3200) {
 786                 dev_priv->ips.c_m = 0;
 787         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 788                 dev_priv->ips.c_m = 1;
 789         } else {
 790                 dev_priv->ips.c_m = 2;
 791         }
 792 }
 793
 794 static const struct cxsr_latency cxsr_latency_table[] = {
 795         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 796         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 797         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 798         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 799         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 800
 801         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 802         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 803         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 804         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 805         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 806
 807         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 808         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 809         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 810         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 811         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 812
 813         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 814         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 815         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 816         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 817         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 818
 819         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 820         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 821         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 822         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 823         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 824
 825         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 826         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 827         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 828         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 829         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 830 };
 831
 832 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 833                                                          int is_ddr3,
 834                                                          int fsb,
 835                                                          int mem)
 836 {
 837         const struct cxsr_latency *latency;
 838         int i;
 839
 840         if (fsb == 0 || mem == 0)
 841                 return NULL;
 842
 843         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 844                 latency = &cxsr_latency_table[i];
 845                 if (is_desktop == latency->is_desktop &&
 846                     is_ddr3 == latency->is_ddr3 &&
 847                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 848                         return latency;
 849         }
 850
 851         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 852
 853         return NULL;
 854 }
 855
 856 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 857 {
 858         struct drm_device *dev = dev_priv->dev;
 859         u32 val;
 860
 861         if (IS_VALLEYVIEW(dev)) {
 862                 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
 863         } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
 864                 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
 865         } else if (IS_PINEVIEW(dev)) {
 866                 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
 867                 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
 868                 I915_WRITE(DSPFW3, val);
 869         } else if (IS_I945G(dev) || IS_I945GM(dev)) {
 870                 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
 871                                _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
 872                 I915_WRITE(FW_BLC_SELF, val);
 873         } else if (IS_I915GM(dev)) {
 874                 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
 875                                _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
 876                 I915_WRITE(INSTPM, val);
 877         } else {
 878                 return;
 879         }
 880
 881         DRM_DEBUG_KMS("memory self-refresh is %s\n",
 882                       enable ? "enabled" : "disabled");
 883 }
 884
 885 /*
 886  * Latency for FIFO fetches is dependent on several factors:
 887  *   - memory configuration (speed, channels)
 888  *   - chipset
 889  *   - current MCH state
 890  * It can be fairly high in some situations, so here we assume a fairly
 891  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 892  * set this value too high, the FIFO will fetch frequently to stay full)
 893  * and power consumption (set it too low to save power and we might see
 894  * FIFO underruns and display "flicker").
 895  *
 896  * A value of 5us seems to be a good balance; safe for very low end
 897  * platforms but not overly aggressive on lower latency configs.
 898  */
 899 static const int pessimal_latency_ns = 5000;
 900
 901 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 902 {
 903         struct drm_i915_private *dev_priv = dev->dev_private;
 904         uint32_t dsparb = I915_READ(DSPARB);
 905         int size;
 906
 907         size = dsparb & 0x7f;
 908         if (plane)
 909                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 910
 911         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 912                       plane ? "B" : "A", size);
 913
 914         return size;
 915 }
 916
 917 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 918 {
 919         struct drm_i915_private *dev_priv = dev->dev_private;
 920         uint32_t dsparb = I915_READ(DSPARB);
 921         int size;
 922
 923         size = dsparb & 0x1ff;
 924         if (plane)
 925                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 926         size >>= 1; /* Convert to cachelines */
 927
 928         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 929                       plane ? "B" : "A", size);
 930
 931         return size;
 932 }
 933
 934 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 935 {
 936         struct drm_i915_private *dev_priv = dev->dev_private;
 937         uint32_t dsparb = I915_READ(DSPARB);
 938         int size;
 939
 940         size = dsparb & 0x7f;
 941         size >>= 2; /* Convert to cachelines */
 942
 943         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 944                       plane ? "B" : "A",
 945                       size);
 946
 947         return size;
 948 }
 949
 950 /* Pineview has different values for various configs */
 951 static const struct intel_watermark_params pineview_display_wm = {
 952         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 953         .max_wm = PINEVIEW_MAX_WM,
 954         .default_wm = PINEVIEW_DFT_WM,
 955         .guard_size = PINEVIEW_GUARD_WM,
 956         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 957 };
 958 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 959         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 960         .max_wm = PINEVIEW_MAX_WM,
 961         .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
 962         .guard_size = PINEVIEW_GUARD_WM,
 963         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 964 };
 965 static const struct intel_watermark_params pineview_cursor_wm = {
 966         .fifo_size = PINEVIEW_CURSOR_FIFO,
 967         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 968         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 969         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 970         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 971 };
 972 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 973         .fifo_size = PINEVIEW_CURSOR_FIFO,
 974         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 975         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 976         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 977         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 978 };
 979 static const struct intel_watermark_params g4x_wm_info = {
 980         .fifo_size = G4X_FIFO_SIZE,
 981         .max_wm = G4X_MAX_WM,
 982         .default_wm = G4X_MAX_WM,
 983         .guard_size = 2,
 984         .cacheline_size = G4X_FIFO_LINE_SIZE,
 985 };
 986 static const struct intel_watermark_params g4x_cursor_wm_info = {
 987         .fifo_size = I965_CURSOR_FIFO,
 988         .max_wm = I965_CURSOR_MAX_WM,
 989         .default_wm = I965_CURSOR_DFT_WM,
 990         .guard_size = 2,
 991         .cacheline_size = G4X_FIFO_LINE_SIZE,
 992 };
 993 static const struct intel_watermark_params valleyview_wm_info = {
 994         .fifo_size = VALLEYVIEW_FIFO_SIZE,
 995         .max_wm = VALLEYVIEW_MAX_WM,
 996         .default_wm = VALLEYVIEW_MAX_WM,
 997         .guard_size = 2,
 998         .cacheline_size = G4X_FIFO_LINE_SIZE,
 999 };
1000 static const struct intel_watermark_params valleyview_cursor_wm_info = {
1001         .fifo_size = I965_CURSOR_FIFO,
1002         .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
1003         .default_wm = I965_CURSOR_DFT_WM,
1004         .guard_size = 2,
1005         .cacheline_size = G4X_FIFO_LINE_SIZE,
1006 };
1007 static const struct intel_watermark_params i965_cursor_wm_info = {
1008         .fifo_size = I965_CURSOR_FIFO,
1009         .max_wm = I965_CURSOR_MAX_WM,
1010         .default_wm = I965_CURSOR_DFT_WM,
1011         .guard_size = 2,
1012         .cacheline_size = I915_FIFO_LINE_SIZE,
1013 };
1014 static const struct intel_watermark_params i945_wm_info = {
1015         .fifo_size = I945_FIFO_SIZE,
1016         .max_wm = I915_MAX_WM,
1017         .default_wm = 1,
1018         .guard_size = 2,
1019         .cacheline_size = I915_FIFO_LINE_SIZE,
1020 };
1021 static const struct intel_watermark_params i915_wm_info = {
1022         .fifo_size = I915_FIFO_SIZE,
1023         .max_wm = I915_MAX_WM,
1024         .default_wm = 1,
1025         .guard_size = 2,
1026         .cacheline_size = I915_FIFO_LINE_SIZE,
1027 };
1028 static const struct intel_watermark_params i830_a_wm_info = {
1029         .fifo_size = I855GM_FIFO_SIZE,
1030         .max_wm = I915_MAX_WM,
1031         .default_wm = 1,
1032         .guard_size = 2,
1033         .cacheline_size = I830_FIFO_LINE_SIZE,
1034 };
1035 static const struct intel_watermark_params i830_bc_wm_info = {
1036         .fifo_size = I855GM_FIFO_SIZE,
1037         .max_wm = I915_MAX_WM/2,
1038         .default_wm = 1,
1039         .guard_size = 2,
1040         .cacheline_size = I830_FIFO_LINE_SIZE,
1041 };
1042 static const struct intel_watermark_params i845_wm_info = {
1043         .fifo_size = I830_FIFO_SIZE,
1044         .max_wm = I915_MAX_WM,
1045         .default_wm = 1,
1046         .guard_size = 2,
1047         .cacheline_size = I830_FIFO_LINE_SIZE,
1048 };
1049
1050 /**
1051  * intel_calculate_wm - calculate watermark level
1052  * @clock_in_khz: pixel clock
1053  * @wm: chip FIFO params
1054  * @pixel_size: display pixel size
1055  * @latency_ns: memory latency for the platform
1056  *
1057  * Calculate the watermark level (the level at which the display plane will
1058  * start fetching from memory again).  Each chip has a different display
1059  * FIFO size and allocation, so the caller needs to figure that out and pass
1060  * in the correct intel_watermark_params structure.
1061  *
1062  * As the pixel clock runs, the FIFO will be drained at a rate that depends
1063  * on the pixel size.  When it reaches the watermark level, it'll start
1064  * fetching FIFO line sized based chunks from memory until the FIFO fills
1065  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
1066  * will occur, and a display engine hang could result.
1067  */
1068 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1069                                         const struct intel_watermark_params *wm,
1070                                         int fifo_size,
1071                                         int pixel_size,
1072                                         unsigned long latency_ns)
1073 {
1074         long entries_required, wm_size;
1075
1076         /*
1077          * Note: we need to make sure we don't overflow for various clock &
1078          * latency values.
1079          * clocks go from a few thousand to several hundred thousand.
1080          * latency is usually a few thousand
1081          */
1082         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1083                 1000;
1084         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1085
1086         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1087
1088         wm_size = fifo_size - (entries_required + wm->guard_size);
1089
1090         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1091
1092         /* Don't promote wm_size to unsigned... */
1093         if (wm_size > (long)wm->max_wm)
1094                 wm_size = wm->max_wm;
1095         if (wm_size <= 0)
1096                 wm_size = wm->default_wm;
1097         return wm_size;
1098 }
1099
1100 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1101 {
1102         struct drm_crtc *crtc, *enabled = NULL;
1103
1104         for_each_crtc(dev, crtc) {
1105                 if (intel_crtc_active(crtc)) {
1106                         if (enabled)
1107                                 return NULL;
1108                         enabled = crtc;
1109                 }
1110         }
1111
1112         return enabled;
1113 }
1114
1115 static void pineview_update_wm(struct drm_crtc *unused_crtc)
1116 {
1117         struct drm_device *dev = unused_crtc->dev;
1118         struct drm_i915_private *dev_priv = dev->dev_private;
1119         struct drm_crtc *crtc;
1120         const struct cxsr_latency *latency;
1121         u32 reg;
1122         unsigned long wm;
1123
1124         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1125                                          dev_priv->fsb_freq, dev_priv->mem_freq);
1126         if (!latency) {
1127                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1128                 intel_set_memory_cxsr(dev_priv, false);
1129                 return;
1130         }
1131
1132         crtc = single_enabled_crtc(dev);
1133         if (crtc) {
1134                 const struct drm_display_mode *adjusted_mode;
1135                 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1136                 int clock;
1137
1138                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1139                 clock = adjusted_mode->crtc_clock;
1140
1141                 /* Display SR */
1142                 wm = intel_calculate_wm(clock, &pineview_display_wm,
1143                                         pineview_display_wm.fifo_size,
1144                                         pixel_size, latency->display_sr);
1145                 reg = I915_READ(DSPFW1);
1146                 reg &= ~DSPFW_SR_MASK;
1147                 reg |= wm << DSPFW_SR_SHIFT;
1148                 I915_WRITE(DSPFW1, reg);
1149                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1150
1151                 /* cursor SR */
1152                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1153                                         pineview_display_wm.fifo_size,
1154                                         pixel_size, latency->cursor_sr);
1155                 reg = I915_READ(DSPFW3);
1156                 reg &= ~DSPFW_CURSOR_SR_MASK;
1157                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1158                 I915_WRITE(DSPFW3, reg);
1159
1160                 /* Display HPLL off SR */
1161                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1162                                         pineview_display_hplloff_wm.fifo_size,
1163                                         pixel_size, latency->display_hpll_disable);
1164                 reg = I915_READ(DSPFW3);
1165                 reg &= ~DSPFW_HPLL_SR_MASK;
1166                 reg |= wm & DSPFW_HPLL_SR_MASK;
1167                 I915_WRITE(DSPFW3, reg);
1168
1169                 /* cursor HPLL off SR */
1170                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1171                                         pineview_display_hplloff_wm.fifo_size,
1172                                         pixel_size, latency->cursor_hpll_disable);
1173                 reg = I915_READ(DSPFW3);
1174                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1175                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1176                 I915_WRITE(DSPFW3, reg);
1177                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1178
1179                 intel_set_memory_cxsr(dev_priv, true);
1180         } else {
1181                 intel_set_memory_cxsr(dev_priv, false);
1182         }
1183 }
1184
1185 static bool g4x_compute_wm0(struct drm_device *dev,
1186                             int plane,
1187                             const struct intel_watermark_params *display,
1188                             int display_latency_ns,
1189                             const struct intel_watermark_params *cursor,
1190                             int cursor_latency_ns,
1191                             int *plane_wm,
1192                             int *cursor_wm)
1193 {
1194         struct drm_crtc *crtc;
1195         const struct drm_display_mode *adjusted_mode;
1196         int htotal, hdisplay, clock, pixel_size;
1197         int line_time_us, line_count;
1198         int entries, tlb_miss;
1199
1200         crtc = intel_get_crtc_for_plane(dev, plane);
1201         if (!intel_crtc_active(crtc)) {
1202                 *cursor_wm = cursor->guard_size;
1203                 *plane_wm = display->guard_size;
1204                 return false;
1205         }
1206
1207         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1208         clock = adjusted_mode->crtc_clock;
1209         htotal = adjusted_mode->crtc_htotal;
1210         hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1211         pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1212
1213         /* Use the small buffer method to calculate plane watermark */
1214         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1215         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1216         if (tlb_miss > 0)
1217                 entries += tlb_miss;
1218         entries = DIV_ROUND_UP(entries, display->cacheline_size);
1219         *plane_wm = entries + display->guard_size;
1220         if (*plane_wm > (int)display->max_wm)
1221                 *plane_wm = display->max_wm;
1222
1223         /* Use the large buffer method to calculate cursor watermark */
1224         line_time_us = max(htotal * 1000 / clock, 1);
1225         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1226         entries = line_count * to_intel_crtc(crtc)->cursor_width * pixel_size;
1227         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1228         if (tlb_miss > 0)
1229                 entries += tlb_miss;
1230         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1231         *cursor_wm = entries + cursor->guard_size;
1232         if (*cursor_wm > (int)cursor->max_wm)
1233                 *cursor_wm = (int)cursor->max_wm;
1234
1235         return true;
1236 }
1237
1238 /*
1239  * Check the wm result.
1240  *
1241  * If any calculated watermark values is larger than the maximum value that
1242  * can be programmed into the associated watermark register, that watermark
1243  * must be disabled.
1244  */
1245 static bool g4x_check_srwm(struct drm_device *dev,
1246                            int display_wm, int cursor_wm,
1247                            const struct intel_watermark_params *display,
1248                            const struct intel_watermark_params *cursor)
1249 {
1250         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1251                       display_wm, cursor_wm);
1252
1253         if (display_wm > display->max_wm) {
1254                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1255                               display_wm, display->max_wm);
1256                 return false;
1257         }
1258
1259         if (cursor_wm > cursor->max_wm) {
1260                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1261                               cursor_wm, cursor->max_wm);
1262                 return false;
1263         }
1264
1265         if (!(display_wm || cursor_wm)) {
1266                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1267                 return false;
1268         }
1269
1270         return true;
1271 }
1272
1273 static bool g4x_compute_srwm(struct drm_device *dev,
1274                              int plane,
1275                              int latency_ns,
1276                              const struct intel_watermark_params *display,
1277                              const struct intel_watermark_params *cursor,
1278                              int *display_wm, int *cursor_wm)
1279 {
1280         struct drm_crtc *crtc;
1281         const struct drm_display_mode *adjusted_mode;
1282         int hdisplay, htotal, pixel_size, clock;
1283         unsigned long line_time_us;
1284         int line_count, line_size;
1285         int small, large;
1286         int entries;
1287
1288         if (!latency_ns) {
1289                 *display_wm = *cursor_wm = 0;
1290                 return false;
1291         }
1292
1293         crtc = intel_get_crtc_for_plane(dev, plane);
1294         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1295         clock = adjusted_mode->crtc_clock;
1296         htotal = adjusted_mode->crtc_htotal;
1297         hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1298         pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1299
1300         line_time_us = max(htotal * 1000 / clock, 1);
1301         line_count = (latency_ns / line_time_us + 1000) / 1000;
1302         line_size = hdisplay * pixel_size;
1303
1304         /* Use the minimum of the small and large buffer method for primary */
1305         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1306         large = line_count * line_size;
1307
1308         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1309         *display_wm = entries + display->guard_size;
1310
1311         /* calculate the self-refresh watermark for display cursor */
1312         entries = line_count * pixel_size * to_intel_crtc(crtc)->cursor_width;
1313         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1314         *cursor_wm = entries + cursor->guard_size;
1315
1316         return g4x_check_srwm(dev,
1317                               *display_wm, *cursor_wm,
1318                               display, cursor);
1319 }
1320
1321 static bool vlv_compute_drain_latency(struct drm_crtc *crtc,
1322                                       int pixel_size,
1323                                       int *prec_mult,
1324                                       int *drain_latency)
1325 {
1326         int entries;
1327         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
1328
1329         if (WARN(clock == 0, "Pixel clock is zero!\n"))
1330                 return false;
1331
1332         if (WARN(pixel_size == 0, "Pixel size is zero!\n"))
1333                 return false;
1334
1335         entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
1336         *prec_mult = (entries > 128) ? DRAIN_LATENCY_PRECISION_64 :
1337                                        DRAIN_LATENCY_PRECISION_32;
1338         *drain_latency = (64 * (*prec_mult) * 4) / entries;
1339
1340         if (*drain_latency > DRAIN_LATENCY_MASK)
1341                 *drain_latency = DRAIN_LATENCY_MASK;
1342
1343         return true;
1344 }
1345
1346 /*
1347  * Update drain latency registers of memory arbiter
1348  *
1349  * Valleyview SoC has a new memory arbiter and needs drain latency registers
1350  * to be programmed. Each plane has a drain latency multiplier and a drain
1351  * latency value.
1352  */
1353
1354 static void vlv_update_drain_latency(struct drm_crtc *crtc)
1355 {
1356         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1357         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1358         int pixel_size;
1359         int drain_latency;
1360         enum pipe pipe = intel_crtc->pipe;
1361         int plane_prec, prec_mult, plane_dl;
1362
1363         plane_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_PLANE_PRECISION_64 |
1364                    DRAIN_LATENCY_MASK | DDL_CURSOR_PRECISION_64 |
1365                    (DRAIN_LATENCY_MASK << DDL_CURSOR_SHIFT));
1366
1367         if (!intel_crtc_active(crtc)) {
1368                 I915_WRITE(VLV_DDL(pipe), plane_dl);
1369                 return;
1370         }
1371
1372         /* Primary plane Drain Latency */
1373         pixel_size = crtc->primary->fb->bits_per_pixel / 8;     /* BPP */
1374         if (vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) {
1375                 plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ?
1376                                            DDL_PLANE_PRECISION_64 :
1377                                            DDL_PLANE_PRECISION_32;
1378                 plane_dl |= plane_prec | drain_latency;
1379         }
1380
1381         /* Cursor Drain Latency
1382          * BPP is always 4 for cursor
1383          */
1384         pixel_size = 4;
1385
1386         /* Program cursor DL only if it is enabled */
1387         if (intel_crtc->cursor_base &&
1388             vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) {
1389                 plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ?
1390                                            DDL_CURSOR_PRECISION_64 :
1391                                            DDL_CURSOR_PRECISION_32;
1392                 plane_dl |= plane_prec | (drain_latency << DDL_CURSOR_SHIFT);
1393         }
1394
1395         I915_WRITE(VLV_DDL(pipe), plane_dl);
1396 }
1397
1398 #define single_plane_enabled(mask) is_power_of_2(mask)
1399
1400 static void valleyview_update_wm(struct drm_crtc *crtc)
1401 {
1402         struct drm_device *dev = crtc->dev;
1403         static const int sr_latency_ns = 12000;
1404         struct drm_i915_private *dev_priv = dev->dev_private;
1405         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1406         int plane_sr, cursor_sr;
1407         int ignore_plane_sr, ignore_cursor_sr;
1408         unsigned int enabled = 0;
1409         bool cxsr_enabled;
1410
1411         vlv_update_drain_latency(crtc);
1412
1413         if (g4x_compute_wm0(dev, PIPE_A,
1414                             &valleyview_wm_info, pessimal_latency_ns,
1415                             &valleyview_cursor_wm_info, pessimal_latency_ns,
1416                             &planea_wm, &cursora_wm))
1417                 enabled |= 1 << PIPE_A;
1418
1419         if (g4x_compute_wm0(dev, PIPE_B,
1420                             &valleyview_wm_info, pessimal_latency_ns,
1421                             &valleyview_cursor_wm_info, pessimal_latency_ns,
1422                             &planeb_wm, &cursorb_wm))
1423                 enabled |= 1 << PIPE_B;
1424
1425         if (single_plane_enabled(enabled) &&
1426             g4x_compute_srwm(dev, ffs(enabled) - 1,
1427                              sr_latency_ns,
1428                              &valleyview_wm_info,
1429                              &valleyview_cursor_wm_info,
1430                              &plane_sr, &ignore_cursor_sr) &&
1431             g4x_compute_srwm(dev, ffs(enabled) - 1,
1432                              2*sr_latency_ns,
1433                              &valleyview_wm_info,
1434                              &valleyview_cursor_wm_info,
1435                              &ignore_plane_sr, &cursor_sr)) {
1436                 cxsr_enabled = true;
1437         } else {
1438                 cxsr_enabled = false;
1439                 intel_set_memory_cxsr(dev_priv, false);
1440                 plane_sr = cursor_sr = 0;
1441         }
1442
1443         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1444                       "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1445                       planea_wm, cursora_wm,
1446                       planeb_wm, cursorb_wm,
1447                       plane_sr, cursor_sr);
1448
1449         I915_WRITE(DSPFW1,
1450                    (plane_sr << DSPFW_SR_SHIFT) |
1451                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1452                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1453                    (planea_wm << DSPFW_PLANEA_SHIFT));
1454         I915_WRITE(DSPFW2,
1455                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1456                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1457         I915_WRITE(DSPFW3,
1458                    (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1459                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1460
1461         if (cxsr_enabled)
1462                 intel_set_memory_cxsr(dev_priv, true);
1463 }
1464
1465 static void cherryview_update_wm(struct drm_crtc *crtc)
1466 {
1467         struct drm_device *dev = crtc->dev;
1468         static const int sr_latency_ns = 12000;
1469         struct drm_i915_private *dev_priv = dev->dev_private;
1470         int planea_wm, planeb_wm, planec_wm;
1471         int cursora_wm, cursorb_wm, cursorc_wm;
1472         int plane_sr, cursor_sr;
1473         int ignore_plane_sr, ignore_cursor_sr;
1474         unsigned int enabled = 0;
1475         bool cxsr_enabled;
1476
1477         vlv_update_drain_latency(crtc);
1478
1479         if (g4x_compute_wm0(dev, PIPE_A,
1480                             &valleyview_wm_info, pessimal_latency_ns,
1481                             &valleyview_cursor_wm_info, pessimal_latency_ns,
1482                             &planea_wm, &cursora_wm))
1483                 enabled |= 1 << PIPE_A;
1484
1485         if (g4x_compute_wm0(dev, PIPE_B,
1486                             &valleyview_wm_info, pessimal_latency_ns,
1487                             &valleyview_cursor_wm_info, pessimal_latency_ns,
1488                             &planeb_wm, &cursorb_wm))
1489                 enabled |= 1 << PIPE_B;
1490
1491         if (g4x_compute_wm0(dev, PIPE_C,
1492                             &valleyview_wm_info, pessimal_latency_ns,
1493                             &valleyview_cursor_wm_info, pessimal_latency_ns,
1494                             &planec_wm, &cursorc_wm))
1495                 enabled |= 1 << PIPE_C;
1496
1497         if (single_plane_enabled(enabled) &&
1498             g4x_compute_srwm(dev, ffs(enabled) - 1,
1499                              sr_latency_ns,
1500                              &valleyview_wm_info,
1501                              &valleyview_cursor_wm_info,
1502                              &plane_sr, &ignore_cursor_sr) &&
1503             g4x_compute_srwm(dev, ffs(enabled) - 1,
1504                              2*sr_latency_ns,
1505                              &valleyview_wm_info,
1506                              &valleyview_cursor_wm_info,
1507                              &ignore_plane_sr, &cursor_sr)) {
1508                 cxsr_enabled = true;
1509         } else {
1510                 cxsr_enabled = false;
1511                 intel_set_memory_cxsr(dev_priv, false);
1512                 plane_sr = cursor_sr = 0;
1513         }
1514
1515         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1516                       "B: plane=%d, cursor=%d, C: plane=%d, cursor=%d, "
1517                       "SR: plane=%d, cursor=%d\n",
1518                       planea_wm, cursora_wm,
1519                       planeb_wm, cursorb_wm,
1520                       planec_wm, cursorc_wm,
1521                       plane_sr, cursor_sr);
1522
1523         I915_WRITE(DSPFW1,
1524                    (plane_sr << DSPFW_SR_SHIFT) |
1525                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1526                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1527                    (planea_wm << DSPFW_PLANEA_SHIFT));
1528         I915_WRITE(DSPFW2,
1529                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1530                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1531         I915_WRITE(DSPFW3,
1532                    (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1533                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1534         I915_WRITE(DSPFW9_CHV,
1535                    (I915_READ(DSPFW9_CHV) & ~(DSPFW_PLANEC_MASK |
1536                                               DSPFW_CURSORC_MASK)) |
1537                    (planec_wm << DSPFW_PLANEC_SHIFT) |
1538                    (cursorc_wm << DSPFW_CURSORC_SHIFT));
1539
1540         if (cxsr_enabled)
1541                 intel_set_memory_cxsr(dev_priv, true);
1542 }
1543
1544 static void valleyview_update_sprite_wm(struct drm_plane *plane,
1545                                         struct drm_crtc *crtc,
1546                                         uint32_t sprite_width,
1547                                         uint32_t sprite_height,
1548                                         int pixel_size,
1549                                         bool enabled, bool scaled)
1550 {
1551         struct drm_device *dev = crtc->dev;
1552         struct drm_i915_private *dev_priv = dev->dev_private;
1553         int pipe = to_intel_plane(plane)->pipe;
1554         int sprite = to_intel_plane(plane)->plane;
1555         int drain_latency;
1556         int plane_prec;
1557         int sprite_dl;
1558         int prec_mult;
1559
1560         sprite_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_SPRITE_PRECISION_64(sprite) |
1561                     (DRAIN_LATENCY_MASK << DDL_SPRITE_SHIFT(sprite)));
1562
1563         if (enabled && vlv_compute_drain_latency(crtc, pixel_size, &prec_mult,
1564                                                  &drain_latency)) {
1565                 plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ?
1566                                            DDL_SPRITE_PRECISION_64(sprite) :
1567                                            DDL_SPRITE_PRECISION_32(sprite);
1568                 sprite_dl |= plane_prec |
1569                              (drain_latency << DDL_SPRITE_SHIFT(sprite));
1570         }
1571
1572         I915_WRITE(VLV_DDL(pipe), sprite_dl);
1573 }
1574
1575 static void g4x_update_wm(struct drm_crtc *crtc)
1576 {
1577         struct drm_device *dev = crtc->dev;
1578         static const int sr_latency_ns = 12000;
1579         struct drm_i915_private *dev_priv = dev->dev_private;
1580         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1581         int plane_sr, cursor_sr;
1582         unsigned int enabled = 0;
1583         bool cxsr_enabled;
1584
1585         if (g4x_compute_wm0(dev, PIPE_A,
1586                             &g4x_wm_info, pessimal_latency_ns,
1587                             &g4x_cursor_wm_info, pessimal_latency_ns,
1588                             &planea_wm, &cursora_wm))
1589                 enabled |= 1 << PIPE_A;
1590
1591         if (g4x_compute_wm0(dev, PIPE_B,
1592                             &g4x_wm_info, pessimal_latency_ns,
1593                             &g4x_cursor_wm_info, pessimal_latency_ns,
1594                             &planeb_wm, &cursorb_wm))
1595                 enabled |= 1 << PIPE_B;
1596
1597         if (single_plane_enabled(enabled) &&
1598             g4x_compute_srwm(dev, ffs(enabled) - 1,
1599                              sr_latency_ns,
1600                              &g4x_wm_info,
1601                              &g4x_cursor_wm_info,
1602                              &plane_sr, &cursor_sr)) {
1603                 cxsr_enabled = true;
1604         } else {
1605                 cxsr_enabled = false;
1606                 intel_set_memory_cxsr(dev_priv, false);
1607                 plane_sr = cursor_sr = 0;
1608         }
1609
1610         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1611                       "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1612                       planea_wm, cursora_wm,
1613                       planeb_wm, cursorb_wm,
1614                       plane_sr, cursor_sr);
1615
1616         I915_WRITE(DSPFW1,
1617                    (plane_sr << DSPFW_SR_SHIFT) |
1618                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1619                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1620                    (planea_wm << DSPFW_PLANEA_SHIFT));
1621         I915_WRITE(DSPFW2,
1622                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1623                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1624         /* HPLL off in SR has some issues on G4x... disable it */
1625         I915_WRITE(DSPFW3,
1626                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1627                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1628
1629         if (cxsr_enabled)
1630                 intel_set_memory_cxsr(dev_priv, true);
1631 }
1632
1633 static void i965_update_wm(struct drm_crtc *unused_crtc)
1634 {
1635         struct drm_device *dev = unused_crtc->dev;
1636         struct drm_i915_private *dev_priv = dev->dev_private;
1637         struct drm_crtc *crtc;
1638         int srwm = 1;
1639         int cursor_sr = 16;
1640         bool cxsr_enabled;
1641
1642         /* Calc sr entries for one plane configs */
1643         crtc = single_enabled_crtc(dev);
1644         if (crtc) {
1645                 /* self-refresh has much higher latency */
1646                 static const int sr_latency_ns = 12000;
1647                 const struct drm_display_mode *adjusted_mode =
1648                         &to_intel_crtc(crtc)->config.adjusted_mode;
1649                 int clock = adjusted_mode->crtc_clock;
1650                 int htotal = adjusted_mode->crtc_htotal;
1651                 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1652                 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1653                 unsigned long line_time_us;
1654                 int entries;
1655
1656                 line_time_us = max(htotal * 1000 / clock, 1);
1657
1658                 /* Use ns/us then divide to preserve precision */
1659                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1660                         pixel_size * hdisplay;
1661                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1662                 srwm = I965_FIFO_SIZE - entries;
1663                 if (srwm < 0)
1664                         srwm = 1;
1665                 srwm &= 0x1ff;
1666                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1667                               entries, srwm);
1668
1669                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1670                         pixel_size * to_intel_crtc(crtc)->cursor_width;
1671                 entries = DIV_ROUND_UP(entries,
1672                                           i965_cursor_wm_info.cacheline_size);
1673                 cursor_sr = i965_cursor_wm_info.fifo_size -
1674                         (entries + i965_cursor_wm_info.guard_size);
1675
1676                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1677                         cursor_sr = i965_cursor_wm_info.max_wm;
1678
1679                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1680                               "cursor %d\n", srwm, cursor_sr);
1681
1682                 cxsr_enabled = true;
1683         } else {
1684                 cxsr_enabled = false;
1685                 /* Turn off self refresh if both pipes are enabled */
1686                 intel_set_memory_cxsr(dev_priv, false);
1687         }
1688
1689         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1690                       srwm);
1691
1692         /* 965 has limitations... */
1693         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1694                    (8 << DSPFW_CURSORB_SHIFT) |
1695                    (8 << DSPFW_PLANEB_SHIFT) |
1696                    (8 << DSPFW_PLANEA_SHIFT));
1697         I915_WRITE(DSPFW2, (8 << DSPFW_CURSORA_SHIFT) |
1698                    (8 << DSPFW_PLANEC_SHIFT_OLD));
1699         /* update cursor SR watermark */
1700         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1701
1702         if (cxsr_enabled)
1703                 intel_set_memory_cxsr(dev_priv, true);
1704 }
1705
1706 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1707 {
1708         struct drm_device *dev = unused_crtc->dev;
1709         struct drm_i915_private *dev_priv = dev->dev_private;
1710         const struct intel_watermark_params *wm_info;
1711         uint32_t fwater_lo;
1712         uint32_t fwater_hi;
1713         int cwm, srwm = 1;
1714         int fifo_size;
1715         int planea_wm, planeb_wm;
1716         struct drm_crtc *crtc, *enabled = NULL;
1717
1718         if (IS_I945GM(dev))
1719                 wm_info = &i945_wm_info;
1720         else if (!IS_GEN2(dev))
1721                 wm_info = &i915_wm_info;
1722         else
1723                 wm_info = &i830_a_wm_info;
1724
1725         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1726         crtc = intel_get_crtc_for_plane(dev, 0);
1727         if (intel_crtc_active(crtc)) {
1728                 const struct drm_display_mode *adjusted_mode;
1729                 int cpp = crtc->primary->fb->bits_per_pixel / 8;
1730                 if (IS_GEN2(dev))
1731                         cpp = 4;
1732
1733                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1734                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1735                                                wm_info, fifo_size, cpp,
1736                                                pessimal_latency_ns);
1737                 enabled = crtc;
1738         } else {
1739                 planea_wm = fifo_size - wm_info->guard_size;
1740                 if (planea_wm > (long)wm_info->max_wm)
1741                         planea_wm = wm_info->max_wm;
1742         }
1743
1744         if (IS_GEN2(dev))
1745                 wm_info = &i830_bc_wm_info;
1746
1747         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1748         crtc = intel_get_crtc_for_plane(dev, 1);
1749         if (intel_crtc_active(crtc)) {
1750                 const struct drm_display_mode *adjusted_mode;
1751                 int cpp = crtc->primary->fb->bits_per_pixel / 8;
1752                 if (IS_GEN2(dev))
1753                         cpp = 4;
1754
1755                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1756                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1757                                                wm_info, fifo_size, cpp,
1758                                                pessimal_latency_ns);
1759                 if (enabled == NULL)
1760                         enabled = crtc;
1761                 else
1762                         enabled = NULL;
1763         } else {
1764                 planeb_wm = fifo_size - wm_info->guard_size;
1765                 if (planeb_wm > (long)wm_info->max_wm)
1766                         planeb_wm = wm_info->max_wm;
1767         }
1768
1769         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1770
1771         if (IS_I915GM(dev) && enabled) {
1772                 struct drm_i915_gem_object *obj;
1773
1774                 obj = intel_fb_obj(enabled->primary->fb);
1775
1776                 /* self-refresh seems busted with untiled */
1777                 if (obj->tiling_mode == I915_TILING_NONE)
1778                         enabled = NULL;
1779         }
1780
1781         /*
1782          * Overlay gets an aggressive default since video jitter is bad.
1783          */
1784         cwm = 2;
1785
1786         /* Play safe and disable self-refresh before adjusting watermarks. */
1787         intel_set_memory_cxsr(dev_priv, false);
1788
1789         /* Calc sr entries for one plane configs */
1790         if (HAS_FW_BLC(dev) && enabled) {
1791                 /* self-refresh has much higher latency */
1792                 static const int sr_latency_ns = 6000;
1793                 const struct drm_display_mode *adjusted_mode =
1794                         &to_intel_crtc(enabled)->config.adjusted_mode;
1795                 int clock = adjusted_mode->crtc_clock;
1796                 int htotal = adjusted_mode->crtc_htotal;
1797                 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
1798                 int pixel_size = enabled->primary->fb->bits_per_pixel / 8;
1799                 unsigned long line_time_us;
1800                 int entries;
1801
1802                 line_time_us = max(htotal * 1000 / clock, 1);
1803
1804                 /* Use ns/us then divide to preserve precision */
1805                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1806                         pixel_size * hdisplay;
1807                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1808                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1809                 srwm = wm_info->fifo_size - entries;
1810                 if (srwm < 0)
1811                         srwm = 1;
1812
1813                 if (IS_I945G(dev) || IS_I945GM(dev))
1814                         I915_WRITE(FW_BLC_SELF,
1815                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1816                 else if (IS_I915GM(dev))
1817                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1818         }
1819
1820         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1821                       planea_wm, planeb_wm, cwm, srwm);
1822
1823         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1824         fwater_hi = (cwm & 0x1f);
1825
1826         /* Set request length to 8 cachelines per fetch */
1827         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1828         fwater_hi = fwater_hi | (1 << 8);
1829
1830         I915_WRITE(FW_BLC, fwater_lo);
1831         I915_WRITE(FW_BLC2, fwater_hi);
1832
1833         if (enabled)
1834                 intel_set_memory_cxsr(dev_priv, true);
1835 }
1836
1837 static void i845_update_wm(struct drm_crtc *unused_crtc)
1838 {
1839         struct drm_device *dev = unused_crtc->dev;
1840         struct drm_i915_private *dev_priv = dev->dev_private;
1841         struct drm_crtc *crtc;
1842         const struct drm_display_mode *adjusted_mode;
1843         uint32_t fwater_lo;
1844         int planea_wm;
1845
1846         crtc = single_enabled_crtc(dev);
1847         if (crtc == NULL)
1848                 return;
1849
1850         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1851         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1852                                        &i845_wm_info,
1853                                        dev_priv->display.get_fifo_size(dev, 0),
1854                                        4, pessimal_latency_ns);
1855         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1856         fwater_lo |= (3<<8) | planea_wm;
1857
1858         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1859
1860         I915_WRITE(FW_BLC, fwater_lo);
1861 }
1862
1863 static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1864                                     struct drm_crtc *crtc)
1865 {
1866         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1867         uint32_t pixel_rate;
1868
1869         pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
1870
1871         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1872          * adjust the pixel_rate here. */
1873
1874         if (intel_crtc->config.pch_pfit.enabled) {
1875                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1876                 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
1877
1878                 pipe_w = intel_crtc->config.pipe_src_w;
1879                 pipe_h = intel_crtc->config.pipe_src_h;
1880                 pfit_w = (pfit_size >> 16) & 0xFFFF;
1881                 pfit_h = pfit_size & 0xFFFF;
1882                 if (pipe_w < pfit_w)
1883                         pipe_w = pfit_w;
1884                 if (pipe_h < pfit_h)
1885                         pipe_h = pfit_h;
1886
1887                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1888                                      pfit_w * pfit_h);
1889         }
1890
1891         return pixel_rate;
1892 }
1893
1894 /* latency must be in 0.1us units. */
1895 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
1896                                uint32_t latency)
1897 {
1898         uint64_t ret;
1899
1900         if (WARN(latency == 0, "Latency value missing\n"))
1901                 return UINT_MAX;
1902
1903         ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1904         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1905
1906         return ret;
1907 }
1908
1909 /* latency must be in 0.1us units. */
1910 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1911                                uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1912                                uint32_t latency)
1913 {
1914         uint32_t ret;
1915
1916         if (WARN(latency == 0, "Latency value missing\n"))
1917                 return UINT_MAX;
1918
1919         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1920         ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1921         ret = DIV_ROUND_UP(ret, 64) + 2;
1922         return ret;
1923 }
1924
1925 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1926                            uint8_t bytes_per_pixel)
1927 {
1928         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1929 }
1930
1931 struct ilk_pipe_wm_parameters {
1932         bool active;
1933         uint32_t pipe_htotal;
1934         uint32_t pixel_rate;
1935         struct intel_plane_wm_parameters pri;
1936         struct intel_plane_wm_parameters spr;
1937         struct intel_plane_wm_parameters cur;
1938 };
1939
1940 struct ilk_wm_maximums {
1941         uint16_t pri;
1942         uint16_t spr;
1943         uint16_t cur;
1944         uint16_t fbc;
1945 };
1946
1947 /* used in computing the new watermarks state */
1948 struct intel_wm_config {
1949         unsigned int num_pipes_active;
1950         bool sprites_enabled;
1951         bool sprites_scaled;
1952 };
1953
1954 /*
1955  * For both WM_PIPE and WM_LP.
1956  * mem_value must be in 0.1us units.
1957  */
1958 static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
1959                                    uint32_t mem_value,
1960                                    bool is_lp)
1961 {
1962         uint32_t method1, method2;
1963
1964         if (!params->active || !params->pri.enabled)
1965                 return 0;
1966
1967         method1 = ilk_wm_method1(params->pixel_rate,
1968                                  params->pri.bytes_per_pixel,
1969                                  mem_value);
1970
1971         if (!is_lp)
1972                 return method1;
1973
1974         method2 = ilk_wm_method2(params->pixel_rate,
1975                                  params->pipe_htotal,
1976                                  params->pri.horiz_pixels,
1977                                  params->pri.bytes_per_pixel,
1978                                  mem_value);
1979
1980         return min(method1, method2);
1981 }
1982
1983 /*
1984  * For both WM_PIPE and WM_LP.
1985  * mem_value must be in 0.1us units.
1986  */
1987 static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
1988                                    uint32_t mem_value)
1989 {
1990         uint32_t method1, method2;
1991
1992         if (!params->active || !params->spr.enabled)
1993                 return 0;
1994
1995         method1 = ilk_wm_method1(params->pixel_rate,
1996                                  params->spr.bytes_per_pixel,
1997                                  mem_value);
1998         method2 = ilk_wm_method2(params->pixel_rate,
1999                                  params->pipe_htotal,
2000                                  params->spr.horiz_pixels,
2001                                  params->spr.bytes_per_pixel,
2002                                  mem_value);
2003         return min(method1, method2);
2004 }
2005
2006 /*
2007  * For both WM_PIPE and WM_LP.
2008  * mem_value must be in 0.1us units.
2009  */
2010 static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
2011                                    uint32_t mem_value)
2012 {
2013         if (!params->active || !params->cur.enabled)
2014                 return 0;
2015
2016         return ilk_wm_method2(params->pixel_rate,
2017                               params->pipe_htotal,
2018                               params->cur.horiz_pixels,
2019                               params->cur.bytes_per_pixel,
2020                               mem_value);
2021 }
2022
2023 /* Only for WM_LP. */
2024 static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
2025                                    uint32_t pri_val)
2026 {
2027         if (!params->active || !params->pri.enabled)
2028                 return 0;
2029
2030         return ilk_wm_fbc(pri_val,
2031                           params->pri.horiz_pixels,
2032                           params->pri.bytes_per_pixel);
2033 }
2034
2035 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
2036 {
2037         if (INTEL_INFO(dev)->gen >= 8)
2038                 return 3072;
2039         else if (INTEL_INFO(dev)->gen >= 7)
2040                 return 768;
2041         else
2042                 return 512;
2043 }
2044
2045 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
2046                                          int level, bool is_sprite)
2047 {
2048         if (INTEL_INFO(dev)->gen >= 8)
2049                 /* BDW primary/sprite plane watermarks */
2050                 return level == 0 ? 255 : 2047;
2051         else if (INTEL_INFO(dev)->gen >= 7)
2052                 /* IVB/HSW primary/sprite plane watermarks */
2053                 return level == 0 ? 127 : 1023;
2054         else if (!is_sprite)
2055                 /* ILK/SNB primary plane watermarks */
2056                 return level == 0 ? 127 : 511;
2057         else
2058                 /* ILK/SNB sprite plane watermarks */
2059                 return level == 0 ? 63 : 255;
2060 }
2061
2062 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
2063                                           int level)
2064 {
2065         if (INTEL_INFO(dev)->gen >= 7)
2066                 return level == 0 ? 63 : 255;
2067         else
2068                 return level == 0 ? 31 : 63;
2069 }
2070
2071 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
2072 {
2073         if (INTEL_INFO(dev)->gen >= 8)
2074                 return 31;
2075         else
2076                 return 15;
2077 }
2078
2079 /* Calculate the maximum primary/sprite plane watermark */
2080 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
2081                                      int level,
2082                                      const struct intel_wm_config *config,
2083                                      enum intel_ddb_partitioning ddb_partitioning,
2084                                      bool is_sprite)
2085 {
2086         unsigned int fifo_size = ilk_display_fifo_size(dev);
2087
2088         /* if sprites aren't enabled, sprites get nothing */
2089         if (is_sprite && !config->sprites_enabled)
2090                 return 0;
2091
2092         /* HSW allows LP1+ watermarks even with multiple pipes */
2093         if (level == 0 || config->num_pipes_active > 1) {
2094                 fifo_size /= INTEL_INFO(dev)->num_pipes;
2095
2096                 /*
2097                  * For some reason the non self refresh
2098                  * FIFO size is only half of the self
2099                  * refresh FIFO size on ILK/SNB.
2100                  */
2101                 if (INTEL_INFO(dev)->gen <= 6)
2102                         fifo_size /= 2;
2103         }
2104
2105         if (config->sprites_enabled) {
2106                 /* level 0 is always calculated with 1:1 split */
2107                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2108                         if (is_sprite)
2109                                 fifo_size *= 5;
2110                         fifo_size /= 6;
2111                 } else {
2112                         fifo_size /= 2;
2113                 }
2114         }
2115
2116         /* clamp to max that the registers can hold */
2117         return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
2118 }
2119
2120 /* Calculate the maximum cursor plane watermark */
2121 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
2122                                       int level,
2123                                       const struct intel_wm_config *config)
2124 {
2125         /* HSW LP1+ watermarks w/ multiple pipes */
2126         if (level > 0 && config->num_pipes_active > 1)
2127                 return 64;
2128
2129         /* otherwise just report max that registers can hold */
2130         return ilk_cursor_wm_reg_max(dev, level);
2131 }
2132
2133 static void ilk_compute_wm_maximums(const struct drm_device *dev,
2134                                     int level,
2135                                     const struct intel_wm_config *config,
2136                                     enum intel_ddb_partitioning ddb_partitioning,
2137                                     struct ilk_wm_maximums *max)
2138 {
2139         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
2140         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
2141         max->cur = ilk_cursor_wm_max(dev, level, config);
2142         max->fbc = ilk_fbc_wm_reg_max(dev);
2143 }
2144
2145 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
2146                                         int level,
2147                                         struct ilk_wm_maximums *max)
2148 {
2149         max->pri = ilk_plane_wm_reg_max(dev, level, false);
2150         max->spr = ilk_plane_wm_reg_max(dev, level, true);
2151         max->cur = ilk_cursor_wm_reg_max(dev, level);
2152         max->fbc = ilk_fbc_wm_reg_max(dev);
2153 }
2154
2155 static bool ilk_validate_wm_level(int level,
2156                                   const struct ilk_wm_maximums *max,
2157                                   struct intel_wm_level *result)
2158 {
2159         bool ret;
2160
2161         /* already determined to be invalid? */
2162         if (!result->enable)
2163                 return false;
2164
2165         result->enable = result->pri_val <= max->pri &&
2166                          result->spr_val <= max->spr &&
2167                          result->cur_val <= max->cur;
2168
2169         ret = result->enable;
2170
2171         /*
2172          * HACK until we can pre-compute everything,
2173          * and thus fail gracefully if LP0 watermarks
2174          * are exceeded...
2175          */
2176         if (level == 0 && !result->enable) {
2177                 if (result->pri_val > max->pri)
2178                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2179                                       level, result->pri_val, max->pri);
2180                 if (result->spr_val > max->spr)
2181                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2182                                       level, result->spr_val, max->spr);
2183                 if (result->cur_val > max->cur)
2184                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2185                                       level, result->cur_val, max->cur);
2186
2187                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2188                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2189                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2190                 result->enable = true;
2191         }
2192
2193         return ret;
2194 }
2195
2196 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2197                                  int level,
2198                                  const struct ilk_pipe_wm_parameters *p,
2199                                  struct intel_wm_level *result)
2200 {
2201         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2202         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2203         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2204
2205         /* WM1+ latency values stored in 0.5us units */
2206         if (level > 0) {
2207                 pri_latency *= 5;
2208                 spr_latency *= 5;
2209                 cur_latency *= 5;
2210         }
2211
2212         result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2213         result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2214         result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2215         result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2216         result->enable = true;
2217 }
2218
2219 static uint32_t
2220 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2221 {
2222         struct drm_i915_private *dev_priv = dev->dev_private;
2223         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2224         struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
2225         u32 linetime, ips_linetime;
2226
2227         if (!intel_crtc_active(crtc))
2228                 return 0;
2229
2230         /* The WM are computed with base on how long it takes to fill a single
2231          * row at the given clock rate, multiplied by 8.
2232          * */
2233         linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2234                                      mode->crtc_clock);
2235         ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2236                                          intel_ddi_get_cdclk_freq(dev_priv));
2237
2238         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2239                PIPE_WM_LINETIME_TIME(linetime);
2240 }
2241
2242 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2243 {
2244         struct drm_i915_private *dev_priv = dev->dev_private;
2245
2246         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2247                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2248
2249                 wm[0] = (sskpd >> 56) & 0xFF;
2250                 if (wm[0] == 0)
2251                         wm[0] = sskpd & 0xF;
2252                 wm[1] = (sskpd >> 4) & 0xFF;
2253                 wm[2] = (sskpd >> 12) & 0xFF;
2254                 wm[3] = (sskpd >> 20) & 0x1FF;
2255                 wm[4] = (sskpd >> 32) & 0x1FF;
2256         } else if (INTEL_INFO(dev)->gen >= 6) {
2257                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2258
2259                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2260                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2261                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2262                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2263         } else if (INTEL_INFO(dev)->gen >= 5) {
2264                 uint32_t mltr = I915_READ(MLTR_ILK);
2265
2266                 /* ILK primary LP0 latency is 700 ns */
2267                 wm[0] = 7;
2268                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2269                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2270         }
2271 }
2272
2273 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2274 {
2275         /* ILK sprite LP0 latency is 1300 ns */
2276         if (INTEL_INFO(dev)->gen == 5)
2277                 wm[0] = 13;
2278 }
2279
2280 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2281 {
2282         /* ILK cursor LP0 latency is 1300 ns */
2283         if (INTEL_INFO(dev)->gen == 5)
2284                 wm[0] = 13;
2285
2286         /* WaDoubleCursorLP3Latency:ivb */
2287         if (IS_IVYBRIDGE(dev))
2288                 wm[3] *= 2;
2289 }
2290
2291 int ilk_wm_max_level(const struct drm_device *dev)
2292 {
2293         /* how many WM levels are we expecting */
2294         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2295                 return 4;
2296         else if (INTEL_INFO(dev)->gen >= 6)
2297                 return 3;
2298         else
2299                 return 2;
2300 }
2301 static void intel_print_wm_latency(struct drm_device *dev,
2302                                    const char *name,
2303                                    const uint16_t wm[5])
2304 {
2305         int level, max_level = ilk_wm_max_level(dev);
2306
2307         for (level = 0; level <= max_level; level++) {
2308                 unsigned int latency = wm[level];
2309
2310                 if (latency == 0) {
2311                         DRM_ERROR("%s WM%d latency not provided\n",
2312                                   name, level);
2313                         continue;
2314                 }
2315
2316                 /* WM1+ latency values in 0.5us units */
2317                 if (level > 0)
2318                         latency *= 5;
2319
2320                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2321                               name, level, wm[level],
2322                               latency / 10, latency % 10);
2323         }
2324 }
2325
2326 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2327                                     uint16_t wm[5], uint16_t min)
2328 {
2329         int level, max_level = ilk_wm_max_level(dev_priv->dev);
2330
2331         if (wm[0] >= min)
2332                 return false;
2333
2334         wm[0] = max(wm[0], min);
2335         for (level = 1; level <= max_level; level++)
2336                 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2337
2338         return true;
2339 }
2340
2341 static void snb_wm_latency_quirk(struct drm_device *dev)
2342 {
2343         struct drm_i915_private *dev_priv = dev->dev_private;
2344         bool changed;
2345
2346         /*
2347          * The BIOS provided WM memory latency values are often
2348          * inadequate for high resolution displays. Adjust them.
2349          */
2350         changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2351                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2352                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2353
2354         if (!changed)
2355                 return;
2356
2357         DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2358         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2359         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2360         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2361 }
2362
2363 static void ilk_setup_wm_latency(struct drm_device *dev)
2364 {
2365         struct drm_i915_private *dev_priv = dev->dev_private;
2366
2367         intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2368
2369         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2370                sizeof(dev_priv->wm.pri_latency));
2371         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2372                sizeof(dev_priv->wm.pri_latency));
2373
2374         intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2375         intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2376
2377         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2378         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2379         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2380
2381         if (IS_GEN6(dev))
2382                 snb_wm_latency_quirk(dev);
2383 }
2384
2385 static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2386                                       struct ilk_pipe_wm_parameters *p)
2387 {
2388         struct drm_device *dev = crtc->dev;
2389         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2390         enum pipe pipe = intel_crtc->pipe;
2391         struct drm_plane *plane;
2392
2393         if (!intel_crtc_active(crtc))
2394                 return;
2395
2396         p->active = true;
2397         p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
2398         p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2399         p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8;
2400         p->cur.bytes_per_pixel = 4;
2401         p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2402         p->cur.horiz_pixels = intel_crtc->cursor_width;
2403         /* TODO: for now, assume primary and cursor planes are always enabled. */
2404         p->pri.enabled = true;
2405         p->cur.enabled = true;
2406
2407         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
2408                 struct intel_plane *intel_plane = to_intel_plane(plane);
2409
2410                 if (intel_plane->pipe == pipe) {
2411                         p->spr = intel_plane->wm;
2412                         break;
2413                 }
2414         }
2415 }
2416
2417 static void ilk_compute_wm_config(struct drm_device *dev,
2418                                   struct intel_wm_config *config)
2419 {
2420         struct intel_crtc *intel_crtc;
2421
2422         /* Compute the currently _active_ config */
2423         for_each_intel_crtc(dev, intel_crtc) {
2424                 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
2425
2426                 if (!wm->pipe_enabled)
2427                         continue;
2428
2429                 config->sprites_enabled |= wm->sprites_enabled;
2430                 config->sprites_scaled |= wm->sprites_scaled;
2431                 config->num_pipes_active++;
2432         }
2433 }
2434
2435 /* Compute new watermarks for the pipe */
2436 static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2437                                   const struct ilk_pipe_wm_parameters *params,
2438                                   struct intel_pipe_wm *pipe_wm)
2439 {
2440         struct drm_device *dev = crtc->dev;
2441         const struct drm_i915_private *dev_priv = dev->dev_private;
2442         int level, max_level = ilk_wm_max_level(dev);
2443         /* LP0 watermark maximums depend on this pipe alone */
2444         struct intel_wm_config config = {
2445                 .num_pipes_active = 1,
2446                 .sprites_enabled = params->spr.enabled,
2447                 .sprites_scaled = params->spr.scaled,
2448         };
2449         struct ilk_wm_maximums max;
2450
2451         pipe_wm->pipe_enabled = params->active;
2452         pipe_wm->sprites_enabled = params->spr.enabled;
2453         pipe_wm->sprites_scaled = params->spr.scaled;
2454
2455         /* ILK/SNB: LP2+ watermarks only w/o sprites */
2456         if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2457                 max_level = 1;
2458
2459         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2460         if (params->spr.scaled)
2461                 max_level = 0;
2462
2463         ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
2464
2465         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2466                 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2467
2468         /* LP0 watermarks always use 1/2 DDB partitioning */
2469         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2470
2471         /* At least LP0 must be valid */
2472         if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2473                 return false;
2474
2475         ilk_compute_wm_reg_maximums(dev, 1, &max);
2476
2477         for (level = 1; level <= max_level; level++) {
2478                 struct intel_wm_level wm = {};
2479
2480                 ilk_compute_wm_level(dev_priv, level, params, &wm);
2481
2482                 /*
2483                  * Disable any watermark level that exceeds the
2484                  * register maximums since such watermarks are
2485                  * always invalid.
2486                  */
2487                 if (!ilk_validate_wm_level(level, &max, &wm))
2488                         break;
2489
2490                 pipe_wm->wm[level] = wm;
2491         }
2492
2493         return true;
2494 }
2495
2496 /*
2497  * Merge the watermarks from all active pipes for a specific level.
2498  */
2499 static void ilk_merge_wm_level(struct drm_device *dev,
2500                                int level,
2501                                struct intel_wm_level *ret_wm)
2502 {
2503         const struct intel_crtc *intel_crtc;
2504
2505         ret_wm->enable = true;
2506
2507         for_each_intel_crtc(dev, intel_crtc) {
2508                 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2509                 const struct intel_wm_level *wm = &active->wm[level];
2510
2511                 if (!active->pipe_enabled)
2512                         continue;
2513
2514                 /*
2515                  * The watermark values may have been used in the past,
2516                  * so we must maintain them in the registers for some
2517                  * time even if the level is now disabled.
2518                  */
2519                 if (!wm->enable)
2520                         ret_wm->enable = false;
2521
2522                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2523                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2524                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2525                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2526         }
2527 }
2528
2529 /*
2530  * Merge all low power watermarks for all active pipes.
2531  */
2532 static void ilk_wm_merge(struct drm_device *dev,
2533                          const struct intel_wm_config *config,
2534                          const struct ilk_wm_maximums *max,
2535                          struct intel_pipe_wm *merged)
2536 {
2537         int level, max_level = ilk_wm_max_level(dev);
2538         int last_enabled_level = max_level;
2539
2540         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2541         if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2542             config->num_pipes_active > 1)
2543                 return;
2544
2545         /* ILK: FBC WM must be disabled always */
2546         merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2547
2548         /* merge each WM1+ level */
2549         for (level = 1; level <= max_level; level++) {
2550                 struct intel_wm_level *wm = &merged->wm[level];
2551
2552                 ilk_merge_wm_level(dev, level, wm);
2553
2554                 if (level > last_enabled_level)
2555                         wm->enable = false;
2556                 else if (!ilk_validate_wm_level(level, max, wm))
2557                         /* make sure all following levels get disabled */
2558                         last_enabled_level = level - 1;
2559
2560                 /*
2561                  * The spec says it is preferred to disable
2562                  * FBC WMs instead of disabling a WM level.
2563                  */
2564                 if (wm->fbc_val > max->fbc) {
2565                         if (wm->enable)
2566                                 merged->fbc_wm_enabled = false;
2567                         wm->fbc_val = 0;
2568                 }
2569         }
2570
2571         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2572         /*
2573          * FIXME this is racy. FBC might get enabled later.
2574          * What we should check here is whether FBC can be
2575          * enabled sometime later.
2576          */
2577         if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2578                 for (level = 2; level <= max_level; level++) {
2579                         struct intel_wm_level *wm = &merged->wm[level];
2580
2581                         wm->enable = false;
2582                 }
2583         }
2584 }
2585
2586 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2587 {
2588         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2589         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2590 }
2591
2592 /* The value we need to program into the WM_LPx latency field */
2593 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2594 {
2595         struct drm_i915_private *dev_priv = dev->dev_private;
2596
2597         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2598                 return 2 * level;
2599         else
2600                 return dev_priv->wm.pri_latency[level];
2601 }
2602
2603 static void ilk_compute_wm_results(struct drm_device *dev,
2604                                    const struct intel_pipe_wm *merged,
2605                                    enum intel_ddb_partitioning partitioning,
2606                                    struct ilk_wm_values *results)
2607 {
2608         struct intel_crtc *intel_crtc;
2609         int level, wm_lp;
2610
2611         results->enable_fbc_wm = merged->fbc_wm_enabled;
2612         results->partitioning = partitioning;
2613
2614         /* LP1+ register values */
2615         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2616                 const struct intel_wm_level *r;
2617
2618                 level = ilk_wm_lp_to_level(wm_lp, merged);
2619
2620                 r = &merged->wm[level];
2621
2622                 /*
2623                  * Maintain the watermark values even if the level is
2624                  * disabled. Doing otherwise could cause underruns.
2625                  */
2626                 results->wm_lp[wm_lp - 1] =
2627                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2628                         (r->pri_val << WM1_LP_SR_SHIFT) |
2629                         r->cur_val;
2630
2631                 if (r->enable)
2632                         results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2633
2634                 if (INTEL_INFO(dev)->gen >= 8)
2635                         results->wm_lp[wm_lp - 1] |=
2636                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2637                 else
2638                         results->wm_lp[wm_lp - 1] |=
2639                                 r->fbc_val << WM1_LP_FBC_SHIFT;
2640
2641                 /*
2642                  * Always set WM1S_LP_EN when spr_val != 0, even if the
2643                  * level is disabled. Doing otherwise could cause underruns.
2644                  */
2645                 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2646                         WARN_ON(wm_lp != 1);
2647                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2648                 } else
2649                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2650         }
2651
2652         /* LP0 register values */
2653         for_each_intel_crtc(dev, intel_crtc) {
2654                 enum pipe pipe = intel_crtc->pipe;
2655                 const struct intel_wm_level *r =
2656                         &intel_crtc->wm.active.wm[0];
2657
2658                 if (WARN_ON(!r->enable))
2659                         continue;
2660
2661                 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2662
2663                 results->wm_pipe[pipe] =
2664                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2665                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2666                         r->cur_val;
2667         }
2668 }
2669
2670 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2671  * case both are at the same level. Prefer r1 in case they're the same. */
2672 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2673                                                   struct intel_pipe_wm *r1,
2674                                                   struct intel_pipe_wm *r2)
2675 {
2676         int level, max_level = ilk_wm_max_level(dev);
2677         int level1 = 0, level2 = 0;
2678
2679         for (level = 1; level <= max_level; level++) {
2680                 if (r1->wm[level].enable)
2681                         level1 = level;
2682                 if (r2->wm[level].enable)
2683                         level2 = level;
2684         }
2685
2686         if (level1 == level2) {
2687                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2688                         return r2;
2689                 else
2690                         return r1;
2691         } else if (level1 > level2) {
2692                 return r1;
2693         } else {
2694                 return r2;
2695         }
2696 }
2697
2698 /* dirty bits used to track which watermarks need changes */
2699 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2700 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2701 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2702 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2703 #define WM_DIRTY_FBC (1 << 24)
2704 #define WM_DIRTY_DDB (1 << 25)
2705
2706 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2707                                          const struct ilk_wm_values *old,
2708                                          const struct ilk_wm_values *new)
2709 {
2710         unsigned int dirty = 0;
2711         enum pipe pipe;
2712         int wm_lp;
2713
2714         for_each_pipe(dev_priv, pipe) {
2715                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2716                         dirty |= WM_DIRTY_LINETIME(pipe);
2717                         /* Must disable LP1+ watermarks too */
2718                         dirty |= WM_DIRTY_LP_ALL;
2719                 }
2720
2721                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2722                         dirty |= WM_DIRTY_PIPE(pipe);
2723                         /* Must disable LP1+ watermarks too */
2724                         dirty |= WM_DIRTY_LP_ALL;
2725                 }
2726         }
2727
2728         if (old->enable_fbc_wm != new->enable_fbc_wm) {
2729                 dirty |= WM_DIRTY_FBC;
2730                 /* Must disable LP1+ watermarks too */
2731                 dirty |= WM_DIRTY_LP_ALL;
2732         }
2733
2734         if (old->partitioning != new->partitioning) {
2735                 dirty |= WM_DIRTY_DDB;
2736                 /* Must disable LP1+ watermarks too */
2737                 dirty |= WM_DIRTY_LP_ALL;
2738         }
2739
2740         /* LP1+ watermarks already deemed dirty, no need to continue */
2741         if (dirty & WM_DIRTY_LP_ALL)
2742                 return dirty;
2743
2744         /* Find the lowest numbered LP1+ watermark in need of an update... */
2745         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2746                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2747                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2748                         break;
2749         }
2750
2751         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2752         for (; wm_lp <= 3; wm_lp++)
2753                 dirty |= WM_DIRTY_LP(wm_lp);
2754
2755         return dirty;
2756 }
2757
2758 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2759                                unsigned int dirty)
2760 {
2761         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2762         bool changed = false;
2763
2764         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2765                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2766                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2767                 changed = true;
2768         }
2769         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2770                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2771                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2772                 changed = true;
2773         }
2774         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2775                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2776                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2777                 changed = true;
2778         }
2779
2780         /*
2781          * Don't touch WM1S_LP_EN here.
2782          * Doing so could cause underruns.
2783          */
2784
2785         return changed;
2786 }
2787
2788 /*
2789  * The spec says we shouldn't write when we don't need, because every write
2790  * causes WMs to be re-evaluated, expending some power.
2791  */
2792 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2793                                 struct ilk_wm_values *results)
2794 {
2795         struct drm_device *dev = dev_priv->dev;
2796         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2797         unsigned int dirty;
2798         uint32_t val;
2799
2800         dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2801         if (!dirty)
2802                 return;
2803
2804         _ilk_disable_lp_wm(dev_priv, dirty);
2805
2806         if (dirty & WM_DIRTY_PIPE(PIPE_A))
2807                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2808         if (dirty & WM_DIRTY_PIPE(PIPE_B))
2809                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2810         if (dirty & WM_DIRTY_PIPE(PIPE_C))
2811                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2812
2813         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2814                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2815         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2816                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2817         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2818                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2819
2820         if (dirty & WM_DIRTY_DDB) {
2821                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2822                         val = I915_READ(WM_MISC);
2823                         if (results->partitioning == INTEL_DDB_PART_1_2)
2824                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
2825                         else
2826                                 val |= WM_MISC_DATA_PARTITION_5_6;
2827                         I915_WRITE(WM_MISC, val);
2828                 } else {
2829                         val = I915_READ(DISP_ARB_CTL2);
2830                         if (results->partitioning == INTEL_DDB_PART_1_2)
2831                                 val &= ~DISP_DATA_PARTITION_5_6;
2832                         else
2833                                 val |= DISP_DATA_PARTITION_5_6;
2834                         I915_WRITE(DISP_ARB_CTL2, val);
2835                 }
2836         }
2837
2838         if (dirty & WM_DIRTY_FBC) {
2839                 val = I915_READ(DISP_ARB_CTL);
2840                 if (results->enable_fbc_wm)
2841                         val &= ~DISP_FBC_WM_DIS;
2842                 else
2843                         val |= DISP_FBC_WM_DIS;
2844                 I915_WRITE(DISP_ARB_CTL, val);
2845         }
2846
2847         if (dirty & WM_DIRTY_LP(1) &&
2848             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2849                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2850
2851         if (INTEL_INFO(dev)->gen >= 7) {
2852                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2853                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2854                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2855                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2856         }
2857
2858         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2859                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2860         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2861                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2862         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2863                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2864
2865         dev_priv->wm.hw = *results;
2866 }
2867
2868 static bool ilk_disable_lp_wm(struct drm_device *dev)
2869 {
2870         struct drm_i915_private *dev_priv = dev->dev_private;
2871
2872         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2873 }
2874
2875 static void ilk_update_wm(struct drm_crtc *crtc)
2876 {
2877         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2878         struct drm_device *dev = crtc->dev;
2879         struct drm_i915_private *dev_priv = dev->dev_private;
2880         struct ilk_wm_maximums max;
2881         struct ilk_pipe_wm_parameters params = {};
2882         struct ilk_wm_values results = {};
2883         enum intel_ddb_partitioning partitioning;
2884         struct intel_pipe_wm pipe_wm = {};
2885         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
2886         struct intel_wm_config config = {};
2887
2888         ilk_compute_wm_parameters(crtc, &params);
2889
2890         intel_compute_pipe_wm(crtc, &params, &pipe_wm);
2891
2892         if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2893                 return;
2894
2895         intel_crtc->wm.active = pipe_wm;
2896
2897         ilk_compute_wm_config(dev, &config);
2898
2899         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
2900         ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
2901
2902         /* 5/6 split only in single pipe config on IVB+ */
2903         if (INTEL_INFO(dev)->gen >= 7 &&
2904             config.num_pipes_active == 1 && config.sprites_enabled) {
2905                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
2906                 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
2907
2908                 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
2909         } else {
2910                 best_lp_wm = &lp_wm_1_2;
2911         }
2912
2913         partitioning = (best_lp_wm == &lp_wm_1_2) ?
2914                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
2915
2916         ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
2917
2918         ilk_write_wm_values(dev_priv, &results);
2919 }
2920
2921 static void
2922 ilk_update_sprite_wm(struct drm_plane *plane,
2923                      struct drm_crtc *crtc,
2924                      uint32_t sprite_width, uint32_t sprite_height,
2925                      int pixel_size, bool enabled, bool scaled)
2926 {
2927         struct drm_device *dev = plane->dev;
2928         struct intel_plane *intel_plane = to_intel_plane(plane);
2929
2930         intel_plane->wm.enabled = enabled;
2931         intel_plane->wm.scaled = scaled;
2932         intel_plane->wm.horiz_pixels = sprite_width;
2933         intel_plane->wm.vert_pixels = sprite_width;
2934         intel_plane->wm.bytes_per_pixel = pixel_size;
2935
2936         /*
2937          * IVB workaround: must disable low power watermarks for at least
2938          * one frame before enabling scaling.  LP watermarks can be re-enabled
2939          * when scaling is disabled.
2940          *
2941          * WaCxSRDisabledForSpriteScaling:ivb
2942          */
2943         if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
2944                 intel_wait_for_vblank(dev, intel_plane->pipe);
2945
2946         ilk_update_wm(crtc);
2947 }
2948
2949 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
2950 {
2951         struct drm_device *dev = crtc->dev;
2952         struct drm_i915_private *dev_priv = dev->dev_private;
2953         struct ilk_wm_values *hw = &dev_priv->wm.hw;
2954         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2955         struct intel_pipe_wm *active = &intel_crtc->wm.active;
2956         enum pipe pipe = intel_crtc->pipe;
2957         static const unsigned int wm0_pipe_reg[] = {
2958                 [PIPE_A] = WM0_PIPEA_ILK,
2959                 [PIPE_B] = WM0_PIPEB_ILK,
2960                 [PIPE_C] = WM0_PIPEC_IVB,
2961         };
2962
2963         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
2964         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2965                 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
2966
2967         active->pipe_enabled = intel_crtc_active(crtc);
2968
2969         if (active->pipe_enabled) {
2970                 u32 tmp = hw->wm_pipe[pipe];
2971
2972                 /*
2973                  * For active pipes LP0 watermark is marked as
2974                  * enabled, and LP1+ watermaks as disabled since
2975                  * we can't really reverse compute them in case
2976                  * multiple pipes are active.
2977                  */
2978                 active->wm[0].enable = true;
2979                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
2980                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
2981                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
2982                 active->linetime = hw->wm_linetime[pipe];
2983         } else {
2984                 int level, max_level = ilk_wm_max_level(dev);
2985
2986                 /*
2987                  * For inactive pipes, all watermark levels
2988                  * should be marked as enabled but zeroed,
2989                  * which is what we'd compute them to.
2990                  */
2991                 for (level = 0; level <= max_level; level++)
2992                         active->wm[level].enable = true;
2993         }
2994 }
2995
2996 void ilk_wm_get_hw_state(struct drm_device *dev)
2997 {
2998         struct drm_i915_private *dev_priv = dev->dev_private;
2999         struct ilk_wm_values *hw = &dev_priv->wm.hw;
3000         struct drm_crtc *crtc;
3001
3002         for_each_crtc(dev, crtc)
3003                 ilk_pipe_wm_get_hw_state(crtc);
3004
3005         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
3006         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
3007         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
3008
3009         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
3010         if (INTEL_INFO(dev)->gen >= 7) {
3011                 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
3012                 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
3013         }
3014
3015         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3016                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
3017                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3018         else if (IS_IVYBRIDGE(dev))
3019                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
3020                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3021
3022         hw->enable_fbc_wm =
3023                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
3024 }
3025
3026 /**
3027  * intel_update_watermarks - update FIFO watermark values based on current modes
3028  *
3029  * Calculate watermark values for the various WM regs based on current mode
3030  * and plane configuration.
3031  *
3032  * There are several cases to deal with here:
3033  *   - normal (i.e. non-self-refresh)
3034  *   - self-refresh (SR) mode
3035  *   - lines are large relative to FIFO size (buffer can hold up to 2)
3036  *   - lines are small relative to FIFO size (buffer can hold more than 2
3037  *     lines), so need to account for TLB latency
3038  *
3039  *   The normal calculation is:
3040  *     watermark = dotclock * bytes per pixel * latency
3041  *   where latency is platform & configuration dependent (we assume pessimal
3042  *   values here).
3043  *
3044  *   The SR calculation is:
3045  *     watermark = (trunc(latency/line time)+1) * surface width *
3046  *       bytes per pixel
3047  *   where
3048  *     line time = htotal / dotclock
3049  *     surface width = hdisplay for normal plane and 64 for cursor
3050  *   and latency is assumed to be high, as above.
3051  *
3052  * The final value programmed to the register should always be rounded up,
3053  * and include an extra 2 entries to account for clock crossings.
3054  *
3055  * We don't use the sprite, so we can ignore that.  And on Crestline we have
3056  * to set the non-SR watermarks to 8.
3057  */
3058 void intel_update_watermarks(struct drm_crtc *crtc)
3059 {
3060         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
3061
3062         if (dev_priv->display.update_wm)
3063                 dev_priv->display.update_wm(crtc);
3064 }
3065
3066 void intel_update_sprite_watermarks(struct drm_plane *plane,
3067                                     struct drm_crtc *crtc,
3068                                     uint32_t sprite_width,
3069                                     uint32_t sprite_height,
3070                                     int pixel_size,
3071                                     bool enabled, bool scaled)
3072 {
3073         struct drm_i915_private *dev_priv = plane->dev->dev_private;
3074
3075         if (dev_priv->display.update_sprite_wm)
3076                 dev_priv->display.update_sprite_wm(plane, crtc,
3077                                                    sprite_width, sprite_height,
3078                                                    pixel_size, enabled, scaled);
3079 }
3080
3081 static struct drm_i915_gem_object *
3082 intel_alloc_context_page(struct drm_device *dev)
3083 {
3084         struct drm_i915_gem_object *ctx;
3085         int ret;
3086
3087         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3088
3089         ctx = i915_gem_alloc_object(dev, 4096);
3090         if (!ctx) {
3091                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
3092                 return NULL;
3093         }
3094
3095         ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0);
3096         if (ret) {
3097                 DRM_ERROR("failed to pin power context: %d\n", ret);
3098                 goto err_unref;
3099         }
3100
3101         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
3102         if (ret) {
3103                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
3104                 goto err_unpin;
3105         }
3106
3107         return ctx;
3108
3109 err_unpin:
3110         i915_gem_object_ggtt_unpin(ctx);
3111 err_unref:
3112         drm_gem_object_unreference(&ctx->base);
3113         return NULL;
3114 }
3115
3116 /**
3117  * Lock protecting IPS related data structures
3118  */
3119 DEFINE_SPINLOCK(mchdev_lock);
3120
3121 /* Global for IPS driver to get at the current i915 device. Protected by
3122  * mchdev_lock. */
3123 static struct drm_i915_private *i915_mch_dev;
3124
3125 bool ironlake_set_drps(struct drm_device *dev, u8 val)
3126 {
3127         struct drm_i915_private *dev_priv = dev->dev_private;
3128         u16 rgvswctl;
3129
3130         assert_spin_locked(&mchdev_lock);
3131
3132         rgvswctl = I915_READ16(MEMSWCTL);
3133         if (rgvswctl & MEMCTL_CMD_STS) {
3134                 DRM_DEBUG("gpu busy, RCS change rejected\n");
3135                 return false; /* still busy with another command */
3136         }
3137
3138         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3139                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3140         I915_WRITE16(MEMSWCTL, rgvswctl);
3141         POSTING_READ16(MEMSWCTL);
3142
3143         rgvswctl |= MEMCTL_CMD_STS;
3144         I915_WRITE16(MEMSWCTL, rgvswctl);
3145
3146         return true;
3147 }
3148
3149 static void ironlake_enable_drps(struct drm_device *dev)
3150 {
3151         struct drm_i915_private *dev_priv = dev->dev_private;
3152         u32 rgvmodectl = I915_READ(MEMMODECTL);
3153         u8 fmax, fmin, fstart, vstart;
3154
3155         spin_lock_irq(&mchdev_lock);
3156
3157         /* Enable temp reporting */
3158         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3159         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3160
3161         /* 100ms RC evaluation intervals */
3162         I915_WRITE(RCUPEI, 100000);
3163         I915_WRITE(RCDNEI, 100000);
3164
3165         /* Set max/min thresholds to 90ms and 80ms respectively */
3166         I915_WRITE(RCBMAXAVG, 90000);
3167         I915_WRITE(RCBMINAVG, 80000);
3168
3169         I915_WRITE(MEMIHYST, 1);
3170
3171         /* Set up min, max, and cur for interrupt handling */
3172         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3173         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3174         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3175                 MEMMODE_FSTART_SHIFT;
3176
3177         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3178                 PXVFREQ_PX_SHIFT;
3179
3180         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3181         dev_priv->ips.fstart = fstart;
3182
3183         dev_priv->ips.max_delay = fstart;
3184         dev_priv->ips.min_delay = fmin;
3185         dev_priv->ips.cur_delay = fstart;
3186
3187         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3188                          fmax, fmin, fstart);
3189
3190         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3191
3192         /*
3193          * Interrupts will be enabled in ironlake_irq_postinstall
3194          */
3195
3196         I915_WRITE(VIDSTART, vstart);
3197         POSTING_READ(VIDSTART);
3198
3199         rgvmodectl |= MEMMODE_SWMODE_EN;
3200         I915_WRITE(MEMMODECTL, rgvmodectl);
3201
3202         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
3203                 DRM_ERROR("stuck trying to change perf mode\n");
3204         mdelay(1);
3205
3206         ironlake_set_drps(dev, fstart);
3207
3208         dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
3209                 I915_READ(0x112e0);
3210         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3211         dev_priv->ips.last_count2 = I915_READ(0x112f4);
3212         dev_priv->ips.last_time2 = ktime_get_raw_ns();
3213
3214         spin_unlock_irq(&mchdev_lock);
3215 }
3216
3217 static void ironlake_disable_drps(struct drm_device *dev)
3218 {
3219         struct drm_i915_private *dev_priv = dev->dev_private;
3220         u16 rgvswctl;
3221
3222         spin_lock_irq(&mchdev_lock);
3223
3224         rgvswctl = I915_READ16(MEMSWCTL);
3225
3226         /* Ack interrupts, disable EFC interrupt */
3227         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3228         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3229         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3230         I915_WRITE(DEIIR, DE_PCU_EVENT);
3231         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3232
3233         /* Go back to the starting frequency */
3234         ironlake_set_drps(dev, dev_priv->ips.fstart);
3235         mdelay(1);
3236         rgvswctl |= MEMCTL_CMD_STS;
3237         I915_WRITE(MEMSWCTL, rgvswctl);
3238         mdelay(1);
3239
3240         spin_unlock_irq(&mchdev_lock);
3241 }
3242
3243 /* There's a funny hw issue where the hw returns all 0 when reading from
3244  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3245  * ourselves, instead of doing a rmw cycle (which might result in us clearing
3246  * all limits and the gpu stuck at whatever frequency it is at atm).
3247  */
3248 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
3249 {
3250         u32 limits;
3251
3252         /* Only set the down limit when we've reached the lowest level to avoid
3253          * getting more interrupts, otherwise leave this clear. This prevents a
3254          * race in the hw when coming out of rc6: There's a tiny window where
3255          * the hw runs at the minimal clock before selecting the desired
3256          * frequency, if the down threshold expires in that window we will not
3257          * receive a down interrupt. */
3258         limits = dev_priv->rps.max_freq_softlimit << 24;
3259         if (val <= dev_priv->rps.min_freq_softlimit)
3260                 limits |= dev_priv->rps.min_freq_softlimit << 16;
3261
3262         return limits;
3263 }
3264
3265 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3266 {
3267         int new_power;
3268
3269         if (dev_priv->rps.is_bdw_sw_turbo)
3270                 return;
3271
3272         new_power = dev_priv->rps.power;
3273         switch (dev_priv->rps.power) {
3274         case LOW_POWER:
3275                 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
3276                         new_power = BETWEEN;
3277                 break;
3278
3279         case BETWEEN:
3280                 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
3281                         new_power = LOW_POWER;
3282                 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
3283                         new_power = HIGH_POWER;
3284                 break;
3285
3286         case HIGH_POWER:
3287                 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
3288                         new_power = BETWEEN;
3289                 break;
3290         }
3291         /* Max/min bins are special */
3292         if (val == dev_priv->rps.min_freq_softlimit)
3293                 new_power = LOW_POWER;
3294         if (val == dev_priv->rps.max_freq_softlimit)
3295                 new_power = HIGH_POWER;
3296         if (new_power == dev_priv->rps.power)
3297                 return;
3298
3299         /* Note the units here are not exactly 1us, but 1280ns. */
3300         switch (new_power) {
3301         case LOW_POWER:
3302                 /* Upclock if more than 95% busy over 16ms */
3303                 I915_WRITE(GEN6_RP_UP_EI, 12500);
3304                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3305
3306                 /* Downclock if less than 85% busy over 32ms */
3307                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3308                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3309
3310                 I915_WRITE(GEN6_RP_CONTROL,
3311                            GEN6_RP_MEDIA_TURBO |
3312                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
3313                            GEN6_RP_MEDIA_IS_GFX |
3314                            GEN6_RP_ENABLE |
3315                            GEN6_RP_UP_BUSY_AVG |
3316                            GEN6_RP_DOWN_IDLE_AVG);
3317                 break;
3318
3319         case BETWEEN:
3320                 /* Upclock if more than 90% busy over 13ms */
3321                 I915_WRITE(GEN6_RP_UP_EI, 10250);
3322                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3323
3324                 /* Downclock if less than 75% busy over 32ms */
3325                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3326                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3327
3328                 I915_WRITE(GEN6_RP_CONTROL,
3329                            GEN6_RP_MEDIA_TURBO |
3330                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
3331                            GEN6_RP_MEDIA_IS_GFX |
3332                            GEN6_RP_ENABLE |
3333                            GEN6_RP_UP_BUSY_AVG |
3334                            GEN6_RP_DOWN_IDLE_AVG);
3335                 break;
3336
3337         case HIGH_POWER:
3338                 /* Upclock if more than 85% busy over 10ms */
3339                 I915_WRITE(GEN6_RP_UP_EI, 8000);
3340                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3341
3342                 /* Downclock if less than 60% busy over 32ms */
3343                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3344                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3345
3346                 I915_WRITE(GEN6_RP_CONTROL,
3347                            GEN6_RP_MEDIA_TURBO |
3348                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
3349                            GEN6_RP_MEDIA_IS_GFX |
3350                            GEN6_RP_ENABLE |
3351                            GEN6_RP_UP_BUSY_AVG |
3352                            GEN6_RP_DOWN_IDLE_AVG);
3353                 break;
3354         }
3355
3356         dev_priv->rps.power = new_power;
3357         dev_priv->rps.last_adj = 0;
3358 }
3359
3360 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
3361 {
3362         u32 mask = 0;
3363
3364         if (val > dev_priv->rps.min_freq_softlimit)
3365                 mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
3366         if (val < dev_priv->rps.max_freq_softlimit)
3367                 mask |= GEN6_PM_RP_UP_THRESHOLD;
3368
3369         mask |= dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED);
3370         mask &= dev_priv->pm_rps_events;
3371
3372         /* IVB and SNB hard hangs on looping batchbuffer
3373          * if GEN6_PM_UP_EI_EXPIRED is masked.
3374          */
3375         if (INTEL_INFO(dev_priv->dev)->gen <= 7 && !IS_HASWELL(dev_priv->dev))
3376                 mask |= GEN6_PM_RP_UP_EI_EXPIRED;
3377
3378         if (IS_GEN8(dev_priv->dev))
3379                 mask |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;
3380
3381         return ~mask;
3382 }
3383
3384 /* gen6_set_rps is called to update the frequency request, but should also be
3385  * called when the range (min_delay and max_delay) is modified so that we can
3386  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
3387 void gen6_set_rps(struct drm_device *dev, u8 val)
3388 {
3389         struct drm_i915_private *dev_priv = dev->dev_private;
3390
3391         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3392         WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3393         WARN_ON(val < dev_priv->rps.min_freq_softlimit);
3394
3395         /* min/max delay may still have been modified so be sure to
3396          * write the limits value.
3397          */
3398         if (val != dev_priv->rps.cur_freq) {
3399                 gen6_set_rps_thresholds(dev_priv, val);
3400
3401                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3402                         I915_WRITE(GEN6_RPNSWREQ,
3403                                    HSW_FREQUENCY(val));
3404                 else
3405                         I915_WRITE(GEN6_RPNSWREQ,
3406                                    GEN6_FREQUENCY(val) |
3407                                    GEN6_OFFSET(0) |
3408                                    GEN6_AGGRESSIVE_TURBO);
3409         }
3410
3411         /* Make sure we continue to get interrupts
3412          * until we hit the minimum or maximum frequencies.
3413          */
3414         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val));
3415         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
3416
3417         POSTING_READ(GEN6_RPNSWREQ);
3418
3419         dev_priv->rps.cur_freq = val;
3420         trace_intel_gpu_freq_change(val * 50);
3421 }
3422
3423 /* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
3424  *
3425  * * If Gfx is Idle, then
3426  * 1. Mask Turbo interrupts
3427  * 2. Bring up Gfx clock
3428  * 3. Change the freq to Rpn and wait till P-Unit updates freq
3429  * 4. Clear the Force GFX CLK ON bit so that Gfx can down
3430  * 5. Unmask Turbo interrupts
3431 */
3432 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
3433 {
3434         struct drm_device *dev = dev_priv->dev;
3435
3436         /* Latest VLV doesn't need to force the gfx clock */
3437         if (dev->pdev->revision >= 0xd) {
3438                 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3439                 return;
3440         }
3441
3442         /*
3443          * When we are idle.  Drop to min voltage state.
3444          */
3445
3446         if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit)
3447                 return;
3448
3449         /* Mask turbo interrupt so that they will not come in between */
3450         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3451
3452         vlv_force_gfx_clock(dev_priv, true);
3453
3454         dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit;
3455
3456         vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ,
3457                                         dev_priv->rps.min_freq_softlimit);
3458
3459         if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
3460                                 & GENFREQSTATUS) == 0, 5))
3461                 DRM_ERROR("timed out waiting for Punit\n");
3462
3463         vlv_force_gfx_clock(dev_priv, false);
3464
3465         I915_WRITE(GEN6_PMINTRMSK,
3466                    gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
3467 }
3468
3469 void gen6_rps_idle(struct drm_i915_private *dev_priv)
3470 {
3471         struct drm_device *dev = dev_priv->dev;
3472
3473         mutex_lock(&dev_priv->rps.hw_lock);
3474         if (dev_priv->rps.enabled) {
3475                 if (IS_CHERRYVIEW(dev))
3476                         valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3477                 else if (IS_VALLEYVIEW(dev))
3478                         vlv_set_rps_idle(dev_priv);
3479                 else if (!dev_priv->rps.is_bdw_sw_turbo
3480                                         || atomic_read(&dev_priv->rps.sw_turbo.flip_received)){
3481                         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3482                 }
3483
3484                 dev_priv->rps.last_adj = 0;
3485         }
3486         mutex_unlock(&dev_priv->rps.hw_lock);
3487 }
3488
3489 void gen6_rps_boost(struct drm_i915_private *dev_priv)
3490 {
3491         struct drm_device *dev = dev_priv->dev;
3492
3493         mutex_lock(&dev_priv->rps.hw_lock);
3494         if (dev_priv->rps.enabled) {
3495                 if (IS_VALLEYVIEW(dev))
3496                         valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
3497                 else if (!dev_priv->rps.is_bdw_sw_turbo
3498                                         || atomic_read(&dev_priv->rps.sw_turbo.flip_received)){
3499                         gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
3500                 }
3501
3502                 dev_priv->rps.last_adj = 0;
3503         }
3504         mutex_unlock(&dev_priv->rps.hw_lock);
3505 }
3506
3507 void valleyview_set_rps(struct drm_device *dev, u8 val)
3508 {
3509         struct drm_i915_private *dev_priv = dev->dev_private;
3510
3511         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3512         WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3513         WARN_ON(val < dev_priv->rps.min_freq_softlimit);
3514
3515         DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3516                          vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
3517                          dev_priv->rps.cur_freq,
3518                          vlv_gpu_freq(dev_priv, val), val);
3519
3520         if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
3521                       "Odd GPU freq value\n"))
3522                 val &= ~1;
3523
3524         if (val != dev_priv->rps.cur_freq)
3525                 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
3526
3527         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
3528
3529         dev_priv->rps.cur_freq = val;
3530         trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
3531 }
3532
3533 static void gen8_disable_rps_interrupts(struct drm_device *dev)
3534 {
3535         struct drm_i915_private *dev_priv = dev->dev_private;
3536         if (IS_BROADWELL(dev) && dev_priv->rps.is_bdw_sw_turbo){
3537                 if (atomic_read(&dev_priv->rps.sw_turbo.flip_received))
3538                         del_timer(&dev_priv->rps.sw_turbo.flip_timer);
3539                 dev_priv-> rps.is_bdw_sw_turbo = false;
3540         } else {
3541                 I915_WRITE(GEN6_PMINTRMSK, ~GEN8_PMINTR_REDIRECT_TO_NON_DISP);
3542                 I915_WRITE(GEN8_GT_IER(2), I915_READ(GEN8_GT_IER(2)) &
3543                                            ~dev_priv->pm_rps_events);
3544                 /* Complete PM interrupt masking here doesn't race with the rps work
3545                  * item again unmasking PM interrupts because that is using a different
3546                  * register (GEN8_GT_IMR(2)) to mask PM interrupts. The only risk is in
3547                  * leaving stale bits in GEN8_GT_IIR(2) and GEN8_GT_IMR(2) which
3548                  * gen8_enable_rps will clean up. */
3549
3550                 spin_lock_irq(&dev_priv->irq_lock);
3551                 dev_priv->rps.pm_iir = 0;
3552                 spin_unlock_irq(&dev_priv->irq_lock);
3553
3554                 I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3555         }
3556 }
3557
3558 static void gen6_disable_rps_interrupts(struct drm_device *dev)
3559 {
3560         struct drm_i915_private *dev_priv = dev->dev_private;
3561
3562         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3563         I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) &
3564                                 ~dev_priv->pm_rps_events);
3565         /* Complete PM interrupt masking here doesn't race with the rps work
3566          * item again unmasking PM interrupts because that is using a different
3567          * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3568          * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3569
3570         spin_lock_irq(&dev_priv->irq_lock);
3571         dev_priv->rps.pm_iir = 0;
3572         spin_unlock_irq(&dev_priv->irq_lock);
3573
3574         I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
3575 }
3576
3577 static void gen6_disable_rps(struct drm_device *dev)
3578 {
3579         struct drm_i915_private *dev_priv = dev->dev_private;
3580
3581         I915_WRITE(GEN6_RC_CONTROL, 0);
3582         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
3583
3584         if (IS_BROADWELL(dev))
3585                 gen8_disable_rps_interrupts(dev);
3586         else
3587                 gen6_disable_rps_interrupts(dev);
3588 }
3589
3590 static void cherryview_disable_rps(struct drm_device *dev)
3591 {
3592         struct drm_i915_private *dev_priv = dev->dev_private;
3593
3594         I915_WRITE(GEN6_RC_CONTROL, 0);
3595
3596         gen8_disable_rps_interrupts(dev);
3597 }
3598
3599 static void valleyview_disable_rps(struct drm_device *dev)
3600 {
3601         struct drm_i915_private *dev_priv = dev->dev_private;
3602
3603         /* we're doing forcewake before Disabling RC6,
3604          * This what the BIOS expects when going into suspend */
3605         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3606
3607         I915_WRITE(GEN6_RC_CONTROL, 0);
3608
3609         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3610
3611         gen6_disable_rps_interrupts(dev);
3612 }
3613
3614 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3615 {
3616         if (IS_VALLEYVIEW(dev)) {
3617                 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
3618                         mode = GEN6_RC_CTL_RC6_ENABLE;
3619                 else
3620                         mode = 0;
3621         }
3622         DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3623                       (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3624                       (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3625                       (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3626 }
3627
3628 static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
3629 {
3630         /* No RC6 before Ironlake */
3631         if (INTEL_INFO(dev)->gen < 5)
3632                 return 0;
3633
3634         /* RC6 is only on Ironlake mobile not on desktop */
3635         if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev))
3636                 return 0;
3637
3638         /* Respect the kernel parameter if it is set */
3639         if (enable_rc6 >= 0) {
3640                 int mask;
3641
3642                 if (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
3643                         mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
3644                                INTEL_RC6pp_ENABLE;
3645                 else
3646                         mask = INTEL_RC6_ENABLE;
3647
3648                 if ((enable_rc6 & mask) != enable_rc6)
3649                         DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
3650                                       enable_rc6 & mask, enable_rc6, mask);
3651
3652                 return enable_rc6 & mask;
3653         }
3654
3655         /* Disable RC6 on Ironlake */
3656         if (INTEL_INFO(dev)->gen == 5)
3657                 return 0;
3658
3659         if (IS_IVYBRIDGE(dev))
3660                 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3661
3662         return INTEL_RC6_ENABLE;
3663 }
3664
3665 int intel_enable_rc6(const struct drm_device *dev)
3666 {
3667         return i915.enable_rc6;
3668 }
3669
3670 static void gen8_enable_rps_interrupts(struct drm_device *dev)
3671 {
3672         struct drm_i915_private *dev_priv = dev->dev_private;
3673
3674         spin_lock_irq(&dev_priv->irq_lock);
3675         WARN_ON(dev_priv->rps.pm_iir);
3676         gen8_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
3677         I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3678         spin_unlock_irq(&dev_priv->irq_lock);
3679 }
3680
3681 static void gen6_enable_rps_interrupts(struct drm_device *dev)
3682 {
3683         struct drm_i915_private *dev_priv = dev->dev_private;
3684
3685         spin_lock_irq(&dev_priv->irq_lock);
3686         WARN_ON(dev_priv->rps.pm_iir);
3687         gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
3688         I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
3689         spin_unlock_irq(&dev_priv->irq_lock);
3690 }
3691
3692 static void parse_rp_state_cap(struct drm_i915_private *dev_priv, u32 rp_state_cap)
3693 {
3694         /* All of these values are in units of 50MHz */
3695         dev_priv->rps.cur_freq          = 0;
3696         /* static values from HW: RP0 < RPe < RP1 < RPn (min_freq) */
3697         dev_priv->rps.rp1_freq          = (rp_state_cap >>  8) & 0xff;
3698         dev_priv->rps.rp0_freq          = (rp_state_cap >>  0) & 0xff;
3699         dev_priv->rps.min_freq          = (rp_state_cap >> 16) & 0xff;
3700         /* XXX: only BYT has a special efficient freq */
3701         dev_priv->rps.efficient_freq    = dev_priv->rps.rp1_freq;
3702         /* hw_max = RP0 until we check for overclocking */
3703         dev_priv->rps.max_freq          = dev_priv->rps.rp0_freq;
3704
3705         /* Preserve min/max settings in case of re-init */
3706         if (dev_priv->rps.max_freq_softlimit == 0)
3707                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3708
3709         if (dev_priv->rps.min_freq_softlimit == 0)
3710                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3711 }
3712
3713 static void bdw_sw_calculate_freq(struct drm_device *dev,
3714                 struct intel_rps_bdw_cal *c, u32 *cur_time, u32 *c0)
3715 {
3716         struct drm_i915_private *dev_priv = dev->dev_private;
3717         u64 busy = 0;
3718         u32 busyness_pct = 0;
3719         u32 elapsed_time = 0;
3720         u16 new_freq = 0;
3721
3722         if (!c || !cur_time || !c0)
3723                 return;
3724
3725         if (0 == c->last_c0)
3726                 goto out;
3727
3728         /* Check Evaluation interval */
3729         elapsed_time = *cur_time - c->last_ts;
3730         if (elapsed_time < c->eval_interval)
3731                 return;
3732
3733         mutex_lock(&dev_priv->rps.hw_lock);
3734
3735         /*
3736          * c0 unit in 32*1.28 usec, elapsed_time unit in 1 usec.
3737          * Whole busyness_pct calculation should be
3738          *     busy = ((u64)(*c0 - c->last_c0) << 5 << 7) / 100;
3739          *     busyness_pct = (u32)(busy * 100 / elapsed_time);
3740          * The final formula is to simplify CPU calculation
3741          */
3742         busy = (u64)(*c0 - c->last_c0) << 12;
3743         do_div(busy, elapsed_time);
3744         busyness_pct = (u32)busy;
3745
3746         if (c->is_up && busyness_pct >= c->it_threshold_pct)
3747                 new_freq = (u16)dev_priv->rps.cur_freq + 3;
3748         if (!c->is_up && busyness_pct <= c->it_threshold_pct)
3749                 new_freq = (u16)dev_priv->rps.cur_freq - 1;
3750
3751         /* Adjust to new frequency busyness and compare with threshold */
3752         if (0 != new_freq) {
3753                 if (new_freq > dev_priv->rps.max_freq_softlimit)
3754                         new_freq = dev_priv->rps.max_freq_softlimit;
3755                 else if (new_freq < dev_priv->rps.min_freq_softlimit)
3756                         new_freq = dev_priv->rps.min_freq_softlimit;
3757
3758                 gen6_set_rps(dev, new_freq);
3759         }
3760
3761         mutex_unlock(&dev_priv->rps.hw_lock);
3762
3763 out:
3764         c->last_c0 = *c0;
3765         c->last_ts = *cur_time;
3766 }
3767
3768 static void gen8_set_frequency_RP0(struct work_struct *work)
3769 {
3770         struct intel_rps_bdw_turbo *p_bdw_turbo =
3771                         container_of(work, struct intel_rps_bdw_turbo, work_max_freq);
3772         struct intel_gen6_power_mgmt *p_power_mgmt =
3773                         container_of(p_bdw_turbo, struct intel_gen6_power_mgmt, sw_turbo);
3774         struct drm_i915_private *dev_priv =
3775                         container_of(p_power_mgmt, struct drm_i915_private, rps);
3776
3777         mutex_lock(&dev_priv->rps.hw_lock);
3778         gen6_set_rps(dev_priv->dev, dev_priv->rps.rp0_freq);
3779         mutex_unlock(&dev_priv->rps.hw_lock);
3780 }
3781
3782 static void flip_active_timeout_handler(unsigned long var)
3783 {
3784         struct drm_i915_private *dev_priv = (struct drm_i915_private *) var;
3785
3786         del_timer(&dev_priv->rps.sw_turbo.flip_timer);
3787         atomic_set(&dev_priv->rps.sw_turbo.flip_received, false);
3788
3789         queue_work(dev_priv->wq, &dev_priv->rps.sw_turbo.work_max_freq);
3790 }
3791
3792 void bdw_software_turbo(struct drm_device *dev)
3793 {
3794         struct drm_i915_private *dev_priv = dev->dev_private;
3795
3796         u32 current_time = I915_READ(TIMESTAMP_CTR); /* unit in usec */
3797         u32 current_c0 = I915_READ(MCHBAR_PCU_C0); /* unit in 32*1.28 usec */
3798
3799         bdw_sw_calculate_freq(dev, &dev_priv->rps.sw_turbo.up,
3800                         &current_time, &current_c0);
3801         bdw_sw_calculate_freq(dev, &dev_priv->rps.sw_turbo.down,
3802                         &current_time, &current_c0);
3803 }
3804
3805 static void gen8_enable_rps(struct drm_device *dev)
3806 {
3807         struct drm_i915_private *dev_priv = dev->dev_private;
3808         struct intel_engine_cs *ring;
3809         uint32_t rc6_mask = 0, rp_state_cap;
3810         uint32_t threshold_up_pct, threshold_down_pct;
3811         uint32_t ei_up, ei_down; /* up and down evaluation interval */
3812         u32 rp_ctl_flag;
3813         int unused;
3814
3815         /* Use software Turbo for BDW */
3816         dev_priv->rps.is_bdw_sw_turbo = IS_BROADWELL(dev);
3817
3818         /* 1a: Software RC state - RC0 */
3819         I915_WRITE(GEN6_RC_STATE, 0);
3820
3821         /* 1c & 1d: Get forcewake during program sequence. Although the driver
3822          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
3823         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3824
3825         /* 2a: Disable RC states. */
3826         I915_WRITE(GEN6_RC_CONTROL, 0);
3827
3828         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3829         parse_rp_state_cap(dev_priv, rp_state_cap);
3830
3831         /* 2b: Program RC6 thresholds.*/
3832         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3833         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3834         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3835         for_each_ring(ring, dev_priv, unused)
3836                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3837         I915_WRITE(GEN6_RC_SLEEP, 0);
3838         if (IS_BROADWELL(dev))
3839                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
3840         else
3841                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
3842
3843         /* 3: Enable RC6 */
3844         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3845                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
3846         intel_print_rc6_info(dev, rc6_mask);
3847         if (IS_BROADWELL(dev))
3848                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3849                                 GEN7_RC_CTL_TO_MODE |
3850                                 rc6_mask);
3851         else
3852                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3853                                 GEN6_RC_CTL_EI_MODE(1) |
3854                                 rc6_mask);
3855
3856         /* 4 Program defaults and thresholds for RPS*/
3857         I915_WRITE(GEN6_RPNSWREQ,
3858                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
3859         I915_WRITE(GEN6_RC_VIDEO_FREQ,
3860                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
3861         ei_up = 84480; /* 84.48ms */
3862         ei_down = 448000;
3863         threshold_up_pct = 90; /* x percent busy */
3864         threshold_down_pct = 70;
3865
3866         if (dev_priv->rps.is_bdw_sw_turbo) {
3867                 dev_priv->rps.sw_turbo.up.it_threshold_pct = threshold_up_pct;
3868                 dev_priv->rps.sw_turbo.up.eval_interval = ei_up;
3869                 dev_priv->rps.sw_turbo.up.is_up = true;
3870                 dev_priv->rps.sw_turbo.up.last_ts = 0;
3871                 dev_priv->rps.sw_turbo.up.last_c0 = 0;
3872
3873                 dev_priv->rps.sw_turbo.down.it_threshold_pct = threshold_down_pct;
3874                 dev_priv->rps.sw_turbo.down.eval_interval = ei_down;
3875                 dev_priv->rps.sw_turbo.down.is_up = false;
3876                 dev_priv->rps.sw_turbo.down.last_ts = 0;
3877                 dev_priv->rps.sw_turbo.down.last_c0 = 0;
3878
3879                 /* Start the timer to track if flip comes*/
3880                 dev_priv->rps.sw_turbo.timeout = 200*1000; /* in us */
3881
3882                 init_timer(&dev_priv->rps.sw_turbo.flip_timer);
3883                 dev_priv->rps.sw_turbo.flip_timer.function = flip_active_timeout_handler;
3884                 dev_priv->rps.sw_turbo.flip_timer.data  = (unsigned long) dev_priv;
3885                 dev_priv->rps.sw_turbo.flip_timer.expires =
3886                         usecs_to_jiffies(dev_priv->rps.sw_turbo.timeout) + jiffies;
3887                 add_timer(&dev_priv->rps.sw_turbo.flip_timer);
3888                 INIT_WORK(&dev_priv->rps.sw_turbo.work_max_freq, gen8_set_frequency_RP0);
3889
3890                 atomic_set(&dev_priv->rps.sw_turbo.flip_received, true);
3891         } else {
3892                 /* NB: Docs say 1s, and 1000000 - which aren't equivalent
3893                  * 1 second timeout*/
3894                 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, FREQ_1_28_US(1000000));
3895
3896                 /* Docs recommend 900MHz, and 300 MHz respectively */
3897                 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3898                            dev_priv->rps.max_freq_softlimit << 24 |
3899                            dev_priv->rps.min_freq_softlimit << 16);
3900
3901                 I915_WRITE(GEN6_RP_UP_THRESHOLD,
3902                         FREQ_1_28_US(ei_up * threshold_up_pct / 100));
3903                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
3904                         FREQ_1_28_US(ei_down * threshold_down_pct / 100));
3905                 I915_WRITE(GEN6_RP_UP_EI,
3906                         FREQ_1_28_US(ei_up));
3907                 I915_WRITE(GEN6_RP_DOWN_EI,
3908                         FREQ_1_28_US(ei_down));
3909
3910                 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3911         }
3912
3913         /* 5: Enable RPS */
3914         rp_ctl_flag = GEN6_RP_MEDIA_TURBO |
3915                                         GEN6_RP_MEDIA_HW_NORMAL_MODE |
3916                                         GEN6_RP_MEDIA_IS_GFX |
3917                                         GEN6_RP_UP_BUSY_AVG |
3918                                         GEN6_RP_DOWN_IDLE_AVG;
3919         if (!dev_priv->rps.is_bdw_sw_turbo)
3920                 rp_ctl_flag |= GEN6_RP_ENABLE;
3921
3922         I915_WRITE(GEN6_RP_CONTROL, rp_ctl_flag);
3923
3924         /* 6: Ring frequency + overclocking
3925          * (our driver does this later */
3926         gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
3927         if (!dev_priv->rps.is_bdw_sw_turbo)
3928                 gen8_enable_rps_interrupts(dev);
3929
3930         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3931 }
3932
3933 static void gen6_enable_rps(struct drm_device *dev)
3934 {
3935         struct drm_i915_private *dev_priv = dev->dev_private;
3936         struct intel_engine_cs *ring;
3937         u32 rp_state_cap;
3938         u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
3939         u32 gtfifodbg;
3940         int rc6_mode;
3941         int i, ret;
3942
3943         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3944
3945         /* Here begins a magic sequence of register writes to enable
3946          * auto-downclocking.
3947          *
3948          * Perhaps there might be some value in exposing these to
3949          * userspace...
3950          */
3951         I915_WRITE(GEN6_RC_STATE, 0);
3952
3953         /* Clear the DBG now so we don't confuse earlier errors */
3954         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3955                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3956                 I915_WRITE(GTFIFODBG, gtfifodbg);
3957         }
3958
3959         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3960
3961         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3962
3963         parse_rp_state_cap(dev_priv, rp_state_cap);
3964
3965         /* disable the counters and set deterministic thresholds */
3966         I915_WRITE(GEN6_RC_CONTROL, 0);
3967
3968         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3969         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3970         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3971         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3972         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3973
3974         for_each_ring(ring, dev_priv, i)
3975                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3976
3977         I915_WRITE(GEN6_RC_SLEEP, 0);
3978         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3979         if (IS_IVYBRIDGE(dev))
3980                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3981         else
3982                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
3983         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
3984         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3985
3986         /* Check if we are enabling RC6 */
3987         rc6_mode = intel_enable_rc6(dev_priv->dev);
3988         if (rc6_mode & INTEL_RC6_ENABLE)
3989                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3990
3991         /* We don't use those on Haswell */
3992         if (!IS_HASWELL(dev)) {
3993                 if (rc6_mode & INTEL_RC6p_ENABLE)
3994                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
3995
3996                 if (rc6_mode & INTEL_RC6pp_ENABLE)
3997                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3998         }
3999
4000         intel_print_rc6_info(dev, rc6_mask);
4001
4002         I915_WRITE(GEN6_RC_CONTROL,
4003                    rc6_mask |
4004                    GEN6_RC_CTL_EI_MODE(1) |
4005                    GEN6_RC_CTL_HW_ENABLE);
4006
4007         /* Power down if completely idle for over 50ms */
4008         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
4009         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4010
4011         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
4012         if (ret)
4013                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
4014
4015         ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
4016         if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
4017                 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
4018                                  (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
4019                                  (pcu_mbox & 0xff) * 50);
4020                 dev_priv->rps.max_freq = pcu_mbox & 0xff;
4021         }
4022
4023         dev_priv->rps.power = HIGH_POWER; /* force a reset */
4024         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
4025
4026         gen6_enable_rps_interrupts(dev);
4027
4028         rc6vids = 0;
4029         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
4030         if (IS_GEN6(dev) && ret) {
4031                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
4032         } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
4033                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
4034                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
4035                 rc6vids &= 0xffff00;
4036                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
4037                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
4038                 if (ret)
4039                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
4040         }
4041
4042         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4043 }
4044
4045 static void __gen6_update_ring_freq(struct drm_device *dev)
4046 {
4047         struct drm_i915_private *dev_priv = dev->dev_private;
4048         int min_freq = 15;
4049         unsigned int gpu_freq;
4050         unsigned int max_ia_freq, min_ring_freq;
4051         int scaling_factor = 180;
4052         struct cpufreq_policy *policy;
4053
4054         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4055
4056         policy = cpufreq_cpu_get(0);
4057         if (policy) {
4058                 max_ia_freq = policy->cpuinfo.max_freq;
4059                 cpufreq_cpu_put(policy);
4060         } else {
4061                 /*
4062                  * Default to measured freq if none found, PCU will ensure we
4063                  * don't go over
4064                  */
4065                 max_ia_freq = tsc_khz;
4066         }
4067
4068         /* Convert from kHz to MHz */
4069         max_ia_freq /= 1000;
4070
4071         min_ring_freq = I915_READ(DCLK) & 0xf;
4072         /* convert DDR frequency from units of 266.6MHz to bandwidth */
4073         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
4074
4075         /*
4076          * For each potential GPU frequency, load a ring frequency we'd like
4077          * to use for memory access.  We do this by specifying the IA frequency
4078          * the PCU should use as a reference to determine the ring frequency.
4079          */
4080         for (gpu_freq = dev_priv->rps.max_freq_softlimit; gpu_freq >= dev_priv->rps.min_freq_softlimit;
4081              gpu_freq--) {
4082                 int diff = dev_priv->rps.max_freq_softlimit - gpu_freq;
4083                 unsigned int ia_freq = 0, ring_freq = 0;
4084
4085                 if (INTEL_INFO(dev)->gen >= 8) {
4086                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
4087                         ring_freq = max(min_ring_freq, gpu_freq);
4088                 } else if (IS_HASWELL(dev)) {
4089                         ring_freq = mult_frac(gpu_freq, 5, 4);
4090                         ring_freq = max(min_ring_freq, ring_freq);
4091                         /* leave ia_freq as the default, chosen by cpufreq */
4092                 } else {
4093                         /* On older processors, there is no separate ring
4094                          * clock domain, so in order to boost the bandwidth
4095                          * of the ring, we need to upclock the CPU (ia_freq).
4096                          *
4097                          * For GPU frequencies less than 750MHz,
4098                          * just use the lowest ring freq.
4099                          */
4100                         if (gpu_freq < min_freq)
4101                                 ia_freq = 800;
4102                         else
4103                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
4104                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
4105                 }
4106
4107                 sandybridge_pcode_write(dev_priv,
4108                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
4109                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
4110                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
4111                                         gpu_freq);
4112         }
4113 }
4114
4115 void gen6_update_ring_freq(struct drm_device *dev)
4116 {
4117         struct drm_i915_private *dev_priv = dev->dev_private;
4118
4119         if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))
4120                 return;
4121
4122         mutex_lock(&dev_priv->rps.hw_lock);
4123         __gen6_update_ring_freq(dev);
4124         mutex_unlock(&dev_priv->rps.hw_lock);
4125 }
4126
4127 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
4128 {
4129         u32 val, rp0;
4130
4131         val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
4132         rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
4133
4134         return rp0;
4135 }
4136
4137 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4138 {
4139         u32 val, rpe;
4140
4141         val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
4142         rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
4143
4144         return rpe;
4145 }
4146
4147 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
4148 {
4149         u32 val, rp1;
4150
4151         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4152         rp1 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
4153
4154         return rp1;
4155 }
4156
4157 static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
4158 {
4159         u32 val, rpn;
4160
4161         val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
4162         rpn = (val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) & PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK;
4163         return rpn;
4164 }
4165
4166 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
4167 {
4168         u32 val, rp1;
4169
4170         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
4171
4172         rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
4173
4174         return rp1;
4175 }
4176
4177 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
4178 {
4179         u32 val, rp0;
4180
4181         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
4182
4183         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
4184         /* Clamp to max */
4185         rp0 = min_t(u32, rp0, 0xea);
4186
4187         return rp0;
4188 }
4189
4190 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4191 {
4192         u32 val, rpe;
4193
4194         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
4195         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
4196         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
4197         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
4198
4199         return rpe;
4200 }
4201
4202 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
4203 {
4204         return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
4205 }
4206
4207 /* Check that the pctx buffer wasn't move under us. */
4208 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
4209 {
4210         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4211
4212         WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
4213                              dev_priv->vlv_pctx->stolen->start);
4214 }
4215
4216
4217 /* Check that the pcbr address is not empty. */
4218 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
4219 {
4220         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4221
4222         WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
4223 }
4224
4225 static void cherryview_setup_pctx(struct drm_device *dev)
4226 {
4227         struct drm_i915_private *dev_priv = dev->dev_private;
4228         unsigned long pctx_paddr, paddr;
4229         struct i915_gtt *gtt = &dev_priv->gtt;
4230         u32 pcbr;
4231         int pctx_size = 32*1024;
4232
4233         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4234
4235         pcbr = I915_READ(VLV_PCBR);
4236         if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
4237                 paddr = (dev_priv->mm.stolen_base +
4238                          (gtt->stolen_size - pctx_size));
4239
4240                 pctx_paddr = (paddr & (~4095));
4241                 I915_WRITE(VLV_PCBR, pctx_paddr);
4242         }
4243 }
4244
4245 static void valleyview_setup_pctx(struct drm_device *dev)
4246 {
4247         struct drm_i915_private *dev_priv = dev->dev_private;
4248         struct drm_i915_gem_object *pctx;
4249         unsigned long pctx_paddr;
4250         u32 pcbr;
4251         int pctx_size = 24*1024;
4252
4253         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4254
4255         pcbr = I915_READ(VLV_PCBR);
4256         if (pcbr) {
4257                 /* BIOS set it up already, grab the pre-alloc'd space */
4258                 int pcbr_offset;
4259
4260                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
4261                 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
4262                                                                       pcbr_offset,
4263                                                                       I915_GTT_OFFSET_NONE,
4264                                                                       pctx_size);
4265                 goto out;
4266         }
4267
4268         /*
4269          * From the Gunit register HAS:
4270          * The Gfx driver is expected to program this register and ensure
4271          * proper allocation within Gfx stolen memory.  For example, this
4272          * register should be programmed such than the PCBR range does not
4273          * overlap with other ranges, such as the frame buffer, protected
4274          * memory, or any other relevant ranges.
4275          */
4276         pctx = i915_gem_object_create_stolen(dev, pctx_size);
4277         if (!pctx) {
4278                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
4279                 return;
4280         }
4281
4282         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
4283         I915_WRITE(VLV_PCBR, pctx_paddr);
4284
4285 out:
4286         dev_priv->vlv_pctx = pctx;
4287 }
4288
4289 static void valleyview_cleanup_pctx(struct drm_device *dev)
4290 {
4291         struct drm_i915_private *dev_priv = dev->dev_private;
4292
4293         if (WARN_ON(!dev_priv->vlv_pctx))
4294                 return;
4295
4296         drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
4297         dev_priv->vlv_pctx = NULL;
4298 }
4299
4300 static void valleyview_init_gt_powersave(struct drm_device *dev)
4301 {
4302         struct drm_i915_private *dev_priv = dev->dev_private;
4303         u32 val;
4304
4305         valleyview_setup_pctx(dev);
4306
4307         mutex_lock(&dev_priv->rps.hw_lock);
4308
4309         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4310         switch ((val >> 6) & 3) {
4311         case 0:
4312         case 1:
4313                 dev_priv->mem_freq = 800;
4314                 break;
4315         case 2:
4316                 dev_priv->mem_freq = 1066;
4317                 break;
4318         case 3:
4319                 dev_priv->mem_freq = 1333;
4320                 break;
4321         }
4322         DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
4323
4324         dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
4325         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4326         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4327                          vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4328                          dev_priv->rps.max_freq);
4329
4330         dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
4331         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4332                          vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4333                          dev_priv->rps.efficient_freq);
4334
4335         dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
4336         DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
4337                          vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
4338                          dev_priv->rps.rp1_freq);
4339
4340         dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
4341         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4342                          vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4343                          dev_priv->rps.min_freq);
4344
4345         /* Preserve min/max settings in case of re-init */
4346         if (dev_priv->rps.max_freq_softlimit == 0)
4347                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4348
4349         if (dev_priv->rps.min_freq_softlimit == 0)
4350                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4351
4352         mutex_unlock(&dev_priv->rps.hw_lock);
4353 }
4354
4355 static void cherryview_init_gt_powersave(struct drm_device *dev)
4356 {
4357         struct drm_i915_private *dev_priv = dev->dev_private;
4358         u32 val;
4359
4360         cherryview_setup_pctx(dev);
4361
4362         mutex_lock(&dev_priv->rps.hw_lock);
4363
4364         val = vlv_punit_read(dev_priv, CCK_FUSE_REG);
4365         switch ((val >> 2) & 0x7) {
4366         case 0:
4367         case 1:
4368                 dev_priv->rps.cz_freq = 200;
4369                 dev_priv->mem_freq = 1600;
4370                 break;
4371         case 2:
4372                 dev_priv->rps.cz_freq = 267;
4373                 dev_priv->mem_freq = 1600;
4374                 break;
4375         case 3:
4376                 dev_priv->rps.cz_freq = 333;
4377                 dev_priv->mem_freq = 2000;
4378                 break;
4379         case 4:
4380                 dev_priv->rps.cz_freq = 320;
4381                 dev_priv->mem_freq = 1600;
4382                 break;
4383         case 5:
4384                 dev_priv->rps.cz_freq = 400;
4385                 dev_priv->mem_freq = 1600;
4386                 break;
4387         }
4388         DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
4389
4390         dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
4391         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4392         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4393                          vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4394                          dev_priv->rps.max_freq);
4395
4396         dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
4397         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4398                          vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4399                          dev_priv->rps.efficient_freq);
4400
4401         dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
4402         DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
4403                          vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
4404                          dev_priv->rps.rp1_freq);
4405
4406         dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
4407         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4408                          vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4409                          dev_priv->rps.min_freq);
4410
4411         WARN_ONCE((dev_priv->rps.max_freq |
4412                    dev_priv->rps.efficient_freq |
4413                    dev_priv->rps.rp1_freq |
4414                    dev_priv->rps.min_freq) & 1,
4415                   "Odd GPU freq values\n");
4416
4417         /* Preserve min/max settings in case of re-init */
4418         if (dev_priv->rps.max_freq_softlimit == 0)
4419                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4420
4421         if (dev_priv->rps.min_freq_softlimit == 0)
4422                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4423
4424         mutex_unlock(&dev_priv->rps.hw_lock);
4425 }
4426
4427 static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
4428 {
4429         valleyview_cleanup_pctx(dev);
4430 }
4431
4432 static void cherryview_enable_rps(struct drm_device *dev)
4433 {
4434         struct drm_i915_private *dev_priv = dev->dev_private;
4435         struct intel_engine_cs *ring;
4436         u32 gtfifodbg, val, rc6_mode = 0, pcbr;
4437         int i;
4438
4439         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4440
4441         gtfifodbg = I915_READ(GTFIFODBG);
4442         if (gtfifodbg) {
4443                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4444                                  gtfifodbg);
4445                 I915_WRITE(GTFIFODBG, gtfifodbg);
4446         }
4447
4448         cherryview_check_pctx(dev_priv);
4449
4450         /* 1a & 1b: Get forcewake during program sequence. Although the driver
4451          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4452         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4453
4454         /* 2a: Program RC6 thresholds.*/
4455         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4456         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4457         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4458
4459         for_each_ring(ring, dev_priv, i)
4460                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4461         I915_WRITE(GEN6_RC_SLEEP, 0);
4462
4463         I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
4464
4465         /* allows RC6 residency counter to work */
4466         I915_WRITE(VLV_COUNTER_CONTROL,
4467                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
4468                                       VLV_MEDIA_RC6_COUNT_EN |
4469                                       VLV_RENDER_RC6_COUNT_EN));
4470
4471         /* For now we assume BIOS is allocating and populating the PCBR  */
4472         pcbr = I915_READ(VLV_PCBR);
4473
4474         DRM_DEBUG_DRIVER("PCBR offset : 0x%x\n", pcbr);
4475
4476         /* 3: Enable RC6 */
4477         if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
4478                                                 (pcbr >> VLV_PCBR_ADDR_SHIFT))
4479                 rc6_mode = GEN6_RC_CTL_EI_MODE(1);
4480
4481         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
4482
4483         /* 4 Program defaults and thresholds for RPS*/
4484         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4485         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4486         I915_WRITE(GEN6_RP_UP_EI, 66000);
4487         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4488
4489         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4490
4491         /* WaDisablePwrmtrEvent:chv (pre-production hw) */
4492         I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff);
4493         I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00);
4494
4495         /* 5: Enable RPS */
4496         I915_WRITE(GEN6_RP_CONTROL,
4497                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
4498                    GEN6_RP_MEDIA_IS_GFX | /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */
4499                    GEN6_RP_ENABLE |
4500                    GEN6_RP_UP_BUSY_AVG |
4501                    GEN6_RP_DOWN_IDLE_AVG);
4502
4503         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4504
4505         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4506         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4507
4508         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
4509         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4510                          vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
4511                          dev_priv->rps.cur_freq);
4512
4513         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4514                          vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4515                          dev_priv->rps.efficient_freq);
4516
4517         valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
4518
4519         gen8_enable_rps_interrupts(dev);
4520
4521         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4522 }
4523
4524 static void valleyview_enable_rps(struct drm_device *dev)
4525 {
4526         struct drm_i915_private *dev_priv = dev->dev_private;
4527         struct intel_engine_cs *ring;
4528         u32 gtfifodbg, val, rc6_mode = 0;
4529         int i;
4530
4531         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4532
4533         valleyview_check_pctx(dev_priv);
4534
4535         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4536                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4537                                  gtfifodbg);
4538                 I915_WRITE(GTFIFODBG, gtfifodbg);
4539         }
4540
4541         /* If VLV, Forcewake all wells, else re-direct to regular path */
4542         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4543
4544         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4545         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4546         I915_WRITE(GEN6_RP_UP_EI, 66000);
4547         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4548
4549         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4550         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 0xf4240);
4551
4552         I915_WRITE(GEN6_RP_CONTROL,
4553                    GEN6_RP_MEDIA_TURBO |
4554                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
4555                    GEN6_RP_MEDIA_IS_GFX |
4556                    GEN6_RP_ENABLE |
4557                    GEN6_RP_UP_BUSY_AVG |
4558                    GEN6_RP_DOWN_IDLE_CONT);
4559
4560         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
4561         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4562         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4563
4564         for_each_ring(ring, dev_priv, i)
4565                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4566
4567         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
4568
4569         /* allows RC6 residency counter to work */
4570         I915_WRITE(VLV_COUNTER_CONTROL,
4571                    _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
4572                                       VLV_RENDER_RC0_COUNT_EN |
4573                                       VLV_MEDIA_RC6_COUNT_EN |
4574                                       VLV_RENDER_RC6_COUNT_EN));
4575
4576         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4577                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
4578
4579         intel_print_rc6_info(dev, rc6_mode);
4580
4581         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
4582
4583         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4584
4585         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4586         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4587
4588         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
4589         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4590                          vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
4591                          dev_priv->rps.cur_freq);
4592
4593         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4594                          vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4595                          dev_priv->rps.efficient_freq);
4596
4597         valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
4598
4599         gen6_enable_rps_interrupts(dev);
4600
4601         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4602 }
4603
4604 void ironlake_teardown_rc6(struct drm_device *dev)
4605 {
4606         struct drm_i915_private *dev_priv = dev->dev_private;
4607
4608         if (dev_priv->ips.renderctx) {
4609                 i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx);
4610                 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
4611                 dev_priv->ips.renderctx = NULL;
4612         }
4613
4614         if (dev_priv->ips.pwrctx) {
4615                 i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx);
4616                 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
4617                 dev_priv->ips.pwrctx = NULL;
4618         }
4619 }
4620
4621 static void ironlake_disable_rc6(struct drm_device *dev)
4622 {
4623         struct drm_i915_private *dev_priv = dev->dev_private;
4624
4625         if (I915_READ(PWRCTXA)) {
4626                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
4627                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
4628                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
4629                          50);
4630
4631                 I915_WRITE(PWRCTXA, 0);
4632                 POSTING_READ(PWRCTXA);
4633
4634                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4635                 POSTING_READ(RSTDBYCTL);
4636         }
4637 }
4638
4639 static int ironlake_setup_rc6(struct drm_device *dev)
4640 {
4641         struct drm_i915_private *dev_priv = dev->dev_private;
4642
4643         if (dev_priv->ips.renderctx == NULL)
4644                 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
4645         if (!dev_priv->ips.renderctx)
4646                 return -ENOMEM;
4647
4648         if (dev_priv->ips.pwrctx == NULL)
4649                 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
4650         if (!dev_priv->ips.pwrctx) {
4651                 ironlake_teardown_rc6(dev);
4652                 return -ENOMEM;
4653         }
4654
4655         return 0;
4656 }
4657
4658 static void ironlake_enable_rc6(struct drm_device *dev)
4659 {
4660         struct drm_i915_private *dev_priv = dev->dev_private;
4661         struct intel_engine_cs *ring = &dev_priv->ring[RCS];
4662         bool was_interruptible;
4663         int ret;
4664
4665         /* rc6 disabled by default due to repeated reports of hanging during
4666          * boot and resume.
4667          */
4668         if (!intel_enable_rc6(dev))
4669                 return;
4670
4671         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4672
4673         ret = ironlake_setup_rc6(dev);
4674         if (ret)
4675                 return;
4676
4677         was_interruptible = dev_priv->mm.interruptible;
4678         dev_priv->mm.interruptible = false;
4679
4680         /*
4681          * GPU can automatically power down the render unit if given a page
4682          * to save state.
4683          */
4684         ret = intel_ring_begin(ring, 6);
4685         if (ret) {
4686                 ironlake_teardown_rc6(dev);
4687                 dev_priv->mm.interruptible = was_interruptible;
4688                 return;
4689         }
4690
4691         intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
4692         intel_ring_emit(ring, MI_SET_CONTEXT);
4693         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
4694                         MI_MM_SPACE_GTT |
4695                         MI_SAVE_EXT_STATE_EN |
4696                         MI_RESTORE_EXT_STATE_EN |
4697                         MI_RESTORE_INHIBIT);
4698         intel_ring_emit(ring, MI_SUSPEND_FLUSH);
4699         intel_ring_emit(ring, MI_NOOP);
4700         intel_ring_emit(ring, MI_FLUSH);
4701         intel_ring_advance(ring);
4702
4703         /*
4704          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4705          * does an implicit flush, combined with MI_FLUSH above, it should be
4706          * safe to assume that renderctx is valid
4707          */
4708         ret = intel_ring_idle(ring);
4709         dev_priv->mm.interruptible = was_interruptible;
4710         if (ret) {
4711                 DRM_ERROR("failed to enable ironlake power savings\n");
4712                 ironlake_teardown_rc6(dev);
4713                 return;
4714         }
4715
4716         I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
4717         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4718
4719         intel_print_rc6_info(dev, GEN6_RC_CTL_RC6_ENABLE);
4720 }
4721
4722 static unsigned long intel_pxfreq(u32 vidfreq)
4723 {
4724         unsigned long freq;
4725         int div = (vidfreq & 0x3f0000) >> 16;
4726         int post = (vidfreq & 0x3000) >> 12;
4727         int pre = (vidfreq & 0x7);
4728
4729         if (!pre)
4730                 return 0;
4731
4732         freq = ((div * 133333) / ((1<<post) * pre));
4733
4734         return freq;
4735 }
4736
4737 static const struct cparams {
4738         u16 i;
4739         u16 t;
4740         u16 m;
4741         u16 c;
4742 } cparams[] = {
4743         { 1, 1333, 301, 28664 },
4744         { 1, 1066, 294, 24460 },
4745         { 1, 800, 294, 25192 },
4746         { 0, 1333, 276, 27605 },
4747         { 0, 1066, 276, 27605 },
4748         { 0, 800, 231, 23784 },
4749 };
4750
4751 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
4752 {
4753         u64 total_count, diff, ret;
4754         u32 count1, count2, count3, m = 0, c = 0;
4755         unsigned long now = jiffies_to_msecs(jiffies), diff1;
4756         int i;
4757
4758         assert_spin_locked(&mchdev_lock);
4759
4760         diff1 = now - dev_priv->ips.last_time1;
4761
4762         /* Prevent division-by-zero if we are asking too fast.
4763          * Also, we don't get interesting results if we are polling
4764          * faster than once in 10ms, so just return the saved value
4765          * in such cases.
4766          */
4767         if (diff1 <= 10)
4768                 return dev_priv->ips.chipset_power;
4769
4770         count1 = I915_READ(DMIEC);
4771         count2 = I915_READ(DDREC);
4772         count3 = I915_READ(CSIEC);
4773
4774         total_count = count1 + count2 + count3;
4775
4776         /* FIXME: handle per-counter overflow */
4777         if (total_count < dev_priv->ips.last_count1) {
4778                 diff = ~0UL - dev_priv->ips.last_count1;
4779                 diff += total_count;
4780         } else {
4781                 diff = total_count - dev_priv->ips.last_count1;
4782         }
4783
4784         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
4785                 if (cparams[i].i == dev_priv->ips.c_m &&
4786                     cparams[i].t == dev_priv->ips.r_t) {
4787                         m = cparams[i].m;
4788                         c = cparams[i].c;
4789                         break;
4790                 }
4791         }
4792
4793         diff = div_u64(diff, diff1);
4794         ret = ((m * diff) + c);
4795         ret = div_u64(ret, 10);
4796
4797         dev_priv->ips.last_count1 = total_count;
4798         dev_priv->ips.last_time1 = now;
4799
4800         dev_priv->ips.chipset_power = ret;
4801
4802         return ret;
4803 }
4804
4805 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4806 {
4807         struct drm_device *dev = dev_priv->dev;
4808         unsigned long val;
4809
4810         if (INTEL_INFO(dev)->gen != 5)
4811                 return 0;
4812
4813         spin_lock_irq(&mchdev_lock);
4814
4815         val = __i915_chipset_val(dev_priv);
4816
4817         spin_unlock_irq(&mchdev_lock);
4818
4819         return val;
4820 }
4821
4822 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4823 {
4824         unsigned long m, x, b;
4825         u32 tsfs;
4826
4827         tsfs = I915_READ(TSFS);
4828
4829         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4830         x = I915_READ8(TR1);
4831
4832         b = tsfs & TSFS_INTR_MASK;
4833
4834         return ((m * x) / 127) - b;
4835 }
4836
4837 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4838 {
4839         struct drm_device *dev = dev_priv->dev;
4840         static const struct v_table {
4841                 u16 vd; /* in .1 mil */
4842                 u16 vm; /* in .1 mil */
4843         } v_table[] = {
4844                 { 0, 0, },
4845                 { 375, 0, },
4846                 { 500, 0, },
4847                 { 625, 0, },
4848                 { 750, 0, },
4849                 { 875, 0, },
4850                 { 1000, 0, },
4851                 { 1125, 0, },
4852                 { 4125, 3000, },
4853                 { 4125, 3000, },
4854                 { 4125, 3000, },
4855                 { 4125, 3000, },
4856                 { 4125, 3000, },
4857                 { 4125, 3000, },
4858                 { 4125, 3000, },
4859                 { 4125, 3000, },
4860                 { 4125, 3000, },
4861                 { 4125, 3000, },
4862                 { 4125, 3000, },
4863                 { 4125, 3000, },
4864                 { 4125, 3000, },
4865                 { 4125, 3000, },
4866                 { 4125, 3000, },
4867                 { 4125, 3000, },
4868                 { 4125, 3000, },
4869                 { 4125, 3000, },
4870                 { 4125, 3000, },
4871                 { 4125, 3000, },
4872                 { 4125, 3000, },
4873                 { 4125, 3000, },
4874                 { 4125, 3000, },
4875                 { 4125, 3000, },
4876                 { 4250, 3125, },
4877                 { 4375, 3250, },
4878                 { 4500, 3375, },
4879                 { 4625, 3500, },
4880                 { 4750, 3625, },
4881                 { 4875, 3750, },
4882                 { 5000, 3875, },
4883                 { 5125, 4000, },
4884                 { 5250, 4125, },
4885                 { 5375, 4250, },
4886                 { 5500, 4375, },
4887                 { 5625, 4500, },
4888                 { 5750, 4625, },
4889                 { 5875, 4750, },
4890                 { 6000, 4875, },
4891                 { 6125, 5000, },
4892                 { 6250, 5125, },
4893                 { 6375, 5250, },
4894                 { 6500, 5375, },
4895                 { 6625, 5500, },
4896                 { 6750, 5625, },
4897                 { 6875, 5750, },
4898                 { 7000, 5875, },
4899                 { 7125, 6000, },
4900                 { 7250, 6125, },
4901                 { 7375, 6250, },
4902                 { 7500, 6375, },
4903                 { 7625, 6500, },
4904                 { 7750, 6625, },
4905                 { 7875, 6750, },
4906                 { 8000, 6875, },
4907                 { 8125, 7000, },
4908                 { 8250, 7125, },
4909                 { 8375, 7250, },
4910                 { 8500, 7375, },
4911                 { 8625, 7500, },
4912                 { 8750, 7625, },
4913                 { 8875, 7750, },
4914                 { 9000, 7875, },
4915                 { 9125, 8000, },
4916                 { 9250, 8125, },
4917                 { 9375, 8250, },
4918                 { 9500, 8375, },
4919                 { 9625, 8500, },
4920                 { 9750, 8625, },
4921                 { 9875, 8750, },
4922                 { 10000, 8875, },
4923                 { 10125, 9000, },
4924                 { 10250, 9125, },
4925                 { 10375, 9250, },
4926                 { 10500, 9375, },
4927                 { 10625, 9500, },
4928                 { 10750, 9625, },
4929                 { 10875, 9750, },
4930                 { 11000, 9875, },
4931                 { 11125, 10000, },
4932                 { 11250, 10125, },
4933                 { 11375, 10250, },
4934                 { 11500, 10375, },
4935                 { 11625, 10500, },
4936                 { 11750, 10625, },
4937                 { 11875, 10750, },
4938                 { 12000, 10875, },
4939                 { 12125, 11000, },
4940                 { 12250, 11125, },
4941                 { 12375, 11250, },
4942                 { 12500, 11375, },
4943                 { 12625, 11500, },
4944                 { 12750, 11625, },
4945                 { 12875, 11750, },
4946                 { 13000, 11875, },
4947                 { 13125, 12000, },
4948                 { 13250, 12125, },
4949                 { 13375, 12250, },
4950                 { 13500, 12375, },
4951                 { 13625, 12500, },
4952                 { 13750, 12625, },
4953                 { 13875, 12750, },
4954                 { 14000, 12875, },
4955                 { 14125, 13000, },
4956                 { 14250, 13125, },
4957                 { 14375, 13250, },
4958                 { 14500, 13375, },
4959                 { 14625, 13500, },
4960                 { 14750, 13625, },
4961                 { 14875, 13750, },
4962                 { 15000, 13875, },
4963                 { 15125, 14000, },
4964                 { 15250, 14125, },
4965                 { 15375, 14250, },
4966                 { 15500, 14375, },
4967                 { 15625, 14500, },
4968                 { 15750, 14625, },
4969                 { 15875, 14750, },
4970                 { 16000, 14875, },
4971                 { 16125, 15000, },
4972         };
4973         if (INTEL_INFO(dev)->is_mobile)
4974                 return v_table[pxvid].vm;
4975         else
4976                 return v_table[pxvid].vd;
4977 }
4978
4979 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
4980 {
4981         u64 now, diff, diffms;
4982         u32 count;
4983
4984         assert_spin_locked(&mchdev_lock);
4985
4986         now = ktime_get_raw_ns();
4987         diffms = now - dev_priv->ips.last_time2;
4988         do_div(diffms, NSEC_PER_MSEC);
4989
4990         /* Don't divide by 0 */
4991         if (!diffms)
4992                 return;
4993
4994         count = I915_READ(GFXEC);
4995
4996         if (count < dev_priv->ips.last_count2) {
4997                 diff = ~0UL - dev_priv->ips.last_count2;
4998                 diff += count;
4999         } else {
5000                 diff = count - dev_priv->ips.last_count2;
5001         }
5002
5003         dev_priv->ips.last_count2 = count;
5004         dev_priv->ips.last_time2 = now;
5005
5006         /* More magic constants... */
5007         diff = diff * 1181;
5008         diff = div_u64(diff, diffms * 10);
5009         dev_priv->ips.gfx_power = diff;
5010 }
5011
5012 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5013 {
5014         struct drm_device *dev = dev_priv->dev;
5015
5016         if (INTEL_INFO(dev)->gen != 5)
5017                 return;
5018
5019         spin_lock_irq(&mchdev_lock);
5020
5021         __i915_update_gfx_val(dev_priv);
5022
5023         spin_unlock_irq(&mchdev_lock);
5024 }
5025
5026 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
5027 {
5028         unsigned long t, corr, state1, corr2, state2;
5029         u32 pxvid, ext_v;
5030
5031         assert_spin_locked(&mchdev_lock);
5032
5033         pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
5034         pxvid = (pxvid >> 24) & 0x7f;
5035         ext_v = pvid_to_extvid(dev_priv, pxvid);
5036
5037         state1 = ext_v;
5038
5039         t = i915_mch_val(dev_priv);
5040
5041         /* Revel in the empirically derived constants */
5042
5043         /* Correction factor in 1/100000 units */
5044         if (t > 80)
5045                 corr = ((t * 2349) + 135940);
5046         else if (t >= 50)
5047                 corr = ((t * 964) + 29317);
5048         else /* < 50 */
5049                 corr = ((t * 301) + 1004);
5050
5051         corr = corr * ((150142 * state1) / 10000 - 78642);
5052         corr /= 100000;
5053         corr2 = (corr * dev_priv->ips.corr);
5054
5055         state2 = (corr2 * state1) / 10000;
5056         state2 /= 100; /* convert to mW */
5057
5058         __i915_update_gfx_val(dev_priv);
5059
5060         return dev_priv->ips.gfx_power + state2;
5061 }
5062
5063 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5064 {
5065         struct drm_device *dev = dev_priv->dev;
5066         unsigned long val;
5067
5068         if (INTEL_INFO(dev)->gen != 5)
5069                 return 0;
5070
5071         spin_lock_irq(&mchdev_lock);
5072
5073         val = __i915_gfx_val(dev_priv);
5074
5075         spin_unlock_irq(&mchdev_lock);
5076
5077         return val;
5078 }
5079
5080 /**
5081  * i915_read_mch_val - return value for IPS use
5082  *
5083  * Calculate and return a value for the IPS driver to use when deciding whether
5084  * we have thermal and power headroom to increase CPU or GPU power budget.
5085  */
5086 unsigned long i915_read_mch_val(void)
5087 {
5088         struct drm_i915_private *dev_priv;
5089         unsigned long chipset_val, graphics_val, ret = 0;
5090
5091         spin_lock_irq(&mchdev_lock);
5092         if (!i915_mch_dev)
5093                 goto out_unlock;
5094         dev_priv = i915_mch_dev;
5095
5096         chipset_val = __i915_chipset_val(dev_priv);
5097         graphics_val = __i915_gfx_val(dev_priv);
5098
5099         ret = chipset_val + graphics_val;
5100
5101 out_unlock:
5102         spin_unlock_irq(&mchdev_lock);
5103
5104         return ret;
5105 }
5106 EXPORT_SYMBOL_GPL(i915_read_mch_val);
5107
5108 /**
5109  * i915_gpu_raise - raise GPU frequency limit
5110  *
5111  * Raise the limit; IPS indicates we have thermal headroom.
5112  */
5113 bool i915_gpu_raise(void)
5114 {
5115         struct drm_i915_private *dev_priv;
5116         bool ret = true;
5117
5118         spin_lock_irq(&mchdev_lock);
5119         if (!i915_mch_dev) {
5120                 ret = false;
5121                 goto out_unlock;
5122         }
5123         dev_priv = i915_mch_dev;
5124
5125         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5126                 dev_priv->ips.max_delay--;
5127
5128 out_unlock:
5129         spin_unlock_irq(&mchdev_lock);
5130
5131         return ret;
5132 }
5133 EXPORT_SYMBOL_GPL(i915_gpu_raise);
5134
5135 /**
5136  * i915_gpu_lower - lower GPU frequency limit
5137  *
5138  * IPS indicates we're close to a thermal limit, so throttle back the GPU
5139  * frequency maximum.
5140  */
5141 bool i915_gpu_lower(void)
5142 {
5143         struct drm_i915_private *dev_priv;
5144         bool ret = true;
5145
5146         spin_lock_irq(&mchdev_lock);
5147         if (!i915_mch_dev) {
5148                 ret = false;
5149                 goto out_unlock;
5150         }
5151         dev_priv = i915_mch_dev;
5152
5153         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5154                 dev_priv->ips.max_delay++;
5155
5156 out_unlock:
5157         spin_unlock_irq(&mchdev_lock);
5158
5159         return ret;
5160 }
5161 EXPORT_SYMBOL_GPL(i915_gpu_lower);
5162
5163 /**
5164  * i915_gpu_busy - indicate GPU business to IPS
5165  *
5166  * Tell the IPS driver whether or not the GPU is busy.
5167  */
5168 bool i915_gpu_busy(void)
5169 {
5170         struct drm_i915_private *dev_priv;
5171         struct intel_engine_cs *ring;
5172         bool ret = false;
5173         int i;
5174
5175         spin_lock_irq(&mchdev_lock);
5176         if (!i915_mch_dev)
5177                 goto out_unlock;
5178         dev_priv = i915_mch_dev;
5179
5180         for_each_ring(ring, dev_priv, i)
5181                 ret |= !list_empty(&ring->request_list);
5182
5183 out_unlock:
5184         spin_unlock_irq(&mchdev_lock);
5185
5186         return ret;
5187 }
5188 EXPORT_SYMBOL_GPL(i915_gpu_busy);
5189
5190 /**
5191  * i915_gpu_turbo_disable - disable graphics turbo
5192  *
5193  * Disable graphics turbo by resetting the max frequency and setting the
5194  * current frequency to the default.
5195  */
5196 bool i915_gpu_turbo_disable(void)
5197 {
5198         struct drm_i915_private *dev_priv;
5199         bool ret = true;
5200
5201         spin_lock_irq(&mchdev_lock);
5202         if (!i915_mch_dev) {
5203                 ret = false;
5204                 goto out_unlock;
5205         }
5206         dev_priv = i915_mch_dev;
5207
5208         dev_priv->ips.max_delay = dev_priv->ips.fstart;
5209
5210         if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
5211                 ret = false;
5212
5213 out_unlock:
5214         spin_unlock_irq(&mchdev_lock);
5215
5216         return ret;
5217 }
5218 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
5219
5220 /**
5221  * Tells the intel_ips driver that the i915 driver is now loaded, if
5222  * IPS got loaded first.
5223  *
5224  * This awkward dance is so that neither module has to depend on the
5225  * other in order for IPS to do the appropriate communication of
5226  * GPU turbo limits to i915.
5227  */
5228 static void
5229 ips_ping_for_i915_load(void)
5230 {
5231         void (*link)(void);
5232
5233         link = symbol_get(ips_link_to_i915_driver);
5234         if (link) {
5235                 link();
5236                 symbol_put(ips_link_to_i915_driver);
5237         }
5238 }
5239
5240 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
5241 {
5242         /* We only register the i915 ips part with intel-ips once everything is
5243          * set up, to avoid intel-ips sneaking in and reading bogus values. */
5244         spin_lock_irq(&mchdev_lock);
5245         i915_mch_dev = dev_priv;
5246         spin_unlock_irq(&mchdev_lock);
5247
5248         ips_ping_for_i915_load();
5249 }
5250
5251 void intel_gpu_ips_teardown(void)
5252 {
5253         spin_lock_irq(&mchdev_lock);
5254         i915_mch_dev = NULL;
5255         spin_unlock_irq(&mchdev_lock);
5256 }
5257
5258 static void intel_init_emon(struct drm_device *dev)
5259 {
5260         struct drm_i915_private *dev_priv = dev->dev_private;
5261         u32 lcfuse;
5262         u8 pxw[16];
5263         int i;
5264
5265         /* Disable to program */
5266         I915_WRITE(ECR, 0);
5267         POSTING_READ(ECR);
5268
5269         /* Program energy weights for various events */
5270         I915_WRITE(SDEW, 0x15040d00);
5271         I915_WRITE(CSIEW0, 0x007f0000);
5272         I915_WRITE(CSIEW1, 0x1e220004);
5273         I915_WRITE(CSIEW2, 0x04000004);
5274
5275         for (i = 0; i < 5; i++)
5276                 I915_WRITE(PEW + (i * 4), 0);
5277         for (i = 0; i < 3; i++)
5278                 I915_WRITE(DEW + (i * 4), 0);
5279
5280         /* Program P-state weights to account for frequency power adjustment */
5281         for (i = 0; i < 16; i++) {
5282                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5283                 unsigned long freq = intel_pxfreq(pxvidfreq);
5284                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5285                         PXVFREQ_PX_SHIFT;
5286                 unsigned long val;
5287
5288                 val = vid * vid;
5289                 val *= (freq / 1000);
5290                 val *= 255;
5291                 val /= (127*127*900);
5292                 if (val > 0xff)
5293                         DRM_ERROR("bad pxval: %ld\n", val);
5294                 pxw[i] = val;
5295         }
5296         /* Render standby states get 0 weight */
5297         pxw[14] = 0;
5298         pxw[15] = 0;
5299
5300         for (i = 0; i < 4; i++) {
5301                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5302                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5303                 I915_WRITE(PXW + (i * 4), val);
5304         }
5305
5306         /* Adjust magic regs to magic values (more experimental results) */
5307         I915_WRITE(OGW0, 0);
5308         I915_WRITE(OGW1, 0);
5309         I915_WRITE(EG0, 0x00007f00);
5310         I915_WRITE(EG1, 0x0000000e);
5311         I915_WRITE(EG2, 0x000e0000);
5312         I915_WRITE(EG3, 0x68000300);
5313         I915_WRITE(EG4, 0x42000000);
5314         I915_WRITE(EG5, 0x00140031);
5315         I915_WRITE(EG6, 0);
5316         I915_WRITE(EG7, 0);
5317
5318         for (i = 0; i < 8; i++)
5319                 I915_WRITE(PXWL + (i * 4), 0);
5320
5321         /* Enable PMON + select events */
5322         I915_WRITE(ECR, 0x80000019);
5323
5324         lcfuse = I915_READ(LCFUSE02);
5325
5326         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
5327 }
5328
5329 void intel_init_gt_powersave(struct drm_device *dev)
5330 {
5331         i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
5332
5333         if (IS_CHERRYVIEW(dev))
5334                 cherryview_init_gt_powersave(dev);
5335         else if (IS_VALLEYVIEW(dev))
5336                 valleyview_init_gt_powersave(dev);
5337 }
5338
5339 void intel_cleanup_gt_powersave(struct drm_device *dev)
5340 {
5341         if (IS_CHERRYVIEW(dev))
5342                 return;
5343         else if (IS_VALLEYVIEW(dev))
5344                 valleyview_cleanup_gt_powersave(dev);
5345 }
5346
5347 /**
5348  * intel_suspend_gt_powersave - suspend PM work and helper threads
5349  * @dev: drm device
5350  *
5351  * We don't want to disable RC6 or other features here, we just want
5352  * to make sure any work we've queued has finished and won't bother
5353  * us while we're suspended.
5354  */
5355 void intel_suspend_gt_powersave(struct drm_device *dev)
5356 {
5357         struct drm_i915_private *dev_priv = dev->dev_private;
5358
5359         /* Interrupts should be disabled already to avoid re-arming. */
5360         WARN_ON(intel_irqs_enabled(dev_priv));
5361
5362         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5363
5364         cancel_work_sync(&dev_priv->rps.work);
5365
5366         /* Force GPU to min freq during suspend */
5367         gen6_rps_idle(dev_priv);
5368 }
5369
5370 void intel_disable_gt_powersave(struct drm_device *dev)
5371 {
5372         struct drm_i915_private *dev_priv = dev->dev_private;
5373
5374         /* Interrupts should be disabled already to avoid re-arming. */
5375         WARN_ON(intel_irqs_enabled(dev_priv));
5376
5377         if (IS_IRONLAKE_M(dev)) {
5378                 ironlake_disable_drps(dev);
5379                 ironlake_disable_rc6(dev);
5380         } else if (INTEL_INFO(dev)->gen >= 6) {
5381                 intel_suspend_gt_powersave(dev);
5382
5383                 mutex_lock(&dev_priv->rps.hw_lock);
5384                 if (IS_CHERRYVIEW(dev))
5385                         cherryview_disable_rps(dev);
5386                 else if (IS_VALLEYVIEW(dev))
5387                         valleyview_disable_rps(dev);
5388                 else
5389                         gen6_disable_rps(dev);
5390                 dev_priv->rps.enabled = false;
5391                 mutex_unlock(&dev_priv->rps.hw_lock);
5392         }
5393 }
5394
5395 static void intel_gen6_powersave_work(struct work_struct *work)
5396 {
5397         struct drm_i915_private *dev_priv =
5398                 container_of(work, struct drm_i915_private,
5399                              rps.delayed_resume_work.work);
5400         struct drm_device *dev = dev_priv->dev;
5401
5402         dev_priv->rps.is_bdw_sw_turbo = false;
5403
5404         mutex_lock(&dev_priv->rps.hw_lock);
5405
5406         if (IS_CHERRYVIEW(dev)) {
5407                 cherryview_enable_rps(dev);
5408         } else if (IS_VALLEYVIEW(dev)) {
5409                 valleyview_enable_rps(dev);
5410         } else if (IS_BROADWELL(dev)) {
5411                 gen8_enable_rps(dev);
5412                 __gen6_update_ring_freq(dev);
5413         } else {
5414                 gen6_enable_rps(dev);
5415                 __gen6_update_ring_freq(dev);
5416         }
5417         dev_priv->rps.enabled = true;
5418         mutex_unlock(&dev_priv->rps.hw_lock);
5419
5420         intel_runtime_pm_put(dev_priv);
5421 }
5422
5423 void intel_enable_gt_powersave(struct drm_device *dev)
5424 {
5425         struct drm_i915_private *dev_priv = dev->dev_private;
5426
5427         if (IS_IRONLAKE_M(dev)) {
5428                 mutex_lock(&dev->struct_mutex);
5429                 ironlake_enable_drps(dev);
5430                 ironlake_enable_rc6(dev);
5431                 intel_init_emon(dev);
5432                 mutex_unlock(&dev->struct_mutex);
5433         } else if (INTEL_INFO(dev)->gen >= 6) {
5434                 /*
5435                  * PCU communication is slow and this doesn't need to be
5436                  * done at any specific time, so do this out of our fast path
5437                  * to make resume and init faster.
5438                  *
5439                  * We depend on the HW RC6 power context save/restore
5440                  * mechanism when entering D3 through runtime PM suspend. So
5441                  * disable RPM until RPS/RC6 is properly setup. We can only
5442                  * get here via the driver load/system resume/runtime resume
5443                  * paths, so the _noresume version is enough (and in case of
5444                  * runtime resume it's necessary).
5445                  */
5446                 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
5447                                            round_jiffies_up_relative(HZ)))
5448                         intel_runtime_pm_get_noresume(dev_priv);
5449         }
5450 }
5451
5452 void intel_reset_gt_powersave(struct drm_device *dev)
5453 {
5454         struct drm_i915_private *dev_priv = dev->dev_private;
5455
5456         dev_priv->rps.enabled = false;
5457         intel_enable_gt_powersave(dev);
5458 }
5459
5460 static void ibx_init_clock_gating(struct drm_device *dev)
5461 {
5462         struct drm_i915_private *dev_priv = dev->dev_private;
5463
5464         /*
5465          * On Ibex Peak and Cougar Point, we need to disable clock
5466          * gating for the panel power sequencer or it will fail to
5467          * start up when no ports are active.
5468          */
5469         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
5470 }
5471
5472 static void g4x_disable_trickle_feed(struct drm_device *dev)
5473 {
5474         struct drm_i915_private *dev_priv = dev->dev_private;
5475         int pipe;
5476
5477         for_each_pipe(dev_priv, pipe) {
5478                 I915_WRITE(DSPCNTR(pipe),
5479                            I915_READ(DSPCNTR(pipe)) |
5480                            DISPPLANE_TRICKLE_FEED_DISABLE);
5481                 intel_flush_primary_plane(dev_priv, pipe);
5482         }
5483 }
5484
5485 static void ilk_init_lp_watermarks(struct drm_device *dev)
5486 {
5487         struct drm_i915_private *dev_priv = dev->dev_private;
5488
5489         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
5490         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
5491         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
5492
5493         /*
5494          * Don't touch WM1S_LP_EN here.
5495          * Doing so could cause underruns.
5496          */
5497 }
5498
5499 static void ironlake_init_clock_gating(struct drm_device *dev)
5500 {
5501         struct drm_i915_private *dev_priv = dev->dev_private;
5502         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
5503
5504         /*
5505          * Required for FBC
5506          * WaFbcDisableDpfcClockGating:ilk
5507          */
5508         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
5509                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
5510                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
5511
5512         I915_WRITE(PCH_3DCGDIS0,
5513                    MARIUNIT_CLOCK_GATE_DISABLE |
5514                    SVSMUNIT_CLOCK_GATE_DISABLE);
5515         I915_WRITE(PCH_3DCGDIS1,
5516                    VFMUNIT_CLOCK_GATE_DISABLE);
5517
5518         /*
5519          * According to the spec the following bits should be set in
5520          * order to enable memory self-refresh
5521          * The bit 22/21 of 0x42004
5522          * The bit 5 of 0x42020
5523          * The bit 15 of 0x45000
5524          */
5525         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5526                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
5527                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5528         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
5529         I915_WRITE(DISP_ARB_CTL,
5530                    (I915_READ(DISP_ARB_CTL) |
5531                     DISP_FBC_WM_DIS));
5532
5533         ilk_init_lp_watermarks(dev);
5534
5535         /*
5536          * Based on the document from hardware guys the following bits
5537          * should be set unconditionally in order to enable FBC.
5538          * The bit 22 of 0x42000
5539          * The bit 22 of 0x42004
5540          * The bit 7,8,9 of 0x42020.
5541          */
5542         if (IS_IRONLAKE_M(dev)) {
5543                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
5544                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5545                            I915_READ(ILK_DISPLAY_CHICKEN1) |
5546                            ILK_FBCQ_DIS);
5547                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5548                            I915_READ(ILK_DISPLAY_CHICKEN2) |
5549                            ILK_DPARB_GATE);
5550         }
5551
5552         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5553
5554         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5555                    I915_READ(ILK_DISPLAY_CHICKEN2) |
5556                    ILK_ELPIN_409_SELECT);
5557         I915_WRITE(_3D_CHICKEN2,
5558                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
5559                    _3D_CHICKEN2_WM_READ_PIPELINED);
5560
5561         /* WaDisableRenderCachePipelinedFlush:ilk */
5562         I915_WRITE(CACHE_MODE_0,
5563                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5564
5565         /* WaDisable_RenderCache_OperationalFlush:ilk */
5566         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5567
5568         g4x_disable_trickle_feed(dev);
5569
5570         ibx_init_clock_gating(dev);
5571 }
5572
5573 static void cpt_init_clock_gating(struct drm_device *dev)
5574 {
5575         struct drm_i915_private *dev_priv = dev->dev_private;
5576         int pipe;
5577         uint32_t val;
5578
5579         /*
5580          * On Ibex Peak and Cougar Point, we need to disable clock
5581          * gating for the panel power sequencer or it will fail to
5582          * start up when no ports are active.
5583          */
5584         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
5585                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
5586                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
5587         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
5588                    DPLS_EDP_PPS_FIX_DIS);
5589         /* The below fixes the weird display corruption, a few pixels shifted
5590          * downward, on (only) LVDS of some HP laptops with IVY.
5591          */
5592         for_each_pipe(dev_priv, pipe) {
5593                 val = I915_READ(TRANS_CHICKEN2(pipe));
5594                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
5595                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
5596                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
5597                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
5598                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
5599                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
5600                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
5601                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
5602         }
5603         /* WADP0ClockGatingDisable */
5604         for_each_pipe(dev_priv, pipe) {
5605                 I915_WRITE(TRANS_CHICKEN1(pipe),
5606                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5607         }
5608 }
5609
5610 static void gen6_check_mch_setup(struct drm_device *dev)
5611 {
5612         struct drm_i915_private *dev_priv = dev->dev_private;
5613         uint32_t tmp;
5614
5615         tmp = I915_READ(MCH_SSKPD);
5616         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
5617                 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
5618                               tmp);
5619 }
5620
5621 static void gen6_init_clock_gating(struct drm_device *dev)
5622 {
5623         struct drm_i915_private *dev_priv = dev->dev_private;
5624         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
5625
5626         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5627
5628         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5629                    I915_READ(ILK_DISPLAY_CHICKEN2) |
5630                    ILK_ELPIN_409_SELECT);
5631
5632         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
5633         I915_WRITE(_3D_CHICKEN,
5634                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
5635
5636         /* WaSetupGtModeTdRowDispatch:snb */
5637         if (IS_SNB_GT1(dev))
5638                 I915_WRITE(GEN6_GT_MODE,
5639                            _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
5640
5641         /* WaDisable_RenderCache_OperationalFlush:snb */
5642         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5643
5644         /*
5645          * BSpec recoomends 8x4 when MSAA is used,
5646          * however in practice 16x4 seems fastest.
5647          *
5648          * Note that PS/WM thread counts depend on the WIZ hashing
5649          * disable bit, which we don't touch here, but it's good
5650          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5651          */
5652         I915_WRITE(GEN6_GT_MODE,
5653                    GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5654
5655         ilk_init_lp_watermarks(dev);
5656
5657         I915_WRITE(CACHE_MODE_0,
5658                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
5659
5660         I915_WRITE(GEN6_UCGCTL1,
5661                    I915_READ(GEN6_UCGCTL1) |
5662                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
5663                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5664
5665         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5666          * gating disable must be set.  Failure to set it results in
5667          * flickering pixels due to Z write ordering failures after
5668          * some amount of runtime in the Mesa "fire" demo, and Unigine
5669          * Sanctuary and Tropics, and apparently anything else with
5670          * alpha test or pixel discard.
5671          *
5672          * According to the spec, bit 11 (RCCUNIT) must also be set,
5673          * but we didn't debug actual testcases to find it out.
5674          *
5675          * WaDisableRCCUnitClockGating:snb
5676          * WaDisableRCPBUnitClockGating:snb
5677          */
5678         I915_WRITE(GEN6_UCGCTL2,
5679                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5680                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5681
5682         /* WaStripsFansDisableFastClipPerformanceFix:snb */
5683         I915_WRITE(_3D_CHICKEN3,
5684                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
5685
5686         /*
5687          * Bspec says:
5688          * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
5689          * 3DSTATE_SF number of SF output attributes is more than 16."
5690          */
5691         I915_WRITE(_3D_CHICKEN3,
5692                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
5693
5694         /*
5695          * According to the spec the following bits should be
5696          * set in order to enable memory self-refresh and fbc:
5697          * The bit21 and bit22 of 0x42000
5698          * The bit21 and bit22 of 0x42004
5699          * The bit5 and bit7 of 0x42020
5700          * The bit14 of 0x70180
5701          * The bit14 of 0x71180
5702          *
5703          * WaFbcAsynchFlipDisableFbcQueue:snb
5704          */
5705         I915_WRITE(ILK_DISPLAY_CHICKEN1,
5706                    I915_READ(ILK_DISPLAY_CHICKEN1) |
5707                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
5708         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5709                    I915_READ(ILK_DISPLAY_CHICKEN2) |
5710                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
5711         I915_WRITE(ILK_DSPCLK_GATE_D,
5712                    I915_READ(ILK_DSPCLK_GATE_D) |
5713                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
5714                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
5715
5716         g4x_disable_trickle_feed(dev);
5717
5718         cpt_init_clock_gating(dev);
5719
5720         gen6_check_mch_setup(dev);
5721 }
5722
5723 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
5724 {
5725         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
5726
5727         /*
5728          * WaVSThreadDispatchOverride:ivb,vlv
5729          *
5730          * This actually overrides the dispatch
5731          * mode for all thread types.
5732          */
5733         reg &= ~GEN7_FF_SCHED_MASK;
5734         reg |= GEN7_FF_TS_SCHED_HW;
5735         reg |= GEN7_FF_VS_SCHED_HW;
5736         reg |= GEN7_FF_DS_SCHED_HW;
5737
5738         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
5739 }
5740
5741 static void lpt_init_clock_gating(struct drm_device *dev)
5742 {
5743         struct drm_i915_private *dev_priv = dev->dev_private;
5744
5745         /*
5746          * TODO: this bit should only be enabled when really needed, then
5747          * disabled when not needed anymore in order to save power.
5748          */
5749         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
5750                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
5751                            I915_READ(SOUTH_DSPCLK_GATE_D) |
5752                            PCH_LP_PARTITION_LEVEL_DISABLE);
5753
5754         /* WADPOClockGatingDisable:hsw */
5755         I915_WRITE(_TRANSA_CHICKEN1,
5756                    I915_READ(_TRANSA_CHICKEN1) |
5757                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5758 }
5759
5760 static void lpt_suspend_hw(struct drm_device *dev)
5761 {
5762         struct drm_i915_private *dev_priv = dev->dev_private;
5763
5764         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
5765                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
5766
5767                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
5768                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
5769         }
5770 }
5771
5772 static void broadwell_init_clock_gating(struct drm_device *dev)
5773 {
5774         struct drm_i915_private *dev_priv = dev->dev_private;
5775         enum pipe pipe;
5776
5777         I915_WRITE(WM3_LP_ILK, 0);
5778         I915_WRITE(WM2_LP_ILK, 0);
5779         I915_WRITE(WM1_LP_ILK, 0);
5780
5781         /* FIXME(BDW): Check all the w/a, some might only apply to
5782          * pre-production hw. */
5783
5784
5785         I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
5786
5787         I915_WRITE(_3D_CHICKEN3,
5788                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2)));
5789
5790
5791         /* WaSwitchSolVfFArbitrationPriority:bdw */
5792         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5793
5794         /* WaPsrDPAMaskVBlankInSRD:bdw */
5795         I915_WRITE(CHICKEN_PAR1_1,
5796                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
5797
5798         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
5799         for_each_pipe(dev_priv, pipe) {
5800                 I915_WRITE(CHICKEN_PIPESL_1(pipe),
5801                            I915_READ(CHICKEN_PIPESL_1(pipe)) |
5802                            BDW_DPRS_MASK_VBLANK_SRD);
5803         }
5804
5805         /* WaVSRefCountFullforceMissDisable:bdw */
5806         /* WaDSRefCountFullforceMissDisable:bdw */
5807         I915_WRITE(GEN7_FF_THREAD_MODE,
5808                    I915_READ(GEN7_FF_THREAD_MODE) &
5809                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
5810
5811         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5812                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
5813
5814         /* WaDisableSDEUnitClockGating:bdw */
5815         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5816                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5817
5818         lpt_init_clock_gating(dev);
5819 }
5820
5821 static void haswell_init_clock_gating(struct drm_device *dev)
5822 {
5823         struct drm_i915_private *dev_priv = dev->dev_private;
5824
5825         ilk_init_lp_watermarks(dev);
5826
5827         /* L3 caching of data atomics doesn't work -- disable it. */
5828         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
5829         I915_WRITE(HSW_ROW_CHICKEN3,
5830                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
5831
5832         /* This is required by WaCatErrorRejectionIssue:hsw */
5833         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5834                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5835                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5836
5837         /* WaVSRefCountFullforceMissDisable:hsw */
5838         I915_WRITE(GEN7_FF_THREAD_MODE,
5839                    I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
5840
5841         /* WaDisable_RenderCache_OperationalFlush:hsw */
5842         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5843
5844         /* enable HiZ Raw Stall Optimization */
5845         I915_WRITE(CACHE_MODE_0_GEN7,
5846                    _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5847
5848         /* WaDisable4x2SubspanOptimization:hsw */
5849         I915_WRITE(CACHE_MODE_1,
5850                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5851
5852         /*
5853          * BSpec recommends 8x4 when MSAA is used,
5854          * however in practice 16x4 seems fastest.
5855          *
5856          * Note that PS/WM thread counts depend on the WIZ hashing
5857          * disable bit, which we don't touch here, but it's good
5858          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5859          */
5860         I915_WRITE(GEN7_GT_MODE,
5861                    GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5862
5863         /* WaSwitchSolVfFArbitrationPriority:hsw */
5864         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5865
5866         /* WaRsPkgCStateDisplayPMReq:hsw */
5867         I915_WRITE(CHICKEN_PAR1_1,
5868                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
5869
5870         lpt_init_clock_gating(dev);
5871 }
5872
5873 static void ivybridge_init_clock_gating(struct drm_device *dev)
5874 {
5875         struct drm_i915_private *dev_priv = dev->dev_private;
5876         uint32_t snpcr;
5877
5878         ilk_init_lp_watermarks(dev);
5879
5880         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
5881
5882         /* WaDisableEarlyCull:ivb */
5883         I915_WRITE(_3D_CHICKEN3,
5884                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5885
5886         /* WaDisableBackToBackFlipFix:ivb */
5887         I915_WRITE(IVB_CHICKEN3,
5888                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5889                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
5890
5891         /* WaDisablePSDDualDispatchEnable:ivb */
5892         if (IS_IVB_GT1(dev))
5893                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5894                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5895
5896         /* WaDisable_RenderCache_OperationalFlush:ivb */
5897         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5898
5899         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
5900         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5901                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5902
5903         /* WaApplyL3ControlAndL3ChickenMode:ivb */
5904         I915_WRITE(GEN7_L3CNTLREG1,
5905                         GEN7_WA_FOR_GEN7_L3_CONTROL);
5906         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5907                    GEN7_WA_L3_CHICKEN_MODE);
5908         if (IS_IVB_GT1(dev))
5909                 I915_WRITE(GEN7_ROW_CHICKEN2,
5910                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5911         else {
5912                 /* must write both registers */
5913                 I915_WRITE(GEN7_ROW_CHICKEN2,
5914                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5915                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5916                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5917         }
5918
5919         /* WaForceL3Serialization:ivb */
5920         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5921                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5922
5923         /*
5924          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5925          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
5926          */
5927         I915_WRITE(GEN6_UCGCTL2,
5928                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5929
5930         /* This is required by WaCatErrorRejectionIssue:ivb */
5931         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5932                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5933                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5934
5935         g4x_disable_trickle_feed(dev);
5936
5937         gen7_setup_fixed_func_scheduler(dev_priv);
5938
5939         if (0) { /* causes HiZ corruption on ivb:gt1 */
5940                 /* enable HiZ Raw Stall Optimization */
5941                 I915_WRITE(CACHE_MODE_0_GEN7,
5942                            _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5943         }
5944
5945         /* WaDisable4x2SubspanOptimization:ivb */
5946         I915_WRITE(CACHE_MODE_1,
5947                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5948
5949         /*
5950          * BSpec recommends 8x4 when MSAA is used,
5951          * however in practice 16x4 seems fastest.
5952          *
5953          * Note that PS/WM thread counts depend on the WIZ hashing
5954          * disable bit, which we don't touch here, but it's good
5955          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5956          */
5957         I915_WRITE(GEN7_GT_MODE,
5958                    GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5959
5960         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5961         snpcr &= ~GEN6_MBC_SNPCR_MASK;
5962         snpcr |= GEN6_MBC_SNPCR_MED;
5963         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5964
5965         if (!HAS_PCH_NOP(dev))
5966                 cpt_init_clock_gating(dev);
5967
5968         gen6_check_mch_setup(dev);
5969 }
5970
5971 static void valleyview_init_clock_gating(struct drm_device *dev)
5972 {
5973         struct drm_i915_private *dev_priv = dev->dev_private;
5974
5975         I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5976
5977         /* WaDisableEarlyCull:vlv */
5978         I915_WRITE(_3D_CHICKEN3,
5979                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5980
5981         /* WaDisableBackToBackFlipFix:vlv */
5982         I915_WRITE(IVB_CHICKEN3,
5983                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5984                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
5985
5986         /* WaPsdDispatchEnable:vlv */
5987         /* WaDisablePSDDualDispatchEnable:vlv */
5988         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5989                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5990                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5991
5992         /* WaDisable_RenderCache_OperationalFlush:vlv */
5993         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5994
5995         /* WaForceL3Serialization:vlv */
5996         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5997                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5998
5999         /* WaDisableDopClockGating:vlv */
6000         I915_WRITE(GEN7_ROW_CHICKEN2,
6001                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6002
6003         /* This is required by WaCatErrorRejectionIssue:vlv */
6004         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6005                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6006                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6007
6008         gen7_setup_fixed_func_scheduler(dev_priv);
6009
6010         /*
6011          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6012          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
6013          */
6014         I915_WRITE(GEN6_UCGCTL2,
6015                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6016
6017         /* WaDisableL3Bank2xClockGate:vlv
6018          * Disabling L3 clock gating- MMIO 940c[25] = 1
6019          * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6020         I915_WRITE(GEN7_UCGCTL4,
6021                    I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
6022
6023         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6024
6025         /*
6026          * BSpec says this must be set, even though
6027          * WaDisable4x2SubspanOptimization isn't listed for VLV.
6028          */
6029         I915_WRITE(CACHE_MODE_1,
6030                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6031
6032         /*
6033          * WaIncreaseL3CreditsForVLVB0:vlv
6034          * This is the hardware default actually.
6035          */
6036         I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6037
6038         /*
6039          * WaDisableVLVClockGating_VBIIssue:vlv
6040          * Disable clock gating on th GCFG unit to prevent a delay
6041          * in the reporting of vblank events.
6042          */
6043         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6044 }
6045
6046 static void cherryview_init_clock_gating(struct drm_device *dev)
6047 {
6048         struct drm_i915_private *dev_priv = dev->dev_private;
6049
6050         I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6051
6052         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6053
6054         /* WaVSRefCountFullforceMissDisable:chv */
6055         /* WaDSRefCountFullforceMissDisable:chv */
6056         I915_WRITE(GEN7_FF_THREAD_MODE,
6057                    I915_READ(GEN7_FF_THREAD_MODE) &
6058                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6059
6060         /* WaDisableSemaphoreAndSyncFlipWait:chv */
6061         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6062                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6063
6064         /* WaDisableCSUnitClockGating:chv */
6065         I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6066                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6067
6068         /* WaDisableSDEUnitClockGating:chv */
6069         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6070                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6071
6072         /* WaDisableGunitClockGating:chv (pre-production hw) */
6073         I915_WRITE(VLV_GUNIT_CLOCK_GATE, I915_READ(VLV_GUNIT_CLOCK_GATE) |
6074                    GINT_DIS);
6075
6076         /* WaDisableFfDopClockGating:chv (pre-production hw) */
6077         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6078                    _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE));
6079
6080         /* WaDisableDopClockGating:chv (pre-production hw) */
6081         I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6082                    GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
6083 }
6084
6085 static void g4x_init_clock_gating(struct drm_device *dev)
6086 {
6087         struct drm_i915_private *dev_priv = dev->dev_private;
6088         uint32_t dspclk_gate;
6089
6090         I915_WRITE(RENCLK_GATE_D1, 0);
6091         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6092                    GS_UNIT_CLOCK_GATE_DISABLE |
6093                    CL_UNIT_CLOCK_GATE_DISABLE);
6094         I915_WRITE(RAMCLK_GATE_D, 0);
6095         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6096                 OVRUNIT_CLOCK_GATE_DISABLE |
6097                 OVCUNIT_CLOCK_GATE_DISABLE;
6098         if (IS_GM45(dev))
6099                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6100         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
6101
6102         /* WaDisableRenderCachePipelinedFlush */
6103         I915_WRITE(CACHE_MODE_0,
6104                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6105
6106         /* WaDisable_RenderCache_OperationalFlush:g4x */
6107         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6108
6109         g4x_disable_trickle_feed(dev);
6110 }
6111
6112 static void crestline_init_clock_gating(struct drm_device *dev)
6113 {
6114         struct drm_i915_private *dev_priv = dev->dev_private;
6115
6116         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6117         I915_WRITE(RENCLK_GATE_D2, 0);
6118         I915_WRITE(DSPCLK_GATE_D, 0);
6119         I915_WRITE(RAMCLK_GATE_D, 0);
6120         I915_WRITE16(DEUC, 0);
6121         I915_WRITE(MI_ARB_STATE,
6122                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6123
6124         /* WaDisable_RenderCache_OperationalFlush:gen4 */
6125         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6126 }
6127
6128 static void broadwater_init_clock_gating(struct drm_device *dev)
6129 {
6130         struct drm_i915_private *dev_priv = dev->dev_private;
6131
6132         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6133                    I965_RCC_CLOCK_GATE_DISABLE |
6134                    I965_RCPB_CLOCK_GATE_DISABLE |
6135                    I965_ISC_CLOCK_GATE_DISABLE |
6136                    I965_FBC_CLOCK_GATE_DISABLE);
6137         I915_WRITE(RENCLK_GATE_D2, 0);
6138         I915_WRITE(MI_ARB_STATE,
6139                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6140
6141         /* WaDisable_RenderCache_OperationalFlush:gen4 */
6142         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6143 }
6144
6145 static void gen3_init_clock_gating(struct drm_device *dev)
6146 {
6147         struct drm_i915_private *dev_priv = dev->dev_private;
6148         u32 dstate = I915_READ(D_STATE);
6149
6150         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6151                 DSTATE_DOT_CLOCK_GATING;
6152         I915_WRITE(D_STATE, dstate);
6153
6154         if (IS_PINEVIEW(dev))
6155                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
6156
6157         /* IIR "flip pending" means done if this bit is set */
6158         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6159
6160         /* interrupts should cause a wake up from C3 */
6161         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
6162
6163         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
6164         I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
6165
6166         I915_WRITE(MI_ARB_STATE,
6167                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6168 }
6169
6170 static void i85x_init_clock_gating(struct drm_device *dev)
6171 {
6172         struct drm_i915_private *dev_priv = dev->dev_private;
6173
6174         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
6175
6176         /* interrupts should cause a wake up from C3 */
6177         I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
6178                    _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
6179
6180         I915_WRITE(MEM_MODE,
6181                    _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6182 }
6183
6184 static void i830_init_clock_gating(struct drm_device *dev)
6185 {
6186         struct drm_i915_private *dev_priv = dev->dev_private;
6187
6188         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
6189
6190         I915_WRITE(MEM_MODE,
6191                    _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
6192                    _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6193 }
6194
6195 void intel_init_clock_gating(struct drm_device *dev)
6196 {
6197         struct drm_i915_private *dev_priv = dev->dev_private;
6198
6199         dev_priv->display.init_clock_gating(dev);
6200 }
6201
6202 void intel_suspend_hw(struct drm_device *dev)
6203 {
6204         if (HAS_PCH_LPT(dev))
6205                 lpt_suspend_hw(dev);
6206 }
6207
6208 #define for_each_power_well(i, power_well, domain_mask, power_domains)  \
6209         for (i = 0;                                                     \
6210              i < (power_domains)->power_well_count &&                   \
6211                  ((power_well) = &(power_domains)->power_wells[i]);     \
6212              i++)                                                       \
6213                 if ((power_well)->domains & (domain_mask))
6214
6215 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
6216         for (i = (power_domains)->power_well_count - 1;                  \
6217              i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
6218              i--)                                                        \
6219                 if ((power_well)->domains & (domain_mask))
6220
6221 /**
6222  * We should only use the power well if we explicitly asked the hardware to
6223  * enable it, so check if it's enabled and also check if we've requested it to
6224  * be enabled.
6225  */
6226 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
6227                                    struct i915_power_well *power_well)
6228 {
6229         return I915_READ(HSW_PWR_WELL_DRIVER) ==
6230                      (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
6231 }
6232
6233 bool intel_display_power_enabled_unlocked(struct drm_i915_private *dev_priv,
6234                                           enum intel_display_power_domain domain)
6235 {
6236         struct i915_power_domains *power_domains;
6237         struct i915_power_well *power_well;
6238         bool is_enabled;
6239         int i;
6240
6241         if (dev_priv->pm.suspended)
6242                 return false;
6243
6244         power_domains = &dev_priv->power_domains;
6245
6246         is_enabled = true;
6247
6248         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
6249                 if (power_well->always_on)
6250                         continue;
6251
6252                 if (!power_well->hw_enabled) {
6253                         is_enabled = false;
6254                         break;
6255                 }
6256         }
6257
6258         return is_enabled;
6259 }
6260
6261 bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
6262                                  enum intel_display_power_domain domain)
6263 {
6264         struct i915_power_domains *power_domains;
6265         bool ret;
6266
6267         power_domains = &dev_priv->power_domains;
6268
6269         mutex_lock(&power_domains->lock);
6270         ret = intel_display_power_enabled_unlocked(dev_priv, domain);
6271         mutex_unlock(&power_domains->lock);
6272
6273         return ret;
6274 }
6275
6276 /*
6277  * Starting with Haswell, we have a "Power Down Well" that can be turned off
6278  * when not needed anymore. We have 4 registers that can request the power well
6279  * to be enabled, and it will only be disabled if none of the registers is
6280  * requesting it to be enabled.
6281  */
6282 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
6283 {
6284         struct drm_device *dev = dev_priv->dev;
6285
6286         /*
6287          * After we re-enable the power well, if we touch VGA register 0x3d5
6288          * we'll get unclaimed register interrupts. This stops after we write
6289          * anything to the VGA MSR register. The vgacon module uses this
6290          * register all the time, so if we unbind our driver and, as a
6291          * consequence, bind vgacon, we'll get stuck in an infinite loop at
6292          * console_unlock(). So make here we touch the VGA MSR register, making
6293          * sure vgacon can keep working normally without triggering interrupts
6294          * and error messages.
6295          */
6296         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6297         outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
6298         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6299
6300         if (IS_BROADWELL(dev) || (INTEL_INFO(dev)->gen >= 9))
6301                 gen8_irq_power_well_post_enable(dev_priv);
6302 }
6303
6304 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
6305                                struct i915_power_well *power_well, bool enable)
6306 {
6307         bool is_enabled, enable_requested;
6308         uint32_t tmp;
6309
6310         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
6311         is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
6312         enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
6313
6314         if (enable) {
6315                 if (!enable_requested)
6316                         I915_WRITE(HSW_PWR_WELL_DRIVER,
6317                                    HSW_PWR_WELL_ENABLE_REQUEST);
6318
6319                 if (!is_enabled) {
6320                         DRM_DEBUG_KMS("Enabling power well\n");
6321                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
6322                                       HSW_PWR_WELL_STATE_ENABLED), 20))
6323                                 DRM_ERROR("Timeout enabling power well\n");
6324                 }
6325
6326                 hsw_power_well_post_enable(dev_priv);
6327         } else {
6328                 if (enable_requested) {
6329                         I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
6330                         POSTING_READ(HSW_PWR_WELL_DRIVER);
6331                         DRM_DEBUG_KMS("Requesting to disable the power well\n");
6332                 }
6333         }
6334 }
6335
6336 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
6337                                    struct i915_power_well *power_well)
6338 {
6339         hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
6340
6341         /*
6342          * We're taking over the BIOS, so clear any requests made by it since
6343          * the driver is in charge now.
6344          */
6345         if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
6346                 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
6347 }
6348
6349 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
6350                                   struct i915_power_well *power_well)
6351 {
6352         hsw_set_power_well(dev_priv, power_well, true);
6353 }
6354
6355 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
6356                                    struct i915_power_well *power_well)
6357 {
6358         hsw_set_power_well(dev_priv, power_well, false);
6359 }
6360
6361 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
6362                                            struct i915_power_well *power_well)
6363 {
6364 }
6365
6366 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
6367                                              struct i915_power_well *power_well)
6368 {
6369         return true;
6370 }
6371
6372 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
6373                                struct i915_power_well *power_well, bool enable)
6374 {
6375         enum punit_power_well power_well_id = power_well->data;
6376         u32 mask;
6377         u32 state;
6378         u32 ctrl;
6379
6380         mask = PUNIT_PWRGT_MASK(power_well_id);
6381         state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
6382                          PUNIT_PWRGT_PWR_GATE(power_well_id);
6383
6384         mutex_lock(&dev_priv->rps.hw_lock);
6385
6386 #define COND \
6387         ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
6388
6389         if (COND)
6390                 goto out;
6391
6392         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
6393         ctrl &= ~mask;
6394         ctrl |= state;
6395         vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
6396
6397         if (wait_for(COND, 100))
6398                 DRM_ERROR("timout setting power well state %08x (%08x)\n",
6399                           state,
6400                           vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
6401
6402 #undef COND
6403
6404 out:
6405         mutex_unlock(&dev_priv->rps.hw_lock);
6406 }
6407
6408 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
6409                                    struct i915_power_well *power_well)
6410 {
6411         vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
6412 }
6413
6414 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
6415                                   struct i915_power_well *power_well)
6416 {
6417         vlv_set_power_well(dev_priv, power_well, true);
6418 }
6419
6420 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
6421                                    struct i915_power_well *power_well)
6422 {
6423         vlv_set_power_well(dev_priv, power_well, false);
6424 }
6425
6426 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
6427                                    struct i915_power_well *power_well)
6428 {
6429         int power_well_id = power_well->data;
6430         bool enabled = false;
6431         u32 mask;
6432         u32 state;
6433         u32 ctrl;
6434
6435         mask = PUNIT_PWRGT_MASK(power_well_id);
6436         ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
6437
6438         mutex_lock(&dev_priv->rps.hw_lock);
6439
6440         state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
6441         /*
6442          * We only ever set the power-on and power-gate states, anything
6443          * else is unexpected.
6444          */
6445         WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
6446                 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
6447         if (state == ctrl)
6448                 enabled = true;
6449
6450         /*
6451          * A transient state at this point would mean some unexpected party
6452          * is poking at the power controls too.
6453          */
6454         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
6455         WARN_ON(ctrl != state);
6456
6457         mutex_unlock(&dev_priv->rps.hw_lock);
6458
6459         return enabled;
6460 }
6461
6462 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
6463                                           struct i915_power_well *power_well)
6464 {
6465         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
6466
6467         vlv_set_power_well(dev_priv, power_well, true);
6468
6469         spin_lock_irq(&dev_priv->irq_lock);
6470         valleyview_enable_display_irqs(dev_priv);
6471         spin_unlock_irq(&dev_priv->irq_lock);
6472
6473         /*
6474          * During driver initialization/resume we can avoid restoring the
6475          * part of the HW/SW state that will be inited anyway explicitly.
6476          */
6477         if (dev_priv->power_domains.initializing)
6478                 return;
6479
6480         intel_hpd_init(dev_priv->dev);
6481
6482         i915_redisable_vga_power_on(dev_priv->dev);
6483 }
6484
6485 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
6486                                            struct i915_power_well *power_well)
6487 {
6488         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
6489
6490         spin_lock_irq(&dev_priv->irq_lock);
6491         valleyview_disable_display_irqs(dev_priv);
6492         spin_unlock_irq(&dev_priv->irq_lock);
6493
6494         vlv_set_power_well(dev_priv, power_well, false);
6495
6496         vlv_power_sequencer_reset(dev_priv);
6497 }
6498
6499 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
6500                                            struct i915_power_well *power_well)
6501 {
6502         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
6503
6504         /*
6505          * Enable the CRI clock source so we can get at the
6506          * display and the reference clock for VGA
6507          * hotplug / manual detection.
6508          */
6509         I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
6510                    DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
6511         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
6512
6513         vlv_set_power_well(dev_priv, power_well, true);
6514
6515         /*
6516          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
6517          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
6518          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
6519          *   b. The other bits such as sfr settings / modesel may all
6520          *      be set to 0.
6521          *
6522          * This should only be done on init and resume from S3 with
6523          * both PLLs disabled, or we risk losing DPIO and PLL
6524          * synchronization.
6525          */
6526         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
6527 }
6528
6529 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
6530                                             struct i915_power_well *power_well)
6531 {
6532         enum pipe pipe;
6533
6534         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
6535
6536         for_each_pipe(dev_priv, pipe)
6537                 assert_pll_disabled(dev_priv, pipe);
6538
6539         /* Assert common reset */
6540         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
6541
6542         vlv_set_power_well(dev_priv, power_well, false);
6543 }
6544
6545 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
6546                                            struct i915_power_well *power_well)
6547 {
6548         enum dpio_phy phy;
6549
6550         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
6551                      power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
6552
6553         /*
6554          * Enable the CRI clock source so we can get at the
6555          * display and the reference clock for VGA
6556          * hotplug / manual detection.
6557          */
6558         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
6559                 phy = DPIO_PHY0;
6560                 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
6561                            DPLL_REFA_CLK_ENABLE_VLV);
6562                 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
6563                            DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
6564         } else {
6565                 phy = DPIO_PHY1;
6566                 I915_WRITE(DPLL(PIPE_C), I915_READ(DPLL(PIPE_C)) |
6567                            DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
6568         }
6569         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
6570         vlv_set_power_well(dev_priv, power_well, true);
6571
6572         /* Poll for phypwrgood signal */
6573         if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
6574                 DRM_ERROR("Display PHY %d is not power up\n", phy);
6575
6576         I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) |
6577                    PHY_COM_LANE_RESET_DEASSERT(phy));
6578 }
6579
6580 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
6581                                             struct i915_power_well *power_well)
6582 {
6583         enum dpio_phy phy;
6584
6585         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
6586                      power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
6587
6588         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
6589                 phy = DPIO_PHY0;
6590                 assert_pll_disabled(dev_priv, PIPE_A);
6591                 assert_pll_disabled(dev_priv, PIPE_B);
6592         } else {
6593                 phy = DPIO_PHY1;
6594                 assert_pll_disabled(dev_priv, PIPE_C);
6595         }
6596
6597         I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) &
6598                    ~PHY_COM_LANE_RESET_DEASSERT(phy));
6599
6600         vlv_set_power_well(dev_priv, power_well, false);
6601 }
6602
6603 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
6604                                         struct i915_power_well *power_well)
6605 {
6606         enum pipe pipe = power_well->data;
6607         bool enabled;
6608         u32 state, ctrl;
6609
6610         mutex_lock(&dev_priv->rps.hw_lock);
6611
6612         state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
6613         /*
6614          * We only ever set the power-on and power-gate states, anything
6615          * else is unexpected.
6616          */
6617         WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
6618         enabled = state == DP_SSS_PWR_ON(pipe);
6619
6620         /*
6621          * A transient state at this point would mean some unexpected party
6622          * is poking at the power controls too.
6623          */
6624         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
6625         WARN_ON(ctrl << 16 != state);
6626
6627         mutex_unlock(&dev_priv->rps.hw_lock);
6628
6629         return enabled;
6630 }
6631
6632 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
6633                                     struct i915_power_well *power_well,
6634                                     bool enable)
6635 {
6636         enum pipe pipe = power_well->data;
6637         u32 state;
6638         u32 ctrl;
6639
6640         state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
6641
6642         mutex_lock(&dev_priv->rps.hw_lock);
6643
6644 #define COND \
6645         ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
6646
6647         if (COND)
6648                 goto out;
6649
6650         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6651         ctrl &= ~DP_SSC_MASK(pipe);
6652         ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
6653         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
6654
6655         if (wait_for(COND, 100))
6656                 DRM_ERROR("timout setting power well state %08x (%08x)\n",
6657                           state,
6658                           vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
6659
6660 #undef COND
6661
6662 out:
6663         mutex_unlock(&dev_priv->rps.hw_lock);
6664 }
6665
6666 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
6667                                         struct i915_power_well *power_well)
6668 {
6669         chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
6670 }
6671
6672 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
6673                                        struct i915_power_well *power_well)
6674 {
6675         WARN_ON_ONCE(power_well->data != PIPE_A &&
6676                      power_well->data != PIPE_B &&
6677                      power_well->data != PIPE_C);
6678
6679         chv_set_pipe_power_well(dev_priv, power_well, true);
6680 }
6681
6682 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
6683                                         struct i915_power_well *power_well)
6684 {
6685         WARN_ON_ONCE(power_well->data != PIPE_A &&
6686                      power_well->data != PIPE_B &&
6687                      power_well->data != PIPE_C);
6688
6689         chv_set_pipe_power_well(dev_priv, power_well, false);
6690 }
6691
6692 static void check_power_well_state(struct drm_i915_private *dev_priv,
6693                                    struct i915_power_well *power_well)
6694 {
6695         bool enabled = power_well->ops->is_enabled(dev_priv, power_well);
6696
6697         if (power_well->always_on || !i915.disable_power_well) {
6698                 if (!enabled)
6699                         goto mismatch;
6700
6701                 return;
6702         }
6703
6704         if (enabled != (power_well->count > 0))
6705                 goto mismatch;
6706
6707         return;
6708
6709 mismatch:
6710         WARN(1, "state mismatch for '%s' (always_on %d hw state %d use-count %d disable_power_well %d\n",
6711                   power_well->name, power_well->always_on, enabled,
6712                   power_well->count, i915.disable_power_well);
6713 }
6714
6715 void intel_display_power_get(struct drm_i915_private *dev_priv,
6716                              enum intel_display_power_domain domain)
6717 {
6718         struct i915_power_domains *power_domains;
6719         struct i915_power_well *power_well;
6720         int i;
6721
6722         intel_runtime_pm_get(dev_priv);
6723
6724         power_domains = &dev_priv->power_domains;
6725
6726         mutex_lock(&power_domains->lock);
6727
6728         for_each_power_well(i, power_well, BIT(domain), power_domains) {
6729                 if (!power_well->count++) {
6730                         DRM_DEBUG_KMS("enabling %s\n", power_well->name);
6731                         power_well->ops->enable(dev_priv, power_well);
6732                         power_well->hw_enabled = true;
6733                 }
6734
6735                 check_power_well_state(dev_priv, power_well);
6736         }
6737
6738         power_domains->domain_use_count[domain]++;
6739
6740         mutex_unlock(&power_domains->lock);
6741 }
6742
6743 void intel_display_power_put(struct drm_i915_private *dev_priv,
6744                              enum intel_display_power_domain domain)
6745 {
6746         struct i915_power_domains *power_domains;
6747         struct i915_power_well *power_well;
6748         int i;
6749
6750         power_domains = &dev_priv->power_domains;
6751
6752         mutex_lock(&power_domains->lock);
6753
6754         WARN_ON(!power_domains->domain_use_count[domain]);
6755         power_domains->domain_use_count[domain]--;
6756
6757         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
6758                 WARN_ON(!power_well->count);
6759
6760                 if (!--power_well->count && i915.disable_power_well) {
6761                         DRM_DEBUG_KMS("disabling %s\n", power_well->name);
6762                         power_well->hw_enabled = false;
6763                         power_well->ops->disable(dev_priv, power_well);
6764                 }
6765
6766                 check_power_well_state(dev_priv, power_well);
6767         }
6768
6769         mutex_unlock(&power_domains->lock);
6770
6771         intel_runtime_pm_put(dev_priv);
6772 }
6773
6774 static struct i915_power_domains *hsw_pwr;
6775
6776 /* Display audio driver power well request */
6777 int i915_request_power_well(void)
6778 {
6779         struct drm_i915_private *dev_priv;
6780
6781         if (!hsw_pwr)
6782                 return -ENODEV;
6783
6784         dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6785                                 power_domains);
6786         intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
6787         return 0;
6788 }
6789 EXPORT_SYMBOL_GPL(i915_request_power_well);
6790
6791 /* Display audio driver power well release */
6792 int i915_release_power_well(void)
6793 {
6794         struct drm_i915_private *dev_priv;
6795
6796         if (!hsw_pwr)
6797                 return -ENODEV;
6798
6799         dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6800                                 power_domains);
6801         intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
6802         return 0;
6803 }
6804 EXPORT_SYMBOL_GPL(i915_release_power_well);
6805
6806 /*
6807  * Private interface for the audio driver to get CDCLK in kHz.
6808  *
6809  * Caller must request power well using i915_request_power_well() prior to
6810  * making the call.
6811  */
6812 int i915_get_cdclk_freq(void)
6813 {
6814         struct drm_i915_private *dev_priv;
6815
6816         if (!hsw_pwr)
6817                 return -ENODEV;
6818
6819         dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6820                                 power_domains);
6821
6822         return intel_ddi_get_cdclk_freq(dev_priv);
6823 }
6824 EXPORT_SYMBOL_GPL(i915_get_cdclk_freq);
6825
6826
6827 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
6828
6829 #define HSW_ALWAYS_ON_POWER_DOMAINS (                   \
6830         BIT(POWER_DOMAIN_PIPE_A) |                      \
6831         BIT(POWER_DOMAIN_TRANSCODER_EDP) |              \
6832         BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) |          \
6833         BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) |          \
6834         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |          \
6835         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |          \
6836         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |          \
6837         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |          \
6838         BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |          \
6839         BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |          \
6840         BIT(POWER_DOMAIN_PORT_CRT) |                    \
6841         BIT(POWER_DOMAIN_PLLS) |                        \
6842         BIT(POWER_DOMAIN_INIT))
6843 #define HSW_DISPLAY_POWER_DOMAINS (                             \
6844         (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) |    \
6845         BIT(POWER_DOMAIN_INIT))
6846
6847 #define BDW_ALWAYS_ON_POWER_DOMAINS (                   \
6848         HSW_ALWAYS_ON_POWER_DOMAINS |                   \
6849         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
6850 #define BDW_DISPLAY_POWER_DOMAINS (                             \
6851         (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) |    \
6852         BIT(POWER_DOMAIN_INIT))
6853
6854 #define VLV_ALWAYS_ON_POWER_DOMAINS     BIT(POWER_DOMAIN_INIT)
6855 #define VLV_DISPLAY_POWER_DOMAINS       POWER_DOMAIN_MASK
6856
6857 #define VLV_DPIO_CMN_BC_POWER_DOMAINS (         \
6858         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |  \
6859         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
6860         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |  \
6861         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
6862         BIT(POWER_DOMAIN_PORT_CRT) |            \
6863         BIT(POWER_DOMAIN_INIT))
6864
6865 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS (  \
6866         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |  \
6867         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
6868         BIT(POWER_DOMAIN_INIT))
6869
6870 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS (  \
6871         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
6872         BIT(POWER_DOMAIN_INIT))
6873
6874 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS (  \
6875         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |  \
6876         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
6877         BIT(POWER_DOMAIN_INIT))
6878
6879 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS (  \
6880         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
6881         BIT(POWER_DOMAIN_INIT))
6882
6883 #define CHV_PIPE_A_POWER_DOMAINS (      \
6884         BIT(POWER_DOMAIN_PIPE_A) |      \
6885         BIT(POWER_DOMAIN_INIT))
6886
6887 #define CHV_PIPE_B_POWER_DOMAINS (      \
6888         BIT(POWER_DOMAIN_PIPE_B) |      \
6889         BIT(POWER_DOMAIN_INIT))
6890
6891 #define CHV_PIPE_C_POWER_DOMAINS (      \
6892         BIT(POWER_DOMAIN_PIPE_C) |      \
6893         BIT(POWER_DOMAIN_INIT))
6894
6895 #define CHV_DPIO_CMN_BC_POWER_DOMAINS (         \
6896         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |  \
6897         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
6898         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |  \
6899         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
6900         BIT(POWER_DOMAIN_INIT))
6901
6902 #define CHV_DPIO_CMN_D_POWER_DOMAINS (          \
6903         BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |  \
6904         BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |  \
6905         BIT(POWER_DOMAIN_INIT))
6906
6907 #define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS (  \
6908         BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |  \
6909         BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |  \
6910         BIT(POWER_DOMAIN_INIT))
6911
6912 #define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS (  \
6913         BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |  \
6914         BIT(POWER_DOMAIN_INIT))
6915
6916 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
6917         .sync_hw = i9xx_always_on_power_well_noop,
6918         .enable = i9xx_always_on_power_well_noop,
6919         .disable = i9xx_always_on_power_well_noop,
6920         .is_enabled = i9xx_always_on_power_well_enabled,
6921 };
6922
6923 static const struct i915_power_well_ops chv_pipe_power_well_ops = {
6924         .sync_hw = chv_pipe_power_well_sync_hw,
6925         .enable = chv_pipe_power_well_enable,
6926         .disable = chv_pipe_power_well_disable,
6927         .is_enabled = chv_pipe_power_well_enabled,
6928 };
6929
6930 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
6931         .sync_hw = vlv_power_well_sync_hw,
6932         .enable = chv_dpio_cmn_power_well_enable,
6933         .disable = chv_dpio_cmn_power_well_disable,
6934         .is_enabled = vlv_power_well_enabled,
6935 };
6936
6937 static struct i915_power_well i9xx_always_on_power_well[] = {
6938         {
6939                 .name = "always-on",
6940                 .always_on = 1,
6941                 .domains = POWER_DOMAIN_MASK,
6942                 .ops = &i9xx_always_on_power_well_ops,
6943         },
6944 };
6945
6946 static const struct i915_power_well_ops hsw_power_well_ops = {
6947         .sync_hw = hsw_power_well_sync_hw,
6948         .enable = hsw_power_well_enable,
6949         .disable = hsw_power_well_disable,
6950         .is_enabled = hsw_power_well_enabled,
6951 };
6952
6953 static struct i915_power_well hsw_power_wells[] = {
6954         {
6955                 .name = "always-on",
6956                 .always_on = 1,
6957                 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
6958                 .ops = &i9xx_always_on_power_well_ops,
6959         },
6960         {
6961                 .name = "display",
6962                 .domains = HSW_DISPLAY_POWER_DOMAINS,
6963                 .ops = &hsw_power_well_ops,
6964         },
6965 };
6966
6967 static struct i915_power_well bdw_power_wells[] = {
6968         {
6969                 .name = "always-on",
6970                 .always_on = 1,
6971                 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
6972                 .ops = &i9xx_always_on_power_well_ops,
6973         },
6974         {
6975                 .name = "display",
6976                 .domains = BDW_DISPLAY_POWER_DOMAINS,
6977                 .ops = &hsw_power_well_ops,
6978         },
6979 };
6980
6981 static const struct i915_power_well_ops vlv_display_power_well_ops = {
6982         .sync_hw = vlv_power_well_sync_hw,
6983         .enable = vlv_display_power_well_enable,
6984         .disable = vlv_display_power_well_disable,
6985         .is_enabled = vlv_power_well_enabled,
6986 };
6987
6988 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
6989         .sync_hw = vlv_power_well_sync_hw,
6990         .enable = vlv_dpio_cmn_power_well_enable,
6991         .disable = vlv_dpio_cmn_power_well_disable,
6992         .is_enabled = vlv_power_well_enabled,
6993 };
6994
6995 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
6996         .sync_hw = vlv_power_well_sync_hw,
6997         .enable = vlv_power_well_enable,
6998         .disable = vlv_power_well_disable,
6999         .is_enabled = vlv_power_well_enabled,
7000 };
7001
7002 static struct i915_power_well vlv_power_wells[] = {
7003         {
7004                 .name = "always-on",
7005                 .always_on = 1,
7006                 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
7007                 .ops = &i9xx_always_on_power_well_ops,
7008         },
7009         {
7010                 .name = "display",
7011                 .domains = VLV_DISPLAY_POWER_DOMAINS,
7012                 .data = PUNIT_POWER_WELL_DISP2D,
7013                 .ops = &vlv_display_power_well_ops,
7014         },
7015         {
7016                 .name = "dpio-tx-b-01",
7017                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
7018                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
7019                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
7020                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
7021                 .ops = &vlv_dpio_power_well_ops,
7022                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
7023         },
7024         {
7025                 .name = "dpio-tx-b-23",
7026                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
7027                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
7028                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
7029                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
7030                 .ops = &vlv_dpio_power_well_ops,
7031                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
7032         },
7033         {
7034                 .name = "dpio-tx-c-01",
7035                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
7036                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
7037                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
7038                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
7039                 .ops = &vlv_dpio_power_well_ops,
7040                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
7041         },
7042         {
7043                 .name = "dpio-tx-c-23",
7044                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
7045                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
7046                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
7047                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
7048                 .ops = &vlv_dpio_power_well_ops,
7049                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
7050         },
7051         {
7052                 .name = "dpio-common",
7053                 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
7054                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
7055                 .ops = &vlv_dpio_cmn_power_well_ops,
7056         },
7057 };
7058
7059 static struct i915_power_well chv_power_wells[] = {
7060         {
7061                 .name = "always-on",
7062                 .always_on = 1,
7063                 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
7064                 .ops = &i9xx_always_on_power_well_ops,
7065         },
7066 #if 0
7067         {
7068                 .name = "display",
7069                 .domains = VLV_DISPLAY_POWER_DOMAINS,
7070                 .data = PUNIT_POWER_WELL_DISP2D,
7071                 .ops = &vlv_display_power_well_ops,
7072         },
7073         {
7074                 .name = "pipe-a",
7075                 .domains = CHV_PIPE_A_POWER_DOMAINS,
7076                 .data = PIPE_A,
7077                 .ops = &chv_pipe_power_well_ops,
7078         },
7079         {
7080                 .name = "pipe-b",
7081                 .domains = CHV_PIPE_B_POWER_DOMAINS,
7082                 .data = PIPE_B,
7083                 .ops = &chv_pipe_power_well_ops,
7084         },
7085         {
7086                 .name = "pipe-c",
7087                 .domains = CHV_PIPE_C_POWER_DOMAINS,
7088                 .data = PIPE_C,
7089                 .ops = &chv_pipe_power_well_ops,
7090         },
7091 #endif
7092         {
7093                 .name = "dpio-common-bc",
7094                 /*
7095                  * XXX: cmnreset for one PHY seems to disturb the other.
7096                  * As a workaround keep both powered on at the same
7097                  * time for now.
7098                  */
7099                 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS,
7100                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
7101                 .ops = &chv_dpio_cmn_power_well_ops,
7102         },
7103         {
7104                 .name = "dpio-common-d",
7105                 /*
7106                  * XXX: cmnreset for one PHY seems to disturb the other.
7107                  * As a workaround keep both powered on at the same
7108                  * time for now.
7109                  */
7110                 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS,
7111                 .data = PUNIT_POWER_WELL_DPIO_CMN_D,
7112                 .ops = &chv_dpio_cmn_power_well_ops,
7113         },
7114 #if 0
7115         {
7116                 .name = "dpio-tx-b-01",
7117                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
7118                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS,
7119                 .ops = &vlv_dpio_power_well_ops,
7120                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
7121         },
7122         {
7123                 .name = "dpio-tx-b-23",
7124                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
7125                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS,
7126                 .ops = &vlv_dpio_power_well_ops,
7127                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
7128         },
7129         {
7130                 .name = "dpio-tx-c-01",
7131                 .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
7132                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
7133                 .ops = &vlv_dpio_power_well_ops,
7134                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
7135         },
7136         {
7137                 .name = "dpio-tx-c-23",
7138                 .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
7139                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
7140                 .ops = &vlv_dpio_power_well_ops,
7141                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
7142         },
7143         {
7144                 .name = "dpio-tx-d-01",
7145                 .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
7146                            CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
7147                 .ops = &vlv_dpio_power_well_ops,
7148                 .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_01,
7149         },
7150         {
7151                 .name = "dpio-tx-d-23",
7152                 .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
7153                            CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
7154                 .ops = &vlv_dpio_power_well_ops,
7155                 .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_23,
7156         },
7157 #endif
7158 };
7159
7160 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
7161                                                  enum punit_power_well power_well_id)
7162 {
7163         struct i915_power_domains *power_domains = &dev_priv->power_domains;
7164         struct i915_power_well *power_well;
7165         int i;
7166
7167         for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
7168                 if (power_well->data == power_well_id)
7169                         return power_well;
7170         }
7171
7172         return NULL;
7173 }
7174
7175 #define set_power_wells(power_domains, __power_wells) ({                \
7176         (power_domains)->power_wells = (__power_wells);                 \
7177         (power_domains)->power_well_count = ARRAY_SIZE(__power_wells);  \
7178 })
7179
7180 int intel_power_domains_init(struct drm_i915_private *dev_priv)
7181 {
7182         struct i915_power_domains *power_domains = &dev_priv->power_domains;
7183
7184         mutex_init(&power_domains->lock);
7185
7186         /*
7187          * The enabling order will be from lower to higher indexed wells,
7188          * the disabling order is reversed.
7189          */
7190         if (IS_HASWELL(dev_priv->dev)) {
7191                 set_power_wells(power_domains, hsw_power_wells);
7192                 hsw_pwr = power_domains;
7193         } else if (IS_BROADWELL(dev_priv->dev)) {
7194                 set_power_wells(power_domains, bdw_power_wells);
7195                 hsw_pwr = power_domains;
7196         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
7197                 set_power_wells(power_domains, chv_power_wells);
7198         } else if (IS_VALLEYVIEW(dev_priv->dev)) {
7199                 set_power_wells(power_domains, vlv_power_wells);
7200         } else {
7201                 set_power_wells(power_domains, i9xx_always_on_power_well);
7202         }
7203
7204         return 0;
7205 }
7206
7207 void intel_power_domains_remove(struct drm_i915_private *dev_priv)
7208 {
7209         hsw_pwr = NULL;
7210 }
7211
7212 static void intel_power_domains_resume(struct drm_i915_private *dev_priv)
7213 {
7214         struct i915_power_domains *power_domains = &dev_priv->power_domains;
7215         struct i915_power_well *power_well;
7216         int i;
7217
7218         mutex_lock(&power_domains->lock);
7219         for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
7220                 power_well->ops->sync_hw(dev_priv, power_well);
7221                 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
7222                                                                      power_well);
7223         }
7224         mutex_unlock(&power_domains->lock);
7225 }
7226
7227 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
7228 {
7229         struct i915_power_well *cmn =
7230                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
7231         struct i915_power_well *disp2d =
7232                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
7233
7234         /* nothing to do if common lane is already off */
7235         if (!cmn->ops->is_enabled(dev_priv, cmn))
7236                 return;
7237
7238         /* If the display might be already active skip this */
7239         if (disp2d->ops->is_enabled(dev_priv, disp2d) &&
7240             I915_READ(DPIO_CTL) & DPIO_CMNRST)
7241                 return;
7242
7243         DRM_DEBUG_KMS("toggling display PHY side reset\n");
7244
7245         /* cmnlane needs DPLL registers */
7246         disp2d->ops->enable(dev_priv, disp2d);
7247
7248         /*
7249          * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
7250          * Need to assert and de-assert PHY SB reset by gating the
7251          * common lane power, then un-gating it.
7252          * Simply ungating isn't enough to reset the PHY enough to get
7253          * ports and lanes running.
7254          */
7255         cmn->ops->disable(dev_priv, cmn);
7256 }
7257
7258 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv)
7259 {
7260         struct drm_device *dev = dev_priv->dev;
7261         struct i915_power_domains *power_domains = &dev_priv->power_domains;
7262
7263         power_domains->initializing = true;
7264
7265         if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
7266                 mutex_lock(&power_domains->lock);
7267                 vlv_cmnlane_wa(dev_priv);
7268                 mutex_unlock(&power_domains->lock);
7269         }
7270
7271         /* For now, we need the power well to be always enabled. */
7272         intel_display_set_init_power(dev_priv, true);
7273         intel_power_domains_resume(dev_priv);
7274         power_domains->initializing = false;
7275 }
7276
7277 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
7278 {
7279         intel_runtime_pm_get(dev_priv);
7280 }
7281
7282 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
7283 {
7284         intel_runtime_pm_put(dev_priv);
7285 }
7286
7287 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
7288 {
7289         struct drm_device *dev = dev_priv->dev;
7290         struct device *device = &dev->pdev->dev;
7291
7292         if (!HAS_RUNTIME_PM(dev))
7293                 return;
7294
7295         pm_runtime_get_sync(device);
7296         WARN(dev_priv->pm.suspended, "Device still suspended.\n");
7297 }
7298
7299 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
7300 {
7301         struct drm_device *dev = dev_priv->dev;
7302         struct device *device = &dev->pdev->dev;
7303
7304         if (!HAS_RUNTIME_PM(dev))
7305                 return;
7306
7307         WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n");
7308         pm_runtime_get_noresume(device);
7309 }
7310
7311 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
7312 {
7313         struct drm_device *dev = dev_priv->dev;
7314         struct device *device = &dev->pdev->dev;
7315
7316         if (!HAS_RUNTIME_PM(dev))
7317                 return;
7318
7319         pm_runtime_mark_last_busy(device);
7320         pm_runtime_put_autosuspend(device);
7321 }
7322
7323 void intel_init_runtime_pm(struct drm_i915_private *dev_priv)
7324 {
7325         struct drm_device *dev = dev_priv->dev;
7326         struct device *device = &dev->pdev->dev;
7327
7328         if (!HAS_RUNTIME_PM(dev))
7329                 return;
7330
7331         pm_runtime_set_active(device);
7332
7333         /*
7334          * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
7335          * requirement.
7336          */
7337         if (!intel_enable_rc6(dev)) {
7338                 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
7339                 return;
7340         }
7341
7342         pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
7343         pm_runtime_mark_last_busy(device);
7344         pm_runtime_use_autosuspend(device);
7345
7346         pm_runtime_put_autosuspend(device);
7347 }
7348
7349 void intel_fini_runtime_pm(struct drm_i915_private *dev_priv)
7350 {
7351         struct drm_device *dev = dev_priv->dev;
7352         struct device *device = &dev->pdev->dev;
7353
7354         if (!HAS_RUNTIME_PM(dev))
7355                 return;
7356
7357         if (!intel_enable_rc6(dev))
7358                 return;
7359
7360         /* Make sure we're not suspended first. */
7361         pm_runtime_get_sync(device);
7362         pm_runtime_disable(device);
7363 }
7364
7365 /* Set up chip specific power management-related functions */
7366 void intel_init_pm(struct drm_device *dev)
7367 {
7368         struct drm_i915_private *dev_priv = dev->dev_private;
7369
7370         if (HAS_FBC(dev)) {
7371                 if (INTEL_INFO(dev)->gen >= 7) {
7372                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7373                         dev_priv->display.enable_fbc = gen7_enable_fbc;
7374                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
7375                 } else if (INTEL_INFO(dev)->gen >= 5) {
7376                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7377                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
7378                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
7379                 } else if (IS_GM45(dev)) {
7380                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
7381                         dev_priv->display.enable_fbc = g4x_enable_fbc;
7382                         dev_priv->display.disable_fbc = g4x_disable_fbc;
7383                 } else {
7384                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
7385                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
7386                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
7387
7388                         /* This value was pulled out of someone's hat */
7389                         I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
7390                 }
7391         }
7392
7393         /* For cxsr */
7394         if (IS_PINEVIEW(dev))
7395                 i915_pineview_get_mem_freq(dev);
7396         else if (IS_GEN5(dev))
7397                 i915_ironlake_get_mem_freq(dev);
7398
7399         /* For FIFO watermark updates */
7400         if (HAS_PCH_SPLIT(dev)) {
7401                 ilk_setup_wm_latency(dev);
7402
7403                 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7404                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7405                     (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7406                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7407                         dev_priv->display.update_wm = ilk_update_wm;
7408                         dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
7409                 } else {
7410                         DRM_DEBUG_KMS("Failed to read display plane latency. "
7411                                       "Disable CxSR\n");
7412                 }
7413
7414                 if (IS_GEN5(dev))
7415                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7416                 else if (IS_GEN6(dev))
7417                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7418                 else if (IS_IVYBRIDGE(dev))
7419                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7420                 else if (IS_HASWELL(dev))
7421                         dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7422                 else if (INTEL_INFO(dev)->gen == 8)
7423                         dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7424                 else if (INTEL_INFO(dev)->gen == 9)
7425                         dev_priv->display.init_clock_gating = gen9_init_clock_gating;
7426         } else if (IS_CHERRYVIEW(dev)) {
7427                 dev_priv->display.update_wm = cherryview_update_wm;
7428                 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
7429                 dev_priv->display.init_clock_gating =
7430                         cherryview_init_clock_gating;
7431         } else if (IS_VALLEYVIEW(dev)) {
7432                 dev_priv->display.update_wm = valleyview_update_wm;
7433                 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
7434                 dev_priv->display.init_clock_gating =
7435                         valleyview_init_clock_gating;
7436         } else if (IS_PINEVIEW(dev)) {
7437                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7438                                             dev_priv->is_ddr3,
7439                                             dev_priv->fsb_freq,
7440                                             dev_priv->mem_freq)) {
7441                         DRM_INFO("failed to find known CxSR latency "
7442                                  "(found ddr%s fsb freq %d, mem freq %d), "
7443                                  "disabling CxSR\n",
7444                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
7445                                  dev_priv->fsb_freq, dev_priv->mem_freq);
7446                         /* Disable CxSR and never update its watermark again */
7447                         intel_set_memory_cxsr(dev_priv, false);
7448                         dev_priv->display.update_wm = NULL;
7449                 } else
7450                         dev_priv->display.update_wm = pineview_update_wm;
7451                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7452         } else if (IS_G4X(dev)) {
7453                 dev_priv->display.update_wm = g4x_update_wm;
7454                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7455         } else if (IS_GEN4(dev)) {
7456                 dev_priv->display.update_wm = i965_update_wm;
7457                 if (IS_CRESTLINE(dev))
7458                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7459                 else if (IS_BROADWATER(dev))
7460                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7461         } else if (IS_GEN3(dev)) {
7462                 dev_priv->display.update_wm = i9xx_update_wm;
7463                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7464                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7465         } else if (IS_GEN2(dev)) {
7466                 if (INTEL_INFO(dev)->num_pipes == 1) {
7467                         dev_priv->display.update_wm = i845_update_wm;
7468                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
7469                 } else {
7470                         dev_priv->display.update_wm = i9xx_update_wm;
7471                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
7472                 }
7473
7474                 if (IS_I85X(dev) || IS_I865G(dev))
7475                         dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7476                 else
7477                         dev_priv->display.init_clock_gating = i830_init_clock_gating;
7478         } else {
7479                 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7480         }
7481 }
7482
7483 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
7484 {
7485         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7486
7487         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7488                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7489                 return -EAGAIN;
7490         }
7491
7492         I915_WRITE(GEN6_PCODE_DATA, *val);
7493         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7494
7495         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7496                      500)) {
7497                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7498                 return -ETIMEDOUT;
7499         }
7500
7501         *val = I915_READ(GEN6_PCODE_DATA);
7502         I915_WRITE(GEN6_PCODE_DATA, 0);
7503
7504         return 0;
7505 }
7506
7507 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
7508 {
7509         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7510
7511         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7512                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7513                 return -EAGAIN;
7514         }
7515
7516         I915_WRITE(GEN6_PCODE_DATA, val);
7517         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7518
7519         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7520                      500)) {
7521                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7522                 return -ETIMEDOUT;
7523         }
7524
7525         I915_WRITE(GEN6_PCODE_DATA, 0);
7526
7527         return 0;
7528 }
7529
7530 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7531 {
7532         int div;
7533
7534         /* 4 x czclk */
7535         switch (dev_priv->mem_freq) {
7536         case 800:
7537                 div = 10;
7538                 break;
7539         case 1066:
7540                 div = 12;
7541                 break;
7542         case 1333:
7543                 div = 16;
7544                 break;
7545         default:
7546                 return -1;
7547         }
7548
7549         return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
7550 }
7551
7552 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7553 {
7554         int mul;
7555
7556         /* 4 x czclk */
7557         switch (dev_priv->mem_freq) {
7558         case 800:
7559                 mul = 10;
7560                 break;
7561         case 1066:
7562                 mul = 12;
7563                 break;
7564         case 1333:
7565                 mul = 16;
7566                 break;
7567         default:
7568                 return -1;
7569         }
7570
7571         return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
7572 }
7573
7574 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7575 {
7576         int div, freq;
7577
7578         switch (dev_priv->rps.cz_freq) {
7579         case 200:
7580                 div = 5;
7581                 break;
7582         case 267:
7583                 div = 6;
7584                 break;
7585         case 320:
7586         case 333:
7587         case 400:
7588                 div = 8;
7589                 break;
7590         default:
7591                 return -1;
7592         }
7593
7594         freq = (DIV_ROUND_CLOSEST((dev_priv->rps.cz_freq * val), 2 * div) / 2);
7595
7596         return freq;
7597 }
7598
7599 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7600 {
7601         int mul, opcode;
7602
7603         switch (dev_priv->rps.cz_freq) {
7604         case 200:
7605                 mul = 5;
7606                 break;
7607         case 267:
7608                 mul = 6;
7609                 break;
7610         case 320:
7611         case 333:
7612         case 400:
7613                 mul = 8;
7614                 break;
7615         default:
7616                 return -1;
7617         }
7618
7619         /* CHV needs even values */
7620         opcode = (DIV_ROUND_CLOSEST((val * 2 * mul), dev_priv->rps.cz_freq) * 2);
7621
7622         return opcode;
7623 }
7624
7625 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7626 {
7627         int ret = -1;
7628
7629         if (IS_CHERRYVIEW(dev_priv->dev))
7630                 ret = chv_gpu_freq(dev_priv, val);
7631         else if (IS_VALLEYVIEW(dev_priv->dev))
7632                 ret = byt_gpu_freq(dev_priv, val);
7633
7634         return ret;
7635 }
7636
7637 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7638 {
7639         int ret = -1;
7640
7641         if (IS_CHERRYVIEW(dev_priv->dev))
7642                 ret = chv_freq_opcode(dev_priv, val);
7643         else if (IS_VALLEYVIEW(dev_priv->dev))
7644                 ret = byt_freq_opcode(dev_priv, val);
7645
7646         return ret;
7647 }
7648
7649 void intel_pm_setup(struct drm_device *dev)
7650 {
7651         struct drm_i915_private *dev_priv = dev->dev_private;
7652
7653         mutex_init(&dev_priv->rps.hw_lock);
7654
7655         INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7656                           intel_gen6_powersave_work);
7657
7658         dev_priv->pm.suspended = false;
7659         dev_priv->pm._irqs_disabled = false;
7660 }