drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "../../../platform/x86/intel_ips.h"
  32 #include <linux/module.h>
  33
  34 #define FORCEWAKE_ACK_TIMEOUT_MS 2
  35
  36 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
  37  * framebuffer contents in-memory, aiming at reducing the required bandwidth
  38  * during in-memory transfers and, therefore, reduce the power packet.
  39  *
  40  * The benefits of FBC are mostly visible with solid backgrounds and
  41  * variation-less patterns.
  42  *
  43  * FBC-related functionality can be enabled by the means of the
  44  * i915.i915_enable_fbc parameter
  45  */
  46
  47 static void i8xx_disable_fbc(struct drm_device *dev)
  48 {
  49         struct drm_i915_private *dev_priv = dev->dev_private;
  50         u32 fbc_ctl;
  51
  52         /* Disable compression */
  53         fbc_ctl = I915_READ(FBC_CONTROL);
  54         if ((fbc_ctl & FBC_CTL_EN) == 0)
  55                 return;
  56
  57         fbc_ctl &= ~FBC_CTL_EN;
  58         I915_WRITE(FBC_CONTROL, fbc_ctl);
  59
  60         /* Wait for compressing bit to clear */
  61         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
  62                 DRM_DEBUG_KMS("FBC idle timed out\n");
  63                 return;
  64         }
  65
  66         DRM_DEBUG_KMS("disabled FBC\n");
  67 }
  68
  69 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  70 {
  71         struct drm_device *dev = crtc->dev;
  72         struct drm_i915_private *dev_priv = dev->dev_private;
  73         struct drm_framebuffer *fb = crtc->fb;
  74         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  75         struct drm_i915_gem_object *obj = intel_fb->obj;
  76         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  77         int cfb_pitch;
  78         int plane, i;
  79         u32 fbc_ctl, fbc_ctl2;
  80
  81         cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
  82         if (fb->pitches[0] < cfb_pitch)
  83                 cfb_pitch = fb->pitches[0];
  84
  85         /* FBC_CTL wants 64B units */
  86         cfb_pitch = (cfb_pitch / 64) - 1;
  87         plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
  88
  89         /* Clear old tags */
  90         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
  91                 I915_WRITE(FBC_TAG + (i * 4), 0);
  92
  93         /* Set it up... */
  94         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
  95         fbc_ctl2 |= plane;
  96         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
  97         I915_WRITE(FBC_FENCE_OFF, crtc->y);
  98
  99         /* enable it... */
 100         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
 101         if (IS_I945GM(dev))
 102                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 103         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 104         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
 105         fbc_ctl |= obj->fence_reg;
 106         I915_WRITE(FBC_CONTROL, fbc_ctl);
 107
 108         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
 109                       cfb_pitch, crtc->y, intel_crtc->plane);
 110 }
 111
 112 static bool i8xx_fbc_enabled(struct drm_device *dev)
 113 {
 114         struct drm_i915_private *dev_priv = dev->dev_private;
 115
 116         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
 117 }
 118
 119 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 120 {
 121         struct drm_device *dev = crtc->dev;
 122         struct drm_i915_private *dev_priv = dev->dev_private;
 123         struct drm_framebuffer *fb = crtc->fb;
 124         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 125         struct drm_i915_gem_object *obj = intel_fb->obj;
 126         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 127         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
 128         unsigned long stall_watermark = 200;
 129         u32 dpfc_ctl;
 130
 131         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
 132         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
 133         I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
 134
 135         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
 136                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
 137                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
 138         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
 139
 140         /* enable it... */
 141         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
 142
 143         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
 144 }
 145
 146 static void g4x_disable_fbc(struct drm_device *dev)
 147 {
 148         struct drm_i915_private *dev_priv = dev->dev_private;
 149         u32 dpfc_ctl;
 150
 151         /* Disable compression */
 152         dpfc_ctl = I915_READ(DPFC_CONTROL);
 153         if (dpfc_ctl & DPFC_CTL_EN) {
 154                 dpfc_ctl &= ~DPFC_CTL_EN;
 155                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
 156
 157                 DRM_DEBUG_KMS("disabled FBC\n");
 158         }
 159 }
 160
 161 static bool g4x_fbc_enabled(struct drm_device *dev)
 162 {
 163         struct drm_i915_private *dev_priv = dev->dev_private;
 164
 165         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
 166 }
 167
 168 static void sandybridge_blit_fbc_update(struct drm_device *dev)
 169 {
 170         struct drm_i915_private *dev_priv = dev->dev_private;
 171         u32 blt_ecoskpd;
 172
 173         /* Make sure blitter notifies FBC of writes */
 174         gen6_gt_force_wake_get(dev_priv);
 175         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
 176         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
 177                 GEN6_BLITTER_LOCK_SHIFT;
 178         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 179         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
 180         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 181         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
 182                          GEN6_BLITTER_LOCK_SHIFT);
 183         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 184         POSTING_READ(GEN6_BLITTER_ECOSKPD);
 185         gen6_gt_force_wake_put(dev_priv);
 186 }
 187
 188 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 189 {
 190         struct drm_device *dev = crtc->dev;
 191         struct drm_i915_private *dev_priv = dev->dev_private;
 192         struct drm_framebuffer *fb = crtc->fb;
 193         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 194         struct drm_i915_gem_object *obj = intel_fb->obj;
 195         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 196         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
 197         unsigned long stall_watermark = 200;
 198         u32 dpfc_ctl;
 199
 200         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 201         dpfc_ctl &= DPFC_RESERVED;
 202         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
 203         /* Set persistent mode for front-buffer rendering, ala X. */
 204         dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
 205         dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
 206         I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
 207
 208         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
 209                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
 210                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
 211         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
 212         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
 213         /* enable it... */
 214         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 215
 216         if (IS_GEN6(dev)) {
 217                 I915_WRITE(SNB_DPFC_CTL_SA,
 218                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 219                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
 220                 sandybridge_blit_fbc_update(dev);
 221         }
 222
 223         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
 224 }
 225
 226 static void ironlake_disable_fbc(struct drm_device *dev)
 227 {
 228         struct drm_i915_private *dev_priv = dev->dev_private;
 229         u32 dpfc_ctl;
 230
 231         /* Disable compression */
 232         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 233         if (dpfc_ctl & DPFC_CTL_EN) {
 234                 dpfc_ctl &= ~DPFC_CTL_EN;
 235                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
 236
 237                 DRM_DEBUG_KMS("disabled FBC\n");
 238         }
 239 }
 240
 241 static bool ironlake_fbc_enabled(struct drm_device *dev)
 242 {
 243         struct drm_i915_private *dev_priv = dev->dev_private;
 244
 245         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 246 }
 247
 248 bool intel_fbc_enabled(struct drm_device *dev)
 249 {
 250         struct drm_i915_private *dev_priv = dev->dev_private;
 251
 252         if (!dev_priv->display.fbc_enabled)
 253                 return false;
 254
 255         return dev_priv->display.fbc_enabled(dev);
 256 }
 257
 258 static void intel_fbc_work_fn(struct work_struct *__work)
 259 {
 260         struct intel_fbc_work *work =
 261                 container_of(to_delayed_work(__work),
 262                              struct intel_fbc_work, work);
 263         struct drm_device *dev = work->crtc->dev;
 264         struct drm_i915_private *dev_priv = dev->dev_private;
 265
 266         mutex_lock(&dev->struct_mutex);
 267         if (work == dev_priv->fbc_work) {
 268                 /* Double check that we haven't switched fb without cancelling
 269                  * the prior work.
 270                  */
 271                 if (work->crtc->fb == work->fb) {
 272                         dev_priv->display.enable_fbc(work->crtc,
 273                                                      work->interval);
 274
 275                         dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
 276                         dev_priv->cfb_fb = work->crtc->fb->base.id;
 277                         dev_priv->cfb_y = work->crtc->y;
 278                 }
 279
 280                 dev_priv->fbc_work = NULL;
 281         }
 282         mutex_unlock(&dev->struct_mutex);
 283
 284         kfree(work);
 285 }
 286
 287 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
 288 {
 289         if (dev_priv->fbc_work == NULL)
 290                 return;
 291
 292         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
 293
 294         /* Synchronisation is provided by struct_mutex and checking of
 295          * dev_priv->fbc_work, so we can perform the cancellation
 296          * entirely asynchronously.
 297          */
 298         if (cancel_delayed_work(&dev_priv->fbc_work->work))
 299                 /* tasklet was killed before being run, clean up */
 300                 kfree(dev_priv->fbc_work);
 301
 302         /* Mark the work as no longer wanted so that if it does
 303          * wake-up (because the work was already running and waiting
 304          * for our mutex), it will discover that is no longer
 305          * necessary to run.
 306          */
 307         dev_priv->fbc_work = NULL;
 308 }
 309
 310 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 311 {
 312         struct intel_fbc_work *work;
 313         struct drm_device *dev = crtc->dev;
 314         struct drm_i915_private *dev_priv = dev->dev_private;
 315
 316         if (!dev_priv->display.enable_fbc)
 317                 return;
 318
 319         intel_cancel_fbc_work(dev_priv);
 320
 321         work = kzalloc(sizeof *work, GFP_KERNEL);
 322         if (work == NULL) {
 323                 dev_priv->display.enable_fbc(crtc, interval);
 324                 return;
 325         }
 326
 327         work->crtc = crtc;
 328         work->fb = crtc->fb;
 329         work->interval = interval;
 330         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
 331
 332         dev_priv->fbc_work = work;
 333
 334         DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
 335
 336         /* Delay the actual enabling to let pageflipping cease and the
 337          * display to settle before starting the compression. Note that
 338          * this delay also serves a second purpose: it allows for a
 339          * vblank to pass after disabling the FBC before we attempt
 340          * to modify the control registers.
 341          *
 342          * A more complicated solution would involve tracking vblanks
 343          * following the termination of the page-flipping sequence
 344          * and indeed performing the enable as a co-routine and not
 345          * waiting synchronously upon the vblank.
 346          */
 347         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
 348 }
 349
 350 void intel_disable_fbc(struct drm_device *dev)
 351 {
 352         struct drm_i915_private *dev_priv = dev->dev_private;
 353
 354         intel_cancel_fbc_work(dev_priv);
 355
 356         if (!dev_priv->display.disable_fbc)
 357                 return;
 358
 359         dev_priv->display.disable_fbc(dev);
 360         dev_priv->cfb_plane = -1;
 361 }
 362
 363 /**
 364  * intel_update_fbc - enable/disable FBC as needed
 365  * @dev: the drm_device
 366  *
 367  * Set up the framebuffer compression hardware at mode set time.  We
 368  * enable it if possible:
 369  *   - plane A only (on pre-965)
 370  *   - no pixel mulitply/line duplication
 371  *   - no alpha buffer discard
 372  *   - no dual wide
 373  *   - framebuffer <= 2048 in width, 1536 in height
 374  *
 375  * We can't assume that any compression will take place (worst case),
 376  * so the compressed buffer has to be the same size as the uncompressed
 377  * one.  It also must reside (along with the line length buffer) in
 378  * stolen memory.
 379  *
 380  * We need to enable/disable FBC on a global basis.
 381  */
 382 void intel_update_fbc(struct drm_device *dev)
 383 {
 384         struct drm_i915_private *dev_priv = dev->dev_private;
 385         struct drm_crtc *crtc = NULL, *tmp_crtc;
 386         struct intel_crtc *intel_crtc;
 387         struct drm_framebuffer *fb;
 388         struct intel_framebuffer *intel_fb;
 389         struct drm_i915_gem_object *obj;
 390         int enable_fbc;
 391
 392         if (!i915_powersave)
 393                 return;
 394
 395         if (!I915_HAS_FBC(dev))
 396                 return;
 397
 398         /*
 399          * If FBC is already on, we just have to verify that we can
 400          * keep it that way...
 401          * Need to disable if:
 402          *   - more than one pipe is active
 403          *   - changing FBC params (stride, fence, mode)
 404          *   - new fb is too large to fit in compressed buffer
 405          *   - going to an unsupported config (interlace, pixel multiply, etc.)
 406          */
 407         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
 408                 if (tmp_crtc->enabled &&
 409                     !to_intel_crtc(tmp_crtc)->primary_disabled &&
 410                     tmp_crtc->fb) {
 411                         if (crtc) {
 412                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
 413                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
 414                                 goto out_disable;
 415                         }
 416                         crtc = tmp_crtc;
 417                 }
 418         }
 419
 420         if (!crtc || crtc->fb == NULL) {
 421                 DRM_DEBUG_KMS("no output, disabling\n");
 422                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
 423                 goto out_disable;
 424         }
 425
 426         intel_crtc = to_intel_crtc(crtc);
 427         fb = crtc->fb;
 428         intel_fb = to_intel_framebuffer(fb);
 429         obj = intel_fb->obj;
 430
 431         enable_fbc = i915_enable_fbc;
 432         if (enable_fbc < 0) {
 433                 DRM_DEBUG_KMS("fbc set to per-chip default\n");
 434                 enable_fbc = 1;
 435                 if (INTEL_INFO(dev)->gen <= 6)
 436                         enable_fbc = 0;
 437         }
 438         if (!enable_fbc) {
 439                 DRM_DEBUG_KMS("fbc disabled per module param\n");
 440                 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
 441                 goto out_disable;
 442         }
 443         if (intel_fb->obj->base.size > dev_priv->cfb_size) {
 444                 DRM_DEBUG_KMS("framebuffer too large, disabling "
 445                               "compression\n");
 446                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
 447                 goto out_disable;
 448         }
 449         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
 450             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
 451                 DRM_DEBUG_KMS("mode incompatible with compression, "
 452                               "disabling\n");
 453                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
 454                 goto out_disable;
 455         }
 456         if ((crtc->mode.hdisplay > 2048) ||
 457             (crtc->mode.vdisplay > 1536)) {
 458                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
 459                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
 460                 goto out_disable;
 461         }
 462         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
 463                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
 464                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
 465                 goto out_disable;
 466         }
 467
 468         /* The use of a CPU fence is mandatory in order to detect writes
 469          * by the CPU to the scanout and trigger updates to the FBC.
 470          */
 471         if (obj->tiling_mode != I915_TILING_X ||
 472             obj->fence_reg == I915_FENCE_REG_NONE) {
 473                 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
 474                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
 475                 goto out_disable;
 476         }
 477
 478         /* If the kernel debugger is active, always disable compression */
 479         if (in_dbg_master())
 480                 goto out_disable;
 481
 482         /* If the scanout has not changed, don't modify the FBC settings.
 483          * Note that we make the fundamental assumption that the fb->obj
 484          * cannot be unpinned (and have its GTT offset and fence revoked)
 485          * without first being decoupled from the scanout and FBC disabled.
 486          */
 487         if (dev_priv->cfb_plane == intel_crtc->plane &&
 488             dev_priv->cfb_fb == fb->base.id &&
 489             dev_priv->cfb_y == crtc->y)
 490                 return;
 491
 492         if (intel_fbc_enabled(dev)) {
 493                 /* We update FBC along two paths, after changing fb/crtc
 494                  * configuration (modeswitching) and after page-flipping
 495                  * finishes. For the latter, we know that not only did
 496                  * we disable the FBC at the start of the page-flip
 497                  * sequence, but also more than one vblank has passed.
 498                  *
 499                  * For the former case of modeswitching, it is possible
 500                  * to switch between two FBC valid configurations
 501                  * instantaneously so we do need to disable the FBC
 502                  * before we can modify its control registers. We also
 503                  * have to wait for the next vblank for that to take
 504                  * effect. However, since we delay enabling FBC we can
 505                  * assume that a vblank has passed since disabling and
 506                  * that we can safely alter the registers in the deferred
 507                  * callback.
 508                  *
 509                  * In the scenario that we go from a valid to invalid
 510                  * and then back to valid FBC configuration we have
 511                  * no strict enforcement that a vblank occurred since
 512                  * disabling the FBC. However, along all current pipe
 513                  * disabling paths we do need to wait for a vblank at
 514                  * some point. And we wait before enabling FBC anyway.
 515                  */
 516                 DRM_DEBUG_KMS("disabling active FBC for update\n");
 517                 intel_disable_fbc(dev);
 518         }
 519
 520         intel_enable_fbc(crtc, 500);
 521         return;
 522
 523 out_disable:
 524         /* Multiple disables should be harmless */
 525         if (intel_fbc_enabled(dev)) {
 526                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
 527                 intel_disable_fbc(dev);
 528         }
 529 }
 530
 531 static void i915_pineview_get_mem_freq(struct drm_device *dev)
 532 {
 533         drm_i915_private_t *dev_priv = dev->dev_private;
 534         u32 tmp;
 535
 536         tmp = I915_READ(CLKCFG);
 537
 538         switch (tmp & CLKCFG_FSB_MASK) {
 539         case CLKCFG_FSB_533:
 540                 dev_priv->fsb_freq = 533; /* 133*4 */
 541                 break;
 542         case CLKCFG_FSB_800:
 543                 dev_priv->fsb_freq = 800; /* 200*4 */
 544                 break;
 545         case CLKCFG_FSB_667:
 546                 dev_priv->fsb_freq =  667; /* 167*4 */
 547                 break;
 548         case CLKCFG_FSB_400:
 549                 dev_priv->fsb_freq = 400; /* 100*4 */
 550                 break;
 551         }
 552
 553         switch (tmp & CLKCFG_MEM_MASK) {
 554         case CLKCFG_MEM_533:
 555                 dev_priv->mem_freq = 533;
 556                 break;
 557         case CLKCFG_MEM_667:
 558                 dev_priv->mem_freq = 667;
 559                 break;
 560         case CLKCFG_MEM_800:
 561                 dev_priv->mem_freq = 800;
 562                 break;
 563         }
 564
 565         /* detect pineview DDR3 setting */
 566         tmp = I915_READ(CSHRDDR3CTL);
 567         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 568 }
 569
 570 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 571 {
 572         drm_i915_private_t *dev_priv = dev->dev_private;
 573         u16 ddrpll, csipll;
 574
 575         ddrpll = I915_READ16(DDRMPLL1);
 576         csipll = I915_READ16(CSIPLL0);
 577
 578         switch (ddrpll & 0xff) {
 579         case 0xc:
 580                 dev_priv->mem_freq = 800;
 581                 break;
 582         case 0x10:
 583                 dev_priv->mem_freq = 1066;
 584                 break;
 585         case 0x14:
 586                 dev_priv->mem_freq = 1333;
 587                 break;
 588         case 0x18:
 589                 dev_priv->mem_freq = 1600;
 590                 break;
 591         default:
 592                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 593                                  ddrpll & 0xff);
 594                 dev_priv->mem_freq = 0;
 595                 break;
 596         }
 597
 598         dev_priv->ips.r_t = dev_priv->mem_freq;
 599
 600         switch (csipll & 0x3ff) {
 601         case 0x00c:
 602                 dev_priv->fsb_freq = 3200;
 603                 break;
 604         case 0x00e:
 605                 dev_priv->fsb_freq = 3733;
 606                 break;
 607         case 0x010:
 608                 dev_priv->fsb_freq = 4266;
 609                 break;
 610         case 0x012:
 611                 dev_priv->fsb_freq = 4800;
 612                 break;
 613         case 0x014:
 614                 dev_priv->fsb_freq = 5333;
 615                 break;
 616         case 0x016:
 617                 dev_priv->fsb_freq = 5866;
 618                 break;
 619         case 0x018:
 620                 dev_priv->fsb_freq = 6400;
 621                 break;
 622         default:
 623                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 624                                  csipll & 0x3ff);
 625                 dev_priv->fsb_freq = 0;
 626                 break;
 627         }
 628
 629         if (dev_priv->fsb_freq == 3200) {
 630                 dev_priv->ips.c_m = 0;
 631         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 632                 dev_priv->ips.c_m = 1;
 633         } else {
 634                 dev_priv->ips.c_m = 2;
 635         }
 636 }
 637
 638 static const struct cxsr_latency cxsr_latency_table[] = {
 639         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 640         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 641         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 642         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 643         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 644
 645         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 646         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 647         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 648         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 649         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 650
 651         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 652         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 653         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 654         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 655         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 656
 657         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 658         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 659         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 660         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 661         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 662
 663         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 664         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 665         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 666         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 667         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 668
 669         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 670         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 671         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 672         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 673         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 674 };
 675
 676 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 677                                                          int is_ddr3,
 678                                                          int fsb,
 679                                                          int mem)
 680 {
 681         const struct cxsr_latency *latency;
 682         int i;
 683
 684         if (fsb == 0 || mem == 0)
 685                 return NULL;
 686
 687         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 688                 latency = &cxsr_latency_table[i];
 689                 if (is_desktop == latency->is_desktop &&
 690                     is_ddr3 == latency->is_ddr3 &&
 691                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 692                         return latency;
 693         }
 694
 695         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 696
 697         return NULL;
 698 }
 699
 700 static void pineview_disable_cxsr(struct drm_device *dev)
 701 {
 702         struct drm_i915_private *dev_priv = dev->dev_private;
 703
 704         /* deactivate cxsr */
 705         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
 706 }
 707
 708 /*
 709  * Latency for FIFO fetches is dependent on several factors:
 710  *   - memory configuration (speed, channels)
 711  *   - chipset
 712  *   - current MCH state
 713  * It can be fairly high in some situations, so here we assume a fairly
 714  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 715  * set this value too high, the FIFO will fetch frequently to stay full)
 716  * and power consumption (set it too low to save power and we might see
 717  * FIFO underruns and display "flicker").
 718  *
 719  * A value of 5us seems to be a good balance; safe for very low end
 720  * platforms but not overly aggressive on lower latency configs.
 721  */
 722 static const int latency_ns = 5000;
 723
 724 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 725 {
 726         struct drm_i915_private *dev_priv = dev->dev_private;
 727         uint32_t dsparb = I915_READ(DSPARB);
 728         int size;
 729
 730         size = dsparb & 0x7f;
 731         if (plane)
 732                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 733
 734         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 735                       plane ? "B" : "A", size);
 736
 737         return size;
 738 }
 739
 740 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
 741 {
 742         struct drm_i915_private *dev_priv = dev->dev_private;
 743         uint32_t dsparb = I915_READ(DSPARB);
 744         int size;
 745
 746         size = dsparb & 0x1ff;
 747         if (plane)
 748                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 749         size >>= 1; /* Convert to cachelines */
 750
 751         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 752                       plane ? "B" : "A", size);
 753
 754         return size;
 755 }
 756
 757 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 758 {
 759         struct drm_i915_private *dev_priv = dev->dev_private;
 760         uint32_t dsparb = I915_READ(DSPARB);
 761         int size;
 762
 763         size = dsparb & 0x7f;
 764         size >>= 2; /* Convert to cachelines */
 765
 766         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 767                       plane ? "B" : "A",
 768                       size);
 769
 770         return size;
 771 }
 772
 773 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 774 {
 775         struct drm_i915_private *dev_priv = dev->dev_private;
 776         uint32_t dsparb = I915_READ(DSPARB);
 777         int size;
 778
 779         size = dsparb & 0x7f;
 780         size >>= 1; /* Convert to cachelines */
 781
 782         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 783                       plane ? "B" : "A", size);
 784
 785         return size;
 786 }
 787
 788 /* Pineview has different values for various configs */
 789 static const struct intel_watermark_params pineview_display_wm = {
 790         PINEVIEW_DISPLAY_FIFO,
 791         PINEVIEW_MAX_WM,
 792         PINEVIEW_DFT_WM,
 793         PINEVIEW_GUARD_WM,
 794         PINEVIEW_FIFO_LINE_SIZE
 795 };
 796 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 797         PINEVIEW_DISPLAY_FIFO,
 798         PINEVIEW_MAX_WM,
 799         PINEVIEW_DFT_HPLLOFF_WM,
 800         PINEVIEW_GUARD_WM,
 801         PINEVIEW_FIFO_LINE_SIZE
 802 };
 803 static const struct intel_watermark_params pineview_cursor_wm = {
 804         PINEVIEW_CURSOR_FIFO,
 805         PINEVIEW_CURSOR_MAX_WM,
 806         PINEVIEW_CURSOR_DFT_WM,
 807         PINEVIEW_CURSOR_GUARD_WM,
 808         PINEVIEW_FIFO_LINE_SIZE,
 809 };
 810 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 811         PINEVIEW_CURSOR_FIFO,
 812         PINEVIEW_CURSOR_MAX_WM,
 813         PINEVIEW_CURSOR_DFT_WM,
 814         PINEVIEW_CURSOR_GUARD_WM,
 815         PINEVIEW_FIFO_LINE_SIZE
 816 };
 817 static const struct intel_watermark_params g4x_wm_info = {
 818         G4X_FIFO_SIZE,
 819         G4X_MAX_WM,
 820         G4X_MAX_WM,
 821         2,
 822         G4X_FIFO_LINE_SIZE,
 823 };
 824 static const struct intel_watermark_params g4x_cursor_wm_info = {
 825         I965_CURSOR_FIFO,
 826         I965_CURSOR_MAX_WM,
 827         I965_CURSOR_DFT_WM,
 828         2,
 829         G4X_FIFO_LINE_SIZE,
 830 };
 831 static const struct intel_watermark_params valleyview_wm_info = {
 832         VALLEYVIEW_FIFO_SIZE,
 833         VALLEYVIEW_MAX_WM,
 834         VALLEYVIEW_MAX_WM,
 835         2,
 836         G4X_FIFO_LINE_SIZE,
 837 };
 838 static const struct intel_watermark_params valleyview_cursor_wm_info = {
 839         I965_CURSOR_FIFO,
 840         VALLEYVIEW_CURSOR_MAX_WM,
 841         I965_CURSOR_DFT_WM,
 842         2,
 843         G4X_FIFO_LINE_SIZE,
 844 };
 845 static const struct intel_watermark_params i965_cursor_wm_info = {
 846         I965_CURSOR_FIFO,
 847         I965_CURSOR_MAX_WM,
 848         I965_CURSOR_DFT_WM,
 849         2,
 850         I915_FIFO_LINE_SIZE,
 851 };
 852 static const struct intel_watermark_params i945_wm_info = {
 853         I945_FIFO_SIZE,
 854         I915_MAX_WM,
 855         1,
 856         2,
 857         I915_FIFO_LINE_SIZE
 858 };
 859 static const struct intel_watermark_params i915_wm_info = {
 860         I915_FIFO_SIZE,
 861         I915_MAX_WM,
 862         1,
 863         2,
 864         I915_FIFO_LINE_SIZE
 865 };
 866 static const struct intel_watermark_params i855_wm_info = {
 867         I855GM_FIFO_SIZE,
 868         I915_MAX_WM,
 869         1,
 870         2,
 871         I830_FIFO_LINE_SIZE
 872 };
 873 static const struct intel_watermark_params i830_wm_info = {
 874         I830_FIFO_SIZE,
 875         I915_MAX_WM,
 876         1,
 877         2,
 878         I830_FIFO_LINE_SIZE
 879 };
 880
 881 static const struct intel_watermark_params ironlake_display_wm_info = {
 882         ILK_DISPLAY_FIFO,
 883         ILK_DISPLAY_MAXWM,
 884         ILK_DISPLAY_DFTWM,
 885         2,
 886         ILK_FIFO_LINE_SIZE
 887 };
 888 static const struct intel_watermark_params ironlake_cursor_wm_info = {
 889         ILK_CURSOR_FIFO,
 890         ILK_CURSOR_MAXWM,
 891         ILK_CURSOR_DFTWM,
 892         2,
 893         ILK_FIFO_LINE_SIZE
 894 };
 895 static const struct intel_watermark_params ironlake_display_srwm_info = {
 896         ILK_DISPLAY_SR_FIFO,
 897         ILK_DISPLAY_MAX_SRWM,
 898         ILK_DISPLAY_DFT_SRWM,
 899         2,
 900         ILK_FIFO_LINE_SIZE
 901 };
 902 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
 903         ILK_CURSOR_SR_FIFO,
 904         ILK_CURSOR_MAX_SRWM,
 905         ILK_CURSOR_DFT_SRWM,
 906         2,
 907         ILK_FIFO_LINE_SIZE
 908 };
 909
 910 static const struct intel_watermark_params sandybridge_display_wm_info = {
 911         SNB_DISPLAY_FIFO,
 912         SNB_DISPLAY_MAXWM,
 913         SNB_DISPLAY_DFTWM,
 914         2,
 915         SNB_FIFO_LINE_SIZE
 916 };
 917 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
 918         SNB_CURSOR_FIFO,
 919         SNB_CURSOR_MAXWM,
 920         SNB_CURSOR_DFTWM,
 921         2,
 922         SNB_FIFO_LINE_SIZE
 923 };
 924 static const struct intel_watermark_params sandybridge_display_srwm_info = {
 925         SNB_DISPLAY_SR_FIFO,
 926         SNB_DISPLAY_MAX_SRWM,
 927         SNB_DISPLAY_DFT_SRWM,
 928         2,
 929         SNB_FIFO_LINE_SIZE
 930 };
 931 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
 932         SNB_CURSOR_SR_FIFO,
 933         SNB_CURSOR_MAX_SRWM,
 934         SNB_CURSOR_DFT_SRWM,
 935         2,
 936         SNB_FIFO_LINE_SIZE
 937 };
 938
 939
 940 /**
 941  * intel_calculate_wm - calculate watermark level
 942  * @clock_in_khz: pixel clock
 943  * @wm: chip FIFO params
 944  * @pixel_size: display pixel size
 945  * @latency_ns: memory latency for the platform
 946  *
 947  * Calculate the watermark level (the level at which the display plane will
 948  * start fetching from memory again).  Each chip has a different display
 949  * FIFO size and allocation, so the caller needs to figure that out and pass
 950  * in the correct intel_watermark_params structure.
 951  *
 952  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 953  * on the pixel size.  When it reaches the watermark level, it'll start
 954  * fetching FIFO line sized based chunks from memory until the FIFO fills
 955  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 956  * will occur, and a display engine hang could result.
 957  */
 958 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 959                                         const struct intel_watermark_params *wm,
 960                                         int fifo_size,
 961                                         int pixel_size,
 962                                         unsigned long latency_ns)
 963 {
 964         long entries_required, wm_size;
 965
 966         /*
 967          * Note: we need to make sure we don't overflow for various clock &
 968          * latency values.
 969          * clocks go from a few thousand to several hundred thousand.
 970          * latency is usually a few thousand
 971          */
 972         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
 973                 1000;
 974         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 975
 976         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 977
 978         wm_size = fifo_size - (entries_required + wm->guard_size);
 979
 980         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
 981
 982         /* Don't promote wm_size to unsigned... */
 983         if (wm_size > (long)wm->max_wm)
 984                 wm_size = wm->max_wm;
 985         if (wm_size <= 0)
 986                 wm_size = wm->default_wm;
 987         return wm_size;
 988 }
 989
 990 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
 991 {
 992         struct drm_crtc *crtc, *enabled = NULL;
 993
 994         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 995                 if (crtc->enabled && crtc->fb) {
 996                         if (enabled)
 997                                 return NULL;
 998                         enabled = crtc;
 999                 }
1000         }
1001
1002         return enabled;
1003 }
1004
1005 static void pineview_update_wm(struct drm_device *dev)
1006 {
1007         struct drm_i915_private *dev_priv = dev->dev_private;
1008         struct drm_crtc *crtc;
1009         const struct cxsr_latency *latency;
1010         u32 reg;
1011         unsigned long wm;
1012
1013         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1014                                          dev_priv->fsb_freq, dev_priv->mem_freq);
1015         if (!latency) {
1016                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1017                 pineview_disable_cxsr(dev);
1018                 return;
1019         }
1020
1021         crtc = single_enabled_crtc(dev);
1022         if (crtc) {
1023                 int clock = crtc->mode.clock;
1024                 int pixel_size = crtc->fb->bits_per_pixel / 8;
1025
1026                 /* Display SR */
1027                 wm = intel_calculate_wm(clock, &pineview_display_wm,
1028                                         pineview_display_wm.fifo_size,
1029                                         pixel_size, latency->display_sr);
1030                 reg = I915_READ(DSPFW1);
1031                 reg &= ~DSPFW_SR_MASK;
1032                 reg |= wm << DSPFW_SR_SHIFT;
1033                 I915_WRITE(DSPFW1, reg);
1034                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1035
1036                 /* cursor SR */
1037                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1038                                         pineview_display_wm.fifo_size,
1039                                         pixel_size, latency->cursor_sr);
1040                 reg = I915_READ(DSPFW3);
1041                 reg &= ~DSPFW_CURSOR_SR_MASK;
1042                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1043                 I915_WRITE(DSPFW3, reg);
1044
1045                 /* Display HPLL off SR */
1046                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1047                                         pineview_display_hplloff_wm.fifo_size,
1048                                         pixel_size, latency->display_hpll_disable);
1049                 reg = I915_READ(DSPFW3);
1050                 reg &= ~DSPFW_HPLL_SR_MASK;
1051                 reg |= wm & DSPFW_HPLL_SR_MASK;
1052                 I915_WRITE(DSPFW3, reg);
1053
1054                 /* cursor HPLL off SR */
1055                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1056                                         pineview_display_hplloff_wm.fifo_size,
1057                                         pixel_size, latency->cursor_hpll_disable);
1058                 reg = I915_READ(DSPFW3);
1059                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1060                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1061                 I915_WRITE(DSPFW3, reg);
1062                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1063
1064                 /* activate cxsr */
1065                 I915_WRITE(DSPFW3,
1066                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1067                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1068         } else {
1069                 pineview_disable_cxsr(dev);
1070                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1071         }
1072 }
1073
1074 static bool g4x_compute_wm0(struct drm_device *dev,
1075                             int plane,
1076                             const struct intel_watermark_params *display,
1077                             int display_latency_ns,
1078                             const struct intel_watermark_params *cursor,
1079                             int cursor_latency_ns,
1080                             int *plane_wm,
1081                             int *cursor_wm)
1082 {
1083         struct drm_crtc *crtc;
1084         int htotal, hdisplay, clock, pixel_size;
1085         int line_time_us, line_count;
1086         int entries, tlb_miss;
1087
1088         crtc = intel_get_crtc_for_plane(dev, plane);
1089         if (crtc->fb == NULL || !crtc->enabled) {
1090                 *cursor_wm = cursor->guard_size;
1091                 *plane_wm = display->guard_size;
1092                 return false;
1093         }
1094
1095         htotal = crtc->mode.htotal;
1096         hdisplay = crtc->mode.hdisplay;
1097         clock = crtc->mode.clock;
1098         pixel_size = crtc->fb->bits_per_pixel / 8;
1099
1100         /* Use the small buffer method to calculate plane watermark */
1101         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1102         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1103         if (tlb_miss > 0)
1104                 entries += tlb_miss;
1105         entries = DIV_ROUND_UP(entries, display->cacheline_size);
1106         *plane_wm = entries + display->guard_size;
1107         if (*plane_wm > (int)display->max_wm)
1108                 *plane_wm = display->max_wm;
1109
1110         /* Use the large buffer method to calculate cursor watermark */
1111         line_time_us = ((htotal * 1000) / clock);
1112         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1113         entries = line_count * 64 * pixel_size;
1114         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1115         if (tlb_miss > 0)
1116                 entries += tlb_miss;
1117         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1118         *cursor_wm = entries + cursor->guard_size;
1119         if (*cursor_wm > (int)cursor->max_wm)
1120                 *cursor_wm = (int)cursor->max_wm;
1121
1122         return true;
1123 }
1124
1125 /*
1126  * Check the wm result.
1127  *
1128  * If any calculated watermark values is larger than the maximum value that
1129  * can be programmed into the associated watermark register, that watermark
1130  * must be disabled.
1131  */
1132 static bool g4x_check_srwm(struct drm_device *dev,
1133                            int display_wm, int cursor_wm,
1134                            const struct intel_watermark_params *display,
1135                            const struct intel_watermark_params *cursor)
1136 {
1137         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1138                       display_wm, cursor_wm);
1139
1140         if (display_wm > display->max_wm) {
1141                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1142                               display_wm, display->max_wm);
1143                 return false;
1144         }
1145
1146         if (cursor_wm > cursor->max_wm) {
1147                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1148                               cursor_wm, cursor->max_wm);
1149                 return false;
1150         }
1151
1152         if (!(display_wm || cursor_wm)) {
1153                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1154                 return false;
1155         }
1156
1157         return true;
1158 }
1159
1160 static bool g4x_compute_srwm(struct drm_device *dev,
1161                              int plane,
1162                              int latency_ns,
1163                              const struct intel_watermark_params *display,
1164                              const struct intel_watermark_params *cursor,
1165                              int *display_wm, int *cursor_wm)
1166 {
1167         struct drm_crtc *crtc;
1168         int hdisplay, htotal, pixel_size, clock;
1169         unsigned long line_time_us;
1170         int line_count, line_size;
1171         int small, large;
1172         int entries;
1173
1174         if (!latency_ns) {
1175                 *display_wm = *cursor_wm = 0;
1176                 return false;
1177         }
1178
1179         crtc = intel_get_crtc_for_plane(dev, plane);
1180         hdisplay = crtc->mode.hdisplay;
1181         htotal = crtc->mode.htotal;
1182         clock = crtc->mode.clock;
1183         pixel_size = crtc->fb->bits_per_pixel / 8;
1184
1185         line_time_us = (htotal * 1000) / clock;
1186         line_count = (latency_ns / line_time_us + 1000) / 1000;
1187         line_size = hdisplay * pixel_size;
1188
1189         /* Use the minimum of the small and large buffer method for primary */
1190         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1191         large = line_count * line_size;
1192
1193         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1194         *display_wm = entries + display->guard_size;
1195
1196         /* calculate the self-refresh watermark for display cursor */
1197         entries = line_count * pixel_size * 64;
1198         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1199         *cursor_wm = entries + cursor->guard_size;
1200
1201         return g4x_check_srwm(dev,
1202                               *display_wm, *cursor_wm,
1203                               display, cursor);
1204 }
1205
1206 static bool vlv_compute_drain_latency(struct drm_device *dev,
1207                                      int plane,
1208                                      int *plane_prec_mult,
1209                                      int *plane_dl,
1210                                      int *cursor_prec_mult,
1211                                      int *cursor_dl)
1212 {
1213         struct drm_crtc *crtc;
1214         int clock, pixel_size;
1215         int entries;
1216
1217         crtc = intel_get_crtc_for_plane(dev, plane);
1218         if (crtc->fb == NULL || !crtc->enabled)
1219                 return false;
1220
1221         clock = crtc->mode.clock;       /* VESA DOT Clock */
1222         pixel_size = crtc->fb->bits_per_pixel / 8;      /* BPP */
1223
1224         entries = (clock / 1000) * pixel_size;
1225         *plane_prec_mult = (entries > 256) ?
1226                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1227         *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1228                                                      pixel_size);
1229
1230         entries = (clock / 1000) * 4;   /* BPP is always 4 for cursor */
1231         *cursor_prec_mult = (entries > 256) ?
1232                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1233         *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1234
1235         return true;
1236 }
1237
1238 /*
1239  * Update drain latency registers of memory arbiter
1240  *
1241  * Valleyview SoC has a new memory arbiter and needs drain latency registers
1242  * to be programmed. Each plane has a drain latency multiplier and a drain
1243  * latency value.
1244  */
1245
1246 static void vlv_update_drain_latency(struct drm_device *dev)
1247 {
1248         struct drm_i915_private *dev_priv = dev->dev_private;
1249         int planea_prec, planea_dl, planeb_prec, planeb_dl;
1250         int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1251         int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1252                                                         either 16 or 32 */
1253
1254         /* For plane A, Cursor A */
1255         if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1256                                       &cursor_prec_mult, &cursora_dl)) {
1257                 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1258                         DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1259                 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1260                         DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1261
1262                 I915_WRITE(VLV_DDL1, cursora_prec |
1263                                 (cursora_dl << DDL_CURSORA_SHIFT) |
1264                                 planea_prec | planea_dl);
1265         }
1266
1267         /* For plane B, Cursor B */
1268         if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1269                                       &cursor_prec_mult, &cursorb_dl)) {
1270                 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1271                         DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1272                 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1273                         DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1274
1275                 I915_WRITE(VLV_DDL2, cursorb_prec |
1276                                 (cursorb_dl << DDL_CURSORB_SHIFT) |
1277                                 planeb_prec | planeb_dl);
1278         }
1279 }
1280
1281 #define single_plane_enabled(mask) is_power_of_2(mask)
1282
1283 static void valleyview_update_wm(struct drm_device *dev)
1284 {
1285         static const int sr_latency_ns = 12000;
1286         struct drm_i915_private *dev_priv = dev->dev_private;
1287         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1288         int plane_sr, cursor_sr;
1289         unsigned int enabled = 0;
1290
1291         vlv_update_drain_latency(dev);
1292
1293         if (g4x_compute_wm0(dev, 0,
1294                             &valleyview_wm_info, latency_ns,
1295                             &valleyview_cursor_wm_info, latency_ns,
1296                             &planea_wm, &cursora_wm))
1297                 enabled |= 1;
1298
1299         if (g4x_compute_wm0(dev, 1,
1300                             &valleyview_wm_info, latency_ns,
1301                             &valleyview_cursor_wm_info, latency_ns,
1302                             &planeb_wm, &cursorb_wm))
1303                 enabled |= 2;
1304
1305         plane_sr = cursor_sr = 0;
1306         if (single_plane_enabled(enabled) &&
1307             g4x_compute_srwm(dev, ffs(enabled) - 1,
1308                              sr_latency_ns,
1309                              &valleyview_wm_info,
1310                              &valleyview_cursor_wm_info,
1311                              &plane_sr, &cursor_sr))
1312                 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1313         else
1314                 I915_WRITE(FW_BLC_SELF_VLV,
1315                            I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1316
1317         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1318                       planea_wm, cursora_wm,
1319                       planeb_wm, cursorb_wm,
1320                       plane_sr, cursor_sr);
1321
1322         I915_WRITE(DSPFW1,
1323                    (plane_sr << DSPFW_SR_SHIFT) |
1324                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1325                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1326                    planea_wm);
1327         I915_WRITE(DSPFW2,
1328                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1329                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1330         I915_WRITE(DSPFW3,
1331                    (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1332                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1333 }
1334
1335 static void g4x_update_wm(struct drm_device *dev)
1336 {
1337         static const int sr_latency_ns = 12000;
1338         struct drm_i915_private *dev_priv = dev->dev_private;
1339         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1340         int plane_sr, cursor_sr;
1341         unsigned int enabled = 0;
1342
1343         if (g4x_compute_wm0(dev, 0,
1344                             &g4x_wm_info, latency_ns,
1345                             &g4x_cursor_wm_info, latency_ns,
1346                             &planea_wm, &cursora_wm))
1347                 enabled |= 1;
1348
1349         if (g4x_compute_wm0(dev, 1,
1350                             &g4x_wm_info, latency_ns,
1351                             &g4x_cursor_wm_info, latency_ns,
1352                             &planeb_wm, &cursorb_wm))
1353                 enabled |= 2;
1354
1355         plane_sr = cursor_sr = 0;
1356         if (single_plane_enabled(enabled) &&
1357             g4x_compute_srwm(dev, ffs(enabled) - 1,
1358                              sr_latency_ns,
1359                              &g4x_wm_info,
1360                              &g4x_cursor_wm_info,
1361                              &plane_sr, &cursor_sr))
1362                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1363         else
1364                 I915_WRITE(FW_BLC_SELF,
1365                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1366
1367         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1368                       planea_wm, cursora_wm,
1369                       planeb_wm, cursorb_wm,
1370                       plane_sr, cursor_sr);
1371
1372         I915_WRITE(DSPFW1,
1373                    (plane_sr << DSPFW_SR_SHIFT) |
1374                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1375                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1376                    planea_wm);
1377         I915_WRITE(DSPFW2,
1378                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1379                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1380         /* HPLL off in SR has some issues on G4x... disable it */
1381         I915_WRITE(DSPFW3,
1382                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1383                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1384 }
1385
1386 static void i965_update_wm(struct drm_device *dev)
1387 {
1388         struct drm_i915_private *dev_priv = dev->dev_private;
1389         struct drm_crtc *crtc;
1390         int srwm = 1;
1391         int cursor_sr = 16;
1392
1393         /* Calc sr entries for one plane configs */
1394         crtc = single_enabled_crtc(dev);
1395         if (crtc) {
1396                 /* self-refresh has much higher latency */
1397                 static const int sr_latency_ns = 12000;
1398                 int clock = crtc->mode.clock;
1399                 int htotal = crtc->mode.htotal;
1400                 int hdisplay = crtc->mode.hdisplay;
1401                 int pixel_size = crtc->fb->bits_per_pixel / 8;
1402                 unsigned long line_time_us;
1403                 int entries;
1404
1405                 line_time_us = ((htotal * 1000) / clock);
1406
1407                 /* Use ns/us then divide to preserve precision */
1408                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1409                         pixel_size * hdisplay;
1410                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1411                 srwm = I965_FIFO_SIZE - entries;
1412                 if (srwm < 0)
1413                         srwm = 1;
1414                 srwm &= 0x1ff;
1415                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1416                               entries, srwm);
1417
1418                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1419                         pixel_size * 64;
1420                 entries = DIV_ROUND_UP(entries,
1421                                           i965_cursor_wm_info.cacheline_size);
1422                 cursor_sr = i965_cursor_wm_info.fifo_size -
1423                         (entries + i965_cursor_wm_info.guard_size);
1424
1425                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1426                         cursor_sr = i965_cursor_wm_info.max_wm;
1427
1428                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1429                               "cursor %d\n", srwm, cursor_sr);
1430
1431                 if (IS_CRESTLINE(dev))
1432                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1433         } else {
1434                 /* Turn off self refresh if both pipes are enabled */
1435                 if (IS_CRESTLINE(dev))
1436                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1437                                    & ~FW_BLC_SELF_EN);
1438         }
1439
1440         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1441                       srwm);
1442
1443         /* 965 has limitations... */
1444         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1445                    (8 << 16) | (8 << 8) | (8 << 0));
1446         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1447         /* update cursor SR watermark */
1448         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1449 }
1450
1451 static void i9xx_update_wm(struct drm_device *dev)
1452 {
1453         struct drm_i915_private *dev_priv = dev->dev_private;
1454         const struct intel_watermark_params *wm_info;
1455         uint32_t fwater_lo;
1456         uint32_t fwater_hi;
1457         int cwm, srwm = 1;
1458         int fifo_size;
1459         int planea_wm, planeb_wm;
1460         struct drm_crtc *crtc, *enabled = NULL;
1461
1462         if (IS_I945GM(dev))
1463                 wm_info = &i945_wm_info;
1464         else if (!IS_GEN2(dev))
1465                 wm_info = &i915_wm_info;
1466         else
1467                 wm_info = &i855_wm_info;
1468
1469         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1470         crtc = intel_get_crtc_for_plane(dev, 0);
1471         if (crtc->enabled && crtc->fb) {
1472                 int cpp = crtc->fb->bits_per_pixel / 8;
1473                 if (IS_GEN2(dev))
1474                         cpp = 4;
1475
1476                 planea_wm = intel_calculate_wm(crtc->mode.clock,
1477                                                wm_info, fifo_size, cpp,
1478                                                latency_ns);
1479                 enabled = crtc;
1480         } else
1481                 planea_wm = fifo_size - wm_info->guard_size;
1482
1483         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1484         crtc = intel_get_crtc_for_plane(dev, 1);
1485         if (crtc->enabled && crtc->fb) {
1486                 int cpp = crtc->fb->bits_per_pixel / 8;
1487                 if (IS_GEN2(dev))
1488                         cpp = 4;
1489
1490                 planeb_wm = intel_calculate_wm(crtc->mode.clock,
1491                                                wm_info, fifo_size, cpp,
1492                                                latency_ns);
1493                 if (enabled == NULL)
1494                         enabled = crtc;
1495                 else
1496                         enabled = NULL;
1497         } else
1498                 planeb_wm = fifo_size - wm_info->guard_size;
1499
1500         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1501
1502         /*
1503          * Overlay gets an aggressive default since video jitter is bad.
1504          */
1505         cwm = 2;
1506
1507         /* Play safe and disable self-refresh before adjusting watermarks. */
1508         if (IS_I945G(dev) || IS_I945GM(dev))
1509                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1510         else if (IS_I915GM(dev))
1511                 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1512
1513         /* Calc sr entries for one plane configs */
1514         if (HAS_FW_BLC(dev) && enabled) {
1515                 /* self-refresh has much higher latency */
1516                 static const int sr_latency_ns = 6000;
1517                 int clock = enabled->mode.clock;
1518                 int htotal = enabled->mode.htotal;
1519                 int hdisplay = enabled->mode.hdisplay;
1520                 int pixel_size = enabled->fb->bits_per_pixel / 8;
1521                 unsigned long line_time_us;
1522                 int entries;
1523
1524                 line_time_us = (htotal * 1000) / clock;
1525
1526                 /* Use ns/us then divide to preserve precision */
1527                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1528                         pixel_size * hdisplay;
1529                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1530                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1531                 srwm = wm_info->fifo_size - entries;
1532                 if (srwm < 0)
1533                         srwm = 1;
1534
1535                 if (IS_I945G(dev) || IS_I945GM(dev))
1536                         I915_WRITE(FW_BLC_SELF,
1537                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1538                 else if (IS_I915GM(dev))
1539                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1540         }
1541
1542         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1543                       planea_wm, planeb_wm, cwm, srwm);
1544
1545         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1546         fwater_hi = (cwm & 0x1f);
1547
1548         /* Set request length to 8 cachelines per fetch */
1549         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1550         fwater_hi = fwater_hi | (1 << 8);
1551
1552         I915_WRITE(FW_BLC, fwater_lo);
1553         I915_WRITE(FW_BLC2, fwater_hi);
1554
1555         if (HAS_FW_BLC(dev)) {
1556                 if (enabled) {
1557                         if (IS_I945G(dev) || IS_I945GM(dev))
1558                                 I915_WRITE(FW_BLC_SELF,
1559                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1560                         else if (IS_I915GM(dev))
1561                                 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1562                         DRM_DEBUG_KMS("memory self refresh enabled\n");
1563                 } else
1564                         DRM_DEBUG_KMS("memory self refresh disabled\n");
1565         }
1566 }
1567
1568 static void i830_update_wm(struct drm_device *dev)
1569 {
1570         struct drm_i915_private *dev_priv = dev->dev_private;
1571         struct drm_crtc *crtc;
1572         uint32_t fwater_lo;
1573         int planea_wm;
1574
1575         crtc = single_enabled_crtc(dev);
1576         if (crtc == NULL)
1577                 return;
1578
1579         planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
1580                                        dev_priv->display.get_fifo_size(dev, 0),
1581                                        4, latency_ns);
1582         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1583         fwater_lo |= (3<<8) | planea_wm;
1584
1585         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1586
1587         I915_WRITE(FW_BLC, fwater_lo);
1588 }
1589
1590 #define ILK_LP0_PLANE_LATENCY           700
1591 #define ILK_LP0_CURSOR_LATENCY          1300
1592
1593 /*
1594  * Check the wm result.
1595  *
1596  * If any calculated watermark values is larger than the maximum value that
1597  * can be programmed into the associated watermark register, that watermark
1598  * must be disabled.
1599  */
1600 static bool ironlake_check_srwm(struct drm_device *dev, int level,
1601                                 int fbc_wm, int display_wm, int cursor_wm,
1602                                 const struct intel_watermark_params *display,
1603                                 const struct intel_watermark_params *cursor)
1604 {
1605         struct drm_i915_private *dev_priv = dev->dev_private;
1606
1607         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1608                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1609
1610         if (fbc_wm > SNB_FBC_MAX_SRWM) {
1611                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1612                               fbc_wm, SNB_FBC_MAX_SRWM, level);
1613
1614                 /* fbc has it's own way to disable FBC WM */
1615                 I915_WRITE(DISP_ARB_CTL,
1616                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1617                 return false;
1618         }
1619
1620         if (display_wm > display->max_wm) {
1621                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1622                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
1623                 return false;
1624         }
1625
1626         if (cursor_wm > cursor->max_wm) {
1627                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1628                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1629                 return false;
1630         }
1631
1632         if (!(fbc_wm || display_wm || cursor_wm)) {
1633                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1634                 return false;
1635         }
1636
1637         return true;
1638 }
1639
1640 /*
1641  * Compute watermark values of WM[1-3],
1642  */
1643 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1644                                   int latency_ns,
1645                                   const struct intel_watermark_params *display,
1646                                   const struct intel_watermark_params *cursor,
1647                                   int *fbc_wm, int *display_wm, int *cursor_wm)
1648 {
1649         struct drm_crtc *crtc;
1650         unsigned long line_time_us;
1651         int hdisplay, htotal, pixel_size, clock;
1652         int line_count, line_size;
1653         int small, large;
1654         int entries;
1655
1656         if (!latency_ns) {
1657                 *fbc_wm = *display_wm = *cursor_wm = 0;
1658                 return false;
1659         }
1660
1661         crtc = intel_get_crtc_for_plane(dev, plane);
1662         hdisplay = crtc->mode.hdisplay;
1663         htotal = crtc->mode.htotal;
1664         clock = crtc->mode.clock;
1665         pixel_size = crtc->fb->bits_per_pixel / 8;
1666
1667         line_time_us = (htotal * 1000) / clock;
1668         line_count = (latency_ns / line_time_us + 1000) / 1000;
1669         line_size = hdisplay * pixel_size;
1670
1671         /* Use the minimum of the small and large buffer method for primary */
1672         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1673         large = line_count * line_size;
1674
1675         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1676         *display_wm = entries + display->guard_size;
1677
1678         /*
1679          * Spec says:
1680          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1681          */
1682         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1683
1684         /* calculate the self-refresh watermark for display cursor */
1685         entries = line_count * pixel_size * 64;
1686         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1687         *cursor_wm = entries + cursor->guard_size;
1688
1689         return ironlake_check_srwm(dev, level,
1690                                    *fbc_wm, *display_wm, *cursor_wm,
1691                                    display, cursor);
1692 }
1693
1694 static void ironlake_update_wm(struct drm_device *dev)
1695 {
1696         struct drm_i915_private *dev_priv = dev->dev_private;
1697         int fbc_wm, plane_wm, cursor_wm;
1698         unsigned int enabled;
1699
1700         enabled = 0;
1701         if (g4x_compute_wm0(dev, 0,
1702                             &ironlake_display_wm_info,
1703                             ILK_LP0_PLANE_LATENCY,
1704                             &ironlake_cursor_wm_info,
1705                             ILK_LP0_CURSOR_LATENCY,
1706                             &plane_wm, &cursor_wm)) {
1707                 I915_WRITE(WM0_PIPEA_ILK,
1708                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1709                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1710                               " plane %d, " "cursor: %d\n",
1711                               plane_wm, cursor_wm);
1712                 enabled |= 1;
1713         }
1714
1715         if (g4x_compute_wm0(dev, 1,
1716                             &ironlake_display_wm_info,
1717                             ILK_LP0_PLANE_LATENCY,
1718                             &ironlake_cursor_wm_info,
1719                             ILK_LP0_CURSOR_LATENCY,
1720                             &plane_wm, &cursor_wm)) {
1721                 I915_WRITE(WM0_PIPEB_ILK,
1722                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1723                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1724                               " plane %d, cursor: %d\n",
1725                               plane_wm, cursor_wm);
1726                 enabled |= 2;
1727         }
1728
1729         /*
1730          * Calculate and update the self-refresh watermark only when one
1731          * display plane is used.
1732          */
1733         I915_WRITE(WM3_LP_ILK, 0);
1734         I915_WRITE(WM2_LP_ILK, 0);
1735         I915_WRITE(WM1_LP_ILK, 0);
1736
1737         if (!single_plane_enabled(enabled))
1738                 return;
1739         enabled = ffs(enabled) - 1;
1740
1741         /* WM1 */
1742         if (!ironlake_compute_srwm(dev, 1, enabled,
1743                                    ILK_READ_WM1_LATENCY() * 500,
1744                                    &ironlake_display_srwm_info,
1745                                    &ironlake_cursor_srwm_info,
1746                                    &fbc_wm, &plane_wm, &cursor_wm))
1747                 return;
1748
1749         I915_WRITE(WM1_LP_ILK,
1750                    WM1_LP_SR_EN |
1751                    (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1752                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1753                    (plane_wm << WM1_LP_SR_SHIFT) |
1754                    cursor_wm);
1755
1756         /* WM2 */
1757         if (!ironlake_compute_srwm(dev, 2, enabled,
1758                                    ILK_READ_WM2_LATENCY() * 500,
1759                                    &ironlake_display_srwm_info,
1760                                    &ironlake_cursor_srwm_info,
1761                                    &fbc_wm, &plane_wm, &cursor_wm))
1762                 return;
1763
1764         I915_WRITE(WM2_LP_ILK,
1765                    WM2_LP_EN |
1766                    (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1767                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1768                    (plane_wm << WM1_LP_SR_SHIFT) |
1769                    cursor_wm);
1770
1771         /*
1772          * WM3 is unsupported on ILK, probably because we don't have latency
1773          * data for that power state
1774          */
1775 }
1776
1777 static void sandybridge_update_wm(struct drm_device *dev)
1778 {
1779         struct drm_i915_private *dev_priv = dev->dev_private;
1780         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
1781         u32 val;
1782         int fbc_wm, plane_wm, cursor_wm;
1783         unsigned int enabled;
1784
1785         enabled = 0;
1786         if (g4x_compute_wm0(dev, 0,
1787                             &sandybridge_display_wm_info, latency,
1788                             &sandybridge_cursor_wm_info, latency,
1789                             &plane_wm, &cursor_wm)) {
1790                 val = I915_READ(WM0_PIPEA_ILK);
1791                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1792                 I915_WRITE(WM0_PIPEA_ILK, val |
1793                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1794                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1795                               " plane %d, " "cursor: %d\n",
1796                               plane_wm, cursor_wm);
1797                 enabled |= 1;
1798         }
1799
1800         if (g4x_compute_wm0(dev, 1,
1801                             &sandybridge_display_wm_info, latency,
1802                             &sandybridge_cursor_wm_info, latency,
1803                             &plane_wm, &cursor_wm)) {
1804                 val = I915_READ(WM0_PIPEB_ILK);
1805                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1806                 I915_WRITE(WM0_PIPEB_ILK, val |
1807                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1808                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1809                               " plane %d, cursor: %d\n",
1810                               plane_wm, cursor_wm);
1811                 enabled |= 2;
1812         }
1813
1814         /*
1815          * Calculate and update the self-refresh watermark only when one
1816          * display plane is used.
1817          *
1818          * SNB support 3 levels of watermark.
1819          *
1820          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1821          * and disabled in the descending order
1822          *
1823          */
1824         I915_WRITE(WM3_LP_ILK, 0);
1825         I915_WRITE(WM2_LP_ILK, 0);
1826         I915_WRITE(WM1_LP_ILK, 0);
1827
1828         if (!single_plane_enabled(enabled) ||
1829             dev_priv->sprite_scaling_enabled)
1830                 return;
1831         enabled = ffs(enabled) - 1;
1832
1833         /* WM1 */
1834         if (!ironlake_compute_srwm(dev, 1, enabled,
1835                                    SNB_READ_WM1_LATENCY() * 500,
1836                                    &sandybridge_display_srwm_info,
1837                                    &sandybridge_cursor_srwm_info,
1838                                    &fbc_wm, &plane_wm, &cursor_wm))
1839                 return;
1840
1841         I915_WRITE(WM1_LP_ILK,
1842                    WM1_LP_SR_EN |
1843                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1844                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1845                    (plane_wm << WM1_LP_SR_SHIFT) |
1846                    cursor_wm);
1847
1848         /* WM2 */
1849         if (!ironlake_compute_srwm(dev, 2, enabled,
1850                                    SNB_READ_WM2_LATENCY() * 500,
1851                                    &sandybridge_display_srwm_info,
1852                                    &sandybridge_cursor_srwm_info,
1853                                    &fbc_wm, &plane_wm, &cursor_wm))
1854                 return;
1855
1856         I915_WRITE(WM2_LP_ILK,
1857                    WM2_LP_EN |
1858                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1859                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1860                    (plane_wm << WM1_LP_SR_SHIFT) |
1861                    cursor_wm);
1862
1863         /* WM3 */
1864         if (!ironlake_compute_srwm(dev, 3, enabled,
1865                                    SNB_READ_WM3_LATENCY() * 500,
1866                                    &sandybridge_display_srwm_info,
1867                                    &sandybridge_cursor_srwm_info,
1868                                    &fbc_wm, &plane_wm, &cursor_wm))
1869                 return;
1870
1871         I915_WRITE(WM3_LP_ILK,
1872                    WM3_LP_EN |
1873                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1874                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1875                    (plane_wm << WM1_LP_SR_SHIFT) |
1876                    cursor_wm);
1877 }
1878
1879 static void ivybridge_update_wm(struct drm_device *dev)
1880 {
1881         struct drm_i915_private *dev_priv = dev->dev_private;
1882         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
1883         u32 val;
1884         int fbc_wm, plane_wm, cursor_wm;
1885         int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
1886         unsigned int enabled;
1887
1888         enabled = 0;
1889         if (g4x_compute_wm0(dev, 0,
1890                             &sandybridge_display_wm_info, latency,
1891                             &sandybridge_cursor_wm_info, latency,
1892                             &plane_wm, &cursor_wm)) {
1893                 val = I915_READ(WM0_PIPEA_ILK);
1894                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1895                 I915_WRITE(WM0_PIPEA_ILK, val |
1896                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1897                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1898                               " plane %d, " "cursor: %d\n",
1899                               plane_wm, cursor_wm);
1900                 enabled |= 1;
1901         }
1902
1903         if (g4x_compute_wm0(dev, 1,
1904                             &sandybridge_display_wm_info, latency,
1905                             &sandybridge_cursor_wm_info, latency,
1906                             &plane_wm, &cursor_wm)) {
1907                 val = I915_READ(WM0_PIPEB_ILK);
1908                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1909                 I915_WRITE(WM0_PIPEB_ILK, val |
1910                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1911                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1912                               " plane %d, cursor: %d\n",
1913                               plane_wm, cursor_wm);
1914                 enabled |= 2;
1915         }
1916
1917         if (g4x_compute_wm0(dev, 2,
1918                             &sandybridge_display_wm_info, latency,
1919                             &sandybridge_cursor_wm_info, latency,
1920                             &plane_wm, &cursor_wm)) {
1921                 val = I915_READ(WM0_PIPEC_IVB);
1922                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1923                 I915_WRITE(WM0_PIPEC_IVB, val |
1924                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1925                 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
1926                               " plane %d, cursor: %d\n",
1927                               plane_wm, cursor_wm);
1928                 enabled |= 3;
1929         }
1930
1931         /*
1932          * Calculate and update the self-refresh watermark only when one
1933          * display plane is used.
1934          *
1935          * SNB support 3 levels of watermark.
1936          *
1937          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1938          * and disabled in the descending order
1939          *
1940          */
1941         I915_WRITE(WM3_LP_ILK, 0);
1942         I915_WRITE(WM2_LP_ILK, 0);
1943         I915_WRITE(WM1_LP_ILK, 0);
1944
1945         if (!single_plane_enabled(enabled) ||
1946             dev_priv->sprite_scaling_enabled)
1947                 return;
1948         enabled = ffs(enabled) - 1;
1949
1950         /* WM1 */
1951         if (!ironlake_compute_srwm(dev, 1, enabled,
1952                                    SNB_READ_WM1_LATENCY() * 500,
1953                                    &sandybridge_display_srwm_info,
1954                                    &sandybridge_cursor_srwm_info,
1955                                    &fbc_wm, &plane_wm, &cursor_wm))
1956                 return;
1957
1958         I915_WRITE(WM1_LP_ILK,
1959                    WM1_LP_SR_EN |
1960                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1961                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1962                    (plane_wm << WM1_LP_SR_SHIFT) |
1963                    cursor_wm);
1964
1965         /* WM2 */
1966         if (!ironlake_compute_srwm(dev, 2, enabled,
1967                                    SNB_READ_WM2_LATENCY() * 500,
1968                                    &sandybridge_display_srwm_info,
1969                                    &sandybridge_cursor_srwm_info,
1970                                    &fbc_wm, &plane_wm, &cursor_wm))
1971                 return;
1972
1973         I915_WRITE(WM2_LP_ILK,
1974                    WM2_LP_EN |
1975                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1976                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1977                    (plane_wm << WM1_LP_SR_SHIFT) |
1978                    cursor_wm);
1979
1980         /* WM3, note we have to correct the cursor latency */
1981         if (!ironlake_compute_srwm(dev, 3, enabled,
1982                                    SNB_READ_WM3_LATENCY() * 500,
1983                                    &sandybridge_display_srwm_info,
1984                                    &sandybridge_cursor_srwm_info,
1985                                    &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
1986             !ironlake_compute_srwm(dev, 3, enabled,
1987                                    2 * SNB_READ_WM3_LATENCY() * 500,
1988                                    &sandybridge_display_srwm_info,
1989                                    &sandybridge_cursor_srwm_info,
1990                                    &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
1991                 return;
1992
1993         I915_WRITE(WM3_LP_ILK,
1994                    WM3_LP_EN |
1995                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1996                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1997                    (plane_wm << WM1_LP_SR_SHIFT) |
1998                    cursor_wm);
1999 }
2000
2001 static void
2002 haswell_update_linetime_wm(struct drm_device *dev, int pipe,
2003                                  struct drm_display_mode *mode)
2004 {
2005         struct drm_i915_private *dev_priv = dev->dev_private;
2006         u32 temp;
2007
2008         temp = I915_READ(PIPE_WM_LINETIME(pipe));
2009         temp &= ~PIPE_WM_LINETIME_MASK;
2010
2011         /* The WM are computed with base on how long it takes to fill a single
2012          * row at the given clock rate, multiplied by 8.
2013          * */
2014         temp |= PIPE_WM_LINETIME_TIME(
2015                 ((mode->crtc_hdisplay * 1000) / mode->clock) * 8);
2016
2017         /* IPS watermarks are only used by pipe A, and are ignored by
2018          * pipes B and C.  They are calculated similarly to the common
2019          * linetime values, except that we are using CD clock frequency
2020          * in MHz instead of pixel rate for the division.
2021          *
2022          * This is a placeholder for the IPS watermark calculation code.
2023          */
2024
2025         I915_WRITE(PIPE_WM_LINETIME(pipe), temp);
2026 }
2027
2028 static bool
2029 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
2030                               uint32_t sprite_width, int pixel_size,
2031                               const struct intel_watermark_params *display,
2032                               int display_latency_ns, int *sprite_wm)
2033 {
2034         struct drm_crtc *crtc;
2035         int clock;
2036         int entries, tlb_miss;
2037
2038         crtc = intel_get_crtc_for_plane(dev, plane);
2039         if (crtc->fb == NULL || !crtc->enabled) {
2040                 *sprite_wm = display->guard_size;
2041                 return false;
2042         }
2043
2044         clock = crtc->mode.clock;
2045
2046         /* Use the small buffer method to calculate the sprite watermark */
2047         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
2048         tlb_miss = display->fifo_size*display->cacheline_size -
2049                 sprite_width * 8;
2050         if (tlb_miss > 0)
2051                 entries += tlb_miss;
2052         entries = DIV_ROUND_UP(entries, display->cacheline_size);
2053         *sprite_wm = entries + display->guard_size;
2054         if (*sprite_wm > (int)display->max_wm)
2055                 *sprite_wm = display->max_wm;
2056
2057         return true;
2058 }
2059
2060 static bool
2061 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
2062                                 uint32_t sprite_width, int pixel_size,
2063                                 const struct intel_watermark_params *display,
2064                                 int latency_ns, int *sprite_wm)
2065 {
2066         struct drm_crtc *crtc;
2067         unsigned long line_time_us;
2068         int clock;
2069         int line_count, line_size;
2070         int small, large;
2071         int entries;
2072
2073         if (!latency_ns) {
2074                 *sprite_wm = 0;
2075                 return false;
2076         }
2077
2078         crtc = intel_get_crtc_for_plane(dev, plane);
2079         clock = crtc->mode.clock;
2080         if (!clock) {
2081                 *sprite_wm = 0;
2082                 return false;
2083         }
2084
2085         line_time_us = (sprite_width * 1000) / clock;
2086         if (!line_time_us) {
2087                 *sprite_wm = 0;
2088                 return false;
2089         }
2090
2091         line_count = (latency_ns / line_time_us + 1000) / 1000;
2092         line_size = sprite_width * pixel_size;
2093
2094         /* Use the minimum of the small and large buffer method for primary */
2095         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
2096         large = line_count * line_size;
2097
2098         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
2099         *sprite_wm = entries + display->guard_size;
2100
2101         return *sprite_wm > 0x3ff ? false : true;
2102 }
2103
2104 static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
2105                                          uint32_t sprite_width, int pixel_size)
2106 {
2107         struct drm_i915_private *dev_priv = dev->dev_private;
2108         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
2109         u32 val;
2110         int sprite_wm, reg;
2111         int ret;
2112
2113         switch (pipe) {
2114         case 0:
2115                 reg = WM0_PIPEA_ILK;
2116                 break;
2117         case 1:
2118                 reg = WM0_PIPEB_ILK;
2119                 break;
2120         case 2:
2121                 reg = WM0_PIPEC_IVB;
2122                 break;
2123         default:
2124                 return; /* bad pipe */
2125         }
2126
2127         ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
2128                                             &sandybridge_display_wm_info,
2129                                             latency, &sprite_wm);
2130         if (!ret) {
2131                 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
2132                               pipe);
2133                 return;
2134         }
2135
2136         val = I915_READ(reg);
2137         val &= ~WM0_PIPE_SPRITE_MASK;
2138         I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
2139         DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
2140
2141
2142         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2143                                               pixel_size,
2144                                               &sandybridge_display_srwm_info,
2145                                               SNB_READ_WM1_LATENCY() * 500,
2146                                               &sprite_wm);
2147         if (!ret) {
2148                 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
2149                               pipe);
2150                 return;
2151         }
2152         I915_WRITE(WM1S_LP_ILK, sprite_wm);
2153
2154         /* Only IVB has two more LP watermarks for sprite */
2155         if (!IS_IVYBRIDGE(dev))
2156                 return;
2157
2158         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2159                                               pixel_size,
2160                                               &sandybridge_display_srwm_info,
2161                                               SNB_READ_WM2_LATENCY() * 500,
2162                                               &sprite_wm);
2163         if (!ret) {
2164                 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
2165                               pipe);
2166                 return;
2167         }
2168         I915_WRITE(WM2S_LP_IVB, sprite_wm);
2169
2170         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2171                                               pixel_size,
2172                                               &sandybridge_display_srwm_info,
2173                                               SNB_READ_WM3_LATENCY() * 500,
2174                                               &sprite_wm);
2175         if (!ret) {
2176                 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
2177                               pipe);
2178                 return;
2179         }
2180         I915_WRITE(WM3S_LP_IVB, sprite_wm);
2181 }
2182
2183 /**
2184  * intel_update_watermarks - update FIFO watermark values based on current modes
2185  *
2186  * Calculate watermark values for the various WM regs based on current mode
2187  * and plane configuration.
2188  *
2189  * There are several cases to deal with here:
2190  *   - normal (i.e. non-self-refresh)
2191  *   - self-refresh (SR) mode
2192  *   - lines are large relative to FIFO size (buffer can hold up to 2)
2193  *   - lines are small relative to FIFO size (buffer can hold more than 2
2194  *     lines), so need to account for TLB latency
2195  *
2196  *   The normal calculation is:
2197  *     watermark = dotclock * bytes per pixel * latency
2198  *   where latency is platform & configuration dependent (we assume pessimal
2199  *   values here).
2200  *
2201  *   The SR calculation is:
2202  *     watermark = (trunc(latency/line time)+1) * surface width *
2203  *       bytes per pixel
2204  *   where
2205  *     line time = htotal / dotclock
2206  *     surface width = hdisplay for normal plane and 64 for cursor
2207  *   and latency is assumed to be high, as above.
2208  *
2209  * The final value programmed to the register should always be rounded up,
2210  * and include an extra 2 entries to account for clock crossings.
2211  *
2212  * We don't use the sprite, so we can ignore that.  And on Crestline we have
2213  * to set the non-SR watermarks to 8.
2214  */
2215 void intel_update_watermarks(struct drm_device *dev)
2216 {
2217         struct drm_i915_private *dev_priv = dev->dev_private;
2218
2219         if (dev_priv->display.update_wm)
2220                 dev_priv->display.update_wm(dev);
2221 }
2222
2223 void intel_update_linetime_watermarks(struct drm_device *dev,
2224                 int pipe, struct drm_display_mode *mode)
2225 {
2226         struct drm_i915_private *dev_priv = dev->dev_private;
2227
2228         if (dev_priv->display.update_linetime_wm)
2229                 dev_priv->display.update_linetime_wm(dev, pipe, mode);
2230 }
2231
2232 void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
2233                                     uint32_t sprite_width, int pixel_size)
2234 {
2235         struct drm_i915_private *dev_priv = dev->dev_private;
2236
2237         if (dev_priv->display.update_sprite_wm)
2238                 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
2239                                                    pixel_size);
2240 }
2241
2242 static struct drm_i915_gem_object *
2243 intel_alloc_context_page(struct drm_device *dev)
2244 {
2245         struct drm_i915_gem_object *ctx;
2246         int ret;
2247
2248         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2249
2250         ctx = i915_gem_alloc_object(dev, 4096);
2251         if (!ctx) {
2252                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2253                 return NULL;
2254         }
2255
2256         ret = i915_gem_object_pin(ctx, 4096, true, false);
2257         if (ret) {
2258                 DRM_ERROR("failed to pin power context: %d\n", ret);
2259                 goto err_unref;
2260         }
2261
2262         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2263         if (ret) {
2264                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2265                 goto err_unpin;
2266         }
2267
2268         return ctx;
2269
2270 err_unpin:
2271         i915_gem_object_unpin(ctx);
2272 err_unref:
2273         drm_gem_object_unreference(&ctx->base);
2274         mutex_unlock(&dev->struct_mutex);
2275         return NULL;
2276 }
2277
2278 /**
2279  * Lock protecting IPS related data structures
2280  */
2281 DEFINE_SPINLOCK(mchdev_lock);
2282
2283 /* Global for IPS driver to get at the current i915 device. Protected by
2284  * mchdev_lock. */
2285 static struct drm_i915_private *i915_mch_dev;
2286
2287 bool ironlake_set_drps(struct drm_device *dev, u8 val)
2288 {
2289         struct drm_i915_private *dev_priv = dev->dev_private;
2290         u16 rgvswctl;
2291
2292         assert_spin_locked(&mchdev_lock);
2293
2294         rgvswctl = I915_READ16(MEMSWCTL);
2295         if (rgvswctl & MEMCTL_CMD_STS) {
2296                 DRM_DEBUG("gpu busy, RCS change rejected\n");
2297                 return false; /* still busy with another command */
2298         }
2299
2300         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2301                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2302         I915_WRITE16(MEMSWCTL, rgvswctl);
2303         POSTING_READ16(MEMSWCTL);
2304
2305         rgvswctl |= MEMCTL_CMD_STS;
2306         I915_WRITE16(MEMSWCTL, rgvswctl);
2307
2308         return true;
2309 }
2310
2311 static void ironlake_enable_drps(struct drm_device *dev)
2312 {
2313         struct drm_i915_private *dev_priv = dev->dev_private;
2314         u32 rgvmodectl = I915_READ(MEMMODECTL);
2315         u8 fmax, fmin, fstart, vstart;
2316
2317         spin_lock_irq(&mchdev_lock);
2318
2319         /* Enable temp reporting */
2320         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2321         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2322
2323         /* 100ms RC evaluation intervals */
2324         I915_WRITE(RCUPEI, 100000);
2325         I915_WRITE(RCDNEI, 100000);
2326
2327         /* Set max/min thresholds to 90ms and 80ms respectively */
2328         I915_WRITE(RCBMAXAVG, 90000);
2329         I915_WRITE(RCBMINAVG, 80000);
2330
2331         I915_WRITE(MEMIHYST, 1);
2332
2333         /* Set up min, max, and cur for interrupt handling */
2334         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2335         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2336         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2337                 MEMMODE_FSTART_SHIFT;
2338
2339         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2340                 PXVFREQ_PX_SHIFT;
2341
2342         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2343         dev_priv->ips.fstart = fstart;
2344
2345         dev_priv->ips.max_delay = fstart;
2346         dev_priv->ips.min_delay = fmin;
2347         dev_priv->ips.cur_delay = fstart;
2348
2349         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2350                          fmax, fmin, fstart);
2351
2352         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2353
2354         /*
2355          * Interrupts will be enabled in ironlake_irq_postinstall
2356          */
2357
2358         I915_WRITE(VIDSTART, vstart);
2359         POSTING_READ(VIDSTART);
2360
2361         rgvmodectl |= MEMMODE_SWMODE_EN;
2362         I915_WRITE(MEMMODECTL, rgvmodectl);
2363
2364         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2365                 DRM_ERROR("stuck trying to change perf mode\n");
2366         mdelay(1);
2367
2368         ironlake_set_drps(dev, fstart);
2369
2370         dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2371                 I915_READ(0x112e0);
2372         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2373         dev_priv->ips.last_count2 = I915_READ(0x112f4);
2374         getrawmonotonic(&dev_priv->ips.last_time2);
2375
2376         spin_unlock_irq(&mchdev_lock);
2377 }
2378
2379 static void ironlake_disable_drps(struct drm_device *dev)
2380 {
2381         struct drm_i915_private *dev_priv = dev->dev_private;
2382         u16 rgvswctl;
2383
2384         spin_lock_irq(&mchdev_lock);
2385
2386         rgvswctl = I915_READ16(MEMSWCTL);
2387
2388         /* Ack interrupts, disable EFC interrupt */
2389         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
2390         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
2391         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
2392         I915_WRITE(DEIIR, DE_PCU_EVENT);
2393         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
2394
2395         /* Go back to the starting frequency */
2396         ironlake_set_drps(dev, dev_priv->ips.fstart);
2397         mdelay(1);
2398         rgvswctl |= MEMCTL_CMD_STS;
2399         I915_WRITE(MEMSWCTL, rgvswctl);
2400         mdelay(1);
2401
2402         spin_unlock_irq(&mchdev_lock);
2403 }
2404
2405 /* There's a funny hw issue where the hw returns all 0 when reading from
2406  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
2407  * ourselves, instead of doing a rmw cycle (which might result in us clearing
2408  * all limits and the gpu stuck at whatever frequency it is at atm).
2409  */
2410 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
2411 {
2412         u32 limits;
2413
2414         limits = 0;
2415
2416         if (*val >= dev_priv->rps.max_delay)
2417                 *val = dev_priv->rps.max_delay;
2418         limits |= dev_priv->rps.max_delay << 24;
2419
2420         /* Only set the down limit when we've reached the lowest level to avoid
2421          * getting more interrupts, otherwise leave this clear. This prevents a
2422          * race in the hw when coming out of rc6: There's a tiny window where
2423          * the hw runs at the minimal clock before selecting the desired
2424          * frequency, if the down threshold expires in that window we will not
2425          * receive a down interrupt. */
2426         if (*val <= dev_priv->rps.min_delay) {
2427                 *val = dev_priv->rps.min_delay;
2428                 limits |= dev_priv->rps.min_delay << 16;
2429         }
2430
2431         return limits;
2432 }
2433
2434 void gen6_set_rps(struct drm_device *dev, u8 val)
2435 {
2436         struct drm_i915_private *dev_priv = dev->dev_private;
2437         u32 limits = gen6_rps_limits(dev_priv, &val);
2438
2439         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2440         WARN_ON(val > dev_priv->rps.max_delay);
2441         WARN_ON(val < dev_priv->rps.min_delay);
2442
2443         if (val == dev_priv->rps.cur_delay)
2444                 return;
2445
2446         I915_WRITE(GEN6_RPNSWREQ,
2447                    GEN6_FREQUENCY(val) |
2448                    GEN6_OFFSET(0) |
2449                    GEN6_AGGRESSIVE_TURBO);
2450
2451         /* Make sure we continue to get interrupts
2452          * until we hit the minimum or maximum frequencies.
2453          */
2454         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
2455
2456         POSTING_READ(GEN6_RPNSWREQ);
2457
2458         dev_priv->rps.cur_delay = val;
2459
2460         trace_intel_gpu_freq_change(val * 50);
2461 }
2462
2463 static void gen6_disable_rps(struct drm_device *dev)
2464 {
2465         struct drm_i915_private *dev_priv = dev->dev_private;
2466
2467         I915_WRITE(GEN6_RC_CONTROL, 0);
2468         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
2469         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
2470         I915_WRITE(GEN6_PMIER, 0);
2471         /* Complete PM interrupt masking here doesn't race with the rps work
2472          * item again unmasking PM interrupts because that is using a different
2473          * register (PMIMR) to mask PM interrupts. The only risk is in leaving
2474          * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
2475
2476         spin_lock_irq(&dev_priv->rps.lock);
2477         dev_priv->rps.pm_iir = 0;
2478         spin_unlock_irq(&dev_priv->rps.lock);
2479
2480         I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2481 }
2482
2483 int intel_enable_rc6(const struct drm_device *dev)
2484 {
2485         /* Respect the kernel parameter if it is set */
2486         if (i915_enable_rc6 >= 0)
2487                 return i915_enable_rc6;
2488
2489         if (INTEL_INFO(dev)->gen == 5) {
2490 #ifdef CONFIG_INTEL_IOMMU
2491                 /* Disable rc6 on ilk if VT-d is on. */
2492                 if (intel_iommu_gfx_mapped)
2493                         return false;
2494 #endif
2495                 DRM_DEBUG_DRIVER("Ironlake: only RC6 available\n");
2496                 return INTEL_RC6_ENABLE;
2497         }
2498
2499         if (IS_HASWELL(dev)) {
2500                 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
2501                 return INTEL_RC6_ENABLE;
2502         }
2503
2504         /* snb/ivb have more than one rc6 state. */
2505         if (INTEL_INFO(dev)->gen == 6) {
2506                 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
2507                 return INTEL_RC6_ENABLE;
2508         }
2509
2510         DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
2511         return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
2512 }
2513
2514 static void gen6_enable_rps(struct drm_device *dev)
2515 {
2516         struct drm_i915_private *dev_priv = dev->dev_private;
2517         struct intel_ring_buffer *ring;
2518         u32 rp_state_cap;
2519         u32 gt_perf_status;
2520         u32 rc6vids, pcu_mbox, rc6_mask = 0;
2521         u32 gtfifodbg;
2522         int rc6_mode;
2523         int i, ret;
2524
2525         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2526
2527         /* Here begins a magic sequence of register writes to enable
2528          * auto-downclocking.
2529          *
2530          * Perhaps there might be some value in exposing these to
2531          * userspace...
2532          */
2533         I915_WRITE(GEN6_RC_STATE, 0);
2534
2535         /* Clear the DBG now so we don't confuse earlier errors */
2536         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
2537                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
2538                 I915_WRITE(GTFIFODBG, gtfifodbg);
2539         }
2540
2541         gen6_gt_force_wake_get(dev_priv);
2542
2543         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
2544         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
2545
2546         /* In units of 100MHz */
2547         dev_priv->rps.max_delay = rp_state_cap & 0xff;
2548         dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16;
2549         dev_priv->rps.cur_delay = 0;
2550
2551         /* disable the counters and set deterministic thresholds */
2552         I915_WRITE(GEN6_RC_CONTROL, 0);
2553
2554         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
2555         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
2556         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
2557         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
2558         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
2559
2560         for_each_ring(ring, dev_priv, i)
2561                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2562
2563         I915_WRITE(GEN6_RC_SLEEP, 0);
2564         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
2565         I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
2566         I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
2567         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
2568
2569         /* Check if we are enabling RC6 */
2570         rc6_mode = intel_enable_rc6(dev_priv->dev);
2571         if (rc6_mode & INTEL_RC6_ENABLE)
2572                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
2573
2574         /* We don't use those on Haswell */
2575         if (!IS_HASWELL(dev)) {
2576                 if (rc6_mode & INTEL_RC6p_ENABLE)
2577                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2578
2579                 if (rc6_mode & INTEL_RC6pp_ENABLE)
2580                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
2581         }
2582
2583         DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
2584                         (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
2585                         (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
2586                         (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
2587
2588         I915_WRITE(GEN6_RC_CONTROL,
2589                    rc6_mask |
2590                    GEN6_RC_CTL_EI_MODE(1) |
2591                    GEN6_RC_CTL_HW_ENABLE);
2592
2593         I915_WRITE(GEN6_RPNSWREQ,
2594                    GEN6_FREQUENCY(10) |
2595                    GEN6_OFFSET(0) |
2596                    GEN6_AGGRESSIVE_TURBO);
2597         I915_WRITE(GEN6_RC_VIDEO_FREQ,
2598                    GEN6_FREQUENCY(12));
2599
2600         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2601         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
2602                    dev_priv->rps.max_delay << 24 |
2603                    dev_priv->rps.min_delay << 16);
2604
2605         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
2606         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
2607         I915_WRITE(GEN6_RP_UP_EI, 66000);
2608         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
2609
2610         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2611         I915_WRITE(GEN6_RP_CONTROL,
2612                    GEN6_RP_MEDIA_TURBO |
2613                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
2614                    GEN6_RP_MEDIA_IS_GFX |
2615                    GEN6_RP_ENABLE |
2616                    GEN6_RP_UP_BUSY_AVG |
2617                    (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
2618
2619         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
2620         if (!ret) {
2621                 pcu_mbox = 0;
2622                 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
2623                 if (ret && pcu_mbox & (1<<31)) { /* OC supported */
2624                         dev_priv->rps.max_delay = pcu_mbox & 0xff;
2625                         DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
2626                 }
2627         } else {
2628                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
2629         }
2630
2631         gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
2632
2633         /* requires MSI enabled */
2634         I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
2635         spin_lock_irq(&dev_priv->rps.lock);
2636         WARN_ON(dev_priv->rps.pm_iir != 0);
2637         I915_WRITE(GEN6_PMIMR, 0);
2638         spin_unlock_irq(&dev_priv->rps.lock);
2639         /* enable all PM interrupts */
2640         I915_WRITE(GEN6_PMINTRMSK, 0);
2641
2642         rc6vids = 0;
2643         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
2644         if (IS_GEN6(dev) && ret) {
2645                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
2646         } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
2647                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
2648                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
2649                 rc6vids &= 0xffff00;
2650                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
2651                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
2652                 if (ret)
2653                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
2654         }
2655
2656         gen6_gt_force_wake_put(dev_priv);
2657 }
2658
2659 static void gen6_update_ring_freq(struct drm_device *dev)
2660 {
2661         struct drm_i915_private *dev_priv = dev->dev_private;
2662         int min_freq = 15;
2663         int gpu_freq;
2664         unsigned int ia_freq, max_ia_freq;
2665         int scaling_factor = 180;
2666
2667         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2668
2669         max_ia_freq = cpufreq_quick_get_max(0);
2670         /*
2671          * Default to measured freq if none found, PCU will ensure we don't go
2672          * over
2673          */
2674         if (!max_ia_freq)
2675                 max_ia_freq = tsc_khz;
2676
2677         /* Convert from kHz to MHz */
2678         max_ia_freq /= 1000;
2679
2680         /*
2681          * For each potential GPU frequency, load a ring frequency we'd like
2682          * to use for memory access.  We do this by specifying the IA frequency
2683          * the PCU should use as a reference to determine the ring frequency.
2684          */
2685         for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
2686              gpu_freq--) {
2687                 int diff = dev_priv->rps.max_delay - gpu_freq;
2688
2689                 /*
2690                  * For GPU frequencies less than 750MHz, just use the lowest
2691                  * ring freq.
2692                  */
2693                 if (gpu_freq < min_freq)
2694                         ia_freq = 800;
2695                 else
2696                         ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
2697                 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
2698                 ia_freq <<= GEN6_PCODE_FREQ_IA_RATIO_SHIFT;
2699
2700                 sandybridge_pcode_write(dev_priv,
2701                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
2702                                         ia_freq | gpu_freq);
2703         }
2704 }
2705
2706 void ironlake_teardown_rc6(struct drm_device *dev)
2707 {
2708         struct drm_i915_private *dev_priv = dev->dev_private;
2709
2710         if (dev_priv->ips.renderctx) {
2711                 i915_gem_object_unpin(dev_priv->ips.renderctx);
2712                 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
2713                 dev_priv->ips.renderctx = NULL;
2714         }
2715
2716         if (dev_priv->ips.pwrctx) {
2717                 i915_gem_object_unpin(dev_priv->ips.pwrctx);
2718                 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
2719                 dev_priv->ips.pwrctx = NULL;
2720         }
2721 }
2722
2723 static void ironlake_disable_rc6(struct drm_device *dev)
2724 {
2725         struct drm_i915_private *dev_priv = dev->dev_private;
2726
2727         if (I915_READ(PWRCTXA)) {
2728                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
2729                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
2730                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
2731                          50);
2732
2733                 I915_WRITE(PWRCTXA, 0);
2734                 POSTING_READ(PWRCTXA);
2735
2736                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2737                 POSTING_READ(RSTDBYCTL);
2738         }
2739 }
2740
2741 static int ironlake_setup_rc6(struct drm_device *dev)
2742 {
2743         struct drm_i915_private *dev_priv = dev->dev_private;
2744
2745         if (dev_priv->ips.renderctx == NULL)
2746                 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
2747         if (!dev_priv->ips.renderctx)
2748                 return -ENOMEM;
2749
2750         if (dev_priv->ips.pwrctx == NULL)
2751                 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
2752         if (!dev_priv->ips.pwrctx) {
2753                 ironlake_teardown_rc6(dev);
2754                 return -ENOMEM;
2755         }
2756
2757         return 0;
2758 }
2759
2760 static void ironlake_enable_rc6(struct drm_device *dev)
2761 {
2762         struct drm_i915_private *dev_priv = dev->dev_private;
2763         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
2764         bool was_interruptible;
2765         int ret;
2766
2767         /* rc6 disabled by default due to repeated reports of hanging during
2768          * boot and resume.
2769          */
2770         if (!intel_enable_rc6(dev))
2771                 return;
2772
2773         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2774
2775         ret = ironlake_setup_rc6(dev);
2776         if (ret)
2777                 return;
2778
2779         was_interruptible = dev_priv->mm.interruptible;
2780         dev_priv->mm.interruptible = false;
2781
2782         /*
2783          * GPU can automatically power down the render unit if given a page
2784          * to save state.
2785          */
2786         ret = intel_ring_begin(ring, 6);
2787         if (ret) {
2788                 ironlake_teardown_rc6(dev);
2789                 dev_priv->mm.interruptible = was_interruptible;
2790                 return;
2791         }
2792
2793         intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
2794         intel_ring_emit(ring, MI_SET_CONTEXT);
2795         intel_ring_emit(ring, dev_priv->ips.renderctx->gtt_offset |
2796                         MI_MM_SPACE_GTT |
2797                         MI_SAVE_EXT_STATE_EN |
2798                         MI_RESTORE_EXT_STATE_EN |
2799                         MI_RESTORE_INHIBIT);
2800         intel_ring_emit(ring, MI_SUSPEND_FLUSH);
2801         intel_ring_emit(ring, MI_NOOP);
2802         intel_ring_emit(ring, MI_FLUSH);
2803         intel_ring_advance(ring);
2804
2805         /*
2806          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
2807          * does an implicit flush, combined with MI_FLUSH above, it should be
2808          * safe to assume that renderctx is valid
2809          */
2810         ret = intel_ring_idle(ring);
2811         dev_priv->mm.interruptible = was_interruptible;
2812         if (ret) {
2813                 DRM_ERROR("failed to enable ironlake power power savings\n");
2814                 ironlake_teardown_rc6(dev);
2815                 return;
2816         }
2817
2818         I915_WRITE(PWRCTXA, dev_priv->ips.pwrctx->gtt_offset | PWRCTX_EN);
2819         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2820 }
2821
2822 static unsigned long intel_pxfreq(u32 vidfreq)
2823 {
2824         unsigned long freq;
2825         int div = (vidfreq & 0x3f0000) >> 16;
2826         int post = (vidfreq & 0x3000) >> 12;
2827         int pre = (vidfreq & 0x7);
2828
2829         if (!pre)
2830                 return 0;
2831
2832         freq = ((div * 133333) / ((1<<post) * pre));
2833
2834         return freq;
2835 }
2836
2837 static const struct cparams {
2838         u16 i;
2839         u16 t;
2840         u16 m;
2841         u16 c;
2842 } cparams[] = {
2843         { 1, 1333, 301, 28664 },
2844         { 1, 1066, 294, 24460 },
2845         { 1, 800, 294, 25192 },
2846         { 0, 1333, 276, 27605 },
2847         { 0, 1066, 276, 27605 },
2848         { 0, 800, 231, 23784 },
2849 };
2850
2851 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
2852 {
2853         u64 total_count, diff, ret;
2854         u32 count1, count2, count3, m = 0, c = 0;
2855         unsigned long now = jiffies_to_msecs(jiffies), diff1;
2856         int i;
2857
2858         assert_spin_locked(&mchdev_lock);
2859
2860         diff1 = now - dev_priv->ips.last_time1;
2861
2862         /* Prevent division-by-zero if we are asking too fast.
2863          * Also, we don't get interesting results if we are polling
2864          * faster than once in 10ms, so just return the saved value
2865          * in such cases.
2866          */
2867         if (diff1 <= 10)
2868                 return dev_priv->ips.chipset_power;
2869
2870         count1 = I915_READ(DMIEC);
2871         count2 = I915_READ(DDREC);
2872         count3 = I915_READ(CSIEC);
2873
2874         total_count = count1 + count2 + count3;
2875
2876         /* FIXME: handle per-counter overflow */
2877         if (total_count < dev_priv->ips.last_count1) {
2878                 diff = ~0UL - dev_priv->ips.last_count1;
2879                 diff += total_count;
2880         } else {
2881                 diff = total_count - dev_priv->ips.last_count1;
2882         }
2883
2884         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
2885                 if (cparams[i].i == dev_priv->ips.c_m &&
2886                     cparams[i].t == dev_priv->ips.r_t) {
2887                         m = cparams[i].m;
2888                         c = cparams[i].c;
2889                         break;
2890                 }
2891         }
2892
2893         diff = div_u64(diff, diff1);
2894         ret = ((m * diff) + c);
2895         ret = div_u64(ret, 10);
2896
2897         dev_priv->ips.last_count1 = total_count;
2898         dev_priv->ips.last_time1 = now;
2899
2900         dev_priv->ips.chipset_power = ret;
2901
2902         return ret;
2903 }
2904
2905 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
2906 {
2907         unsigned long val;
2908
2909         if (dev_priv->info->gen != 5)
2910                 return 0;
2911
2912         spin_lock_irq(&mchdev_lock);
2913
2914         val = __i915_chipset_val(dev_priv);
2915
2916         spin_unlock_irq(&mchdev_lock);
2917
2918         return val;
2919 }
2920
2921 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
2922 {
2923         unsigned long m, x, b;
2924         u32 tsfs;
2925
2926         tsfs = I915_READ(TSFS);
2927
2928         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
2929         x = I915_READ8(TR1);
2930
2931         b = tsfs & TSFS_INTR_MASK;
2932
2933         return ((m * x) / 127) - b;
2934 }
2935
2936 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
2937 {
2938         static const struct v_table {
2939                 u16 vd; /* in .1 mil */
2940                 u16 vm; /* in .1 mil */
2941         } v_table[] = {
2942                 { 0, 0, },
2943                 { 375, 0, },
2944                 { 500, 0, },
2945                 { 625, 0, },
2946                 { 750, 0, },
2947                 { 875, 0, },
2948                 { 1000, 0, },
2949                 { 1125, 0, },
2950                 { 4125, 3000, },
2951                 { 4125, 3000, },
2952                 { 4125, 3000, },
2953                 { 4125, 3000, },
2954                 { 4125, 3000, },
2955                 { 4125, 3000, },
2956                 { 4125, 3000, },
2957                 { 4125, 3000, },
2958                 { 4125, 3000, },
2959                 { 4125, 3000, },
2960                 { 4125, 3000, },
2961                 { 4125, 3000, },
2962                 { 4125, 3000, },
2963                 { 4125, 3000, },
2964                 { 4125, 3000, },
2965                 { 4125, 3000, },
2966                 { 4125, 3000, },
2967                 { 4125, 3000, },
2968                 { 4125, 3000, },
2969                 { 4125, 3000, },
2970                 { 4125, 3000, },
2971                 { 4125, 3000, },
2972                 { 4125, 3000, },
2973                 { 4125, 3000, },
2974                 { 4250, 3125, },
2975                 { 4375, 3250, },
2976                 { 4500, 3375, },
2977                 { 4625, 3500, },
2978                 { 4750, 3625, },
2979                 { 4875, 3750, },
2980                 { 5000, 3875, },
2981                 { 5125, 4000, },
2982                 { 5250, 4125, },
2983                 { 5375, 4250, },
2984                 { 5500, 4375, },
2985                 { 5625, 4500, },
2986                 { 5750, 4625, },
2987                 { 5875, 4750, },
2988                 { 6000, 4875, },
2989                 { 6125, 5000, },
2990                 { 6250, 5125, },
2991                 { 6375, 5250, },
2992                 { 6500, 5375, },
2993                 { 6625, 5500, },
2994                 { 6750, 5625, },
2995                 { 6875, 5750, },
2996                 { 7000, 5875, },
2997                 { 7125, 6000, },
2998                 { 7250, 6125, },
2999                 { 7375, 6250, },
3000                 { 7500, 6375, },
3001                 { 7625, 6500, },
3002                 { 7750, 6625, },
3003                 { 7875, 6750, },
3004                 { 8000, 6875, },
3005                 { 8125, 7000, },
3006                 { 8250, 7125, },
3007                 { 8375, 7250, },
3008                 { 8500, 7375, },
3009                 { 8625, 7500, },
3010                 { 8750, 7625, },
3011                 { 8875, 7750, },
3012                 { 9000, 7875, },
3013                 { 9125, 8000, },
3014                 { 9250, 8125, },
3015                 { 9375, 8250, },
3016                 { 9500, 8375, },
3017                 { 9625, 8500, },
3018                 { 9750, 8625, },
3019                 { 9875, 8750, },
3020                 { 10000, 8875, },
3021                 { 10125, 9000, },
3022                 { 10250, 9125, },
3023                 { 10375, 9250, },
3024                 { 10500, 9375, },
3025                 { 10625, 9500, },
3026                 { 10750, 9625, },
3027                 { 10875, 9750, },
3028                 { 11000, 9875, },
3029                 { 11125, 10000, },
3030                 { 11250, 10125, },
3031                 { 11375, 10250, },
3032                 { 11500, 10375, },
3033                 { 11625, 10500, },
3034                 { 11750, 10625, },
3035                 { 11875, 10750, },
3036                 { 12000, 10875, },
3037                 { 12125, 11000, },
3038                 { 12250, 11125, },
3039                 { 12375, 11250, },
3040                 { 12500, 11375, },
3041                 { 12625, 11500, },
3042                 { 12750, 11625, },
3043                 { 12875, 11750, },
3044                 { 13000, 11875, },
3045                 { 13125, 12000, },
3046                 { 13250, 12125, },
3047                 { 13375, 12250, },
3048                 { 13500, 12375, },
3049                 { 13625, 12500, },
3050                 { 13750, 12625, },
3051                 { 13875, 12750, },
3052                 { 14000, 12875, },
3053                 { 14125, 13000, },
3054                 { 14250, 13125, },
3055                 { 14375, 13250, },
3056                 { 14500, 13375, },
3057                 { 14625, 13500, },
3058                 { 14750, 13625, },
3059                 { 14875, 13750, },
3060                 { 15000, 13875, },
3061                 { 15125, 14000, },
3062                 { 15250, 14125, },
3063                 { 15375, 14250, },
3064                 { 15500, 14375, },
3065                 { 15625, 14500, },
3066                 { 15750, 14625, },
3067                 { 15875, 14750, },
3068                 { 16000, 14875, },
3069                 { 16125, 15000, },
3070         };
3071         if (dev_priv->info->is_mobile)
3072                 return v_table[pxvid].vm;
3073         else
3074                 return v_table[pxvid].vd;
3075 }
3076
3077 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
3078 {
3079         struct timespec now, diff1;
3080         u64 diff;
3081         unsigned long diffms;
3082         u32 count;
3083
3084         assert_spin_locked(&mchdev_lock);
3085
3086         getrawmonotonic(&now);
3087         diff1 = timespec_sub(now, dev_priv->ips.last_time2);
3088
3089         /* Don't divide by 0 */
3090         diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
3091         if (!diffms)
3092                 return;
3093
3094         count = I915_READ(GFXEC);
3095
3096         if (count < dev_priv->ips.last_count2) {
3097                 diff = ~0UL - dev_priv->ips.last_count2;
3098                 diff += count;
3099         } else {
3100                 diff = count - dev_priv->ips.last_count2;
3101         }
3102
3103         dev_priv->ips.last_count2 = count;
3104         dev_priv->ips.last_time2 = now;
3105
3106         /* More magic constants... */
3107         diff = diff * 1181;
3108         diff = div_u64(diff, diffms * 10);
3109         dev_priv->ips.gfx_power = diff;
3110 }
3111
3112 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
3113 {
3114         if (dev_priv->info->gen != 5)
3115                 return;
3116
3117         spin_lock_irq(&mchdev_lock);
3118
3119         __i915_update_gfx_val(dev_priv);
3120
3121         spin_unlock_irq(&mchdev_lock);
3122 }
3123
3124 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
3125 {
3126         unsigned long t, corr, state1, corr2, state2;
3127         u32 pxvid, ext_v;
3128
3129         assert_spin_locked(&mchdev_lock);
3130
3131         pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
3132         pxvid = (pxvid >> 24) & 0x7f;
3133         ext_v = pvid_to_extvid(dev_priv, pxvid);
3134
3135         state1 = ext_v;
3136
3137         t = i915_mch_val(dev_priv);
3138
3139         /* Revel in the empirically derived constants */
3140
3141         /* Correction factor in 1/100000 units */
3142         if (t > 80)
3143                 corr = ((t * 2349) + 135940);
3144         else if (t >= 50)
3145                 corr = ((t * 964) + 29317);
3146         else /* < 50 */
3147                 corr = ((t * 301) + 1004);
3148
3149         corr = corr * ((150142 * state1) / 10000 - 78642);
3150         corr /= 100000;
3151         corr2 = (corr * dev_priv->ips.corr);
3152
3153         state2 = (corr2 * state1) / 10000;
3154         state2 /= 100; /* convert to mW */
3155
3156         __i915_update_gfx_val(dev_priv);
3157
3158         return dev_priv->ips.gfx_power + state2;
3159 }
3160
3161 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
3162 {
3163         unsigned long val;
3164
3165         if (dev_priv->info->gen != 5)
3166                 return 0;
3167
3168         spin_lock_irq(&mchdev_lock);
3169
3170         val = __i915_gfx_val(dev_priv);
3171
3172         spin_unlock_irq(&mchdev_lock);
3173
3174         return val;
3175 }
3176
3177 /**
3178  * i915_read_mch_val - return value for IPS use
3179  *
3180  * Calculate and return a value for the IPS driver to use when deciding whether
3181  * we have thermal and power headroom to increase CPU or GPU power budget.
3182  */
3183 unsigned long i915_read_mch_val(void)
3184 {
3185         struct drm_i915_private *dev_priv;
3186         unsigned long chipset_val, graphics_val, ret = 0;
3187
3188         spin_lock_irq(&mchdev_lock);
3189         if (!i915_mch_dev)
3190                 goto out_unlock;
3191         dev_priv = i915_mch_dev;
3192
3193         chipset_val = __i915_chipset_val(dev_priv);
3194         graphics_val = __i915_gfx_val(dev_priv);
3195
3196         ret = chipset_val + graphics_val;
3197
3198 out_unlock:
3199         spin_unlock_irq(&mchdev_lock);
3200
3201         return ret;
3202 }
3203 EXPORT_SYMBOL_GPL(i915_read_mch_val);
3204
3205 /**
3206  * i915_gpu_raise - raise GPU frequency limit
3207  *
3208  * Raise the limit; IPS indicates we have thermal headroom.
3209  */
3210 bool i915_gpu_raise(void)
3211 {
3212         struct drm_i915_private *dev_priv;
3213         bool ret = true;
3214
3215         spin_lock_irq(&mchdev_lock);
3216         if (!i915_mch_dev) {
3217                 ret = false;
3218                 goto out_unlock;
3219         }
3220         dev_priv = i915_mch_dev;
3221
3222         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
3223                 dev_priv->ips.max_delay--;
3224
3225 out_unlock:
3226         spin_unlock_irq(&mchdev_lock);
3227
3228         return ret;
3229 }
3230 EXPORT_SYMBOL_GPL(i915_gpu_raise);
3231
3232 /**
3233  * i915_gpu_lower - lower GPU frequency limit
3234  *
3235  * IPS indicates we're close to a thermal limit, so throttle back the GPU
3236  * frequency maximum.
3237  */
3238 bool i915_gpu_lower(void)
3239 {
3240         struct drm_i915_private *dev_priv;
3241         bool ret = true;
3242
3243         spin_lock_irq(&mchdev_lock);
3244         if (!i915_mch_dev) {
3245                 ret = false;
3246                 goto out_unlock;
3247         }
3248         dev_priv = i915_mch_dev;
3249
3250         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
3251                 dev_priv->ips.max_delay++;
3252
3253 out_unlock:
3254         spin_unlock_irq(&mchdev_lock);
3255
3256         return ret;
3257 }
3258 EXPORT_SYMBOL_GPL(i915_gpu_lower);
3259
3260 /**
3261  * i915_gpu_busy - indicate GPU business to IPS
3262  *
3263  * Tell the IPS driver whether or not the GPU is busy.
3264  */
3265 bool i915_gpu_busy(void)
3266 {
3267         struct drm_i915_private *dev_priv;
3268         struct intel_ring_buffer *ring;
3269         bool ret = false;
3270         int i;
3271
3272         spin_lock_irq(&mchdev_lock);
3273         if (!i915_mch_dev)
3274                 goto out_unlock;
3275         dev_priv = i915_mch_dev;
3276
3277         for_each_ring(ring, dev_priv, i)
3278                 ret |= !list_empty(&ring->request_list);
3279
3280 out_unlock:
3281         spin_unlock_irq(&mchdev_lock);
3282
3283         return ret;
3284 }
3285 EXPORT_SYMBOL_GPL(i915_gpu_busy);
3286
3287 /**
3288  * i915_gpu_turbo_disable - disable graphics turbo
3289  *
3290  * Disable graphics turbo by resetting the max frequency and setting the
3291  * current frequency to the default.
3292  */
3293 bool i915_gpu_turbo_disable(void)
3294 {
3295         struct drm_i915_private *dev_priv;
3296         bool ret = true;
3297
3298         spin_lock_irq(&mchdev_lock);
3299         if (!i915_mch_dev) {
3300                 ret = false;
3301                 goto out_unlock;
3302         }
3303         dev_priv = i915_mch_dev;
3304
3305         dev_priv->ips.max_delay = dev_priv->ips.fstart;
3306
3307         if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
3308                 ret = false;
3309
3310 out_unlock:
3311         spin_unlock_irq(&mchdev_lock);
3312
3313         return ret;
3314 }
3315 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
3316
3317 /**
3318  * Tells the intel_ips driver that the i915 driver is now loaded, if
3319  * IPS got loaded first.
3320  *
3321  * This awkward dance is so that neither module has to depend on the
3322  * other in order for IPS to do the appropriate communication of
3323  * GPU turbo limits to i915.
3324  */
3325 static void
3326 ips_ping_for_i915_load(void)
3327 {
3328         void (*link)(void);
3329
3330         link = symbol_get(ips_link_to_i915_driver);
3331         if (link) {
3332                 link();
3333                 symbol_put(ips_link_to_i915_driver);
3334         }
3335 }
3336
3337 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
3338 {
3339         /* We only register the i915 ips part with intel-ips once everything is
3340          * set up, to avoid intel-ips sneaking in and reading bogus values. */
3341         spin_lock_irq(&mchdev_lock);
3342         i915_mch_dev = dev_priv;
3343         spin_unlock_irq(&mchdev_lock);
3344
3345         ips_ping_for_i915_load();
3346 }
3347
3348 void intel_gpu_ips_teardown(void)
3349 {
3350         spin_lock_irq(&mchdev_lock);
3351         i915_mch_dev = NULL;
3352         spin_unlock_irq(&mchdev_lock);
3353 }
3354 static void intel_init_emon(struct drm_device *dev)
3355 {
3356         struct drm_i915_private *dev_priv = dev->dev_private;
3357         u32 lcfuse;
3358         u8 pxw[16];
3359         int i;
3360
3361         /* Disable to program */
3362         I915_WRITE(ECR, 0);
3363         POSTING_READ(ECR);
3364
3365         /* Program energy weights for various events */
3366         I915_WRITE(SDEW, 0x15040d00);
3367         I915_WRITE(CSIEW0, 0x007f0000);
3368         I915_WRITE(CSIEW1, 0x1e220004);
3369         I915_WRITE(CSIEW2, 0x04000004);
3370
3371         for (i = 0; i < 5; i++)
3372                 I915_WRITE(PEW + (i * 4), 0);
3373         for (i = 0; i < 3; i++)
3374                 I915_WRITE(DEW + (i * 4), 0);
3375
3376         /* Program P-state weights to account for frequency power adjustment */
3377         for (i = 0; i < 16; i++) {
3378                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
3379                 unsigned long freq = intel_pxfreq(pxvidfreq);
3380                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
3381                         PXVFREQ_PX_SHIFT;
3382                 unsigned long val;
3383
3384                 val = vid * vid;
3385                 val *= (freq / 1000);
3386                 val *= 255;
3387                 val /= (127*127*900);
3388                 if (val > 0xff)
3389                         DRM_ERROR("bad pxval: %ld\n", val);
3390                 pxw[i] = val;
3391         }
3392         /* Render standby states get 0 weight */
3393         pxw[14] = 0;
3394         pxw[15] = 0;
3395
3396         for (i = 0; i < 4; i++) {
3397                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
3398                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
3399                 I915_WRITE(PXW + (i * 4), val);
3400         }
3401
3402         /* Adjust magic regs to magic values (more experimental results) */
3403         I915_WRITE(OGW0, 0);
3404         I915_WRITE(OGW1, 0);
3405         I915_WRITE(EG0, 0x00007f00);
3406         I915_WRITE(EG1, 0x0000000e);
3407         I915_WRITE(EG2, 0x000e0000);
3408         I915_WRITE(EG3, 0x68000300);
3409         I915_WRITE(EG4, 0x42000000);
3410         I915_WRITE(EG5, 0x00140031);
3411         I915_WRITE(EG6, 0);
3412         I915_WRITE(EG7, 0);
3413
3414         for (i = 0; i < 8; i++)
3415                 I915_WRITE(PXWL + (i * 4), 0);
3416
3417         /* Enable PMON + select events */
3418         I915_WRITE(ECR, 0x80000019);
3419
3420         lcfuse = I915_READ(LCFUSE02);
3421
3422         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
3423 }
3424
3425 void intel_disable_gt_powersave(struct drm_device *dev)
3426 {
3427         struct drm_i915_private *dev_priv = dev->dev_private;
3428
3429         if (IS_IRONLAKE_M(dev)) {
3430                 ironlake_disable_drps(dev);
3431                 ironlake_disable_rc6(dev);
3432         } else if (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev)) {
3433                 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
3434                 mutex_lock(&dev_priv->rps.hw_lock);
3435                 gen6_disable_rps(dev);
3436                 mutex_unlock(&dev_priv->rps.hw_lock);
3437         }
3438 }
3439
3440 static void intel_gen6_powersave_work(struct work_struct *work)
3441 {
3442         struct drm_i915_private *dev_priv =
3443                 container_of(work, struct drm_i915_private,
3444                              rps.delayed_resume_work.work);
3445         struct drm_device *dev = dev_priv->dev;
3446
3447         mutex_lock(&dev_priv->rps.hw_lock);
3448         gen6_enable_rps(dev);
3449         gen6_update_ring_freq(dev);
3450         mutex_unlock(&dev_priv->rps.hw_lock);
3451 }
3452
3453 void intel_enable_gt_powersave(struct drm_device *dev)
3454 {
3455         struct drm_i915_private *dev_priv = dev->dev_private;
3456
3457         if (IS_IRONLAKE_M(dev)) {
3458                 ironlake_enable_drps(dev);
3459                 ironlake_enable_rc6(dev);
3460                 intel_init_emon(dev);
3461         } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
3462                 /*
3463                  * PCU communication is slow and this doesn't need to be
3464                  * done at any specific time, so do this out of our fast path
3465                  * to make resume and init faster.
3466                  */
3467                 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
3468                                       round_jiffies_up_relative(HZ));
3469         }
3470 }
3471
3472 static void ibx_init_clock_gating(struct drm_device *dev)
3473 {
3474         struct drm_i915_private *dev_priv = dev->dev_private;
3475
3476         /*
3477          * On Ibex Peak and Cougar Point, we need to disable clock
3478          * gating for the panel power sequencer or it will fail to
3479          * start up when no ports are active.
3480          */
3481         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
3482 }
3483
3484 static void ironlake_init_clock_gating(struct drm_device *dev)
3485 {
3486         struct drm_i915_private *dev_priv = dev->dev_private;
3487         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
3488
3489         /* Required for FBC */
3490         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
3491                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
3492                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
3493
3494         I915_WRITE(PCH_3DCGDIS0,
3495                    MARIUNIT_CLOCK_GATE_DISABLE |
3496                    SVSMUNIT_CLOCK_GATE_DISABLE);
3497         I915_WRITE(PCH_3DCGDIS1,
3498                    VFMUNIT_CLOCK_GATE_DISABLE);
3499
3500         /*
3501          * According to the spec the following bits should be set in
3502          * order to enable memory self-refresh
3503          * The bit 22/21 of 0x42004
3504          * The bit 5 of 0x42020
3505          * The bit 15 of 0x45000
3506          */
3507         I915_WRITE(ILK_DISPLAY_CHICKEN2,
3508                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
3509                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
3510         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
3511         I915_WRITE(DISP_ARB_CTL,
3512                    (I915_READ(DISP_ARB_CTL) |
3513                     DISP_FBC_WM_DIS));
3514         I915_WRITE(WM3_LP_ILK, 0);
3515         I915_WRITE(WM2_LP_ILK, 0);
3516         I915_WRITE(WM1_LP_ILK, 0);
3517
3518         /*
3519          * Based on the document from hardware guys the following bits
3520          * should be set unconditionally in order to enable FBC.
3521          * The bit 22 of 0x42000
3522          * The bit 22 of 0x42004
3523          * The bit 7,8,9 of 0x42020.
3524          */
3525         if (IS_IRONLAKE_M(dev)) {
3526                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
3527                            I915_READ(ILK_DISPLAY_CHICKEN1) |
3528                            ILK_FBCQ_DIS);
3529                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3530                            I915_READ(ILK_DISPLAY_CHICKEN2) |
3531                            ILK_DPARB_GATE);
3532         }
3533
3534         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
3535
3536         I915_WRITE(ILK_DISPLAY_CHICKEN2,
3537                    I915_READ(ILK_DISPLAY_CHICKEN2) |
3538                    ILK_ELPIN_409_SELECT);
3539         I915_WRITE(_3D_CHICKEN2,
3540                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
3541                    _3D_CHICKEN2_WM_READ_PIPELINED);
3542
3543         /* WaDisableRenderCachePipelinedFlush */
3544         I915_WRITE(CACHE_MODE_0,
3545                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3546
3547         ibx_init_clock_gating(dev);
3548 }
3549
3550 static void cpt_init_clock_gating(struct drm_device *dev)
3551 {
3552         struct drm_i915_private *dev_priv = dev->dev_private;
3553         int pipe;
3554
3555         /*
3556          * On Ibex Peak and Cougar Point, we need to disable clock
3557          * gating for the panel power sequencer or it will fail to
3558          * start up when no ports are active.
3559          */
3560         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
3561         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
3562                    DPLS_EDP_PPS_FIX_DIS);
3563         /* The below fixes the weird display corruption, a few pixels shifted
3564          * downward, on (only) LVDS of some HP laptops with IVY.
3565          */
3566         for_each_pipe(pipe)
3567                 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_CHICKEN2_TIMING_OVERRIDE);
3568         /* WADP0ClockGatingDisable */
3569         for_each_pipe(pipe) {
3570                 I915_WRITE(TRANS_CHICKEN1(pipe),
3571                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
3572         }
3573 }
3574
3575 static void gen6_init_clock_gating(struct drm_device *dev)
3576 {
3577         struct drm_i915_private *dev_priv = dev->dev_private;
3578         int pipe;
3579         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
3580
3581         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
3582
3583         I915_WRITE(ILK_DISPLAY_CHICKEN2,
3584                    I915_READ(ILK_DISPLAY_CHICKEN2) |
3585                    ILK_ELPIN_409_SELECT);
3586
3587         I915_WRITE(WM3_LP_ILK, 0);
3588         I915_WRITE(WM2_LP_ILK, 0);
3589         I915_WRITE(WM1_LP_ILK, 0);
3590
3591         I915_WRITE(CACHE_MODE_0,
3592                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
3593
3594         I915_WRITE(GEN6_UCGCTL1,
3595                    I915_READ(GEN6_UCGCTL1) |
3596                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
3597                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
3598
3599         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3600          * gating disable must be set.  Failure to set it results in
3601          * flickering pixels due to Z write ordering failures after
3602          * some amount of runtime in the Mesa "fire" demo, and Unigine
3603          * Sanctuary and Tropics, and apparently anything else with
3604          * alpha test or pixel discard.
3605          *
3606          * According to the spec, bit 11 (RCCUNIT) must also be set,
3607          * but we didn't debug actual testcases to find it out.
3608          *
3609          * Also apply WaDisableVDSUnitClockGating and
3610          * WaDisableRCPBUnitClockGating.
3611          */
3612         I915_WRITE(GEN6_UCGCTL2,
3613                    GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
3614                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
3615                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3616
3617         /* Bspec says we need to always set all mask bits. */
3618         I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
3619                    _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
3620
3621         /*
3622          * According to the spec the following bits should be
3623          * set in order to enable memory self-refresh and fbc:
3624          * The bit21 and bit22 of 0x42000
3625          * The bit21 and bit22 of 0x42004
3626          * The bit5 and bit7 of 0x42020
3627          * The bit14 of 0x70180
3628          * The bit14 of 0x71180
3629          */
3630         I915_WRITE(ILK_DISPLAY_CHICKEN1,
3631                    I915_READ(ILK_DISPLAY_CHICKEN1) |
3632                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
3633         I915_WRITE(ILK_DISPLAY_CHICKEN2,
3634                    I915_READ(ILK_DISPLAY_CHICKEN2) |
3635                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
3636         I915_WRITE(ILK_DSPCLK_GATE_D,
3637                    I915_READ(ILK_DSPCLK_GATE_D) |
3638                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
3639                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
3640
3641         /* WaMbcDriverBootEnable */
3642         I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3643                    GEN6_MBCTL_ENABLE_BOOT_FETCH);
3644
3645         for_each_pipe(pipe) {
3646                 I915_WRITE(DSPCNTR(pipe),
3647                            I915_READ(DSPCNTR(pipe)) |
3648                            DISPPLANE_TRICKLE_FEED_DISABLE);
3649                 intel_flush_display_plane(dev_priv, pipe);
3650         }
3651
3652         /* The default value should be 0x200 according to docs, but the two
3653          * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
3654         I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
3655         I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
3656
3657         cpt_init_clock_gating(dev);
3658 }
3659
3660 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
3661 {
3662         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
3663
3664         reg &= ~GEN7_FF_SCHED_MASK;
3665         reg |= GEN7_FF_TS_SCHED_HW;
3666         reg |= GEN7_FF_VS_SCHED_HW;
3667         reg |= GEN7_FF_DS_SCHED_HW;
3668
3669         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
3670 }
3671
3672 static void lpt_init_clock_gating(struct drm_device *dev)
3673 {
3674         struct drm_i915_private *dev_priv = dev->dev_private;
3675
3676         /*
3677          * TODO: this bit should only be enabled when really needed, then
3678          * disabled when not needed anymore in order to save power.
3679          */
3680         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
3681                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
3682                            I915_READ(SOUTH_DSPCLK_GATE_D) |
3683                            PCH_LP_PARTITION_LEVEL_DISABLE);
3684 }
3685
3686 static void haswell_init_clock_gating(struct drm_device *dev)
3687 {
3688         struct drm_i915_private *dev_priv = dev->dev_private;
3689         int pipe;
3690
3691         I915_WRITE(WM3_LP_ILK, 0);
3692         I915_WRITE(WM2_LP_ILK, 0);
3693         I915_WRITE(WM1_LP_ILK, 0);
3694
3695         /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3696          * This implements the WaDisableRCZUnitClockGating workaround.
3697          */
3698         I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
3699
3700         /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3701         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3702                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
3703
3704         /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3705         I915_WRITE(GEN7_L3CNTLREG1,
3706                         GEN7_WA_FOR_GEN7_L3_CONTROL);
3707         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
3708                         GEN7_WA_L3_CHICKEN_MODE);
3709
3710         /* This is required by WaCatErrorRejectionIssue */
3711         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
3712                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
3713                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
3714
3715         for_each_pipe(pipe) {
3716                 I915_WRITE(DSPCNTR(pipe),
3717                            I915_READ(DSPCNTR(pipe)) |
3718                            DISPPLANE_TRICKLE_FEED_DISABLE);
3719                 intel_flush_display_plane(dev_priv, pipe);
3720         }
3721
3722         gen7_setup_fixed_func_scheduler(dev_priv);
3723
3724         /* WaDisable4x2SubspanOptimization */
3725         I915_WRITE(CACHE_MODE_1,
3726                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
3727
3728         /* WaMbcDriverBootEnable */
3729         I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3730                    GEN6_MBCTL_ENABLE_BOOT_FETCH);
3731
3732         /* XXX: This is a workaround for early silicon revisions and should be
3733          * removed later.
3734          */
3735         I915_WRITE(WM_DBG,
3736                         I915_READ(WM_DBG) |
3737                         WM_DBG_DISALLOW_MULTIPLE_LP |
3738                         WM_DBG_DISALLOW_SPRITE |
3739                         WM_DBG_DISALLOW_MAXFIFO);
3740
3741         lpt_init_clock_gating(dev);
3742 }
3743
3744 static void ivybridge_init_clock_gating(struct drm_device *dev)
3745 {
3746         struct drm_i915_private *dev_priv = dev->dev_private;
3747         int pipe;
3748         uint32_t snpcr;
3749
3750         I915_WRITE(WM3_LP_ILK, 0);
3751         I915_WRITE(WM2_LP_ILK, 0);
3752         I915_WRITE(WM1_LP_ILK, 0);
3753
3754         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
3755
3756         /* WaDisableEarlyCull */
3757         I915_WRITE(_3D_CHICKEN3,
3758                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
3759
3760         /* WaDisableBackToBackFlipFix */
3761         I915_WRITE(IVB_CHICKEN3,
3762                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
3763                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
3764
3765         /* WaDisablePSDDualDispatchEnable */
3766         if (IS_IVB_GT1(dev))
3767                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
3768                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
3769         else
3770                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
3771                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
3772
3773         /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3774         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3775                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
3776
3777         /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3778         I915_WRITE(GEN7_L3CNTLREG1,
3779                         GEN7_WA_FOR_GEN7_L3_CONTROL);
3780         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
3781                    GEN7_WA_L3_CHICKEN_MODE);
3782         if (IS_IVB_GT1(dev))
3783                 I915_WRITE(GEN7_ROW_CHICKEN2,
3784                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
3785         else
3786                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
3787                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
3788
3789
3790         /* WaForceL3Serialization */
3791         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
3792                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
3793
3794         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3795          * gating disable must be set.  Failure to set it results in
3796          * flickering pixels due to Z write ordering failures after
3797          * some amount of runtime in the Mesa "fire" demo, and Unigine
3798          * Sanctuary and Tropics, and apparently anything else with
3799          * alpha test or pixel discard.
3800          *
3801          * According to the spec, bit 11 (RCCUNIT) must also be set,
3802          * but we didn't debug actual testcases to find it out.
3803          *
3804          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3805          * This implements the WaDisableRCZUnitClockGating workaround.
3806          */
3807         I915_WRITE(GEN6_UCGCTL2,
3808                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
3809                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3810
3811         /* This is required by WaCatErrorRejectionIssue */
3812         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
3813                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
3814                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
3815
3816         for_each_pipe(pipe) {
3817                 I915_WRITE(DSPCNTR(pipe),
3818                            I915_READ(DSPCNTR(pipe)) |
3819                            DISPPLANE_TRICKLE_FEED_DISABLE);
3820                 intel_flush_display_plane(dev_priv, pipe);
3821         }
3822
3823         /* WaMbcDriverBootEnable */
3824         I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3825                    GEN6_MBCTL_ENABLE_BOOT_FETCH);
3826
3827         gen7_setup_fixed_func_scheduler(dev_priv);
3828
3829         /* WaDisable4x2SubspanOptimization */
3830         I915_WRITE(CACHE_MODE_1,
3831                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
3832
3833         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3834         snpcr &= ~GEN6_MBC_SNPCR_MASK;
3835         snpcr |= GEN6_MBC_SNPCR_MED;
3836         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3837
3838         cpt_init_clock_gating(dev);
3839 }
3840
3841 static void valleyview_init_clock_gating(struct drm_device *dev)
3842 {
3843         struct drm_i915_private *dev_priv = dev->dev_private;
3844         int pipe;
3845
3846         I915_WRITE(WM3_LP_ILK, 0);
3847         I915_WRITE(WM2_LP_ILK, 0);
3848         I915_WRITE(WM1_LP_ILK, 0);
3849
3850         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
3851
3852         /* WaDisableEarlyCull */
3853         I915_WRITE(_3D_CHICKEN3,
3854                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
3855
3856         /* WaDisableBackToBackFlipFix */
3857         I915_WRITE(IVB_CHICKEN3,
3858                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
3859                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
3860
3861         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
3862                    _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
3863
3864         /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3865         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3866                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
3867
3868         /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3869         I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
3870         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
3871
3872         /* WaForceL3Serialization */
3873         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
3874                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
3875
3876         /* WaDisableDopClockGating */
3877         I915_WRITE(GEN7_ROW_CHICKEN2,
3878                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
3879
3880         /* WaForceL3Serialization */
3881         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
3882                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
3883
3884         /* This is required by WaCatErrorRejectionIssue */
3885         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
3886                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
3887                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
3888
3889         /* WaMbcDriverBootEnable */
3890         I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3891                    GEN6_MBCTL_ENABLE_BOOT_FETCH);
3892
3893
3894         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3895          * gating disable must be set.  Failure to set it results in
3896          * flickering pixels due to Z write ordering failures after
3897          * some amount of runtime in the Mesa "fire" demo, and Unigine
3898          * Sanctuary and Tropics, and apparently anything else with
3899          * alpha test or pixel discard.
3900          *
3901          * According to the spec, bit 11 (RCCUNIT) must also be set,
3902          * but we didn't debug actual testcases to find it out.
3903          *
3904          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3905          * This implements the WaDisableRCZUnitClockGating workaround.
3906          *
3907          * Also apply WaDisableVDSUnitClockGating and
3908          * WaDisableRCPBUnitClockGating.
3909          */
3910         I915_WRITE(GEN6_UCGCTL2,
3911                    GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
3912                    GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
3913                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
3914                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
3915                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3916
3917         I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
3918
3919         for_each_pipe(pipe) {
3920                 I915_WRITE(DSPCNTR(pipe),
3921                            I915_READ(DSPCNTR(pipe)) |
3922                            DISPPLANE_TRICKLE_FEED_DISABLE);
3923                 intel_flush_display_plane(dev_priv, pipe);
3924         }
3925
3926         I915_WRITE(CACHE_MODE_1,
3927                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
3928
3929         /*
3930          * On ValleyView, the GUnit needs to signal the GT
3931          * when flip and other events complete.  So enable
3932          * all the GUnit->GT interrupts here
3933          */
3934         I915_WRITE(VLV_DPFLIPSTAT, PIPEB_LINE_COMPARE_INT_EN |
3935                    PIPEB_HLINE_INT_EN | PIPEB_VBLANK_INT_EN |
3936                    SPRITED_FLIPDONE_INT_EN | SPRITEC_FLIPDONE_INT_EN |
3937                    PLANEB_FLIPDONE_INT_EN | PIPEA_LINE_COMPARE_INT_EN |
3938                    PIPEA_HLINE_INT_EN | PIPEA_VBLANK_INT_EN |
3939                    SPRITEB_FLIPDONE_INT_EN | SPRITEA_FLIPDONE_INT_EN |
3940                    PLANEA_FLIPDONE_INT_EN);
3941
3942         /*
3943          * WaDisableVLVClockGating_VBIIssue
3944          * Disable clock gating on th GCFG unit to prevent a delay
3945          * in the reporting of vblank events.
3946          */
3947         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
3948 }
3949
3950 static void g4x_init_clock_gating(struct drm_device *dev)
3951 {
3952         struct drm_i915_private *dev_priv = dev->dev_private;
3953         uint32_t dspclk_gate;
3954
3955         I915_WRITE(RENCLK_GATE_D1, 0);
3956         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
3957                    GS_UNIT_CLOCK_GATE_DISABLE |
3958                    CL_UNIT_CLOCK_GATE_DISABLE);
3959         I915_WRITE(RAMCLK_GATE_D, 0);
3960         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
3961                 OVRUNIT_CLOCK_GATE_DISABLE |
3962                 OVCUNIT_CLOCK_GATE_DISABLE;
3963         if (IS_GM45(dev))
3964                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
3965         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
3966
3967         /* WaDisableRenderCachePipelinedFlush */
3968         I915_WRITE(CACHE_MODE_0,
3969                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3970 }
3971
3972 static void crestline_init_clock_gating(struct drm_device *dev)
3973 {
3974         struct drm_i915_private *dev_priv = dev->dev_private;
3975
3976         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
3977         I915_WRITE(RENCLK_GATE_D2, 0);
3978         I915_WRITE(DSPCLK_GATE_D, 0);
3979         I915_WRITE(RAMCLK_GATE_D, 0);
3980         I915_WRITE16(DEUC, 0);
3981 }
3982
3983 static void broadwater_init_clock_gating(struct drm_device *dev)
3984 {
3985         struct drm_i915_private *dev_priv = dev->dev_private;
3986
3987         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
3988                    I965_RCC_CLOCK_GATE_DISABLE |
3989                    I965_RCPB_CLOCK_GATE_DISABLE |
3990                    I965_ISC_CLOCK_GATE_DISABLE |
3991                    I965_FBC_CLOCK_GATE_DISABLE);
3992         I915_WRITE(RENCLK_GATE_D2, 0);
3993 }
3994
3995 static void gen3_init_clock_gating(struct drm_device *dev)
3996 {
3997         struct drm_i915_private *dev_priv = dev->dev_private;
3998         u32 dstate = I915_READ(D_STATE);
3999
4000         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4001                 DSTATE_DOT_CLOCK_GATING;
4002         I915_WRITE(D_STATE, dstate);
4003
4004         if (IS_PINEVIEW(dev))
4005                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
4006
4007         /* IIR "flip pending" means done if this bit is set */
4008         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
4009 }
4010
4011 static void i85x_init_clock_gating(struct drm_device *dev)
4012 {
4013         struct drm_i915_private *dev_priv = dev->dev_private;
4014
4015         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4016 }
4017
4018 static void i830_init_clock_gating(struct drm_device *dev)
4019 {
4020         struct drm_i915_private *dev_priv = dev->dev_private;
4021
4022         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4023 }
4024
4025 void intel_init_clock_gating(struct drm_device *dev)
4026 {
4027         struct drm_i915_private *dev_priv = dev->dev_private;
4028
4029         dev_priv->display.init_clock_gating(dev);
4030 }
4031
4032 /* Starting with Haswell, we have different power wells for
4033  * different parts of the GPU. This attempts to enable them all.
4034  */
4035 void intel_init_power_wells(struct drm_device *dev)
4036 {
4037         struct drm_i915_private *dev_priv = dev->dev_private;
4038         unsigned long power_wells[] = {
4039                 HSW_PWR_WELL_CTL1,
4040                 HSW_PWR_WELL_CTL2,
4041                 HSW_PWR_WELL_CTL4
4042         };
4043         int i;
4044
4045         if (!IS_HASWELL(dev))
4046                 return;
4047
4048         mutex_lock(&dev->struct_mutex);
4049
4050         for (i = 0; i < ARRAY_SIZE(power_wells); i++) {
4051                 int well = I915_READ(power_wells[i]);
4052
4053                 if ((well & HSW_PWR_WELL_STATE) == 0) {
4054                         I915_WRITE(power_wells[i], well & HSW_PWR_WELL_ENABLE);
4055                         if (wait_for((I915_READ(power_wells[i]) & HSW_PWR_WELL_STATE), 20))
4056                                 DRM_ERROR("Error enabling power well %lx\n", power_wells[i]);
4057                 }
4058         }
4059
4060         mutex_unlock(&dev->struct_mutex);
4061 }
4062
4063 /* Set up chip specific power management-related functions */
4064 void intel_init_pm(struct drm_device *dev)
4065 {
4066         struct drm_i915_private *dev_priv = dev->dev_private;
4067
4068         if (I915_HAS_FBC(dev)) {
4069                 if (HAS_PCH_SPLIT(dev)) {
4070                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
4071                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
4072                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
4073                 } else if (IS_GM45(dev)) {
4074                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
4075                         dev_priv->display.enable_fbc = g4x_enable_fbc;
4076                         dev_priv->display.disable_fbc = g4x_disable_fbc;
4077                 } else if (IS_CRESTLINE(dev)) {
4078                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
4079                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
4080                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
4081                 }
4082                 /* 855GM needs testing */
4083         }
4084
4085         /* For cxsr */
4086         if (IS_PINEVIEW(dev))
4087                 i915_pineview_get_mem_freq(dev);
4088         else if (IS_GEN5(dev))
4089                 i915_ironlake_get_mem_freq(dev);
4090
4091         /* For FIFO watermark updates */
4092         if (HAS_PCH_SPLIT(dev)) {
4093                 if (IS_GEN5(dev)) {
4094                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
4095                                 dev_priv->display.update_wm = ironlake_update_wm;
4096                         else {
4097                                 DRM_DEBUG_KMS("Failed to get proper latency. "
4098                                               "Disable CxSR\n");
4099                                 dev_priv->display.update_wm = NULL;
4100                         }
4101                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
4102                 } else if (IS_GEN6(dev)) {
4103                         if (SNB_READ_WM0_LATENCY()) {
4104                                 dev_priv->display.update_wm = sandybridge_update_wm;
4105                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4106                         } else {
4107                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
4108                                               "Disable CxSR\n");
4109                                 dev_priv->display.update_wm = NULL;
4110                         }
4111                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
4112                 } else if (IS_IVYBRIDGE(dev)) {
4113                         /* FIXME: detect B0+ stepping and use auto training */
4114                         if (SNB_READ_WM0_LATENCY()) {
4115                                 dev_priv->display.update_wm = ivybridge_update_wm;
4116                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4117                         } else {
4118                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
4119                                               "Disable CxSR\n");
4120                                 dev_priv->display.update_wm = NULL;
4121                         }
4122                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
4123                 } else if (IS_HASWELL(dev)) {
4124                         if (SNB_READ_WM0_LATENCY()) {
4125                                 dev_priv->display.update_wm = sandybridge_update_wm;
4126                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4127                                 dev_priv->display.update_linetime_wm = haswell_update_linetime_wm;
4128                         } else {
4129                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
4130                                               "Disable CxSR\n");
4131                                 dev_priv->display.update_wm = NULL;
4132                         }
4133                         dev_priv->display.init_clock_gating = haswell_init_clock_gating;
4134                 } else
4135                         dev_priv->display.update_wm = NULL;
4136         } else if (IS_VALLEYVIEW(dev)) {
4137                 dev_priv->display.update_wm = valleyview_update_wm;
4138                 dev_priv->display.init_clock_gating =
4139                         valleyview_init_clock_gating;
4140         } else if (IS_PINEVIEW(dev)) {
4141                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
4142                                             dev_priv->is_ddr3,
4143                                             dev_priv->fsb_freq,
4144                                             dev_priv->mem_freq)) {
4145                         DRM_INFO("failed to find known CxSR latency "
4146                                  "(found ddr%s fsb freq %d, mem freq %d), "
4147                                  "disabling CxSR\n",
4148                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
4149                                  dev_priv->fsb_freq, dev_priv->mem_freq);
4150                         /* Disable CxSR and never update its watermark again */
4151                         pineview_disable_cxsr(dev);
4152                         dev_priv->display.update_wm = NULL;
4153                 } else
4154                         dev_priv->display.update_wm = pineview_update_wm;
4155                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
4156         } else if (IS_G4X(dev)) {
4157                 dev_priv->display.update_wm = g4x_update_wm;
4158                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
4159         } else if (IS_GEN4(dev)) {
4160                 dev_priv->display.update_wm = i965_update_wm;
4161                 if (IS_CRESTLINE(dev))
4162                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
4163                 else if (IS_BROADWATER(dev))
4164                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
4165         } else if (IS_GEN3(dev)) {
4166                 dev_priv->display.update_wm = i9xx_update_wm;
4167                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
4168                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
4169         } else if (IS_I865G(dev)) {
4170                 dev_priv->display.update_wm = i830_update_wm;
4171                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
4172                 dev_priv->display.get_fifo_size = i830_get_fifo_size;
4173         } else if (IS_I85X(dev)) {
4174                 dev_priv->display.update_wm = i9xx_update_wm;
4175                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4176                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
4177         } else {
4178                 dev_priv->display.update_wm = i830_update_wm;
4179                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
4180                 if (IS_845G(dev))
4181                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
4182                 else
4183                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
4184         }
4185 }
4186
4187 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
4188 {
4189         u32 gt_thread_status_mask;
4190
4191         if (IS_HASWELL(dev_priv->dev))
4192                 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW;
4193         else
4194                 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK;
4195
4196         /* w/a for a sporadic read returning 0 by waiting for the GT
4197          * thread to wake up.
4198          */
4199         if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))
4200                 DRM_ERROR("GT thread status wait timed out\n");
4201 }
4202
4203 static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
4204 {
4205         I915_WRITE_NOTRACE(FORCEWAKE, 0);
4206         POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4207 }
4208
4209 static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
4210 {
4211         u32 forcewake_ack;
4212
4213         if (IS_HASWELL(dev_priv->dev))
4214                 forcewake_ack = FORCEWAKE_ACK_HSW;
4215         else
4216                 forcewake_ack = FORCEWAKE_ACK;
4217
4218         if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1) == 0,
4219                             FORCEWAKE_ACK_TIMEOUT_MS))
4220                 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
4221
4222         I915_WRITE_NOTRACE(FORCEWAKE, FORCEWAKE_KERNEL);
4223         POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4224
4225         if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1),
4226                             FORCEWAKE_ACK_TIMEOUT_MS))
4227                 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
4228
4229         __gen6_gt_wait_for_thread_c0(dev_priv);
4230 }
4231
4232 static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
4233 {
4234         I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));
4235         POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4236 }
4237
4238 static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
4239 {
4240         u32 forcewake_ack;
4241
4242         if (IS_HASWELL(dev_priv->dev))
4243                 forcewake_ack = FORCEWAKE_ACK_HSW;
4244         else
4245                 forcewake_ack = FORCEWAKE_MT_ACK;
4246
4247         if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1) == 0,
4248                             FORCEWAKE_ACK_TIMEOUT_MS))
4249                 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
4250
4251         I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
4252         POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4253
4254         if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1),
4255                             FORCEWAKE_ACK_TIMEOUT_MS))
4256                 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
4257
4258         __gen6_gt_wait_for_thread_c0(dev_priv);
4259 }
4260
4261 /*
4262  * Generally this is called implicitly by the register read function. However,
4263  * if some sequence requires the GT to not power down then this function should
4264  * be called at the beginning of the sequence followed by a call to
4265  * gen6_gt_force_wake_put() at the end of the sequence.
4266  */
4267 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
4268 {
4269         unsigned long irqflags;
4270
4271         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
4272         if (dev_priv->forcewake_count++ == 0)
4273                 dev_priv->gt.force_wake_get(dev_priv);
4274         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
4275 }
4276
4277 void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
4278 {
4279         u32 gtfifodbg;
4280         gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
4281         if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
4282              "MMIO read or write has been dropped %x\n", gtfifodbg))
4283                 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
4284 }
4285
4286 static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
4287 {
4288         I915_WRITE_NOTRACE(FORCEWAKE, 0);
4289         /* gen6_gt_check_fifodbg doubles as the POSTING_READ */
4290         gen6_gt_check_fifodbg(dev_priv);
4291 }
4292
4293 static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
4294 {
4295         I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
4296         /* gen6_gt_check_fifodbg doubles as the POSTING_READ */
4297         gen6_gt_check_fifodbg(dev_priv);
4298 }
4299
4300 /*
4301  * see gen6_gt_force_wake_get()
4302  */
4303 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
4304 {
4305         unsigned long irqflags;
4306
4307         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
4308         if (--dev_priv->forcewake_count == 0)
4309                 dev_priv->gt.force_wake_put(dev_priv);
4310         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
4311 }
4312
4313 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
4314 {
4315         int ret = 0;
4316
4317         if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
4318                 int loop = 500;
4319                 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
4320                 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
4321                         udelay(10);
4322                         fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
4323                 }
4324                 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
4325                         ++ret;
4326                 dev_priv->gt_fifo_count = fifo;
4327         }
4328         dev_priv->gt_fifo_count--;
4329
4330         return ret;
4331 }
4332
4333 static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
4334 {
4335         I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(0xffff));
4336 }
4337
4338 static void vlv_force_wake_get(struct drm_i915_private *dev_priv)
4339 {
4340         if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0,
4341                             FORCEWAKE_ACK_TIMEOUT_MS))
4342                 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
4343
4344         I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
4345
4346         if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1),
4347                             FORCEWAKE_ACK_TIMEOUT_MS))
4348                 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
4349
4350         __gen6_gt_wait_for_thread_c0(dev_priv);
4351 }
4352
4353 static void vlv_force_wake_put(struct drm_i915_private *dev_priv)
4354 {
4355         I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
4356         /* The below doubles as a POSTING_READ */
4357         gen6_gt_check_fifodbg(dev_priv);
4358 }
4359
4360 void intel_gt_reset(struct drm_device *dev)
4361 {
4362         struct drm_i915_private *dev_priv = dev->dev_private;
4363
4364         if (IS_VALLEYVIEW(dev)) {
4365                 vlv_force_wake_reset(dev_priv);
4366         } else if (INTEL_INFO(dev)->gen >= 6) {
4367                 __gen6_gt_force_wake_reset(dev_priv);
4368                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4369                         __gen6_gt_force_wake_mt_reset(dev_priv);
4370         }
4371 }
4372
4373 void intel_gt_init(struct drm_device *dev)
4374 {
4375         struct drm_i915_private *dev_priv = dev->dev_private;
4376
4377         spin_lock_init(&dev_priv->gt_lock);
4378
4379         intel_gt_reset(dev);
4380
4381         if (IS_VALLEYVIEW(dev)) {
4382                 dev_priv->gt.force_wake_get = vlv_force_wake_get;
4383                 dev_priv->gt.force_wake_put = vlv_force_wake_put;
4384         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
4385                 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_mt_get;
4386                 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_mt_put;
4387         } else if (IS_GEN6(dev)) {
4388                 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get;
4389                 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put;
4390         }
4391         INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
4392                           intel_gen6_powersave_work);
4393 }
4394
4395 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
4396 {
4397         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4398
4399         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
4400                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
4401                 return -EAGAIN;
4402         }
4403
4404         I915_WRITE(GEN6_PCODE_DATA, *val);
4405         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
4406
4407         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
4408                      500)) {
4409                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
4410                 return -ETIMEDOUT;
4411         }
4412
4413         *val = I915_READ(GEN6_PCODE_DATA);
4414         I915_WRITE(GEN6_PCODE_DATA, 0);
4415
4416         return 0;
4417 }
4418
4419 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
4420 {
4421         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4422
4423         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
4424                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
4425                 return -EAGAIN;
4426         }
4427
4428         I915_WRITE(GEN6_PCODE_DATA, val);
4429         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
4430
4431         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
4432                      500)) {
4433                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
4434                 return -ETIMEDOUT;
4435         }
4436
4437         I915_WRITE(GEN6_PCODE_DATA, 0);
4438
4439         return 0;
4440 }