drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "../../../platform/x86/intel_ips.h"
  32 #include <linux/module.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/i915_powerwell.h>
  35 #include <linux/pm_runtime.h>
  36
  37 /**
  38  * RC6 is a special power stage which allows the GPU to enter an very
  39  * low-voltage mode when idle, using down to 0V while at this stage.  This
  40  * stage is entered automatically when the GPU is idle when RC6 support is
  41  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  42  *
  43  * There are different RC6 modes available in Intel GPU, which differentiate
  44  * among each other with the latency required to enter and leave RC6 and
  45  * voltage consumed by the GPU in different states.
  46  *
  47  * The combination of the following flags define which states GPU is allowed
  48  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  49  * RC6pp is deepest RC6. Their support by hardware varies according to the
  50  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  51  * which brings the most power savings; deeper states save more power, but
  52  * require higher latency to switch to and wake up.
  53  */
  54 #define INTEL_RC6_ENABLE                        (1<<0)
  55 #define INTEL_RC6p_ENABLE                       (1<<1)
  56 #define INTEL_RC6pp_ENABLE                      (1<<2)
  57
  58 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
  59  * framebuffer contents in-memory, aiming at reducing the required bandwidth
  60  * during in-memory transfers and, therefore, reduce the power packet.
  61  *
  62  * The benefits of FBC are mostly visible with solid backgrounds and
  63  * variation-less patterns.
  64  *
  65  * FBC-related functionality can be enabled by the means of the
  66  * i915.i915_enable_fbc parameter
  67  */
  68
  69 static void i8xx_disable_fbc(struct drm_device *dev)
  70 {
  71         struct drm_i915_private *dev_priv = dev->dev_private;
  72         u32 fbc_ctl;
  73
  74         /* Disable compression */
  75         fbc_ctl = I915_READ(FBC_CONTROL);
  76         if ((fbc_ctl & FBC_CTL_EN) == 0)
  77                 return;
  78
  79         fbc_ctl &= ~FBC_CTL_EN;
  80         I915_WRITE(FBC_CONTROL, fbc_ctl);
  81
  82         /* Wait for compressing bit to clear */
  83         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
  84                 DRM_DEBUG_KMS("FBC idle timed out\n");
  85                 return;
  86         }
  87
  88         DRM_DEBUG_KMS("disabled FBC\n");
  89 }
  90
  91 static void i8xx_enable_fbc(struct drm_crtc *crtc)
  92 {
  93         struct drm_device *dev = crtc->dev;
  94         struct drm_i915_private *dev_priv = dev->dev_private;
  95         struct drm_framebuffer *fb = crtc->fb;
  96         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  97         struct drm_i915_gem_object *obj = intel_fb->obj;
  98         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  99         int cfb_pitch;
 100         int i;
 101         u32 fbc_ctl;
 102
 103         cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
 104         if (fb->pitches[0] < cfb_pitch)
 105                 cfb_pitch = fb->pitches[0];
 106
 107         /* FBC_CTL wants 32B or 64B units */
 108         if (IS_GEN2(dev))
 109                 cfb_pitch = (cfb_pitch / 32) - 1;
 110         else
 111                 cfb_pitch = (cfb_pitch / 64) - 1;
 112
 113         /* Clear old tags */
 114         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 115                 I915_WRITE(FBC_TAG + (i * 4), 0);
 116
 117         if (IS_GEN4(dev)) {
 118                 u32 fbc_ctl2;
 119
 120                 /* Set it up... */
 121                 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
 122                 fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane);
 123                 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 124                 I915_WRITE(FBC_FENCE_OFF, crtc->y);
 125         }
 126
 127         /* enable it... */
 128         fbc_ctl = I915_READ(FBC_CONTROL);
 129         fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
 130         fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
 131         if (IS_I945GM(dev))
 132                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 133         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 134         fbc_ctl |= obj->fence_reg;
 135         I915_WRITE(FBC_CONTROL, fbc_ctl);
 136
 137         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
 138                       cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
 139 }
 140
 141 static bool i8xx_fbc_enabled(struct drm_device *dev)
 142 {
 143         struct drm_i915_private *dev_priv = dev->dev_private;
 144
 145         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
 146 }
 147
 148 static void g4x_enable_fbc(struct drm_crtc *crtc)
 149 {
 150         struct drm_device *dev = crtc->dev;
 151         struct drm_i915_private *dev_priv = dev->dev_private;
 152         struct drm_framebuffer *fb = crtc->fb;
 153         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 154         struct drm_i915_gem_object *obj = intel_fb->obj;
 155         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 156         u32 dpfc_ctl;
 157
 158         dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN;
 159         if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
 160                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 161         else
 162                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 163         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
 164
 165         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
 166
 167         /* enable it... */
 168         I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 169
 170         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 171 }
 172
 173 static void g4x_disable_fbc(struct drm_device *dev)
 174 {
 175         struct drm_i915_private *dev_priv = dev->dev_private;
 176         u32 dpfc_ctl;
 177
 178         /* Disable compression */
 179         dpfc_ctl = I915_READ(DPFC_CONTROL);
 180         if (dpfc_ctl & DPFC_CTL_EN) {
 181                 dpfc_ctl &= ~DPFC_CTL_EN;
 182                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
 183
 184                 DRM_DEBUG_KMS("disabled FBC\n");
 185         }
 186 }
 187
 188 static bool g4x_fbc_enabled(struct drm_device *dev)
 189 {
 190         struct drm_i915_private *dev_priv = dev->dev_private;
 191
 192         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
 193 }
 194
 195 static void sandybridge_blit_fbc_update(struct drm_device *dev)
 196 {
 197         struct drm_i915_private *dev_priv = dev->dev_private;
 198         u32 blt_ecoskpd;
 199
 200         /* Make sure blitter notifies FBC of writes */
 201
 202         /* Blitter is part of Media powerwell on VLV. No impact of
 203          * his param in other platforms for now */
 204         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
 205
 206         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
 207         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
 208                 GEN6_BLITTER_LOCK_SHIFT;
 209         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 210         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
 211         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 212         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
 213                          GEN6_BLITTER_LOCK_SHIFT);
 214         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 215         POSTING_READ(GEN6_BLITTER_ECOSKPD);
 216
 217         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
 218 }
 219
 220 static void ironlake_enable_fbc(struct drm_crtc *crtc)
 221 {
 222         struct drm_device *dev = crtc->dev;
 223         struct drm_i915_private *dev_priv = dev->dev_private;
 224         struct drm_framebuffer *fb = crtc->fb;
 225         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 226         struct drm_i915_gem_object *obj = intel_fb->obj;
 227         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 228         u32 dpfc_ctl;
 229
 230         dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane);
 231         if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
 232                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 233         else
 234                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 235         dpfc_ctl |= DPFC_CTL_FENCE_EN;
 236         if (IS_GEN5(dev))
 237                 dpfc_ctl |= obj->fence_reg;
 238
 239         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
 240         I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
 241         /* enable it... */
 242         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 243
 244         if (IS_GEN6(dev)) {
 245                 I915_WRITE(SNB_DPFC_CTL_SA,
 246                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 247                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
 248                 sandybridge_blit_fbc_update(dev);
 249         }
 250
 251         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 252 }
 253
 254 static void ironlake_disable_fbc(struct drm_device *dev)
 255 {
 256         struct drm_i915_private *dev_priv = dev->dev_private;
 257         u32 dpfc_ctl;
 258
 259         /* Disable compression */
 260         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 261         if (dpfc_ctl & DPFC_CTL_EN) {
 262                 dpfc_ctl &= ~DPFC_CTL_EN;
 263                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
 264
 265                 DRM_DEBUG_KMS("disabled FBC\n");
 266         }
 267 }
 268
 269 static bool ironlake_fbc_enabled(struct drm_device *dev)
 270 {
 271         struct drm_i915_private *dev_priv = dev->dev_private;
 272
 273         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 274 }
 275
 276 static void gen7_enable_fbc(struct drm_crtc *crtc)
 277 {
 278         struct drm_device *dev = crtc->dev;
 279         struct drm_i915_private *dev_priv = dev->dev_private;
 280         struct drm_framebuffer *fb = crtc->fb;
 281         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 282         struct drm_i915_gem_object *obj = intel_fb->obj;
 283         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 284         u32 dpfc_ctl;
 285
 286         dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane);
 287         if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
 288                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 289         else
 290                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 291         dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
 292
 293         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 294
 295         if (IS_IVYBRIDGE(dev)) {
 296                 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
 297                 I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
 298         } else {
 299                 /* WaFbcAsynchFlipDisableFbcQueue:hsw */
 300                 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
 301                            HSW_BYPASS_FBC_QUEUE);
 302         }
 303
 304         I915_WRITE(SNB_DPFC_CTL_SA,
 305                    SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 306         I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
 307
 308         sandybridge_blit_fbc_update(dev);
 309
 310         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 311 }
 312
 313 bool intel_fbc_enabled(struct drm_device *dev)
 314 {
 315         struct drm_i915_private *dev_priv = dev->dev_private;
 316
 317         if (!dev_priv->display.fbc_enabled)
 318                 return false;
 319
 320         return dev_priv->display.fbc_enabled(dev);
 321 }
 322
 323 static void intel_fbc_work_fn(struct work_struct *__work)
 324 {
 325         struct intel_fbc_work *work =
 326                 container_of(to_delayed_work(__work),
 327                              struct intel_fbc_work, work);
 328         struct drm_device *dev = work->crtc->dev;
 329         struct drm_i915_private *dev_priv = dev->dev_private;
 330
 331         mutex_lock(&dev->struct_mutex);
 332         if (work == dev_priv->fbc.fbc_work) {
 333                 /* Double check that we haven't switched fb without cancelling
 334                  * the prior work.
 335                  */
 336                 if (work->crtc->fb == work->fb) {
 337                         dev_priv->display.enable_fbc(work->crtc);
 338
 339                         dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
 340                         dev_priv->fbc.fb_id = work->crtc->fb->base.id;
 341                         dev_priv->fbc.y = work->crtc->y;
 342                 }
 343
 344                 dev_priv->fbc.fbc_work = NULL;
 345         }
 346         mutex_unlock(&dev->struct_mutex);
 347
 348         kfree(work);
 349 }
 350
 351 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
 352 {
 353         if (dev_priv->fbc.fbc_work == NULL)
 354                 return;
 355
 356         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
 357
 358         /* Synchronisation is provided by struct_mutex and checking of
 359          * dev_priv->fbc.fbc_work, so we can perform the cancellation
 360          * entirely asynchronously.
 361          */
 362         if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
 363                 /* tasklet was killed before being run, clean up */
 364                 kfree(dev_priv->fbc.fbc_work);
 365
 366         /* Mark the work as no longer wanted so that if it does
 367          * wake-up (because the work was already running and waiting
 368          * for our mutex), it will discover that is no longer
 369          * necessary to run.
 370          */
 371         dev_priv->fbc.fbc_work = NULL;
 372 }
 373
 374 static void intel_enable_fbc(struct drm_crtc *crtc)
 375 {
 376         struct intel_fbc_work *work;
 377         struct drm_device *dev = crtc->dev;
 378         struct drm_i915_private *dev_priv = dev->dev_private;
 379
 380         if (!dev_priv->display.enable_fbc)
 381                 return;
 382
 383         intel_cancel_fbc_work(dev_priv);
 384
 385         work = kzalloc(sizeof(*work), GFP_KERNEL);
 386         if (work == NULL) {
 387                 DRM_ERROR("Failed to allocate FBC work structure\n");
 388                 dev_priv->display.enable_fbc(crtc);
 389                 return;
 390         }
 391
 392         work->crtc = crtc;
 393         work->fb = crtc->fb;
 394         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
 395
 396         dev_priv->fbc.fbc_work = work;
 397
 398         /* Delay the actual enabling to let pageflipping cease and the
 399          * display to settle before starting the compression. Note that
 400          * this delay also serves a second purpose: it allows for a
 401          * vblank to pass after disabling the FBC before we attempt
 402          * to modify the control registers.
 403          *
 404          * A more complicated solution would involve tracking vblanks
 405          * following the termination of the page-flipping sequence
 406          * and indeed performing the enable as a co-routine and not
 407          * waiting synchronously upon the vblank.
 408          *
 409          * WaFbcWaitForVBlankBeforeEnable:ilk,snb
 410          */
 411         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
 412 }
 413
 414 void intel_disable_fbc(struct drm_device *dev)
 415 {
 416         struct drm_i915_private *dev_priv = dev->dev_private;
 417
 418         intel_cancel_fbc_work(dev_priv);
 419
 420         if (!dev_priv->display.disable_fbc)
 421                 return;
 422
 423         dev_priv->display.disable_fbc(dev);
 424         dev_priv->fbc.plane = -1;
 425 }
 426
 427 static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
 428                               enum no_fbc_reason reason)
 429 {
 430         if (dev_priv->fbc.no_fbc_reason == reason)
 431                 return false;
 432
 433         dev_priv->fbc.no_fbc_reason = reason;
 434         return true;
 435 }
 436
 437 /**
 438  * intel_update_fbc - enable/disable FBC as needed
 439  * @dev: the drm_device
 440  *
 441  * Set up the framebuffer compression hardware at mode set time.  We
 442  * enable it if possible:
 443  *   - plane A only (on pre-965)
 444  *   - no pixel mulitply/line duplication
 445  *   - no alpha buffer discard
 446  *   - no dual wide
 447  *   - framebuffer <= max_hdisplay in width, max_vdisplay in height
 448  *
 449  * We can't assume that any compression will take place (worst case),
 450  * so the compressed buffer has to be the same size as the uncompressed
 451  * one.  It also must reside (along with the line length buffer) in
 452  * stolen memory.
 453  *
 454  * We need to enable/disable FBC on a global basis.
 455  */
 456 void intel_update_fbc(struct drm_device *dev)
 457 {
 458         struct drm_i915_private *dev_priv = dev->dev_private;
 459         struct drm_crtc *crtc = NULL, *tmp_crtc;
 460         struct intel_crtc *intel_crtc;
 461         struct drm_framebuffer *fb;
 462         struct intel_framebuffer *intel_fb;
 463         struct drm_i915_gem_object *obj;
 464         const struct drm_display_mode *adjusted_mode;
 465         unsigned int max_width, max_height;
 466
 467         if (!HAS_FBC(dev)) {
 468                 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
 469                 return;
 470         }
 471
 472         if (!i915.powersave) {
 473                 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
 474                         DRM_DEBUG_KMS("fbc disabled per module param\n");
 475                 return;
 476         }
 477
 478         /*
 479          * If FBC is already on, we just have to verify that we can
 480          * keep it that way...
 481          * Need to disable if:
 482          *   - more than one pipe is active
 483          *   - changing FBC params (stride, fence, mode)
 484          *   - new fb is too large to fit in compressed buffer
 485          *   - going to an unsupported config (interlace, pixel multiply, etc.)
 486          */
 487         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
 488                 if (intel_crtc_active(tmp_crtc) &&
 489                     to_intel_crtc(tmp_crtc)->primary_enabled) {
 490                         if (crtc) {
 491                                 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
 492                                         DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
 493                                 goto out_disable;
 494                         }
 495                         crtc = tmp_crtc;
 496                 }
 497         }
 498
 499         if (!crtc || crtc->fb == NULL) {
 500                 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
 501                         DRM_DEBUG_KMS("no output, disabling\n");
 502                 goto out_disable;
 503         }
 504
 505         intel_crtc = to_intel_crtc(crtc);
 506         fb = crtc->fb;
 507         intel_fb = to_intel_framebuffer(fb);
 508         obj = intel_fb->obj;
 509         adjusted_mode = &intel_crtc->config.adjusted_mode;
 510
 511         if (i915.enable_fbc < 0 &&
 512             INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
 513                 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
 514                         DRM_DEBUG_KMS("disabled per chip default\n");
 515                 goto out_disable;
 516         }
 517         if (!i915.enable_fbc) {
 518                 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
 519                         DRM_DEBUG_KMS("fbc disabled per module param\n");
 520                 goto out_disable;
 521         }
 522         if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
 523             (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
 524                 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
 525                         DRM_DEBUG_KMS("mode incompatible with compression, "
 526                                       "disabling\n");
 527                 goto out_disable;
 528         }
 529
 530         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 531                 max_width = 4096;
 532                 max_height = 2048;
 533         } else {
 534                 max_width = 2048;
 535                 max_height = 1536;
 536         }
 537         if (intel_crtc->config.pipe_src_w > max_width ||
 538             intel_crtc->config.pipe_src_h > max_height) {
 539                 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
 540                         DRM_DEBUG_KMS("mode too large for compression, disabling\n");
 541                 goto out_disable;
 542         }
 543         if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) &&
 544             intel_crtc->plane != PLANE_A) {
 545                 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
 546                         DRM_DEBUG_KMS("plane not A, disabling compression\n");
 547                 goto out_disable;
 548         }
 549
 550         /* The use of a CPU fence is mandatory in order to detect writes
 551          * by the CPU to the scanout and trigger updates to the FBC.
 552          */
 553         if (obj->tiling_mode != I915_TILING_X ||
 554             obj->fence_reg == I915_FENCE_REG_NONE) {
 555                 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
 556                         DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
 557                 goto out_disable;
 558         }
 559
 560         /* If the kernel debugger is active, always disable compression */
 561         if (in_dbg_master())
 562                 goto out_disable;
 563
 564         if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
 565                 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
 566                         DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
 567                 goto out_disable;
 568         }
 569
 570         /* If the scanout has not changed, don't modify the FBC settings.
 571          * Note that we make the fundamental assumption that the fb->obj
 572          * cannot be unpinned (and have its GTT offset and fence revoked)
 573          * without first being decoupled from the scanout and FBC disabled.
 574          */
 575         if (dev_priv->fbc.plane == intel_crtc->plane &&
 576             dev_priv->fbc.fb_id == fb->base.id &&
 577             dev_priv->fbc.y == crtc->y)
 578                 return;
 579
 580         if (intel_fbc_enabled(dev)) {
 581                 /* We update FBC along two paths, after changing fb/crtc
 582                  * configuration (modeswitching) and after page-flipping
 583                  * finishes. For the latter, we know that not only did
 584                  * we disable the FBC at the start of the page-flip
 585                  * sequence, but also more than one vblank has passed.
 586                  *
 587                  * For the former case of modeswitching, it is possible
 588                  * to switch between two FBC valid configurations
 589                  * instantaneously so we do need to disable the FBC
 590                  * before we can modify its control registers. We also
 591                  * have to wait for the next vblank for that to take
 592                  * effect. However, since we delay enabling FBC we can
 593                  * assume that a vblank has passed since disabling and
 594                  * that we can safely alter the registers in the deferred
 595                  * callback.
 596                  *
 597                  * In the scenario that we go from a valid to invalid
 598                  * and then back to valid FBC configuration we have
 599                  * no strict enforcement that a vblank occurred since
 600                  * disabling the FBC. However, along all current pipe
 601                  * disabling paths we do need to wait for a vblank at
 602                  * some point. And we wait before enabling FBC anyway.
 603                  */
 604                 DRM_DEBUG_KMS("disabling active FBC for update\n");
 605                 intel_disable_fbc(dev);
 606         }
 607
 608         intel_enable_fbc(crtc);
 609         dev_priv->fbc.no_fbc_reason = FBC_OK;
 610         return;
 611
 612 out_disable:
 613         /* Multiple disables should be harmless */
 614         if (intel_fbc_enabled(dev)) {
 615                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
 616                 intel_disable_fbc(dev);
 617         }
 618         i915_gem_stolen_cleanup_compression(dev);
 619 }
 620
 621 static void i915_pineview_get_mem_freq(struct drm_device *dev)
 622 {
 623         drm_i915_private_t *dev_priv = dev->dev_private;
 624         u32 tmp;
 625
 626         tmp = I915_READ(CLKCFG);
 627
 628         switch (tmp & CLKCFG_FSB_MASK) {
 629         case CLKCFG_FSB_533:
 630                 dev_priv->fsb_freq = 533; /* 133*4 */
 631                 break;
 632         case CLKCFG_FSB_800:
 633                 dev_priv->fsb_freq = 800; /* 200*4 */
 634                 break;
 635         case CLKCFG_FSB_667:
 636                 dev_priv->fsb_freq =  667; /* 167*4 */
 637                 break;
 638         case CLKCFG_FSB_400:
 639                 dev_priv->fsb_freq = 400; /* 100*4 */
 640                 break;
 641         }
 642
 643         switch (tmp & CLKCFG_MEM_MASK) {
 644         case CLKCFG_MEM_533:
 645                 dev_priv->mem_freq = 533;
 646                 break;
 647         case CLKCFG_MEM_667:
 648                 dev_priv->mem_freq = 667;
 649                 break;
 650         case CLKCFG_MEM_800:
 651                 dev_priv->mem_freq = 800;
 652                 break;
 653         }
 654
 655         /* detect pineview DDR3 setting */
 656         tmp = I915_READ(CSHRDDR3CTL);
 657         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 658 }
 659
 660 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 661 {
 662         drm_i915_private_t *dev_priv = dev->dev_private;
 663         u16 ddrpll, csipll;
 664
 665         ddrpll = I915_READ16(DDRMPLL1);
 666         csipll = I915_READ16(CSIPLL0);
 667
 668         switch (ddrpll & 0xff) {
 669         case 0xc:
 670                 dev_priv->mem_freq = 800;
 671                 break;
 672         case 0x10:
 673                 dev_priv->mem_freq = 1066;
 674                 break;
 675         case 0x14:
 676                 dev_priv->mem_freq = 1333;
 677                 break;
 678         case 0x18:
 679                 dev_priv->mem_freq = 1600;
 680                 break;
 681         default:
 682                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 683                                  ddrpll & 0xff);
 684                 dev_priv->mem_freq = 0;
 685                 break;
 686         }
 687
 688         dev_priv->ips.r_t = dev_priv->mem_freq;
 689
 690         switch (csipll & 0x3ff) {
 691         case 0x00c:
 692                 dev_priv->fsb_freq = 3200;
 693                 break;
 694         case 0x00e:
 695                 dev_priv->fsb_freq = 3733;
 696                 break;
 697         case 0x010:
 698                 dev_priv->fsb_freq = 4266;
 699                 break;
 700         case 0x012:
 701                 dev_priv->fsb_freq = 4800;
 702                 break;
 703         case 0x014:
 704                 dev_priv->fsb_freq = 5333;
 705                 break;
 706         case 0x016:
 707                 dev_priv->fsb_freq = 5866;
 708                 break;
 709         case 0x018:
 710                 dev_priv->fsb_freq = 6400;
 711                 break;
 712         default:
 713                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 714                                  csipll & 0x3ff);
 715                 dev_priv->fsb_freq = 0;
 716                 break;
 717         }
 718
 719         if (dev_priv->fsb_freq == 3200) {
 720                 dev_priv->ips.c_m = 0;
 721         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 722                 dev_priv->ips.c_m = 1;
 723         } else {
 724                 dev_priv->ips.c_m = 2;
 725         }
 726 }
 727
 728 static const struct cxsr_latency cxsr_latency_table[] = {
 729         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 730         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 731         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 732         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 733         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 734
 735         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 736         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 737         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 738         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 739         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 740
 741         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 742         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 743         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 744         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 745         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 746
 747         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 748         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 749         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 750         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 751         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 752
 753         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 754         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 755         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 756         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 757         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 758
 759         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 760         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 761         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 762         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 763         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 764 };
 765
 766 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 767                                                          int is_ddr3,
 768                                                          int fsb,
 769                                                          int mem)
 770 {
 771         const struct cxsr_latency *latency;
 772         int i;
 773
 774         if (fsb == 0 || mem == 0)
 775                 return NULL;
 776
 777         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 778                 latency = &cxsr_latency_table[i];
 779                 if (is_desktop == latency->is_desktop &&
 780                     is_ddr3 == latency->is_ddr3 &&
 781                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 782                         return latency;
 783         }
 784
 785         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 786
 787         return NULL;
 788 }
 789
 790 static void pineview_disable_cxsr(struct drm_device *dev)
 791 {
 792         struct drm_i915_private *dev_priv = dev->dev_private;
 793
 794         /* deactivate cxsr */
 795         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
 796 }
 797
 798 /*
 799  * Latency for FIFO fetches is dependent on several factors:
 800  *   - memory configuration (speed, channels)
 801  *   - chipset
 802  *   - current MCH state
 803  * It can be fairly high in some situations, so here we assume a fairly
 804  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 805  * set this value too high, the FIFO will fetch frequently to stay full)
 806  * and power consumption (set it too low to save power and we might see
 807  * FIFO underruns and display "flicker").
 808  *
 809  * A value of 5us seems to be a good balance; safe for very low end
 810  * platforms but not overly aggressive on lower latency configs.
 811  */
 812 static const int latency_ns = 5000;
 813
 814 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 815 {
 816         struct drm_i915_private *dev_priv = dev->dev_private;
 817         uint32_t dsparb = I915_READ(DSPARB);
 818         int size;
 819
 820         size = dsparb & 0x7f;
 821         if (plane)
 822                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 823
 824         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 825                       plane ? "B" : "A", size);
 826
 827         return size;
 828 }
 829
 830 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 831 {
 832         struct drm_i915_private *dev_priv = dev->dev_private;
 833         uint32_t dsparb = I915_READ(DSPARB);
 834         int size;
 835
 836         size = dsparb & 0x1ff;
 837         if (plane)
 838                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 839         size >>= 1; /* Convert to cachelines */
 840
 841         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 842                       plane ? "B" : "A", size);
 843
 844         return size;
 845 }
 846
 847 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 848 {
 849         struct drm_i915_private *dev_priv = dev->dev_private;
 850         uint32_t dsparb = I915_READ(DSPARB);
 851         int size;
 852
 853         size = dsparb & 0x7f;
 854         size >>= 2; /* Convert to cachelines */
 855
 856         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 857                       plane ? "B" : "A",
 858                       size);
 859
 860         return size;
 861 }
 862
 863 /* Pineview has different values for various configs */
 864 static const struct intel_watermark_params pineview_display_wm = {
 865         PINEVIEW_DISPLAY_FIFO,
 866         PINEVIEW_MAX_WM,
 867         PINEVIEW_DFT_WM,
 868         PINEVIEW_GUARD_WM,
 869         PINEVIEW_FIFO_LINE_SIZE
 870 };
 871 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 872         PINEVIEW_DISPLAY_FIFO,
 873         PINEVIEW_MAX_WM,
 874         PINEVIEW_DFT_HPLLOFF_WM,
 875         PINEVIEW_GUARD_WM,
 876         PINEVIEW_FIFO_LINE_SIZE
 877 };
 878 static const struct intel_watermark_params pineview_cursor_wm = {
 879         PINEVIEW_CURSOR_FIFO,
 880         PINEVIEW_CURSOR_MAX_WM,
 881         PINEVIEW_CURSOR_DFT_WM,
 882         PINEVIEW_CURSOR_GUARD_WM,
 883         PINEVIEW_FIFO_LINE_SIZE,
 884 };
 885 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 886         PINEVIEW_CURSOR_FIFO,
 887         PINEVIEW_CURSOR_MAX_WM,
 888         PINEVIEW_CURSOR_DFT_WM,
 889         PINEVIEW_CURSOR_GUARD_WM,
 890         PINEVIEW_FIFO_LINE_SIZE
 891 };
 892 static const struct intel_watermark_params g4x_wm_info = {
 893         G4X_FIFO_SIZE,
 894         G4X_MAX_WM,
 895         G4X_MAX_WM,
 896         2,
 897         G4X_FIFO_LINE_SIZE,
 898 };
 899 static const struct intel_watermark_params g4x_cursor_wm_info = {
 900         I965_CURSOR_FIFO,
 901         I965_CURSOR_MAX_WM,
 902         I965_CURSOR_DFT_WM,
 903         2,
 904         G4X_FIFO_LINE_SIZE,
 905 };
 906 static const struct intel_watermark_params valleyview_wm_info = {
 907         VALLEYVIEW_FIFO_SIZE,
 908         VALLEYVIEW_MAX_WM,
 909         VALLEYVIEW_MAX_WM,
 910         2,
 911         G4X_FIFO_LINE_SIZE,
 912 };
 913 static const struct intel_watermark_params valleyview_cursor_wm_info = {
 914         I965_CURSOR_FIFO,
 915         VALLEYVIEW_CURSOR_MAX_WM,
 916         I965_CURSOR_DFT_WM,
 917         2,
 918         G4X_FIFO_LINE_SIZE,
 919 };
 920 static const struct intel_watermark_params i965_cursor_wm_info = {
 921         I965_CURSOR_FIFO,
 922         I965_CURSOR_MAX_WM,
 923         I965_CURSOR_DFT_WM,
 924         2,
 925         I915_FIFO_LINE_SIZE,
 926 };
 927 static const struct intel_watermark_params i945_wm_info = {
 928         I945_FIFO_SIZE,
 929         I915_MAX_WM,
 930         1,
 931         2,
 932         I915_FIFO_LINE_SIZE
 933 };
 934 static const struct intel_watermark_params i915_wm_info = {
 935         I915_FIFO_SIZE,
 936         I915_MAX_WM,
 937         1,
 938         2,
 939         I915_FIFO_LINE_SIZE
 940 };
 941 static const struct intel_watermark_params i830_wm_info = {
 942         I855GM_FIFO_SIZE,
 943         I915_MAX_WM,
 944         1,
 945         2,
 946         I830_FIFO_LINE_SIZE
 947 };
 948 static const struct intel_watermark_params i845_wm_info = {
 949         I830_FIFO_SIZE,
 950         I915_MAX_WM,
 951         1,
 952         2,
 953         I830_FIFO_LINE_SIZE
 954 };
 955
 956 /**
 957  * intel_calculate_wm - calculate watermark level
 958  * @clock_in_khz: pixel clock
 959  * @wm: chip FIFO params
 960  * @pixel_size: display pixel size
 961  * @latency_ns: memory latency for the platform
 962  *
 963  * Calculate the watermark level (the level at which the display plane will
 964  * start fetching from memory again).  Each chip has a different display
 965  * FIFO size and allocation, so the caller needs to figure that out and pass
 966  * in the correct intel_watermark_params structure.
 967  *
 968  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 969  * on the pixel size.  When it reaches the watermark level, it'll start
 970  * fetching FIFO line sized based chunks from memory until the FIFO fills
 971  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 972  * will occur, and a display engine hang could result.
 973  */
 974 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 975                                         const struct intel_watermark_params *wm,
 976                                         int fifo_size,
 977                                         int pixel_size,
 978                                         unsigned long latency_ns)
 979 {
 980         long entries_required, wm_size;
 981
 982         /*
 983          * Note: we need to make sure we don't overflow for various clock &
 984          * latency values.
 985          * clocks go from a few thousand to several hundred thousand.
 986          * latency is usually a few thousand
 987          */
 988         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
 989                 1000;
 990         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 991
 992         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 993
 994         wm_size = fifo_size - (entries_required + wm->guard_size);
 995
 996         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
 997
 998         /* Don't promote wm_size to unsigned... */
 999         if (wm_size > (long)wm->max_wm)
1000                 wm_size = wm->max_wm;
1001         if (wm_size <= 0)
1002                 wm_size = wm->default_wm;
1003         return wm_size;
1004 }
1005
1006 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1007 {
1008         struct drm_crtc *crtc, *enabled = NULL;
1009
1010         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1011                 if (intel_crtc_active(crtc)) {
1012                         if (enabled)
1013                                 return NULL;
1014                         enabled = crtc;
1015                 }
1016         }
1017
1018         return enabled;
1019 }
1020
1021 static void pineview_update_wm(struct drm_crtc *unused_crtc)
1022 {
1023         struct drm_device *dev = unused_crtc->dev;
1024         struct drm_i915_private *dev_priv = dev->dev_private;
1025         struct drm_crtc *crtc;
1026         const struct cxsr_latency *latency;
1027         u32 reg;
1028         unsigned long wm;
1029
1030         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1031                                          dev_priv->fsb_freq, dev_priv->mem_freq);
1032         if (!latency) {
1033                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1034                 pineview_disable_cxsr(dev);
1035                 return;
1036         }
1037
1038         crtc = single_enabled_crtc(dev);
1039         if (crtc) {
1040                 const struct drm_display_mode *adjusted_mode;
1041                 int pixel_size = crtc->fb->bits_per_pixel / 8;
1042                 int clock;
1043
1044                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1045                 clock = adjusted_mode->crtc_clock;
1046
1047                 /* Display SR */
1048                 wm = intel_calculate_wm(clock, &pineview_display_wm,
1049                                         pineview_display_wm.fifo_size,
1050                                         pixel_size, latency->display_sr);
1051                 reg = I915_READ(DSPFW1);
1052                 reg &= ~DSPFW_SR_MASK;
1053                 reg |= wm << DSPFW_SR_SHIFT;
1054                 I915_WRITE(DSPFW1, reg);
1055                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1056
1057                 /* cursor SR */
1058                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1059                                         pineview_display_wm.fifo_size,
1060                                         pixel_size, latency->cursor_sr);
1061                 reg = I915_READ(DSPFW3);
1062                 reg &= ~DSPFW_CURSOR_SR_MASK;
1063                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1064                 I915_WRITE(DSPFW3, reg);
1065
1066                 /* Display HPLL off SR */
1067                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1068                                         pineview_display_hplloff_wm.fifo_size,
1069                                         pixel_size, latency->display_hpll_disable);
1070                 reg = I915_READ(DSPFW3);
1071                 reg &= ~DSPFW_HPLL_SR_MASK;
1072                 reg |= wm & DSPFW_HPLL_SR_MASK;
1073                 I915_WRITE(DSPFW3, reg);
1074
1075                 /* cursor HPLL off SR */
1076                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1077                                         pineview_display_hplloff_wm.fifo_size,
1078                                         pixel_size, latency->cursor_hpll_disable);
1079                 reg = I915_READ(DSPFW3);
1080                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1081                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1082                 I915_WRITE(DSPFW3, reg);
1083                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1084
1085                 /* activate cxsr */
1086                 I915_WRITE(DSPFW3,
1087                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1088                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1089         } else {
1090                 pineview_disable_cxsr(dev);
1091                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1092         }
1093 }
1094
1095 static bool g4x_compute_wm0(struct drm_device *dev,
1096                             int plane,
1097                             const struct intel_watermark_params *display,
1098                             int display_latency_ns,
1099                             const struct intel_watermark_params *cursor,
1100                             int cursor_latency_ns,
1101                             int *plane_wm,
1102                             int *cursor_wm)
1103 {
1104         struct drm_crtc *crtc;
1105         const struct drm_display_mode *adjusted_mode;
1106         int htotal, hdisplay, clock, pixel_size;
1107         int line_time_us, line_count;
1108         int entries, tlb_miss;
1109
1110         crtc = intel_get_crtc_for_plane(dev, plane);
1111         if (!intel_crtc_active(crtc)) {
1112                 *cursor_wm = cursor->guard_size;
1113                 *plane_wm = display->guard_size;
1114                 return false;
1115         }
1116
1117         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1118         clock = adjusted_mode->crtc_clock;
1119         htotal = adjusted_mode->crtc_htotal;
1120         hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1121         pixel_size = crtc->fb->bits_per_pixel / 8;
1122
1123         /* Use the small buffer method to calculate plane watermark */
1124         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1125         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1126         if (tlb_miss > 0)
1127                 entries += tlb_miss;
1128         entries = DIV_ROUND_UP(entries, display->cacheline_size);
1129         *plane_wm = entries + display->guard_size;
1130         if (*plane_wm > (int)display->max_wm)
1131                 *plane_wm = display->max_wm;
1132
1133         /* Use the large buffer method to calculate cursor watermark */
1134         line_time_us = ((htotal * 1000) / clock);
1135         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1136         entries = line_count * 64 * pixel_size;
1137         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1138         if (tlb_miss > 0)
1139                 entries += tlb_miss;
1140         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1141         *cursor_wm = entries + cursor->guard_size;
1142         if (*cursor_wm > (int)cursor->max_wm)
1143                 *cursor_wm = (int)cursor->max_wm;
1144
1145         return true;
1146 }
1147
1148 /*
1149  * Check the wm result.
1150  *
1151  * If any calculated watermark values is larger than the maximum value that
1152  * can be programmed into the associated watermark register, that watermark
1153  * must be disabled.
1154  */
1155 static bool g4x_check_srwm(struct drm_device *dev,
1156                            int display_wm, int cursor_wm,
1157                            const struct intel_watermark_params *display,
1158                            const struct intel_watermark_params *cursor)
1159 {
1160         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1161                       display_wm, cursor_wm);
1162
1163         if (display_wm > display->max_wm) {
1164                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1165                               display_wm, display->max_wm);
1166                 return false;
1167         }
1168
1169         if (cursor_wm > cursor->max_wm) {
1170                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1171                               cursor_wm, cursor->max_wm);
1172                 return false;
1173         }
1174
1175         if (!(display_wm || cursor_wm)) {
1176                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1177                 return false;
1178         }
1179
1180         return true;
1181 }
1182
1183 static bool g4x_compute_srwm(struct drm_device *dev,
1184                              int plane,
1185                              int latency_ns,
1186                              const struct intel_watermark_params *display,
1187                              const struct intel_watermark_params *cursor,
1188                              int *display_wm, int *cursor_wm)
1189 {
1190         struct drm_crtc *crtc;
1191         const struct drm_display_mode *adjusted_mode;
1192         int hdisplay, htotal, pixel_size, clock;
1193         unsigned long line_time_us;
1194         int line_count, line_size;
1195         int small, large;
1196         int entries;
1197
1198         if (!latency_ns) {
1199                 *display_wm = *cursor_wm = 0;
1200                 return false;
1201         }
1202
1203         crtc = intel_get_crtc_for_plane(dev, plane);
1204         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1205         clock = adjusted_mode->crtc_clock;
1206         htotal = adjusted_mode->crtc_htotal;
1207         hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1208         pixel_size = crtc->fb->bits_per_pixel / 8;
1209
1210         line_time_us = (htotal * 1000) / clock;
1211         line_count = (latency_ns / line_time_us + 1000) / 1000;
1212         line_size = hdisplay * pixel_size;
1213
1214         /* Use the minimum of the small and large buffer method for primary */
1215         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1216         large = line_count * line_size;
1217
1218         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1219         *display_wm = entries + display->guard_size;
1220
1221         /* calculate the self-refresh watermark for display cursor */
1222         entries = line_count * pixel_size * 64;
1223         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1224         *cursor_wm = entries + cursor->guard_size;
1225
1226         return g4x_check_srwm(dev,
1227                               *display_wm, *cursor_wm,
1228                               display, cursor);
1229 }
1230
1231 static bool vlv_compute_drain_latency(struct drm_device *dev,
1232                                      int plane,
1233                                      int *plane_prec_mult,
1234                                      int *plane_dl,
1235                                      int *cursor_prec_mult,
1236                                      int *cursor_dl)
1237 {
1238         struct drm_crtc *crtc;
1239         int clock, pixel_size;
1240         int entries;
1241
1242         crtc = intel_get_crtc_for_plane(dev, plane);
1243         if (!intel_crtc_active(crtc))
1244                 return false;
1245
1246         clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
1247         pixel_size = crtc->fb->bits_per_pixel / 8;      /* BPP */
1248
1249         entries = (clock / 1000) * pixel_size;
1250         *plane_prec_mult = (entries > 256) ?
1251                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1252         *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1253                                                      pixel_size);
1254
1255         entries = (clock / 1000) * 4;   /* BPP is always 4 for cursor */
1256         *cursor_prec_mult = (entries > 256) ?
1257                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1258         *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1259
1260         return true;
1261 }
1262
1263 /*
1264  * Update drain latency registers of memory arbiter
1265  *
1266  * Valleyview SoC has a new memory arbiter and needs drain latency registers
1267  * to be programmed. Each plane has a drain latency multiplier and a drain
1268  * latency value.
1269  */
1270
1271 static void vlv_update_drain_latency(struct drm_device *dev)
1272 {
1273         struct drm_i915_private *dev_priv = dev->dev_private;
1274         int planea_prec, planea_dl, planeb_prec, planeb_dl;
1275         int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1276         int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1277                                                         either 16 or 32 */
1278
1279         /* For plane A, Cursor A */
1280         if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1281                                       &cursor_prec_mult, &cursora_dl)) {
1282                 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1283                         DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1284                 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1285                         DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1286
1287                 I915_WRITE(VLV_DDL1, cursora_prec |
1288                                 (cursora_dl << DDL_CURSORA_SHIFT) |
1289                                 planea_prec | planea_dl);
1290         }
1291
1292         /* For plane B, Cursor B */
1293         if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1294                                       &cursor_prec_mult, &cursorb_dl)) {
1295                 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1296                         DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1297                 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1298                         DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1299
1300                 I915_WRITE(VLV_DDL2, cursorb_prec |
1301                                 (cursorb_dl << DDL_CURSORB_SHIFT) |
1302                                 planeb_prec | planeb_dl);
1303         }
1304 }
1305
1306 #define single_plane_enabled(mask) is_power_of_2(mask)
1307
1308 static void valleyview_update_wm(struct drm_crtc *crtc)
1309 {
1310         struct drm_device *dev = crtc->dev;
1311         static const int sr_latency_ns = 12000;
1312         struct drm_i915_private *dev_priv = dev->dev_private;
1313         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1314         int plane_sr, cursor_sr;
1315         int ignore_plane_sr, ignore_cursor_sr;
1316         unsigned int enabled = 0;
1317
1318         vlv_update_drain_latency(dev);
1319
1320         if (g4x_compute_wm0(dev, PIPE_A,
1321                             &valleyview_wm_info, latency_ns,
1322                             &valleyview_cursor_wm_info, latency_ns,
1323                             &planea_wm, &cursora_wm))
1324                 enabled |= 1 << PIPE_A;
1325
1326         if (g4x_compute_wm0(dev, PIPE_B,
1327                             &valleyview_wm_info, latency_ns,
1328                             &valleyview_cursor_wm_info, latency_ns,
1329                             &planeb_wm, &cursorb_wm))
1330                 enabled |= 1 << PIPE_B;
1331
1332         if (single_plane_enabled(enabled) &&
1333             g4x_compute_srwm(dev, ffs(enabled) - 1,
1334                              sr_latency_ns,
1335                              &valleyview_wm_info,
1336                              &valleyview_cursor_wm_info,
1337                              &plane_sr, &ignore_cursor_sr) &&
1338             g4x_compute_srwm(dev, ffs(enabled) - 1,
1339                              2*sr_latency_ns,
1340                              &valleyview_wm_info,
1341                              &valleyview_cursor_wm_info,
1342                              &ignore_plane_sr, &cursor_sr)) {
1343                 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1344         } else {
1345                 I915_WRITE(FW_BLC_SELF_VLV,
1346                            I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1347                 plane_sr = cursor_sr = 0;
1348         }
1349
1350         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1351                       planea_wm, cursora_wm,
1352                       planeb_wm, cursorb_wm,
1353                       plane_sr, cursor_sr);
1354
1355         I915_WRITE(DSPFW1,
1356                    (plane_sr << DSPFW_SR_SHIFT) |
1357                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1358                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1359                    planea_wm);
1360         I915_WRITE(DSPFW2,
1361                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1362                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1363         I915_WRITE(DSPFW3,
1364                    (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1365                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1366 }
1367
1368 static void g4x_update_wm(struct drm_crtc *crtc)
1369 {
1370         struct drm_device *dev = crtc->dev;
1371         static const int sr_latency_ns = 12000;
1372         struct drm_i915_private *dev_priv = dev->dev_private;
1373         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1374         int plane_sr, cursor_sr;
1375         unsigned int enabled = 0;
1376
1377         if (g4x_compute_wm0(dev, PIPE_A,
1378                             &g4x_wm_info, latency_ns,
1379                             &g4x_cursor_wm_info, latency_ns,
1380                             &planea_wm, &cursora_wm))
1381                 enabled |= 1 << PIPE_A;
1382
1383         if (g4x_compute_wm0(dev, PIPE_B,
1384                             &g4x_wm_info, latency_ns,
1385                             &g4x_cursor_wm_info, latency_ns,
1386                             &planeb_wm, &cursorb_wm))
1387                 enabled |= 1 << PIPE_B;
1388
1389         if (single_plane_enabled(enabled) &&
1390             g4x_compute_srwm(dev, ffs(enabled) - 1,
1391                              sr_latency_ns,
1392                              &g4x_wm_info,
1393                              &g4x_cursor_wm_info,
1394                              &plane_sr, &cursor_sr)) {
1395                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1396         } else {
1397                 I915_WRITE(FW_BLC_SELF,
1398                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1399                 plane_sr = cursor_sr = 0;
1400         }
1401
1402         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1403                       planea_wm, cursora_wm,
1404                       planeb_wm, cursorb_wm,
1405                       plane_sr, cursor_sr);
1406
1407         I915_WRITE(DSPFW1,
1408                    (plane_sr << DSPFW_SR_SHIFT) |
1409                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1410                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1411                    planea_wm);
1412         I915_WRITE(DSPFW2,
1413                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1414                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1415         /* HPLL off in SR has some issues on G4x... disable it */
1416         I915_WRITE(DSPFW3,
1417                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1418                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1419 }
1420
1421 static void i965_update_wm(struct drm_crtc *unused_crtc)
1422 {
1423         struct drm_device *dev = unused_crtc->dev;
1424         struct drm_i915_private *dev_priv = dev->dev_private;
1425         struct drm_crtc *crtc;
1426         int srwm = 1;
1427         int cursor_sr = 16;
1428
1429         /* Calc sr entries for one plane configs */
1430         crtc = single_enabled_crtc(dev);
1431         if (crtc) {
1432                 /* self-refresh has much higher latency */
1433                 static const int sr_latency_ns = 12000;
1434                 const struct drm_display_mode *adjusted_mode =
1435                         &to_intel_crtc(crtc)->config.adjusted_mode;
1436                 int clock = adjusted_mode->crtc_clock;
1437                 int htotal = adjusted_mode->crtc_htotal;
1438                 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1439                 int pixel_size = crtc->fb->bits_per_pixel / 8;
1440                 unsigned long line_time_us;
1441                 int entries;
1442
1443                 line_time_us = ((htotal * 1000) / clock);
1444
1445                 /* Use ns/us then divide to preserve precision */
1446                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1447                         pixel_size * hdisplay;
1448                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1449                 srwm = I965_FIFO_SIZE - entries;
1450                 if (srwm < 0)
1451                         srwm = 1;
1452                 srwm &= 0x1ff;
1453                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1454                               entries, srwm);
1455
1456                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1457                         pixel_size * 64;
1458                 entries = DIV_ROUND_UP(entries,
1459                                           i965_cursor_wm_info.cacheline_size);
1460                 cursor_sr = i965_cursor_wm_info.fifo_size -
1461                         (entries + i965_cursor_wm_info.guard_size);
1462
1463                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1464                         cursor_sr = i965_cursor_wm_info.max_wm;
1465
1466                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1467                               "cursor %d\n", srwm, cursor_sr);
1468
1469                 if (IS_CRESTLINE(dev))
1470                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1471         } else {
1472                 /* Turn off self refresh if both pipes are enabled */
1473                 if (IS_CRESTLINE(dev))
1474                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1475                                    & ~FW_BLC_SELF_EN);
1476         }
1477
1478         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1479                       srwm);
1480
1481         /* 965 has limitations... */
1482         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1483                    (8 << 16) | (8 << 8) | (8 << 0));
1484         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1485         /* update cursor SR watermark */
1486         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1487 }
1488
1489 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1490 {
1491         struct drm_device *dev = unused_crtc->dev;
1492         struct drm_i915_private *dev_priv = dev->dev_private;
1493         const struct intel_watermark_params *wm_info;
1494         uint32_t fwater_lo;
1495         uint32_t fwater_hi;
1496         int cwm, srwm = 1;
1497         int fifo_size;
1498         int planea_wm, planeb_wm;
1499         struct drm_crtc *crtc, *enabled = NULL;
1500
1501         if (IS_I945GM(dev))
1502                 wm_info = &i945_wm_info;
1503         else if (!IS_GEN2(dev))
1504                 wm_info = &i915_wm_info;
1505         else
1506                 wm_info = &i830_wm_info;
1507
1508         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1509         crtc = intel_get_crtc_for_plane(dev, 0);
1510         if (intel_crtc_active(crtc)) {
1511                 const struct drm_display_mode *adjusted_mode;
1512                 int cpp = crtc->fb->bits_per_pixel / 8;
1513                 if (IS_GEN2(dev))
1514                         cpp = 4;
1515
1516                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1517                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1518                                                wm_info, fifo_size, cpp,
1519                                                latency_ns);
1520                 enabled = crtc;
1521         } else
1522                 planea_wm = fifo_size - wm_info->guard_size;
1523
1524         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1525         crtc = intel_get_crtc_for_plane(dev, 1);
1526         if (intel_crtc_active(crtc)) {
1527                 const struct drm_display_mode *adjusted_mode;
1528                 int cpp = crtc->fb->bits_per_pixel / 8;
1529                 if (IS_GEN2(dev))
1530                         cpp = 4;
1531
1532                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1533                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1534                                                wm_info, fifo_size, cpp,
1535                                                latency_ns);
1536                 if (enabled == NULL)
1537                         enabled = crtc;
1538                 else
1539                         enabled = NULL;
1540         } else
1541                 planeb_wm = fifo_size - wm_info->guard_size;
1542
1543         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1544
1545         /*
1546          * Overlay gets an aggressive default since video jitter is bad.
1547          */
1548         cwm = 2;
1549
1550         /* Play safe and disable self-refresh before adjusting watermarks. */
1551         if (IS_I945G(dev) || IS_I945GM(dev))
1552                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1553         else if (IS_I915GM(dev))
1554                 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_SELF_EN));
1555
1556         /* Calc sr entries for one plane configs */
1557         if (HAS_FW_BLC(dev) && enabled) {
1558                 /* self-refresh has much higher latency */
1559                 static const int sr_latency_ns = 6000;
1560                 const struct drm_display_mode *adjusted_mode =
1561                         &to_intel_crtc(enabled)->config.adjusted_mode;
1562                 int clock = adjusted_mode->crtc_clock;
1563                 int htotal = adjusted_mode->crtc_htotal;
1564                 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
1565                 int pixel_size = enabled->fb->bits_per_pixel / 8;
1566                 unsigned long line_time_us;
1567                 int entries;
1568
1569                 line_time_us = (htotal * 1000) / clock;
1570
1571                 /* Use ns/us then divide to preserve precision */
1572                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1573                         pixel_size * hdisplay;
1574                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1575                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1576                 srwm = wm_info->fifo_size - entries;
1577                 if (srwm < 0)
1578                         srwm = 1;
1579
1580                 if (IS_I945G(dev) || IS_I945GM(dev))
1581                         I915_WRITE(FW_BLC_SELF,
1582                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1583                 else if (IS_I915GM(dev))
1584                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1585         }
1586
1587         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1588                       planea_wm, planeb_wm, cwm, srwm);
1589
1590         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1591         fwater_hi = (cwm & 0x1f);
1592
1593         /* Set request length to 8 cachelines per fetch */
1594         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1595         fwater_hi = fwater_hi | (1 << 8);
1596
1597         I915_WRITE(FW_BLC, fwater_lo);
1598         I915_WRITE(FW_BLC2, fwater_hi);
1599
1600         if (HAS_FW_BLC(dev)) {
1601                 if (enabled) {
1602                         if (IS_I945G(dev) || IS_I945GM(dev))
1603                                 I915_WRITE(FW_BLC_SELF,
1604                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1605                         else if (IS_I915GM(dev))
1606                                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_SELF_EN));
1607                         DRM_DEBUG_KMS("memory self refresh enabled\n");
1608                 } else
1609                         DRM_DEBUG_KMS("memory self refresh disabled\n");
1610         }
1611 }
1612
1613 static void i845_update_wm(struct drm_crtc *unused_crtc)
1614 {
1615         struct drm_device *dev = unused_crtc->dev;
1616         struct drm_i915_private *dev_priv = dev->dev_private;
1617         struct drm_crtc *crtc;
1618         const struct drm_display_mode *adjusted_mode;
1619         uint32_t fwater_lo;
1620         int planea_wm;
1621
1622         crtc = single_enabled_crtc(dev);
1623         if (crtc == NULL)
1624                 return;
1625
1626         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1627         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1628                                        &i845_wm_info,
1629                                        dev_priv->display.get_fifo_size(dev, 0),
1630                                        4, latency_ns);
1631         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1632         fwater_lo |= (3<<8) | planea_wm;
1633
1634         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1635
1636         I915_WRITE(FW_BLC, fwater_lo);
1637 }
1638
1639 static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1640                                     struct drm_crtc *crtc)
1641 {
1642         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1643         uint32_t pixel_rate;
1644
1645         pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
1646
1647         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1648          * adjust the pixel_rate here. */
1649
1650         if (intel_crtc->config.pch_pfit.enabled) {
1651                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1652                 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
1653
1654                 pipe_w = intel_crtc->config.pipe_src_w;
1655                 pipe_h = intel_crtc->config.pipe_src_h;
1656                 pfit_w = (pfit_size >> 16) & 0xFFFF;
1657                 pfit_h = pfit_size & 0xFFFF;
1658                 if (pipe_w < pfit_w)
1659                         pipe_w = pfit_w;
1660                 if (pipe_h < pfit_h)
1661                         pipe_h = pfit_h;
1662
1663                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1664                                      pfit_w * pfit_h);
1665         }
1666
1667         return pixel_rate;
1668 }
1669
1670 /* latency must be in 0.1us units. */
1671 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
1672                                uint32_t latency)
1673 {
1674         uint64_t ret;
1675
1676         if (WARN(latency == 0, "Latency value missing\n"))
1677                 return UINT_MAX;
1678
1679         ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1680         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1681
1682         return ret;
1683 }
1684
1685 /* latency must be in 0.1us units. */
1686 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1687                                uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1688                                uint32_t latency)
1689 {
1690         uint32_t ret;
1691
1692         if (WARN(latency == 0, "Latency value missing\n"))
1693                 return UINT_MAX;
1694
1695         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1696         ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1697         ret = DIV_ROUND_UP(ret, 64) + 2;
1698         return ret;
1699 }
1700
1701 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1702                            uint8_t bytes_per_pixel)
1703 {
1704         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1705 }
1706
1707 struct ilk_pipe_wm_parameters {
1708         bool active;
1709         uint32_t pipe_htotal;
1710         uint32_t pixel_rate;
1711         struct intel_plane_wm_parameters pri;
1712         struct intel_plane_wm_parameters spr;
1713         struct intel_plane_wm_parameters cur;
1714 };
1715
1716 struct ilk_wm_maximums {
1717         uint16_t pri;
1718         uint16_t spr;
1719         uint16_t cur;
1720         uint16_t fbc;
1721 };
1722
1723 /* used in computing the new watermarks state */
1724 struct intel_wm_config {
1725         unsigned int num_pipes_active;
1726         bool sprites_enabled;
1727         bool sprites_scaled;
1728 };
1729
1730 /*
1731  * For both WM_PIPE and WM_LP.
1732  * mem_value must be in 0.1us units.
1733  */
1734 static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
1735                                    uint32_t mem_value,
1736                                    bool is_lp)
1737 {
1738         uint32_t method1, method2;
1739
1740         if (!params->active || !params->pri.enabled)
1741                 return 0;
1742
1743         method1 = ilk_wm_method1(params->pixel_rate,
1744                                  params->pri.bytes_per_pixel,
1745                                  mem_value);
1746
1747         if (!is_lp)
1748                 return method1;
1749
1750         method2 = ilk_wm_method2(params->pixel_rate,
1751                                  params->pipe_htotal,
1752                                  params->pri.horiz_pixels,
1753                                  params->pri.bytes_per_pixel,
1754                                  mem_value);
1755
1756         return min(method1, method2);
1757 }
1758
1759 /*
1760  * For both WM_PIPE and WM_LP.
1761  * mem_value must be in 0.1us units.
1762  */
1763 static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
1764                                    uint32_t mem_value)
1765 {
1766         uint32_t method1, method2;
1767
1768         if (!params->active || !params->spr.enabled)
1769                 return 0;
1770
1771         method1 = ilk_wm_method1(params->pixel_rate,
1772                                  params->spr.bytes_per_pixel,
1773                                  mem_value);
1774         method2 = ilk_wm_method2(params->pixel_rate,
1775                                  params->pipe_htotal,
1776                                  params->spr.horiz_pixels,
1777                                  params->spr.bytes_per_pixel,
1778                                  mem_value);
1779         return min(method1, method2);
1780 }
1781
1782 /*
1783  * For both WM_PIPE and WM_LP.
1784  * mem_value must be in 0.1us units.
1785  */
1786 static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
1787                                    uint32_t mem_value)
1788 {
1789         if (!params->active || !params->cur.enabled)
1790                 return 0;
1791
1792         return ilk_wm_method2(params->pixel_rate,
1793                               params->pipe_htotal,
1794                               params->cur.horiz_pixels,
1795                               params->cur.bytes_per_pixel,
1796                               mem_value);
1797 }
1798
1799 /* Only for WM_LP. */
1800 static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1801                                    uint32_t pri_val)
1802 {
1803         if (!params->active || !params->pri.enabled)
1804                 return 0;
1805
1806         return ilk_wm_fbc(pri_val,
1807                           params->pri.horiz_pixels,
1808                           params->pri.bytes_per_pixel);
1809 }
1810
1811 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1812 {
1813         if (INTEL_INFO(dev)->gen >= 8)
1814                 return 3072;
1815         else if (INTEL_INFO(dev)->gen >= 7)
1816                 return 768;
1817         else
1818                 return 512;
1819 }
1820
1821 /* Calculate the maximum primary/sprite plane watermark */
1822 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1823                                      int level,
1824                                      const struct intel_wm_config *config,
1825                                      enum intel_ddb_partitioning ddb_partitioning,
1826                                      bool is_sprite)
1827 {
1828         unsigned int fifo_size = ilk_display_fifo_size(dev);
1829         unsigned int max;
1830
1831         /* if sprites aren't enabled, sprites get nothing */
1832         if (is_sprite && !config->sprites_enabled)
1833                 return 0;
1834
1835         /* HSW allows LP1+ watermarks even with multiple pipes */
1836         if (level == 0 || config->num_pipes_active > 1) {
1837                 fifo_size /= INTEL_INFO(dev)->num_pipes;
1838
1839                 /*
1840                  * For some reason the non self refresh
1841                  * FIFO size is only half of the self
1842                  * refresh FIFO size on ILK/SNB.
1843                  */
1844                 if (INTEL_INFO(dev)->gen <= 6)
1845                         fifo_size /= 2;
1846         }
1847
1848         if (config->sprites_enabled) {
1849                 /* level 0 is always calculated with 1:1 split */
1850                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1851                         if (is_sprite)
1852                                 fifo_size *= 5;
1853                         fifo_size /= 6;
1854                 } else {
1855                         fifo_size /= 2;
1856                 }
1857         }
1858
1859         /* clamp to max that the registers can hold */
1860         if (INTEL_INFO(dev)->gen >= 8)
1861                 max = level == 0 ? 255 : 2047;
1862         else if (INTEL_INFO(dev)->gen >= 7)
1863                 /* IVB/HSW primary/sprite plane watermarks */
1864                 max = level == 0 ? 127 : 1023;
1865         else if (!is_sprite)
1866                 /* ILK/SNB primary plane watermarks */
1867                 max = level == 0 ? 127 : 511;
1868         else
1869                 /* ILK/SNB sprite plane watermarks */
1870                 max = level == 0 ? 63 : 255;
1871
1872         return min(fifo_size, max);
1873 }
1874
1875 /* Calculate the maximum cursor plane watermark */
1876 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1877                                       int level,
1878                                       const struct intel_wm_config *config)
1879 {
1880         /* HSW LP1+ watermarks w/ multiple pipes */
1881         if (level > 0 && config->num_pipes_active > 1)
1882                 return 64;
1883
1884         /* otherwise just report max that registers can hold */
1885         if (INTEL_INFO(dev)->gen >= 7)
1886                 return level == 0 ? 63 : 255;
1887         else
1888                 return level == 0 ? 31 : 63;
1889 }
1890
1891 /* Calculate the maximum FBC watermark */
1892 static unsigned int ilk_fbc_wm_max(const struct drm_device *dev)
1893 {
1894         /* max that registers can hold */
1895         if (INTEL_INFO(dev)->gen >= 8)
1896                 return 31;
1897         else
1898                 return 15;
1899 }
1900
1901 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1902                                     int level,
1903                                     const struct intel_wm_config *config,
1904                                     enum intel_ddb_partitioning ddb_partitioning,
1905                                     struct ilk_wm_maximums *max)
1906 {
1907         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1908         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1909         max->cur = ilk_cursor_wm_max(dev, level, config);
1910         max->fbc = ilk_fbc_wm_max(dev);
1911 }
1912
1913 static bool ilk_validate_wm_level(int level,
1914                                   const struct ilk_wm_maximums *max,
1915                                   struct intel_wm_level *result)
1916 {
1917         bool ret;
1918
1919         /* already determined to be invalid? */
1920         if (!result->enable)
1921                 return false;
1922
1923         result->enable = result->pri_val <= max->pri &&
1924                          result->spr_val <= max->spr &&
1925                          result->cur_val <= max->cur;
1926
1927         ret = result->enable;
1928
1929         /*
1930          * HACK until we can pre-compute everything,
1931          * and thus fail gracefully if LP0 watermarks
1932          * are exceeded...
1933          */
1934         if (level == 0 && !result->enable) {
1935                 if (result->pri_val > max->pri)
1936                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1937                                       level, result->pri_val, max->pri);
1938                 if (result->spr_val > max->spr)
1939                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1940                                       level, result->spr_val, max->spr);
1941                 if (result->cur_val > max->cur)
1942                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1943                                       level, result->cur_val, max->cur);
1944
1945                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1946                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1947                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1948                 result->enable = true;
1949         }
1950
1951         return ret;
1952 }
1953
1954 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
1955                                  int level,
1956                                  const struct ilk_pipe_wm_parameters *p,
1957                                  struct intel_wm_level *result)
1958 {
1959         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1960         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1961         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1962
1963         /* WM1+ latency values stored in 0.5us units */
1964         if (level > 0) {
1965                 pri_latency *= 5;
1966                 spr_latency *= 5;
1967                 cur_latency *= 5;
1968         }
1969
1970         result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
1971         result->spr_val = ilk_compute_spr_wm(p, spr_latency);
1972         result->cur_val = ilk_compute_cur_wm(p, cur_latency);
1973         result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
1974         result->enable = true;
1975 }
1976
1977 static uint32_t
1978 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1979 {
1980         struct drm_i915_private *dev_priv = dev->dev_private;
1981         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1982         struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
1983         u32 linetime, ips_linetime;
1984
1985         if (!intel_crtc_active(crtc))
1986                 return 0;
1987
1988         /* The WM are computed with base on how long it takes to fill a single
1989          * row at the given clock rate, multiplied by 8.
1990          * */
1991         linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
1992                                      mode->crtc_clock);
1993         ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
1994                                          intel_ddi_get_cdclk_freq(dev_priv));
1995
1996         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
1997                PIPE_WM_LINETIME_TIME(linetime);
1998 }
1999
2000 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2001 {
2002         struct drm_i915_private *dev_priv = dev->dev_private;
2003
2004         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2005                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2006
2007                 wm[0] = (sskpd >> 56) & 0xFF;
2008                 if (wm[0] == 0)
2009                         wm[0] = sskpd & 0xF;
2010                 wm[1] = (sskpd >> 4) & 0xFF;
2011                 wm[2] = (sskpd >> 12) & 0xFF;
2012                 wm[3] = (sskpd >> 20) & 0x1FF;
2013                 wm[4] = (sskpd >> 32) & 0x1FF;
2014         } else if (INTEL_INFO(dev)->gen >= 6) {
2015                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2016
2017                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2018                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2019                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2020                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2021         } else if (INTEL_INFO(dev)->gen >= 5) {
2022                 uint32_t mltr = I915_READ(MLTR_ILK);
2023
2024                 /* ILK primary LP0 latency is 700 ns */
2025                 wm[0] = 7;
2026                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2027                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2028         }
2029 }
2030
2031 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2032 {
2033         /* ILK sprite LP0 latency is 1300 ns */
2034         if (INTEL_INFO(dev)->gen == 5)
2035                 wm[0] = 13;
2036 }
2037
2038 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2039 {
2040         /* ILK cursor LP0 latency is 1300 ns */
2041         if (INTEL_INFO(dev)->gen == 5)
2042                 wm[0] = 13;
2043
2044         /* WaDoubleCursorLP3Latency:ivb */
2045         if (IS_IVYBRIDGE(dev))
2046                 wm[3] *= 2;
2047 }
2048
2049 static int ilk_wm_max_level(const struct drm_device *dev)
2050 {
2051         /* how many WM levels are we expecting */
2052         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2053                 return 4;
2054         else if (INTEL_INFO(dev)->gen >= 6)
2055                 return 3;
2056         else
2057                 return 2;
2058 }
2059
2060 static void intel_print_wm_latency(struct drm_device *dev,
2061                                    const char *name,
2062                                    const uint16_t wm[5])
2063 {
2064         int level, max_level = ilk_wm_max_level(dev);
2065
2066         for (level = 0; level <= max_level; level++) {
2067                 unsigned int latency = wm[level];
2068
2069                 if (latency == 0) {
2070                         DRM_ERROR("%s WM%d latency not provided\n",
2071                                   name, level);
2072                         continue;
2073                 }
2074
2075                 /* WM1+ latency values in 0.5us units */
2076                 if (level > 0)
2077                         latency *= 5;
2078
2079                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2080                               name, level, wm[level],
2081                               latency / 10, latency % 10);
2082         }
2083 }
2084
2085 static void intel_setup_wm_latency(struct drm_device *dev)
2086 {
2087         struct drm_i915_private *dev_priv = dev->dev_private;
2088
2089         intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2090
2091         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2092                sizeof(dev_priv->wm.pri_latency));
2093         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2094                sizeof(dev_priv->wm.pri_latency));
2095
2096         intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2097         intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2098
2099         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2100         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2101         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2102 }
2103
2104 static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2105                                       struct ilk_pipe_wm_parameters *p,
2106                                       struct intel_wm_config *config)
2107 {
2108         struct drm_device *dev = crtc->dev;
2109         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2110         enum pipe pipe = intel_crtc->pipe;
2111         struct drm_plane *plane;
2112
2113         p->active = intel_crtc_active(crtc);
2114         if (p->active) {
2115                 p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
2116                 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2117                 p->pri.bytes_per_pixel = crtc->fb->bits_per_pixel / 8;
2118                 p->cur.bytes_per_pixel = 4;
2119                 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2120                 p->cur.horiz_pixels = 64;
2121                 /* TODO: for now, assume primary and cursor planes are always enabled. */
2122                 p->pri.enabled = true;
2123                 p->cur.enabled = true;
2124         }
2125
2126         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
2127                 config->num_pipes_active += intel_crtc_active(crtc);
2128
2129         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2130                 struct intel_plane *intel_plane = to_intel_plane(plane);
2131
2132                 if (intel_plane->pipe == pipe)
2133                         p->spr = intel_plane->wm;
2134
2135                 config->sprites_enabled |= intel_plane->wm.enabled;
2136                 config->sprites_scaled |= intel_plane->wm.scaled;
2137         }
2138 }
2139
2140 /* Compute new watermarks for the pipe */
2141 static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2142                                   const struct ilk_pipe_wm_parameters *params,
2143                                   struct intel_pipe_wm *pipe_wm)
2144 {
2145         struct drm_device *dev = crtc->dev;
2146         const struct drm_i915_private *dev_priv = dev->dev_private;
2147         int level, max_level = ilk_wm_max_level(dev);
2148         /* LP0 watermark maximums depend on this pipe alone */
2149         struct intel_wm_config config = {
2150                 .num_pipes_active = 1,
2151                 .sprites_enabled = params->spr.enabled,
2152                 .sprites_scaled = params->spr.scaled,
2153         };
2154         struct ilk_wm_maximums max;
2155
2156         /* LP0 watermarks always use 1/2 DDB partitioning */
2157         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2158
2159         /* ILK/SNB: LP2+ watermarks only w/o sprites */
2160         if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2161                 max_level = 1;
2162
2163         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2164         if (params->spr.scaled)
2165                 max_level = 0;
2166
2167         for (level = 0; level <= max_level; level++)
2168                 ilk_compute_wm_level(dev_priv, level, params,
2169                                      &pipe_wm->wm[level]);
2170
2171         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2172                 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2173
2174         /* At least LP0 must be valid */
2175         return ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]);
2176 }
2177
2178 /*
2179  * Merge the watermarks from all active pipes for a specific level.
2180  */
2181 static void ilk_merge_wm_level(struct drm_device *dev,
2182                                int level,
2183                                struct intel_wm_level *ret_wm)
2184 {
2185         const struct intel_crtc *intel_crtc;
2186
2187         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2188                 const struct intel_wm_level *wm =
2189                         &intel_crtc->wm.active.wm[level];
2190
2191                 if (!wm->enable)
2192                         return;
2193
2194                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2195                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2196                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2197                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2198         }
2199
2200         ret_wm->enable = true;
2201 }
2202
2203 /*
2204  * Merge all low power watermarks for all active pipes.
2205  */
2206 static void ilk_wm_merge(struct drm_device *dev,
2207                          const struct intel_wm_config *config,
2208                          const struct ilk_wm_maximums *max,
2209                          struct intel_pipe_wm *merged)
2210 {
2211         int level, max_level = ilk_wm_max_level(dev);
2212
2213         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2214         if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2215             config->num_pipes_active > 1)
2216                 return;
2217
2218         /* ILK: FBC WM must be disabled always */
2219         merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2220
2221         /* merge each WM1+ level */
2222         for (level = 1; level <= max_level; level++) {
2223                 struct intel_wm_level *wm = &merged->wm[level];
2224
2225                 ilk_merge_wm_level(dev, level, wm);
2226
2227                 if (!ilk_validate_wm_level(level, max, wm))
2228                         break;
2229
2230                 /*
2231                  * The spec says it is preferred to disable
2232                  * FBC WMs instead of disabling a WM level.
2233                  */
2234                 if (wm->fbc_val > max->fbc) {
2235                         merged->fbc_wm_enabled = false;
2236                         wm->fbc_val = 0;
2237                 }
2238         }
2239
2240         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2241         /*
2242          * FIXME this is racy. FBC might get enabled later.
2243          * What we should check here is whether FBC can be
2244          * enabled sometime later.
2245          */
2246         if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2247                 for (level = 2; level <= max_level; level++) {
2248                         struct intel_wm_level *wm = &merged->wm[level];
2249
2250                         wm->enable = false;
2251                 }
2252         }
2253 }
2254
2255 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2256 {
2257         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2258         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2259 }
2260
2261 /* The value we need to program into the WM_LPx latency field */
2262 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2263 {
2264         struct drm_i915_private *dev_priv = dev->dev_private;
2265
2266         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2267                 return 2 * level;
2268         else
2269                 return dev_priv->wm.pri_latency[level];
2270 }
2271
2272 static void ilk_compute_wm_results(struct drm_device *dev,
2273                                    const struct intel_pipe_wm *merged,
2274                                    enum intel_ddb_partitioning partitioning,
2275                                    struct ilk_wm_values *results)
2276 {
2277         struct intel_crtc *intel_crtc;
2278         int level, wm_lp;
2279
2280         results->enable_fbc_wm = merged->fbc_wm_enabled;
2281         results->partitioning = partitioning;
2282
2283         /* LP1+ register values */
2284         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2285                 const struct intel_wm_level *r;
2286
2287                 level = ilk_wm_lp_to_level(wm_lp, merged);
2288
2289                 r = &merged->wm[level];
2290                 if (!r->enable)
2291                         break;
2292
2293                 results->wm_lp[wm_lp - 1] = WM3_LP_EN |
2294                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2295                         (r->pri_val << WM1_LP_SR_SHIFT) |
2296                         r->cur_val;
2297
2298                 if (INTEL_INFO(dev)->gen >= 8)
2299                         results->wm_lp[wm_lp - 1] |=
2300                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2301                 else
2302                         results->wm_lp[wm_lp - 1] |=
2303                                 r->fbc_val << WM1_LP_FBC_SHIFT;
2304
2305                 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2306                         WARN_ON(wm_lp != 1);
2307                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2308                 } else
2309                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2310         }
2311
2312         /* LP0 register values */
2313         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2314                 enum pipe pipe = intel_crtc->pipe;
2315                 const struct intel_wm_level *r =
2316                         &intel_crtc->wm.active.wm[0];
2317
2318                 if (WARN_ON(!r->enable))
2319                         continue;
2320
2321                 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2322
2323                 results->wm_pipe[pipe] =
2324                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2325                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2326                         r->cur_val;
2327         }
2328 }
2329
2330 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2331  * case both are at the same level. Prefer r1 in case they're the same. */
2332 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2333                                                   struct intel_pipe_wm *r1,
2334                                                   struct intel_pipe_wm *r2)
2335 {
2336         int level, max_level = ilk_wm_max_level(dev);
2337         int level1 = 0, level2 = 0;
2338
2339         for (level = 1; level <= max_level; level++) {
2340                 if (r1->wm[level].enable)
2341                         level1 = level;
2342                 if (r2->wm[level].enable)
2343                         level2 = level;
2344         }
2345
2346         if (level1 == level2) {
2347                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2348                         return r2;
2349                 else
2350                         return r1;
2351         } else if (level1 > level2) {
2352                 return r1;
2353         } else {
2354                 return r2;
2355         }
2356 }
2357
2358 /* dirty bits used to track which watermarks need changes */
2359 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2360 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2361 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2362 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2363 #define WM_DIRTY_FBC (1 << 24)
2364 #define WM_DIRTY_DDB (1 << 25)
2365
2366 static unsigned int ilk_compute_wm_dirty(struct drm_device *dev,
2367                                          const struct ilk_wm_values *old,
2368                                          const struct ilk_wm_values *new)
2369 {
2370         unsigned int dirty = 0;
2371         enum pipe pipe;
2372         int wm_lp;
2373
2374         for_each_pipe(pipe) {
2375                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2376                         dirty |= WM_DIRTY_LINETIME(pipe);
2377                         /* Must disable LP1+ watermarks too */
2378                         dirty |= WM_DIRTY_LP_ALL;
2379                 }
2380
2381                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2382                         dirty |= WM_DIRTY_PIPE(pipe);
2383                         /* Must disable LP1+ watermarks too */
2384                         dirty |= WM_DIRTY_LP_ALL;
2385                 }
2386         }
2387
2388         if (old->enable_fbc_wm != new->enable_fbc_wm) {
2389                 dirty |= WM_DIRTY_FBC;
2390                 /* Must disable LP1+ watermarks too */
2391                 dirty |= WM_DIRTY_LP_ALL;
2392         }
2393
2394         if (old->partitioning != new->partitioning) {
2395                 dirty |= WM_DIRTY_DDB;
2396                 /* Must disable LP1+ watermarks too */
2397                 dirty |= WM_DIRTY_LP_ALL;
2398         }
2399
2400         /* LP1+ watermarks already deemed dirty, no need to continue */
2401         if (dirty & WM_DIRTY_LP_ALL)
2402                 return dirty;
2403
2404         /* Find the lowest numbered LP1+ watermark in need of an update... */
2405         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2406                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2407                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2408                         break;
2409         }
2410
2411         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2412         for (; wm_lp <= 3; wm_lp++)
2413                 dirty |= WM_DIRTY_LP(wm_lp);
2414
2415         return dirty;
2416 }
2417
2418 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2419                                unsigned int dirty)
2420 {
2421         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2422         bool changed = false;
2423
2424         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2425                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2426                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2427                 changed = true;
2428         }
2429         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2430                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2431                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2432                 changed = true;
2433         }
2434         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2435                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2436                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2437                 changed = true;
2438         }
2439
2440         /*
2441          * Don't touch WM1S_LP_EN here.
2442          * Doing so could cause underruns.
2443          */
2444
2445         return changed;
2446 }
2447
2448 /*
2449  * The spec says we shouldn't write when we don't need, because every write
2450  * causes WMs to be re-evaluated, expending some power.
2451  */
2452 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2453                                 struct ilk_wm_values *results)
2454 {
2455         struct drm_device *dev = dev_priv->dev;
2456         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2457         unsigned int dirty;
2458         uint32_t val;
2459
2460         dirty = ilk_compute_wm_dirty(dev, previous, results);
2461         if (!dirty)
2462                 return;
2463
2464         _ilk_disable_lp_wm(dev_priv, dirty);
2465
2466         if (dirty & WM_DIRTY_PIPE(PIPE_A))
2467                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2468         if (dirty & WM_DIRTY_PIPE(PIPE_B))
2469                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2470         if (dirty & WM_DIRTY_PIPE(PIPE_C))
2471                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2472
2473         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2474                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2475         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2476                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2477         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2478                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2479
2480         if (dirty & WM_DIRTY_DDB) {
2481                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2482                         val = I915_READ(WM_MISC);
2483                         if (results->partitioning == INTEL_DDB_PART_1_2)
2484                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
2485                         else
2486                                 val |= WM_MISC_DATA_PARTITION_5_6;
2487                         I915_WRITE(WM_MISC, val);
2488                 } else {
2489                         val = I915_READ(DISP_ARB_CTL2);
2490                         if (results->partitioning == INTEL_DDB_PART_1_2)
2491                                 val &= ~DISP_DATA_PARTITION_5_6;
2492                         else
2493                                 val |= DISP_DATA_PARTITION_5_6;
2494                         I915_WRITE(DISP_ARB_CTL2, val);
2495                 }
2496         }
2497
2498         if (dirty & WM_DIRTY_FBC) {
2499                 val = I915_READ(DISP_ARB_CTL);
2500                 if (results->enable_fbc_wm)
2501                         val &= ~DISP_FBC_WM_DIS;
2502                 else
2503                         val |= DISP_FBC_WM_DIS;
2504                 I915_WRITE(DISP_ARB_CTL, val);
2505         }
2506
2507         if (dirty & WM_DIRTY_LP(1) &&
2508             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2509                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2510
2511         if (INTEL_INFO(dev)->gen >= 7) {
2512                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2513                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2514                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2515                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2516         }
2517
2518         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2519                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2520         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2521                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2522         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2523                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2524
2525         dev_priv->wm.hw = *results;
2526 }
2527
2528 static bool ilk_disable_lp_wm(struct drm_device *dev)
2529 {
2530         struct drm_i915_private *dev_priv = dev->dev_private;
2531
2532         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2533 }
2534
2535 static void ilk_update_wm(struct drm_crtc *crtc)
2536 {
2537         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2538         struct drm_device *dev = crtc->dev;
2539         struct drm_i915_private *dev_priv = dev->dev_private;
2540         struct ilk_wm_maximums max;
2541         struct ilk_pipe_wm_parameters params = {};
2542         struct ilk_wm_values results = {};
2543         enum intel_ddb_partitioning partitioning;
2544         struct intel_pipe_wm pipe_wm = {};
2545         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
2546         struct intel_wm_config config = {};
2547
2548         ilk_compute_wm_parameters(crtc, &params, &config);
2549
2550         intel_compute_pipe_wm(crtc, &params, &pipe_wm);
2551
2552         if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2553                 return;
2554
2555         intel_crtc->wm.active = pipe_wm;
2556
2557         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
2558         ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
2559
2560         /* 5/6 split only in single pipe config on IVB+ */
2561         if (INTEL_INFO(dev)->gen >= 7 &&
2562             config.num_pipes_active == 1 && config.sprites_enabled) {
2563                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
2564                 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
2565
2566                 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
2567         } else {
2568                 best_lp_wm = &lp_wm_1_2;
2569         }
2570
2571         partitioning = (best_lp_wm == &lp_wm_1_2) ?
2572                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
2573
2574         ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
2575
2576         ilk_write_wm_values(dev_priv, &results);
2577 }
2578
2579 static void ilk_update_sprite_wm(struct drm_plane *plane,
2580                                      struct drm_crtc *crtc,
2581                                      uint32_t sprite_width, int pixel_size,
2582                                      bool enabled, bool scaled)
2583 {
2584         struct drm_device *dev = plane->dev;
2585         struct intel_plane *intel_plane = to_intel_plane(plane);
2586
2587         intel_plane->wm.enabled = enabled;
2588         intel_plane->wm.scaled = scaled;
2589         intel_plane->wm.horiz_pixels = sprite_width;
2590         intel_plane->wm.bytes_per_pixel = pixel_size;
2591
2592         /*
2593          * IVB workaround: must disable low power watermarks for at least
2594          * one frame before enabling scaling.  LP watermarks can be re-enabled
2595          * when scaling is disabled.
2596          *
2597          * WaCxSRDisabledForSpriteScaling:ivb
2598          */
2599         if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
2600                 intel_wait_for_vblank(dev, intel_plane->pipe);
2601
2602         ilk_update_wm(crtc);
2603 }
2604
2605 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
2606 {
2607         struct drm_device *dev = crtc->dev;
2608         struct drm_i915_private *dev_priv = dev->dev_private;
2609         struct ilk_wm_values *hw = &dev_priv->wm.hw;
2610         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2611         struct intel_pipe_wm *active = &intel_crtc->wm.active;
2612         enum pipe pipe = intel_crtc->pipe;
2613         static const unsigned int wm0_pipe_reg[] = {
2614                 [PIPE_A] = WM0_PIPEA_ILK,
2615                 [PIPE_B] = WM0_PIPEB_ILK,
2616                 [PIPE_C] = WM0_PIPEC_IVB,
2617         };
2618
2619         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
2620         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2621                 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
2622
2623         if (intel_crtc_active(crtc)) {
2624                 u32 tmp = hw->wm_pipe[pipe];
2625
2626                 /*
2627                  * For active pipes LP0 watermark is marked as
2628                  * enabled, and LP1+ watermaks as disabled since
2629                  * we can't really reverse compute them in case
2630                  * multiple pipes are active.
2631                  */
2632                 active->wm[0].enable = true;
2633                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
2634                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
2635                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
2636                 active->linetime = hw->wm_linetime[pipe];
2637         } else {
2638                 int level, max_level = ilk_wm_max_level(dev);
2639
2640                 /*
2641                  * For inactive pipes, all watermark levels
2642                  * should be marked as enabled but zeroed,
2643                  * which is what we'd compute them to.
2644                  */
2645                 for (level = 0; level <= max_level; level++)
2646                         active->wm[level].enable = true;
2647         }
2648 }
2649
2650 void ilk_wm_get_hw_state(struct drm_device *dev)
2651 {
2652         struct drm_i915_private *dev_priv = dev->dev_private;
2653         struct ilk_wm_values *hw = &dev_priv->wm.hw;
2654         struct drm_crtc *crtc;
2655
2656         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
2657                 ilk_pipe_wm_get_hw_state(crtc);
2658
2659         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
2660         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
2661         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
2662
2663         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
2664         hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2665         hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2666
2667         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2668                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
2669                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2670         else if (IS_IVYBRIDGE(dev))
2671                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
2672                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2673
2674         hw->enable_fbc_wm =
2675                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2676 }
2677
2678 /**
2679  * intel_update_watermarks - update FIFO watermark values based on current modes
2680  *
2681  * Calculate watermark values for the various WM regs based on current mode
2682  * and plane configuration.
2683  *
2684  * There are several cases to deal with here:
2685  *   - normal (i.e. non-self-refresh)
2686  *   - self-refresh (SR) mode
2687  *   - lines are large relative to FIFO size (buffer can hold up to 2)
2688  *   - lines are small relative to FIFO size (buffer can hold more than 2
2689  *     lines), so need to account for TLB latency
2690  *
2691  *   The normal calculation is:
2692  *     watermark = dotclock * bytes per pixel * latency
2693  *   where latency is platform & configuration dependent (we assume pessimal
2694  *   values here).
2695  *
2696  *   The SR calculation is:
2697  *     watermark = (trunc(latency/line time)+1) * surface width *
2698  *       bytes per pixel
2699  *   where
2700  *     line time = htotal / dotclock
2701  *     surface width = hdisplay for normal plane and 64 for cursor
2702  *   and latency is assumed to be high, as above.
2703  *
2704  * The final value programmed to the register should always be rounded up,
2705  * and include an extra 2 entries to account for clock crossings.
2706  *
2707  * We don't use the sprite, so we can ignore that.  And on Crestline we have
2708  * to set the non-SR watermarks to 8.
2709  */
2710 void intel_update_watermarks(struct drm_crtc *crtc)
2711 {
2712         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
2713
2714         if (dev_priv->display.update_wm)
2715                 dev_priv->display.update_wm(crtc);
2716 }
2717
2718 void intel_update_sprite_watermarks(struct drm_plane *plane,
2719                                     struct drm_crtc *crtc,
2720                                     uint32_t sprite_width, int pixel_size,
2721                                     bool enabled, bool scaled)
2722 {
2723         struct drm_i915_private *dev_priv = plane->dev->dev_private;
2724
2725         if (dev_priv->display.update_sprite_wm)
2726                 dev_priv->display.update_sprite_wm(plane, crtc, sprite_width,
2727                                                    pixel_size, enabled, scaled);
2728 }
2729
2730 static struct drm_i915_gem_object *
2731 intel_alloc_context_page(struct drm_device *dev)
2732 {
2733         struct drm_i915_gem_object *ctx;
2734         int ret;
2735
2736         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2737
2738         ctx = i915_gem_alloc_object(dev, 4096);
2739         if (!ctx) {
2740                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2741                 return NULL;
2742         }
2743
2744         ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0);
2745         if (ret) {
2746                 DRM_ERROR("failed to pin power context: %d\n", ret);
2747                 goto err_unref;
2748         }
2749
2750         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2751         if (ret) {
2752                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2753                 goto err_unpin;
2754         }
2755
2756         return ctx;
2757
2758 err_unpin:
2759         i915_gem_object_ggtt_unpin(ctx);
2760 err_unref:
2761         drm_gem_object_unreference(&ctx->base);
2762         return NULL;
2763 }
2764
2765 /**
2766  * Lock protecting IPS related data structures
2767  */
2768 DEFINE_SPINLOCK(mchdev_lock);
2769
2770 /* Global for IPS driver to get at the current i915 device. Protected by
2771  * mchdev_lock. */
2772 static struct drm_i915_private *i915_mch_dev;
2773
2774 bool ironlake_set_drps(struct drm_device *dev, u8 val)
2775 {
2776         struct drm_i915_private *dev_priv = dev->dev_private;
2777         u16 rgvswctl;
2778
2779         assert_spin_locked(&mchdev_lock);
2780
2781         rgvswctl = I915_READ16(MEMSWCTL);
2782         if (rgvswctl & MEMCTL_CMD_STS) {
2783                 DRM_DEBUG("gpu busy, RCS change rejected\n");
2784                 return false; /* still busy with another command */
2785         }
2786
2787         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2788                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2789         I915_WRITE16(MEMSWCTL, rgvswctl);
2790         POSTING_READ16(MEMSWCTL);
2791
2792         rgvswctl |= MEMCTL_CMD_STS;
2793         I915_WRITE16(MEMSWCTL, rgvswctl);
2794
2795         return true;
2796 }
2797
2798 static void ironlake_enable_drps(struct drm_device *dev)
2799 {
2800         struct drm_i915_private *dev_priv = dev->dev_private;
2801         u32 rgvmodectl = I915_READ(MEMMODECTL);
2802         u8 fmax, fmin, fstart, vstart;
2803
2804         spin_lock_irq(&mchdev_lock);
2805
2806         /* Enable temp reporting */
2807         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2808         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2809
2810         /* 100ms RC evaluation intervals */
2811         I915_WRITE(RCUPEI, 100000);
2812         I915_WRITE(RCDNEI, 100000);
2813
2814         /* Set max/min thresholds to 90ms and 80ms respectively */
2815         I915_WRITE(RCBMAXAVG, 90000);
2816         I915_WRITE(RCBMINAVG, 80000);
2817
2818         I915_WRITE(MEMIHYST, 1);
2819
2820         /* Set up min, max, and cur for interrupt handling */
2821         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2822         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2823         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2824                 MEMMODE_FSTART_SHIFT;
2825
2826         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2827                 PXVFREQ_PX_SHIFT;
2828
2829         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2830         dev_priv->ips.fstart = fstart;
2831
2832         dev_priv->ips.max_delay = fstart;
2833         dev_priv->ips.min_delay = fmin;
2834         dev_priv->ips.cur_delay = fstart;
2835
2836         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2837                          fmax, fmin, fstart);
2838
2839         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2840
2841         /*
2842          * Interrupts will be enabled in ironlake_irq_postinstall
2843          */
2844
2845         I915_WRITE(VIDSTART, vstart);
2846         POSTING_READ(VIDSTART);
2847
2848         rgvmodectl |= MEMMODE_SWMODE_EN;
2849         I915_WRITE(MEMMODECTL, rgvmodectl);
2850
2851         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2852                 DRM_ERROR("stuck trying to change perf mode\n");
2853         mdelay(1);
2854
2855         ironlake_set_drps(dev, fstart);
2856
2857         dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2858                 I915_READ(0x112e0);
2859         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2860         dev_priv->ips.last_count2 = I915_READ(0x112f4);
2861         getrawmonotonic(&dev_priv->ips.last_time2);
2862
2863         spin_unlock_irq(&mchdev_lock);
2864 }
2865
2866 static void ironlake_disable_drps(struct drm_device *dev)
2867 {
2868         struct drm_i915_private *dev_priv = dev->dev_private;
2869         u16 rgvswctl;
2870
2871         spin_lock_irq(&mchdev_lock);
2872
2873         rgvswctl = I915_READ16(MEMSWCTL);
2874
2875         /* Ack interrupts, disable EFC interrupt */
2876         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
2877         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
2878         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
2879         I915_WRITE(DEIIR, DE_PCU_EVENT);
2880         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
2881
2882         /* Go back to the starting frequency */
2883         ironlake_set_drps(dev, dev_priv->ips.fstart);
2884         mdelay(1);
2885         rgvswctl |= MEMCTL_CMD_STS;
2886         I915_WRITE(MEMSWCTL, rgvswctl);
2887         mdelay(1);
2888
2889         spin_unlock_irq(&mchdev_lock);
2890 }
2891
2892 /* There's a funny hw issue where the hw returns all 0 when reading from
2893  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
2894  * ourselves, instead of doing a rmw cycle (which might result in us clearing
2895  * all limits and the gpu stuck at whatever frequency it is at atm).
2896  */
2897 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2898 {
2899         u32 limits;
2900
2901         /* Only set the down limit when we've reached the lowest level to avoid
2902          * getting more interrupts, otherwise leave this clear. This prevents a
2903          * race in the hw when coming out of rc6: There's a tiny window where
2904          * the hw runs at the minimal clock before selecting the desired
2905          * frequency, if the down threshold expires in that window we will not
2906          * receive a down interrupt. */
2907         limits = dev_priv->rps.max_delay << 24;
2908         if (val <= dev_priv->rps.min_delay)
2909                 limits |= dev_priv->rps.min_delay << 16;
2910
2911         return limits;
2912 }
2913
2914 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
2915 {
2916         int new_power;
2917
2918         new_power = dev_priv->rps.power;
2919         switch (dev_priv->rps.power) {
2920         case LOW_POWER:
2921                 if (val > dev_priv->rps.rpe_delay + 1 && val > dev_priv->rps.cur_delay)
2922                         new_power = BETWEEN;
2923                 break;
2924
2925         case BETWEEN:
2926                 if (val <= dev_priv->rps.rpe_delay && val < dev_priv->rps.cur_delay)
2927                         new_power = LOW_POWER;
2928                 else if (val >= dev_priv->rps.rp0_delay && val > dev_priv->rps.cur_delay)
2929                         new_power = HIGH_POWER;
2930                 break;
2931
2932         case HIGH_POWER:
2933                 if (val < (dev_priv->rps.rp1_delay + dev_priv->rps.rp0_delay) >> 1 && val < dev_priv->rps.cur_delay)
2934                         new_power = BETWEEN;
2935                 break;
2936         }
2937         /* Max/min bins are special */
2938         if (val == dev_priv->rps.min_delay)
2939                 new_power = LOW_POWER;
2940         if (val == dev_priv->rps.max_delay)
2941                 new_power = HIGH_POWER;
2942         if (new_power == dev_priv->rps.power)
2943                 return;
2944
2945         /* Note the units here are not exactly 1us, but 1280ns. */
2946         switch (new_power) {
2947         case LOW_POWER:
2948                 /* Upclock if more than 95% busy over 16ms */
2949                 I915_WRITE(GEN6_RP_UP_EI, 12500);
2950                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
2951
2952                 /* Downclock if less than 85% busy over 32ms */
2953                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
2954                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
2955
2956                 I915_WRITE(GEN6_RP_CONTROL,
2957                            GEN6_RP_MEDIA_TURBO |
2958                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
2959                            GEN6_RP_MEDIA_IS_GFX |
2960                            GEN6_RP_ENABLE |
2961                            GEN6_RP_UP_BUSY_AVG |
2962                            GEN6_RP_DOWN_IDLE_AVG);
2963                 break;
2964
2965         case BETWEEN:
2966                 /* Upclock if more than 90% busy over 13ms */
2967                 I915_WRITE(GEN6_RP_UP_EI, 10250);
2968                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
2969
2970                 /* Downclock if less than 75% busy over 32ms */
2971                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
2972                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
2973
2974                 I915_WRITE(GEN6_RP_CONTROL,
2975                            GEN6_RP_MEDIA_TURBO |
2976                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
2977                            GEN6_RP_MEDIA_IS_GFX |
2978                            GEN6_RP_ENABLE |
2979                            GEN6_RP_UP_BUSY_AVG |
2980                            GEN6_RP_DOWN_IDLE_AVG);
2981                 break;
2982
2983         case HIGH_POWER:
2984                 /* Upclock if more than 85% busy over 10ms */
2985                 I915_WRITE(GEN6_RP_UP_EI, 8000);
2986                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
2987
2988                 /* Downclock if less than 60% busy over 32ms */
2989                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
2990                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
2991
2992                 I915_WRITE(GEN6_RP_CONTROL,
2993                            GEN6_RP_MEDIA_TURBO |
2994                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
2995                            GEN6_RP_MEDIA_IS_GFX |
2996                            GEN6_RP_ENABLE |
2997                            GEN6_RP_UP_BUSY_AVG |
2998                            GEN6_RP_DOWN_IDLE_AVG);
2999                 break;
3000         }
3001
3002         dev_priv->rps.power = new_power;
3003         dev_priv->rps.last_adj = 0;
3004 }
3005
3006 /* gen6_set_rps is called to update the frequency request, but should also be
3007  * called when the range (min_delay and max_delay) is modified so that we can
3008  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
3009 void gen6_set_rps(struct drm_device *dev, u8 val)
3010 {
3011         struct drm_i915_private *dev_priv = dev->dev_private;
3012
3013         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3014         WARN_ON(val > dev_priv->rps.max_delay);
3015         WARN_ON(val < dev_priv->rps.min_delay);
3016
3017         if (val == dev_priv->rps.cur_delay) {
3018                 /* min/max delay may still have been modified so be sure to
3019                  * write the limits value */
3020                 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3021                            gen6_rps_limits(dev_priv, val));
3022
3023                 return;
3024         }
3025
3026         gen6_set_rps_thresholds(dev_priv, val);
3027
3028         if (IS_HASWELL(dev))
3029                 I915_WRITE(GEN6_RPNSWREQ,
3030                            HSW_FREQUENCY(val));
3031         else
3032                 I915_WRITE(GEN6_RPNSWREQ,
3033                            GEN6_FREQUENCY(val) |
3034                            GEN6_OFFSET(0) |
3035                            GEN6_AGGRESSIVE_TURBO);
3036
3037         /* Make sure we continue to get interrupts
3038          * until we hit the minimum or maximum frequencies.
3039          */
3040         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3041                    gen6_rps_limits(dev_priv, val));
3042
3043         POSTING_READ(GEN6_RPNSWREQ);
3044
3045         dev_priv->rps.cur_delay = val;
3046
3047         trace_intel_gpu_freq_change(val * 50);
3048 }
3049
3050 /* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
3051  *
3052  * * If Gfx is Idle, then
3053  * 1. Mask Turbo interrupts
3054  * 2. Bring up Gfx clock
3055  * 3. Change the freq to Rpn and wait till P-Unit updates freq
3056  * 4. Clear the Force GFX CLK ON bit so that Gfx can down
3057  * 5. Unmask Turbo interrupts
3058 */
3059 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
3060 {
3061         /*
3062          * When we are idle.  Drop to min voltage state.
3063          */
3064
3065         if (dev_priv->rps.cur_delay <= dev_priv->rps.min_delay)
3066                 return;
3067
3068         /* Mask turbo interrupt so that they will not come in between */
3069         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3070
3071         /* Bring up the Gfx clock */
3072         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG,
3073                 I915_READ(VLV_GTLC_SURVIVABILITY_REG) |
3074                                 VLV_GFX_CLK_FORCE_ON_BIT);
3075
3076         if (wait_for(((VLV_GFX_CLK_STATUS_BIT &
3077                 I915_READ(VLV_GTLC_SURVIVABILITY_REG)) != 0), 5)) {
3078                         DRM_ERROR("GFX_CLK_ON request timed out\n");
3079                 return;
3080         }
3081
3082         dev_priv->rps.cur_delay = dev_priv->rps.min_delay;
3083
3084         vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ,
3085                                         dev_priv->rps.min_delay);
3086
3087         if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
3088                                 & GENFREQSTATUS) == 0, 5))
3089                 DRM_ERROR("timed out waiting for Punit\n");
3090
3091         /* Release the Gfx clock */
3092         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG,
3093                 I915_READ(VLV_GTLC_SURVIVABILITY_REG) &
3094                                 ~VLV_GFX_CLK_FORCE_ON_BIT);
3095
3096         /* Unmask Up interrupts */
3097         dev_priv->rps.rp_up_masked = true;
3098         gen6_set_pm_mask(dev_priv, GEN6_PM_RP_DOWN_THRESHOLD,
3099                                                 dev_priv->rps.min_delay);
3100 }
3101
3102 void gen6_rps_idle(struct drm_i915_private *dev_priv)
3103 {
3104         struct drm_device *dev = dev_priv->dev;
3105
3106         mutex_lock(&dev_priv->rps.hw_lock);
3107         if (dev_priv->rps.enabled) {
3108                 if (IS_VALLEYVIEW(dev))
3109                         vlv_set_rps_idle(dev_priv);
3110                 else
3111                         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3112                 dev_priv->rps.last_adj = 0;
3113         }
3114         mutex_unlock(&dev_priv->rps.hw_lock);
3115 }
3116
3117 void gen6_rps_boost(struct drm_i915_private *dev_priv)
3118 {
3119         struct drm_device *dev = dev_priv->dev;
3120
3121         mutex_lock(&dev_priv->rps.hw_lock);
3122         if (dev_priv->rps.enabled) {
3123                 if (IS_VALLEYVIEW(dev))
3124                         valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3125                 else
3126                         gen6_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3127                 dev_priv->rps.last_adj = 0;
3128         }
3129         mutex_unlock(&dev_priv->rps.hw_lock);
3130 }
3131
3132 void valleyview_set_rps(struct drm_device *dev, u8 val)
3133 {
3134         struct drm_i915_private *dev_priv = dev->dev_private;
3135
3136         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3137         WARN_ON(val > dev_priv->rps.max_delay);
3138         WARN_ON(val < dev_priv->rps.min_delay);
3139
3140         DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3141                          vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay),
3142                          dev_priv->rps.cur_delay,
3143                          vlv_gpu_freq(dev_priv, val), val);
3144
3145         if (val == dev_priv->rps.cur_delay)
3146                 return;
3147
3148         vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
3149
3150         dev_priv->rps.cur_delay = val;
3151
3152         trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
3153 }
3154
3155 static void gen6_disable_rps_interrupts(struct drm_device *dev)
3156 {
3157         struct drm_i915_private *dev_priv = dev->dev_private;
3158
3159         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3160         I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS);
3161         /* Complete PM interrupt masking here doesn't race with the rps work
3162          * item again unmasking PM interrupts because that is using a different
3163          * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3164          * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3165
3166         spin_lock_irq(&dev_priv->irq_lock);
3167         dev_priv->rps.pm_iir = 0;
3168         spin_unlock_irq(&dev_priv->irq_lock);
3169
3170         I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3171 }
3172
3173 static void gen6_disable_rps(struct drm_device *dev)
3174 {
3175         struct drm_i915_private *dev_priv = dev->dev_private;
3176
3177         I915_WRITE(GEN6_RC_CONTROL, 0);
3178         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
3179
3180         gen6_disable_rps_interrupts(dev);
3181 }
3182
3183 static void valleyview_disable_rps(struct drm_device *dev)
3184 {
3185         struct drm_i915_private *dev_priv = dev->dev_private;
3186
3187         I915_WRITE(GEN6_RC_CONTROL, 0);
3188
3189         gen6_disable_rps_interrupts(dev);
3190
3191         if (dev_priv->vlv_pctx) {
3192                 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3193                 dev_priv->vlv_pctx = NULL;
3194         }
3195 }
3196
3197 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3198 {
3199         DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3200                  (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3201                  (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3202                  (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3203 }
3204
3205 int intel_enable_rc6(const struct drm_device *dev)
3206 {
3207         /* No RC6 before Ironlake */
3208         if (INTEL_INFO(dev)->gen < 5)
3209                 return 0;
3210
3211         /* Respect the kernel parameter if it is set */
3212         if (i915.enable_rc6 >= 0)
3213                 return i915.enable_rc6;
3214
3215         /* Disable RC6 on Ironlake */
3216         if (INTEL_INFO(dev)->gen == 5)
3217                 return 0;
3218
3219         if (IS_IVYBRIDGE(dev))
3220                 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3221
3222         return INTEL_RC6_ENABLE;
3223 }
3224
3225 static void gen6_enable_rps_interrupts(struct drm_device *dev)
3226 {
3227         struct drm_i915_private *dev_priv = dev->dev_private;
3228         u32 enabled_intrs;
3229
3230         spin_lock_irq(&dev_priv->irq_lock);
3231         WARN_ON(dev_priv->rps.pm_iir);
3232         snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
3233         I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3234         spin_unlock_irq(&dev_priv->irq_lock);
3235
3236         /* only unmask PM interrupts we need. Mask all others. */
3237         enabled_intrs = GEN6_PM_RPS_EVENTS;
3238
3239         /* IVB and SNB hard hangs on looping batchbuffer
3240          * if GEN6_PM_UP_EI_EXPIRED is masked.
3241          */
3242         if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
3243                 enabled_intrs |= GEN6_PM_RP_UP_EI_EXPIRED;
3244
3245         I915_WRITE(GEN6_PMINTRMSK, ~enabled_intrs);
3246 }
3247
3248 static void gen8_enable_rps(struct drm_device *dev)
3249 {
3250         struct drm_i915_private *dev_priv = dev->dev_private;
3251         struct intel_ring_buffer *ring;
3252         uint32_t rc6_mask = 0, rp_state_cap;
3253         int unused;
3254
3255         /* 1a: Software RC state - RC0 */
3256         I915_WRITE(GEN6_RC_STATE, 0);
3257
3258         /* 1c & 1d: Get forcewake during program sequence. Although the driver
3259          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
3260         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3261
3262         /* 2a: Disable RC states. */
3263         I915_WRITE(GEN6_RC_CONTROL, 0);
3264
3265         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3266
3267         /* 2b: Program RC6 thresholds.*/
3268         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3269         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3270         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3271         for_each_ring(ring, dev_priv, unused)
3272                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3273         I915_WRITE(GEN6_RC_SLEEP, 0);
3274         I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
3275
3276         /* 3: Enable RC6 */
3277         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3278                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
3279         intel_print_rc6_info(dev, rc6_mask);
3280         I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3281                                     GEN6_RC_CTL_EI_MODE(1) |
3282                                     rc6_mask);
3283
3284         /* 4 Program defaults and thresholds for RPS*/
3285         I915_WRITE(GEN6_RPNSWREQ, HSW_FREQUENCY(10)); /* Request 500 MHz */
3286         I915_WRITE(GEN6_RC_VIDEO_FREQ, HSW_FREQUENCY(12)); /* Request 600 MHz */
3287         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
3288         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
3289
3290         /* Docs recommend 900MHz, and 300 MHz respectively */
3291         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3292                    dev_priv->rps.max_delay << 24 |
3293                    dev_priv->rps.min_delay << 16);
3294
3295         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
3296         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
3297         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
3298         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
3299
3300         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3301
3302         /* 5: Enable RPS */
3303         I915_WRITE(GEN6_RP_CONTROL,
3304                    GEN6_RP_MEDIA_TURBO |
3305                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
3306                    GEN6_RP_MEDIA_IS_GFX |
3307                    GEN6_RP_ENABLE |
3308                    GEN6_RP_UP_BUSY_AVG |
3309                    GEN6_RP_DOWN_IDLE_AVG);
3310
3311         /* 6: Ring frequency + overclocking (our driver does this later */
3312
3313         gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
3314
3315         gen6_enable_rps_interrupts(dev);
3316
3317         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3318 }
3319
3320 static void gen6_enable_rps(struct drm_device *dev)
3321 {
3322         struct drm_i915_private *dev_priv = dev->dev_private;
3323         struct intel_ring_buffer *ring;
3324         u32 rp_state_cap, hw_max, hw_min;
3325         u32 gt_perf_status;
3326         u32 rc6vids, pcu_mbox, rc6_mask = 0;
3327         u32 gtfifodbg;
3328         int rc6_mode;
3329         int i, ret;
3330
3331         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3332
3333         /* Here begins a magic sequence of register writes to enable
3334          * auto-downclocking.
3335          *
3336          * Perhaps there might be some value in exposing these to
3337          * userspace...
3338          */
3339         I915_WRITE(GEN6_RC_STATE, 0);
3340
3341         /* Clear the DBG now so we don't confuse earlier errors */
3342         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3343                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3344                 I915_WRITE(GTFIFODBG, gtfifodbg);
3345         }
3346
3347         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3348
3349         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3350         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3351
3352         /* In units of 50MHz */
3353         dev_priv->rps.hw_max = hw_max = rp_state_cap & 0xff;
3354         hw_min = (rp_state_cap >> 16) & 0xff;
3355         dev_priv->rps.rp1_delay = (rp_state_cap >>  8) & 0xff;
3356         dev_priv->rps.rp0_delay = (rp_state_cap >>  0) & 0xff;
3357         dev_priv->rps.rpe_delay = dev_priv->rps.rp1_delay;
3358         dev_priv->rps.cur_delay = 0;
3359
3360         /* Preserve min/max settings in case of re-init */
3361         if (dev_priv->rps.max_delay == 0)
3362                 dev_priv->rps.max_delay = hw_max;
3363
3364         if (dev_priv->rps.min_delay == 0)
3365                 dev_priv->rps.min_delay = hw_min;
3366
3367         /* disable the counters and set deterministic thresholds */
3368         I915_WRITE(GEN6_RC_CONTROL, 0);
3369
3370         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3371         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3372         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3373         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3374         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3375
3376         for_each_ring(ring, dev_priv, i)
3377                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3378
3379         I915_WRITE(GEN6_RC_SLEEP, 0);
3380         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3381         if (IS_IVYBRIDGE(dev))
3382                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3383         else
3384                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
3385         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
3386         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3387
3388         /* Check if we are enabling RC6 */
3389         rc6_mode = intel_enable_rc6(dev_priv->dev);
3390         if (rc6_mode & INTEL_RC6_ENABLE)
3391                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3392
3393         /* We don't use those on Haswell */
3394         if (!IS_HASWELL(dev)) {
3395                 if (rc6_mode & INTEL_RC6p_ENABLE)
3396                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
3397
3398                 if (rc6_mode & INTEL_RC6pp_ENABLE)
3399                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3400         }
3401
3402         intel_print_rc6_info(dev, rc6_mask);
3403
3404         I915_WRITE(GEN6_RC_CONTROL,
3405                    rc6_mask |
3406                    GEN6_RC_CTL_EI_MODE(1) |
3407                    GEN6_RC_CTL_HW_ENABLE);
3408
3409         /* Power down if completely idle for over 50ms */
3410         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
3411         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3412
3413         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
3414         if (!ret) {
3415                 pcu_mbox = 0;
3416                 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3417                 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3418                         DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
3419                                          (dev_priv->rps.max_delay & 0xff) * 50,
3420                                          (pcu_mbox & 0xff) * 50);
3421                         dev_priv->rps.hw_max = pcu_mbox & 0xff;
3422                 }
3423         } else {
3424                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
3425         }
3426
3427         dev_priv->rps.power = HIGH_POWER; /* force a reset */
3428         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3429
3430         gen6_enable_rps_interrupts(dev);
3431
3432         rc6vids = 0;
3433         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3434         if (IS_GEN6(dev) && ret) {
3435                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3436         } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3437                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3438                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3439                 rc6vids &= 0xffff00;
3440                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3441                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3442                 if (ret)
3443                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3444         }
3445
3446         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3447 }
3448
3449 void gen6_update_ring_freq(struct drm_device *dev)
3450 {
3451         struct drm_i915_private *dev_priv = dev->dev_private;
3452         int min_freq = 15;
3453         unsigned int gpu_freq;
3454         unsigned int max_ia_freq, min_ring_freq;
3455         int scaling_factor = 180;
3456         struct cpufreq_policy *policy;
3457
3458         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3459
3460         policy = cpufreq_cpu_get(0);
3461         if (policy) {
3462                 max_ia_freq = policy->cpuinfo.max_freq;
3463                 cpufreq_cpu_put(policy);
3464         } else {
3465                 /*
3466                  * Default to measured freq if none found, PCU will ensure we
3467                  * don't go over
3468                  */
3469                 max_ia_freq = tsc_khz;
3470         }
3471
3472         /* Convert from kHz to MHz */
3473         max_ia_freq /= 1000;
3474
3475         min_ring_freq = I915_READ(DCLK) & 0xf;
3476         /* convert DDR frequency from units of 266.6MHz to bandwidth */
3477         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3478
3479         /*
3480          * For each potential GPU frequency, load a ring frequency we'd like
3481          * to use for memory access.  We do this by specifying the IA frequency
3482          * the PCU should use as a reference to determine the ring frequency.
3483          */
3484         for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
3485              gpu_freq--) {
3486                 int diff = dev_priv->rps.max_delay - gpu_freq;
3487                 unsigned int ia_freq = 0, ring_freq = 0;
3488
3489                 if (INTEL_INFO(dev)->gen >= 8) {
3490                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
3491                         ring_freq = max(min_ring_freq, gpu_freq);
3492                 } else if (IS_HASWELL(dev)) {
3493                         ring_freq = mult_frac(gpu_freq, 5, 4);
3494                         ring_freq = max(min_ring_freq, ring_freq);
3495                         /* leave ia_freq as the default, chosen by cpufreq */
3496                 } else {
3497                         /* On older processors, there is no separate ring
3498                          * clock domain, so in order to boost the bandwidth
3499                          * of the ring, we need to upclock the CPU (ia_freq).
3500                          *
3501                          * For GPU frequencies less than 750MHz,
3502                          * just use the lowest ring freq.
3503                          */
3504                         if (gpu_freq < min_freq)
3505                                 ia_freq = 800;
3506                         else
3507                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3508                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3509                 }
3510
3511                 sandybridge_pcode_write(dev_priv,
3512                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3513                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3514                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3515                                         gpu_freq);
3516         }
3517 }
3518
3519 int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3520 {
3521         u32 val, rp0;
3522
3523         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
3524
3525         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3526         /* Clamp to max */
3527         rp0 = min_t(u32, rp0, 0xea);
3528
3529         return rp0;
3530 }
3531
3532 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3533 {
3534         u32 val, rpe;
3535
3536         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
3537         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
3538         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
3539         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3540
3541         return rpe;
3542 }
3543
3544 int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3545 {
3546         return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
3547 }
3548
3549 static void valleyview_setup_pctx(struct drm_device *dev)
3550 {
3551         struct drm_i915_private *dev_priv = dev->dev_private;
3552         struct drm_i915_gem_object *pctx;
3553         unsigned long pctx_paddr;
3554         u32 pcbr;
3555         int pctx_size = 24*1024;
3556
3557         pcbr = I915_READ(VLV_PCBR);
3558         if (pcbr) {
3559                 /* BIOS set it up already, grab the pre-alloc'd space */
3560                 int pcbr_offset;
3561
3562                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3563                 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3564                                                                       pcbr_offset,
3565                                                                       I915_GTT_OFFSET_NONE,
3566                                                                       pctx_size);
3567                 goto out;
3568         }
3569
3570         /*
3571          * From the Gunit register HAS:
3572          * The Gfx driver is expected to program this register and ensure
3573          * proper allocation within Gfx stolen memory.  For example, this
3574          * register should be programmed such than the PCBR range does not
3575          * overlap with other ranges, such as the frame buffer, protected
3576          * memory, or any other relevant ranges.
3577          */
3578         pctx = i915_gem_object_create_stolen(dev, pctx_size);
3579         if (!pctx) {
3580                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3581                 return;
3582         }
3583
3584         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
3585         I915_WRITE(VLV_PCBR, pctx_paddr);
3586
3587 out:
3588         dev_priv->vlv_pctx = pctx;
3589 }
3590
3591 static void valleyview_enable_rps(struct drm_device *dev)
3592 {
3593         struct drm_i915_private *dev_priv = dev->dev_private;
3594         struct intel_ring_buffer *ring;
3595         u32 gtfifodbg, val, hw_max, hw_min, rc6_mode = 0;
3596         int i;
3597
3598         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3599
3600         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3601                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
3602                                  gtfifodbg);
3603                 I915_WRITE(GTFIFODBG, gtfifodbg);
3604         }
3605
3606         valleyview_setup_pctx(dev);
3607
3608         /* If VLV, Forcewake all wells, else re-direct to regular path */
3609         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3610
3611         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3612         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3613         I915_WRITE(GEN6_RP_UP_EI, 66000);
3614         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
3615
3616         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3617
3618         I915_WRITE(GEN6_RP_CONTROL,
3619                    GEN6_RP_MEDIA_TURBO |
3620                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
3621                    GEN6_RP_MEDIA_IS_GFX |
3622                    GEN6_RP_ENABLE |
3623                    GEN6_RP_UP_BUSY_AVG |
3624                    GEN6_RP_DOWN_IDLE_CONT);
3625
3626         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
3627         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3628         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3629
3630         for_each_ring(ring, dev_priv, i)
3631                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3632
3633         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
3634
3635         /* allows RC6 residency counter to work */
3636         I915_WRITE(VLV_COUNTER_CONTROL,
3637                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
3638                                       VLV_MEDIA_RC6_COUNT_EN |
3639                                       VLV_RENDER_RC6_COUNT_EN));
3640         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3641                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
3642
3643         intel_print_rc6_info(dev, rc6_mode);
3644
3645         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
3646
3647         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
3648
3649         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
3650         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
3651
3652         dev_priv->rps.cur_delay = (val >> 8) & 0xff;
3653         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
3654                          vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay),
3655                          dev_priv->rps.cur_delay);
3656
3657         dev_priv->rps.hw_max = hw_max = valleyview_rps_max_freq(dev_priv);
3658         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3659                          vlv_gpu_freq(dev_priv, hw_max),
3660                          hw_max);
3661
3662         dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv);
3663         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3664                          vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay),
3665                          dev_priv->rps.rpe_delay);
3666
3667         hw_min = valleyview_rps_min_freq(dev_priv);
3668         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3669                          vlv_gpu_freq(dev_priv, hw_min),
3670                          hw_min);
3671
3672         /* Preserve min/max settings in case of re-init */
3673         if (dev_priv->rps.max_delay == 0)
3674                 dev_priv->rps.max_delay = hw_max;
3675
3676         if (dev_priv->rps.min_delay == 0)
3677                 dev_priv->rps.min_delay = hw_min;
3678
3679         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
3680                          vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay),
3681                          dev_priv->rps.rpe_delay);
3682
3683         valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
3684
3685         dev_priv->rps.rp_up_masked = false;
3686         dev_priv->rps.rp_down_masked = false;
3687
3688         gen6_enable_rps_interrupts(dev);
3689
3690         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3691 }
3692
3693 void ironlake_teardown_rc6(struct drm_device *dev)
3694 {
3695         struct drm_i915_private *dev_priv = dev->dev_private;
3696
3697         if (dev_priv->ips.renderctx) {
3698                 i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx);
3699                 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
3700                 dev_priv->ips.renderctx = NULL;
3701         }
3702
3703         if (dev_priv->ips.pwrctx) {
3704                 i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx);
3705                 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
3706                 dev_priv->ips.pwrctx = NULL;
3707         }
3708 }
3709
3710 static void ironlake_disable_rc6(struct drm_device *dev)
3711 {
3712         struct drm_i915_private *dev_priv = dev->dev_private;
3713
3714         if (I915_READ(PWRCTXA)) {
3715                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
3716                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
3717                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
3718                          50);
3719
3720                 I915_WRITE(PWRCTXA, 0);
3721                 POSTING_READ(PWRCTXA);
3722
3723                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3724                 POSTING_READ(RSTDBYCTL);
3725         }
3726 }
3727
3728 static int ironlake_setup_rc6(struct drm_device *dev)
3729 {
3730         struct drm_i915_private *dev_priv = dev->dev_private;
3731
3732         if (dev_priv->ips.renderctx == NULL)
3733                 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
3734         if (!dev_priv->ips.renderctx)
3735                 return -ENOMEM;
3736
3737         if (dev_priv->ips.pwrctx == NULL)
3738                 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
3739         if (!dev_priv->ips.pwrctx) {
3740                 ironlake_teardown_rc6(dev);
3741                 return -ENOMEM;
3742         }
3743
3744         return 0;
3745 }
3746
3747 static void ironlake_enable_rc6(struct drm_device *dev)
3748 {
3749         struct drm_i915_private *dev_priv = dev->dev_private;
3750         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
3751         bool was_interruptible;
3752         int ret;
3753
3754         /* rc6 disabled by default due to repeated reports of hanging during
3755          * boot and resume.
3756          */
3757         if (!intel_enable_rc6(dev))
3758                 return;
3759
3760         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3761
3762         ret = ironlake_setup_rc6(dev);
3763         if (ret)
3764                 return;
3765
3766         was_interruptible = dev_priv->mm.interruptible;
3767         dev_priv->mm.interruptible = false;
3768
3769         /*
3770          * GPU can automatically power down the render unit if given a page
3771          * to save state.
3772          */
3773         ret = intel_ring_begin(ring, 6);
3774         if (ret) {
3775                 ironlake_teardown_rc6(dev);
3776                 dev_priv->mm.interruptible = was_interruptible;
3777                 return;
3778         }
3779
3780         intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
3781         intel_ring_emit(ring, MI_SET_CONTEXT);
3782         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
3783                         MI_MM_SPACE_GTT |
3784                         MI_SAVE_EXT_STATE_EN |
3785                         MI_RESTORE_EXT_STATE_EN |
3786                         MI_RESTORE_INHIBIT);
3787         intel_ring_emit(ring, MI_SUSPEND_FLUSH);
3788         intel_ring_emit(ring, MI_NOOP);
3789         intel_ring_emit(ring, MI_FLUSH);
3790         intel_ring_advance(ring);
3791
3792         /*
3793          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
3794          * does an implicit flush, combined with MI_FLUSH above, it should be
3795          * safe to assume that renderctx is valid
3796          */
3797         ret = intel_ring_idle(ring);
3798         dev_priv->mm.interruptible = was_interruptible;
3799         if (ret) {
3800                 DRM_ERROR("failed to enable ironlake power savings\n");
3801                 ironlake_teardown_rc6(dev);
3802                 return;
3803         }
3804
3805         I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
3806         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3807
3808         intel_print_rc6_info(dev, INTEL_RC6_ENABLE);
3809 }
3810
3811 static unsigned long intel_pxfreq(u32 vidfreq)
3812 {
3813         unsigned long freq;
3814         int div = (vidfreq & 0x3f0000) >> 16;
3815         int post = (vidfreq & 0x3000) >> 12;
3816         int pre = (vidfreq & 0x7);
3817
3818         if (!pre)
3819                 return 0;
3820
3821         freq = ((div * 133333) / ((1<<post) * pre));
3822
3823         return freq;
3824 }
3825
3826 static const struct cparams {
3827         u16 i;
3828         u16 t;
3829         u16 m;
3830         u16 c;
3831 } cparams[] = {
3832         { 1, 1333, 301, 28664 },
3833         { 1, 1066, 294, 24460 },
3834         { 1, 800, 294, 25192 },
3835         { 0, 1333, 276, 27605 },
3836         { 0, 1066, 276, 27605 },
3837         { 0, 800, 231, 23784 },
3838 };
3839
3840 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
3841 {
3842         u64 total_count, diff, ret;
3843         u32 count1, count2, count3, m = 0, c = 0;
3844         unsigned long now = jiffies_to_msecs(jiffies), diff1;
3845         int i;
3846
3847         assert_spin_locked(&mchdev_lock);
3848
3849         diff1 = now - dev_priv->ips.last_time1;
3850
3851         /* Prevent division-by-zero if we are asking too fast.
3852          * Also, we don't get interesting results if we are polling
3853          * faster than once in 10ms, so just return the saved value
3854          * in such cases.
3855          */
3856         if (diff1 <= 10)
3857                 return dev_priv->ips.chipset_power;
3858
3859         count1 = I915_READ(DMIEC);
3860         count2 = I915_READ(DDREC);
3861         count3 = I915_READ(CSIEC);
3862
3863         total_count = count1 + count2 + count3;
3864
3865         /* FIXME: handle per-counter overflow */
3866         if (total_count < dev_priv->ips.last_count1) {
3867                 diff = ~0UL - dev_priv->ips.last_count1;
3868                 diff += total_count;
3869         } else {
3870                 diff = total_count - dev_priv->ips.last_count1;
3871         }
3872
3873         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
3874                 if (cparams[i].i == dev_priv->ips.c_m &&
3875                     cparams[i].t == dev_priv->ips.r_t) {
3876                         m = cparams[i].m;
3877                         c = cparams[i].c;
3878                         break;
3879                 }
3880         }
3881
3882         diff = div_u64(diff, diff1);
3883         ret = ((m * diff) + c);
3884         ret = div_u64(ret, 10);
3885
3886         dev_priv->ips.last_count1 = total_count;
3887         dev_priv->ips.last_time1 = now;
3888
3889         dev_priv->ips.chipset_power = ret;
3890
3891         return ret;
3892 }
3893
3894 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
3895 {
3896         struct drm_device *dev = dev_priv->dev;
3897         unsigned long val;
3898
3899         if (INTEL_INFO(dev)->gen != 5)
3900                 return 0;
3901
3902         spin_lock_irq(&mchdev_lock);
3903
3904         val = __i915_chipset_val(dev_priv);
3905
3906         spin_unlock_irq(&mchdev_lock);
3907
3908         return val;
3909 }
3910
3911 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
3912 {
3913         unsigned long m, x, b;
3914         u32 tsfs;
3915
3916         tsfs = I915_READ(TSFS);
3917
3918         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
3919         x = I915_READ8(TR1);
3920
3921         b = tsfs & TSFS_INTR_MASK;
3922
3923         return ((m * x) / 127) - b;
3924 }
3925
3926 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
3927 {
3928         struct drm_device *dev = dev_priv->dev;
3929         static const struct v_table {
3930                 u16 vd; /* in .1 mil */
3931                 u16 vm; /* in .1 mil */
3932         } v_table[] = {
3933                 { 0, 0, },
3934                 { 375, 0, },
3935                 { 500, 0, },
3936                 { 625, 0, },
3937                 { 750, 0, },
3938                 { 875, 0, },
3939                 { 1000, 0, },
3940                 { 1125, 0, },
3941                 { 4125, 3000, },
3942                 { 4125, 3000, },
3943                 { 4125, 3000, },
3944                 { 4125, 3000, },
3945                 { 4125, 3000, },
3946                 { 4125, 3000, },
3947                 { 4125, 3000, },
3948                 { 4125, 3000, },
3949                 { 4125, 3000, },
3950                 { 4125, 3000, },
3951                 { 4125, 3000, },
3952                 { 4125, 3000, },
3953                 { 4125, 3000, },
3954                 { 4125, 3000, },
3955                 { 4125, 3000, },
3956                 { 4125, 3000, },
3957                 { 4125, 3000, },
3958                 { 4125, 3000, },
3959                 { 4125, 3000, },
3960                 { 4125, 3000, },
3961                 { 4125, 3000, },
3962                 { 4125, 3000, },
3963                 { 4125, 3000, },
3964                 { 4125, 3000, },
3965                 { 4250, 3125, },
3966                 { 4375, 3250, },
3967                 { 4500, 3375, },
3968                 { 4625, 3500, },
3969                 { 4750, 3625, },
3970                 { 4875, 3750, },
3971                 { 5000, 3875, },
3972                 { 5125, 4000, },
3973                 { 5250, 4125, },
3974                 { 5375, 4250, },
3975                 { 5500, 4375, },
3976                 { 5625, 4500, },
3977                 { 5750, 4625, },
3978                 { 5875, 4750, },
3979                 { 6000, 4875, },
3980                 { 6125, 5000, },
3981                 { 6250, 5125, },
3982                 { 6375, 5250, },
3983                 { 6500, 5375, },
3984                 { 6625, 5500, },
3985                 { 6750, 5625, },
3986                 { 6875, 5750, },
3987                 { 7000, 5875, },
3988                 { 7125, 6000, },
3989                 { 7250, 6125, },
3990                 { 7375, 6250, },
3991                 { 7500, 6375, },
3992                 { 7625, 6500, },
3993                 { 7750, 6625, },
3994                 { 7875, 6750, },
3995                 { 8000, 6875, },
3996                 { 8125, 7000, },
3997                 { 8250, 7125, },
3998                 { 8375, 7250, },
3999                 { 8500, 7375, },
4000                 { 8625, 7500, },
4001                 { 8750, 7625, },
4002                 { 8875, 7750, },
4003                 { 9000, 7875, },
4004                 { 9125, 8000, },
4005                 { 9250, 8125, },
4006                 { 9375, 8250, },
4007                 { 9500, 8375, },
4008                 { 9625, 8500, },
4009                 { 9750, 8625, },
4010                 { 9875, 8750, },
4011                 { 10000, 8875, },
4012                 { 10125, 9000, },
4013                 { 10250, 9125, },
4014                 { 10375, 9250, },
4015                 { 10500, 9375, },
4016                 { 10625, 9500, },
4017                 { 10750, 9625, },
4018                 { 10875, 9750, },
4019                 { 11000, 9875, },
4020                 { 11125, 10000, },
4021                 { 11250, 10125, },
4022                 { 11375, 10250, },
4023                 { 11500, 10375, },
4024                 { 11625, 10500, },
4025                 { 11750, 10625, },
4026                 { 11875, 10750, },
4027                 { 12000, 10875, },
4028                 { 12125, 11000, },
4029                 { 12250, 11125, },
4030                 { 12375, 11250, },
4031                 { 12500, 11375, },
4032                 { 12625, 11500, },
4033                 { 12750, 11625, },
4034                 { 12875, 11750, },
4035                 { 13000, 11875, },
4036                 { 13125, 12000, },
4037                 { 13250, 12125, },
4038                 { 13375, 12250, },
4039                 { 13500, 12375, },
4040                 { 13625, 12500, },
4041                 { 13750, 12625, },
4042                 { 13875, 12750, },
4043                 { 14000, 12875, },
4044                 { 14125, 13000, },
4045                 { 14250, 13125, },
4046                 { 14375, 13250, },
4047                 { 14500, 13375, },
4048                 { 14625, 13500, },
4049                 { 14750, 13625, },
4050                 { 14875, 13750, },
4051                 { 15000, 13875, },
4052                 { 15125, 14000, },
4053                 { 15250, 14125, },
4054                 { 15375, 14250, },
4055                 { 15500, 14375, },
4056                 { 15625, 14500, },
4057                 { 15750, 14625, },
4058                 { 15875, 14750, },
4059                 { 16000, 14875, },
4060                 { 16125, 15000, },
4061         };
4062         if (INTEL_INFO(dev)->is_mobile)
4063                 return v_table[pxvid].vm;
4064         else
4065                 return v_table[pxvid].vd;
4066 }
4067
4068 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
4069 {
4070         struct timespec now, diff1;
4071         u64 diff;
4072         unsigned long diffms;
4073         u32 count;
4074
4075         assert_spin_locked(&mchdev_lock);
4076
4077         getrawmonotonic(&now);
4078         diff1 = timespec_sub(now, dev_priv->ips.last_time2);
4079
4080         /* Don't divide by 0 */
4081         diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4082         if (!diffms)
4083                 return;
4084
4085         count = I915_READ(GFXEC);
4086
4087         if (count < dev_priv->ips.last_count2) {
4088                 diff = ~0UL - dev_priv->ips.last_count2;
4089                 diff += count;
4090         } else {
4091                 diff = count - dev_priv->ips.last_count2;
4092         }
4093
4094         dev_priv->ips.last_count2 = count;
4095         dev_priv->ips.last_time2 = now;
4096
4097         /* More magic constants... */
4098         diff = diff * 1181;
4099         diff = div_u64(diff, diffms * 10);
4100         dev_priv->ips.gfx_power = diff;
4101 }
4102
4103 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4104 {
4105         struct drm_device *dev = dev_priv->dev;
4106
4107         if (INTEL_INFO(dev)->gen != 5)
4108                 return;
4109
4110         spin_lock_irq(&mchdev_lock);
4111
4112         __i915_update_gfx_val(dev_priv);
4113
4114         spin_unlock_irq(&mchdev_lock);
4115 }
4116
4117 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
4118 {
4119         unsigned long t, corr, state1, corr2, state2;
4120         u32 pxvid, ext_v;
4121
4122         assert_spin_locked(&mchdev_lock);
4123
4124         pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
4125         pxvid = (pxvid >> 24) & 0x7f;
4126         ext_v = pvid_to_extvid(dev_priv, pxvid);
4127
4128         state1 = ext_v;
4129
4130         t = i915_mch_val(dev_priv);
4131
4132         /* Revel in the empirically derived constants */
4133
4134         /* Correction factor in 1/100000 units */
4135         if (t > 80)
4136                 corr = ((t * 2349) + 135940);
4137         else if (t >= 50)
4138                 corr = ((t * 964) + 29317);
4139         else /* < 50 */
4140                 corr = ((t * 301) + 1004);
4141
4142         corr = corr * ((150142 * state1) / 10000 - 78642);
4143         corr /= 100000;
4144         corr2 = (corr * dev_priv->ips.corr);
4145
4146         state2 = (corr2 * state1) / 10000;
4147         state2 /= 100; /* convert to mW */
4148
4149         __i915_update_gfx_val(dev_priv);
4150
4151         return dev_priv->ips.gfx_power + state2;
4152 }
4153
4154 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4155 {
4156         struct drm_device *dev = dev_priv->dev;
4157         unsigned long val;
4158
4159         if (INTEL_INFO(dev)->gen != 5)
4160                 return 0;
4161
4162         spin_lock_irq(&mchdev_lock);
4163
4164         val = __i915_gfx_val(dev_priv);
4165
4166         spin_unlock_irq(&mchdev_lock);
4167
4168         return val;
4169 }
4170
4171 /**
4172  * i915_read_mch_val - return value for IPS use
4173  *
4174  * Calculate and return a value for the IPS driver to use when deciding whether
4175  * we have thermal and power headroom to increase CPU or GPU power budget.
4176  */
4177 unsigned long i915_read_mch_val(void)
4178 {
4179         struct drm_i915_private *dev_priv;
4180         unsigned long chipset_val, graphics_val, ret = 0;
4181
4182         spin_lock_irq(&mchdev_lock);
4183         if (!i915_mch_dev)
4184                 goto out_unlock;
4185         dev_priv = i915_mch_dev;
4186
4187         chipset_val = __i915_chipset_val(dev_priv);
4188         graphics_val = __i915_gfx_val(dev_priv);
4189
4190         ret = chipset_val + graphics_val;
4191
4192 out_unlock:
4193         spin_unlock_irq(&mchdev_lock);
4194
4195         return ret;
4196 }
4197 EXPORT_SYMBOL_GPL(i915_read_mch_val);
4198
4199 /**
4200  * i915_gpu_raise - raise GPU frequency limit
4201  *
4202  * Raise the limit; IPS indicates we have thermal headroom.
4203  */
4204 bool i915_gpu_raise(void)
4205 {
4206         struct drm_i915_private *dev_priv;
4207         bool ret = true;
4208
4209         spin_lock_irq(&mchdev_lock);
4210         if (!i915_mch_dev) {
4211                 ret = false;
4212                 goto out_unlock;
4213         }
4214         dev_priv = i915_mch_dev;
4215
4216         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4217                 dev_priv->ips.max_delay--;
4218
4219 out_unlock:
4220         spin_unlock_irq(&mchdev_lock);
4221
4222         return ret;
4223 }
4224 EXPORT_SYMBOL_GPL(i915_gpu_raise);
4225
4226 /**
4227  * i915_gpu_lower - lower GPU frequency limit
4228  *
4229  * IPS indicates we're close to a thermal limit, so throttle back the GPU
4230  * frequency maximum.
4231  */
4232 bool i915_gpu_lower(void)
4233 {
4234         struct drm_i915_private *dev_priv;
4235         bool ret = true;
4236
4237         spin_lock_irq(&mchdev_lock);
4238         if (!i915_mch_dev) {
4239                 ret = false;
4240                 goto out_unlock;
4241         }
4242         dev_priv = i915_mch_dev;
4243
4244         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4245                 dev_priv->ips.max_delay++;
4246
4247 out_unlock:
4248         spin_unlock_irq(&mchdev_lock);
4249
4250         return ret;
4251 }
4252 EXPORT_SYMBOL_GPL(i915_gpu_lower);
4253
4254 /**
4255  * i915_gpu_busy - indicate GPU business to IPS
4256  *
4257  * Tell the IPS driver whether or not the GPU is busy.
4258  */
4259 bool i915_gpu_busy(void)
4260 {
4261         struct drm_i915_private *dev_priv;
4262         struct intel_ring_buffer *ring;
4263         bool ret = false;
4264         int i;
4265
4266         spin_lock_irq(&mchdev_lock);
4267         if (!i915_mch_dev)
4268                 goto out_unlock;
4269         dev_priv = i915_mch_dev;
4270
4271         for_each_ring(ring, dev_priv, i)
4272                 ret |= !list_empty(&ring->request_list);
4273
4274 out_unlock:
4275         spin_unlock_irq(&mchdev_lock);
4276
4277         return ret;
4278 }
4279 EXPORT_SYMBOL_GPL(i915_gpu_busy);
4280
4281 /**
4282  * i915_gpu_turbo_disable - disable graphics turbo
4283  *
4284  * Disable graphics turbo by resetting the max frequency and setting the
4285  * current frequency to the default.
4286  */
4287 bool i915_gpu_turbo_disable(void)
4288 {
4289         struct drm_i915_private *dev_priv;
4290         bool ret = true;
4291
4292         spin_lock_irq(&mchdev_lock);
4293         if (!i915_mch_dev) {
4294                 ret = false;
4295                 goto out_unlock;
4296         }
4297         dev_priv = i915_mch_dev;
4298
4299         dev_priv->ips.max_delay = dev_priv->ips.fstart;
4300
4301         if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
4302                 ret = false;
4303
4304 out_unlock:
4305         spin_unlock_irq(&mchdev_lock);
4306
4307         return ret;
4308 }
4309 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4310
4311 /**
4312  * Tells the intel_ips driver that the i915 driver is now loaded, if
4313  * IPS got loaded first.
4314  *
4315  * This awkward dance is so that neither module has to depend on the
4316  * other in order for IPS to do the appropriate communication of
4317  * GPU turbo limits to i915.
4318  */
4319 static void
4320 ips_ping_for_i915_load(void)
4321 {
4322         void (*link)(void);
4323
4324         link = symbol_get(ips_link_to_i915_driver);
4325         if (link) {
4326                 link();
4327                 symbol_put(ips_link_to_i915_driver);
4328         }
4329 }
4330
4331 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4332 {
4333         /* We only register the i915 ips part with intel-ips once everything is
4334          * set up, to avoid intel-ips sneaking in and reading bogus values. */
4335         spin_lock_irq(&mchdev_lock);
4336         i915_mch_dev = dev_priv;
4337         spin_unlock_irq(&mchdev_lock);
4338
4339         ips_ping_for_i915_load();
4340 }
4341
4342 void intel_gpu_ips_teardown(void)
4343 {
4344         spin_lock_irq(&mchdev_lock);
4345         i915_mch_dev = NULL;
4346         spin_unlock_irq(&mchdev_lock);
4347 }
4348
4349 static void intel_init_emon(struct drm_device *dev)
4350 {
4351         struct drm_i915_private *dev_priv = dev->dev_private;
4352         u32 lcfuse;
4353         u8 pxw[16];
4354         int i;
4355
4356         /* Disable to program */
4357         I915_WRITE(ECR, 0);
4358         POSTING_READ(ECR);
4359
4360         /* Program energy weights for various events */
4361         I915_WRITE(SDEW, 0x15040d00);
4362         I915_WRITE(CSIEW0, 0x007f0000);
4363         I915_WRITE(CSIEW1, 0x1e220004);
4364         I915_WRITE(CSIEW2, 0x04000004);
4365
4366         for (i = 0; i < 5; i++)
4367                 I915_WRITE(PEW + (i * 4), 0);
4368         for (i = 0; i < 3; i++)
4369                 I915_WRITE(DEW + (i * 4), 0);
4370
4371         /* Program P-state weights to account for frequency power adjustment */
4372         for (i = 0; i < 16; i++) {
4373                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4374                 unsigned long freq = intel_pxfreq(pxvidfreq);
4375                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4376                         PXVFREQ_PX_SHIFT;
4377                 unsigned long val;
4378
4379                 val = vid * vid;
4380                 val *= (freq / 1000);
4381                 val *= 255;
4382                 val /= (127*127*900);
4383                 if (val > 0xff)
4384                         DRM_ERROR("bad pxval: %ld\n", val);
4385                 pxw[i] = val;
4386         }
4387         /* Render standby states get 0 weight */
4388         pxw[14] = 0;
4389         pxw[15] = 0;
4390
4391         for (i = 0; i < 4; i++) {
4392                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4393                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4394                 I915_WRITE(PXW + (i * 4), val);
4395         }
4396
4397         /* Adjust magic regs to magic values (more experimental results) */
4398         I915_WRITE(OGW0, 0);
4399         I915_WRITE(OGW1, 0);
4400         I915_WRITE(EG0, 0x00007f00);
4401         I915_WRITE(EG1, 0x0000000e);
4402         I915_WRITE(EG2, 0x000e0000);
4403         I915_WRITE(EG3, 0x68000300);
4404         I915_WRITE(EG4, 0x42000000);
4405         I915_WRITE(EG5, 0x00140031);
4406         I915_WRITE(EG6, 0);
4407         I915_WRITE(EG7, 0);
4408
4409         for (i = 0; i < 8; i++)
4410                 I915_WRITE(PXWL + (i * 4), 0);
4411
4412         /* Enable PMON + select events */
4413         I915_WRITE(ECR, 0x80000019);
4414
4415         lcfuse = I915_READ(LCFUSE02);
4416
4417         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
4418 }
4419
4420 void intel_disable_gt_powersave(struct drm_device *dev)
4421 {
4422         struct drm_i915_private *dev_priv = dev->dev_private;
4423
4424         /* Interrupts should be disabled already to avoid re-arming. */
4425         WARN_ON(dev->irq_enabled);
4426
4427         if (IS_IRONLAKE_M(dev)) {
4428                 ironlake_disable_drps(dev);
4429                 ironlake_disable_rc6(dev);
4430         } else if (INTEL_INFO(dev)->gen >= 6) {
4431                 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
4432                 cancel_work_sync(&dev_priv->rps.work);
4433                 mutex_lock(&dev_priv->rps.hw_lock);
4434                 if (IS_VALLEYVIEW(dev))
4435                         valleyview_disable_rps(dev);
4436                 else
4437                         gen6_disable_rps(dev);
4438                 dev_priv->rps.enabled = false;
4439                 mutex_unlock(&dev_priv->rps.hw_lock);
4440         }
4441 }
4442
4443 static void intel_gen6_powersave_work(struct work_struct *work)
4444 {
4445         struct drm_i915_private *dev_priv =
4446                 container_of(work, struct drm_i915_private,
4447                              rps.delayed_resume_work.work);
4448         struct drm_device *dev = dev_priv->dev;
4449
4450         mutex_lock(&dev_priv->rps.hw_lock);
4451
4452         if (IS_VALLEYVIEW(dev)) {
4453                 valleyview_enable_rps(dev);
4454         } else if (IS_BROADWELL(dev)) {
4455                 gen8_enable_rps(dev);
4456                 gen6_update_ring_freq(dev);
4457         } else {
4458                 gen6_enable_rps(dev);
4459                 gen6_update_ring_freq(dev);
4460         }
4461         dev_priv->rps.enabled = true;
4462         mutex_unlock(&dev_priv->rps.hw_lock);
4463 }
4464
4465 void intel_enable_gt_powersave(struct drm_device *dev)
4466 {
4467         struct drm_i915_private *dev_priv = dev->dev_private;
4468
4469         if (IS_IRONLAKE_M(dev)) {
4470                 ironlake_enable_drps(dev);
4471                 ironlake_enable_rc6(dev);
4472                 intel_init_emon(dev);
4473         } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
4474                 /*
4475                  * PCU communication is slow and this doesn't need to be
4476                  * done at any specific time, so do this out of our fast path
4477                  * to make resume and init faster.
4478                  */
4479                 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4480                                       round_jiffies_up_relative(HZ));
4481         }
4482 }
4483
4484 static void ibx_init_clock_gating(struct drm_device *dev)
4485 {
4486         struct drm_i915_private *dev_priv = dev->dev_private;
4487
4488         /*
4489          * On Ibex Peak and Cougar Point, we need to disable clock
4490          * gating for the panel power sequencer or it will fail to
4491          * start up when no ports are active.
4492          */
4493         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4494 }
4495
4496 static void g4x_disable_trickle_feed(struct drm_device *dev)
4497 {
4498         struct drm_i915_private *dev_priv = dev->dev_private;
4499         int pipe;
4500
4501         for_each_pipe(pipe) {
4502                 I915_WRITE(DSPCNTR(pipe),
4503                            I915_READ(DSPCNTR(pipe)) |
4504                            DISPPLANE_TRICKLE_FEED_DISABLE);
4505                 intel_flush_primary_plane(dev_priv, pipe);
4506         }
4507 }
4508
4509 static void ilk_init_lp_watermarks(struct drm_device *dev)
4510 {
4511         struct drm_i915_private *dev_priv = dev->dev_private;
4512
4513         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
4514         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
4515         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
4516
4517         /*
4518          * Don't touch WM1S_LP_EN here.
4519          * Doing so could cause underruns.
4520          */
4521 }
4522
4523 static void ironlake_init_clock_gating(struct drm_device *dev)
4524 {
4525         struct drm_i915_private *dev_priv = dev->dev_private;
4526         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
4527
4528         /*
4529          * Required for FBC
4530          * WaFbcDisableDpfcClockGating:ilk
4531          */
4532         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4533                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4534                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
4535
4536         I915_WRITE(PCH_3DCGDIS0,
4537                    MARIUNIT_CLOCK_GATE_DISABLE |
4538                    SVSMUNIT_CLOCK_GATE_DISABLE);
4539         I915_WRITE(PCH_3DCGDIS1,
4540                    VFMUNIT_CLOCK_GATE_DISABLE);
4541
4542         /*
4543          * According to the spec the following bits should be set in
4544          * order to enable memory self-refresh
4545          * The bit 22/21 of 0x42004
4546          * The bit 5 of 0x42020
4547          * The bit 15 of 0x45000
4548          */
4549         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4550                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
4551                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4552         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
4553         I915_WRITE(DISP_ARB_CTL,
4554                    (I915_READ(DISP_ARB_CTL) |
4555                     DISP_FBC_WM_DIS));
4556
4557         ilk_init_lp_watermarks(dev);
4558
4559         /*
4560          * Based on the document from hardware guys the following bits
4561          * should be set unconditionally in order to enable FBC.
4562          * The bit 22 of 0x42000
4563          * The bit 22 of 0x42004
4564          * The bit 7,8,9 of 0x42020.
4565          */
4566         if (IS_IRONLAKE_M(dev)) {
4567                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
4568                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4569                            I915_READ(ILK_DISPLAY_CHICKEN1) |
4570                            ILK_FBCQ_DIS);
4571                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4572                            I915_READ(ILK_DISPLAY_CHICKEN2) |
4573                            ILK_DPARB_GATE);
4574         }
4575
4576         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4577
4578         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4579                    I915_READ(ILK_DISPLAY_CHICKEN2) |
4580                    ILK_ELPIN_409_SELECT);
4581         I915_WRITE(_3D_CHICKEN2,
4582                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
4583                    _3D_CHICKEN2_WM_READ_PIPELINED);
4584
4585         /* WaDisableRenderCachePipelinedFlush:ilk */
4586         I915_WRITE(CACHE_MODE_0,
4587                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
4588
4589         g4x_disable_trickle_feed(dev);
4590
4591         ibx_init_clock_gating(dev);
4592 }
4593
4594 static void cpt_init_clock_gating(struct drm_device *dev)
4595 {
4596         struct drm_i915_private *dev_priv = dev->dev_private;
4597         int pipe;
4598         uint32_t val;
4599
4600         /*
4601          * On Ibex Peak and Cougar Point, we need to disable clock
4602          * gating for the panel power sequencer or it will fail to
4603          * start up when no ports are active.
4604          */
4605         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
4606                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
4607                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
4608         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
4609                    DPLS_EDP_PPS_FIX_DIS);
4610         /* The below fixes the weird display corruption, a few pixels shifted
4611          * downward, on (only) LVDS of some HP laptops with IVY.
4612          */
4613         for_each_pipe(pipe) {
4614                 val = I915_READ(TRANS_CHICKEN2(pipe));
4615                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
4616                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
4617                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
4618                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
4619                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
4620                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
4621                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
4622                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
4623         }
4624         /* WADP0ClockGatingDisable */
4625         for_each_pipe(pipe) {
4626                 I915_WRITE(TRANS_CHICKEN1(pipe),
4627                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4628         }
4629 }
4630
4631 static void gen6_check_mch_setup(struct drm_device *dev)
4632 {
4633         struct drm_i915_private *dev_priv = dev->dev_private;
4634         uint32_t tmp;
4635
4636         tmp = I915_READ(MCH_SSKPD);
4637         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
4638                 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
4639                 DRM_INFO("This can cause pipe underruns and display issues.\n");
4640                 DRM_INFO("Please upgrade your BIOS to fix this.\n");
4641         }
4642 }
4643
4644 static void gen6_init_clock_gating(struct drm_device *dev)
4645 {
4646         struct drm_i915_private *dev_priv = dev->dev_private;
4647         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
4648
4649         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4650
4651         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4652                    I915_READ(ILK_DISPLAY_CHICKEN2) |
4653                    ILK_ELPIN_409_SELECT);
4654
4655         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4656         I915_WRITE(_3D_CHICKEN,
4657                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
4658
4659         /* WaSetupGtModeTdRowDispatch:snb */
4660         if (IS_SNB_GT1(dev))
4661                 I915_WRITE(GEN6_GT_MODE,
4662                            _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
4663
4664         /*
4665          * BSpec recoomends 8x4 when MSAA is used,
4666          * however in practice 16x4 seems fastest.
4667          *
4668          * Note that PS/WM thread counts depend on the WIZ hashing
4669          * disable bit, which we don't touch here, but it's good
4670          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
4671          */
4672         I915_WRITE(GEN6_GT_MODE,
4673                    GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
4674
4675         ilk_init_lp_watermarks(dev);
4676
4677         I915_WRITE(CACHE_MODE_0,
4678                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
4679
4680         I915_WRITE(GEN6_UCGCTL1,
4681                    I915_READ(GEN6_UCGCTL1) |
4682                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
4683                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
4684
4685         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4686          * gating disable must be set.  Failure to set it results in
4687          * flickering pixels due to Z write ordering failures after
4688          * some amount of runtime in the Mesa "fire" demo, and Unigine
4689          * Sanctuary and Tropics, and apparently anything else with
4690          * alpha test or pixel discard.
4691          *
4692          * According to the spec, bit 11 (RCCUNIT) must also be set,
4693          * but we didn't debug actual testcases to find it out.
4694          *
4695          * WaDisableRCCUnitClockGating:snb
4696          * WaDisableRCPBUnitClockGating:snb
4697          */
4698         I915_WRITE(GEN6_UCGCTL2,
4699                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4700                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4701
4702         /* WaStripsFansDisableFastClipPerformanceFix:snb */
4703         I915_WRITE(_3D_CHICKEN3,
4704                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
4705
4706         /*
4707          * Bspec says:
4708          * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
4709          * 3DSTATE_SF number of SF output attributes is more than 16."
4710          */
4711         I915_WRITE(_3D_CHICKEN3,
4712                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
4713
4714         /*
4715          * According to the spec the following bits should be
4716          * set in order to enable memory self-refresh and fbc:
4717          * The bit21 and bit22 of 0x42000
4718          * The bit21 and bit22 of 0x42004
4719          * The bit5 and bit7 of 0x42020
4720          * The bit14 of 0x70180
4721          * The bit14 of 0x71180
4722          *
4723          * WaFbcAsynchFlipDisableFbcQueue:snb
4724          */
4725         I915_WRITE(ILK_DISPLAY_CHICKEN1,
4726                    I915_READ(ILK_DISPLAY_CHICKEN1) |
4727                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
4728         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4729                    I915_READ(ILK_DISPLAY_CHICKEN2) |
4730                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
4731         I915_WRITE(ILK_DSPCLK_GATE_D,
4732                    I915_READ(ILK_DSPCLK_GATE_D) |
4733                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
4734                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
4735
4736         g4x_disable_trickle_feed(dev);
4737
4738         cpt_init_clock_gating(dev);
4739
4740         gen6_check_mch_setup(dev);
4741 }
4742
4743 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
4744 {
4745         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
4746
4747         /*
4748          * WaVSThreadDispatchOverride:ivb,vlv
4749          *
4750          * This actually overrides the dispatch
4751          * mode for all thread types.
4752          */
4753         reg &= ~GEN7_FF_SCHED_MASK;
4754         reg |= GEN7_FF_TS_SCHED_HW;
4755         reg |= GEN7_FF_VS_SCHED_HW;
4756         reg |= GEN7_FF_DS_SCHED_HW;
4757
4758         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
4759 }
4760
4761 static void lpt_init_clock_gating(struct drm_device *dev)
4762 {
4763         struct drm_i915_private *dev_priv = dev->dev_private;
4764
4765         /*
4766          * TODO: this bit should only be enabled when really needed, then
4767          * disabled when not needed anymore in order to save power.
4768          */
4769         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
4770                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
4771                            I915_READ(SOUTH_DSPCLK_GATE_D) |
4772                            PCH_LP_PARTITION_LEVEL_DISABLE);
4773
4774         /* WADPOClockGatingDisable:hsw */
4775         I915_WRITE(_TRANSA_CHICKEN1,
4776                    I915_READ(_TRANSA_CHICKEN1) |
4777                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4778 }
4779
4780 static void lpt_suspend_hw(struct drm_device *dev)
4781 {
4782         struct drm_i915_private *dev_priv = dev->dev_private;
4783
4784         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
4785                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
4786
4787                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
4788                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
4789         }
4790 }
4791
4792 static void gen8_init_clock_gating(struct drm_device *dev)
4793 {
4794         struct drm_i915_private *dev_priv = dev->dev_private;
4795         enum pipe i;
4796
4797         I915_WRITE(WM3_LP_ILK, 0);
4798         I915_WRITE(WM2_LP_ILK, 0);
4799         I915_WRITE(WM1_LP_ILK, 0);
4800
4801         /* FIXME(BDW): Check all the w/a, some might only apply to
4802          * pre-production hw. */
4803
4804         /* WaDisablePartialInstShootdown:bdw */
4805         I915_WRITE(GEN8_ROW_CHICKEN,
4806                    _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
4807
4808         /* WaDisableThreadStallDopClockGating:bdw */
4809         /* FIXME: Unclear whether we really need this on production bdw. */
4810         I915_WRITE(GEN8_ROW_CHICKEN,
4811                    _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
4812
4813         /*
4814          * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for
4815          * pre-production hardware
4816          */
4817         I915_WRITE(HALF_SLICE_CHICKEN3,
4818                    _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));
4819         I915_WRITE(HALF_SLICE_CHICKEN3,
4820                    _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
4821         I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
4822
4823         I915_WRITE(_3D_CHICKEN3,
4824                    _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2));
4825
4826         I915_WRITE(COMMON_SLICE_CHICKEN2,
4827                    _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
4828
4829         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4830                    _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
4831
4832         /* WaSwitchSolVfFArbitrationPriority:bdw */
4833         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
4834
4835         /* WaPsrDPAMaskVBlankInSRD:bdw */
4836         I915_WRITE(CHICKEN_PAR1_1,
4837                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
4838
4839         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
4840         for_each_pipe(i) {
4841                 I915_WRITE(CHICKEN_PIPESL_1(i),
4842                            I915_READ(CHICKEN_PIPESL_1(i) |
4843                                      DPRS_MASK_VBLANK_SRD));
4844         }
4845
4846         /* Use Force Non-Coherent whenever executing a 3D context. This is a
4847          * workaround for for a possible hang in the unlikely event a TLB
4848          * invalidation occurs during a PSD flush.
4849          */
4850         I915_WRITE(HDC_CHICKEN0,
4851                    I915_READ(HDC_CHICKEN0) |
4852                    _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT));
4853
4854         /* WaVSRefCountFullforceMissDisable:bdw */
4855         /* WaDSRefCountFullforceMissDisable:bdw */
4856         I915_WRITE(GEN7_FF_THREAD_MODE,
4857                    I915_READ(GEN7_FF_THREAD_MODE) &
4858                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
4859
4860         /*
4861          * BSpec recommends 8x4 when MSAA is used,
4862          * however in practice 16x4 seems fastest.
4863          *
4864          * Note that PS/WM thread counts depend on the WIZ hashing
4865          * disable bit, which we don't touch here, but it's good
4866          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
4867          */
4868         I915_WRITE(GEN7_GT_MODE,
4869                    GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
4870 }
4871
4872 static void haswell_init_clock_gating(struct drm_device *dev)
4873 {
4874         struct drm_i915_private *dev_priv = dev->dev_private;
4875
4876         ilk_init_lp_watermarks(dev);
4877
4878         /* L3 caching of data atomics doesn't work -- disable it. */
4879         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
4880         I915_WRITE(HSW_ROW_CHICKEN3,
4881                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
4882
4883         /* This is required by WaCatErrorRejectionIssue:hsw */
4884         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4885                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4886                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4887
4888         /* WaVSRefCountFullforceMissDisable:hsw */
4889         I915_WRITE(GEN7_FF_THREAD_MODE,
4890                    I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
4891
4892         /* enable HiZ Raw Stall Optimization */
4893         I915_WRITE(CACHE_MODE_0_GEN7,
4894                    _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
4895
4896         /* WaDisable4x2SubspanOptimization:hsw */
4897         I915_WRITE(CACHE_MODE_1,
4898                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
4899
4900         /*
4901          * BSpec recommends 8x4 when MSAA is used,
4902          * however in practice 16x4 seems fastest.
4903          *
4904          * Note that PS/WM thread counts depend on the WIZ hashing
4905          * disable bit, which we don't touch here, but it's good
4906          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
4907          */
4908         I915_WRITE(GEN7_GT_MODE,
4909                    GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
4910
4911         /* WaSwitchSolVfFArbitrationPriority:hsw */
4912         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
4913
4914         /* WaRsPkgCStateDisplayPMReq:hsw */
4915         I915_WRITE(CHICKEN_PAR1_1,
4916                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
4917
4918         lpt_init_clock_gating(dev);
4919 }
4920
4921 static void ivybridge_init_clock_gating(struct drm_device *dev)
4922 {
4923         struct drm_i915_private *dev_priv = dev->dev_private;
4924         uint32_t snpcr;
4925
4926         ilk_init_lp_watermarks(dev);
4927
4928         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
4929
4930         /* WaDisableEarlyCull:ivb */
4931         I915_WRITE(_3D_CHICKEN3,
4932                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4933
4934         /* WaDisableBackToBackFlipFix:ivb */
4935         I915_WRITE(IVB_CHICKEN3,
4936                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4937                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
4938
4939         /* WaDisablePSDDualDispatchEnable:ivb */
4940         if (IS_IVB_GT1(dev))
4941                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4942                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4943
4944         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
4945         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4946                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4947
4948         /* WaApplyL3ControlAndL3ChickenMode:ivb */
4949         I915_WRITE(GEN7_L3CNTLREG1,
4950                         GEN7_WA_FOR_GEN7_L3_CONTROL);
4951         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
4952                    GEN7_WA_L3_CHICKEN_MODE);
4953         if (IS_IVB_GT1(dev))
4954                 I915_WRITE(GEN7_ROW_CHICKEN2,
4955                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4956         else {
4957                 /* must write both registers */
4958                 I915_WRITE(GEN7_ROW_CHICKEN2,
4959                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4960                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
4961                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4962         }
4963
4964         /* WaForceL3Serialization:ivb */
4965         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4966                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4967
4968         /*
4969          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
4970          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
4971          */
4972         I915_WRITE(GEN6_UCGCTL2,
4973                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
4974
4975         /* This is required by WaCatErrorRejectionIssue:ivb */
4976         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4977                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4978                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4979
4980         g4x_disable_trickle_feed(dev);
4981
4982         gen7_setup_fixed_func_scheduler(dev_priv);
4983
4984         if (0) { /* causes HiZ corruption on ivb:gt1 */
4985                 /* enable HiZ Raw Stall Optimization */
4986                 I915_WRITE(CACHE_MODE_0_GEN7,
4987                            _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
4988         }
4989
4990         /* WaDisable4x2SubspanOptimization:ivb */
4991         I915_WRITE(CACHE_MODE_1,
4992                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
4993
4994         /*
4995          * BSpec recommends 8x4 when MSAA is used,
4996          * however in practice 16x4 seems fastest.
4997          *
4998          * Note that PS/WM thread counts depend on the WIZ hashing
4999          * disable bit, which we don't touch here, but it's good
5000          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5001          */
5002         I915_WRITE(GEN7_GT_MODE,
5003                    GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5004
5005         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5006         snpcr &= ~GEN6_MBC_SNPCR_MASK;
5007         snpcr |= GEN6_MBC_SNPCR_MED;
5008         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5009
5010         if (!HAS_PCH_NOP(dev))
5011                 cpt_init_clock_gating(dev);
5012
5013         gen6_check_mch_setup(dev);
5014 }
5015
5016 static void valleyview_init_clock_gating(struct drm_device *dev)
5017 {
5018         struct drm_i915_private *dev_priv = dev->dev_private;
5019         u32 val;
5020
5021         mutex_lock(&dev_priv->rps.hw_lock);
5022         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5023         mutex_unlock(&dev_priv->rps.hw_lock);
5024         switch ((val >> 6) & 3) {
5025         case 0:
5026                 dev_priv->mem_freq = 800;
5027                 break;
5028         case 1:
5029                 dev_priv->mem_freq = 1066;
5030                 break;
5031         case 2:
5032                 dev_priv->mem_freq = 1333;
5033                 break;
5034         case 3:
5035                 dev_priv->mem_freq = 1333;
5036                 break;
5037         }
5038         DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
5039
5040         I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5041
5042         /* WaDisableEarlyCull:vlv */
5043         I915_WRITE(_3D_CHICKEN3,
5044                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5045
5046         /* WaDisableBackToBackFlipFix:vlv */
5047         I915_WRITE(IVB_CHICKEN3,
5048                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5049                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
5050
5051         /* WaPsdDispatchEnable:vlv */
5052         /* WaDisablePSDDualDispatchEnable:vlv */
5053         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5054                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5055                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5056
5057         /* WaForceL3Serialization:vlv */
5058         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5059                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5060
5061         /* WaDisableDopClockGating:vlv */
5062         I915_WRITE(GEN7_ROW_CHICKEN2,
5063                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5064
5065         /* This is required by WaCatErrorRejectionIssue:vlv */
5066         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5067                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5068                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5069
5070         gen7_setup_fixed_func_scheduler(dev_priv);
5071
5072         /*
5073          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5074          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
5075          */
5076         I915_WRITE(GEN6_UCGCTL2,
5077                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5078
5079         /* WaDisableL3Bank2xClockGate:vlv */
5080         I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
5081
5082         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
5083
5084         /*
5085          * BSpec says this must be set, even though
5086          * WaDisable4x2SubspanOptimization isn't listed for VLV.
5087          */
5088         I915_WRITE(CACHE_MODE_1,
5089                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5090
5091         /*
5092          * WaIncreaseL3CreditsForVLVB0:vlv
5093          * This is the hardware default actually.
5094          */
5095         I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
5096
5097         /*
5098          * WaDisableVLVClockGating_VBIIssue:vlv
5099          * Disable clock gating on th GCFG unit to prevent a delay
5100          * in the reporting of vblank events.
5101          */
5102         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
5103 }
5104
5105 static void g4x_init_clock_gating(struct drm_device *dev)
5106 {
5107         struct drm_i915_private *dev_priv = dev->dev_private;
5108         uint32_t dspclk_gate;
5109
5110         I915_WRITE(RENCLK_GATE_D1, 0);
5111         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5112                    GS_UNIT_CLOCK_GATE_DISABLE |
5113                    CL_UNIT_CLOCK_GATE_DISABLE);
5114         I915_WRITE(RAMCLK_GATE_D, 0);
5115         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5116                 OVRUNIT_CLOCK_GATE_DISABLE |
5117                 OVCUNIT_CLOCK_GATE_DISABLE;
5118         if (IS_GM45(dev))
5119                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5120         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5121
5122         /* WaDisableRenderCachePipelinedFlush */
5123         I915_WRITE(CACHE_MODE_0,
5124                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5125
5126         g4x_disable_trickle_feed(dev);
5127 }
5128
5129 static void crestline_init_clock_gating(struct drm_device *dev)
5130 {
5131         struct drm_i915_private *dev_priv = dev->dev_private;
5132
5133         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5134         I915_WRITE(RENCLK_GATE_D2, 0);
5135         I915_WRITE(DSPCLK_GATE_D, 0);
5136         I915_WRITE(RAMCLK_GATE_D, 0);
5137         I915_WRITE16(DEUC, 0);
5138         I915_WRITE(MI_ARB_STATE,
5139                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5140 }
5141
5142 static void broadwater_init_clock_gating(struct drm_device *dev)
5143 {
5144         struct drm_i915_private *dev_priv = dev->dev_private;
5145
5146         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5147                    I965_RCC_CLOCK_GATE_DISABLE |
5148                    I965_RCPB_CLOCK_GATE_DISABLE |
5149                    I965_ISC_CLOCK_GATE_DISABLE |
5150                    I965_FBC_CLOCK_GATE_DISABLE);
5151         I915_WRITE(RENCLK_GATE_D2, 0);
5152         I915_WRITE(MI_ARB_STATE,
5153                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5154 }
5155
5156 static void gen3_init_clock_gating(struct drm_device *dev)
5157 {
5158         struct drm_i915_private *dev_priv = dev->dev_private;
5159         u32 dstate = I915_READ(D_STATE);
5160
5161         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5162                 DSTATE_DOT_CLOCK_GATING;
5163         I915_WRITE(D_STATE, dstate);
5164
5165         if (IS_PINEVIEW(dev))
5166                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
5167
5168         /* IIR "flip pending" means done if this bit is set */
5169         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
5170 }
5171
5172 static void i85x_init_clock_gating(struct drm_device *dev)
5173 {
5174         struct drm_i915_private *dev_priv = dev->dev_private;
5175
5176         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5177 }
5178
5179 static void i830_init_clock_gating(struct drm_device *dev)
5180 {
5181         struct drm_i915_private *dev_priv = dev->dev_private;
5182
5183         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5184 }
5185
5186 void intel_init_clock_gating(struct drm_device *dev)
5187 {
5188         struct drm_i915_private *dev_priv = dev->dev_private;
5189
5190         dev_priv->display.init_clock_gating(dev);
5191 }
5192
5193 void intel_suspend_hw(struct drm_device *dev)
5194 {
5195         if (HAS_PCH_LPT(dev))
5196                 lpt_suspend_hw(dev);
5197 }
5198
5199 #define for_each_power_well(i, power_well, domain_mask, power_domains)  \
5200         for (i = 0;                                                     \
5201              i < (power_domains)->power_well_count &&                   \
5202                  ((power_well) = &(power_domains)->power_wells[i]);     \
5203              i++)                                                       \
5204                 if ((power_well)->domains & (domain_mask))
5205
5206 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
5207         for (i = (power_domains)->power_well_count - 1;                  \
5208              i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
5209              i--)                                                        \
5210                 if ((power_well)->domains & (domain_mask))
5211
5212 /**
5213  * We should only use the power well if we explicitly asked the hardware to
5214  * enable it, so check if it's enabled and also check if we've requested it to
5215  * be enabled.
5216  */
5217 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
5218                                    struct i915_power_well *power_well)
5219 {
5220         return I915_READ(HSW_PWR_WELL_DRIVER) ==
5221                      (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
5222 }
5223
5224 bool intel_display_power_enabled_sw(struct drm_i915_private *dev_priv,
5225                                     enum intel_display_power_domain domain)
5226 {
5227         struct i915_power_domains *power_domains;
5228
5229         power_domains = &dev_priv->power_domains;
5230
5231         return power_domains->domain_use_count[domain];
5232 }
5233
5234 bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
5235                                  enum intel_display_power_domain domain)
5236 {
5237         struct i915_power_domains *power_domains;
5238         struct i915_power_well *power_well;
5239         bool is_enabled;
5240         int i;
5241
5242         power_domains = &dev_priv->power_domains;
5243
5244         is_enabled = true;
5245
5246         mutex_lock(&power_domains->lock);
5247         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
5248                 if (power_well->always_on)
5249                         continue;
5250
5251                 if (!power_well->is_enabled(dev_priv, power_well)) {
5252                         is_enabled = false;
5253                         break;
5254                 }
5255         }
5256         mutex_unlock(&power_domains->lock);
5257
5258         return is_enabled;
5259 }
5260
5261 /*
5262  * Starting with Haswell, we have a "Power Down Well" that can be turned off
5263  * when not needed anymore. We have 4 registers that can request the power well
5264  * to be enabled, and it will only be disabled if none of the registers is
5265  * requesting it to be enabled.
5266  */
5267 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
5268 {
5269         struct drm_device *dev = dev_priv->dev;
5270         unsigned long irqflags;
5271
5272         /*
5273          * After we re-enable the power well, if we touch VGA register 0x3d5
5274          * we'll get unclaimed register interrupts. This stops after we write
5275          * anything to the VGA MSR register. The vgacon module uses this
5276          * register all the time, so if we unbind our driver and, as a
5277          * consequence, bind vgacon, we'll get stuck in an infinite loop at
5278          * console_unlock(). So make here we touch the VGA MSR register, making
5279          * sure vgacon can keep working normally without triggering interrupts
5280          * and error messages.
5281          */
5282         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
5283         outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
5284         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
5285
5286         if (IS_BROADWELL(dev)) {
5287                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5288                 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B),
5289                            dev_priv->de_irq_mask[PIPE_B]);
5290                 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B),
5291                            ~dev_priv->de_irq_mask[PIPE_B] |
5292                            GEN8_PIPE_VBLANK);
5293                 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C),
5294                            dev_priv->de_irq_mask[PIPE_C]);
5295                 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C),
5296                            ~dev_priv->de_irq_mask[PIPE_C] |
5297                            GEN8_PIPE_VBLANK);
5298                 POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C));
5299                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5300         }
5301 }
5302
5303 static void hsw_power_well_post_disable(struct drm_i915_private *dev_priv)
5304 {
5305         struct drm_device *dev = dev_priv->dev;
5306         enum pipe p;
5307         unsigned long irqflags;
5308
5309         /*
5310          * After this, the registers on the pipes that are part of the power
5311          * well will become zero, so we have to adjust our counters according to
5312          * that.
5313          *
5314          * FIXME: Should we do this in general in drm_vblank_post_modeset?
5315          */
5316         spin_lock_irqsave(&dev->vbl_lock, irqflags);
5317         for_each_pipe(p)
5318                 if (p != PIPE_A)
5319                         dev->vblank[p].last = 0;
5320         spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
5321 }
5322
5323 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
5324                                struct i915_power_well *power_well, bool enable)
5325 {
5326         bool is_enabled, enable_requested;
5327         uint32_t tmp;
5328
5329         WARN_ON(dev_priv->pc8.enabled);
5330
5331         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
5332         is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5333         enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
5334
5335         if (enable) {
5336                 if (!enable_requested)
5337                         I915_WRITE(HSW_PWR_WELL_DRIVER,
5338                                    HSW_PWR_WELL_ENABLE_REQUEST);
5339
5340                 if (!is_enabled) {
5341                         DRM_DEBUG_KMS("Enabling power well\n");
5342                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
5343                                       HSW_PWR_WELL_STATE_ENABLED), 20))
5344                                 DRM_ERROR("Timeout enabling power well\n");
5345                 }
5346
5347                 hsw_power_well_post_enable(dev_priv);
5348         } else {
5349                 if (enable_requested) {
5350                         I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
5351                         POSTING_READ(HSW_PWR_WELL_DRIVER);
5352                         DRM_DEBUG_KMS("Requesting to disable the power well\n");
5353
5354                         hsw_power_well_post_disable(dev_priv);
5355                 }
5356         }
5357 }
5358
5359 static void __intel_power_well_get(struct drm_i915_private *dev_priv,
5360                                    struct i915_power_well *power_well)
5361 {
5362         if (!power_well->count++ && power_well->set) {
5363                 hsw_disable_package_c8(dev_priv);
5364                 power_well->set(dev_priv, power_well, true);
5365         }
5366 }
5367
5368 static void __intel_power_well_put(struct drm_i915_private *dev_priv,
5369                                    struct i915_power_well *power_well)
5370 {
5371         WARN_ON(!power_well->count);
5372
5373         if (!--power_well->count && power_well->set &&
5374             i915.disable_power_well) {
5375                 power_well->set(dev_priv, power_well, false);
5376                 hsw_enable_package_c8(dev_priv);
5377         }
5378 }
5379
5380 void intel_display_power_get(struct drm_i915_private *dev_priv,
5381                              enum intel_display_power_domain domain)
5382 {
5383         struct i915_power_domains *power_domains;
5384         struct i915_power_well *power_well;
5385         int i;
5386
5387         power_domains = &dev_priv->power_domains;
5388
5389         mutex_lock(&power_domains->lock);
5390
5391         for_each_power_well(i, power_well, BIT(domain), power_domains)
5392                 __intel_power_well_get(dev_priv, power_well);
5393
5394         power_domains->domain_use_count[domain]++;
5395
5396         mutex_unlock(&power_domains->lock);
5397 }
5398
5399 void intel_display_power_put(struct drm_i915_private *dev_priv,
5400                              enum intel_display_power_domain domain)
5401 {
5402         struct i915_power_domains *power_domains;
5403         struct i915_power_well *power_well;
5404         int i;
5405
5406         power_domains = &dev_priv->power_domains;
5407
5408         mutex_lock(&power_domains->lock);
5409
5410         WARN_ON(!power_domains->domain_use_count[domain]);
5411         power_domains->domain_use_count[domain]--;
5412
5413         for_each_power_well_rev(i, power_well, BIT(domain), power_domains)
5414                 __intel_power_well_put(dev_priv, power_well);
5415
5416         mutex_unlock(&power_domains->lock);
5417 }
5418
5419 static struct i915_power_domains *hsw_pwr;
5420
5421 /* Display audio driver power well request */
5422 void i915_request_power_well(void)
5423 {
5424         struct drm_i915_private *dev_priv;
5425
5426         if (WARN_ON(!hsw_pwr))
5427                 return;
5428
5429         dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5430                                 power_domains);
5431         intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
5432 }
5433 EXPORT_SYMBOL_GPL(i915_request_power_well);
5434
5435 /* Display audio driver power well release */
5436 void i915_release_power_well(void)
5437 {
5438         struct drm_i915_private *dev_priv;
5439
5440         if (WARN_ON(!hsw_pwr))
5441                 return;
5442
5443         dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5444                                 power_domains);
5445         intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
5446 }
5447 EXPORT_SYMBOL_GPL(i915_release_power_well);
5448
5449 static struct i915_power_well i9xx_always_on_power_well[] = {
5450         {
5451                 .name = "always-on",
5452                 .always_on = 1,
5453                 .domains = POWER_DOMAIN_MASK,
5454         },
5455 };
5456
5457 static struct i915_power_well hsw_power_wells[] = {
5458         {
5459                 .name = "always-on",
5460                 .always_on = 1,
5461                 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
5462         },
5463         {
5464                 .name = "display",
5465                 .domains = POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS,
5466                 .is_enabled = hsw_power_well_enabled,
5467                 .set = hsw_set_power_well,
5468         },
5469 };
5470
5471 static struct i915_power_well bdw_power_wells[] = {
5472         {
5473                 .name = "always-on",
5474                 .always_on = 1,
5475                 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
5476         },
5477         {
5478                 .name = "display",
5479                 .domains = POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS,
5480                 .is_enabled = hsw_power_well_enabled,
5481                 .set = hsw_set_power_well,
5482         },
5483 };
5484
5485 #define set_power_wells(power_domains, __power_wells) ({                \
5486         (power_domains)->power_wells = (__power_wells);                 \
5487         (power_domains)->power_well_count = ARRAY_SIZE(__power_wells);  \
5488 })
5489
5490 int intel_power_domains_init(struct drm_i915_private *dev_priv)
5491 {
5492         struct i915_power_domains *power_domains = &dev_priv->power_domains;
5493
5494         mutex_init(&power_domains->lock);
5495
5496         /*
5497          * The enabling order will be from lower to higher indexed wells,
5498          * the disabling order is reversed.
5499          */
5500         if (IS_HASWELL(dev_priv->dev)) {
5501                 set_power_wells(power_domains, hsw_power_wells);
5502                 hsw_pwr = power_domains;
5503         } else if (IS_BROADWELL(dev_priv->dev)) {
5504                 set_power_wells(power_domains, bdw_power_wells);
5505                 hsw_pwr = power_domains;
5506         } else {
5507                 set_power_wells(power_domains, i9xx_always_on_power_well);
5508         }
5509
5510         return 0;
5511 }
5512
5513 void intel_power_domains_remove(struct drm_i915_private *dev_priv)
5514 {
5515         hsw_pwr = NULL;
5516 }
5517
5518 static void intel_power_domains_resume(struct drm_i915_private *dev_priv)
5519 {
5520         struct i915_power_domains *power_domains = &dev_priv->power_domains;
5521         struct i915_power_well *power_well;
5522         int i;
5523
5524         mutex_lock(&power_domains->lock);
5525         for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
5526                 if (power_well->set)
5527                         power_well->set(dev_priv, power_well, power_well->count > 0);
5528         }
5529         mutex_unlock(&power_domains->lock);
5530 }
5531
5532 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv)
5533 {
5534         /* For now, we need the power well to be always enabled. */
5535         intel_display_set_init_power(dev_priv, true);
5536         intel_power_domains_resume(dev_priv);
5537
5538         if (!(IS_HASWELL(dev_priv->dev) || IS_BROADWELL(dev_priv->dev)))
5539                 return;
5540
5541         /* We're taking over the BIOS, so clear any requests made by it since
5542          * the driver is in charge now. */
5543         if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
5544                 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
5545 }
5546
5547 /* Disables PC8 so we can use the GMBUS and DP AUX interrupts. */
5548 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
5549 {
5550         hsw_disable_package_c8(dev_priv);
5551 }
5552
5553 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
5554 {
5555         hsw_enable_package_c8(dev_priv);
5556 }
5557
5558 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
5559 {
5560         struct drm_device *dev = dev_priv->dev;
5561         struct device *device = &dev->pdev->dev;
5562
5563         if (!HAS_RUNTIME_PM(dev))
5564                 return;
5565
5566         pm_runtime_get_sync(device);
5567         WARN(dev_priv->pm.suspended, "Device still suspended.\n");
5568 }
5569
5570 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
5571 {
5572         struct drm_device *dev = dev_priv->dev;
5573         struct device *device = &dev->pdev->dev;
5574
5575         if (!HAS_RUNTIME_PM(dev))
5576                 return;
5577
5578         pm_runtime_mark_last_busy(device);
5579         pm_runtime_put_autosuspend(device);
5580 }
5581
5582 void intel_init_runtime_pm(struct drm_i915_private *dev_priv)
5583 {
5584         struct drm_device *dev = dev_priv->dev;
5585         struct device *device = &dev->pdev->dev;
5586
5587         dev_priv->pm.suspended = false;
5588
5589         if (!HAS_RUNTIME_PM(dev))
5590                 return;
5591
5592         pm_runtime_set_active(device);
5593
5594         pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
5595         pm_runtime_mark_last_busy(device);
5596         pm_runtime_use_autosuspend(device);
5597 }
5598
5599 void intel_fini_runtime_pm(struct drm_i915_private *dev_priv)
5600 {
5601         struct drm_device *dev = dev_priv->dev;
5602         struct device *device = &dev->pdev->dev;
5603
5604         if (!HAS_RUNTIME_PM(dev))
5605                 return;
5606
5607         /* Make sure we're not suspended first. */
5608         pm_runtime_get_sync(device);
5609         pm_runtime_disable(device);
5610 }
5611
5612 /* Set up chip specific power management-related functions */
5613 void intel_init_pm(struct drm_device *dev)
5614 {
5615         struct drm_i915_private *dev_priv = dev->dev_private;
5616
5617         if (HAS_FBC(dev)) {
5618                 if (INTEL_INFO(dev)->gen >= 7) {
5619                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5620                         dev_priv->display.enable_fbc = gen7_enable_fbc;
5621                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
5622                 } else if (INTEL_INFO(dev)->gen >= 5) {
5623                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5624                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
5625                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
5626                 } else if (IS_GM45(dev)) {
5627                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5628                         dev_priv->display.enable_fbc = g4x_enable_fbc;
5629                         dev_priv->display.disable_fbc = g4x_disable_fbc;
5630                 } else {
5631                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5632                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
5633                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
5634
5635                         /* This value was pulled out of someone's hat */
5636                         I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
5637                 }
5638         }
5639
5640         /* For cxsr */
5641         if (IS_PINEVIEW(dev))
5642                 i915_pineview_get_mem_freq(dev);
5643         else if (IS_GEN5(dev))
5644                 i915_ironlake_get_mem_freq(dev);
5645
5646         /* For FIFO watermark updates */
5647         if (HAS_PCH_SPLIT(dev)) {
5648                 intel_setup_wm_latency(dev);
5649
5650                 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
5651                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
5652                     (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
5653                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
5654                         dev_priv->display.update_wm = ilk_update_wm;
5655                         dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
5656                 } else {
5657                         DRM_DEBUG_KMS("Failed to read display plane latency. "
5658                                       "Disable CxSR\n");
5659                 }
5660
5661                 if (IS_GEN5(dev))
5662                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
5663                 else if (IS_GEN6(dev))
5664                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
5665                 else if (IS_IVYBRIDGE(dev))
5666                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
5667                 else if (IS_HASWELL(dev))
5668                         dev_priv->display.init_clock_gating = haswell_init_clock_gating;
5669                 else if (INTEL_INFO(dev)->gen == 8)
5670                         dev_priv->display.init_clock_gating = gen8_init_clock_gating;
5671         } else if (IS_VALLEYVIEW(dev)) {
5672                 dev_priv->display.update_wm = valleyview_update_wm;
5673                 dev_priv->display.init_clock_gating =
5674                         valleyview_init_clock_gating;
5675         } else if (IS_PINEVIEW(dev)) {
5676                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5677                                             dev_priv->is_ddr3,
5678                                             dev_priv->fsb_freq,
5679                                             dev_priv->mem_freq)) {
5680                         DRM_INFO("failed to find known CxSR latency "
5681                                  "(found ddr%s fsb freq %d, mem freq %d), "
5682                                  "disabling CxSR\n",
5683                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
5684                                  dev_priv->fsb_freq, dev_priv->mem_freq);
5685                         /* Disable CxSR and never update its watermark again */
5686                         pineview_disable_cxsr(dev);
5687                         dev_priv->display.update_wm = NULL;
5688                 } else
5689                         dev_priv->display.update_wm = pineview_update_wm;
5690                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5691         } else if (IS_G4X(dev)) {
5692                 dev_priv->display.update_wm = g4x_update_wm;
5693                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
5694         } else if (IS_GEN4(dev)) {
5695                 dev_priv->display.update_wm = i965_update_wm;
5696                 if (IS_CRESTLINE(dev))
5697                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
5698                 else if (IS_BROADWATER(dev))
5699                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
5700         } else if (IS_GEN3(dev)) {
5701                 dev_priv->display.update_wm = i9xx_update_wm;
5702                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5703                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5704         } else if (IS_GEN2(dev)) {
5705                 if (INTEL_INFO(dev)->num_pipes == 1) {
5706                         dev_priv->display.update_wm = i845_update_wm;
5707                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
5708                 } else {
5709                         dev_priv->display.update_wm = i9xx_update_wm;
5710                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
5711                 }
5712
5713                 if (IS_I85X(dev) || IS_I865G(dev))
5714                         dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5715                 else
5716                         dev_priv->display.init_clock_gating = i830_init_clock_gating;
5717         } else {
5718                 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
5719         }
5720 }
5721
5722 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
5723 {
5724         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5725
5726         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5727                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
5728                 return -EAGAIN;
5729         }
5730
5731         I915_WRITE(GEN6_PCODE_DATA, *val);
5732         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5733
5734         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5735                      500)) {
5736                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
5737                 return -ETIMEDOUT;
5738         }
5739
5740         *val = I915_READ(GEN6_PCODE_DATA);
5741         I915_WRITE(GEN6_PCODE_DATA, 0);
5742
5743         return 0;
5744 }
5745
5746 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
5747 {
5748         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5749
5750         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5751                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
5752                 return -EAGAIN;
5753         }
5754
5755         I915_WRITE(GEN6_PCODE_DATA, val);
5756         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5757
5758         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5759                      500)) {
5760                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
5761                 return -ETIMEDOUT;
5762         }
5763
5764         I915_WRITE(GEN6_PCODE_DATA, 0);
5765
5766         return 0;
5767 }
5768
5769 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
5770 {
5771         int div;
5772
5773         /* 4 x czclk */
5774         switch (dev_priv->mem_freq) {
5775         case 800:
5776                 div = 10;
5777                 break;
5778         case 1066:
5779                 div = 12;
5780                 break;
5781         case 1333:
5782                 div = 16;
5783                 break;
5784         default:
5785                 return -1;
5786         }
5787
5788         return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
5789 }
5790
5791 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
5792 {
5793         int mul;
5794
5795         /* 4 x czclk */
5796         switch (dev_priv->mem_freq) {
5797         case 800:
5798                 mul = 10;
5799                 break;
5800         case 1066:
5801                 mul = 12;
5802                 break;
5803         case 1333:
5804                 mul = 16;
5805                 break;
5806         default:
5807                 return -1;
5808         }
5809
5810         return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
5811 }
5812
5813 void intel_pm_setup(struct drm_device *dev)
5814 {
5815         struct drm_i915_private *dev_priv = dev->dev_private;
5816
5817         mutex_init(&dev_priv->rps.hw_lock);
5818
5819         mutex_init(&dev_priv->pc8.lock);
5820         dev_priv->pc8.requirements_met = false;
5821         dev_priv->pc8.irqs_disabled = false;
5822         dev_priv->pc8.enabled = false;
5823         dev_priv->pc8.disable_count = 1; /* requirements_met */
5824         INIT_DELAYED_WORK(&dev_priv->pc8.enable_work, hsw_enable_pc8_work);
5825         INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
5826                           intel_gen6_powersave_work);
5827 }