drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "../../../platform/x86/intel_ips.h"
  32 #include <linux/module.h>
  33
  34 #define FORCEWAKE_ACK_TIMEOUT_MS 2
  35
  36 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
  37  * framebuffer contents in-memory, aiming at reducing the required bandwidth
  38  * during in-memory transfers and, therefore, reduce the power packet.
  39  *
  40  * The benefits of FBC are mostly visible with solid backgrounds and
  41  * variation-less patterns.
  42  *
  43  * FBC-related functionality can be enabled by the means of the
  44  * i915.i915_enable_fbc parameter
  45  */
  46
  47 static void i8xx_disable_fbc(struct drm_device *dev)
  48 {
  49         struct drm_i915_private *dev_priv = dev->dev_private;
  50         u32 fbc_ctl;
  51
  52         /* Disable compression */
  53         fbc_ctl = I915_READ(FBC_CONTROL);
  54         if ((fbc_ctl & FBC_CTL_EN) == 0)
  55                 return;
  56
  57         fbc_ctl &= ~FBC_CTL_EN;
  58         I915_WRITE(FBC_CONTROL, fbc_ctl);
  59
  60         /* Wait for compressing bit to clear */
  61         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
  62                 DRM_DEBUG_KMS("FBC idle timed out\n");
  63                 return;
  64         }
  65
  66         DRM_DEBUG_KMS("disabled FBC\n");
  67 }
  68
  69 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  70 {
  71         struct drm_device *dev = crtc->dev;
  72         struct drm_i915_private *dev_priv = dev->dev_private;
  73         struct drm_framebuffer *fb = crtc->fb;
  74         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  75         struct drm_i915_gem_object *obj = intel_fb->obj;
  76         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  77         int cfb_pitch;
  78         int plane, i;
  79         u32 fbc_ctl, fbc_ctl2;
  80
  81         cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
  82         if (fb->pitches[0] < cfb_pitch)
  83                 cfb_pitch = fb->pitches[0];
  84
  85         /* FBC_CTL wants 64B units */
  86         cfb_pitch = (cfb_pitch / 64) - 1;
  87         plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
  88
  89         /* Clear old tags */
  90         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
  91                 I915_WRITE(FBC_TAG + (i * 4), 0);
  92
  93         /* Set it up... */
  94         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
  95         fbc_ctl2 |= plane;
  96         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
  97         I915_WRITE(FBC_FENCE_OFF, crtc->y);
  98
  99         /* enable it... */
 100         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
 101         if (IS_I945GM(dev))
 102                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 103         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 104         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
 105         fbc_ctl |= obj->fence_reg;
 106         I915_WRITE(FBC_CONTROL, fbc_ctl);
 107
 108         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
 109                       cfb_pitch, crtc->y, intel_crtc->plane);
 110 }
 111
 112 static bool i8xx_fbc_enabled(struct drm_device *dev)
 113 {
 114         struct drm_i915_private *dev_priv = dev->dev_private;
 115
 116         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
 117 }
 118
 119 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 120 {
 121         struct drm_device *dev = crtc->dev;
 122         struct drm_i915_private *dev_priv = dev->dev_private;
 123         struct drm_framebuffer *fb = crtc->fb;
 124         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 125         struct drm_i915_gem_object *obj = intel_fb->obj;
 126         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 127         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
 128         unsigned long stall_watermark = 200;
 129         u32 dpfc_ctl;
 130
 131         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
 132         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
 133         I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
 134
 135         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
 136                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
 137                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
 138         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
 139
 140         /* enable it... */
 141         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
 142
 143         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
 144 }
 145
 146 static void g4x_disable_fbc(struct drm_device *dev)
 147 {
 148         struct drm_i915_private *dev_priv = dev->dev_private;
 149         u32 dpfc_ctl;
 150
 151         /* Disable compression */
 152         dpfc_ctl = I915_READ(DPFC_CONTROL);
 153         if (dpfc_ctl & DPFC_CTL_EN) {
 154                 dpfc_ctl &= ~DPFC_CTL_EN;
 155                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
 156
 157                 DRM_DEBUG_KMS("disabled FBC\n");
 158         }
 159 }
 160
 161 static bool g4x_fbc_enabled(struct drm_device *dev)
 162 {
 163         struct drm_i915_private *dev_priv = dev->dev_private;
 164
 165         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
 166 }
 167
 168 static void sandybridge_blit_fbc_update(struct drm_device *dev)
 169 {
 170         struct drm_i915_private *dev_priv = dev->dev_private;
 171         u32 blt_ecoskpd;
 172
 173         /* Make sure blitter notifies FBC of writes */
 174         gen6_gt_force_wake_get(dev_priv);
 175         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
 176         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
 177                 GEN6_BLITTER_LOCK_SHIFT;
 178         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 179         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
 180         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 181         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
 182                          GEN6_BLITTER_LOCK_SHIFT);
 183         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 184         POSTING_READ(GEN6_BLITTER_ECOSKPD);
 185         gen6_gt_force_wake_put(dev_priv);
 186 }
 187
 188 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 189 {
 190         struct drm_device *dev = crtc->dev;
 191         struct drm_i915_private *dev_priv = dev->dev_private;
 192         struct drm_framebuffer *fb = crtc->fb;
 193         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 194         struct drm_i915_gem_object *obj = intel_fb->obj;
 195         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 196         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
 197         unsigned long stall_watermark = 200;
 198         u32 dpfc_ctl;
 199
 200         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 201         dpfc_ctl &= DPFC_RESERVED;
 202         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
 203         /* Set persistent mode for front-buffer rendering, ala X. */
 204         dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
 205         dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
 206         I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
 207
 208         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
 209                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
 210                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
 211         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
 212         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
 213         /* enable it... */
 214         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 215
 216         if (IS_GEN6(dev)) {
 217                 I915_WRITE(SNB_DPFC_CTL_SA,
 218                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 219                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
 220                 sandybridge_blit_fbc_update(dev);
 221         }
 222
 223         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
 224 }
 225
 226 static void ironlake_disable_fbc(struct drm_device *dev)
 227 {
 228         struct drm_i915_private *dev_priv = dev->dev_private;
 229         u32 dpfc_ctl;
 230
 231         /* Disable compression */
 232         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 233         if (dpfc_ctl & DPFC_CTL_EN) {
 234                 dpfc_ctl &= ~DPFC_CTL_EN;
 235                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
 236
 237                 DRM_DEBUG_KMS("disabled FBC\n");
 238         }
 239 }
 240
 241 static bool ironlake_fbc_enabled(struct drm_device *dev)
 242 {
 243         struct drm_i915_private *dev_priv = dev->dev_private;
 244
 245         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 246 }
 247
 248 bool intel_fbc_enabled(struct drm_device *dev)
 249 {
 250         struct drm_i915_private *dev_priv = dev->dev_private;
 251
 252         if (!dev_priv->display.fbc_enabled)
 253                 return false;
 254
 255         return dev_priv->display.fbc_enabled(dev);
 256 }
 257
 258 static void intel_fbc_work_fn(struct work_struct *__work)
 259 {
 260         struct intel_fbc_work *work =
 261                 container_of(to_delayed_work(__work),
 262                              struct intel_fbc_work, work);
 263         struct drm_device *dev = work->crtc->dev;
 264         struct drm_i915_private *dev_priv = dev->dev_private;
 265
 266         mutex_lock(&dev->struct_mutex);
 267         if (work == dev_priv->fbc_work) {
 268                 /* Double check that we haven't switched fb without cancelling
 269                  * the prior work.
 270                  */
 271                 if (work->crtc->fb == work->fb) {
 272                         dev_priv->display.enable_fbc(work->crtc,
 273                                                      work->interval);
 274
 275                         dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
 276                         dev_priv->cfb_fb = work->crtc->fb->base.id;
 277                         dev_priv->cfb_y = work->crtc->y;
 278                 }
 279
 280                 dev_priv->fbc_work = NULL;
 281         }
 282         mutex_unlock(&dev->struct_mutex);
 283
 284         kfree(work);
 285 }
 286
 287 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
 288 {
 289         if (dev_priv->fbc_work == NULL)
 290                 return;
 291
 292         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
 293
 294         /* Synchronisation is provided by struct_mutex and checking of
 295          * dev_priv->fbc_work, so we can perform the cancellation
 296          * entirely asynchronously.
 297          */
 298         if (cancel_delayed_work(&dev_priv->fbc_work->work))
 299                 /* tasklet was killed before being run, clean up */
 300                 kfree(dev_priv->fbc_work);
 301
 302         /* Mark the work as no longer wanted so that if it does
 303          * wake-up (because the work was already running and waiting
 304          * for our mutex), it will discover that is no longer
 305          * necessary to run.
 306          */
 307         dev_priv->fbc_work = NULL;
 308 }
 309
 310 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 311 {
 312         struct intel_fbc_work *work;
 313         struct drm_device *dev = crtc->dev;
 314         struct drm_i915_private *dev_priv = dev->dev_private;
 315
 316         if (!dev_priv->display.enable_fbc)
 317                 return;
 318
 319         intel_cancel_fbc_work(dev_priv);
 320
 321         work = kzalloc(sizeof *work, GFP_KERNEL);
 322         if (work == NULL) {
 323                 dev_priv->display.enable_fbc(crtc, interval);
 324                 return;
 325         }
 326
 327         work->crtc = crtc;
 328         work->fb = crtc->fb;
 329         work->interval = interval;
 330         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
 331
 332         dev_priv->fbc_work = work;
 333
 334         DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
 335
 336         /* Delay the actual enabling to let pageflipping cease and the
 337          * display to settle before starting the compression. Note that
 338          * this delay also serves a second purpose: it allows for a
 339          * vblank to pass after disabling the FBC before we attempt
 340          * to modify the control registers.
 341          *
 342          * A more complicated solution would involve tracking vblanks
 343          * following the termination of the page-flipping sequence
 344          * and indeed performing the enable as a co-routine and not
 345          * waiting synchronously upon the vblank.
 346          */
 347         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
 348 }
 349
 350 void intel_disable_fbc(struct drm_device *dev)
 351 {
 352         struct drm_i915_private *dev_priv = dev->dev_private;
 353
 354         intel_cancel_fbc_work(dev_priv);
 355
 356         if (!dev_priv->display.disable_fbc)
 357                 return;
 358
 359         dev_priv->display.disable_fbc(dev);
 360         dev_priv->cfb_plane = -1;
 361 }
 362
 363 /**
 364  * intel_update_fbc - enable/disable FBC as needed
 365  * @dev: the drm_device
 366  *
 367  * Set up the framebuffer compression hardware at mode set time.  We
 368  * enable it if possible:
 369  *   - plane A only (on pre-965)
 370  *   - no pixel mulitply/line duplication
 371  *   - no alpha buffer discard
 372  *   - no dual wide
 373  *   - framebuffer <= 2048 in width, 1536 in height
 374  *
 375  * We can't assume that any compression will take place (worst case),
 376  * so the compressed buffer has to be the same size as the uncompressed
 377  * one.  It also must reside (along with the line length buffer) in
 378  * stolen memory.
 379  *
 380  * We need to enable/disable FBC on a global basis.
 381  */
 382 void intel_update_fbc(struct drm_device *dev)
 383 {
 384         struct drm_i915_private *dev_priv = dev->dev_private;
 385         struct drm_crtc *crtc = NULL, *tmp_crtc;
 386         struct intel_crtc *intel_crtc;
 387         struct drm_framebuffer *fb;
 388         struct intel_framebuffer *intel_fb;
 389         struct drm_i915_gem_object *obj;
 390         int enable_fbc;
 391
 392         if (!i915_powersave)
 393                 return;
 394
 395         if (!I915_HAS_FBC(dev))
 396                 return;
 397
 398         /*
 399          * If FBC is already on, we just have to verify that we can
 400          * keep it that way...
 401          * Need to disable if:
 402          *   - more than one pipe is active
 403          *   - changing FBC params (stride, fence, mode)
 404          *   - new fb is too large to fit in compressed buffer
 405          *   - going to an unsupported config (interlace, pixel multiply, etc.)
 406          */
 407         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
 408                 if (tmp_crtc->enabled &&
 409                     !to_intel_crtc(tmp_crtc)->primary_disabled &&
 410                     tmp_crtc->fb) {
 411                         if (crtc) {
 412                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
 413                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
 414                                 goto out_disable;
 415                         }
 416                         crtc = tmp_crtc;
 417                 }
 418         }
 419
 420         if (!crtc || crtc->fb == NULL) {
 421                 DRM_DEBUG_KMS("no output, disabling\n");
 422                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
 423                 goto out_disable;
 424         }
 425
 426         intel_crtc = to_intel_crtc(crtc);
 427         fb = crtc->fb;
 428         intel_fb = to_intel_framebuffer(fb);
 429         obj = intel_fb->obj;
 430
 431         enable_fbc = i915_enable_fbc;
 432         if (enable_fbc < 0) {
 433                 DRM_DEBUG_KMS("fbc set to per-chip default\n");
 434                 enable_fbc = 1;
 435                 if (INTEL_INFO(dev)->gen <= 6)
 436                         enable_fbc = 0;
 437         }
 438         if (!enable_fbc) {
 439                 DRM_DEBUG_KMS("fbc disabled per module param\n");
 440                 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
 441                 goto out_disable;
 442         }
 443         if (intel_fb->obj->base.size > dev_priv->cfb_size) {
 444                 DRM_DEBUG_KMS("framebuffer too large, disabling "
 445                               "compression\n");
 446                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
 447                 goto out_disable;
 448         }
 449         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
 450             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
 451                 DRM_DEBUG_KMS("mode incompatible with compression, "
 452                               "disabling\n");
 453                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
 454                 goto out_disable;
 455         }
 456         if ((crtc->mode.hdisplay > 2048) ||
 457             (crtc->mode.vdisplay > 1536)) {
 458                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
 459                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
 460                 goto out_disable;
 461         }
 462         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
 463                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
 464                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
 465                 goto out_disable;
 466         }
 467
 468         /* The use of a CPU fence is mandatory in order to detect writes
 469          * by the CPU to the scanout and trigger updates to the FBC.
 470          */
 471         if (obj->tiling_mode != I915_TILING_X ||
 472             obj->fence_reg == I915_FENCE_REG_NONE) {
 473                 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
 474                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
 475                 goto out_disable;
 476         }
 477
 478         /* If the kernel debugger is active, always disable compression */
 479         if (in_dbg_master())
 480                 goto out_disable;
 481
 482         /* If the scanout has not changed, don't modify the FBC settings.
 483          * Note that we make the fundamental assumption that the fb->obj
 484          * cannot be unpinned (and have its GTT offset and fence revoked)
 485          * without first being decoupled from the scanout and FBC disabled.
 486          */
 487         if (dev_priv->cfb_plane == intel_crtc->plane &&
 488             dev_priv->cfb_fb == fb->base.id &&
 489             dev_priv->cfb_y == crtc->y)
 490                 return;
 491
 492         if (intel_fbc_enabled(dev)) {
 493                 /* We update FBC along two paths, after changing fb/crtc
 494                  * configuration (modeswitching) and after page-flipping
 495                  * finishes. For the latter, we know that not only did
 496                  * we disable the FBC at the start of the page-flip
 497                  * sequence, but also more than one vblank has passed.
 498                  *
 499                  * For the former case of modeswitching, it is possible
 500                  * to switch between two FBC valid configurations
 501                  * instantaneously so we do need to disable the FBC
 502                  * before we can modify its control registers. We also
 503                  * have to wait for the next vblank for that to take
 504                  * effect. However, since we delay enabling FBC we can
 505                  * assume that a vblank has passed since disabling and
 506                  * that we can safely alter the registers in the deferred
 507                  * callback.
 508                  *
 509                  * In the scenario that we go from a valid to invalid
 510                  * and then back to valid FBC configuration we have
 511                  * no strict enforcement that a vblank occurred since
 512                  * disabling the FBC. However, along all current pipe
 513                  * disabling paths we do need to wait for a vblank at
 514                  * some point. And we wait before enabling FBC anyway.
 515                  */
 516                 DRM_DEBUG_KMS("disabling active FBC for update\n");
 517                 intel_disable_fbc(dev);
 518         }
 519
 520         intel_enable_fbc(crtc, 500);
 521         return;
 522
 523 out_disable:
 524         /* Multiple disables should be harmless */
 525         if (intel_fbc_enabled(dev)) {
 526                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
 527                 intel_disable_fbc(dev);
 528         }
 529 }
 530
 531 static void i915_pineview_get_mem_freq(struct drm_device *dev)
 532 {
 533         drm_i915_private_t *dev_priv = dev->dev_private;
 534         u32 tmp;
 535
 536         tmp = I915_READ(CLKCFG);
 537
 538         switch (tmp & CLKCFG_FSB_MASK) {
 539         case CLKCFG_FSB_533:
 540                 dev_priv->fsb_freq = 533; /* 133*4 */
 541                 break;
 542         case CLKCFG_FSB_800:
 543                 dev_priv->fsb_freq = 800; /* 200*4 */
 544                 break;
 545         case CLKCFG_FSB_667:
 546                 dev_priv->fsb_freq =  667; /* 167*4 */
 547                 break;
 548         case CLKCFG_FSB_400:
 549                 dev_priv->fsb_freq = 400; /* 100*4 */
 550                 break;
 551         }
 552
 553         switch (tmp & CLKCFG_MEM_MASK) {
 554         case CLKCFG_MEM_533:
 555                 dev_priv->mem_freq = 533;
 556                 break;
 557         case CLKCFG_MEM_667:
 558                 dev_priv->mem_freq = 667;
 559                 break;
 560         case CLKCFG_MEM_800:
 561                 dev_priv->mem_freq = 800;
 562                 break;
 563         }
 564
 565         /* detect pineview DDR3 setting */
 566         tmp = I915_READ(CSHRDDR3CTL);
 567         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 568 }
 569
 570 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 571 {
 572         drm_i915_private_t *dev_priv = dev->dev_private;
 573         u16 ddrpll, csipll;
 574
 575         ddrpll = I915_READ16(DDRMPLL1);
 576         csipll = I915_READ16(CSIPLL0);
 577
 578         switch (ddrpll & 0xff) {
 579         case 0xc:
 580                 dev_priv->mem_freq = 800;
 581                 break;
 582         case 0x10:
 583                 dev_priv->mem_freq = 1066;
 584                 break;
 585         case 0x14:
 586                 dev_priv->mem_freq = 1333;
 587                 break;
 588         case 0x18:
 589                 dev_priv->mem_freq = 1600;
 590                 break;
 591         default:
 592                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 593                                  ddrpll & 0xff);
 594                 dev_priv->mem_freq = 0;
 595                 break;
 596         }
 597
 598         dev_priv->ips.r_t = dev_priv->mem_freq;
 599
 600         switch (csipll & 0x3ff) {
 601         case 0x00c:
 602                 dev_priv->fsb_freq = 3200;
 603                 break;
 604         case 0x00e:
 605                 dev_priv->fsb_freq = 3733;
 606                 break;
 607         case 0x010:
 608                 dev_priv->fsb_freq = 4266;
 609                 break;
 610         case 0x012:
 611                 dev_priv->fsb_freq = 4800;
 612                 break;
 613         case 0x014:
 614                 dev_priv->fsb_freq = 5333;
 615                 break;
 616         case 0x016:
 617                 dev_priv->fsb_freq = 5866;
 618                 break;
 619         case 0x018:
 620                 dev_priv->fsb_freq = 6400;
 621                 break;
 622         default:
 623                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 624                                  csipll & 0x3ff);
 625                 dev_priv->fsb_freq = 0;
 626                 break;
 627         }
 628
 629         if (dev_priv->fsb_freq == 3200) {
 630                 dev_priv->ips.c_m = 0;
 631         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 632                 dev_priv->ips.c_m = 1;
 633         } else {
 634                 dev_priv->ips.c_m = 2;
 635         }
 636 }
 637
 638 static const struct cxsr_latency cxsr_latency_table[] = {
 639         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 640         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 641         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 642         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 643         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 644
 645         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 646         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 647         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 648         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 649         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 650
 651         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 652         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 653         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 654         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 655         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 656
 657         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 658         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 659         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 660         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 661         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 662
 663         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 664         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 665         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 666         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 667         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 668
 669         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 670         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 671         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 672         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 673         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 674 };
 675
 676 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 677                                                          int is_ddr3,
 678                                                          int fsb,
 679                                                          int mem)
 680 {
 681         const struct cxsr_latency *latency;
 682         int i;
 683
 684         if (fsb == 0 || mem == 0)
 685                 return NULL;
 686
 687         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 688                 latency = &cxsr_latency_table[i];
 689                 if (is_desktop == latency->is_desktop &&
 690                     is_ddr3 == latency->is_ddr3 &&
 691                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 692                         return latency;
 693         }
 694
 695         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 696
 697         return NULL;
 698 }
 699
 700 static void pineview_disable_cxsr(struct drm_device *dev)
 701 {
 702         struct drm_i915_private *dev_priv = dev->dev_private;
 703
 704         /* deactivate cxsr */
 705         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
 706 }
 707
 708 /*
 709  * Latency for FIFO fetches is dependent on several factors:
 710  *   - memory configuration (speed, channels)
 711  *   - chipset
 712  *   - current MCH state
 713  * It can be fairly high in some situations, so here we assume a fairly
 714  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 715  * set this value too high, the FIFO will fetch frequently to stay full)
 716  * and power consumption (set it too low to save power and we might see
 717  * FIFO underruns and display "flicker").
 718  *
 719  * A value of 5us seems to be a good balance; safe for very low end
 720  * platforms but not overly aggressive on lower latency configs.
 721  */
 722 static const int latency_ns = 5000;
 723
 724 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 725 {
 726         struct drm_i915_private *dev_priv = dev->dev_private;
 727         uint32_t dsparb = I915_READ(DSPARB);
 728         int size;
 729
 730         size = dsparb & 0x7f;
 731         if (plane)
 732                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 733
 734         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 735                       plane ? "B" : "A", size);
 736
 737         return size;
 738 }
 739
 740 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
 741 {
 742         struct drm_i915_private *dev_priv = dev->dev_private;
 743         uint32_t dsparb = I915_READ(DSPARB);
 744         int size;
 745
 746         size = dsparb & 0x1ff;
 747         if (plane)
 748                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 749         size >>= 1; /* Convert to cachelines */
 750
 751         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 752                       plane ? "B" : "A", size);
 753
 754         return size;
 755 }
 756
 757 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 758 {
 759         struct drm_i915_private *dev_priv = dev->dev_private;
 760         uint32_t dsparb = I915_READ(DSPARB);
 761         int size;
 762
 763         size = dsparb & 0x7f;
 764         size >>= 2; /* Convert to cachelines */
 765
 766         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 767                       plane ? "B" : "A",
 768                       size);
 769
 770         return size;
 771 }
 772
 773 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 774 {
 775         struct drm_i915_private *dev_priv = dev->dev_private;
 776         uint32_t dsparb = I915_READ(DSPARB);
 777         int size;
 778
 779         size = dsparb & 0x7f;
 780         size >>= 1; /* Convert to cachelines */
 781
 782         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 783                       plane ? "B" : "A", size);
 784
 785         return size;
 786 }
 787
 788 /* Pineview has different values for various configs */
 789 static const struct intel_watermark_params pineview_display_wm = {
 790         PINEVIEW_DISPLAY_FIFO,
 791         PINEVIEW_MAX_WM,
 792         PINEVIEW_DFT_WM,
 793         PINEVIEW_GUARD_WM,
 794         PINEVIEW_FIFO_LINE_SIZE
 795 };
 796 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 797         PINEVIEW_DISPLAY_FIFO,
 798         PINEVIEW_MAX_WM,
 799         PINEVIEW_DFT_HPLLOFF_WM,
 800         PINEVIEW_GUARD_WM,
 801         PINEVIEW_FIFO_LINE_SIZE
 802 };
 803 static const struct intel_watermark_params pineview_cursor_wm = {
 804         PINEVIEW_CURSOR_FIFO,
 805         PINEVIEW_CURSOR_MAX_WM,
 806         PINEVIEW_CURSOR_DFT_WM,
 807         PINEVIEW_CURSOR_GUARD_WM,
 808         PINEVIEW_FIFO_LINE_SIZE,
 809 };
 810 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 811         PINEVIEW_CURSOR_FIFO,
 812         PINEVIEW_CURSOR_MAX_WM,
 813         PINEVIEW_CURSOR_DFT_WM,
 814         PINEVIEW_CURSOR_GUARD_WM,
 815         PINEVIEW_FIFO_LINE_SIZE
 816 };
 817 static const struct intel_watermark_params g4x_wm_info = {
 818         G4X_FIFO_SIZE,
 819         G4X_MAX_WM,
 820         G4X_MAX_WM,
 821         2,
 822         G4X_FIFO_LINE_SIZE,
 823 };
 824 static const struct intel_watermark_params g4x_cursor_wm_info = {
 825         I965_CURSOR_FIFO,
 826         I965_CURSOR_MAX_WM,
 827         I965_CURSOR_DFT_WM,
 828         2,
 829         G4X_FIFO_LINE_SIZE,
 830 };
 831 static const struct intel_watermark_params valleyview_wm_info = {
 832         VALLEYVIEW_FIFO_SIZE,
 833         VALLEYVIEW_MAX_WM,
 834         VALLEYVIEW_MAX_WM,
 835         2,
 836         G4X_FIFO_LINE_SIZE,
 837 };
 838 static const struct intel_watermark_params valleyview_cursor_wm_info = {
 839         I965_CURSOR_FIFO,
 840         VALLEYVIEW_CURSOR_MAX_WM,
 841         I965_CURSOR_DFT_WM,
 842         2,
 843         G4X_FIFO_LINE_SIZE,
 844 };
 845 static const struct intel_watermark_params i965_cursor_wm_info = {
 846         I965_CURSOR_FIFO,
 847         I965_CURSOR_MAX_WM,
 848         I965_CURSOR_DFT_WM,
 849         2,
 850         I915_FIFO_LINE_SIZE,
 851 };
 852 static const struct intel_watermark_params i945_wm_info = {
 853         I945_FIFO_SIZE,
 854         I915_MAX_WM,
 855         1,
 856         2,
 857         I915_FIFO_LINE_SIZE
 858 };
 859 static const struct intel_watermark_params i915_wm_info = {
 860         I915_FIFO_SIZE,
 861         I915_MAX_WM,
 862         1,
 863         2,
 864         I915_FIFO_LINE_SIZE
 865 };
 866 static const struct intel_watermark_params i855_wm_info = {
 867         I855GM_FIFO_SIZE,
 868         I915_MAX_WM,
 869         1,
 870         2,
 871         I830_FIFO_LINE_SIZE
 872 };
 873 static const struct intel_watermark_params i830_wm_info = {
 874         I830_FIFO_SIZE,
 875         I915_MAX_WM,
 876         1,
 877         2,
 878         I830_FIFO_LINE_SIZE
 879 };
 880
 881 static const struct intel_watermark_params ironlake_display_wm_info = {
 882         ILK_DISPLAY_FIFO,
 883         ILK_DISPLAY_MAXWM,
 884         ILK_DISPLAY_DFTWM,
 885         2,
 886         ILK_FIFO_LINE_SIZE
 887 };
 888 static const struct intel_watermark_params ironlake_cursor_wm_info = {
 889         ILK_CURSOR_FIFO,
 890         ILK_CURSOR_MAXWM,
 891         ILK_CURSOR_DFTWM,
 892         2,
 893         ILK_FIFO_LINE_SIZE
 894 };
 895 static const struct intel_watermark_params ironlake_display_srwm_info = {
 896         ILK_DISPLAY_SR_FIFO,
 897         ILK_DISPLAY_MAX_SRWM,
 898         ILK_DISPLAY_DFT_SRWM,
 899         2,
 900         ILK_FIFO_LINE_SIZE
 901 };
 902 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
 903         ILK_CURSOR_SR_FIFO,
 904         ILK_CURSOR_MAX_SRWM,
 905         ILK_CURSOR_DFT_SRWM,
 906         2,
 907         ILK_FIFO_LINE_SIZE
 908 };
 909
 910 static const struct intel_watermark_params sandybridge_display_wm_info = {
 911         SNB_DISPLAY_FIFO,
 912         SNB_DISPLAY_MAXWM,
 913         SNB_DISPLAY_DFTWM,
 914         2,
 915         SNB_FIFO_LINE_SIZE
 916 };
 917 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
 918         SNB_CURSOR_FIFO,
 919         SNB_CURSOR_MAXWM,
 920         SNB_CURSOR_DFTWM,
 921         2,
 922         SNB_FIFO_LINE_SIZE
 923 };
 924 static const struct intel_watermark_params sandybridge_display_srwm_info = {
 925         SNB_DISPLAY_SR_FIFO,
 926         SNB_DISPLAY_MAX_SRWM,
 927         SNB_DISPLAY_DFT_SRWM,
 928         2,
 929         SNB_FIFO_LINE_SIZE
 930 };
 931 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
 932         SNB_CURSOR_SR_FIFO,
 933         SNB_CURSOR_MAX_SRWM,
 934         SNB_CURSOR_DFT_SRWM,
 935         2,
 936         SNB_FIFO_LINE_SIZE
 937 };
 938
 939
 940 /**
 941  * intel_calculate_wm - calculate watermark level
 942  * @clock_in_khz: pixel clock
 943  * @wm: chip FIFO params
 944  * @pixel_size: display pixel size
 945  * @latency_ns: memory latency for the platform
 946  *
 947  * Calculate the watermark level (the level at which the display plane will
 948  * start fetching from memory again).  Each chip has a different display
 949  * FIFO size and allocation, so the caller needs to figure that out and pass
 950  * in the correct intel_watermark_params structure.
 951  *
 952  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 953  * on the pixel size.  When it reaches the watermark level, it'll start
 954  * fetching FIFO line sized based chunks from memory until the FIFO fills
 955  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 956  * will occur, and a display engine hang could result.
 957  */
 958 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 959                                         const struct intel_watermark_params *wm,
 960                                         int fifo_size,
 961                                         int pixel_size,
 962                                         unsigned long latency_ns)
 963 {
 964         long entries_required, wm_size;
 965
 966         /*
 967          * Note: we need to make sure we don't overflow for various clock &
 968          * latency values.
 969          * clocks go from a few thousand to several hundred thousand.
 970          * latency is usually a few thousand
 971          */
 972         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
 973                 1000;
 974         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 975
 976         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 977
 978         wm_size = fifo_size - (entries_required + wm->guard_size);
 979
 980         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
 981
 982         /* Don't promote wm_size to unsigned... */
 983         if (wm_size > (long)wm->max_wm)
 984                 wm_size = wm->max_wm;
 985         if (wm_size <= 0)
 986                 wm_size = wm->default_wm;
 987         return wm_size;
 988 }
 989
 990 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
 991 {
 992         struct drm_crtc *crtc, *enabled = NULL;
 993
 994         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 995                 if (crtc->enabled && crtc->fb) {
 996                         if (enabled)
 997                                 return NULL;
 998                         enabled = crtc;
 999                 }
1000         }
1001
1002         return enabled;
1003 }
1004
1005 static void pineview_update_wm(struct drm_device *dev)
1006 {
1007         struct drm_i915_private *dev_priv = dev->dev_private;
1008         struct drm_crtc *crtc;
1009         const struct cxsr_latency *latency;
1010         u32 reg;
1011         unsigned long wm;
1012
1013         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1014                                          dev_priv->fsb_freq, dev_priv->mem_freq);
1015         if (!latency) {
1016                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1017                 pineview_disable_cxsr(dev);
1018                 return;
1019         }
1020
1021         crtc = single_enabled_crtc(dev);
1022         if (crtc) {
1023                 int clock = crtc->mode.clock;
1024                 int pixel_size = crtc->fb->bits_per_pixel / 8;
1025
1026                 /* Display SR */
1027                 wm = intel_calculate_wm(clock, &pineview_display_wm,
1028                                         pineview_display_wm.fifo_size,
1029                                         pixel_size, latency->display_sr);
1030                 reg = I915_READ(DSPFW1);
1031                 reg &= ~DSPFW_SR_MASK;
1032                 reg |= wm << DSPFW_SR_SHIFT;
1033                 I915_WRITE(DSPFW1, reg);
1034                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1035
1036                 /* cursor SR */
1037                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1038                                         pineview_display_wm.fifo_size,
1039                                         pixel_size, latency->cursor_sr);
1040                 reg = I915_READ(DSPFW3);
1041                 reg &= ~DSPFW_CURSOR_SR_MASK;
1042                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1043                 I915_WRITE(DSPFW3, reg);
1044
1045                 /* Display HPLL off SR */
1046                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1047                                         pineview_display_hplloff_wm.fifo_size,
1048                                         pixel_size, latency->display_hpll_disable);
1049                 reg = I915_READ(DSPFW3);
1050                 reg &= ~DSPFW_HPLL_SR_MASK;
1051                 reg |= wm & DSPFW_HPLL_SR_MASK;
1052                 I915_WRITE(DSPFW3, reg);
1053
1054                 /* cursor HPLL off SR */
1055                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1056                                         pineview_display_hplloff_wm.fifo_size,
1057                                         pixel_size, latency->cursor_hpll_disable);
1058                 reg = I915_READ(DSPFW3);
1059                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1060                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1061                 I915_WRITE(DSPFW3, reg);
1062                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1063
1064                 /* activate cxsr */
1065                 I915_WRITE(DSPFW3,
1066                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1067                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1068         } else {
1069                 pineview_disable_cxsr(dev);
1070                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1071         }
1072 }
1073
1074 static bool g4x_compute_wm0(struct drm_device *dev,
1075                             int plane,
1076                             const struct intel_watermark_params *display,
1077                             int display_latency_ns,
1078                             const struct intel_watermark_params *cursor,
1079                             int cursor_latency_ns,
1080                             int *plane_wm,
1081                             int *cursor_wm)
1082 {
1083         struct drm_crtc *crtc;
1084         int htotal, hdisplay, clock, pixel_size;
1085         int line_time_us, line_count;
1086         int entries, tlb_miss;
1087
1088         crtc = intel_get_crtc_for_plane(dev, plane);
1089         if (crtc->fb == NULL || !crtc->enabled) {
1090                 *cursor_wm = cursor->guard_size;
1091                 *plane_wm = display->guard_size;
1092                 return false;
1093         }
1094
1095         htotal = crtc->mode.htotal;
1096         hdisplay = crtc->mode.hdisplay;
1097         clock = crtc->mode.clock;
1098         pixel_size = crtc->fb->bits_per_pixel / 8;
1099
1100         /* Use the small buffer method to calculate plane watermark */
1101         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1102         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1103         if (tlb_miss > 0)
1104                 entries += tlb_miss;
1105         entries = DIV_ROUND_UP(entries, display->cacheline_size);
1106         *plane_wm = entries + display->guard_size;
1107         if (*plane_wm > (int)display->max_wm)
1108                 *plane_wm = display->max_wm;
1109
1110         /* Use the large buffer method to calculate cursor watermark */
1111         line_time_us = ((htotal * 1000) / clock);
1112         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1113         entries = line_count * 64 * pixel_size;
1114         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1115         if (tlb_miss > 0)
1116                 entries += tlb_miss;
1117         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1118         *cursor_wm = entries + cursor->guard_size;
1119         if (*cursor_wm > (int)cursor->max_wm)
1120                 *cursor_wm = (int)cursor->max_wm;
1121
1122         return true;
1123 }
1124
1125 /*
1126  * Check the wm result.
1127  *
1128  * If any calculated watermark values is larger than the maximum value that
1129  * can be programmed into the associated watermark register, that watermark
1130  * must be disabled.
1131  */
1132 static bool g4x_check_srwm(struct drm_device *dev,
1133                            int display_wm, int cursor_wm,
1134                            const struct intel_watermark_params *display,
1135                            const struct intel_watermark_params *cursor)
1136 {
1137         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1138                       display_wm, cursor_wm);
1139
1140         if (display_wm > display->max_wm) {
1141                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1142                               display_wm, display->max_wm);
1143                 return false;
1144         }
1145
1146         if (cursor_wm > cursor->max_wm) {
1147                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1148                               cursor_wm, cursor->max_wm);
1149                 return false;
1150         }
1151
1152         if (!(display_wm || cursor_wm)) {
1153                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1154                 return false;
1155         }
1156
1157         return true;
1158 }
1159
1160 static bool g4x_compute_srwm(struct drm_device *dev,
1161                              int plane,
1162                              int latency_ns,
1163                              const struct intel_watermark_params *display,
1164                              const struct intel_watermark_params *cursor,
1165                              int *display_wm, int *cursor_wm)
1166 {
1167         struct drm_crtc *crtc;
1168         int hdisplay, htotal, pixel_size, clock;
1169         unsigned long line_time_us;
1170         int line_count, line_size;
1171         int small, large;
1172         int entries;
1173
1174         if (!latency_ns) {
1175                 *display_wm = *cursor_wm = 0;
1176                 return false;
1177         }
1178
1179         crtc = intel_get_crtc_for_plane(dev, plane);
1180         hdisplay = crtc->mode.hdisplay;
1181         htotal = crtc->mode.htotal;
1182         clock = crtc->mode.clock;
1183         pixel_size = crtc->fb->bits_per_pixel / 8;
1184
1185         line_time_us = (htotal * 1000) / clock;
1186         line_count = (latency_ns / line_time_us + 1000) / 1000;
1187         line_size = hdisplay * pixel_size;
1188
1189         /* Use the minimum of the small and large buffer method for primary */
1190         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1191         large = line_count * line_size;
1192
1193         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1194         *display_wm = entries + display->guard_size;
1195
1196         /* calculate the self-refresh watermark for display cursor */
1197         entries = line_count * pixel_size * 64;
1198         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1199         *cursor_wm = entries + cursor->guard_size;
1200
1201         return g4x_check_srwm(dev,
1202                               *display_wm, *cursor_wm,
1203                               display, cursor);
1204 }
1205
1206 static bool vlv_compute_drain_latency(struct drm_device *dev,
1207                                      int plane,
1208                                      int *plane_prec_mult,
1209                                      int *plane_dl,
1210                                      int *cursor_prec_mult,
1211                                      int *cursor_dl)
1212 {
1213         struct drm_crtc *crtc;
1214         int clock, pixel_size;
1215         int entries;
1216
1217         crtc = intel_get_crtc_for_plane(dev, plane);
1218         if (crtc->fb == NULL || !crtc->enabled)
1219                 return false;
1220
1221         clock = crtc->mode.clock;       /* VESA DOT Clock */
1222         pixel_size = crtc->fb->bits_per_pixel / 8;      /* BPP */
1223
1224         entries = (clock / 1000) * pixel_size;
1225         *plane_prec_mult = (entries > 256) ?
1226                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1227         *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1228                                                      pixel_size);
1229
1230         entries = (clock / 1000) * 4;   /* BPP is always 4 for cursor */
1231         *cursor_prec_mult = (entries > 256) ?
1232                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1233         *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1234
1235         return true;
1236 }
1237
1238 /*
1239  * Update drain latency registers of memory arbiter
1240  *
1241  * Valleyview SoC has a new memory arbiter and needs drain latency registers
1242  * to be programmed. Each plane has a drain latency multiplier and a drain
1243  * latency value.
1244  */
1245
1246 static void vlv_update_drain_latency(struct drm_device *dev)
1247 {
1248         struct drm_i915_private *dev_priv = dev->dev_private;
1249         int planea_prec, planea_dl, planeb_prec, planeb_dl;
1250         int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1251         int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1252                                                         either 16 or 32 */
1253
1254         /* For plane A, Cursor A */
1255         if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1256                                       &cursor_prec_mult, &cursora_dl)) {
1257                 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1258                         DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1259                 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1260                         DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1261
1262                 I915_WRITE(VLV_DDL1, cursora_prec |
1263                                 (cursora_dl << DDL_CURSORA_SHIFT) |
1264                                 planea_prec | planea_dl);
1265         }
1266
1267         /* For plane B, Cursor B */
1268         if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1269                                       &cursor_prec_mult, &cursorb_dl)) {
1270                 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1271                         DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1272                 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1273                         DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1274
1275                 I915_WRITE(VLV_DDL2, cursorb_prec |
1276                                 (cursorb_dl << DDL_CURSORB_SHIFT) |
1277                                 planeb_prec | planeb_dl);
1278         }
1279 }
1280
1281 #define single_plane_enabled(mask) is_power_of_2(mask)
1282
1283 static void valleyview_update_wm(struct drm_device *dev)
1284 {
1285         static const int sr_latency_ns = 12000;
1286         struct drm_i915_private *dev_priv = dev->dev_private;
1287         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1288         int plane_sr, cursor_sr;
1289         int ignore_plane_sr, ignore_cursor_sr;
1290         unsigned int enabled = 0;
1291
1292         vlv_update_drain_latency(dev);
1293
1294         if (g4x_compute_wm0(dev, 0,
1295                             &valleyview_wm_info, latency_ns,
1296                             &valleyview_cursor_wm_info, latency_ns,
1297                             &planea_wm, &cursora_wm))
1298                 enabled |= 1;
1299
1300         if (g4x_compute_wm0(dev, 1,
1301                             &valleyview_wm_info, latency_ns,
1302                             &valleyview_cursor_wm_info, latency_ns,
1303                             &planeb_wm, &cursorb_wm))
1304                 enabled |= 2;
1305
1306         plane_sr = cursor_sr = 0;
1307         if (single_plane_enabled(enabled) &&
1308             g4x_compute_srwm(dev, ffs(enabled) - 1,
1309                              sr_latency_ns,
1310                              &valleyview_wm_info,
1311                              &valleyview_cursor_wm_info,
1312                              &plane_sr, &ignore_cursor_sr) &&
1313             g4x_compute_srwm(dev, ffs(enabled) - 1,
1314                              2*sr_latency_ns,
1315                              &valleyview_wm_info,
1316                              &valleyview_cursor_wm_info,
1317                              &ignore_plane_sr, &cursor_sr))
1318                 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1319         else
1320                 I915_WRITE(FW_BLC_SELF_VLV,
1321                            I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1322
1323         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1324                       planea_wm, cursora_wm,
1325                       planeb_wm, cursorb_wm,
1326                       plane_sr, cursor_sr);
1327
1328         I915_WRITE(DSPFW1,
1329                    (plane_sr << DSPFW_SR_SHIFT) |
1330                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1331                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1332                    planea_wm);
1333         I915_WRITE(DSPFW2,
1334                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1335                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1336         I915_WRITE(DSPFW3,
1337                    (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1338                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1339 }
1340
1341 static void g4x_update_wm(struct drm_device *dev)
1342 {
1343         static const int sr_latency_ns = 12000;
1344         struct drm_i915_private *dev_priv = dev->dev_private;
1345         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1346         int plane_sr, cursor_sr;
1347         unsigned int enabled = 0;
1348
1349         if (g4x_compute_wm0(dev, 0,
1350                             &g4x_wm_info, latency_ns,
1351                             &g4x_cursor_wm_info, latency_ns,
1352                             &planea_wm, &cursora_wm))
1353                 enabled |= 1;
1354
1355         if (g4x_compute_wm0(dev, 1,
1356                             &g4x_wm_info, latency_ns,
1357                             &g4x_cursor_wm_info, latency_ns,
1358                             &planeb_wm, &cursorb_wm))
1359                 enabled |= 2;
1360
1361         plane_sr = cursor_sr = 0;
1362         if (single_plane_enabled(enabled) &&
1363             g4x_compute_srwm(dev, ffs(enabled) - 1,
1364                              sr_latency_ns,
1365                              &g4x_wm_info,
1366                              &g4x_cursor_wm_info,
1367                              &plane_sr, &cursor_sr))
1368                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1369         else
1370                 I915_WRITE(FW_BLC_SELF,
1371                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1372
1373         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1374                       planea_wm, cursora_wm,
1375                       planeb_wm, cursorb_wm,
1376                       plane_sr, cursor_sr);
1377
1378         I915_WRITE(DSPFW1,
1379                    (plane_sr << DSPFW_SR_SHIFT) |
1380                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1381                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1382                    planea_wm);
1383         I915_WRITE(DSPFW2,
1384                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1385                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1386         /* HPLL off in SR has some issues on G4x... disable it */
1387         I915_WRITE(DSPFW3,
1388                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1389                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1390 }
1391
1392 static void i965_update_wm(struct drm_device *dev)
1393 {
1394         struct drm_i915_private *dev_priv = dev->dev_private;
1395         struct drm_crtc *crtc;
1396         int srwm = 1;
1397         int cursor_sr = 16;
1398
1399         /* Calc sr entries for one plane configs */
1400         crtc = single_enabled_crtc(dev);
1401         if (crtc) {
1402                 /* self-refresh has much higher latency */
1403                 static const int sr_latency_ns = 12000;
1404                 int clock = crtc->mode.clock;
1405                 int htotal = crtc->mode.htotal;
1406                 int hdisplay = crtc->mode.hdisplay;
1407                 int pixel_size = crtc->fb->bits_per_pixel / 8;
1408                 unsigned long line_time_us;
1409                 int entries;
1410
1411                 line_time_us = ((htotal * 1000) / clock);
1412
1413                 /* Use ns/us then divide to preserve precision */
1414                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1415                         pixel_size * hdisplay;
1416                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1417                 srwm = I965_FIFO_SIZE - entries;
1418                 if (srwm < 0)
1419                         srwm = 1;
1420                 srwm &= 0x1ff;
1421                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1422                               entries, srwm);
1423
1424                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1425                         pixel_size * 64;
1426                 entries = DIV_ROUND_UP(entries,
1427                                           i965_cursor_wm_info.cacheline_size);
1428                 cursor_sr = i965_cursor_wm_info.fifo_size -
1429                         (entries + i965_cursor_wm_info.guard_size);
1430
1431                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1432                         cursor_sr = i965_cursor_wm_info.max_wm;
1433
1434                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1435                               "cursor %d\n", srwm, cursor_sr);
1436
1437                 if (IS_CRESTLINE(dev))
1438                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1439         } else {
1440                 /* Turn off self refresh if both pipes are enabled */
1441                 if (IS_CRESTLINE(dev))
1442                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1443                                    & ~FW_BLC_SELF_EN);
1444         }
1445
1446         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1447                       srwm);
1448
1449         /* 965 has limitations... */
1450         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1451                    (8 << 16) | (8 << 8) | (8 << 0));
1452         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1453         /* update cursor SR watermark */
1454         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1455 }
1456
1457 static void i9xx_update_wm(struct drm_device *dev)
1458 {
1459         struct drm_i915_private *dev_priv = dev->dev_private;
1460         const struct intel_watermark_params *wm_info;
1461         uint32_t fwater_lo;
1462         uint32_t fwater_hi;
1463         int cwm, srwm = 1;
1464         int fifo_size;
1465         int planea_wm, planeb_wm;
1466         struct drm_crtc *crtc, *enabled = NULL;
1467
1468         if (IS_I945GM(dev))
1469                 wm_info = &i945_wm_info;
1470         else if (!IS_GEN2(dev))
1471                 wm_info = &i915_wm_info;
1472         else
1473                 wm_info = &i855_wm_info;
1474
1475         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1476         crtc = intel_get_crtc_for_plane(dev, 0);
1477         if (crtc->enabled && crtc->fb) {
1478                 int cpp = crtc->fb->bits_per_pixel / 8;
1479                 if (IS_GEN2(dev))
1480                         cpp = 4;
1481
1482                 planea_wm = intel_calculate_wm(crtc->mode.clock,
1483                                                wm_info, fifo_size, cpp,
1484                                                latency_ns);
1485                 enabled = crtc;
1486         } else
1487                 planea_wm = fifo_size - wm_info->guard_size;
1488
1489         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1490         crtc = intel_get_crtc_for_plane(dev, 1);
1491         if (crtc->enabled && crtc->fb) {
1492                 int cpp = crtc->fb->bits_per_pixel / 8;
1493                 if (IS_GEN2(dev))
1494                         cpp = 4;
1495
1496                 planeb_wm = intel_calculate_wm(crtc->mode.clock,
1497                                                wm_info, fifo_size, cpp,
1498                                                latency_ns);
1499                 if (enabled == NULL)
1500                         enabled = crtc;
1501                 else
1502                         enabled = NULL;
1503         } else
1504                 planeb_wm = fifo_size - wm_info->guard_size;
1505
1506         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1507
1508         /*
1509          * Overlay gets an aggressive default since video jitter is bad.
1510          */
1511         cwm = 2;
1512
1513         /* Play safe and disable self-refresh before adjusting watermarks. */
1514         if (IS_I945G(dev) || IS_I945GM(dev))
1515                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1516         else if (IS_I915GM(dev))
1517                 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1518
1519         /* Calc sr entries for one plane configs */
1520         if (HAS_FW_BLC(dev) && enabled) {
1521                 /* self-refresh has much higher latency */
1522                 static const int sr_latency_ns = 6000;
1523                 int clock = enabled->mode.clock;
1524                 int htotal = enabled->mode.htotal;
1525                 int hdisplay = enabled->mode.hdisplay;
1526                 int pixel_size = enabled->fb->bits_per_pixel / 8;
1527                 unsigned long line_time_us;
1528                 int entries;
1529
1530                 line_time_us = (htotal * 1000) / clock;
1531
1532                 /* Use ns/us then divide to preserve precision */
1533                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1534                         pixel_size * hdisplay;
1535                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1536                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1537                 srwm = wm_info->fifo_size - entries;
1538                 if (srwm < 0)
1539                         srwm = 1;
1540
1541                 if (IS_I945G(dev) || IS_I945GM(dev))
1542                         I915_WRITE(FW_BLC_SELF,
1543                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1544                 else if (IS_I915GM(dev))
1545                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1546         }
1547
1548         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1549                       planea_wm, planeb_wm, cwm, srwm);
1550
1551         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1552         fwater_hi = (cwm & 0x1f);
1553
1554         /* Set request length to 8 cachelines per fetch */
1555         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1556         fwater_hi = fwater_hi | (1 << 8);
1557
1558         I915_WRITE(FW_BLC, fwater_lo);
1559         I915_WRITE(FW_BLC2, fwater_hi);
1560
1561         if (HAS_FW_BLC(dev)) {
1562                 if (enabled) {
1563                         if (IS_I945G(dev) || IS_I945GM(dev))
1564                                 I915_WRITE(FW_BLC_SELF,
1565                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1566                         else if (IS_I915GM(dev))
1567                                 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1568                         DRM_DEBUG_KMS("memory self refresh enabled\n");
1569                 } else
1570                         DRM_DEBUG_KMS("memory self refresh disabled\n");
1571         }
1572 }
1573
1574 static void i830_update_wm(struct drm_device *dev)
1575 {
1576         struct drm_i915_private *dev_priv = dev->dev_private;
1577         struct drm_crtc *crtc;
1578         uint32_t fwater_lo;
1579         int planea_wm;
1580
1581         crtc = single_enabled_crtc(dev);
1582         if (crtc == NULL)
1583                 return;
1584
1585         planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
1586                                        dev_priv->display.get_fifo_size(dev, 0),
1587                                        4, latency_ns);
1588         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1589         fwater_lo |= (3<<8) | planea_wm;
1590
1591         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1592
1593         I915_WRITE(FW_BLC, fwater_lo);
1594 }
1595
1596 #define ILK_LP0_PLANE_LATENCY           700
1597 #define ILK_LP0_CURSOR_LATENCY          1300
1598
1599 /*
1600  * Check the wm result.
1601  *
1602  * If any calculated watermark values is larger than the maximum value that
1603  * can be programmed into the associated watermark register, that watermark
1604  * must be disabled.
1605  */
1606 static bool ironlake_check_srwm(struct drm_device *dev, int level,
1607                                 int fbc_wm, int display_wm, int cursor_wm,
1608                                 const struct intel_watermark_params *display,
1609                                 const struct intel_watermark_params *cursor)
1610 {
1611         struct drm_i915_private *dev_priv = dev->dev_private;
1612
1613         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1614                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1615
1616         if (fbc_wm > SNB_FBC_MAX_SRWM) {
1617                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1618                               fbc_wm, SNB_FBC_MAX_SRWM, level);
1619
1620                 /* fbc has it's own way to disable FBC WM */
1621                 I915_WRITE(DISP_ARB_CTL,
1622                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1623                 return false;
1624         }
1625
1626         if (display_wm > display->max_wm) {
1627                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1628                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
1629                 return false;
1630         }
1631
1632         if (cursor_wm > cursor->max_wm) {
1633                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1634                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1635                 return false;
1636         }
1637
1638         if (!(fbc_wm || display_wm || cursor_wm)) {
1639                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1640                 return false;
1641         }
1642
1643         return true;
1644 }
1645
1646 /*
1647  * Compute watermark values of WM[1-3],
1648  */
1649 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1650                                   int latency_ns,
1651                                   const struct intel_watermark_params *display,
1652                                   const struct intel_watermark_params *cursor,
1653                                   int *fbc_wm, int *display_wm, int *cursor_wm)
1654 {
1655         struct drm_crtc *crtc;
1656         unsigned long line_time_us;
1657         int hdisplay, htotal, pixel_size, clock;
1658         int line_count, line_size;
1659         int small, large;
1660         int entries;
1661
1662         if (!latency_ns) {
1663                 *fbc_wm = *display_wm = *cursor_wm = 0;
1664                 return false;
1665         }
1666
1667         crtc = intel_get_crtc_for_plane(dev, plane);
1668         hdisplay = crtc->mode.hdisplay;
1669         htotal = crtc->mode.htotal;
1670         clock = crtc->mode.clock;
1671         pixel_size = crtc->fb->bits_per_pixel / 8;
1672
1673         line_time_us = (htotal * 1000) / clock;
1674         line_count = (latency_ns / line_time_us + 1000) / 1000;
1675         line_size = hdisplay * pixel_size;
1676
1677         /* Use the minimum of the small and large buffer method for primary */
1678         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1679         large = line_count * line_size;
1680
1681         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1682         *display_wm = entries + display->guard_size;
1683
1684         /*
1685          * Spec says:
1686          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1687          */
1688         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1689
1690         /* calculate the self-refresh watermark for display cursor */
1691         entries = line_count * pixel_size * 64;
1692         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1693         *cursor_wm = entries + cursor->guard_size;
1694
1695         return ironlake_check_srwm(dev, level,
1696                                    *fbc_wm, *display_wm, *cursor_wm,
1697                                    display, cursor);
1698 }
1699
1700 static void ironlake_update_wm(struct drm_device *dev)
1701 {
1702         struct drm_i915_private *dev_priv = dev->dev_private;
1703         int fbc_wm, plane_wm, cursor_wm;
1704         unsigned int enabled;
1705
1706         enabled = 0;
1707         if (g4x_compute_wm0(dev, 0,
1708                             &ironlake_display_wm_info,
1709                             ILK_LP0_PLANE_LATENCY,
1710                             &ironlake_cursor_wm_info,
1711                             ILK_LP0_CURSOR_LATENCY,
1712                             &plane_wm, &cursor_wm)) {
1713                 I915_WRITE(WM0_PIPEA_ILK,
1714                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1715                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1716                               " plane %d, " "cursor: %d\n",
1717                               plane_wm, cursor_wm);
1718                 enabled |= 1;
1719         }
1720
1721         if (g4x_compute_wm0(dev, 1,
1722                             &ironlake_display_wm_info,
1723                             ILK_LP0_PLANE_LATENCY,
1724                             &ironlake_cursor_wm_info,
1725                             ILK_LP0_CURSOR_LATENCY,
1726                             &plane_wm, &cursor_wm)) {
1727                 I915_WRITE(WM0_PIPEB_ILK,
1728                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1729                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1730                               " plane %d, cursor: %d\n",
1731                               plane_wm, cursor_wm);
1732                 enabled |= 2;
1733         }
1734
1735         /*
1736          * Calculate and update the self-refresh watermark only when one
1737          * display plane is used.
1738          */
1739         I915_WRITE(WM3_LP_ILK, 0);
1740         I915_WRITE(WM2_LP_ILK, 0);
1741         I915_WRITE(WM1_LP_ILK, 0);
1742
1743         if (!single_plane_enabled(enabled))
1744                 return;
1745         enabled = ffs(enabled) - 1;
1746
1747         /* WM1 */
1748         if (!ironlake_compute_srwm(dev, 1, enabled,
1749                                    ILK_READ_WM1_LATENCY() * 500,
1750                                    &ironlake_display_srwm_info,
1751                                    &ironlake_cursor_srwm_info,
1752                                    &fbc_wm, &plane_wm, &cursor_wm))
1753                 return;
1754
1755         I915_WRITE(WM1_LP_ILK,
1756                    WM1_LP_SR_EN |
1757                    (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1758                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1759                    (plane_wm << WM1_LP_SR_SHIFT) |
1760                    cursor_wm);
1761
1762         /* WM2 */
1763         if (!ironlake_compute_srwm(dev, 2, enabled,
1764                                    ILK_READ_WM2_LATENCY() * 500,
1765                                    &ironlake_display_srwm_info,
1766                                    &ironlake_cursor_srwm_info,
1767                                    &fbc_wm, &plane_wm, &cursor_wm))
1768                 return;
1769
1770         I915_WRITE(WM2_LP_ILK,
1771                    WM2_LP_EN |
1772                    (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1773                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1774                    (plane_wm << WM1_LP_SR_SHIFT) |
1775                    cursor_wm);
1776
1777         /*
1778          * WM3 is unsupported on ILK, probably because we don't have latency
1779          * data for that power state
1780          */
1781 }
1782
1783 static void sandybridge_update_wm(struct drm_device *dev)
1784 {
1785         struct drm_i915_private *dev_priv = dev->dev_private;
1786         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
1787         u32 val;
1788         int fbc_wm, plane_wm, cursor_wm;
1789         unsigned int enabled;
1790
1791         enabled = 0;
1792         if (g4x_compute_wm0(dev, 0,
1793                             &sandybridge_display_wm_info, latency,
1794                             &sandybridge_cursor_wm_info, latency,
1795                             &plane_wm, &cursor_wm)) {
1796                 val = I915_READ(WM0_PIPEA_ILK);
1797                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1798                 I915_WRITE(WM0_PIPEA_ILK, val |
1799                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1800                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1801                               " plane %d, " "cursor: %d\n",
1802                               plane_wm, cursor_wm);
1803                 enabled |= 1;
1804         }
1805
1806         if (g4x_compute_wm0(dev, 1,
1807                             &sandybridge_display_wm_info, latency,
1808                             &sandybridge_cursor_wm_info, latency,
1809                             &plane_wm, &cursor_wm)) {
1810                 val = I915_READ(WM0_PIPEB_ILK);
1811                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1812                 I915_WRITE(WM0_PIPEB_ILK, val |
1813                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1814                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1815                               " plane %d, cursor: %d\n",
1816                               plane_wm, cursor_wm);
1817                 enabled |= 2;
1818         }
1819
1820         /*
1821          * Calculate and update the self-refresh watermark only when one
1822          * display plane is used.
1823          *
1824          * SNB support 3 levels of watermark.
1825          *
1826          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1827          * and disabled in the descending order
1828          *
1829          */
1830         I915_WRITE(WM3_LP_ILK, 0);
1831         I915_WRITE(WM2_LP_ILK, 0);
1832         I915_WRITE(WM1_LP_ILK, 0);
1833
1834         if (!single_plane_enabled(enabled) ||
1835             dev_priv->sprite_scaling_enabled)
1836                 return;
1837         enabled = ffs(enabled) - 1;
1838
1839         /* WM1 */
1840         if (!ironlake_compute_srwm(dev, 1, enabled,
1841                                    SNB_READ_WM1_LATENCY() * 500,
1842                                    &sandybridge_display_srwm_info,
1843                                    &sandybridge_cursor_srwm_info,
1844                                    &fbc_wm, &plane_wm, &cursor_wm))
1845                 return;
1846
1847         I915_WRITE(WM1_LP_ILK,
1848                    WM1_LP_SR_EN |
1849                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1850                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1851                    (plane_wm << WM1_LP_SR_SHIFT) |
1852                    cursor_wm);
1853
1854         /* WM2 */
1855         if (!ironlake_compute_srwm(dev, 2, enabled,
1856                                    SNB_READ_WM2_LATENCY() * 500,
1857                                    &sandybridge_display_srwm_info,
1858                                    &sandybridge_cursor_srwm_info,
1859                                    &fbc_wm, &plane_wm, &cursor_wm))
1860                 return;
1861
1862         I915_WRITE(WM2_LP_ILK,
1863                    WM2_LP_EN |
1864                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1865                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1866                    (plane_wm << WM1_LP_SR_SHIFT) |
1867                    cursor_wm);
1868
1869         /* WM3 */
1870         if (!ironlake_compute_srwm(dev, 3, enabled,
1871                                    SNB_READ_WM3_LATENCY() * 500,
1872                                    &sandybridge_display_srwm_info,
1873                                    &sandybridge_cursor_srwm_info,
1874                                    &fbc_wm, &plane_wm, &cursor_wm))
1875                 return;
1876
1877         I915_WRITE(WM3_LP_ILK,
1878                    WM3_LP_EN |
1879                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1880                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1881                    (plane_wm << WM1_LP_SR_SHIFT) |
1882                    cursor_wm);
1883 }
1884
1885 static void ivybridge_update_wm(struct drm_device *dev)
1886 {
1887         struct drm_i915_private *dev_priv = dev->dev_private;
1888         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
1889         u32 val;
1890         int fbc_wm, plane_wm, cursor_wm;
1891         int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
1892         unsigned int enabled;
1893
1894         enabled = 0;
1895         if (g4x_compute_wm0(dev, 0,
1896                             &sandybridge_display_wm_info, latency,
1897                             &sandybridge_cursor_wm_info, latency,
1898                             &plane_wm, &cursor_wm)) {
1899                 val = I915_READ(WM0_PIPEA_ILK);
1900                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1901                 I915_WRITE(WM0_PIPEA_ILK, val |
1902                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1903                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1904                               " plane %d, " "cursor: %d\n",
1905                               plane_wm, cursor_wm);
1906                 enabled |= 1;
1907         }
1908
1909         if (g4x_compute_wm0(dev, 1,
1910                             &sandybridge_display_wm_info, latency,
1911                             &sandybridge_cursor_wm_info, latency,
1912                             &plane_wm, &cursor_wm)) {
1913                 val = I915_READ(WM0_PIPEB_ILK);
1914                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1915                 I915_WRITE(WM0_PIPEB_ILK, val |
1916                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1917                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1918                               " plane %d, cursor: %d\n",
1919                               plane_wm, cursor_wm);
1920                 enabled |= 2;
1921         }
1922
1923         if (g4x_compute_wm0(dev, 2,
1924                             &sandybridge_display_wm_info, latency,
1925                             &sandybridge_cursor_wm_info, latency,
1926                             &plane_wm, &cursor_wm)) {
1927                 val = I915_READ(WM0_PIPEC_IVB);
1928                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1929                 I915_WRITE(WM0_PIPEC_IVB, val |
1930                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1931                 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
1932                               " plane %d, cursor: %d\n",
1933                               plane_wm, cursor_wm);
1934                 enabled |= 3;
1935         }
1936
1937         /*
1938          * Calculate and update the self-refresh watermark only when one
1939          * display plane is used.
1940          *
1941          * SNB support 3 levels of watermark.
1942          *
1943          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1944          * and disabled in the descending order
1945          *
1946          */
1947         I915_WRITE(WM3_LP_ILK, 0);
1948         I915_WRITE(WM2_LP_ILK, 0);
1949         I915_WRITE(WM1_LP_ILK, 0);
1950
1951         if (!single_plane_enabled(enabled) ||
1952             dev_priv->sprite_scaling_enabled)
1953                 return;
1954         enabled = ffs(enabled) - 1;
1955
1956         /* WM1 */
1957         if (!ironlake_compute_srwm(dev, 1, enabled,
1958                                    SNB_READ_WM1_LATENCY() * 500,
1959                                    &sandybridge_display_srwm_info,
1960                                    &sandybridge_cursor_srwm_info,
1961                                    &fbc_wm, &plane_wm, &cursor_wm))
1962                 return;
1963
1964         I915_WRITE(WM1_LP_ILK,
1965                    WM1_LP_SR_EN |
1966                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1967                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1968                    (plane_wm << WM1_LP_SR_SHIFT) |
1969                    cursor_wm);
1970
1971         /* WM2 */
1972         if (!ironlake_compute_srwm(dev, 2, enabled,
1973                                    SNB_READ_WM2_LATENCY() * 500,
1974                                    &sandybridge_display_srwm_info,
1975                                    &sandybridge_cursor_srwm_info,
1976                                    &fbc_wm, &plane_wm, &cursor_wm))
1977                 return;
1978
1979         I915_WRITE(WM2_LP_ILK,
1980                    WM2_LP_EN |
1981                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1982                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1983                    (plane_wm << WM1_LP_SR_SHIFT) |
1984                    cursor_wm);
1985
1986         /* WM3, note we have to correct the cursor latency */
1987         if (!ironlake_compute_srwm(dev, 3, enabled,
1988                                    SNB_READ_WM3_LATENCY() * 500,
1989                                    &sandybridge_display_srwm_info,
1990                                    &sandybridge_cursor_srwm_info,
1991                                    &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
1992             !ironlake_compute_srwm(dev, 3, enabled,
1993                                    2 * SNB_READ_WM3_LATENCY() * 500,
1994                                    &sandybridge_display_srwm_info,
1995                                    &sandybridge_cursor_srwm_info,
1996                                    &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
1997                 return;
1998
1999         I915_WRITE(WM3_LP_ILK,
2000                    WM3_LP_EN |
2001                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2002                    (fbc_wm << WM1_LP_FBC_SHIFT) |
2003                    (plane_wm << WM1_LP_SR_SHIFT) |
2004                    cursor_wm);
2005 }
2006
2007 static void
2008 haswell_update_linetime_wm(struct drm_device *dev, int pipe,
2009                                  struct drm_display_mode *mode)
2010 {
2011         struct drm_i915_private *dev_priv = dev->dev_private;
2012         u32 temp;
2013
2014         temp = I915_READ(PIPE_WM_LINETIME(pipe));
2015         temp &= ~PIPE_WM_LINETIME_MASK;
2016
2017         /* The WM are computed with base on how long it takes to fill a single
2018          * row at the given clock rate, multiplied by 8.
2019          * */
2020         temp |= PIPE_WM_LINETIME_TIME(
2021                 ((mode->crtc_hdisplay * 1000) / mode->clock) * 8);
2022
2023         /* IPS watermarks are only used by pipe A, and are ignored by
2024          * pipes B and C.  They are calculated similarly to the common
2025          * linetime values, except that we are using CD clock frequency
2026          * in MHz instead of pixel rate for the division.
2027          *
2028          * This is a placeholder for the IPS watermark calculation code.
2029          */
2030
2031         I915_WRITE(PIPE_WM_LINETIME(pipe), temp);
2032 }
2033
2034 static bool
2035 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
2036                               uint32_t sprite_width, int pixel_size,
2037                               const struct intel_watermark_params *display,
2038                               int display_latency_ns, int *sprite_wm)
2039 {
2040         struct drm_crtc *crtc;
2041         int clock;
2042         int entries, tlb_miss;
2043
2044         crtc = intel_get_crtc_for_plane(dev, plane);
2045         if (crtc->fb == NULL || !crtc->enabled) {
2046                 *sprite_wm = display->guard_size;
2047                 return false;
2048         }
2049
2050         clock = crtc->mode.clock;
2051
2052         /* Use the small buffer method to calculate the sprite watermark */
2053         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
2054         tlb_miss = display->fifo_size*display->cacheline_size -
2055                 sprite_width * 8;
2056         if (tlb_miss > 0)
2057                 entries += tlb_miss;
2058         entries = DIV_ROUND_UP(entries, display->cacheline_size);
2059         *sprite_wm = entries + display->guard_size;
2060         if (*sprite_wm > (int)display->max_wm)
2061                 *sprite_wm = display->max_wm;
2062
2063         return true;
2064 }
2065
2066 static bool
2067 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
2068                                 uint32_t sprite_width, int pixel_size,
2069                                 const struct intel_watermark_params *display,
2070                                 int latency_ns, int *sprite_wm)
2071 {
2072         struct drm_crtc *crtc;
2073         unsigned long line_time_us;
2074         int clock;
2075         int line_count, line_size;
2076         int small, large;
2077         int entries;
2078
2079         if (!latency_ns) {
2080                 *sprite_wm = 0;
2081                 return false;
2082         }
2083
2084         crtc = intel_get_crtc_for_plane(dev, plane);
2085         clock = crtc->mode.clock;
2086         if (!clock) {
2087                 *sprite_wm = 0;
2088                 return false;
2089         }
2090
2091         line_time_us = (sprite_width * 1000) / clock;
2092         if (!line_time_us) {
2093                 *sprite_wm = 0;
2094                 return false;
2095         }
2096
2097         line_count = (latency_ns / line_time_us + 1000) / 1000;
2098         line_size = sprite_width * pixel_size;
2099
2100         /* Use the minimum of the small and large buffer method for primary */
2101         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
2102         large = line_count * line_size;
2103
2104         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
2105         *sprite_wm = entries + display->guard_size;
2106
2107         return *sprite_wm > 0x3ff ? false : true;
2108 }
2109
2110 static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
2111                                          uint32_t sprite_width, int pixel_size)
2112 {
2113         struct drm_i915_private *dev_priv = dev->dev_private;
2114         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
2115         u32 val;
2116         int sprite_wm, reg;
2117         int ret;
2118
2119         switch (pipe) {
2120         case 0:
2121                 reg = WM0_PIPEA_ILK;
2122                 break;
2123         case 1:
2124                 reg = WM0_PIPEB_ILK;
2125                 break;
2126         case 2:
2127                 reg = WM0_PIPEC_IVB;
2128                 break;
2129         default:
2130                 return; /* bad pipe */
2131         }
2132
2133         ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
2134                                             &sandybridge_display_wm_info,
2135                                             latency, &sprite_wm);
2136         if (!ret) {
2137                 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
2138                               pipe);
2139                 return;
2140         }
2141
2142         val = I915_READ(reg);
2143         val &= ~WM0_PIPE_SPRITE_MASK;
2144         I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
2145         DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
2146
2147
2148         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2149                                               pixel_size,
2150                                               &sandybridge_display_srwm_info,
2151                                               SNB_READ_WM1_LATENCY() * 500,
2152                                               &sprite_wm);
2153         if (!ret) {
2154                 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
2155                               pipe);
2156                 return;
2157         }
2158         I915_WRITE(WM1S_LP_ILK, sprite_wm);
2159
2160         /* Only IVB has two more LP watermarks for sprite */
2161         if (!IS_IVYBRIDGE(dev))
2162                 return;
2163
2164         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2165                                               pixel_size,
2166                                               &sandybridge_display_srwm_info,
2167                                               SNB_READ_WM2_LATENCY() * 500,
2168                                               &sprite_wm);
2169         if (!ret) {
2170                 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
2171                               pipe);
2172                 return;
2173         }
2174         I915_WRITE(WM2S_LP_IVB, sprite_wm);
2175
2176         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2177                                               pixel_size,
2178                                               &sandybridge_display_srwm_info,
2179                                               SNB_READ_WM3_LATENCY() * 500,
2180                                               &sprite_wm);
2181         if (!ret) {
2182                 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
2183                               pipe);
2184                 return;
2185         }
2186         I915_WRITE(WM3S_LP_IVB, sprite_wm);
2187 }
2188
2189 /**
2190  * intel_update_watermarks - update FIFO watermark values based on current modes
2191  *
2192  * Calculate watermark values for the various WM regs based on current mode
2193  * and plane configuration.
2194  *
2195  * There are several cases to deal with here:
2196  *   - normal (i.e. non-self-refresh)
2197  *   - self-refresh (SR) mode
2198  *   - lines are large relative to FIFO size (buffer can hold up to 2)
2199  *   - lines are small relative to FIFO size (buffer can hold more than 2
2200  *     lines), so need to account for TLB latency
2201  *
2202  *   The normal calculation is:
2203  *     watermark = dotclock * bytes per pixel * latency
2204  *   where latency is platform & configuration dependent (we assume pessimal
2205  *   values here).
2206  *
2207  *   The SR calculation is:
2208  *     watermark = (trunc(latency/line time)+1) * surface width *
2209  *       bytes per pixel
2210  *   where
2211  *     line time = htotal / dotclock
2212  *     surface width = hdisplay for normal plane and 64 for cursor
2213  *   and latency is assumed to be high, as above.
2214  *
2215  * The final value programmed to the register should always be rounded up,
2216  * and include an extra 2 entries to account for clock crossings.
2217  *
2218  * We don't use the sprite, so we can ignore that.  And on Crestline we have
2219  * to set the non-SR watermarks to 8.
2220  */
2221 void intel_update_watermarks(struct drm_device *dev)
2222 {
2223         struct drm_i915_private *dev_priv = dev->dev_private;
2224
2225         if (dev_priv->display.update_wm)
2226                 dev_priv->display.update_wm(dev);
2227 }
2228
2229 void intel_update_linetime_watermarks(struct drm_device *dev,
2230                 int pipe, struct drm_display_mode *mode)
2231 {
2232         struct drm_i915_private *dev_priv = dev->dev_private;
2233
2234         if (dev_priv->display.update_linetime_wm)
2235                 dev_priv->display.update_linetime_wm(dev, pipe, mode);
2236 }
2237
2238 void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
2239                                     uint32_t sprite_width, int pixel_size)
2240 {
2241         struct drm_i915_private *dev_priv = dev->dev_private;
2242
2243         if (dev_priv->display.update_sprite_wm)
2244                 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
2245                                                    pixel_size);
2246 }
2247
2248 static struct drm_i915_gem_object *
2249 intel_alloc_context_page(struct drm_device *dev)
2250 {
2251         struct drm_i915_gem_object *ctx;
2252         int ret;
2253
2254         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2255
2256         ctx = i915_gem_alloc_object(dev, 4096);
2257         if (!ctx) {
2258                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2259                 return NULL;
2260         }
2261
2262         ret = i915_gem_object_pin(ctx, 4096, true, false);
2263         if (ret) {
2264                 DRM_ERROR("failed to pin power context: %d\n", ret);
2265                 goto err_unref;
2266         }
2267
2268         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2269         if (ret) {
2270                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2271                 goto err_unpin;
2272         }
2273
2274         return ctx;
2275
2276 err_unpin:
2277         i915_gem_object_unpin(ctx);
2278 err_unref:
2279         drm_gem_object_unreference(&ctx->base);
2280         mutex_unlock(&dev->struct_mutex);
2281         return NULL;
2282 }
2283
2284 /**
2285  * Lock protecting IPS related data structures
2286  */
2287 DEFINE_SPINLOCK(mchdev_lock);
2288
2289 /* Global for IPS driver to get at the current i915 device. Protected by
2290  * mchdev_lock. */
2291 static struct drm_i915_private *i915_mch_dev;
2292
2293 bool ironlake_set_drps(struct drm_device *dev, u8 val)
2294 {
2295         struct drm_i915_private *dev_priv = dev->dev_private;
2296         u16 rgvswctl;
2297
2298         assert_spin_locked(&mchdev_lock);
2299
2300         rgvswctl = I915_READ16(MEMSWCTL);
2301         if (rgvswctl & MEMCTL_CMD_STS) {
2302                 DRM_DEBUG("gpu busy, RCS change rejected\n");
2303                 return false; /* still busy with another command */
2304         }
2305
2306         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2307                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2308         I915_WRITE16(MEMSWCTL, rgvswctl);
2309         POSTING_READ16(MEMSWCTL);
2310
2311         rgvswctl |= MEMCTL_CMD_STS;
2312         I915_WRITE16(MEMSWCTL, rgvswctl);
2313
2314         return true;
2315 }
2316
2317 static void ironlake_enable_drps(struct drm_device *dev)
2318 {
2319         struct drm_i915_private *dev_priv = dev->dev_private;
2320         u32 rgvmodectl = I915_READ(MEMMODECTL);
2321         u8 fmax, fmin, fstart, vstart;
2322
2323         spin_lock_irq(&mchdev_lock);
2324
2325         /* Enable temp reporting */
2326         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2327         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2328
2329         /* 100ms RC evaluation intervals */
2330         I915_WRITE(RCUPEI, 100000);
2331         I915_WRITE(RCDNEI, 100000);
2332
2333         /* Set max/min thresholds to 90ms and 80ms respectively */
2334         I915_WRITE(RCBMAXAVG, 90000);
2335         I915_WRITE(RCBMINAVG, 80000);
2336
2337         I915_WRITE(MEMIHYST, 1);
2338
2339         /* Set up min, max, and cur for interrupt handling */
2340         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2341         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2342         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2343                 MEMMODE_FSTART_SHIFT;
2344
2345         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2346                 PXVFREQ_PX_SHIFT;
2347
2348         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2349         dev_priv->ips.fstart = fstart;
2350
2351         dev_priv->ips.max_delay = fstart;
2352         dev_priv->ips.min_delay = fmin;
2353         dev_priv->ips.cur_delay = fstart;
2354
2355         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2356                          fmax, fmin, fstart);
2357
2358         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2359
2360         /*
2361          * Interrupts will be enabled in ironlake_irq_postinstall
2362          */
2363
2364         I915_WRITE(VIDSTART, vstart);
2365         POSTING_READ(VIDSTART);
2366
2367         rgvmodectl |= MEMMODE_SWMODE_EN;
2368         I915_WRITE(MEMMODECTL, rgvmodectl);
2369
2370         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2371                 DRM_ERROR("stuck trying to change perf mode\n");
2372         mdelay(1);
2373
2374         ironlake_set_drps(dev, fstart);
2375
2376         dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2377                 I915_READ(0x112e0);
2378         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2379         dev_priv->ips.last_count2 = I915_READ(0x112f4);
2380         getrawmonotonic(&dev_priv->ips.last_time2);
2381
2382         spin_unlock_irq(&mchdev_lock);
2383 }
2384
2385 static void ironlake_disable_drps(struct drm_device *dev)
2386 {
2387         struct drm_i915_private *dev_priv = dev->dev_private;
2388         u16 rgvswctl;
2389
2390         spin_lock_irq(&mchdev_lock);
2391
2392         rgvswctl = I915_READ16(MEMSWCTL);
2393
2394         /* Ack interrupts, disable EFC interrupt */
2395         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
2396         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
2397         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
2398         I915_WRITE(DEIIR, DE_PCU_EVENT);
2399         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
2400
2401         /* Go back to the starting frequency */
2402         ironlake_set_drps(dev, dev_priv->ips.fstart);
2403         mdelay(1);
2404         rgvswctl |= MEMCTL_CMD_STS;
2405         I915_WRITE(MEMSWCTL, rgvswctl);
2406         mdelay(1);
2407
2408         spin_unlock_irq(&mchdev_lock);
2409 }
2410
2411 /* There's a funny hw issue where the hw returns all 0 when reading from
2412  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
2413  * ourselves, instead of doing a rmw cycle (which might result in us clearing
2414  * all limits and the gpu stuck at whatever frequency it is at atm).
2415  */
2416 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
2417 {
2418         u32 limits;
2419
2420         limits = 0;
2421
2422         if (*val >= dev_priv->rps.max_delay)
2423                 *val = dev_priv->rps.max_delay;
2424         limits |= dev_priv->rps.max_delay << 24;
2425
2426         /* Only set the down limit when we've reached the lowest level to avoid
2427          * getting more interrupts, otherwise leave this clear. This prevents a
2428          * race in the hw when coming out of rc6: There's a tiny window where
2429          * the hw runs at the minimal clock before selecting the desired
2430          * frequency, if the down threshold expires in that window we will not
2431          * receive a down interrupt. */
2432         if (*val <= dev_priv->rps.min_delay) {
2433                 *val = dev_priv->rps.min_delay;
2434                 limits |= dev_priv->rps.min_delay << 16;
2435         }
2436
2437         return limits;
2438 }
2439
2440 void gen6_set_rps(struct drm_device *dev, u8 val)
2441 {
2442         struct drm_i915_private *dev_priv = dev->dev_private;
2443         u32 limits = gen6_rps_limits(dev_priv, &val);
2444
2445         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2446         WARN_ON(val > dev_priv->rps.max_delay);
2447         WARN_ON(val < dev_priv->rps.min_delay);
2448
2449         if (val == dev_priv->rps.cur_delay)
2450                 return;
2451
2452         I915_WRITE(GEN6_RPNSWREQ,
2453                    GEN6_FREQUENCY(val) |
2454                    GEN6_OFFSET(0) |
2455                    GEN6_AGGRESSIVE_TURBO);
2456
2457         /* Make sure we continue to get interrupts
2458          * until we hit the minimum or maximum frequencies.
2459          */
2460         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
2461
2462         POSTING_READ(GEN6_RPNSWREQ);
2463
2464         dev_priv->rps.cur_delay = val;
2465
2466         trace_intel_gpu_freq_change(val * 50);
2467 }
2468
2469 static void gen6_disable_rps(struct drm_device *dev)
2470 {
2471         struct drm_i915_private *dev_priv = dev->dev_private;
2472
2473         I915_WRITE(GEN6_RC_CONTROL, 0);
2474         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
2475         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
2476         I915_WRITE(GEN6_PMIER, 0);
2477         /* Complete PM interrupt masking here doesn't race with the rps work
2478          * item again unmasking PM interrupts because that is using a different
2479          * register (PMIMR) to mask PM interrupts. The only risk is in leaving
2480          * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
2481
2482         spin_lock_irq(&dev_priv->rps.lock);
2483         dev_priv->rps.pm_iir = 0;
2484         spin_unlock_irq(&dev_priv->rps.lock);
2485
2486         I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2487 }
2488
2489 int intel_enable_rc6(const struct drm_device *dev)
2490 {
2491         /* Respect the kernel parameter if it is set */
2492         if (i915_enable_rc6 >= 0)
2493                 return i915_enable_rc6;
2494
2495         if (INTEL_INFO(dev)->gen == 5) {
2496 #ifdef CONFIG_INTEL_IOMMU
2497                 /* Disable rc6 on ilk if VT-d is on. */
2498                 if (intel_iommu_gfx_mapped)
2499                         return false;
2500 #endif
2501                 DRM_DEBUG_DRIVER("Ironlake: only RC6 available\n");
2502                 return INTEL_RC6_ENABLE;
2503         }
2504
2505         if (IS_HASWELL(dev)) {
2506                 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
2507                 return INTEL_RC6_ENABLE;
2508         }
2509
2510         /* snb/ivb have more than one rc6 state. */
2511         if (INTEL_INFO(dev)->gen == 6) {
2512                 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
2513                 return INTEL_RC6_ENABLE;
2514         }
2515
2516         DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
2517         return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
2518 }
2519
2520 static void gen6_enable_rps(struct drm_device *dev)
2521 {
2522         struct drm_i915_private *dev_priv = dev->dev_private;
2523         struct intel_ring_buffer *ring;
2524         u32 rp_state_cap;
2525         u32 gt_perf_status;
2526         u32 rc6vids, pcu_mbox, rc6_mask = 0;
2527         u32 gtfifodbg;
2528         int rc6_mode;
2529         int i, ret;
2530
2531         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2532
2533         /* Here begins a magic sequence of register writes to enable
2534          * auto-downclocking.
2535          *
2536          * Perhaps there might be some value in exposing these to
2537          * userspace...
2538          */
2539         I915_WRITE(GEN6_RC_STATE, 0);
2540
2541         /* Clear the DBG now so we don't confuse earlier errors */
2542         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
2543                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
2544                 I915_WRITE(GTFIFODBG, gtfifodbg);
2545         }
2546
2547         gen6_gt_force_wake_get(dev_priv);
2548
2549         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
2550         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
2551
2552         /* In units of 100MHz */
2553         dev_priv->rps.max_delay = rp_state_cap & 0xff;
2554         dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16;
2555         dev_priv->rps.cur_delay = 0;
2556
2557         /* disable the counters and set deterministic thresholds */
2558         I915_WRITE(GEN6_RC_CONTROL, 0);
2559
2560         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
2561         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
2562         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
2563         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
2564         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
2565
2566         for_each_ring(ring, dev_priv, i)
2567                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2568
2569         I915_WRITE(GEN6_RC_SLEEP, 0);
2570         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
2571         I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
2572         I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
2573         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
2574
2575         /* Check if we are enabling RC6 */
2576         rc6_mode = intel_enable_rc6(dev_priv->dev);
2577         if (rc6_mode & INTEL_RC6_ENABLE)
2578                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
2579
2580         /* We don't use those on Haswell */
2581         if (!IS_HASWELL(dev)) {
2582                 if (rc6_mode & INTEL_RC6p_ENABLE)
2583                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2584
2585                 if (rc6_mode & INTEL_RC6pp_ENABLE)
2586                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
2587         }
2588
2589         DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
2590                         (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
2591                         (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
2592                         (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
2593
2594         I915_WRITE(GEN6_RC_CONTROL,
2595                    rc6_mask |
2596                    GEN6_RC_CTL_EI_MODE(1) |
2597                    GEN6_RC_CTL_HW_ENABLE);
2598
2599         I915_WRITE(GEN6_RPNSWREQ,
2600                    GEN6_FREQUENCY(10) |
2601                    GEN6_OFFSET(0) |
2602                    GEN6_AGGRESSIVE_TURBO);
2603         I915_WRITE(GEN6_RC_VIDEO_FREQ,
2604                    GEN6_FREQUENCY(12));
2605
2606         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2607         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
2608                    dev_priv->rps.max_delay << 24 |
2609                    dev_priv->rps.min_delay << 16);
2610
2611         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
2612         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
2613         I915_WRITE(GEN6_RP_UP_EI, 66000);
2614         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
2615
2616         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2617         I915_WRITE(GEN6_RP_CONTROL,
2618                    GEN6_RP_MEDIA_TURBO |
2619                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
2620                    GEN6_RP_MEDIA_IS_GFX |
2621                    GEN6_RP_ENABLE |
2622                    GEN6_RP_UP_BUSY_AVG |
2623                    (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
2624
2625         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
2626         if (!ret) {
2627                 pcu_mbox = 0;
2628                 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
2629                 if (ret && pcu_mbox & (1<<31)) { /* OC supported */
2630                         dev_priv->rps.max_delay = pcu_mbox & 0xff;
2631                         DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
2632                 }
2633         } else {
2634                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
2635         }
2636
2637         gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
2638
2639         /* requires MSI enabled */
2640         I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
2641         spin_lock_irq(&dev_priv->rps.lock);
2642         WARN_ON(dev_priv->rps.pm_iir != 0);
2643         I915_WRITE(GEN6_PMIMR, 0);
2644         spin_unlock_irq(&dev_priv->rps.lock);
2645         /* enable all PM interrupts */
2646         I915_WRITE(GEN6_PMINTRMSK, 0);
2647
2648         rc6vids = 0;
2649         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
2650         if (IS_GEN6(dev) && ret) {
2651                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
2652         } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
2653                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
2654                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
2655                 rc6vids &= 0xffff00;
2656                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
2657                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
2658                 if (ret)
2659                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
2660         }
2661
2662         gen6_gt_force_wake_put(dev_priv);
2663 }
2664
2665 static void gen6_update_ring_freq(struct drm_device *dev)
2666 {
2667         struct drm_i915_private *dev_priv = dev->dev_private;
2668         int min_freq = 15;
2669         int gpu_freq;
2670         unsigned int ia_freq, max_ia_freq;
2671         int scaling_factor = 180;
2672
2673         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2674
2675         max_ia_freq = cpufreq_quick_get_max(0);
2676         /*
2677          * Default to measured freq if none found, PCU will ensure we don't go
2678          * over
2679          */
2680         if (!max_ia_freq)
2681                 max_ia_freq = tsc_khz;
2682
2683         /* Convert from kHz to MHz */
2684         max_ia_freq /= 1000;
2685
2686         /*
2687          * For each potential GPU frequency, load a ring frequency we'd like
2688          * to use for memory access.  We do this by specifying the IA frequency
2689          * the PCU should use as a reference to determine the ring frequency.
2690          */
2691         for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
2692              gpu_freq--) {
2693                 int diff = dev_priv->rps.max_delay - gpu_freq;
2694
2695                 /*
2696                  * For GPU frequencies less than 750MHz, just use the lowest
2697                  * ring freq.
2698                  */
2699                 if (gpu_freq < min_freq)
2700                         ia_freq = 800;
2701                 else
2702                         ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
2703                 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
2704                 ia_freq <<= GEN6_PCODE_FREQ_IA_RATIO_SHIFT;
2705
2706                 sandybridge_pcode_write(dev_priv,
2707                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
2708                                         ia_freq | gpu_freq);
2709         }
2710 }
2711
2712 void ironlake_teardown_rc6(struct drm_device *dev)
2713 {
2714         struct drm_i915_private *dev_priv = dev->dev_private;
2715
2716         if (dev_priv->ips.renderctx) {
2717                 i915_gem_object_unpin(dev_priv->ips.renderctx);
2718                 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
2719                 dev_priv->ips.renderctx = NULL;
2720         }
2721
2722         if (dev_priv->ips.pwrctx) {
2723                 i915_gem_object_unpin(dev_priv->ips.pwrctx);
2724                 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
2725                 dev_priv->ips.pwrctx = NULL;
2726         }
2727 }
2728
2729 static void ironlake_disable_rc6(struct drm_device *dev)
2730 {
2731         struct drm_i915_private *dev_priv = dev->dev_private;
2732
2733         if (I915_READ(PWRCTXA)) {
2734                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
2735                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
2736                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
2737                          50);
2738
2739                 I915_WRITE(PWRCTXA, 0);
2740                 POSTING_READ(PWRCTXA);
2741
2742                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2743                 POSTING_READ(RSTDBYCTL);
2744         }
2745 }
2746
2747 static int ironlake_setup_rc6(struct drm_device *dev)
2748 {
2749         struct drm_i915_private *dev_priv = dev->dev_private;
2750
2751         if (dev_priv->ips.renderctx == NULL)
2752                 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
2753         if (!dev_priv->ips.renderctx)
2754                 return -ENOMEM;
2755
2756         if (dev_priv->ips.pwrctx == NULL)
2757                 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
2758         if (!dev_priv->ips.pwrctx) {
2759                 ironlake_teardown_rc6(dev);
2760                 return -ENOMEM;
2761         }
2762
2763         return 0;
2764 }
2765
2766 static void ironlake_enable_rc6(struct drm_device *dev)
2767 {
2768         struct drm_i915_private *dev_priv = dev->dev_private;
2769         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
2770         bool was_interruptible;
2771         int ret;
2772
2773         /* rc6 disabled by default due to repeated reports of hanging during
2774          * boot and resume.
2775          */
2776         if (!intel_enable_rc6(dev))
2777                 return;
2778
2779         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2780
2781         ret = ironlake_setup_rc6(dev);
2782         if (ret)
2783                 return;
2784
2785         was_interruptible = dev_priv->mm.interruptible;
2786         dev_priv->mm.interruptible = false;
2787
2788         /*
2789          * GPU can automatically power down the render unit if given a page
2790          * to save state.
2791          */
2792         ret = intel_ring_begin(ring, 6);
2793         if (ret) {
2794                 ironlake_teardown_rc6(dev);
2795                 dev_priv->mm.interruptible = was_interruptible;
2796                 return;
2797         }
2798
2799         intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
2800         intel_ring_emit(ring, MI_SET_CONTEXT);
2801         intel_ring_emit(ring, dev_priv->ips.renderctx->gtt_offset |
2802                         MI_MM_SPACE_GTT |
2803                         MI_SAVE_EXT_STATE_EN |
2804                         MI_RESTORE_EXT_STATE_EN |
2805                         MI_RESTORE_INHIBIT);
2806         intel_ring_emit(ring, MI_SUSPEND_FLUSH);
2807         intel_ring_emit(ring, MI_NOOP);
2808         intel_ring_emit(ring, MI_FLUSH);
2809         intel_ring_advance(ring);
2810
2811         /*
2812          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
2813          * does an implicit flush, combined with MI_FLUSH above, it should be
2814          * safe to assume that renderctx is valid
2815          */
2816         ret = intel_ring_idle(ring);
2817         dev_priv->mm.interruptible = was_interruptible;
2818         if (ret) {
2819                 DRM_ERROR("failed to enable ironlake power power savings\n");
2820                 ironlake_teardown_rc6(dev);
2821                 return;
2822         }
2823
2824         I915_WRITE(PWRCTXA, dev_priv->ips.pwrctx->gtt_offset | PWRCTX_EN);
2825         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2826 }
2827
2828 static unsigned long intel_pxfreq(u32 vidfreq)
2829 {
2830         unsigned long freq;
2831         int div = (vidfreq & 0x3f0000) >> 16;
2832         int post = (vidfreq & 0x3000) >> 12;
2833         int pre = (vidfreq & 0x7);
2834
2835         if (!pre)
2836                 return 0;
2837
2838         freq = ((div * 133333) / ((1<<post) * pre));
2839
2840         return freq;
2841 }
2842
2843 static const struct cparams {
2844         u16 i;
2845         u16 t;
2846         u16 m;
2847         u16 c;
2848 } cparams[] = {
2849         { 1, 1333, 301, 28664 },
2850         { 1, 1066, 294, 24460 },
2851         { 1, 800, 294, 25192 },
2852         { 0, 1333, 276, 27605 },
2853         { 0, 1066, 276, 27605 },
2854         { 0, 800, 231, 23784 },
2855 };
2856
2857 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
2858 {
2859         u64 total_count, diff, ret;
2860         u32 count1, count2, count3, m = 0, c = 0;
2861         unsigned long now = jiffies_to_msecs(jiffies), diff1;
2862         int i;
2863
2864         assert_spin_locked(&mchdev_lock);
2865
2866         diff1 = now - dev_priv->ips.last_time1;
2867
2868         /* Prevent division-by-zero if we are asking too fast.
2869          * Also, we don't get interesting results if we are polling
2870          * faster than once in 10ms, so just return the saved value
2871          * in such cases.
2872          */
2873         if (diff1 <= 10)
2874                 return dev_priv->ips.chipset_power;
2875
2876         count1 = I915_READ(DMIEC);
2877         count2 = I915_READ(DDREC);
2878         count3 = I915_READ(CSIEC);
2879
2880         total_count = count1 + count2 + count3;
2881
2882         /* FIXME: handle per-counter overflow */
2883         if (total_count < dev_priv->ips.last_count1) {
2884                 diff = ~0UL - dev_priv->ips.last_count1;
2885                 diff += total_count;
2886         } else {
2887                 diff = total_count - dev_priv->ips.last_count1;
2888         }
2889
2890         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
2891                 if (cparams[i].i == dev_priv->ips.c_m &&
2892                     cparams[i].t == dev_priv->ips.r_t) {
2893                         m = cparams[i].m;
2894                         c = cparams[i].c;
2895                         break;
2896                 }
2897         }
2898
2899         diff = div_u64(diff, diff1);
2900         ret = ((m * diff) + c);
2901         ret = div_u64(ret, 10);
2902
2903         dev_priv->ips.last_count1 = total_count;
2904         dev_priv->ips.last_time1 = now;
2905
2906         dev_priv->ips.chipset_power = ret;
2907
2908         return ret;
2909 }
2910
2911 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
2912 {
2913         unsigned long val;
2914
2915         if (dev_priv->info->gen != 5)
2916                 return 0;
2917
2918         spin_lock_irq(&mchdev_lock);
2919
2920         val = __i915_chipset_val(dev_priv);
2921
2922         spin_unlock_irq(&mchdev_lock);
2923
2924         return val;
2925 }
2926
2927 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
2928 {
2929         unsigned long m, x, b;
2930         u32 tsfs;
2931
2932         tsfs = I915_READ(TSFS);
2933
2934         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
2935         x = I915_READ8(TR1);
2936
2937         b = tsfs & TSFS_INTR_MASK;
2938
2939         return ((m * x) / 127) - b;
2940 }
2941
2942 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
2943 {
2944         static const struct v_table {
2945                 u16 vd; /* in .1 mil */
2946                 u16 vm; /* in .1 mil */
2947         } v_table[] = {
2948                 { 0, 0, },
2949                 { 375, 0, },
2950                 { 500, 0, },
2951                 { 625, 0, },
2952                 { 750, 0, },
2953                 { 875, 0, },
2954                 { 1000, 0, },
2955                 { 1125, 0, },
2956                 { 4125, 3000, },
2957                 { 4125, 3000, },
2958                 { 4125, 3000, },
2959                 { 4125, 3000, },
2960                 { 4125, 3000, },
2961                 { 4125, 3000, },
2962                 { 4125, 3000, },
2963                 { 4125, 3000, },
2964                 { 4125, 3000, },
2965                 { 4125, 3000, },
2966                 { 4125, 3000, },
2967                 { 4125, 3000, },
2968                 { 4125, 3000, },
2969                 { 4125, 3000, },
2970                 { 4125, 3000, },
2971                 { 4125, 3000, },
2972                 { 4125, 3000, },
2973                 { 4125, 3000, },
2974                 { 4125, 3000, },
2975                 { 4125, 3000, },
2976                 { 4125, 3000, },
2977                 { 4125, 3000, },
2978                 { 4125, 3000, },
2979                 { 4125, 3000, },
2980                 { 4250, 3125, },
2981                 { 4375, 3250, },
2982                 { 4500, 3375, },
2983                 { 4625, 3500, },
2984                 { 4750, 3625, },
2985                 { 4875, 3750, },
2986                 { 5000, 3875, },
2987                 { 5125, 4000, },
2988                 { 5250, 4125, },
2989                 { 5375, 4250, },
2990                 { 5500, 4375, },
2991                 { 5625, 4500, },
2992                 { 5750, 4625, },
2993                 { 5875, 4750, },
2994                 { 6000, 4875, },
2995                 { 6125, 5000, },
2996                 { 6250, 5125, },
2997                 { 6375, 5250, },
2998                 { 6500, 5375, },
2999                 { 6625, 5500, },
3000                 { 6750, 5625, },
3001                 { 6875, 5750, },
3002                 { 7000, 5875, },
3003                 { 7125, 6000, },
3004                 { 7250, 6125, },
3005                 { 7375, 6250, },
3006                 { 7500, 6375, },
3007                 { 7625, 6500, },
3008                 { 7750, 6625, },
3009                 { 7875, 6750, },
3010                 { 8000, 6875, },
3011                 { 8125, 7000, },
3012                 { 8250, 7125, },
3013                 { 8375, 7250, },
3014                 { 8500, 7375, },
3015                 { 8625, 7500, },
3016                 { 8750, 7625, },
3017                 { 8875, 7750, },
3018                 { 9000, 7875, },
3019                 { 9125, 8000, },
3020                 { 9250, 8125, },
3021                 { 9375, 8250, },
3022                 { 9500, 8375, },
3023                 { 9625, 8500, },
3024                 { 9750, 8625, },
3025                 { 9875, 8750, },
3026                 { 10000, 8875, },
3027                 { 10125, 9000, },
3028                 { 10250, 9125, },
3029                 { 10375, 9250, },
3030                 { 10500, 9375, },
3031                 { 10625, 9500, },
3032                 { 10750, 9625, },
3033                 { 10875, 9750, },
3034                 { 11000, 9875, },
3035                 { 11125, 10000, },
3036                 { 11250, 10125, },
3037                 { 11375, 10250, },
3038                 { 11500, 10375, },
3039                 { 11625, 10500, },
3040                 { 11750, 10625, },
3041                 { 11875, 10750, },
3042                 { 12000, 10875, },
3043                 { 12125, 11000, },
3044                 { 12250, 11125, },
3045                 { 12375, 11250, },
3046                 { 12500, 11375, },
3047                 { 12625, 11500, },
3048                 { 12750, 11625, },
3049                 { 12875, 11750, },
3050                 { 13000, 11875, },
3051                 { 13125, 12000, },
3052                 { 13250, 12125, },
3053                 { 13375, 12250, },
3054                 { 13500, 12375, },
3055                 { 13625, 12500, },
3056                 { 13750, 12625, },
3057                 { 13875, 12750, },
3058                 { 14000, 12875, },
3059                 { 14125, 13000, },
3060                 { 14250, 13125, },
3061                 { 14375, 13250, },
3062                 { 14500, 13375, },
3063                 { 14625, 13500, },
3064                 { 14750, 13625, },
3065                 { 14875, 13750, },
3066                 { 15000, 13875, },
3067                 { 15125, 14000, },
3068                 { 15250, 14125, },
3069                 { 15375, 14250, },
3070                 { 15500, 14375, },
3071                 { 15625, 14500, },
3072                 { 15750, 14625, },
3073                 { 15875, 14750, },
3074                 { 16000, 14875, },
3075                 { 16125, 15000, },
3076         };
3077         if (dev_priv->info->is_mobile)
3078                 return v_table[pxvid].vm;
3079         else
3080                 return v_table[pxvid].vd;
3081 }
3082
3083 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
3084 {
3085         struct timespec now, diff1;
3086         u64 diff;
3087         unsigned long diffms;
3088         u32 count;
3089
3090         assert_spin_locked(&mchdev_lock);
3091
3092         getrawmonotonic(&now);
3093         diff1 = timespec_sub(now, dev_priv->ips.last_time2);
3094
3095         /* Don't divide by 0 */
3096         diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
3097         if (!diffms)
3098                 return;
3099
3100         count = I915_READ(GFXEC);
3101
3102         if (count < dev_priv->ips.last_count2) {
3103                 diff = ~0UL - dev_priv->ips.last_count2;
3104                 diff += count;
3105         } else {
3106                 diff = count - dev_priv->ips.last_count2;
3107         }
3108
3109         dev_priv->ips.last_count2 = count;
3110         dev_priv->ips.last_time2 = now;
3111
3112         /* More magic constants... */
3113         diff = diff * 1181;
3114         diff = div_u64(diff, diffms * 10);
3115         dev_priv->ips.gfx_power = diff;
3116 }
3117
3118 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
3119 {
3120         if (dev_priv->info->gen != 5)
3121                 return;
3122
3123         spin_lock_irq(&mchdev_lock);
3124
3125         __i915_update_gfx_val(dev_priv);
3126
3127         spin_unlock_irq(&mchdev_lock);
3128 }
3129
3130 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
3131 {
3132         unsigned long t, corr, state1, corr2, state2;
3133         u32 pxvid, ext_v;
3134
3135         assert_spin_locked(&mchdev_lock);
3136
3137         pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
3138         pxvid = (pxvid >> 24) & 0x7f;
3139         ext_v = pvid_to_extvid(dev_priv, pxvid);
3140
3141         state1 = ext_v;
3142
3143         t = i915_mch_val(dev_priv);
3144
3145         /* Revel in the empirically derived constants */
3146
3147         /* Correction factor in 1/100000 units */
3148         if (t > 80)
3149                 corr = ((t * 2349) + 135940);
3150         else if (t >= 50)
3151                 corr = ((t * 964) + 29317);
3152         else /* < 50 */
3153                 corr = ((t * 301) + 1004);
3154
3155         corr = corr * ((150142 * state1) / 10000 - 78642);
3156         corr /= 100000;
3157         corr2 = (corr * dev_priv->ips.corr);
3158
3159         state2 = (corr2 * state1) / 10000;
3160         state2 /= 100; /* convert to mW */
3161
3162         __i915_update_gfx_val(dev_priv);
3163
3164         return dev_priv->ips.gfx_power + state2;
3165 }
3166
3167 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
3168 {
3169         unsigned long val;
3170
3171         if (dev_priv->info->gen != 5)
3172                 return 0;
3173
3174         spin_lock_irq(&mchdev_lock);
3175
3176         val = __i915_gfx_val(dev_priv);
3177
3178         spin_unlock_irq(&mchdev_lock);
3179
3180         return val;
3181 }
3182
3183 /**
3184  * i915_read_mch_val - return value for IPS use
3185  *
3186  * Calculate and return a value for the IPS driver to use when deciding whether
3187  * we have thermal and power headroom to increase CPU or GPU power budget.
3188  */
3189 unsigned long i915_read_mch_val(void)
3190 {
3191         struct drm_i915_private *dev_priv;
3192         unsigned long chipset_val, graphics_val, ret = 0;
3193
3194         spin_lock_irq(&mchdev_lock);
3195         if (!i915_mch_dev)
3196                 goto out_unlock;
3197         dev_priv = i915_mch_dev;
3198
3199         chipset_val = __i915_chipset_val(dev_priv);
3200         graphics_val = __i915_gfx_val(dev_priv);
3201
3202         ret = chipset_val + graphics_val;
3203
3204 out_unlock:
3205         spin_unlock_irq(&mchdev_lock);
3206
3207         return ret;
3208 }
3209 EXPORT_SYMBOL_GPL(i915_read_mch_val);
3210
3211 /**
3212  * i915_gpu_raise - raise GPU frequency limit
3213  *
3214  * Raise the limit; IPS indicates we have thermal headroom.
3215  */
3216 bool i915_gpu_raise(void)
3217 {
3218         struct drm_i915_private *dev_priv;
3219         bool ret = true;
3220
3221         spin_lock_irq(&mchdev_lock);
3222         if (!i915_mch_dev) {
3223                 ret = false;
3224                 goto out_unlock;
3225         }
3226         dev_priv = i915_mch_dev;
3227
3228         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
3229                 dev_priv->ips.max_delay--;
3230
3231 out_unlock:
3232         spin_unlock_irq(&mchdev_lock);
3233
3234         return ret;
3235 }
3236 EXPORT_SYMBOL_GPL(i915_gpu_raise);
3237
3238 /**
3239  * i915_gpu_lower - lower GPU frequency limit
3240  *
3241  * IPS indicates we're close to a thermal limit, so throttle back the GPU
3242  * frequency maximum.
3243  */
3244 bool i915_gpu_lower(void)
3245 {
3246         struct drm_i915_private *dev_priv;
3247         bool ret = true;
3248
3249         spin_lock_irq(&mchdev_lock);
3250         if (!i915_mch_dev) {
3251                 ret = false;
3252                 goto out_unlock;
3253         }
3254         dev_priv = i915_mch_dev;
3255
3256         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
3257                 dev_priv->ips.max_delay++;
3258
3259 out_unlock:
3260         spin_unlock_irq(&mchdev_lock);
3261
3262         return ret;
3263 }
3264 EXPORT_SYMBOL_GPL(i915_gpu_lower);
3265
3266 /**
3267  * i915_gpu_busy - indicate GPU business to IPS
3268  *
3269  * Tell the IPS driver whether or not the GPU is busy.
3270  */
3271 bool i915_gpu_busy(void)
3272 {
3273         struct drm_i915_private *dev_priv;
3274         struct intel_ring_buffer *ring;
3275         bool ret = false;
3276         int i;
3277
3278         spin_lock_irq(&mchdev_lock);
3279         if (!i915_mch_dev)
3280                 goto out_unlock;
3281         dev_priv = i915_mch_dev;
3282
3283         for_each_ring(ring, dev_priv, i)
3284                 ret |= !list_empty(&ring->request_list);
3285
3286 out_unlock:
3287         spin_unlock_irq(&mchdev_lock);
3288
3289         return ret;
3290 }
3291 EXPORT_SYMBOL_GPL(i915_gpu_busy);
3292
3293 /**
3294  * i915_gpu_turbo_disable - disable graphics turbo
3295  *
3296  * Disable graphics turbo by resetting the max frequency and setting the
3297  * current frequency to the default.
3298  */
3299 bool i915_gpu_turbo_disable(void)
3300 {
3301         struct drm_i915_private *dev_priv;
3302         bool ret = true;
3303
3304         spin_lock_irq(&mchdev_lock);
3305         if (!i915_mch_dev) {
3306                 ret = false;
3307                 goto out_unlock;
3308         }
3309         dev_priv = i915_mch_dev;
3310
3311         dev_priv->ips.max_delay = dev_priv->ips.fstart;
3312
3313         if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
3314                 ret = false;
3315
3316 out_unlock:
3317         spin_unlock_irq(&mchdev_lock);
3318
3319         return ret;
3320 }
3321 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
3322
3323 /**
3324  * Tells the intel_ips driver that the i915 driver is now loaded, if
3325  * IPS got loaded first.
3326  *
3327  * This awkward dance is so that neither module has to depend on the
3328  * other in order for IPS to do the appropriate communication of
3329  * GPU turbo limits to i915.
3330  */
3331 static void
3332 ips_ping_for_i915_load(void)
3333 {
3334         void (*link)(void);
3335
3336         link = symbol_get(ips_link_to_i915_driver);
3337         if (link) {
3338                 link();
3339                 symbol_put(ips_link_to_i915_driver);
3340         }
3341 }
3342
3343 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
3344 {
3345         /* We only register the i915 ips part with intel-ips once everything is
3346          * set up, to avoid intel-ips sneaking in and reading bogus values. */
3347         spin_lock_irq(&mchdev_lock);
3348         i915_mch_dev = dev_priv;
3349         spin_unlock_irq(&mchdev_lock);
3350
3351         ips_ping_for_i915_load();
3352 }
3353
3354 void intel_gpu_ips_teardown(void)
3355 {
3356         spin_lock_irq(&mchdev_lock);
3357         i915_mch_dev = NULL;
3358         spin_unlock_irq(&mchdev_lock);
3359 }
3360 static void intel_init_emon(struct drm_device *dev)
3361 {
3362         struct drm_i915_private *dev_priv = dev->dev_private;
3363         u32 lcfuse;
3364         u8 pxw[16];
3365         int i;
3366
3367         /* Disable to program */
3368         I915_WRITE(ECR, 0);
3369         POSTING_READ(ECR);
3370
3371         /* Program energy weights for various events */
3372         I915_WRITE(SDEW, 0x15040d00);
3373         I915_WRITE(CSIEW0, 0x007f0000);
3374         I915_WRITE(CSIEW1, 0x1e220004);
3375         I915_WRITE(CSIEW2, 0x04000004);
3376
3377         for (i = 0; i < 5; i++)
3378                 I915_WRITE(PEW + (i * 4), 0);
3379         for (i = 0; i < 3; i++)
3380                 I915_WRITE(DEW + (i * 4), 0);
3381
3382         /* Program P-state weights to account for frequency power adjustment */
3383         for (i = 0; i < 16; i++) {
3384                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
3385                 unsigned long freq = intel_pxfreq(pxvidfreq);
3386                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
3387                         PXVFREQ_PX_SHIFT;
3388                 unsigned long val;
3389
3390                 val = vid * vid;
3391                 val *= (freq / 1000);
3392                 val *= 255;
3393                 val /= (127*127*900);
3394                 if (val > 0xff)
3395                         DRM_ERROR("bad pxval: %ld\n", val);
3396                 pxw[i] = val;
3397         }
3398         /* Render standby states get 0 weight */
3399         pxw[14] = 0;
3400         pxw[15] = 0;
3401
3402         for (i = 0; i < 4; i++) {
3403                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
3404                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
3405                 I915_WRITE(PXW + (i * 4), val);
3406         }
3407
3408         /* Adjust magic regs to magic values (more experimental results) */
3409         I915_WRITE(OGW0, 0);
3410         I915_WRITE(OGW1, 0);
3411         I915_WRITE(EG0, 0x00007f00);
3412         I915_WRITE(EG1, 0x0000000e);
3413         I915_WRITE(EG2, 0x000e0000);
3414         I915_WRITE(EG3, 0x68000300);
3415         I915_WRITE(EG4, 0x42000000);
3416         I915_WRITE(EG5, 0x00140031);
3417         I915_WRITE(EG6, 0);
3418         I915_WRITE(EG7, 0);
3419
3420         for (i = 0; i < 8; i++)
3421                 I915_WRITE(PXWL + (i * 4), 0);
3422
3423         /* Enable PMON + select events */
3424         I915_WRITE(ECR, 0x80000019);
3425
3426         lcfuse = I915_READ(LCFUSE02);
3427
3428         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
3429 }
3430
3431 void intel_disable_gt_powersave(struct drm_device *dev)
3432 {
3433         struct drm_i915_private *dev_priv = dev->dev_private;
3434
3435         if (IS_IRONLAKE_M(dev)) {
3436                 ironlake_disable_drps(dev);
3437                 ironlake_disable_rc6(dev);
3438         } else if (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev)) {
3439                 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
3440                 mutex_lock(&dev_priv->rps.hw_lock);
3441                 gen6_disable_rps(dev);
3442                 mutex_unlock(&dev_priv->rps.hw_lock);
3443         }
3444 }
3445
3446 static void intel_gen6_powersave_work(struct work_struct *work)
3447 {
3448         struct drm_i915_private *dev_priv =
3449                 container_of(work, struct drm_i915_private,
3450                              rps.delayed_resume_work.work);
3451         struct drm_device *dev = dev_priv->dev;
3452
3453         mutex_lock(&dev_priv->rps.hw_lock);
3454         gen6_enable_rps(dev);
3455         gen6_update_ring_freq(dev);
3456         mutex_unlock(&dev_priv->rps.hw_lock);
3457 }
3458
3459 void intel_enable_gt_powersave(struct drm_device *dev)
3460 {
3461         struct drm_i915_private *dev_priv = dev->dev_private;
3462
3463         if (IS_IRONLAKE_M(dev)) {
3464                 ironlake_enable_drps(dev);
3465                 ironlake_enable_rc6(dev);
3466                 intel_init_emon(dev);
3467         } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
3468                 /*
3469                  * PCU communication is slow and this doesn't need to be
3470                  * done at any specific time, so do this out of our fast path
3471                  * to make resume and init faster.
3472                  */
3473                 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
3474                                       round_jiffies_up_relative(HZ));
3475         }
3476 }
3477
3478 static void ibx_init_clock_gating(struct drm_device *dev)
3479 {
3480         struct drm_i915_private *dev_priv = dev->dev_private;
3481
3482         /*
3483          * On Ibex Peak and Cougar Point, we need to disable clock
3484          * gating for the panel power sequencer or it will fail to
3485          * start up when no ports are active.
3486          */
3487         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
3488 }
3489
3490 static void ironlake_init_clock_gating(struct drm_device *dev)
3491 {
3492         struct drm_i915_private *dev_priv = dev->dev_private;
3493         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
3494
3495         /* Required for FBC */
3496         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
3497                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
3498                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
3499
3500         I915_WRITE(PCH_3DCGDIS0,
3501                    MARIUNIT_CLOCK_GATE_DISABLE |
3502                    SVSMUNIT_CLOCK_GATE_DISABLE);
3503         I915_WRITE(PCH_3DCGDIS1,
3504                    VFMUNIT_CLOCK_GATE_DISABLE);
3505
3506         /*
3507          * According to the spec the following bits should be set in
3508          * order to enable memory self-refresh
3509          * The bit 22/21 of 0x42004
3510          * The bit 5 of 0x42020
3511          * The bit 15 of 0x45000
3512          */
3513         I915_WRITE(ILK_DISPLAY_CHICKEN2,
3514                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
3515                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
3516         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
3517         I915_WRITE(DISP_ARB_CTL,
3518                    (I915_READ(DISP_ARB_CTL) |
3519                     DISP_FBC_WM_DIS));
3520         I915_WRITE(WM3_LP_ILK, 0);
3521         I915_WRITE(WM2_LP_ILK, 0);
3522         I915_WRITE(WM1_LP_ILK, 0);
3523
3524         /*
3525          * Based on the document from hardware guys the following bits
3526          * should be set unconditionally in order to enable FBC.
3527          * The bit 22 of 0x42000
3528          * The bit 22 of 0x42004
3529          * The bit 7,8,9 of 0x42020.
3530          */
3531         if (IS_IRONLAKE_M(dev)) {
3532                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
3533                            I915_READ(ILK_DISPLAY_CHICKEN1) |
3534                            ILK_FBCQ_DIS);
3535                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3536                            I915_READ(ILK_DISPLAY_CHICKEN2) |
3537                            ILK_DPARB_GATE);
3538         }
3539
3540         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
3541
3542         I915_WRITE(ILK_DISPLAY_CHICKEN2,
3543                    I915_READ(ILK_DISPLAY_CHICKEN2) |
3544                    ILK_ELPIN_409_SELECT);
3545         I915_WRITE(_3D_CHICKEN2,
3546                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
3547                    _3D_CHICKEN2_WM_READ_PIPELINED);
3548
3549         /* WaDisableRenderCachePipelinedFlush */
3550         I915_WRITE(CACHE_MODE_0,
3551                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3552
3553         ibx_init_clock_gating(dev);
3554 }
3555
3556 static void cpt_init_clock_gating(struct drm_device *dev)
3557 {
3558         struct drm_i915_private *dev_priv = dev->dev_private;
3559         int pipe;
3560
3561         /*
3562          * On Ibex Peak and Cougar Point, we need to disable clock
3563          * gating for the panel power sequencer or it will fail to
3564          * start up when no ports are active.
3565          */
3566         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
3567         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
3568                    DPLS_EDP_PPS_FIX_DIS);
3569         /* The below fixes the weird display corruption, a few pixels shifted
3570          * downward, on (only) LVDS of some HP laptops with IVY.
3571          */
3572         for_each_pipe(pipe)
3573                 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_CHICKEN2_TIMING_OVERRIDE);
3574         /* WADP0ClockGatingDisable */
3575         for_each_pipe(pipe) {
3576                 I915_WRITE(TRANS_CHICKEN1(pipe),
3577                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
3578         }
3579 }
3580
3581 static void gen6_init_clock_gating(struct drm_device *dev)
3582 {
3583         struct drm_i915_private *dev_priv = dev->dev_private;
3584         int pipe;
3585         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
3586
3587         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
3588
3589         I915_WRITE(ILK_DISPLAY_CHICKEN2,
3590                    I915_READ(ILK_DISPLAY_CHICKEN2) |
3591                    ILK_ELPIN_409_SELECT);
3592
3593         I915_WRITE(WM3_LP_ILK, 0);
3594         I915_WRITE(WM2_LP_ILK, 0);
3595         I915_WRITE(WM1_LP_ILK, 0);
3596
3597         I915_WRITE(CACHE_MODE_0,
3598                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
3599
3600         I915_WRITE(GEN6_UCGCTL1,
3601                    I915_READ(GEN6_UCGCTL1) |
3602                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
3603                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
3604
3605         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3606          * gating disable must be set.  Failure to set it results in
3607          * flickering pixels due to Z write ordering failures after
3608          * some amount of runtime in the Mesa "fire" demo, and Unigine
3609          * Sanctuary and Tropics, and apparently anything else with
3610          * alpha test or pixel discard.
3611          *
3612          * According to the spec, bit 11 (RCCUNIT) must also be set,
3613          * but we didn't debug actual testcases to find it out.
3614          *
3615          * Also apply WaDisableVDSUnitClockGating and
3616          * WaDisableRCPBUnitClockGating.
3617          */
3618         I915_WRITE(GEN6_UCGCTL2,
3619                    GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
3620                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
3621                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3622
3623         /* Bspec says we need to always set all mask bits. */
3624         I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
3625                    _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
3626
3627         /*
3628          * According to the spec the following bits should be
3629          * set in order to enable memory self-refresh and fbc:
3630          * The bit21 and bit22 of 0x42000
3631          * The bit21 and bit22 of 0x42004
3632          * The bit5 and bit7 of 0x42020
3633          * The bit14 of 0x70180
3634          * The bit14 of 0x71180
3635          */
3636         I915_WRITE(ILK_DISPLAY_CHICKEN1,
3637                    I915_READ(ILK_DISPLAY_CHICKEN1) |
3638                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
3639         I915_WRITE(ILK_DISPLAY_CHICKEN2,
3640                    I915_READ(ILK_DISPLAY_CHICKEN2) |
3641                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
3642         I915_WRITE(ILK_DSPCLK_GATE_D,
3643                    I915_READ(ILK_DSPCLK_GATE_D) |
3644                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
3645                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
3646
3647         /* WaMbcDriverBootEnable */
3648         I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3649                    GEN6_MBCTL_ENABLE_BOOT_FETCH);
3650
3651         for_each_pipe(pipe) {
3652                 I915_WRITE(DSPCNTR(pipe),
3653                            I915_READ(DSPCNTR(pipe)) |
3654                            DISPPLANE_TRICKLE_FEED_DISABLE);
3655                 intel_flush_display_plane(dev_priv, pipe);
3656         }
3657
3658         /* The default value should be 0x200 according to docs, but the two
3659          * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
3660         I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
3661         I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
3662
3663         cpt_init_clock_gating(dev);
3664 }
3665
3666 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
3667 {
3668         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
3669
3670         reg &= ~GEN7_FF_SCHED_MASK;
3671         reg |= GEN7_FF_TS_SCHED_HW;
3672         reg |= GEN7_FF_VS_SCHED_HW;
3673         reg |= GEN7_FF_DS_SCHED_HW;
3674
3675         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
3676 }
3677
3678 static void lpt_init_clock_gating(struct drm_device *dev)
3679 {
3680         struct drm_i915_private *dev_priv = dev->dev_private;
3681
3682         /*
3683          * TODO: this bit should only be enabled when really needed, then
3684          * disabled when not needed anymore in order to save power.
3685          */
3686         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
3687                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
3688                            I915_READ(SOUTH_DSPCLK_GATE_D) |
3689                            PCH_LP_PARTITION_LEVEL_DISABLE);
3690 }
3691
3692 static void haswell_init_clock_gating(struct drm_device *dev)
3693 {
3694         struct drm_i915_private *dev_priv = dev->dev_private;
3695         int pipe;
3696
3697         I915_WRITE(WM3_LP_ILK, 0);
3698         I915_WRITE(WM2_LP_ILK, 0);
3699         I915_WRITE(WM1_LP_ILK, 0);
3700
3701         /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3702          * This implements the WaDisableRCZUnitClockGating workaround.
3703          */
3704         I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
3705
3706         /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3707         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3708                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
3709
3710         /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3711         I915_WRITE(GEN7_L3CNTLREG1,
3712                         GEN7_WA_FOR_GEN7_L3_CONTROL);
3713         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
3714                         GEN7_WA_L3_CHICKEN_MODE);
3715
3716         /* This is required by WaCatErrorRejectionIssue */
3717         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
3718                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
3719                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
3720
3721         for_each_pipe(pipe) {
3722                 I915_WRITE(DSPCNTR(pipe),
3723                            I915_READ(DSPCNTR(pipe)) |
3724                            DISPPLANE_TRICKLE_FEED_DISABLE);
3725                 intel_flush_display_plane(dev_priv, pipe);
3726         }
3727
3728         gen7_setup_fixed_func_scheduler(dev_priv);
3729
3730         /* WaDisable4x2SubspanOptimization */
3731         I915_WRITE(CACHE_MODE_1,
3732                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
3733
3734         /* WaMbcDriverBootEnable */
3735         I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3736                    GEN6_MBCTL_ENABLE_BOOT_FETCH);
3737
3738         /* XXX: This is a workaround for early silicon revisions and should be
3739          * removed later.
3740          */
3741         I915_WRITE(WM_DBG,
3742                         I915_READ(WM_DBG) |
3743                         WM_DBG_DISALLOW_MULTIPLE_LP |
3744                         WM_DBG_DISALLOW_SPRITE |
3745                         WM_DBG_DISALLOW_MAXFIFO);
3746
3747         lpt_init_clock_gating(dev);
3748 }
3749
3750 static void ivybridge_init_clock_gating(struct drm_device *dev)
3751 {
3752         struct drm_i915_private *dev_priv = dev->dev_private;
3753         int pipe;
3754         uint32_t snpcr;
3755
3756         I915_WRITE(WM3_LP_ILK, 0);
3757         I915_WRITE(WM2_LP_ILK, 0);
3758         I915_WRITE(WM1_LP_ILK, 0);
3759
3760         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
3761
3762         /* WaDisableEarlyCull */
3763         I915_WRITE(_3D_CHICKEN3,
3764                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
3765
3766         /* WaDisableBackToBackFlipFix */
3767         I915_WRITE(IVB_CHICKEN3,
3768                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
3769                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
3770
3771         /* WaDisablePSDDualDispatchEnable */
3772         if (IS_IVB_GT1(dev))
3773                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
3774                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
3775         else
3776                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
3777                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
3778
3779         /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3780         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3781                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
3782
3783         /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3784         I915_WRITE(GEN7_L3CNTLREG1,
3785                         GEN7_WA_FOR_GEN7_L3_CONTROL);
3786         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
3787                    GEN7_WA_L3_CHICKEN_MODE);
3788         if (IS_IVB_GT1(dev))
3789                 I915_WRITE(GEN7_ROW_CHICKEN2,
3790                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
3791         else
3792                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
3793                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
3794
3795
3796         /* WaForceL3Serialization */
3797         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
3798                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
3799
3800         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3801          * gating disable must be set.  Failure to set it results in
3802          * flickering pixels due to Z write ordering failures after
3803          * some amount of runtime in the Mesa "fire" demo, and Unigine
3804          * Sanctuary and Tropics, and apparently anything else with
3805          * alpha test or pixel discard.
3806          *
3807          * According to the spec, bit 11 (RCCUNIT) must also be set,
3808          * but we didn't debug actual testcases to find it out.
3809          *
3810          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3811          * This implements the WaDisableRCZUnitClockGating workaround.
3812          */
3813         I915_WRITE(GEN6_UCGCTL2,
3814                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
3815                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3816
3817         /* This is required by WaCatErrorRejectionIssue */
3818         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
3819                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
3820                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
3821
3822         for_each_pipe(pipe) {
3823                 I915_WRITE(DSPCNTR(pipe),
3824                            I915_READ(DSPCNTR(pipe)) |
3825                            DISPPLANE_TRICKLE_FEED_DISABLE);
3826                 intel_flush_display_plane(dev_priv, pipe);
3827         }
3828
3829         /* WaMbcDriverBootEnable */
3830         I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3831                    GEN6_MBCTL_ENABLE_BOOT_FETCH);
3832
3833         gen7_setup_fixed_func_scheduler(dev_priv);
3834
3835         /* WaDisable4x2SubspanOptimization */
3836         I915_WRITE(CACHE_MODE_1,
3837                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
3838
3839         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3840         snpcr &= ~GEN6_MBC_SNPCR_MASK;
3841         snpcr |= GEN6_MBC_SNPCR_MED;
3842         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3843
3844         cpt_init_clock_gating(dev);
3845 }
3846
3847 static void valleyview_init_clock_gating(struct drm_device *dev)
3848 {
3849         struct drm_i915_private *dev_priv = dev->dev_private;
3850         int pipe;
3851
3852         I915_WRITE(WM3_LP_ILK, 0);
3853         I915_WRITE(WM2_LP_ILK, 0);
3854         I915_WRITE(WM1_LP_ILK, 0);
3855
3856         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
3857
3858         /* WaDisableEarlyCull */
3859         I915_WRITE(_3D_CHICKEN3,
3860                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
3861
3862         /* WaDisableBackToBackFlipFix */
3863         I915_WRITE(IVB_CHICKEN3,
3864                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
3865                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
3866
3867         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
3868                    _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
3869
3870         /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3871         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3872                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
3873
3874         /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3875         I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
3876         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
3877
3878         /* WaForceL3Serialization */
3879         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
3880                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
3881
3882         /* WaDisableDopClockGating */
3883         I915_WRITE(GEN7_ROW_CHICKEN2,
3884                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
3885
3886         /* WaForceL3Serialization */
3887         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
3888                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
3889
3890         /* This is required by WaCatErrorRejectionIssue */
3891         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
3892                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
3893                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
3894
3895         /* WaMbcDriverBootEnable */
3896         I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3897                    GEN6_MBCTL_ENABLE_BOOT_FETCH);
3898
3899
3900         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3901          * gating disable must be set.  Failure to set it results in
3902          * flickering pixels due to Z write ordering failures after
3903          * some amount of runtime in the Mesa "fire" demo, and Unigine
3904          * Sanctuary and Tropics, and apparently anything else with
3905          * alpha test or pixel discard.
3906          *
3907          * According to the spec, bit 11 (RCCUNIT) must also be set,
3908          * but we didn't debug actual testcases to find it out.
3909          *
3910          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3911          * This implements the WaDisableRCZUnitClockGating workaround.
3912          *
3913          * Also apply WaDisableVDSUnitClockGating and
3914          * WaDisableRCPBUnitClockGating.
3915          */
3916         I915_WRITE(GEN6_UCGCTL2,
3917                    GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
3918                    GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
3919                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
3920                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
3921                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3922
3923         I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
3924
3925         for_each_pipe(pipe) {
3926                 I915_WRITE(DSPCNTR(pipe),
3927                            I915_READ(DSPCNTR(pipe)) |
3928                            DISPPLANE_TRICKLE_FEED_DISABLE);
3929                 intel_flush_display_plane(dev_priv, pipe);
3930         }
3931
3932         I915_WRITE(CACHE_MODE_1,
3933                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
3934
3935         /*
3936          * On ValleyView, the GUnit needs to signal the GT
3937          * when flip and other events complete.  So enable
3938          * all the GUnit->GT interrupts here
3939          */
3940         I915_WRITE(VLV_DPFLIPSTAT, PIPEB_LINE_COMPARE_INT_EN |
3941                    PIPEB_HLINE_INT_EN | PIPEB_VBLANK_INT_EN |
3942                    SPRITED_FLIPDONE_INT_EN | SPRITEC_FLIPDONE_INT_EN |
3943                    PLANEB_FLIPDONE_INT_EN | PIPEA_LINE_COMPARE_INT_EN |
3944                    PIPEA_HLINE_INT_EN | PIPEA_VBLANK_INT_EN |
3945                    SPRITEB_FLIPDONE_INT_EN | SPRITEA_FLIPDONE_INT_EN |
3946                    PLANEA_FLIPDONE_INT_EN);
3947
3948         /*
3949          * WaDisableVLVClockGating_VBIIssue
3950          * Disable clock gating on th GCFG unit to prevent a delay
3951          * in the reporting of vblank events.
3952          */
3953         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
3954 }
3955
3956 static void g4x_init_clock_gating(struct drm_device *dev)
3957 {
3958         struct drm_i915_private *dev_priv = dev->dev_private;
3959         uint32_t dspclk_gate;
3960
3961         I915_WRITE(RENCLK_GATE_D1, 0);
3962         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
3963                    GS_UNIT_CLOCK_GATE_DISABLE |
3964                    CL_UNIT_CLOCK_GATE_DISABLE);
3965         I915_WRITE(RAMCLK_GATE_D, 0);
3966         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
3967                 OVRUNIT_CLOCK_GATE_DISABLE |
3968                 OVCUNIT_CLOCK_GATE_DISABLE;
3969         if (IS_GM45(dev))
3970                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
3971         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
3972
3973         /* WaDisableRenderCachePipelinedFlush */
3974         I915_WRITE(CACHE_MODE_0,
3975                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3976 }
3977
3978 static void crestline_init_clock_gating(struct drm_device *dev)
3979 {
3980         struct drm_i915_private *dev_priv = dev->dev_private;
3981
3982         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
3983         I915_WRITE(RENCLK_GATE_D2, 0);
3984         I915_WRITE(DSPCLK_GATE_D, 0);
3985         I915_WRITE(RAMCLK_GATE_D, 0);
3986         I915_WRITE16(DEUC, 0);
3987 }
3988
3989 static void broadwater_init_clock_gating(struct drm_device *dev)
3990 {
3991         struct drm_i915_private *dev_priv = dev->dev_private;
3992
3993         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
3994                    I965_RCC_CLOCK_GATE_DISABLE |
3995                    I965_RCPB_CLOCK_GATE_DISABLE |
3996                    I965_ISC_CLOCK_GATE_DISABLE |
3997                    I965_FBC_CLOCK_GATE_DISABLE);
3998         I915_WRITE(RENCLK_GATE_D2, 0);
3999 }
4000
4001 static void gen3_init_clock_gating(struct drm_device *dev)
4002 {
4003         struct drm_i915_private *dev_priv = dev->dev_private;
4004         u32 dstate = I915_READ(D_STATE);
4005
4006         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4007                 DSTATE_DOT_CLOCK_GATING;
4008         I915_WRITE(D_STATE, dstate);
4009
4010         if (IS_PINEVIEW(dev))
4011                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
4012
4013         /* IIR "flip pending" means done if this bit is set */
4014         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
4015 }
4016
4017 static void i85x_init_clock_gating(struct drm_device *dev)
4018 {
4019         struct drm_i915_private *dev_priv = dev->dev_private;
4020
4021         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4022 }
4023
4024 static void i830_init_clock_gating(struct drm_device *dev)
4025 {
4026         struct drm_i915_private *dev_priv = dev->dev_private;
4027
4028         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4029 }
4030
4031 void intel_init_clock_gating(struct drm_device *dev)
4032 {
4033         struct drm_i915_private *dev_priv = dev->dev_private;
4034
4035         dev_priv->display.init_clock_gating(dev);
4036 }
4037
4038 /* Starting with Haswell, we have different power wells for
4039  * different parts of the GPU. This attempts to enable them all.
4040  */
4041 void intel_init_power_wells(struct drm_device *dev)
4042 {
4043         struct drm_i915_private *dev_priv = dev->dev_private;
4044         unsigned long power_wells[] = {
4045                 HSW_PWR_WELL_CTL1,
4046                 HSW_PWR_WELL_CTL2,
4047                 HSW_PWR_WELL_CTL4
4048         };
4049         int i;
4050
4051         if (!IS_HASWELL(dev))
4052                 return;
4053
4054         mutex_lock(&dev->struct_mutex);
4055
4056         for (i = 0; i < ARRAY_SIZE(power_wells); i++) {
4057                 int well = I915_READ(power_wells[i]);
4058
4059                 if ((well & HSW_PWR_WELL_STATE) == 0) {
4060                         I915_WRITE(power_wells[i], well & HSW_PWR_WELL_ENABLE);
4061                         if (wait_for((I915_READ(power_wells[i]) & HSW_PWR_WELL_STATE), 20))
4062                                 DRM_ERROR("Error enabling power well %lx\n", power_wells[i]);
4063                 }
4064         }
4065
4066         mutex_unlock(&dev->struct_mutex);
4067 }
4068
4069 /* Set up chip specific power management-related functions */
4070 void intel_init_pm(struct drm_device *dev)
4071 {
4072         struct drm_i915_private *dev_priv = dev->dev_private;
4073
4074         if (I915_HAS_FBC(dev)) {
4075                 if (HAS_PCH_SPLIT(dev)) {
4076                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
4077                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
4078                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
4079                 } else if (IS_GM45(dev)) {
4080                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
4081                         dev_priv->display.enable_fbc = g4x_enable_fbc;
4082                         dev_priv->display.disable_fbc = g4x_disable_fbc;
4083                 } else if (IS_CRESTLINE(dev)) {
4084                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
4085                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
4086                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
4087                 }
4088                 /* 855GM needs testing */
4089         }
4090
4091         /* For cxsr */
4092         if (IS_PINEVIEW(dev))
4093                 i915_pineview_get_mem_freq(dev);
4094         else if (IS_GEN5(dev))
4095                 i915_ironlake_get_mem_freq(dev);
4096
4097         /* For FIFO watermark updates */
4098         if (HAS_PCH_SPLIT(dev)) {
4099                 if (IS_GEN5(dev)) {
4100                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
4101                                 dev_priv->display.update_wm = ironlake_update_wm;
4102                         else {
4103                                 DRM_DEBUG_KMS("Failed to get proper latency. "
4104                                               "Disable CxSR\n");
4105                                 dev_priv->display.update_wm = NULL;
4106                         }
4107                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
4108                 } else if (IS_GEN6(dev)) {
4109                         if (SNB_READ_WM0_LATENCY()) {
4110                                 dev_priv->display.update_wm = sandybridge_update_wm;
4111                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4112                         } else {
4113                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
4114                                               "Disable CxSR\n");
4115                                 dev_priv->display.update_wm = NULL;
4116                         }
4117                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
4118                 } else if (IS_IVYBRIDGE(dev)) {
4119                         /* FIXME: detect B0+ stepping and use auto training */
4120                         if (SNB_READ_WM0_LATENCY()) {
4121                                 dev_priv->display.update_wm = ivybridge_update_wm;
4122                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4123                         } else {
4124                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
4125                                               "Disable CxSR\n");
4126                                 dev_priv->display.update_wm = NULL;
4127                         }
4128                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
4129                 } else if (IS_HASWELL(dev)) {
4130                         if (SNB_READ_WM0_LATENCY()) {
4131                                 dev_priv->display.update_wm = sandybridge_update_wm;
4132                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4133                                 dev_priv->display.update_linetime_wm = haswell_update_linetime_wm;
4134                         } else {
4135                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
4136                                               "Disable CxSR\n");
4137                                 dev_priv->display.update_wm = NULL;
4138                         }
4139                         dev_priv->display.init_clock_gating = haswell_init_clock_gating;
4140                 } else
4141                         dev_priv->display.update_wm = NULL;
4142         } else if (IS_VALLEYVIEW(dev)) {
4143                 dev_priv->display.update_wm = valleyview_update_wm;
4144                 dev_priv->display.init_clock_gating =
4145                         valleyview_init_clock_gating;
4146         } else if (IS_PINEVIEW(dev)) {
4147                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
4148                                             dev_priv->is_ddr3,
4149                                             dev_priv->fsb_freq,
4150                                             dev_priv->mem_freq)) {
4151                         DRM_INFO("failed to find known CxSR latency "
4152                                  "(found ddr%s fsb freq %d, mem freq %d), "
4153                                  "disabling CxSR\n",
4154                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
4155                                  dev_priv->fsb_freq, dev_priv->mem_freq);
4156                         /* Disable CxSR and never update its watermark again */
4157                         pineview_disable_cxsr(dev);
4158                         dev_priv->display.update_wm = NULL;
4159                 } else
4160                         dev_priv->display.update_wm = pineview_update_wm;
4161                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
4162         } else if (IS_G4X(dev)) {
4163                 dev_priv->display.update_wm = g4x_update_wm;
4164                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
4165         } else if (IS_GEN4(dev)) {
4166                 dev_priv->display.update_wm = i965_update_wm;
4167                 if (IS_CRESTLINE(dev))
4168                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
4169                 else if (IS_BROADWATER(dev))
4170                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
4171         } else if (IS_GEN3(dev)) {
4172                 dev_priv->display.update_wm = i9xx_update_wm;
4173                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
4174                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
4175         } else if (IS_I865G(dev)) {
4176                 dev_priv->display.update_wm = i830_update_wm;
4177                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
4178                 dev_priv->display.get_fifo_size = i830_get_fifo_size;
4179         } else if (IS_I85X(dev)) {
4180                 dev_priv->display.update_wm = i9xx_update_wm;
4181                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4182                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
4183         } else {
4184                 dev_priv->display.update_wm = i830_update_wm;
4185                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
4186                 if (IS_845G(dev))
4187                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
4188                 else
4189                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
4190         }
4191 }
4192
4193 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
4194 {
4195         u32 gt_thread_status_mask;
4196
4197         if (IS_HASWELL(dev_priv->dev))
4198                 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW;
4199         else
4200                 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK;
4201
4202         /* w/a for a sporadic read returning 0 by waiting for the GT
4203          * thread to wake up.
4204          */
4205         if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))
4206                 DRM_ERROR("GT thread status wait timed out\n");
4207 }
4208
4209 static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
4210 {
4211         I915_WRITE_NOTRACE(FORCEWAKE, 0);
4212         POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4213 }
4214
4215 static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
4216 {
4217         u32 forcewake_ack;
4218
4219         if (IS_HASWELL(dev_priv->dev))
4220                 forcewake_ack = FORCEWAKE_ACK_HSW;
4221         else
4222                 forcewake_ack = FORCEWAKE_ACK;
4223
4224         if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1) == 0,
4225                             FORCEWAKE_ACK_TIMEOUT_MS))
4226                 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
4227
4228         I915_WRITE_NOTRACE(FORCEWAKE, FORCEWAKE_KERNEL);
4229         POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4230
4231         if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1),
4232                             FORCEWAKE_ACK_TIMEOUT_MS))
4233                 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
4234
4235         __gen6_gt_wait_for_thread_c0(dev_priv);
4236 }
4237
4238 static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
4239 {
4240         I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));
4241         POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4242 }
4243
4244 static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
4245 {
4246         u32 forcewake_ack;
4247
4248         if (IS_HASWELL(dev_priv->dev))
4249                 forcewake_ack = FORCEWAKE_ACK_HSW;
4250         else
4251                 forcewake_ack = FORCEWAKE_MT_ACK;
4252
4253         if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1) == 0,
4254                             FORCEWAKE_ACK_TIMEOUT_MS))
4255                 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
4256
4257         I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
4258         POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4259
4260         if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1),
4261                             FORCEWAKE_ACK_TIMEOUT_MS))
4262                 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
4263
4264         __gen6_gt_wait_for_thread_c0(dev_priv);
4265 }
4266
4267 /*
4268  * Generally this is called implicitly by the register read function. However,
4269  * if some sequence requires the GT to not power down then this function should
4270  * be called at the beginning of the sequence followed by a call to
4271  * gen6_gt_force_wake_put() at the end of the sequence.
4272  */
4273 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
4274 {
4275         unsigned long irqflags;
4276
4277         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
4278         if (dev_priv->forcewake_count++ == 0)
4279                 dev_priv->gt.force_wake_get(dev_priv);
4280         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
4281 }
4282
4283 void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
4284 {
4285         u32 gtfifodbg;
4286         gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
4287         if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
4288              "MMIO read or write has been dropped %x\n", gtfifodbg))
4289                 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
4290 }
4291
4292 static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
4293 {
4294         I915_WRITE_NOTRACE(FORCEWAKE, 0);
4295         /* gen6_gt_check_fifodbg doubles as the POSTING_READ */
4296         gen6_gt_check_fifodbg(dev_priv);
4297 }
4298
4299 static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
4300 {
4301         I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
4302         /* gen6_gt_check_fifodbg doubles as the POSTING_READ */
4303         gen6_gt_check_fifodbg(dev_priv);
4304 }
4305
4306 /*
4307  * see gen6_gt_force_wake_get()
4308  */
4309 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
4310 {
4311         unsigned long irqflags;
4312
4313         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
4314         if (--dev_priv->forcewake_count == 0)
4315                 dev_priv->gt.force_wake_put(dev_priv);
4316         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
4317 }
4318
4319 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
4320 {
4321         int ret = 0;
4322
4323         if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
4324                 int loop = 500;
4325                 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
4326                 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
4327                         udelay(10);
4328                         fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
4329                 }
4330                 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
4331                         ++ret;
4332                 dev_priv->gt_fifo_count = fifo;
4333         }
4334         dev_priv->gt_fifo_count--;
4335
4336         return ret;
4337 }
4338
4339 static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
4340 {
4341         I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(0xffff));
4342 }
4343
4344 static void vlv_force_wake_get(struct drm_i915_private *dev_priv)
4345 {
4346         if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0,
4347                             FORCEWAKE_ACK_TIMEOUT_MS))
4348                 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
4349
4350         I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
4351
4352         if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1),
4353                             FORCEWAKE_ACK_TIMEOUT_MS))
4354                 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
4355
4356         __gen6_gt_wait_for_thread_c0(dev_priv);
4357 }
4358
4359 static void vlv_force_wake_put(struct drm_i915_private *dev_priv)
4360 {
4361         I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
4362         /* The below doubles as a POSTING_READ */
4363         gen6_gt_check_fifodbg(dev_priv);
4364 }
4365
4366 void intel_gt_reset(struct drm_device *dev)
4367 {
4368         struct drm_i915_private *dev_priv = dev->dev_private;
4369
4370         if (IS_VALLEYVIEW(dev)) {
4371                 vlv_force_wake_reset(dev_priv);
4372         } else if (INTEL_INFO(dev)->gen >= 6) {
4373                 __gen6_gt_force_wake_reset(dev_priv);
4374                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4375                         __gen6_gt_force_wake_mt_reset(dev_priv);
4376         }
4377 }
4378
4379 void intel_gt_init(struct drm_device *dev)
4380 {
4381         struct drm_i915_private *dev_priv = dev->dev_private;
4382
4383         spin_lock_init(&dev_priv->gt_lock);
4384
4385         intel_gt_reset(dev);
4386
4387         if (IS_VALLEYVIEW(dev)) {
4388                 dev_priv->gt.force_wake_get = vlv_force_wake_get;
4389                 dev_priv->gt.force_wake_put = vlv_force_wake_put;
4390         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
4391                 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_mt_get;
4392                 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_mt_put;
4393         } else if (IS_GEN6(dev)) {
4394                 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get;
4395                 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put;
4396         }
4397         INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
4398                           intel_gen6_powersave_work);
4399 }
4400
4401 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
4402 {
4403         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4404
4405         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
4406                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
4407                 return -EAGAIN;
4408         }
4409
4410         I915_WRITE(GEN6_PCODE_DATA, *val);
4411         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
4412
4413         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
4414                      500)) {
4415                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
4416                 return -ETIMEDOUT;
4417         }
4418
4419         *val = I915_READ(GEN6_PCODE_DATA);
4420         I915_WRITE(GEN6_PCODE_DATA, 0);
4421
4422         return 0;
4423 }
4424
4425 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
4426 {
4427         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4428
4429         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
4430                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
4431                 return -EAGAIN;
4432         }
4433
4434         I915_WRITE(GEN6_PCODE_DATA, val);
4435         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
4436
4437         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
4438                      500)) {
4439                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
4440                 return -ETIMEDOUT;
4441         }
4442
4443         I915_WRITE(GEN6_PCODE_DATA, 0);
4444
4445         return 0;
4446 }